A fully functional 3-stage pipelined RISC-V CPU implementation in Verilog. This project implements a complete RISC-V instruction set architecture processor with memory hierarchy, cache system, and comprehensive test infrastructure.
This is a 3-stage pipelined RISC-V processor core that supports the RV32I base instruction set. The processor features:
- 3-stage pipeline: Fetch, Decode/Execute, Writeback
- Complete RISC-V RV32I instruction set support
- Direct-mapped instruction and data cache
- Memory management unit with partial load/store support
Total area of 2000 × 2400 µm. I-cache SRAMs on the left, D-cache SRAMs on the right, CPU logic in the center. Each cache uses one 64×32 metadata SRAM and four 256×32 data banks.
The CPU implements a classic 3-stage pipeline:
- Fetch Stage: Instruction fetch from memory/cache
- Decode/Execute Stage: Instruction decoding, ALU operations, memory access
- Writeback Stage: Register file updates
The main processor module implementing the 3-stage pipeline. Handles instruction flow, hazard detection, and pipeline control.
Arithmetic Logic Unit supporting all RISC-V arithmetic and logical operations including:
- Addition, subtraction
- Bitwise operations (AND, OR, XOR)
- Shift operations
- Comparison operations
Generates control signals for instruction execution, including:
- ALU control signals
- Register file read/write enables
- Memory access control
- Branch and jump control
32-entry register file with dual read ports and single write port, implementing the RISC-V register specification (x0-x31).
- Cache (
Cache.sv): Instruction and data cache - Memory (
Memory151.sv): Main memory controller - Partial Load/Store: Handles byte and halfword memory operations
