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chipyard
chipyard PublicForked from ucb-bar/chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
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riscv-boom
riscv-boom PublicForked from riscv-boom/riscv-boom
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rocket-chip-inclusive-cache
rocket-chip-inclusive-cache PublicForked from SmartAgentPrefetcher/rocket-chip-inclusive-cache
An RTL generator for a last-level shared inclusive TileLink cache controller
Scala
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