Zephyr device driver for the Texas Instruments ADS1293 three-channel, 24-bit biopotential analog front end.
The driver is chip-level and intentionally exposes the ADS1293's complete routing, filtering, lead-off, reference, RLD, Wilson-reference, alarm, pace, status, and raw-data controls. Application policy, BLE behavior, buffering, and the NAM device's restricted 50/100/200 Hz profile live outside this driver.
The device-tree binding is ti,ads1293. The SPI bus performs register and sample transfers. drdy-gpios, alarm-gpios, and reset-gpios are optional GPIO interfaces. clock-frequency selects an externally supplied clock; omitting it selects the ADS1293 internal oscillator.
&spi21 {
status = "okay";
ads1293: ads1293@0 {
compatible = "ti,ads1293";
reg = <0>;
spi-max-frequency = <8000000>;
drdy-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
clock-frequency = <409600>;
ch1-inputs = <1 2>;
ch2-inputs = <2 3>;
ch3-inputs = <3 1>;
};
};
ch1-inputs, ch2-inputs, and ch3-inputs are <positive negative> physical input numbers from zero (disconnected) through six (IN6). NAM uses three direct differential routes: CH1 = IN1 - IN2, CH2 = IN2 - IN3, and CH3 = IN3 - IN1. The Wilson reference, common-mode detector, and RLD remain disabled because the board has no separate reference or driven electrode.
The external clock must satisfy the ADS1293 electrical limits. NAM supplies a fixed nominal 409.6 kHz clock from FLPR; changing ECG sample rate changes ADS1293 decimation and never changes that clock.
Call ads1293ConfigDefaults() to initialize every field of ADS1293Config, modify the required fields, then call ads1293Configure(). Complete configuration stops conversion and leaves the device in standby; call ads1293Start() explicitly after configuration.
The generic driver accepts every decimation value represented by ADS1293R2Rate and ADS1293R3Rate. With a 409.6 kHz external clock and low-frequency modulator:
ODR = 25600 / (R2 * R3)
ADS1293Config also controls:
- ECG and pace channel enable bits.
- Per-channel differential input routing.
- Per-channel R1 and R3 decimation plus the shared R2 decimation.
- Low-power or high-resolution analog operation.
- 102.4 or 204.8 kHz modulator selection.
- DRDY source.
- DC/AC lead-off detection and monitored inputs.
- Common-mode detection, RLD, and external/internal clock selection.
ADS1293Decimation.r1_double_rate_mask maps directly to R1_RATE: bit 0 controls channel 1, bit 1 controls channel 2, and bit 2 controls channel 3. A clear bit selects standard R1 = 4; a set bit selects double pace rate R1 = 2. For example, ADS1293_R1_RATE_CH1_DOUBLE | ADS1293_R1_RATE_CH3_DOUBLE writes 0x05, doubling channels 1 and 3 without changing channel 2.
The standalone setter functions apply one chip feature at a time. Do not use them while converting unless the function documentation explicitly permits it; configuration registers are protected while conversion is active.
Register ads1293SetDataReadyCallback() for DRDY-driven operation. The callback runs in interrupt context, so it must only initiate bounded interrupt-safe work. ads1293ReadRaw() performs one burst read of all three ECG output registers. ads1293ReadChannelRaw() reads one channel.
Native ECG values are unsigned 24-bit offset-binary codes. They are not signed two's-complement values:
zero differential input = ADCMAX / 2
Vin = (2 * raw - ADCMAX) * (2 * VREF) / (7 * ADCMAX)
VREF is nominally 2.4 V with the internal reference. ADCMAX depends on R2/R3; use ads1293RawToNanovolts() rather than assuming 0xFFFFFF. ads1293ReadData() and ads1293ReadChannelData() combine acquisition and conversion to input-referred nanovolts.
- Lifecycle:
ads1293Start,ads1293Stop,ads1293Reset - Complete configuration:
ads1293ConfigDefaults,ads1293Configure,ads1293GetConfig - Routing and filters:
ads1293SetChannelInputs,ads1293SetChannelsEnabled,ads1293SetSampleRate,ads1293SetAFEResolution - Raw and converted data:
ads1293ReadRaw,ads1293ReadChannelRaw,ads1293ReadData,ads1293ReadChannelData,ads1293RawToNanovolts - Interrupts and readiness:
ads1293SetDataReadySource,ads1293SetDataReadyCallback,ads1293SetAlarmCallback,ads1293DataReady - Diagnostics:
ads1293GetStatus,ads1293GetLeadOffStatus,ads1293GetRevision, error-register getters, pin readers, and sample counters - Extended chip features: clock, lead-off, RLD, Wilson reference, common-mode, VBAT, pace, alarm, reference, filter bypass, and DIO controls
include/ads1293.h is the authoritative function contract. include/ads1293_types.h defines every public configuration and result type. include/ads1293_regs.h defines the datasheet register map and bit fields.
Device tree supplies the baseline clock source, sample rate, analog mode, RLD state, and channel routing. NAM defines these once in its board DTS and then applies runtime rate/mode changes through its sensor-owned ECGConfig. Lead-off Kconfig fields remain generic driver boot defaults and are also available through the runtime API.
The NAM ECG system firmware checks device identity, lifecycle, every application rate and mode, three-channel acquisition, callbacks, bounded-buffer behavior, status/lead-off reporting, and raw-code conversion. Direct oscilloscope measurement remains required to verify external-clock duty cycle and edge quality; DRDY rate only verifies effective clock frequency and decimation.
MIT. See LICENSE.