Verilog Benchmarks

Curated collection of combinational Verilog netlists used as benchmarks in circuit analysis and optimization experiments, in particular with thermalbits.

All files are flat gate-level netlists (combinational logic only).

Collections

Directory	Files	Description
EDGE/	29	EDGE benchmark suite — medium/large combinational circuits (e.g. apex2, C6288, cps, seq).
EPFL/	5	Subset of the EPFL combinational benchmark suite (cavlc, ctrl, dec, int2float, sin).
Adders_BCGEN_Balanced/	42	BCGEN-generated adders, balanced with ABC (*.balanced.aig.v), in increasing bit widths.
basic/	1	Minimal circuits for quick smoke tests (half_adder.v).

Usage with thermalbits

git clone https://github.com/Carlos-Jr/verilog-benchmarks.git
thermalbits analyze verilog-benchmarks/EPFL/sin.v
thermalbits batch verilog-benchmarks/EDGE -o results.csv