64-Point FFT Block-Convolution Accelerator

A synthesizable fixed-point Verilog accelerator for one-dimensional FIR filtering. The design uses 64-point FFT-based block convolution with the overlap-save method and was developed as a VLSI DSP course project.

The current architecture reuses one iterative radix-2 FFT/IFFT core and one pipelined complex multiplier across the transform and frequency-domain filtering phases. This favors area and implementation clarity over peak streaming throughput.

Design summary

Item	Value
FFT length	64 points
FIR length	16 taps
Valid outputs per block	49 samples
Input / coefficient format	Signed Q1.15
Internal datapath	Signed 32-bit fixed point
FFT architecture	Iterative radix-2, shared FFT/IFFT core
Complex multiplication	One shared two-cycle pipelined unit
Reference technology	TSMC 90 nm typical standard-cell library

The checked-in test fixture contains two blocks (98 input and output samples). Cadence Xcelium simulation produced:

PASS: 98 output samples matched within tolerance 16.

The final Design Compiler reports for the shared-multiplier RTL show:

Metric	Result
Clock constraint	10.00 ns (100 MHz)
Critical-path slack	+2.42 ns
Total cell area	368,306.270659 library area units
Standard-cell count	54,030
Estimated total power	12.7989 mW
Steady-state block interval	2,536 cycles
Throughput at 100 MHz	1.93 MSamples/s

These are synthesis-level results, not post-layout measurements. Power was estimated without annotated switching activity or extracted parasitics.

Architecture

Each processing block contains 15 history samples and 49 new samples:

input stream
    -> overlap-save block buffer
    -> 64-point FFT
    -> point-wise multiplication by precomputed FFT(h)
    -> 64-point IFFT and 1/64 normalization
    -> discard 15 overlap samples
    -> 49-sample output block

The coefficient spectrum and test vectors are generated from a 16-tap moving-average FIR filter. rtl/coeff_rom64_values.vh is generated as a synthesizable constant ROM so the ASIC and FPGA synthesis flows do not depend on $readmemh support.

Repository layout

Path	Contents
rtl/	Synthesizable Verilog RTL and generated coefficient ROM values
tb/	Self-checking Verilog testbench and simulation file list
scripts/	Deterministic vector generator and Xcelium/Vivado launch helpers
data/	Checked-in input, coefficient, and golden-output fixtures
syn/	Synopsys Design Compiler and Vivado synthesis scripts
reports/	Final Design Compiler area, timing, power, and QoR reports
waveform/	GTKWave views and report-ready waveform screenshots
docs/	Implementation notes and generated-artifact policy
report.tex	Public, student-ID-redacted final report source
fft_based_convolution_proposal.tex	Original project proposal source

Quick start with Icarus Verilog

Requirements:

• Python 3.8 or later
• Icarus Verilog 11 or later (iverilog and vvp)

Run the commands from the repository root:

mkdir -p build
python3 scripts/generate_vectors.py
iverilog -g2012 -o build/fft_block_conv_tb.vvp -f tb/filelist_tb.f
vvp build/fft_block_conv_tb.vvp

On Windows PowerShell, use python instead of python3 if necessary:

New-Item -ItemType Directory -Force build | Out-Null
python scripts/generate_vectors.py
iverilog -g2012 -o build/fft_block_conv_tb.vvp -f tb/filelist_tb.f
vvp build/fft_block_conv_tb.vvp

The testbench writes fft_block_conv_top.vcd. Open it with GTKWave and load either view in waveform/ if desired.

Cadence Xcelium flow

The laboratory EDA setup uses tcsh. From the repository root:

tcsh
source scripts/setup_eda.csh
tcsh scripts/run_xrun.csh

For a waveform-oriented run that opens SimVision when a graphical display is available:

tcsh scripts/run_xrun_gui.csh

The setup script expects the site-specific EDA environment at $HOME/eda; adjust it for another installation.

Synthesis

Synopsys Design Compiler

syn/dc_synthesis.tcl currently references the course laboratory's TSMC 90 nm library path. Change target_library if your installation differs, then run:

dc_shell -f syn/dc_synthesis.tcl

The script recreates the generated netlist, SDC, and reports. The technology library is proprietary and is not included.

Vivado sanity check

Vivado is used only as an RTL synthesizability and FPGA timing sanity check:

vivado -mode batch -source syn/vivado_synth.tcl

or:

powershell -ExecutionPolicy Bypass -File scripts/run_vivado_synth.ps1

Vivado LUT/FF/DSP results are not comparable to the TSMC 90 nm standard-cell results. Existing local Vivado outputs predate the final shared-multiplier RTL, so they are intentionally excluded from version control and must be regenerated before use.

Reproducibility notes

• scripts/generate_vectors.py is deterministic and should reproduce every checked-in file in data/ plus rtl/coeff_rom64_values.vh.
• Generated simulator databases, logs, wave dumps, synthesis work files, netlists, and checkpoints are excluded by .gitignore.
• The final Design Compiler text reports are retained as compact evidence for the results quoted above.
• report.pdf is intentionally ignored because the existing local copy contains a student ID. Build a public PDF from the redacted report.tex before publishing it separately.
• See docs/artifacts.md for the complete tracked/generated-file policy.

Known limitations

• The FFT length and FIR length are fixed at 64 and 16 in the top-level implementation.
• The testbench covers one deterministic two-block fixture rather than randomized or assertion-based verification.
• The design uses no SRAM, ROM, or multiplier macros; arrays and arithmetic are mapped by the synthesis tool.
• ASIC power is a low-effort vectorless synthesis estimate.
• The included Design Compiler script depends on a site-specific commercial library and tool installation.

License

This project is released under the MIT License.