Verilog Programs Repository

Welcome to the Verilog Programs repository! This collection contains various Verilog HDL projects designed to demonstrate and practice digital logic design concepts. Each project includes Verilog modules, testbenches, and simulation results.

Repository Structure

The repository is organized into the following directories:

• 4-bit-Ripple-Adder/: Implementation of a 4-bit Ripple Carry Adder using behavioral and structural modeling.
• Adder-Subtractor/: Parameterized N-bit Adder-Subtractor with addition and subtraction functionality.
• All_Gates/: Demonstration of all basic logic gates in Verilog.
• Comparator/: 4-bit digital comparator using behavioral and gate-level modeling.
• DeMultiplexer/: 1-to-8 demultiplexer implemented with behavioral and structural models.
• Flip-Flops/: Verilog implementations of fundamental flip-flops (SR, D, JK, T).
• Full_Adder/: 1-bit full adder using behavioral and structural modeling.
• Full-Subtractor/: 1-bit full subtractor implemented in Verilog.
• multiplexer/: 8-to-1 multiplexer using behavioral and gate-level modeling.

Each directory contains its own README file with detailed information about the project, including circuit diagrams and timing diagrams.

Tools Used

• Vivado Design Suite: For writing, simulating, and visualizing RTL designs.
• GTKWave: Optional tool for waveform inspection.
• Git & GitHub: For version control and collaboration.

How to Use

1. Clone the repository:

   git clone https://github.com/your-username/Verilog-Programs.git

2. Navigate to the desired project directory.
3. Open the Verilog files in your preferred HDL editor or Vivado.
4. Follow the instructions in the project-specific README to simulate and analyze the design.

License

This repository is licensed under the MIT License. See the LICENSE file for details.

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Happy coding and learning Verilog!