Learning-Verilog

All of the Verilog solution files I have written for the HDLBits problems in order to teach myself Verilog.

Structure

Closely follows the problems on HDLBits. So, folder structure matches the hierarchy of the problems on the website. Not all problems are included here, only most important ones.

Goal

I plan to follow the HDLBits problems to learn Verilog. After completing them, I plan to move on to learn SystemVerilog. Once I am comfortable with SV, I plan to implement my own RISC-V Core. A separate repo will be made for the RISC-V Core once I start the project.

Progress

[✅] Verilog Language
    [✅] Basics
    [✅] Vectors
    [✅] Modules
    [✅] Procedures
    [✅] More Features
[🟨] Circuits
    [✅] Combinational Logic
        [✅] Basic Gates
        [✅] Multiplexers
        [✅] Arithmetic Circuits
        [✅] K-Map to Circuit
    [🟨] Sequential Logic
        [✅] Latches and Flip-Flops
        [✅] Counters
        [ ] Shift Registers
        [ ] More Circuits
        [ ] Finite State Machines
    [ ] Larger Circuits
[ ] Verification
    [ ] Reading Simulations
    [ ] Writing Testbenches