Conversation
…sion configs
nvidia/Qwen3.8-Flash-Next-NVFP4 declares its FP8 PLE table per layer in
the ModelOpt mixed-precision config and does not set
ple_embedding_dtype. The PLE embedding then got no quant method, and on
pre-Ampere cards the pinned-host placement refused to start ("requires
FP8 checkpoint storage"). Resolve the table's algorithm through the
mixed-precision config as well; the table layout is the same 129-shard
FP8 table with one weight_scale as in the other Flash-Next exports.
Co-authored-by: Claude
Signed-off-by: Peuqui <peuqui@github.com>
Peuqui
pushed a commit
to Peuqui/1Cat-vLLM
that referenced
this pull request
Sep 16, 2026
The PR branch for 1Cat (qwen4exp-ple-tier-cascade-pr) needed a few changes; the fork carries the same ones so both stay equal except for 1CatAI#640's hunk: - The PLE offload worker drops an inherited VLLM_PP_LAYER_PARTITION with an upstream-ready comment (was an overlay note), plus a regression test that fails without the line. - The store-card check and load use torch.accelerator.device_count() and torch.accelerator.synchronize(): 1Cat's pre-commit hook refuses new torch.cuda calls. Tests patch torch.accelerator accordingly. - PLEPlacement's docstring names the disk tier; a test comment loses its German quote; ruff format on one test call. - docs/design/qwen4exp_ple_tier_cascade.md: tiers, configuration, placement, per-step flow, validation and limits. Checked: test_ple 87, test_ple_offload_worker 31, test_sm70_decode_graph 24 passed; boot of the PLE-Disk llama-swap entry on this code without errors, store 1.0 GiB loaded in 24.7 s, probe 4/4 identical to the reference. Co-authored-by: Claude <noreply@anthropic.com> Signed-off-by: Peuqui <peuqui@github.com> Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
4 tasks
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Purpose
nvidia/Qwen3.8-Flash-Next-NVFP4stores its PLE table exactly like the otherFlash-Next NVFP4 exports: 129 FP8 E4M3 shards under
model.language_model.layers.1.ple.ple_embedding.ngram_embeddingwith oneweight_scale. It declares that table in the ModelOpt mixed-precision config(
quantized_layers[...ngram_embedding] = {"quant_algo": "FP8"}) and does notset
ple_embedding_dtypeintext_config._get_ple_embedding_quant_methodonly recognises FP8 storage throughple_embedding_dtype == "float8_e4m3fn"or anFp8Config. For this checkpointit returns
None, and on pre-Ampere cards, where the pinned-host PLE placementis taken, the engine refuses to start:
The change adds a
ModelOptMixedPrecisionConfigbranch: if the table is notexcluded and its per-layer algorithm resolves to
FP8, the existingQwen4ExpPLEFp8EmbeddingMethodis selected. The lookup goes through theconfig's own
is_layer_excludedand_resolve_quant_algo, which already mapbetween the checkpoint's
model.language_model.and vLLM'slanguage_model.model.prefixes and are used the same way for MTP experts in
mtp_fp8_experts.py.Checkpoints that set
ple_embedding_dtypeor useFp8Configtake the same pathas before.
Not a duplicate: searched open and closed PRs and issues for "PLE FP8",
"ple_embedding_dtype", "ModelOptMixedPrecision PLE", "pinned-host PLE",
"Flash-Next nvidia". #553 concerns the MTP experts of the same checkpoint and
does not touch the PLE table.
Test Plan
End to end with
nvidia/Qwen3.8-Flash-Next-NVFP4revision fc694b54 on 2x QuadroRTX 8000 + 2x Tesla V100, TP2 x PP2, pinned-host PLE with a 6 GiB host budget.
Test Result
mixed-precision dict and checks both prefix spellings: FP8 table selects the
FP8 embedding method, an unlisted table and an excluded table do not. Without
the fix both parametrized cases fail.
editing its config, and serves; the same run is described in [Bugfix][Qwen4Exp] Allow checkpoint FP8 MTP experts under pipeline parallelism #639
for FP8 MTP experts under pipeline parallelism, which this checkpoint needs as
well for MTP on that topology.
These end-to-end runs were made on our fork (1Cat main 80c88e8 plus our open
PRs).
AI assistance (Claude) was used for this change and this description. I reviewed
every changed line and ran the tests and measurements above.
Essential Elements of an Effective PR Description Checklist
supported_models.mdandexamplesfor a new model.🤖 Generated with Claude Code