[Kernel][WIP] Port FlashInfer GDN and HC layer fusion to SM70

[yangzhuxinyzx]

Purpose

Port real FlashInfer layer-fusion computation to SM70 and finish operator
screening before a consolidated model E2E/quality run. No serving defaults
are changed by this benchmark prototype.

• Base: 755baae1d075ee04fa9096b23fc0225b23589a86 (main).
• Initial implementation: e2061d5049.
• First GPU correctness/component screen head: 72af224161.
• Upstream FlashInfer pin: 6c14bbd5ff34210404d5d4b5f6ff3b4b2527f59f.
• GDN: port gate projection + width-4 convolution + FP32 recurrent update,
  FP16 activations, graph-safe cooperative grid synchronization.
• HC: port fused-add norm vector/staging/reduction algorithm, adapt HC gate,
  materialized-residual rounding and Gemma affine semantics.
• Preserve actual production mul.f16 -> cvt.f32.f16 convolution boundary
  confirmed in captured Triton PTX; do not silently use widened products.

Duplicate audit: this is not #513's QSA kernel nor #504's batch HC TP sharding.
M1 #506/#510 work and previous v0.6.13 negative probes are left untouched.
The existing TurboMind quantization and native/FA paths are not replaced.

Test Plan

1. Native SM70 build, independent oracle, dynamic pool indices and padding,
   poisoned-buffer eager/graph replay.
2. Paired B1/4/8/16 production-conv/FlashQLA and HC-Triton component screens,
   real checkpoint GDN weights, FP32 state, unchanged numerical gates.
3. Targeted sanitizer, independent long recurrent histories, multistream
   lifetime/synchronization checks; only integrate operator winners.
4. Then one consolidated same-contract E2E C1/4/8/16 and coding/tool/schema
   quality validation. Micro timings do not establish model quality or TPS.

Test Result

• GDN (including cooperative launch) and HC native SM70 builds/load passed,
  Python 3.12.13 / Torch 2.10.0+cu128 / CUDA 12.8.
• TP4 Hq4/Hv12 and TP2 Hq8/Hv24 specializations compile and load together;
  distinct Torch operator namespaces avoid geometry registration collisions.
• Initial complete GPU pytest: 16 passed, including 8 GPU cases, in
  33.39 s. Independent GDN histories, HC oracle and graph replay pass.
• Real checkpoint FP16 GDN/FP32-state chain, paired CUDA Graph medians:
  B4 28.604 → 15.087 us, B8 33.041 → 22.801 us,
  B16 57.344 → 47.343 us. All 256-step independent-history screens pass.
  These are component timings, not model throughput or quality admission.
• Both HC variants are numerically correct but slower than current Triton.
  Updated GPU suite: 20 passed, including the new register variant.
  FP16 B16: current 3.164 us vs register HC 3.779 us. Neither is enabled.
• Targeted CUDA 12.8 GDN memcheck: 0 errors (B16); racecheck: 0 errors / 0 warnings (B4).
• Applicable staged pre-commit hooks passed, including Ruff, mypy,
  clang-format, Markdown and repository-specific checks.
• The earlier GPU-lease rejection (75) remains a pre-launch negative result.
  The user subsequently freed GPU 4–7; component checks above completed there.
  Runtime integration and E2E evidence are tracked separately in [Kernel][WIP] Integrate native FlashInfer SM70 batch GDN and QSA probes #523.
• Serving dispatch remains unchanged. No model-quality pass or E2E speedup
  is claimed. Retain existing M1 projection and HC paths.

Worklog: docs/design/sm70_flashinfer_layer_fusion.md.
All build/test caches are task-private and generated files are unversioned.
Reference QLA source matches the retained current baseline; hash in worklog.

Keep Draft. FP16-state compression and failed prior GEMV/HC substitutions
are deliberately not retried or promoted. No deployed API is touched.
This work is AI-assisted (Codex). Human review is required before admission;
commits have DCO sign-off and AI attribution.

September 6 integration note: #523 exposed and corrected a prefill-trace specialization that initially bypassed fused GDN. Its first model result is therefore QSA-only, not a GDN speedup; it also has a negative small-sample tool-quality signal. The corrected combined run completed in #523: C4/8/16 throughput +6.98% / +7.00% / +7.35%, with both native paths selected, but offline BFCL is 49/64 vs 52/64 control. All throughput targets remain unmet and quality is unadmitted. Keep default-off/Draft; all owned GPU workers exited.