diff --git a/boards/stm32c031_nucleo/board.c b/boards/stm32c031_nucleo/board.c index dfbf37e..15c1592 100644 --- a/boards/stm32c031_nucleo/board.c +++ b/boards/stm32c031_nucleo/board.c @@ -54,60 +54,36 @@ whal_Gpio g_whalGpio = { .cfg = &(whal_Stm32c0Gpio_Cfg) { .pinCfg = (whal_Stm32c0Gpio_PinCfg[PIN_COUNT]) { - [LED_PIN] = { /* LD4 Green LED on PA5 */ - .port = WHAL_STM32C0_GPIO_PORT_A, - .pin = 5, - .mode = WHAL_STM32C0_GPIO_MODE_OUT, - .outType = WHAL_STM32C0_GPIO_OUTTYPE_PUSHPULL, - .speed = WHAL_STM32C0_GPIO_SPEED_LOW, - .pull = WHAL_STM32C0_GPIO_PULL_NONE, - .altFn = 0, - }, - [UART_TX_PIN] = { /* USART1 TX on PB6, AF1 */ - .port = WHAL_STM32C0_GPIO_PORT_B, - .pin = 6, - .mode = WHAL_STM32C0_GPIO_MODE_ALTFN, - .outType = WHAL_STM32C0_GPIO_OUTTYPE_PUSHPULL, - .speed = WHAL_STM32C0_GPIO_SPEED_FAST, - .pull = WHAL_STM32C0_GPIO_PULL_UP, - .altFn = 0, - }, - [UART_RX_PIN] = { /* USART1 RX on PB7, AF1 */ - .port = WHAL_STM32C0_GPIO_PORT_B, - .pin = 7, - .mode = WHAL_STM32C0_GPIO_MODE_ALTFN, - .outType = WHAL_STM32C0_GPIO_OUTTYPE_PUSHPULL, - .speed = WHAL_STM32C0_GPIO_SPEED_FAST, - .pull = WHAL_STM32C0_GPIO_PULL_UP, - .altFn = 0, - }, - [SPI_SCK_PIN] = { /* SPI1 SCK on PA1, AF0 */ - .port = WHAL_STM32C0_GPIO_PORT_A, - .pin = 1, - .mode = WHAL_STM32C0_GPIO_MODE_ALTFN, - .outType = WHAL_STM32C0_GPIO_OUTTYPE_PUSHPULL, - .speed = WHAL_STM32C0_GPIO_SPEED_FAST, - .pull = WHAL_STM32C0_GPIO_PULL_NONE, - .altFn = 0, - }, - [SPI_MISO_PIN] = { /* SPI1 MISO on PA6, AF0 */ - .port = WHAL_STM32C0_GPIO_PORT_A, - .pin = 6, - .mode = WHAL_STM32C0_GPIO_MODE_ALTFN, - .outType = WHAL_STM32C0_GPIO_OUTTYPE_PUSHPULL, - .speed = WHAL_STM32C0_GPIO_SPEED_FAST, - .pull = WHAL_STM32C0_GPIO_PULL_NONE, - .altFn = 0, - }, - [SPI_MOSI_PIN] = { /* SPI1 MOSI on PA7, AF0 */ - .port = WHAL_STM32C0_GPIO_PORT_A, - .pin = 7, - .mode = WHAL_STM32C0_GPIO_MODE_ALTFN, - .outType = WHAL_STM32C0_GPIO_OUTTYPE_PUSHPULL, - .speed = WHAL_STM32C0_GPIO_SPEED_FAST, - .pull = WHAL_STM32C0_GPIO_PULL_NONE, - .altFn = 0, - }, + /* LD4 Green LED on PA5 */ + [LED_PIN] = WHAL_STM32C0_GPIO_PIN( + WHAL_STM32C0_GPIO_PORT_A, 5, WHAL_STM32C0_GPIO_MODE_OUT, + WHAL_STM32C0_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32C0_GPIO_SPEED_LOW, + WHAL_STM32C0_GPIO_PULL_NONE, 0), + /* USART1 TX on PB6, AF0 */ + [UART_TX_PIN] = WHAL_STM32C0_GPIO_PIN( + WHAL_STM32C0_GPIO_PORT_B, 6, WHAL_STM32C0_GPIO_MODE_ALTFN, + WHAL_STM32C0_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32C0_GPIO_SPEED_FAST, + WHAL_STM32C0_GPIO_PULL_UP, 0), + /* USART1 RX on PB7, AF0 */ + [UART_RX_PIN] = WHAL_STM32C0_GPIO_PIN( + WHAL_STM32C0_GPIO_PORT_B, 7, WHAL_STM32C0_GPIO_MODE_ALTFN, + WHAL_STM32C0_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32C0_GPIO_SPEED_FAST, + WHAL_STM32C0_GPIO_PULL_UP, 0), + /* SPI1 SCK on PA1, AF0 */ + [SPI_SCK_PIN] = WHAL_STM32C0_GPIO_PIN( + WHAL_STM32C0_GPIO_PORT_A, 1, WHAL_STM32C0_GPIO_MODE_ALTFN, + WHAL_STM32C0_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32C0_GPIO_SPEED_FAST, + WHAL_STM32C0_GPIO_PULL_NONE, 0), + /* SPI1 MISO on PA6, AF0 */ + [SPI_MISO_PIN] = WHAL_STM32C0_GPIO_PIN( + WHAL_STM32C0_GPIO_PORT_A, 6, WHAL_STM32C0_GPIO_MODE_ALTFN, + WHAL_STM32C0_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32C0_GPIO_SPEED_FAST, + WHAL_STM32C0_GPIO_PULL_NONE, 0), + /* SPI1 MOSI on PA7, AF0 */ + [SPI_MOSI_PIN] = WHAL_STM32C0_GPIO_PIN( + WHAL_STM32C0_GPIO_PORT_A, 7, WHAL_STM32C0_GPIO_MODE_ALTFN, + WHAL_STM32C0_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32C0_GPIO_SPEED_FAST, + WHAL_STM32C0_GPIO_PULL_NONE, 0), }, .pinCount = PIN_COUNT, }, diff --git a/boards/stm32f411_blackpill/board.c b/boards/stm32f411_blackpill/board.c index 5de2c25..6fd5a6b 100644 --- a/boards/stm32f411_blackpill/board.c +++ b/boards/stm32f411_blackpill/board.c @@ -70,60 +70,36 @@ whal_Gpio g_whalGpio = { .cfg = &(whal_Stm32f4Gpio_Cfg) { .pinCfg = (whal_Stm32f4Gpio_PinCfg[PIN_COUNT]) { - [LED_PIN] = { /* LED on PC13 (active low) */ - .port = WHAL_STM32F4_GPIO_PORT_C, - .pin = 13, - .mode = WHAL_STM32F4_GPIO_MODE_OUT, - .outType = WHAL_STM32F4_GPIO_OUTTYPE_PUSHPULL, - .speed = WHAL_STM32F4_GPIO_SPEED_LOW, - .pull = WHAL_STM32F4_GPIO_PULL_NONE, - .altFn = 0, - }, - [UART_TX_PIN] = { /* USART2 TX on PA2 (AF7) */ - .port = WHAL_STM32F4_GPIO_PORT_A, - .pin = 2, - .mode = WHAL_STM32F4_GPIO_MODE_ALTFN, - .outType = WHAL_STM32F4_GPIO_OUTTYPE_PUSHPULL, - .speed = WHAL_STM32F4_GPIO_SPEED_FAST, - .pull = WHAL_STM32F4_GPIO_PULL_UP, - .altFn = 7, - }, - [UART_RX_PIN] = { /* USART2 RX on PA3 (AF7) */ - .port = WHAL_STM32F4_GPIO_PORT_A, - .pin = 3, - .mode = WHAL_STM32F4_GPIO_MODE_ALTFN, - .outType = WHAL_STM32F4_GPIO_OUTTYPE_PUSHPULL, - .speed = WHAL_STM32F4_GPIO_SPEED_FAST, - .pull = WHAL_STM32F4_GPIO_PULL_UP, - .altFn = 7, - }, - [SPI_SCK_PIN] = { /* SPI1 SCK on PA5 (AF5) */ - .port = WHAL_STM32F4_GPIO_PORT_A, - .pin = 5, - .mode = WHAL_STM32F4_GPIO_MODE_ALTFN, - .outType = WHAL_STM32F4_GPIO_OUTTYPE_PUSHPULL, - .speed = WHAL_STM32F4_GPIO_SPEED_FAST, - .pull = WHAL_STM32F4_GPIO_PULL_NONE, - .altFn = 5, - }, - [SPI_MISO_PIN] = { /* SPI1 MISO on PA6 (AF5) */ - .port = WHAL_STM32F4_GPIO_PORT_A, - .pin = 6, - .mode = WHAL_STM32F4_GPIO_MODE_ALTFN, - .outType = WHAL_STM32F4_GPIO_OUTTYPE_PUSHPULL, - .speed = WHAL_STM32F4_GPIO_SPEED_FAST, - .pull = WHAL_STM32F4_GPIO_PULL_NONE, - .altFn = 5, - }, - [SPI_MOSI_PIN] = { /* SPI1 MOSI on PA7 (AF5) */ - .port = WHAL_STM32F4_GPIO_PORT_A, - .pin = 7, - .mode = WHAL_STM32F4_GPIO_MODE_ALTFN, - .outType = WHAL_STM32F4_GPIO_OUTTYPE_PUSHPULL, - .speed = WHAL_STM32F4_GPIO_SPEED_FAST, - .pull = WHAL_STM32F4_GPIO_PULL_NONE, - .altFn = 5, - }, + /* LED on PC13 (active low) */ + [LED_PIN] = WHAL_STM32F4_GPIO_PIN( + WHAL_STM32F4_GPIO_PORT_C, 13, WHAL_STM32F4_GPIO_MODE_OUT, + WHAL_STM32F4_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32F4_GPIO_SPEED_LOW, + WHAL_STM32F4_GPIO_PULL_NONE, 0), + /* USART2 TX on PA2 (AF7) */ + [UART_TX_PIN] = WHAL_STM32F4_GPIO_PIN( + WHAL_STM32F4_GPIO_PORT_A, 2, WHAL_STM32F4_GPIO_MODE_ALTFN, + WHAL_STM32F4_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32F4_GPIO_SPEED_FAST, + WHAL_STM32F4_GPIO_PULL_UP, 7), + /* USART2 RX on PA3 (AF7) */ + [UART_RX_PIN] = WHAL_STM32F4_GPIO_PIN( + WHAL_STM32F4_GPIO_PORT_A, 3, WHAL_STM32F4_GPIO_MODE_ALTFN, + WHAL_STM32F4_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32F4_GPIO_SPEED_FAST, + WHAL_STM32F4_GPIO_PULL_UP, 7), + /* SPI1 SCK on PA5 (AF5) */ + [SPI_SCK_PIN] = WHAL_STM32F4_GPIO_PIN( + WHAL_STM32F4_GPIO_PORT_A, 5, WHAL_STM32F4_GPIO_MODE_ALTFN, + WHAL_STM32F4_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32F4_GPIO_SPEED_FAST, + WHAL_STM32F4_GPIO_PULL_NONE, 5), + /* SPI1 MISO on PA6 (AF5) */ + [SPI_MISO_PIN] = WHAL_STM32F4_GPIO_PIN( + WHAL_STM32F4_GPIO_PORT_A, 6, WHAL_STM32F4_GPIO_MODE_ALTFN, + WHAL_STM32F4_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32F4_GPIO_SPEED_FAST, + WHAL_STM32F4_GPIO_PULL_NONE, 5), + /* SPI1 MOSI on PA7 (AF5) */ + [SPI_MOSI_PIN] = WHAL_STM32F4_GPIO_PIN( + WHAL_STM32F4_GPIO_PORT_A, 7, WHAL_STM32F4_GPIO_MODE_ALTFN, + WHAL_STM32F4_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32F4_GPIO_SPEED_FAST, + WHAL_STM32F4_GPIO_PULL_NONE, 5), }, .pinCount = PIN_COUNT, }, diff --git a/boards/stm32h563zi_nucleo/board.c b/boards/stm32h563zi_nucleo/board.c index e2f4de4..9b81a04 100644 --- a/boards/stm32h563zi_nucleo/board.c +++ b/boards/stm32h563zi_nucleo/board.c @@ -69,140 +69,86 @@ whal_Gpio g_whalGpio = { .cfg = &(whal_Stm32h5Gpio_Cfg) { .pinCfg = (whal_Stm32h5Gpio_PinCfg[PIN_COUNT]) { - [LED_PIN] = { /* LD1 Green LED on PB0 */ - .port = WHAL_STM32H5_GPIO_PORT_B, - .pin = 0, - .mode = WHAL_STM32H5_GPIO_MODE_OUT, - .outType = WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, - .speed = WHAL_STM32H5_GPIO_SPEED_LOW, - .pull = WHAL_STM32H5_GPIO_PULL_NONE, - .altFn = 0, - }, - [UART_TX_PIN] = { /* USART2 TX on PD5 */ - .port = WHAL_STM32H5_GPIO_PORT_D, - .pin = 5, - .mode = WHAL_STM32H5_GPIO_MODE_ALTFN, - .outType = WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, - .speed = WHAL_STM32H5_GPIO_SPEED_FAST, - .pull = WHAL_STM32H5_GPIO_PULL_UP, - .altFn = 7, - }, - [UART_RX_PIN] = { /* USART2 RX on PD6 */ - .port = WHAL_STM32H5_GPIO_PORT_D, - .pin = 6, - .mode = WHAL_STM32H5_GPIO_MODE_ALTFN, - .outType = WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, - .speed = WHAL_STM32H5_GPIO_SPEED_FAST, - .pull = WHAL_STM32H5_GPIO_PULL_UP, - .altFn = 7, - }, - [SPI_SCK_PIN] = { /* SPI1 SCK on PA5 */ - .port = WHAL_STM32H5_GPIO_PORT_A, - .pin = 5, - .mode = WHAL_STM32H5_GPIO_MODE_ALTFN, - .outType = WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, - .speed = WHAL_STM32H5_GPIO_SPEED_FAST, - .pull = WHAL_STM32H5_GPIO_PULL_NONE, - .altFn = 5, - }, - [SPI_MISO_PIN] = { /* SPI1 MISO on PG9 */ - .port = WHAL_STM32H5_GPIO_PORT_G, - .pin = 9, - .mode = WHAL_STM32H5_GPIO_MODE_ALTFN, - .outType = WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, - .speed = WHAL_STM32H5_GPIO_SPEED_FAST, - .pull = WHAL_STM32H5_GPIO_PULL_NONE, - .altFn = 5, - }, - [SPI_MOSI_PIN] = { /* SPI1 MOSI on PB5 */ - .port = WHAL_STM32H5_GPIO_PORT_B, - .pin = 5, - .mode = WHAL_STM32H5_GPIO_MODE_ALTFN, - .outType = WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, - .speed = WHAL_STM32H5_GPIO_SPEED_FAST, - .pull = WHAL_STM32H5_GPIO_PULL_NONE, - .altFn = 5, - }, - [SPI_CS_PIN] = { /* SPI CS on PD14 */ - .port = WHAL_STM32H5_GPIO_PORT_D, - .pin = 14, - .mode = WHAL_STM32H5_GPIO_MODE_OUT, - .outType = WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, - .speed = WHAL_STM32H5_GPIO_SPEED_FAST, - .pull = WHAL_STM32H5_GPIO_PULL_UP, - }, - [ETH_RMII_REF_CLK_PIN] = { /* RMII REF_CLK on PA1 */ - .port = WHAL_STM32H5_GPIO_PORT_A, - .pin = 1, - .mode = WHAL_STM32H5_GPIO_MODE_ALTFN, - .speed = WHAL_STM32H5_GPIO_SPEED_HIGH, - .pull = WHAL_STM32H5_GPIO_PULL_NONE, - .altFn = 11, - }, - [ETH_RMII_MDIO_PIN] = { /* RMII MDIO on PA2 */ - .port = WHAL_STM32H5_GPIO_PORT_A, - .pin = 2, - .mode = WHAL_STM32H5_GPIO_MODE_ALTFN, - .speed = WHAL_STM32H5_GPIO_SPEED_HIGH, - .pull = WHAL_STM32H5_GPIO_PULL_NONE, - .altFn = 11, - }, - [ETH_RMII_MDC_PIN] = { /* RMII MDC on PC1 */ - .port = WHAL_STM32H5_GPIO_PORT_C, - .pin = 1, - .mode = WHAL_STM32H5_GPIO_MODE_ALTFN, - .speed = WHAL_STM32H5_GPIO_SPEED_HIGH, - .pull = WHAL_STM32H5_GPIO_PULL_NONE, - .altFn = 11, - }, - [ETH_RMII_CRS_DV_PIN] = { /* RMII CRS_DV on PA7 */ - .port = WHAL_STM32H5_GPIO_PORT_A, - .pin = 7, - .mode = WHAL_STM32H5_GPIO_MODE_ALTFN, - .speed = WHAL_STM32H5_GPIO_SPEED_HIGH, - .pull = WHAL_STM32H5_GPIO_PULL_NONE, - .altFn = 11, - }, - [ETH_RMII_RXD0_PIN] = { /* RMII RXD0 on PC4 */ - .port = WHAL_STM32H5_GPIO_PORT_C, - .pin = 4, - .mode = WHAL_STM32H5_GPIO_MODE_ALTFN, - .speed = WHAL_STM32H5_GPIO_SPEED_HIGH, - .pull = WHAL_STM32H5_GPIO_PULL_NONE, - .altFn = 11, - }, - [ETH_RMII_RXD1_PIN] = { /* RMII RXD1 on PC5 */ - .port = WHAL_STM32H5_GPIO_PORT_C, - .pin = 5, - .mode = WHAL_STM32H5_GPIO_MODE_ALTFN, - .speed = WHAL_STM32H5_GPIO_SPEED_HIGH, - .pull = WHAL_STM32H5_GPIO_PULL_NONE, - .altFn = 11, - }, - [ETH_RMII_TX_EN_PIN] = { /* RMII TX_EN on PG11 */ - .port = WHAL_STM32H5_GPIO_PORT_G, - .pin = 11, - .mode = WHAL_STM32H5_GPIO_MODE_ALTFN, - .speed = WHAL_STM32H5_GPIO_SPEED_HIGH, - .pull = WHAL_STM32H5_GPIO_PULL_NONE, - .altFn = 11, - }, - [ETH_RMII_TXD0_PIN] = { /* RMII TXD0 on PG13 */ - .port = WHAL_STM32H5_GPIO_PORT_G, - .pin = 13, - .mode = WHAL_STM32H5_GPIO_MODE_ALTFN, - .speed = WHAL_STM32H5_GPIO_SPEED_HIGH, - .pull = WHAL_STM32H5_GPIO_PULL_NONE, - .altFn = 11, - }, - [ETH_RMII_TXD1_PIN] = { /* RMII TXD1 on PB15 */ - .port = WHAL_STM32H5_GPIO_PORT_B, - .pin = 15, - .mode = WHAL_STM32H5_GPIO_MODE_ALTFN, - .speed = WHAL_STM32H5_GPIO_SPEED_HIGH, - .pull = WHAL_STM32H5_GPIO_PULL_NONE, - .altFn = 11, - }, + /* LD1 Green LED on PB0 */ + [LED_PIN] = WHAL_STM32H5_GPIO_PIN( + WHAL_STM32H5_GPIO_PORT_B, 0, WHAL_STM32H5_GPIO_MODE_OUT, + WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_LOW, + WHAL_STM32H5_GPIO_PULL_NONE, 0), + /* USART2 TX on PD5 */ + [UART_TX_PIN] = WHAL_STM32H5_GPIO_PIN( + WHAL_STM32H5_GPIO_PORT_D, 5, WHAL_STM32H5_GPIO_MODE_ALTFN, + WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_FAST, + WHAL_STM32H5_GPIO_PULL_UP, 7), + /* USART2 RX on PD6 */ + [UART_RX_PIN] = WHAL_STM32H5_GPIO_PIN( + WHAL_STM32H5_GPIO_PORT_D, 6, WHAL_STM32H5_GPIO_MODE_ALTFN, + WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_FAST, + WHAL_STM32H5_GPIO_PULL_UP, 7), + /* SPI1 SCK on PA5 */ + [SPI_SCK_PIN] = WHAL_STM32H5_GPIO_PIN( + WHAL_STM32H5_GPIO_PORT_A, 5, WHAL_STM32H5_GPIO_MODE_ALTFN, + WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_FAST, + WHAL_STM32H5_GPIO_PULL_NONE, 5), + /* SPI1 MISO on PG9 */ + [SPI_MISO_PIN] = WHAL_STM32H5_GPIO_PIN( + WHAL_STM32H5_GPIO_PORT_G, 9, WHAL_STM32H5_GPIO_MODE_ALTFN, + WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_FAST, + WHAL_STM32H5_GPIO_PULL_NONE, 5), + /* SPI1 MOSI on PB5 */ + [SPI_MOSI_PIN] = WHAL_STM32H5_GPIO_PIN( + WHAL_STM32H5_GPIO_PORT_B, 5, WHAL_STM32H5_GPIO_MODE_ALTFN, + WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_FAST, + WHAL_STM32H5_GPIO_PULL_NONE, 5), + /* SPI CS on PD14 */ + [SPI_CS_PIN] = WHAL_STM32H5_GPIO_PIN( + WHAL_STM32H5_GPIO_PORT_D, 14, WHAL_STM32H5_GPIO_MODE_OUT, + WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_FAST, + WHAL_STM32H5_GPIO_PULL_UP, 0), + /* RMII REF_CLK on PA1 */ + [ETH_RMII_REF_CLK_PIN] = WHAL_STM32H5_GPIO_PIN( + WHAL_STM32H5_GPIO_PORT_A, 1, WHAL_STM32H5_GPIO_MODE_ALTFN, + WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_HIGH, + WHAL_STM32H5_GPIO_PULL_NONE, 11), + /* RMII MDIO on PA2 */ + [ETH_RMII_MDIO_PIN] = WHAL_STM32H5_GPIO_PIN( + WHAL_STM32H5_GPIO_PORT_A, 2, WHAL_STM32H5_GPIO_MODE_ALTFN, + WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_HIGH, + WHAL_STM32H5_GPIO_PULL_NONE, 11), + /* RMII MDC on PC1 */ + [ETH_RMII_MDC_PIN] = WHAL_STM32H5_GPIO_PIN( + WHAL_STM32H5_GPIO_PORT_C, 1, WHAL_STM32H5_GPIO_MODE_ALTFN, + WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_HIGH, + WHAL_STM32H5_GPIO_PULL_NONE, 11), + /* RMII CRS_DV on PA7 */ + [ETH_RMII_CRS_DV_PIN] = WHAL_STM32H5_GPIO_PIN( + WHAL_STM32H5_GPIO_PORT_A, 7, WHAL_STM32H5_GPIO_MODE_ALTFN, + WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_HIGH, + WHAL_STM32H5_GPIO_PULL_NONE, 11), + /* RMII RXD0 on PC4 */ + [ETH_RMII_RXD0_PIN] = WHAL_STM32H5_GPIO_PIN( + WHAL_STM32H5_GPIO_PORT_C, 4, WHAL_STM32H5_GPIO_MODE_ALTFN, + WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_HIGH, + WHAL_STM32H5_GPIO_PULL_NONE, 11), + /* RMII RXD1 on PC5 */ + [ETH_RMII_RXD1_PIN] = WHAL_STM32H5_GPIO_PIN( + WHAL_STM32H5_GPIO_PORT_C, 5, WHAL_STM32H5_GPIO_MODE_ALTFN, + WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_HIGH, + WHAL_STM32H5_GPIO_PULL_NONE, 11), + /* RMII TX_EN on PG11 */ + [ETH_RMII_TX_EN_PIN] = WHAL_STM32H5_GPIO_PIN( + WHAL_STM32H5_GPIO_PORT_G, 11, WHAL_STM32H5_GPIO_MODE_ALTFN, + WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_HIGH, + WHAL_STM32H5_GPIO_PULL_NONE, 11), + /* RMII TXD0 on PG13 */ + [ETH_RMII_TXD0_PIN] = WHAL_STM32H5_GPIO_PIN( + WHAL_STM32H5_GPIO_PORT_G, 13, WHAL_STM32H5_GPIO_MODE_ALTFN, + WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_HIGH, + WHAL_STM32H5_GPIO_PULL_NONE, 11), + /* RMII TXD1 on PB15 */ + [ETH_RMII_TXD1_PIN] = WHAL_STM32H5_GPIO_PIN( + WHAL_STM32H5_GPIO_PORT_B, 15, WHAL_STM32H5_GPIO_MODE_ALTFN, + WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_HIGH, + WHAL_STM32H5_GPIO_PULL_NONE, 11), }, .pinCount = PIN_COUNT, }, @@ -278,8 +224,8 @@ static uint8_t ethRxBufs[ETH_RX_DESC_COUNT * ETH_RX_BUF_SIZE] whal_Eth g_whalEth = { WHAL_STM32H563_ETH_DEVICE, + .macAddr = {0x00, 0x80, 0xE1, 0x00, 0x00, 0x01}, .cfg = &(whal_Stm32h5Eth_Cfg) { - .macAddr = {0x00, 0x80, 0xE1, 0x00, 0x00, 0x01}, .txDescs = ethTxDescs, .txBufs = ethTxBufs, .txDescCount = ETH_TX_DESC_COUNT, diff --git a/boards/stm32wb55xx_nucleo/board.c b/boards/stm32wb55xx_nucleo/board.c index b2146bf..fa1384e 100644 --- a/boards/stm32wb55xx_nucleo/board.c +++ b/boards/stm32wb55xx_nucleo/board.c @@ -68,86 +68,51 @@ whal_Gpio g_whalGpio = { .cfg = &(whal_Stm32wbGpio_Cfg) { .pinCfg = (whal_Stm32wbGpio_PinCfg[PIN_COUNT]) { - [LED_PIN] = { /* LED */ - .port = WHAL_STM32WB_GPIO_PORT_B, - .pin = 5, - .mode = WHAL_STM32WB_GPIO_MODE_OUT, - .outType = WHAL_STM32WB_GPIO_OUTTYPE_PUSHPULL, - .speed = WHAL_STM32WB_GPIO_SPEED_LOW, - .pull = WHAL_STM32WB_GPIO_PULL_UP, - .altFn = 0, - }, - [UART_TX_PIN] = { /* UART1 TX */ - .port = WHAL_STM32WB_GPIO_PORT_B, - .pin = 6, - .mode = WHAL_STM32WB_GPIO_MODE_ALTFN, - .outType = WHAL_STM32WB_GPIO_OUTTYPE_PUSHPULL, - .speed = WHAL_STM32WB_GPIO_SPEED_FAST, - .pull = WHAL_STM32WB_GPIO_PULL_UP, - .altFn = 7, - }, - [UART_RX_PIN] = { /* UART1 RX */ - .port = WHAL_STM32WB_GPIO_PORT_B, - .pin = 7, - .mode = WHAL_STM32WB_GPIO_MODE_ALTFN, - .outType = WHAL_STM32WB_GPIO_OUTTYPE_PUSHPULL, - .speed = WHAL_STM32WB_GPIO_SPEED_FAST, - .pull = WHAL_STM32WB_GPIO_PULL_UP, - .altFn = 7, - }, - [SPI_SCK_PIN] = { /* SPI1 SCK */ - .port = WHAL_STM32WB_GPIO_PORT_A, - .pin = 5, - .mode = WHAL_STM32WB_GPIO_MODE_ALTFN, - .outType = WHAL_STM32WB_GPIO_OUTTYPE_PUSHPULL, - .speed = WHAL_STM32WB_GPIO_SPEED_FAST, - .pull = WHAL_STM32WB_GPIO_PULL_NONE, - .altFn = 5, - }, - [SPI_MISO_PIN] = { /* SPI1 MISO */ - .port = WHAL_STM32WB_GPIO_PORT_A, - .pin = 6, - .mode = WHAL_STM32WB_GPIO_MODE_ALTFN, - .outType = WHAL_STM32WB_GPIO_OUTTYPE_PUSHPULL, - .speed = WHAL_STM32WB_GPIO_SPEED_FAST, - .pull = WHAL_STM32WB_GPIO_PULL_NONE, - .altFn = 5, - }, - [SPI_MOSI_PIN] = { /* SPI1 MOSI */ - .port = WHAL_STM32WB_GPIO_PORT_A, - .pin = 7, - .mode = WHAL_STM32WB_GPIO_MODE_ALTFN, - .outType = WHAL_STM32WB_GPIO_OUTTYPE_PUSHPULL, - .speed = WHAL_STM32WB_GPIO_SPEED_FAST, - .pull = WHAL_STM32WB_GPIO_PULL_NONE, - .altFn = 5, - }, - [SPI_CS_PIN] = { /* SPI CS */ - .port = WHAL_STM32WB_GPIO_PORT_A, - .pin = 4, - .mode = WHAL_STM32WB_GPIO_MODE_OUT, - .outType = WHAL_STM32WB_GPIO_OUTTYPE_PUSHPULL, - .speed = WHAL_STM32WB_GPIO_SPEED_FAST, - .pull = WHAL_STM32WB_GPIO_PULL_UP, - }, - [I2C_SCL_PIN] = { /* I2C1 SCL */ - .port = WHAL_STM32WB_GPIO_PORT_B, - .pin = 8, - .mode = WHAL_STM32WB_GPIO_MODE_ALTFN, - .outType = WHAL_STM32WB_GPIO_OUTTYPE_OPENDRAIN, - .speed = WHAL_STM32WB_GPIO_SPEED_FAST, - .pull = WHAL_STM32WB_GPIO_PULL_UP, - .altFn = 4, - }, - [I2C_SDA_PIN] = { /* I2C1 SDA */ - .port = WHAL_STM32WB_GPIO_PORT_B, - .pin = 9, - .mode = WHAL_STM32WB_GPIO_MODE_ALTFN, - .outType = WHAL_STM32WB_GPIO_OUTTYPE_OPENDRAIN, - .speed = WHAL_STM32WB_GPIO_SPEED_FAST, - .pull = WHAL_STM32WB_GPIO_PULL_UP, - .altFn = 4, - }, + /* LED: PB5, output, push-pull, low speed, pull-up */ + [LED_PIN] = WHAL_STM32WB_GPIO_PIN( + WHAL_STM32WB_GPIO_PORT_B, 5, WHAL_STM32WB_GPIO_MODE_OUT, + WHAL_STM32WB_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32WB_GPIO_SPEED_LOW, + WHAL_STM32WB_GPIO_PULL_UP, 0), + /* UART1 TX: PB6, AF7 */ + [UART_TX_PIN] = WHAL_STM32WB_GPIO_PIN( + WHAL_STM32WB_GPIO_PORT_B, 6, WHAL_STM32WB_GPIO_MODE_ALTFN, + WHAL_STM32WB_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32WB_GPIO_SPEED_FAST, + WHAL_STM32WB_GPIO_PULL_UP, 7), + /* UART1 RX: PB7, AF7 */ + [UART_RX_PIN] = WHAL_STM32WB_GPIO_PIN( + WHAL_STM32WB_GPIO_PORT_B, 7, WHAL_STM32WB_GPIO_MODE_ALTFN, + WHAL_STM32WB_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32WB_GPIO_SPEED_FAST, + WHAL_STM32WB_GPIO_PULL_UP, 7), + /* SPI1 SCK: PA5, AF5 */ + [SPI_SCK_PIN] = WHAL_STM32WB_GPIO_PIN( + WHAL_STM32WB_GPIO_PORT_A, 5, WHAL_STM32WB_GPIO_MODE_ALTFN, + WHAL_STM32WB_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32WB_GPIO_SPEED_FAST, + WHAL_STM32WB_GPIO_PULL_NONE, 5), + /* SPI1 MISO: PA6, AF5 */ + [SPI_MISO_PIN] = WHAL_STM32WB_GPIO_PIN( + WHAL_STM32WB_GPIO_PORT_A, 6, WHAL_STM32WB_GPIO_MODE_ALTFN, + WHAL_STM32WB_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32WB_GPIO_SPEED_FAST, + WHAL_STM32WB_GPIO_PULL_NONE, 5), + /* SPI1 MOSI: PA7, AF5 */ + [SPI_MOSI_PIN] = WHAL_STM32WB_GPIO_PIN( + WHAL_STM32WB_GPIO_PORT_A, 7, WHAL_STM32WB_GPIO_MODE_ALTFN, + WHAL_STM32WB_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32WB_GPIO_SPEED_FAST, + WHAL_STM32WB_GPIO_PULL_NONE, 5), + /* SPI CS: PA4, output, push-pull */ + [SPI_CS_PIN] = WHAL_STM32WB_GPIO_PIN( + WHAL_STM32WB_GPIO_PORT_A, 4, WHAL_STM32WB_GPIO_MODE_OUT, + WHAL_STM32WB_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32WB_GPIO_SPEED_FAST, + WHAL_STM32WB_GPIO_PULL_UP, 0), + /* I2C1 SCL: PB8, AF4, open-drain */ + [I2C_SCL_PIN] = WHAL_STM32WB_GPIO_PIN( + WHAL_STM32WB_GPIO_PORT_B, 8, WHAL_STM32WB_GPIO_MODE_ALTFN, + WHAL_STM32WB_GPIO_OUTTYPE_OPENDRAIN, WHAL_STM32WB_GPIO_SPEED_FAST, + WHAL_STM32WB_GPIO_PULL_UP, 4), + /* I2C1 SDA: PB9, AF4, open-drain */ + [I2C_SDA_PIN] = WHAL_STM32WB_GPIO_PIN( + WHAL_STM32WB_GPIO_PORT_B, 9, WHAL_STM32WB_GPIO_MODE_ALTFN, + WHAL_STM32WB_GPIO_OUTTYPE_OPENDRAIN, WHAL_STM32WB_GPIO_SPEED_FAST, + WHAL_STM32WB_GPIO_PULL_UP, 4), }, .pinCount = PIN_COUNT, }, diff --git a/src/eth/stm32h5_eth.c b/src/eth/stm32h5_eth.c index 82f0a7d..a05d7e4 100644 --- a/src/eth/stm32h5_eth.c +++ b/src/eth/stm32h5_eth.c @@ -206,13 +206,13 @@ whal_Error whal_Stm32h5Eth_Init(whal_Eth *ethDev) /* MAC address */ whal_Reg_Write(base, ETH_MACA0LR_REG, - ((uint32_t)cfg->macAddr[3] << 24) | - ((uint32_t)cfg->macAddr[2] << 16) | - ((uint32_t)cfg->macAddr[1] << 8) | - ((uint32_t)cfg->macAddr[0])); + ((uint32_t)ethDev->macAddr[3] << 24) | + ((uint32_t)ethDev->macAddr[2] << 16) | + ((uint32_t)ethDev->macAddr[1] << 8) | + ((uint32_t)ethDev->macAddr[0])); whal_Reg_Write(base, ETH_MACA0HR_REG, - ((uint32_t)cfg->macAddr[5] << 8) | - ((uint32_t)cfg->macAddr[4])); + ((uint32_t)ethDev->macAddr[5] << 8) | + ((uint32_t)ethDev->macAddr[4])); /* Reset ring tracking state */ cfg->txHead = 0; diff --git a/src/flash/stm32h5_flash.c b/src/flash/stm32h5_flash.c index a60007a..674b6be 100644 --- a/src/flash/stm32h5_flash.c +++ b/src/flash/stm32h5_flash.c @@ -292,18 +292,15 @@ whal_Error whal_Stm32h5Flash_Erase(whal_Flash *flashDev, size_t addr, size_t bank = (sector >= FLASH_SECTORS_PER_BANK) ? 1 : 0; size_t sectorInBank = sector - (bank * FLASH_SECTORS_PER_BANK); - /* Configure: sector erase, sector number, bank select */ + /* Configure and start sector erase in one write */ whal_Reg_Update(regmap->base, FLASH_NSCR_REG, FLASH_NSCR_SER_Msk | FLASH_NSCR_SNB_Msk | - FLASH_NSCR_BKSEL_Msk, + FLASH_NSCR_BKSEL_Msk | FLASH_NSCR_STRT_Msk, whal_SetBits(FLASH_NSCR_SER_Msk, FLASH_NSCR_SER_Pos, 1) | whal_SetBits(FLASH_NSCR_SNB_Msk, FLASH_NSCR_SNB_Pos, sectorInBank) | whal_SetBits(FLASH_NSCR_BKSEL_Msk, FLASH_NSCR_BKSEL_Pos, - bank)); - - /* Start erase */ - whal_Reg_Update(regmap->base, FLASH_NSCR_REG, FLASH_NSCR_STRT_Msk, + bank) | whal_SetBits(FLASH_NSCR_STRT_Msk, FLASH_NSCR_STRT_Pos, 1)); err = WaitNotBusy(regmap->base, cfg->timeout); @@ -322,6 +319,20 @@ whal_Error whal_Stm32h5Flash_Erase(whal_Flash *flashDev, size_t addr, return err; } +#define FLASH_ACR_LATENCY_WRHIGHFREQ_Msk 0x3FUL + +whal_Error whal_Stm32h5Flash_Ext_SetLatency(whal_Flash *flashDev, + uint8_t latency) +{ + if (!flashDev) + return WHAL_EINVAL; + + whal_Reg_Update(flashDev->regmap.base, FLASH_ACR_REG, + FLASH_ACR_LATENCY_WRHIGHFREQ_Msk, latency); + + return WHAL_SUCCESS; +} + const whal_FlashDriver whal_Stm32h5Flash_Driver = { .Init = whal_Stm32h5Flash_Init, .Deinit = whal_Stm32h5Flash_Deinit, diff --git a/src/gpio/stm32wb_gpio.c b/src/gpio/stm32wb_gpio.c index e77f45b..bd335cf 100644 --- a/src/gpio/stm32wb_gpio.c +++ b/src/gpio/stm32wb_gpio.c @@ -39,54 +39,45 @@ * a 64-bit value for easier manipulation. Each pin uses 4 bits to select * one of 16 alternate functions (AF0-AF15). */ -static inline void whal_Stm32wbGpio_InitAltFn(whal_Regmap *portReg, whal_Stm32wbGpio_PinCfg *pinCfg) -{ - uint8_t pin = pinCfg->pin; - size_t offset = (pin < 8) ? GPIO_ALTFNL_REG : GPIO_ALTFNH_REG; - uint8_t pos = (pin & 7) << 2; - size_t mask = WHAL_BITMASK(4) << pos; - - whal_Reg_Update(portReg->base, offset, mask, - whal_SetBits(mask, pos, pinCfg->altFn)); -} - /* * Initialize a single GPIO pin with the specified configuration. */ -static inline whal_Error whal_Stm32wbGpio_InitPin(whal_Gpio *gpioDev, whal_Stm32wbGpio_PinCfg *pinCfg) +static inline whal_Error whal_Stm32wbGpio_InitPin(whal_Gpio *gpioDev, + whal_Stm32wbGpio_PinCfg cfg) { - whal_Regmap portReg; + uint8_t pin = WHAL_STM32WB_GPIO_GET_PIN(cfg); + size_t portBase; + uint8_t pos2; + size_t mask2, mask1; - if (pinCfg->pin > 15) { + if (pin > 15) return WHAL_EINVAL; - } - /* Calculate port base address */ - portReg.size = GPIO_PORT_SIZE; - portReg.base = (size_t)(gpioDev->regmap.base + (pinCfg->port * GPIO_PORT_SIZE)); + portBase = gpioDev->regmap.base + + (WHAL_STM32WB_GPIO_GET_PORT(cfg) * GPIO_PORT_SIZE); + pos2 = pin << 1; + mask2 = WHAL_BITMASK(2) << pos2; + mask1 = 1UL << pin; - uint8_t pin = pinCfg->pin; - /* 2-bit field mask for MODE, SPEED, PULL registers */ - uint8_t maskBit = pin << 1; - size_t mask1 = (WHAL_BITMASK(2) << maskBit); - /* 1-bit mask for OUTTYPE register */ - size_t mask2 = (1UL << pin); + whal_Reg_Update(portBase, GPIO_MODE_REG, mask2, + WHAL_STM32WB_GPIO_GET_MODE(cfg) << pos2); - /* Configure pin mode (input/output/altfn/analog) */ - whal_Reg_Update(portReg.base, GPIO_MODE_REG, mask1, - whal_SetBits(mask1, maskBit, pinCfg->mode)); + whal_Reg_Update(portBase, GPIO_SPEED_REG, mask2, + WHAL_STM32WB_GPIO_GET_SPEED(cfg) << pos2); - /* Configure output speed */ - whal_Reg_Update(portReg.base, GPIO_SPEED_REG, mask1, - whal_SetBits(mask1, maskBit, pinCfg->speed)); + whal_Reg_Update(portBase, GPIO_PULL_REG, mask2, + WHAL_STM32WB_GPIO_GET_PULL(cfg) << pos2); - /* Configure output type (push-pull or open-drain) */ - whal_Reg_Update(portReg.base, GPIO_OUTTYPE_REG, mask2, - whal_SetBits(mask2, pin, pinCfg->outType)); + whal_Reg_Update(portBase, GPIO_OUTTYPE_REG, mask1, + WHAL_STM32WB_GPIO_GET_OUTTYPE(cfg) << pin); - /* Configure alternate function if in ALTFN mode */ - if (pinCfg->mode == WHAL_STM32WB_GPIO_MODE_ALTFN) { - whal_Stm32wbGpio_InitAltFn(&portReg, pinCfg); + if (WHAL_STM32WB_GPIO_GET_MODE(cfg) == WHAL_STM32WB_GPIO_MODE_ALTFN) { + uint8_t afPos = (pin & 7) << 2; + + whal_Reg_Update(portBase, + (pin < 8) ? GPIO_ALTFNL_REG : GPIO_ALTFNH_REG, + WHAL_BITMASK(4) << afPos, + WHAL_STM32WB_GPIO_GET_ALTFN(cfg) << afPos); } return WHAL_SUCCESS; @@ -107,7 +98,7 @@ whal_Error whal_Stm32wbGpio_Init(whal_Gpio *gpioDev) /* Initialize each pin in the configuration array */ for (size_t pin = 0; pin < cfg->pinCount; ++pin) { - err = whal_Stm32wbGpio_InitPin(gpioDev, &pinCfg[pin]); + err = whal_Stm32wbGpio_InitPin(gpioDev, pinCfg[pin]); if (err) { return err; } @@ -129,37 +120,35 @@ whal_Error whal_Stm32wbGpio_Deinit(whal_Gpio *gpioDev) * For set operations (set=1): writes value to ODR register * For get operations (set=0): reads value from IDR register */ -static whal_Error whal_Stm32wbGpio_SetOrGet(whal_Gpio *gpioDev, size_t pin, size_t *value, uint8_t set) +static whal_Error whal_Stm32wbGpio_SetOrGet(whal_Gpio *gpioDev, size_t idx, + size_t *value, uint8_t set) { - whal_Regmap portReg; whal_Stm32wbGpio_Cfg *cfg; - whal_Stm32wbGpio_PinCfg *pinCfg; - size_t mask; + whal_Stm32wbGpio_PinCfg pinCfg; + uint8_t port, pin; + size_t portBase, mask; if (!gpioDev || !gpioDev->cfg) { return WHAL_EINVAL; } cfg = (whal_Stm32wbGpio_Cfg *)gpioDev->cfg; - pinCfg = cfg->pinCfg; + pinCfg = cfg->pinCfg[idx]; + port = WHAL_STM32WB_GPIO_GET_PORT(pinCfg); + pin = WHAL_STM32WB_GPIO_GET_PIN(pinCfg); - if (pinCfg[pin].pin > 15) { + if (pin > 15) { return WHAL_EINVAL; } - /* Calculate port base address from config */ - portReg.size = GPIO_PORT_SIZE; - portReg.base = (size_t)(gpioDev->regmap.base + (pinCfg[pin].port * GPIO_PORT_SIZE)); + portBase = gpioDev->regmap.base + (port * GPIO_PORT_SIZE); + mask = 1UL << pin; - mask = (1UL << (pinCfg[pin].pin)); if (set) { - /* Write to output data register */ - whal_Reg_Update(portReg.base, GPIO_ODR_REG, mask, - whal_SetBits(mask, pinCfg[pin].pin, *value)); - } - else { - /* Read from input data register */ - whal_Reg_Get(portReg.base, GPIO_IDR_REG, mask, pinCfg[pin].pin, value); + whal_Reg_Update(portBase, GPIO_ODR_REG, mask, + whal_SetBits(mask, pin, *value)); + } else { + whal_Reg_Get(portBase, GPIO_IDR_REG, mask, pin, value); } return WHAL_SUCCESS; diff --git a/tests/gpio/test_stm32wb_gpio.c b/tests/gpio/test_stm32wb_gpio.c index 44c08d1..4b93b61 100644 --- a/tests/gpio/test_stm32wb_gpio.c +++ b/tests/gpio/test_stm32wb_gpio.c @@ -11,6 +11,22 @@ #define GPIOx_MODE_REG 0x00 #define GPIOx_ODR_REG 0x14 +static void Test_Gpio_PinCfgRoundTrip(void) +{ + whal_Stm32wbGpio_PinCfg cfg = WHAL_STM32WB_GPIO_PIN( + WHAL_STM32WB_GPIO_PORT_C, 13, WHAL_STM32WB_GPIO_MODE_ALTFN, + WHAL_STM32WB_GPIO_OUTTYPE_OPENDRAIN, WHAL_STM32WB_GPIO_SPEED_HIGH, + WHAL_STM32WB_GPIO_PULL_DOWN, 9); + + WHAL_ASSERT_EQ(WHAL_STM32WB_GPIO_GET_PORT(cfg), WHAL_STM32WB_GPIO_PORT_C); + WHAL_ASSERT_EQ(WHAL_STM32WB_GPIO_GET_PIN(cfg), 13); + WHAL_ASSERT_EQ(WHAL_STM32WB_GPIO_GET_MODE(cfg), WHAL_STM32WB_GPIO_MODE_ALTFN); + WHAL_ASSERT_EQ(WHAL_STM32WB_GPIO_GET_OUTTYPE(cfg), WHAL_STM32WB_GPIO_OUTTYPE_OPENDRAIN); + WHAL_ASSERT_EQ(WHAL_STM32WB_GPIO_GET_SPEED(cfg), WHAL_STM32WB_GPIO_SPEED_HIGH); + WHAL_ASSERT_EQ(WHAL_STM32WB_GPIO_GET_PULL(cfg), WHAL_STM32WB_GPIO_PULL_DOWN); + WHAL_ASSERT_EQ(WHAL_STM32WB_GPIO_GET_ALTFN(cfg), 9); +} + static void Test_Gpio_NoDuplicatePins(void) { whal_Stm32wbGpio_Cfg *cfg = (whal_Stm32wbGpio_Cfg *)g_whalGpio.cfg; @@ -18,9 +34,10 @@ static void Test_Gpio_NoDuplicatePins(void) for (size_t i = 0; i < cfg->pinCount; i++) { for (size_t j = i + 1; j < cfg->pinCount; j++) { - if (pins[i].port == pins[j].port && - pins[i].pin == pins[j].pin) { - WHAL_ASSERT_NEQ(pins[i].port, pins[j].port); + if (WHAL_STM32WB_GPIO_GET_PORT(pins[i]) == WHAL_STM32WB_GPIO_GET_PORT(pins[j]) && + WHAL_STM32WB_GPIO_GET_PIN(pins[i]) == WHAL_STM32WB_GPIO_GET_PIN(pins[j])) { + WHAL_ASSERT_NEQ(WHAL_STM32WB_GPIO_GET_PORT(pins[i]), + WHAL_STM32WB_GPIO_GET_PORT(pins[j])); } } } @@ -61,6 +78,7 @@ static void Test_Gpio_SetLowReg(void) void whal_Test_Gpio_Platform(void) { + WHAL_TEST(Test_Gpio_PinCfgRoundTrip); WHAL_TEST(Test_Gpio_NoDuplicatePins); WHAL_TEST(Test_Gpio_ModeRegister); WHAL_TEST(Test_Gpio_SetHighReg); diff --git a/wolfHAL/eth/eth.h b/wolfHAL/eth/eth.h index 07a09d0..e1a969e 100644 --- a/wolfHAL/eth/eth.h +++ b/wolfHAL/eth/eth.h @@ -56,6 +56,7 @@ struct whal_Eth { const whal_Regmap regmap; const whal_EthDriver *driver; void *cfg; + uint8_t macAddr[6]; }; /* diff --git a/wolfHAL/eth/stm32h5_eth.h b/wolfHAL/eth/stm32h5_eth.h index 7e3affe..11e1cf4 100644 --- a/wolfHAL/eth/stm32h5_eth.h +++ b/wolfHAL/eth/stm32h5_eth.h @@ -32,7 +32,6 @@ typedef struct { * @brief STM32H5 Ethernet MAC configuration. */ typedef struct whal_Stm32h5Eth_Cfg { - uint8_t macAddr[6]; /* MAC address */ whal_Stm32h5Eth_TxDesc *txDescs; /* TX descriptor ring (pre-allocated) */ uint8_t *txBufs; /* TX frame buffers (pre-allocated) */ size_t txDescCount; /* Number of TX descriptors */ diff --git a/wolfHAL/flash/stm32h5_flash.h b/wolfHAL/flash/stm32h5_flash.h index fcbb914..4631e3b 100644 --- a/wolfHAL/flash/stm32h5_flash.h +++ b/wolfHAL/flash/stm32h5_flash.h @@ -122,4 +122,21 @@ whal_Error whal_Stm32h5Flash_Write(whal_Flash *flashDev, size_t addr, whal_Error whal_Stm32h5Flash_Erase(whal_Flash *flashDev, size_t addr, size_t dataSz); +/* + * @brief Set flash access latency (wait states) and write high-frequency mode. + * + * Must be called before increasing the system clock to avoid flash access + * faults. The value is written directly to FLASH_ACR[7:0]: + * bits [3:0] = LATENCY (wait states, 0-15) + * bits [5:4] = WRHIGHFREQ (0-2, based on frequency range) + * + * @param flashDev Flash device instance. + * @param latency Combined LATENCY | (WRHIGHFREQ << 4) value. + * + * @retval WHAL_SUCCESS Latency updated. + * @retval WHAL_EINVAL Invalid arguments. + */ +whal_Error whal_Stm32h5Flash_Ext_SetLatency(whal_Flash *flashDev, + uint8_t latency); + #endif /* WHAL_STM32H5_FLASH_H */ diff --git a/wolfHAL/gpio/stm32c0_gpio.h b/wolfHAL/gpio/stm32c0_gpio.h index 8ae0981..b263761 100644 --- a/wolfHAL/gpio/stm32c0_gpio.h +++ b/wolfHAL/gpio/stm32c0_gpio.h @@ -59,4 +59,10 @@ typedef whal_Stm32wbGpio_PinCfg whal_Stm32c0Gpio_PinCfg; #define WHAL_STM32C0_GPIO_PORT_D WHAL_STM32WB_GPIO_PORT_D #define WHAL_STM32C0_GPIO_PORT_F WHAL_STM32WB_GPIO_PORT_F +/* + * @brief Pack a GPIO pin configuration into a single word (re-exported from + * STM32WB). + */ +#define WHAL_STM32C0_GPIO_PIN WHAL_STM32WB_GPIO_PIN + #endif /* WHAL_STM32C0_GPIO_H */ diff --git a/wolfHAL/gpio/stm32f4_gpio.h b/wolfHAL/gpio/stm32f4_gpio.h index be6564c..79c0905 100644 --- a/wolfHAL/gpio/stm32f4_gpio.h +++ b/wolfHAL/gpio/stm32f4_gpio.h @@ -62,4 +62,10 @@ typedef whal_Stm32wbGpio_PinCfg whal_Stm32f4Gpio_PinCfg; #define WHAL_STM32F4_GPIO_PORT_G WHAL_STM32WB_GPIO_PORT_G #define WHAL_STM32F4_GPIO_PORT_H WHAL_STM32WB_GPIO_PORT_H +/* + * @brief Pack a GPIO pin configuration into a single word (re-exported from + * STM32WB). + */ +#define WHAL_STM32F4_GPIO_PIN WHAL_STM32WB_GPIO_PIN + #endif /* WHAL_STM32F4_GPIO_H */ diff --git a/wolfHAL/gpio/stm32h5_gpio.h b/wolfHAL/gpio/stm32h5_gpio.h index edc49e9..56c8a0d 100644 --- a/wolfHAL/gpio/stm32h5_gpio.h +++ b/wolfHAL/gpio/stm32h5_gpio.h @@ -63,4 +63,10 @@ typedef whal_Stm32wbGpio_PinCfg whal_Stm32h5Gpio_PinCfg; #define WHAL_STM32H5_GPIO_PORT_H WHAL_STM32WB_GPIO_PORT_H #define WHAL_STM32H5_GPIO_PORT_I WHAL_STM32WB_GPIO_PORT_I +/* + * @brief Pack a GPIO pin configuration into a single word (re-exported from + * STM32WB). + */ +#define WHAL_STM32H5_GPIO_PIN WHAL_STM32WB_GPIO_PIN + #endif /* WHAL_STM32H5_GPIO_H */ diff --git a/wolfHAL/gpio/stm32wb_gpio.h b/wolfHAL/gpio/stm32wb_gpio.h index 4e12d3c..f89f3fa 100644 --- a/wolfHAL/gpio/stm32wb_gpio.h +++ b/wolfHAL/gpio/stm32wb_gpio.h @@ -21,79 +21,81 @@ */ /* - * @brief GPIO port identifiers. + * @brief Packed per-pin GPIO configuration (uint32_t). * - * Port index is used to calculate register offset: base + (port * 0x400) - */ -typedef enum { - WHAL_STM32WB_GPIO_PORT_A, - WHAL_STM32WB_GPIO_PORT_B, - WHAL_STM32WB_GPIO_PORT_C, - WHAL_STM32WB_GPIO_PORT_D, - WHAL_STM32WB_GPIO_PORT_E, - WHAL_STM32WB_GPIO_PORT_F, - WHAL_STM32WB_GPIO_PORT_G, - WHAL_STM32WB_GPIO_PORT_H, -} whal_Stm32wbGpio_Port; - -/* - * @brief GPIO pin mode selection. + * Bit layout: + * [3:0] port — GPIO port A-I (4 bits) + * [7:4] pin — Pin number 0-15 (4 bits) + * [9:8] mode — Pin mode (2 bits) + * [10] outType — Output type (1 bit) + * [12:11] speed — Output speed (2 bits) + * [14:13] pull — Pull resistor (2 bits) + * [18:15] altFn — Alternate function 0-15 (4 bits) * - * Determines the basic function of the pin. + * Use WHAL_STM32WB_GPIO_PIN() to build values and + * WHAL_STM32WB_GPIO_GET_*() to extract fields. */ -typedef enum { - WHAL_STM32WB_GPIO_MODE_IN, /* Digital input */ - WHAL_STM32WB_GPIO_MODE_OUT, /* Digital output */ - WHAL_STM32WB_GPIO_MODE_ALTFN, /* Alternate function (peripheral control) */ - WHAL_STM32WB_GPIO_MODE_ANALOG, /* Analog mode (ADC/DAC) */ -} whal_Stm32wbGpio_Mode; +typedef uint32_t whal_Stm32wbGpio_PinCfg; -/* - * @brief Output driver type. - */ -typedef enum { - WHAL_STM32WB_GPIO_OUTTYPE_PUSHPULL, /* Push-pull output */ - WHAL_STM32WB_GPIO_OUTTYPE_OPENDRAIN, /* Open-drain output */ -} whal_Stm32wbGpio_OutType; +/* Field positions */ +#define WHAL_STM32WB_GPIO_PORT_Pos 0 +#define WHAL_STM32WB_GPIO_PIN_Pos 4 +#define WHAL_STM32WB_GPIO_MODE_Pos 8 +#define WHAL_STM32WB_GPIO_OUTTYPE_Pos 10 +#define WHAL_STM32WB_GPIO_SPEED_Pos 11 +#define WHAL_STM32WB_GPIO_PULL_Pos 13 +#define WHAL_STM32WB_GPIO_ALTFN_Pos 15 -/* - * @brief Output speed settings. - * - * Higher speeds allow faster edge transitions but increase EMI and power. - * Use the lowest speed that meets timing requirements. - */ -typedef enum { - WHAL_STM32WB_GPIO_SPEED_LOW, - WHAL_STM32WB_GPIO_SPEED_MEDIUM, - WHAL_STM32WB_GPIO_SPEED_FAST, - WHAL_STM32WB_GPIO_SPEED_HIGH, -} whal_Stm32wbGpio_Speed; +/* Port values */ +#define WHAL_STM32WB_GPIO_PORT_A 0 +#define WHAL_STM32WB_GPIO_PORT_B 1 +#define WHAL_STM32WB_GPIO_PORT_C 2 +#define WHAL_STM32WB_GPIO_PORT_D 3 +#define WHAL_STM32WB_GPIO_PORT_E 4 +#define WHAL_STM32WB_GPIO_PORT_F 5 +#define WHAL_STM32WB_GPIO_PORT_G 6 +#define WHAL_STM32WB_GPIO_PORT_H 7 +#define WHAL_STM32WB_GPIO_PORT_I 8 -/* - * @brief Internal pull resistor configuration. - */ -typedef enum { - WHAL_STM32WB_GPIO_PULL_NONE, /* No pull resistor (floating) */ - WHAL_STM32WB_GPIO_PULL_UP, /* Internal pull-up */ - WHAL_STM32WB_GPIO_PULL_DOWN, /* Internal pull-down */ -} whal_Stm32wbGpio_Pull; +/* Mode values */ +#define WHAL_STM32WB_GPIO_MODE_IN 0 +#define WHAL_STM32WB_GPIO_MODE_OUT 1 +#define WHAL_STM32WB_GPIO_MODE_ALTFN 2 +#define WHAL_STM32WB_GPIO_MODE_ANALOG 3 -/* - * @brief Per-pin GPIO configuration. - * - * For alternate function mode, consult the datasheet's "Alternate function - * mapping" table to find the correct altFn value for your peripheral. - * For example, USART1_TX on PA9 uses AF7. - */ -typedef struct { - whal_Stm32wbGpio_Port port; /* GPIO port (A-H) */ - uint8_t pin; /* Pin number (0-15) */ - whal_Stm32wbGpio_Mode mode; /* Pin mode */ - whal_Stm32wbGpio_OutType outType; /* Output type (push-pull/open-drain) */ - whal_Stm32wbGpio_Speed speed; /* Output speed */ - whal_Stm32wbGpio_Pull pull; /* Pull resistor config */ - uint8_t altFn; /* Alternate function (0-15, AF0-AF15) */ -} whal_Stm32wbGpio_PinCfg; +/* Output type values */ +#define WHAL_STM32WB_GPIO_OUTTYPE_PUSHPULL 0 +#define WHAL_STM32WB_GPIO_OUTTYPE_OPENDRAIN 1 + +/* Speed values */ +#define WHAL_STM32WB_GPIO_SPEED_LOW 0 +#define WHAL_STM32WB_GPIO_SPEED_MEDIUM 1 +#define WHAL_STM32WB_GPIO_SPEED_FAST 2 +#define WHAL_STM32WB_GPIO_SPEED_HIGH 3 + +/* Pull values */ +#define WHAL_STM32WB_GPIO_PULL_NONE 0 +#define WHAL_STM32WB_GPIO_PULL_UP 1 +#define WHAL_STM32WB_GPIO_PULL_DOWN 2 + +/* Pack a pin configuration into a uint32_t */ +#define WHAL_STM32WB_GPIO_PIN(port, pin, mode, outType, speed, pull, altFn) \ + ((((uint32_t)(port) & 0xFu) << WHAL_STM32WB_GPIO_PORT_Pos) | \ + (((uint32_t)(pin) & 0xFu) << WHAL_STM32WB_GPIO_PIN_Pos) | \ + (((uint32_t)(mode) & 0x3u) << WHAL_STM32WB_GPIO_MODE_Pos) | \ + (((uint32_t)(outType) & 0x1u) << WHAL_STM32WB_GPIO_OUTTYPE_Pos) | \ + (((uint32_t)(speed) & 0x3u) << WHAL_STM32WB_GPIO_SPEED_Pos) | \ + (((uint32_t)(pull) & 0x3u) << WHAL_STM32WB_GPIO_PULL_Pos) | \ + (((uint32_t)(altFn) & 0xFu) << WHAL_STM32WB_GPIO_ALTFN_Pos)) + +/* Extract individual fields */ +#define WHAL_STM32WB_GPIO_GET_PORT(cfg) (((cfg) >> WHAL_STM32WB_GPIO_PORT_Pos) & 0xF) +#define WHAL_STM32WB_GPIO_GET_PIN(cfg) (((cfg) >> WHAL_STM32WB_GPIO_PIN_Pos) & 0xF) +#define WHAL_STM32WB_GPIO_GET_MODE(cfg) (((cfg) >> WHAL_STM32WB_GPIO_MODE_Pos) & 0x3) +#define WHAL_STM32WB_GPIO_GET_OUTTYPE(cfg) (((cfg) >> WHAL_STM32WB_GPIO_OUTTYPE_Pos) & 0x1) +#define WHAL_STM32WB_GPIO_GET_SPEED(cfg) (((cfg) >> WHAL_STM32WB_GPIO_SPEED_Pos) & 0x3) +#define WHAL_STM32WB_GPIO_GET_PULL(cfg) (((cfg) >> WHAL_STM32WB_GPIO_PULL_Pos) & 0x3) +#define WHAL_STM32WB_GPIO_GET_ALTFN(cfg) (((cfg) >> WHAL_STM32WB_GPIO_ALTFN_Pos) & 0xF) /* * @brief GPIO device configuration.