Describe the issue
On the WildbitsK / F256K1 running the 2x core, I'm unable to get the system to successfully boot from code written to flash that immediately tries to switch the system into full 24-bit flat/direct memory modes.
This is the very beginning of the code that starts executing at 0x00ff00 (via the reset vector):
__program_start:
sei
clc
xce ; native 16-bit mode
sep #32 ; 8-bit registers
lda #8 ; enable SRAM direct 24-bit access
sta 0x0000
lda #48 ; map flash and IO into himem for direct 24-bit access
sta 0x0001
...
I've tried various things like inserting delays, etc, to no effect.
On some further investigation I noticed that execution seems to lock up when this code enables either SRAM 24-bit access (bit 3 in 0x0000) OR Flash 24-bit access (bit 5 in 0x0001). However, just enabling IO memory 24-bit access (bit 4 in 0x0001) and nothing else works and code execution continues on from there.
The same code when loaded onto the system and booted from RAM instead of flash works just fine.
To reproduce
I've attached a ZIP file containing code and pre-built binaries that can be flashed via FoenixMgr that demonstrate the problem.
k1-core2x-flash-flatmem-test.zip
Inside the ZIP file you'll find the flashable files under the /flashable directory. These can be flashed via FoenixMgr with something like:
cd flashable
fm.sh --flash-bulk core2x-minimal-tester.csv
After this has been written to flash, booting the device on the 2x core will just display the default black screen with purple border.
Expected behavior
I would expect this code to boot successfully on the 2x core. It should display a simple "hello world" text message on screen when it works.
I did search through Discord to see if there was any mention of boot process changes with the 2x cores, but could not find anything, so I am under the current assumption that my code should work with what I currently understand about the boot process on these devices.
Of note, on the old "extended" core, F256Ke_WBh_CFP6309_Rev0004_June13th_2024.jic, this code boots as-is from flash (since the MMU register manipulation is effectively a no-op on that core).
Hardware version
- SuperBASIC Hardware version string:
01000003 B0
- Machine type: Wildbits/K / F256K1
- PCB revision: purple board (received on Feb 12, 2024)
- CPU: 65816
- FPGA core:
F256Kc_WBh_Jun23th_RC0100_0003_DualSpeed_CPU.jic
Describe the issue
On the WildbitsK / F256K1 running the 2x core, I'm unable to get the system to successfully boot from code written to flash that immediately tries to switch the system into full 24-bit flat/direct memory modes.
This is the very beginning of the code that starts executing at 0x00ff00 (via the reset vector):
I've tried various things like inserting delays, etc, to no effect.
On some further investigation I noticed that execution seems to lock up when this code enables either SRAM 24-bit access (bit 3 in 0x0000) OR Flash 24-bit access (bit 5 in 0x0001). However, just enabling IO memory 24-bit access (bit 4 in 0x0001) and nothing else works and code execution continues on from there.
The same code when loaded onto the system and booted from RAM instead of flash works just fine.
To reproduce
I've attached a ZIP file containing code and pre-built binaries that can be flashed via FoenixMgr that demonstrate the problem.
k1-core2x-flash-flatmem-test.zip
Inside the ZIP file you'll find the flashable files under the
/flashabledirectory. These can be flashed via FoenixMgr with something like:After this has been written to flash, booting the device on the 2x core will just display the default black screen with purple border.
Expected behavior
I would expect this code to boot successfully on the 2x core. It should display a simple "hello world" text message on screen when it works.
I did search through Discord to see if there was any mention of boot process changes with the 2x cores, but could not find anything, so I am under the current assumption that my code should work with what I currently understand about the boot process on these devices.
Of note, on the old "extended" core,
F256Ke_WBh_CFP6309_Rev0004_June13th_2024.jic, this code boots as-is from flash (since the MMU register manipulation is effectively a no-op on that core).Hardware version
01000003 B0F256Kc_WBh_Jun23th_RC0100_0003_DualSpeed_CPU.jic