feat(riscv): add RV32F (FPU) to the RISC-V core for FPU-equipped chips (ESP32-P4)

[w1ne]

Problem

LabWired's Xtensa LX7 core has a working FPU (single-precision float
registers + FLOAT/UFLOAT/fadd-style ops in crates/core/src/cpu/xtensa_lx7.rs),
but the RISC-V core has no floating-point support at all — no f0..f31, no
FCSR, no F-extension decode. Any RISC-V firmware that uses float must be
compiled soft-float (rv32imc), so every expf/fadd/fmul becomes thousands
of integer instructions via libgcc/newlib.

This surfaced building the Leo air-quality example's surface-condensation channel
(dew point + surface RH via Magnus, real expf/logf): on the FPU-less ESP32-C3
the soft-float is correct and faithful (the real C3 has no FPU either), but it
is heavy, and there is no way to model an FPU-equipped RISC-V MCU running that
same math at hardware speed.

Why it matters

A real product that leans on floating-point would pick an FPU MCU. On the RISC-V
side that's the ESP32-P4 (RV32 with the F/D extensions) or any rv32imfc
core. Today we cannot model those faithfully: we'd either run soft-float (wrong —
understates their real performance) or have no FPU at all.

Note the fidelity boundary this must respect: never enable the FPU for a chip
whose ISA does not have it (e.g. the C3). Adding an FPU to the C3 model would be
a false-pass — float code that runs in sim but faults on real silicon — which is
exactly what this simulator exists to prevent. Gate F support on the chip
descriptor's declared ISA.

Proposed work

• Add f0..f31 + FCSR (single precision RV32F; consider RV32D later) to the
  RISC-V CPU state.
• Decode + execute the F opcodes: FLW/FSW, FADD/FSUB/FMUL/FDIV/FSQRT.S,
  FMADD/FMSUB/FNMADD/FNMSUB.S, FCVT.*, FMV.*, FSGNJ.*, FMIN/FMAX.S,
  FEQ/FLT/FLE.S, FCLASS.S.
• Reuse the Xtensa core's float handling as a reference implementation
  (fget/fset, rounding) for consistency.
• Add a chip-descriptor ISA flag (e.g. isa: rv32imfc) and only wire the FPU
  when present; soft-float remains the default for rv32imc parts like the C3.
• Model an FPU-equipped RISC-V chip (ESP32-P4 or a generic rv32imfc test chip)
  and a small firmware test that does hardware-float arithmetic.

Out of scope / non-goals

• Does not change the ESP32-C3 (stays soft-float, faithfully).
• D (double) extension can be a follow-up; start with single-precision F.