No clock signals being traced inside testbench module

[pah69]

I was running Makefile in /test folder to trace .vcd files, in order to investigate waveforms. Upon doing that, I cannot see anything values being driven into clk signal inside /sim/vproc_tb.sv module. The same thing happened with vproc_top.sv .

Tools version :
gcc & g++ : both version 11
verilator : v4.210

Any ideas on how this happened and are there any solutions to it?
Thanks !

[pah69]

@stevobailey @michael-platzer @kuoyaoming93 @davideschiavone