From 393251c77d5fba2d07a83862be575e12cde8b791 Mon Sep 17 00:00:00 2001 From: JacyCui Date: Tue, 29 Jul 2025 13:49:08 +0000 Subject: [PATCH] fix blocking assignments in sequential logic process --- src/dcache/dcache_core_tag_ram.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/dcache/dcache_core_tag_ram.v b/src/dcache/dcache_core_tag_ram.v index aec0ff3..d818033 100644 --- a/src/dcache/dcache_core_tag_ram.v +++ b/src/dcache/dcache_core_tag_ram.v @@ -54,9 +54,9 @@ reg [20:0] ram_read0_q; always @ (posedge clk1_i) begin if (wr1_i) - ram[addr1_i] = data1_i; + ram[addr1_i] <= data1_i; - ram_read0_q = ram[addr0_i]; + ram_read0_q <= ram[addr0_i]; end assign data0_o = ram_read0_q;