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<meta name="description" content="TinyEDA is building performant and simple Electronic Design Automation tools and design IP for the chip design industry.">
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<title>TinyEDA: Accelerating chip design</title>
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<div class="layout">
<header class="sidebar">
<a class="logo" href="#what"><span class="mark"></span>TinyEDA</a>
<input id="nav-toggle" type="checkbox" aria-label="Toggle navigation">
<label class="nav-button" for="nav-toggle" aria-label="Toggle navigation"><i></i><i></i><i></i></label>
<nav class="menu" aria-label="Main navigation">
<a href="#what">What</a>
<a href="#why">Why</a>
<a href="#how">How</a>
<a href="#who">Who</a>
<a href="#faq">FAQ</a>
<a href="https://github.com/tinyeda">GitHub</a>
</nav>
</header>
<main>
<h1 id="what">Accelerating chip design.</h1>
<div class="intro">
<p>Go from idea to tapeout 100x faster</p>
</div>
<div class="rows">
<section class="row" id="why">
<h2>Why</h2>
<div class="copy">
<p>Most EDA tooling was built decades ago, under assumptions very different from modern computing. Their arcane user experience requires extensive scripting to get work done.</p>
<p>EDA vendors aren't incentivised to build simpler tools since they can charge to set up and provide you with an environment that <em>just works</em>.</p>
<p>We are changing this with performant, user-friendly tools so you can spend time on your design instead of endless Tcl / Python scripting to orchestrate workflows.</p>
</div>
</section>
<section class="row" id="how">
<h2>How</h2>
<div class="copy">
<p><strong>TinyEDA Studio</strong> is an integrated digital ASIC design environment. It massively accelerates the physical design process, improves performance, power, and area (PPA) results, and makes it easier to trace design errors back to original RTL.</p>
<span class="subhead">Faster, simpler tools</span>
<ul>
<li>Faster classical and ML algorithms for macro placement, place and route, and static timing analysis.</li>
<li>GPU acceleration for massively parallel workloads and SIMD/vector compute for CPU workloads.</li>
<li>Well-designed APIs that eliminate glue code between tools.</li>
</ul>
<span class="subhead">Design IP</span>
<p>We will use these tools internally alongside automated schematic, layout, and simulation tooling to create digital / analog design IP for:</p>
<ol>
<li>Automotive</li><li>Aerospace (radiation hardened)</li><li>Consumer electronics</li><li>Industrial automation</li><li>Medical</li><li>Nuclear (radiation hardened)</li>
</ol>
</div>
</section>
<section class="row" id="who">
<h2>Who</h2>
<div class="copy person">
<img src="assets/rahul.webp" alt="Rahul Bhagwat" loading="lazy" decoding="async">
<div><p><strong>Rahul Bhagwat</strong></p><p class="role">Founder</p></div>
</div>
</section>
<section class="row" id="faq">
<h2>FAQ</h2>
<div class="copy">
<details><summary>Can I run this locally?</summary><p>Yes. We will have local apps for MacOS, Windows, and Linux, as well as a collaborative web app hostable on-premise.</p></details>
<details><summary>How difficult is it to switch from my existing EDA suite?</summary><p>We will provide tooling to port your Tcl scripts and tool-specific configurations, making the switch painless and inexpensive for your organization.</p></details>
<details><summary>Why should we trust your tool?</summary><p>We will formally verify equivalence where applicable and work closely with foundries to qualify our tools as signoff-ready.</p></details>
</div>
</section>
</div>
<footer>
<span>© TinyEDA</span>
<nav class="footer-links" aria-label="Footer navigation"><a href="mailto:rahul@tinyeda.com">Contact</a><a href="https://github.com/tinyeda">GitHub</a></nav>
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