makefile

# =========================================================
#             RISC-V PROCESSOR VERIFICATION MAKEFILE
# =========================================================

# ---------------------------------------------------------
# 1. CONFIGURATION
# ---------------------------------------------------------
RISCV_PREFIX ?= riscv64-unknown-elf
CC           := $(RISCV_PREFIX)-gcc
OBJCOPY      := $(RISCV_PREFIX)-objcopy
OBJDUMP      := $(RISCV_PREFIX)-objdump

# Simulator
VSIM         := vsim
VLOG         := vlog
VLIB         := vlib
VMAP         := vmap

# Flags
ISA_ARCH     := rv64i_zba
ABI          := lp64
CFLAGS       := -march=$(ISA_ARCH) -mabi=$(ABI) -nostdlib -Og -g -ffreestanding

# ---------------------------------------------------------
# 2. PATHS & SOURCES
# ---------------------------------------------------------
# Directories
DIR_RTL      := rtl
DIR_SW       := sw/C
DIR_TB_SYS   := sw/tb
DIR_ISA      := test/isa/instructions
DIR_ISA_TB   := test/isa/tb
DIR_UNIT     := test/unittests
DIR_BUILD    := build
DIR_BIN      := $(DIR_BUILD)/bin
DIR_ISA_OUT  := $(DIR_BUILD)/isa
DIR_LOGS     := $(DIR_BUILD)/logs

# Sources
SRCS_RTL     := $(wildcard $(DIR_RTL)/*.sv)
SRCS_C       := $(wildcard $(DIR_SW)/*.c)
SRC_STARTUP  := $(DIR_SW)/start.S
SCRIPT_LD    := $(DIR_SW)/link.ld
SRC_MACRO    := test/macro.S

# Testbenches
TB_SYS       := $(DIR_TB_SYS)/tb_processor.sv
TB_ISA       := $(DIR_ISA_TB)/isa_tb.sv
TB_UNIT      := $(wildcard $(DIR_UNIT)/*_tb.sv) # All unit test files

# Top Modules
TOP_SYS      := tb_processor
TOP_ISA      := isa_tb

# ---------------------------------------------------------
# 3. BUILD ARTIFACTS
# ---------------------------------------------------------
SW_HEX_IMEM  := $(DIR_BIN)/prog_text.mem
SW_HEX_DMEM  := $(DIR_BIN)/prog_data.mem

ISA_SRCS     := $(wildcard $(DIR_ISA)/*.S)
ISA_TESTS    := $(notdir $(basename $(ISA_SRCS)))
# Generate list of expected ISA output files
ISA_HEX_TARGETS := $(patsubst $(DIR_ISA)/%.S, $(DIR_ISA_OUT)/%_text.mem, $(ISA_SRCS)) \
                   $(patsubst $(DIR_ISA)/%.S, $(DIR_ISA_OUT)/%_data.mem, $(ISA_SRCS))

UNIT_TESTS   := $(notdir $(basename $(TB_UNIT)))

# =========================================================
#                 PRIMARY TARGETS
# =========================================================

.PHONY: all help build clean run_sys run_isa run_unit

all: help

help:
	@echo "----------------------------------------------------------------"
	@echo " RISC-V VERIFICATION WORKFLOW"
	@echo "----------------------------------------------------------------"
	@echo "STEP 1: COMPILATION (Run this if you change RTL/TB/SW code)"
	@echo "  make build          : Compiles C, ASM, RTL, and ALL Testbenches"
	@echo ""
	@echo "STEP 2: SIMULATION (Run these to verify)"
	@echo "  make run_sys        : Run System Self-Test"
	@echo "  make run_isa        : Run All ISA Tests"
	@echo "  make run_unit       : Run All Unit Tests"
	@echo "  make <name>_tb      : Run specific Unit Test (e.g. make alu_tb)"
	@echo ""
	@echo "UTILITIES"
	@echo "  make clean          : Clear build files"
	@echo "----------------------------------------------------------------"

# =========================================================
#                 STEP 1: BUILD (COMPILE EVERYTHING)
# =========================================================

# This is the master build target.
build: work_lib compile_sw compile_isa_sw compile_rtl compile_tbs
	@echo "------------------------------------------------"
	@echo "BUILD COMPLETE. READY FOR SIMULATION."

# 1. Create Library
work_lib:
	@if [ ! -d "work" ]; then \
		echo "[BUILD] Creating ModelSim Library..."; \
		$(VLIB) work; \
		$(VMAP) work work; \
	fi

# 2. Compile Software (C)
compile_sw: $(SW_HEX_IMEM) $(SW_HEX_DMEM)
	@echo "[BUILD] System Software Compiled"

# 3. Compile ISA Assembly
compile_isa_sw: $(ISA_HEX_TARGETS)
	@echo "[BUILD] ISA Tests Assembly Compiled"

# 4. Compile RTL
compile_rtl:
	@echo "[BUILD] Compiling RTL..."
	$(VLOG) -sv -suppress 2583 $(SRCS_RTL)

# 5. Compile ALL Testbenches
# We compile System TB, ISA TB, and ALL Unit TBs in one go.
compile_tbs:
	@echo "[BUILD] Compiling All Testbenches..."
	$(VLOG) -sv -suppress 2583 $(TB_SYS) $(TB_ISA) $(TB_UNIT)

# =========================================================
#                 STEP 2: SIMULATION (EXECUTE ONLY)
# =========================================================

# --- SYSTEM TEST ---
run_sys:
	@echo "[SIM] Running System Test..."
	$(VSIM) -c $(TOP_SYS) \
		-gIMEM=$(SW_HEX_IMEM) \
		-gDMEM=$(SW_HEX_DMEM) \
		-do "run -all; quit"

# --- UNIT TESTS ---
run_unit: $(UNIT_TESTS)
	@echo "------------------------------------------------"
	@echo "ALL UNIT TESTS FINISHED"

# Pattern rule for running unit tests
# Since we already compiled everything in 'make build', we just run vsim here.
%_tb:
	@echo "[SIM] Running Unit Test: $@"
	$(VSIM) -c $@ -do "run -all; quit"

# --- ISA TESTS ---
run_isa: $(addprefix isa_exec_,$(ISA_TESTS))
	@echo "------------------------------------------------"
	@echo "ALL ISA TESTS FINISHED"
	@echo "Logs: $(DIR_LOGS)"

isa_exec_%:
	@mkdir -p $(DIR_LOGS)
	@echo "[SIM] ISA Test: $*"
	$(VSIM) -c $(TOP_ISA) \
		-gIMEM=$(DIR_ISA_OUT)/$*_text.mem \
		-gDMEM=$(DIR_ISA_OUT)/$*_data.mem \
		-do "run -all; quit" | tee $(DIR_LOGS)/$*.log

# Helper for individual ISA run
isa_%: isa_exec_%
	@:

# =========================================================
#                 FILE GENERATION RULES
# =========================================================

# System SW
$(DIR_BIN)/prog.elf: $(SRCS_C) $(SRC_STARTUP) $(SCRIPT_LD)
	@mkdir -p $(DIR_BIN)
	$(CC) $(CFLAGS) -fno-tree-loop-distribute-patterns -T $(SCRIPT_LD) $(SRC_STARTUP) $(SRCS_C) -o $@

$(DIR_BIN)/%_text.mem: $(DIR_BIN)/%.elf
	$(OBJCOPY) -O verilog --only-section=.text $< $@

$(DIR_BIN)/%_data.mem: $(DIR_BIN)/%.elf
	$(OBJCOPY) -O verilog --only-section=.data --only-section=.rodata $< $@

# ISA SW
$(DIR_ISA_OUT)/%.elf: $(DIR_ISA)/%.S $(SRC_MACRO) $(SCRIPT_LD)
	@mkdir -p $(DIR_ISA_OUT)
	$(CC) $(CFLAGS) -T $(SCRIPT_LD) $< $(SRC_MACRO) -o $@

$(DIR_ISA_OUT)/%_text.mem: $(DIR_ISA_OUT)/%.elf
	$(OBJCOPY) -O verilog --only-section=.text $< $@

$(DIR_ISA_OUT)/%_data.mem: $(DIR_ISA_OUT)/%.elf
	$(OBJCOPY) -O verilog --only-section=.data --only-section=.rodata $< $@

# =========================================================
#                 CLEAN
# =========================================================
clean:
	rm -rf $(DIR_BUILD) work transcript vsim.wlf wave.vcd