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[Feature] Support of combinational wires in dataflow region #9

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@choonsik1

Motivation and Expected Behavior

Currently, kernels within a dataflow region can only be connected via Streams, hence FIFOs. In some cases a simple wire is needed instead of a FIFO which is not possible on dataflow level. This makes composability harder and leads to the need to put all logic within a single kernel to avoid the usage of a FIFO.

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