From 39752d582c7f24787c9e401e3e2f3be19f79a856 Mon Sep 17 00:00:00 2001
From: seedds <seedds@gmail.com>
Date: Fri, 30 Oct 2026 16:26:16 -0700
Subject: [PATCH] Fix shared UE region Python lint failures

---
 dm/tools/patch_nso.py | 1 +
 dm/tools/ue_region.py | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/dm/tools/patch_nso.py b/dm/tools/patch_nso.py
index e1b834deb3..f5fe49ccb4 100644
--- a/dm/tools/patch_nso.py
+++ b/dm/tools/patch_nso.py
@@ -1184,6 +1184,7 @@ def stdalloc_gates():
     region_obs.append((UE_CALL, OBS_UE_MALLOC, f'{NOP:08x}', 'FMallocBinned3 constructor call (cut): the object in x0; the host puts its allocator\'s vtable in (hle_uemalloc.c)'))
 # Unreal's engine region (above): the gate on the store of its size, which the callback changes in that register and x1, the size the call asks for
 if UE_REGION is not None:
+    assert UE_REGION_REG is not None, 'engine region gate has no size register'
     assert UE_REGION not in kinds and not any(lo <= UE_REGION < hi for wseg in windows for lo, hi in [(wseg[0].address, wseg[-1].address + 4)]), f'engine region gate conflicts with a rewrite site {UE_REGION:#x}'
     region_obs.append((UE_REGION, OBS_UE_REGION | UE_REGION_REG << 8, f'{struct.unpack_from("<I", IMG, UE_REGION)[0]:08x}',
                        f'Unreal\'s engine region: its size in x{UE_REGION_REG}, stored before nninitStartup reserves it; the host gives what the alias region has room for (hle_svc.c)'))
diff --git a/dm/tools/ue_region.py b/dm/tools/ue_region.py
index 9aec64ce9a..8ef095ff82 100644
--- a/dm/tools/ue_region.py
+++ b/dm/tools/ue_region.py
@@ -33,7 +33,7 @@ def size_store(img, call, start, md):
     vals, stores, x1_at = {}, [], None   # register → ('c', constant) | ('page',) | ('lo', the low 12 bits of an address)
     for ins in md.disasm(img[a:call], a):
         ops, m = ins.operands, ins.mnemonic
-        reg = lambda o: ins.reg_name(o.reg)
+        reg = lambda o, ins=ins: ins.reg_name(o.reg)
         if m == 'str' and reg(ops[0]).startswith('x') and ops[1].type == ARM64_OP_MEM and not ins.writeback and ops[1].mem.index == 0:   # str xS, [xB, #o]
             stores.append((ins.address, int(reg(ops[0])[1:]) if reg(ops[0]) != 'xzr' else None, ops[1].mem.disp, vals.get(reg(ops[0]))))
             continue