From e60a0fb1cecf65c5ac0fc0dfd5ea70ccb8b81bc9 Mon Sep 17 00:00:00 2001 From: Folkert de Vries Date: Sat, 25 Apr 2026 01:01:21 +0200 Subject: [PATCH] mark `vstl1_*` functions as unsafe these functions write to a raw pointer, and so are clearly unsafe to use --- .../core_arch/src/aarch64/neon/generated.rs | 56 +++++++++++-------- .../spec/neon/aarch64.spec.yml | 6 +- 2 files changed, 38 insertions(+), 24 deletions(-) diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs index c9ce7a69a6..a88e901bcf 100644 --- a/crates/core_arch/src/aarch64/neon/generated.rs +++ b/crates/core_arch/src/aarch64/neon/generated.rs @@ -25421,107 +25421,119 @@ pub unsafe fn vst4q_u64(a: *mut u64, b: uint64x2x4_t) { } #[doc = "Store-Release a single-element structure from one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] #[cfg(target_has_atomic = "64")] -pub fn vstl1_lane_f64(ptr: *mut f64, val: float64x1_t) { +pub unsafe fn vstl1_lane_f64(ptr: *mut f64, val: float64x1_t) { static_assert!(LANE == 0); - unsafe { vstl1_lane_s64::(ptr as *mut i64, transmute(val)) } + vstl1_lane_s64::(ptr as *mut i64, transmute(val)) } #[doc = "Store-Release a single-element structure from one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] #[cfg(target_has_atomic = "64")] -pub fn vstl1q_lane_f64(ptr: *mut f64, val: float64x2_t) { +pub unsafe fn vstl1q_lane_f64(ptr: *mut f64, val: float64x2_t) { static_assert_uimm_bits!(LANE, 1); - unsafe { vstl1q_lane_s64::(ptr as *mut i64, transmute(val)) } + vstl1q_lane_s64::(ptr as *mut i64, transmute(val)) } #[doc = "Store-Release a single-element structure from one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] #[cfg(target_has_atomic = "64")] -pub fn vstl1_lane_u64(ptr: *mut u64, val: uint64x1_t) { +pub unsafe fn vstl1_lane_u64(ptr: *mut u64, val: uint64x1_t) { static_assert!(LANE == 0); - unsafe { vstl1_lane_s64::(ptr as *mut i64, transmute(val)) } + vstl1_lane_s64::(ptr as *mut i64, transmute(val)) } #[doc = "Store-Release a single-element structure from one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] #[cfg(target_has_atomic = "64")] -pub fn vstl1q_lane_u64(ptr: *mut u64, val: uint64x2_t) { +pub unsafe fn vstl1q_lane_u64(ptr: *mut u64, val: uint64x2_t) { static_assert_uimm_bits!(LANE, 1); - unsafe { vstl1q_lane_s64::(ptr as *mut i64, transmute(val)) } + vstl1q_lane_s64::(ptr as *mut i64, transmute(val)) } #[doc = "Store-Release a single-element structure from one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] #[cfg(target_has_atomic = "64")] -pub fn vstl1_lane_p64(ptr: *mut p64, val: poly64x1_t) { +pub unsafe fn vstl1_lane_p64(ptr: *mut p64, val: poly64x1_t) { static_assert!(LANE == 0); - unsafe { vstl1_lane_s64::(ptr as *mut i64, transmute(val)) } + vstl1_lane_s64::(ptr as *mut i64, transmute(val)) } #[doc = "Store-Release a single-element structure from one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] #[cfg(target_has_atomic = "64")] -pub fn vstl1q_lane_p64(ptr: *mut p64, val: poly64x2_t) { +pub unsafe fn vstl1q_lane_p64(ptr: *mut p64, val: poly64x2_t) { static_assert_uimm_bits!(LANE, 1); - unsafe { vstl1q_lane_s64::(ptr as *mut i64, transmute(val)) } + vstl1q_lane_s64::(ptr as *mut i64, transmute(val)) } #[doc = "Store-Release a single-element structure from one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1_lane_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] #[cfg(target_has_atomic = "64")] -pub fn vstl1_lane_s64(ptr: *mut i64, val: int64x1_t) { +pub unsafe fn vstl1_lane_s64(ptr: *mut i64, val: int64x1_t) { static_assert!(LANE == 0); let atomic_dst = ptr as *mut crate::sync::atomic::AtomicI64; - unsafe { - let lane: i64 = simd_extract!(val, LANE as u32); - (*atomic_dst).store(transmute(lane), crate::sync::atomic::Ordering::Release) - } + let lane: i64 = simd_extract!(val, LANE as u32); + (*atomic_dst).store(transmute(lane), crate::sync::atomic::Ordering::Release) } #[doc = "Store-Release a single-element structure from one lane of one register."] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vstl1q_lane_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon intrinsic unsafe"] #[inline(always)] #[target_feature(enable = "neon,rcpc3")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(stl1, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_neon_feat_lrcpc3", issue = "none")] #[cfg(target_has_atomic = "64")] -pub fn vstl1q_lane_s64(ptr: *mut i64, val: int64x2_t) { +pub unsafe fn vstl1q_lane_s64(ptr: *mut i64, val: int64x2_t) { static_assert_uimm_bits!(LANE, 1); let atomic_dst = ptr as *mut crate::sync::atomic::AtomicI64; - unsafe { - let lane: i64 = simd_extract!(val, LANE as u32); - (*atomic_dst).store(transmute(lane), crate::sync::atomic::Ordering::Release) - } + let lane: i64 = simd_extract!(val, LANE as u32); + (*atomic_dst).store(transmute(lane), crate::sync::atomic::Ordering::Release) } #[doc = "Subtract"] #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f64)"] diff --git a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml index a769d35264..c8d63fd771 100644 --- a/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml +++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml @@ -4459,7 +4459,8 @@ intrinsics: doc: "Store-Release a single-element structure from one lane of one register." arguments: ["ptr: {type[0]}", "val: {neon_type[1]}"] static_defs: ["const LANE: i32"] - safety: safe + safety: + unsafe: [neon] attr: - FnCall: [target_feature, ['enable = "neon,rcpc3"']] - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [stl1, 'LANE = 0']]}]] @@ -4488,7 +4489,8 @@ intrinsics: doc: "Store-Release a single-element structure from one lane of one register." arguments: ["ptr: {type[0]}", "val: {neon_type[1]}"] static_defs: ["const LANE: i32"] - safety: safe + safety: + unsafe: [neon] attr: - FnCall: [target_feature, ['enable = "neon,rcpc3"']] - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env= "msvc"']]}]]}, {FnCall: [assert_instr, [stl1, 'LANE = 0']]}]]