diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 9e600605..8313aa8f 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -14,7 +14,7 @@ jobs:
     steps:
       - id: set-matrix
         run: |
-          echo 'rust_versions=["stable", "1.83"]' >> "$GITHUB_OUTPUT"
+          echo 'rust_versions=["stable", "1.85"]' >> "$GITHUB_OUTPUT"
           echo 'stable_targets=["armv7a-none-eabi","armv7a-none-eabihf","armv7r-none-eabi","armv7r-none-eabihf","armv8r-none-eabihf"]' >> "$GITHUB_OUTPUT"
 
   # Build the workspace for a target architecture
@@ -26,9 +26,9 @@ jobs:
         rust: ${{ fromJSON(needs.setup.outputs.rust-versions) }}
         target: ${{ fromJSON(needs.setup.outputs.stable-targets) }}
         exclude:
-          - rust: 1.83
+          - rust: 1.85
             target: armv7a-none-eabihf
-          - rust: 1.83
+          - rust: 1.85
             target: armv8r-none-eabihf
     steps:
       - name: Checkout
@@ -63,9 +63,9 @@ jobs:
         uses: taiki-e/install-action@just
       - name: Install Rust
         run: |
-          rustup install nightly-2026-02-26
-          rustup component add rust-src --toolchain nightly-2026-02-26
-          rustup default nightly-2026-02-26
+          rustup install stable
+          rustup default stable
+          rustup component add rust-src
       - name: Build
         run: |
           just build-tier3 ${{ matrix.target }}
@@ -89,9 +89,9 @@ jobs:
         uses: taiki-e/install-action@just
       - name: Install Rust
         run: |
-          rustup install nightly-2026-02-26
-          rustup component add rust-src --toolchain nightly-2026-02-26
-          rustup default nightly-2026-02-26
+          rustup install stable
+          rustup default stable
+          rustup component add rust-src
       - name: Build
         run: |
           just build-tier3-no-atomics ${{ matrix.target }}
@@ -132,9 +132,9 @@ jobs:
         rust: ${{ fromJSON(needs.setup.outputs.rust-versions) }}
         target: ${{ fromJSON(needs.setup.outputs.stable-targets) }}
         exclude:
-          - rust: 1.83
+          - rust: 1.85
             target: armv7a-none-eabihf
-          - rust: 1.83
+          - rust: 1.85
             target: armv8r-none-eabihf
     steps:
       - name: Checkout
diff --git a/Cargo.toml b/Cargo.toml
index 61edd8f7..cdfffa6e 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -11,4 +11,4 @@ members = [
   "aarch32-rt",
   "aarch32-rt-macros",
 ]
-resolver = "2"
+resolver = "3"
diff --git a/aarch32-cpu/CHANGELOG.md b/aarch32-cpu/CHANGELOG.md
index 623df8cd..d607b9ba 100644
--- a/aarch32-cpu/CHANGELOG.md
+++ b/aarch32-cpu/CHANGELOG.md
@@ -8,6 +8,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 ## [Unreleased]
 
 - Added `Iciallu` register which allows invalidating the instruction cache.
+- Bumped MSRV to v1.85 to allow switch to Edition 2024
 
 ## [aarch32-cpu v0.2.0]
 
diff --git a/aarch32-cpu/Cargo.toml b/aarch32-cpu/Cargo.toml
index 76903a97..465552b1 100644
--- a/aarch32-cpu/Cargo.toml
+++ b/aarch32-cpu/Cargo.toml
@@ -8,7 +8,7 @@ categories = [
     "no-std",
 ]
 description = "CPU support for AArch32 Arm Processors"
-edition = "2021"
+edition = "2024"
 keywords = [
     "arm",
     "cortex-a",
@@ -21,7 +21,7 @@ name = "aarch32-cpu"
 readme = "README.md"
 repository = "https://github.com/rust-embedded/aarch32.git"
 homepage = "https://github.com/rust-embedded/aarch32"
-rust-version = "1.83"
+rust-version = "1.85"
 version = "0.2.0"
 
 [dependencies]
@@ -51,11 +51,81 @@ serde = ["dep:serde", "arbitrary-int/serde"]
 check-asm = []
 
 [package.metadata.docs.rs]
-# This is a list of supported Tier 2 targets, as of latest stable
 targets = [
-    "armv7r-none-eabihf",
-    "armv7r-none-eabi",
-    "armv7a-none-eabihf",
+    "armebv7r-none-eabi",
+    "armebv7r-none-eabihf",
+    "armv4t-none-eabi",
+    "armv5te-none-eabi",
+    "armv6-none-eabi",
+    "armv6-none-eabihf",
     "armv7a-none-eabi",
-    "armv8r-none-eabihf"
+    "armv7a-none-eabihf",
+    "armv7r-none-eabi",
+    "armv7r-none-eabihf",
+    "armv8r-none-eabihf",
+    "thumbv4t-none-eabi",
+    "thumbv5te-none-eabi",
+    "thumbv6-none-eabi",
+    "thumbv7a-none-eabi",
+    "thumbv7a-none-eabihf",
+    "thumbv7r-none-eabi",
+    "thumbv7r-none-eabihf",
+    "thumbv8r-none-eabihf",
 ]
+cargo-args = ["-Z", "build-std"]
+
+[lints.rust]
+missing_docs = "warn" # Indicates missing documentation on public functions
+missing_abi = "warn" # Explicit ABI documents the assumptions of the code
+unsafe_op_in_unsafe_fn = "warn" # Satisfies the recommendation in section 4.3.1
+elided_lifetimes_in_paths = "warn" # Highlights confusing implicit use of types with lifetimes
+explicit_outlives_requirements = "warn" # Less explicit lifetime bounds improve readability
+macro_use-extern_crate = "warn" # obscures the source of identifiers
+meta_variable_misuse = "warn" # More macro quality checks outweigh potential false positives
+non-local-definitions = "warn" # Highlights outdated and confusing location of definitions
+redundant-lifetimes = "warn" # Highlights a mistake or unfinished code
+single-use-lifetimes = "warn" # Simplifies code, improving readability
+trivial-numeric-casts = "warn" # Simplifies code, improving readability
+unit-bindings = "warn" # Simplifies code, improving readability
+unnameable-types = "warn" # Highlights inconsistency in public interface
+unreachable-pub = "warn" # Highlights inconsistency in public interface
+variant-size-differences = "warn" # Highlights inefficient data structures
+rust-2018-compatibility = "warn"
+rust-2018-idioms = "warn"
+rust-2021-compatibility = "warn"
+rust-2024-compatibility = "warn"
+unused = { level = "warn", priority = -1 } # this group might overlap
+unused_results = "warn"
+unused-qualifications = "warn"
+unused-lifetimes = "warn"
+unused-import-braces = "warn"
+
+[lints.clippy]
+cast_lossless = "warn" # Indicates a more idiomatic way to replace the cast
+cast_possible_truncation = "warn"
+cast_possible_wrap = "warn"
+cast_ptr_alignment = "warn"
+cast_sign_loss = "warn" # Should be checked for and properly handled in safety related projects
+exit = "warn" # Calling exit directly is likely wrong in a safety related environment
+infinite_loop = "warn" # Indicates improper return type
+iter_over_hash_type = "warn" # Indicates unpredictable order
+invalid_upcast_comparisons = "warn" # Likely wrong code
+lossy_float_literal = "warn" # Indicates rounding error
+missing_errors_doc = "warn" # Indicates incomplete documentation
+missing_docs_in_private_items = "warn" # Undocumented internal items are not an option
+panic_in_result_fn = "warn" # Indicates unexpected behavior
+ptr_cast_constness = "warn"
+ref_as_ptr = "warn"
+transmute_ptr_to_ptr = "warn" # Safer alternative available
+redundant_type_annotations = "warn" # Simpler code, highlights special cases
+shadow_unrelated = "warn" # Unidiomatic and high-risk use of shadowing
+try_err = "warn" # Indicates non-idiomatic way to avoid return
+wildcard_enum_match_arm = "warn" # See section 4.4.21.3, clashes with non-exhaustive
+as_underscore = "warn"
+format_push_string = "warn" # Avoids extra allocation
+as_ptr_cast_mut = "deny" # Clear misuse with a better alternative
+let_underscore_must_use = "deny" # Prevents a shortcut to ignore must-use results
+missing_panics_doc = "deny" # Indicates missing panic documentation
+undocumented_unsafe_blocks = "deny" # Indicates missing "unsafe" reasoning
+wildcard_imports = "deny" # Indicates unconstrained symbol imports
+declare_interior_mutable_const = "deny" # Indicates common mistake
diff --git a/aarch32-cpu/README.md b/aarch32-cpu/README.md
index 495b739e..6bbedd5d 100644
--- a/aarch32-cpu/README.md
+++ b/aarch32-cpu/README.md
@@ -29,7 +29,7 @@ If you need a driver for the Arm Generic Interrupt Controller, see
 
 ## Minimum Supported Rust Version (MSRV)
 
-This crate is guaranteed to compile on stable Rust 1.83.0 and up, as recorded
+This crate is guaranteed to compile on stable Rust 1.85.0 and up, as recorded
 by the `package.rust-version` property in `Cargo.toml`.
 
 Increasing the MSRV is not considered a breaking change and may occur in a
diff --git a/aarch32-cpu/build.rs b/aarch32-cpu/build.rs
index 8371f210..66e87efd 100644
--- a/aarch32-cpu/build.rs
+++ b/aarch32-cpu/build.rs
@@ -5,5 +5,5 @@
 //! Copyright (c) Ferrous Systems, 2025
 
 fn main() {
-    arm_targets::process();
+    _ = arm_targets::process();
 }
diff --git a/aarch32-cpu/src/asmv4.rs b/aarch32-cpu/src/asmv4.rs
index b6db42af..d56db7b6 100644
--- a/aarch32-cpu/src/asmv4.rs
+++ b/aarch32-cpu/src/asmv4.rs
@@ -66,7 +66,8 @@ pub fn core_id() -> u32 {
     r & 0x00FF_FFFF
 }
 
-#[no_mangle]
+/// LLVM intrinsic for memory barriers
+#[unsafe(no_mangle)]
 pub extern "C" fn __sync_synchronize() {
     // we don't have a barrier instruction - the linux kernel just uses an empty inline asm block
     unsafe {
diff --git a/aarch32-cpu/src/asmv7.rs b/aarch32-cpu/src/asmv7.rs
index f101e3ee..10fe6d4c 100644
--- a/aarch32-cpu/src/asmv7.rs
+++ b/aarch32-cpu/src/asmv7.rs
@@ -7,7 +7,7 @@
 /// after the `DMB` instruction.
 #[cfg_attr(not(feature = "check-asm"), inline)]
 pub fn dmb() {
-    use core::sync::atomic::{compiler_fence, Ordering};
+    use core::sync::atomic::{Ordering, compiler_fence};
     compiler_fence(Ordering::SeqCst);
     unsafe {
         core::arch::asm!("dmb", options(nostack, preserves_flags));
@@ -24,7 +24,7 @@ pub fn dmb() {
 ///  * all cache and branch predictor maintenance operations before this instruction complete
 #[cfg_attr(not(feature = "check-asm"), inline)]
 pub fn dsb() {
-    use core::sync::atomic::{compiler_fence, Ordering};
+    use core::sync::atomic::{Ordering, compiler_fence};
     compiler_fence(Ordering::SeqCst);
     unsafe {
         core::arch::asm!("dsb", options(nostack, preserves_flags));
@@ -38,7 +38,7 @@ pub fn dsb() {
 /// from cache or memory, after the instruction has been completed.
 #[cfg_attr(not(feature = "check-asm"), inline)]
 pub fn isb() {
-    use core::sync::atomic::{compiler_fence, Ordering};
+    use core::sync::atomic::{Ordering, compiler_fence};
     compiler_fence(Ordering::SeqCst);
     unsafe {
         core::arch::asm!("isb", options(nostack, preserves_flags));
diff --git a/aarch32-cpu/src/critical_section.rs b/aarch32-cpu/src/critical_section.rs
index ba984028..5d2e003e 100644
--- a/aarch32-cpu/src/critical_section.rs
+++ b/aarch32-cpu/src/critical_section.rs
@@ -10,10 +10,10 @@ mod single_core {
     critical_section::set_impl!(SingleCoreCriticalSection);
 
     /// Indicates the critical section was entered with interrupts on
-    pub const INT_ON: u8 = 0;
+    const INT_ON: u8 = 0;
 
     /// Indicates the critical section was entered with interrupts off
-    pub const INT_OFF: u8 = 1;
+    const INT_OFF: u8 = 1;
 
     #[cfg(feature = "critical-section-single-core")]
     unsafe impl critical_section::Impl for SingleCoreCriticalSection {
@@ -23,11 +23,7 @@ mod single_core {
             let was_active = !crate::register::Cpsr::read().i();
             crate::interrupt::disable();
             atomic::compiler_fence(atomic::Ordering::SeqCst);
-            if was_active {
-                INT_ON
-            } else {
-                INT_OFF
-            }
+            if was_active { INT_ON } else { INT_OFF }
         }
 
         unsafe fn release(was_active: critical_section::RawRestoreState) {
@@ -52,18 +48,18 @@ mod multi_core {
     critical_section::set_impl!(MultiCoreCriticalSection);
 
     /// The default value for our spin-lock
-    pub const UNLOCKED: u32 = 0xFFFF_FFFF;
+    const UNLOCKED: u32 = 0xFFFF_FFFF;
 
     /// Indicates the critical section was entered with interrupts on, and the spin-lock unlocked
-    pub const INT_ON_UNLOCKED: u8 = 0;
+    const INT_ON_UNLOCKED: u8 = 0;
 
     /// Indicates the critical section was entered with interrupts off, and the spin-lock locked (by us)
-    pub const INT_OFF_LOCKED: u8 = 1;
+    const INT_OFF_LOCKED: u8 = 1;
 
     /// Indicates the critical section was entered with interrupts off, and the spin-lock unlocked
-    pub const INT_OFF_UNLOCKED: u8 = 2;
+    const INT_OFF_UNLOCKED: u8 = 2;
 
-    pub static CORE_SPIN_LOCK: core::sync::atomic::AtomicU32 =
+    static CORE_SPIN_LOCK: core::sync::atomic::AtomicU32 =
         core::sync::atomic::AtomicU32::new(UNLOCKED);
     unsafe impl critical_section::Impl for MultiCoreCriticalSection {
         unsafe fn acquire() -> critical_section::RawRestoreState {
diff --git a/aarch32-cpu/src/generic_timer/el0.rs b/aarch32-cpu/src/generic_timer/el0.rs
index d4a571e6..90dd61f3 100644
--- a/aarch32-cpu/src/generic_timer/el0.rs
+++ b/aarch32-cpu/src/generic_timer/el0.rs
@@ -2,7 +2,7 @@
 
 use crate::register;
 
-/// Represents our Physical Timer when we are running at EL0.
+/// Represents our Generic Physical Timer when we are running at EL0.
 ///
 /// Note that for most of these APIs to work, EL0 needs to have been granted
 /// access using methods like
@@ -75,11 +75,11 @@ impl super::GenericTimer for El0PhysicalTimer {
     }
 }
 
-/// Represents our Virtual Timer when we are running at EL0.
+/// Represents our Generic Virtual Timer when we are running at EL0.
 ///
 /// Note that for most of these APIs to work, EL0 needs to have been granted
 /// access using methods like
-/// [El1PhysicalTimer::el0_access_virtual_counter](crate::generic_timer::El1VirtualTimer::el0_access_virtual_counter).
+/// [El1VirtualTimer::el0_access_virtual_counter](crate::generic_timer::El1VirtualTimer::el0_access_virtual_counter).
 pub struct El0VirtualTimer();
 
 impl El0VirtualTimer {
diff --git a/aarch32-cpu/src/generic_timer/el2.rs b/aarch32-cpu/src/generic_timer/el2.rs
index fd34c915..2f79aa2b 100644
--- a/aarch32-cpu/src/generic_timer/el2.rs
+++ b/aarch32-cpu/src/generic_timer/el2.rs
@@ -161,7 +161,7 @@ impl El2HypPhysicalTimer {
     }
 }
 
-impl super::GenericTimer for El2HypPhysicalTimer {
+impl GenericTimer for El2HypPhysicalTimer {
     fn frequency_hz(&self) -> u32 {
         register::Cntfrq::read().0
     }
diff --git a/aarch32-cpu/src/interrupt.rs b/aarch32-cpu/src/interrupt.rs
index fca33b32..05929c8c 100644
--- a/aarch32-cpu/src/interrupt.rs
+++ b/aarch32-cpu/src/interrupt.rs
@@ -1,6 +1,6 @@
 //! Interrupts on Arm AArch32
 
-use core::sync::atomic::{compiler_fence, Ordering};
+use core::sync::atomic::{Ordering, compiler_fence};
 
 /// Enable interrupts
 ///
diff --git a/aarch32-cpu/src/lib.rs b/aarch32-cpu/src/lib.rs
index 4df0fce5..644e70ff 100644
--- a/aarch32-cpu/src/lib.rs
+++ b/aarch32-cpu/src/lib.rs
@@ -1,7 +1,14 @@
 //! CPU/peripheral support for Arm AArch32
 #![no_std]
+#![deny(missing_docs)]
+#![deny(unsafe_op_in_unsafe_fn)]
+#![deny(clippy::missing_safety_doc)]
+#![deny(clippy::unnecessary_safety_comment)]
+#![deny(clippy::unnecessary_safety_doc)]
 
-mod critical_section;
+pub mod cache;
+pub mod interrupt;
+pub mod register;
 
 #[cfg(any(
     doc,
@@ -21,26 +28,22 @@ pub mod asm;
 #[path = "asmv4.rs"]
 pub mod asm;
 
-pub mod cache;
-
 #[cfg(any(test, doc, arm_architecture = "v7-a", arm_architecture = "v8-r"))]
 pub mod generic_timer;
 
-pub mod interrupt;
-
-#[cfg(any(test, doc, arm_architecture = "v7-a"))]
+#[cfg(any(test, arm_profile = "a", arm_profile = "legacy"))]
 pub mod mmu;
 
-pub mod register;
+#[cfg(any(test, arm_architecture = "v7-r"))]
+pub mod pmsav7;
+
+#[cfg(any(test, arm_architecture = "v8-r"))]
+pub mod pmsav8;
 
 #[cfg(target_arch = "arm")]
 pub mod stacks;
 
-#[cfg(any(test, doc, arm_architecture = "v7-r"))]
-pub mod pmsav7;
-
-#[cfg(any(test, doc, arm_architecture = "v8-r"))]
-pub mod pmsav8;
+mod critical_section;
 
 /// Generate an SVC call with no parameters.
 ///
@@ -52,7 +55,7 @@ pub mod pmsav8;
 /// ```
 #[macro_export]
 macro_rules! svc {
-    ($num:expr) => { {
+    ($num:expr_2021) => { {
         let retval: u32;
         unsafe {
             core::arch::asm!("svc {arg}", arg = const $num, lateout("r0") retval);
@@ -72,7 +75,7 @@ macro_rules! svc {
 /// ```
 #[macro_export]
 macro_rules! svc1 {
-    ($num:expr, $arg0:expr) => { {
+    ($num:expr_2021, $arg0:expr_2021) => { {
         let retval: u32;
         let arg0: u32 = $arg0;
         unsafe {
@@ -97,7 +100,7 @@ macro_rules! svc1 {
 /// ```
 #[macro_export]
 macro_rules! svc2 {
-    ($num:expr, $arg0:expr, $arg1:expr) => { {
+    ($num:expr_2021, $arg0:expr_2021, $arg1:expr_2021) => { {
         let retval: u32;
         let arg0: u32 = $arg0;
         let arg1: u32 = $arg1;
@@ -124,7 +127,7 @@ macro_rules! svc2 {
 /// ```
 #[macro_export]
 macro_rules! svc3 {
-    ($num:expr, $arg0:expr, $arg1:expr, $arg2:expr) => { {
+    ($num:expr_2021, $arg0:expr_2021, $arg1:expr_2021, $arg2:expr_2021) => { {
         let retval: u32;
         let arg0: u32 = $arg0;
         let arg1: u32 = $arg1;
@@ -153,7 +156,7 @@ macro_rules! svc3 {
 /// ```
 #[macro_export]
 macro_rules! svc4 {
-    ($num:expr, $arg0:expr, $arg1:expr, $arg2:expr, $arg3:expr) => { {
+    ($num:expr_2021, $arg0:expr_2021, $arg1:expr_2021, $arg2:expr_2021, $arg3:expr_2021) => { {
         let retval: u32;
         let arg0: u32 = $arg0;
         let arg1: u32 = $arg1;
@@ -184,7 +187,7 @@ macro_rules! svc4 {
 /// ```
 #[macro_export]
 macro_rules! svc5 {
-    ($num:expr, $arg0:expr, $arg1:expr, $arg2:expr, $arg3:expr, $arg4:expr) => { {
+    ($num:expr_2021, $arg0:expr_2021, $arg1:expr_2021, $arg2:expr_2021, $arg3:expr_2021, $arg4:expr_2021) => { {
         let retval: u32;
         let arg0: u32 = $arg0;
         let arg1: u32 = $arg1;
@@ -217,7 +220,7 @@ macro_rules! svc5 {
 /// ```
 #[macro_export]
 macro_rules! svc6 {
-    ($num:expr, $arg0:expr, $arg1:expr, $arg2:expr, $arg3:expr, $arg4:expr, $arg5:expr) => { {
+    ($num:expr_2021, $arg0:expr_2021, $arg1:expr_2021, $arg2:expr_2021, $arg3:expr_2021, $arg4:expr_2021, $arg5:expr_2021) => { {
         let retval: u32;
         let arg0: u32 = $arg0;
         let arg1: u32 = $arg1;
@@ -244,7 +247,7 @@ macro_rules! svc6 {
 /// Generate an HVC call with the given argument.
 #[macro_export]
 macro_rules! hvc {
-    ($r0:expr) => {
+    ($r0:expr_2021) => {
         unsafe {
             core::arch::asm!("hvc {arg}", arg = const $r0);
         }
@@ -262,7 +265,7 @@ macro_rules! hvc {
 /// ```
 #[macro_export]
 macro_rules! hvc1 {
-    ($num:expr, $arg0:expr) => { {
+    ($num:expr_2021, $arg0:expr_2021) => { {
         let retval: u32;
         let arg0: u32 = $arg0;
         unsafe {
@@ -287,7 +290,7 @@ macro_rules! hvc1 {
 /// ```
 #[macro_export]
 macro_rules! hvc2 {
-    ($num:expr, $arg0:expr, $arg1:expr) => { {
+    ($num:expr_2021, $arg0:expr_2021, $arg1:expr_2021) => { {
         let retval: u32;
         let arg0: u32 = $arg0;
         let arg1: u32 = $arg1;
@@ -314,7 +317,7 @@ macro_rules! hvc2 {
 /// ```
 #[macro_export]
 macro_rules! hvc3 {
-    ($num:expr, $arg0:expr, $arg1:expr, $arg2:expr) => { {
+    ($num:expr_2021, $arg0:expr_2021, $arg1:expr_2021, $arg2:expr_2021) => { {
         let retval: u32;
         let arg0: u32 = $arg0;
         let arg1: u32 = $arg1;
@@ -343,7 +346,7 @@ macro_rules! hvc3 {
 /// ```
 #[macro_export]
 macro_rules! hvc4 {
-    ($num:expr, $arg0:expr, $arg1:expr, $arg2:expr, $arg3:expr) => { {
+    ($num:expr_2021, $arg0:expr_2021, $arg1:expr_2021, $arg2:expr_2021, $arg3:expr_2021) => { {
         let retval: u32;
         let arg0: u32 = $arg0;
         let arg1: u32 = $arg1;
@@ -374,7 +377,7 @@ macro_rules! hvc4 {
 /// ```
 #[macro_export]
 macro_rules! hvc5 {
-    ($num:expr, $arg0:expr, $arg1:expr, $arg2:expr, $arg3:expr, $arg4:expr) => { {
+    ($num:expr_2021, $arg0:expr_2021, $arg1:expr_2021, $arg2:expr_2021, $arg3:expr_2021, $arg4:expr_2021) => { {
         let retval: u32;
         let arg0: u32 = $arg0;
         let arg1: u32 = $arg1;
@@ -407,7 +410,7 @@ macro_rules! hvc5 {
 /// ```
 #[macro_export]
 macro_rules! hvc6 {
-    ($num:expr, $arg0:expr, $arg1:expr, $arg2:expr, $arg3:expr, $arg4:expr, $arg5:expr) => { {
+    ($num:expr_2021, $arg0:expr_2021, $arg1:expr_2021, $arg2:expr_2021, $arg3:expr_2021, $arg4:expr_2021, $arg5:expr_2021) => { {
         let retval: u32;
         let arg0: u32 = $arg0;
         let arg1: u32 = $arg1;
diff --git a/aarch32-cpu/src/mmu.rs b/aarch32-cpu/src/mmu.rs
index baafeacc..aed202c4 100644
--- a/aarch32-cpu/src/mmu.rs
+++ b/aarch32-cpu/src/mmu.rs
@@ -1,6 +1,6 @@
 //! Support for the VMSAv7 MMU
 
-use arbitrary_int::{u12, u2, u3, u4};
+use arbitrary_int::{u2, u3, u4, u12};
 
 /// Number of 1 MiB pages in a 4 GiB virtual address space
 pub const NUM_L1_PAGE_TABLE_ENTRIES: usize = 4096;
@@ -9,7 +9,11 @@ pub const NUM_L1_PAGE_TABLE_ENTRIES: usize = 4096;
 ///
 /// You should create a static variable of this type, to represent your page table.
 #[repr(C, align(1048576))]
+#[derive(Debug)]
 pub struct L1Table {
+    /// Our mutable list of MMU table entries
+    ///
+    /// This table is read by the hardware.
     pub entries: core::cell::UnsafeCell<[L1Section; NUM_L1_PAGE_TABLE_ENTRIES]>,
 }
 
@@ -24,25 +28,39 @@ unsafe impl Sync for L1Table {}
 pub struct InvalidL1EntryType(pub L1EntryType);
 
 /// Access permissions for a region of memory
-#[bitbybit::bitenum(u3, exhaustive = true)]
+#[bitbybit::bitenum(u3)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 #[derive(Debug, PartialEq, Eq)]
 pub enum AccessPermissions {
+    /// All accesses generate Permission faults
     PermissionFault = 0b000,
+    /// Privileged access only
     PrivilegedOnly = 0b001,
+    /// Writes in User mode generate Permission faults
     NoUserWrite = 0b010,
+    /// Full access
     FullAccess = 0b011,
-    _Reserved1 = 0b100,
+    /// Privileged read-only
     PrivilegedReadOnly = 0b101,
-    ReadOnly = 0b110,
-    _Reserved2 = 0b111,
+    /// Privileged and User read-only (deprecated in VMSAv7)
+    ReadOnlyv6 = 0b110,
+    /// Privileged and User read-only
+    ReadOnly = 0b111,
 }
 
 impl AccessPermissions {
+    /// Create a new [`AccessPermissions`] value from the APX bit at the AP bit
+    /// pair
+    ///
+    /// Will panic if you select an invalid value.
     #[inline]
     pub const fn new(apx: bool, ap: u2) -> Self {
-        Self::new_with_raw_value(u3::new(((apx as u8) << 2) | ap.value()))
+        let x = u3::new(((apx as u8) << 2) | ap.value());
+        let Ok(ap) = Self::new_with_raw_value(x) else {
+            panic!("Invalid access permissions");
+        };
+        ap
     }
 
     /// AP bit for the given access permission.
@@ -65,21 +83,25 @@ impl AccessPermissions {
 #[derive(Debug, PartialEq, Eq)]
 #[repr(u8)]
 pub enum L1EntryType {
-    /// Access generates an abort exception. Indicates an unmapped virtual address.
+    /// Access generates an abort exception. Indicates an unmapped virtual
+    /// address.
     Fault = 0b00,
-    /// Entry points to a L2 translation table, allowing 1 MB of memory to be further divided
+    /// Entry points to a L2 translation table, allowing 1 MB of memory to be
+    /// further divided
     PageTable = 0b01,
     /// Maps a 1 MB region to a physical address.
     Section = 0b10,
-    /// Special 1MB section entry which requires 16 entries in the translation table.
+    /// Special 1MB section entry which requires 16 entries in the translation
+    /// table.
     Supersection = 0b11,
 }
 
-/// The ARM Cortex-A architecture reference manual p.1363 specifies these attributes in more detail.
+/// The ARM Cortex-A architecture reference manual p.1363 specifies these
+/// attributes in more detail.
 ///
-/// The B (Bufferable), C (Cacheable), and TEX (Type extension) bit names are inherited from
-/// earlier versions of the architecture. These names no longer adequately describe the function
-/// of the B, C, and TEX bits.
+/// The B (Bufferable), C (Cacheable), and TEX (Type extension) bit names are
+/// inherited from earlier versions of the architecture. These names no longer
+/// adequately describe the function of the B, C, and TEX bits.
 #[derive(Debug, Copy, Clone, PartialEq, Eq)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
@@ -91,6 +113,7 @@ pub struct MemoryRegionAttributesRaw {
 }
 
 impl MemoryRegionAttributesRaw {
+    /// Create a new [`MemoryRegionAttributesRaw`] from constituent parts
     #[inline]
     pub const fn new(type_extensions: u3, c: bool, b: bool) -> Self {
         Self {
@@ -105,11 +128,15 @@ impl MemoryRegionAttributesRaw {
 #[bitbybit::bitenum(u2, exhaustive = true)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
-#[derive(Debug)]
-pub enum CacheableMemoryAttribute {
+#[derive(Debug, PartialEq, Eq)]
+pub enum CachePolicy {
+    /// Non-cacheable
     NonCacheable = 0b00,
+    /// Write-Back Cacheable, Write-Allocate
     WriteBackWriteAlloc = 0b01,
+    /// Write-Through Cacheable
     WriteThroughNoWriteAlloc = 0b10,
+    /// Write-Back Cacheable, no Write-Allocate
     WriteBackNoWriteAlloc = 0b11,
 }
 
@@ -118,20 +145,43 @@ pub enum CacheableMemoryAttribute {
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub enum MemoryRegionAttributes {
+    /// Strongly- ordered
+    ///
+    /// All memory accesses to Strongly-ordered memory occur in program order.
+    /// All Strongly-ordered regions are assumed to be Shareable.
     StronglyOrdered,
+    /// Device Shareable
+    ///
+    /// Intended to handle memory-mapped peripherals that are shared by several
+    /// processors.
     ShareableDevice,
+    /// Normal Memory, Write-Through Cacheable for both Inner and Outer Cache
     OuterAndInnerWriteThroughNoWriteAlloc,
+    /// Normal Memory, Write-Back no Write-Allocate Cacheable for both Inner and
+    /// Outer Cache
     OuterAndInnerWriteBackNoWriteAlloc,
+    /// Normal Memory, Non-cacheable for both Inner and Outer Cache
     OuterAndInnerNonCacheable,
+    /// Normal Memory, Write-Back Write-Allocate Cacheable for both Inner and
+    /// Outer Cache
     OuterAndInnerWriteBackWriteAlloc,
+    /// Device Non-Shareable
+    ///
+    /// Intended to handle memory-mapped peripherals that are used only by a
+    /// single processor.
     NonShareableDevice,
+    /// Normal Memory, where Inner and Outer cache have different settings
     CacheableMemory {
-        inner: CacheableMemoryAttribute,
-        outer: CacheableMemoryAttribute,
+        /// Settings for the Inner Cache
+        inner: CachePolicy,
+        /// Settings for the Outer Cache
+        outer: CachePolicy,
     },
 }
 
 impl MemoryRegionAttributes {
+    /// Convert the Rust enum type [`MemoryRegionAttributes`] into a raw
+    /// [`MemoryRegionAttributesRaw`] value for the hardware
     pub const fn as_raw(&self) -> MemoryRegionAttributesRaw {
         match self {
             MemoryRegionAttributes::StronglyOrdered => {
@@ -175,10 +225,13 @@ pub struct SectionAttributes {
     pub non_global: bool,
     /// Implementation defined bit.
     pub p_bit: bool,
+    /// Is memory shareable across multiple CPUs
     pub shareable: bool,
-    /// AP bits
+    /// Access permissions
     pub access: AccessPermissions,
+    /// Raw memory attributes
     pub memory_attrs: MemoryRegionAttributesRaw,
+    /// Domain value for this section
     pub domain: u4,
     /// xN bit.
     pub execute_never: bool,
@@ -195,7 +248,8 @@ impl SectionAttributes {
         Ok(Self::from_raw_unchecked(raw))
     }
 
-    /// Retrieves the corresponding L1 section part without the section base address being set.
+    /// Retrieves the corresponding L1 section part without the section base
+    /// address being set.
     const fn l1_section_part(&self) -> L1Section {
         L1Section::builder()
             .with_base_addr_upper_bits(u12::new(0))
@@ -231,8 +285,9 @@ impl SectionAttributes {
 
 /// 1 MB section translation entry, mapping a 1 MB region to a physical address.
 ///
-/// The ARM Cortex-A architecture programmers manual chapter 9.4 (p.163) or the ARMv7-A and ArmV7-R
-/// architecture reference manual p.1323 specify these attributes in more detail.
+/// The ARM Cortex-A architecture programmers manual chapter 9.4 (p.163) or the
+/// ARMv7-A and ArmV7-R architecture reference manual p.1323 specify these
+/// attributes in more detail.
 #[bitbybit::bitfield(u32, default = 0, defmt_fields(feature = "defmt"))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 #[derive(PartialEq, Eq)]
@@ -246,23 +301,31 @@ pub struct L1Section {
     /// Shareable bit.
     #[bit(16, rw)]
     s: bool,
+    /// Part of the access permissions field
     #[bit(15, rw)]
     apx: bool,
-    /// Type extension bits.
+    /// Memory Region Attribute bit
     #[bits(12..=14, rw)]
     tex: u3,
+    /// Part of the access permissions field
     #[bits(10..=11, rw)]
     ap: u2,
+    /// Implementation defined bit
     #[bit(9, rw)]
     p_bit: bool,
+    /// Domain field
     #[bits(5..=8, rw)]
     domain: u4,
+    /// Execute-never bit
     #[bit(4, rw)]
     xn: bool,
+    /// Memory Region Attribute bit
     #[bit(3, rw)]
     c: bool,
+    /// Memory Region Attribute bit
     #[bit(2, rw)]
     b: bool,
+    /// Entry Type
     #[bits(0..=1, rw)]
     entry_type: L1EntryType,
 }
@@ -287,11 +350,12 @@ impl core::fmt::Debug for L1Section {
 }
 
 impl L1Section {
-    /// Generates a new L1 section from a physical address and section attributes.
+    /// Generates a new L1 section from a physical address and section
+    /// attributes.
     ///
-    /// The uppermost 12 bits of the physical address define which 1 MB of virtual address space
-    /// are being accessed. They will be stored in the L1 section table. This address MUST be
-    /// aligned to 1 MB.
+    /// The uppermost 12 bits of the physical address define which 1 MB of
+    /// virtual address space are being accessed. They will be stored in the L1
+    /// section table. This address MUST be aligned to 1 MB.
     ///
     /// # Panics
     ///
@@ -316,7 +380,8 @@ impl L1Section {
         *self = Self::new_with_addr_upper_bits_and_attrs(self.base_addr_upper_bits(), section_attrs)
     }
 
-    /// Create a new L1 section with the given upper 12 bits of the address and section attributes.
+    /// Create a new L1 section with the given upper 12 bits of the address and
+    /// section attributes.
     #[inline]
     pub const fn new_with_addr_upper_bits_and_attrs(
         addr_upper_twelve_bits: u12,
@@ -368,8 +433,8 @@ mod tests {
         access: AccessPermissions::FullAccess,
         // TEX 0b101, c false, b true
         memory_attrs: MemoryRegionAttributes::CacheableMemory {
-            inner: CacheableMemoryAttribute::WriteBackWriteAlloc,
-            outer: CacheableMemoryAttribute::WriteBackWriteAlloc,
+            inner: CachePolicy::WriteBackWriteAlloc,
+            outer: CachePolicy::WriteBackWriteAlloc,
         }
         .as_raw(),
         domain: u4::new(0b1010),
@@ -431,7 +496,7 @@ mod tests {
             p_bit: true,
             shareable: false,
             // APX true, AP 0b10
-            access: AccessPermissions::ReadOnly,
+            access: AccessPermissions::ReadOnlyv6,
             // TEX 0b000, c false, b false
             memory_attrs: MemoryRegionAttributes::StronglyOrdered.as_raw(),
             domain: u4::new(0b1001),
diff --git a/aarch32-cpu/src/pmsav7.rs b/aarch32-cpu/src/pmsav7.rs
index 2b55a457..117ebc7a 100644
--- a/aarch32-cpu/src/pmsav7.rs
+++ b/aarch32-cpu/src/pmsav7.rs
@@ -8,6 +8,7 @@
 use crate::register;
 
 use arbitrary_int::{u2, u3};
+
 #[doc(inline)]
 pub use register::drsr::RegionSize;
 
@@ -108,7 +109,7 @@ impl Mpu {
     }
 
     /// Configure the EL1 MPU
-    pub fn configure(&mut self, config: &Config) -> Result<(), Error> {
+    pub fn configure(&mut self, config: &Config<'_>) -> Result<(), Error> {
         if config.iregions.len() > self.num_iregions() as usize {
             return Err(Error::TooManyRegions);
         }
@@ -235,21 +236,42 @@ pub enum MemAttr {
     /// Strongly-ordered memory
     StronglyOrdered,
     /// Device (shareable or non-shareable)
-    Device { shareable: bool },
-    /// Outer and Inner Write-Through, no Write-Allocate
-    WriteThroughNoWriteAllocate { shareable: bool },
-    /// Outer and Inner Write-Back, no Write-Allocate
-    WriteBackNoWriteAllocate { shareable: bool },
-    /// Outer and Inner Non-cacheable
-    NonCacheable { shareable: bool },
+    Device {
+        /// Is device shareable (across multiple CPUs)
+        shareable: bool,
+    },
+    /// Normal Memory, Outer and Inner Cache are Write-Through, no Write-Allocate
+    WriteThroughNoWriteAlloc {
+        /// Is memory shareable (across multiple CPUs)
+        shareable: bool,
+    },
+    /// Normal Memory, Outer and Inner Cache are Write-Back, no Write-Allocate
+    WriteBackNoWriteAlloc {
+        /// Is memory shareable (across multiple CPUs)
+        shareable: bool,
+    },
+    /// Normal Memory, Non-cacheable in Outer and Inner Caches
+    NonCacheable {
+        /// Is memory shareable (across multiple CPUs)
+        shareable: bool,
+    },
     /// Implementation Defined
-    ImplementationDefined { shareable: bool },
+    ImplementationDefined {
+        /// Is memory shareable (across multiple CPUs)
+        shareable: bool,
+    },
     /// Outer and Inner Write-Back, Write-Allocate
-    WriteBackWriteAllocate { shareable: bool },
-    /// Cacheable memory
+    WriteBackWriteAlloc {
+        /// Is memory shareable (across multiple CPUs)
+        shareable: bool,
+    },
+    /// Normal Memory, where Inner and Outer cache have different settings
     Cacheable {
-        outer: CacheablePolicy,
-        inner: CacheablePolicy,
+        /// Settings for the Outer Cache
+        outer: CachePolicy,
+        /// Settings for the Inner Cache
+        inner: CachePolicy,
+        /// Is memory shareable (across multiple CPUs)
         shareable: bool,
     },
 }
@@ -276,13 +298,13 @@ impl MemAttr {
                 b: false,
                 s: false,
             },
-            MemAttr::WriteThroughNoWriteAllocate { shareable } => MemAttrBits {
+            MemAttr::WriteThroughNoWriteAlloc { shareable } => MemAttrBits {
                 tex: u3::from_u8(0b000),
                 c: true,
                 b: false,
                 s: *shareable,
             },
-            MemAttr::WriteBackNoWriteAllocate { shareable } => MemAttrBits {
+            MemAttr::WriteBackNoWriteAlloc { shareable } => MemAttrBits {
                 tex: u3::from_u8(0b000),
                 c: true,
                 b: true,
@@ -300,7 +322,7 @@ impl MemAttr {
                 b: false,
                 s: *shareable,
             },
-            MemAttr::WriteBackWriteAllocate { shareable } => MemAttrBits {
+            MemAttr::WriteBackWriteAlloc { shareable } => MemAttrBits {
                 tex: u3::from_u8(0b000),
                 c: true,
                 b: true,
@@ -338,20 +360,18 @@ impl MemAttrBits {
         match (self.tex.value(), self.c, self.b) {
             (0b000, false, false) => Some(MemAttr::StronglyOrdered),
             (0b000, false, true) => Some(MemAttr::Device { shareable: true }),
-            (0b000, true, false) => {
-                Some(MemAttr::WriteThroughNoWriteAllocate { shareable: self.s })
-            }
-            (0b000, true, true) => Some(MemAttr::WriteBackNoWriteAllocate { shareable: self.s }),
+            (0b000, true, false) => Some(MemAttr::WriteThroughNoWriteAlloc { shareable: self.s }),
+            (0b000, true, true) => Some(MemAttr::WriteBackNoWriteAlloc { shareable: self.s }),
             (0b001, false, false) => Some(MemAttr::NonCacheable { shareable: self.s }),
             (0b001, true, false) => Some(MemAttr::ImplementationDefined { shareable: self.s }),
-            (0b001, true, true) => Some(MemAttr::WriteBackWriteAllocate { shareable: self.s }),
+            (0b001, true, true) => Some(MemAttr::WriteBackWriteAlloc { shareable: self.s }),
             (0b010, false, false) => Some(MemAttr::Device { shareable: false }),
             (tex, c, b) if tex >= 0b100 => {
                 let outer = tex & 0b11;
                 let inner = ((c as u8) << 1) | (b as u8);
                 Some(MemAttr::Cacheable {
-                    outer: CacheablePolicy::new_with_raw_value(u2::from_u8(outer)),
-                    inner: CacheablePolicy::new_with_raw_value(u2::from_u8(inner)),
+                    outer: CachePolicy::new_with_raw_value(u2::from_u8(outer)),
+                    inner: CachePolicy::new_with_raw_value(u2::from_u8(inner)),
                     shareable: self.s,
                 })
             }
@@ -363,14 +383,20 @@ impl MemAttrBits {
     }
 }
 
-/// Describes the cache policy of a region
-#[derive(Debug, PartialEq, Eq)]
+/// Whether/how a region is cacheable
 #[bitbybit::bitenum(u2, exhaustive = true)]
-pub enum CacheablePolicy {
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
+#[derive(Debug, PartialEq, Eq)]
+pub enum CachePolicy {
+    /// Non-cacheable
     NonCacheable = 0b00,
-    WriteBackWriteAllocate = 0b01,
-    WriteThroughNoWriteAllocate = 0b10,
-    WriteBackNoWriteAllocate = 0b11,
+    /// Write-Back Cacheable, Write-Allocate
+    WriteBackWriteAlloc = 0b01,
+    /// Write-Through Cacheable
+    WriteThroughNoWriteAlloc = 0b10,
+    /// Write-Back Cacheable, no Write-Allocate
+    WriteBackNoWriteAlloc = 0b11,
 }
 
 #[cfg(test)]
@@ -398,9 +424,9 @@ mod test {
     fn mem_attr_complex() {
         let mem_attr = MemAttr::Cacheable {
             // 0b01
-            outer: CacheablePolicy::WriteBackWriteAllocate,
+            outer: CachePolicy::WriteBackWriteAlloc,
             // 0b10
-            inner: CacheablePolicy::WriteThroughNoWriteAllocate,
+            inner: CachePolicy::WriteThroughNoWriteAlloc,
             shareable: true,
         };
         let mem_attr_bits = mem_attr.to_bits();
diff --git a/aarch32-cpu/src/pmsav8.rs b/aarch32-cpu/src/pmsav8.rs
index 91be34ed..9a1aff33 100644
--- a/aarch32-cpu/src/pmsav8.rs
+++ b/aarch32-cpu/src/pmsav8.rs
@@ -6,7 +6,7 @@
 //!
 //! [armv8r]: https://developer.arm.com/documentation/ddi0568/latest/
 
-use arbitrary_int::{u26, u3};
+use arbitrary_int::{u3, u26};
 
 use crate::register;
 
@@ -172,7 +172,7 @@ impl El1Mpu {
     ///
     /// Write regions, attributes and enable/disable the background region
     /// with a single [El1Config] struct.
-    pub fn configure(&mut self, config: &El1Config) -> Result<(), Error> {
+    pub fn configure(&mut self, config: &El1Config<'_>) -> Result<(), Error> {
         self.set_regions(0, config.regions)?;
 
         self.set_attributes(config.memory_attributes);
@@ -336,7 +336,7 @@ impl El2Mpu {
     /// Configure the EL2 MPU
     ///
     /// Write regions, attributes and enable/disable the background region with a single [El2Config] struct.
-    pub fn configure(&mut self, config: &El2Config) -> Result<(), Error> {
+    pub fn configure(&mut self, config: &El2Config<'_>) -> Result<(), Error> {
         self.set_regions(0, config.regions)?;
 
         self.set_attributes(config.memory_attributes);
@@ -461,9 +461,9 @@ pub enum MemAttr {
     /// Normal memory
     NormalMemory {
         /// Controls outer access
-        outer: Cacheable,
+        outer: CachePolicy,
         /// Controls inner access
-        inner: Cacheable,
+        inner: CachePolicy,
     },
 }
 
@@ -484,23 +484,28 @@ impl MemAttr {
 
 /// Cacheability of a region
 #[derive(Debug, Clone, PartialEq, Eq)]
-pub enum Cacheable {
+pub enum CachePolicy {
+    /// Normal memory, Outer Write-Through Transient
     WriteThroughTransient(RwAllocPolicy),
+    /// Normal memory, Outer Write-Back Transient
     WriteBackTransient(RwAllocPolicy),
+    /// Normal memory, Outer Write-Through Non-transient
     WriteThroughNonTransient(RwAllocPolicy),
+    /// Normal memory, Outer Write-Back Non-transient
     WriteBackNonTransient(RwAllocPolicy),
+    /// Normal memory, Outer Non-cacheable
     NonCacheable,
 }
 
-impl Cacheable {
+impl CachePolicy {
     const fn to_bits(&self) -> u8 {
         #[allow(clippy::identity_op)]
         match self {
-            Cacheable::WriteThroughTransient(rw_alloc) => 0b0000 | (*rw_alloc as u8),
-            Cacheable::WriteBackTransient(rw_alloc) => 0b0100 | (*rw_alloc as u8),
-            Cacheable::WriteThroughNonTransient(rw_alloc) => 0b1000 | (*rw_alloc as u8),
-            Cacheable::WriteBackNonTransient(rw_alloc) => 0b1100 | (*rw_alloc as u8),
-            Cacheable::NonCacheable => 0b0100,
+            CachePolicy::WriteThroughTransient(rw_alloc) => 0b0000 | (*rw_alloc as u8),
+            CachePolicy::WriteBackTransient(rw_alloc) => 0b0100 | (*rw_alloc as u8),
+            CachePolicy::WriteThroughNonTransient(rw_alloc) => 0b1000 | (*rw_alloc as u8),
+            CachePolicy::WriteBackNonTransient(rw_alloc) => 0b1100 | (*rw_alloc as u8),
+            CachePolicy::NonCacheable => 0b0100,
         }
     }
 }
@@ -536,8 +541,8 @@ mod test {
     #[test]
     fn mem_attr_normal() {
         let mem_attr = MemAttr::NormalMemory {
-            outer: Cacheable::NonCacheable,
-            inner: Cacheable::WriteBackNonTransient(RwAllocPolicy::W),
+            outer: CachePolicy::NonCacheable,
+            inner: CachePolicy::WriteBackNonTransient(RwAllocPolicy::W),
         };
         assert_eq!(
             mem_attr.to_bits(),
diff --git a/aarch32-cpu/src/register/actlr.rs b/aarch32-cpu/src/register/actlr.rs
index d4b909f8..7484720b 100644
--- a/aarch32-cpu/src/register/actlr.rs
+++ b/aarch32-cpu/src/register/actlr.rs
@@ -16,7 +16,7 @@ impl SysReg for Actlr {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for Actlr {}
+impl SysRegRead for Actlr {}
 
 impl Actlr {
     #[inline]
@@ -26,7 +26,7 @@ impl Actlr {
     }
 }
 
-impl crate::register::SysRegWrite for Actlr {}
+impl SysRegWrite for Actlr {}
 
 impl Actlr {
     #[inline]
diff --git a/aarch32-cpu/src/register/actlr2.rs b/aarch32-cpu/src/register/actlr2.rs
index bc2b79f0..20fa2853 100644
--- a/aarch32-cpu/src/register/actlr2.rs
+++ b/aarch32-cpu/src/register/actlr2.rs
@@ -16,7 +16,7 @@ impl SysReg for Actlr2 {
     const OP2: u32 = 3;
 }
 
-impl crate::register::SysRegRead for Actlr2 {}
+impl SysRegRead for Actlr2 {}
 
 impl Actlr2 {
     #[inline]
@@ -26,7 +26,7 @@ impl Actlr2 {
     }
 }
 
-impl crate::register::SysRegWrite for Actlr2 {}
+impl SysRegWrite for Actlr2 {}
 
 impl Actlr2 {
     #[inline]
diff --git a/aarch32-cpu/src/register/adfsr.rs b/aarch32-cpu/src/register/adfsr.rs
index 17406c93..c6755c1e 100644
--- a/aarch32-cpu/src/register/adfsr.rs
+++ b/aarch32-cpu/src/register/adfsr.rs
@@ -16,7 +16,7 @@ impl SysReg for Adfsr {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for Adfsr {}
+impl SysRegRead for Adfsr {}
 
 impl Adfsr {
     #[inline]
@@ -26,7 +26,7 @@ impl Adfsr {
     }
 }
 
-impl crate::register::SysRegWrite for Adfsr {}
+impl SysRegWrite for Adfsr {}
 
 impl Adfsr {
     #[inline]
diff --git a/aarch32-cpu/src/register/aidr.rs b/aarch32-cpu/src/register/aidr.rs
index d126d460..49825eed 100644
--- a/aarch32-cpu/src/register/aidr.rs
+++ b/aarch32-cpu/src/register/aidr.rs
@@ -16,7 +16,7 @@ impl SysReg for Aidr {
     const OP2: u32 = 7;
 }
 
-impl crate::register::SysRegRead for Aidr {}
+impl SysRegRead for Aidr {}
 
 impl Aidr {
     #[inline]
diff --git a/aarch32-cpu/src/register/aifsr.rs b/aarch32-cpu/src/register/aifsr.rs
index dc99a22f..23d3c54b 100644
--- a/aarch32-cpu/src/register/aifsr.rs
+++ b/aarch32-cpu/src/register/aifsr.rs
@@ -16,7 +16,7 @@ impl SysReg for Aifsr {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for Aifsr {}
+impl SysRegRead for Aifsr {}
 
 impl Aifsr {
     #[inline]
@@ -26,7 +26,7 @@ impl Aifsr {
     }
 }
 
-impl crate::register::SysRegWrite for Aifsr {}
+impl SysRegWrite for Aifsr {}
 
 impl Aifsr {
     #[inline]
diff --git a/aarch32-cpu/src/register/amair0.rs b/aarch32-cpu/src/register/amair0.rs
index 9f3ebfce..18edb795 100644
--- a/aarch32-cpu/src/register/amair0.rs
+++ b/aarch32-cpu/src/register/amair0.rs
@@ -16,7 +16,7 @@ impl SysReg for Amair0 {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for Amair0 {}
+impl SysRegRead for Amair0 {}
 
 impl Amair0 {
     #[inline]
@@ -26,7 +26,7 @@ impl Amair0 {
     }
 }
 
-impl crate::register::SysRegWrite for Amair0 {}
+impl SysRegWrite for Amair0 {}
 
 impl Amair0 {
     #[inline]
diff --git a/aarch32-cpu/src/register/amair1.rs b/aarch32-cpu/src/register/amair1.rs
index 5a9e8d6b..5583a595 100644
--- a/aarch32-cpu/src/register/amair1.rs
+++ b/aarch32-cpu/src/register/amair1.rs
@@ -16,7 +16,7 @@ impl SysReg for Amair1 {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for Amair1 {}
+impl SysRegRead for Amair1 {}
 
 impl Amair1 {
     #[inline]
@@ -26,7 +26,7 @@ impl Amair1 {
     }
 }
 
-impl crate::register::SysRegWrite for Amair1 {}
+impl SysRegWrite for Amair1 {}
 
 impl Amair1 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/hmpuir.rs b/aarch32-cpu/src/register/armv8r/hmpuir.rs
index 090fc4b6..bb3bcb7b 100644
--- a/aarch32-cpu/src/register/armv8r/hmpuir.rs
+++ b/aarch32-cpu/src/register/armv8r/hmpuir.rs
@@ -19,12 +19,13 @@ impl SysReg for Hmpuir {
     const OP2: u32 = 4;
 }
 
-impl crate::register::SysRegRead for Hmpuir {}
+impl SysRegRead for Hmpuir {}
 
 impl Hmpuir {
     #[inline]
     /// Reads HMPUIR (*Hyp MPU Type Register*)
     pub fn read() -> Hmpuir {
+        // Safety: it's OK to set bits with no accessors specified
         unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
     }
 }
diff --git a/aarch32-cpu/src/register/armv8r/hprbar.rs b/aarch32-cpu/src/register/armv8r/hprbar.rs
index e313c1ef..18d59855 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar.rs
@@ -61,17 +61,18 @@ impl SysReg for Hprbar {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for Hprbar {}
+impl SysRegRead for Hprbar {}
 
 impl Hprbar {
     #[inline]
     /// Reads HPRBAR (*Hyp Protection Region Base Address Register*)
     pub fn read() -> Hprbar {
+        // Safety: it's OK to set bits with no accessors specified
         unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
     }
 }
 
-impl crate::register::SysRegWrite for Hprbar {}
+impl SysRegWrite for Hprbar {}
 
 impl Hprbar {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/hprbar0.rs b/aarch32-cpu/src/register/armv8r/hprbar0.rs
index 00161ab6..4272b37d 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar0.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar0.rs
@@ -16,7 +16,7 @@ impl SysReg for Hprbar0 {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for Hprbar0 {}
+impl SysRegRead for Hprbar0 {}
 
 impl Hprbar0 {
     #[inline]
@@ -26,7 +26,7 @@ impl Hprbar0 {
     }
 }
 
-impl crate::register::SysRegWrite for Hprbar0 {}
+impl SysRegWrite for Hprbar0 {}
 
 impl Hprbar0 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/hprbar1.rs b/aarch32-cpu/src/register/armv8r/hprbar1.rs
index f5c988a5..611cefdc 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar1.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar1.rs
@@ -16,7 +16,7 @@ impl SysReg for Hprbar1 {
     const OP2: u32 = 4;
 }
 
-impl crate::register::SysRegRead for Hprbar1 {}
+impl SysRegRead for Hprbar1 {}
 
 impl Hprbar1 {
     #[inline]
@@ -26,7 +26,7 @@ impl Hprbar1 {
     }
 }
 
-impl crate::register::SysRegWrite for Hprbar1 {}
+impl SysRegWrite for Hprbar1 {}
 
 impl Hprbar1 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/hprbar10.rs b/aarch32-cpu/src/register/armv8r/hprbar10.rs
index 3167b274..6be89e19 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar10.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar10.rs
@@ -16,7 +16,7 @@ impl SysReg for Hprbar10 {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for Hprbar10 {}
+impl SysRegRead for Hprbar10 {}
 
 impl Hprbar10 {
     #[inline]
@@ -26,7 +26,7 @@ impl Hprbar10 {
     }
 }
 
-impl crate::register::SysRegWrite for Hprbar10 {}
+impl SysRegWrite for Hprbar10 {}
 
 impl Hprbar10 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/hprbar11.rs b/aarch32-cpu/src/register/armv8r/hprbar11.rs
index 8abca05c..a5b29f03 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar11.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar11.rs
@@ -16,7 +16,7 @@ impl SysReg for Hprbar11 {
     const OP2: u32 = 4;
 }
 
-impl crate::register::SysRegRead for Hprbar11 {}
+impl SysRegRead for Hprbar11 {}
 
 impl Hprbar11 {
     #[inline]
@@ -26,7 +26,7 @@ impl Hprbar11 {
     }
 }
 
-impl crate::register::SysRegWrite for Hprbar11 {}
+impl SysRegWrite for Hprbar11 {}
 
 impl Hprbar11 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/hprbar12.rs b/aarch32-cpu/src/register/armv8r/hprbar12.rs
index 735a147c..35aa1650 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar12.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar12.rs
@@ -16,7 +16,7 @@ impl SysReg for Hprbar12 {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for Hprbar12 {}
+impl SysRegRead for Hprbar12 {}
 
 impl Hprbar12 {
     #[inline]
@@ -26,7 +26,7 @@ impl Hprbar12 {
     }
 }
 
-impl crate::register::SysRegWrite for Hprbar12 {}
+impl SysRegWrite for Hprbar12 {}
 
 impl Hprbar12 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/hprbar13.rs b/aarch32-cpu/src/register/armv8r/hprbar13.rs
index 4afa8142..ff693782 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar13.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar13.rs
@@ -16,7 +16,7 @@ impl SysReg for Hprbar13 {
     const OP2: u32 = 4;
 }
 
-impl crate::register::SysRegRead for Hprbar13 {}
+impl SysRegRead for Hprbar13 {}
 
 impl Hprbar13 {
     #[inline]
@@ -26,7 +26,7 @@ impl Hprbar13 {
     }
 }
 
-impl crate::register::SysRegWrite for Hprbar13 {}
+impl SysRegWrite for Hprbar13 {}
 
 impl Hprbar13 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/hprbar14.rs b/aarch32-cpu/src/register/armv8r/hprbar14.rs
index 9ae75ca2..b91f8710 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar14.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar14.rs
@@ -16,7 +16,7 @@ impl SysReg for Hprbar14 {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for Hprbar14 {}
+impl SysRegRead for Hprbar14 {}
 
 impl Hprbar14 {
     #[inline]
@@ -26,7 +26,7 @@ impl Hprbar14 {
     }
 }
 
-impl crate::register::SysRegWrite for Hprbar14 {}
+impl SysRegWrite for Hprbar14 {}
 
 impl Hprbar14 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/hprbar15.rs b/aarch32-cpu/src/register/armv8r/hprbar15.rs
index ce6e56d8..3485c646 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar15.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar15.rs
@@ -16,7 +16,7 @@ impl SysReg for Hprbar15 {
     const OP2: u32 = 4;
 }
 
-impl crate::register::SysRegRead for Hprbar15 {}
+impl SysRegRead for Hprbar15 {}
 
 impl Hprbar15 {
     #[inline]
@@ -26,7 +26,7 @@ impl Hprbar15 {
     }
 }
 
-impl crate::register::SysRegWrite for Hprbar15 {}
+impl SysRegWrite for Hprbar15 {}
 
 impl Hprbar15 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/hprbar2.rs b/aarch32-cpu/src/register/armv8r/hprbar2.rs
index 1d4a1af7..58800c81 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar2.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar2.rs
@@ -16,7 +16,7 @@ impl SysReg for Hprbar2 {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for Hprbar2 {}
+impl SysRegRead for Hprbar2 {}
 
 impl Hprbar2 {
     #[inline]
@@ -26,7 +26,7 @@ impl Hprbar2 {
     }
 }
 
-impl crate::register::SysRegWrite for Hprbar2 {}
+impl SysRegWrite for Hprbar2 {}
 
 impl Hprbar2 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/hprbar3.rs b/aarch32-cpu/src/register/armv8r/hprbar3.rs
index 208743d6..fbf1e2b5 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar3.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar3.rs
@@ -16,7 +16,7 @@ impl SysReg for Hprbar3 {
     const OP2: u32 = 4;
 }
 
-impl crate::register::SysRegRead for Hprbar3 {}
+impl SysRegRead for Hprbar3 {}
 
 impl Hprbar3 {
     #[inline]
@@ -26,7 +26,7 @@ impl Hprbar3 {
     }
 }
 
-impl crate::register::SysRegWrite for Hprbar3 {}
+impl SysRegWrite for Hprbar3 {}
 
 impl Hprbar3 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/hprbar4.rs b/aarch32-cpu/src/register/armv8r/hprbar4.rs
index 3476af55..9982dc29 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar4.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar4.rs
@@ -16,7 +16,7 @@ impl SysReg for Hprbar4 {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for Hprbar4 {}
+impl SysRegRead for Hprbar4 {}
 
 impl Hprbar4 {
     #[inline]
@@ -26,7 +26,7 @@ impl Hprbar4 {
     }
 }
 
-impl crate::register::SysRegWrite for Hprbar4 {}
+impl SysRegWrite for Hprbar4 {}
 
 impl Hprbar4 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/hprbar5.rs b/aarch32-cpu/src/register/armv8r/hprbar5.rs
index ee606ac5..789ab69b 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar5.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar5.rs
@@ -16,7 +16,7 @@ impl SysReg for Hprbar5 {
     const OP2: u32 = 4;
 }
 
-impl crate::register::SysRegRead for Hprbar5 {}
+impl SysRegRead for Hprbar5 {}
 
 impl Hprbar5 {
     #[inline]
@@ -26,7 +26,7 @@ impl Hprbar5 {
     }
 }
 
-impl crate::register::SysRegWrite for Hprbar5 {}
+impl SysRegWrite for Hprbar5 {}
 
 impl Hprbar5 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/hprbar6.rs b/aarch32-cpu/src/register/armv8r/hprbar6.rs
index 743fdf59..53c95aff 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar6.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar6.rs
@@ -16,7 +16,7 @@ impl SysReg for Hprbar6 {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for Hprbar6 {}
+impl SysRegRead for Hprbar6 {}
 
 impl Hprbar6 {
     #[inline]
@@ -26,7 +26,7 @@ impl Hprbar6 {
     }
 }
 
-impl crate::register::SysRegWrite for Hprbar6 {}
+impl SysRegWrite for Hprbar6 {}
 
 impl Hprbar6 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/hprbar7.rs b/aarch32-cpu/src/register/armv8r/hprbar7.rs
index 5ee4cce4..d0f992eb 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar7.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar7.rs
@@ -16,7 +16,7 @@ impl SysReg for Hprbar7 {
     const OP2: u32 = 4;
 }
 
-impl crate::register::SysRegRead for Hprbar7 {}
+impl SysRegRead for Hprbar7 {}
 
 impl Hprbar7 {
     #[inline]
@@ -26,7 +26,7 @@ impl Hprbar7 {
     }
 }
 
-impl crate::register::SysRegWrite for Hprbar7 {}
+impl SysRegWrite for Hprbar7 {}
 
 impl Hprbar7 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/hprbar8.rs b/aarch32-cpu/src/register/armv8r/hprbar8.rs
index a8404afc..ae9987ea 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar8.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar8.rs
@@ -16,7 +16,7 @@ impl SysReg for Hprbar8 {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for Hprbar8 {}
+impl SysRegRead for Hprbar8 {}
 
 impl Hprbar8 {
     #[inline]
@@ -26,7 +26,7 @@ impl Hprbar8 {
     }
 }
 
-impl crate::register::SysRegWrite for Hprbar8 {}
+impl SysRegWrite for Hprbar8 {}
 
 impl Hprbar8 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/hprbar9.rs b/aarch32-cpu/src/register/armv8r/hprbar9.rs
index 93d07c80..5008c100 100644
--- a/aarch32-cpu/src/register/armv8r/hprbar9.rs
+++ b/aarch32-cpu/src/register/armv8r/hprbar9.rs
@@ -16,7 +16,7 @@ impl SysReg for Hprbar9 {
     const OP2: u32 = 4;
 }
 
-impl crate::register::SysRegRead for Hprbar9 {}
+impl SysRegRead for Hprbar9 {}
 
 impl Hprbar9 {
     #[inline]
@@ -26,7 +26,7 @@ impl Hprbar9 {
     }
 }
 
-impl crate::register::SysRegWrite for Hprbar9 {}
+impl SysRegWrite for Hprbar9 {}
 
 impl Hprbar9 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/hprenr.rs b/aarch32-cpu/src/register/armv8r/hprenr.rs
index ccc556b4..0014bc61 100644
--- a/aarch32-cpu/src/register/armv8r/hprenr.rs
+++ b/aarch32-cpu/src/register/armv8r/hprenr.rs
@@ -16,7 +16,7 @@ impl SysReg for Hprenr {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for Hprenr {}
+impl SysRegRead for Hprenr {}
 
 impl Hprenr {
     #[inline]
@@ -26,7 +26,7 @@ impl Hprenr {
     }
 }
 
-impl crate::register::SysRegWrite for Hprenr {}
+impl SysRegWrite for Hprenr {}
 
 impl Hprenr {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/hprlar.rs b/aarch32-cpu/src/register/armv8r/hprlar.rs
index b4f4549c..76af0e32 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar.rs
@@ -1,6 +1,6 @@
 //! Code for managing HPRLAR (*Hyp Protection Region Limit Address Register*)
 
-use arbitrary_int::{u26, u3};
+use arbitrary_int::{u3, u26};
 
 use crate::register::{SysReg, SysRegRead, SysRegWrite};
 
@@ -26,17 +26,18 @@ impl SysReg for Hprlar {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for Hprlar {}
+impl SysRegRead for Hprlar {}
 
 impl Hprlar {
     #[inline]
     /// Reads HPRLAR (*Hyp Protection Region Limit Address Register*)
     pub fn read() -> Hprlar {
+        // Safety: it's OK to set bits with no accessors specified
         unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
     }
 }
 
-impl crate::register::SysRegWrite for Hprlar {}
+impl SysRegWrite for Hprlar {}
 
 impl Hprlar {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/hprlar0.rs b/aarch32-cpu/src/register/armv8r/hprlar0.rs
index cdfec7d6..26233fbd 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar0.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar0.rs
@@ -16,7 +16,7 @@ impl SysReg for Hprlar0 {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for Hprlar0 {}
+impl SysRegRead for Hprlar0 {}
 
 impl Hprlar0 {
     #[inline]
@@ -26,7 +26,7 @@ impl Hprlar0 {
     }
 }
 
-impl crate::register::SysRegWrite for Hprlar0 {}
+impl SysRegWrite for Hprlar0 {}
 
 impl Hprlar0 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/hprlar1.rs b/aarch32-cpu/src/register/armv8r/hprlar1.rs
index 34dc23b7..759350ab 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar1.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar1.rs
@@ -16,7 +16,7 @@ impl SysReg for Hprlar1 {
     const OP2: u32 = 5;
 }
 
-impl crate::register::SysRegRead for Hprlar1 {}
+impl SysRegRead for Hprlar1 {}
 
 impl Hprlar1 {
     #[inline]
@@ -26,7 +26,7 @@ impl Hprlar1 {
     }
 }
 
-impl crate::register::SysRegWrite for Hprlar1 {}
+impl SysRegWrite for Hprlar1 {}
 
 impl Hprlar1 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/hprlar10.rs b/aarch32-cpu/src/register/armv8r/hprlar10.rs
index e32f2055..a6968210 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar10.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar10.rs
@@ -16,7 +16,7 @@ impl SysReg for Hprlar10 {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for Hprlar10 {}
+impl SysRegRead for Hprlar10 {}
 
 impl Hprlar10 {
     #[inline]
@@ -26,7 +26,7 @@ impl Hprlar10 {
     }
 }
 
-impl crate::register::SysRegWrite for Hprlar10 {}
+impl SysRegWrite for Hprlar10 {}
 
 impl Hprlar10 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/hprlar11.rs b/aarch32-cpu/src/register/armv8r/hprlar11.rs
index 4685e3a8..08131b5e 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar11.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar11.rs
@@ -16,7 +16,7 @@ impl SysReg for Hprlar11 {
     const OP2: u32 = 5;
 }
 
-impl crate::register::SysRegRead for Hprlar11 {}
+impl SysRegRead for Hprlar11 {}
 
 impl Hprlar11 {
     #[inline]
@@ -26,7 +26,7 @@ impl Hprlar11 {
     }
 }
 
-impl crate::register::SysRegWrite for Hprlar11 {}
+impl SysRegWrite for Hprlar11 {}
 
 impl Hprlar11 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/hprlar12.rs b/aarch32-cpu/src/register/armv8r/hprlar12.rs
index 7b44a656..2ca65e75 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar12.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar12.rs
@@ -16,7 +16,7 @@ impl SysReg for Hprlar12 {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for Hprlar12 {}
+impl SysRegRead for Hprlar12 {}
 
 impl Hprlar12 {
     #[inline]
@@ -26,7 +26,7 @@ impl Hprlar12 {
     }
 }
 
-impl crate::register::SysRegWrite for Hprlar12 {}
+impl SysRegWrite for Hprlar12 {}
 
 impl Hprlar12 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/hprlar13.rs b/aarch32-cpu/src/register/armv8r/hprlar13.rs
index ca44175a..14d7edd9 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar13.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar13.rs
@@ -16,7 +16,7 @@ impl SysReg for Hprlar13 {
     const OP2: u32 = 5;
 }
 
-impl crate::register::SysRegRead for Hprlar13 {}
+impl SysRegRead for Hprlar13 {}
 
 impl Hprlar13 {
     #[inline]
@@ -26,7 +26,7 @@ impl Hprlar13 {
     }
 }
 
-impl crate::register::SysRegWrite for Hprlar13 {}
+impl SysRegWrite for Hprlar13 {}
 
 impl Hprlar13 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/hprlar14.rs b/aarch32-cpu/src/register/armv8r/hprlar14.rs
index 339d09d7..d3ecc35c 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar14.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar14.rs
@@ -16,7 +16,7 @@ impl SysReg for Hprlar14 {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for Hprlar14 {}
+impl SysRegRead for Hprlar14 {}
 
 impl Hprlar14 {
     #[inline]
@@ -26,7 +26,7 @@ impl Hprlar14 {
     }
 }
 
-impl crate::register::SysRegWrite for Hprlar14 {}
+impl SysRegWrite for Hprlar14 {}
 
 impl Hprlar14 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/hprlar15.rs b/aarch32-cpu/src/register/armv8r/hprlar15.rs
index e06fa459..bbcec63d 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar15.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar15.rs
@@ -16,7 +16,7 @@ impl SysReg for Hprlar15 {
     const OP2: u32 = 5;
 }
 
-impl crate::register::SysRegRead for Hprlar15 {}
+impl SysRegRead for Hprlar15 {}
 
 impl Hprlar15 {
     #[inline]
@@ -26,7 +26,7 @@ impl Hprlar15 {
     }
 }
 
-impl crate::register::SysRegWrite for Hprlar15 {}
+impl SysRegWrite for Hprlar15 {}
 
 impl Hprlar15 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/hprlar2.rs b/aarch32-cpu/src/register/armv8r/hprlar2.rs
index ecc55c13..53db9c37 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar2.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar2.rs
@@ -16,7 +16,7 @@ impl SysReg for Hprlar2 {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for Hprlar2 {}
+impl SysRegRead for Hprlar2 {}
 
 impl Hprlar2 {
     #[inline]
@@ -26,7 +26,7 @@ impl Hprlar2 {
     }
 }
 
-impl crate::register::SysRegWrite for Hprlar2 {}
+impl SysRegWrite for Hprlar2 {}
 
 impl Hprlar2 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/hprlar3.rs b/aarch32-cpu/src/register/armv8r/hprlar3.rs
index 2d80fb5d..df5f677a 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar3.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar3.rs
@@ -16,7 +16,7 @@ impl SysReg for Hprlar3 {
     const OP2: u32 = 5;
 }
 
-impl crate::register::SysRegRead for Hprlar3 {}
+impl SysRegRead for Hprlar3 {}
 
 impl Hprlar3 {
     #[inline]
@@ -26,7 +26,7 @@ impl Hprlar3 {
     }
 }
 
-impl crate::register::SysRegWrite for Hprlar3 {}
+impl SysRegWrite for Hprlar3 {}
 
 impl Hprlar3 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/hprlar4.rs b/aarch32-cpu/src/register/armv8r/hprlar4.rs
index 840ea92e..0c6b911c 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar4.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar4.rs
@@ -16,7 +16,7 @@ impl SysReg for Hprlar4 {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for Hprlar4 {}
+impl SysRegRead for Hprlar4 {}
 
 impl Hprlar4 {
     #[inline]
@@ -26,7 +26,7 @@ impl Hprlar4 {
     }
 }
 
-impl crate::register::SysRegWrite for Hprlar4 {}
+impl SysRegWrite for Hprlar4 {}
 
 impl Hprlar4 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/hprlar5.rs b/aarch32-cpu/src/register/armv8r/hprlar5.rs
index 254d358f..7bd30c7e 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar5.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar5.rs
@@ -16,7 +16,7 @@ impl SysReg for Hprlar5 {
     const OP2: u32 = 5;
 }
 
-impl crate::register::SysRegRead for Hprlar5 {}
+impl SysRegRead for Hprlar5 {}
 
 impl Hprlar5 {
     #[inline]
@@ -26,7 +26,7 @@ impl Hprlar5 {
     }
 }
 
-impl crate::register::SysRegWrite for Hprlar5 {}
+impl SysRegWrite for Hprlar5 {}
 
 impl Hprlar5 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/hprlar6.rs b/aarch32-cpu/src/register/armv8r/hprlar6.rs
index 3f35515f..d6aaace1 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar6.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar6.rs
@@ -16,7 +16,7 @@ impl SysReg for Hprlar6 {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for Hprlar6 {}
+impl SysRegRead for Hprlar6 {}
 
 impl Hprlar6 {
     #[inline]
@@ -26,7 +26,7 @@ impl Hprlar6 {
     }
 }
 
-impl crate::register::SysRegWrite for Hprlar6 {}
+impl SysRegWrite for Hprlar6 {}
 
 impl Hprlar6 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/hprlar7.rs b/aarch32-cpu/src/register/armv8r/hprlar7.rs
index bd57de79..14e1fb78 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar7.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar7.rs
@@ -16,7 +16,7 @@ impl SysReg for Hprlar7 {
     const OP2: u32 = 5;
 }
 
-impl crate::register::SysRegRead for Hprlar7 {}
+impl SysRegRead for Hprlar7 {}
 
 impl Hprlar7 {
     #[inline]
@@ -26,7 +26,7 @@ impl Hprlar7 {
     }
 }
 
-impl crate::register::SysRegWrite for Hprlar7 {}
+impl SysRegWrite for Hprlar7 {}
 
 impl Hprlar7 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/hprlar8.rs b/aarch32-cpu/src/register/armv8r/hprlar8.rs
index 67f5246a..fd1c36c3 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar8.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar8.rs
@@ -16,7 +16,7 @@ impl SysReg for Hprlar8 {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for Hprlar8 {}
+impl SysRegRead for Hprlar8 {}
 
 impl Hprlar8 {
     #[inline]
@@ -26,7 +26,7 @@ impl Hprlar8 {
     }
 }
 
-impl crate::register::SysRegWrite for Hprlar8 {}
+impl SysRegWrite for Hprlar8 {}
 
 impl Hprlar8 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/hprlar9.rs b/aarch32-cpu/src/register/armv8r/hprlar9.rs
index 00459760..d7ee0bad 100644
--- a/aarch32-cpu/src/register/armv8r/hprlar9.rs
+++ b/aarch32-cpu/src/register/armv8r/hprlar9.rs
@@ -16,7 +16,7 @@ impl SysReg for Hprlar9 {
     const OP2: u32 = 5;
 }
 
-impl crate::register::SysRegRead for Hprlar9 {}
+impl SysRegRead for Hprlar9 {}
 
 impl Hprlar9 {
     #[inline]
@@ -26,7 +26,7 @@ impl Hprlar9 {
     }
 }
 
-impl crate::register::SysRegWrite for Hprlar9 {}
+impl SysRegWrite for Hprlar9 {}
 
 impl Hprlar9 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/hprselr.rs b/aarch32-cpu/src/register/armv8r/hprselr.rs
index ea2c18be..db990b0d 100644
--- a/aarch32-cpu/src/register/armv8r/hprselr.rs
+++ b/aarch32-cpu/src/register/armv8r/hprselr.rs
@@ -16,7 +16,7 @@ impl SysReg for Hprselr {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for Hprselr {}
+impl SysRegRead for Hprselr {}
 
 impl Hprselr {
     #[inline]
@@ -26,7 +26,7 @@ impl Hprselr {
     }
 }
 
-impl crate::register::SysRegWrite for Hprselr {}
+impl SysRegWrite for Hprselr {}
 
 impl Hprselr {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/mod.rs b/aarch32-cpu/src/register/armv8r/mod.rs
index b033b6f6..84c957c0 100644
--- a/aarch32-cpu/src/register/armv8r/mod.rs
+++ b/aarch32-cpu/src/register/armv8r/mod.rs
@@ -78,12 +78,6 @@ pub use hmpuir::Hmpuir;
 pub use hprbar::Hprbar;
 pub use hprbar0::Hprbar0;
 pub use hprbar1::Hprbar1;
-pub use hprbar10::Hprbar10;
-pub use hprbar11::Hprbar11;
-pub use hprbar12::Hprbar12;
-pub use hprbar13::Hprbar13;
-pub use hprbar14::Hprbar14;
-pub use hprbar15::Hprbar15;
 pub use hprbar2::Hprbar2;
 pub use hprbar3::Hprbar3;
 pub use hprbar4::Hprbar4;
@@ -92,16 +86,16 @@ pub use hprbar6::Hprbar6;
 pub use hprbar7::Hprbar7;
 pub use hprbar8::Hprbar8;
 pub use hprbar9::Hprbar9;
+pub use hprbar10::Hprbar10;
+pub use hprbar11::Hprbar11;
+pub use hprbar12::Hprbar12;
+pub use hprbar13::Hprbar13;
+pub use hprbar14::Hprbar14;
+pub use hprbar15::Hprbar15;
 pub use hprenr::Hprenr;
 pub use hprlar::Hprlar;
 pub use hprlar0::Hprlar0;
 pub use hprlar1::Hprlar1;
-pub use hprlar10::Hprlar10;
-pub use hprlar11::Hprlar11;
-pub use hprlar12::Hprlar12;
-pub use hprlar13::Hprlar13;
-pub use hprlar14::Hprlar14;
-pub use hprlar15::Hprlar15;
 pub use hprlar2::Hprlar2;
 pub use hprlar3::Hprlar3;
 pub use hprlar4::Hprlar4;
@@ -110,16 +104,16 @@ pub use hprlar6::Hprlar6;
 pub use hprlar7::Hprlar7;
 pub use hprlar8::Hprlar8;
 pub use hprlar9::Hprlar9;
+pub use hprlar10::Hprlar10;
+pub use hprlar11::Hprlar11;
+pub use hprlar12::Hprlar12;
+pub use hprlar13::Hprlar13;
+pub use hprlar14::Hprlar14;
+pub use hprlar15::Hprlar15;
 pub use hprselr::Hprselr;
 pub use prbar::Prbar;
 pub use prbar0::Prbar0;
 pub use prbar1::Prbar1;
-pub use prbar10::Prbar10;
-pub use prbar11::Prbar11;
-pub use prbar12::Prbar12;
-pub use prbar13::Prbar13;
-pub use prbar14::Prbar14;
-pub use prbar15::Prbar15;
 pub use prbar2::Prbar2;
 pub use prbar3::Prbar3;
 pub use prbar4::Prbar4;
@@ -128,15 +122,15 @@ pub use prbar6::Prbar6;
 pub use prbar7::Prbar7;
 pub use prbar8::Prbar8;
 pub use prbar9::Prbar9;
+pub use prbar10::Prbar10;
+pub use prbar11::Prbar11;
+pub use prbar12::Prbar12;
+pub use prbar13::Prbar13;
+pub use prbar14::Prbar14;
+pub use prbar15::Prbar15;
 pub use prlar::Prlar;
 pub use prlar0::Prlar0;
 pub use prlar1::Prlar1;
-pub use prlar10::Prlar10;
-pub use prlar11::Prlar11;
-pub use prlar12::Prlar12;
-pub use prlar13::Prlar13;
-pub use prlar14::Prlar14;
-pub use prlar15::Prlar15;
 pub use prlar2::Prlar2;
 pub use prlar3::Prlar3;
 pub use prlar4::Prlar4;
@@ -145,5 +139,11 @@ pub use prlar6::Prlar6;
 pub use prlar7::Prlar7;
 pub use prlar8::Prlar8;
 pub use prlar9::Prlar9;
+pub use prlar10::Prlar10;
+pub use prlar11::Prlar11;
+pub use prlar12::Prlar12;
+pub use prlar13::Prlar13;
+pub use prlar14::Prlar14;
+pub use prlar15::Prlar15;
 pub use prselr::Prselr;
 pub use vbar::Vbar;
diff --git a/aarch32-cpu/src/register/armv8r/prbar.rs b/aarch32-cpu/src/register/armv8r/prbar.rs
index 4acabd14..2c1e7cd0 100644
--- a/aarch32-cpu/src/register/armv8r/prbar.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar.rs
@@ -61,17 +61,18 @@ impl SysReg for Prbar {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for Prbar {}
+impl SysRegRead for Prbar {}
 
 impl Prbar {
     #[inline]
     /// Reads PRBAR (*Protection Region Base Address Register*)
     pub fn read() -> Prbar {
+        // Safety: it's OK to set bits with no accessors specified
         unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
     }
 }
 
-impl crate::register::SysRegWrite for Prbar {}
+impl SysRegWrite for Prbar {}
 
 impl Prbar {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/prbar0.rs b/aarch32-cpu/src/register/armv8r/prbar0.rs
index ed78bf45..56ec5802 100644
--- a/aarch32-cpu/src/register/armv8r/prbar0.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar0.rs
@@ -16,7 +16,7 @@ impl SysReg for Prbar0 {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for Prbar0 {}
+impl SysRegRead for Prbar0 {}
 
 impl Prbar0 {
     #[inline]
@@ -26,7 +26,7 @@ impl Prbar0 {
     }
 }
 
-impl crate::register::SysRegWrite for Prbar0 {}
+impl SysRegWrite for Prbar0 {}
 
 impl Prbar0 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/prbar1.rs b/aarch32-cpu/src/register/armv8r/prbar1.rs
index 2b343fc5..001852e4 100644
--- a/aarch32-cpu/src/register/armv8r/prbar1.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar1.rs
@@ -16,7 +16,7 @@ impl SysReg for Prbar1 {
     const OP2: u32 = 4;
 }
 
-impl crate::register::SysRegRead for Prbar1 {}
+impl SysRegRead for Prbar1 {}
 
 impl Prbar1 {
     #[inline]
@@ -26,7 +26,7 @@ impl Prbar1 {
     }
 }
 
-impl crate::register::SysRegWrite for Prbar1 {}
+impl SysRegWrite for Prbar1 {}
 
 impl Prbar1 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/prbar10.rs b/aarch32-cpu/src/register/armv8r/prbar10.rs
index 7f606a68..cf823905 100644
--- a/aarch32-cpu/src/register/armv8r/prbar10.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar10.rs
@@ -16,7 +16,7 @@ impl SysReg for Prbar10 {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for Prbar10 {}
+impl SysRegRead for Prbar10 {}
 
 impl Prbar10 {
     #[inline]
@@ -26,7 +26,7 @@ impl Prbar10 {
     }
 }
 
-impl crate::register::SysRegWrite for Prbar10 {}
+impl SysRegWrite for Prbar10 {}
 
 impl Prbar10 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/prbar11.rs b/aarch32-cpu/src/register/armv8r/prbar11.rs
index e919e7dc..19ce066a 100644
--- a/aarch32-cpu/src/register/armv8r/prbar11.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar11.rs
@@ -16,7 +16,7 @@ impl SysReg for Prbar11 {
     const OP2: u32 = 4;
 }
 
-impl crate::register::SysRegRead for Prbar11 {}
+impl SysRegRead for Prbar11 {}
 
 impl Prbar11 {
     #[inline]
@@ -26,7 +26,7 @@ impl Prbar11 {
     }
 }
 
-impl crate::register::SysRegWrite for Prbar11 {}
+impl SysRegWrite for Prbar11 {}
 
 impl Prbar11 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/prbar12.rs b/aarch32-cpu/src/register/armv8r/prbar12.rs
index c681d98f..91250133 100644
--- a/aarch32-cpu/src/register/armv8r/prbar12.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar12.rs
@@ -16,7 +16,7 @@ impl SysReg for Prbar12 {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for Prbar12 {}
+impl SysRegRead for Prbar12 {}
 
 impl Prbar12 {
     #[inline]
@@ -26,7 +26,7 @@ impl Prbar12 {
     }
 }
 
-impl crate::register::SysRegWrite for Prbar12 {}
+impl SysRegWrite for Prbar12 {}
 
 impl Prbar12 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/prbar13.rs b/aarch32-cpu/src/register/armv8r/prbar13.rs
index 586b0b1c..981f70f5 100644
--- a/aarch32-cpu/src/register/armv8r/prbar13.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar13.rs
@@ -16,7 +16,7 @@ impl SysReg for Prbar13 {
     const OP2: u32 = 4;
 }
 
-impl crate::register::SysRegRead for Prbar13 {}
+impl SysRegRead for Prbar13 {}
 
 impl Prbar13 {
     #[inline]
@@ -26,7 +26,7 @@ impl Prbar13 {
     }
 }
 
-impl crate::register::SysRegWrite for Prbar13 {}
+impl SysRegWrite for Prbar13 {}
 
 impl Prbar13 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/prbar14.rs b/aarch32-cpu/src/register/armv8r/prbar14.rs
index 23a82437..b87fe0a2 100644
--- a/aarch32-cpu/src/register/armv8r/prbar14.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar14.rs
@@ -16,7 +16,7 @@ impl SysReg for Prbar14 {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for Prbar14 {}
+impl SysRegRead for Prbar14 {}
 
 impl Prbar14 {
     #[inline]
@@ -26,7 +26,7 @@ impl Prbar14 {
     }
 }
 
-impl crate::register::SysRegWrite for Prbar14 {}
+impl SysRegWrite for Prbar14 {}
 
 impl Prbar14 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/prbar15.rs b/aarch32-cpu/src/register/armv8r/prbar15.rs
index 59b67daf..8efbe349 100644
--- a/aarch32-cpu/src/register/armv8r/prbar15.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar15.rs
@@ -16,7 +16,7 @@ impl SysReg for Prbar15 {
     const OP2: u32 = 4;
 }
 
-impl crate::register::SysRegRead for Prbar15 {}
+impl SysRegRead for Prbar15 {}
 
 impl Prbar15 {
     #[inline]
@@ -26,7 +26,7 @@ impl Prbar15 {
     }
 }
 
-impl crate::register::SysRegWrite for Prbar15 {}
+impl SysRegWrite for Prbar15 {}
 
 impl Prbar15 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/prbar2.rs b/aarch32-cpu/src/register/armv8r/prbar2.rs
index bf4139af..102577ca 100644
--- a/aarch32-cpu/src/register/armv8r/prbar2.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar2.rs
@@ -16,7 +16,7 @@ impl SysReg for Prbar2 {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for Prbar2 {}
+impl SysRegRead for Prbar2 {}
 
 impl Prbar2 {
     #[inline]
@@ -26,7 +26,7 @@ impl Prbar2 {
     }
 }
 
-impl crate::register::SysRegWrite for Prbar2 {}
+impl SysRegWrite for Prbar2 {}
 
 impl Prbar2 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/prbar3.rs b/aarch32-cpu/src/register/armv8r/prbar3.rs
index faa2c27c..8fc3a066 100644
--- a/aarch32-cpu/src/register/armv8r/prbar3.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar3.rs
@@ -16,7 +16,7 @@ impl SysReg for Prbar3 {
     const OP2: u32 = 4;
 }
 
-impl crate::register::SysRegRead for Prbar3 {}
+impl SysRegRead for Prbar3 {}
 
 impl Prbar3 {
     #[inline]
@@ -26,7 +26,7 @@ impl Prbar3 {
     }
 }
 
-impl crate::register::SysRegWrite for Prbar3 {}
+impl SysRegWrite for Prbar3 {}
 
 impl Prbar3 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/prbar4.rs b/aarch32-cpu/src/register/armv8r/prbar4.rs
index d854d8f0..256d2eac 100644
--- a/aarch32-cpu/src/register/armv8r/prbar4.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar4.rs
@@ -16,7 +16,7 @@ impl SysReg for Prbar4 {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for Prbar4 {}
+impl SysRegRead for Prbar4 {}
 
 impl Prbar4 {
     #[inline]
@@ -26,7 +26,7 @@ impl Prbar4 {
     }
 }
 
-impl crate::register::SysRegWrite for Prbar4 {}
+impl SysRegWrite for Prbar4 {}
 
 impl Prbar4 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/prbar5.rs b/aarch32-cpu/src/register/armv8r/prbar5.rs
index ea498520..bbd1714e 100644
--- a/aarch32-cpu/src/register/armv8r/prbar5.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar5.rs
@@ -16,7 +16,7 @@ impl SysReg for Prbar5 {
     const OP2: u32 = 4;
 }
 
-impl crate::register::SysRegRead for Prbar5 {}
+impl SysRegRead for Prbar5 {}
 
 impl Prbar5 {
     #[inline]
@@ -26,7 +26,7 @@ impl Prbar5 {
     }
 }
 
-impl crate::register::SysRegWrite for Prbar5 {}
+impl SysRegWrite for Prbar5 {}
 
 impl Prbar5 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/prbar6.rs b/aarch32-cpu/src/register/armv8r/prbar6.rs
index 52ceb526..d8149b30 100644
--- a/aarch32-cpu/src/register/armv8r/prbar6.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar6.rs
@@ -16,7 +16,7 @@ impl SysReg for Prbar6 {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for Prbar6 {}
+impl SysRegRead for Prbar6 {}
 
 impl Prbar6 {
     #[inline]
@@ -26,7 +26,7 @@ impl Prbar6 {
     }
 }
 
-impl crate::register::SysRegWrite for Prbar6 {}
+impl SysRegWrite for Prbar6 {}
 
 impl Prbar6 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/prbar7.rs b/aarch32-cpu/src/register/armv8r/prbar7.rs
index 27db0d5a..a95d3e0c 100644
--- a/aarch32-cpu/src/register/armv8r/prbar7.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar7.rs
@@ -16,7 +16,7 @@ impl SysReg for Prbar7 {
     const OP2: u32 = 4;
 }
 
-impl crate::register::SysRegRead for Prbar7 {}
+impl SysRegRead for Prbar7 {}
 
 impl Prbar7 {
     #[inline]
@@ -26,7 +26,7 @@ impl Prbar7 {
     }
 }
 
-impl crate::register::SysRegWrite for Prbar7 {}
+impl SysRegWrite for Prbar7 {}
 
 impl Prbar7 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/prbar8.rs b/aarch32-cpu/src/register/armv8r/prbar8.rs
index 46bd9659..479720e1 100644
--- a/aarch32-cpu/src/register/armv8r/prbar8.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar8.rs
@@ -16,7 +16,7 @@ impl SysReg for Prbar8 {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for Prbar8 {}
+impl SysRegRead for Prbar8 {}
 
 impl Prbar8 {
     #[inline]
@@ -26,7 +26,7 @@ impl Prbar8 {
     }
 }
 
-impl crate::register::SysRegWrite for Prbar8 {}
+impl SysRegWrite for Prbar8 {}
 
 impl Prbar8 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/prbar9.rs b/aarch32-cpu/src/register/armv8r/prbar9.rs
index eabe9861..f39e605c 100644
--- a/aarch32-cpu/src/register/armv8r/prbar9.rs
+++ b/aarch32-cpu/src/register/armv8r/prbar9.rs
@@ -16,7 +16,7 @@ impl SysReg for Prbar9 {
     const OP2: u32 = 4;
 }
 
-impl crate::register::SysRegRead for Prbar9 {}
+impl SysRegRead for Prbar9 {}
 
 impl Prbar9 {
     #[inline]
@@ -26,7 +26,7 @@ impl Prbar9 {
     }
 }
 
-impl crate::register::SysRegWrite for Prbar9 {}
+impl SysRegWrite for Prbar9 {}
 
 impl Prbar9 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/prlar.rs b/aarch32-cpu/src/register/armv8r/prlar.rs
index 6285fefd..8b78c367 100644
--- a/aarch32-cpu/src/register/armv8r/prlar.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar.rs
@@ -1,6 +1,6 @@
 //! Code for managing PRLAR (*Protection Region Limit Address Register*)
 
-use arbitrary_int::{traits::Integer, u26, u3};
+use arbitrary_int::{traits::Integer, u3, u26};
 
 use crate::register::{SysReg, SysRegRead, SysRegWrite};
 
@@ -26,17 +26,18 @@ impl SysReg for Prlar {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for Prlar {}
+impl SysRegRead for Prlar {}
 
 impl Prlar {
     #[inline]
     /// Reads PRLAR (*Protection Region Limit Address Register*)
     pub fn read() -> Prlar {
+        // Safety: it's OK to set bits with no accessors specified
         unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
     }
 }
 
-impl crate::register::SysRegWrite for Prlar {}
+impl SysRegWrite for Prlar {}
 
 impl Prlar {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/prlar0.rs b/aarch32-cpu/src/register/armv8r/prlar0.rs
index 48c3a4e6..6bc96dc5 100644
--- a/aarch32-cpu/src/register/armv8r/prlar0.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar0.rs
@@ -16,7 +16,7 @@ impl SysReg for Prlar0 {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for Prlar0 {}
+impl SysRegRead for Prlar0 {}
 
 impl Prlar0 {
     #[inline]
@@ -26,7 +26,7 @@ impl Prlar0 {
     }
 }
 
-impl crate::register::SysRegWrite for Prlar0 {}
+impl SysRegWrite for Prlar0 {}
 
 impl Prlar0 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/prlar1.rs b/aarch32-cpu/src/register/armv8r/prlar1.rs
index 09ef217b..f27f78b2 100644
--- a/aarch32-cpu/src/register/armv8r/prlar1.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar1.rs
@@ -16,7 +16,7 @@ impl SysReg for Prlar1 {
     const OP2: u32 = 5;
 }
 
-impl crate::register::SysRegRead for Prlar1 {}
+impl SysRegRead for Prlar1 {}
 
 impl Prlar1 {
     #[inline]
@@ -26,7 +26,7 @@ impl Prlar1 {
     }
 }
 
-impl crate::register::SysRegWrite for Prlar1 {}
+impl SysRegWrite for Prlar1 {}
 
 impl Prlar1 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/prlar10.rs b/aarch32-cpu/src/register/armv8r/prlar10.rs
index ea3e10ca..300a8a4f 100644
--- a/aarch32-cpu/src/register/armv8r/prlar10.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar10.rs
@@ -16,7 +16,7 @@ impl SysReg for Prlar10 {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for Prlar10 {}
+impl SysRegRead for Prlar10 {}
 
 impl Prlar10 {
     #[inline]
@@ -26,7 +26,7 @@ impl Prlar10 {
     }
 }
 
-impl crate::register::SysRegWrite for Prlar10 {}
+impl SysRegWrite for Prlar10 {}
 
 impl Prlar10 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/prlar11.rs b/aarch32-cpu/src/register/armv8r/prlar11.rs
index 0be023a0..4fa837fd 100644
--- a/aarch32-cpu/src/register/armv8r/prlar11.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar11.rs
@@ -16,7 +16,7 @@ impl SysReg for Prlar11 {
     const OP2: u32 = 5;
 }
 
-impl crate::register::SysRegRead for Prlar11 {}
+impl SysRegRead for Prlar11 {}
 
 impl Prlar11 {
     #[inline]
@@ -26,7 +26,7 @@ impl Prlar11 {
     }
 }
 
-impl crate::register::SysRegWrite for Prlar11 {}
+impl SysRegWrite for Prlar11 {}
 
 impl Prlar11 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/prlar12.rs b/aarch32-cpu/src/register/armv8r/prlar12.rs
index 69150ce4..1b6b4b08 100644
--- a/aarch32-cpu/src/register/armv8r/prlar12.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar12.rs
@@ -16,7 +16,7 @@ impl SysReg for Prlar12 {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for Prlar12 {}
+impl SysRegRead for Prlar12 {}
 
 impl Prlar12 {
     #[inline]
@@ -26,7 +26,7 @@ impl Prlar12 {
     }
 }
 
-impl crate::register::SysRegWrite for Prlar12 {}
+impl SysRegWrite for Prlar12 {}
 
 impl Prlar12 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/prlar13.rs b/aarch32-cpu/src/register/armv8r/prlar13.rs
index 19e96389..ac415e2c 100644
--- a/aarch32-cpu/src/register/armv8r/prlar13.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar13.rs
@@ -16,7 +16,7 @@ impl SysReg for Prlar13 {
     const OP2: u32 = 5;
 }
 
-impl crate::register::SysRegRead for Prlar13 {}
+impl SysRegRead for Prlar13 {}
 
 impl Prlar13 {
     #[inline]
@@ -26,7 +26,7 @@ impl Prlar13 {
     }
 }
 
-impl crate::register::SysRegWrite for Prlar13 {}
+impl SysRegWrite for Prlar13 {}
 
 impl Prlar13 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/prlar14.rs b/aarch32-cpu/src/register/armv8r/prlar14.rs
index a75497df..4d283f7f 100644
--- a/aarch32-cpu/src/register/armv8r/prlar14.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar14.rs
@@ -16,7 +16,7 @@ impl SysReg for Prlar14 {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for Prlar14 {}
+impl SysRegRead for Prlar14 {}
 
 impl Prlar14 {
     #[inline]
@@ -26,7 +26,7 @@ impl Prlar14 {
     }
 }
 
-impl crate::register::SysRegWrite for Prlar14 {}
+impl SysRegWrite for Prlar14 {}
 
 impl Prlar14 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/prlar15.rs b/aarch32-cpu/src/register/armv8r/prlar15.rs
index f0b2267c..7eafc3ba 100644
--- a/aarch32-cpu/src/register/armv8r/prlar15.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar15.rs
@@ -16,7 +16,7 @@ impl SysReg for Prlar15 {
     const OP2: u32 = 5;
 }
 
-impl crate::register::SysRegRead for Prlar15 {}
+impl SysRegRead for Prlar15 {}
 
 impl Prlar15 {
     #[inline]
@@ -26,7 +26,7 @@ impl Prlar15 {
     }
 }
 
-impl crate::register::SysRegWrite for Prlar15 {}
+impl SysRegWrite for Prlar15 {}
 
 impl Prlar15 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/prlar2.rs b/aarch32-cpu/src/register/armv8r/prlar2.rs
index 625199b2..83f44759 100644
--- a/aarch32-cpu/src/register/armv8r/prlar2.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar2.rs
@@ -16,7 +16,7 @@ impl SysReg for Prlar2 {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for Prlar2 {}
+impl SysRegRead for Prlar2 {}
 
 impl Prlar2 {
     #[inline]
@@ -26,7 +26,7 @@ impl Prlar2 {
     }
 }
 
-impl crate::register::SysRegWrite for Prlar2 {}
+impl SysRegWrite for Prlar2 {}
 
 impl Prlar2 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/prlar3.rs b/aarch32-cpu/src/register/armv8r/prlar3.rs
index 2276b859..5f726851 100644
--- a/aarch32-cpu/src/register/armv8r/prlar3.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar3.rs
@@ -16,7 +16,7 @@ impl SysReg for Prlar3 {
     const OP2: u32 = 5;
 }
 
-impl crate::register::SysRegRead for Prlar3 {}
+impl SysRegRead for Prlar3 {}
 
 impl Prlar3 {
     #[inline]
@@ -26,7 +26,7 @@ impl Prlar3 {
     }
 }
 
-impl crate::register::SysRegWrite for Prlar3 {}
+impl SysRegWrite for Prlar3 {}
 
 impl Prlar3 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/prlar4.rs b/aarch32-cpu/src/register/armv8r/prlar4.rs
index 86d5fd52..8fc5771e 100644
--- a/aarch32-cpu/src/register/armv8r/prlar4.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar4.rs
@@ -16,7 +16,7 @@ impl SysReg for Prlar4 {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for Prlar4 {}
+impl SysRegRead for Prlar4 {}
 
 impl Prlar4 {
     #[inline]
@@ -26,7 +26,7 @@ impl Prlar4 {
     }
 }
 
-impl crate::register::SysRegWrite for Prlar4 {}
+impl SysRegWrite for Prlar4 {}
 
 impl Prlar4 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/prlar5.rs b/aarch32-cpu/src/register/armv8r/prlar5.rs
index 65f55ae4..387c7ee3 100644
--- a/aarch32-cpu/src/register/armv8r/prlar5.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar5.rs
@@ -16,7 +16,7 @@ impl SysReg for Prlar5 {
     const OP2: u32 = 5;
 }
 
-impl crate::register::SysRegRead for Prlar5 {}
+impl SysRegRead for Prlar5 {}
 
 impl Prlar5 {
     #[inline]
@@ -26,7 +26,7 @@ impl Prlar5 {
     }
 }
 
-impl crate::register::SysRegWrite for Prlar5 {}
+impl SysRegWrite for Prlar5 {}
 
 impl Prlar5 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/prlar6.rs b/aarch32-cpu/src/register/armv8r/prlar6.rs
index 2882ba6f..9b6e5d96 100644
--- a/aarch32-cpu/src/register/armv8r/prlar6.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar6.rs
@@ -16,7 +16,7 @@ impl SysReg for Prlar6 {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for Prlar6 {}
+impl SysRegRead for Prlar6 {}
 
 impl Prlar6 {
     #[inline]
@@ -26,7 +26,7 @@ impl Prlar6 {
     }
 }
 
-impl crate::register::SysRegWrite for Prlar6 {}
+impl SysRegWrite for Prlar6 {}
 
 impl Prlar6 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/prlar7.rs b/aarch32-cpu/src/register/armv8r/prlar7.rs
index f0c82252..f01c53a2 100644
--- a/aarch32-cpu/src/register/armv8r/prlar7.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar7.rs
@@ -16,7 +16,7 @@ impl SysReg for Prlar7 {
     const OP2: u32 = 5;
 }
 
-impl crate::register::SysRegRead for Prlar7 {}
+impl SysRegRead for Prlar7 {}
 
 impl Prlar7 {
     #[inline]
@@ -26,7 +26,7 @@ impl Prlar7 {
     }
 }
 
-impl crate::register::SysRegWrite for Prlar7 {}
+impl SysRegWrite for Prlar7 {}
 
 impl Prlar7 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/prlar8.rs b/aarch32-cpu/src/register/armv8r/prlar8.rs
index d488cf3d..429e5e9d 100644
--- a/aarch32-cpu/src/register/armv8r/prlar8.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar8.rs
@@ -16,7 +16,7 @@ impl SysReg for Prlar8 {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for Prlar8 {}
+impl SysRegRead for Prlar8 {}
 
 impl Prlar8 {
     #[inline]
@@ -26,7 +26,7 @@ impl Prlar8 {
     }
 }
 
-impl crate::register::SysRegWrite for Prlar8 {}
+impl SysRegWrite for Prlar8 {}
 
 impl Prlar8 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/prlar9.rs b/aarch32-cpu/src/register/armv8r/prlar9.rs
index ad1e0eb7..5d986ab1 100644
--- a/aarch32-cpu/src/register/armv8r/prlar9.rs
+++ b/aarch32-cpu/src/register/armv8r/prlar9.rs
@@ -16,7 +16,7 @@ impl SysReg for Prlar9 {
     const OP2: u32 = 5;
 }
 
-impl crate::register::SysRegRead for Prlar9 {}
+impl SysRegRead for Prlar9 {}
 
 impl Prlar9 {
     #[inline]
@@ -26,7 +26,7 @@ impl Prlar9 {
     }
 }
 
-impl crate::register::SysRegWrite for Prlar9 {}
+impl SysRegWrite for Prlar9 {}
 
 impl Prlar9 {
     #[inline]
diff --git a/aarch32-cpu/src/register/armv8r/prselr.rs b/aarch32-cpu/src/register/armv8r/prselr.rs
index 01f3e6c0..9f0cdc14 100644
--- a/aarch32-cpu/src/register/armv8r/prselr.rs
+++ b/aarch32-cpu/src/register/armv8r/prselr.rs
@@ -16,7 +16,7 @@ impl SysReg for Prselr {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for Prselr {}
+impl SysRegRead for Prselr {}
 
 impl Prselr {
     #[inline]
@@ -26,7 +26,7 @@ impl Prselr {
     }
 }
 
-impl crate::register::SysRegWrite for Prselr {}
+impl SysRegWrite for Prselr {}
 
 impl Prselr {
     #[inline]
diff --git a/aarch32-cpu/src/register/bpiall.rs b/aarch32-cpu/src/register/bpiall.rs
index 7f0ce864..f69d50f9 100644
--- a/aarch32-cpu/src/register/bpiall.rs
+++ b/aarch32-cpu/src/register/bpiall.rs
@@ -1,6 +1,6 @@
 //! Code for managing BPIALL (*Branch Predictor Invalidate All*)
 
-use crate::register::SysReg;
+use crate::register::{SysReg, SysRegWrite};
 
 /// BPIALL (*Branch Predictor Invalidate All*)
 pub struct BpIAll;
@@ -13,11 +13,12 @@ impl SysReg for BpIAll {
     const OP2: u32 = 6;
 }
 
-impl crate::register::SysRegWrite for BpIAll {}
+impl SysRegWrite for BpIAll {}
 
 impl BpIAll {
     #[inline]
+    /// Writes 0 to BPIALL (*Branch Predictor Invalidate All*) to trigger operation
     pub fn write() {
-        unsafe { <Self as crate::register::SysRegWrite>::write_raw(0) }
+        unsafe { <Self as SysRegWrite>::write_raw(0) }
     }
 }
diff --git a/aarch32-cpu/src/register/ccsidr.rs b/aarch32-cpu/src/register/ccsidr.rs
index f9955761..df8cb1b2 100644
--- a/aarch32-cpu/src/register/ccsidr.rs
+++ b/aarch32-cpu/src/register/ccsidr.rs
@@ -1,24 +1,31 @@
 //! Code for managing CCSIDR (*Current Cache Size ID Register*)
 
 use crate::register::{SysReg, SysRegRead};
-use arbitrary_int::{u10, u15, u3};
+use arbitrary_int::{u3, u10, u15};
 
 /// CCSIDR (*Current Cache Size ID Register*)
 #[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Ccsidr {
+    /// Indicates whether the cache level supports Write-Through
     #[bit(31, rw)]
     write_through: bool,
+    /// Indicates whether the cache level supports Write-Back
     #[bit(30, rw)]
     write_back: bool,
+    /// Indicates whether the cache level supports Read-Allocation
     #[bit(29, rw)]
     read_alloc: bool,
+    /// Indicates whether the cache level supports Write-Allocation
     #[bit(28, rw)]
     write_alloc: bool,
+    /// Number of sets in cache, minus 1
     #[bits(13..=27, rw)]
     num_sets: u15,
+    /// Associativity of cache, minus 1
     #[bits(3..=12, rw)]
     associativity: u10,
+    /// log2(cache line size in words), minus 1
     #[bits(0..=2, rw)]
     line_size: u3,
 }
@@ -31,12 +38,13 @@ impl SysReg for Ccsidr {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for Ccsidr {}
+impl SysRegRead for Ccsidr {}
 
 impl Ccsidr {
     #[inline]
     /// Reads CCSIDR (*Current Cache Size ID Register*)
     pub fn read() -> Ccsidr {
+        // Safety: it's OK to set bits with no accessors specified
         unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
     }
 }
diff --git a/aarch32-cpu/src/register/clidr.rs b/aarch32-cpu/src/register/clidr.rs
index 25b78031..99818fde 100644
--- a/aarch32-cpu/src/register/clidr.rs
+++ b/aarch32-cpu/src/register/clidr.rs
@@ -16,7 +16,7 @@ impl SysReg for Clidr {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for Clidr {}
+impl SysRegRead for Clidr {}
 
 impl Clidr {
     #[inline]
diff --git a/aarch32-cpu/src/register/contextidr.rs b/aarch32-cpu/src/register/contextidr.rs
index 9c503fec..e869dcc6 100644
--- a/aarch32-cpu/src/register/contextidr.rs
+++ b/aarch32-cpu/src/register/contextidr.rs
@@ -16,7 +16,7 @@ impl SysReg for Contextidr {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for Contextidr {}
+impl SysRegRead for Contextidr {}
 
 impl Contextidr {
     #[inline]
@@ -26,7 +26,7 @@ impl Contextidr {
     }
 }
 
-impl crate::register::SysRegWrite for Contextidr {}
+impl SysRegWrite for Contextidr {}
 
 impl Contextidr {
     #[inline]
diff --git a/aarch32-cpu/src/register/cpacr.rs b/aarch32-cpu/src/register/cpacr.rs
index 29a5c553..17690e3d 100644
--- a/aarch32-cpu/src/register/cpacr.rs
+++ b/aarch32-cpu/src/register/cpacr.rs
@@ -16,7 +16,7 @@ impl SysReg for Cpacr {
     const OP2: u32 = 2;
 }
 
-impl crate::register::SysRegRead for Cpacr {}
+impl SysRegRead for Cpacr {}
 
 impl Cpacr {
     #[inline]
@@ -26,7 +26,7 @@ impl Cpacr {
     }
 }
 
-impl crate::register::SysRegWrite for Cpacr {}
+impl SysRegWrite for Cpacr {}
 
 impl Cpacr {
     #[inline]
diff --git a/aarch32-cpu/src/register/cpsr.rs b/aarch32-cpu/src/register/cpsr.rs
index 718f0e35..8064a709 100644
--- a/aarch32-cpu/src/register/cpsr.rs
+++ b/aarch32-cpu/src/register/cpsr.rs
@@ -168,7 +168,11 @@ impl core::fmt::Debug for Cpsr {
 
 #[cfg(feature = "defmt")]
 impl defmt::Format for Cpsr {
-    fn format(&self, f: defmt::Formatter) {
-        defmt::write!(f, "CPSR {{ N={0=31..32} Z={0=30..31} C={0=29..30} V={0=28..29} Q={0=27..28} J={0=24..25} E={0=9..10} A={0=8..9} I={0=7..8} F={0=6..7} T={0=5..6} MODE={0=0..5} }}", self.raw_value())
+    fn format(&self, f: defmt::Formatter<'_>) {
+        defmt::write!(
+            f,
+            "CPSR {{ N={0=31..32} Z={0=30..31} C={0=29..30} V={0=28..29} Q={0=27..28} J={0=24..25} E={0=9..10} A={0=8..9} I={0=7..8} F={0=6..7} T={0=5..6} MODE={0=0..5} }}",
+            self.raw_value()
+        )
     }
 }
diff --git a/aarch32-cpu/src/register/csselr.rs b/aarch32-cpu/src/register/csselr.rs
index eed48318..694520af 100644
--- a/aarch32-cpu/src/register/csselr.rs
+++ b/aarch32-cpu/src/register/csselr.rs
@@ -7,8 +7,11 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[derive(Debug, PartialEq, Eq)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
+/// Type of processor cache
 pub enum CacheType {
+    /// Data or Unified Cache
     DataOrUnified = 0,
+    /// Instruction Cache
     Instruction = 1,
 }
 
@@ -20,6 +23,7 @@ pub struct Csselr {
     /// 0 for L1 cache, 1 for L2, etc.
     #[bits(1..=3, rw)]
     level: u3,
+    /// The type of cache
     #[bit(0, rw)]
     cache_type: CacheType,
 }
@@ -32,17 +36,18 @@ impl SysReg for Csselr {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for Csselr {}
+impl SysRegRead for Csselr {}
 
 impl Csselr {
     #[inline]
     /// Reads CSSELR (*Cache Size Selection Register*)
     pub fn read() -> Csselr {
+        // Safety: it's OK to set bits with no accessors specified
         unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
     }
 }
 
-impl crate::register::SysRegWrite for Csselr {}
+impl SysRegWrite for Csselr {}
 
 impl Csselr {
     #[inline]
diff --git a/aarch32-cpu/src/register/ctr.rs b/aarch32-cpu/src/register/ctr.rs
index 14b9c1bf..624ed1bb 100644
--- a/aarch32-cpu/src/register/ctr.rs
+++ b/aarch32-cpu/src/register/ctr.rs
@@ -16,7 +16,7 @@ impl SysReg for Ctr {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for Ctr {}
+impl SysRegRead for Ctr {}
 
 impl Ctr {
     #[inline]
diff --git a/aarch32-cpu/src/register/dacr.rs b/aarch32-cpu/src/register/dacr.rs
index 1c52743e..5fde5284 100644
--- a/aarch32-cpu/src/register/dacr.rs
+++ b/aarch32-cpu/src/register/dacr.rs
@@ -6,6 +6,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Dacr {
+    /// An array of bits controlling access to each of the 16 domains
     #[bits(0..=1, rw)]
     d: [DomainAccess; 16],
 }
@@ -34,17 +35,18 @@ impl SysReg for Dacr {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for Dacr {}
+impl SysRegRead for Dacr {}
 
 impl Dacr {
     #[inline]
     /// Reads DACR (*Domain Access Control Register*)
     pub fn read() -> Dacr {
+        // Safety: it's OK to set bits with no accessors specified
         unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
     }
 }
 
-impl crate::register::SysRegWrite for Dacr {}
+impl SysRegWrite for Dacr {}
 
 impl Dacr {
     #[inline]
diff --git a/aarch32-cpu/src/register/dccimvac.rs b/aarch32-cpu/src/register/dccimvac.rs
index 9cd5f18e..035f2d62 100644
--- a/aarch32-cpu/src/register/dccimvac.rs
+++ b/aarch32-cpu/src/register/dccimvac.rs
@@ -1,7 +1,8 @@
-//! Code for managing DCCIMVAC (*Clean And Invalidate Data Cache Or Unified Cache Line by MVA to Point of Coherence.*)
+//! Code for managing DCCIMVAC (*Data Cache line Clean and Invalidate by VA to PoC Register*)
 
 use crate::register::{SysReg, SysRegWrite};
 
+/// DCCIMVAC (*Data Cache line Clean and Invalidate by VA to PoC Register*)
 #[derive(Debug, Copy, Clone)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
@@ -9,6 +10,7 @@ pub struct Dccimvac(pub u32);
 
 impl Dccimvac {
     #[inline]
+    /// Create a new DCCIMVAC containing the address to clean and invalidate
     pub const fn new(addr: u32) -> Self {
         Self(addr)
     }
@@ -22,11 +24,11 @@ impl SysReg for Dccimvac {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegWrite for Dccimvac {}
+impl SysRegWrite for Dccimvac {}
 
 impl Dccimvac {
     #[inline]
-    /// Writes DCCIMVAC (*Clean And Invalidate Data Cache Or Unified Cache Line by MVA to Point of Coherence.*)
+    /// Writes DCCIMVAC (*Data Cache line Clean and Invalidate by VA to PoC Register*)
     ///
     /// # Safety
     ///
diff --git a/aarch32-cpu/src/register/dccisw.rs b/aarch32-cpu/src/register/dccisw.rs
index e8152f24..fb65fda4 100644
--- a/aarch32-cpu/src/register/dccisw.rs
+++ b/aarch32-cpu/src/register/dccisw.rs
@@ -1,4 +1,4 @@
-//! Code for managing DCCISW (*Clean and Invalidate Data or Unified cache line by Set/Way.*)
+//! Code for managing DCCISW (*Data Cache line Clean and Invalidate by Set/Way Register*)
 
 use arbitrary_int::u3;
 
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegWrite};
 #[derive(Debug, Copy, Clone)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
+/// DCCISW (*Data Cache line Clean and Invalidate by Set/Way Register*)
 pub struct Dccisw(pub u32);
 
 impl Dccisw {
@@ -48,11 +49,11 @@ impl SysReg for Dccisw {
     const OP2: u32 = 2;
 }
 
-impl crate::register::SysRegWrite for Dccisw {}
+impl SysRegWrite for Dccisw {}
 
 impl Dccisw {
     #[inline]
-    /// Writes DCCISW (*Clean and Invalidate data or unified cache line by set/way.*)
+    /// Writes DCCISW (*Data Cache line Clean and Invalidate by Set/Way Register*)
     ///
     /// # Safety
     ///
diff --git a/aarch32-cpu/src/register/dccmvac.rs b/aarch32-cpu/src/register/dccmvac.rs
index abf7ad27..764d9964 100644
--- a/aarch32-cpu/src/register/dccmvac.rs
+++ b/aarch32-cpu/src/register/dccmvac.rs
@@ -1,14 +1,16 @@
-//! Code for managing DCCMVAC (*Clean Data Cache Or Unified Cache Line by MVA to Point of Coherence.*)
+//! Code for managing DCCMVAC (*Data Cache line Clean by VA to PoC Register*)
 
 use crate::register::{SysReg, SysRegWrite};
 
 #[derive(Debug, Copy, Clone)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
+/// DCCMVAC (*Data Cache line Clean by VA to PoC Register*)
 pub struct Dccmvac(pub u32);
 
 impl Dccmvac {
     #[inline]
+    /// Create a new DCCMVAC containing the Virtual Address to clean
     pub const fn new(addr: u32) -> Self {
         Self(addr)
     }
@@ -22,11 +24,11 @@ impl SysReg for Dccmvac {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegWrite for Dccmvac {}
+impl SysRegWrite for Dccmvac {}
 
 impl Dccmvac {
     #[inline]
-    /// Writes DCCMVAC (*Clean Data Cache Or Unified Cache Line by MVA to Point of Coherence.*)
+    /// Writes DCCMVAC (*Data Cache line Clean by VA to PoC Register*)
     ///
     /// # Safety
     ///
diff --git a/aarch32-cpu/src/register/dccmvau.rs b/aarch32-cpu/src/register/dccmvau.rs
index 98fdc70e..5e82ab26 100644
--- a/aarch32-cpu/src/register/dccmvau.rs
+++ b/aarch32-cpu/src/register/dccmvau.rs
@@ -1,14 +1,16 @@
-//! Code for managing DCCMVAU (*Clean Data Cache Or Unified Cache Line by MVA to Point of Unification.*)
+//! Code for managing DCCMVAU (*Data Cache line Clean by VA to PoU Register*)
 
 use crate::register::{SysReg, SysRegWrite};
 
 #[derive(Debug, Copy, Clone)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
+/// DCCMVAU (*Data Cache line Clean by VA to PoU Register*)
 pub struct Dccmvau(pub u32);
 
 impl Dccmvau {
     #[inline]
+    /// Create a new DCCMVAU value containing the Virtual Address to clean
     pub const fn new(addr: u32) -> Self {
         Self(addr)
     }
@@ -22,11 +24,11 @@ impl SysReg for Dccmvau {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegWrite for Dccmvau {}
+impl SysRegWrite for Dccmvau {}
 
 impl Dccmvau {
     #[inline]
-    /// Writes DCCMVAU (*Clean Data Cache Or Unified Cache Line by MVA to Point of Unification.*)
+    /// Writes DCCMVAU (*Data Cache line Clean by VA to PoU Register*)
     ///
     /// # Safety
     ///
diff --git a/aarch32-cpu/src/register/dccsw.rs b/aarch32-cpu/src/register/dccsw.rs
index 77f58b9e..998b616f 100644
--- a/aarch32-cpu/src/register/dccsw.rs
+++ b/aarch32-cpu/src/register/dccsw.rs
@@ -1,4 +1,4 @@
-//! Code for managing DCCSW (*Clean Data or Unified Cache line by Set/Way.*)
+//! Code for managing DCCSW (*Data Cache line Clean by Set/Way Register*)
 
 use arbitrary_int::u3;
 
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegWrite};
 #[derive(Debug, Copy, Clone)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
+/// DCCSW (*Data Cache line Clean by Set/Way Register*)
 pub struct Dccsw(pub u32);
 
 impl Dccsw {
@@ -48,11 +49,11 @@ impl SysReg for Dccsw {
     const OP2: u32 = 2;
 }
 
-impl crate::register::SysRegWrite for Dccsw {}
+impl SysRegWrite for Dccsw {}
 
 impl Dccsw {
     #[inline]
-    /// Writes DCCSW (*Clean Data or Unified Cache line by Set/Way.*)
+    /// Writes DCCSW (*Data Cache line Clean by Set/Way Register*)
     ///
     /// # Safety
     ///
diff --git a/aarch32-cpu/src/register/dcimvac.rs b/aarch32-cpu/src/register/dcimvac.rs
index 9848585a..020e39c8 100644
--- a/aarch32-cpu/src/register/dcimvac.rs
+++ b/aarch32-cpu/src/register/dcimvac.rs
@@ -1,14 +1,16 @@
-//! Code for managing DCIMVAC (*Invalidate Data Cache Or Unified Cache Line by MVA to Point of Coherence.*)
+//! Code for managing DCIMVAC (*Data Cache line Invalidate by VA to PoC Register*)
 
 use crate::register::{SysReg, SysRegWrite};
 
 #[derive(Debug, Copy, Clone)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
+/// DCIMVAC (*Data Cache line Invalidate by VA to PoC Register*)
 pub struct Dcimvac(pub u32);
 
 impl Dcimvac {
     #[inline]
+    /// Create a new DCIMVAC value, given an address
     pub const fn new(addr: u32) -> Self {
         Self(addr)
     }
@@ -22,11 +24,11 @@ impl SysReg for Dcimvac {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegWrite for Dcimvac {}
+impl SysRegWrite for Dcimvac {}
 
 impl Dcimvac {
     #[inline]
-    /// Writes DCIMVAC (*Invalidate Data Cache Or Unified Cache Line by MVA to Point of Coherence.*)
+    /// Writes DCIMVAC (*Data Cache line Invalidate by VA to PoC Register*)
     ///
     /// # Safety
     ///
diff --git a/aarch32-cpu/src/register/dcisw.rs b/aarch32-cpu/src/register/dcisw.rs
index 444b79d4..4a451294 100644
--- a/aarch32-cpu/src/register/dcisw.rs
+++ b/aarch32-cpu/src/register/dcisw.rs
@@ -1,4 +1,4 @@
-//! Code for managing DCISW (*Invalidate Data or Unified Cache line by Set/Way.*)
+//! Code for managing DCISW (*Data Cache line Invalidate by Set/Way Register*)
 
 use arbitrary_int::u3;
 
@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegWrite};
 #[derive(Debug, Copy, Clone)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
+/// DCISW (*Data Cache line Invalidate by Set/Way Register*)
 pub struct Dcisw(pub u32);
 
 impl Dcisw {
@@ -48,11 +49,11 @@ impl SysReg for Dcisw {
     const OP2: u32 = 2;
 }
 
-impl crate::register::SysRegWrite for Dcisw {}
+impl SysRegWrite for Dcisw {}
 
 impl Dcisw {
     #[inline]
-    /// Writes DCSW (*Invalidate Data or Unified Cache line by Set/Way.*)
+    /// Writes DCSW (*Data Cache line Invalidate by Set/Way Register*)
     ///
     /// # Safety
     ///
diff --git a/aarch32-cpu/src/register/dfar.rs b/aarch32-cpu/src/register/dfar.rs
index 7fa38db9..32c08f14 100644
--- a/aarch32-cpu/src/register/dfar.rs
+++ b/aarch32-cpu/src/register/dfar.rs
@@ -16,7 +16,7 @@ impl SysReg for Dfar {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for Dfar {}
+impl SysRegRead for Dfar {}
 
 impl Dfar {
     #[inline]
@@ -26,7 +26,7 @@ impl Dfar {
     }
 }
 
-impl crate::register::SysRegWrite for Dfar {}
+impl SysRegWrite for Dfar {}
 
 impl Dfar {
     #[inline]
diff --git a/aarch32-cpu/src/register/dfsr.rs b/aarch32-cpu/src/register/dfsr.rs
index fe132db2..b46f2ba6 100644
--- a/aarch32-cpu/src/register/dfsr.rs
+++ b/aarch32-cpu/src/register/dfsr.rs
@@ -92,18 +92,31 @@ pub struct Dfsr {
 #[derive(Debug, PartialEq, Eq)]
 #[repr(u8)]
 pub enum DfsrStatus {
+    /// Alignment fault
     AlignmentFault = 1,
+    /// Debug Exception
     Debug = 2,
+    /// Alternate value for Alignment fault
     AlignmentAlt = 3,
+    /// Translation fault, level 1
     TranslationFaultFirstLevel = 5,
+    /// Translation fault, level 2
     TranslationFaultSecondLevel = 7,
+    /// Synchronous External Abort
     SyncExtAbort = 8,
+    /// Domain fault, level 1
     DomainFaultFirstLevel = 9,
+    /// Alternate value for Synchronous External Abort
     SyncExtAbortAlt = 10,
+    /// Domain fault, level 2
     DomainFaultSecondLevel = 11,
+    /// Synchronous External abort, on translation table walk, level 1
     SyncExtAbortOnTranslationTableWalkFirstLevel = 12,
+    /// Permission fault, level 1
     PermissionFaultFirstLevel = 13,
+    /// Synchronous External abort, on translation table walk, level 2
     SyncExtAbortOnTranslationTableWalkSecondLevel = 14,
+    /// Permission fault, level 2
     PermissionFaultSecondLevel = 15,
 }
 
@@ -185,11 +198,11 @@ pub enum DfsrStatus {
     AlignmentFault = 0b00001,
     /// Debug exception.
     Debug = 0b00010,
-    /// Access flag fault, level 1.
+    /// Access flag fault, level 1
     AccessFlagFaultFirstLevel = 0b00011,
     /// Fault on instruction cache maintenance.
     CacheMaintenance = 0b00100,
-    /// Translation fault, level 1.
+    /// Translation fault, level 1
     TranslationFaultFirstLevel = 0b00101,
     /// Access flag fault, level 2.
     AccessFlagFaultSecondLevel = 0b00110,
@@ -197,13 +210,13 @@ pub enum DfsrStatus {
     TranslationFaultSecondLevel = 0b00111,
     /// Synchronous External abort, not on translation table walk.
     SyncExtAbort = 0b01000,
-    /// Domain fault, level 1.
+    /// Domain fault, level 1
     DomainFaultFirstLevel = 0b01001,
     /// Domain fault, level 2.
     DomainFaultSecondLevel = 0b01011,
-    /// Synchronous External abort, on translation table walk, level 1.
+    /// Synchronous External abort, on translation table walk, level 1
     SyncExtAbortOnTranslationTableWalkFirstLevel = 0b01100,
-    /// Permission fault, level 1.
+    /// Permission fault, level 1
     PermissionFaultFirstLevel = 0b01101,
     /// Synchronous External abort, on translation table walk, level 2.
     SyncExtAbortOnTranslationTableWalkSecondLevel = 0b01110,
@@ -217,7 +230,7 @@ pub enum DfsrStatus {
     SErrorParityEccError = 0b11000,
     /// Synchronous parity or ECC error on memory access, not on translation table walk.
     SyncParErrorOnMemAccess = 0b11001,
-    /// Synchronous parity or ECC error on translation table walk, level 1.
+    /// Synchronous parity or ECC error on translation table walk, level 1
     SyncParErrorOnTranslationTableWalkFirstLevel = 0b11100,
     /// Synchronous parity or ECC error on translation table walk, level 2.
     SyncParErrorOnTranslationTableWalkSecondLevel = 0b11110,
@@ -257,17 +270,18 @@ impl SysReg for Dfsr {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for Dfsr {}
+impl SysRegRead for Dfsr {}
 
 impl Dfsr {
     #[inline]
     /// Reads DFSR (*Data Fault Status Register*)
     pub fn read() -> Dfsr {
+        // Safety: it's OK to set bits with no accessors specified
         unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
     }
 }
 
-impl crate::register::SysRegWrite for Dfsr {}
+impl SysRegWrite for Dfsr {}
 
 impl Dfsr {
     #[inline]
diff --git a/aarch32-cpu/src/register/dlr.rs b/aarch32-cpu/src/register/dlr.rs
index 03c7f535..baa96c13 100644
--- a/aarch32-cpu/src/register/dlr.rs
+++ b/aarch32-cpu/src/register/dlr.rs
@@ -16,7 +16,7 @@ impl SysReg for Dlr {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for Dlr {}
+impl SysRegRead for Dlr {}
 
 impl Dlr {
     #[inline]
@@ -26,7 +26,7 @@ impl Dlr {
     }
 }
 
-impl crate::register::SysRegWrite for Dlr {}
+impl SysRegWrite for Dlr {}
 
 impl Dlr {
     #[inline]
diff --git a/aarch32-cpu/src/register/dracr.rs b/aarch32-cpu/src/register/dracr.rs
index 5edd99cc..3816b6a8 100644
--- a/aarch32-cpu/src/register/dracr.rs
+++ b/aarch32-cpu/src/register/dracr.rs
@@ -36,7 +36,7 @@ impl SysReg for Dracr {
     const OP2: u32 = 4;
 }
 
-impl crate::register::SysRegRead for Dracr {}
+impl SysRegRead for Dracr {}
 
 impl Dracr {
     #[inline]
@@ -44,11 +44,12 @@ impl Dracr {
     ///
     /// Set RGNR to control which region this reads.
     pub fn read() -> Dracr {
+        // Safety: it's OK to set bits with no accessors specified
         unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
     }
 }
 
-impl crate::register::SysRegWrite for Dracr {}
+impl SysRegWrite for Dracr {}
 
 impl Dracr {
     #[inline]
diff --git a/aarch32-cpu/src/register/drbar.rs b/aarch32-cpu/src/register/drbar.rs
index 5e5f85f6..f6ec7e99 100644
--- a/aarch32-cpu/src/register/drbar.rs
+++ b/aarch32-cpu/src/register/drbar.rs
@@ -17,7 +17,7 @@ impl SysReg for Drbar {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for Drbar {}
+impl SysRegRead for Drbar {}
 
 impl Drbar {
     #[inline]
@@ -29,7 +29,7 @@ impl Drbar {
     }
 }
 
-impl crate::register::SysRegWrite for Drbar {}
+impl SysRegWrite for Drbar {}
 
 impl Drbar {
     #[inline]
diff --git a/aarch32-cpu/src/register/drsr.rs b/aarch32-cpu/src/register/drsr.rs
index b0d893c8..fabba60d 100644
--- a/aarch32-cpu/src/register/drsr.rs
+++ b/aarch32-cpu/src/register/drsr.rs
@@ -77,6 +77,9 @@ pub enum RegionSize {
 }
 
 impl RegionSize {
+    /// Check address alignment
+    ///
+    /// Reports whether an address is aligned according to this region size
     pub fn is_aligned(&self, addr: *const u8) -> bool {
         let addr = addr as usize;
         if *self == RegionSize::_4G {
@@ -119,7 +122,7 @@ impl SysReg for Drsr {
     const OP2: u32 = 2;
 }
 
-impl crate::register::SysRegRead for Drsr {}
+impl SysRegRead for Drsr {}
 
 impl Drsr {
     #[inline]
@@ -127,11 +130,12 @@ impl Drsr {
     ///
     /// Set RGNR to control which region this reads.
     pub fn read() -> Drsr {
+        // Safety: it's OK to set bits with no accessors specified
         unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
     }
 }
 
-impl crate::register::SysRegWrite for Drsr {}
+impl SysRegWrite for Drsr {}
 
 impl Drsr {
     #[inline]
diff --git a/aarch32-cpu/src/register/dspsr.rs b/aarch32-cpu/src/register/dspsr.rs
index ad5287b8..21d43034 100644
--- a/aarch32-cpu/src/register/dspsr.rs
+++ b/aarch32-cpu/src/register/dspsr.rs
@@ -16,7 +16,7 @@ impl SysReg for Dspsr {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for Dspsr {}
+impl SysRegRead for Dspsr {}
 
 impl Dspsr {
     #[inline]
@@ -26,7 +26,7 @@ impl Dspsr {
     }
 }
 
-impl crate::register::SysRegWrite for Dspsr {}
+impl SysRegWrite for Dspsr {}
 
 impl Dspsr {
     #[inline]
diff --git a/aarch32-cpu/src/register/fcseidr.rs b/aarch32-cpu/src/register/fcseidr.rs
index 1ad63f0a..ac8c3213 100644
--- a/aarch32-cpu/src/register/fcseidr.rs
+++ b/aarch32-cpu/src/register/fcseidr.rs
@@ -16,7 +16,7 @@ impl SysReg for Fcseidr {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for Fcseidr {}
+impl SysRegRead for Fcseidr {}
 
 impl Fcseidr {
     #[inline]
@@ -26,7 +26,7 @@ impl Fcseidr {
     }
 }
 
-impl crate::register::SysRegWrite for Fcseidr {}
+impl SysRegWrite for Fcseidr {}
 
 impl Fcseidr {
     #[inline]
diff --git a/aarch32-cpu/src/register/generic_timer/cnthctl.rs b/aarch32-cpu/src/register/generic_timer/cnthctl.rs
index 3bbf894c..e83992d5 100644
--- a/aarch32-cpu/src/register/generic_timer/cnthctl.rs
+++ b/aarch32-cpu/src/register/generic_timer/cnthctl.rs
@@ -8,40 +8,27 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Cnthctl {
-    #[bits(19..=19, rw)]
-    cntpmask: bool,
-    #[bits(18..=18, rw)]
-    cntvmask: bool,
-    #[bits(17..=17, rw)]
-    evntis: bool,
-    #[bits(16..=16, rw)]
-    el1nvvct: bool,
-    #[bits(15..=15, rw)]
-    el1nvpct: bool,
-    #[bits(14..=14, rw)]
-    el1tvct: bool,
-    #[bits(13..=13, rw)]
-    el1tvt: bool,
-    #[bits(12..=12, rw)]
-    ecv: bool,
-    #[bits(11..=11, rw)]
-    el1pten: bool,
-    #[bits(10..=10, rw)]
-    el1pcten: bool,
-    #[bits(9..=9, rw)]
-    el0pten: bool,
-    #[bits(8..=8, rw)]
-    el0vten: bool,
+    /// Selects which bit of CNTPCT, as seen from EL2, is the trigger for the
+    /// event stream generated from that counter when that stream is enabled.
     #[bits(4..=7, rw)]
     evnti: u4,
+    /// Controls which transition of the CNTPCT trigger bit, as seen from EL2
+    /// and defined by EVNTI, generates an event when the event stream is
+    /// enabled.
     #[bits(3..=3, rw)]
     evntdir: bool,
+    /// Enables the generation of an event stream from CNTPCT as seen from EL2.
     #[bits(2..=2, rw)]
     evnten: bool,
+    /// Traps Non-secure EL0 and EL1 MRC or MCR accesses, reported using EC
+    /// syndrome value 0x03, and MRRC or MCRR accesses, reported using EC
+    /// syndrome value 0x04, to the physical timer registers to Hyp mode.
     #[bits(1..=1, rw)]
-    el0vcten: bool,
+    pl1pcen: bool,
+    /// Traps Non-secure EL0 and EL1 MRRC or MCRR accesses, reported using EC
+    /// syndrome value 0x04, to the physical counter register to Hyp mode.
     #[bits(0..=0, rw)]
-    el0pcten: bool,
+    pl1pcten: bool,
 }
 
 impl SysReg for Cnthctl {
@@ -58,6 +45,7 @@ impl Cnthctl {
     #[inline]
     /// Reads CNTHCTL (*Hyp Counter-timer Control Register*)
     pub fn read() -> Cnthctl {
+        // Safety: it's OK to set bits with no accessors specified
         unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
     }
 }
diff --git a/aarch32-cpu/src/register/generic_timer/cnthp_ctl.rs b/aarch32-cpu/src/register/generic_timer/cnthp_ctl.rs
index 9dd3aa9e..b0162b70 100644
--- a/aarch32-cpu/src/register/generic_timer/cnthp_ctl.rs
+++ b/aarch32-cpu/src/register/generic_timer/cnthp_ctl.rs
@@ -34,6 +34,7 @@ impl CnthpCtl {
     #[inline]
     /// Reads CNTHP_CTL (*Hyp Physical Counter-timer Control Register (EL2)*)
     pub fn read() -> CnthpCtl {
+        // Safety: it's OK to set bits with no accessors specified
         unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
     }
 }
diff --git a/aarch32-cpu/src/register/generic_timer/cntkctl.rs b/aarch32-cpu/src/register/generic_timer/cntkctl.rs
index 92db33f1..49fc9c70 100644
--- a/aarch32-cpu/src/register/generic_timer/cntkctl.rs
+++ b/aarch32-cpu/src/register/generic_timer/cntkctl.rs
@@ -68,6 +68,7 @@ impl Cntkctl {
     #[inline]
     /// Reads CNTKCTL (*Counter-timer Kernel Control Register*)
     pub fn read() -> Cntkctl {
+        // Safety: it's OK to set bits with no accessors specified
         unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
     }
 }
diff --git a/aarch32-cpu/src/register/generic_timer/cntp_ctl.rs b/aarch32-cpu/src/register/generic_timer/cntp_ctl.rs
index a61da3b9..0a78b081 100644
--- a/aarch32-cpu/src/register/generic_timer/cntp_ctl.rs
+++ b/aarch32-cpu/src/register/generic_timer/cntp_ctl.rs
@@ -44,6 +44,7 @@ impl CntpCtl {
     #[inline]
     /// Reads CNTP_CTL (*Physical Counter-timer Control Register*)
     pub fn read() -> CntpCtl {
+        // Safety: it's OK to set bits with no accessors specified
         unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
     }
 }
diff --git a/aarch32-cpu/src/register/generic_timer/cntv_ctl.rs b/aarch32-cpu/src/register/generic_timer/cntv_ctl.rs
index e7b4bc45..55bd739f 100644
--- a/aarch32-cpu/src/register/generic_timer/cntv_ctl.rs
+++ b/aarch32-cpu/src/register/generic_timer/cntv_ctl.rs
@@ -44,6 +44,7 @@ impl CntvCtl {
     #[inline]
     /// Reads CNTV_CTL (*Virtual Counter-timer Control Register*)
     pub fn read() -> CntvCtl {
+        // Safety: it's OK to set bits with no accessors specified
         unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
     }
 }
diff --git a/aarch32-cpu/src/register/generic_timer/cntv_tval.rs b/aarch32-cpu/src/register/generic_timer/cntv_tval.rs
index ba184f42..ab2fcdb5 100644
--- a/aarch32-cpu/src/register/generic_timer/cntv_tval.rs
+++ b/aarch32-cpu/src/register/generic_timer/cntv_tval.rs
@@ -16,7 +16,7 @@ impl SysReg for CntvTval {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for CntvTval {}
+impl SysRegRead for CntvTval {}
 
 impl CntvTval {
     #[inline]
@@ -26,7 +26,7 @@ impl CntvTval {
     }
 }
 
-impl crate::register::SysRegWrite for CntvTval {}
+impl SysRegWrite for CntvTval {}
 
 impl CntvTval {
     #[inline]
diff --git a/aarch32-cpu/src/register/hyp/hacr.rs b/aarch32-cpu/src/register/hyp/hacr.rs
index 1690e9ca..b15dd251 100644
--- a/aarch32-cpu/src/register/hyp/hacr.rs
+++ b/aarch32-cpu/src/register/hyp/hacr.rs
@@ -16,7 +16,7 @@ impl SysReg for Hacr {
     const OP2: u32 = 7;
 }
 
-impl crate::register::SysRegRead for Hacr {}
+impl SysRegRead for Hacr {}
 
 impl Hacr {
     #[inline]
@@ -26,7 +26,7 @@ impl Hacr {
     }
 }
 
-impl crate::register::SysRegWrite for Hacr {}
+impl SysRegWrite for Hacr {}
 
 impl Hacr {
     #[inline]
diff --git a/aarch32-cpu/src/register/hyp/hactlr.rs b/aarch32-cpu/src/register/hyp/hactlr.rs
index 8c88fb12..6d90e4d3 100644
--- a/aarch32-cpu/src/register/hyp/hactlr.rs
+++ b/aarch32-cpu/src/register/hyp/hactlr.rs
@@ -79,7 +79,9 @@ impl Hactlr {
 
 impl core::fmt::Debug for Hactlr {
     fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        write!(f, "HACTLR {{ CPUACTLR={}, CDBGDCI={}, FLASHIFREGIONR={}, PERIPHPREGIONR={}, QOSR={}, BUSTIMEOUTR={}, INTMONR={}, ERR={}, TESTR1={} }}",
+        write!(
+            f,
+            "HACTLR {{ CPUACTLR={}, CDBGDCI={}, FLASHIFREGIONR={}, PERIPHPREGIONR={}, QOSR={}, BUSTIMEOUTR={}, INTMONR={}, ERR={}, TESTR1={} }}",
             self.cpuactlr() as u8,
             self.cdbgdci() as u8,
             self.flashifregionr() as u8,
@@ -95,7 +97,11 @@ impl core::fmt::Debug for Hactlr {
 
 #[cfg(feature = "defmt")]
 impl defmt::Format for Hactlr {
-    fn format(&self, f: defmt::Formatter) {
-        defmt::write!(f, "HACTLR {{ CPUACTLR={0=0..1}, CDBGDCI={0=1..2}, FLASHIFREGIONR={0=7..8}, PERIPHPREGIONR={0=8..9}, QOSR={0=9..10}, BUSTIMEOUTR={0=10..11}, INTMONR={0=12..13}, ERR={0=13..14}, TESTR1={0=15..16} }}", self.raw_value())
+    fn format(&self, f: defmt::Formatter<'_>) {
+        defmt::write!(
+            f,
+            "HACTLR {{ CPUACTLR={0=0..1}, CDBGDCI={0=1..2}, FLASHIFREGIONR={0=7..8}, PERIPHPREGIONR={0=8..9}, QOSR={0=9..10}, BUSTIMEOUTR={0=10..11}, INTMONR={0=12..13}, ERR={0=13..14}, TESTR1={0=15..16} }}",
+            self.raw_value()
+        )
     }
 }
diff --git a/aarch32-cpu/src/register/hyp/hactlr2.rs b/aarch32-cpu/src/register/hyp/hactlr2.rs
index 23cb4341..829c7926 100644
--- a/aarch32-cpu/src/register/hyp/hactlr2.rs
+++ b/aarch32-cpu/src/register/hyp/hactlr2.rs
@@ -16,7 +16,7 @@ impl SysReg for Hactlr2 {
     const OP2: u32 = 3;
 }
 
-impl crate::register::SysRegRead for Hactlr2 {}
+impl SysRegRead for Hactlr2 {}
 
 impl Hactlr2 {
     #[inline]
@@ -26,7 +26,7 @@ impl Hactlr2 {
     }
 }
 
-impl crate::register::SysRegWrite for Hactlr2 {}
+impl SysRegWrite for Hactlr2 {}
 
 impl Hactlr2 {
     #[inline]
diff --git a/aarch32-cpu/src/register/hyp/hadfsr.rs b/aarch32-cpu/src/register/hyp/hadfsr.rs
index c7041c04..5f7855c0 100644
--- a/aarch32-cpu/src/register/hyp/hadfsr.rs
+++ b/aarch32-cpu/src/register/hyp/hadfsr.rs
@@ -16,7 +16,7 @@ impl SysReg for Hadfsr {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for Hadfsr {}
+impl SysRegRead for Hadfsr {}
 
 impl Hadfsr {
     #[inline]
@@ -26,7 +26,7 @@ impl Hadfsr {
     }
 }
 
-impl crate::register::SysRegWrite for Hadfsr {}
+impl SysRegWrite for Hadfsr {}
 
 impl Hadfsr {
     #[inline]
diff --git a/aarch32-cpu/src/register/hyp/haifsr.rs b/aarch32-cpu/src/register/hyp/haifsr.rs
index e97b31fa..339e36eb 100644
--- a/aarch32-cpu/src/register/hyp/haifsr.rs
+++ b/aarch32-cpu/src/register/hyp/haifsr.rs
@@ -16,7 +16,7 @@ impl SysReg for Haifsr {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for Haifsr {}
+impl SysRegRead for Haifsr {}
 
 impl Haifsr {
     #[inline]
@@ -26,7 +26,7 @@ impl Haifsr {
     }
 }
 
-impl crate::register::SysRegWrite for Haifsr {}
+impl SysRegWrite for Haifsr {}
 
 impl Haifsr {
     #[inline]
diff --git a/aarch32-cpu/src/register/hyp/hamair0.rs b/aarch32-cpu/src/register/hyp/hamair0.rs
index afa1300d..09fc00e9 100644
--- a/aarch32-cpu/src/register/hyp/hamair0.rs
+++ b/aarch32-cpu/src/register/hyp/hamair0.rs
@@ -16,7 +16,7 @@ impl SysReg for Hamair0 {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for Hamair0 {}
+impl SysRegRead for Hamair0 {}
 
 impl Hamair0 {
     #[inline]
@@ -26,7 +26,7 @@ impl Hamair0 {
     }
 }
 
-impl crate::register::SysRegWrite for Hamair0 {}
+impl SysRegWrite for Hamair0 {}
 
 impl Hamair0 {
     #[inline]
diff --git a/aarch32-cpu/src/register/hyp/hamair1.rs b/aarch32-cpu/src/register/hyp/hamair1.rs
index 4f8b6a18..af633129 100644
--- a/aarch32-cpu/src/register/hyp/hamair1.rs
+++ b/aarch32-cpu/src/register/hyp/hamair1.rs
@@ -16,7 +16,7 @@ impl SysReg for Hamair1 {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for Hamair1 {}
+impl SysRegRead for Hamair1 {}
 
 impl Hamair1 {
     #[inline]
@@ -26,7 +26,7 @@ impl Hamair1 {
     }
 }
 
-impl crate::register::SysRegWrite for Hamair1 {}
+impl SysRegWrite for Hamair1 {}
 
 impl Hamair1 {
     #[inline]
diff --git a/aarch32-cpu/src/register/hyp/hcptr.rs b/aarch32-cpu/src/register/hyp/hcptr.rs
index 864adea7..9dcf4578 100644
--- a/aarch32-cpu/src/register/hyp/hcptr.rs
+++ b/aarch32-cpu/src/register/hyp/hcptr.rs
@@ -28,12 +28,13 @@ impl SysReg for Hcptr {
     const OP2: u32 = 2;
 }
 
-impl crate::register::SysRegRead for Hcptr {}
+impl SysRegRead for Hcptr {}
 
 impl Hcptr {
     #[inline]
     /// Reads HCPTR (*Hyp Architectural Feature Trap Register*)
     pub fn read() -> Hcptr {
+        // Safety: it's OK to set bits with no accessors specified
         unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
     }
 
@@ -49,7 +50,7 @@ impl Hcptr {
     }
 }
 
-impl crate::register::SysRegWrite for Hcptr {}
+impl SysRegWrite for Hcptr {}
 
 impl Hcptr {
     #[inline]
diff --git a/aarch32-cpu/src/register/hyp/hcr.rs b/aarch32-cpu/src/register/hyp/hcr.rs
index 9424f92b..7f6efa50 100644
--- a/aarch32-cpu/src/register/hyp/hcr.rs
+++ b/aarch32-cpu/src/register/hyp/hcr.rs
@@ -98,9 +98,13 @@ pub struct Hcr {
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 #[derive(Debug, PartialEq, Eq)]
 pub enum Bsu {
+    /// No effect
     NoEffect = 0b00,
+    /// Inner Shareable
     InnerShareable = 0b01,
+    /// Outer Shareable
     OuterShareable = 0b10,
+    /// Full System
     FullSystem = 0b11,
 }
 
@@ -112,17 +116,18 @@ impl SysReg for Hcr {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for Hcr {}
+impl SysRegRead for Hcr {}
 
 impl Hcr {
     #[inline]
     /// Reads HCR (*Hyp Configuration Register*)
     pub fn read() -> Hcr {
+        // Safety: it's OK to set bits with no accessors specified
         unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
     }
 }
 
-impl crate::register::SysRegWrite for Hcr {}
+impl SysRegWrite for Hcr {}
 
 impl Hcr {
     #[inline]
diff --git a/aarch32-cpu/src/register/hyp/hcr2.rs b/aarch32-cpu/src/register/hyp/hcr2.rs
index 436873e3..4280a7cf 100644
--- a/aarch32-cpu/src/register/hyp/hcr2.rs
+++ b/aarch32-cpu/src/register/hyp/hcr2.rs
@@ -16,7 +16,7 @@ impl SysReg for Hcr2 {
     const OP2: u32 = 4;
 }
 
-impl crate::register::SysRegRead for Hcr2 {}
+impl SysRegRead for Hcr2 {}
 
 impl Hcr2 {
     #[inline]
@@ -26,7 +26,7 @@ impl Hcr2 {
     }
 }
 
-impl crate::register::SysRegWrite for Hcr2 {}
+impl SysRegWrite for Hcr2 {}
 
 impl Hcr2 {
     #[inline]
diff --git a/aarch32-cpu/src/register/hyp/hdcr.rs b/aarch32-cpu/src/register/hyp/hdcr.rs
index 2fb31010..6be8de92 100644
--- a/aarch32-cpu/src/register/hyp/hdcr.rs
+++ b/aarch32-cpu/src/register/hyp/hdcr.rs
@@ -16,7 +16,7 @@ impl SysReg for Hdcr {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for Hdcr {}
+impl SysRegRead for Hdcr {}
 
 impl Hdcr {
     #[inline]
@@ -26,7 +26,7 @@ impl Hdcr {
     }
 }
 
-impl crate::register::SysRegWrite for Hdcr {}
+impl SysRegWrite for Hdcr {}
 
 impl Hdcr {
     #[inline]
diff --git a/aarch32-cpu/src/register/hyp/hdfar.rs b/aarch32-cpu/src/register/hyp/hdfar.rs
index a6eff518..6c06a6ec 100644
--- a/aarch32-cpu/src/register/hyp/hdfar.rs
+++ b/aarch32-cpu/src/register/hyp/hdfar.rs
@@ -16,7 +16,7 @@ impl SysReg for Hdfar {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for Hdfar {}
+impl SysRegRead for Hdfar {}
 
 impl Hdfar {
     #[inline]
@@ -26,7 +26,7 @@ impl Hdfar {
     }
 }
 
-impl crate::register::SysRegWrite for Hdfar {}
+impl SysRegWrite for Hdfar {}
 
 impl Hdfar {
     #[inline]
diff --git a/aarch32-cpu/src/register/hyp/hifar.rs b/aarch32-cpu/src/register/hyp/hifar.rs
index ed385157..f0ea7b85 100644
--- a/aarch32-cpu/src/register/hyp/hifar.rs
+++ b/aarch32-cpu/src/register/hyp/hifar.rs
@@ -16,7 +16,7 @@ impl SysReg for Hifar {
     const OP2: u32 = 2;
 }
 
-impl crate::register::SysRegRead for Hifar {}
+impl SysRegRead for Hifar {}
 
 impl Hifar {
     #[inline]
@@ -26,7 +26,7 @@ impl Hifar {
     }
 }
 
-impl crate::register::SysRegWrite for Hifar {}
+impl SysRegWrite for Hifar {}
 
 impl Hifar {
     #[inline]
diff --git a/aarch32-cpu/src/register/hyp/hmair0.rs b/aarch32-cpu/src/register/hyp/hmair0.rs
index 3e217c43..2bcfb2e9 100644
--- a/aarch32-cpu/src/register/hyp/hmair0.rs
+++ b/aarch32-cpu/src/register/hyp/hmair0.rs
@@ -16,7 +16,7 @@ impl SysReg for Hmair0 {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for Hmair0 {}
+impl SysRegRead for Hmair0 {}
 
 impl Hmair0 {
     #[inline]
@@ -26,7 +26,7 @@ impl Hmair0 {
     }
 }
 
-impl crate::register::SysRegWrite for Hmair0 {}
+impl SysRegWrite for Hmair0 {}
 
 impl Hmair0 {
     #[inline]
diff --git a/aarch32-cpu/src/register/hyp/hmair1.rs b/aarch32-cpu/src/register/hyp/hmair1.rs
index 75febb28..1586ec1b 100644
--- a/aarch32-cpu/src/register/hyp/hmair1.rs
+++ b/aarch32-cpu/src/register/hyp/hmair1.rs
@@ -16,7 +16,7 @@ impl SysReg for Hmair1 {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for Hmair1 {}
+impl SysRegRead for Hmair1 {}
 
 impl Hmair1 {
     #[inline]
@@ -26,7 +26,7 @@ impl Hmair1 {
     }
 }
 
-impl crate::register::SysRegWrite for Hmair1 {}
+impl SysRegWrite for Hmair1 {}
 
 impl Hmair1 {
     #[inline]
diff --git a/aarch32-cpu/src/register/hyp/hpfar.rs b/aarch32-cpu/src/register/hyp/hpfar.rs
index 261004e8..8a636af1 100644
--- a/aarch32-cpu/src/register/hyp/hpfar.rs
+++ b/aarch32-cpu/src/register/hyp/hpfar.rs
@@ -17,7 +17,7 @@ impl SysReg for Hpfar {
     const OP2: u32 = 4;
 }
 
-impl crate::register::SysRegRead for Hpfar {}
+impl SysRegRead for Hpfar {}
 
 impl Hpfar {
     #[inline]
@@ -27,7 +27,7 @@ impl Hpfar {
     }
 }
 
-impl crate::register::SysRegWrite for Hpfar {}
+impl SysRegWrite for Hpfar {}
 
 impl Hpfar {
     #[inline]
diff --git a/aarch32-cpu/src/register/hyp/hsctlr.rs b/aarch32-cpu/src/register/hyp/hsctlr.rs
index b09e65e6..96822c7e 100644
--- a/aarch32-cpu/src/register/hyp/hsctlr.rs
+++ b/aarch32-cpu/src/register/hyp/hsctlr.rs
@@ -51,17 +51,18 @@ impl SysReg for Hsctlr {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for Hsctlr {}
+impl SysRegRead for Hsctlr {}
 
 impl Hsctlr {
     #[inline]
     /// Reads HSCTLR (*Hyp System Control Register*)
     pub fn read() -> Hsctlr {
+        // Safety: it's OK to set bits with no accessors specified
         unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
     }
 }
 
-impl crate::register::SysRegWrite for Hsctlr {}
+impl SysRegWrite for Hsctlr {}
 
 impl Hsctlr {
     #[inline]
diff --git a/aarch32-cpu/src/register/hyp/hsr.rs b/aarch32-cpu/src/register/hyp/hsr.rs
index b499db95..1ace6f3b 100644
--- a/aarch32-cpu/src/register/hyp/hsr.rs
+++ b/aarch32-cpu/src/register/hyp/hsr.rs
@@ -2,7 +2,7 @@
 
 use crate::register::{SysReg, SysRegRead, SysRegWrite};
 
-use arbitrary_int::{u2, u25, u3, u4, u6};
+use arbitrary_int::{u2, u3, u4, u6, u25};
 
 /// HSR (*Hyp Syndrome Register*)
 #[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
@@ -42,24 +42,43 @@ impl Hsr {
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 #[derive(Debug, PartialEq, Eq)]
+/// Exception Class value from the HSR (*Hyp Syndrome Register*)
 pub enum ExceptionClass {
+    /// Unknown reason
     Unknown = 0b00_0000,
+    /// Trapped WFI or WFE instruction execution
     TrappedWfiWfe = 0b00_0001,
+    /// Trapped MCR or MRC access with (coproc==`0b1111`) that is not reported using EC value `0b000000``
     TrappedCp15McrMrc = 0b00_0011,
+    /// Trapped MCRR or MRRC access with (coproc==`0b1111`) that is not reported using EC value `0b000000``
     TrappedCp15McrrMrrc = 0b00_0100,
+    /// Trapped MCR or MRC access with (coproc==`0b1110``)
     TrappedCp14McrMrc = 0b00_0101,
+    /// Trapped LDC or STC access
     TrappedLdcStc = 0b00_0110,
+    /// Access to Advanced SIMD or floating-point functionality trapped by a `HCPTR.{TASE, TCP10}` control
     TrappedFpu = 0b00_0111,
+    /// Trapped VMRS access, from ID group trap, that is not reported using EC value `0b000111`
     TrappedVmrs = 0b00_1000,
+    /// Trapped MRRC access with (coproc==`0b1110`)
     TrappedCp14McrrMrrc = 0b00_1100,
+    /// Illegal exception return to AArch32 state
     IllegalAArch32Eret = 0b00_1110,
+    /// Exception on SVC instruction execution in AArch32 state routed to EL2
     Svc = 0b01_0001,
+    /// HVC instruction execution in AArch32 state, when HVC is not disabled
     Hvc = 0b01_0010,
+    /// Trapped execution of SMC instruction in AArch32 state
     Smc = 0b01_0011,
+    /// Prefetch Abort from a lower Exception level
     PrefetchAbortFromLower = 0b10_0000,
+    /// Prefetch Abort taken without a change in Exception level
     PrefetchAbortFromCurrent = 0b10_0001,
+    /// PC alignment fault exception
     PcAlignment = 0b10_0010,
+    /// Data Abort exception from a lower Exception level
     DataAbortFromLower = 0b10_0100,
+    /// Data Abort exception taken without a change in Exception level
     DataAbortFromCurrent = 0b10_0101,
 }
 
@@ -68,27 +87,46 @@ pub enum ExceptionClass {
 /// ISS is a 25 bit field whose meaning varies depending on the value of the EC field.
 #[derive(Debug, Clone)]
 pub enum Iss {
+    /// ISS for [`ExceptionClass::Unknown`]
     Unknown(IssUnknown),
+    /// ISS for [`ExceptionClass::TrappedWfiWfe`]
     TrappedWfiWfe(IssTrappedWfiWfe),
+    /// ISS for [`ExceptionClass::TrappedCp15McrMrc`]
     TrappedCp15McrMrc(IssTrappedMcrMrc),
+    /// ISS for [`ExceptionClass::TrappedCp15McrrMrrc`]
     TrappedCp15McrrMrrc(IssTrappedMcrrMrrc),
+    /// ISS for [`ExceptionClass::TrappedCp14McrMrc`]
     TrappedCp14McrMrc(IssTrappedMcrMrc),
+    /// ISS for [`ExceptionClass::TrappedLdcStc`]
     TrappedLdcStc(IssTrappedLdcStc),
+    /// ISS for [`ExceptionClass::TrappedFpu`]
     TrappedFpu(IssTrappedFpu),
+    /// ISS for [`ExceptionClass::TrappedVmrs`]
     TrappedVmrs(IssTrappedVmrs),
+    /// ISS for [`ExceptionClass::TrappedCp14McrrMrrc`]
     TrappedCp14McrrMrrc(IssTrappedMcrrMrrc),
+    /// ISS for [`ExceptionClass::IllegalAArch32Eret`]
     IllegalAArch32Eret,
+    /// ISS for [`ExceptionClass::Svc`]
     Svc(IssCall),
+    /// ISS for [`ExceptionClass::Hvc`]
     Hvc(IssCall),
+    /// ISS for [`ExceptionClass::Smc`]
     Smc(IssSmc),
+    /// ISS for [`ExceptionClass::PrefetchAbortFromLower`]
     PrefetchAbortFromLower(IssPrefetchAbort),
+    /// ISS for [`ExceptionClass::PrefetchAbortFromCurrent`]
     PrefetchAbortFromCurrent(IssPrefetchAbort),
+    /// ISS for [`ExceptionClass::PcAlignment`]
     PcAlignment,
+    /// ISS for [`ExceptionClass::DataAbortFromLower`]
     DataAbortFromLower(IssDataAbort),
+    /// ISS for [`ExceptionClass::DataAbortFromCurrent`]
     DataAbortFromCurrent(IssDataAbort),
 }
 
 impl ExceptionClass {
+    /// Convert an ISS value based on the Exception Class
     pub fn decode_iss(&self, iss: u25) -> Iss {
         match self {
             ExceptionClass::Unknown => Iss::Unknown(IssUnknown(iss.value())),
@@ -324,8 +362,11 @@ pub struct IssDataAbort {
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 #[derive(Debug, PartialEq, Eq)]
+/// The length of the instruction that trapped
 pub enum InstructionLength {
+    /// A 16-bit instruction
     SixteenBit = 0b0,
+    /// A 32-bit instruction
     ThirtyTwoBit = 0b1,
 }
 
@@ -337,17 +378,18 @@ impl SysReg for Hsr {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for Hsr {}
+impl SysRegRead for Hsr {}
 
 impl Hsr {
     #[inline]
     /// Reads HSR (*Hyp Syndrome Register*)
     pub fn read() -> Hsr {
+        // Safety: it's OK to set bits with no accessors specified
         unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
     }
 }
 
-impl crate::register::SysRegWrite for Hsr {}
+impl SysRegWrite for Hsr {}
 
 impl Hsr {
     #[inline]
diff --git a/aarch32-cpu/src/register/hyp/hstr.rs b/aarch32-cpu/src/register/hyp/hstr.rs
index 331f1360..3b2605ad 100644
--- a/aarch32-cpu/src/register/hyp/hstr.rs
+++ b/aarch32-cpu/src/register/hyp/hstr.rs
@@ -16,7 +16,7 @@ impl SysReg for Hstr {
     const OP2: u32 = 3;
 }
 
-impl crate::register::SysRegRead for Hstr {}
+impl SysRegRead for Hstr {}
 
 impl Hstr {
     #[inline]
@@ -26,7 +26,7 @@ impl Hstr {
     }
 }
 
-impl crate::register::SysRegWrite for Hstr {}
+impl SysRegWrite for Hstr {}
 
 impl Hstr {
     #[inline]
diff --git a/aarch32-cpu/src/register/hyp/htpidr.rs b/aarch32-cpu/src/register/hyp/htpidr.rs
index 7534bf0d..99ff32cf 100644
--- a/aarch32-cpu/src/register/hyp/htpidr.rs
+++ b/aarch32-cpu/src/register/hyp/htpidr.rs
@@ -16,7 +16,7 @@ impl SysReg for Htpidr {
     const OP2: u32 = 2;
 }
 
-impl crate::register::SysRegRead for Htpidr {}
+impl SysRegRead for Htpidr {}
 
 impl Htpidr {
     #[inline]
@@ -26,7 +26,7 @@ impl Htpidr {
     }
 }
 
-impl crate::register::SysRegWrite for Htpidr {}
+impl SysRegWrite for Htpidr {}
 
 impl Htpidr {
     #[inline]
diff --git a/aarch32-cpu/src/register/hyp/hvbar.rs b/aarch32-cpu/src/register/hyp/hvbar.rs
index 13e238c5..bc076e93 100644
--- a/aarch32-cpu/src/register/hyp/hvbar.rs
+++ b/aarch32-cpu/src/register/hyp/hvbar.rs
@@ -1,4 +1,4 @@
-//! Code for HVBAR (*Hyp Vector Base Address Register*)
+//! Code for managing HVBAR (*Hyp Vector Base Address Register*)
 
 use crate::register::{SysReg, SysRegRead, SysRegWrite};
 
diff --git a/aarch32-cpu/src/register/icc_pmr.rs b/aarch32-cpu/src/register/icc_pmr.rs
index 7e5c77b4..f6fbee6f 100644
--- a/aarch32-cpu/src/register/icc_pmr.rs
+++ b/aarch32-cpu/src/register/icc_pmr.rs
@@ -16,7 +16,7 @@ impl SysReg for IccPmr {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for IccPmr {}
+impl SysRegRead for IccPmr {}
 
 impl IccPmr {
     #[inline]
@@ -26,7 +26,7 @@ impl IccPmr {
     }
 }
 
-impl crate::register::SysRegWrite for IccPmr {}
+impl SysRegWrite for IccPmr {}
 
 impl IccPmr {
     #[inline]
diff --git a/aarch32-cpu/src/register/iciallu.rs b/aarch32-cpu/src/register/iciallu.rs
index 589bd949..b828ceb7 100644
--- a/aarch32-cpu/src/register/iciallu.rs
+++ b/aarch32-cpu/src/register/iciallu.rs
@@ -1,4 +1,4 @@
-//! Code for managing ICIALLU (*Invalidate all instruction caches to PoU.*)
+//! Code for managing ICIALLU (*Invalidate entire instruction cache to PoU Register*)
 //!
 //! Starting with ARMv6, the type of cache can be determined from the System Coprocessor register 0,
 //! and controlled through registers 1, 7 and 9. In earlier architecture variants, it is
@@ -8,6 +8,7 @@ use crate::register::{SysReg, SysRegWrite};
 #[derive(Debug, Copy, Clone)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
+/// ICIALLU (*Invalidate entire instruction cache to PoU Register*)
 pub struct Iciallu;
 
 impl SysReg for Iciallu {
@@ -18,11 +19,11 @@ impl SysReg for Iciallu {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegWrite for Iciallu {}
+impl SysRegWrite for Iciallu {}
 
 impl Iciallu {
     #[inline]
-    /// Writes ICIALLU (*Invalidate all instruction caches to PoU.*)
+    /// Writes 0 to ICIALLU (*Invalidate entire instruction cache to PoU Register*) to trigger operation
     pub fn write() {
         unsafe {
             <Self as SysRegWrite>::write_raw(0);
diff --git a/aarch32-cpu/src/register/id_afr0.rs b/aarch32-cpu/src/register/id_afr0.rs
index 54fbf320..41c39afd 100644
--- a/aarch32-cpu/src/register/id_afr0.rs
+++ b/aarch32-cpu/src/register/id_afr0.rs
@@ -16,7 +16,7 @@ impl SysReg for IdAfr0 {
     const OP2: u32 = 3;
 }
 
-impl crate::register::SysRegRead for IdAfr0 {}
+impl SysRegRead for IdAfr0 {}
 
 impl IdAfr0 {
     #[inline]
diff --git a/aarch32-cpu/src/register/id_dfr0.rs b/aarch32-cpu/src/register/id_dfr0.rs
index c19b0e4e..073b5fd4 100644
--- a/aarch32-cpu/src/register/id_dfr0.rs
+++ b/aarch32-cpu/src/register/id_dfr0.rs
@@ -16,7 +16,7 @@ impl SysReg for IdDfr0 {
     const OP2: u32 = 2;
 }
 
-impl crate::register::SysRegRead for IdDfr0 {}
+impl SysRegRead for IdDfr0 {}
 
 impl IdDfr0 {
     #[inline]
diff --git a/aarch32-cpu/src/register/id_isar0.rs b/aarch32-cpu/src/register/id_isar0.rs
index 63cf8851..56daed0e 100644
--- a/aarch32-cpu/src/register/id_isar0.rs
+++ b/aarch32-cpu/src/register/id_isar0.rs
@@ -16,7 +16,7 @@ impl SysReg for IdIsar0 {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for IdIsar0 {}
+impl SysRegRead for IdIsar0 {}
 
 impl IdIsar0 {
     #[inline]
diff --git a/aarch32-cpu/src/register/id_isar1.rs b/aarch32-cpu/src/register/id_isar1.rs
index 4fdce861..18bbeb35 100644
--- a/aarch32-cpu/src/register/id_isar1.rs
+++ b/aarch32-cpu/src/register/id_isar1.rs
@@ -16,7 +16,7 @@ impl SysReg for IdIsar1 {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for IdIsar1 {}
+impl SysRegRead for IdIsar1 {}
 
 impl IdIsar1 {
     #[inline]
diff --git a/aarch32-cpu/src/register/id_isar2.rs b/aarch32-cpu/src/register/id_isar2.rs
index 84b9d0a2..97ab9d16 100644
--- a/aarch32-cpu/src/register/id_isar2.rs
+++ b/aarch32-cpu/src/register/id_isar2.rs
@@ -16,7 +16,7 @@ impl SysReg for IdIsar2 {
     const OP2: u32 = 2;
 }
 
-impl crate::register::SysRegRead for IdIsar2 {}
+impl SysRegRead for IdIsar2 {}
 
 impl IdIsar2 {
     #[inline]
diff --git a/aarch32-cpu/src/register/id_isar3.rs b/aarch32-cpu/src/register/id_isar3.rs
index 66764315..39739dcc 100644
--- a/aarch32-cpu/src/register/id_isar3.rs
+++ b/aarch32-cpu/src/register/id_isar3.rs
@@ -16,7 +16,7 @@ impl SysReg for IdIsar3 {
     const OP2: u32 = 3;
 }
 
-impl crate::register::SysRegRead for IdIsar3 {}
+impl SysRegRead for IdIsar3 {}
 
 impl IdIsar3 {
     #[inline]
diff --git a/aarch32-cpu/src/register/id_isar4.rs b/aarch32-cpu/src/register/id_isar4.rs
index 8d2cab9f..081d3a5e 100644
--- a/aarch32-cpu/src/register/id_isar4.rs
+++ b/aarch32-cpu/src/register/id_isar4.rs
@@ -16,7 +16,7 @@ impl SysReg for IdIsar4 {
     const OP2: u32 = 4;
 }
 
-impl crate::register::SysRegRead for IdIsar4 {}
+impl SysRegRead for IdIsar4 {}
 
 impl IdIsar4 {
     #[inline]
diff --git a/aarch32-cpu/src/register/id_isar5.rs b/aarch32-cpu/src/register/id_isar5.rs
index ed6540d8..6e32f807 100644
--- a/aarch32-cpu/src/register/id_isar5.rs
+++ b/aarch32-cpu/src/register/id_isar5.rs
@@ -16,7 +16,7 @@ impl SysReg for IdIsar5 {
     const OP2: u32 = 5;
 }
 
-impl crate::register::SysRegRead for IdIsar5 {}
+impl SysRegRead for IdIsar5 {}
 
 impl IdIsar5 {
     #[inline]
diff --git a/aarch32-cpu/src/register/id_mmfr0.rs b/aarch32-cpu/src/register/id_mmfr0.rs
index fd9d3c2e..56d176f7 100644
--- a/aarch32-cpu/src/register/id_mmfr0.rs
+++ b/aarch32-cpu/src/register/id_mmfr0.rs
@@ -16,7 +16,7 @@ impl SysReg for IdMmfr0 {
     const OP2: u32 = 4;
 }
 
-impl crate::register::SysRegRead for IdMmfr0 {}
+impl SysRegRead for IdMmfr0 {}
 
 impl IdMmfr0 {
     #[inline]
diff --git a/aarch32-cpu/src/register/id_mmfr1.rs b/aarch32-cpu/src/register/id_mmfr1.rs
index 6ebd0ec8..b5e0358a 100644
--- a/aarch32-cpu/src/register/id_mmfr1.rs
+++ b/aarch32-cpu/src/register/id_mmfr1.rs
@@ -16,7 +16,7 @@ impl SysReg for IdMmfr1 {
     const OP2: u32 = 5;
 }
 
-impl crate::register::SysRegRead for IdMmfr1 {}
+impl SysRegRead for IdMmfr1 {}
 
 impl IdMmfr1 {
     #[inline]
diff --git a/aarch32-cpu/src/register/id_mmfr2.rs b/aarch32-cpu/src/register/id_mmfr2.rs
index e71fb8b0..c12ab99f 100644
--- a/aarch32-cpu/src/register/id_mmfr2.rs
+++ b/aarch32-cpu/src/register/id_mmfr2.rs
@@ -16,7 +16,7 @@ impl SysReg for IdMmfr2 {
     const OP2: u32 = 6;
 }
 
-impl crate::register::SysRegRead for IdMmfr2 {}
+impl SysRegRead for IdMmfr2 {}
 
 impl IdMmfr2 {
     #[inline]
diff --git a/aarch32-cpu/src/register/id_mmfr3.rs b/aarch32-cpu/src/register/id_mmfr3.rs
index 4fe042af..54c81289 100644
--- a/aarch32-cpu/src/register/id_mmfr3.rs
+++ b/aarch32-cpu/src/register/id_mmfr3.rs
@@ -16,7 +16,7 @@ impl SysReg for IdMmfr3 {
     const OP2: u32 = 7;
 }
 
-impl crate::register::SysRegRead for IdMmfr3 {}
+impl SysRegRead for IdMmfr3 {}
 
 impl IdMmfr3 {
     #[inline]
diff --git a/aarch32-cpu/src/register/id_mmfr4.rs b/aarch32-cpu/src/register/id_mmfr4.rs
index a4d101f2..e174f284 100644
--- a/aarch32-cpu/src/register/id_mmfr4.rs
+++ b/aarch32-cpu/src/register/id_mmfr4.rs
@@ -16,7 +16,7 @@ impl SysReg for IdMmfr4 {
     const OP2: u32 = 6;
 }
 
-impl crate::register::SysRegRead for IdMmfr4 {}
+impl SysRegRead for IdMmfr4 {}
 
 impl IdMmfr4 {
     #[inline]
diff --git a/aarch32-cpu/src/register/id_pfr0.rs b/aarch32-cpu/src/register/id_pfr0.rs
index 06435711..dfa49bbc 100644
--- a/aarch32-cpu/src/register/id_pfr0.rs
+++ b/aarch32-cpu/src/register/id_pfr0.rs
@@ -16,7 +16,7 @@ impl SysReg for IdPfr0 {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for IdPfr0 {}
+impl SysRegRead for IdPfr0 {}
 
 impl IdPfr0 {
     #[inline]
diff --git a/aarch32-cpu/src/register/id_pfr1.rs b/aarch32-cpu/src/register/id_pfr1.rs
index f3bea178..e422f8e7 100644
--- a/aarch32-cpu/src/register/id_pfr1.rs
+++ b/aarch32-cpu/src/register/id_pfr1.rs
@@ -16,7 +16,7 @@ impl SysReg for IdPfr1 {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for IdPfr1 {}
+impl SysRegRead for IdPfr1 {}
 
 impl IdPfr1 {
     #[inline]
diff --git a/aarch32-cpu/src/register/ifar.rs b/aarch32-cpu/src/register/ifar.rs
index b2cfa875..645bbe7e 100644
--- a/aarch32-cpu/src/register/ifar.rs
+++ b/aarch32-cpu/src/register/ifar.rs
@@ -16,7 +16,7 @@ impl SysReg for Ifar {
     const OP2: u32 = 2;
 }
 
-impl crate::register::SysRegRead for Ifar {}
+impl SysRegRead for Ifar {}
 
 impl Ifar {
     #[inline]
@@ -26,7 +26,7 @@ impl Ifar {
     }
 }
 
-impl crate::register::SysRegWrite for Ifar {}
+impl SysRegWrite for Ifar {}
 
 impl Ifar {
     #[inline]
diff --git a/aarch32-cpu/src/register/ifsr.rs b/aarch32-cpu/src/register/ifsr.rs
index 00efa8d7..5559f2f2 100644
--- a/aarch32-cpu/src/register/ifsr.rs
+++ b/aarch32-cpu/src/register/ifsr.rs
@@ -86,18 +86,31 @@ pub struct Ifsr {
 #[derive(Debug, PartialEq, Eq)]
 #[cfg(arm_architecture = "v5te")]
 pub enum IfsrStatus {
+    /// PC Alignment Fault
     Alignment = 1,
+    /// Debug Exception
     DebugEvent = 2,
+    /// Alternate value for PC Alignment Fault
     AlignmentAlt = 3,
+    /// Translation fault, level 1
     TranslationFaultFirstLevel = 5,
+    /// Translation fault, level 2
     TranslationFaultSecondLevel = 7,
+    /// Synchronous External abort
     SyncExtAbort = 8,
+    /// Domain fault, level 1
     DomainFaultFirstLevel = 9,
+    /// Alternate value for Synchronous External abort
     SyncExtAbortAlt = 10,
+    /// Domain fault, level 2
     DomainFaultSecondLevel = 11,
+    /// Synchronous External abort, on translation table walk, level 1
     SyncExtAbortOnTranslationTableWalkFirstLevel = 12,
+    /// Permission fault, level 1
     PermissionFaultFirstLevel = 13,
+    /// Synchronous External abort, on translation table walk, level 2
     SyncExtAbortOnTranslationTableWalkSecondLevel = 14,
+    /// Permission fault, level 2
     PermissionFaultSecondLevel = 15,
 }
 
@@ -108,18 +121,31 @@ pub enum IfsrStatus {
 #[derive(Debug, PartialEq, Eq)]
 #[cfg(arm_architecture = "v6")]
 pub enum IfsrStatus {
+    /// PC Alignment Fault
     Alignment = 1,
+    /// Debug Exception
     DebugEvent = 2,
+    /// Access Flag fault, level 1
     AccessFlagFaultFirstLevel = 3,
+    /// Translation fault, level 1
     TranslationFaultFirstLevel = 5,
+    /// Access Flag fault, level 2
     AccessFlagFaultSecondLevel = 6,
+    /// Translation fault, level 2
     TranslationFaultSecondLevel = 7,
+    /// Synchronouse External Abort
     SyncExtAbort = 8,
+    /// Domain fault, level 1
     DomainFaultFirstLevel = 9,
+    /// Domain fault, level 2
     DomainFaultSecondLevel = 11,
+    /// Synchronous External abort, on translation table walk, level 1
     SyncExtAbortOnTranslationTableWalkFirstLevel = 12,
+    /// Permission fault, level 1
     PermissionFaultFirstLevel = 13,
+    /// Synchronous External abort, on translation table walk, level 2
     SyncExtAbortOnTranslationTableWalkSecondLevel = 14,
+    /// Permission fault, level 2
     PermissionFaultSecondLevel = 15,
 }
 
@@ -130,12 +156,19 @@ pub enum IfsrStatus {
 #[derive(Debug, PartialEq, Eq)]
 #[cfg(arm_architecture = "v7-r")]
 pub enum IfsrStatus {
+    /// PC Alignment Fault
     Alignment = 1,
+    /// Debug Exception
     DebugEvent = 2,
+    /// Synchronous External abort
     SyncExtAbort = 8,
+    /// Permission fault, level 1
     PermissionFaultFirstLevel = 13,
+    /// Asynchronous External abort
     AsyncExtAbort = 21,
+    /// Synchronous parity or ECC error
     SyncParityEccError = 25,
+    /// asynchronous parity or ECC error
     AsyncParityEccError = 24,
 }
 
@@ -146,23 +179,41 @@ pub enum IfsrStatus {
 #[derive(Debug, PartialEq, Eq)]
 #[cfg(arm_architecture = "v7-a")]
 pub enum IfsrStatus {
+    /// Synchronous External abort, on translation table walk, level 1
     SyncExtAbortOnTranslationTableWalkFirstLevel = 0b01100,
+    /// Synchronous External abort, on translation table walk, level 2
     SyncExtAbortOnTranslationTableWalkSecondLevel = 0b01110,
+    /// Synchronous parity or ECC error on memory access, on translation table walk, level 1
     SyncParErrorOnTranslationTableWalkFirstLevel = 0b11100,
+    /// Synchronous parity or ECC error on memory access, on translation table walk, level 2
     SyncParErrorOnTranslationTableWalkSecondLevel = 0b11110,
+    /// Translation fault, level 1
     TranslationFaultFirstLevel = 0b00101,
+    /// Translation fault, level 2
     TranslationFaultSecondLevel = 0b00111,
+    /// Access flag fault, level 1
     AccessFlagFaultFirstLevel = 0b00011,
+    /// Access flag fault, level 2
     AccessFlagFaultSecondLevel = 0b00110,
+    /// Domain fault, level 1
     DomainFaultFirstLevel = 0b01001,
+    /// Domain fault, level 2
     DomainFaultSecondLevel = 0b01011,
+    /// Permission fault, level 1
     PermissionFaultFirstLevel = 0b01101,
+    /// Permission fault, level 2
     PermissionFaultSecondLevel = 0b01111,
+    /// Debug exception
     DebugEvent = 0b00010,
+    /// Synchronous External abort
     SyncExtAbort = 0b01000,
+    /// TLB conflict abort
     TlbConflictAbort = 0b10000,
+    /// IMPLEMENTATION DEFINED fault (Lockdown fault)
     Lockdown = 0b10100,
+    /// Co-Processor Abort
     CoprocessorAbort = 0b11010,
+    /// Synchronous parity or ECC error on memory access, not on translation table walk
     SyncParErrorOnMemAccess = 0b11001,
 }
 
@@ -173,11 +224,17 @@ pub enum IfsrStatus {
 #[derive(Debug, PartialEq, Eq)]
 #[cfg(arm_architecture = "v8-r")]
 pub enum IfsrStatus {
+    /// Translation fault
     Translation = 4,
+    /// Permission fault
     Permission = 12,
+    /// Synchronous External abort
     SyncExtAbort = 16,
+    /// Synchronous parity or ECC error on memory access
     SyncParityEccError = 24,
+    /// PC alignment fault
     PcAlignment = 33,
+    /// Debug exception
     Debug = 34,
 }
 
@@ -189,17 +246,18 @@ impl SysReg for Ifsr {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for Ifsr {}
+impl SysRegRead for Ifsr {}
 
 impl Ifsr {
     #[inline]
     /// Reads IFSR (*Instruction Fault Status Register*)
     pub fn read() -> Ifsr {
+        // Safety: it's OK to set bits with no accessors specified
         unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
     }
 }
 
-impl crate::register::SysRegWrite for Ifsr {}
+impl SysRegWrite for Ifsr {}
 
 impl Ifsr {
     #[inline]
diff --git a/aarch32-cpu/src/register/imp/imp_atcmregionr.rs b/aarch32-cpu/src/register/imp/imp_atcmregionr.rs
index d64b6bf5..6a4cb787 100644
--- a/aarch32-cpu/src/register/imp/imp_atcmregionr.rs
+++ b/aarch32-cpu/src/register/imp/imp_atcmregionr.rs
@@ -16,7 +16,7 @@ impl SysReg for ImpAtcmregionr {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for ImpAtcmregionr {}
+impl SysRegRead for ImpAtcmregionr {}
 
 impl ImpAtcmregionr {
     #[inline]
@@ -26,7 +26,7 @@ impl ImpAtcmregionr {
     }
 }
 
-impl crate::register::SysRegWrite for ImpAtcmregionr {}
+impl SysRegWrite for ImpAtcmregionr {}
 
 impl ImpAtcmregionr {
     #[inline]
diff --git a/aarch32-cpu/src/register/imp/imp_bpctlr.rs b/aarch32-cpu/src/register/imp/imp_bpctlr.rs
index 4f1a2826..5518cc69 100644
--- a/aarch32-cpu/src/register/imp/imp_bpctlr.rs
+++ b/aarch32-cpu/src/register/imp/imp_bpctlr.rs
@@ -16,7 +16,7 @@ impl SysReg for ImpBpctlr {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for ImpBpctlr {}
+impl SysRegRead for ImpBpctlr {}
 
 impl ImpBpctlr {
     #[inline]
@@ -26,7 +26,7 @@ impl ImpBpctlr {
     }
 }
 
-impl crate::register::SysRegWrite for ImpBpctlr {}
+impl SysRegWrite for ImpBpctlr {}
 
 impl ImpBpctlr {
     #[inline]
diff --git a/aarch32-cpu/src/register/imp/imp_btcmregionr.rs b/aarch32-cpu/src/register/imp/imp_btcmregionr.rs
index 60dccb0f..0396477b 100644
--- a/aarch32-cpu/src/register/imp/imp_btcmregionr.rs
+++ b/aarch32-cpu/src/register/imp/imp_btcmregionr.rs
@@ -16,7 +16,7 @@ impl SysReg for ImpBtcmregionr {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for ImpBtcmregionr {}
+impl SysRegRead for ImpBtcmregionr {}
 
 impl ImpBtcmregionr {
     #[inline]
@@ -26,7 +26,7 @@ impl ImpBtcmregionr {
     }
 }
 
-impl crate::register::SysRegWrite for ImpBtcmregionr {}
+impl SysRegWrite for ImpBtcmregionr {}
 
 impl ImpBtcmregionr {
     #[inline]
diff --git a/aarch32-cpu/src/register/imp/imp_buildoptr.rs b/aarch32-cpu/src/register/imp/imp_buildoptr.rs
index 6b173d71..1b13e423 100644
--- a/aarch32-cpu/src/register/imp/imp_buildoptr.rs
+++ b/aarch32-cpu/src/register/imp/imp_buildoptr.rs
@@ -16,7 +16,7 @@ impl SysReg for ImpBuildoptr {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for ImpBuildoptr {}
+impl SysRegRead for ImpBuildoptr {}
 
 impl ImpBuildoptr {
     #[inline]
diff --git a/aarch32-cpu/src/register/imp/imp_bustimeoutr.rs b/aarch32-cpu/src/register/imp/imp_bustimeoutr.rs
index 2fe9b22d..fb0ef5a8 100644
--- a/aarch32-cpu/src/register/imp/imp_bustimeoutr.rs
+++ b/aarch32-cpu/src/register/imp/imp_bustimeoutr.rs
@@ -16,7 +16,7 @@ impl SysReg for ImpBustimeoutr {
     const OP2: u32 = 2;
 }
 
-impl crate::register::SysRegRead for ImpBustimeoutr {}
+impl SysRegRead for ImpBustimeoutr {}
 
 impl ImpBustimeoutr {
     #[inline]
@@ -26,7 +26,7 @@ impl ImpBustimeoutr {
     }
 }
 
-impl crate::register::SysRegWrite for ImpBustimeoutr {}
+impl SysRegWrite for ImpBustimeoutr {}
 
 impl ImpBustimeoutr {
     #[inline]
diff --git a/aarch32-cpu/src/register/imp/imp_cbar.rs b/aarch32-cpu/src/register/imp/imp_cbar.rs
index 0d0384f3..28c26e72 100644
--- a/aarch32-cpu/src/register/imp/imp_cbar.rs
+++ b/aarch32-cpu/src/register/imp/imp_cbar.rs
@@ -39,7 +39,7 @@ impl core::fmt::Debug for ImpCbar {
 
 #[cfg(feature = "defmt")]
 impl defmt::Format for ImpCbar {
-    fn format(&self, f: defmt::Formatter) {
+    fn format(&self, f: defmt::Formatter<'_>) {
         defmt::write!(f, "IMP_CBAR {{ 0x{=usize:08x} }}", self.0 as usize)
     }
 }
diff --git a/aarch32-cpu/src/register/imp/imp_cdbgdcd.rs b/aarch32-cpu/src/register/imp/imp_cdbgdcd.rs
index 9abc129a..8c67f18a 100644
--- a/aarch32-cpu/src/register/imp/imp_cdbgdcd.rs
+++ b/aarch32-cpu/src/register/imp/imp_cdbgdcd.rs
@@ -1,8 +1,8 @@
-//! Code for managing IMP_CDBGDCD (*Data Cache Data Read Operation.*)
+//! Code for managing IMP_CDBGDCD (*Data Cache Data Read Operation*)
 
 use crate::register::{SysReg, SysRegWrite};
 
-/// IMP_CDBGDCD (*Data Cache Data Read Operation.*)
+/// IMP_CDBGDCD (*Data Cache Data Read Operation*)
 #[derive(Debug, Clone, Copy)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
@@ -16,11 +16,11 @@ impl SysReg for ImpCdbgdcd {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegWrite for ImpCdbgdcd {}
+impl SysRegWrite for ImpCdbgdcd {}
 
 impl ImpCdbgdcd {
     #[inline]
-    /// Writes IMP_CDBGDCD (*Data Cache Data Read Operation.*)
+    /// Writes IMP_CDBGDCD (*Data Cache Data Read Operation*)
     ///
     /// # Safety
     ///
diff --git a/aarch32-cpu/src/register/imp/imp_cdbgdci.rs b/aarch32-cpu/src/register/imp/imp_cdbgdci.rs
index e1dfb711..c50927cc 100644
--- a/aarch32-cpu/src/register/imp/imp_cdbgdci.rs
+++ b/aarch32-cpu/src/register/imp/imp_cdbgdci.rs
@@ -16,7 +16,7 @@ impl SysReg for ImpCdbgdci {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegWrite for ImpCdbgdci {}
+impl SysRegWrite for ImpCdbgdci {}
 
 impl ImpCdbgdci {
     #[inline]
diff --git a/aarch32-cpu/src/register/imp/imp_cdbgdct.rs b/aarch32-cpu/src/register/imp/imp_cdbgdct.rs
index 00194b37..c2429ab1 100644
--- a/aarch32-cpu/src/register/imp/imp_cdbgdct.rs
+++ b/aarch32-cpu/src/register/imp/imp_cdbgdct.rs
@@ -1,8 +1,8 @@
-//! Code for managing IMP_CDBGDCT (*Data Cache Tag Read Operation.*)
+//! Code for managing IMP_CDBGDCT (*Data Cache Tag Read Operation*)
 
 use crate::register::{SysReg, SysRegWrite};
 
-/// IMP_CDBGDCT (*Data Cache Tag Read Operation.*)
+/// IMP_CDBGDCT (*Data Cache Tag Read Operation*)
 #[derive(Debug, Clone, Copy)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
@@ -16,11 +16,11 @@ impl SysReg for ImpCdbgdct {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegWrite for ImpCdbgdct {}
+impl SysRegWrite for ImpCdbgdct {}
 
 impl ImpCdbgdct {
     #[inline]
-    /// Writes IMP_CDBGDCT (*Data Cache Tag Read Operation.*)
+    /// Writes IMP_CDBGDCT (*Data Cache Tag Read Operation*)
     ///
     /// # Safety
     ///
diff --git a/aarch32-cpu/src/register/imp/imp_cdbgdr0.rs b/aarch32-cpu/src/register/imp/imp_cdbgdr0.rs
index 1d3e87b7..3addcdc6 100644
--- a/aarch32-cpu/src/register/imp/imp_cdbgdr0.rs
+++ b/aarch32-cpu/src/register/imp/imp_cdbgdr0.rs
@@ -1,8 +1,8 @@
-//! Code for managing IMP_CDBGDR0 (*Cache Debug Data Register 0.*)
+//! Code for managing IMP_CDBGDR0 (*Cache Debug Data Register 0*)
 
 use crate::register::{SysReg, SysRegRead};
 
-/// IMP_CDBGDR0 (*Cache Debug Data Register 0.*)
+/// IMP_CDBGDR0 (*Cache Debug Data Register 0*)
 #[derive(Debug, Clone, Copy)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
@@ -16,11 +16,11 @@ impl SysReg for ImpCdbgdr0 {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for ImpCdbgdr0 {}
+impl SysRegRead for ImpCdbgdr0 {}
 
 impl ImpCdbgdr0 {
     #[inline]
-    /// Reads IMP_CDBGDR0 (*Cache Debug Data Register 0.*)
+    /// Reads IMP_CDBGDR0 (*Cache Debug Data Register 0*)
     pub fn read() -> ImpCdbgdr0 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
diff --git a/aarch32-cpu/src/register/imp/imp_cdbgdr1.rs b/aarch32-cpu/src/register/imp/imp_cdbgdr1.rs
index 128919dd..2451481e 100644
--- a/aarch32-cpu/src/register/imp/imp_cdbgdr1.rs
+++ b/aarch32-cpu/src/register/imp/imp_cdbgdr1.rs
@@ -1,8 +1,8 @@
-//! Code for managing IMP_CDBGDR1 (*Cache Debug Data Register 1.*)
+//! Code for managing IMP_CDBGDR1 (*Cache Debug Data Register 1*)
 
 use crate::register::{SysReg, SysRegRead};
 
-/// IMP_CDBGDR1 (*Cache Debug Data Register 1.*)
+/// IMP_CDBGDR1 (*Cache Debug Data Register 1*)
 #[derive(Debug, Clone, Copy)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
@@ -16,11 +16,11 @@ impl SysReg for ImpCdbgdr1 {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for ImpCdbgdr1 {}
+impl SysRegRead for ImpCdbgdr1 {}
 
 impl ImpCdbgdr1 {
     #[inline]
-    /// Reads IMP_CDBGDR1 (*Cache Debug Data Register 1.*)
+    /// Reads IMP_CDBGDR1 (*Cache Debug Data Register 1*)
     pub fn read() -> ImpCdbgdr1 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
diff --git a/aarch32-cpu/src/register/imp/imp_cdbgdr2.rs b/aarch32-cpu/src/register/imp/imp_cdbgdr2.rs
index 4fc3e103..5e13da75 100644
--- a/aarch32-cpu/src/register/imp/imp_cdbgdr2.rs
+++ b/aarch32-cpu/src/register/imp/imp_cdbgdr2.rs
@@ -1,8 +1,8 @@
-//! Code for managing IMP_CDBGDR2 (*Cache Debug Data Register 2.*)
+//! Code for managing IMP_CDBGDR2 (*Cache Debug Data Register 2*)
 
 use crate::register::{SysReg, SysRegRead};
 
-/// IMP_CDBGDR2 (*Cache Debug Data Register 2.*)
+/// IMP_CDBGDR2 (*Cache Debug Data Register 2*)
 #[derive(Debug, Clone, Copy)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
@@ -16,11 +16,11 @@ impl SysReg for ImpCdbgdr2 {
     const OP2: u32 = 2;
 }
 
-impl crate::register::SysRegRead for ImpCdbgdr2 {}
+impl SysRegRead for ImpCdbgdr2 {}
 
 impl ImpCdbgdr2 {
     #[inline]
-    /// Reads IMP_CDBGDR2 (*Cache Debug Data Register 2.*)
+    /// Reads IMP_CDBGDR2 (*Cache Debug Data Register 2*)
     pub fn read() -> ImpCdbgdr2 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
diff --git a/aarch32-cpu/src/register/imp/imp_cdbgicd.rs b/aarch32-cpu/src/register/imp/imp_cdbgicd.rs
index 9847be2b..fa11d75d 100644
--- a/aarch32-cpu/src/register/imp/imp_cdbgicd.rs
+++ b/aarch32-cpu/src/register/imp/imp_cdbgicd.rs
@@ -1,8 +1,8 @@
-//! Code for managing IMP_CDBGICD (*Instruction Cache Data Read Operation.*)
+//! Code for managing IMP_CDBGICD (*Instruction Cache Data Read Operation*)
 
 use crate::register::{SysReg, SysRegWrite};
 
-/// IMP_CDBGICD (*Instruction Cache Data Read Operation.*)
+/// IMP_CDBGICD (*Instruction Cache Data Read Operation*)
 #[derive(Debug, Clone, Copy)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
@@ -16,11 +16,11 @@ impl SysReg for ImpCdbgicd {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegWrite for ImpCdbgicd {}
+impl SysRegWrite for ImpCdbgicd {}
 
 impl ImpCdbgicd {
     #[inline]
-    /// Writes IMP_CDBGICD (*Instruction Cache Data Read Operation.*)
+    /// Writes IMP_CDBGICD (*Instruction Cache Data Read Operation*)
     ///
     /// # Safety
     ///
diff --git a/aarch32-cpu/src/register/imp/imp_cdbgict.rs b/aarch32-cpu/src/register/imp/imp_cdbgict.rs
index cab5cec1..9464242d 100644
--- a/aarch32-cpu/src/register/imp/imp_cdbgict.rs
+++ b/aarch32-cpu/src/register/imp/imp_cdbgict.rs
@@ -1,8 +1,8 @@
-//! Code for managing IMP_CDBGICT (*Instruction Cache Tag Read Operation.*)
+//! Code for managing IMP_CDBGICT (*Instruction Cache Tag Read Operation*)
 
 use crate::register::{SysReg, SysRegWrite};
 
-/// IMP_CDBGICT (*Instruction Cache Tag Read Operation.*)
+/// IMP_CDBGICT (*Instruction Cache Tag Read Operation*)
 #[derive(Debug, Clone, Copy)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
@@ -16,11 +16,11 @@ impl SysReg for ImpCdbgict {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegWrite for ImpCdbgict {}
+impl SysRegWrite for ImpCdbgict {}
 
 impl ImpCdbgict {
     #[inline]
-    /// Writes IMP_CDBGICT (*Instruction Cache Tag Read Operation.*)
+    /// Writes IMP_CDBGICT (*Instruction Cache Tag Read Operation*)
     ///
     /// # Safety
     ///
diff --git a/aarch32-cpu/src/register/imp/imp_csctlr.rs b/aarch32-cpu/src/register/imp/imp_csctlr.rs
index aa0d8d9e..b309f53a 100644
--- a/aarch32-cpu/src/register/imp/imp_csctlr.rs
+++ b/aarch32-cpu/src/register/imp/imp_csctlr.rs
@@ -16,7 +16,7 @@ impl SysReg for ImpCsctlr {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for ImpCsctlr {}
+impl SysRegRead for ImpCsctlr {}
 
 impl ImpCsctlr {
     #[inline]
@@ -26,7 +26,7 @@ impl ImpCsctlr {
     }
 }
 
-impl crate::register::SysRegWrite for ImpCsctlr {}
+impl SysRegWrite for ImpCsctlr {}
 
 impl ImpCsctlr {
     #[inline]
diff --git a/aarch32-cpu/src/register/imp/imp_ctcmregionr.rs b/aarch32-cpu/src/register/imp/imp_ctcmregionr.rs
index 6674163c..6d1b7c1c 100644
--- a/aarch32-cpu/src/register/imp/imp_ctcmregionr.rs
+++ b/aarch32-cpu/src/register/imp/imp_ctcmregionr.rs
@@ -16,7 +16,7 @@ impl SysReg for ImpCtcmregionr {
     const OP2: u32 = 2;
 }
 
-impl crate::register::SysRegRead for ImpCtcmregionr {}
+impl SysRegRead for ImpCtcmregionr {}
 
 impl ImpCtcmregionr {
     #[inline]
@@ -26,7 +26,7 @@ impl ImpCtcmregionr {
     }
 }
 
-impl crate::register::SysRegWrite for ImpCtcmregionr {}
+impl SysRegWrite for ImpCtcmregionr {}
 
 impl ImpCtcmregionr {
     #[inline]
diff --git a/aarch32-cpu/src/register/imp/imp_dcerr0.rs b/aarch32-cpu/src/register/imp/imp_dcerr0.rs
index 1ef40da1..556f750b 100644
--- a/aarch32-cpu/src/register/imp/imp_dcerr0.rs
+++ b/aarch32-cpu/src/register/imp/imp_dcerr0.rs
@@ -16,7 +16,7 @@ impl SysReg for ImpDcerr0 {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for ImpDcerr0 {}
+impl SysRegRead for ImpDcerr0 {}
 
 impl ImpDcerr0 {
     #[inline]
@@ -26,7 +26,7 @@ impl ImpDcerr0 {
     }
 }
 
-impl crate::register::SysRegWrite for ImpDcerr0 {}
+impl SysRegWrite for ImpDcerr0 {}
 
 impl ImpDcerr0 {
     #[inline]
diff --git a/aarch32-cpu/src/register/imp/imp_dcerr1.rs b/aarch32-cpu/src/register/imp/imp_dcerr1.rs
index 07b9e5cc..dc3b5959 100644
--- a/aarch32-cpu/src/register/imp/imp_dcerr1.rs
+++ b/aarch32-cpu/src/register/imp/imp_dcerr1.rs
@@ -16,7 +16,7 @@ impl SysReg for ImpDcerr1 {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for ImpDcerr1 {}
+impl SysRegRead for ImpDcerr1 {}
 
 impl ImpDcerr1 {
     #[inline]
@@ -26,7 +26,7 @@ impl ImpDcerr1 {
     }
 }
 
-impl crate::register::SysRegWrite for ImpDcerr1 {}
+impl SysRegWrite for ImpDcerr1 {}
 
 impl ImpDcerr1 {
     #[inline]
diff --git a/aarch32-cpu/src/register/imp/imp_flasherr0.rs b/aarch32-cpu/src/register/imp/imp_flasherr0.rs
index ebdea8d9..e92b242f 100644
--- a/aarch32-cpu/src/register/imp/imp_flasherr0.rs
+++ b/aarch32-cpu/src/register/imp/imp_flasherr0.rs
@@ -16,7 +16,7 @@ impl SysReg for ImpFlasherr0 {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for ImpFlasherr0 {}
+impl SysRegRead for ImpFlasherr0 {}
 
 impl ImpFlasherr0 {
     #[inline]
@@ -26,7 +26,7 @@ impl ImpFlasherr0 {
     }
 }
 
-impl crate::register::SysRegWrite for ImpFlasherr0 {}
+impl SysRegWrite for ImpFlasherr0 {}
 
 impl ImpFlasherr0 {
     #[inline]
diff --git a/aarch32-cpu/src/register/imp/imp_flasherr1.rs b/aarch32-cpu/src/register/imp/imp_flasherr1.rs
index 1fe83787..c68b8ef8 100644
--- a/aarch32-cpu/src/register/imp/imp_flasherr1.rs
+++ b/aarch32-cpu/src/register/imp/imp_flasherr1.rs
@@ -16,7 +16,7 @@ impl SysReg for ImpFlasherr1 {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for ImpFlasherr1 {}
+impl SysRegRead for ImpFlasherr1 {}
 
 impl ImpFlasherr1 {
     #[inline]
@@ -26,7 +26,7 @@ impl ImpFlasherr1 {
     }
 }
 
-impl crate::register::SysRegWrite for ImpFlasherr1 {}
+impl SysRegWrite for ImpFlasherr1 {}
 
 impl ImpFlasherr1 {
     #[inline]
diff --git a/aarch32-cpu/src/register/imp/imp_flashifregionr.rs b/aarch32-cpu/src/register/imp/imp_flashifregionr.rs
index 8b9290e0..c0701e6e 100644
--- a/aarch32-cpu/src/register/imp/imp_flashifregionr.rs
+++ b/aarch32-cpu/src/register/imp/imp_flashifregionr.rs
@@ -16,7 +16,7 @@ impl SysReg for ImpFlashifregionr {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for ImpFlashifregionr {}
+impl SysRegRead for ImpFlashifregionr {}
 
 impl ImpFlashifregionr {
     #[inline]
@@ -26,7 +26,7 @@ impl ImpFlashifregionr {
     }
 }
 
-impl crate::register::SysRegWrite for ImpFlashifregionr {}
+impl SysRegWrite for ImpFlashifregionr {}
 
 impl ImpFlashifregionr {
     #[inline]
diff --git a/aarch32-cpu/src/register/imp/imp_icerr0.rs b/aarch32-cpu/src/register/imp/imp_icerr0.rs
index cdfb24fa..21e9f3e0 100644
--- a/aarch32-cpu/src/register/imp/imp_icerr0.rs
+++ b/aarch32-cpu/src/register/imp/imp_icerr0.rs
@@ -16,7 +16,7 @@ impl SysReg for ImpIcerr0 {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for ImpIcerr0 {}
+impl SysRegRead for ImpIcerr0 {}
 
 impl ImpIcerr0 {
     #[inline]
@@ -26,7 +26,7 @@ impl ImpIcerr0 {
     }
 }
 
-impl crate::register::SysRegWrite for ImpIcerr0 {}
+impl SysRegWrite for ImpIcerr0 {}
 
 impl ImpIcerr0 {
     #[inline]
diff --git a/aarch32-cpu/src/register/imp/imp_icerr1.rs b/aarch32-cpu/src/register/imp/imp_icerr1.rs
index 12da076c..dd12150a 100644
--- a/aarch32-cpu/src/register/imp/imp_icerr1.rs
+++ b/aarch32-cpu/src/register/imp/imp_icerr1.rs
@@ -16,7 +16,7 @@ impl SysReg for ImpIcerr1 {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for ImpIcerr1 {}
+impl SysRegRead for ImpIcerr1 {}
 
 impl ImpIcerr1 {
     #[inline]
@@ -26,7 +26,7 @@ impl ImpIcerr1 {
     }
 }
 
-impl crate::register::SysRegWrite for ImpIcerr1 {}
+impl SysRegWrite for ImpIcerr1 {}
 
 impl ImpIcerr1 {
     #[inline]
diff --git a/aarch32-cpu/src/register/imp/imp_intmonr.rs b/aarch32-cpu/src/register/imp/imp_intmonr.rs
index 86315ab8..efcc8328 100644
--- a/aarch32-cpu/src/register/imp/imp_intmonr.rs
+++ b/aarch32-cpu/src/register/imp/imp_intmonr.rs
@@ -16,7 +16,7 @@ impl SysReg for ImpIntmonr {
     const OP2: u32 = 4;
 }
 
-impl crate::register::SysRegRead for ImpIntmonr {}
+impl SysRegRead for ImpIntmonr {}
 
 impl ImpIntmonr {
     #[inline]
@@ -26,7 +26,7 @@ impl ImpIntmonr {
     }
 }
 
-impl crate::register::SysRegWrite for ImpIntmonr {}
+impl SysRegWrite for ImpIntmonr {}
 
 impl ImpIntmonr {
     #[inline]
diff --git a/aarch32-cpu/src/register/imp/imp_memprotctlr.rs b/aarch32-cpu/src/register/imp/imp_memprotctlr.rs
index 14960247..44fff4b2 100644
--- a/aarch32-cpu/src/register/imp/imp_memprotctlr.rs
+++ b/aarch32-cpu/src/register/imp/imp_memprotctlr.rs
@@ -16,7 +16,7 @@ impl SysReg for ImpMemprotctlr {
     const OP2: u32 = 2;
 }
 
-impl crate::register::SysRegRead for ImpMemprotctlr {}
+impl SysRegRead for ImpMemprotctlr {}
 
 impl ImpMemprotctlr {
     #[inline]
@@ -26,7 +26,7 @@ impl ImpMemprotctlr {
     }
 }
 
-impl crate::register::SysRegWrite for ImpMemprotctlr {}
+impl SysRegWrite for ImpMemprotctlr {}
 
 impl ImpMemprotctlr {
     #[inline]
diff --git a/aarch32-cpu/src/register/imp/imp_periphpregionr.rs b/aarch32-cpu/src/register/imp/imp_periphpregionr.rs
index 51643758..6f2c18c6 100644
--- a/aarch32-cpu/src/register/imp/imp_periphpregionr.rs
+++ b/aarch32-cpu/src/register/imp/imp_periphpregionr.rs
@@ -16,7 +16,7 @@ impl SysReg for ImpPeriphpregionr {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for ImpPeriphpregionr {}
+impl SysRegRead for ImpPeriphpregionr {}
 
 impl ImpPeriphpregionr {
     #[inline]
@@ -26,7 +26,7 @@ impl ImpPeriphpregionr {
     }
 }
 
-impl crate::register::SysRegWrite for ImpPeriphpregionr {}
+impl SysRegWrite for ImpPeriphpregionr {}
 
 impl ImpPeriphpregionr {
     #[inline]
diff --git a/aarch32-cpu/src/register/imp/imp_pinoptr.rs b/aarch32-cpu/src/register/imp/imp_pinoptr.rs
index e2b7b6ad..46c9a51a 100644
--- a/aarch32-cpu/src/register/imp/imp_pinoptr.rs
+++ b/aarch32-cpu/src/register/imp/imp_pinoptr.rs
@@ -16,7 +16,7 @@ impl SysReg for ImpPinoptr {
     const OP2: u32 = 7;
 }
 
-impl crate::register::SysRegRead for ImpPinoptr {}
+impl SysRegRead for ImpPinoptr {}
 
 impl ImpPinoptr {
     #[inline]
diff --git a/aarch32-cpu/src/register/imp/imp_qosr.rs b/aarch32-cpu/src/register/imp/imp_qosr.rs
index d8e74e75..896af68e 100644
--- a/aarch32-cpu/src/register/imp/imp_qosr.rs
+++ b/aarch32-cpu/src/register/imp/imp_qosr.rs
@@ -16,7 +16,7 @@ impl SysReg for ImpQosr {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for ImpQosr {}
+impl SysRegRead for ImpQosr {}
 
 impl ImpQosr {
     #[inline]
@@ -26,7 +26,7 @@ impl ImpQosr {
     }
 }
 
-impl crate::register::SysRegWrite for ImpQosr {}
+impl SysRegWrite for ImpQosr {}
 
 impl ImpQosr {
     #[inline]
diff --git a/aarch32-cpu/src/register/imp/imp_slavepctlr.rs b/aarch32-cpu/src/register/imp/imp_slavepctlr.rs
index f259a0d1..658e269d 100644
--- a/aarch32-cpu/src/register/imp/imp_slavepctlr.rs
+++ b/aarch32-cpu/src/register/imp/imp_slavepctlr.rs
@@ -16,7 +16,7 @@ impl SysReg for ImpSlavepctlr {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for ImpSlavepctlr {}
+impl SysRegRead for ImpSlavepctlr {}
 
 impl ImpSlavepctlr {
     #[inline]
@@ -26,7 +26,7 @@ impl ImpSlavepctlr {
     }
 }
 
-impl crate::register::SysRegWrite for ImpSlavepctlr {}
+impl SysRegWrite for ImpSlavepctlr {}
 
 impl ImpSlavepctlr {
     #[inline]
diff --git a/aarch32-cpu/src/register/imp/imp_tcmerr0.rs b/aarch32-cpu/src/register/imp/imp_tcmerr0.rs
index b98ccad4..fdf926a4 100644
--- a/aarch32-cpu/src/register/imp/imp_tcmerr0.rs
+++ b/aarch32-cpu/src/register/imp/imp_tcmerr0.rs
@@ -16,7 +16,7 @@ impl SysReg for ImpTcmerr0 {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for ImpTcmerr0 {}
+impl SysRegRead for ImpTcmerr0 {}
 
 impl ImpTcmerr0 {
     #[inline]
@@ -26,7 +26,7 @@ impl ImpTcmerr0 {
     }
 }
 
-impl crate::register::SysRegWrite for ImpTcmerr0 {}
+impl SysRegWrite for ImpTcmerr0 {}
 
 impl ImpTcmerr0 {
     #[inline]
diff --git a/aarch32-cpu/src/register/imp/imp_tcmerr1.rs b/aarch32-cpu/src/register/imp/imp_tcmerr1.rs
index 99fea8e3..1bd9843c 100644
--- a/aarch32-cpu/src/register/imp/imp_tcmerr1.rs
+++ b/aarch32-cpu/src/register/imp/imp_tcmerr1.rs
@@ -16,7 +16,7 @@ impl SysReg for ImpTcmerr1 {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for ImpTcmerr1 {}
+impl SysRegRead for ImpTcmerr1 {}
 
 impl ImpTcmerr1 {
     #[inline]
@@ -26,7 +26,7 @@ impl ImpTcmerr1 {
     }
 }
 
-impl crate::register::SysRegWrite for ImpTcmerr1 {}
+impl SysRegWrite for ImpTcmerr1 {}
 
 impl ImpTcmerr1 {
     #[inline]
diff --git a/aarch32-cpu/src/register/imp/imp_tcmsyndr0.rs b/aarch32-cpu/src/register/imp/imp_tcmsyndr0.rs
index 38be2914..4886b60e 100644
--- a/aarch32-cpu/src/register/imp/imp_tcmsyndr0.rs
+++ b/aarch32-cpu/src/register/imp/imp_tcmsyndr0.rs
@@ -16,7 +16,7 @@ impl SysReg for ImpTcmsyndr0 {
     const OP2: u32 = 2;
 }
 
-impl crate::register::SysRegRead for ImpTcmsyndr0 {}
+impl SysRegRead for ImpTcmsyndr0 {}
 
 impl ImpTcmsyndr0 {
     #[inline]
diff --git a/aarch32-cpu/src/register/imp/imp_tcmsyndr1.rs b/aarch32-cpu/src/register/imp/imp_tcmsyndr1.rs
index e9ba5907..ef0ae173 100644
--- a/aarch32-cpu/src/register/imp/imp_tcmsyndr1.rs
+++ b/aarch32-cpu/src/register/imp/imp_tcmsyndr1.rs
@@ -16,7 +16,7 @@ impl SysReg for ImpTcmsyndr1 {
     const OP2: u32 = 3;
 }
 
-impl crate::register::SysRegRead for ImpTcmsyndr1 {}
+impl SysRegRead for ImpTcmsyndr1 {}
 
 impl ImpTcmsyndr1 {
     #[inline]
diff --git a/aarch32-cpu/src/register/imp/imp_testr0.rs b/aarch32-cpu/src/register/imp/imp_testr0.rs
index 1948ad1f..381d97ea 100644
--- a/aarch32-cpu/src/register/imp/imp_testr0.rs
+++ b/aarch32-cpu/src/register/imp/imp_testr0.rs
@@ -16,7 +16,7 @@ impl SysReg for ImpTestr0 {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for ImpTestr0 {}
+impl SysRegRead for ImpTestr0 {}
 
 impl ImpTestr0 {
     #[inline]
diff --git a/aarch32-cpu/src/register/iracr.rs b/aarch32-cpu/src/register/iracr.rs
index ae640f09..502e455c 100644
--- a/aarch32-cpu/src/register/iracr.rs
+++ b/aarch32-cpu/src/register/iracr.rs
@@ -36,7 +36,7 @@ impl SysReg for Iracr {
     const OP2: u32 = 5;
 }
 
-impl crate::register::SysRegRead for Iracr {}
+impl SysRegRead for Iracr {}
 
 impl Iracr {
     #[inline]
@@ -44,11 +44,12 @@ impl Iracr {
     ///
     /// Set RGNR to control which region this reads.
     pub fn read() -> Iracr {
+        // Safety: it's OK to set bits with no accessors specified
         unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
     }
 }
 
-impl crate::register::SysRegWrite for Iracr {}
+impl SysRegWrite for Iracr {}
 
 impl Iracr {
     #[inline]
diff --git a/aarch32-cpu/src/register/irbar.rs b/aarch32-cpu/src/register/irbar.rs
index db704204..58ba943e 100644
--- a/aarch32-cpu/src/register/irbar.rs
+++ b/aarch32-cpu/src/register/irbar.rs
@@ -17,7 +17,7 @@ impl SysReg for Irbar {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for Irbar {}
+impl SysRegRead for Irbar {}
 
 impl Irbar {
     #[inline]
@@ -29,7 +29,7 @@ impl Irbar {
     }
 }
 
-impl crate::register::SysRegWrite for Irbar {}
+impl SysRegWrite for Irbar {}
 
 impl Irbar {
     #[inline]
diff --git a/aarch32-cpu/src/register/irsr.rs b/aarch32-cpu/src/register/irsr.rs
index 5e249923..cbe889fa 100644
--- a/aarch32-cpu/src/register/irsr.rs
+++ b/aarch32-cpu/src/register/irsr.rs
@@ -34,7 +34,7 @@ impl SysReg for Irsr {
     const OP2: u32 = 3;
 }
 
-impl crate::register::SysRegRead for Irsr {}
+impl SysRegRead for Irsr {}
 
 impl Irsr {
     #[inline]
@@ -42,11 +42,12 @@ impl Irsr {
     ///
     /// Set RGNR to control which region this reads.
     pub fn read() -> Irsr {
+        // Safety: it's OK to set bits with no accessors specified
         unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
     }
 }
 
-impl crate::register::SysRegWrite for Irsr {}
+impl SysRegWrite for Irsr {}
 
 impl Irsr {
     #[inline]
diff --git a/aarch32-cpu/src/register/mair0.rs b/aarch32-cpu/src/register/mair0.rs
index 51ec500b..f056ea29 100644
--- a/aarch32-cpu/src/register/mair0.rs
+++ b/aarch32-cpu/src/register/mair0.rs
@@ -25,7 +25,7 @@ impl SysReg for Mair0 {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for Mair0 {}
+impl SysRegRead for Mair0 {}
 
 impl Mair0 {
     #[inline]
@@ -35,7 +35,7 @@ impl Mair0 {
     }
 }
 
-impl crate::register::SysRegWrite for Mair0 {}
+impl SysRegWrite for Mair0 {}
 
 impl Mair0 {
     #[inline]
diff --git a/aarch32-cpu/src/register/mair1.rs b/aarch32-cpu/src/register/mair1.rs
index 95081c73..1f5f28be 100644
--- a/aarch32-cpu/src/register/mair1.rs
+++ b/aarch32-cpu/src/register/mair1.rs
@@ -17,7 +17,7 @@ impl SysReg for Mair1 {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for Mair1 {}
+impl SysRegRead for Mair1 {}
 
 impl Mair1 {
     #[inline]
@@ -27,7 +27,7 @@ impl Mair1 {
     }
 }
 
-impl crate::register::SysRegWrite for Mair1 {}
+impl SysRegWrite for Mair1 {}
 
 impl Mair1 {
     #[inline]
diff --git a/aarch32-cpu/src/register/midr.rs b/aarch32-cpu/src/register/midr.rs
index 055c2746..62e56c04 100644
--- a/aarch32-cpu/src/register/midr.rs
+++ b/aarch32-cpu/src/register/midr.rs
@@ -1,6 +1,6 @@
 //! Code for managing MIDR (*Main ID Register*)
 
-use arbitrary_int::{u12, u4};
+use arbitrary_int::{u4, u12};
 
 use super::{SysReg, SysRegRead};
 
@@ -45,14 +45,25 @@ impl Midr {
 
 impl core::fmt::Debug for Midr {
     fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        write!(f, "MIDR {{ implementer=0x{:02x} variant=0x{:x} arch=0x{:x} part_no=0x{:03x} rev=0x{:x} }}",
-        self.implementer(), self.variant(), self.arch(), self.part_no(), self.rev())
+        write!(
+            f,
+            "MIDR {{ implementer=0x{:02x} variant=0x{:x} arch=0x{:x} part_no=0x{:03x} rev=0x{:x} }}",
+            self.implementer(),
+            self.variant(),
+            self.arch(),
+            self.part_no(),
+            self.rev()
+        )
     }
 }
 
 #[cfg(feature = "defmt")]
 impl defmt::Format for Midr {
-    fn format(&self, f: defmt::Formatter) {
-        defmt::write!(f, "MIDR {{ implementer=0x{0=24..32:02x} variant=0x{0=20..24:x} arch=0x{0=16..20:x} part_no=0x{0=4..16:03x} rev=0x{0=0..4:x} }}", self.raw_value())
+    fn format(&self, f: defmt::Formatter<'_>) {
+        defmt::write!(
+            f,
+            "MIDR {{ implementer=0x{0=24..32:02x} variant=0x{0=20..24:x} arch=0x{0=16..20:x} part_no=0x{0=4..16:03x} rev=0x{0=0..4:x} }}",
+            self.raw_value()
+        )
     }
 }
diff --git a/aarch32-cpu/src/register/mod.rs b/aarch32-cpu/src/register/mod.rs
index 94a79de4..bde57d65 100644
--- a/aarch32-cpu/src/register/mod.rs
+++ b/aarch32-cpu/src/register/mod.rs
@@ -1,4 +1,6 @@
-//! CPU system register access code
+//! Defines various AArch32 system registers
+//!
+//! These are all ready using Co-Processor read/write instructions
 
 pub mod actlr;
 pub mod actlr2;
@@ -204,9 +206,10 @@ pub use vmpidr::Vmpidr;
 pub use vpidr::Vpidr;
 pub use vsctlr::Vsctlr;
 
-#[cfg(any(test, doc, arm_architecture = "v8-r"))]
-pub mod armv8r;
-#[cfg(any(test, doc, arm_architecture = "v8-r"))]
+#[cfg(any(test, arm_architecture = "v8-r"))]
+mod armv8r;
+#[cfg(any(test, arm_architecture = "v8-r"))]
+#[doc(inline)]
 pub use armv8r::*;
 
 #[cfg(any(test, doc, arm_architecture = "v7-a", arm_architecture = "v8-r"))]
diff --git a/aarch32-cpu/src/register/mpidr.rs b/aarch32-cpu/src/register/mpidr.rs
index 2495b24d..c011c52f 100644
--- a/aarch32-cpu/src/register/mpidr.rs
+++ b/aarch32-cpu/src/register/mpidr.rs
@@ -16,7 +16,7 @@ impl SysReg for Mpidr {
     const OP2: u32 = 5;
 }
 
-impl crate::register::SysRegRead for Mpidr {}
+impl SysRegRead for Mpidr {}
 
 impl Mpidr {
     #[inline]
diff --git a/aarch32-cpu/src/register/mpuir.rs b/aarch32-cpu/src/register/mpuir.rs
index f28df795..53ef9a38 100644
--- a/aarch32-cpu/src/register/mpuir.rs
+++ b/aarch32-cpu/src/register/mpuir.rs
@@ -27,12 +27,13 @@ impl SysReg for Mpuir {
     const OP2: u32 = 4;
 }
 
-impl crate::register::SysRegRead for Mpuir {}
+impl SysRegRead for Mpuir {}
 
 impl Mpuir {
     #[inline]
     /// Reads MPUIR (*MPU Type Register*)
     pub fn read() -> Mpuir {
+        // Safety: it's OK to set bits with no accessors specified
         unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
     }
 }
@@ -49,7 +50,7 @@ impl core::fmt::Debug for Mpuir {
 
 #[cfg(feature = "defmt")]
 impl defmt::Format for Mpuir {
-    fn format(&self, f: defmt::Formatter) {
+    fn format(&self, f: defmt::Formatter<'_>) {
         defmt::write!(
             f,
             "MPUIR {{ iregions={=u8}, dregions={=u8}, non_unified={=bool} }}",
diff --git a/aarch32-cpu/src/register/nsacr.rs b/aarch32-cpu/src/register/nsacr.rs
index d9806578..9aa3f901 100644
--- a/aarch32-cpu/src/register/nsacr.rs
+++ b/aarch32-cpu/src/register/nsacr.rs
@@ -16,7 +16,7 @@ impl SysReg for Nsacr {
     const OP2: u32 = 2;
 }
 
-impl crate::register::SysRegRead for Nsacr {}
+impl SysRegRead for Nsacr {}
 
 impl Nsacr {
     #[inline]
diff --git a/aarch32-cpu/src/register/par.rs b/aarch32-cpu/src/register/par.rs
index ac29f584..c2a91954 100644
--- a/aarch32-cpu/src/register/par.rs
+++ b/aarch32-cpu/src/register/par.rs
@@ -16,7 +16,7 @@ impl SysReg for Par {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for Par {}
+impl SysRegRead for Par {}
 
 impl Par {
     #[inline]
@@ -26,7 +26,7 @@ impl Par {
     }
 }
 
-impl crate::register::SysRegWrite for Par {}
+impl SysRegWrite for Par {}
 
 impl Par {
     #[inline]
diff --git a/aarch32-cpu/src/register/pmccfiltr.rs b/aarch32-cpu/src/register/pmccfiltr.rs
index 2dcd5ba7..8ea2304b 100644
--- a/aarch32-cpu/src/register/pmccfiltr.rs
+++ b/aarch32-cpu/src/register/pmccfiltr.rs
@@ -16,7 +16,7 @@ impl SysReg for Pmccfiltr {
     const OP2: u32 = 7;
 }
 
-impl crate::register::SysRegRead for Pmccfiltr {}
+impl SysRegRead for Pmccfiltr {}
 
 impl Pmccfiltr {
     #[inline]
@@ -26,7 +26,7 @@ impl Pmccfiltr {
     }
 }
 
-impl crate::register::SysRegWrite for Pmccfiltr {}
+impl SysRegWrite for Pmccfiltr {}
 
 impl Pmccfiltr {
     #[inline]
diff --git a/aarch32-cpu/src/register/pmccntr.rs b/aarch32-cpu/src/register/pmccntr.rs
index 63ab0dc9..cd83af6d 100644
--- a/aarch32-cpu/src/register/pmccntr.rs
+++ b/aarch32-cpu/src/register/pmccntr.rs
@@ -16,7 +16,7 @@ impl SysReg for Pmccntr {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for Pmccntr {}
+impl SysRegRead for Pmccntr {}
 
 impl Pmccntr {
     #[inline]
@@ -26,7 +26,7 @@ impl Pmccntr {
     }
 }
 
-impl crate::register::SysRegWrite for Pmccntr {}
+impl SysRegWrite for Pmccntr {}
 
 impl Pmccntr {
     #[inline]
diff --git a/aarch32-cpu/src/register/pmceid0.rs b/aarch32-cpu/src/register/pmceid0.rs
index dd87cd76..dcd002b3 100644
--- a/aarch32-cpu/src/register/pmceid0.rs
+++ b/aarch32-cpu/src/register/pmceid0.rs
@@ -16,7 +16,7 @@ impl SysReg for Pmceid0 {
     const OP2: u32 = 6;
 }
 
-impl crate::register::SysRegRead for Pmceid0 {}
+impl SysRegRead for Pmceid0 {}
 
 impl Pmceid0 {
     #[inline]
diff --git a/aarch32-cpu/src/register/pmceid1.rs b/aarch32-cpu/src/register/pmceid1.rs
index 2d250970..719a0cb0 100644
--- a/aarch32-cpu/src/register/pmceid1.rs
+++ b/aarch32-cpu/src/register/pmceid1.rs
@@ -16,7 +16,7 @@ impl SysReg for Pmceid1 {
     const OP2: u32 = 7;
 }
 
-impl crate::register::SysRegRead for Pmceid1 {}
+impl SysRegRead for Pmceid1 {}
 
 impl Pmceid1 {
     #[inline]
diff --git a/aarch32-cpu/src/register/pmcntenclr.rs b/aarch32-cpu/src/register/pmcntenclr.rs
index 3eceb9dc..74347e44 100644
--- a/aarch32-cpu/src/register/pmcntenclr.rs
+++ b/aarch32-cpu/src/register/pmcntenclr.rs
@@ -16,7 +16,7 @@ impl SysReg for Pmcntenclr {
     const OP2: u32 = 2;
 }
 
-impl crate::register::SysRegRead for Pmcntenclr {}
+impl SysRegRead for Pmcntenclr {}
 
 impl Pmcntenclr {
     #[inline]
@@ -26,7 +26,7 @@ impl Pmcntenclr {
     }
 }
 
-impl crate::register::SysRegWrite for Pmcntenclr {}
+impl SysRegWrite for Pmcntenclr {}
 
 impl Pmcntenclr {
     #[inline]
diff --git a/aarch32-cpu/src/register/pmcntenset.rs b/aarch32-cpu/src/register/pmcntenset.rs
index dfc07bfb..50e8f4fb 100644
--- a/aarch32-cpu/src/register/pmcntenset.rs
+++ b/aarch32-cpu/src/register/pmcntenset.rs
@@ -16,7 +16,7 @@ impl SysReg for Pmcntenset {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for Pmcntenset {}
+impl SysRegRead for Pmcntenset {}
 
 impl Pmcntenset {
     #[inline]
@@ -26,7 +26,7 @@ impl Pmcntenset {
     }
 }
 
-impl crate::register::SysRegWrite for Pmcntenset {}
+impl SysRegWrite for Pmcntenset {}
 
 impl Pmcntenset {
     #[inline]
diff --git a/aarch32-cpu/src/register/pmcr.rs b/aarch32-cpu/src/register/pmcr.rs
index df22c6c0..fa1863ea 100644
--- a/aarch32-cpu/src/register/pmcr.rs
+++ b/aarch32-cpu/src/register/pmcr.rs
@@ -16,7 +16,7 @@ impl SysReg for Pmcr {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for Pmcr {}
+impl SysRegRead for Pmcr {}
 
 impl Pmcr {
     #[inline]
@@ -26,7 +26,7 @@ impl Pmcr {
     }
 }
 
-impl crate::register::SysRegWrite for Pmcr {}
+impl SysRegWrite for Pmcr {}
 
 impl Pmcr {
     #[inline]
diff --git a/aarch32-cpu/src/register/pmevcntr0.rs b/aarch32-cpu/src/register/pmevcntr0.rs
index cbdf038c..23cbd5aa 100644
--- a/aarch32-cpu/src/register/pmevcntr0.rs
+++ b/aarch32-cpu/src/register/pmevcntr0.rs
@@ -16,7 +16,7 @@ impl SysReg for Pmevcntr0 {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for Pmevcntr0 {}
+impl SysRegRead for Pmevcntr0 {}
 
 impl Pmevcntr0 {
     #[inline]
@@ -26,7 +26,7 @@ impl Pmevcntr0 {
     }
 }
 
-impl crate::register::SysRegWrite for Pmevcntr0 {}
+impl SysRegWrite for Pmevcntr0 {}
 
 impl Pmevcntr0 {
     #[inline]
diff --git a/aarch32-cpu/src/register/pmevcntr1.rs b/aarch32-cpu/src/register/pmevcntr1.rs
index 4f0b0cb2..0f9125a9 100644
--- a/aarch32-cpu/src/register/pmevcntr1.rs
+++ b/aarch32-cpu/src/register/pmevcntr1.rs
@@ -16,7 +16,7 @@ impl SysReg for Pmevcntr1 {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for Pmevcntr1 {}
+impl SysRegRead for Pmevcntr1 {}
 
 impl Pmevcntr1 {
     #[inline]
@@ -26,7 +26,7 @@ impl Pmevcntr1 {
     }
 }
 
-impl crate::register::SysRegWrite for Pmevcntr1 {}
+impl SysRegWrite for Pmevcntr1 {}
 
 impl Pmevcntr1 {
     #[inline]
diff --git a/aarch32-cpu/src/register/pmevcntr2.rs b/aarch32-cpu/src/register/pmevcntr2.rs
index d2c9bc97..9fae70dc 100644
--- a/aarch32-cpu/src/register/pmevcntr2.rs
+++ b/aarch32-cpu/src/register/pmevcntr2.rs
@@ -16,7 +16,7 @@ impl SysReg for Pmevcntr2 {
     const OP2: u32 = 2;
 }
 
-impl crate::register::SysRegRead for Pmevcntr2 {}
+impl SysRegRead for Pmevcntr2 {}
 
 impl Pmevcntr2 {
     #[inline]
@@ -26,7 +26,7 @@ impl Pmevcntr2 {
     }
 }
 
-impl crate::register::SysRegWrite for Pmevcntr2 {}
+impl SysRegWrite for Pmevcntr2 {}
 
 impl Pmevcntr2 {
     #[inline]
diff --git a/aarch32-cpu/src/register/pmevcntr3.rs b/aarch32-cpu/src/register/pmevcntr3.rs
index 4ce3865e..dbe87663 100644
--- a/aarch32-cpu/src/register/pmevcntr3.rs
+++ b/aarch32-cpu/src/register/pmevcntr3.rs
@@ -16,7 +16,7 @@ impl SysReg for Pmevcntr3 {
     const OP2: u32 = 3;
 }
 
-impl crate::register::SysRegRead for Pmevcntr3 {}
+impl SysRegRead for Pmevcntr3 {}
 
 impl Pmevcntr3 {
     #[inline]
@@ -26,7 +26,7 @@ impl Pmevcntr3 {
     }
 }
 
-impl crate::register::SysRegWrite for Pmevcntr3 {}
+impl SysRegWrite for Pmevcntr3 {}
 
 impl Pmevcntr3 {
     #[inline]
diff --git a/aarch32-cpu/src/register/pmevtyper0.rs b/aarch32-cpu/src/register/pmevtyper0.rs
index aad9168e..1a567308 100644
--- a/aarch32-cpu/src/register/pmevtyper0.rs
+++ b/aarch32-cpu/src/register/pmevtyper0.rs
@@ -16,7 +16,7 @@ impl SysReg for Pmevtyper0 {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for Pmevtyper0 {}
+impl SysRegRead for Pmevtyper0 {}
 
 impl Pmevtyper0 {
     #[inline]
@@ -26,7 +26,7 @@ impl Pmevtyper0 {
     }
 }
 
-impl crate::register::SysRegWrite for Pmevtyper0 {}
+impl SysRegWrite for Pmevtyper0 {}
 
 impl Pmevtyper0 {
     #[inline]
diff --git a/aarch32-cpu/src/register/pmevtyper1.rs b/aarch32-cpu/src/register/pmevtyper1.rs
index 3bf58221..14f03281 100644
--- a/aarch32-cpu/src/register/pmevtyper1.rs
+++ b/aarch32-cpu/src/register/pmevtyper1.rs
@@ -16,7 +16,7 @@ impl SysReg for Pmevtyper1 {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for Pmevtyper1 {}
+impl SysRegRead for Pmevtyper1 {}
 
 impl Pmevtyper1 {
     #[inline]
@@ -26,7 +26,7 @@ impl Pmevtyper1 {
     }
 }
 
-impl crate::register::SysRegWrite for Pmevtyper1 {}
+impl SysRegWrite for Pmevtyper1 {}
 
 impl Pmevtyper1 {
     #[inline]
diff --git a/aarch32-cpu/src/register/pmevtyper2.rs b/aarch32-cpu/src/register/pmevtyper2.rs
index 8207fe31..554645a4 100644
--- a/aarch32-cpu/src/register/pmevtyper2.rs
+++ b/aarch32-cpu/src/register/pmevtyper2.rs
@@ -16,7 +16,7 @@ impl SysReg for Pmevtyper2 {
     const OP2: u32 = 2;
 }
 
-impl crate::register::SysRegRead for Pmevtyper2 {}
+impl SysRegRead for Pmevtyper2 {}
 
 impl Pmevtyper2 {
     #[inline]
@@ -26,7 +26,7 @@ impl Pmevtyper2 {
     }
 }
 
-impl crate::register::SysRegWrite for Pmevtyper2 {}
+impl SysRegWrite for Pmevtyper2 {}
 
 impl Pmevtyper2 {
     #[inline]
diff --git a/aarch32-cpu/src/register/pmevtyper3.rs b/aarch32-cpu/src/register/pmevtyper3.rs
index b5d4bc64..51576536 100644
--- a/aarch32-cpu/src/register/pmevtyper3.rs
+++ b/aarch32-cpu/src/register/pmevtyper3.rs
@@ -16,7 +16,7 @@ impl SysReg for Pmevtyper3 {
     const OP2: u32 = 3;
 }
 
-impl crate::register::SysRegRead for Pmevtyper3 {}
+impl SysRegRead for Pmevtyper3 {}
 
 impl Pmevtyper3 {
     #[inline]
@@ -26,7 +26,7 @@ impl Pmevtyper3 {
     }
 }
 
-impl crate::register::SysRegWrite for Pmevtyper3 {}
+impl SysRegWrite for Pmevtyper3 {}
 
 impl Pmevtyper3 {
     #[inline]
diff --git a/aarch32-cpu/src/register/pmintenclr.rs b/aarch32-cpu/src/register/pmintenclr.rs
index f82eac07..78522d65 100644
--- a/aarch32-cpu/src/register/pmintenclr.rs
+++ b/aarch32-cpu/src/register/pmintenclr.rs
@@ -16,7 +16,7 @@ impl SysReg for Pmintenclr {
     const OP2: u32 = 2;
 }
 
-impl crate::register::SysRegRead for Pmintenclr {}
+impl SysRegRead for Pmintenclr {}
 
 impl Pmintenclr {
     #[inline]
@@ -26,7 +26,7 @@ impl Pmintenclr {
     }
 }
 
-impl crate::register::SysRegWrite for Pmintenclr {}
+impl SysRegWrite for Pmintenclr {}
 
 impl Pmintenclr {
     #[inline]
diff --git a/aarch32-cpu/src/register/pmintenset.rs b/aarch32-cpu/src/register/pmintenset.rs
index fbf35887..05dd661a 100644
--- a/aarch32-cpu/src/register/pmintenset.rs
+++ b/aarch32-cpu/src/register/pmintenset.rs
@@ -16,7 +16,7 @@ impl SysReg for Pmintenset {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for Pmintenset {}
+impl SysRegRead for Pmintenset {}
 
 impl Pmintenset {
     #[inline]
@@ -26,7 +26,7 @@ impl Pmintenset {
     }
 }
 
-impl crate::register::SysRegWrite for Pmintenset {}
+impl SysRegWrite for Pmintenset {}
 
 impl Pmintenset {
     #[inline]
diff --git a/aarch32-cpu/src/register/pmovsr.rs b/aarch32-cpu/src/register/pmovsr.rs
index c0634198..ed1abaec 100644
--- a/aarch32-cpu/src/register/pmovsr.rs
+++ b/aarch32-cpu/src/register/pmovsr.rs
@@ -16,7 +16,7 @@ impl SysReg for Pmovsr {
     const OP2: u32 = 3;
 }
 
-impl crate::register::SysRegRead for Pmovsr {}
+impl SysRegRead for Pmovsr {}
 
 impl Pmovsr {
     #[inline]
@@ -26,7 +26,7 @@ impl Pmovsr {
     }
 }
 
-impl crate::register::SysRegWrite for Pmovsr {}
+impl SysRegWrite for Pmovsr {}
 
 impl Pmovsr {
     #[inline]
diff --git a/aarch32-cpu/src/register/pmovsset.rs b/aarch32-cpu/src/register/pmovsset.rs
index 4ad574f8..e9987b40 100644
--- a/aarch32-cpu/src/register/pmovsset.rs
+++ b/aarch32-cpu/src/register/pmovsset.rs
@@ -16,7 +16,7 @@ impl SysReg for Pmovsset {
     const OP2: u32 = 3;
 }
 
-impl crate::register::SysRegRead for Pmovsset {}
+impl SysRegRead for Pmovsset {}
 
 impl Pmovsset {
     #[inline]
@@ -26,7 +26,7 @@ impl Pmovsset {
     }
 }
 
-impl crate::register::SysRegWrite for Pmovsset {}
+impl SysRegWrite for Pmovsset {}
 
 impl Pmovsset {
     #[inline]
diff --git a/aarch32-cpu/src/register/pmselr.rs b/aarch32-cpu/src/register/pmselr.rs
index 7a7b44d7..a1d1d57e 100644
--- a/aarch32-cpu/src/register/pmselr.rs
+++ b/aarch32-cpu/src/register/pmselr.rs
@@ -16,7 +16,7 @@ impl SysReg for Pmselr {
     const OP2: u32 = 5;
 }
 
-impl crate::register::SysRegRead for Pmselr {}
+impl SysRegRead for Pmselr {}
 
 impl Pmselr {
     #[inline]
@@ -26,7 +26,7 @@ impl Pmselr {
     }
 }
 
-impl crate::register::SysRegWrite for Pmselr {}
+impl SysRegWrite for Pmselr {}
 
 impl Pmselr {
     #[inline]
diff --git a/aarch32-cpu/src/register/pmswinc.rs b/aarch32-cpu/src/register/pmswinc.rs
index 9f9c0644..b440d045 100644
--- a/aarch32-cpu/src/register/pmswinc.rs
+++ b/aarch32-cpu/src/register/pmswinc.rs
@@ -16,7 +16,7 @@ impl SysReg for Pmswinc {
     const OP2: u32 = 4;
 }
 
-impl crate::register::SysRegWrite for Pmswinc {}
+impl SysRegWrite for Pmswinc {}
 
 impl Pmswinc {
     #[inline]
diff --git a/aarch32-cpu/src/register/pmuserenr.rs b/aarch32-cpu/src/register/pmuserenr.rs
index 266814c4..446e665c 100644
--- a/aarch32-cpu/src/register/pmuserenr.rs
+++ b/aarch32-cpu/src/register/pmuserenr.rs
@@ -16,7 +16,7 @@ impl SysReg for Pmuserenr {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for Pmuserenr {}
+impl SysRegRead for Pmuserenr {}
 
 impl Pmuserenr {
     #[inline]
@@ -26,7 +26,7 @@ impl Pmuserenr {
     }
 }
 
-impl crate::register::SysRegWrite for Pmuserenr {}
+impl SysRegWrite for Pmuserenr {}
 
 impl Pmuserenr {
     #[inline]
diff --git a/aarch32-cpu/src/register/pmxevcntr.rs b/aarch32-cpu/src/register/pmxevcntr.rs
index 9c7f7d44..11a080ed 100644
--- a/aarch32-cpu/src/register/pmxevcntr.rs
+++ b/aarch32-cpu/src/register/pmxevcntr.rs
@@ -16,7 +16,7 @@ impl SysReg for Pmxevcntr {
     const OP2: u32 = 2;
 }
 
-impl crate::register::SysRegRead for Pmxevcntr {}
+impl SysRegRead for Pmxevcntr {}
 
 impl Pmxevcntr {
     #[inline]
@@ -26,7 +26,7 @@ impl Pmxevcntr {
     }
 }
 
-impl crate::register::SysRegWrite for Pmxevcntr {}
+impl SysRegWrite for Pmxevcntr {}
 
 impl Pmxevcntr {
     #[inline]
diff --git a/aarch32-cpu/src/register/pmxevtyper.rs b/aarch32-cpu/src/register/pmxevtyper.rs
index 4be65a2c..3466013f 100644
--- a/aarch32-cpu/src/register/pmxevtyper.rs
+++ b/aarch32-cpu/src/register/pmxevtyper.rs
@@ -16,7 +16,7 @@ impl SysReg for Pmxevtyper {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for Pmxevtyper {}
+impl SysRegRead for Pmxevtyper {}
 
 impl Pmxevtyper {
     #[inline]
@@ -26,7 +26,7 @@ impl Pmxevtyper {
     }
 }
 
-impl crate::register::SysRegWrite for Pmxevtyper {}
+impl SysRegWrite for Pmxevtyper {}
 
 impl Pmxevtyper {
     #[inline]
diff --git a/aarch32-cpu/src/register/revidr.rs b/aarch32-cpu/src/register/revidr.rs
index e86dc7ec..a9a89cc6 100644
--- a/aarch32-cpu/src/register/revidr.rs
+++ b/aarch32-cpu/src/register/revidr.rs
@@ -16,7 +16,7 @@ impl SysReg for Revidr {
     const OP2: u32 = 6;
 }
 
-impl crate::register::SysRegRead for Revidr {}
+impl SysRegRead for Revidr {}
 
 impl Revidr {
     #[inline]
diff --git a/aarch32-cpu/src/register/rgnr.rs b/aarch32-cpu/src/register/rgnr.rs
index c7f05c3b..b0bada53 100644
--- a/aarch32-cpu/src/register/rgnr.rs
+++ b/aarch32-cpu/src/register/rgnr.rs
@@ -18,7 +18,7 @@ impl SysReg for Rgnr {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for Rgnr {}
+impl SysRegRead for Rgnr {}
 
 impl Rgnr {
     #[inline]
@@ -28,7 +28,7 @@ impl Rgnr {
     }
 }
 
-impl crate::register::SysRegWrite for Rgnr {}
+impl SysRegWrite for Rgnr {}
 
 impl Rgnr {
     #[inline]
diff --git a/aarch32-cpu/src/register/rvbar.rs b/aarch32-cpu/src/register/rvbar.rs
index 02f79221..232b5e52 100644
--- a/aarch32-cpu/src/register/rvbar.rs
+++ b/aarch32-cpu/src/register/rvbar.rs
@@ -17,7 +17,7 @@ impl SysReg for Rvbar {
     const OP2: u32 = 1;
 }
 
-impl crate::register::SysRegRead for Rvbar {}
+impl SysRegRead for Rvbar {}
 
 impl Rvbar {
     #[inline]
diff --git a/aarch32-cpu/src/register/sctlr.rs b/aarch32-cpu/src/register/sctlr.rs
index 486857a1..922bae32 100644
--- a/aarch32-cpu/src/register/sctlr.rs
+++ b/aarch32-cpu/src/register/sctlr.rs
@@ -72,6 +72,7 @@ impl Sctlr {
     /// Read SCTLR (*System Control Register*)
     #[inline]
     pub fn read() -> Self {
+        // Safety: it's OK to set bits with no accessors specified
         unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
     }
 
@@ -129,7 +130,11 @@ impl core::fmt::Debug for Sctlr {
 
 #[cfg(feature = "defmt")]
 impl defmt::Format for Sctlr {
-    fn format(&self, f: defmt::Formatter) {
-        defmt::write!(f, "SCTLR {{ IE={0=31..32} TE={0=30..31} NMFI={0=27..28} EE={0=25..26} U={0=22..23} FI={0=21..22} DZ={0=18..19} BR={0=17..18} RR={0=14..15} V={0=13..14} I={0=12..13} Z={0=11..12} SW={0=10..11} C={0=2..3} A={0=1..2} M={0=0..1} }}", self.raw_value())
+    fn format(&self, f: defmt::Formatter<'_>) {
+        defmt::write!(
+            f,
+            "SCTLR {{ IE={0=31..32} TE={0=30..31} NMFI={0=27..28} EE={0=25..26} U={0=22..23} FI={0=21..22} DZ={0=18..19} BR={0=17..18} RR={0=14..15} V={0=13..14} I={0=12..13} Z={0=11..12} SW={0=10..11} C={0=2..3} A={0=1..2} M={0=0..1} }}",
+            self.raw_value()
+        )
     }
 }
diff --git a/aarch32-cpu/src/register/tcmtr.rs b/aarch32-cpu/src/register/tcmtr.rs
index 19789ce4..9ba477b4 100644
--- a/aarch32-cpu/src/register/tcmtr.rs
+++ b/aarch32-cpu/src/register/tcmtr.rs
@@ -16,7 +16,7 @@ impl SysReg for Tcmtr {
     const OP2: u32 = 2;
 }
 
-impl crate::register::SysRegRead for Tcmtr {}
+impl SysRegRead for Tcmtr {}
 
 impl Tcmtr {
     #[inline]
diff --git a/aarch32-cpu/src/register/tlbiall.rs b/aarch32-cpu/src/register/tlbiall.rs
index e6f664eb..5ff2112c 100644
--- a/aarch32-cpu/src/register/tlbiall.rs
+++ b/aarch32-cpu/src/register/tlbiall.rs
@@ -1,6 +1,6 @@
 //! Code for managing TLBIALL (*TLB Invalidate All Register*)
 
-use crate::register::SysReg;
+use crate::register::{SysReg, SysRegWrite};
 
 /// TLBIALL (*TLB Invalidate All Register*)
 pub struct TlbIAll;
@@ -13,11 +13,12 @@ impl SysReg for TlbIAll {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegWrite for TlbIAll {}
+impl SysRegWrite for TlbIAll {}
 
 impl TlbIAll {
     #[inline]
+    /// Writes 0 to TLBIALL (*TLB Invalidate All Register*) to trigger operation
     pub fn write() {
-        unsafe { <Self as crate::register::SysRegWrite>::write_raw(0) }
+        unsafe { <Self as SysRegWrite>::write_raw(0) }
     }
 }
diff --git a/aarch32-cpu/src/register/tlbtr.rs b/aarch32-cpu/src/register/tlbtr.rs
index 41ce0ae1..07af4fa6 100644
--- a/aarch32-cpu/src/register/tlbtr.rs
+++ b/aarch32-cpu/src/register/tlbtr.rs
@@ -16,7 +16,7 @@ impl SysReg for Tlbtr {
     const OP2: u32 = 3;
 }
 
-impl crate::register::SysRegRead for Tlbtr {}
+impl SysRegRead for Tlbtr {}
 
 impl Tlbtr {
     #[inline]
diff --git a/aarch32-cpu/src/register/tpidrprw.rs b/aarch32-cpu/src/register/tpidrprw.rs
index c6bcc917..244aa5c4 100644
--- a/aarch32-cpu/src/register/tpidrprw.rs
+++ b/aarch32-cpu/src/register/tpidrprw.rs
@@ -16,7 +16,7 @@ impl SysReg for Tpidrprw {
     const OP2: u32 = 4;
 }
 
-impl crate::register::SysRegRead for Tpidrprw {}
+impl SysRegRead for Tpidrprw {}
 
 impl Tpidrprw {
     #[inline]
@@ -26,7 +26,7 @@ impl Tpidrprw {
     }
 }
 
-impl crate::register::SysRegWrite for Tpidrprw {}
+impl SysRegWrite for Tpidrprw {}
 
 impl Tpidrprw {
     #[inline]
diff --git a/aarch32-cpu/src/register/tpidruro.rs b/aarch32-cpu/src/register/tpidruro.rs
index a17fed5b..0944fd96 100644
--- a/aarch32-cpu/src/register/tpidruro.rs
+++ b/aarch32-cpu/src/register/tpidruro.rs
@@ -16,7 +16,7 @@ impl SysReg for Tpidruro {
     const OP2: u32 = 3;
 }
 
-impl crate::register::SysRegRead for Tpidruro {}
+impl SysRegRead for Tpidruro {}
 
 impl Tpidruro {
     #[inline]
@@ -26,7 +26,7 @@ impl Tpidruro {
     }
 }
 
-impl crate::register::SysRegWrite for Tpidruro {}
+impl SysRegWrite for Tpidruro {}
 
 impl Tpidruro {
     #[inline]
diff --git a/aarch32-cpu/src/register/tpidrurw.rs b/aarch32-cpu/src/register/tpidrurw.rs
index 3733b2e6..a13a9eb6 100644
--- a/aarch32-cpu/src/register/tpidrurw.rs
+++ b/aarch32-cpu/src/register/tpidrurw.rs
@@ -16,7 +16,7 @@ impl SysReg for Tpidrurw {
     const OP2: u32 = 2;
 }
 
-impl crate::register::SysRegRead for Tpidrurw {}
+impl SysRegRead for Tpidrurw {}
 
 impl Tpidrurw {
     #[inline]
@@ -26,7 +26,7 @@ impl Tpidrurw {
     }
 }
 
-impl crate::register::SysRegWrite for Tpidrurw {}
+impl SysRegWrite for Tpidrurw {}
 
 impl Tpidrurw {
     #[inline]
diff --git a/aarch32-cpu/src/register/ttbr0.rs b/aarch32-cpu/src/register/ttbr0.rs
index ea9c8dd2..320b74cc 100644
--- a/aarch32-cpu/src/register/ttbr0.rs
+++ b/aarch32-cpu/src/register/ttbr0.rs
@@ -87,11 +87,11 @@ pub enum Region {
     /// Normal memory, Outer Non-cacheable
     NonCacheable = 0b00,
     /// Normal memory, Outer Write-Back Write-Allocate Cacheable
-    WriteBackWriteAllocateCacheable = 0b01,
+    WriteBackWriteAllocCacheable = 0b01,
     /// Normal memory, Outer Write-Through Cacheable
     WriteThroughCacheable = 0b10,
     /// Normal memory, Outer Write-Back no Write-Allocate Cacheable
-    WriteBackNoWriteAllocateCacheable = 0b11,
+    WriteBackNoWriteAllocCacheable = 0b11,
 }
 
 impl SysReg for Ttbr0 {
@@ -102,14 +102,15 @@ impl SysReg for Ttbr0 {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for Ttbr0 {}
+impl SysRegRead for Ttbr0 {}
 
-impl crate::register::SysRegWrite for Ttbr0 {}
+impl SysRegWrite for Ttbr0 {}
 
 impl Ttbr0 {
     #[inline]
     /// Reads TTBR0 (*Translation Table Base Register 0*)
     pub fn read() -> Ttbr0 {
+        // Safety: it's OK to set bits with no accessors specified
         unsafe { Self::new_with_raw_value(<Self as SysRegRead>::read_raw()) }
     }
 
diff --git a/aarch32-cpu/src/register/vmpidr.rs b/aarch32-cpu/src/register/vmpidr.rs
index 3a0fed37..2cb24dd6 100644
--- a/aarch32-cpu/src/register/vmpidr.rs
+++ b/aarch32-cpu/src/register/vmpidr.rs
@@ -16,7 +16,7 @@ impl SysReg for Vmpidr {
     const OP2: u32 = 5;
 }
 
-impl crate::register::SysRegRead for Vmpidr {}
+impl SysRegRead for Vmpidr {}
 
 impl Vmpidr {
     #[inline]
@@ -26,7 +26,7 @@ impl Vmpidr {
     }
 }
 
-impl crate::register::SysRegWrite for Vmpidr {}
+impl SysRegWrite for Vmpidr {}
 
 impl Vmpidr {
     #[inline]
diff --git a/aarch32-cpu/src/register/vpidr.rs b/aarch32-cpu/src/register/vpidr.rs
index 2e824158..4ab8c457 100644
--- a/aarch32-cpu/src/register/vpidr.rs
+++ b/aarch32-cpu/src/register/vpidr.rs
@@ -16,7 +16,7 @@ impl SysReg for Vpidr {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for Vpidr {}
+impl SysRegRead for Vpidr {}
 
 impl Vpidr {
     #[inline]
@@ -26,7 +26,7 @@ impl Vpidr {
     }
 }
 
-impl crate::register::SysRegWrite for Vpidr {}
+impl SysRegWrite for Vpidr {}
 
 impl Vpidr {
     #[inline]
diff --git a/aarch32-cpu/src/register/vsctlr.rs b/aarch32-cpu/src/register/vsctlr.rs
index dfc92587..d8397754 100644
--- a/aarch32-cpu/src/register/vsctlr.rs
+++ b/aarch32-cpu/src/register/vsctlr.rs
@@ -16,7 +16,7 @@ impl SysReg for Vsctlr {
     const OP2: u32 = 0;
 }
 
-impl crate::register::SysRegRead for Vsctlr {}
+impl SysRegRead for Vsctlr {}
 
 impl Vsctlr {
     #[inline]
@@ -26,7 +26,7 @@ impl Vsctlr {
     }
 }
 
-impl crate::register::SysRegWrite for Vsctlr {}
+impl SysRegWrite for Vsctlr {}
 
 impl Vsctlr {
     #[inline]
diff --git a/aarch32-cpu/src/stacks.rs b/aarch32-cpu/src/stacks.rs
index 161902f7..8668fbc5 100644
--- a/aarch32-cpu/src/stacks.rs
+++ b/aarch32-cpu/src/stacks.rs
@@ -13,10 +13,7 @@ pub unsafe fn stack_used_bytes(stack: core::ops::Range<*const u32>) -> (usize, u
     let size_words = unsafe { stack.end.offset_from(stack.start) } as usize;
     let unused_words = unsafe { stack_unused_bytes_asm(stack.start, size_words) };
     let used_words = size_words - unused_words;
-    (
-        size_words * core::mem::size_of::<u32>(),
-        used_words * core::mem::size_of::<u32>(),
-    )
+    (size_words * size_of::<u32>(), used_words * size_of::<u32>())
 }
 
 /// Counts number of words that are equal to zero
@@ -33,30 +30,32 @@ pub unsafe fn stack_used_bytes(stack: core::ops::Range<*const u32>) -> (usize, u
 /// of at least `size` words in length.
 unsafe fn stack_unused_bytes_asm(start: *const u32, size: usize) -> usize {
     let result: usize;
-    core::arch::asm!(
-        r#"
-        // skip out if size is zero
-        movs    {result}, #0
-        cmp     {size}, #0
-        beq     3f
-2:      // loop
-        ldr     {scratch}, [{start}]
-        cmp     {scratch}, #0
-        // break out if value is non-zero
-        bne     3f
-        // otherwise increment counter
-        adds    {result}, {result}, #1
-        adds    {start}, {start}, #4
-        // loop if not finished yet
-        cmp     {result}, {size}
-        bne     2b
-        // all finished
-3:
-        "#,
-        size = in(reg) size,
-        start = inout(reg) start => _,
-        result = out(reg) result,
-        scratch = out(reg) _,
-    );
+    unsafe {
+        core::arch::asm!(
+            r#"
+            // skip out if size is zero
+            movs    {result}, #0
+            cmp     {size}, #0
+            beq     3f
+    2:      // loop
+            ldr     {scratch}, [{start}]
+            cmp     {scratch}, #0
+            // break out if value is non-zero
+            bne     3f
+            // otherwise increment counter
+            adds    {result}, {result}, #1
+            adds    {start}, {start}, #4
+            // loop if not finished yet
+            cmp     {result}, {size}
+            bne     2b
+            // all finished
+    3:
+            "#,
+            size = in(reg) size,
+            start = inout(reg) start => _,
+            result = out(reg) result,
+            scratch = out(reg) _,
+        );
+    }
     result
 }
diff --git a/aarch32-rt-macros/CHANGELOG.md b/aarch32-rt-macros/CHANGELOG.md
index 09563300..126439cc 100644
--- a/aarch32-rt-macros/CHANGELOG.md
+++ b/aarch32-rt-macros/CHANGELOG.md
@@ -12,6 +12,7 @@ As of *aarch32-rt-macros v0.1.0*, this project is released in lock-step with
 
 - Handle outer `unsafe` for whitelisted proc macro attributes. For example, this allows
   `#[unsafe(link_section="...")]` which previously did not work.
+- Bumped MSRV to v1.85 to allow switch to Edition 2024
 
 ## [aarch32-rt-macros v0.2.0]
 
diff --git a/aarch32-rt-macros/Cargo.toml b/aarch32-rt-macros/Cargo.toml
index 6176cc27..ace9b724 100644
--- a/aarch32-rt-macros/Cargo.toml
+++ b/aarch32-rt-macros/Cargo.toml
@@ -5,13 +5,13 @@ authors = [
   "The Embedded Devices Working Group Arm Team <arm@teams.rust-embedded.org>"
 ]
 description = "Run-Time macros for aarch32-rt"
-edition = "2021"
+edition = "2024"
 license = "MIT OR Apache-2.0"
 name = "aarch32-rt-macros"
 readme = "README.md"
 repository = "https://github.com/rust-embedded/aarch32.git"
 homepage = "https://github.com/rust-embedded/aarch32"
-rust-version = "1.83"
+rust-version = "1.85"
 version = "0.2.0"
 
 [lib]
@@ -24,3 +24,59 @@ proc-macro2 = "1.0"
 [dependencies.syn]
 features = ["extra-traits", "full"]
 version = "2.0"
+
+[lints.rust]
+missing_docs = "warn" # Indicates missing documentation on public functions
+missing_abi = "warn" # Explicit ABI documents the assumptions of the code
+unsafe_op_in_unsafe_fn = "warn" # Satisfies the recommendation in section 4.3.1
+elided_lifetimes_in_paths = "warn" # Highlights confusing implicit use of types with lifetimes
+explicit_outlives_requirements = "warn" # Less explicit lifetime bounds improve readability
+macro_use-extern_crate = "warn" # obscures the source of identifiers
+meta_variable_misuse = "warn" # More macro quality checks outweigh potential false positives
+non-local-definitions = "warn" # Highlights outdated and confusing location of definitions
+redundant-lifetimes = "warn" # Highlights a mistake or unfinished code
+single-use-lifetimes = "warn" # Simplifies code, improving readability
+trivial-numeric-casts = "warn" # Simplifies code, improving readability
+unit-bindings = "warn" # Simplifies code, improving readability
+unnameable-types = "warn" # Highlights inconsistency in public interface
+unreachable-pub = "warn" # Highlights inconsistency in public interface
+variant-size-differences = "warn" # Highlights inefficient data structures
+rust-2018-compatibility = "warn"
+rust-2018-idioms = "warn"
+rust-2021-compatibility = "warn"
+rust-2024-compatibility = "warn"
+unused = { level = "warn", priority = -1 } # this group might overlap
+unused_results = "warn"
+unused-qualifications = "warn"
+unused-lifetimes = "warn"
+unused-import-braces = "warn"
+
+[lints.clippy]
+cast_lossless = "warn" # Indicates a more idiomatic way to replace the cast
+cast_possible_truncation = "warn"
+cast_possible_wrap = "warn"
+cast_ptr_alignment = "warn"
+cast_sign_loss = "warn" # Should be checked for and properly handled in safety related projects
+exit = "warn" # Calling exit directly is likely wrong in a safety related environment
+infinite_loop = "warn" # Indicates improper return type
+iter_over_hash_type = "warn" # Indicates unpredictable order
+invalid_upcast_comparisons = "warn" # Likely wrong code
+lossy_float_literal = "warn" # Indicates rounding error
+missing_errors_doc = "warn" # Indicates incomplete documentation
+missing_docs_in_private_items = "warn" # Undocumented internal items are not an option
+panic_in_result_fn = "warn" # Indicates unexpected behavior
+ptr_cast_constness = "warn"
+ref_as_ptr = "warn"
+transmute_ptr_to_ptr = "warn" # Safer alternative available
+redundant_type_annotations = "warn" # Simpler code, highlights special cases
+shadow_unrelated = "warn" # Unidiomatic and high-risk use of shadowing
+try_err = "warn" # Indicates non-idiomatic way to avoid return
+wildcard_enum_match_arm = "warn" # See section 4.4.21.3, clashes with non-exhaustive
+as_underscore = "warn"
+format_push_string = "warn" # Avoids extra allocation
+as_ptr_cast_mut = "deny" # Clear misuse with a better alternative
+let_underscore_must_use = "deny" # Prevents a shortcut to ignore must-use results
+missing_panics_doc = "deny" # Indicates missing panic documentation
+undocumented_unsafe_blocks = "deny" # Indicates missing "unsafe" reasoning
+wildcard_imports = "deny" # Indicates unconstrained symbol imports
+declare_interior_mutable_const = "deny" # Indicates common mistake
diff --git a/aarch32-rt-macros/README.md b/aarch32-rt-macros/README.md
index 64e3c979..c639dec2 100644
--- a/aarch32-rt-macros/README.md
+++ b/aarch32-rt-macros/README.md
@@ -6,7 +6,7 @@ This crate contains proc-macros that are re-exported through the `aarch32-rt` cr
 
 ## Minimum Supported Rust Version (MSRV)
 
-This crate is guaranteed to compile on stable Rust 1.83.0 and up, as recorded
+This crate is guaranteed to compile on stable Rust 1.85.0 and up, as recorded
 by the `package.rust-version` property in `Cargo.toml`.
 
 Increasing the MSRV is not considered a breaking change and may occur in a
diff --git a/aarch32-rt-macros/src/lib.rs b/aarch32-rt-macros/src/lib.rs
index e290dc04..485fca78 100644
--- a/aarch32-rt-macros/src/lib.rs
+++ b/aarch32-rt-macros/src/lib.rs
@@ -6,14 +6,12 @@
 //!
 //! Based on <https://github.com/rust-embedded/cortex-m/tree/c-m-rt-v0.7.5/cortex-m-rt/macros>.
 
-extern crate proc_macro;
-
 use proc_macro::{TokenStream, TokenTree};
 use proc_macro2::Span;
 use quote::quote;
 use syn::{
-    parse, parse_macro_input, spanned::Spanned, AttrStyle, Attribute, Ident, ItemFn, ReturnType,
-    Type, Visibility,
+    AttrStyle, Attribute, Ident, ItemFn, ReturnType, Type, Visibility, parse, parse_macro_input,
+    spanned::Spanned,
 };
 
 /// Creates an `unsafe` program entry point (i.e. a `kmain` function).
@@ -34,7 +32,7 @@ use syn::{
 ///
 /// ```rust
 /// #[doc(hidden)]
-/// #[export_name = "kmain"]
+/// #[unsafe(export_name = "kmain")]
 /// pub unsafe extern "C" fn __aarch32_rt_kmain() -> ! {
 ///     foo()
 /// }
@@ -101,7 +99,7 @@ pub fn entry(args: TokenStream, input: TokenStream) -> TokenStream {
         #(#cfgs)*
         #(#attrs)*
         #[doc(hidden)]
-        #[export_name = "kmain"]
+        #[unsafe(export_name = "kmain")]
         pub unsafe extern "C" fn #tramp_ident() -> ! {
             #block
         }
@@ -151,7 +149,7 @@ impl std::fmt::Display for Exception {
 ///
 /// ```rust
 /// #[doc(hidden)]
-/// #[export_name = "_undefined_handler"]
+/// #[unsafe(export_name = "_undefined_handler")]
 /// pub unsafe extern "C" fn __aarch32_rt_undefined_handler(addr: usize) -> ! {
 ///     foo(addr)
 /// }
@@ -192,7 +190,7 @@ pub fn exception(args: TokenStream, input: TokenStream) -> TokenStream {
 ///
 /// ```rust
 /// #[doc(hidden)]
-/// #[export_name = "_irq_handler"]
+/// #[unsafe(export_name = "_irq_handler")]
 /// pub unsafe extern "C" fn __aarch32_rt_irq_handler(addr: usize) -> ! {
 ///     foo(addr)
 /// }
@@ -319,7 +317,7 @@ fn handle_vector(args: TokenStream, input: TokenStream, kind: VectorKind) -> Tok
                     #(#cfgs)*
                     #(#attrs)*
                     #[doc(hidden)]
-                    #[export_name = "_undefined_handler"]
+                    #[unsafe(export_name = "_undefined_handler")]
                     pub unsafe extern "C" fn #tramp_ident(addr: usize) -> ! {
                         #block
                     }
@@ -330,7 +328,7 @@ fn handle_vector(args: TokenStream, input: TokenStream, kind: VectorKind) -> Tok
                     #(#cfgs)*
                     #(#attrs)*
                     #[doc(hidden)]
-                    #[export_name = "_undefined_handler"]
+                    #[unsafe(export_name = "_undefined_handler")]
                     pub unsafe extern "C" fn #tramp_ident(addr: usize) -> usize {
                         #block
                     }
@@ -347,7 +345,7 @@ fn handle_vector(args: TokenStream, input: TokenStream, kind: VectorKind) -> Tok
                     #(#cfgs)*
                     #(#attrs)*
                     #[doc(hidden)]
-                    #[export_name = "_prefetch_abort_handler"]
+                    #[unsafe(export_name = "_prefetch_abort_handler")]
                     pub unsafe extern "C" fn #tramp_ident(addr: usize) -> ! {
                         #block
                     }
@@ -357,7 +355,7 @@ fn handle_vector(args: TokenStream, input: TokenStream, kind: VectorKind) -> Tok
                     #(#cfgs)*
                     #(#attrs)*
                     #[doc(hidden)]
-                    #[export_name = "_prefetch_abort_handler"]
+                    #[unsafe(export_name = "_prefetch_abort_handler")]
                     pub unsafe extern "C" fn #tramp_ident(addr: usize) -> usize {
                         #block
                     }
@@ -374,7 +372,7 @@ fn handle_vector(args: TokenStream, input: TokenStream, kind: VectorKind) -> Tok
                     #(#cfgs)*
                     #(#attrs)*
                     #[doc(hidden)]
-                    #[export_name = "_data_abort_handler"]
+                    #[unsafe(export_name = "_data_abort_handler")]
                     pub unsafe extern "C" fn #tramp_ident(addr: usize) -> ! {
                         #block
                     }
@@ -385,7 +383,7 @@ fn handle_vector(args: TokenStream, input: TokenStream, kind: VectorKind) -> Tok
                     #(#cfgs)*
                     #(#attrs)*
                     #[doc(hidden)]
-                    #[export_name = "_data_abort_handler"]
+                    #[unsafe(export_name = "_data_abort_handler")]
                     pub unsafe extern "C" fn #tramp_ident(addr: usize) -> usize {
                         #block
                     }
@@ -399,7 +397,7 @@ fn handle_vector(args: TokenStream, input: TokenStream, kind: VectorKind) -> Tok
                 #(#cfgs)*
                 #(#attrs)*
                 #[doc(hidden)]
-                #[export_name = "_svc_handler"]
+                #[unsafe(export_name = "_svc_handler")]
                 pub unsafe extern "C" fn #tramp_ident(arg: u32, frame: &aarch32_rt::Frame) -> u32 {
                     #f
 
@@ -414,7 +412,7 @@ fn handle_vector(args: TokenStream, input: TokenStream, kind: VectorKind) -> Tok
                 #(#cfgs)*
                 #(#attrs)*
                 #[doc(hidden)]
-                #[export_name = "_hvc_handler"]
+                #[unsafe(export_name = "_hvc_handler")]
                 pub unsafe extern "C" fn #tramp_ident(hsr: u32, frame: &aarch32_rt::Frame) -> u32 {
                     #f
 
@@ -429,7 +427,7 @@ fn handle_vector(args: TokenStream, input: TokenStream, kind: VectorKind) -> Tok
                 #(#cfgs)*
                 #(#attrs)*
                 #[doc(hidden)]
-                #[export_name = "_irq_handler"]
+                #[unsafe(export_name = "_irq_handler")]
                 pub unsafe extern "C" fn #tramp_ident() {
                     #block
                 }
diff --git a/aarch32-rt/CHANGELOG.md b/aarch32-rt/CHANGELOG.md
index 99042246..27977222 100644
--- a/aarch32-rt/CHANGELOG.md
+++ b/aarch32-rt/CHANGELOG.md
@@ -7,6 +7,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+- Bumped MSRV to v1.85 to allow switch to Edition 2024
+
 ## [aarch32-rt v0.2.0]
 
 ### Changed
diff --git a/aarch32-rt/Cargo.toml b/aarch32-rt/Cargo.toml
index f796ebe7..ce30c18a 100644
--- a/aarch32-rt/Cargo.toml
+++ b/aarch32-rt/Cargo.toml
@@ -8,7 +8,7 @@ categories = [
     "no-std",
 ]
 description = "Run-time support for Arm AArch32"
-edition = "2021"
+edition = "2024"
 keywords = [
     "arm",
     "aarch32",
@@ -20,7 +20,7 @@ license = "MIT OR Apache-2.0"
 name = "aarch32-rt"
 readme = "README.md"
 repository = "https://github.com/rust-embedded/aarch32.git"
-rust-version = "1.83"
+rust-version = "1.85"
 version = "0.2.0"
 
 [dependencies]
@@ -50,3 +50,59 @@ targets = [
     "armv7a-none-eabi",
     "armv8r-none-eabihf"
 ]
+
+[lints.rust]
+missing_docs = "warn" # Indicates missing documentation on public functions
+missing_abi = "warn" # Explicit ABI documents the assumptions of the code
+unsafe_op_in_unsafe_fn = "warn" # Satisfies the recommendation in section 4.3.1
+elided_lifetimes_in_paths = "warn" # Highlights confusing implicit use of types with lifetimes
+explicit_outlives_requirements = "warn" # Less explicit lifetime bounds improve readability
+macro_use-extern_crate = "warn" # obscures the source of identifiers
+meta_variable_misuse = "warn" # More macro quality checks outweigh potential false positives
+non-local-definitions = "warn" # Highlights outdated and confusing location of definitions
+redundant-lifetimes = "warn" # Highlights a mistake or unfinished code
+single-use-lifetimes = "warn" # Simplifies code, improving readability
+trivial-numeric-casts = "warn" # Simplifies code, improving readability
+unit-bindings = "warn" # Simplifies code, improving readability
+unnameable-types = "warn" # Highlights inconsistency in public interface
+unreachable-pub = "warn" # Highlights inconsistency in public interface
+variant-size-differences = "warn" # Highlights inefficient data structures
+rust-2018-compatibility = "warn"
+rust-2018-idioms = "warn"
+rust-2021-compatibility = "warn"
+rust-2024-compatibility = "warn"
+unused = { level = "warn", priority = -1 } # this group might overlap
+unused_results = "warn"
+unused-qualifications = "warn"
+unused-lifetimes = "warn"
+unused-import-braces = "warn"
+
+[lints.clippy]
+cast_lossless = "warn" # Indicates a more idiomatic way to replace the cast
+cast_possible_truncation = "warn"
+cast_possible_wrap = "warn"
+cast_ptr_alignment = "warn"
+cast_sign_loss = "warn" # Should be checked for and properly handled in safety related projects
+exit = "warn" # Calling exit directly is likely wrong in a safety related environment
+infinite_loop = "warn" # Indicates improper return type
+iter_over_hash_type = "warn" # Indicates unpredictable order
+invalid_upcast_comparisons = "warn" # Likely wrong code
+lossy_float_literal = "warn" # Indicates rounding error
+missing_errors_doc = "warn" # Indicates incomplete documentation
+missing_docs_in_private_items = "warn" # Undocumented internal items are not an option
+panic_in_result_fn = "warn" # Indicates unexpected behavior
+ptr_cast_constness = "warn"
+ref_as_ptr = "warn"
+transmute_ptr_to_ptr = "warn" # Safer alternative available
+redundant_type_annotations = "warn" # Simpler code, highlights special cases
+shadow_unrelated = "warn" # Unidiomatic and high-risk use of shadowing
+try_err = "warn" # Indicates non-idiomatic way to avoid return
+wildcard_enum_match_arm = "warn" # See section 4.4.21.3, clashes with non-exhaustive
+as_underscore = "warn"
+format_push_string = "warn" # Avoids extra allocation
+as_ptr_cast_mut = "deny" # Clear misuse with a better alternative
+let_underscore_must_use = "deny" # Prevents a shortcut to ignore must-use results
+missing_panics_doc = "deny" # Indicates missing panic documentation
+undocumented_unsafe_blocks = "deny" # Indicates missing "unsafe" reasoning
+wildcard_imports = "deny" # Indicates unconstrained symbol imports
+declare_interior_mutable_const = "deny" # Indicates common mistake
diff --git a/aarch32-rt/README.md b/aarch32-rt/README.md
index a94854e8..724c14c7 100644
--- a/aarch32-rt/README.md
+++ b/aarch32-rt/README.md
@@ -22,7 +22,7 @@ uses different instructions for reading/writing system registers.
 
 ## Minimum Supported Rust Version (MSRV)
 
-This crate is guaranteed to compile on stable Rust 1.83.0 and up, as recorded
+This crate is guaranteed to compile on stable Rust 1.85.0 and up, as recorded
 by the `package.rust-version` property in `Cargo.toml`.
 
 Increasing the MSRV is not considered a breaking change and may occur in a
diff --git a/aarch32-rt/build.rs b/aarch32-rt/build.rs
index 2f0bd789..a8e06212 100644
--- a/aarch32-rt/build.rs
+++ b/aarch32-rt/build.rs
@@ -7,7 +7,7 @@
 use std::io::Write;
 
 fn main() {
-    arm_targets::process();
+    _ = arm_targets::process();
     write("link.x", include_bytes!("link.x"));
 }
 
diff --git a/aarch32-rt/src/lib.rs b/aarch32-rt/src/lib.rs
index 04bb2824..8056f064 100644
--- a/aarch32-rt/src/lib.rs
+++ b/aarch32-rt/src/lib.rs
@@ -529,7 +529,7 @@
 #![no_std]
 
 #[cfg(target_arch = "arm")]
-use aarch32_cpu::register::{cpsr::ProcessorMode, Cpsr};
+use aarch32_cpu::register::{Cpsr, cpsr::ProcessorMode};
 
 #[cfg(all(
     any(arm_architecture = "v7-a", arm_architecture = "v8-r"),
@@ -569,7 +569,7 @@ pub mod stacks;
 ///
 /// We end up here if an exception fires and the weak 'PROVIDE' in the link.x
 /// file hasn't been over-ridden.
-#[no_mangle]
+#[unsafe(no_mangle)]
 pub extern "C" fn _default_handler() {
     loop {
         core::hint::spin_loop();
@@ -610,11 +610,17 @@ core::arch::global_asm!(
 #[derive(Debug, Clone, PartialEq, Eq)]
 #[repr(C)]
 pub struct Frame {
+    /// Copy of the R0 register, captured on exception entry
     pub r0: u32,
+    /// Copy of the R1 register, captured on exception entry
     pub r1: u32,
+    /// Copy of the R2 register, captured on exception entry
     pub r2: u32,
+    /// Copy of the R3 register, captured on exception entry
     pub r3: u32,
+    /// Copy of the R4 register, captured on exception entry
     pub r4: u32,
+    /// Copy of the R5 register, captured on exception entry
     pub r5: u32,
 }
 
@@ -1149,5 +1155,5 @@ core::arch::global_asm!(
         b       .
     .size _default_start, . - _default_start
     "#,
-    irq_fiq = const aarch32_cpu::register::Cpsr::new_with_raw_value(0).with_i(true).with_f(true).raw_value()
+    irq_fiq = const Cpsr::new_with_raw_value(0).with_i(true).with_f(true).raw_value()
 );
diff --git a/aarch32-rt/src/sections.rs b/aarch32-rt/src/sections.rs
index 87eec9ca..c219a93b 100644
--- a/aarch32-rt/src/sections.rs
+++ b/aarch32-rt/src/sections.rs
@@ -32,7 +32,7 @@ pub enum Section {
 }
 
 impl core::fmt::Display for Section {
-    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
         f.pad(match self {
             Section::VectorTable => ".vector_table",
             Section::Text => ".text",
diff --git a/aarch32-rt/src/stacks.rs b/aarch32-rt/src/stacks.rs
index 9a889edc..fdd04fcb 100644
--- a/aarch32-rt/src/stacks.rs
+++ b/aarch32-rt/src/stacks.rs
@@ -20,7 +20,7 @@ pub enum Stack {
 }
 
 impl core::fmt::Display for Stack {
-    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
         f.pad(match self {
             Stack::Und => "UND",
             Stack::Svc => "SVC",
diff --git a/arm-targets/CHANGELOG.md b/arm-targets/CHANGELOG.md
index 9f5e1cee..01560e8f 100644
--- a/arm-targets/CHANGELOG.md
+++ b/arm-targets/CHANGELOG.md
@@ -10,6 +10,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 ### Changed
 
 - Take `CARGO_CFG_TARGET_*` variables into account for detecting targets.
+- Bumped MSRV to v1.85 to allow switch to Edition 2024
+- Amended CLI tool output
 
 ## [v0.4.1]
 
diff --git a/arm-targets/Cargo.toml b/arm-targets/Cargo.toml
index 44c79e8e..b6d6c420 100644
--- a/arm-targets/Cargo.toml
+++ b/arm-targets/Cargo.toml
@@ -5,16 +5,72 @@ authors = [
 ]
 categories = ["development-tools::build-utils"]
 description = "Compile-time feature detection for Arm processors"
-edition = "2021"
+edition = "2024"
 license = "MIT OR Apache-2.0"
 name = "arm-targets"
 readme = "README.md"
 repository = "https://github.com/rust-embedded/aarch32.git"
 homepage = "https://github.com/rust-embedded/aarch32"
-rust-version = "1.83"
+rust-version = "1.85"
 version = "0.4.2"
 
 [dependencies]
 
 [dev-dependencies]
 temp-env = "0.3"
+
+[lints.rust]
+missing_docs = "warn" # Indicates missing documentation on public functions
+missing_abi = "warn" # Explicit ABI documents the assumptions of the code
+unsafe_op_in_unsafe_fn = "warn" # Satisfies the recommendation in section 4.3.1
+elided_lifetimes_in_paths = "warn" # Highlights confusing implicit use of types with lifetimes
+explicit_outlives_requirements = "warn" # Less explicit lifetime bounds improve readability
+macro_use-extern_crate = "warn" # obscures the source of identifiers
+meta_variable_misuse = "warn" # More macro quality checks outweigh potential false positives
+non-local-definitions = "warn" # Highlights outdated and confusing location of definitions
+redundant-lifetimes = "warn" # Highlights a mistake or unfinished code
+single-use-lifetimes = "warn" # Simplifies code, improving readability
+trivial-numeric-casts = "warn" # Simplifies code, improving readability
+unit-bindings = "warn" # Simplifies code, improving readability
+unnameable-types = "warn" # Highlights inconsistency in public interface
+unreachable-pub = "warn" # Highlights inconsistency in public interface
+variant-size-differences = "warn" # Highlights inefficient data structures
+rust-2018-compatibility = "warn"
+rust-2018-idioms = "warn"
+rust-2021-compatibility = "warn"
+rust-2024-compatibility = "warn"
+unused = { level = "warn", priority = -1 } # this group might overlap
+unused_results = "warn"
+unused-qualifications = "warn"
+unused-lifetimes = "warn"
+unused-import-braces = "warn"
+
+[lints.clippy]
+cast_lossless = "warn" # Indicates a more idiomatic way to replace the cast
+cast_possible_truncation = "warn"
+cast_possible_wrap = "warn"
+cast_ptr_alignment = "warn"
+cast_sign_loss = "warn" # Should be checked for and properly handled in safety related projects
+exit = "warn" # Calling exit directly is likely wrong in a safety related environment
+infinite_loop = "warn" # Indicates improper return type
+iter_over_hash_type = "warn" # Indicates unpredictable order
+invalid_upcast_comparisons = "warn" # Likely wrong code
+lossy_float_literal = "warn" # Indicates rounding error
+missing_errors_doc = "warn" # Indicates incomplete documentation
+missing_docs_in_private_items = "warn" # Undocumented internal items are not an option
+panic_in_result_fn = "warn" # Indicates unexpected behavior
+ptr_cast_constness = "warn"
+ref_as_ptr = "warn"
+transmute_ptr_to_ptr = "warn" # Safer alternative available
+redundant_type_annotations = "warn" # Simpler code, highlights special cases
+shadow_unrelated = "warn" # Unidiomatic and high-risk use of shadowing
+try_err = "warn" # Indicates non-idiomatic way to avoid return
+wildcard_enum_match_arm = "warn" # See section 4.4.21.3, clashes with non-exhaustive
+as_underscore = "warn"
+format_push_string = "warn" # Avoids extra allocation
+as_ptr_cast_mut = "deny" # Clear misuse with a better alternative
+let_underscore_must_use = "deny" # Prevents a shortcut to ignore must-use results
+missing_panics_doc = "deny" # Indicates missing panic documentation
+undocumented_unsafe_blocks = "deny" # Indicates missing "unsafe" reasoning
+wildcard_imports = "deny" # Indicates unconstrained symbol imports
+declare_interior_mutable_const = "deny" # Indicates common mistake
\ No newline at end of file
diff --git a/arm-targets/README.md b/arm-targets/README.md
index 94fbb87a..b8a24b6c 100644
--- a/arm-targets/README.md
+++ b/arm-targets/README.md
@@ -29,7 +29,7 @@ This allows you to write Rust code in your firmware like:
 
 ## Minimum Supported Rust Version (MSRV)
 
-This crate is guaranteed to compile on stable Rust 1.83.0 and up, as recorded
+This crate is guaranteed to compile on stable Rust 1.85.0 and up, as recorded
 by the `package.rust-version` property in `Cargo.toml`.
 
 Increasing the MSRV is not considered a breaking change and may occur in a
diff --git a/arm-targets/src/lib.rs b/arm-targets/src/lib.rs
index 8b8b7b8d..78729018 100644
--- a/arm-targets/src/lib.rs
+++ b/arm-targets/src/lib.rs
@@ -19,7 +19,7 @@
 //! This will then let you write application code like:
 //!
 //! ```rust
-//! #[cfg(arm_architecture = "armv7m")]
+//! #[cfg(arm_architecture = "v7-m")]
 //! fn only_for_cortex_m3() { }
 //!
 //! #[cfg(arm_isa = "a32")]
@@ -40,12 +40,16 @@
 //! cargo:rustc-check-cfg=cfg(arm_abi, values("eabi", "eabihf"))
 //! ```
 
-use std::env;
+use std::{collections::HashSet, env};
 
+/// Describes a target in terms of its support for the Arm architecture
 #[derive(Default, Debug)]
 pub struct TargetInfo {
+    /// The Arm Instruction Set Architecture supported (if known)
     isa: Option<Isa>,
+    /// The Arm Architecture supported (if known)
     arch: Option<Arch>,
+    /// The Application Binary Interface supported (if known)
     abi: Option<Abi>,
 }
 
@@ -88,6 +92,7 @@ impl TargetInfo {
         self.abi
     }
 
+    /// Export a target-info as cargo:rustc-cfg options on stdout.
     fn dump(&self) {
         if let Some(isa) = self.isa() {
             println!(r#"cargo:rustc-cfg=arm_isa="{}""#, isa);
@@ -123,10 +128,17 @@ impl TargetInfo {
     }
 }
 
-/// Process the ${TARGET} environment variable, and emit cargo configuration to
-/// standard out.
+/// Process the `${TARGET}` environment variable, and emit cargo configuration
+/// to standard out.
+///
+/// You probably want to call this from your build script.
+///
+/// When `${TARGET}` isn't known to this library, it falls back to using
+/// `CARGO_CFG_TARGET_*` variables. These are only really useful on nightly Rust
+/// currently, because the ones that give us details about the architecture are
+/// not yet stable.
 pub fn process() -> TargetInfo {
-    let target = std::env::var("TARGET").expect("build script TARGET variable");
+    let target = env::var("TARGET").expect("build script TARGET variable");
     let target_info_from_target = TargetInfo::get(&target);
 
     let target_info_from_cargo_env = TargetInfo::from_cargo_env();
@@ -149,6 +161,9 @@ pub fn process() -> TargetInfo {
 }
 
 /// Process a given target string, and emit cargo configuration to standard out.
+///
+/// Note that this function does not take `CARGO_CFG_TARGET_*` variables into
+/// account so you probably do not want to call this from your build script.
 #[deprecated(
     since = "0.4.2",
     note = "This function does not take `CARGO_CFG_TARGET_*` variables into account."
@@ -162,11 +177,11 @@ pub fn process_target(target: &str) -> TargetInfo {
 /// The Arm Instruction Set
 #[derive(Debug, Copy, Clone, PartialEq, Eq)]
 pub enum Isa {
-    /// A64 instructions are executed by Arm processors in Aarch64 mode
+    /// A64 instructions are executed by Arm processors in AArch64 mode
     A64,
-    /// A32 instructions are executed by Arm processors in Aarch32 Arm mode
+    /// A32 instructions are executed by Arm processors in AArch32 Arm mode
     A32,
-    /// T32 instructions are executed by Arm processors in Aarch32 Thumb mode
+    /// T32 instructions are executed by Arm processors in AArch32 Thumb mode
     T32,
 }
 
@@ -175,7 +190,7 @@ impl Isa {
     pub fn from_cargo_env() -> Option<Self> {
         let arch = env::var("CARGO_CFG_TARGET_ARCH").ok()?;
         let features = env::var("CARGO_CFG_TARGET_FEATURE").ok()?;
-        let features = features.split(",").collect::<Vec<_>>();
+        let features: HashSet<&str> = features.split(",").collect();
 
         match arch.as_str() {
             "arm" if features.contains(&"thumb-mode") => Some(Self::T32),
@@ -258,7 +273,7 @@ impl Arch {
     pub fn from_cargo_env() -> Option<Self> {
         let arch = env::var("CARGO_CFG_TARGET_ARCH").ok()?;
         let features = env::var("CARGO_CFG_TARGET_FEATURE").ok()?;
-        let features = features.split(",").collect::<Vec<_>>();
+        let features: HashSet<&str> = features.split(",").collect();
 
         if (arch == "arm" && features.contains(&"v8")) || arch == "aarch64" {
             if features.contains(&"mclass") {
@@ -334,15 +349,23 @@ impl Arch {
             || target.starts_with("thumbv8r-")
         {
             Some(Arch::Armv8R)
-        } else if target.starts_with("armv7a-") || target.starts_with("thumbv7a-") {
+        } else if target.starts_with("armv7a-")
+            || target.starts_with("armv7-")
+            || target.starts_with("armv7s-")
+            || target.starts_with("armv7k-")
+            || target.starts_with("thumbv7a-")
+            || target.starts_with("thumbv7neon-")
+        {
             Some(Arch::Armv7A)
         } else if target.starts_with("aarch64-") || target.starts_with("aarch64be-") {
             Some(Arch::Armv8A)
         } else if target.starts_with("arm-")
+            || target.starts_with("armeb-")
             || target.starts_with("armv6-")
+            || target.starts_with("armv6k-")
             || target.starts_with("thumbv6-")
         {
-            // If not specified, assume ARMv6.
+            // NB: We assume bare 'arm' is ARMv6.
             Some(Arch::Armv6)
         } else {
             None
diff --git a/arm-targets/src/main.rs b/arm-targets/src/main.rs
index d2da7d9a..79391460 100644
--- a/arm-targets/src/main.rs
+++ b/arm-targets/src/main.rs
@@ -2,19 +2,35 @@
 
 use std::env;
 
+use arm_targets::TargetInfo;
+
 /// Entry point to the program
+#[allow(deprecated)]
 fn main() {
+    let target_info = get_target_info();
+    if let Some(isa) = target_info.isa() {
+        println!("- ISA is {}", isa);
+    } else {
+        println!("- ISA is unknown");
+    }
+    if let Some(arch) = target_info.arch() {
+        println!("- Architecture is {}", arch);
+    } else {
+        println!("- Architecture is unknown");
+    }
+    if let Some(abi) = target_info.abi() {
+        println!("- ABI is {}", abi);
+    } else {
+        println!("- ABI is unknown");
+    }
+}
+
+fn get_target_info() -> TargetInfo {
     if let Some(target) = env::args().nth(1) {
-        println!("// These are the features for the target '{}'", target);
-        #[allow(deprecated)]
-        arm_targets::process_target(&target);
+        println!("These are the features for the target {:?}", target);
+        TargetInfo::get(&target)
     } else {
-        println!("// These are the features this crate enables:");
-        if env::var("TARGET").is_ok() {
-            arm_targets::process();
-        } else {
-            #[allow(deprecated)]
-            arm_targets::process_target("");
-        }
+        eprintln!(r#"I need a target string as an argument, like "armv7a-none-eabi""#);
+        std::process::exit(1);
     }
 }
diff --git a/examples/mps3-an536-el2/src/bin/generic-timer.rs b/examples/mps3-an536-el2/src/bin/generic-timer.rs
index 102a3220..3a20c547 100644
--- a/examples/mps3-an536-el2/src/bin/generic-timer.rs
+++ b/examples/mps3-an536-el2/src/bin/generic-timer.rs
@@ -44,7 +44,7 @@ fn main() -> ! {
     hyp_timer.countdown_set(hyp_timer.frequency_hz() / 5);
     hyp_timer.enable(true);
     // used in interrupt handler
-    drop(hyp_timer);
+    let _ = hyp_timer;
 
     println!("Enabling interrupts...");
     dump_sctlr();
@@ -111,5 +111,5 @@ fn hvc_handler(hsr: u32, frame: &aarch32_rt::Frame) -> u32 {
         hsr.get_iss(),
         frame
     );
-    return frame.r0;
+    frame.r0
 }
diff --git a/examples/mps3-an536-el2/src/bin/hvc-a32.rs b/examples/mps3-an536-el2/src/bin/hvc-a32.rs
index 8d12237b..5bb2aa89 100644
--- a/examples/mps3-an536-el2/src/bin/hvc-a32.rs
+++ b/examples/mps3-an536-el2/src/bin/hvc-a32.rs
@@ -34,7 +34,7 @@ fn hvc_handler(hsr: u32, frame: &aarch32_rt::Frame) -> u32 {
     if hsr.iss().value() == 0xABCD {
         do_hvc2();
     }
-    return 0x12345678;
+    0x12345678
 }
 
 #[instruction_set(arm::a32)]
diff --git a/examples/mps3-an536-el2/src/bin/hvc-t32.rs b/examples/mps3-an536-el2/src/bin/hvc-t32.rs
index 98ad5808..9b63655c 100644
--- a/examples/mps3-an536-el2/src/bin/hvc-t32.rs
+++ b/examples/mps3-an536-el2/src/bin/hvc-t32.rs
@@ -34,7 +34,7 @@ fn hvc_handler(hsr: u32, frame: &aarch32_rt::Frame) -> u32 {
     if hsr.iss().value() == 0xABCD {
         do_hvc2();
     }
-    return 0x12345678;
+    0x12345678
 }
 
 #[instruction_set(arm::t32)]
diff --git a/examples/mps3-an536-el2/src/bin/svc-a32.rs b/examples/mps3-an536-el2/src/bin/svc-a32.rs
index e131b768..02adc0a3 100644
--- a/examples/mps3-an536-el2/src/bin/svc-a32.rs
+++ b/examples/mps3-an536-el2/src/bin/svc-a32.rs
@@ -34,7 +34,7 @@ fn hvc_handler(hsr: u32, frame: &aarch32_rt::Frame) -> u32 {
     if hsr.iss().value() == 0xABCD {
         do_svc2();
     }
-    return 0x12345678;
+    0x12345678
 }
 
 #[instruction_set(arm::a32)]
diff --git a/examples/mps3-an536-el2/src/bin/svc-t32.rs b/examples/mps3-an536-el2/src/bin/svc-t32.rs
index 6957aea0..e542a727 100644
--- a/examples/mps3-an536-el2/src/bin/svc-t32.rs
+++ b/examples/mps3-an536-el2/src/bin/svc-t32.rs
@@ -34,7 +34,7 @@ fn hvc_handler(hsr: u32, frame: &aarch32_rt::Frame) -> u32 {
     if hsr.iss().value() == 0x12 {
         do_svc2();
     }
-    return 0x12345678;
+    0x12345678
 }
 
 #[instruction_set(arm::t32)]
diff --git a/examples/mps3-an536/src/bin/mpu_setup.rs b/examples/mps3-an536/src/bin/mpu_setup.rs
index ae84cac8..42d5881e 100644
--- a/examples/mps3-an536/src/bin/mpu_setup.rs
+++ b/examples/mps3-an536/src/bin/mpu_setup.rs
@@ -6,7 +6,7 @@
 #![no_main]
 
 use aarch32_cpu::pmsav8::{
-    Cacheable, El1AccessPerms, El1Mpu, El1Region, El1Shareability, MemAttr, RwAllocPolicy,
+    CachePolicy, El1AccessPerms, El1Mpu, El1Region, El1Shareability, MemAttr, RwAllocPolicy,
 };
 use aarch32_rt::{entry, sections::Section, stacks::Stack};
 use semihosting::println;
@@ -31,13 +31,13 @@ const MAIR_DEVICE: u8 = 2;
 static MEM_ATTRS: [MemAttr; 8] = [
     // Read-only Code RAM
     MemAttr::NormalMemory {
-        outer: Cacheable::WriteThroughNonTransient(RwAllocPolicy::R),
-        inner: Cacheable::WriteThroughNonTransient(RwAllocPolicy::R),
+        outer: CachePolicy::WriteThroughNonTransient(RwAllocPolicy::R),
+        inner: CachePolicy::WriteThroughNonTransient(RwAllocPolicy::R),
     },
     // Read-write RAM
     MemAttr::NormalMemory {
-        outer: Cacheable::WriteBackNonTransient(RwAllocPolicy::W),
-        inner: Cacheable::WriteBackNonTransient(RwAllocPolicy::W),
+        outer: CachePolicy::WriteBackNonTransient(RwAllocPolicy::W),
+        inner: CachePolicy::WriteBackNonTransient(RwAllocPolicy::W),
     },
     // Device Memory
     MemAttr::DeviceMemory,
diff --git a/examples/mps3-an536/src/bin/registers.rs b/examples/mps3-an536/src/bin/registers.rs
index 46cb0b9d..5fdce39b 100644
--- a/examples/mps3-an536/src/bin/registers.rs
+++ b/examples/mps3-an536/src/bin/registers.rs
@@ -36,7 +36,7 @@ fn chip_info() {
 #[cfg(arm_architecture = "v7-r")]
 fn mpu_pmsa_v7() {
     use aarch32_cpu::{
-        pmsav7::{CacheablePolicy, Config, MemAttr, Mpu, Region, RegionSize},
+        pmsav7::{Cacheable, Config, MemAttr, Mpu, Region, RegionSize},
         register::Mpuir,
     };
 
@@ -69,8 +69,8 @@ fn mpu_pmsa_v7() {
             enabled: true,
             no_exec: false,
             mem_attr: MemAttr::Cacheable {
-                inner: CacheablePolicy::WriteThroughNoWriteAllocate,
-                outer: CacheablePolicy::NonCacheable,
+                inner: Cacheable::WriteThroughNoWriteAlloc,
+                outer: Cacheable::NonCacheable,
                 shareable: true,
             },
         }],
@@ -90,10 +90,10 @@ fn mpu_pmsa_v7() {
 fn mpu_pmsa_v8() {
     use aarch32_cpu::{
         pmsav8::{
-            Cacheable, El1AccessPerms, El1Config, El1Mpu, El1Region, El1Shareability, MemAttr,
+            CachePolicy, El1AccessPerms, El1Config, El1Mpu, El1Region, El1Shareability, MemAttr,
             RwAllocPolicy,
         },
-        register::{Mpuir, armv8r::*},
+        register::*,
     };
 
     // How many regions?
@@ -261,8 +261,8 @@ fn mpu_pmsa_v8() {
             },
         ],
         memory_attributes: &[MemAttr::NormalMemory {
-            outer: Cacheable::WriteThroughNonTransient(RwAllocPolicy::RW),
-            inner: Cacheable::WriteThroughNonTransient(RwAllocPolicy::RW),
+            outer: CachePolicy::WriteThroughNonTransient(RwAllocPolicy::RW),
+            inner: CachePolicy::WriteThroughNonTransient(RwAllocPolicy::RW),
         }],
     })
     .unwrap();
diff --git a/examples/versatileab/reference/registers-armv7r-none-eabi.out b/examples/versatileab/reference/registers-armv7r-none-eabi.out
index de0f7f8e..a1d95060 100644
--- a/examples/versatileab/reference/registers-armv7r-none-eabi.out
+++ b/examples/versatileab/reference/registers-armv7r-none-eabi.out
@@ -20,7 +20,7 @@ DRegion 12: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false
 DRegion 13: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
 DRegion 14: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
 DRegion 15: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
-DRegion 0: Region { base: 0x20000000, size: _16M, subregion_mask: 0, enabled: true, no_exec: false, mem_attr: Cacheable { outer: NonCacheable, inner: WriteThroughNoWriteAllocate, shareable: true } }
+DRegion 0: Region { base: 0x20000000, size: _16M, subregion_mask: 0, enabled: true, no_exec: false, mem_attr: Cacheable { outer: NonCacheable, inner: WriteThroughNoWriteAlloc, shareable: true } }
 DRegion 1: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
 DRegion 2: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
 DRegion 3: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
diff --git a/examples/versatileab/reference/registers-armv7r-none-eabihf.out b/examples/versatileab/reference/registers-armv7r-none-eabihf.out
index de0f7f8e..a1d95060 100644
--- a/examples/versatileab/reference/registers-armv7r-none-eabihf.out
+++ b/examples/versatileab/reference/registers-armv7r-none-eabihf.out
@@ -20,7 +20,7 @@ DRegion 12: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false
 DRegion 13: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
 DRegion 14: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
 DRegion 15: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
-DRegion 0: Region { base: 0x20000000, size: _16M, subregion_mask: 0, enabled: true, no_exec: false, mem_attr: Cacheable { outer: NonCacheable, inner: WriteThroughNoWriteAllocate, shareable: true } }
+DRegion 0: Region { base: 0x20000000, size: _16M, subregion_mask: 0, enabled: true, no_exec: false, mem_attr: Cacheable { outer: NonCacheable, inner: WriteThroughNoWriteAlloc, shareable: true } }
 DRegion 1: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
 DRegion 2: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
 DRegion 3: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
diff --git a/examples/versatileab/reference/registers-thumbv7r-none-eabi.out b/examples/versatileab/reference/registers-thumbv7r-none-eabi.out
index de0f7f8e..a1d95060 100644
--- a/examples/versatileab/reference/registers-thumbv7r-none-eabi.out
+++ b/examples/versatileab/reference/registers-thumbv7r-none-eabi.out
@@ -20,7 +20,7 @@ DRegion 12: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false
 DRegion 13: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
 DRegion 14: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
 DRegion 15: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
-DRegion 0: Region { base: 0x20000000, size: _16M, subregion_mask: 0, enabled: true, no_exec: false, mem_attr: Cacheable { outer: NonCacheable, inner: WriteThroughNoWriteAllocate, shareable: true } }
+DRegion 0: Region { base: 0x20000000, size: _16M, subregion_mask: 0, enabled: true, no_exec: false, mem_attr: Cacheable { outer: NonCacheable, inner: WriteThroughNoWriteAlloc, shareable: true } }
 DRegion 1: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
 DRegion 2: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
 DRegion 3: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
diff --git a/examples/versatileab/reference/registers-thumbv7r-none-eabihf.out b/examples/versatileab/reference/registers-thumbv7r-none-eabihf.out
index de0f7f8e..a1d95060 100644
--- a/examples/versatileab/reference/registers-thumbv7r-none-eabihf.out
+++ b/examples/versatileab/reference/registers-thumbv7r-none-eabihf.out
@@ -20,7 +20,7 @@ DRegion 12: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false
 DRegion 13: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
 DRegion 14: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
 DRegion 15: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
-DRegion 0: Region { base: 0x20000000, size: _16M, subregion_mask: 0, enabled: true, no_exec: false, mem_attr: Cacheable { outer: NonCacheable, inner: WriteThroughNoWriteAllocate, shareable: true } }
+DRegion 0: Region { base: 0x20000000, size: _16M, subregion_mask: 0, enabled: true, no_exec: false, mem_attr: Cacheable { outer: NonCacheable, inner: WriteThroughNoWriteAlloc, shareable: true } }
 DRegion 1: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
 DRegion 2: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
 DRegion 3: Region { base: 0x0, size: Invalid, subregion_mask: 0, enabled: false, no_exec: false, mem_attr: StronglyOrdered }
diff --git a/examples/versatileab/src/bin/registers.rs b/examples/versatileab/src/bin/registers.rs
index 7951be3c..e882dbb9 100644
--- a/examples/versatileab/src/bin/registers.rs
+++ b/examples/versatileab/src/bin/registers.rs
@@ -29,7 +29,7 @@ fn chip_info() {
 #[cfg(arm_architecture = "v7-r")]
 fn mpu_pmsa_v7() {
     use aarch32_cpu::{
-        pmsav7::{CacheablePolicy, Config, MemAttr, Mpu, Region, RegionSize},
+        pmsav7::{CachePolicy, Config, MemAttr, Mpu, Region, RegionSize},
         register::Mpuir,
     };
 
@@ -62,8 +62,8 @@ fn mpu_pmsa_v7() {
             enabled: true,
             no_exec: false,
             mem_attr: MemAttr::Cacheable {
-                inner: CacheablePolicy::WriteThroughNoWriteAllocate,
-                outer: CacheablePolicy::NonCacheable,
+                inner: CachePolicy::WriteThroughNoWriteAlloc,
+                outer: CachePolicy::NonCacheable,
                 shareable: true,
             },
         }],
diff --git a/examples/versatileab/src/mmu.rs b/examples/versatileab/src/mmu.rs
index 60da0210..afe918a0 100644
--- a/examples/versatileab/src/mmu.rs
+++ b/examples/versatileab/src/mmu.rs
@@ -18,7 +18,7 @@
 //! all the hardware either on the real board or emulated by QEMU.
 
 use aarch32_cpu::mmu::{
-    AccessPermissions, CacheableMemoryAttribute, L1Section, L1Table, MemoryRegionAttributes,
+    AccessPermissions, CachePolicy, L1Section, L1Table, MemoryRegionAttributes,
     NUM_L1_PAGE_TABLE_ENTRIES, SectionAttributes,
 };
 use arbitrary_int::u4;
@@ -32,8 +32,8 @@ const SDRAM_ATTRS: SectionAttributes = SectionAttributes {
     shareable: true,
     access: AccessPermissions::FullAccess,
     memory_attrs: MemoryRegionAttributes::CacheableMemory {
-        inner: CacheableMemoryAttribute::WriteBackWriteAlloc,
-        outer: CacheableMemoryAttribute::WriteBackWriteAlloc,
+        inner: CachePolicy::WriteBackWriteAlloc,
+        outer: CachePolicy::WriteBackWriteAlloc,
     }
     .as_raw(),
     domain: u4::new(0b0),
@@ -84,7 +84,7 @@ pub fn set_mmu() {
         .with_address(core::ptr::addr_of!(MMU_L1_PAGE_TABLE) as usize)
         .with_irgn(false)
         .with_nos(false)
-        .with_rgn(aarch32_cpu::register::ttbr0::Region::WriteBackWriteAllocateCacheable)
+        .with_rgn(aarch32_cpu::register::ttbr0::Region::WriteBackWriteAllocCacheable)
         .with_s(true)
         .with_c(true);
     unsafe { aarch32_cpu::register::Ttbr0::write(ttbr0) }
diff --git a/justfile b/justfile
index 07e66086..57a2b8a6 100644
--- a/justfile
+++ b/justfile
@@ -11,7 +11,6 @@ export RUSTC_BOOTSTRAP := "1"
 # If you run with `just --set v 1` then we make cargo run in verbose mode
 v := "0"
 verbose := if v == "1" { "--verbose" } else { "" }
-nightly := "nightly-2026-02-26"
 
 # Our default target. It does everything that you might want to do pre-checkin.
 check: build-all build-all-examples fmt-check clippy-examples clippy-targets clippy-host test
@@ -57,14 +56,14 @@ build-arm-targets:
 
 # Builds our workspace with various features, building core from source, but skipping anything that requires atomics
 build-tier3-no-atomics target:
-    cargo +{{nightly}} build --target {{target}} -Zbuild-std=core {{verbose}}
-    cargo +{{nightly}} build --target {{target}} -Zbuild-std=core --features "serde, defmt, critical-section-single-core, check-asm" {{verbose}}
+    cargo build --target {{target}} -Zbuild-std=core {{verbose}}
+    cargo build --target {{target}} -Zbuild-std=core --features "serde, defmt, critical-section-single-core, check-asm" {{verbose}}
 
 # Builds our workspace with various features, building core from source
 build-tier3 target:
-    cargo +{{nightly}} build --target {{target}} -Zbuild-std=core {{verbose}}
-    cargo +{{nightly}} build --target {{target}} -Zbuild-std=core --features "serde, defmt, critical-section-multi-core, check-asm" {{verbose}}
-    cargo +{{nightly}} build --target {{target}} -Zbuild-std=core --features "serde, defmt, critical-section-single-core, check-asm" {{verbose}}
+    cargo build --target {{target}} -Zbuild-std=core {{verbose}}
+    cargo build --target {{target}} -Zbuild-std=core --features "serde, defmt, critical-section-multi-core, check-asm" {{verbose}}
+    cargo build --target {{target}} -Zbuild-std=core --features "serde, defmt, critical-section-single-core, check-asm" {{verbose}}
 
 # Builds our workspace with various features
 build-tier2 target: