diff --git a/docs/spec/isa.mdx b/docs/spec/isa.mdx
deleted file mode 100644
index 565721a18..000000000
--- a/docs/spec/isa.mdx
+++ /dev/null
@@ -1,51 +0,0 @@
----
-id: isa
-title: ISA Manuals
-sidebar_position: 4
-hide_table_of_contents: true
----
-
-import siteConfig from '@site/docusaurus.config';
-
-## Instruction Set (ISA) Manual's
-
-These are the current ratified versions of the ISA specifications. Previously published versions and the original ratification specifications for included extensions can be found on the [RISC-V Technical Specifications Archive page](https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154899/RISC-V+Technical+Specifications+Archive).
-
-
-
-
-
-
-
-
- The older profiles. Archived for historical purposes
-
-
-
-
-
-
-
-
-
diff --git a/docs/spec/profiles/riscv-profiles.mdx b/docs/spec/profiles/riscv-profiles.mdx
index 9f38c97b3..9710343c9 100644
--- a/docs/spec/profiles/riscv-profiles.mdx
+++ b/docs/spec/profiles/riscv-profiles.mdx
@@ -4,8 +4,24 @@ hide_table_of_contents: true
pdf: "/pdf/RISC-V_Profiles2024-12-02.pdf"
---
+# RISC-V Profiles
-Provides the processor-specific application binary interface document for RISC-V.
+Base profile overview with RVA20, RVI20, and RVA22 profile definitions.
-
-
\ No newline at end of file
+*Latest version: 1.0 Date: March 2023*
+
+[PDF](https://drive.google.com/file/d/1Kg7Ner5ZlxFDclf92-9Tz88JvmZWt5Wb/view)
+
+# **Details**
+
+| RISC-V Community: | [Profiles SIG](https://lists.riscv.org/g/sig-profiles) |
+| :---- | :---- |
+| **Source:** | [riscv/riscv-profiles](https://github.com/riscv/riscv-profiles) |
+
+# **History**
+
+All published versions of the specification are listed below from newest to oldest.
+
+| Version | Publish Date | View |
+| :---- | :---: | :---- |
+| 1.0 | March 2023 | [PDF](https://drive.google.com/file/d/1Kg7Ner5ZlxFDclf92-9Tz88JvmZWt5Wb/view) |
diff --git a/docs/spec/profiles/rva23.mdx b/docs/spec/profiles/rva23.mdx
index 23d904e07..e42f5d5e2 100644
--- a/docs/spec/profiles/rva23.mdx
+++ b/docs/spec/profiles/rva23.mdx
@@ -4,7 +4,25 @@ id: rva23
hide_table_of_contents: true
pdf: '/pdf/rva23-profile.pdf'
---
-Provides the processor-specific application binary interface document for RISC-V.
+# RVA23 Profile
+
+A Profile focused on Servers and application class processors.
+
+*Latest version: 1.0 Date: October 2024*
+
+[PDF](https://drive.google.com/file/d/12QKRm92cLcEk8-5J9NI91m0fAQOxqNAq/view?usp=drive_link)
+
+# **Details**
+
+| RISC-V Community: | [Profiles SIG](https://lists.riscv.org/g/sig-profiles) |
+| :---- | :---- |
+| **Source:** | [riscv/riscv-profiles](https://github.com/riscv/riscv-profiles) |
+
+# **History**
+
+All published versions of the specification are listed below from newest to oldest.
+
+| Version | Publish Date | View |
+| :---- | :---: | :---- |
+| 1.0 | October 2024 | [PDF](https://drive.google.com/file/d/12QKRm92cLcEk8-5J9NI91m0fAQOxqNAq/view?usp=drive_link) |
-
-
\ No newline at end of file
diff --git a/docs/spec/profiles/rvb23.mdx b/docs/spec/profiles/rvb23.mdx
index c383e65f9..35ef02828 100644
--- a/docs/spec/profiles/rvb23.mdx
+++ b/docs/spec/profiles/rvb23.mdx
@@ -4,7 +4,25 @@ id: rvb23
hide_table_of_contents: true
pdf: "/pdf/rvb23-profile.pdf"
---
-Provides the processor-specific application binary interface document for RISC-V.
+# RVB23 Profile
-
-
\ No newline at end of file
+
+A Profile focused on edge embedded devices.
+
+*Latest version: 1.0 Date: October 2024*
+
+[PDF](https://drive.google.com/file/d/1pBQAeTasG6smBxZc_zLkQU1GPA4Zngo7/view?usp=drive_link)
+
+# **Details**
+
+| RISC-V Community: | [Profiles SIG](https://lists.riscv.org/g/sig-profiles) |
+| :---- | :---- |
+| **Source:** | [riscv/riscv-profiles](https://github.com/riscv/riscv-profiles) |
+
+# **History**
+
+All published versions of the specification are listed below from newest to oldest.
+
+| Version | Publish Date | View |
+| :---- | :---: | :---- |
+| 1.0 | October 2024 | [PDF](https://drive.google.com/file/d/1pBQAeTasG6smBxZc_zLkQU1GPA4Zngo7/view?usp=drive_link) |
diff --git a/docs/spec/reference.mdx b/docs/spec/reference.mdx
index d31339c25..0ac99a145 100644
--- a/docs/spec/reference.mdx
+++ b/docs/spec/reference.mdx
@@ -3,44 +3,55 @@ id: reference
title: Reference
sidebar_position: 1
hide_table_of_contents: true
+hide_title: true
---
import siteConfig from '@site/docusaurus.config';
-The RISC-V Library contains a comprehensive list of all of the ratified RISC-V technical publications.
+## ISA Specifications
-## Instruction Set (ISA) Specifications
-
-These are the current ratified versions of the ISA specifications. Previously published versions and the original ratification specifications for included extensions can be found on the [RISC-V Technical Specifications Archive page](https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154899/RISC-V+Technical+Specifications+Archive).
+These are the current, published versions of the ISA specifications. See the “More…” links for details on each specification such as community details, source repositories, recently ratified extensions, older versions, and project archives.
-
+
-
Volume I
+
Unprivileged Architecture
- Unprivileged Architecture
+ ISA Volume I
+ Version: 20250508 Date: May 2025
-
+ {/*
-
+ */}
+ HTML
+ |
+ PDF
+ |
+ More ...
-
+
-
Volume II
+
Privileged Architecture
- Privileged Architecture
+ ISA Volume II
+ Version: 20250508 Date: May 2025
-
+ {/*
-
+ */}
+ HTML
+ |
+ PDF
+ |
+ More ...
@@ -53,96 +64,121 @@ Extensions that are ratified, but not yet included in the full specifications, c
---
## Profiles
-These are the current, published versions of the Profiles specifications.
+These are the current, published versions of the Profiles specifications. See the “More…” links for details on each specification such as community details, source repositories, and older versions.
+
-
+
RVA23 Profile
Focused on Servers and application class processors.
+ Version: 1.0 Date: October 2024
-
+ {/*
-
+ */}
+ PDF
+ |
+ More ...
-
+
RVB23 Profile
- Focused on Edge embedded Devices.
+ Focused on Edge embedded Devices.
+ Version: 1.0 Date: October 2024
-
+ {/*
-
+ */}
+ PDF
+ |
+ More ...
-
+
RISC-V Profiles
- Base profile overview with RVA20, RVI20, and RVA22 profile definitions.
+ The older profiles. Archived for historical purposes
+ Version: 1.0 Date: March 2023
-
+ {/*
-
+ */}
+ PDF
+ |
+ More ...
---
-## Processor Infrastructure
-- [RISC-V Advanced Interrupt Architecture](./non-isa/advanced-interrupt)
-- [RISC-V IO Mapping Table Specification](./non-isa/io-mapping)
-- [RISC-V IOMMU Architecture Specification ](./non-isa/iommu-architecture)
-- [RISC-V Platform-Level Interrupt Controller Specification](./non-isa/platform-interrupt)
-- [RISC-V Server SOC Specification](./non-isa/server-soc)
-
-## Debug, Trace, & RAS
-- [The RISC-V Debug Specification](./non-isa/debug)
-- [Efficient Trace for RISC-V](./non-isa/efficient-trace)
-- [RISC-V N-Trace (Nexus-based Trace)](./non-isa/n-trace)
-- [RISC-V Capacity and Bandwidth QoS Register Interface](./non-isa/qos)
-- [RISC-V RERI Architecture Specification](./non-isa/reri)
-- [RISC-V Trace Connectors](./non-isa/trace-conectors)
-- [RISC-V Trace Control Interface](./non-isa/trace-control-interface)
-- [Unformatted Trace & Diagnostic Data Packet Encapsulation for RISC-V](./non-isa/unformatted-trace)
-
-## Platform Software
-- [RISC-V Functional Fixed Hardware Specification](./non-isa/functional-fixed)
-- [RISC-V Semihosting](./non-isa/semihosting)
-- [RISC-V Supervisor Binary Interface Specification](./non-isa/sbi)
-- [RISC-V UEFI Protocol Specification](./non-isa/uefi)
-
-## Application Software
-- [RISC-V ABIs Specification](./non-isa/abi)
-
-## Guides
-- [Authoring and Editing RISC-V Specifications](https://github.com/riscv/docs-dev-guide/releases/tag/v0.2.0-example)
-
-## Glossary
-- Terms
-- Acronyms
-- Alphabetical listing of Extensions
-- CSRs
----
+# Non-ISA Hardware Specifications
+
+These are the current, published versions of the non-ISA hardware specifications. See the “More…” links for details on each specification such as community details, source repositories, and older versions.
+
+| | Version | Published | Updated |
+| :---- | :---: | :---: | ----- |
+| **RISC-V Advanced Interrupt Architecture** Describes an Advanced Interrupt Architecture for RISC-V systems. [PDF](https://drive.google.com/file/d/16life2Y5u7Plebbl4v1fFM1-NK-KHw0Y/view?usp=sharing) | [More…](https://riscv.atlassian.net/wiki/spaces/HOME/pages/806289428) | 1.0 | June 2023 | |
+| **RISC-V IOMMU Architecture Specification** Describes an Input-Output Memory Management Unit (IOMMU) that connects direct-memory-access-capable Input/Output (I/O) devices to system memory. [PDF](https://drive.google.com/file/d/1kVapIJPXUUNFQv_yauCDgtWzMvpgh6C2/view?usp=drive_link) | [More…](https://riscv.atlassian.net/wiki/spaces/HOME/pages/806617089) | 1.0 | June 2023 | August 2025 |
+| **RISC-V Platform-Level Interrupt Controller Specification** Delineates the operational parameters for a platform-level interrupt controller on RISC-V. [PDF](https://drive.google.com/file/d/1at94PNJl4v2eAsKIwKOsZWBxsVcY2U2F/view?usp=drive_link) | [More…](https://riscv.atlassian.net/wiki/spaces/HOME/pages/806617106) | 1.0.0 | February 2023 | |
+| **RISC-V Server SOC Specification** Defines a standardized set of capabilities that portable system software such as operating systems and hypervisors, can rely on being present in a RISC-V server SoC. [PDF](https://drive.google.com/file/d/1KjewRE0NltEmbKOz7YlgOsTF51lZ6aPL/view?usp=sharing) | [More…](https://riscv.atlassian.net/wiki/spaces/HOME/pages/806617123) | 1.0 | February 2025 | |
+
:::note
-If you do not see a specification in this library, visit the [RISC-V GitHub `riscv-non-isa`](https://github.com/riscv-non-isa) organization to see a complete list of all specifications that have been developed or are presently under development.
+If you do not see a specification in the above table, visit the RISC-V GitHub [riscv-non-isa](https://github.com/riscv-non-isa) organization to see a complete list of all specifications which have been developed or are presently under development.
:::
-
+
+# Software Specifications
+
+These are the current, published versions of the software specifications. Prior published versions can be found on the [RISC-V Technical Specifications Archive page](https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154899).
+
+## Debug, Trace, RAS
+
+| | Version | Published | Updated |
+| :---- | :---: | :---: | :---: |
+| **Efficient Trace for RISC-V** Specifies the signals between the RISC-V core and the encoder, compressed branch trace algorithm, and the packet format used to encapsulate the compressed branch trace information to implement processor tracing. [PDF](https://drive.google.com/file/d/1iijHsZB7YXW0A2HuuzHo5QTZSKrO_KbW/view?usp=drive_link) | [More…](https://riscv.atlassian.net/wiki/spaces/HOME/pages/809926657) | 2.0 | June 2022 | June 2025 |
+| **RISC-V Capacity and Bandwidth QoS Register Interface** Specifies: QoS identifiers to identify workloads that originate requests to the shared resources. Access-type identifiers to accompany request to access a shared resource to allow differentiated treatment of each access-type. Register interface for capacity allocation in controllers such as shared caches, directories, etc. Register interface for capacity usage monitoring. Register interface for bandwidth allocation in controllers such as interconnect and memory controllers. Register interface for bandwidth usage monitoring. [PDF](https://drive.google.com/file/d/1XSKqg6MXEmRdpdUYLj-Q03kZD6TDQhtu/view?usp=drive_link) | [More…](https://riscv.atlassian.net/wiki/spaces/HOME/pages/809697292) | 1.0 | June 2024 | |
+| **The RISC-V Debug Specification** Outlines a standard architecture for debug support on RISC-V hardware platforms. This architecture allows a variety of implementations and tradeoffs, which is complementary to the wide range of RISC-V implementations. At the same time, this specification defines common interfaces to allow debugging tools and components to target a variety of hardware platforms based on the RISC-V ISA. [PDF](https://drive.google.com/file/d/1h_f9NgB_8m2fS6uCnKP1Oho-3x1MpBEl/view?usp=drive_link) | [More…](https://riscv.atlassian.net/wiki/spaces/HOME/pages/809926674) | 1.0 | February 2025 | |
+| **RISC-V N-Trace (Nexus-based Trace)** Implements the IEEE-5001 Nexus Standard tailored to support the trace of RISC-V ISA cores, harts and SoC/MCU designs. [PDF](https://drive.google.com/file/d/1UXFptcTjd5akPhKRtn0onBC6t53O61qU/view?usp=drive_link) | [More…](https://riscv.atlassian.net/wiki/spaces/HOME/pages/809926691) | 1.0 | November 2024 | |
+| **RISC-V RERI Architecture Specification** Augments Reliability, Availability, and Serviceability (RAS) features in the SoC with a standard mechanism for reporting errors by means of a memory-mapped register interface to enable error reporting. Additionally, this specification supports software-initiated error logging, reporting, and testing of RAS handlers. Lastly, this specification provides maximal flexibility to implement error handling and coexists with RAS frameworks defined by other standards such as PCIe and CXL. [PDF](https://drive.google.com/file/d/19gMRFbWDrfDZKyqoO3iFkySPvKpxm26a/view?usp=drive_link) | [More…](https://riscv.atlassian.net/wiki/spaces/HOME/pages/809697310) | 1.0 | May 2024 | |
+| **RISC-V Trace Connectors** Adds trace signals to connectors described in [RISC-V External Debug Support](https://riscv.atlassian.net/wiki/spaces/HOME/pages/805568530/RISC-V+Technical+Specifications+Proposed#The-RISC-V-Debug-Specification) and provides a small, optional extension to connectors described in and MIPI Debug & Trace Connectors Recommendations White Paper, Version 1.20, 2 July 2021\. [PDF](https://drive.google.com/file/d/1SMypv0CUL338L-sURMyJuO60WZ7oDi9V/view?usp=drive_link) | [More…](https://riscv.atlassian.net/wiki/spaces/HOME/pages/810057729) | 1.0 | November 2024 | |
+| **RISC-V Trace Control Interface** Presents a standardized control interface for RISC-V trace infrastructure (such as trace encoders, trace funnels, trace sinks) for the [Efficient Trace for RISC-V](https://riscv.atlassian.net/wiki/spaces/HOME/pages/805568530/RISC-V+Technical+Specifications+Proposed#Efficient-Trace-for-RISC-V) specification and for the [RISC-V N-Trace (Nexus-based Trace)](https://riscv.atlassian.net/wiki/spaces/HOME/pages/805568530/RISC-V+Technical+Specifications+Proposed#RISC-V-N-Trace-\(Nexus-based-Trace\)) specification. Standardized control interface allows trace control software development tools to be used interchangeably with any RISC-V device implementing processor and/or data trace. [PDF](https://drive.google.com/file/d/1ZQvU1WNamY5EHGum4yP1z-WmPrcxH2b8/view?usp=drive_link) | [More…](https://riscv.atlassian.net/wiki/spaces/HOME/pages/810057747) | 1.0 | November 2024 | |
+| **Unformatted Trace & Diagnostic Data Packet Encapsulation for RISC-V** Defines an encapsulation format suitable for use with a variety of transport mechanisms, including but not limited to AMBA Advanced Trace Bus (ATB) and Siemens' Messaging Infrastructure. [PDF](https://drive.google.com/file/d/1R-_koXIpdb9_qW6jpz74TSnNXOfJGhfn/view?usp=drive_link) | [More…](https://riscv.atlassian.net/wiki/spaces/HOME/pages/810057766) | 1.0 | June 2024 | |
+
+## Platform Software Specifications
+
+| | Version | Published | Updated |
+| :---- | :---: | :---: | ----- |
+| **RISC-V Boot and Runtime Services Specification (BRS)** Defines a standardized set of software capabilities, that portable system software, such as operating systems and hypervisors, can rely on being present in an implementation to utilize in acts of device discovery, OS boot and hand-off, system management, and other operations. [PDF](https://drive.google.com/file/d/1ZvEa5AX3j7FXmXW5H1chIMVkyjJGmFmh/view?usp=sharing) | [More…](https://riscv.atlassian.net/wiki/spaces/HOME/pages/809926709) | 1.0 | August 2025 | |
+| **RISC-V Functional Fixed Hardware Specification** Provides additional system specification for RISC-V systems which use Advanced Configuration and Power Interface (ACPI), specifically for some ACPI object fields of type “Resource Descriptor”. [PDF](https://drive.google.com/file/d/1XzlA0LE4N5_47wJXsU3aqyD69pHGvdcL/view?usp=drive_link) | [More…](https://riscv.atlassian.net/wiki/spaces/HOME/pages/810057786) | 1.0.1 | January 2024 | October 2024 |
+| **RISC-V IO Mapping Table Specification** Provides information about the RISC-V IOMMU and the relationship between the IO topology and the IOMMU in ACPI based RISC-V platforms. The RIMT identifies which components are behind IOMMU and how they are connected together. [PDF](https://drive.google.com/file/d/1sxQ3iQ1l5Jgq9tukvGMnucRUvY16s8zN/view?usp=sharing) | [More…](https://riscv.atlassian.net/wiki/spaces/HOME/pages/809926726) | 1.0 | March 2025 | |
+| **RISC-V Platform Management Interface Specification (RPMI)** Describes an OS-agnostic, firmware-agnostic, scalable and extensible interface for platform management and control from dedicated microcontrollers (also referred to as platform microcontroller or PuC). [PDF](https://drive.google.com/file/d/1DeN7MZcH4ER7dTIQnmCjTx2PafxkuGVU/view?usp=drive_link) | [More…](https://riscv.atlassian.net/wiki/spaces/HOME/pages/810057803) | 1.0 | July 2025 | |
+| **RISC-V Semihosting** Defines the semihosting binary interface for RISC-V platforms. [PDF](https://drive.google.com/file/d/1qu74D4_EmjGmc03qzfQ7Pf4g6m0fOtcD/view?usp=sharing) | [More…](https://riscv.atlassian.net/wiki/spaces/HOME/pages/810057820) | 1.0 | February 2025 | |
+| **RISC-V Supervisor Binary Interface Specification** The RISC-V Supervisor Binary Interface, allows supervisor-mode (S-mode or VS-mode) software to be portable across all RISC-V implementations by defining an abstraction for platform (or hypervisor) specific functionality. The design of the SBI follows the general RISC-V philosophy of having a small core along with a set of optional modular extensions. Version 3.0 adds PMU event information and base event type; new extensions for MPXY, DBTR, FWFT, and SSE; additional error codes; and clarifications in the set\_timer function and IPI and RFENCE error codes. [PDF](https://drive.google.com/file/d/1RHY5Gj0cDSrY5BlK6pGblZt03fDRF2-g/view?usp=drive_link) | [More…](https://riscv.atlassian.net/wiki/spaces/HOME/pages/810057837) | 3.0.0 | July 2025 | |
+| **RISC-V UEFI Protocol Specification** Details all new UEFI protocols required only for RISC-V platforms. [PDF](https://drive.google.com/file/d/1rbQDRkoeJyqTKTI6tTCKw8zmh7T9dLUZ/view?usp=drive_link) | [More…](https://riscv.atlassian.net/wiki/spaces/HOME/pages/810057854) | 1.0.0 | May 2022 | |
+
+## Application Enablement Specifications
+
+| | Version | Published | Updated |
+| :---- | :---: | :---: | ----- |
+| **RISC-V ABIs Specification** Provides the processor-specific application binary interface document for RISC-V. [PDF](https://drive.google.com/file/d/1Ja_Tpp_5Me583CGVD-BIZMlgGBnlKU4R/view?usp=drive_link) | [More…](https://riscv.atlassian.net/wiki/spaces/HOME/pages/810057873) | 1.0 | November 2022 | |
+| **RISC-V Vector C Intrinsic Specification** Provide user interfaces in the C language level to directly leverage the RISC-V Vector Extensions with assistance from the compiler in handling instruction scheduling and register allocation. The intrinsics also free users from responsibility of maintaining the correct configuration settings for the vector instruction executions. [PDF](https://drive.google.com/file/d/1RTZi2iOLKzqaX95JCCnzwOm7iCIN3JEq/view?usp=drive_link) | [More…](https://riscv.atlassian.net/wiki/spaces/HOME/pages/810057854) | 1.0 | April 2025 | |
+
diff --git a/sidebars.ts b/sidebars.ts
index 3d801454d..bcaf695ec 100644
--- a/sidebars.ts
+++ b/sidebars.ts
@@ -46,15 +46,25 @@ const sidebars: SidebarsConfig = {
label:'The ISA Specification',
// link: {type: 'doc', id: 'spec/isa'},
items:[
+ // {
+ // type:"link",
+ // label:"ISA Volume 1: Priv",
+ // href:"pathname:///docs/reference/isa/unpriv/intro.html",
+ // },
+ // {
+ // type:"link",
+ // label:"ISA Volume 2: Un-Priv",
+ // href:"pathname:///docs/reference/isa/priv/priv-intro.html",
+ // },
{
- type:"link",
- label:"ISA Volume 1: Priv",
- href:"pathname:///docs/reference/isa/unpriv/intro.html",
+ type:"doc",
+ label:"ISA Volume 1: UnPrivileged",
+ id:"spec/isa1",
},
{
- type:"link",
- label:"ISA Volume 2: Un-Priv",
- href:"pathname:///docs/reference/isa/priv/priv-intro.html",
+ type:"doc",
+ label:"ISA Volume 2: Privileged",
+ id:"spec/isa2",
},
],
@@ -113,11 +123,13 @@ const sidebars: SidebarsConfig = {
label:'Platform Software',
collapsed:true,
items:[
+ 'spec/non-isa/brs',
'spec/non-isa/functional-fixed',
+ 'spec/non-isa/io-mapping',
+ 'spec/non-isa/rpmi',
'spec/non-isa/semihosting',
'spec/non-isa/sbi',
'spec/non-isa/uefi',
- 'spec/non-isa/io-mapping',
],
},
{
@@ -126,6 +138,7 @@ const sidebars: SidebarsConfig = {
collapsed:true,
items:[
'spec/non-isa/abi',
+ 'spec/non-isa/vector-c',
],
},
// {
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diff --git a/static/pdf/vector-c.pdf b/static/pdf/vector-c.pdf
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