The name DAG is a bit confusing in that the term "DAG" is not the best name to describe it. It is actually the "Sequence Representation" in our paper (https://arxiv.org/pdf/2204.09033.pdf, page 4, section 3.1).
I am considering renaming it to CircuitSeq to avoid confusion. Here is the complete renaming plan:
DAG -> CircuitSeqDAGNode -> CircuitWireDAGHyperEdge -> CircuitGate (I am not sure if this is clear enough that this is a gate in a circuit and easily distinguishable with the abstract Gate type)DAG::nodes -> CircuitSeq::wiresDAG::edges -> CircuitSeq::gatesDAGNode::input_edges -> CircuitWire::input_gatesDAGNode::output_edges -> CircuitWire::output_gatesDAGHyperEdge::input_nodes -> CircuitGate::input_wiresDAGHyperEdge::output_nodes -> CircuitGate::output_wiresGraph::to_dag -> Graph::to_circuit_sequence
Do you think the new names are clear? Any suggestions are welcome.
Edit after merging #61: the class name is renamed, but there are a lot of variable names still being dag. Help wanted for renaming these to seq :)
The name
DAGis a bit confusing in that the term "DAG" is not the best name to describe it. It is actually the "Sequence Representation" in our paper (https://arxiv.org/pdf/2204.09033.pdf, page 4, section 3.1).I am considering renaming it to
CircuitSeqto avoid confusion. Here is the complete renaming plan:DAG->CircuitSeqDAGNode->CircuitWireDAGHyperEdge->CircuitGate(I am not sure if this is clear enough that this is a gate in a circuit and easily distinguishable with the abstractGatetype)DAG::nodes->CircuitSeq::wiresDAG::edges->CircuitSeq::gatesDAGNode::input_edges->CircuitWire::input_gatesDAGNode::output_edges->CircuitWire::output_gatesDAGHyperEdge::input_nodes->CircuitGate::input_wiresDAGHyperEdge::output_nodes->CircuitGate::output_wiresGraph::to_dag->Graph::to_circuit_sequenceDo you think the new names are clear? Any suggestions are welcome.
Edit after merging #61: the class name is renamed, but there are a lot of variable names still being
dag. Help wanted for renaming these toseq:)