diff --git a/.gitignore b/.gitignore index 4319689c..f2898294 100644 --- a/.gitignore +++ b/.gitignore @@ -10,6 +10,7 @@ snitch_cluster deps/ *.OLD *.egg-info/ +*compile.log # EMACS diff --git a/Bender.local b/Bender.local new file mode 100644 index 00000000..00fd9d2b --- /dev/null +++ b/Bender.local @@ -0,0 +1,3 @@ +overrides: + common_cells: { git: "https://github.com/pulp-platform/common_cells.git", rev: ca9d577f2fbc45ec557ab4e0905bbfc154441540 } # snitch branch from 15.12.25 commit "Add iomsb function used in most other PULP repos" + axi: { git: "https://github.com/colluca/axi", rev: bd1abffc0812f8170902e5fb93142c7785c0b8c1 } # idma: { git: "https://github.com/pulp-platform/iDMA.git", rev: 28a36e5e07705549e59fc33db96ab681bc1ca88e} diff --git a/Bender.lock b/Bender.lock index 7b85b9c4..5683c4ba 100644 --- a/Bender.lock +++ b/Bender.lock @@ -17,7 +17,7 @@ packages: - obi_peripherals - register_interface axi: - revision: 8e04779f341eb2c89412aae92223a292beef487e + revision: bd1abffc0812f8170902e5fb93142c7785c0b8c1 version: null source: Git: https://github.com/colluca/axi @@ -37,8 +37,8 @@ packages: - register_interface - tech_cells_generic axi_riscv_atomics: - revision: 0ac3a78fe342c5a5b9b10bff49d58897f773059e - version: 0.8.2 + revision: 97a1dd2ac643c276880420a0cf8eea697f228aa9 + version: 0.8.3 source: Git: https://github.com/pulp-platform/axi_riscv_atomics.git dependencies: @@ -71,7 +71,7 @@ packages: - common_cells - register_interface cheshire: - revision: 1b6ba6294a5925a5dc199b4f98704adb76648ed1 + revision: b34d22838ed54b8f4f941f4eabb6a15ca29192a0 version: null source: Git: https://github.com/pulp-platform/cheshire.git @@ -87,6 +87,7 @@ packages: - common_cells - common_verification - cva6 + - dram_rtl_sim - idma - irq_router - opentitan_peripherals @@ -95,8 +96,8 @@ packages: - serial_link - unbent clic: - revision: 8ed76ffc779a435d0ed034f3068e4c3334fe2ecf - version: 2.0.0 + revision: 6515a71eb4ae3b143ab912d265e79832b3179a76 + version: 3.0.0 source: Git: https://github.com/pulp-platform/clic.git dependencies: @@ -128,8 +129,8 @@ packages: dependencies: - common_cells common_cells: - revision: 9afda9abb565971649c2aa0985639c096f351171 - version: 1.38.0 + revision: ca9d577f2fbc45ec557ab4e0905bbfc154441540 + version: null source: Git: https://github.com/pulp-platform/common_cells.git dependencies: @@ -142,17 +143,24 @@ packages: Git: https://github.com/pulp-platform/common_verification.git dependencies: [] cva6: - revision: 630bd959c9cc69a35d461a2abc205310d2edacf8 + revision: 4c02b24fe7c04690f626776a92274da24f80d1da version: null source: - Git: https://github.com/Scheremo/cva6.git + Git: https://github.com/pulp-platform/cva6.git dependencies: - axi - common_cells - fpnew - tech_cells_generic + dram_rtl_sim: + revision: 2cac4a9e12a60537567276b539ab6c919c87b5dc + version: 0.1.1 + source: + Git: https://github.com/pulp-platform/dram_rtl_sim.git + dependencies: + - axi fpnew: - revision: a8e0cba6dd50f357ece73c2c955d96efc3c6c315 + revision: e5aa6a01b5bbe1675c3aa8872e1203413ded83d1 version: null source: Git: https://github.com/pulp-platform/cvfpu.git @@ -167,8 +175,8 @@ packages: dependencies: - common_cells hyperbus: - revision: 841deb9d821b63bf05a1c85d3a4746352a8bcae2 - version: null + revision: 2a14bd8f9a985b488ee23d240764f52f129f7729 + version: 0.0.9 source: Git: https://github.com/pulp-platform/hyperbus.git dependencies: @@ -198,7 +206,7 @@ packages: - common_cells - register_interface memory_island: - revision: 64828cb7a9ccc1f1656ec92d06129072f445c319 + revision: d072ba0945adad5ccd0af2d4604abe57c1058252 version: null source: Git: https://github.com/pulp-platform/memory_island.git @@ -234,8 +242,8 @@ packages: - register_interface - tech_cells_generic register_interface: - revision: 8e8c209ea559d3b54f45cf30fcce95ce70ff5e49 - version: 0.4.6 + revision: d6e1d4cdaab7870f4faf3f88a1c788eaf5ac129d + version: 0.4.7 source: Git: https://github.com/pulp-platform/register_interface.git dependencies: @@ -252,8 +260,8 @@ packages: - common_cells - tech_cells_generic scm: - revision: 472f99affe44ff7b282b519c047a3cfeb35b16c6 - version: 1.2.0 + revision: 1976c7efb4979271eee2abe262fde0f9a20e2557 + version: 1.2.1 source: Git: https://github.com/pulp-platform/scm.git dependencies: diff --git a/Bender.yml b/Bender.yml index df8d180d..052ec1f9 100644 --- a/Bender.yml +++ b/Bender.yml @@ -9,25 +9,20 @@ package: - "Lorenzo Leone " dependencies: - register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.3 } - axi: { git: https://github.com/colluca/axi, rev: multicast } - cheshire: { git: "https://github.com/pulp-platform/cheshire.git", rev: 1b6ba6294a5925a5dc199b4f98704adb76648ed1} - snitch_cluster: { git: "https://github.com/pulp-platform/snitch_cluster.git", rev: 5b2fccd96c42812774c20ab2f9b811e164809789} - common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.31.1} + register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.7 } + axi: { git: "https://github.com/colluca/axi", rev: bd1abffc0812f8170902e5fb93142c7785c0b8c1 } # + cheshire: { git: "https://github.com/pulp-platform/cheshire.git", rev: wiesep/chimera-main } + snitch_cluster: { git: "https://github.com/pulp-platform/snitch_cluster.git", rev: 5b2fccd96c42812774c20ab2f9b811e164809789 } # main branch from 22.09.25 commit "treewide: Bump AXI after rebase" + common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.39.0 } idma: { git: "https://github.com/pulp-platform/iDMA.git", version: 0.6.5 } - memory_island: { git: "https://github.com/pulp-platform/memory_island.git", rev: 64828cb7a9ccc1f1656ec92d06129072f445c319 } # main branch - apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.4 } - hyperbus: { git: "https://github.com/pulp-platform/hyperbus.git", rev: aottaviano/nonfree } # TMP: to fix hyperbus model issue + memory_island: { git: "https://github.com/pulp-platform/memory_island.git", rev: main } + apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.4 } + hyperbus: { git: "https://github.com/pulp-platform/hyperbus.git", version : 0.0.9 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.12 } export_include_dirs: - hw/include -workspace: - package_links: - cheshire: cheshire - idma: idma - sources: # Level 0 - hw/chimera_pkg.sv diff --git a/Makefile b/Makefile index cf880d4e..58e6801f 100644 --- a/Makefile +++ b/Makefile @@ -35,7 +35,7 @@ SN_CFG = $(SN_ROOT)/cfg/default.json BENDER_YML = $(CHIM_ROOT)/Bender.yml BENDER_LOCK = $(CHIM_ROOT)/Bender.lock -CHS_XLEN ?= 32 +CHS_XLEN ?= 64 CHIM_HW_DIR ?= $(CHIM_ROOT)/hw CHIM_SW_DIR ?= $(CHIM_ROOT)/sw diff --git a/bender.mk b/bender.mk index 2039e684..f0679c09 100644 --- a/bender.mk +++ b/bender.mk @@ -6,6 +6,6 @@ # Lorenzo Leone COMMON_TARGS ?= -COMMON_TARGS += -t snitch_cluster -t cv32a6_convolve -t cva6 -t rtl +COMMON_TARGS += -t snitch_cluster -t cv64a6_imafdchsclic_sv39_wb -t cva6 -t rtl SIM_TARGS = $(COMMON_TARGS) -t test -t sim diff --git a/chimera.mk b/chimera.mk index f5248233..645b6038 100644 --- a/chimera.mk +++ b/chimera.mk @@ -52,7 +52,7 @@ $(CHIM_HW_DIR)/regs/pcr.md: $(CHIM_ROOT)/hw/regs/chimera_regs.hjson .PHONY: snitch_bootrom CHIM_BROM_SRCS = $(wildcard $(CHIM_ROOT)/hw/bootrom/snitch/*.S $(CHIM_ROOT)/hw/bootrom/snitch/*.c) $(CHIM_SW_LIBS) -CHIM_BROM_FLAGS = $(CHS_SW_LDFLAGS) -Os -fno-zero-initialized-in-bss -flto -fwhole-program -march=rv32im +CHIM_BROM_FLAGS = $(CHS_SW_LDFLAGS) -Os -fno-zero-initialized-in-bss -flto -fwhole-program -march=rv32im_zicsr -mabi=ilp32 CHIM_BOOTROM_ALL += $(CHIM_ROOT)/hw/bootrom/snitch/snitch_bootrom.sv $(CHIM_ROOT)/hw/bootrom/snitch/snitch_bootrom.dump diff --git a/hw/bootrom/snitch/snitch_bootrom.bin b/hw/bootrom/snitch/snitch_bootrom.bin index a1166c51..3f70cba5 100755 Binary files a/hw/bootrom/snitch/snitch_bootrom.bin and b/hw/bootrom/snitch/snitch_bootrom.bin differ diff --git a/hw/bootrom/snitch/snitch_bootrom.sv b/hw/bootrom/snitch/snitch_bootrom.sv index 5253b812..8c40fe6b 100644 --- a/hw/bootrom/snitch/snitch_bootrom.sv +++ b/hw/bootrom/snitch/snitch_bootrom.sv @@ -30,7 +30,7 @@ module snitch_bootrom #( data_o = '0; unique case (word) 000: data_o = 32'h30057073 /* 0x0000 */; - 001: data_o = 32'h244000ef /* 0x0004 */; + 001: data_o = 32'h0cc000ef /* 0x0004 */; 002: data_o = 32'h00000297 /* 0x0008 */; 003: data_o = 32'h0a828293 /* 0x000c */; 004: data_o = 32'h30529073 /* 0x0010 */; @@ -61,14 +61,14 @@ module snitch_bootrom #( 029: data_o = 32'h00000e93 /* 0x0074 */; 030: data_o = 32'h00000f13 /* 0x0078 */; 031: data_o = 32'h00000f93 /* 0x007c */; - 032: data_o = 32'h0d4000ef /* 0x0080 */; + 032: data_o = 32'h0d8000ef /* 0x0080 */; 033: data_o = 32'h10500073 /* 0x0084 */; - 034: data_o = 32'h048000ef /* 0x0088 */; + 034: data_o = 32'h148000ef /* 0x0088 */; 035: data_o = 32'h00001297 /* 0x008c */; 036: data_o = 32'hf7428293 /* 0x0090 */; 037: data_o = 32'h0002a283 /* 0x0094 */; 038: data_o = 32'h000280e7 /* 0x0098 */; - 039: data_o = 32'h130000ef /* 0x009c */; + 039: data_o = 32'h040000ef /* 0x009c */; 040: data_o = 32'hf75ff06f /* 0x00a0 */; 041: data_o = 32'h00000013 /* 0x00a4 */; 042: data_o = 32'h00000013 /* 0x00a8 */; @@ -81,102 +81,102 @@ module snitch_bootrom #( 049: data_o = 32'h00000000 /* 0x00c4 */; 050: data_o = 32'h00000000 /* 0x00c8 */; 051: data_o = 32'h00000000 /* 0x00cc */; - 052: data_o = 32'hf14027f3 /* 0x00d0 */; - 053: data_o = 32'h01300713 /* 0x00d4 */; - 054: data_o = 32'h0ff7f793 /* 0x00d8 */; - 055: data_o = 32'h04e78463 /* 0x00dc */; - 056: data_o = 32'h00f76c63 /* 0x00e0 */; - 057: data_o = 32'h00100713 /* 0x00e4 */; - 058: data_o = 32'h02e78263 /* 0x00e8 */; - 059: data_o = 32'h00a00693 /* 0x00ec */; - 060: data_o = 32'h02d78463 /* 0x00f0 */; - 061: data_o = 32'h00008067 /* 0x00f4 */; - 062: data_o = 32'h01c00713 /* 0x00f8 */; - 063: data_o = 32'h02e78c63 /* 0x00fc */; - 064: data_o = 32'h02500713 /* 0x0100 */; - 065: data_o = 32'h04e78063 /* 0x0104 */; - 066: data_o = 32'h00008067 /* 0x0108 */; - 067: data_o = 32'h30001737 /* 0x010c */; - 068: data_o = 32'h04f72e23 /* 0x0110 */; - 069: data_o = 32'h00008067 /* 0x0114 */; - 070: data_o = 32'h300017b7 /* 0x0118 */; - 071: data_o = 32'h06e7a023 /* 0x011c */; - 072: data_o = 32'h00008067 /* 0x0120 */; - 073: data_o = 32'h300017b7 /* 0x0124 */; - 074: data_o = 32'h00100713 /* 0x0128 */; - 075: data_o = 32'h06e7a223 /* 0x012c */; + 052: data_o = 32'h304467f3 /* 0x00d0 */; + 053: data_o = 32'h300467f3 /* 0x00d4 */; + 054: data_o = 32'h00008067 /* 0x00d8 */; + 055: data_o = 32'hf14027f3 /* 0x00dc */; + 056: data_o = 32'h01300713 /* 0x00e0 */; + 057: data_o = 32'h0ff7f793 /* 0x00e4 */; + 058: data_o = 32'h00156513 /* 0x00e8 */; + 059: data_o = 32'h04e78463 /* 0x00ec */; + 060: data_o = 32'h00f76c63 /* 0x00f0 */; + 061: data_o = 32'h00100713 /* 0x00f4 */; + 062: data_o = 32'h02e78263 /* 0x00f8 */; + 063: data_o = 32'h00a00713 /* 0x00fc */; + 064: data_o = 32'h02e78463 /* 0x0100 */; + 065: data_o = 32'h00008067 /* 0x0104 */; + 066: data_o = 32'h01c00713 /* 0x0108 */; + 067: data_o = 32'h02e78a63 /* 0x010c */; + 068: data_o = 32'h02500713 /* 0x0110 */; + 069: data_o = 32'h02e78c63 /* 0x0114 */; + 070: data_o = 32'h00008067 /* 0x0118 */; + 071: data_o = 32'h300017b7 /* 0x011c */; + 072: data_o = 32'h00a7a623 /* 0x0120 */; + 073: data_o = 32'h00008067 /* 0x0124 */; + 074: data_o = 32'h300017b7 /* 0x0128 */; + 075: data_o = 32'h00a7a823 /* 0x012c */; 076: data_o = 32'h00008067 /* 0x0130 */; 077: data_o = 32'h300017b7 /* 0x0134 */; - 078: data_o = 32'h00100713 /* 0x0138 */; - 079: data_o = 32'h06e7a423 /* 0x013c */; - 080: data_o = 32'h00008067 /* 0x0140 */; - 081: data_o = 32'h300017b7 /* 0x0144 */; - 082: data_o = 32'h00100713 /* 0x0148 */; - 083: data_o = 32'h06e7a623 /* 0x014c */; - 084: data_o = 32'h00008067 /* 0x0150 */; - 085: data_o = 32'hf14027f3 /* 0x0154 */; - 086: data_o = 32'h01300713 /* 0x0158 */; - 087: data_o = 32'h0ff7f793 /* 0x015c */; - 088: data_o = 32'h04e78463 /* 0x0160 */; - 089: data_o = 32'h00f76c63 /* 0x0164 */; - 090: data_o = 32'h00100713 /* 0x0168 */; - 091: data_o = 32'h02e78263 /* 0x016c */; - 092: data_o = 32'h00a00713 /* 0x0170 */; - 093: data_o = 32'h02e78463 /* 0x0174 */; - 094: data_o = 32'h00008067 /* 0x0178 */; - 095: data_o = 32'h01c00713 /* 0x017c */; - 096: data_o = 32'h02e78a63 /* 0x0180 */; - 097: data_o = 32'h02500713 /* 0x0184 */; - 098: data_o = 32'h02e78c63 /* 0x0188 */; - 099: data_o = 32'h00008067 /* 0x018c */; - 100: data_o = 32'h300017b7 /* 0x0190 */; - 101: data_o = 32'h0407ae23 /* 0x0194 */; - 102: data_o = 32'h00008067 /* 0x0198 */; - 103: data_o = 32'h300017b7 /* 0x019c */; - 104: data_o = 32'h0607a023 /* 0x01a0 */; - 105: data_o = 32'h00008067 /* 0x01a4 */; - 106: data_o = 32'h300017b7 /* 0x01a8 */; - 107: data_o = 32'h0607a223 /* 0x01ac */; - 108: data_o = 32'h00008067 /* 0x01b0 */; - 109: data_o = 32'h300017b7 /* 0x01b4 */; - 110: data_o = 32'h0607a423 /* 0x01b8 */; - 111: data_o = 32'h00008067 /* 0x01bc */; - 112: data_o = 32'h300017b7 /* 0x01c0 */; - 113: data_o = 32'h0607a623 /* 0x01c4 */; - 114: data_o = 32'h00008067 /* 0x01c8 */; - 115: data_o = 32'hf14027f3 /* 0x01cc */; - 116: data_o = 32'h01300713 /* 0x01d0 */; - 117: data_o = 32'h0ff7f793 /* 0x01d4 */; - 118: data_o = 32'h00156513 /* 0x01d8 */; + 078: data_o = 32'h00a7aa23 /* 0x0138 */; + 079: data_o = 32'h00008067 /* 0x013c */; + 080: data_o = 32'h300017b7 /* 0x0140 */; + 081: data_o = 32'h00a7ac23 /* 0x0144 */; + 082: data_o = 32'h00008067 /* 0x0148 */; + 083: data_o = 32'h300017b7 /* 0x014c */; + 084: data_o = 32'h00a7ae23 /* 0x0150 */; + 085: data_o = 32'h00008067 /* 0x0154 */; + 086: data_o = 32'hf14027f3 /* 0x0158 */; + 087: data_o = 32'h01300713 /* 0x015c */; + 088: data_o = 32'h0ff7f793 /* 0x0160 */; + 089: data_o = 32'h04e78463 /* 0x0164 */; + 090: data_o = 32'h00f76c63 /* 0x0168 */; + 091: data_o = 32'h00100713 /* 0x016c */; + 092: data_o = 32'h02e78263 /* 0x0170 */; + 093: data_o = 32'h00a00713 /* 0x0174 */; + 094: data_o = 32'h02e78463 /* 0x0178 */; + 095: data_o = 32'h00008067 /* 0x017c */; + 096: data_o = 32'h01c00713 /* 0x0180 */; + 097: data_o = 32'h02e78a63 /* 0x0184 */; + 098: data_o = 32'h02500713 /* 0x0188 */; + 099: data_o = 32'h02e78c63 /* 0x018c */; + 100: data_o = 32'h00008067 /* 0x0190 */; + 101: data_o = 32'h300017b7 /* 0x0194 */; + 102: data_o = 32'h0407ae23 /* 0x0198 */; + 103: data_o = 32'h00008067 /* 0x019c */; + 104: data_o = 32'h300017b7 /* 0x01a0 */; + 105: data_o = 32'h0607a023 /* 0x01a4 */; + 106: data_o = 32'h00008067 /* 0x01a8 */; + 107: data_o = 32'h300017b7 /* 0x01ac */; + 108: data_o = 32'h0607a223 /* 0x01b0 */; + 109: data_o = 32'h00008067 /* 0x01b4 */; + 110: data_o = 32'h300017b7 /* 0x01b8 */; + 111: data_o = 32'h0607a423 /* 0x01bc */; + 112: data_o = 32'h00008067 /* 0x01c0 */; + 113: data_o = 32'h300017b7 /* 0x01c4 */; + 114: data_o = 32'h0607a623 /* 0x01c8 */; + 115: data_o = 32'h00008067 /* 0x01cc */; + 116: data_o = 32'hf14027f3 /* 0x01d0 */; + 117: data_o = 32'h01300713 /* 0x01d4 */; + 118: data_o = 32'h0ff7f793 /* 0x01d8 */; 119: data_o = 32'h04e78463 /* 0x01dc */; 120: data_o = 32'h00f76c63 /* 0x01e0 */; 121: data_o = 32'h00100713 /* 0x01e4 */; 122: data_o = 32'h02e78263 /* 0x01e8 */; - 123: data_o = 32'h00a00713 /* 0x01ec */; - 124: data_o = 32'h02e78463 /* 0x01f0 */; + 123: data_o = 32'h00a00693 /* 0x01ec */; + 124: data_o = 32'h02d78463 /* 0x01f0 */; 125: data_o = 32'h00008067 /* 0x01f4 */; 126: data_o = 32'h01c00713 /* 0x01f8 */; - 127: data_o = 32'h02e78a63 /* 0x01fc */; + 127: data_o = 32'h02e78c63 /* 0x01fc */; 128: data_o = 32'h02500713 /* 0x0200 */; - 129: data_o = 32'h02e78c63 /* 0x0204 */; + 129: data_o = 32'h04e78063 /* 0x0204 */; 130: data_o = 32'h00008067 /* 0x0208 */; - 131: data_o = 32'h300017b7 /* 0x020c */; - 132: data_o = 32'h00a7a623 /* 0x0210 */; + 131: data_o = 32'h30001737 /* 0x020c */; + 132: data_o = 32'h04f72e23 /* 0x0210 */; 133: data_o = 32'h00008067 /* 0x0214 */; 134: data_o = 32'h300017b7 /* 0x0218 */; - 135: data_o = 32'h00a7a823 /* 0x021c */; + 135: data_o = 32'h06e7a023 /* 0x021c */; 136: data_o = 32'h00008067 /* 0x0220 */; 137: data_o = 32'h300017b7 /* 0x0224 */; - 138: data_o = 32'h00a7aa23 /* 0x0228 */; - 139: data_o = 32'h00008067 /* 0x022c */; - 140: data_o = 32'h300017b7 /* 0x0230 */; - 141: data_o = 32'h00a7ac23 /* 0x0234 */; - 142: data_o = 32'h00008067 /* 0x0238 */; - 143: data_o = 32'h300017b7 /* 0x023c */; - 144: data_o = 32'h00a7ae23 /* 0x0240 */; - 145: data_o = 32'h00008067 /* 0x0244 */; - 146: data_o = 32'h304467f3 /* 0x0248 */; - 147: data_o = 32'h300467f3 /* 0x024c */; + 138: data_o = 32'h00100713 /* 0x0228 */; + 139: data_o = 32'h06e7a223 /* 0x022c */; + 140: data_o = 32'h00008067 /* 0x0230 */; + 141: data_o = 32'h300017b7 /* 0x0234 */; + 142: data_o = 32'h00100713 /* 0x0238 */; + 143: data_o = 32'h06e7a423 /* 0x023c */; + 144: data_o = 32'h00008067 /* 0x0240 */; + 145: data_o = 32'h300017b7 /* 0x0244 */; + 146: data_o = 32'h00100713 /* 0x0248 */; + 147: data_o = 32'h06e7a623 /* 0x024c */; 148: data_o = 32'h00008067 /* 0x0250 */; 149: data_o = 32'h00000000 /* 0x0254 */; 150: data_o = 32'h00000000 /* 0x0258 */; diff --git a/hw/chimera_pkg.sv b/hw/chimera_pkg.sv index 96aaca0b..8eb88ee4 100644 --- a/hw/chimera_pkg.sv +++ b/hw/chimera_pkg.sv @@ -141,15 +141,18 @@ ExtClusters localparam shrt_bt MemIslWordsPerBank = 1024; // WIESEP: Memory Island size = 16 * 2 * 4096 * 32 bit = 512 KB - // Hyperbus - localparam byte_bt HyperbusIdx = MemIslandIdx + 1; - // WIESEP: Address space 256 MiB - localparam doub_bt HyperbusRegionLength = 64'h1000_0000; + + localparam doub_bt HyperbusRegionLength = 64'h1_0000_0000; localparam doub_bt HyperbusRegionStart = 64'h8000_0000; localparam doub_bt HyperbusRegionEnd = HyperbusRegionStart + HyperbusRegionLength; localparam int unsigned HypNumPhys = 1; localparam int unsigned HypNumChips = 2; + // Per-chip HyperRAM device address space (128 MiB for the IS66WVH8M8ALL). Single + // source of truth for the hyperbus RstChipSpace parameter (see chimera_top_wrapper). + localparam doub_bt HyperRamChipSize = 64'h800_0000; + // Reset address space the hyperbus controller decodes: all PHYs x all chips. + localparam doub_bt HyperbusRstChipSpace = HypNumPhys * HypNumChips * HyperRamChipSize; localparam int unsigned LogDepth = 3; localparam int unsigned SyncStages = 3; @@ -166,34 +169,41 @@ ExtClusters chimera_cfg_t chimera_cfg; cheshire_cfg_t cfg = DefaultCfg; - // Global CFG - // Set all Chimera addresses as uncached - cfg.Cva6ExtCieLength = 'h0; - cfg.Cva6ExtCieOnTop = 1; + // Configure Cached, In, Execute Regions + cfg.Cva6ExtCieBase = MemIslRegionStart; + cfg.Cva6ExtCieLength = MemIslRegionLength; + // Global CFG cfg.Vga = 0; cfg.SerialLink = 0; - // SCHEREMO: Fully remove LLC - cfg.LlcNotBypass = 0; - cfg.LlcOutConnect = 0; + cfg.Clic = 1; + cfg.Usb = 0; + // LLC Config + // 64 KiB (8 way-set associative, 128 lines, 64B line size) + cfg.LlcNotBypass = 1; + cfg.LlcOutConnect = 1; + cfg.LlcSetAssoc = 8; + cfg.LlcNumLines = 128; + cfg.LlcNumBlocks = 8; + cfg.LlcOutRegionStart = HyperbusRegionStart; + cfg.LlcOutRegionEnd = HyperbusRegionEnd; // AXI CFG cfg.AxiMstIdWidth = 2; - cfg.AxiDataWidth = 32; + cfg.AxiDataWidth = 64; cfg.AddrWidth = 48; - cfg.LlcOutRegionEnd = 'hFFFF_FFFF; cfg.AxiExtNumWideMst = $countones(ChimeraClusterCfg.hasWideMasterPort); // SCHEREMO: Two ports for each cluster: one to convert stray wides, one for the original narrow cfg.AxiExtNumMst = ExtClusters + $countones(ChimeraClusterCfg.hasWideMasterPort); - cfg.AxiExtNumSlv = ExtClusters + MemoryIsland + Hyperbus; - cfg.AxiExtNumRules = ExtClusters + MemoryIsland + Hyperbus; + cfg.AxiExtNumSlv = ExtClusters + MemoryIsland; + cfg.AxiExtNumRules = ExtClusters + MemoryIsland; - cfg.AxiExtRegionIdx = {HyperbusIdx, MemIslandIdx, ClusterIdx}; - cfg.AxiExtRegionStart = {HyperbusRegionStart, MemIslRegionStart, ClusterRegionStart}; - cfg.AxiExtRegionEnd = {HyperbusRegionEnd, MemIslRegionEnd, ClusterRegionEnd}; + cfg.AxiExtRegionIdx = {MemIslandIdx, ClusterIdx}; + cfg.AxiExtRegionStart = {MemIslRegionStart, ClusterRegionStart}; + cfg.AxiExtRegionEnd = {MemIslRegionEnd, ClusterRegionEnd}; // REG CFG cfg.RegExtNumSlv = ExtRegNum; diff --git a/hw/chimera_top_wrapper.sv b/hw/chimera_top_wrapper.sv index 467f273d..dc13e81d 100644 --- a/hw/chimera_top_wrapper.sv +++ b/hw/chimera_top_wrapper.sv @@ -99,6 +99,8 @@ module chimera_top_wrapper // External AXI crossbar ports axi_mst_req_t [iomsb(ChsCfg.AxiExtNumMst):0] axi_mst_req; axi_mst_rsp_t [iomsb(ChsCfg.AxiExtNumMst):0] axi_mst_rsp; + axi_llc_req_t axi_llc_req; + axi_llc_rsp_t axi_llc_rsp; axi_wide_mst_req_t [iomsb(ChsCfg.AxiExtNumWideMst):0] axi_wide_mst_req; axi_wide_mst_rsp_t [iomsb(ChsCfg.AxiExtNumWideMst):0] axi_wide_mst_rsp; axi_slv_req_t [iomsb(ChsCfg.AxiExtNumSlv):0] axi_slv_req; @@ -133,8 +135,8 @@ module chimera_top_wrapper cheshire_soc #( .Cfg (ChsCfg), .ExtHartinfo ('0), - .axi_ext_llc_req_t(axi_mst_req_t), - .axi_ext_llc_rsp_t(axi_mst_rsp_t), + .axi_ext_llc_req_t(axi_llc_req_t), + .axi_ext_llc_rsp_t(axi_llc_rsp_t), .axi_ext_mst_req_t(axi_mst_req_t), .axi_ext_mst_rsp_t(axi_mst_rsp_t), .axi_ext_slv_req_t(axi_slv_req_t), @@ -148,8 +150,8 @@ module chimera_top_wrapper .boot_mode_i, .rtc_i, // External AXI LLC (DRAM) port - .axi_llc_mst_req_o(), - .axi_llc_mst_rsp_i('0), + .axi_llc_mst_req_o(axi_llc_req), + .axi_llc_mst_rsp_i(axi_llc_rsp), // External AXI crossbar ports .axi_ext_mst_req_i(axi_mst_req), .axi_ext_mst_rsp_o(axi_mst_rsp), @@ -412,9 +414,9 @@ module chimera_top_wrapper .axi_wide_rsp_o (axi_wide_mst_rsp) ); - localparam int unsigned AxiSlvIdWidth = ChsCfg.AxiMstIdWidth + $clog2(AxiIn.num_in); // Slave CDC parameters + localparam int unsigned AxiSlvIdWidth = ChsCfg.AxiMstIdWidth + $clog2(AxiIn.num_in); localparam int unsigned ChimeraAxiSlvAwWidth = (2 ** LogDepth) * axi_pkg::aw_width( ChsCfg.AddrWidth, AxiSlvIdWidth, ChsCfg.AxiUserWidth ); @@ -448,38 +450,49 @@ module chimera_top_wrapper ChsCfg.AxiDataWidth, ChsCfg.AxiMstIdWidth, ChsCfg.AxiUserWidth ); - logic [ChimeraAxiSlvArWidth-1:0] hyper_ar_data; + // LLC CDC async-bus widths. The channel/ID widths are single-sourced from the + // `axi_llc_*` types emitted by `CHESHIRE_TYPEDEF_ALL` above (instead of + // recomputing them with axi_pkg::*_width). The `(2**LogDepth)` factor is the + // depth of the axi_cdc gray-coded FIFO exposed on the async data buses. + localparam int unsigned ChimeraAxiLlcIdWidth = $bits(axi_llc_id_t); + localparam int unsigned ChimeraAxiLlcArWidth = (2 ** LogDepth) * $bits(axi_llc_ar_chan_t); + localparam int unsigned ChimeraAxiLlcAwWidth = (2 ** LogDepth) * $bits(axi_llc_aw_chan_t); + localparam int unsigned ChimeraAxiLlcBWidth = (2 ** LogDepth) * $bits(axi_llc_b_chan_t); + localparam int unsigned ChimeraAxiLlcRWidth = (2 ** LogDepth) * $bits(axi_llc_r_chan_t); + localparam int unsigned ChimeraAxiLlcWWidth = (2 ** LogDepth) * $bits(axi_llc_w_chan_t); + + logic [ChimeraAxiLlcArWidth-1:0] hyper_ar_data; logic [ LogDepth:0] hyper_ar_wptr; logic [ LogDepth:0] hyper_ar_rptr; - logic [ChimeraAxiSlvAwWidth-1:0] hyper_aw_data; + logic [ChimeraAxiLlcAwWidth-1:0] hyper_aw_data; logic [ LogDepth:0] hyper_aw_wptr; logic [ LogDepth:0] hyper_aw_rptr; - logic [ ChimeraAxiSlvBWidth-1:0] hyper_b_data; + logic [ ChimeraAxiLlcBWidth-1:0] hyper_b_data; logic [ LogDepth:0] hyper_b_wptr; logic [ LogDepth:0] hyper_b_rptr; - logic [ ChimeraAxiSlvRWidth-1:0] hyper_r_data; + logic [ ChimeraAxiLlcRWidth-1:0] hyper_r_data; logic [ LogDepth:0] hyper_r_wptr; logic [ LogDepth:0] hyper_r_rptr; - logic [ ChimeraAxiSlvWWidth-1:0] hyper_w_data; + logic [ ChimeraAxiLlcWWidth-1:0] hyper_w_data; logic [ LogDepth:0] hyper_w_wptr; logic [ LogDepth:0] hyper_w_rptr; axi_cdc_src #( .LogDepth (LogDepth), .SyncStages(SyncStages), - .aw_chan_t (axi_slv_aw_chan_t), - .w_chan_t (axi_slv_w_chan_t), - .b_chan_t (axi_slv_b_chan_t), - .ar_chan_t (axi_slv_ar_chan_t), - .r_chan_t (axi_slv_r_chan_t), - .axi_req_t (axi_slv_req_t), - .axi_resp_t(axi_slv_rsp_t) + .aw_chan_t (axi_llc_aw_chan_t), + .w_chan_t (axi_llc_w_chan_t), + .b_chan_t (axi_llc_b_chan_t), + .ar_chan_t (axi_llc_ar_chan_t), + .r_chan_t (axi_llc_r_chan_t), + .axi_req_t (axi_llc_req_t), + .axi_resp_t(axi_llc_rsp_t) ) hyperbus_slv_cdc_src ( // synchronous slave port .src_clk_i (soc_clk_i), .src_rst_ni (rst_ni), - .src_req_i (axi_slv_req[HyperbusIdx]), - .src_resp_o (axi_slv_rsp[HyperbusIdx]), + .src_req_i (axi_llc_req), + .src_resp_o (axi_llc_rsp), // asynchronous master port .async_data_master_aw_data_o(hyper_aw_data), .async_data_master_aw_wptr_o(hyper_aw_wptr), @@ -504,30 +517,30 @@ module chimera_top_wrapper .IsClockODelayed (1'b0), .AxiAddrWidth (ChsCfg.AddrWidth), .AxiDataWidth (ChsCfg.AxiDataWidth), - .AxiIdWidth (AxiSlvIdWidth), + .AxiIdWidth (ChimeraAxiLlcIdWidth), .AxiUserWidth (ChsCfg.AxiUserWidth), - .axi_req_t (axi_slv_req_t), - .axi_rsp_t (axi_slv_rsp_t), - .axi_w_chan_t (axi_slv_w_chan_t), - .axi_b_chan_t (axi_slv_b_chan_t), - .axi_ar_chan_t (axi_slv_ar_chan_t), - .axi_r_chan_t (axi_slv_r_chan_t), - .axi_aw_chan_t (axi_slv_aw_chan_t), + .axi_req_t (axi_llc_req_t), + .axi_rsp_t (axi_llc_rsp_t), + .axi_w_chan_t (axi_llc_w_chan_t), + .axi_b_chan_t (axi_llc_b_chan_t), + .axi_ar_chan_t (axi_llc_ar_chan_t), + .axi_r_chan_t (axi_llc_r_chan_t), + .axi_aw_chan_t (axi_llc_aw_chan_t), .RegAddrWidth (ChsCfg.AddrWidth), - .RegDataWidth (ChsCfg.AxiDataWidth), + .RegDataWidth (RegDataWidth), .reg_req_t (reg_req_t), .reg_rsp_t (reg_rsp_t), .RxFifoLogDepth (32'd2), .TxFifoLogDepth (32'd2), - .RstChipBase (ChsCfg.LlcOutRegionStart), - .RstChipSpace (HyperbusRegionEnd - HyperbusRegionStart), + .RstChipBase (HyperbusRegionStart), + .RstChipSpace (HyperbusRstChipSpace), .PhyStartupCycles(300 * 200), .AxiLogDepth (LogDepth), - .AxiSlaveArWidth (ChimeraAxiSlvArWidth), - .AxiSlaveAwWidth (ChimeraAxiSlvAwWidth), - .AxiSlaveBWidth (ChimeraAxiSlvBWidth), - .AxiSlaveRWidth (ChimeraAxiSlvRWidth), - .AxiSlaveWWidth (ChimeraAxiSlvWWidth), + .AxiSlaveArWidth (ChimeraAxiLlcArWidth), + .AxiSlaveAwWidth (ChimeraAxiLlcAwWidth), + .AxiSlaveBWidth (ChimeraAxiLlcBWidth), + .AxiSlaveRWidth (ChimeraAxiLlcRWidth), + .AxiSlaveWWidth (ChimeraAxiLlcWWidth), .AxiMaxTrans (ChsCfg.AxiMaxSlvTrans), .CdcSyncStages (SyncStages) ) i_hyperbus_wrap ( diff --git a/iis-env.sh b/iis-env.sh index beb92989..7e9d22a8 100755 --- a/iis-env.sh +++ b/iis-env.sh @@ -9,7 +9,8 @@ export VOPT="questa-2022.3 vopt" export VLIB="questa-2022.3 vlib" export BASE_PYTHON=/usr/local/anaconda3/bin/python3.11 export CHS_SW_32_GCC_BINROOT=/usr/pack/riscv-1.0-kgf/pulp-gcc-2.5.0/bin -export RISCV_GCC_BINROOT=/usr/pack/riscv-1.0-kgf/pulp-gcc-2.5.0/bin +export CHS_SW_64_GCC_BINROOT=/usr/pack/riscv-1.0-kgf/riscv64-gcc-12.2.0/bin +export CHS_SW_GCC_BINROOT=/usr/pack/riscv-1.0-kgf/riscv64-gcc-12.2.0/bin export CC=/usr/pack/gcc-11.2.0-af/linux-x64/bin/gcc export CXX=/usr/pack/gcc-11.2.0-af/linux-x64/bin/g++ export CMAKE=cmake-3.28.3 diff --git a/iis_compile.sh b/iis_compile.sh new file mode 100755 index 00000000..e69de29b diff --git a/sw/sw.mk b/sw/sw.mk index e297f777..5a69eac1 100644 --- a/sw/sw.mk +++ b/sw/sw.mk @@ -14,8 +14,8 @@ CHS_SW_INCLUDES += -I$(CHIM_SW_DIR)/include # SCHEREMO: use im for platform-level SW, as the smallest common denominator between CVA6 and the Snitch cluster. # CVA6's bootrom however needs imc, so override that for this specific case. -CHS_SW_FLAGS += -falign-functions=64 -march=rv32im -CHS_BROM_FLAGS += -march=rv32imc +CHS_SW_FLAGS += -falign-functions=64 -march=rv64gc_zifencei -mabi=lp64d +CHS_BROM_FLAGS += -march=rv64gc_zifencei -mabi=lp64d CHS_SW_LDFLAGS += -L$(CHIM_SW_DIR)/lib diff --git a/sw/tests/testHyperbusAddr.c b/sw/tests/testHyperbusAddr.c index d1bef52b..33899cf3 100644 --- a/sw/tests/testHyperbusAddr.c +++ b/sw/tests/testHyperbusAddr.c @@ -14,16 +14,20 @@ #define TESTVAL (uint32_t)0x1234ABCD int main() { - volatile uint8_t *regPtr = (volatile uint8_t *)SOC_CTRL_BASE; - setAllClusterReset(regPtr, 0); - setAllClusterClockGating(regPtr, 0); + // This test does not use any cluster, so it neither resets nor ungates them. + volatile uint32_t *hyperCtrlPtr = (volatile uint32_t *)HYPERBUS_CFG_BASE; volatile uint32_t *hyperMemPtr = (volatile uint32_t *)HYPER_BASE; volatile uint32_t result; + // Write T_TX_CLK values + hyperCtrlPtr[5] = 4; + // write *(hyperMemPtr) = TESTVAL; + asm volatile("fence" ::: "memory"); // read result = *(hyperMemPtr); + asm volatile("fence" ::: "memory"); // verify if (result == TESTVAL) { diff --git a/target/sim/sim.mk b/target/sim/sim.mk index efd3e739..337d3f26 100644 --- a/target/sim/sim.mk +++ b/target/sim/sim.mk @@ -28,7 +28,7 @@ CHIM_VLOG_ARGS += +define+PATH_TO_HYP_SDF=\"$(CHIM_HYPERBUS_SDF_PATH)\" VSIM_FLAGS_GUI = -voptargs=+acc -override VSIM_FLAGS += -work $(VSIM_WORK) +override VSIM_FLAGS += -work $(VSIM_WORK) -suppress 8386 # Set testbech parameters define add_vsim_flag diff --git a/target/sim/src/tb_chimera_soc.sv b/target/sim/src/tb_chimera_soc.sv index 3ca6d760..64cb3363 100644 --- a/target/sim/src/tb_chimera_soc.sv +++ b/target/sim/src/tb_chimera_soc.sv @@ -41,7 +41,7 @@ module tb_chimera_soc force fix.dut.i_memisland_domain.i_memory_island.i_memory_island.narrow_req_i[1] = 1'b1; force fix.dut.i_memisland_domain.i_memory_island.i_memory_island.narrow_we_i[1] = 1'b1; force fix.dut.i_memisland_domain.i_memory_island.i_memory_island.narrow_wdata_i[1] = write_data; - force fix.dut.i_memisland_domain.i_memory_island.i_memory_island.narrow_strb_i[1] = 4'hf; + force fix.dut.i_memisland_domain.i_memory_island.i_memory_island.narrow_strb_i[1] = 8'hff; force fix.dut.i_memisland_domain.i_memory_island.i_memory_island.narrow_gnt_o[1] = 1'b0; force fix.dut.i_memisland_domain.i_memory_island.i_memory_island.narrow_rvalid_o[1] = 1'b0; endtask @@ -58,18 +58,19 @@ module tb_chimera_soc $display("[FAST PRELOAD] Preloading section at 0x%h (%0d bytes)", sec_addr, sec_len); if (read_section(sec_addr, bf, sec_len)) $fatal(1, "[FAST PRELOAD] Failed to read ELF section!"); - @(posedge fix.vip.soc_clk); // + @(posedge fix.vip.soc_clk); // for (longint i = 0; i <= sec_len; i += riscv::XLEN / 8) begin bit checkpoint = (i != 0 && i % 512 == 0); - if (checkpoint) + //if (checkpoint) $display( - "[FAST PRELOAD] - %0d/%0d bytes (%0d%%)", + "%0t ns [FAST PRELOAD] - %0d/%0d bytes (%0d%%)", + $time, i, sec_len, i * 100 / (sec_len > 1 ? sec_len - 1 : 1) ); @(posedge fix.vip.soc_clk); - force_write((sec_addr + i), {bf[i+3], bf[i+2], bf[i+1], bf[i]}); + force_write((sec_addr + i), {bf[i+7], bf[i+6], bf[i+5], bf[i+4], bf[i+3], bf[i+2], bf[i+1], bf[i]}); end end @(posedge fix.vip.soc_clk); @@ -112,7 +113,7 @@ module tb_chimera_soc fix.vip.uart_debug_elf_run_and_wait(preload_elf, exit_code); end 3: begin // FAST DEBUG - // Initialize JTAG + // Initialize JTAG fix.vip.jtag_init(); // Halt the core fix.vip.jtag_halt_hart(); diff --git a/target/sim/vsim/wave/waves.tcl b/target/sim/vsim/wave/waves.tcl index 26c13ef5..d8a00088 100644 --- a/target/sim/vsim/wave/waves.tcl +++ b/target/sim/vsim/wave/waves.tcl @@ -49,6 +49,10 @@ add wave -noupdate -expand -group {Global} {/tb_chimera_soc/fix/dut/uart_rx_i} add wave -noupdate -expand -group {CVA6} {/tb_chimera_soc/fix/dut/i_cheshire/gen_cva6_cores[0]/i_core_cva6/hart_id_i} add wave -noupdate -expand -group {CVA6} {/tb_chimera_soc/fix/dut/i_cheshire/gen_cva6_cores[0]/i_core_cva6/pc_commit} +add wave -noupdate -expand -group {CVA6} {/tb_chimera_soc/fix/dut/i_cheshire/intr_routed} +add wave -noupdate -expand -group {CVA6} {/tb_chimera_soc/fix/dut/i_cheshire/intr} +add wave -noupdate -expand -group {CVA6} {/tb_chimera_soc/fix/dut/i_cheshire/msip} +add wave -noupdate -expand -group {CVA6} {/tb_chimera_soc/fix/dut/i_cheshire/mtip} add wave -noupdate -expand -group {Cluster Register} {tb_chimera_soc/fix/dut/i_reg_top/reg2hw}