SEGFAULT when running verilator with traces

[GeertenV]

"app=hello_world make simv trace=1" gives me a SEGFAULT when I used "make verilate trace=1".
"app=hello_world make simv" work fine when I used "make verilate".
Is this fixable or would you recommend switching to QuestaSim?

ps:
I had to take a few extra steps that were not in the readme.md just to get the non-traced Verilator to run:

1. Had to change Qemu repo's:
   url = https://git.qemu.org/git/u-boot.git changed to url = https://gitlab.com/qemu-project-mirrors/u-boot.git
   url = https://git.qemu.org/git/u-boot-sam460ex.git changed to url = https://gitlab.com/qemu-project-mirrors/u-boot-sam460ex.git
2. add option to makefile as mentioned in: Error with make toolchain-llvm #410
3. delete the if (defined($ENV{VERILATOR_ROOT})) clause in installed verilator file
4. "make toolchain-gcc". I did not expect this as the project switched to LLVM

[rayxxxxxl]

I am having the same issue. Any solutions?

[GeertenV]

I am having the same issue. Any solutions?

I ended up switching to using our licenced QuestaSim server :(
Something in the Ara codebase has been changed that seems to have broken Verilator compatibility.

[rayxxxxxl]

Root Cause Found: Verilator 5.012 addModel() Bug in Hierarchical Verilation + Trace Mode

Problem

Running with trace=1 causes a SEGFAULT, while non-trace simulation works fine:
app=hello_world trace=1 make simv → SEGFAULT
app=hello_world make simv → Works fine

GDB Backtrace

#0 VerilatedTrace<VerilatedFst, VerilatedFstBuffer>::addModel(VerilatedModel*) ← crash here
#1 Vlane_9::trace(VerilatedFstC*, int, int)
#2 VerilatorSimCtrl::Run()
#3 VerilatorSimCtrl::RunSimulation()
#4 main()

Analysis

The crash occurs during trace initialization, when the hierarchically-compiled sub-module Vlane_9 tries to register its signals with the top-level FST trace object via addModel(). This function accesses an invalid memory pointer inside the Verilator 5.012 runtime library.

• Without trace: sub-modules only participate in simulation via eval() — addModel() is never called → no crash.
• With trace: each sub-module must register itself with the trace recorder via addModel() → triggers the bug.
  --trace-depth does not help because the crash happens at the model registration stage, before any signal-level depth filtering takes place.

Solution

Upgrade the project's bundled Verilator from v5.012 to v5.024:

rm -rf install/verilator
VERIL_VERSION=v5.024 make verilator
cd hardware
rm -rf build/verilator*
trace=1 make verilate
app=hello_world trace=1 make simv

Result after upgrading:
Tracing enabled.
Writing simulation traces to sim.fst
Ariane says Hello!
Core Test *** SUCCESS ***
Simulation speed: 2883.23 cycles/s

Suggestion

Consider updating VERIL_VERSION in the project's root Makefile from v5.012 to v5.024, as the default version has a known bug that causes trace-mode SEGFAULT in hierarchical verilation. Anyone cloning this repo and building with the default configuration will encounter this issue.