From 52f483e5db6aa7f734518c6b8e74df01f32f1282 Mon Sep 17 00:00:00 2001
From: Hong Pang <hopang@larain5.ee.ethz.ch>
Date: Fri, 3 Oct 2025 18:59:06 +0200
Subject: [PATCH 01/37] [HW] 1. Support reduction operation for integer; 2. Fix
 single-burst misaligned read issue; 3 Fix vl calculation problem for each
 cluster. 4. Support running kernel with vector length smaller than
 NrLane*NrCluster

---
 apps/common/default_args.mk            |     8 +-
 apps/dotproduct/data.S                 | 34504 ++++++++++++++++++++---
 apps/dotproduct/main.c                 |   153 +-
 apps/dotproduct/script/gen_data.py     |     2 +
 apps/fdotproduct/main.c                |    88 +-
 apps/fdotproduct/script/gen_data.py    |     2 +
 apps/fmatmul/main.c                    |     2 +
 apps/fmatmul/script/gen_data.py        |     1 +
 hardware/include/ara_pkg.sv            |     6 +
 hardware/src/ara.sv                    |     5 +-
 hardware/src/ara_cluster.sv            |     6 +-
 hardware/src/ara_dispatcher.sv         |    48 +-
 hardware/src/ara_macro.sv              |     2 +
 hardware/src/lane/lane_sequencer.sv    |    27 +
 hardware/src/lane/operand_queue.sv     |    21 +-
 hardware/src/lane/operand_requester.sv |     6 +-
 hardware/src/lane/valu.sv              |    25 +-
 hardware/src/lane/vector_fus_stage.sv  |     2 +
 hardware/src/sldu/sldu.sv              |     3 +
 hardware/src/vlsu/align_stage.sv       |     5 +
 hardware/src/vlsu/global_dispatcher.sv |    13 +-
 hardware/src/vlsu/global_ldst.sv       |     1 +
 hardware/src/vlsu/shuffle_stage.sv     |     1 +
 23 files changed, 30970 insertions(+), 3961 deletions(-)

diff --git a/apps/common/default_args.mk b/apps/common/default_args.mk
index 6aa0edd..07205cf 100644
--- a/apps/common/default_args.mk
+++ b/apps/common/default_args.mk
@@ -1,16 +1,16 @@
 # Default app parameters
 
 # Matrix sizes
-def_args_imatmul     ?= "128 128 128"
-def_args_fmatmul     ?= "128 128 128"
+def_args_imatmul     ?= "64 64 64"
+def_args_fmatmul     ?= "64 64 64"
 # Matrix size, filter size
 def_args_iconv2d     ?= "112 7"
 def_args_fconv2d     ?= "112 7"
 def_args_fconv3d     ?= "112 7"
 # Vector size
-def_args_fdotproduct ?= "512"
+def_args_fdotproduct ?= "8192"
 # Vector size
-def_args_dotproduct  ?= "512"
+def_args_dotproduct  ?= "8192"
 # Matrix padded size 0, matrix padded size 1, onlyvec
 def_args_jacobi2d    ?= "130 130"
 # Vector size
diff --git a/apps/dotproduct/data.S b/apps/dotproduct/data.S
index becdaec..be9fb29 100644
--- a/apps/dotproduct/data.S
+++ b/apps/dotproduct/data.S
@@ -2,3872 +2,30752 @@
 .global vsize
 .balign 8
 vsize:
-    .word 0x00000200
+    .word 0x00001000
     .word 0x00000000
 .global v64a
 .balign NR_LANES*4
 v64a:
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-    .word 0x00015ae9
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 .balign NR_LANES*4
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 .balign NR_LANES*4
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 .balign NR_LANES*4
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 .balign NR_LANES*4
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     .word 0x00fdfdfc
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-    .word 0xfffc0202
-    .word 0xfdfdfc02
-    .word 0x01feff00
-    .word 0x00020000
-    .word 0xfe0201fd
+    .word 0xfdfcfeff
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+    .word 0xfe0200ff
+    .word 0x02fdfffd
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+    .word 0xfdfd01ff
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+    .word 0x00010001
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+    .word 0x00fdfdfe
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     .word 0x0001ff02
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-    .word 0xfd01fc02
-    .word 0xfffc01fe
-    .word 0x02fd0102
-    .word 0x02fd0201
-    .word 0xfefcfc02
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-    .word 0xfdff0001
-    .word 0x00fe0002
-    .word 0x02fffeff
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+    .word 0xfd01fefd
 .global v8b
 .balign NR_LANES*4
 v8b:
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     .word 0xfcfc0002
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     .word 0x00000202
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+    .word 0x0002fdfd
+    .word 0x02ff01fc
+    .word 0x020002fc
+    .word 0x01fc02fc
+    .word 0x020002fc
+    .word 0xfc0000ff
+    .word 0x0102fc02
+    .word 0x010001fe
+    .word 0x02fdfffe
+    .word 0x02fcfe01
+    .word 0x00fffcff
+    .word 0x00fdfd00
+    .word 0xfd02fd02
+    .word 0xfdfcfdfe
+    .word 0x00020002
     .word 0x00ff00ff
-    .word 0x02fd00fc
-    .word 0xfc02ff01
-    .word 0x02fdfeff
-    .word 0x01fd01fe
-    .word 0x02fd0002
+    .word 0x02fcfcfc
+    .word 0xfcfffdfd
+    .word 0x02fdfffd
+    .word 0xfcfdfd00
+    .word 0x01fcff00
+    .word 0xfcfd00fe
+    .word 0x0201fc02
+    .word 0xff00fcfc
+    .word 0xfd00fefc
+    .word 0xff00fefc
+    .word 0xfffefefc
+    .word 0xfc01fe01
+    .word 0x02010002
+    .word 0xfcfc02fc
+    .word 0x0001ff01
+    .word 0xfffd02ff
+    .word 0x00fdfffe
+    .word 0xfefffefc
+    .word 0xfefffc01
+    .word 0x0202fefc
+    .word 0x01fc00fe
+    .word 0xfc00fdfd
+    .word 0x0102fc02
+    .word 0xff02fc02
+    .word 0xfd0201fe
+    .word 0xfdfd00ff
+    .word 0xfefffcff
+    .word 0xfcfeffff
+    .word 0x01fffefe
+    .word 0x00fcfffc
+    .word 0x02fdff02
+    .word 0x00fdfe01
+    .word 0xfe01fcfc
+    .word 0x01fd0002
+    .word 0xfdfe02fe
+    .word 0x020002fc
+    .word 0xfdfffefe
+    .word 0x02fefc02
+    .word 0xfcff02fe
+    .word 0x00fc0202
+    .word 0xfdfd0002
+    .word 0xfc00fdff
+    .word 0xfffe0002
+    .word 0xfdfd0202
+    .word 0x01fdfd02
+    .word 0x0102fc01
+    .word 0x02fefc02
+    .word 0x020102ff
+    .word 0x0100fffd
+    .word 0xfefefcfc
+    .word 0x01ff0001
+    .word 0x0101fffe
+    .word 0xfefdfdfc
+    .word 0xfe0202ff
+    .word 0x0102fcfd
+    .word 0x010100fd
+    .word 0x0002fdfc
+    .word 0xfcff02fd
+    .word 0xfefc0200
+    .word 0xfefffc00
+    .word 0x0100fd01
+    .word 0x0202fdfe
+    .word 0x00fcfc00
+    .word 0x00fcff00
+    .word 0xfcfc00ff
+    .word 0xfcfe00fe
+    .word 0xfeff0202
+    .word 0xfefdfdfc
+    .word 0x02fefcfd
 .global res64_v
 .balign 8
 res64_v:
diff --git a/apps/dotproduct/main.c b/apps/dotproduct/main.c
index f864e00..d6a5965 100644
--- a/apps/dotproduct/main.c
+++ b/apps/dotproduct/main.c
@@ -62,7 +62,9 @@ int main() {
 
   int64_t runtime_s, runtime_v;
 
-  for (uint64_t avl = 8; avl <= (vsize >> 3); avl *= 8) {
+  // for (uint64_t avl = 32; avl <= (vsize >> 3); avl *= 2) {
+  for (uint64_t avl = (vsize >> 3); avl >=8; avl /= 2) {
+  // uint64_t avl = 4;
     // Dotp
     printf("Calulating 64b dotp with vectors with length = %lu\n", avl);
     start_timer();
@@ -87,80 +89,81 @@ int main() {
     }
   }
 
-  for (uint64_t avl = 8; avl <= (vsize >> 2); avl *= 8) {
-    // Dotp
-    printf("Calulating 32b dotp with vectors with length = %lu\n", avl);
-    start_timer();
-    res32_v = dotp_v32b(v32a, v32b, avl);
-    stop_timer();
-    runtime_v = get_timer();
-    printf("Vector runtime: %ld\n", runtime_v);
-
-    if (SCALAR) {
-      start_timer();
-      res32_s = dotp_s32b(v32a, v32b, avl);
-      stop_timer();
-      runtime_s = get_timer();
-      printf("Scalar runtime: %ld\n", runtime_s);
-
-      if (CHECK) {
-        if (res32_v != res32_s) {
-          printf("Error: v = %ld, g = %ld\n", res32_v, res32_s);
-          return -1;
-        }
-      }
-    }
-  }
-
-  for (uint64_t avl = 8; avl <= (vsize >> 1); avl *= 8) {
-    // Dotp
-    printf("Calulating 16b dotp with vectors with length = %lu\n", avl);
-    start_timer();
-    res16_v = dotp_v16b(v16a, v16b, avl);
-    stop_timer();
-    runtime_v = get_timer();
-    printf("Vector runtime: %ld\n", runtime_v);
-
-    if (SCALAR) {
-      start_timer();
-      res16_s = dotp_s16b(v16a, v16b, avl);
-      stop_timer();
-      runtime_s = get_timer();
-      printf("Scalar runtime: %ld\n", runtime_s);
-
-      if (CHECK) {
-        if (res16_v != res16_s) {
-          printf("Error: v = %ld, g = %ld\n", res16_v, res16_s);
-          return -1;
-        }
-      }
-    }
-  }
-
-  for (uint64_t avl = 8; avl <= (vsize >> 0); avl *= 8) {
-    // Dotp
-    printf("Calulating 8b dotp with vectors with length = %lu\n", avl);
-    start_timer();
-    res8_v = dotp_v8b(v8a, v8b, avl);
-    stop_timer();
-    runtime_v = get_timer();
-    printf("Vector runtime: %ld\n", runtime_v);
-
-    if (SCALAR) {
-      start_timer();
-      res8_s = dotp_s8b(v8a, v8b, avl);
-      stop_timer();
-      runtime_s = get_timer();
-      printf("Scalar runtime: %ld\n", runtime_s);
-
-      if (CHECK) {
-        if (res8_v != res8_s) {
-          printf("Error: v = %ld, g = %ld\n", res8_v, res8_s);
-          return -1;
-        }
-      }
-    }
-  }
+  // for (uint64_t avl = 8; avl <= (vsize >> 2); avl *= 8) {
+  //   // Dotp
+  //   // uint64_t avl = 4;
+  //   printf("Calulating 32b dotp with vectors with length = %lu\n", avl);
+  //   start_timer();
+  //   res32_v = dotp_v32b(v32a, v32b, avl);
+  //   stop_timer();
+  //   runtime_v = get_timer();
+  //   printf("Vector runtime: %ld\n", runtime_v);
+
+  //   if (SCALAR) {
+  //     start_timer();
+  //     res32_s = dotp_s32b(v32a, v32b, avl);
+  //     stop_timer();
+  //     runtime_s = get_timer();
+  //     printf("Scalar runtime: %ld\n", runtime_s);
+
+  //     if (CHECK) {
+  //       if (res32_v != res32_s) {
+  //         printf("Error: v = %ld, g = %ld\n", res32_v, res32_s);
+  //         return -1;
+  //       }
+  //     }
+  //   }
+  // }
+
+  // for (uint64_t avl = 8; avl <= (vsize >> 1); avl *= 8) {
+  //   // Dotp
+  //   printf("Calulating 16b dotp with vectors with length = %lu\n", avl);
+  //   start_timer();
+  //   res16_v = dotp_v16b(v16a, v16b, avl);
+  //   stop_timer();
+  //   runtime_v = get_timer();
+  //   printf("Vector runtime: %ld\n", runtime_v);
+
+  //   if (SCALAR) {
+  //     start_timer();
+  //     res16_s = dotp_s16b(v16a, v16b, avl);
+  //     stop_timer();
+  //     runtime_s = get_timer();
+  //     printf("Scalar runtime: %ld\n", runtime_s);
+
+  //     if (CHECK) {
+  //       if (res16_v != res16_s) {
+  //         printf("Error: v = %ld, g = %ld\n", res16_v, res16_s);
+  //         return -1;
+  //       }
+  //     }
+  //   }
+  // }
+
+  // for (uint64_t avl = 8; avl <= (vsize >> 0); avl *= 8) {
+  //   // Dotp
+  //   printf("Calulating 8b dotp with vectors with length = %lu\n", avl);
+  //   start_timer();
+  //   res8_v = dotp_v8b(v8a, v8b, avl);
+  //   stop_timer();
+  //   runtime_v = get_timer();
+  //   printf("Vector runtime: %ld\n", runtime_v);
+
+  //   if (SCALAR) {
+  //     start_timer();
+  //     res8_s = dotp_s8b(v8a, v8b, avl);
+  //     stop_timer();
+  //     runtime_s = get_timer();
+  //     printf("Scalar runtime: %ld\n", runtime_s);
+
+  //     if (CHECK) {
+  //       if (res8_v != res8_s) {
+  //         printf("Error: v = %ld, g = %ld\n", res8_v, res8_s);
+  //         return -1;
+  //       }
+  //     }
+  //   }
+  // }
 
   printf("SUCCESS.\n");
 
diff --git a/apps/dotproduct/script/gen_data.py b/apps/dotproduct/script/gen_data.py
index 371c906..c6eb863 100755
--- a/apps/dotproduct/script/gen_data.py
+++ b/apps/dotproduct/script/gen_data.py
@@ -48,6 +48,8 @@ def emit(name, array, alignment='8'):
 # Create the vectors
 v64a = np.random.randint(-2**(50), high=2**(50)-1, size=avl64, dtype=np.int64)
 v64b = np.random.randint(-2**(50), high=2**(50)-1, size=avl64, dtype=np.int64)
+# v64a = np.random.randint(1, 2, size=avl64, dtype=np.int64)
+# v64b = np.random.randint(1, 2, size=avl64, dtype=np.int64)
 v32a = np.random.randint(-2**(20), high=2**(20)-1, size=avl32, dtype=np.int32)
 v32b = np.random.randint(-2**(20), high=2**(20)-1, size=avl32, dtype=np.int32)
 v16a = np.random.randint(-2**(10), high=2**(10)-1, size=avl16, dtype=np.int16)
diff --git a/apps/fdotproduct/main.c b/apps/fdotproduct/main.c
index 028d799..55bf647 100644
--- a/apps/fdotproduct/main.c
+++ b/apps/fdotproduct/main.c
@@ -72,8 +72,10 @@ int main() {
 
   uint64_t runtime_s, runtime_v;
 
-  //for (uint64_t avl = 8; avl <= (vsize >> 3); avl *= 8) {
-    uint64_t avl = vsize;
+  // for (uint64_t avl = 32; avl <= (vsize >> 3); avl *= 2) {
+  for (uint64_t avl = (vsize >> 3); avl >= 8; avl /= 2) {
+    // uint64_t avl = vsize >> 3;
+    // uint64_t avl = 4;
     printf("Calulating 64b dotp with vectors with length = %lu\n", avl);
     start_timer();
     res64_v = fdotp_v64b(v64a, v64b, avl);
@@ -98,49 +100,49 @@ int main() {
         }
       }
     }
-  // }
+  }
 
-  /*
-  // for (uint64_t avl = 16; avl <= (vsize); avl *= 2) {
-    uint64_t avl=vsize;
-    printf("Calulating 32b dotp with vectors with length = %lu\n", avl);
-    start_timer();
-    res32_v = fdotp_v32b(v32a, v32b, avl);
-    stop_timer();
-    runtime_v = get_timer();
-    printf("Vector runtime: %ld\n", runtime_v);
 
-    if (SCALAR) {
-      start_timer();
-      res32_s = fdotp_s32b(v32a, v32b, avl);
-      stop_timer();
-      runtime_s = get_timer();
-      printf("Scalar runtime: %ld\n", runtime_s);
-    }
-
-    if (CHECK) {
-      if (SCALAR) {
-        printf("Checking results: v = %f, s = %f\n", res32_v, res32_s);
-        if (!similarity_check_32b(res32_v, res32_s, THRESHOLD_32b)) {
-          printf("Error: v = %f, s = %f\n", res32_v, res32_s);
-          return -1;
-        }
-      }
-    }
-
-    // Dotproduct Arithmetic intensity calculation
-    // Ops = 2N FP32 ops 
-    // Bytes = 2N * 4B = 8N Bytes , AI = 1/4 FP32 Op/B
-    // BW = 32N bits/ cycle = 4N Bytes
-    // Max Perf = N * 2 * 2 FP32op/cycle = 4N FP32 op/cycle
-    // From roofline max perf at the arithmetic intensity = N FP32 op/cycle
-    float performance = avl * 1.0 / runtime_v;
-    float utilization = 100.0 * performance / (NR_LANES * NR_CLUSTERS);
-    printf("The execution took %d cycles.\n", runtime_v);
-    printf("The performance is %f FLOP/cycle (%f%% utilization).\n",
-           performance, utilization);
-
-  // }*/
+  // for (uint64_t avl = 16; avl <= (vsize); avl *= 2) {
+  // for (uint64_t avl = 32; avl <= 32; avl *= 2) {
+    // uint64_t avl=4;
+    // printf("Calulating 32b dotp with vectors with length = %lu\n", avl);
+    // start_timer();
+    // res32_v = fdotp_v32b(v32a, v32b, avl);
+    // stop_timer();
+    // runtime_v = get_timer();
+    // printf("Vector runtime: %ld\n", runtime_v);
+
+    // if (SCALAR) {
+    //   start_timer();
+    //   res32_s = fdotp_s32b(v32a, v32b, avl);
+    //   stop_timer();
+    //   runtime_s = get_timer();
+    //   printf("Scalar runtime: %ld\n", runtime_s);
+    // }
+
+    // if (CHECK) {
+    //   if (SCALAR) {
+    //     printf("Checking results: v = %f, s = %f\n", res32_v, res32_s);
+    //     if (!similarity_check_32b(res32_v, res32_s, THRESHOLD_32b)) {
+    //       printf("Error: v = %f, s = %f\n", res32_v, res32_s);
+    //       return -1;
+    //     }
+    //   }
+    // }
+
+    // // Dotproduct Arithmetic intensity calculation
+    // // Ops = 2N FP32 ops 
+    // // Bytes = 2N * 4B = 8N Bytes , AI = 1/4 FP32 Op/B
+    // // BW = 32N bits/ cycle = 4N Bytes
+    // // Max Perf = N * 2 * 2 FP32op/cycle = 4N FP32 op/cycle
+    // // From roofline max perf at the arithmetic intensity = N FP32 op/cycle
+    // float performance = avl * 1.0 / runtime_v;
+    // float utilization = 100.0 * performance / (NR_LANES * NR_CLUSTERS);
+    // printf("The execution took %d cycles.\n", runtime_v);
+    // printf("The performance is %f FLOP/cycle (%f%% utilization).\n",
+    //        performance, utilization);
+  // }
   
   /*
   for (uint64_t avl = 8; avl <= (vsize >> 2); avl *= 8) {
diff --git a/apps/fdotproduct/script/gen_data.py b/apps/fdotproduct/script/gen_data.py
index 15c06ed..f91155e 100755
--- a/apps/fdotproduct/script/gen_data.py
+++ b/apps/fdotproduct/script/gen_data.py
@@ -47,6 +47,8 @@ def emit(name, array, alignment='8'):
 # Create the vectors
 v64a = np.random.rand(avl64).astype(np.float64)
 v64b = np.random.rand(avl64).astype(np.float64)
+# v64a = np.ones(avl64, dtype=np.float64)
+# v64b = np.ones(avl64, dtype=np.float64)
 v32a = np.random.rand(avl32).astype(np.float32)
 v32b = np.random.rand(avl32).astype(np.float32)
 v16a = np.random.rand(avl16).astype(np.float16)
diff --git a/apps/fmatmul/main.c b/apps/fmatmul/main.c
index b8977b8..91b46e3 100644
--- a/apps/fmatmul/main.c
+++ b/apps/fmatmul/main.c
@@ -52,6 +52,7 @@ int verify_matrix(double *result, double *gold, size_t R, size_t C,
     for (uint64_t j = 0; j < C; ++j) {
       uint64_t idx = i * C + j;
       if (!similarity_check(result[idx], gold[idx], threshold)) {
+      // if (!similarity_check(result[idx+1], gold[idx], threshold)) {
         return (i + j) == 0 ? -1 : idx;
       }
     }
@@ -119,6 +120,7 @@ int main() {
     printf("Calculating fmatmul 64-bit...\n");
     start_timer();
     fmatmul(c, a, b, s, N, P);
+    // fmatmul(c+1, a, b, s, N, P);
     stop_timer();
 #endif
 
diff --git a/apps/fmatmul/script/gen_data.py b/apps/fmatmul/script/gen_data.py
index ec77e8f..76c57bc 100644
--- a/apps/fmatmul/script/gen_data.py
+++ b/apps/fmatmul/script/gen_data.py
@@ -54,6 +54,7 @@ def emit(name, array, alignment='8'):
 # Matrices and results
 A = np.random.rand(M, N).astype(dtype)
 B = np.random.rand(N, P).astype(dtype)
+# C = np.zeros([M+1, P+1], dtype=dtype)
 C = np.zeros([M, P], dtype=dtype)
 # Golden result matrix
 G = np.matmul(A, B).astype(dtype)
diff --git a/hardware/include/ara_pkg.sv b/hardware/include/ara_pkg.sv
index 55ff403..1bbacfc 100644
--- a/hardware/include/ara_pkg.sv
+++ b/hardware/include/ara_pkg.sv
@@ -1060,6 +1060,9 @@ package ara_pkg;
 
     // Hazards
     logic [NrVInsn-1:0] hazard;
+
+    // Reduction idle case
+    logic instr_idle;
   } operand_request_cmd_t;
 
   typedef struct packed {
@@ -1069,6 +1072,8 @@ package ara_pkg;
     logic [1:0] ntr_red;       // Neutral type for reductions
     logic is_reduct;           // Is this a reduction?
     target_fu_e target_fu;     // Target FU of the opqueue (if it is not clear)
+    // Reduction idle case
+    logic instr_idle;
   } operand_queue_cmd_t;
 
   // This is the interface between the lane's sequencer and the lane's VFUs.
@@ -1100,6 +1105,7 @@ package ara_pkg;
     vlen_t vl;
     vlen_t vstart;
     rvv_pkg::vtype_t vtype;
+    logic instr_idle;
   } vfu_operation_t;
 
   // Due to the shuffled nature of the vector elements inside one lane, the byte enable
diff --git a/hardware/src/ara.sv b/hardware/src/ara.sv
index 4f51486..d39f5f1 100644
--- a/hardware/src/ara.sv
+++ b/hardware/src/ara.sv
@@ -9,6 +9,7 @@
 module ara import ara_pkg::*; import rvv_pkg::*; #(
     // RVV Parameters
     parameter  int           unsigned NrLanes      = 0,  // Number of parallel vector lanes.
+    parameter  int           unsigned NrClusters   = 0,   // Number of Ara instances
     // Support for floating-point data types
     parameter  fpu_support_e          FPUSupport   = FPUSupportHalfSingleDouble,
     // External support for vfrec7, vfrsqrt7
@@ -104,12 +105,14 @@ module ara import ara_pkg::*; import rvv_pkg::*; #(
   vxrm_t     [NrLanes-1:0]      alu_vxrm;
 
   ara_dispatcher #(
-    .NrLanes     (NrLanes    )
+    .NrLanes     (NrLanes    ),
+    .NrClusters  (NrClusters )
   ) i_dispatcher (
     .clk_i             (clk_i           ),
     .rst_ni            (rst_ni          ),
     // Id
     .num_clusters_i    (num_clusters_i  ),
+    .cluster_id_i      (cluster_id_i    ),
     // Interface with Ariane
     .acc_req_i         (acc_req_i       ),
     .acc_resp_o        (acc_resp_o      ),
diff --git a/hardware/src/ara_cluster.sv b/hardware/src/ara_cluster.sv
index 901e023..1c1fb3a 100644
--- a/hardware/src/ara_cluster.sv
+++ b/hardware/src/ara_cluster.sv
@@ -130,6 +130,7 @@ module ara_cluster import ara_pkg::*; import rvv_pkg::*;  #(
   for (genvar cluster=0; cluster < NrClusters; cluster++) begin : p_cluster
       ara_macro #(
         .NrLanes           (NrLanes             ),
+        .NrClusters        (NrClusters          ),
         .FPUSupport        (FPUSupport          ),
         .FPExtSupport      (FPExtSupport        ),
         .FixPtSupport      (FixPtSupport        ),
@@ -331,8 +332,8 @@ module ara_cluster import ara_pkg::*; import rvv_pkg::*;  #(
   assign ara_axi_req_cut = ara_axi_req_shuffle_cut[ShuffleCuts];
   assign ara_axi_resp_shuffle_cut[ShuffleCuts] = ara_axi_resp_cut;
   shuffle_stage #(
-    .NrLanes              (NrLanes              ),
-    .NrClusters           (NrClusters           ),
+      .NrLanes            (NrLanes              ),
+      .NrClusters         (NrClusters           ),
       .ClusterAxiDataWidth(ClusterAxiDataWidth  ),
       .AxiAddrWidth       (AxiAddrWidth         ),
       .axi_r_t            (cluster_axi_r_t      ),
@@ -421,6 +422,7 @@ module ara_cluster import ara_pkg::*; import rvv_pkg::*;  #(
 
   // Align stage
   align_stage #(
+      .NrLanes          (NrLanes            ),
       .NrClusters       (NrClusters         ),
       .AxiDataWidth     (AxiDataWidth       ),
       .AxiAddrWidth     (AxiAddrWidth       ),
diff --git a/hardware/src/ara_dispatcher.sv b/hardware/src/ara_dispatcher.sv
index e6f5c90..a10924f 100644
--- a/hardware/src/ara_dispatcher.sv
+++ b/hardware/src/ara_dispatcher.sv
@@ -10,6 +10,7 @@
 
 module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
     parameter int           unsigned NrLanes      = 0,
+    parameter int           unsigned NrClusters   = 0,   // Number of Ara instances
     // Support for floating-point data types
     parameter fpu_support_e          FPUSupport   = FPUSupportHalfSingleDouble,
     // External support for vfrec7, vfrsqrt7
@@ -22,6 +23,7 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
     input  logic                                 rst_ni,
     // Id
     input num_cluster_t                          num_clusters_i,
+    input  id_cluster_t                          cluster_id_i,
     // Interfaces with Ariane
     input  accelerator_req_t                     acc_req_i,
     output accelerator_resp_t                    acc_resp_o,
@@ -224,7 +226,8 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
   // Is the stride power of two?
   popcount #(
     // .INPUT_WIDTH (idx_width(VLENB << 3))
-    .INPUT_WIDTH (2)
+    // .INPUT_WIDTH (2)
+    .INPUT_WIDTH ($clog2(NrLanes))
   ) i_np2_stride (
     //.data_i    (ara_req_d.stride[idx_width(VLENB << 3)-1:0]),
     .data_i      (ara_req_d.stride[$clog2(NrLanes)-1:0]    ),
@@ -240,6 +243,13 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
   logic illegal_insn;
   elen_t vfmvfs_result;
 
+  vlen_t total_cluster_pieces;
+  // assign total_cluster_pieces = vlen_t'(acc_req_i.rs1) >> $clog2(VLENB >> vtype_d.vsew);
+  assign total_cluster_pieces = vlen_t'(acc_req_i.rs1) >> $clog2(NrLanes);
+
+  vlen_t check_total_cluster_pieces;
+  assign check_total_cluster_pieces = ((total_cluster_pieces >> $clog2(NrClusters)) + 1) * NrLanes;
+
   always_comb begin: p_decoder
     // Default values
     vstart_d     = vstart_q;
@@ -473,6 +483,7 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
                     (signed'($clog2(ELENB)) + signed'(vtype_d.vlmul) < signed'(vtype_d.vsew))) begin
                   vtype_d = '{vill: 1'b1, default: '0};
                   vl_d    = '0;
+                  acc_resp_o.result = vl_d << num_clusters_i;
                 end
 
                 // Update the vector length
@@ -493,24 +504,46 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
 
                   if (insn.vsetivli_type.func2 == 2'b11) begin // vsetivli
                     vl_d = vlen_t'(insn.vsetivli_type.uimm5) >> num_clusters_i;
+                    acc_resp_o.result = vl_d << num_clusters_i;
                   end else begin // vsetvl || vsetvli
                     if (insn.vsetvl_type.rs1 == '0 && insn.vsetvl_type.rd == '0) begin
                       // Do not update the vector length
                       vl_d = vl_q;
+                      acc_resp_o.result = vl_d << num_clusters_i;
                     end else if (insn.vsetvl_type.rs1 == '0 && insn.vsetvl_type.rd != '0) begin
                       // Set the vector length to vlmax
                       vl_d = vlmax;
+                      acc_resp_o.result = vl_d << num_clusters_i;
                     end else begin
+                      // // Normal stripmining
+                      // vl_d = ((|acc_req_i.rs1[$bits(acc_req_i.rs1)-1:$bits(vl_d)]) ||
+                      //   ((vlen_t'(acc_req_i.rs1) >> num_clusters_i) > vlmax)) ? vlmax : (vlen_t'(acc_req_i.rs1) >> num_clusters_i);
                       // Normal stripmining
-                      vl_d = ((|acc_req_i.rs1[$bits(acc_req_i.rs1)-1:$bits(vl_d)]) ||
-                        ((vlen_t'(acc_req_i.rs1) >> num_clusters_i) > vlmax)) ? vlmax : (vlen_t'(acc_req_i.rs1) >> num_clusters_i);
+                      if ((|acc_req_i.rs1[$bits(acc_req_i.rs1)-1:$bits(vl_d)]) || 
+                        ((vlen_t'(acc_req_i.rs1) >> $clog2(NrClusters)) > vlmax)) begin
+                        vl_d = vlmax;
+                        // Return the new vl
+                        acc_resp_o.result = vl_d << num_clusters_i;
+                      end else begin
+                        if (cluster_id_i < total_cluster_pieces[$clog2(NrClusters) - 1 : 0]) begin
+                          // vl_d = (total_cluster_pieces >> $clog2(NrClusters) + 1) * (VLENB >> vtype_d.vsew);
+                          vl_d = ((total_cluster_pieces >> $clog2(NrClusters)) + 1) * NrLanes;
+                        end else if (cluster_id_i == total_cluster_pieces[$clog2(NrClusters) - 1 : 0]) begin
+                          // vl_d = (total_cluster_pieces >> $clog2(NrClusters)) * (VLENB >> vtype_d.vsew) + 
+                          //         acc_req_i.rs1 % (VLENB >> vtype_d.vsew);
+                          vl_d = (total_cluster_pieces >> $clog2(NrClusters)) * NrLanes + 
+                                  acc_req_i.rs1 % NrLanes;
+                        end else begin
+                          // vl_d = (total_cluster_pieces >> $clog2(NrClusters)) * (VLENB >> vtype_d.vsew);
+                          vl_d = (total_cluster_pieces >> $clog2(NrClusters)) * NrLanes;
+                        end
+                        // Return the new vl
+                        acc_resp_o.result = vlen_t'(acc_req_i.rs1);
+                      end
                     end
                   end
                 end
 
-                // Return the new vl
-                acc_resp_o.result = vl_d << num_clusters_i;
-
                 // If the vtype has changed, wait for the backend before issuing any new instructions.
                 // This is to avoid hazards on implicit register labels when LMUL_old > LMUL_new
                 // and both the LMULs are greater then LMUL_1 (i.e., lmul[2] == 1'b0)
@@ -3210,7 +3243,8 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
 
     // Any valid non-config instruction is a NOP if vl == 0, with some exceptions,
     // e.g. whole vector memory operations / whole vector register move
-    if (is_decoding && (vl_q == '0 || null_vslideup) && !is_config &&
+    if (is_decoding && (vl_q == '0 || null_vslideup) && !is_config && 
+      !(ara_req_d.op inside {[VREDSUM:VWREDSUM], [VFREDUSUM:VFWREDOSUM]}) &&
       !ignore_zero_vl_check && !acc_resp_o.error) begin
       // If we are acknowledging a memory operation, we must tell Ariane that the memory
       // operation was resolved (to decrement its pending load/store counter)
diff --git a/hardware/src/ara_macro.sv b/hardware/src/ara_macro.sv
index 4d0afec..4b826f8 100644
--- a/hardware/src/ara_macro.sv
+++ b/hardware/src/ara_macro.sv
@@ -9,6 +9,7 @@
 module ara_macro import ara_pkg::*; import rvv_pkg::*; #(
     // RVV Parameters
     parameter  int           unsigned NrLanes      = 0,   // Number of parallel vector lanes per Ara instance
+    parameter  int           unsigned NrClusters   = 0,   // Number of Ara instances
 
     // Support for floating-point data types
     parameter  fpu_support_e          FPUSupport   = FPUSupportHalfSingleDouble,
@@ -228,6 +229,7 @@ module ara_macro import ara_pkg::*; import rvv_pkg::*; #(
 
   ara #(
     .NrLanes     (NrLanes             ),
+    .NrClusters  (NrClusters          ),
     .FPUSupport  (FPUSupport          ),
     .FPExtSupport(FPExtSupport        ),
     .FixPtSupport(FixPtSupport        ),
diff --git a/hardware/src/lane/lane_sequencer.sv b/hardware/src/lane/lane_sequencer.sv
index 864ce70..e74bd1e 100644
--- a/hardware/src/lane/lane_sequencer.sv
+++ b/hardware/src/lane/lane_sequencer.sv
@@ -263,7 +263,11 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
       vfu_operation_valid_d = (vfu_operation_d.vfu != VFU_None) ? 1'b1 : 1'b0;
 
       // Vector length calculation
+      // vfu_operation_d.vl = (!pe_req.vl) ? 1 : pe_req.vl / NrLanes;
       vfu_operation_d.vl = pe_req.vl / NrLanes;
+      // For idle reduction case
+      vfu_operation_d.instr_idle = !pe_req.vl;
+
       // If lane_id_i < vl % NrLanes, this lane has to execute one extra micro-operation.
       if (lane_id_i < pe_req.vl[idx_width(NrLanes)-1:0]) vfu_operation_d.vl += 1;
 
@@ -307,6 +311,7 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
             hazard     : pe_req.hazard_vs1 | pe_req.hazard_vd,
             is_reduct  : pe_req.op inside {[VREDSUM:VWREDSUM]} ? 1'b1 : 0,
             target_fu  : ALU_SLDU,
+            instr_idle : !pe_req.vl,
             default    : '0
           };
           operand_request_push[AluA] = pe_req.use_vs1;
@@ -328,6 +333,7 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
             hazard     : pe_req.hazard_vs2 | pe_req.hazard_vd,
             is_reduct  : pe_req.op inside {[VREDSUM:VWREDSUM]} ? 1'b1 : 0,
             target_fu  : ALU_SLDU,
+            instr_idle : !pe_req.vl,
             default    : '0
           };
           operand_request_push[AluB] = pe_req.use_vs2;
@@ -343,6 +349,7 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
             vl     : (pe_req.vl / NrLanes / 8) >> int'(pe_req.vtype.vsew),
             vstart : vfu_operation_d.vstart,
             hazard : pe_req.hazard_vm | pe_req.hazard_vd,
+            instr_idle : !pe_req.vl,
             default: '0
           };
           if ((operand_request_i[MaskM].vl << int'(pe_req.vtype.vsew)) *
@@ -362,10 +369,12 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
             // If reductions and vl == 0, we must replace the operands with neutral
             // values in the opqueues. So, vl must be 1 at least
             vl         : (pe_req.op inside {[VFREDUSUM:VFWREDOSUM]}) ? 1 : vfu_operation_d.vl,
+            // vl         : (pe_req.op inside {[VFREDUSUM:VFWREDOSUM]}) ? (|pe_req.vl ? 1 : 0) : vfu_operation_d.vl,
             vstart     : vfu_operation_d.vstart,
             hazard     : pe_req.hazard_vs1 | pe_req.hazard_vd,
             is_reduct  : pe_req.op inside {[VFREDUSUM:VFWREDOSUM]} ? 1'b1 : 0,
             target_fu  : MFPU_ADDRGEN,
+            instr_idle : !pe_req.vl,
             default    : '0
           };
           operand_request_push[MulFPUA] = pe_req.use_vs1;
@@ -388,6 +397,7 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
             pe_req.hazard_vd : (pe_req.hazard_vs2 | pe_req.hazard_vd)),
             is_reduct  : pe_req.op inside {[VFREDUSUM:VFWREDOSUM]} ? 1'b1 : 0,
             target_fu  : MFPU_ADDRGEN,
+            instr_idle : !pe_req.vl,
             default: '0
           };
           operand_request_push[MulFPUB] = pe_req.swap_vs2_vd_op ?
@@ -404,12 +414,14 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
             // values in the opqueues. So, vl must be 1 at least
             vl         : (pe_req.op inside {[VFREDUSUM:VFWREDOSUM]} && vfu_operation_d.vl == '0)
                         ? 1 : vfu_operation_d.vl,
+            // vl         : vfu_operation_d.vl = vfu_operation_d.vl,
             vstart     : vfu_operation_d.vstart,
             vtype      : pe_req.vtype,
             hazard     : pe_req.swap_vs2_vd_op ?
             (pe_req.hazard_vs2 | pe_req.hazard_vd) : pe_req.hazard_vd,
             is_reduct  : pe_req.op inside {[VFREDUSUM:VFWREDOSUM]} ? 1'b1 : 0,
             target_fu  : MFPU_ADDRGEN,
+            instr_idle : !pe_req.vl,
             default : '0
           };
           operand_request_push[MulFPUC] = pe_req.swap_vs2_vd_op ?
@@ -426,6 +438,7 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
             vl     : (pe_req.vl / NrLanes / 8) >> int'(pe_req.vtype.vsew),
             vstart : vfu_operation_d.vstart,
             hazard : pe_req.hazard_vm | pe_req.hazard_vd,
+            instr_idle : !pe_req.vl,
             default: '0
           };
           if ((operand_request_i[MaskM].vl << int'(pe_req.vtype.vsew)) *
@@ -444,6 +457,7 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
             vl     : (pe_req.vl / NrLanes / 8) >> int'(pe_req.vtype.vsew),
             vstart : vfu_operation_d.vstart,
             hazard : pe_req.hazard_vm | pe_req.hazard_vd,
+            instr_idle : !pe_req.vl,
             default: '0
           };
           if ((operand_request_i[MaskM].vl << int'(pe_req.vtype.vsew)) *
@@ -462,6 +476,7 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
             vstart   : vfu_operation_d.vstart,
             vtype    : pe_req_i.vtype,
             hazard   : pe_req_i.hazard_vs2 | pe_req_i.hazard_vd,
+            instr_idle : !pe_req.vl,
             default  : '0
           };
           // Since this request goes outside of the lane, we might need to request an
@@ -484,6 +499,7 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
             vl      : pe_req.vl / NrLanes,
             vstart  : vfu_operation_d.vstart,
             hazard  : pe_req.hazard_vs1 | pe_req.hazard_vd,
+            instr_idle : !pe_req.vl,
             default : '0
           };
           if (operand_request_i[StA].vl * NrLanes != pe_req.vl) operand_request_i[StA].vl += 1;
@@ -500,6 +516,7 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
             vl     : (pe_req.vl / NrLanes / 8) >> int'(pe_req.vtype.vsew),
             vstart : vfu_operation_d.vstart,
             hazard : pe_req.hazard_vm | pe_req.hazard_vd,
+            instr_idle : !pe_req.vl,
             default: '0
           };
           if ((operand_request_i[MaskM].vl << int'(pe_req.vtype.vsew)) *
@@ -518,6 +535,7 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
             vstart   : vfu_operation_d.vstart,
             vtype    : pe_req_i.vtype,
             hazard   : pe_req_i.hazard_vs2 | pe_req_i.hazard_vd,
+            instr_idle : !pe_req.vl,
             default  : '0
           };
           // Since this request goes outside of the lane, we might need to request an
@@ -538,6 +556,7 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
             vtype    : pe_req.vtype,
             vstart   : vfu_operation_d.vstart,
             hazard   : pe_req.hazard_vs2 | pe_req.hazard_vd,
+            instr_idle : !pe_req.vl,
             default  : '0
           };
           operand_request_push[SlideAddrGenA] = pe_req.use_vs2;
@@ -601,6 +620,7 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
             vtype  : pe_req.vtype,
             vstart : vfu_operation_d.vstart,
             hazard : pe_req.hazard_vm | pe_req.hazard_vd,
+            instr_idle : !pe_req.vl,
             default: '0
           };
           operand_request_push[MaskM] = !pe_req.vm;
@@ -647,6 +667,7 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
             vtype   : pe_req.vtype,
             vstart  : vfu_operation_d.vstart,
             hazard  : pe_req.hazard_vs1 | pe_req.hazard_vd,
+            instr_idle : !pe_req.vl,
             default : '0
           };
 
@@ -675,6 +696,7 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
             vtype   : pe_req.vtype,
             vstart  : vfu_operation_d.vstart,
             hazard  : pe_req.hazard_vs2 | pe_req.hazard_vd,
+            instr_idle : !pe_req.vl,
             default : '0
           };
           // This is an operation that runs normally on the ALU, and then gets *condensed* and
@@ -702,6 +724,7 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
             vtype   : pe_req.vtype,
             vstart  : vfu_operation_d.vstart,
             hazard  : pe_req.hazard_vs1 | pe_req.hazard_vd,
+            instr_idle : !pe_req.vl,
             default : '0
           };
 
@@ -718,6 +741,7 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
             vtype   : pe_req.vtype,
             vstart  : vfu_operation_d.vstart,
             hazard  : pe_req.hazard_vs2 | pe_req.hazard_vd,
+            instr_idle : !pe_req.vl,
             default : '0
           };
           // This is an operation that runs normally on the ALU, and then gets *condensed* and
@@ -736,6 +760,7 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
             vl      : (pe_req.vl / NrLanes / ELEN) << (int'(EW64) - int'(pe_req.vtype.vsew)),
             vstart  : vfu_operation_d.vstart,
             hazard  : pe_req.hazard_vd,
+            instr_idle : !pe_req.vl,
             default : '0
           };
           if (((pe_req.vl / NrLanes / ELEN) * NrLanes * ELEN) !=
@@ -752,6 +777,7 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
             vl     : (pe_req.vl / NrLanes / ELEN),
             vstart : vfu_operation_d.vstart,
             hazard : pe_req.hazard_vm,
+            instr_idle : !pe_req.vl,
             default: '0
           };
           if ((operand_request_i[MaskM].vl * NrLanes * ELEN) != pe_req.vl) begin
@@ -771,6 +797,7 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
             vl         : vfu_operation_d.vl,
             vstart     : vfu_operation_d.vstart,
             hazard     : pe_req.hazard_vs2,
+            instr_idle : !pe_req.vl,
             default    : '0
           };
           operand_request_push[MaskB] = 1'b1;
diff --git a/hardware/src/lane/operand_queue.sv b/hardware/src/lane/operand_queue.sv
index 10c075c..c180d63 100644
--- a/hardware/src/lane/operand_queue.sv
+++ b/hardware/src/lane/operand_queue.sv
@@ -314,10 +314,10 @@ module operand_queue import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::i
         if (SupportReduct) begin
           if (lane_id_i == '0) begin
             unique case (cmd.eew)
-              EW8 : conv_operand = {ntr.w8[7:1] , ibuf_operand[7:0]};
-              EW16: conv_operand = {ntr.w16[3:1], ibuf_operand[15:0]};
-              EW32: conv_operand = {ntr.w32[1:1], ibuf_operand[31:0]};
-              default:;
+              EW8 : conv_operand = (cmd.instr_idle) ? ntr.w8 : {ntr.w8[7:1] , ibuf_operand[7:0]};
+              EW16: conv_operand = (cmd.instr_idle) ? ntr.w16 : {ntr.w16[3:1], ibuf_operand[15:0]};
+              EW32: conv_operand = (cmd.instr_idle) ? ntr.w32 : {ntr.w32[1:1], ibuf_operand[31:0]};
+              default:conv_operand = (cmd.instr_idle) ? ntr.w64 : ibuf_operand;
             endcase
           end else begin
             conv_operand = ntr.w64;
@@ -369,21 +369,24 @@ module operand_queue import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::i
       // not to compromise reductions.
       default: begin
         // Pad only the last packet during a reduction, and pad the correct bytes only!
-        if (last_packet && incomplete_packet) begin
+        if (cmd.instr_idle || (last_packet && incomplete_packet)) begin
           if (SupportNtrVal) unique case (cmd.eew)
             EW8 : for (int unsigned b = 0; b < 8; b++) begin
                     automatic int unsigned bs = shuffle_index(b, 1, EW8);
-                    if ((b >> 0) >= cmd.vl[2:0]) conv_operand[8*bs +: 8] = ntr.w8[b];
+                    if (cmd.instr_idle || ((b >> 0) >= cmd.vl[2:0])) conv_operand[8*bs +: 8] = ntr.w8[b];
                   end
             EW16: for (int unsigned b = 0; b < 8; b++) begin
                     automatic int unsigned bs = shuffle_index(b, 1, EW16);
-                    if ((b >> 1) >= cmd.vl[1:0]) conv_operand[8*bs +: 8] = ntr.w8[b];
+                    if (cmd.instr_idle || ((b >> 1) >= cmd.vl[1:0])) conv_operand[8*bs +: 8] = ntr.w8[b];
                   end
             EW32: for (int unsigned b = 0; b < 8; b++) begin
                     automatic int unsigned bs = shuffle_index(b, 1, EW32);
-                    if ((b >> 2) >= cmd.vl[0:0]) conv_operand[8*bs +: 8] = ntr.w8[b];
+                    if (cmd.instr_idle || ((b >> 2) >= cmd.vl[0:0])) conv_operand[8*bs +: 8] = ntr.w8[b];
                   end
-            default:;
+            default:  for (int unsigned b = 0; b < 8; b++) begin
+                        automatic int unsigned bs = shuffle_index(b, 1, EW32);
+                        if (cmd.instr_idle) conv_operand[8*bs +: 8] = ntr.w8[b];
+                      end
           endcase
         end
       end
diff --git a/hardware/src/lane/operand_requester.sv b/hardware/src/lane/operand_requester.sv
index f660a21..ad2af99 100644
--- a/hardware/src/lane/operand_requester.sv
+++ b/hardware/src/lane/operand_requester.sv
@@ -303,7 +303,8 @@ module operand_requester import ara_pkg::*; import rvv_pkg::*; #(
               conv     : operand_request_i[requester].conv,
               ntr_red  : operand_request_i[requester].cvt_resize,
               target_fu: operand_request_i[requester].target_fu,
-              is_reduct: operand_request_i[requester].is_reduct
+              is_reduct: operand_request_i[requester].is_reduct,
+              instr_idle: operand_request_i[requester].instr_idle
             };
             // The length should be at least one after the rescaling
             if (operand_queue_cmd_o[requester].vl == '0)
@@ -392,7 +393,8 @@ module operand_requester import ara_pkg::*; import rvv_pkg::*; #(
                   conv     : operand_request_i[requester].conv,
                   ntr_red  : operand_request_i[requester].cvt_resize,
                   target_fu: operand_request_i[requester].target_fu,
-                  is_reduct: operand_request_i[requester].is_reduct
+                  is_reduct: operand_request_i[requester].is_reduct,
+                  instr_idle: operand_request_i[requester].instr_idle
                 };
                 operand_queue_cmd_valid_o[requester] = 1'b1;
                 // The length should be at least one after the rescaling
diff --git a/hardware/src/lane/valu.sv b/hardware/src/lane/valu.sv
index aefd481..8c2d210 100644
--- a/hardware/src/lane/valu.sv
+++ b/hardware/src/lane/valu.sv
@@ -21,6 +21,8 @@ module valu import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::idx_width;
     input  logic                         clk_i,
     input  logic                         rst_ni,
     input  logic[idx_width(NrLanes)-1:0] lane_id_i,
+    input  id_cluster_t                  cluster_id_i,
+    input  num_cluster_t                 num_clusters_i,
     // Interface with Dispatcher
     output logic                         vxsat_flag_o,
     input  vxrm_t                        alu_vxrm_i,
@@ -264,7 +266,7 @@ module valu import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::idx_width;
   // so on. In the end, the result is collected in Lane 0 and the last SIMD reduction is performed.
   // The following function determines how many partial results this lane must process during the
   // inter-lane reduction.
-  typedef logic [idx_width(NrLanes/2):0] reduction_rx_cnt_t;
+  typedef logic [idx_width(NrLanes*MaxNrClusters/2):0] reduction_rx_cnt_t;
   reduction_rx_cnt_t reduction_rx_cnt_d, reduction_rx_cnt_q;
   reduction_rx_cnt_t simd_red_cnt_max_d, simd_red_cnt_max_q;
 
@@ -298,6 +300,12 @@ module valu import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::idx_width;
     endcase
   endfunction: reduction_rx_cnt_init
 
+  // Inter cluster reductions are handled like inter lane reductions.
+  // In inter cluster only the last lane participates.
+  // Finally, the lane-0 receives the last packet for SIMD
+  id_cluster_t max_cluster_id; 
+  assign max_cluster_id = (1 << num_clusters_i) - 1;
+
   // Count how many transactions we must do in total to complete the reduction operation
   logic [idx_width($clog2(NrLanes)+1):0] sldu_transactions_cnt_d, sldu_transactions_cnt_q;
 
@@ -309,7 +317,10 @@ module valu import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::idx_width;
   logic first_op_d, first_op_q;
 
   // Signal to indicate the state of the ALU
-  typedef enum logic [2:0] {NO_REDUCTION, INTRA_LANE_REDUCTION, INTER_LANES_REDUCTION_RX, INTER_LANES_REDUCTION_TX, LN0_REDUCTION_COMMIT, SIMD_REDUCTION} alu_state_e;
+  typedef enum logic [2:0] {NO_REDUCTION, INTRA_LANE_REDUCTION, 
+    INTER_LANES_REDUCTION_RX, INTER_LANES_REDUCTION_TX, 
+    LN0_REDUCTION_COMMIT, SIMD_REDUCTION
+  } alu_state_e;
   alu_state_e alu_state_d, alu_state_q;
 
   // Reductions commit by zeroing the commit counter
@@ -782,7 +793,10 @@ module valu import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::idx_width;
         // Initialize reduction-related sequential elements
         first_op_d              = 1'b1;
         reduction_rx_cnt_d      = reduction_rx_cnt_init(NrLanes, lane_id_i);
-        sldu_transactions_cnt_d = $clog2(NrLanes) + 1;
+        if (lane_id_i == NrLanes-1)
+            reduction_rx_cnt_d += reduction_rx_cnt_init(max_cluster_id, cluster_id_i); // Inter cluster
+        // sldu_transactions_cnt_d = $clog2(NrLanes) + 1;
+        sldu_transactions_cnt_d = $clog2(NrLanes) + reduction_rx_cnt_init(max_cluster_id, cluster_id_i) + 1;
 
         alu_state_d = INTRA_LANE_REDUCTION;
       end else begin
@@ -810,7 +824,10 @@ module valu import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::idx_width;
         // Initialize reduction-related sequential elements
         first_op_d              = 1'b1;
         reduction_rx_cnt_d      = reduction_rx_cnt_init(NrLanes, lane_id_i);
-        sldu_transactions_cnt_d = $clog2(NrLanes) + 1;
+        if (lane_id_i == NrLanes-1)
+            reduction_rx_cnt_d += reduction_rx_cnt_init(max_cluster_id, cluster_id_i); // Inter cluster
+        // sldu_transactions_cnt_d = $clog2(NrLanes) + 1;
+        sldu_transactions_cnt_d = $clog2(NrLanes) + reduction_rx_cnt_init(max_cluster_id, cluster_id_i) + 1;
 
         issue_cnt_d = vfu_operation_i.vl;
         if (!(vfu_operation_i.op inside {[VMANDNOT:VMXNOR]}))
diff --git a/hardware/src/lane/vector_fus_stage.sv b/hardware/src/lane/vector_fus_stage.sv
index d99f979..ffcf6dd 100644
--- a/hardware/src/lane/vector_fus_stage.sv
+++ b/hardware/src/lane/vector_fus_stage.sv
@@ -107,6 +107,8 @@ module vector_fus_stage import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg
     .clk_i                (clk_i                          ),
     .rst_ni               (rst_ni                         ),
     .lane_id_i            (lane_id_i                      ),
+    .cluster_id_i         (cluster_id_i                    ),
+    .num_clusters_i       (num_clusters_i                  ),
     // Interface with Dispatcher
     .vxsat_flag_o         (alu_vxsat                      ),
     .alu_vxrm_i           (alu_vxrm_i                     ),
diff --git a/hardware/src/sldu/sldu.sv b/hardware/src/sldu/sldu.sv
index 04e4219..7d3e444 100644
--- a/hardware/src/sldu/sldu.sv
+++ b/hardware/src/sldu/sldu.sv
@@ -1422,6 +1422,9 @@ module sldu import ara_pkg::*; import rvv_pkg::*; #(
     if (!vinsn_queue_full && pe_req_valid_i && !vinsn_running_q[pe_req_i.id] &&
       (pe_req_i.vfu == VFU_SlideUnit || pe_req_i.op inside {[VREDSUM:VWREDSUM], [VFREDUSUM:VFWREDOSUM]})) begin
       vinsn_queue_d.vinsn[vinsn_queue_q.accept_pnt] = pe_req_i;
+      // if ((pe_req_i.op inside {[VREDSUM:VWREDSUM], [VFREDUSUM:VFWREDOSUM]}) && (pe_req_i.vl < NrLanes)) begin
+      //   vinsn_queue_d.vinsn[vinsn_queue_q.accept_pnt].vl = NrLanes;
+      // end
       vinsn_running_d[pe_req_i.id]                  = 1'b1;
 
       // Calculate the slide offset inside the vector register
diff --git a/hardware/src/vlsu/align_stage.sv b/hardware/src/vlsu/align_stage.sv
index ad5a59d..4c7708c 100644
--- a/hardware/src/vlsu/align_stage.sv
+++ b/hardware/src/vlsu/align_stage.sv
@@ -9,6 +9,7 @@
 // This means the alignment in the Load store unit can be removed.
 
 module align_stage import ara_pkg::*; import rvv_pkg::*;  #(
+  parameter  int           unsigned NrLanes             = 0,  // Number of parallel vector lanes.
   parameter  int           unsigned NrClusters          = 0,
   parameter  int           unsigned AxiDataWidth        = 0,
   parameter  int           unsigned AxiAddrWidth        = 0,
@@ -43,6 +44,7 @@ vlen_cl_t vl, vl_d, vl_q;
 vtype_t vtype;
 
 global_dispatcher #(
+  .NrLanes      (NrLanes   ),
   .NrClusters   (NrClusters),
   .vlen_cl_t    (vlen_cl_t )
 ) i_global_dispatcher (
@@ -291,6 +293,9 @@ always_comb begin
       if (be_final_d != '1) begin
         // For unaligned data, this is the last packet.
         axi_resp_o.r.last = 1'b1;
+        if (!data_prev_valid_q) begin
+          axi_resp_o.r_valid  = 1'b1;
+        end
         data_prev_d       = '0;
         data_prev_valid_d = 1'b0;
       end else begin
diff --git a/hardware/src/vlsu/global_dispatcher.sv b/hardware/src/vlsu/global_dispatcher.sv
index 82f1e38..e4bb34b 100644
--- a/hardware/src/vlsu/global_dispatcher.sv
+++ b/hardware/src/vlsu/global_dispatcher.sv
@@ -9,6 +9,7 @@
 // vl and vtype of the current configuration for LdSt requests.
 
 module global_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
+    parameter int unsigned NrLanes    = 0,  // Number of parallel vector lanes.
     parameter int unsigned NrClusters = 0,
     parameter type         vlen_cl_t  = logic
 )
@@ -108,8 +109,16 @@ module global_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
                                 vl_d = vlmax;
                             end else begin
                                 // Normal stripmining
-                                vl_d = ((|acc_req_i.rs1[$bits(acc_req_i.rs1)-1:$bits(vl_d)]) ||
-                                    (vlen_t'(acc_req_i.rs1) > vlmax)) ? vlmax : vlen_t'(acc_req_i.rs1);
+                                // vl_d = ((|acc_req_i.rs1[$bits(acc_req_i.rs1)-1:$bits(vl_d)]) ||
+                                //     (vlen_t'(acc_req_i.rs1) > vlmax)) ? vlmax : vlen_t'(acc_req_i.rs1);
+                                if (((|acc_req_i.rs1[$bits(acc_req_i.rs1)-1:$bits(vl_d)]) ||
+                                    (vlen_t'(acc_req_i.rs1) > vlmax))) begin
+                                    vl_d = vlmax;
+                                end else if (vlen_t'(acc_req_i.rs1) < NrClusters * NrLanes) begin
+                                    vl_d = NrClusters * NrLanes;
+                                end else begin
+                                    vl_d = vlen_t'(acc_req_i.rs1);
+                                end
                             end
                         end
                     end
diff --git a/hardware/src/vlsu/global_ldst.sv b/hardware/src/vlsu/global_ldst.sv
index 8d2d2c2..58b920f 100644
--- a/hardware/src/vlsu/global_ldst.sv
+++ b/hardware/src/vlsu/global_ldst.sv
@@ -46,6 +46,7 @@ vlen_cl_t vl;
 vtype_t vtype;
 
 global_dispatcher #(
+  .NrLanes      (NrLanes   ),
   .NrClusters   (NrClusters),
   .vlen_cl_t    (vlen_cl_t )
 ) i_global_dispatcher (
diff --git a/hardware/src/vlsu/shuffle_stage.sv b/hardware/src/vlsu/shuffle_stage.sv
index c7be052..9f61521 100644
--- a/hardware/src/vlsu/shuffle_stage.sv
+++ b/hardware/src/vlsu/shuffle_stage.sv
@@ -47,6 +47,7 @@ vlen_cl_t vl, vl_d, vl_q;
 vtype_t vtype;
 
 global_dispatcher #(
+  .NrLanes      (NrLanes   ),
   .NrClusters   (NrClusters),
   .vlen_cl_t    (vlen_cl_t )
 ) i_global_dispatcher (

From 3890099b58bcd8755e114585185850eab45c7e74 Mon Sep 17 00:00:00 2001
From: Hong Pang <hopang@larain5.ee.ethz.ch>
Date: Fri, 10 Oct 2025 20:08:49 +0200
Subject: [PATCH 02/37] [HW] 1. Fix sldu issue on reduction: align transaction
 number among clusters; 2. Fix valu issue on reduction: return back to
 NO_REDUCTION state when finish reduction, reduction operation should only
 start when the previous reduction is finished; 3. Update addrgen and vldu
 module to the newest released Ara version and adapt to support GLSU
 interaction; 4. (WIP)Adapt vl length for vector load to NrLanes*NrClusters as
 smallest number to support short vector load (TODO: GLSU may not need to be
 adjusted); 5. Fix shuffle stage resp issue: take control signal from the last
 stage instead of the first stage

---
 apps/dotproduct/main.c                 |  154 ++--
 apps/fdotproduct/main.c                |  114 +--
 hardware/include/ara_pkg.sv            |    1 +
 hardware/src/ara_dispatcher.sv         |   33 +-
 hardware/src/lane/valu.sv              |   29 +-
 hardware/src/lane/vmfpu.sv             |    3 +-
 hardware/src/sldu/sldu.sv              |    9 +-
 hardware/src/vlsu/addrgen.sv           | 1053 +++++++++++++++++++-----
 hardware/src/vlsu/global_dispatcher.sv |    8 +-
 hardware/src/vlsu/shuffle_stage.sv     |    9 +-
 hardware/src/vlsu/vldu.sv              |  381 ++++++---
 11 files changed, 1295 insertions(+), 499 deletions(-)

diff --git a/apps/dotproduct/main.c b/apps/dotproduct/main.c
index d6a5965..e3d7988 100644
--- a/apps/dotproduct/main.c
+++ b/apps/dotproduct/main.c
@@ -62,8 +62,8 @@ int main() {
 
   int64_t runtime_s, runtime_v;
 
-  // for (uint64_t avl = 32; avl <= (vsize >> 3); avl *= 2) {
-  for (uint64_t avl = (vsize >> 3); avl >=8; avl /= 2) {
+  for (uint64_t avl = 8; avl <= (vsize); avl *= 2) {
+  // for (uint64_t avl = (vsize >> 3); avl >=8; avl /= 2) {
   // uint64_t avl = 4;
     // Dotp
     printf("Calulating 64b dotp with vectors with length = %lu\n", avl);
@@ -89,81 +89,81 @@ int main() {
     }
   }
 
-  // for (uint64_t avl = 8; avl <= (vsize >> 2); avl *= 8) {
-  //   // Dotp
-  //   // uint64_t avl = 4;
-  //   printf("Calulating 32b dotp with vectors with length = %lu\n", avl);
-  //   start_timer();
-  //   res32_v = dotp_v32b(v32a, v32b, avl);
-  //   stop_timer();
-  //   runtime_v = get_timer();
-  //   printf("Vector runtime: %ld\n", runtime_v);
-
-  //   if (SCALAR) {
-  //     start_timer();
-  //     res32_s = dotp_s32b(v32a, v32b, avl);
-  //     stop_timer();
-  //     runtime_s = get_timer();
-  //     printf("Scalar runtime: %ld\n", runtime_s);
-
-  //     if (CHECK) {
-  //       if (res32_v != res32_s) {
-  //         printf("Error: v = %ld, g = %ld\n", res32_v, res32_s);
-  //         return -1;
-  //       }
-  //     }
-  //   }
-  // }
-
-  // for (uint64_t avl = 8; avl <= (vsize >> 1); avl *= 8) {
-  //   // Dotp
-  //   printf("Calulating 16b dotp with vectors with length = %lu\n", avl);
-  //   start_timer();
-  //   res16_v = dotp_v16b(v16a, v16b, avl);
-  //   stop_timer();
-  //   runtime_v = get_timer();
-  //   printf("Vector runtime: %ld\n", runtime_v);
-
-  //   if (SCALAR) {
-  //     start_timer();
-  //     res16_s = dotp_s16b(v16a, v16b, avl);
-  //     stop_timer();
-  //     runtime_s = get_timer();
-  //     printf("Scalar runtime: %ld\n", runtime_s);
-
-  //     if (CHECK) {
-  //       if (res16_v != res16_s) {
-  //         printf("Error: v = %ld, g = %ld\n", res16_v, res16_s);
-  //         return -1;
-  //       }
-  //     }
-  //   }
-  // }
-
-  // for (uint64_t avl = 8; avl <= (vsize >> 0); avl *= 8) {
-  //   // Dotp
-  //   printf("Calulating 8b dotp with vectors with length = %lu\n", avl);
-  //   start_timer();
-  //   res8_v = dotp_v8b(v8a, v8b, avl);
-  //   stop_timer();
-  //   runtime_v = get_timer();
-  //   printf("Vector runtime: %ld\n", runtime_v);
-
-  //   if (SCALAR) {
-  //     start_timer();
-  //     res8_s = dotp_s8b(v8a, v8b, avl);
-  //     stop_timer();
-  //     runtime_s = get_timer();
-  //     printf("Scalar runtime: %ld\n", runtime_s);
-
-  //     if (CHECK) {
-  //       if (res8_v != res8_s) {
-  //         printf("Error: v = %ld, g = %ld\n", res8_v, res8_s);
-  //         return -1;
-  //       }
-  //     }
-  //   }
-  // }
+  for (uint64_t avl = 8; avl <= (vsize); avl *= 2) {
+    // Dotp
+    // uint64_t avl = 4;
+    printf("Calulating 32b dotp with vectors with length = %lu\n", avl);
+    start_timer();
+    res32_v = dotp_v32b(v32a, v32b, avl);
+    stop_timer();
+    runtime_v = get_timer();
+    printf("Vector runtime: %ld\n", runtime_v);
+
+    if (SCALAR) {
+      start_timer();
+      res32_s = dotp_s32b(v32a, v32b, avl);
+      stop_timer();
+      runtime_s = get_timer();
+      printf("Scalar runtime: %ld\n", runtime_s);
+
+      if (CHECK) {
+        if (res32_v != res32_s) {
+          printf("Error: v = %ld, g = %ld\n", res32_v, res32_s);
+          return -1;
+        }
+      }
+    }
+  }
+
+  for (uint64_t avl = 8; avl <= (vsize); avl *= 2) {
+    // Dotp
+    printf("Calulating 16b dotp with vectors with length = %lu\n", avl);
+    start_timer();
+    res16_v = dotp_v16b(v16a, v16b, avl);
+    stop_timer();
+    runtime_v = get_timer();
+    printf("Vector runtime: %ld\n", runtime_v);
+
+    if (SCALAR) {
+      start_timer();
+      res16_s = dotp_s16b(v16a, v16b, avl);
+      stop_timer();
+      runtime_s = get_timer();
+      printf("Scalar runtime: %ld\n", runtime_s);
+
+      if (CHECK) {
+        if (res16_v != res16_s) {
+          printf("Error: v = %ld, g = %ld\n", res16_v, res16_s);
+          return -1;
+        }
+      }
+    }
+  }
+
+  for (uint64_t avl = 8; avl <= (vsize); avl *= 2) {
+    // Dotp
+    printf("Calulating 8b dotp with vectors with length = %lu\n", avl);
+    start_timer();
+    res8_v = dotp_v8b(v8a, v8b, avl);
+    stop_timer();
+    runtime_v = get_timer();
+    printf("Vector runtime: %ld\n", runtime_v);
+
+    if (SCALAR) {
+      start_timer();
+      res8_s = dotp_s8b(v8a, v8b, avl);
+      stop_timer();
+      runtime_s = get_timer();
+      printf("Scalar runtime: %ld\n", runtime_s);
+
+      if (CHECK) {
+        if (res8_v != res8_s) {
+          printf("Error: v = %ld, g = %ld\n", res8_v, res8_s);
+          return -1;
+        }
+      }
+    }
+  }
 
   printf("SUCCESS.\n");
 
diff --git a/apps/fdotproduct/main.c b/apps/fdotproduct/main.c
index 55bf647..dea7770 100644
--- a/apps/fdotproduct/main.c
+++ b/apps/fdotproduct/main.c
@@ -32,7 +32,7 @@
 
 // Threshold for FP comparisons
 #define THRESHOLD_64b 0.0000000001
-#define THRESHOLD_32b 0.0001
+#define THRESHOLD_32b 0.01
 #define THRESHOLD_16b 1
 
 // Run also the scalar benchmark
@@ -72,10 +72,8 @@ int main() {
 
   uint64_t runtime_s, runtime_v;
 
-  // for (uint64_t avl = 32; avl <= (vsize >> 3); avl *= 2) {
-  for (uint64_t avl = (vsize >> 3); avl >= 8; avl /= 2) {
+  for (uint64_t avl = 8; avl <= (vsize); avl *= 2) {
     // uint64_t avl = vsize >> 3;
-    // uint64_t avl = 4;
     printf("Calulating 64b dotp with vectors with length = %lu\n", avl);
     start_timer();
     res64_v = fdotp_v64b(v64a, v64b, avl);
@@ -103,77 +101,83 @@ int main() {
   }
 
 
-  // for (uint64_t avl = 16; avl <= (vsize); avl *= 2) {
-  // for (uint64_t avl = 32; avl <= 32; avl *= 2) {
-    // uint64_t avl=4;
-    // printf("Calulating 32b dotp with vectors with length = %lu\n", avl);
+  for (uint64_t avl = 8; avl <= (vsize); avl *= 2) {
+  // for (uint64_t avl = vsize; avl <= (vsize); avl *= 2) {
     // start_timer();
-    // res32_v = fdotp_v32b(v32a, v32b, avl);
+    // res32_s = fdotp_s32b(v32a, v32b, avl);
     // stop_timer();
-    // runtime_v = get_timer();
-    // printf("Vector runtime: %ld\n", runtime_v);
-
-    // if (SCALAR) {
-    //   start_timer();
-    //   res32_s = fdotp_s32b(v32a, v32b, avl);
-    //   stop_timer();
-    //   runtime_s = get_timer();
-    //   printf("Scalar runtime: %ld\n", runtime_s);
-    // }
-
-    // if (CHECK) {
-    //   if (SCALAR) {
-    //     printf("Checking results: v = %f, s = %f\n", res32_v, res32_s);
-    //     if (!similarity_check_32b(res32_v, res32_s, THRESHOLD_32b)) {
-    //       printf("Error: v = %f, s = %f\n", res32_v, res32_s);
-    //       return -1;
-    //     }
-    //   }
-    // }
+    // runtime_s = get_timer();
+    // printf("Scalar runtime: %ld\n, result: %f\n", runtime_s, res32_s);
 
-    // // Dotproduct Arithmetic intensity calculation
-    // // Ops = 2N FP32 ops 
-    // // Bytes = 2N * 4B = 8N Bytes , AI = 1/4 FP32 Op/B
-    // // BW = 32N bits/ cycle = 4N Bytes
-    // // Max Perf = N * 2 * 2 FP32op/cycle = 4N FP32 op/cycle
-    // // From roofline max perf at the arithmetic intensity = N FP32 op/cycle
-    // float performance = avl * 1.0 / runtime_v;
-    // float utilization = 100.0 * performance / (NR_LANES * NR_CLUSTERS);
-    // printf("The execution took %d cycles.\n", runtime_v);
-    // printf("The performance is %f FLOP/cycle (%f%% utilization).\n",
-    //        performance, utilization);
-  // }
-  
-  /*
-  for (uint64_t avl = 8; avl <= (vsize >> 2); avl *= 8) {
-    // Dotp
-    printf("Calulating 16b dotp with vectors with length = %lu\n", avl);
+    printf("Calulating 32b dotp with vectors with length = %lu\n", avl);
     start_timer();
-    res16_v = fdotp_v16b(v16a, v16b, avl);
+    res32_v = fdotp_v32b(v32a, v32b, avl);
+    printf("Finished!\n");
     stop_timer();
     runtime_v = get_timer();
     printf("Vector runtime: %ld\n", runtime_v);
 
     if (SCALAR) {
       start_timer();
-      res16_s = fdotp_s16b(v16a, v16b, avl);
+      res32_s = fdotp_s32b(v32a, v32b, avl);
       stop_timer();
       runtime_s = get_timer();
-      printf("Scalar runtime: %ld\n", runtime_s);
+      printf("Scalar runtime: %ld\n, result: %f\n", runtime_s, res32_s);
     }
 
     if (CHECK) {
       if (SCALAR) {
-        printf("Checking results: v = %x, s = %x\n", *((uint16_t *)&res16_v),
-               *((uint16_t *)&res16_s));
-        if (!similarity_check(res16_v, res16_s, THRESHOLD_16b)) {
-          printf("Error: v = %x, s = %x\n", *((uint16_t *)&res16_v),
-                 *((uint16_t *)&res16_s));
+        printf("Checking results: v = %f, s = %f\n", res32_v, res32_s);
+        if (!similarity_check_32b(res32_v, res32_s, THRESHOLD_32b)) {
+          printf("Error: v = %f, s = %f\n", res32_v, res32_s);
           return -1;
         }
       }
     }
-  }*/
+
+    // // Dotproduct Arithmetic intensity calculation
+    // // Ops = 2N FP32 ops 
+    // // Bytes = 2N * 4B = 8N Bytes , AI = 1/4 FP32 Op/B
+    // // BW = 32N bits/ cycle = 4N Bytes
+    // // Max Perf = N * 2 * 2 FP32op/cycle = 4N FP32 op/cycle
+    // // From roofline max perf at the arithmetic intensity = N FP32 op/cycle
+    // float performance = avl * 1.0 / runtime_v;
+    // float utilization = 100.0 * performance / (NR_LANES * NR_CLUSTERS);
+    // printf("The execution took %d cycles.\n", runtime_v);
+    // printf("The performance is %f FLOP/cycle (%f%% utilization).\n",
+    //        performance, utilization);
+  }
+  
+
+  // for (uint64_t avl = 8; avl <= (vsize); avl *= 8) {
+  //   // Dotp
+  //   printf("Calulating 16b dotp with vectors with length = %lu\n", avl);
+  //   start_timer();
+  //   res16_v = fdotp_v16b(v16a, v16b, avl);
+  //   stop_timer();
+  //   runtime_v = get_timer();
+  //   printf("Vector runtime: %ld\n", runtime_v);
+
+  //   if (SCALAR) {
+  //     start_timer();
+  //     res16_s = fdotp_s16b(v16a, v16b, avl);
+  //     stop_timer();
+  //     runtime_s = get_timer();
+  //     printf("Scalar runtime: %ld\n", runtime_s);
+  //   }
+
+  //   if (CHECK) {
+  //     if (SCALAR) {
+  //       printf("Checking results: v = %x, s = %x\n", *((uint16_t *)&res16_v),
+  //              *((uint16_t *)&res16_s));
+  //       if (!similarity_check(res16_v, res16_s, THRESHOLD_16b)) {
+  //         printf("Error: v = %x, s = %x\n", *((uint16_t *)&res16_v),
+  //                *((uint16_t *)&res16_s));
+  //         return -1;
+  //       }
+  //     }
+  //   }
+  // }
 
   printf("SUCCESS.\n");
 
diff --git a/hardware/include/ara_pkg.sv b/hardware/include/ara_pkg.sv
index 1bbacfc..ead2dc7 100644
--- a/hardware/include/ara_pkg.sv
+++ b/hardware/include/ara_pkg.sv
@@ -32,6 +32,7 @@ package ara_pkg;
   
   // Maximum number of clusters that Ara can support.
   localparam int unsigned MaxNrClusters = 32;
+  // localparam int unsigned NrClusters    = 4;
   typedef logic [$clog2(MaxNrClusters)-1:0] id_cluster_t;
   typedef logic [$clog2(MaxNrLanes)-1:0] id_lane_t;
   typedef logic [cf_math_pkg::idx_width($clog2(MaxNrClusters))-1:0] num_cluster_t;
diff --git a/hardware/src/ara_dispatcher.sv b/hardware/src/ara_dispatcher.sv
index a10924f..1d331f8 100644
--- a/hardware/src/ara_dispatcher.sv
+++ b/hardware/src/ara_dispatcher.sv
@@ -58,13 +58,15 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
   ////////////
 
   vlen_t  vstart_d, vstart_q;
-  vlen_t  vl_d, vl_q;
+  vlen_t  vl_d, vl_q, vl_max_check;
+  vlen_t  vl_ld_d, vl_ld_q;
   vtype_t vtype_d, vtype_q;
   vxsat_e vxsat_d, vxsat_q;
   vxrm_t  vxrm_d, vxrm_q;
 
   `FF(vstart_q, vstart_d, '0)
   `FF(vl_q, vl_d, '0)
+  `FF(vl_ld_q, vl_ld_d, '0)
   `FF(vtype_q, vtype_d, '{vill: 1'b1, default: '0})
   `FF(vxsat_q, vxsat_d, '0)
   `FF(vxrm_q, vxrm_d, '0)
@@ -254,6 +256,7 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
     // Default values
     vstart_d     = vstart_q;
     vl_d         = vl_q;
+    vl_ld_d      = vl_ld_q;
     vtype_d      = vtype_q;
     state_d      = state_q;
     eew_d        = eew_q;
@@ -502,6 +505,8 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
                     default:;
                   endcase
 
+                  vl_max_check = vlmax;
+
                   if (insn.vsetivli_type.func2 == 2'b11) begin // vsetivli
                     vl_d = vlen_t'(insn.vsetivli_type.uimm5) >> num_clusters_i;
                     acc_resp_o.result = vl_d << num_clusters_i;
@@ -526,20 +531,25 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
                         acc_resp_o.result = vl_d << num_clusters_i;
                       end else begin
                         if (cluster_id_i < total_cluster_pieces[$clog2(NrClusters) - 1 : 0]) begin
-                          // vl_d = (total_cluster_pieces >> $clog2(NrClusters) + 1) * (VLENB >> vtype_d.vsew);
                           vl_d = ((total_cluster_pieces >> $clog2(NrClusters)) + 1) * NrLanes;
                         end else if (cluster_id_i == total_cluster_pieces[$clog2(NrClusters) - 1 : 0]) begin
-                          // vl_d = (total_cluster_pieces >> $clog2(NrClusters)) * (VLENB >> vtype_d.vsew) + 
-                          //         acc_req_i.rs1 % (VLENB >> vtype_d.vsew);
                           vl_d = (total_cluster_pieces >> $clog2(NrClusters)) * NrLanes + 
                                   acc_req_i.rs1 % NrLanes;
                         end else begin
-                          // vl_d = (total_cluster_pieces >> $clog2(NrClusters)) * (VLENB >> vtype_d.vsew);
                           vl_d = (total_cluster_pieces >> $clog2(NrClusters)) * NrLanes;
                         end
                         // Return the new vl
                         acc_resp_o.result = vlen_t'(acc_req_i.rs1);
                       end
+                      // vector length for load instruction (need to be align with GLSU)
+                      if (((|acc_req_i.rs1[$bits(acc_req_i.rs1)-1:$bits(vl_d)]) ||
+                          ((acc_req_i.rs1 >> num_clusters_i) > vlmax))) begin
+                          vl_ld_d = vlmax;
+                      end else if (|acc_req_i.rs1[$clog2(NrClusters * NrLanes)-1:0]) begin
+                          vl_ld_d = vlen_t'((((acc_req_i.rs1 >> $clog2(NrClusters * NrLanes)) + 1) << $clog2(NrClusters * NrLanes)) >> $clog2(NrClusters));
+                      end else begin
+                          vl_ld_d = vlen_t'(acc_req_i.rs1 >> $clog2(NrClusters));
+                      end
                     end
                   end
                 end
@@ -2550,6 +2560,7 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
             acc_resp_o.req_ready = 1'b0;
 
             // These generate a request to Ara's backend
+            ara_req_d.vl        = vl_ld_q;
             ara_req_d.vd        = insn.vmem_type.rd;
             ara_req_d.use_vd    = 1'b1;
             ara_req_d.vm        = insn.vmem_type.vm;
@@ -2610,7 +2621,8 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
                   5'b01000:;      // Unit-strided, whole registers
                   5'b01011: begin // Unit-strided, mask load, EEW=1
                     // We operate ceil(vl/8) bytes
-                    ara_req_d.vl         = (vl_q >> 3) + |vl_q[2:0];
+                    // ara_req_d.vl         = (vl_q >> 3) + |vl_q[2:0];
+                    ara_req_d.vl         = (vl_ld_q >> 3) + |vl_ld_q[2:0];
                     ara_req_d.vtype.vsew = EW8;
                   end
                   5'b10000: begin // Unit-strided, fault-only first
@@ -2762,6 +2774,7 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
             ara_req_d.scale_vl = 1'b1;
 
             // These generate a request to Ara's backend
+            ara_req_d.vl        = vl_q;
             ara_req_d.vs1       = insn.vmem_type.rd; // vs3 is encoded in the same position as rd
             ara_req_d.use_vs1   = 1'b1;
             ara_req_d.eew_vs1   = eew_q[insn.vmem_type.rd]; // This is the vs1 EEW
@@ -3243,8 +3256,8 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
 
     // Any valid non-config instruction is a NOP if vl == 0, with some exceptions,
     // e.g. whole vector memory operations / whole vector register move
-    if (is_decoding && (vl_q == '0 || null_vslideup) && !is_config && 
-      !(ara_req_d.op inside {[VREDSUM:VWREDSUM], [VFREDUSUM:VFWREDOSUM]}) &&
+    if (is_decoding && (((vl_q == '0 && (!(ara_req_d.op inside {[VLE:VSXE]}))) || 
+      (vl_ld_q == '0 && (ara_req_d.op inside {[VLE:VSXE]}))) || null_vslideup) && !is_config &&
       !ignore_zero_vl_check && !acc_resp_o.error) begin
       // If we are acknowledging a memory operation, we must tell Ariane that the memory
       // operation was resolved (to decrement its pending load/store counter)
@@ -3252,7 +3265,9 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
       // delay the zero_vl acknowledge by 1 cycle
       acc_resp_o.req_ready  = ~((is_vload & load_complete_q) | (is_vstore & store_complete_q));
       acc_resp_o.resp_valid = ~((is_vload & load_complete_q) | (is_vstore & store_complete_q));
-      ara_req_valid_d  = 1'b0;
+      if (!(ara_req_d.op inside {[VREDSUM:VWREDSUM], [VFREDUSUM:VFWREDOSUM]})) begin
+        ara_req_valid_d  = 1'b0;
+      end
       load_zero_vl     = is_vload;
       store_zero_vl    = is_vstore;
     end
diff --git a/hardware/src/lane/valu.sv b/hardware/src/lane/valu.sv
index 8c2d210..37eb808 100644
--- a/hardware/src/lane/valu.sv
+++ b/hardware/src/lane/valu.sv
@@ -674,6 +674,8 @@ module valu import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::idx_width;
             end
           end
 
+          alu_state_d = NO_REDUCTION;
+
           // Give the done to the main sequencer
           commit_cnt_d = '0;
         end
@@ -692,6 +694,7 @@ module valu import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::idx_width;
               simd_red_cnt_d = simd_red_cnt_q + 1;
               result_queue_d[result_queue_write_pnt_q].wdata = valu_result;
             end else begin
+              alu_state_d = NO_REDUCTION;
               // Bump issue counter and pointers
               vinsn_queue_d.issue_cnt -= 1;
               if (vinsn_queue_q.issue_pnt == VInsnQueueDepth-1)
@@ -789,18 +792,20 @@ module valu import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::idx_width;
 
       // Initialize counters and alu state if needed by the next instruction
       // After a reduction, the next instructions starts after the reduction commits
-      if (is_reduction(vinsn_queue_q.vinsn[vinsn_queue_d.issue_pnt].op) && (vinsn_queue_d.issue_cnt != '0)) begin
-        // Initialize reduction-related sequential elements
-        first_op_d              = 1'b1;
-        reduction_rx_cnt_d      = reduction_rx_cnt_init(NrLanes, lane_id_i);
-        if (lane_id_i == NrLanes-1)
-            reduction_rx_cnt_d += reduction_rx_cnt_init(max_cluster_id, cluster_id_i); // Inter cluster
-        // sldu_transactions_cnt_d = $clog2(NrLanes) + 1;
-        sldu_transactions_cnt_d = $clog2(NrLanes) + reduction_rx_cnt_init(max_cluster_id, cluster_id_i) + 1;
-
-        alu_state_d = INTRA_LANE_REDUCTION;
-      end else begin
-        alu_state_d = NO_REDUCTION;
+      if (alu_state_q == NO_REDUCTION) begin
+        if (is_reduction(vinsn_queue_q.vinsn[vinsn_queue_d.issue_pnt].op) && (vinsn_queue_d.issue_cnt != '0)) begin
+          // Initialize reduction-related sequential elements
+          first_op_d              = 1'b1;
+          reduction_rx_cnt_d      = reduction_rx_cnt_init(NrLanes, lane_id_i);
+          if (lane_id_i == NrLanes-1)
+              reduction_rx_cnt_d += reduction_rx_cnt_init(max_cluster_id, cluster_id_i); // Inter cluster
+          // sldu_transactions_cnt_d = $clog2(NrLanes) + 1;
+          sldu_transactions_cnt_d = $clog2(NrLanes) + reduction_rx_cnt_init(max_cluster_id, cluster_id_i) + 1;
+          
+          alu_state_d = INTRA_LANE_REDUCTION;
+        end else begin
+          alu_state_d = NO_REDUCTION;
+        end
       end
     end
 
diff --git a/hardware/src/lane/vmfpu.sv b/hardware/src/lane/vmfpu.sv
index 1e2f49e..fc1886f 100644
--- a/hardware/src/lane/vmfpu.sv
+++ b/hardware/src/lane/vmfpu.sv
@@ -594,7 +594,8 @@ module vmfpu import ara_pkg::*; import rvv_pkg::*; import fpnew_pkg::*;
   logic prevent_commit;
 
   // Count how many transactions we must do in total to complete the reduction operation
-  logic [idx_width($clog2(NrLanes)+1):0] sldu_transactions_cnt_d, sldu_transactions_cnt_q;
+  // logic [idx_width($clog2(NrLanes)+1):0] sldu_transactions_cnt_d, sldu_transactions_cnt_q;
+  logic [idx_width(NrLanes*MaxNrClusters/2):0] sldu_transactions_cnt_d, sldu_transactions_cnt_q;
 
   // Handshake synchronizer
   // Since the SLDU must receive a valid signals also from lanes that should not send anything,
diff --git a/hardware/src/sldu/sldu.sv b/hardware/src/sldu/sldu.sv
index 7d3e444..75414e7 100644
--- a/hardware/src/sldu/sldu.sv
+++ b/hardware/src/sldu/sldu.sv
@@ -1135,7 +1135,7 @@ module sldu import ara_pkg::*; import rvv_pkg::*; #(
     slide_data_accepted = '0;
     for (int lane = 0; lane < NrLanes; lane++) begin: result_write
       sldu_result_req_o[lane]   = result_queue_valid_q[result_queue_read_pnt_q][lane] & (~(vinsn_commit.vfu inside {VFU_Alu, VFU_MFpu}));
-      sldu_red_valid_o[lane]    = result_queue_valid_q[result_queue_read_pnt_q][lane] & (vinsn_commit.vfu inside {VFU_Alu, VFU_MFpu});
+      sldu_red_valid_o[lane]    = result_queue_valid_q[result_queue_read_pnt_q][lane] & vinsn_commit_valid & (vinsn_commit.vfu inside {VFU_Alu, VFU_MFpu});
       sldu_result_addr_o[lane]  = result_queue_q[result_queue_read_pnt_q][lane].addr;
       sldu_result_id_o[lane]    = result_queue_q[result_queue_read_pnt_q][lane].id;
       sldu_result_wdata_o[lane] = result_queue_q[result_queue_read_pnt_q][lane].wdata;
@@ -1160,7 +1160,7 @@ module sldu import ara_pkg::*; import rvv_pkg::*; #(
     // If this is a reduction, no need for the final grants
     // if (!(|result_queue_valid_d[result_queue_read_pnt_q]) &&
     //   (vinsn_commit.vfu inside {VFU_Alu, VFU_MFpu} || (&result_final_gnt_d || commit_cnt_q > (NrLanes * 8))))
-    if (|slide_data_accepted && (vinsn_commit.vfu inside {VFU_Alu, VFU_MFpu} || (&result_final_gnt_d || commit_cnt_q >= (NrLanes * 8))))
+    if (|slide_data_accepted && ((vinsn_commit.vfu inside {VFU_Alu, VFU_MFpu}) || (&result_final_gnt_d || commit_cnt_q >= (NrLanes * 8))))
       // There is something waiting to be written
       if (!result_queue_empty) begin
         if (!vinsn_commit.is_stride_np2) // if (state_q != SLIDE_NP2_SETUP)
@@ -1205,7 +1205,7 @@ module sldu import ara_pkg::*; import rvv_pkg::*; #(
         // Add packets for inter cluster reduction
         if (vinsn_queue_q.vinsn[vinsn_queue_d.commit_pnt].vfu inside {VFU_Alu, VFU_MFpu}) begin
           // results to be committed after receiving from ring, cluster0 commits 1 additional packet for final result
-          commit_cnt_d += (NrLanes * (cluster_reduction_rx_cnt_init(cluster_id_i) - 1 + (cluster_id_i==0 ? 1 : 0))) << EW64;
+          commit_cnt_d += (NrLanes * (cluster_reduction_rx_cnt_init(cluster_id_i))) << EW64;
         end
 
         // Trim vector elements which are not written by the slide unit
@@ -1445,7 +1445,8 @@ module sldu import ara_pkg::*; import rvv_pkg::*; #(
         // Add packets for inter cluster reduction
         if (pe_req_i.vfu inside {VFU_Alu, VFU_MFpu}) begin
           // results to be committed after receiving from ring, cluster0 commits 1 additional packet for final result
-          commit_cnt_d += (NrLanes * (cluster_reduction_rx_cnt_init(cluster_id_i) - 1 + (cluster_id_i==0 ? 1 : 0))) << EW64;
+          // commit_cnt_d += (NrLanes * (cluster_reduction_rx_cnt_init(cluster_id_i) - 1 + (cluster_id_i==0 ? 1 : 0))) << EW64;
+          commit_cnt_d += (NrLanes * (cluster_reduction_rx_cnt_init(cluster_id_i))) << EW64;
         end
 
         // Trim vector elements which are not written by the slide unit
diff --git a/hardware/src/vlsu/addrgen.sv b/hardware/src/vlsu/addrgen.sv
index a862646..8112062 100644
--- a/hardware/src/vlsu/addrgen.sv
+++ b/hardware/src/vlsu/addrgen.sv
@@ -49,14 +49,37 @@ module addrgen import ara_pkg::*; import rvv_pkg::*; #(
     output logic                           addrgen_operand_ready_o
   );
 
+  localparam unsigned DataWidth = $bits(elen_t);
+  localparam unsigned DataWidthB = DataWidth / 8;
+
+  localparam unsigned Log2NrLanes = $clog2(NrLanes);
+  localparam unsigned Log2LaneWordWidthB = $clog2(DataWidthB/1);
+  localparam unsigned Log2LaneWordWidthH = $clog2(DataWidthB/2);
+  localparam unsigned Log2LaneWordWidthS = $clog2(DataWidthB/4);
+  localparam unsigned Log2LaneWordWidthD = $clog2(DataWidthB/8);
+  localparam unsigned Log2VRFWordWidthB = Log2NrLanes + Log2LaneWordWidthB;
+  localparam unsigned Log2VRFWordWidthH = Log2NrLanes + Log2LaneWordWidthH;
+  localparam unsigned Log2VRFWordWidthS = Log2NrLanes + Log2LaneWordWidthS;
+  localparam unsigned Log2VRFWordWidthD = Log2NrLanes + Log2LaneWordWidthD;
+
   import cf_math_pkg::idx_width;
   import axi_pkg::aligned_addr;
   import axi_pkg::BURST_INCR;
   import axi_pkg::CACHE_MODIFIABLE;
 
+  // // Check if the address is aligned to a particular width
+  // function automatic logic is_addr_error(axi_addr_t addr, vew_e vew);
+  //   is_addr_error = |(addr & (elen_t'(1 << vew) - 1));
+  // endfunction // is_addr_error
+
   // Check if the address is aligned to a particular width
-  function automatic logic is_addr_error(axi_addr_t addr, vew_e vew);
-    is_addr_error = |(addr & (elen_t'(1 << vew) - 1));
+  // Max element width: 8 bytes
+  function automatic logic is_addr_error(axi_addr_t addr, logic [1:0] vew);
+    // log2(MAX_ELEMENT_WIDTH_BYTE)
+    localparam LOG2_MAX_SEW_BYTE = 3;
+    typedef logic [LOG2_MAX_SEW_BYTE:0] max_sew_byte_t;
+
+    is_addr_error = |(max_sew_byte_t'(addr[LOG2_MAX_SEW_BYTE-1:0]) & (max_sew_byte_t'(1 << vew) - 1));
   endfunction // is_addr_error
 
   ////////////////////
@@ -69,9 +92,10 @@ module addrgen import ara_pkg::*; import rvv_pkg::*; #(
     axi_addr_t addr;
     vlen_t len;
     elen_t stride;
-    vew_e vew;
+    logic [1:0] vew;
     logic is_load;
     logic is_burst; // Unit-strided instructions can be converted into AXI INCR bursts
+    vlen_t vstart;
   } addrgen_req_t;
   addrgen_req_t addrgen_req;
   logic         addrgen_req_valid;
@@ -89,6 +113,9 @@ module addrgen import ara_pkg::*; import rvv_pkg::*; #(
   logic             axi_addrgen_queue_push;
   logic             axi_addrgen_queue_full;
   logic             axi_addrgen_queue_empty;
+  logic             axi_addrgen_queue_pop;
+
+  assign axi_addrgen_queue_pop = ldu_axi_addrgen_req_ready_i | stu_axi_addrgen_req_ready_i;
 
   fifo_v3 #(
     .DEPTH(VaddrgenInsnQueueDepth),
@@ -102,7 +129,7 @@ module addrgen import ara_pkg::*; import rvv_pkg::*; #(
     .push_i    (axi_addrgen_queue_push                                   ),
     .full_o    (axi_addrgen_queue_full                                   ),
     .data_o    (axi_addrgen_req_o                                        ),
-    .pop_i     (ldu_axi_addrgen_req_ready_i | stu_axi_addrgen_req_ready_i),
+    .pop_i     (axi_addrgen_queue_pop                                    ),
     .empty_o   (axi_addrgen_queue_empty                                  ),
     .usage_o   (/* Unused */                                             )
   );
@@ -149,6 +176,9 @@ module addrgen import ara_pkg::*; import rvv_pkg::*; #(
   //  Address generation  //
   //////////////////////////
 
+  vlen_t len_temp;
+  axi_addr_t next_addr_strided_temp;
+
   // Running vector instructions
   logic [NrVInsn-1:0] vinsn_running_d, vinsn_running_q;
 
@@ -165,10 +195,19 @@ module addrgen import ara_pkg::*; import rvv_pkg::*; #(
     ADDRGEN_IDX_OP_END
   } state_q, state_d;
 
+  axi_addr_t lookahead_addr_e_d, lookahead_addr_e_q;
+  axi_addr_t lookahead_addr_se_d, lookahead_addr_se_q;
+  vlen_t lookahead_len_d, lookahead_len_q;
+
+  logic [VLEN-1:0] vaddr_start;
+
   always_comb begin: addr_generation
     // Maintain state
     state_d  = state_q;
     pe_req_d = pe_req_q;
+    lookahead_addr_e_d  = lookahead_addr_e_q;
+    lookahead_addr_se_d = lookahead_addr_se_q;
+    lookahead_len_d     = lookahead_len_q;
 
     // Running vector instructions
     vinsn_running_d = vinsn_running_q & pe_vinsn_running_i;
@@ -216,71 +255,182 @@ module addrgen import ara_pkg::*; import rvv_pkg::*; #(
           // Store the PE request
           pe_req_d = pe_req_i;
 
+          // Pre-calculate expensive additions / multiplications
+          // pe_req_i shouldn't be that critical at this point
+          lookahead_addr_e_d  = pe_req_i.scalar_op + (pe_req_i.vstart << unsigned'(pe_req_i.vtype.vsew));
+          lookahead_addr_se_d = pe_req_i.scalar_op + (pe_req_i.vstart * pe_req_i.stride);
+          lookahead_len_d     = (pe_req_i.vl - pe_req_i.vstart) << unsigned'(pe_req_i.vtype.vsew[1:0]);
+
           case (pe_req_i.op)
             VLXE, VSXE: begin
               state_d = ADDRGEN_IDX_OP;
 
               // Load element pointers
               case (pe_req_i.eew_vs2)
-                EW8:  last_elm_subw_d = 7;
-                EW16: last_elm_subw_d = 3;
-                EW32: last_elm_subw_d = 1;
-                EW64: last_elm_subw_d = 0;
-                default:
+                EW8: begin
+                  last_elm_subw_d = 7;
+                  word_lane_ptr_d = pe_req_i.vstart[Log2VRFWordWidthB-1:Log2LaneWordWidthB];
+                  elm_ptr_d       = pe_req_i.vstart[Log2LaneWordWidthB-1:0];
+                end
+                EW16: begin
+                  last_elm_subw_d = 3;
+                  word_lane_ptr_d = pe_req_i.vstart[Log2VRFWordWidthH-1:Log2LaneWordWidthH];
+                  elm_ptr_d       = pe_req_i.vstart[Log2LaneWordWidthH-1:0];
+                end
+                EW32: begin
+                  last_elm_subw_d = 1;
+                  word_lane_ptr_d = pe_req_i.vstart[Log2VRFWordWidthS-1:Log2LaneWordWidthS];
+                  elm_ptr_d       = pe_req_i.vstart[Log2LaneWordWidthS-1:0];
+                end
+                default: begin // EW64
                   last_elm_subw_d = 0;
+                  word_lane_ptr_d = pe_req_i.vstart[Log2VRFWordWidthD-1:0];
+                  elm_ptr_d       = 0;
+                end
               endcase
 
               // Load element counter
-              idx_op_cnt_d = pe_req_i.vl;
+              idx_op_cnt_d = pe_req_i.vl - pe_req_i.vstart;
             end
             default: state_d = ADDRGEN;
           endcase
         end
       end
+      // IDLE: begin
+      //   // Received a new request
+      //   if (pe_req_valid_i &&
+      //       (is_load(pe_req_i.op) || is_store(pe_req_i.op)) && !vinsn_running_q[pe_req_i.id]) begin
+      //     // Mark the instruction as running in this unit
+      //     vinsn_running_d[pe_req_i.id] = 1'b1;
+
+      //     // Store the PE request
+      //     pe_req_d = pe_req_i;
+
+      //     case (pe_req_i.op)
+      //       VLXE, VSXE: begin
+      //         state_d = ADDRGEN_IDX_OP;
+
+      //         // Load element pointers
+      //         case (pe_req_i.eew_vs2)
+      //           EW8:  last_elm_subw_d = 7;
+      //           EW16: last_elm_subw_d = 3;
+      //           EW32: last_elm_subw_d = 1;
+      //           EW64: last_elm_subw_d = 0;
+      //           default:
+      //             last_elm_subw_d = 0;
+      //         endcase
+
+      //         // Load element counter
+      //         idx_op_cnt_d = pe_req_i.vl;
+      //       end
+      //       default: state_d = ADDRGEN;
+      //     endcase
+      //   end
+      // end
       ADDRGEN: begin
+        // NOTE: indexed are not covered here
+        case (pe_req_q.op)
+          // Unit-stride: address = base + (vstart in elements)
+          VLE,  VSE : vaddr_start = lookahead_addr_e_q;
+          // Strided: address = base + (vstart * stride)
+          VLSE, VSSE: vaddr_start = lookahead_addr_se_q;
+          // Indexed: let the next stage take care of vstart
+          VLXE, VSXE: vaddr_start = pe_req_q.scalar_op;
+          default   : vaddr_start = '0;
+        endcase // pe_req_q.op
+
+        // Start the computation already
+        addrgen_req = '{
+          addr    : vaddr_start,
+          len     : lookahead_len_q,
+          stride  : pe_req_q.stride,
+          vew     : pe_req_q.vtype.vsew[1:0],
+          is_load : is_load(pe_req_q.op),
+          // Unit-strided loads/stores trigger incremental AXI bursts.
+          is_burst: (pe_req_q.op inside {VLE, VSE}),
+          vstart  : pe_req_q.vstart
+        };
+
         // Ara does not support misaligned AXI requests
-        if (is_addr_error(pe_req_q.scalar_op, pe_req_q.vtype.vsew)) begin
+        if (is_addr_error(pe_req_q.scalar_op, pe_req_q.vtype.vsew[1:0])) begin
           state_d         = IDLE;
           addrgen_ack_o   = 1'b1;
           addrgen_error_o = 1'b1;
-        end else begin
-          addrgen_req = '{
-            addr    : pe_req_q.scalar_op,
-            len     : pe_req_q.vl,
-            stride  : pe_req_q.stride,
-            vew     : pe_req_q.vtype.vsew,
-            is_load : is_load(pe_req_q.op),
-            // Unit-strided loads/stores trigger incremental AXI bursts.
-            is_burst: (pe_req_q.op inside {VLE, VSE})
-          };
+        end
+        else begin : address_valid
           addrgen_req_valid = 1'b1;
 
-          if (addrgen_req_ready) begin
+          if (addrgen_req_ready) begin : finished
             addrgen_req_valid = '0;
             addrgen_ack_o     = 1'b1;
             state_d           = IDLE;
-          end
-        end
+          end : finished
+        end : address_valid
       end
+      // ADDRGEN: begin
+      //   // Ara does not support misaligned AXI requests
+      //   if (is_addr_error(pe_req_q.scalar_op, pe_req_q.vtype.vsew)) begin
+      //     state_d         = IDLE;
+      //     addrgen_ack_o   = 1'b1;
+      //     addrgen_error_o = 1'b1;
+      //   end else begin
+      //     addrgen_req = '{
+      //       addr    : pe_req_q.scalar_op,
+      //       len     : pe_req_q.vl,
+      //       stride  : pe_req_q.stride,
+      //       vew     : pe_req_q.vtype.vsew,
+      //       is_load : is_load(pe_req_q.op),
+      //       // Unit-strided loads/stores trigger incremental AXI bursts.
+      //       is_burst: (pe_req_q.op inside {VLE, VSE})
+      //     };
+      //     addrgen_req_valid = 1'b1;
+
+      //     if (addrgen_req_ready) begin
+      //       addrgen_req_valid = '0;
+      //       addrgen_ack_o     = 1'b1;
+      //       state_d           = IDLE;
+      //     end
+      //   end
+      // end
       ADDRGEN_IDX_OP: begin
+        // NOTE: vstart is not supported for indexed operations
+        //       the logic shuld be introduced:
+        //       1. in the addrgen_operand_i operand read
+        //       2. in idx_addr computation
+        automatic logic [NrLanes-1:0] addrgen_operand_valid;
+
         // Stall the interface until the operation is over to catch possible exceptions
 
         // Every address can generate an exception
         addrgen_req = '{
           addr    : pe_req_q.scalar_op,
-          len     : pe_req_q.vl,
+          len     : lookahead_len_q,
           stride  : pe_req_q.stride,
-          vew     : pe_req_q.vtype.vsew,
+          vew     : pe_req_q.vtype.vsew[1:0],
           is_load : is_load(pe_req_q.op),
           // Unit-strided loads/stores trigger incremental AXI bursts.
-          is_burst: 1'b0
+          is_burst: 1'b0,
+          vstart  : pe_req_q.vstart
         };
         addrgen_req_valid = 1'b1;
 
+        // Adjust valid signals to the next block "operands_ready"
+        addrgen_operand_valid = addrgen_operand_valid_i;
+        for (int unsigned lane = 0; lane < NrLanes; lane++) begin : adjust_operand_valid
+          // - We are left with less byte than the maximim to issue,
+          //    this means that at least one lane is not going to push us any operand anymore
+          // - For the lanes which index % NrLanes != 0
+          if (((idx_op_cnt_q << pe_req_q.vtype.vsew) < (NrLanes * DataWidthB))
+               && (lane < pe_req_q.vstart[idx_width(NrLanes)-1:0])) begin : vstart_lane_adjust
+            addrgen_operand_valid[lane] |= 1'b1;
+          end : vstart_lane_adjust
+        end : adjust_operand_valid
+        // TODO: apply the same vstart logic also to mask_valid_i
+
         // Handle handshake and data between VRF and spill register
         // We accept all the incoming data, without any checks
         // since Ara stalls on an indexed memory operation
-        if (&addrgen_operand_valid_i & addrgen_operand_target_fu_i[0] == MFPU_ADDRGEN) begin
+        if (&addrgen_operand_valid) begin
 
           // Valid data for the spill register
           idx_addr_valid_d = 1'b1;
@@ -346,7 +496,90 @@ module addrgen import ara_pkg::*; import rvv_pkg::*; #(
           state_d = ADDRGEN_IDX_OP_END;
         end
       end
-
+      // ADDRGEN_IDX_OP: begin
+      //   // Stall the interface until the operation is over to catch possible exceptions
+
+      //   // Every address can generate an exception
+      //   addrgen_req = '{
+      //     addr    : pe_req_q.scalar_op,
+      //     len     : pe_req_q.vl,
+      //     stride  : pe_req_q.stride,
+      //     vew     : pe_req_q.vtype.vsew,
+      //     is_load : is_load(pe_req_q.op),
+      //     // Unit-strided loads/stores trigger incremental AXI bursts.
+      //     is_burst: 1'b0
+      //   };
+      //   addrgen_req_valid = 1'b1;
+
+      //   // Handle handshake and data between VRF and spill register
+      //   // We accept all the incoming data, without any checks
+      //   // since Ara stalls on an indexed memory operation
+      //   if (&addrgen_operand_valid_i & addrgen_operand_target_fu_i[0] == MFPU_ADDRGEN) begin
+
+      //     // Valid data for the spill register
+      //     idx_addr_valid_d = 1'b1;
+
+      //     // Select the correct element, and zero extend it depending on vsew
+      //     case (pe_req_q.eew_vs2)
+      //       EW8: begin
+      //         for (int unsigned b = 0; b < 8; b++)
+      //           if (b == elm_ptr_q)
+      //             idx_addr = reduced_word[b*8 +: 8];
+      //       end
+      //       EW16: begin
+      //         for (int unsigned h = 0; h < 4; h++)
+      //           if (h == elm_ptr_q)
+      //             idx_addr = reduced_word[h*16 +: 16];
+      //       end
+      //       EW32: begin
+      //         for (int unsigned w = 0; w < 2; w++)
+      //           if (w == elm_ptr_q)
+      //             idx_addr = reduced_word[w*32 +: 32];
+      //       end
+      //       EW64: begin
+      //         for (int unsigned d = 0; d < 1; d++)
+      //           if (d == elm_ptr_q)
+      //             idx_addr = reduced_word[d*64 +: 64];
+      //       end
+      //       default: begin
+      //         for (int unsigned b = 0; b < 8; b++)
+      //           if (b == elm_ptr_q)
+      //             idx_addr = reduced_word[b*8 +: 8];
+      //       end
+      //     endcase
+
+      //     // Compose the address
+      //     idx_final_addr_d = pe_req_q.scalar_op + idx_addr;
+
+      //     // When the data is accepted
+      //     if (idx_addr_ready_q) begin
+      //       // Consumed one element
+      //       idx_op_cnt_d = idx_op_cnt_q - 1;
+      //       // Have we finished a full NrLanes*64b word?
+      //       if (elm_ptr_q == last_elm_subw_q) begin
+      //         // Bump lane pointer
+      //         elm_ptr_d       = '0;
+      //         word_lane_ptr_d += 1;
+      //         if (word_lane_ptr_q == NrLanes - 1) begin
+      //           // Ready for the next full word
+      //           addrgen_operand_ready_o = 1'b1;
+      //         end
+      //       end else begin
+      //         // Bump element pointer
+      //         elm_ptr_d += 1;
+      //       end
+      //     end
+
+      //     if (idx_op_cnt_d == '0) begin
+      //       // Give a ready to the lanes if this was not done before
+      //       addrgen_operand_ready_o = 1'b1;
+      //     end
+      //   end
+
+      //   if (idx_op_error_d || addrgen_req_ready) begin
+      //     state_d = ADDRGEN_IDX_OP_END;
+      //   end
+      // end
       // This state exists not to create combinatorial paths on the interface
       ADDRGEN_IDX_OP_END : begin
         // Acknowledge the indexed memory operation
@@ -358,9 +591,23 @@ module addrgen import ara_pkg::*; import rvv_pkg::*; #(
         word_lane_ptr_d = '0;
         // Raise an error if necessary
         if (idx_op_error_q) begin
+          // In this case, we always get EEW-misaligned exceptions
           addrgen_error_o = 1'b1;
         end
       end
+      // ADDRGEN_IDX_OP_END : begin
+      //   // Acknowledge the indexed memory operation
+      //   addrgen_ack_o     = 1'b1;
+      //   addrgen_req_valid = '0;
+      //   state_d           = IDLE;
+      //   // Reset pointers
+      //   elm_ptr_d       = '0;
+      //   word_lane_ptr_d = '0;
+      //   // Raise an error if necessary
+      //   if (idx_op_error_q) begin
+      //     addrgen_error_o = 1'b1;
+      //   end
+      // end
     endcase
   end
 
@@ -375,6 +622,9 @@ module addrgen import ara_pkg::*; import rvv_pkg::*; #(
       last_elm_subw_q    <= '0;
       idx_op_error_q     <= '0;
       addrgen_error_vl_o <= '0;
+      lookahead_addr_e_q         <= '0;
+      lookahead_addr_se_q        <= '0;
+      lookahead_len_q            <= '0;
     end else begin
       state_q            <= state_d;
       pe_req_q           <= pe_req_d;
@@ -385,6 +635,9 @@ module addrgen import ara_pkg::*; import rvv_pkg::*; #(
       last_elm_subw_q    <= last_elm_subw_d;
       idx_op_error_q     <= idx_op_error_d;
       addrgen_error_vl_o <= addrgen_error_vl_d;
+      lookahead_addr_e_q         <= lookahead_addr_e_d;
+      lookahead_addr_se_q        <= lookahead_addr_se_d;
+      lookahead_len_q            <= lookahead_len_d;
     end
   end
 
@@ -392,6 +645,8 @@ module addrgen import ara_pkg::*; import rvv_pkg::*; #(
   //  Support for misaligned stores  //
   /////////////////////////////////////
 
+  localparam clog2_AxiStrobeWidth = $clog2(AxiDataWidth/8);
+
   // AXI Request Generation signals, declared here for convenience
   addrgen_req_t axi_addrgen_d, axi_addrgen_q;
 
@@ -430,8 +685,8 @@ module addrgen import ara_pkg::*; import rvv_pkg::*; #(
   } axi_addrgen_state_d, axi_addrgen_state_q;
 
   axi_addr_t aligned_start_addr_d, aligned_start_addr_q;
-  axi_addr_t aligned_next_start_addr_d, aligned_next_start_addr_q;
-  axi_addr_t aligned_end_addr_d, aligned_end_addr_q;
+  axi_addr_t aligned_next_start_addr_d, aligned_next_start_addr_q, aligned_next_start_addr_temp;
+  axi_addr_t aligned_end_addr_d, aligned_end_addr_q, aligned_end_addr_temp;
 
   // MSb of the next-next page (page selector for page 2 positions after the current one)
   logic [($bits(aligned_start_addr_d) - 12)-1:0] next_2page_msb_d, next_2page_msb_q;
@@ -439,6 +694,35 @@ module addrgen import ara_pkg::*; import rvv_pkg::*; #(
   logic [$clog2(AxiDataWidth/8):0]            eff_axi_dw_d, eff_axi_dw_q;
   logic [idx_width($clog2(AxiDataWidth/8)):0] eff_axi_dw_log_d, eff_axi_dw_log_q;
 
+  function automatic void set_end_addr (
+      input  logic [($bits(axi_addr_t) - 12)-1:0]       next_2page_msb,
+      input  vlen_t                                     num_bytes,
+      input  axi_addr_t                                 addr,
+      input  logic [clog2_AxiStrobeWidth:0]             eff_axi_dw,
+      input  logic [idx_width(clog2_AxiStrobeWidth):0]  eff_axi_dw_log,
+      input  axi_addr_t                                 aligned_start_addr,
+      output axi_addr_t                                 aligned_end_addr,
+      output axi_addr_t                                 aligned_next_start_addr
+  );
+
+    automatic int unsigned max_burst_bytes = 256 << eff_axi_dw_log;
+
+    // The final address can be found similarly...
+    if (num_bytes >= max_burst_bytes) begin
+        aligned_next_start_addr = aligned_addr(addr + max_burst_bytes, eff_axi_dw_log);
+    end else begin
+        aligned_next_start_addr = aligned_addr(addr + num_bytes - 1, eff_axi_dw_log) + eff_axi_dw;
+    end
+    aligned_end_addr = aligned_next_start_addr - 1;
+
+    // But since AXI requests are aligned in 4 KiB pages, aligned_end_addr must be in the
+    // same page as aligned_start_addr
+    if (aligned_start_addr[AxiAddrWidth-1:12] != aligned_end_addr[AxiAddrWidth-1:12]) begin
+        aligned_end_addr        = {aligned_start_addr[AxiAddrWidth-1:12], 12'hFFF};
+        aligned_next_start_addr = {                     next_2page_msb  , 12'h000};
+    end
+  endfunction
+
   always_comb begin: axi_addrgen
     // Maintain state
     axi_addrgen_state_d = axi_addrgen_state_q;
@@ -477,14 +761,42 @@ module addrgen import ara_pkg::*; import rvv_pkg::*; #(
 
     case (axi_addrgen_state_q)
       AXI_ADDRGEN_IDLE: begin
+        // This computation is timing-critical. Look ahead and compute even if addr not valid.
+        axi_addrgen_d = addrgen_req;
+
+        // The start address is found by aligning the original request address by the width of
+        // the memory interface.
+        aligned_start_addr_d = aligned_addr(axi_addrgen_d.addr, clog2_AxiStrobeWidth);
+        // Pre-calculate the next_2page_msb. This should not require much energy if the addr
+        // has zeroes in the upper positions.
+        // We can use this also for the misaligned address calculation, as the next 2 page msb
+        // will be the same either way.
+        next_2page_msb_d = aligned_start_addr_d[AxiAddrWidth-1:12] + 1;
+        // The final address can be found similarly...
+        set_end_addr (
+          next_2page_msb_d,
+          axi_addrgen_d.len,
+          axi_addrgen_d.addr,
+          AxiDataWidth/8,
+          clog2_AxiStrobeWidth,
+          aligned_start_addr_d,
+          aligned_end_addr_d,
+          aligned_next_start_addr_d
+        );
+
         if (addrgen_req_valid) begin
-          axi_addrgen_d       = addrgen_req;
           axi_addrgen_state_d = core_st_pending_i ? AXI_ADDRGEN_WAITING : AXI_ADDRGEN_REQUESTING;
 
           // In case of a misaligned store, reduce the effective width of the AXI transaction,
           // since the store unit does not support misalignments between the AXI bus and the lanes
-          if ((axi_addrgen_d.addr[$clog2(AxiDataWidth/8)-1:0] != '0) && !axi_addrgen_d.is_load)
-          begin
+          if (axi_addrgen_d.vstart != 0 && !axi_addrgen_d.is_load) begin
+            // vstart > 0 can create problems similar to the ones a misalignment would create.
+            // Limit the effective AXI bus width to the element width to avoid problems.
+            axi_addrgen_state_d = AXI_ADDRGEN_MISALIGNED;
+
+            eff_axi_dw_d     = 1 << axi_addrgen_d.vew;
+            eff_axi_dw_log_d = axi_addrgen_d.vew;
+          end else if ((axi_addrgen_d.addr[clog2_AxiStrobeWidth-1:0] != '0) && !axi_addrgen_d.is_load) begin
             // Calculate the start and the end addresses in the AXI_ADDRGEN_MISALIGNED state
             axi_addrgen_state_d = AXI_ADDRGEN_MISALIGNED;
 
@@ -492,86 +804,149 @@ module addrgen import ara_pkg::*; import rvv_pkg::*; #(
             eff_axi_dw_log_d = zeroes_cnt;
           end else begin
             eff_axi_dw_d     = AxiDataWidth/8;
-            eff_axi_dw_log_d = $clog2(AxiDataWidth/8);
-          end
-          
-          /*// The start address is found by aligning the original request address by the width of
-          // the memory interface.
-          aligned_start_addr_d = aligned_addr(axi_addrgen_d.addr, $clog2(AxiDataWidth/8));
-          // Pre-calculate the next_2page_msb. This should not require much energy if the addr
-          // has zeroes in the upper positions.
-          next_2page_msb_d = aligned_start_addr_d[AxiAddrWidth-1:12] + 1;
-          // The final address can be found similarly...
-          if (axi_addrgen_d.len << int'(axi_addrgen_d.vew) >= (256 << $clog2(AxiDataWidth/8))) begin
-            aligned_next_start_addr_d =
-              aligned_addr(axi_addrgen_d.addr + (256 << $clog2(AxiDataWidth/8)), $clog2(AxiDataWidth/8));
-            aligned_end_addr_d = aligned_next_start_addr_d - 1;
-          end else begin
-            aligned_next_start_addr_d =
-              aligned_addr(axi_addrgen_d.addr + (axi_addrgen_d.len << int'(axi_addrgen_d.vew)) - 1,
-              $clog2(AxiDataWidth/8)) + AxiDataWidth/8;
-            aligned_end_addr_d = aligned_next_start_addr_d - 1;
+            eff_axi_dw_log_d = clog2_AxiStrobeWidth;
           end
-          // But since AXI requests are aligned in 4 KiB pages, aligned_end_addr must be in the
-          // same page as aligned_start_addr
-          if (aligned_start_addr_d[AxiAddrWidth-1:12] != aligned_end_addr_d[AxiAddrWidth-1:12]) begin
-            aligned_end_addr_d        = {aligned_start_addr_d[AxiAddrWidth-1:12], 12'hFFF};
-            aligned_next_start_addr_d = {                       next_2page_msb_d, 12'h000};
-          end*/
-
-          /*aligned_start_addr_d = axi_addrgen_d.addr;
-          aligned_next_start_addr_d = axi_addrgen_d.addr + (axi_addrgen_d.len << int'(axi_addrgen_d.vew));
-          aligned_end_addr_d = aligned_next_start_addr_d - 1;*/
         end
       end
+      // AXI_ADDRGEN_IDLE: begin
+      //   if (addrgen_req_valid) begin
+      //     axi_addrgen_d       = addrgen_req;
+      //     axi_addrgen_state_d = core_st_pending_i ? AXI_ADDRGEN_WAITING : AXI_ADDRGEN_REQUESTING;
+
+      //     // In case of a misaligned store, reduce the effective width of the AXI transaction,
+      //     // since the store unit does not support misalignments between the AXI bus and the lanes
+      //     if ((axi_addrgen_d.addr[$clog2(AxiDataWidth/8)-1:0] != '0) && !axi_addrgen_d.is_load)
+      //     begin
+      //       // Calculate the start and the end addresses in the AXI_ADDRGEN_MISALIGNED state
+      //       axi_addrgen_state_d = AXI_ADDRGEN_MISALIGNED;
+
+      //       eff_axi_dw_d     = {1'b0, narrow_axi_data_bwidth};
+      //       eff_axi_dw_log_d = zeroes_cnt;
+      //     end else begin
+      //       eff_axi_dw_d     = AxiDataWidth/8;
+      //       eff_axi_dw_log_d = $clog2(AxiDataWidth/8);
+      //     end
+          
+      //     /*// The start address is found by aligning the original request address by the width of
+      //     // the memory interface.
+      //     aligned_start_addr_d = aligned_addr(axi_addrgen_d.addr, $clog2(AxiDataWidth/8));
+      //     // Pre-calculate the next_2page_msb. This should not require much energy if the addr
+      //     // has zeroes in the upper positions.
+      //     next_2page_msb_d = aligned_start_addr_d[AxiAddrWidth-1:12] + 1;
+      //     // The final address can be found similarly...
+      //     if (axi_addrgen_d.len << int'(axi_addrgen_d.vew) >= (256 << $clog2(AxiDataWidth/8))) begin
+      //       aligned_next_start_addr_d =
+      //         aligned_addr(axi_addrgen_d.addr + (256 << $clog2(AxiDataWidth/8)), $clog2(AxiDataWidth/8));
+      //       aligned_end_addr_d = aligned_next_start_addr_d - 1;
+      //     end else begin
+      //       aligned_next_start_addr_d =
+      //         aligned_addr(axi_addrgen_d.addr + (axi_addrgen_d.len << int'(axi_addrgen_d.vew)) - 1,
+      //         $clog2(AxiDataWidth/8)) + AxiDataWidth/8;
+      //       aligned_end_addr_d = aligned_next_start_addr_d - 1;
+      //     end
+      //     // But since AXI requests are aligned in 4 KiB pages, aligned_end_addr must be in the
+      //     // same page as aligned_start_addr
+      //     if (aligned_start_addr_d[AxiAddrWidth-1:12] != aligned_end_addr_d[AxiAddrWidth-1:12]) begin
+      //       aligned_end_addr_d        = {aligned_start_addr_d[AxiAddrWidth-1:12], 12'hFFF};
+      //       aligned_next_start_addr_d = {                       next_2page_msb_d, 12'h000};
+      //     end*/
+
+      //     /*aligned_start_addr_d = axi_addrgen_d.addr;
+      //     aligned_next_start_addr_d = axi_addrgen_d.addr + (axi_addrgen_d.len << int'(axi_addrgen_d.vew));
+      //     aligned_end_addr_d = aligned_next_start_addr_d - 1;*/
+      //   end
+      // end
       AXI_ADDRGEN_MISALIGNED: begin
         axi_addrgen_state_d = core_st_pending_i ? AXI_ADDRGEN_WAITING : AXI_ADDRGEN_REQUESTING;
 
         // The start address is found by aligning the original request address by the width of
         // the memory interface.
         aligned_start_addr_d = aligned_addr(axi_addrgen_q.addr, eff_axi_dw_log_q);
-        // The final address can be found similarly...
-        if (axi_addrgen_q.len << int'(axi_addrgen_q.vew) >= (256 << eff_axi_dw_log_q)) begin
-          aligned_next_start_addr_d =
-            aligned_addr(axi_addrgen_q.addr + (256 << eff_axi_dw_log_q), eff_axi_dw_log_q);
-          aligned_end_addr_d = aligned_next_start_addr_d - 1;
-        end else begin
-          aligned_next_start_addr_d =
-            aligned_addr(axi_addrgen_q.addr + (axi_addrgen_q.len << int'(axi_addrgen_q.vew)) - 1,
-            eff_axi_dw_log_q) + eff_axi_dw_q;
-          aligned_end_addr_d = aligned_next_start_addr_d - 1;
-        end
-        // But since AXI requests are aligned in 4 KiB pages, aligned_end_addr must be in the
-        // same page as aligned_start_addr
-        if (aligned_start_addr_d[AxiAddrWidth-1:12] != aligned_end_addr_d[AxiAddrWidth-1:12]) begin
-          aligned_end_addr_d = {aligned_start_addr_d[AxiAddrWidth-1:12], 12'hFFF};
-          aligned_next_start_addr_d = {                next_2page_msb_q, 12'h000};
-        end
+
+        set_end_addr (
+          next_2page_msb_q,
+          axi_addrgen_q.len,
+          axi_addrgen_q.addr,
+          eff_axi_dw_q,
+          eff_axi_dw_log_q,
+          aligned_start_addr_d,
+          aligned_end_addr_d,
+          aligned_next_start_addr_d
+        );
       end
+      // AXI_ADDRGEN_MISALIGNED: begin
+      //   axi_addrgen_state_d = core_st_pending_i ? AXI_ADDRGEN_WAITING : AXI_ADDRGEN_REQUESTING;
+
+      //   // The start address is found by aligning the original request address by the width of
+      //   // the memory interface.
+      //   aligned_start_addr_d = aligned_addr(axi_addrgen_q.addr, eff_axi_dw_log_q);
+      //   // The final address can be found similarly...
+      //   if (axi_addrgen_q.len << int'(axi_addrgen_q.vew) >= (256 << eff_axi_dw_log_q)) begin
+      //     aligned_next_start_addr_d =
+      //       aligned_addr(axi_addrgen_q.addr + (256 << eff_axi_dw_log_q), eff_axi_dw_log_q);
+      //     aligned_end_addr_d = aligned_next_start_addr_d - 1;
+      //   end else begin
+      //     aligned_next_start_addr_d =
+      //       aligned_addr(axi_addrgen_q.addr + (axi_addrgen_q.len << int'(axi_addrgen_q.vew)) - 1,
+      //       eff_axi_dw_log_q) + eff_axi_dw_q;
+      //     aligned_end_addr_d = aligned_next_start_addr_d - 1;
+      //   end
+      //   // But since AXI requests are aligned in 4 KiB pages, aligned_end_addr must be in the
+      //   // same page as aligned_start_addr
+      //   if (aligned_start_addr_d[AxiAddrWidth-1:12] != aligned_end_addr_d[AxiAddrWidth-1:12]) begin
+      //     aligned_end_addr_d = {aligned_start_addr_d[AxiAddrWidth-1:12], 12'hFFF};
+      //     aligned_next_start_addr_d = {                next_2page_msb_q, 12'h000};
+      //   end
+      // end
       AXI_ADDRGEN_WAITING: begin
         if (!core_st_pending_i)
           axi_addrgen_state_d = AXI_ADDRGEN_REQUESTING;
       end
       AXI_ADDRGEN_REQUESTING : begin
-        automatic logic axi_ax_ready = (axi_addrgen_q.is_load && axi_ar_ready_i) || (!
-          axi_addrgen_q.is_load && axi_aw_ready_i);
+        automatic logic axi_ax_ready = (axi_addrgen_q.is_load && axi_ar_ready_i) || (!axi_addrgen_q.is_load && axi_aw_ready_i);
+        automatic logic [12:0] num_bytes; // Cannot consume more than 4 KiB
+        automatic vlen_t remaining_bytes;
 
         // Pre-calculate the next_2page_msb. This should not require much energy if the addr
         // has zeroes in the upper positions.
         next_2page_msb_d = aligned_next_start_addr_q[AxiAddrWidth-1:12] + 1;
+        // Pre-calculate the bytes used in a unit-strided access and the remaining bytes to ask.
+        // The proper way to do so would be aligned_end_addr_q[11:0] + 1 - axi_addrgen_q.addr[11:0].
+        // Avoid explicit computation of aligned_next_start_addr + 1 with a trick that works if
+        // aligned_next_start_addr <= 12'hFFF.
+        if (aligned_end_addr_q[11:0] != 12'hFFF) begin
+          num_bytes = aligned_next_start_addr_q[11:0] - axi_addrgen_q.addr[11:0];
+        end else begin
+        // Special case: aligned_next_start_addr > 12'hFFF.
+          num_bytes = 13'h1000 - axi_addrgen_q.addr[11:0];
+        end
+        // remaining_bytes = axi_addrgen_q.len - num_bytes;
+        // if (axi_addrgen_q.len < num_bytes) begin
+        //   remaining_bytes = 0;
+        // end
+        remaining_bytes = 0;
 
         // Before starting a transaction on a different channel, wait the formers to complete
         // Otherwise, the ordering of the responses is not guaranteed, and with the current
         // implementation we can incur in deadlocks
+        // NOTE: this might be referring to an obsolete axi_cut implementation
         if (axi_addrgen_queue_empty || (axi_addrgen_req_o.is_load && axi_addrgen_q.is_load) ||
-            (~axi_addrgen_req_o.is_load && ~axi_addrgen_q.is_load)) begin
-          if (!axi_addrgen_queue_full && axi_ax_ready) begin
-            if (axi_addrgen_q.is_burst) begin
+             (~axi_addrgen_req_o.is_load && ~axi_addrgen_q.is_load)) begin : axi_ax_idle
+          if (!axi_addrgen_queue_full && axi_ax_ready) begin : start_req
+            automatic axi_addr_t paddr;
+
+            // Mux target address
+            paddr = axi_addrgen_q.addr;
 
+            // Prepare data in advance
+            if (axi_addrgen_q.is_burst) begin : unit_stride_data
               /////////////////////////
               //  Unit-Stride access //
               /////////////////////////
 
+              // NOTE: all these variables could be narrowed to the minimum number of bits
+              automatic int unsigned num_beats;
+
               // AXI burst length
               automatic int unsigned burst_length;
 
@@ -580,37 +955,28 @@ module addrgen import ara_pkg::*; import rvv_pkg::*; #(
               // 2 - The AXI burst length cannot be longer than the number of beats required
               //     to access the memory regions between aligned_start_addr and
               //     aligned_end_addr
-              // if (burst_length > ((aligned_end_addr_q - aligned_start_addr_q) >>
-              //       eff_axi_dw_log_q) + 1)
-              // burst_length = ((aligned_end_addr_q - aligned_start_addr_q) >>
-              //   eff_axi_dw_log_q) + 1;
+              num_beats = ((aligned_end_addr_q[11:0] - aligned_start_addr_q[11:0]) >> eff_axi_dw_log_q) + 1;
+              if (burst_length > num_beats) begin
+                burst_length = num_beats;
+              end
 
-              burst_length = (((axi_addrgen_q.len << int'(axi_addrgen_q.vew))-1) >> eff_axi_dw_log_q) + 1;
+              burst_length = ((axi_addrgen_q.len-1) >> eff_axi_dw_log_q) + 1;
 
-              // if (burst_length > ((aligned_end_addr_q[11:0] - aligned_start_addr_q[11:0]) >>
-              //       eff_axi_dw_log_q) + 1)
-              //   burst_length = ((aligned_end_addr_q[11:0] - aligned_start_addr_q[11:0]) >>
-              //     eff_axi_dw_log_q) + 1;
-              
-              // The above burst length is only used for vldu and vstu to know how many packets to receive.
-              // The AXI request to Memory in Global Ld-St unit takes care of the maximum burst limit.
               // AR Channel
               if (axi_addrgen_q.is_load) begin
                 axi_ar_o = '{
-                  addr   : axi_addrgen_q.addr,
+                  addr   : paddr,
                   len    : burst_length - 1,
                   size   : eff_axi_dw_log_q,
                   cache  : CACHE_MODIFIABLE,
                   burst  : BURST_INCR,
                   default: '0
                 };
-                vew_ar_o = axi_addrgen_q.vew;
-                axi_ar_valid_o = 1'b1;
               end
               // AW Channel
               else begin
                 axi_aw_o = '{
-                  addr   : axi_addrgen_q.addr,
+                  addr   : paddr,
                   len    : burst_length - 1,
                   // If misaligned store access, reduce the effective AXI width
                   // This hurts performance
@@ -619,173 +985,432 @@ module addrgen import ara_pkg::*; import rvv_pkg::*; #(
                   burst  : BURST_INCR,
                   default: '0
                 };
-                vew_aw_o = axi_addrgen_q.vew; 
-                axi_aw_valid_o = 1'b1;
               end
 
               // Send this request to the load/store units
               axi_addrgen_queue = '{
-                addr   : axi_addrgen_q.addr,
-                len    : burst_length - 1,
-                size   : eff_axi_dw_log_q,
-                is_load: axi_addrgen_q.is_load
+                addr         : paddr,
+                len          : burst_length - 1,
+                size         : eff_axi_dw_log_q,
+                is_load      : axi_addrgen_q.is_load
               };
-              axi_addrgen_queue_push = 1'b1;
 
-              // Account for the requested operands
-              /*axi_addrgen_d.len = axi_addrgen_q.len - ((aligned_end_addr_q[11:0] - axi_addrgen_q.addr[11:0] + 1)
-                  >> int'(axi_addrgen_q.vew));
-              if (axi_addrgen_q.len < ((aligned_end_addr_q[11:0] - axi_addrgen_q.addr[11:0] + 1)
-                  >> int'(axi_addrgen_q.vew)))
-                axi_addrgen_d.len = 0;
-              axi_addrgen_d.addr = aligned_next_start_addr_q;
-              */
-              // Finished generating AXI requests
-              // if (axi_addrgen_d.len == 0) begin
-                addrgen_req_ready   = 1'b1;
-                axi_addrgen_state_d = AXI_ADDRGEN_IDLE;
-              // end
-              /*
               // Calculate the addresses for the next iteration
+              // TODO: test this for SEW!=64, otherwise this computation is never used
               // The start address is found by aligning the original request address by the width of
               // the memory interface. In our case, we have it already.
-              aligned_start_addr_d = axi_addrgen_d.addr;
-              // The final address can be found similarly.
-              // How many B we requested? No more than (256 << burst_size)
-              if (axi_addrgen_d.len << int'(axi_addrgen_q.vew) >= (256 << eff_axi_dw_log_q)) begin
-                aligned_next_start_addr_d =
-                  aligned_addr(aligned_start_addr_d + (256 << eff_axi_dw_log_q), eff_axi_dw_log_q);
-                aligned_end_addr_d = aligned_next_start_addr_d - 1;
-              end else begin
-                aligned_next_start_addr_d =
-                  aligned_addr(aligned_start_addr_d + (axi_addrgen_d.len << int'(axi_addrgen_q.vew))
-                  - 1, eff_axi_dw_log_q) + eff_axi_dw_q;
-                aligned_end_addr_d = aligned_next_start_addr_d - 1;
-              end
-              // But since AXI requests are aligned in 4 KiB pages, aligned_end_addr must be in the
-              // same page as aligned_start_addr
-              if (aligned_start_addr_d[AxiAddrWidth-1:12] != aligned_end_addr_d[AxiAddrWidth-1:12]) begin
-                aligned_end_addr_d        = {aligned_start_addr_d[AxiAddrWidth-1:12], 12'hFFF};
-                aligned_next_start_addr_d = {                       next_2page_msb_d, 12'h000};
-              end*/
-              
-            end else if (state_q != ADDRGEN_IDX_OP) begin
-
+              set_end_addr (
+                next_2page_msb_d,
+                axi_addrgen_q.len - num_bytes,
+                aligned_next_start_addr_q,
+                eff_axi_dw_q,
+                eff_axi_dw_log_q,
+                aligned_next_start_addr_q,
+                aligned_end_addr_temp,
+                aligned_next_start_addr_temp
+              );
+            end : unit_stride_data
+            else if (state_q != ADDRGEN_IDX_OP) begin : strided_data
               /////////////////////
               //  Strided access //
               /////////////////////
-
               // AR Channel
               if (axi_addrgen_q.is_load) begin
                 axi_ar_o = '{
-                  addr   : axi_addrgen_q.addr,
+                  addr   : paddr,
                   len    : 0,
                   size   : axi_addrgen_q.vew,
                   cache  : CACHE_MODIFIABLE,
                   burst  : BURST_INCR,
                   default: '0
                 };
-                axi_ar_valid_o = 1'b1;
               end
               // AW Channel
               else begin
                 axi_aw_o = '{
-                  addr   : axi_addrgen_q.addr,
+                  addr   : paddr,
                   len    : 0,
                   size   : axi_addrgen_q.vew,
                   cache  : CACHE_MODIFIABLE,
                   burst  : BURST_INCR,
                   default: '0
                 };
-                axi_aw_valid_o = 1'b1;
               end
 
               // Send this request to the load/store units
               axi_addrgen_queue = '{
-                addr   : axi_addrgen_q.addr,
-                size   : axi_addrgen_q.vew,
-                len    : 0,
-                is_load: axi_addrgen_q.is_load
+                addr         : paddr,
+                size         : axi_addrgen_q.vew,
+                len          : 0,
+                is_load      : axi_addrgen_q.is_load
               };
-              axi_addrgen_queue_push = 1'b1;
 
               // Account for the requested operands
-              axi_addrgen_d.len  = axi_addrgen_q.len - 1;
+              // This should never overflow
+              len_temp = axi_addrgen_q.len - (1 << axi_addrgen_q.vew);
               // Calculate the addresses for the next iteration, adding the correct stride
-              axi_addrgen_d.addr = axi_addrgen_q.addr + axi_addrgen_q.stride;
-
-              // Finished generating AXI requests
-              if (axi_addrgen_d.len == 0) begin
-                addrgen_req_ready   = 1'b1;
-                axi_addrgen_state_d = AXI_ADDRGEN_IDLE;
-              end
-            end else begin
+              next_addr_strided_temp = axi_addrgen_q.addr + axi_addrgen_q.stride;
+            end : strided_data
+            else begin : indexed_data
+              // NOTE: address translation is not yet been implemented/tested for indexed
 
+              automatic axi_addr_t idx_final_paddr;
               //////////////////////
               //  Indexed access  //
               //////////////////////
 
-              if (idx_addr_valid_q) begin
-                // We consumed a word
-                idx_addr_ready_d = 1'b1;
-
-                // AR Channel
-                if (axi_addrgen_q.is_load) begin
-                  axi_ar_o = '{
-                    addr   : idx_final_addr_q,
-                    len    : 0,
-                    size   : axi_addrgen_q.vew,
-                    cache  : CACHE_MODIFIABLE,
-                    burst  : BURST_INCR,
-                    default: '0
-                  };
-                  axi_ar_valid_o = 1'b1;
-                end
-                // AW Channel
-                else begin
-                  axi_aw_o = '{
-                    addr   : idx_final_addr_q,
-                    len    : 0,
-                    size   : axi_addrgen_q.vew,
-                    cache  : CACHE_MODIFIABLE,
-                    burst  : BURST_INCR,
-                    default: '0
-                  };
-                  axi_aw_valid_o = 1'b1;
-                end
-
-                // Send this request to the load/store units
-                axi_addrgen_queue = '{
-                  addr   : idx_final_addr_q,
-                  size   : axi_addrgen_q.vew,
-                  len    : 0,
-                  is_load: axi_addrgen_q.is_load
-                };
-                axi_addrgen_queue_push = 1'b1;
-
-                // Account for the requested operands
-                axi_addrgen_d.len = axi_addrgen_q.len - 1;
-
-                // Check if the address does generate an exception
-                if (is_addr_error(idx_final_addr_q, axi_addrgen_q.vew)) begin
+              // TODO: check if idx_addr_valid_q is stable
+              if (idx_addr_valid_q) begin : if_idx_addr_valid_q
+                // Check if the virtual address generates an exception
+                // NOTE: we can do this even before address translation, since the
+                //       page offset (2^12) is the same for both physical and virtual addresses
+                if (is_addr_error(idx_final_addr_q, axi_addrgen_q.vew[1:0])) begin : eew_misaligned_error
                   // Generate an error
                   idx_op_error_d          = 1'b1;
                   // Forward next vstart info to the dispatcher
                   addrgen_error_vl_d      = addrgen_req.len - axi_addrgen_q.len - 1;
                   addrgen_req_ready       = 1'b1;
                   axi_addrgen_state_d     = AXI_ADDRGEN_IDLE;
-                end
+                end : eew_misaligned_error
+                else begin : aligned_vaddress
+                  // Mux target address
+                  idx_final_paddr = idx_final_addr_q;
+
+                  // AR Channel
+                  if (axi_addrgen_q.is_load) begin
+                    axi_ar_o = '{
+                      addr   : idx_final_paddr,
+                      len    : 0,
+                      size   : axi_addrgen_q.vew,
+                      cache  : CACHE_MODIFIABLE,
+                      burst  : BURST_INCR,
+                      default: '0
+                    };
+                  end
+                  // AW Channel
+                  else begin
+                    axi_aw_o = '{
+                      addr   : idx_final_paddr,
+                      len    : 0,
+                      size   : axi_addrgen_q.vew,
+                      cache  : CACHE_MODIFIABLE,
+                      burst  : BURST_INCR,
+                      default: '0
+                    };
+                  end
+
+                  // Prepare the request for the load or store unit
+                  axi_addrgen_queue = '{
+                    addr         : idx_final_paddr,
+                    size         : axi_addrgen_q.vew,
+                    len          : 0,
+                    is_load      : axi_addrgen_q.is_load
+                  };
 
-                // Finished generating AXI requests
-                if (axi_addrgen_d.len == 0) begin
-                  addrgen_req_ready   = 1'b1;
-                  axi_addrgen_state_d = AXI_ADDRGEN_IDLE;
-                end
-              end
-            end
+                  // Account for the requested operands
+                  // This should never overflow
+                  len_temp = axi_addrgen_q.len - (1 << axi_addrgen_q.vew);
+                end : aligned_vaddress
+              end : if_idx_addr_valid_q
+            end : indexed_data
+
+            if (axi_addrgen_q.is_burst) begin : unit_stride // UNIT-STRIDED ACCESS
+              // AR Channel
+              axi_ar_valid_o = axi_addrgen_q.is_load;
+              // AW Channel
+              axi_aw_valid_o = ~axi_addrgen_q.is_load;
+
+              // Send this request to the load/store units
+              axi_addrgen_queue_push = 1'b1;
+
+              // We pre-calculated the values already
+              axi_addrgen_d.len  = remaining_bytes;
+              axi_addrgen_d.addr = aligned_next_start_addr_q;
+
+              aligned_start_addr_d      = axi_addrgen_d.addr;
+              aligned_end_addr_d        = aligned_end_addr_temp;
+              aligned_next_start_addr_d = aligned_next_start_addr_temp;
+            end : unit_stride
+            else if (state_q != ADDRGEN_IDX_OP) begin : strided // STRIDED ACCESS
+              // AR Channel
+              axi_ar_valid_o = axi_addrgen_q.is_load;
+              // AW Channel
+              axi_aw_valid_o = ~axi_addrgen_q.is_load;
+
+              // Send this request to the load/store units
+              axi_addrgen_queue_push = 1'b1;
+
+              // We pre-calculated the values already
+              axi_addrgen_d.len = len_temp;
+              axi_addrgen_d.addr = next_addr_strided_temp;
+            end : strided
+            else begin : indexed // INDEXED ACCESS
+              automatic axi_addr_t idx_final_paddr;
+              // TODO: check if idx_addr_valid_q is stable
+              if (idx_addr_valid_q) begin : if_idx_addr_valid_q
+
+                // Check if the virtual address generates an exception
+                // NOTE: we can do this even before address translation, since the
+                //       page offset (2^12) is the same for both physical and virtual addresses
+                if (!is_addr_error(idx_final_addr_q, axi_addrgen_q.vew[1:0])) begin : aligned_vaddress
+                  // We consumed a word
+                  idx_addr_ready_d = 1'b1;
+
+                  // AR Channel
+                  axi_ar_valid_o = axi_addrgen_q.is_load;
+                  // AW Channel
+                  axi_aw_valid_o = ~axi_addrgen_q.is_load;
+
+                  // Send this request to the load/store units
+                  axi_addrgen_queue_push = 1'b1;
+
+                  // We pre-calculated the values already
+                  axi_addrgen_d.len = len_temp;
+                end : aligned_vaddress
+              end : if_idx_addr_valid_q
+            end : indexed
+            // Finished generating AXI requests
+            if (axi_addrgen_d.len == 0) begin : finished
+              addrgen_req_ready   = 1'b1;
+              axi_addrgen_state_d = AXI_ADDRGEN_IDLE;
+            end : finished
           end
         end
       end
+      // AXI_ADDRGEN_REQUESTING : begin
+      //   automatic logic axi_ax_ready = (axi_addrgen_q.is_load && axi_ar_ready_i) || (!
+      //     axi_addrgen_q.is_load && axi_aw_ready_i);
+
+      //   // Pre-calculate the next_2page_msb. This should not require much energy if the addr
+      //   // has zeroes in the upper positions.
+      //   next_2page_msb_d = aligned_next_start_addr_q[AxiAddrWidth-1:12] + 1;
+
+      //   // Before starting a transaction on a different channel, wait the formers to complete
+      //   // Otherwise, the ordering of the responses is not guaranteed, and with the current
+      //   // implementation we can incur in deadlocks
+      //   if (axi_addrgen_queue_empty || (axi_addrgen_req_o.is_load && axi_addrgen_q.is_load) ||
+      //       (~axi_addrgen_req_o.is_load && ~axi_addrgen_q.is_load)) begin
+      //     if (!axi_addrgen_queue_full && axi_ax_ready) begin
+      //       if (axi_addrgen_q.is_burst) begin
+
+      //         /////////////////////////
+      //         //  Unit-Stride access //
+      //         /////////////////////////
+
+      //         // AXI burst length
+      //         automatic int unsigned burst_length;
+
+      //         // 1 - AXI bursts are at most 256 beats long.
+      //         burst_length = 256;
+      //         // 2 - The AXI burst length cannot be longer than the number of beats required
+      //         //     to access the memory regions between aligned_start_addr and
+      //         //     aligned_end_addr
+      //         // if (burst_length > ((aligned_end_addr_q - aligned_start_addr_q) >>
+      //         //       eff_axi_dw_log_q) + 1)
+      //         // burst_length = ((aligned_end_addr_q - aligned_start_addr_q) >>
+      //         //   eff_axi_dw_log_q) + 1;
+
+      //         burst_length = (((axi_addrgen_q.len << int'(axi_addrgen_q.vew))-1) >> eff_axi_dw_log_q) + 1;
+
+      //         // if (burst_length > ((aligned_end_addr_q[11:0] - aligned_start_addr_q[11:0]) >>
+      //         //       eff_axi_dw_log_q) + 1)
+      //         //   burst_length = ((aligned_end_addr_q[11:0] - aligned_start_addr_q[11:0]) >>
+      //         //     eff_axi_dw_log_q) + 1;
+              
+      //         // The above burst length is only used for vldu and vstu to know how many packets to receive.
+      //         // The AXI request to Memory in Global Ld-St unit takes care of the maximum burst limit.
+      //         // AR Channel
+      //         if (axi_addrgen_q.is_load) begin
+      //           axi_ar_o = '{
+      //             addr   : axi_addrgen_q.addr,
+      //             len    : burst_length - 1,
+      //             size   : eff_axi_dw_log_q,
+      //             cache  : CACHE_MODIFIABLE,
+      //             burst  : BURST_INCR,
+      //             default: '0
+      //           };
+      //           vew_ar_o = axi_addrgen_q.vew;
+      //           axi_ar_valid_o = 1'b1;
+      //         end
+      //         // AW Channel
+      //         else begin
+      //           axi_aw_o = '{
+      //             addr   : axi_addrgen_q.addr,
+      //             len    : burst_length - 1,
+      //             // If misaligned store access, reduce the effective AXI width
+      //             // This hurts performance
+      //             size   : eff_axi_dw_log_q,
+      //             cache  : CACHE_MODIFIABLE,
+      //             burst  : BURST_INCR,
+      //             default: '0
+      //           };
+      //           vew_aw_o = axi_addrgen_q.vew; 
+      //           axi_aw_valid_o = 1'b1;
+      //         end
+
+      //         // Send this request to the load/store units
+      //         axi_addrgen_queue = '{
+      //           addr   : axi_addrgen_q.addr,
+      //           len    : burst_length - 1,
+      //           size   : eff_axi_dw_log_q,
+      //           is_load: axi_addrgen_q.is_load
+      //         };
+      //         axi_addrgen_queue_push = 1'b1;
+
+      //         // Account for the requested operands
+      //         /*axi_addrgen_d.len = axi_addrgen_q.len - ((aligned_end_addr_q[11:0] - axi_addrgen_q.addr[11:0] + 1)
+      //             >> int'(axi_addrgen_q.vew));
+      //         if (axi_addrgen_q.len < ((aligned_end_addr_q[11:0] - axi_addrgen_q.addr[11:0] + 1)
+      //             >> int'(axi_addrgen_q.vew)))
+      //           axi_addrgen_d.len = 0;
+      //         axi_addrgen_d.addr = aligned_next_start_addr_q;
+      //         */
+      //         // Finished generating AXI requests
+      //         // if (axi_addrgen_d.len == 0) begin
+      //           addrgen_req_ready   = 1'b1;
+      //           axi_addrgen_state_d = AXI_ADDRGEN_IDLE;
+      //         // end
+      //         /*
+      //         // Calculate the addresses for the next iteration
+      //         // The start address is found by aligning the original request address by the width of
+      //         // the memory interface. In our case, we have it already.
+      //         aligned_start_addr_d = axi_addrgen_d.addr;
+      //         // The final address can be found similarly.
+      //         // How many B we requested? No more than (256 << burst_size)
+      //         if (axi_addrgen_d.len << int'(axi_addrgen_q.vew) >= (256 << eff_axi_dw_log_q)) begin
+      //           aligned_next_start_addr_d =
+      //             aligned_addr(aligned_start_addr_d + (256 << eff_axi_dw_log_q), eff_axi_dw_log_q);
+      //           aligned_end_addr_d = aligned_next_start_addr_d - 1;
+      //         end else begin
+      //           aligned_next_start_addr_d =
+      //             aligned_addr(aligned_start_addr_d + (axi_addrgen_d.len << int'(axi_addrgen_q.vew))
+      //             - 1, eff_axi_dw_log_q) + eff_axi_dw_q;
+      //           aligned_end_addr_d = aligned_next_start_addr_d - 1;
+      //         end
+      //         // But since AXI requests are aligned in 4 KiB pages, aligned_end_addr must be in the
+      //         // same page as aligned_start_addr
+      //         if (aligned_start_addr_d[AxiAddrWidth-1:12] != aligned_end_addr_d[AxiAddrWidth-1:12]) begin
+      //           aligned_end_addr_d        = {aligned_start_addr_d[AxiAddrWidth-1:12], 12'hFFF};
+      //           aligned_next_start_addr_d = {                       next_2page_msb_d, 12'h000};
+      //         end*/
+              
+      //       end else if (state_q != ADDRGEN_IDX_OP) begin
+
+      //         /////////////////////
+      //         //  Strided access //
+      //         /////////////////////
+
+      //         // AR Channel
+      //         if (axi_addrgen_q.is_load) begin
+      //           axi_ar_o = '{
+      //             addr   : axi_addrgen_q.addr,
+      //             len    : 0,
+      //             size   : axi_addrgen_q.vew,
+      //             cache  : CACHE_MODIFIABLE,
+      //             burst  : BURST_INCR,
+      //             default: '0
+      //           };
+      //           axi_ar_valid_o = 1'b1;
+      //         end
+      //         // AW Channel
+      //         else begin
+      //           axi_aw_o = '{
+      //             addr   : axi_addrgen_q.addr,
+      //             len    : 0,
+      //             size   : axi_addrgen_q.vew,
+      //             cache  : CACHE_MODIFIABLE,
+      //             burst  : BURST_INCR,
+      //             default: '0
+      //           };
+      //           axi_aw_valid_o = 1'b1;
+      //         end
+
+      //         // Send this request to the load/store units
+      //         axi_addrgen_queue = '{
+      //           addr   : axi_addrgen_q.addr,
+      //           size   : axi_addrgen_q.vew,
+      //           len    : 0,
+      //           is_load: axi_addrgen_q.is_load
+      //         };
+      //         axi_addrgen_queue_push = 1'b1;
+
+      //         // Account for the requested operands
+      //         axi_addrgen_d.len  = axi_addrgen_q.len - 1;
+      //         // Calculate the addresses for the next iteration, adding the correct stride
+      //         axi_addrgen_d.addr = axi_addrgen_q.addr + axi_addrgen_q.stride;
+
+      //         // Finished generating AXI requests
+      //         if (axi_addrgen_d.len == 0) begin
+      //           addrgen_req_ready   = 1'b1;
+      //           axi_addrgen_state_d = AXI_ADDRGEN_IDLE;
+      //         end
+      //       end else begin
+
+      //         //////////////////////
+      //         //  Indexed access  //
+      //         //////////////////////
+
+      //         if (idx_addr_valid_q) begin
+      //           // We consumed a word
+      //           idx_addr_ready_d = 1'b1;
+
+      //           // AR Channel
+      //           if (axi_addrgen_q.is_load) begin
+      //             axi_ar_o = '{
+      //               addr   : idx_final_addr_q,
+      //               len    : 0,
+      //               size   : axi_addrgen_q.vew,
+      //               cache  : CACHE_MODIFIABLE,
+      //               burst  : BURST_INCR,
+      //               default: '0
+      //             };
+      //             axi_ar_valid_o = 1'b1;
+      //           end
+      //           // AW Channel
+      //           else begin
+      //             axi_aw_o = '{
+      //               addr   : idx_final_addr_q,
+      //               len    : 0,
+      //               size   : axi_addrgen_q.vew,
+      //               cache  : CACHE_MODIFIABLE,
+      //               burst  : BURST_INCR,
+      //               default: '0
+      //             };
+      //             axi_aw_valid_o = 1'b1;
+      //           end
+
+      //           // Send this request to the load/store units
+      //           axi_addrgen_queue = '{
+      //             addr   : idx_final_addr_q,
+      //             size   : axi_addrgen_q.vew,
+      //             len    : 0,
+      //             is_load: axi_addrgen_q.is_load
+      //           };
+      //           axi_addrgen_queue_push = 1'b1;
+
+      //           // Account for the requested operands
+      //           axi_addrgen_d.len = axi_addrgen_q.len - 1;
+
+      //           // Check if the address does generate an exception
+      //           if (is_addr_error(idx_final_addr_q, axi_addrgen_q.vew)) begin
+      //             // Generate an error
+      //             idx_op_error_d          = 1'b1;
+      //             // Forward next vstart info to the dispatcher
+      //             addrgen_error_vl_d      = addrgen_req.len - axi_addrgen_q.len - 1;
+      //             addrgen_req_ready       = 1'b1;
+      //             axi_addrgen_state_d     = AXI_ADDRGEN_IDLE;
+      //           end
+
+      //           // Finished generating AXI requests
+      //           if (axi_addrgen_d.len == 0) begin
+      //             addrgen_req_ready   = 1'b1;
+      //             axi_addrgen_state_d = AXI_ADDRGEN_IDLE;
+      //           end
+      //         end
+      //       end
+      //     end
+      //   end
+      // end
     endcase
   end: axi_addrgen
 
diff --git a/hardware/src/vlsu/global_dispatcher.sv b/hardware/src/vlsu/global_dispatcher.sv
index e4bb34b..94f6432 100644
--- a/hardware/src/vlsu/global_dispatcher.sv
+++ b/hardware/src/vlsu/global_dispatcher.sv
@@ -112,12 +112,12 @@ module global_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
                                 // vl_d = ((|acc_req_i.rs1[$bits(acc_req_i.rs1)-1:$bits(vl_d)]) ||
                                 //     (vlen_t'(acc_req_i.rs1) > vlmax)) ? vlmax : vlen_t'(acc_req_i.rs1);
                                 if (((|acc_req_i.rs1[$bits(acc_req_i.rs1)-1:$bits(vl_d)]) ||
-                                    (vlen_t'(acc_req_i.rs1) > vlmax))) begin
+                                    (vlen_cl_t'(acc_req_i.rs1) > vlmax))) begin
                                     vl_d = vlmax;
-                                end else if (vlen_t'(acc_req_i.rs1) < NrClusters * NrLanes) begin
-                                    vl_d = NrClusters * NrLanes;
+                                end else if (|vlen_cl_t'(acc_req_i.rs1[$clog2(NrClusters * NrLanes)-1:0])) begin
+                                    vl_d = vlen_cl_t'(((acc_req_i.rs1 >> $clog2(NrClusters * NrLanes)) + 1) << $clog2(NrClusters * NrLanes));
                                 end else begin
-                                    vl_d = vlen_t'(acc_req_i.rs1);
+                                    vl_d = vlen_cl_t'(acc_req_i.rs1);
                                 end
                             end
                         end
diff --git a/hardware/src/vlsu/shuffle_stage.sv b/hardware/src/vlsu/shuffle_stage.sv
index 9f61521..ec6412d 100644
--- a/hardware/src/vlsu/shuffle_stage.sv
+++ b/hardware/src/vlsu/shuffle_stage.sv
@@ -213,8 +213,9 @@ logic [NumBuffers-1:0] shift_d, shift_q;                           // For each b
 logic [NumBuffers-1:0] buf_valid_d, buf_valid_q;
 logic r_ready_buf, r_ready_buf_q;
 
-logic rd_buffer_en; 
+logic rd_buffer_en, rd_buffer_en_last_stage; 
 assign rd_buffer_en = rd_tracker_q[rd_issue_pnt_q[0]].buffer_en;
+assign rd_buffer_en_last_stage = rd_tracker_q[rd_issue_pnt_q[1]].buffer_en;
 
 // Write packets
 logic [NrClusters-1:0] [ClusterAxiDataWidth*2-1:0]  wrbuf_d, wrbuf_q;
@@ -504,8 +505,10 @@ for (genvar c=0; c < NrClusters; c++) begin
 
   // Reads  
   assign r_data_in[0][c] = rd_buffer_en ? '0 : axi_resp_i[c].r;             // Copy input resp to first stage
-  assign axi_resp_o[c].r = rd_buffer_en ? axi_resp_buf_out[c].r : r_data_out[NumStages-1][c];  // Copy output resp from last stage
-  assign axi_resp_o[c].r_valid = rd_buffer_en ? axi_resp_buf_out[c].r_valid : r_valid_o[c];          // Copy valid from stream fork to output
+  // assign axi_resp_o[c].r = rd_buffer_en ? axi_resp_buf_out[c].r : r_data_out[NumStages-1][c];  // Copy output resp from last stage
+  // assign axi_resp_o[c].r_valid = rd_buffer_en ? axi_resp_buf_out[c].r_valid : r_valid_o[c];          // Copy valid from stream fork to output
+  assign axi_resp_o[c].r = rd_buffer_en_last_stage ? axi_resp_buf_out[c].r : r_data_out[NumStages-1][c];  // Copy output resp from last stage
+  assign axi_resp_o[c].r_valid = rd_buffer_en_last_stage ? axi_resp_buf_out[c].r_valid : r_valid_o[c];          // Copy valid from stream fork to output
 
   // Writes
   assign axi_resp_o[c].w_ready = wr_buffer_en ? ~wrbuf_full[c] : w_ready_o[c];          // Copy ready from stream join output to response
diff --git a/hardware/src/vlsu/vldu.sv b/hardware/src/vlsu/vldu.sv
index 00b87dd..56a6a7d 100644
--- a/hardware/src/vlsu/vldu.sv
+++ b/hardware/src/vlsu/vldu.sv
@@ -1,4 +1,4 @@
-// Copyright 2021-2025 ETH Zurich and University of Bologna.
+// Copyright 2021 ETH Zurich and University of Bologna.
 // Solderpad Hardware License, Version 0.51, see LICENSE for details.
 // SPDX-License-Identifier: SHL-0.51
 //
@@ -8,8 +8,8 @@
 // upon receiving vector memory operations.
 
 module vldu import ara_pkg::*; import rvv_pkg::*; #(
-    parameter  int  unsigned NrLanes = 0,
-    parameter  type          vaddr_t = logic,  // Type used to address vector register file elements
+    parameter  int  unsigned NrLanes   = 0,
+    parameter  type          vaddr_t   = logic,  // Type used to address vector register file elements
     // AXI Interface parameters
     parameter  int  unsigned AxiDataWidth = 0,
     parameter  int  unsigned AxiAddrWidth = 0,
@@ -52,10 +52,43 @@ module vldu import ara_pkg::*; import rvv_pkg::*; #(
   );
 
   import cf_math_pkg::idx_width;
-  import axi_pkg::beat_lower_byte;
-  import axi_pkg::beat_upper_byte;
+  // import axi_pkg::beat_lower_byte;
+  // import axi_pkg::beat_upper_byte;
   import axi_pkg::BURST_INCR;
 
+  ////////////////
+  //  MASK cut  //
+  ////////////////
+
+  strb_t [NrLanes-1:0] mask_q;
+  logic  [NrLanes-1:0] mask_valid_d, mask_valid_q;
+  logic                mask_ready_d;
+  logic  [NrLanes-1:0] mask_ready_q;
+  // Insn queue related signal
+  pe_req_t vinsn_issue_d, vinsn_issue_q;
+  logic vinsn_issue_valid;
+
+  for (genvar l = 0; l < NrLanes; l++) begin
+    spill_register #(
+      .T(strb_t)
+    ) i_vldu_mask_register (
+      .clk_i     (clk_i           ),
+      .rst_ni    (rst_ni          ),
+      .data_o    (mask_q[l]       ),
+      .valid_o   (mask_valid_q[l] ),
+      .ready_i   (mask_ready_d    ),
+      .data_i    (mask_i[l]       ),
+      .valid_i   (mask_valid_d[l] ),
+      .ready_o   (mask_ready_q[l] )
+    );
+
+    // Sample only SLDU mask valid
+    assign mask_valid_d[l] = mask_valid_i[l] & ~vinsn_issue_q.vm & vinsn_issue_valid;
+  end
+
+  // Don't upset the masku with a spurious ready
+  assign mask_ready_o = mask_ready_q[0] & mask_valid_i[0] & ~vinsn_issue_q.vm & vinsn_issue_valid;
+
   ////////////////////////////////
   //  Vector instruction queue  //
   ////////////////////////////////
@@ -91,8 +124,6 @@ module vldu import ara_pkg::*; import rvv_pkg::*; #(
   assign vinsn_queue_full = (vinsn_queue_q.commit_cnt == VInsnQueueDepth);
 
   // Do we have a vector instruction ready to be issued?
-  pe_req_t vinsn_issue_d, vinsn_issue_q;
-  logic    vinsn_issue_valid;
   assign vinsn_issue_d     = vinsn_queue_d.vinsn[vinsn_queue_d.issue_pnt];
   assign vinsn_issue_valid = (vinsn_queue_q.issue_cnt != '0);
 
@@ -136,7 +167,7 @@ module vldu import ara_pkg::*; import rvv_pkg::*; #(
   // reading from and writing into the lanes (read_pnt).
   logic     [idx_width(ResultQueueDepth)-1:0]   result_queue_write_pnt_d, result_queue_write_pnt_q;
   logic     [idx_width(ResultQueueDepth)-1:0]   result_queue_read_pnt_d, result_queue_read_pnt_q;
-  // We need to count how many valid elements are there in this result queue.
+  // We need to count how many valid elements (payload_t) are there in this result queue.
   logic     [idx_width(ResultQueueDepth):0]     result_queue_cnt_d, result_queue_cnt_q;
   // Vector to register the final grants from the operand requesters, which indicate
   // that the result was actually written in the VRF (while the normal grant just says
@@ -174,33 +205,57 @@ module vldu import ara_pkg::*; import rvv_pkg::*; #(
   logic [NrVInsn-1:0] vinsn_running_d, vinsn_running_q;
 
   // Interface with the main sequencer
-  pe_resp_t pe_resp;
+  pe_resp_t pe_resp_d;
 
   // Remaining bytes of the current instruction in the issue phase
-  vlen_t issue_cnt_d, issue_cnt_q;
+  vlen_t issue_cnt_bytes_d, issue_cnt_bytes_q;
   // Remaining bytes of the current instruction in the commit phase
-  vlen_t commit_cnt_d, commit_cnt_q;
+  vlen_t commit_cnt_bytes_d, commit_cnt_bytes_q;
 
   // Pointers
   //
   // We need several pointers to copy data from the memory interface
   // into the VRF. Namely, we need:
   // - A counter of how many beats are left in the current AXI burst
-  axi_pkg::len_t len_d, len_q;
+  axi_pkg::len_t                           axi_len_d, axi_len_q;
   // - A pointer to which byte in the current R beat we are reading data from.
-  logic [idx_width(AxiDataWidth/8):0]      r_pnt_d, r_pnt_q;
+  logic [idx_width(AxiDataWidth/8):0]      axi_r_byte_pnt_d, axi_r_byte_pnt_q;
   // - A pointer to which byte in the full VRF word we are writing data into.
-  logic [idx_width(DataWidth*NrLanes/8):0] vrf_pnt_d, vrf_pnt_q;
+  logic [idx_width(DataWidth*NrLanes/8):0] vrf_word_byte_pnt_d, vrf_word_byte_pnt_q;
+  // - A pointer that indicates the start byte in the vrf word.
+  logic [$clog2(8*NrLanes)-1:0] vrf_word_start_byte;
+
+  // A counter that follows the vrf_word_byte_pnt pointer, but without the vstart information
+  // We can compare this counter witht the issue_cnt_bytes counter to find the last byte in
+  // our transaction
+  logic [idx_width(DataWidth*NrLanes/8):0] vrf_word_byte_cnt_d, vrf_word_byte_cnt_q;
+
+  // When vstart > 0, the very first payload written to the VRF contains less than
+  // (8 * NrLanes) bytes.
+  logic [$clog2(8*NrLanes):0] first_payload_byte_d, first_payload_byte_q;
+  logic [$clog2(8*NrLanes):0] vrf_eff_write_bytes;
+  // Same thing, but for the commit (resqueue -> VRF)
+  // Track if this VRF write is the first one for this instruction
+  logic first_result_queue_read_d, first_result_queue_read_q;
+  logic [$clog2(8*NrLanes):0] res_queue_eff_write_bytes;
+
+  // Signal that the current burst is having an exception
+  logic ldu_current_burst_exception_d;
+
+  // Counter to increase the VRF write address.
+  vlen_t seq_word_wr_offset_d, seq_word_wr_offset_q;
+
+  localparam unsigned DataWidthB = DataWidth / 8;
 
   always_comb begin: p_vldu
     // Maintain state
     vinsn_queue_d = vinsn_queue_q;
-    issue_cnt_d   = issue_cnt_q;
-    commit_cnt_d  = commit_cnt_q;
+    issue_cnt_bytes_d   = issue_cnt_bytes_q;
+    commit_cnt_bytes_d  = commit_cnt_bytes_q;
 
-    len_d     = len_q;
-    r_pnt_d   = r_pnt_q;
-    vrf_pnt_d = vrf_pnt_q;
+    axi_len_d           = axi_len_q;
+    axi_r_byte_pnt_d    = axi_r_byte_pnt_q;
+    vrf_word_byte_pnt_d = vrf_word_byte_pnt_q;
 
     result_queue_d           = result_queue_q;
     result_queue_valid_d     = result_queue_valid_q;
@@ -210,16 +265,28 @@ module vldu import ara_pkg::*; import rvv_pkg::*; #(
 
     result_final_gnt_d = result_final_gnt_q;
 
+    seq_word_wr_offset_d = seq_word_wr_offset_q;
+    first_payload_byte_d = first_payload_byte_q;
+    vrf_word_byte_cnt_d  = vrf_word_byte_cnt_q;
+
     // Vector instructions currently running
     vinsn_running_d = vinsn_running_q & pe_vinsn_running_i;
 
     // We are not ready, by default
     axi_addrgen_req_ready_o = 1'b0;
-    pe_resp                 = '0;
+    pe_resp_d               = '0;
     axi_r_ready_o           = 1'b0;
-    mask_ready_o            = 1'b0;
+    mask_ready_d            = 1'b0;
     load_complete_o         = 1'b0;
 
+    first_result_queue_read_d = first_result_queue_read_q;
+
+    // Normally write multiple of resqueue width
+    vrf_eff_write_bytes       = (NrLanes * DataWidthB);
+    res_queue_eff_write_bytes = (NrLanes * DataWidthB);
+
+    ldu_current_burst_exception_d = 1'b0;
+
     // Inform the main sequencer if we are idle
     pe_req_ready_o = !vinsn_queue_full;
 
@@ -231,129 +298,164 @@ module vldu import ara_pkg::*; import rvv_pkg::*; #(
     // - There is an R beat available.
     // - The Address Generator sent us the data about the corresponding AR beat
     // - There is place in the result queue to write the data read from the R channel
+    // - This request did not generate an exception
     if (axi_r_valid_i && axi_addrgen_req_valid_i
-        && axi_addrgen_req_i.is_load && !result_queue_full) begin
-      // Bytes valid in the current R beat
-      // If non-unit strided load, we do not progress within the beat
-      automatic shortint unsigned lower_byte = beat_lower_byte(axi_addrgen_req_i.addr,
-        axi_addrgen_req_i.size, axi_addrgen_req_i.len, BURST_INCR, AxiDataWidth/8, len_q);
-      automatic shortint unsigned upper_byte = beat_upper_byte(axi_addrgen_req_i.addr,
-        axi_addrgen_req_i.size, axi_addrgen_req_i.len, BURST_INCR, AxiDataWidth/8, len_q);
+        && axi_addrgen_req_i.is_load && !result_queue_full) begin : axi_r_beat_read
+      // // Bytes valid in the current R beat
+      // // If non-unit strided load, we do not progress within the beat
+      // automatic logic [idx_width(AxiDataWidth/8)-1:0] lower_byte = beat_lower_byte(axi_addrgen_req_i.addr,
+      //   axi_addrgen_req_i.size, axi_addrgen_req_i.len, BURST_INCR, AxiDataWidth/8, axi_len_q);
+      // automatic logic [idx_width(AxiDataWidth/8)-1:0] upper_byte = beat_upper_byte(axi_addrgen_req_i.addr,
+      //   axi_addrgen_req_i.size, axi_addrgen_req_i.len, BURST_INCR, AxiDataWidth/8, axi_len_q);
 
       // Is there a vector instruction ready to be issued?
       // Do we have the operands for it?
-      if (vinsn_issue_valid && (vinsn_issue_q.vm || (|mask_valid_i))) begin
+      if (vinsn_issue_valid && (vinsn_issue_q.vm || (|mask_valid_q))) begin : operands_valid
         // Account for the issued bytes
         // How many bytes are valid in this VRF word
-        automatic vlen_t vrf_valid_bytes   = NrLanes * 8 - vrf_pnt_q;
+        automatic vlen_t vrf_valid_bytes   = (NrLanes * DataWidthB) - vrf_word_byte_pnt_q;
         // How many bytes are valid in this instruction
-        automatic vlen_t vinsn_valid_bytes = issue_cnt_q - vrf_pnt_q;
+        automatic vlen_t vinsn_valid_bytes = issue_cnt_bytes_q - vrf_word_byte_cnt_q;
         // How many bytes are valid in this AXI word
         automatic vlen_t axi_valid_bytes   = AxiDataWidth/8; // upper_byte - lower_byte - r_pnt_q + 1;
 
+
         // How many bytes are we committing?
         automatic logic [idx_width(DataWidth*NrLanes/8):0] valid_bytes;
-        valid_bytes = issue_cnt_q < NrLanes * 8     ? vinsn_valid_bytes : vrf_valid_bytes;
-        valid_bytes = valid_bytes < axi_valid_bytes ? valid_bytes       : axi_valid_bytes;
+        valid_bytes = (issue_cnt_bytes_q < (NrLanes * DataWidthB)) ? vinsn_valid_bytes : vrf_valid_bytes;
+        valid_bytes = (valid_bytes       < axi_valid_bytes       ) ? valid_bytes       : axi_valid_bytes;
 
-        r_pnt_d   = r_pnt_q + valid_bytes;
-        vrf_pnt_d = vrf_pnt_q + valid_bytes;
+        // Bump R beat and VRF word pointers
+        axi_r_byte_pnt_d    = axi_r_byte_pnt_q + valid_bytes;
+        vrf_word_byte_pnt_d = vrf_word_byte_pnt_q + valid_bytes;
+        vrf_word_byte_cnt_d = vrf_word_byte_cnt_q + valid_bytes;
 
         // Copy data from the R channel into the result queue
-        for (int axi_byte = 0; axi_byte < AxiDataWidth/8; axi_byte++) begin
+        for (int unsigned axi_byte = 0; axi_byte < AxiDataWidth/8; axi_byte++) begin : axi_r_to_result_queue
           // Map axi_byte to the corresponding byte in the VRF word (sequential)
-          // And then shuffle it - shuffling has 2 components
-          // First AxiDataWidth/8 byte indices are found from shuffle_index 
-          // Second, for the next axi packets only the additional offset change depending on vrf_pnt_q
-          automatic int vrf_byte       = shuffle_index(axi_byte, NrLanes, vinsn_issue_q.vtype.vsew);
-          automatic int vrf_seq_offset = shuffle_offset(vrf_pnt_q, NrLanes, vinsn_issue_q.vtype.vsew);
-          vrf_byte = vrf_byte + vrf_seq_offset;
+          automatic int unsigned vrf_seq_byte = axi_byte - axi_r_byte_pnt_q + vrf_word_byte_pnt_q;
+          // Follow the vrf_seq_byte, but without the vstart information
+          automatic int unsigned vrf_seq_byte_cnt = axi_byte - axi_r_byte_pnt_q + vrf_word_byte_cnt_q;
+          // And then shuffle it
+          automatic int unsigned vrf_byte = shuffle_index(vrf_seq_byte, NrLanes, vinsn_issue_q.vtype.vsew);
 
           // Is this byte a valid byte in the VRF word?
-          if (axi_byte < issue_cnt_q && axi_byte < NrLanes * 8) begin
+          // We compare vrf_seq_byte_cnt since vrf_seq_byte contains also the vstart contribution, while the issue_cnt_bytes
+          // counter does not.
+          if (vrf_seq_byte_cnt < issue_cnt_bytes_q && vrf_seq_byte < (NrLanes * DataWidthB)) begin : is_vrf_byte
             // At which lane, and what is the byte offset in that lane, of the byte vrf_byte?
-            automatic int vrf_lane   = vrf_byte >> 3;
-            automatic int vrf_offset = vrf_byte[2:0];
+            automatic int unsigned vrf_offset = vrf_byte[2:0];
+            // Make sure this index wraps around the number of lane
+            automatic int unsigned vrf_lane = (vrf_byte >> 3);
 
             // Copy data and byte strobe
             result_queue_d[result_queue_write_pnt_q][vrf_lane].wdata[8*vrf_offset +: 8] =
               axi_r_i.data[8*axi_byte +: 8];
             result_queue_d[result_queue_write_pnt_q][vrf_lane].be[vrf_offset] =
-              vinsn_issue_q.vm || mask_i[vrf_lane][vrf_offset];
-          end
-        end
+              vinsn_issue_q.vm || mask_q[vrf_lane][vrf_offset];
+          end : is_vrf_byte
+        end : axi_r_to_result_queue
+
+        for (int unsigned lane = 0; lane < NrLanes; lane++) begin : compute_vrf_addr
+          // vstart value local ot the lane
+          automatic vlen_t vstart_lane;
 
-        // Initialize id and addr fields of the result queue requests
-        for (int lane = 0; lane < NrLanes; lane++) begin
+          // vstart of the lanes that we are writing to in this cycle
+          vstart_lane = vinsn_issue_q.vstart / NrLanes;
+
+          // Store in result queue
+          result_queue_d[result_queue_write_pnt_q][lane].addr = vaddr(vinsn_issue_q.vd, NrLanes) + (vstart_lane >> (EW64 - vinsn_issue_q.vtype.vsew)) + seq_word_wr_offset_q;
           result_queue_d[result_queue_write_pnt_q][lane].id   = vinsn_issue_q.id;
-          result_queue_d[result_queue_write_pnt_q][lane].addr = vaddr(vinsn_issue_q.vd, NrLanes) +
-            (((vinsn_issue_q.vl - (issue_cnt_q >> int'(vinsn_issue_q.vtype.vsew))) / NrLanes) >>
-            (int'(EW64) - int'(vinsn_issue_q.vtype.vsew)));
-        end
-      end
+        end : compute_vrf_addr
+      end : operands_valid
 
       // We have a word ready to be sent to the lanes
-      if (vrf_pnt_d == NrLanes*8 || vrf_pnt_d == issue_cnt_q) begin
+      if (vrf_word_byte_pnt_d == (NrLanes * DataWidthB) || vrf_word_byte_cnt_d == issue_cnt_bytes_q) begin : vrf_word_ready
         // Increment result queue pointers and counters
         result_queue_cnt_d += 1;
-        if (result_queue_write_pnt_q == ResultQueueDepth-1)
+        if (result_queue_write_pnt_q == ResultQueueDepth-1) begin : result_queue_write_pnt_overflow
           result_queue_write_pnt_d = '0;
-        else
+        end : result_queue_write_pnt_overflow
+        else begin : result_queue_write_pnt_increment
           result_queue_write_pnt_d = result_queue_write_pnt_q + 1;
+        end : result_queue_write_pnt_increment
 
         // Trigger the request signal
         result_queue_valid_d[result_queue_write_pnt_q] = {NrLanes{1'b1}};
 
+        // Increase the VRF-write sequential counter
+        seq_word_wr_offset_d = seq_word_wr_offset_q + 1;
+
         // Acknowledge the mask operands
-        mask_ready_o = !vinsn_issue_q.vm;
+        mask_ready_d = !vinsn_issue_q.vm;
 
         // Reset the pointer in the VRF word
-        vrf_pnt_d   = '0;
+        vrf_word_byte_pnt_d   = '0;
+        vrf_word_byte_cnt_d   = '0;
         // Account for the results that were issued
-        issue_cnt_d = issue_cnt_q - NrLanes * 8;
-        if (issue_cnt_q < NrLanes * 8)
-          issue_cnt_d = '0;
-      end
+        if (seq_word_wr_offset_q) begin
+          vrf_eff_write_bytes = (NrLanes * DataWidthB);
+        end else begin
+          // First payload of the vector instruction
+          vrf_eff_write_bytes = first_payload_byte_q;
+        end
+        issue_cnt_bytes_d = issue_cnt_bytes_q - vrf_eff_write_bytes;
+        if (issue_cnt_bytes_q < vrf_eff_write_bytes) begin : issue_cnt_bytes_overflow
+          issue_cnt_bytes_d = '0;
+        end : issue_cnt_bytes_overflow
+      end : vrf_word_ready
 
       // Consumed all valid bytes in this R beat
-      if (r_pnt_d == AxiDataWidth/8 || issue_cnt_d == '0) begin
+      if ((axi_r_byte_pnt_d == AxiDataWidth/8) || (issue_cnt_bytes_d == '0)) begin : axi_r_beat_finish
         // Request another beat
         axi_r_ready_o = 1'b1;
-        r_pnt_d       = '0;
+        axi_r_byte_pnt_d   = '0;
         // Account for the beat we consumed
-        len_d         = len_q + 1;
-      end
+        axi_len_d     = axi_len_q + 1;
+      end : axi_r_beat_finish
 
       // Consumed all beats from this burst
-      if ($unsigned(len_d) == axi_pkg::len_t'($unsigned(axi_addrgen_req_i.len) + 1)) begin
+      if ($unsigned(axi_len_d) == axi_pkg::len_t'($unsigned(axi_addrgen_req_i.len) + 1)) begin : axi_finish
         // Reset AXI pointers
-        len_d                   = '0;
-        r_pnt_d                 = '0;
+        axi_len_d               = '0;
+        axi_r_byte_pnt_d             = '0;
         // Wait for another AXI request
         axi_addrgen_req_ready_o = 1'b1;
-      end
+      end : axi_finish
 
       // Finished issuing results
-      if (vinsn_issue_valid && issue_cnt_d == '0) begin
+      if (vinsn_issue_valid && issue_cnt_bytes_d == '0 ) begin : vrf_results_finish
         // Increment vector instruction queue pointers and counters
         vinsn_queue_d.issue_cnt -= 1;
-        if (vinsn_queue_q.issue_pnt == VInsnQueueDepth-1)
+        if (vinsn_queue_q.issue_pnt == (VInsnQueueDepth-1)) begin : issue_pnt_overflow
           vinsn_queue_d.issue_pnt = '0;
-        else
+        end : issue_pnt_overflow
+        else begin : issue_pnt_increment
           vinsn_queue_d.issue_pnt += 1;
+        end : issue_pnt_increment
 
         // Prepare for the next vector instruction
-        if (vinsn_queue_d.issue_cnt != 0)
-          issue_cnt_d = vinsn_queue_q.vinsn[vinsn_queue_d.issue_pnt].vl << int'(vinsn_queue_q.vinsn[
-              vinsn_queue_d.issue_pnt].vtype.vsew);
-      end
-    end
+        if (vinsn_queue_d.issue_cnt != 0) begin : issue_cnt_bytes_update
+          issue_cnt_bytes_d = (
+                                vinsn_queue_q.vinsn[vinsn_queue_d.issue_pnt].vl
+                                - vinsn_queue_q.vinsn[vinsn_queue_d.issue_pnt].vstart
+                              ) << unsigned'(vinsn_queue_q.vinsn[vinsn_queue_d.issue_pnt].vtype.vsew);
+          // Prepare the VRF start pointer
+          vrf_word_start_byte  = vinsn_issue_d.vstart[$clog2(8*NrLanes)-1:0] << vinsn_issue_d.vtype.vsew;
+          vrf_word_byte_pnt_d  = {1'b0, vrf_word_start_byte[$clog2(8*NrLanes)-1:0]};
+          vrf_word_byte_cnt_d  = '0;
+          seq_word_wr_offset_d = '0;
+          // The first payload byte width for this vload
+          first_payload_byte_d = (NrLanes * DataWidthB) - vrf_word_start_byte[$clog2(8*NrLanes)-1:0];
+        end : issue_cnt_bytes_update
+      end : vrf_results_finish
+    end : axi_r_beat_read
 
     //////////////////////////////////
     //  Write results into the VRF  //
     //////////////////////////////////
 
-    for (int lane = 0; lane < NrLanes; lane++) begin: result_write
+    for (int unsigned lane = 0; lane < NrLanes; lane++) begin: vrf_result_write
       ldu_result_req_o[lane]   = result_queue_valid_q[result_queue_read_pnt_q][lane];
       ldu_result_addr_o[lane]  = result_queue_q[result_queue_read_pnt_q][lane].addr;
       ldu_result_id_o[lane]    = result_queue_q[result_queue_read_pnt_q][lane].id;
@@ -365,39 +467,53 @@ module vldu import ara_pkg::*; import rvv_pkg::*; #(
 
       // Received a grant from the VRF.
       // Deactivate the request, but do not bump the pointers for now.
-      if (ldu_result_req_o[lane] && ldu_result_gnt_i[lane]) begin
+      if (ldu_result_req_o[lane] && ldu_result_gnt_i[lane]) begin : vrf_grant
         result_queue_valid_d[result_queue_read_pnt_q][lane] = 1'b0;
         result_queue_d[result_queue_read_pnt_q][lane]       = '0;
         // Reset the final gnt vector since we are now waiting for another final gnt
         result_final_gnt_d[lane] = 1'b0;
-      end
-    end: result_write
+      end : vrf_grant
+    end: vrf_result_write
+
+    // How many result bytes can possibly be committed this cycle?
+    res_queue_eff_write_bytes = (NrLanes * DataWidthB);
+    // If vstart > 0, the first payload can contain less than (NrLanes * DataWidthB) Bytes
+    if (first_result_queue_read_q) begin
+      res_queue_eff_write_bytes = first_payload_byte_q;
+    end
 
     // All lanes accepted the VRF request
     // Wait for all the final grants, to be sure that all the results were written back
     if (!(|result_queue_valid_d[result_queue_read_pnt_q]) &&
-      (&result_final_gnt_d || commit_cnt_q > (NrLanes * 8)))
+      (&result_final_gnt_d || commit_cnt_bytes_q > (NrLanes * DataWidthB))) begin : wait_for_write_back
       // There is something waiting to be written
-      if (!result_queue_empty) begin
+      if (!result_queue_empty) begin : result_available
         // Increment the read pointer
-        if (result_queue_read_pnt_q == ResultQueueDepth-1)
+        if (result_queue_read_pnt_q == (ResultQueueDepth-1)) begin : result_queue_read_pnt_overflow
           result_queue_read_pnt_d = 0;
-        else
+        end : result_queue_read_pnt_overflow
+        else begin  : result_queue_read_pnt_increment
           result_queue_read_pnt_d = result_queue_read_pnt_q + 1;
+        end : result_queue_read_pnt_increment
 
         // Decrement the counter of results waiting to be written
         result_queue_cnt_d -= 1;
 
+        // The next write will surely not be the first one anymore
+        first_result_queue_read_d = 1'b0;
+
         // Decrement the counter of remaining vector elements waiting to be written
-        commit_cnt_d = commit_cnt_q - NrLanes * 8;
-        if (commit_cnt_q < (NrLanes * 8))
-          commit_cnt_d = '0;
-      end
+        commit_cnt_bytes_d = commit_cnt_bytes_q - res_queue_eff_write_bytes;
+        if (commit_cnt_bytes_q < (NrLanes * DataWidthB)) begin : commit_cnt_bytes_overflow
+          commit_cnt_bytes_d = '0;
+        end : commit_cnt_bytes_overflow
+      end : result_available
+    end : wait_for_write_back
 
     // Finished committing the results of a vector instruction
-    if (vinsn_commit_valid && commit_cnt_d == '0) begin
+    if (vinsn_commit_valid && commit_cnt_bytes_d == '0) begin : vinsn_done
       // Mark the vector instruction as being done
-      pe_resp.vinsn_done[vinsn_commit.id] = 1'b1;
+      pe_resp_d.vinsn_done[vinsn_commit.id] = 1'b1;
 
       // Signal complete load
       load_complete_o = 1'b1;
@@ -410,52 +526,77 @@ module vldu import ara_pkg::*; import rvv_pkg::*; #(
         vinsn_queue_d.commit_pnt += 1;
 
       // Update the commit counter for the next instruction
-      if (vinsn_queue_d.commit_cnt != '0)
-        commit_cnt_d = vinsn_queue_q.vinsn[vinsn_queue_d.commit_pnt].vl << int'(vinsn_queue_q.vinsn[
-            vinsn_queue_d.commit_pnt].vtype.vsew);
-    end
+      if (vinsn_queue_d.commit_cnt != '0) begin
+        first_result_queue_read_d = 1'b1;
+        commit_cnt_bytes_d = (
+                               vinsn_queue_q.vinsn[vinsn_queue_d.commit_pnt].vl
+                                - vinsn_queue_q.vinsn[vinsn_queue_d.commit_pnt].vstart
+                              ) << unsigned'(vinsn_queue_q.vinsn[vinsn_queue_d.commit_pnt].vtype.vsew);
+      end
+    end : vinsn_done
 
     //////////////////////////////
     //  Accept new instruction  //
     //////////////////////////////
 
     if (!vinsn_queue_full && pe_req_valid_i && !vinsn_running_q[pe_req_i.id] &&
-      pe_req_i.vfu == VFU_LoadUnit) begin
+      pe_req_i.vfu == VFU_LoadUnit) begin : pe_req_valid
       vinsn_queue_d.vinsn[vinsn_queue_q.accept_pnt] = pe_req_i;
       vinsn_running_d[pe_req_i.id]                  = 1'b1;
 
       // Initialize counters
-      if (vinsn_queue_d.issue_cnt == '0)
-        issue_cnt_d = pe_req_i.vl << int'(pe_req_i.vtype.vsew);
-      if (vinsn_queue_d.commit_cnt == '0)
-        commit_cnt_d = pe_req_i.vl << int'(pe_req_i.vtype.vsew);
+      if (vinsn_queue_d.issue_cnt == '0) begin : issue_cnt_bytes_init
+        issue_cnt_bytes_d = (pe_req_i.vl - pe_req_i.vstart) << unsigned'(pe_req_i.vtype.vsew);
+      end : issue_cnt_bytes_init
+      if (vinsn_queue_d.commit_cnt == '0) begin : commit_cnt_bytes_init
+        first_result_queue_read_d = 1'b1;
+        commit_cnt_bytes_d = (pe_req_i.vl - pe_req_i.vstart) << unsigned'(pe_req_i.vtype.vsew);
+      end : commit_cnt_bytes_init
+
+      // New instruction with new vstart. Initialize the vrf byte ptr
+      if (vinsn_queue_d.issue_cnt == '0) begin
+        vrf_word_start_byte  = pe_req_i.vstart[$clog2(8*NrLanes)-1:0] << pe_req_i.vtype.vsew;
+        vrf_word_byte_pnt_d  = {1'b0, vrf_word_start_byte[$clog2(8*NrLanes)-1:0]};
+        vrf_word_byte_cnt_d  = '0;
+        seq_word_wr_offset_d = '0;
+        // The first payload byte width for this vload
+        first_payload_byte_d = (NrLanes * DataWidthB) - vrf_word_start_byte[$clog2(8*NrLanes)-1:0];
+      end
 
       // Bump pointers and counters of the vector instruction queue
       vinsn_queue_d.accept_pnt += 1;
       vinsn_queue_d.issue_cnt += 1;
       vinsn_queue_d.commit_cnt += 1;
-    end
+    end : pe_req_valid
   end: p_vldu
 
   always_ff @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
-      vinsn_running_q    <= '0;
-      issue_cnt_q        <= '0;
-      commit_cnt_q       <= '0;
-      len_q              <= '0;
-      r_pnt_q            <= '0;
-      vrf_pnt_q          <= '0;
-      pe_resp_o          <= '0;
-      result_final_gnt_q <= '0;
+      vinsn_running_q               <= '0;
+      issue_cnt_bytes_q             <= '0;
+      commit_cnt_bytes_q            <= '0;
+      axi_len_q                     <= '0;
+      axi_r_byte_pnt_q              <= '0;
+      vrf_word_byte_pnt_q           <= '0;
+      pe_resp_o                     <= '0;
+      result_final_gnt_q            <= '0;
+      seq_word_wr_offset_q          <= '0;
+      first_payload_byte_q          <= '0;
+      vrf_word_byte_cnt_q           <= '0;
+      first_result_queue_read_q     <= 1'b0;
     end else begin
-      vinsn_running_q    <= vinsn_running_d;
-      issue_cnt_q        <= issue_cnt_d;
-      commit_cnt_q       <= commit_cnt_d;
-      len_q              <= len_d;
-      r_pnt_q            <= r_pnt_d;
-      vrf_pnt_q          <= vrf_pnt_d;
-      pe_resp_o          <= pe_resp;
-      result_final_gnt_q <= result_final_gnt_d;
+      vinsn_running_q               <= vinsn_running_d;
+      issue_cnt_bytes_q             <= issue_cnt_bytes_d;
+      commit_cnt_bytes_q            <= commit_cnt_bytes_d;
+      axi_len_q                     <= axi_len_d;
+      axi_r_byte_pnt_q              <= axi_r_byte_pnt_d;
+      vrf_word_byte_pnt_q           <= vrf_word_byte_pnt_d;
+      pe_resp_o                     <= pe_resp_d;
+      result_final_gnt_q            <= result_final_gnt_d;
+      seq_word_wr_offset_q          <= seq_word_wr_offset_d;
+      first_payload_byte_q          <= first_payload_byte_d;
+      vrf_word_byte_cnt_q           <= vrf_word_byte_cnt_d;
+      first_result_queue_read_q     <= first_result_queue_read_d;
     end
   end
 

From fb7dd9d85c88781c8d3d96cf2d970b48ce574759 Mon Sep 17 00:00:00 2001
From: Hong Pang <hopang@larain5.ee.ethz.ch>
Date: Fri, 17 Oct 2025 16:04:51 +0200
Subject: [PATCH 03/37] [HW/SW] [SW] 1. Fix bug in dotproduct kernel on red vl;
 2. Align data generation with 4*Nrlanes*NrClusters for imatmul and iconv2d
 kernels; [HW] 1. Synchronize instruction of Ara and GLSU; 2. VSE: support the
 case where number of elements stored is not multiplier of NrLanes*NrClusters;
 3. VSE: axi write req controlling signal fix; 4. Fix SLIDEDOWN operation
 issue; 5. Recalculate slide operation to ensure vl is multiplier of
 NrLanes*NrClusters for inter-cluster ring interaction

---
 apps/common/default_args.mk            |  13 +-
 apps/fdotproduct/kernel/fdotproduct.c  |  18 ++-
 apps/iconv2d/main.c                    |  17 ++-
 apps/iconv2d/script/gen_data.py        |  12 +-
 apps/imatmul/main.c                    |  10 +-
 apps/imatmul/script/gen_data.py        |   8 +-
 hardware/include/ara_pkg.sv            |   5 +
 hardware/src/ara_cluster.sv            |  35 ++++-
 hardware/src/ara_dispatcher.sv         |  14 +-
 hardware/src/ara_sequencer.sv          |   1 +
 hardware/src/sldu/sldu.sv              |  60 +++++++--
 hardware/src/vlsu/addrgen.sv           |  83 ++++++------
 hardware/src/vlsu/align_stage.sv       |  29 ++--
 hardware/src/vlsu/global_dispatcher.sv | 175 +++++++++++++++----------
 hardware/src/vlsu/global_ldst.sv       |  57 ++++++--
 hardware/src/vlsu/shuffle_stage.sv     |  20 ++-
 hardware/src/vlsu/vldu.sv              |   2 +-
 hardware/src/vlsu/vstu.sv              |  47 ++++---
 18 files changed, 394 insertions(+), 212 deletions(-)

diff --git a/apps/common/default_args.mk b/apps/common/default_args.mk
index 07205cf..bc0fa22 100644
--- a/apps/common/default_args.mk
+++ b/apps/common/default_args.mk
@@ -1,16 +1,17 @@
 # Default app parameters
 
 # Matrix sizes
-def_args_imatmul     ?= "64 64 64"
-def_args_fmatmul     ?= "64 64 64"
+def_args_imatmul     ?= "32 32 32"
+def_args_fmatmul     ?= "32 32 32"
 # Matrix size, filter size
-def_args_iconv2d     ?= "112 7"
-def_args_fconv2d     ?= "112 7"
+def_args_iconv2d     ?= "32 3"
+def_args_fconv2d     ?= "128 128 3"
+# def_args_fconv2d     ?= "128 128 7"
 def_args_fconv3d     ?= "112 7"
 # Vector size
-def_args_fdotproduct ?= "8192"
+def_args_fdotproduct ?= "4096"
 # Vector size
-def_args_dotproduct  ?= "8192"
+def_args_dotproduct  ?= "4096"
 # Matrix padded size 0, matrix padded size 1, onlyvec
 def_args_jacobi2d    ?= "130 130"
 # Vector size
diff --git a/apps/fdotproduct/kernel/fdotproduct.c b/apps/fdotproduct/kernel/fdotproduct.c
index 99e1cf1..e4070cf 100644
--- a/apps/fdotproduct/kernel/fdotproduct.c
+++ b/apps/fdotproduct/kernel/fdotproduct.c
@@ -24,6 +24,7 @@ double fdotp_v64b(const double *a, const double *b, size_t avl) {
 
   size_t orig_avl = avl;
   size_t vl = vsetvl_e64m8(avl);
+  size_t vl_red = vl;
 
   vfloat64m8_t acc, buf_a, buf_b;
   vfloat64m1_t red;
@@ -50,6 +51,7 @@ double fdotp_v64b(const double *a, const double *b, size_t avl) {
     b_ += vl;
   }
 
+  vl = vsetvl_e64m8(vl_red);
   // Reduce and return
   red = vfredusum_vs_f64m8_f64m1(red, acc, red, vl);
   return vfmv_f_s_f64m1_f64(red);
@@ -58,7 +60,9 @@ double fdotp_v64b(const double *a, const double *b, size_t avl) {
 
   size_t orig_avl = avl;
   size_t vl;
+  size_t vl_red;
   asm volatile("vsetvli %0, %1, e64, m8, ta, ma" : "=r"(vl) : "r"(avl));
+  vl_red = vl;
 
   double red;
 
@@ -85,6 +89,7 @@ double fdotp_v64b(const double *a, const double *b, size_t avl) {
   }
 
   // Reduce and return
+  asm volatile("vsetvli %0, %1, e64, m8, ta, ma" : "=r"(vl) : "r"(vl_red));
   asm volatile("vfredusum.vs v0, v24, v0");
   asm volatile("vfmv.f.s %0, v0" : "=f"(red));
   return red;
@@ -98,6 +103,7 @@ float fdotp_v32b(const float *a, const float *b, size_t avl) {
 
   size_t orig_avl = avl;
   size_t vl = vsetvl_e32m8(avl);
+  size_t vl_red = vl;
 
   vfloat32m8_t acc, buf_a, buf_b;
   vfloat32m1_t red;
@@ -125,6 +131,7 @@ float fdotp_v32b(const float *a, const float *b, size_t avl) {
   }
 
   // Reduce and return
+  vl = vsetvl_e32m8(vl_red);
   red = vfredusum_vs_f32m8_f32m1(red, acc, red, vl);
   return vfmv_f_s_f32m1_f32(red);
 
@@ -132,7 +139,9 @@ float fdotp_v32b(const float *a, const float *b, size_t avl) {
 
   size_t orig_avl = avl;
   size_t vl;
+  size_t vl_red;
   asm volatile("vsetvli %0, %1, e32, m8, ta, ma" : "=r"(vl) : "r"(avl));
+  vl_red = vl;
 
   float red;
 
@@ -148,7 +157,7 @@ float fdotp_v32b(const float *a, const float *b, size_t avl) {
     asm volatile("vle32.v v8,  (%0)" ::"r"(a_));
     asm volatile("vle32.v v16, (%0)" ::"r"(b_));
     // Multiply and accumulate
-    if (avl == orig_avl) {
+     if (avl == orig_avl) {
       asm volatile("vfmul.vv v24, v8, v16");
     } else {
       asm volatile("vfmacc.vv v24, v8, v16");
@@ -159,9 +168,11 @@ float fdotp_v32b(const float *a, const float *b, size_t avl) {
   }
 
   // Reduce and return
+  asm volatile("vsetvli %0, %1, e32, m8, ta, ma" : "=r"(vl) : "r"(vl_red));
   asm volatile("vfredusum.vs v0, v24, v0");
   asm volatile("vfmv.f.s %0, v0" : "=f"(red));
   return red;
+  // return 1.5;
 
 #endif
 }
@@ -172,6 +183,7 @@ _Float16 fdotp_v16b(const _Float16 *a, const _Float16 *b, size_t avl) {
 
   size_t orig_avl = avl;
   size_t vl = vsetvl_e16m8(avl);
+  size_t vl_red = vl;
 
   vfloat16m8_t acc, buf_a, buf_b;
   vfloat16m1_t red;
@@ -199,6 +211,7 @@ _Float16 fdotp_v16b(const _Float16 *a, const _Float16 *b, size_t avl) {
   }
 
   // Reduce and store
+  vl = vsetvl_e16m8(vl_red);
   red = vfredusum_vs_f16m8_f16m1(red, acc, red, vl);
   return vfmv_f_s_f16m1_f16(red);
 
@@ -206,7 +219,9 @@ _Float16 fdotp_v16b(const _Float16 *a, const _Float16 *b, size_t avl) {
 
   size_t orig_avl = avl;
   size_t vl;
+  size_t vl_red;
   asm volatile("vsetvli %0, %1, e16, m8, ta, ma" : "=r"(vl) : "r"(avl));
+  vl_red = vl;
 
   _Float16 red;
 
@@ -233,6 +248,7 @@ _Float16 fdotp_v16b(const _Float16 *a, const _Float16 *b, size_t avl) {
   }
 
   // Reduce and return
+  asm volatile("vsetvli %0, %1, e16, m8, ta, ma" : "=r"(vl) : "r"(vl_red));
   asm volatile("vfredusum.vs v0, v24, v0");
   asm volatile("vfmv.f.s %0, v0" : "=f"(red));
   return red;
diff --git a/apps/iconv2d/main.c b/apps/iconv2d/main.c
index 5d5f7e7..6fe86fb 100644
--- a/apps/iconv2d/main.c
+++ b/apps/iconv2d/main.c
@@ -31,12 +31,19 @@
 // o = i ° f, with i=[MxN], f=[FxF], o=[MxN]
 // The filter is a square matrix, and F is odd
 
+// // Matrices defined in data.S
+// extern int64_t i[] __attribute__((
+//     aligned(4 * NR_LANES))); // [ (M+floor(F/2)) * (N+floor(F/2)) ]
+// extern int64_t f[] __attribute__((aligned(4 * NR_LANES)));        // [ F*F ]
+// extern int64_t o[] __attribute__((aligned(4 * NR_LANES)));        // [ M*N ]
+// extern int64_t golden_o[] __attribute__((aligned(4 * NR_LANES))); // [ M*N ]
+
 // Matrices defined in data.S
-extern int64_t i[] __attribute__((
-    aligned(4 * NR_LANES))); // [ (M+floor(F/2)) * (N+floor(F/2)) ]
-extern int64_t f[] __attribute__((aligned(4 * NR_LANES)));        // [ F*F ]
-extern int64_t o[] __attribute__((aligned(4 * NR_LANES)));        // [ M*N ]
-extern int64_t golden_o[] __attribute__((aligned(4 * NR_LANES))); // [ M*N ]
+extern int64_t i[] __attribute__((aligned(4 * NR_LANES * NR_CLUSTERS)));        // [ (M+floor(F/2)) * (N+floor(F/2)) ]
+extern int64_t f[] __attribute__((aligned(4 * NR_LANES * NR_CLUSTERS)));        // [ F*F ]
+extern int64_t o[] __attribute__((aligned(4 * NR_LANES * NR_CLUSTERS)));        // [ M*N ]
+extern int64_t golden_o[] __attribute__((aligned(4 * NR_LANES * NR_CLUSTERS))); // [ M*N ]
+
 // M, N, F defined in data.S
 extern int64_t M;
 extern int64_t N;
diff --git a/apps/iconv2d/script/gen_data.py b/apps/iconv2d/script/gen_data.py
index 1572466..312ac85 100644
--- a/apps/iconv2d/script/gen_data.py
+++ b/apps/iconv2d/script/gen_data.py
@@ -109,7 +109,11 @@ def emit(name, array, alignment='8'):
 emit("M", np.array(M, dtype=np.uint64))
 emit("N", np.array(N, dtype=np.uint64))
 emit("F", np.array(F, dtype=np.uint64))
-emit("i", image, 'NR_LANES*4')
-emit("f", gen_filter, 'NR_LANES*4')
-emit("o", empty_o, 'NR_LANES*4')
-emit("golden_o", result, 'NR_LANES*4')
+# emit("i", image, 'NR_LANES*4')
+# emit("f", gen_filter, 'NR_LANES*4')
+# emit("o", empty_o, 'NR_LANES*4')
+# emit("golden_o", result, 'NR_LANES*4')
+emit("i", image, 'NR_LANES*4*NR_CLUSTERS')
+emit("f", gen_filter, 'NR_LANES*4*NR_CLUSTERS')
+emit("o", empty_o, 'NR_LANES*4*NR_CLUSTERS')
+emit("golden_o", result, 'NR_LANES*4*NR_CLUSTERS')
diff --git a/apps/imatmul/main.c b/apps/imatmul/main.c
index 31430a4..ca8922a 100644
--- a/apps/imatmul/main.c
+++ b/apps/imatmul/main.c
@@ -35,11 +35,11 @@ extern uint64_t M;
 extern uint64_t N;
 extern uint64_t P;
 
-extern int64_t a[] __attribute__((aligned(32 * NR_LANES), section(".l2")));
-extern int64_t b[] __attribute__((aligned(32 * NR_LANES), section(".l2")));
-extern int64_t c[] __attribute__((aligned(32 * NR_LANES), section(".l2")));
+extern double a[] __attribute__((aligned(4 * NR_LANES * NR_CLUSTERS), section(".l2")));
+extern double b[] __attribute__((aligned(4 * NR_LANES * NR_CLUSTERS), section(".l2")));
+extern double c[] __attribute__((aligned(4 * NR_LANES * NR_CLUSTERS), section(".l2")));
 // Gold results
-extern int64_t g[] __attribute__((aligned(32 * NR_LANES), section(".l2")));
+extern double g[] __attribute__((aligned(4 * NR_LANES * NR_CLUSTERS), section(".l2")));
 
 // Verify the matrix
 int verify_matrix(int64_t *result, int64_t *gold, size_t R, size_t C) {
@@ -66,7 +66,7 @@ int main() {
   // Measure only the full-size matmul
   for (uint64_t s = M; s <= M; s *= 2) {
 #else
-  for (int s = 4; s <= M; s *= 2) {
+  for (uint64_t s = M; s <= M; s *= 2) {
 #endif
     printf("\n");
     printf("------------------------------------------------------------\n");
diff --git a/apps/imatmul/script/gen_data.py b/apps/imatmul/script/gen_data.py
index 05457a6..dcf5dba 100644
--- a/apps/imatmul/script/gen_data.py
+++ b/apps/imatmul/script/gen_data.py
@@ -65,7 +65,7 @@ def emit(name, array, alignment='8'):
 emit("M", np.array(M, dtype=np.uint64))
 emit("N", np.array(N, dtype=np.uint64))
 emit("P", np.array(P, dtype=np.uint64))
-emit("a", A, 'NR_LANES*4')
-emit("b", B, 'NR_LANES*4')
-emit("c", C, 'NR_LANES*4')
-emit("g", G, 'NR_LANES*4')
+emit("a", A, 'NR_LANES*4*NR_CLUSTERS')
+emit("b", B, 'NR_LANES*4*NR_CLUSTERS')
+emit("c", C, 'NR_LANES*4*NR_CLUSTERS')
+emit("g", G, 'NR_LANES*4*NR_CLUSTERS')
diff --git a/hardware/include/ara_pkg.sv b/hardware/include/ara_pkg.sv
index ead2dc7..216fc2c 100644
--- a/hardware/include/ara_pkg.sv
+++ b/hardware/include/ara_pkg.sv
@@ -318,6 +318,8 @@ package ara_pkg;
 
     // Vector machine metadata
     vlen_t vl;
+    // Real vector length number assigned for vle and vse
+    vlen_t vl_ldst;
     vlen_t vstart;
     rvv_pkg::vtype_t vtype;
 
@@ -416,6 +418,8 @@ package ara_pkg;
 
     // Vector machine metadata
     vlen_t vl;
+    // Actual vector length assigned for vle and vse
+    vlen_t vl_ldst;
     vlen_t vstart;
     rvv_pkg::vtype_t vtype;
 
@@ -1158,6 +1162,7 @@ package ara_pkg;
     axi_pkg::size_t size;
     axi_pkg::len_t len;
     logic is_load;
+    vlen_t vl_ldst; // Meaning that vstu should write enable to zero when executing vse (vl-vl_ldst)
   } addrgen_axi_req_t;
 
 
diff --git a/hardware/src/ara_cluster.sv b/hardware/src/ara_cluster.sv
index 1c1fb3a..a831011 100644
--- a/hardware/src/ara_cluster.sv
+++ b/hardware/src/ara_cluster.sv
@@ -96,6 +96,7 @@ module ara_cluster import ara_pkg::*; import rvv_pkg::*;  #(
 
   fork_req_t  [nlevels : 0] acc_req_fork;
   fork_resp_t [nlevels : 0] acc_resp_fork;
+  accelerator_resp_t        acc_resp_fork_glb;
 
   // Shuffle stage to ARA cuts
   localparam int ShuffleCuts = $clog2(NrClusters);
@@ -105,6 +106,10 @@ module ara_cluster import ara_pkg::*; import rvv_pkg::*;  #(
   group_req_t [ShuffleCuts:0] ara_axi_req_shuffle_cut;
   group_resp_t [ShuffleCuts:0] ara_axi_resp_shuffle_cut;
 
+  // GLSU ready to accept new acc req
+  logic acc_req_ready_glsu;
+  logic ar_addrgen_ack, aw_addrgen_ack;
+
   /////////
   // ARA //
   /////////
@@ -344,7 +349,11 @@ module ara_cluster import ara_pkg::*; import rvv_pkg::*;  #(
       .clk_i              (clk_i                ),
       .rst_ni             (rst_ni               ),
 
-      .acc_req_i          (acc_req_i          ),
+      .acc_req_i          (acc_req_fork[nlevels][0] ),
+
+      // To Shuffle stage and Align stage
+      .ar_addrgen_ack_i   (ar_addrgen_ack       ),
+      .aw_addrgen_ack_i   (aw_addrgen_ack       ),
 
       .axi_req_i          (ara_axi_req_cut      ),
       .axi_resp_o         (ara_axi_resp_cut     ),
@@ -388,7 +397,8 @@ module ara_cluster import ara_pkg::*; import rvv_pkg::*;  #(
   ) i_global_ldst (
     .clk_i              (clk_i              ),
     .rst_ni             (rst_ni             ),
-    .acc_req_i          (acc_req_i          ),
+    .acc_req_i          (acc_req_fork[nlevels][0] ),
+    .acc_req_ready_o    (acc_req_ready_glsu ),
     // To Ara
     .axi_req_i          (ldst_axi_req       ),
     .axi_resp_o         (ldst_axi_resp      ),
@@ -396,6 +406,9 @@ module ara_cluster import ara_pkg::*; import rvv_pkg::*;  #(
     // .axi_req_i       (ara_axi_req_cut    ),
     // .axi_resp_o      (ara_axi_resp_cut   ),
 
+    // To Shuffle stage and Align stage
+    .ar_addrgen_ack_o   (ar_addrgen_ack     ),
+    .aw_addrgen_ack_o   (aw_addrgen_ack     ),
     // To System
     .axi_resp_i         (axi_resp_cut       ),
     .axi_req_o          (axi_req_cut        )
@@ -436,7 +449,11 @@ module ara_cluster import ara_pkg::*; import rvv_pkg::*;  #(
     ) i_align_stage (
       .clk_i            (clk_i              ),
       .rst_ni           (rst_ni             ),
-      .acc_req_i        (acc_req_i          ),
+      .acc_req_i        (acc_req_fork[nlevels][0] ),
+
+      // To Shuffle stage and Align stage
+      .ar_addrgen_ack_i (ar_addrgen_ack     ),
+      .aw_addrgen_ack_i (aw_addrgen_ack     ),
 
       // .axi_req_i        (axi_req_cut        ),
       // .axi_resp_o       (axi_resp_cut       ),
@@ -509,6 +526,12 @@ module ara_cluster import ara_pkg::*; import rvv_pkg::*;  #(
 
   `endif
 
+   
+  always_comb begin
+    acc_resp_fork_glb = acc_resp_fork[0][0];
+    acc_resp_fork_glb.req_ready = acc_resp_fork[0][0].req_ready && acc_req_ready_glsu;
+  end
+
   //////////////////
   ////// CVA6 //////
   //////////////////
@@ -541,11 +564,13 @@ module ara_cluster import ara_pkg::*; import rvv_pkg::*;  #(
     assign acc_resp_o = resp_cut_o;
 
     assign acc_req_fork[0][0] = req_cut_o;
-    assign resp_cut_i = acc_resp_fork[0][0];
+    // assign resp_cut_i = acc_resp_fork[0][0];
+    assign resp_cut_i = acc_resp_fork_glb;
 
   `else
     assign acc_req_fork[0][0] = acc_req_i;
-    assign acc_resp_o = acc_resp_fork[0][0];
+    // assign acc_resp_o = acc_resp_fork[0][0];
+    assign acc_resp_o = acc_resp_fork_glb;
 
   `endif
 
diff --git a/hardware/src/ara_dispatcher.sv b/hardware/src/ara_dispatcher.sv
index 1d331f8..e15d0aa 100644
--- a/hardware/src/ara_dispatcher.sv
+++ b/hardware/src/ara_dispatcher.sv
@@ -514,10 +514,12 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
                     if (insn.vsetvl_type.rs1 == '0 && insn.vsetvl_type.rd == '0) begin
                       // Do not update the vector length
                       vl_d = vl_q;
+                      vl_ld_d = vl_ld_q;
                       acc_resp_o.result = vl_d << num_clusters_i;
                     end else if (insn.vsetvl_type.rs1 == '0 && insn.vsetvl_type.rd != '0) begin
                       // Set the vector length to vlmax
                       vl_d = vlmax;
+                      vl_ld_d = vlmax;
                       acc_resp_o.result = vl_d << num_clusters_i;
                     end else begin
                       // // Normal stripmining
@@ -2561,6 +2563,7 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
 
             // These generate a request to Ara's backend
             ara_req_d.vl        = vl_ld_q;
+            ara_req_d.vl_ldst   = vl_q;
             ara_req_d.vd        = insn.vmem_type.rd;
             ara_req_d.use_vd    = 1'b1;
             ara_req_d.vm        = insn.vmem_type.vm;
@@ -2774,7 +2777,9 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
             ara_req_d.scale_vl = 1'b1;
 
             // These generate a request to Ara's backend
-            ara_req_d.vl        = vl_q;
+            // ara_req_d.vl        = vl_q;
+            ara_req_d.vl        = vl_ld_q;
+            ara_req_d.vl_ldst   = vl_q;
             ara_req_d.vs1       = insn.vmem_type.rd; // vs3 is encoded in the same position as rd
             ara_req_d.use_vs1   = 1'b1;
             ara_req_d.eew_vs1   = eew_q[insn.vmem_type.rd]; // This is the vs1 EEW
@@ -2836,7 +2841,8 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
                   5'b01000:;     // Unit-strided, whole registers
                   5'b01011: begin // Unit-strided, mask store, EEW=1
                     // We operate ceil(vl/8) bytes
-                    ara_req_d.vl         = (vl_q >> 3) + |vl_q[2:0];
+                    // ara_req_d.vl         = (vl_q >> 3) + |vl_q[2:0];
+                    ara_req_d.vl         = (vl_ld_q >> 3) + |vl_ld_q[2:0];
                     ara_req_d.vtype.vsew = EW8;
                   end
                   default: begin // Reserved
@@ -3141,6 +3147,10 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
             acc_resp_o.resp_valid = 1'b1;
           end
         endcase
+
+        if (ara_req_d.op inside {VSLIDEUP, VSLIDEDOWN}) begin
+          ara_req_d.vl = vl_ld_q;
+        end
       end
 
       // Check that we have fixed-point support if requested
diff --git a/hardware/src/ara_sequencer.sv b/hardware/src/ara_sequencer.sv
index 3132f75..7b017ae 100644
--- a/hardware/src/ara_sequencer.sv
+++ b/hardware/src/ara_sequencer.sv
@@ -361,6 +361,7 @@ module ara_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::i
               cvt_resize    : ara_req_i.cvt_resize,
               scale_vl      : ara_req_i.scale_vl,
               vl            : ara_req_i.vl,
+              vl_ldst       : ara_req_i.vl_ldst,
               vstart        : ara_req_i.vstart,
               vtype         : ara_req_i.vtype,
               hazard_vd     : pe_req_d.hazard_vd,
diff --git a/hardware/src/sldu/sldu.sv b/hardware/src/sldu/sldu.sv
index 75414e7..06a21b3 100644
--- a/hardware/src/sldu/sldu.sv
+++ b/hardware/src/sldu/sldu.sv
@@ -446,6 +446,11 @@ module sldu import ara_pkg::*; import rvv_pkg::*; #(
 
   // Remaining bytes of the current instruction in the issue phase
   vlen_t issue_cnt_d, issue_cnt_q;
+  vlen_t rest_issue_cnt_d;
+  // We give slidedown (not slide1down) extra flits, for upper most elements,
+  // these number should be minused to get the actual count to be issued
+  assign rest_issue_cnt_d = ((vinsn_ring.op == VSLIDEDOWN) && (!(vinsn_ring.use_scalar_op || (vinsn_ring.stride == 0)))) ? 
+                            (issue_cnt_d - 8 * NrLanes) : issue_cnt_d;
   // Respected by default: input_limit_d  = 8*NrLanes + out_pnt_d - in_pnt_d;
   // To enforce: output_limit_d = out_pnt_d + issue_cnt_d;
   logic [idx_width(MAXVL+1):0] output_limit_d, output_limit_q;
@@ -564,7 +569,12 @@ module sldu import ara_pkg::*; import rvv_pkg::*; #(
       eff_stride_q           <= eff_stride_d;
     end
   end
-  
+
+  logic slidedown_extra_flit;
+  // assign slidedown_extra_flit = (vinsn_issue_q.op == VSLIDEDOWN) && (!vinsn_issue_q.use_scalar_op) && (issue_cnt_q <= 8*NrLanes);
+  assign slidedown_extra_flit = (|vinsn_issue_q.stride) ? 
+                                ((vinsn_issue_q.op == VSLIDEDOWN) && (!vinsn_issue_q.use_scalar_op) && (issue_cnt_q <= 8*NrLanes)) : 0;
+
   always_comb begin: p_sldu
     // Maintain state
     vinsn_queue_d = vinsn_queue_q;
@@ -752,8 +762,12 @@ module sldu import ara_pkg::*; import rvv_pkg::*; #(
               eff_stride_d = eff_stride;
 
               // Initialize counters
-              issue_cnt_d = vinsn_issue_q.vl << int'(vinsn_issue_q.vtype.vsew);
-              output_limit_d = issue_cnt_d;
+              // issue_cnt_d = vinsn_issue_q.vl << int'(vinsn_issue_q.vtype.vsew);
+              // issue_cnt_d = (vinsn_issue_q.use_scalar_op) ? (vinsn_issue_q.vl << int'(vinsn_issue_q.vtype.vsew)) : 
+              //               ((vinsn_issue_q.vl << int'(vinsn_issue_q.vtype.vsew)) + 8*NrLanes);
+              issue_cnt_d = (vinsn_issue_q.use_scalar_op || (vinsn_issue_q.stride == 0)) ? (vinsn_issue_q.vl << int'(vinsn_issue_q.vtype.vsew)) : 
+                            ((vinsn_issue_q.vl << int'(vinsn_issue_q.vtype.vsew)) + 8*NrLanes);
+              output_limit_d = vinsn_issue_q.vl << int'(vinsn_issue_q.vtype.vsew);
 
             end
             // Ordered sum reductions
@@ -804,7 +818,7 @@ module sldu import ara_pkg::*; import rvv_pkg::*; #(
           out_en = out_en_flat & ({8*NrLanes{vinsn_issue_q.vm | (vinsn_issue_q.vfu inside {VFU_Alu, VFU_MFpu})}} | mask_q);
 
           // Write in the correct bytes
-          if (init_queue_q) begin
+          if (init_queue_q && !slidedown_extra_flit) begin
             // To initialize the queue only once with the local shifted data
             // The ring data is written later on top of the initialized data
             for (int lane = 0; lane < NrLanes; lane++)
@@ -1011,12 +1025,14 @@ module sldu import ara_pkg::*; import rvv_pkg::*; #(
                 vinsn_queue_d.issue_cnt -= 1;
             end
 
-            // Send result to the VRF
-            result_queue_cnt_d += 1;
+            if (!slidedown_extra_flit) begin
+              // Send result to the VRF
+              result_queue_cnt_d += 1;
 
-            result_queue_write_pnt_d = result_queue_write_pnt_q+1;
-            if (result_queue_write_pnt_q == ResultQueueDepth-1)
-              result_queue_write_pnt_d = '0;
+              result_queue_write_pnt_d = result_queue_write_pnt_q+1;
+              if (result_queue_write_pnt_q == ResultQueueDepth-1)
+                result_queue_write_pnt_d = '0;
+            end
 
             // if (state_q == SLIDE_NP2_COMMIT) 
             //   state_d = SLIDE_NP2_WAIT;
@@ -1231,12 +1247,15 @@ module sldu import ara_pkg::*; import rvv_pkg::*; #(
 
     // For the edge cluster alone, for slidedown, the last 8*NrLanes bytes should not be ring but from previous ring packet and scalar operand.
     use_fifo_inp = 1'b1;
-    if (is_edge_cluster && vinsn_ring.op==VSLIDEDOWN && (ring_cnt_q <= 8*NrLanes) && |ring_data_prev_valid_q) begin
+    if (is_edge_cluster && vinsn_ring.op==VSLIDEDOWN && (vinsn_ring.use_scalar_op || (vinsn_ring.stride == 0)) && (ring_cnt_q <= 8*NrLanes) && |ring_data_prev_valid_q) begin
       use_fifo_inp = 1'b0;
     end
     
-    if ((result_queue_cnt_d || issue_cnt_d==0) &&
-        (((vinsn_queue_d.issue_pnt != vinsn_queue_d.ring_pnt) || ((issue_cnt_d < ring_cnt_d) && (vinsn_queue_d.issue_pnt == vinsn_queue_d.ring_pnt))) || 
+    // if ((result_queue_cnt_d || issue_cnt_d==0) &&
+    //     (((vinsn_queue_d.issue_pnt != vinsn_queue_d.ring_pnt) || ((issue_cnt_d < ring_cnt_d) && (vinsn_queue_d.issue_pnt == vinsn_queue_d.ring_pnt))) || 
+    //     is_ring_reduction)) begin
+    if ((result_queue_cnt_d || issue_cnt_d==0) && (ring_cnt_d > 0) &&
+        (((vinsn_queue_d.issue_pnt != vinsn_queue_d.ring_pnt) || ((rest_issue_cnt_d < ring_cnt_d) && (vinsn_queue_d.issue_pnt == vinsn_queue_d.ring_pnt))) || 
         is_ring_reduction)) begin
     
     // if (((vinsn_queue_d.issue_pnt != vinsn_queue_d.ring_pnt) || ((issue_cnt_d < ring_cnt_d) && (vinsn_queue_d.issue_pnt == vinsn_queue_d.ring_pnt))) || 
@@ -1297,6 +1316,7 @@ module sldu import ara_pkg::*; import rvv_pkg::*; #(
                                                                                            ring_data_prev[63:56]};
                   endcase
                 end
+                // ring_data_prev_valid_d[lane_id] = 1'b0;
                 n_ring_in_d = n_ring_in_q - 1;
                 slide_data_valid = (n_ring_in_q == 1) ? 1'b1 : 1'b0;
               end else begin
@@ -1345,7 +1365,8 @@ module sldu import ara_pkg::*; import rvv_pkg::*; #(
             fifo_ring_ready_out = 1'b1;  // Acknowledge fifo that data has been accepted.
       end else begin
           // For the last data for slide1down use the scalar op
-          if (cluster_id_i == max_cluster_id && vinsn_ring.op==VSLIDEDOWN && (ring_cnt_q <= 8*NrLanes) && |ring_data_prev_valid_q && issue_cnt_q==0) begin
+          // if (cluster_id_i == max_cluster_id && vinsn_ring.op==VSLIDEDOWN && (ring_cnt_q <= 8*NrLanes) && |ring_data_prev_valid_q && issue_cnt_q==0) begin
+          if (cluster_id_i == max_cluster_id && vinsn_ring.op==VSLIDEDOWN && (vinsn_ring.use_scalar_op || (vinsn_ring.stride == 0)) && (ring_cnt_q <= 8*NrLanes) && |ring_data_prev_valid_q && issue_cnt_q==0) begin
             automatic elen_t ring_data_prev = ring_data_prev_q[edge_lane_id];
             unique case (vinsn_ring.vtype.vsew)
               EW64: result_queue_d[result_queue_write_pnt_q2][edge_lane_id].wdata = {vinsn_ring.scalar_op};
@@ -1363,6 +1384,17 @@ module sldu import ara_pkg::*; import rvv_pkg::*; #(
       end
     end
 
+    // Consume extra ring element;
+    if ((result_queue_cnt_d || issue_cnt_d==0) && (ring_cnt_d == 0) && fifo_ring_valid_inp && use_fifo_inp) begin
+      fifo_ring_ready_out = 1'b1;
+    end
+
+    // if ((result_queue_cnt_d || issue_cnt_d==0) && (ring_cnt_d == 0) &&
+    //   (((vinsn_queue_d.issue_pnt != vinsn_queue_d.ring_pnt) || ((rest_issue_cnt_d < ring_cnt_d) && (vinsn_queue_d.issue_pnt == vinsn_queue_d.ring_pnt))) || 
+    //   is_ring_reduction) && fifo_ring_valid_inp && use_fifo_inp) begin
+    //     fifo_ring_ready_out = 1'b1;
+    // end
+
     // Set the data to valid to be sent to the VRF
     // Update the write_pnt_q2
     if (slide_data_valid) begin
@@ -1565,4 +1597,4 @@ module sldu import ara_pkg::*; import rvv_pkg::*; #(
     end
   end
 
-endmodule: sldu
+endmodule: sldu
\ No newline at end of file
diff --git a/hardware/src/vlsu/addrgen.sv b/hardware/src/vlsu/addrgen.sv
index 8112062..68a6700 100644
--- a/hardware/src/vlsu/addrgen.sv
+++ b/hardware/src/vlsu/addrgen.sv
@@ -96,6 +96,7 @@ module addrgen import ara_pkg::*; import rvv_pkg::*; #(
     logic is_load;
     logic is_burst; // Unit-strided instructions can be converted into AXI INCR bursts
     vlen_t vstart;
+    vlen_t vl_ldst;  // Meaning that the cluster should pad zero for write data
   } addrgen_req_t;
   addrgen_req_t addrgen_req;
   logic         addrgen_req_valid;
@@ -197,7 +198,7 @@ module addrgen import ara_pkg::*; import rvv_pkg::*; #(
 
   axi_addr_t lookahead_addr_e_d, lookahead_addr_e_q;
   axi_addr_t lookahead_addr_se_d, lookahead_addr_se_q;
-  vlen_t lookahead_len_d, lookahead_len_q;
+  vlen_t lookahead_len_d, lookahead_len_q, lookahead_len_ldst_d, lookahead_len_ldst_q;
 
   logic [VLEN-1:0] vaddr_start;
 
@@ -208,6 +209,7 @@ module addrgen import ara_pkg::*; import rvv_pkg::*; #(
     lookahead_addr_e_d  = lookahead_addr_e_q;
     lookahead_addr_se_d = lookahead_addr_se_q;
     lookahead_len_d     = lookahead_len_q;
+    lookahead_len_ldst_d = lookahead_len_ldst_q;
 
     // Running vector instructions
     vinsn_running_d = vinsn_running_q & pe_vinsn_running_i;
@@ -260,6 +262,9 @@ module addrgen import ara_pkg::*; import rvv_pkg::*; #(
           lookahead_addr_e_d  = pe_req_i.scalar_op + (pe_req_i.vstart << unsigned'(pe_req_i.vtype.vsew));
           lookahead_addr_se_d = pe_req_i.scalar_op + (pe_req_i.vstart * pe_req_i.stride);
           lookahead_len_d     = (pe_req_i.vl - pe_req_i.vstart) << unsigned'(pe_req_i.vtype.vsew[1:0]);
+          // For synchronization among clusters, vl for vse is always multiplier of NrLanes*NrClusters, but actual write vl may 
+          // be smaller. Here we tell vstu module how many data should not be written (i.e. set write enable to zero)
+          lookahead_len_ldst_d = (pe_req_i.vl - pe_req_i.vl_ldst) << unsigned'(pe_req_i.vtype.vsew[1:0]);
 
           case (pe_req_i.op)
             VLXE, VSXE: begin
@@ -348,7 +353,8 @@ module addrgen import ara_pkg::*; import rvv_pkg::*; #(
           is_load : is_load(pe_req_q.op),
           // Unit-strided loads/stores trigger incremental AXI bursts.
           is_burst: (pe_req_q.op inside {VLE, VSE}),
-          vstart  : pe_req_q.vstart
+          vstart  : pe_req_q.vstart,
+          vl_ldst : lookahead_len_ldst_q
         };
 
         // Ara does not support misaligned AXI requests
@@ -410,7 +416,8 @@ module addrgen import ara_pkg::*; import rvv_pkg::*; #(
           is_load : is_load(pe_req_q.op),
           // Unit-strided loads/stores trigger incremental AXI bursts.
           is_burst: 1'b0,
-          vstart  : pe_req_q.vstart
+          vstart  : pe_req_q.vstart,
+          vl_ldst : lookahead_len_ldst_q
         };
         addrgen_req_valid = 1'b1;
 
@@ -625,6 +632,7 @@ module addrgen import ara_pkg::*; import rvv_pkg::*; #(
       lookahead_addr_e_q         <= '0;
       lookahead_addr_se_q        <= '0;
       lookahead_len_q            <= '0;
+      lookahead_len_ldst_q       <= '0;
     end else begin
       state_q            <= state_d;
       pe_req_q           <= pe_req_d;
@@ -638,6 +646,7 @@ module addrgen import ara_pkg::*; import rvv_pkg::*; #(
       lookahead_addr_e_q         <= lookahead_addr_e_d;
       lookahead_addr_se_q        <= lookahead_addr_se_d;
       lookahead_len_q            <= lookahead_len_d;
+      lookahead_len_ldst_q       <= lookahead_len_ldst_d;
     end
   end
 
@@ -680,8 +689,12 @@ module addrgen import ara_pkg::*; import rvv_pkg::*; #(
   //  AXI Request Generation  //
   //////////////////////////////
 
+  // enum logic [1:0] {
+  //   AXI_ADDRGEN_IDLE, AXI_ADDRGEN_MISALIGNED, AXI_ADDRGEN_WAITING, AXI_ADDRGEN_REQUESTING
+  // } axi_addrgen_state_d, axi_addrgen_state_q;
+
   enum logic [1:0] {
-    AXI_ADDRGEN_IDLE, AXI_ADDRGEN_MISALIGNED, AXI_ADDRGEN_WAITING, AXI_ADDRGEN_REQUESTING
+    AXI_ADDRGEN_IDLE, AXI_ADDRGEN_WAITING, AXI_ADDRGEN_REQUESTING
   } axi_addrgen_state_d, axi_addrgen_state_q;
 
   axi_addr_t aligned_start_addr_d, aligned_start_addr_q;
@@ -787,25 +800,8 @@ module addrgen import ara_pkg::*; import rvv_pkg::*; #(
         if (addrgen_req_valid) begin
           axi_addrgen_state_d = core_st_pending_i ? AXI_ADDRGEN_WAITING : AXI_ADDRGEN_REQUESTING;
 
-          // In case of a misaligned store, reduce the effective width of the AXI transaction,
-          // since the store unit does not support misalignments between the AXI bus and the lanes
-          if (axi_addrgen_d.vstart != 0 && !axi_addrgen_d.is_load) begin
-            // vstart > 0 can create problems similar to the ones a misalignment would create.
-            // Limit the effective AXI bus width to the element width to avoid problems.
-            axi_addrgen_state_d = AXI_ADDRGEN_MISALIGNED;
-
-            eff_axi_dw_d     = 1 << axi_addrgen_d.vew;
-            eff_axi_dw_log_d = axi_addrgen_d.vew;
-          end else if ((axi_addrgen_d.addr[clog2_AxiStrobeWidth-1:0] != '0) && !axi_addrgen_d.is_load) begin
-            // Calculate the start and the end addresses in the AXI_ADDRGEN_MISALIGNED state
-            axi_addrgen_state_d = AXI_ADDRGEN_MISALIGNED;
-
-            eff_axi_dw_d     = {1'b0, narrow_axi_data_bwidth};
-            eff_axi_dw_log_d = zeroes_cnt;
-          end else begin
-            eff_axi_dw_d     = AxiDataWidth/8;
-            eff_axi_dw_log_d = clog2_AxiStrobeWidth;
-          end
+          eff_axi_dw_d     = AxiDataWidth/8;
+          eff_axi_dw_log_d = clog2_AxiStrobeWidth;
         end
       end
       // AXI_ADDRGEN_IDLE: begin
@@ -856,24 +852,24 @@ module addrgen import ara_pkg::*; import rvv_pkg::*; #(
       //     aligned_end_addr_d = aligned_next_start_addr_d - 1;*/
       //   end
       // end
-      AXI_ADDRGEN_MISALIGNED: begin
-        axi_addrgen_state_d = core_st_pending_i ? AXI_ADDRGEN_WAITING : AXI_ADDRGEN_REQUESTING;
+      // AXI_ADDRGEN_MISALIGNED: begin
+      //   axi_addrgen_state_d = core_st_pending_i ? AXI_ADDRGEN_WAITING : AXI_ADDRGEN_REQUESTING;
 
-        // The start address is found by aligning the original request address by the width of
-        // the memory interface.
-        aligned_start_addr_d = aligned_addr(axi_addrgen_q.addr, eff_axi_dw_log_q);
+      //   // The start address is found by aligning the original request address by the width of
+      //   // the memory interface.
+      //   aligned_start_addr_d = aligned_addr(axi_addrgen_q.addr, eff_axi_dw_log_q);
 
-        set_end_addr (
-          next_2page_msb_q,
-          axi_addrgen_q.len,
-          axi_addrgen_q.addr,
-          eff_axi_dw_q,
-          eff_axi_dw_log_q,
-          aligned_start_addr_d,
-          aligned_end_addr_d,
-          aligned_next_start_addr_d
-        );
-      end
+      //   set_end_addr (
+      //     next_2page_msb_q,
+      //     axi_addrgen_q.len,
+      //     axi_addrgen_q.addr,
+      //     eff_axi_dw_q,
+      //     eff_axi_dw_log_q,
+      //     aligned_start_addr_d,
+      //     aligned_end_addr_d,
+      //     aligned_next_start_addr_d
+      //   );
+      // end
       // AXI_ADDRGEN_MISALIGNED: begin
       //   axi_addrgen_state_d = core_st_pending_i ? AXI_ADDRGEN_WAITING : AXI_ADDRGEN_REQUESTING;
 
@@ -992,7 +988,8 @@ module addrgen import ara_pkg::*; import rvv_pkg::*; #(
                 addr         : paddr,
                 len          : burst_length - 1,
                 size         : eff_axi_dw_log_q,
-                is_load      : axi_addrgen_q.is_load
+                is_load      : axi_addrgen_q.is_load,
+                vl_ldst      : axi_addrgen_q.vl_ldst
               };
 
               // Calculate the addresses for the next iteration
@@ -1042,7 +1039,8 @@ module addrgen import ara_pkg::*; import rvv_pkg::*; #(
                 addr         : paddr,
                 size         : axi_addrgen_q.vew,
                 len          : 0,
-                is_load      : axi_addrgen_q.is_load
+                is_load      : axi_addrgen_q.is_load,
+                vl_ldst      : axi_addrgen_q.vl_ldst
               };
 
               // Account for the requested operands
@@ -1104,7 +1102,8 @@ module addrgen import ara_pkg::*; import rvv_pkg::*; #(
                     addr         : idx_final_paddr,
                     size         : axi_addrgen_q.vew,
                     len          : 0,
-                    is_load      : axi_addrgen_q.is_load
+                    is_load      : axi_addrgen_q.is_load,
+                    vl_ldst      : axi_addrgen_q.vl_ldst
                   };
 
                   // Account for the requested operands
diff --git a/hardware/src/vlsu/align_stage.sv b/hardware/src/vlsu/align_stage.sv
index 4c7708c..1a470ff 100644
--- a/hardware/src/vlsu/align_stage.sv
+++ b/hardware/src/vlsu/align_stage.sv
@@ -30,6 +30,9 @@ module align_stage import ara_pkg::*; import rvv_pkg::*;  #(
   input  logic              rst_ni,
   // Interfaces with Ariane
   input  accelerator_req_t               acc_req_i,
+  // From global_ldst
+  input  logic                        ar_addrgen_ack_i,
+  input  logic                        aw_addrgen_ack_i,
   
   input  axi_req_t axi_req_i,
   output axi_req_t axi_req_o, 
@@ -40,7 +43,7 @@ module align_stage import ara_pkg::*; import rvv_pkg::*;  #(
 
 localparam int unsigned MAXVL_CL = VLEN * NrClusters;
 typedef logic [$clog2(MAXVL_CL+1)-1:0] vlen_cl_t;
-vlen_cl_t vl, vl_d, vl_q; 
+vlen_cl_t vl_ld, vl_st, rd_vl_d, rd_vl_q; 
 vtype_t vtype;
 
 global_dispatcher #(
@@ -51,7 +54,11 @@ global_dispatcher #(
   .clk_i            (clk_i),
   .rst_ni           (rst_ni),
   .acc_req_i        (acc_req_i),
-  .vl_o             (vl),
+  .acc_req_ready_o  (),
+  .ar_addrgen_ack_i (ar_addrgen_ack_i),
+  .aw_addrgen_ack_i (aw_addrgen_ack_i),
+  .vl_ld_o          (vl_ld),
+  .vl_st_o          (vl_st),
   .vtype_o          (vtype)
 );
 
@@ -92,9 +99,9 @@ be_data_t be_final_d, be_final_q;
 
 always_ff @(posedge clk_i or negedge rst_ni) begin
   if(~rst_ni) begin
-    vl_q <= '0;
+    rd_vl_q <= '0;
   end else begin
-    vl_q <= vl_d;
+    rd_vl_q <= rd_vl_d;
   end
 end
 
@@ -191,7 +198,7 @@ always_comb begin
   r_pnt_tracker_d = r_pnt_tracker_q;
   data_prev_d = data_prev_q;
   data_prev_valid_d = data_prev_valid_q;
-  vl_d = vl_q;
+  rd_vl_d = rd_vl_q;
  
   // If a request arrives, add to tracker.
   // Assign shift enable for different stages
@@ -199,16 +206,16 @@ always_comb begin
     automatic int       burst        = axi_req_i.ar.len + 1;
     automatic int       axi_bytes    = AxiDataWidth/8;
     automatic vlen_cl_t vlen_request = ((burst << $clog2(AxiDataWidth/8)) - (axi_req_i.ar.addr[$clog2(AxiDataWidth/8)-1:0])) >> vtype.vsew;
-    vl_d = vl_q + vlen_request;
+    rd_vl_d = rd_vl_q + vlen_request;
 
     tracker_d[w_pnt_tracker_q].addr  = axi_req_i.ar.addr;
-    tracker_d[w_pnt_tracker_q].len   = vl;
+    tracker_d[w_pnt_tracker_q].len   = vl_ld;
     tracker_d[w_pnt_tracker_q].vew   = vtype.vsew;
     for (int s=0; s < NumStages; s++)
       tracker_d[w_pnt_tracker_q].num_requests[s] += 1;
     
     // If the first request
-    if (vl_q == 0) begin
+    if (rd_vl_q == 0) begin
       for (int s=0; s<NumStages; s++) begin 
         if (axi_req_i.ar.addr & (1<<s)) begin 
           tracker_d[w_pnt_tracker_q].shift_en[s] = 1'b1;
@@ -217,8 +224,8 @@ always_comb begin
     end
 
     // If last request
-    if (vl_d >= vl) begin
-      vl_d = 0;
+    if (rd_vl_d >= vl_ld) begin
+      rd_vl_d = 0;
       w_pnt_tracker_d = w_pnt_tracker_q + 1;
       if (w_pnt_tracker_q == NumTrackers-1) begin 
         w_pnt_tracker_d = 0;
@@ -380,7 +387,7 @@ always_comb begin
 
     wr_cnt_d += 1;
     wr_pnt_d = (wr_pnt_q == NumTrackers-1) ? 0 : wr_pnt_q + 1;
-    if (wr_vl_d >= vl) begin
+    if (wr_vl_d >= vl_st) begin
       wr_vl_d = 0;
       b_pnt_d = (b_pnt_q == NumTrackers-1) ? 0 : b_pnt_q + 1;
     end
diff --git a/hardware/src/vlsu/global_dispatcher.sv b/hardware/src/vlsu/global_dispatcher.sv
index 94f6432..aaffbc1 100644
--- a/hardware/src/vlsu/global_dispatcher.sv
+++ b/hardware/src/vlsu/global_dispatcher.sv
@@ -19,27 +19,43 @@ module global_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
     input  logic                                 rst_ni,
     // Interfaces with Ariane
     input  accelerator_req_t                     acc_req_i,
+    output logic                                 acc_req_ready_o,
 
-    output vlen_cl_t vl_o,
+    // Interface with GLSU
+    // To prevent vl_ld/vl_st from changing before the undergoing ld/st finishes
+    input  logic                                 ar_addrgen_ack_i,
+    input  logic                                 aw_addrgen_ack_i,
+
+    output vlen_cl_t vl_ld_o,
+    output vlen_cl_t vl_st_o,
     output vtype_t   vtype_o
 );
   `include "common_cells/registers.svh"
 
-  vlen_cl_t  vl_d, vl_q;
-  vtype_t vtype_d, vtype_q;
+  vlen_cl_t  vl_st_d, vl_st_q;
+  vlen_cl_t  vl_ld_d, vl_ld_q;
+  vtype_t    vtype_d, vtype_q;
+  logic      acc_req_ready_d, acc_req_ready_q;
 
   always_ff @(posedge clk_i or negedge rst_ni) begin
     if(~rst_ni) begin
-        vl_q <= 0;
+        vl_ld_q <= 0;
+        vl_st_q <= 0;
         vtype_q <= '{vill: 1'b1, default: '0};
+        acc_req_ready_q <= 1'b1;
     end else begin
-        vl_q <= vl_d;
+        vl_ld_q <= vl_ld_d;
+        vl_st_q <= vl_st_d;
         vtype_q <= vtype_d;
+        acc_req_ready_q <= acc_req_ready_d;
     end
   end
 
-  assign vl_o = vl_q;
+  assign vl_ld_o = vl_ld_q;
+  assign vl_st_o = vl_st_q;
   assign vtype_o = vtype_q;
+//   assign acc_req_ready_o = acc_req_ready_d;
+  assign acc_req_ready_o = 1'b1;
   
   // Converts between the XLEN-bit vtype CSR and its internal representation
   function automatic vtype_t vtype_xlen(riscv::xlen_t xlen);
@@ -53,80 +69,101 @@ module global_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
   endfunction : vtype_xlen
 
   always_comb begin
-    vl_d = vl_q;
+    vl_ld_d = vl_ld_q;
+    vl_st_d = vl_st_q;
     vtype_d = vtype_q;
+    acc_req_ready_d = acc_req_ready_q;
+
+    if ((!acc_req_ready_q) && (ar_addrgen_ack_i || aw_addrgen_ack_i)) begin
+        acc_req_ready_d = 1'b1;
+    end
 
-    if (acc_req_i.req_valid) begin
+    if (acc_req_i.req_valid && acc_req_ready_q) begin
+        automatic rvv_instruction_t insn = rvv_instruction_t'(acc_req_i.insn.instr);
         // Decode the instructions based on their opcode
         unique case (acc_req_i.insn.itype.opcode)
-        riscv::OpcodeVec: begin
-            automatic rvv_instruction_t insn = rvv_instruction_t'(acc_req_i.insn.instr);
-            unique case (insn.varith_type.func3)
-                OPCFG: begin
-
-                    // Update vtype
-                    if (insn.vsetvli_type.func1 == 1'b0) begin // vsetvli
-                        vtype_d = vtype_xlen(riscv::xlen_t'(insn.vsetvli_type.zimm11));
-                    end else if (insn.vsetivli_type.func2 == 2'b11) begin // vsetivli
-                        vtype_d = vtype_xlen(riscv::xlen_t'(insn.vsetivli_type.zimm10));
-                    end else if (insn.vsetvl_type.func7 == 7'b100_0000) begin // vsetvl
-                        vtype_d = vtype_xlen(riscv::xlen_t'(acc_req_i.rs2[7:0]));
-                    end
+            riscv::OpcodeLoadFp: begin
+                acc_req_ready_d = 1'b0;
+            end
+            riscv::OpcodeStoreFp: begin
+                acc_req_ready_d = 1'b0;
+            end
+            riscv::OpcodeVec: begin
+                acc_req_ready_d = 1'b1;
+                unique case (insn.varith_type.func3)
+                    OPCFG: begin
+                        // Update vtype
+                        if (insn.vsetvli_type.func1 == 1'b0) begin // vsetvli
+                            vtype_d = vtype_xlen(riscv::xlen_t'(insn.vsetvli_type.zimm11));
+                        end else if (insn.vsetivli_type.func2 == 2'b11) begin // vsetivli
+                            vtype_d = vtype_xlen(riscv::xlen_t'(insn.vsetivli_type.zimm10));
+                        end else if (insn.vsetvl_type.func7 == 7'b100_0000) begin // vsetvl
+                            vtype_d = vtype_xlen(riscv::xlen_t'(acc_req_i.rs2[7:0]));
+                        end
 
-                    // Check whether the updated vtype makes sense
-                    if ((vtype_d.vsew > rvv_pkg::vew_e'($clog2(ELENB))) || // SEW <= ELEN
-                        (vtype_d.vlmul == LMUL_RSVD) ||                    // reserved value
-                        // LMUL >= SEW/ELEN
-                        (signed'($clog2(ELENB)) + signed'(vtype_d.vlmul) < signed'(vtype_d.vsew))) begin
-                        vtype_d = '{vill: 1'b1, default: '0};
-                        vl_d    = '0;
-                    end
+                        // Check whether the updated vtype makes sense
+                        if ((vtype_d.vsew > rvv_pkg::vew_e'($clog2(ELENB))) || // SEW <= ELEN
+                            (vtype_d.vlmul == LMUL_RSVD) ||                    // reserved value
+                            // LMUL >= SEW/ELEN
+                            (signed'($clog2(ELENB)) + signed'(vtype_d.vlmul) < signed'(vtype_d.vsew))) begin
+                            vtype_d = '{vill: 1'b1, default: '0};
+                            vl_ld_d    = '0;
+                            vl_st_d    = '0;
+                        end
+
+                        // Update the vector length
+                        else begin
+                            // Maximum vector length. VLMAX = LMUL * VLEN / SEW.
+                            automatic int unsigned vlmax = (VLENB << $clog2(NrClusters)) >> vtype_d.vsew;
+                            unique case (vtype_d.vlmul)
+                                LMUL_1  : vlmax <<= 0;
+                                LMUL_2  : vlmax <<= 1;
+                                LMUL_4  : vlmax <<= 2;
+                                LMUL_8  : vlmax <<= 3;
+                                // Fractional LMUL
+                                LMUL_1_2: vlmax >>= 1;
+                                LMUL_1_4: vlmax >>= 2;
+                                LMUL_1_8: vlmax >>= 3;
+                                default:;
+                            endcase
 
-                    // Update the vector length
-                    else begin
-                        // Maximum vector length. VLMAX = LMUL * VLEN / SEW.
-                        automatic int unsigned vlmax = (VLENB << $clog2(NrClusters)) >> vtype_d.vsew;
-                        unique case (vtype_d.vlmul)
-                            LMUL_1  : vlmax <<= 0;
-                            LMUL_2  : vlmax <<= 1;
-                            LMUL_4  : vlmax <<= 2;
-                            LMUL_8  : vlmax <<= 3;
-                            // Fractional LMUL
-                            LMUL_1_2: vlmax >>= 1;
-                            LMUL_1_4: vlmax >>= 2;
-                            LMUL_1_8: vlmax >>= 3;
-                            default:;
-                        endcase
-
-                        if (insn.vsetivli_type.func2 == 2'b11) begin // vsetivli
-                            vl_d = vlen_t'(insn.vsetivli_type.uimm5);
-                        end else begin // vsetvl || vsetvli
-                            if (insn.vsetvl_type.rs1 == '0 && insn.vsetvl_type.rd == '0) begin
-                                // Do not update the vector length
-                                vl_d = vl_q;
-                            end else if (insn.vsetvl_type.rs1 == '0 && insn.vsetvl_type.rd != '0) begin
-                                // Set the vector length to vlmax
-                                vl_d = vlmax;
-                            end else begin
-                                // Normal stripmining
-                                // vl_d = ((|acc_req_i.rs1[$bits(acc_req_i.rs1)-1:$bits(vl_d)]) ||
-                                //     (vlen_t'(acc_req_i.rs1) > vlmax)) ? vlmax : vlen_t'(acc_req_i.rs1);
-                                if (((|acc_req_i.rs1[$bits(acc_req_i.rs1)-1:$bits(vl_d)]) ||
-                                    (vlen_cl_t'(acc_req_i.rs1) > vlmax))) begin
-                                    vl_d = vlmax;
-                                end else if (|vlen_cl_t'(acc_req_i.rs1[$clog2(NrClusters * NrLanes)-1:0])) begin
-                                    vl_d = vlen_cl_t'(((acc_req_i.rs1 >> $clog2(NrClusters * NrLanes)) + 1) << $clog2(NrClusters * NrLanes));
+                            if (insn.vsetivli_type.func2 == 2'b11) begin // vsetivli
+                                vl_ld_d = vlen_t'(insn.vsetivli_type.uimm5);
+                                vl_st_d = vlen_t'(insn.vsetivli_type.uimm5);
+                            end else begin // vsetvl || vsetvli
+                                if (insn.vsetvl_type.rs1 == '0 && insn.vsetvl_type.rd == '0) begin
+                                    // Do not update the vector length
+                                    vl_ld_d = vl_ld_q;
+                                    vl_st_d = vl_st_q;
+                                end else if (insn.vsetvl_type.rs1 == '0 && insn.vsetvl_type.rd != '0) begin
+                                    // Set the vector length to vlmax
+                                    vl_ld_d = vlmax;
+                                    vl_st_d = vlmax;
                                 end else begin
-                                    vl_d = vlen_cl_t'(acc_req_i.rs1);
+                                    // vl_st_d = ((|acc_req_i.rs1[$bits(acc_req_i.rs1)-1:$bits(vl_st_d)]) ||
+                                    //   (vlen_cl_t'(acc_req_i.rs1) > vlmax)) ? vlmax : vlen_cl_t'(acc_req_i.rs1);
+
+                                    // Normal stripmining
+                                    // vl_d = ((|acc_req_i.rs1[$bits(acc_req_i.rs1)-1:$bits(vl_d)]) ||
+                                    //     (vlen_t'(acc_req_i.rs1) > vlmax)) ? vlmax : vlen_t'(acc_req_i.rs1);
+                                    if (((|acc_req_i.rs1[$bits(acc_req_i.rs1)-1:$bits(vl_ld_d)]) ||
+                                        (vlen_cl_t'(acc_req_i.rs1) > vlmax))) begin
+                                        vl_ld_d = vlmax;
+                                    end else if (|vlen_cl_t'(acc_req_i.rs1[$clog2(NrClusters * NrLanes)-1:0])) begin
+                                        vl_ld_d = vlen_cl_t'(((acc_req_i.rs1 >> $clog2(NrClusters * NrLanes)) + 1) << $clog2(NrClusters * NrLanes));
+                                    end else begin
+                                        vl_ld_d = vlen_cl_t'(acc_req_i.rs1);
+                                    end
+
+                                    vl_st_d = vl_ld_d;
                                 end
                             end
                         end
                     end
-                end
-                default: ;
-            endcase
-        end
-        default: ;
+                    default: ;
+                endcase
+            end
+            default: acc_req_ready_d = 1'b1;
         endcase
     end
   end
diff --git a/hardware/src/vlsu/global_ldst.sv b/hardware/src/vlsu/global_ldst.sv
index 58b920f..772bb47 100644
--- a/hardware/src/vlsu/global_ldst.sv
+++ b/hardware/src/vlsu/global_ldst.sv
@@ -30,10 +30,15 @@ module global_ldst import ara_pkg::*; import rvv_pkg::*;  #(
 
   // Interfaces with Ariane
   input  accelerator_req_t               acc_req_i,
+  output logic                           acc_req_ready_o,
   
   // To ARA
   input  cluster_axi_req_t   [NrClusters-1:0] axi_req_i,
   output cluster_axi_resp_t  [NrClusters-1:0] axi_resp_o,
+
+  // To shuffle stage and align stage
+  output logic                          ar_addrgen_ack_o,
+  output logic                          aw_addrgen_ack_o,
   
   // To System AXI 
   input  axi_resp_t                     axi_resp_i,
@@ -42,9 +47,13 @@ module global_ldst import ara_pkg::*; import rvv_pkg::*;  #(
 
 localparam int unsigned MAXVL_CL = VLEN * NrClusters;
 typedef logic [$clog2(MAXVL_CL+1)-1:0] vlen_cl_t;
-vlen_cl_t vl; 
+vlen_cl_t vl_ld, vl_st; 
 vtype_t vtype;
 
+logic ar_addrgen_ack, aw_addrgen_ack;
+assign ar_addrgen_ack_o = ar_addrgen_ack;
+assign aw_addrgen_ack_o = aw_addrgen_ack;
+
 global_dispatcher #(
   .NrLanes      (NrLanes   ),
   .NrClusters   (NrClusters),
@@ -53,7 +62,11 @@ global_dispatcher #(
   .clk_i            (clk_i),
   .rst_ni           (rst_ni),
   .acc_req_i        (acc_req_i),
-  .vl_o             (vl),
+  .acc_req_ready_o  (acc_req_ready_o),
+  .ar_addrgen_ack_i (ar_addrgen_ack),
+  .aw_addrgen_ack_i (aw_addrgen_ack),
+  .vl_ld_o          (vl_ld),
+  .vl_st_o          (vl_st),
   .vtype_o          (vtype)
 );
 
@@ -64,7 +77,7 @@ import axi_pkg::CACHE_MODIFIABLE;
 
 logic w_ready_q, w_ready_d; // If this unit is ready to receive data from ARA
 logic w_valid_d, w_valid_q; // If this unit has a walid write data to System 
-logic w_last_d, w_last_q;   // If this is a last write packer
+// logic w_last_d, w_last_q;   // If this is a last write packer
 
 // Pointers to clusters to which data has to be written or read from
 logic [$clog2(NrClusters)-1:0] cluster_start_r_d, cluster_start_r_q, cluster_start_wr_d, cluster_start_wr_q;
@@ -109,6 +122,8 @@ always_ff @(posedge clk_i or negedge rst_ni) begin
   end
 end
 
+logic [8:0] w_burst_length, wr_length_check;
+
 always_comb begin : p_global_ldst
   
   // Copy data between ARA<->System
@@ -120,17 +135,20 @@ always_comb begin : p_global_ldst
   w_req_ready = ~w_req_valid_q;
   vl_w_d = vl_w_q;
 
+  ar_addrgen_ack = 1'b0;
+  aw_addrgen_ack = 1'b0;
+
   req_wrmem = '0; 
   req_wrmem.aw_valid = 1'b0; 
   
   if (axi_req_i[0].aw_valid && w_req_ready) begin
     req_d.aw = axi_req_i[0].aw;
     w_req_valid_d = 1'b1;
-    vl_w_d = vl;
+    vl_w_d = vl_st;
   end
 
   if (w_req_valid_d==1'b1 && axi_resp_i.aw_ready) begin
-    automatic logic [8:0] w_burst_length;
+    // automatic logic [8:0] w_burst_length;
     automatic axi_addr_t wr_aligned_start_addr_d, wr_aligned_next_start_addr_d, wr_aligned_end_addr_d;
     automatic logic [($bits(wr_aligned_start_addr_d) - 12)-1:0] wr_next_2page_msb_d;
 
@@ -152,7 +170,8 @@ always_comb begin : p_global_ldst
     end
     // 2 - AXI bursts are at most 256 beats long.
     w_burst_length = MaxAxiBurst;
-    if (w_burst_length > ((wr_aligned_end_addr_d - wr_aligned_start_addr_d) >> size_axi) + 1) begin
+    wr_length_check = ((wr_aligned_end_addr_d - wr_aligned_start_addr_d) >> size_axi) + 1;
+    if (w_burst_length > (((wr_aligned_end_addr_d - wr_aligned_start_addr_d) >> size_axi) + 1)) begin
       w_burst_length = ((wr_aligned_end_addr_d - wr_aligned_start_addr_d) >> size_axi) + 1;
     end else begin
       wr_aligned_next_start_addr_d = wr_aligned_start_addr_d + ((w_burst_length) << size_axi);
@@ -168,6 +187,7 @@ always_comb begin : p_global_ldst
       w_req_valid_d = 1'b1;
     end else begin
       w_req_valid_d = 1'b0;
+      aw_addrgen_ack = 1'b1;
     end
   end
   axi_req_o.aw = req_wrmem.aw;
@@ -191,7 +211,7 @@ always_comb begin : p_global_ldst
   if (axi_req_i[0].ar_valid && r_req_ready) begin 
     req_d.ar = axi_req_i[0].ar;
     r_req_valid_d = 1'b1;
-    vl_req_d = vl;
+    vl_req_d = vl_ld;
   end
 
   if (r_req_valid_d==1'b1 && axi_resp_i.ar_ready) begin
@@ -217,7 +237,9 @@ always_comb begin : p_global_ldst
     end
     // 2 - AXI bursts are at most 256 beats long.
     burst_length = MaxAxiBurst;
-    if (burst_length > ((aligned_end_addr_d - aligned_start_addr_d) >> size_axi) + 1) begin
+    // if (burst_length > ((aligned_end_addr_d - aligned_start_addr_d) >> size_axi) + 1) begin
+    //   burst_length = ((aligned_end_addr_d - aligned_start_addr_d) >> size_axi) + 1;
+    if (burst_length > (((aligned_end_addr_d - aligned_start_addr_d) >> size_axi) + 1)) begin
       burst_length = ((aligned_end_addr_d - aligned_start_addr_d) >> size_axi) + 1;
     end else begin
       aligned_next_start_addr_d = aligned_start_addr_d + ((burst_length) << size_axi);
@@ -233,6 +255,7 @@ always_comb begin : p_global_ldst
     end else begin
       req_d = '0;
       r_req_valid_d = 1'b0;
+      ar_addrgen_ack = 1'b1;
     end
   end
   axi_req_o.ar = req_final.ar;
@@ -243,9 +266,17 @@ always_comb begin : p_global_ldst
   // axi_req_o.ar.len = len_r ? len_r-1 : 0;
   // axi_req_o.ar.size = size_axi;
   // axi_req_o.ar_valid = axi_req_i[0].ar_valid;
+
+
+
+
+
+
   
   // b channel
-  axi_req_o.b_ready = axi_req_i[0].b_ready;                                            
+  axi_req_o.b_ready = 1'b1;
+  for (int i=0; i<NrClusters; i++)
+    axi_req_o.b_ready &= axi_req_i[i].b_ready;                                          
   // r channel
   axi_req_o.r_ready = 1'b1;
   for (int i=0; i<NrClusters; i++)
@@ -313,7 +344,7 @@ always_comb begin : p_global_ldst
     axi_req_data_d[i] = w_cluster_ready_q[i] ? axi_req_i[i] : axi_req_data_q[i];
     w_cluster_last_d[i] = w_cluster_ready_q[i] ? axi_req_i[0].w.last : w_cluster_last_q[i];  // Only expecting last signal from cluster-0
   end
-  w_last_d = w_ready_q ? axi_req_i[0].w.last : w_last_q;
+  // w_last_d = w_ready_q ? axi_req_i[0].w.last : w_last_q;
 
   //if (axi_req_i[0].w_valid) begin : p_valid_write_data
   if (&w_cluster_valid) begin : p_valid_write_data
@@ -347,7 +378,7 @@ always_comb begin : p_global_ldst
         w_valid_d = 1'b0; // We don't have valid data anymore
         if (&w_cluster_last_d) begin
           axi_req_o.w.last = 1'b1;
-          w_last_d = 1'b0;
+          // w_last_d = 1'b0;
           w_cluster_last_d = '0; 
         end
       end
@@ -366,7 +397,7 @@ always_ff @(posedge clk_i or negedge rst_ni) begin
     cluster_start_r_q <= 0;
 
     w_valid_q <= 1'b0;
-    w_last_q <= 1'b0;
+    // w_last_q <= 1'b0;
     cluster_start_wr_q <= 0;
     axi_req_data_q <= '0;
     w_ready_q <= 1'b1;
@@ -378,7 +409,7 @@ always_ff @(posedge clk_i or negedge rst_ni) begin
     cluster_start_r_q <= cluster_start_r_d;
 
     w_valid_q <= w_valid_d;
-    w_last_q <= w_last_d;
+    // w_last_q <= w_last_d;
     cluster_start_wr_q <= cluster_start_wr_d;
     axi_req_data_q <= axi_req_data_d;
     w_ready_q <= w_ready_d;
diff --git a/hardware/src/vlsu/shuffle_stage.sv b/hardware/src/vlsu/shuffle_stage.sv
index ec6412d..aa16741 100644
--- a/hardware/src/vlsu/shuffle_stage.sv
+++ b/hardware/src/vlsu/shuffle_stage.sv
@@ -30,6 +30,9 @@ module shuffle_stage import ara_pkg::*; import rvv_pkg::*;  #(
 
   // Interfaces with Ariane
   input  accelerator_req_t               acc_req_i,
+  // From global_ldst
+  input  logic                        ar_addrgen_ack_i,
+  input  logic                        aw_addrgen_ack_i,
   
   input   axi_req_t  [NrClusters-1:0] axi_req_i,
   output  axi_req_t  [NrClusters-1:0] axi_req_o,
@@ -43,7 +46,7 @@ module shuffle_stage import ara_pkg::*; import rvv_pkg::*;  #(
 
 localparam int unsigned MAXVL_CL = VLEN * NrClusters;
 typedef logic [$clog2(MAXVL_CL+1)-1:0] vlen_cl_t;
-vlen_cl_t vl, vl_d, vl_q; 
+// vlen_cl_t vl, vl_d, vl_q; 
 vtype_t vtype;
 
 global_dispatcher #(
@@ -54,7 +57,11 @@ global_dispatcher #(
   .clk_i            (clk_i),
   .rst_ni           (rst_ni),
   .acc_req_i        (acc_req_i),
-  .vl_o             (vl),
+  .acc_req_ready_o  (),
+  .ar_addrgen_ack_i (ar_addrgen_ack_i),
+  .aw_addrgen_ack_i (aw_addrgen_ack_i),
+  .vl_ld_o          (),
+  .vl_st_o          (),
   .vtype_o          (vtype)
 );
 
@@ -215,7 +222,7 @@ logic r_ready_buf, r_ready_buf_q;
 
 logic rd_buffer_en, rd_buffer_en_last_stage; 
 assign rd_buffer_en = rd_tracker_q[rd_issue_pnt_q[0]].buffer_en;
-assign rd_buffer_en_last_stage = rd_tracker_q[rd_issue_pnt_q[1]].buffer_en;
+assign rd_buffer_en_last_stage = rd_tracker_q[rd_issue_pnt_q[NumStages-1]].buffer_en;
 
 // Write packets
 logic [NrClusters-1:0] [ClusterAxiDataWidth*2-1:0]  wrbuf_d, wrbuf_q;
@@ -228,8 +235,9 @@ logic [NrClusters-1:0] wrbuf_valid, wrbuf_valid_q;
 logic [NrClusters-1:0] wrbuf_full, wrbuf_full_q;
 logic wr_out_ready, wr_out_valid;
 
-logic wr_buffer_en; 
+logic wr_buffer_en, wr_buffer_en_last_stage; 
 assign wr_buffer_en = wr_tracker_q[wr_issue_pnt_q[0]].buffer_en;
+assign wr_buffer_en_last_stage = wr_tracker_q[wr_issue_pnt_q[NumStages-1]].buffer_en;
 
 
 always_ff @(posedge clk_i or negedge rst_ni) begin
@@ -533,8 +541,8 @@ for (genvar c=0; c < NrClusters; c++) begin
   assign w_data_in[0][c] = wr_buffer_en ? '0 : axi_req_i[c].w;              // Copy input write data to first shuffle stage
   assign w_valid_i[c]    = wr_buffer_en ? 1'b0 : axi_req_i[c].w_valid;           // Copy valid signals to stream join
    
-  assign axi_req_o[c].w       = wr_buffer_en ? axi_req_buf_out[c].w       : w_data_out[NumStages-1][c];  // Copy last stage data to req output
-  assign axi_req_o[c].w_valid = wr_buffer_en ? axi_req_buf_out[c].w_valid : w_valid[NumStages-1];   // valid signal is the output valid of stream join
+  assign axi_req_o[c].w       = wr_buffer_en_last_stage ? axi_req_buf_out[c].w       : w_data_out[NumStages-1][c];  // Copy last stage data to req output
+  assign axi_req_o[c].w_valid = wr_buffer_en_last_stage ? axi_req_buf_out[c].w_valid : w_valid[NumStages-1];   // valid signal is the output valid of stream join
 
 end
 assign w_ready[NumStages-1] = axi_resp_i[0].w_ready; // The Global Ld-St is ready to receive write packets together. Hence using only cluster-0 's w_ready.
diff --git a/hardware/src/vlsu/vldu.sv b/hardware/src/vlsu/vldu.sv
index 56a6a7d..505f13d 100644
--- a/hardware/src/vlsu/vldu.sv
+++ b/hardware/src/vlsu/vldu.sv
@@ -317,7 +317,7 @@ module vldu import ara_pkg::*; import rvv_pkg::*; #(
         // How many bytes are valid in this instruction
         automatic vlen_t vinsn_valid_bytes = issue_cnt_bytes_q - vrf_word_byte_cnt_q;
         // How many bytes are valid in this AXI word
-        automatic vlen_t axi_valid_bytes   = AxiDataWidth/8; // upper_byte - lower_byte - r_pnt_q + 1;
+        automatic vlen_t axi_valid_bytes   = AxiDataWidth / 8; // upper_byte - lower_byte - r_pnt_q + 1;
 
 
         // How many bytes are we committing?
diff --git a/hardware/src/vlsu/vstu.sv b/hardware/src/vlsu/vstu.sv
index 9c69881..e7e10e4 100644
--- a/hardware/src/vlsu/vstu.sv
+++ b/hardware/src/vlsu/vstu.sv
@@ -59,8 +59,6 @@ module vstu import ara_pkg::*; import rvv_pkg::*; #(
   );
 
   import cf_math_pkg::idx_width;
-  import axi_pkg::beat_lower_byte;
-  import axi_pkg::beat_upper_byte;
   import axi_pkg::BURST_INCR;
 
   ///////////////////////
@@ -170,6 +168,8 @@ module vstu import ara_pkg::*; import rvv_pkg::*; #(
   axi_pkg::len_t len_d, len_q;
   // - A pointer to which byte in the full VRF word we are reading data from.
   logic [idx_width(DataWidth*NrLanes/8):0] vrf_pnt_d, vrf_pnt_q;
+  logic [DataWidth * NrLanes / 8 - 1 : 0] st_strb_en;
+  assign st_strb_en = ('1 >> axi_addrgen_req_i.vl_ldst);
 
   always_comb begin: p_vstu
     // Maintain state
@@ -206,11 +206,11 @@ module vstu import ara_pkg::*; import rvv_pkg::*; #(
     // - The AXI subsystem is ready to accept this W beat
     if (vinsn_issue_valid && &stu_operand_valid && (vinsn_issue_q.vm || (|mask_valid_i)) &&
         axi_addrgen_req_valid_i && !axi_addrgen_req_i.is_load && axi_w_ready_i) begin
-      // Bytes valid in the current W beat
-      automatic shortint unsigned lower_byte = beat_lower_byte(axi_addrgen_req_i.addr,
-        axi_addrgen_req_i.size, axi_addrgen_req_i.len, BURST_INCR, AxiDataWidth/8, len_q);
-      automatic shortint unsigned upper_byte = beat_upper_byte(axi_addrgen_req_i.addr,
-        axi_addrgen_req_i.size, axi_addrgen_req_i.len, BURST_INCR, AxiDataWidth/8, len_q);
+      // // Bytes valid in the current W beat
+      // automatic shortint unsigned lower_byte = beat_lower_byte(axi_addrgen_req_i.addr,
+      //   axi_addrgen_req_i.size, axi_addrgen_req_i.len, BURST_INCR, AxiDataWidth/8, len_q);
+      // automatic shortint unsigned upper_byte = beat_upper_byte(axi_addrgen_req_i.addr,
+      //   axi_addrgen_req_i.size, axi_addrgen_req_i.len, BURST_INCR, AxiDataWidth/8, len_q);
 
       // Account for the issued bytes
       // How many bytes are valid in this VRF word
@@ -218,7 +218,7 @@ module vstu import ara_pkg::*; import rvv_pkg::*; #(
       // How many bytes are valid in this instruction
       automatic vlen_t vinsn_valid_bytes = issue_cnt_q - vrf_pnt_q;
       // How many bytes are valid in this AXI word
-      automatic vlen_t axi_valid_bytes   = upper_byte - lower_byte + 1;
+      automatic vlen_t axi_valid_bytes   = AxiDataWidth / 8;
 
       // How many bytes are we committing?
       automatic logic [idx_width(DataWidth*NrLanes/8):0] valid_bytes;
@@ -230,22 +230,21 @@ module vstu import ara_pkg::*; import rvv_pkg::*; #(
       // Copy data from the operands into the W channel
       for (int axi_byte = 0; axi_byte < AxiDataWidth/8; axi_byte++) begin
         // Is this byte a valid byte in the W beat?
-        if (axi_byte >= lower_byte && axi_byte <= upper_byte) begin
-          // Map axy_byte to the corresponding byte in the VRF word (sequential)
-          automatic int vrf_seq_byte = axi_byte - lower_byte + vrf_pnt_q;
-          // And then shuffle it
-          automatic int vrf_byte     = shuffle_index(vrf_seq_byte, NrLanes, vinsn_issue_q.eew_vs1);
-
-          // Is this byte a valid byte in the VRF word?
-          if (vrf_seq_byte < issue_cnt_q) begin
-            // At which lane, and what is the byte offset in that lane, of the byte vrf_byte?
-            automatic int vrf_lane   = vrf_byte >> 3;
-            automatic int vrf_offset = vrf_byte[2:0];
-
-            // Copy data
-            axi_w_o.data[8*axi_byte +: 8] = stu_operand[vrf_lane][8*vrf_offset +: 8];
-            axi_w_o.strb[axi_byte]        = vinsn_issue_q.vm || mask_i[vrf_lane][vrf_offset];
-          end
+        // Map axy_byte to the corresponding byte in the VRF word (sequential)
+        automatic int vrf_seq_byte = axi_byte + vrf_pnt_q;
+        // And then shuffle it
+        automatic int vrf_byte     = shuffle_index(vrf_seq_byte, NrLanes, vinsn_issue_q.eew_vs1);
+
+        // Is this byte a valid byte in the VRF word?
+        if (vrf_seq_byte < issue_cnt_q) begin
+          // At which lane, and what is the byte offset in that lane, of the byte vrf_byte?
+          automatic int vrf_lane   = vrf_byte >> 3;
+          automatic int vrf_offset = vrf_byte[2:0];
+
+          // Copy data
+          axi_w_o.data[8*axi_byte +: 8] = stu_operand[vrf_lane][8*vrf_offset +: 8];
+          axi_w_o.strb[axi_byte]        = (vinsn_issue_q.vm || mask_i[vrf_lane][vrf_offset]) && st_strb_en[vrf_seq_byte];
+          // axi_w_o.strb[axi_byte]        = (vinsn_issue_q.vm || mask_i[vrf_lane][vrf_offset]);
         end
       end
 

From f8b60fe74b36bebe925dff5fd2f10ab9f16acb41 Mon Sep 17 00:00:00 2001
From: Hong Pang <hopang@larain5.ee.ethz.ch>
Date: Thu, 23 Oct 2025 21:12:48 +0200
Subject: [PATCH 04/37] [HW] 1. Synchronize vl and vew between Ara and GLSU for
 load/store operation, delete global_dispatcher module; 2. Support effective
 slided data which is not multiple of NrLanes*NrClusters; 3. Support load
 element number which is not multiple of NrLanes*NrClusters; 4. Support
 misaligned processing for VSE; 5. Fix store strb bug; 6. Fix cache-cosistency
 issue between GLSU and scalar core

---
 Bender.yml                             |   1 -
 hardware/src/ara.sv                    |   3 +
 hardware/src/ara_cluster.sv            | 129 +++--
 hardware/src/ara_dispatcher.sv         |   7 +-
 hardware/src/ara_macro.sv              |   7 +-
 hardware/src/lane/lane_sequencer.sv    |   5 +
 hardware/src/sldu/sldu.sv              |  19 +-
 hardware/src/vlsu/addrgen.sv           |  18 +-
 hardware/src/vlsu/align_stage.sv       |  45 +-
 hardware/src/vlsu/global_dispatcher.sv | 172 -------
 hardware/src/vlsu/global_ldst.sv       | 675 +++++++++++++++++++------
 hardware/src/vlsu/shuffle_stage.sv     |  46 +-
 hardware/src/vlsu/vldu.sv              |  13 +-
 hardware/src/vlsu/vlsu.sv              |   2 +
 hardware/src/vlsu/vstu.sv              |  37 +-
 15 files changed, 692 insertions(+), 487 deletions(-)
 delete mode 100644 hardware/src/vlsu/global_dispatcher.sv

diff --git a/Bender.yml b/Bender.yml
index 895eee4..2231773 100644
--- a/Bender.yml
+++ b/Bender.yml
@@ -52,7 +52,6 @@ sources:
     - hardware/src/vlsu/addrgen.sv
     - hardware/src/vlsu/vldu.sv
     - hardware/src/vlsu/vstu.sv
-    - hardware/src/vlsu/global_dispatcher.sv
     - hardware/src/vlsu/global_ldst.sv
     - hardware/src/vlsu/align_stage.sv
     - hardware/src/vlsu/shuffle_stage.sv
diff --git a/hardware/src/ara.sv b/hardware/src/ara.sv
index d39f5f1..78fdaeb 100644
--- a/hardware/src/ara.sv
+++ b/hardware/src/ara.sv
@@ -53,6 +53,8 @@ module ara import ara_pkg::*; import rvv_pkg::*; #(
     input  axi_resp_t         axi_resp_i,
     output vew_e              vew_ar_o,
     output vew_e              vew_aw_o,
+    // vl upper rounded to multiple of NrLanes and each cluster has the same vl_ldst
+    output vlen_t             vl_ldst_o,
 
     // Interface with Ring Interconnect
     output remote_data_t ring_data_o,
@@ -354,6 +356,7 @@ module ara import ara_pkg::*; import rvv_pkg::*; #(
     .axi_resp_i                 (axi_resp_i                                            ),
     .vew_ar_o                   (vew_ar_o                                              ),
     .vew_aw_o                   (vew_aw_o                                              ),
+    .vl_ldst_o                  (vl_ldst_o                                             ),
     // Interface with the dispatcher
     .core_st_pending_i          (core_st_pending                                       ),
     .load_complete_o            (load_complete                                         ),
diff --git a/hardware/src/ara_cluster.sv b/hardware/src/ara_cluster.sv
index a831011..8684d9f 100644
--- a/hardware/src/ara_cluster.sv
+++ b/hardware/src/ara_cluster.sv
@@ -63,6 +63,8 @@ module ara_cluster import ara_pkg::*; import rvv_pkg::*;  #(
 
   );
 
+  `include "common_cells/registers.svh" 
+
   // Number of Clusters configuration
   num_cluster_t numClusters;
   assign numClusters = $clog2(NrClusters);
@@ -80,8 +82,6 @@ module ara_cluster import ara_pkg::*; import rvv_pkg::*;  #(
   axi_req_t  axi_req_cut, axi_req_ldst, axi_req_align, axi_req_align_o;
   axi_resp_t axi_resp_cut, axi_resp_ldst, axi_resp_align, axi_resp_align_i;
 
-  vew_e [NrClusters-1:0] vew_ar, vew_aw;
-
   // Ring connections
   remote_data_t [NrClusters-1:0] ring_data_l, ring_data_r;
   logic [NrClusters-1:0] ring_data_l_ready, ring_data_l_valid, ring_data_r_ready, ring_data_r_valid;
@@ -96,20 +96,29 @@ module ara_cluster import ara_pkg::*; import rvv_pkg::*;  #(
 
   fork_req_t  [nlevels : 0] acc_req_fork;
   fork_resp_t [nlevels : 0] acc_resp_fork;
-  accelerator_resp_t        acc_resp_fork_glb;
 
   // Shuffle stage to ARA cuts
   localparam int ShuffleCuts = $clog2(NrClusters);
+
+  vew_e [NrClusters-1:0]  vew_ar, vew_aw;
+  vew_e                   vew_ar_cut, vew_aw_cut, vew_ar_cut_glsu, vew_aw_cut_glsu, 
+                          vew_ar_glsu2align, vew_aw_glsu2align, vew_ar_align, vew_aw_align;
+  vlen_t [NrClusters-1:0] vl_ldst;
+  vlen_t                  vl_ldst_cut, vl_ldst_cut_glsu, vl_ldst_rd_glsu2align, vl_ldst_wr_glsu2align, 
+                          vl_ldst_rd_align, vl_ldst_wr_align;
+
+  typedef vew_e [NrClusters-1:0] vew_group_t;
+  typedef vlen_t [NrClusters-1:0] vlen_group_t;
+
+  vew_group_t [ShuffleCuts:0] vew_ar_shuffle_cut, vew_aw_shuffle_cut;
+  vlen_group_t [ShuffleCuts:0] vl_ldst_suhffle_cut;
+
   typedef cluster_axi_req_t   [NrClusters-1:0] group_req_t;
   typedef cluster_axi_resp_t  [NrClusters-1:0] group_resp_t;
 
   group_req_t [ShuffleCuts:0] ara_axi_req_shuffle_cut;
   group_resp_t [ShuffleCuts:0] ara_axi_resp_shuffle_cut;
 
-  // GLSU ready to accept new acc req
-  logic acc_req_ready_glsu;
-  logic ar_addrgen_ack, aw_addrgen_ack;
-
   /////////
   // ARA //
   /////////
@@ -171,6 +180,7 @@ module ara_cluster import ara_pkg::*; import rvv_pkg::*;  #(
 
         .vew_ar_o        (vew_ar[cluster]         ),
         .vew_aw_o        (vew_aw[cluster]         ),
+        .vl_ldst_o       (vl_ldst[cluster]        ),
 
         // Ring
         .ring_data_r_i       (ring_data_l_cut        [cluster == NrClusters-1 ? 0 : cluster + 1]     ),
@@ -194,6 +204,10 @@ module ara_cluster import ara_pkg::*; import rvv_pkg::*;  #(
       assign ara_axi_req_shuffle_cut[0][cluster] = ara_axi_req[cluster];
       assign ara_axi_resp[cluster] = ara_axi_resp_shuffle_cut[0][cluster];
 
+      assign vew_ar_shuffle_cut[0][cluster] = vew_ar[cluster];
+      assign vew_aw_shuffle_cut[0][cluster] = vew_aw[cluster];
+      assign vl_ldst_suhffle_cut[0][cluster] = vl_ldst[cluster];
+
       for (genvar s=0; s < ShuffleCuts; s++) begin
         axi_cut #(
           .ar_chan_t   (cluster_axi_ar_t     ),
@@ -213,6 +227,9 @@ module ara_cluster import ara_pkg::*; import rvv_pkg::*;  #(
           .mst_req_o   (ara_axi_req_shuffle_cut [s+1][cluster]),
           .mst_resp_i  (ara_axi_resp_shuffle_cut[s+1][cluster])
         );
+        `FF(vew_ar_shuffle_cut[s+1][cluster], vew_ar_shuffle_cut[s][cluster], vew_e'(1'b0), clk_i, rst_ni);
+        `FF(vew_aw_shuffle_cut[s+1][cluster], vew_aw_shuffle_cut[s][cluster], vew_e'(1'b0), clk_i, rst_ni);
+        `FF(vl_ldst_suhffle_cut[s+1][cluster], vl_ldst_suhffle_cut[s][cluster], '0, clk_i, rst_ni);
       end
   end
 
@@ -336,6 +353,10 @@ module ara_cluster import ara_pkg::*; import rvv_pkg::*;  #(
   // Shuffle stage
   assign ara_axi_req_cut = ara_axi_req_shuffle_cut[ShuffleCuts];
   assign ara_axi_resp_shuffle_cut[ShuffleCuts] = ara_axi_resp_cut;
+  assign vew_ar_cut = vew_ar_shuffle_cut[ShuffleCuts][0];
+  assign vew_aw_cut = vew_aw_shuffle_cut[ShuffleCuts][0];
+  assign vl_ldst_cut = vl_ldst_suhffle_cut[ShuffleCuts][0];
+
   shuffle_stage #(
       .NrLanes            (NrLanes              ),
       .NrClusters         (NrClusters           ),
@@ -349,11 +370,8 @@ module ara_cluster import ara_pkg::*; import rvv_pkg::*;  #(
       .clk_i              (clk_i                ),
       .rst_ni             (rst_ni               ),
 
-      .acc_req_i          (acc_req_fork[nlevels][0] ),
-
-      // To Shuffle stage and Align stage
-      .ar_addrgen_ack_i   (ar_addrgen_ack       ),
-      .aw_addrgen_ack_i   (aw_addrgen_ack       ),
+      .vew_ar_i           (vew_ar_cut),
+      .vew_aw_i           (vew_aw_cut),
 
       .axi_req_i          (ara_axi_req_cut      ),
       .axi_resp_o         (ara_axi_resp_cut     ),
@@ -381,6 +399,10 @@ module ara_cluster import ara_pkg::*; import rvv_pkg::*;  #(
         .mst_req_o   (ldst_axi_req[cluster]),
         .mst_resp_i  (ldst_axi_resp[cluster])
       );
+
+    `FF(vew_ar_cut_glsu, vew_ar_cut, vew_e'(1'b0), clk_i, rst_ni);
+    `FF(vew_aw_cut_glsu, vew_aw_cut, vew_e'(1'b0), clk_i, rst_ni);
+    `FF(vl_ldst_cut_glsu, vl_ldst_cut, '0, clk_i, rst_ni);
   end
 
   // Global Ld/St Unit
@@ -398,17 +420,22 @@ module ara_cluster import ara_pkg::*; import rvv_pkg::*;  #(
     .clk_i              (clk_i              ),
     .rst_ni             (rst_ni             ),
     .acc_req_i          (acc_req_fork[nlevels][0] ),
-    .acc_req_ready_o    (acc_req_ready_glsu ),
     // To Ara
     .axi_req_i          (ldst_axi_req       ),
     .axi_resp_o         (ldst_axi_resp      ),
 
+    .vew_ar_i           (vew_ar_cut_glsu),
+    .vew_aw_i           (vew_aw_cut_glsu),
+    .vl_ldst_i          (vl_ldst_cut_glsu),
+
+    .vew_ar_o           (vew_ar_glsu2align),
+    .vew_aw_o           (vew_aw_glsu2align),
+    .vl_ldst_rd_o       (vl_ldst_rd_glsu2align),
+    .vl_ldst_wr_o       (vl_ldst_wr_glsu2align),
+
     // .axi_req_i       (ara_axi_req_cut    ),
     // .axi_resp_o      (ara_axi_resp_cut   ),
 
-    // To Shuffle stage and Align stage
-    .ar_addrgen_ack_o   (ar_addrgen_ack     ),
-    .aw_addrgen_ack_o   (aw_addrgen_ack     ),
     // To System
     .axi_resp_i         (axi_resp_cut       ),
     .axi_req_o          (axi_req_cut        )
@@ -433,36 +460,38 @@ module ara_cluster import ara_pkg::*; import rvv_pkg::*;  #(
     .mst_resp_i  (axi_resp_ldst)
   );
 
+  `FF(vew_ar_align, vew_ar_glsu2align, vew_e'(1'b0), clk_i, rst_ni);
+  `FF(vew_aw_align, vew_aw_glsu2align, vew_e'(1'b0), clk_i, rst_ni);
+  `FF(vl_ldst_rd_align, vl_ldst_rd_glsu2align, '0, clk_i, rst_ni);
+  `FF(vl_ldst_wr_align, vl_ldst_wr_glsu2align, '0, clk_i, rst_ni);
+
   // Align stage
   align_stage #(
-      .NrLanes          (NrLanes            ),
-      .NrClusters       (NrClusters         ),
-      .AxiDataWidth     (AxiDataWidth       ),
-      .AxiAddrWidth     (AxiAddrWidth       ),
-      .axi_ar_t         (axi_ar_t           ),
-      .axi_aw_t         (axi_aw_t           ),
-      .axi_b_t          (axi_b_t            ),
-      .axi_r_t          (axi_r_t            ),
-      .axi_w_t          (axi_w_t            ),
-      .axi_req_t        (axi_req_t          ),
-      .axi_resp_t       (axi_resp_t         )
-    ) i_align_stage (
-      .clk_i            (clk_i              ),
-      .rst_ni           (rst_ni             ),
-      .acc_req_i        (acc_req_fork[nlevels][0] ),
-
-      // To Shuffle stage and Align stage
-      .ar_addrgen_ack_i (ar_addrgen_ack     ),
-      .aw_addrgen_ack_i (aw_addrgen_ack     ),
-
-      // .axi_req_i        (axi_req_cut        ),
-      // .axi_resp_o       (axi_resp_cut       ),
-
-      .axi_req_i        (axi_req_ldst        ),
-      .axi_resp_o       (axi_resp_ldst       ),
-
-      .axi_req_o        (axi_req_align      ),
-      .axi_resp_i       (axi_resp_align     )
+    .NrLanes          (NrLanes            ),
+    .NrClusters       (NrClusters         ),
+    .AxiDataWidth     (AxiDataWidth       ),
+    .AxiAddrWidth     (AxiAddrWidth       ),
+    .axi_ar_t         (axi_ar_t           ),
+    .axi_aw_t         (axi_aw_t           ),
+    .axi_b_t          (axi_b_t            ),
+    .axi_r_t          (axi_r_t            ),
+    .axi_w_t          (axi_w_t            ),
+    .axi_req_t        (axi_req_t          ),
+    .axi_resp_t       (axi_resp_t         )
+  ) i_align_stage (
+    .clk_i            (clk_i              ),
+    .rst_ni           (rst_ni             ),
+
+    .axi_req_i        (axi_req_ldst        ),
+    .axi_resp_o       (axi_resp_ldst       ),
+
+    .vew_ar_i         (vew_ar_align),
+    .vew_aw_i         (vew_aw_align),
+    .vl_ldst_rd_i     (vl_ldst_rd_align),
+    .vl_ldst_wr_i     (vl_ldst_wr_align),
+
+    .axi_req_o        (axi_req_align      ),
+    .axi_resp_i       (axi_resp_align     )
   );
 
   axi_cut #(
@@ -526,11 +555,7 @@ module ara_cluster import ara_pkg::*; import rvv_pkg::*;  #(
 
   `endif
 
-   
-  always_comb begin
-    acc_resp_fork_glb = acc_resp_fork[0][0];
-    acc_resp_fork_glb.req_ready = acc_resp_fork[0][0].req_ready && acc_req_ready_glsu;
-  end
+
 
   //////////////////
   ////// CVA6 //////
@@ -564,13 +589,11 @@ module ara_cluster import ara_pkg::*; import rvv_pkg::*;  #(
     assign acc_resp_o = resp_cut_o;
 
     assign acc_req_fork[0][0] = req_cut_o;
-    // assign resp_cut_i = acc_resp_fork[0][0];
-    assign resp_cut_i = acc_resp_fork_glb;
+    assign resp_cut_i = acc_resp_fork[0][0];
 
   `else
     assign acc_req_fork[0][0] = acc_req_i;
-    // assign acc_resp_o = acc_resp_fork[0][0];
-    assign acc_resp_o = acc_resp_fork_glb;
+    assign acc_resp_o = acc_resp_fork[0][0];
 
   `endif
 
diff --git a/hardware/src/ara_dispatcher.sv b/hardware/src/ara_dispatcher.sv
index e15d0aa..992c9f3 100644
--- a/hardware/src/ara_dispatcher.sv
+++ b/hardware/src/ara_dispatcher.sv
@@ -3149,7 +3149,8 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
         endcase
 
         if (ara_req_d.op inside {VSLIDEUP, VSLIDEDOWN}) begin
-          ara_req_d.vl = vl_ld_q;
+          ara_req_d.vl      = vl_ld_q;
+          ara_req_d.vl_ldst = vl_q;
         end
       end
 
@@ -3266,8 +3267,8 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
 
     // Any valid non-config instruction is a NOP if vl == 0, with some exceptions,
     // e.g. whole vector memory operations / whole vector register move
-    if (is_decoding && (((vl_q == '0 && (!(ara_req_d.op inside {[VLE:VSXE]}))) || 
-      (vl_ld_q == '0 && (ara_req_d.op inside {[VLE:VSXE]}))) || null_vslideup) && !is_config &&
+    if (is_decoding && (((vl_q == '0 && (!(ara_req_d.op inside {[VLE:VSXE], [VSLIDEUP:VSLIDEDOWN]}))) || 
+      (vl_ld_q == '0 && (ara_req_d.op inside {[VLE:VSXE], [VSLIDEUP:VSLIDEDOWN]}))) || null_vslideup) && !is_config &&
       !ignore_zero_vl_check && !acc_resp_o.error) begin
       // If we are acknowledging a memory operation, we must tell Ariane that the memory
       // operation was resolved (to decrement its pending load/store counter)
diff --git a/hardware/src/ara_macro.sv b/hardware/src/ara_macro.sv
index 4b826f8..cbcd1de 100644
--- a/hardware/src/ara_macro.sv
+++ b/hardware/src/ara_macro.sv
@@ -76,8 +76,8 @@ module ara_macro import ara_pkg::*; import rvv_pkg::*; #(
     input logic          ring_data_l_ready_i,
 
     output vew_e              vew_ar_o,
-    output vew_e              vew_aw_o
-
+    output vew_e              vew_aw_o,
+    output vlen_t             vl_ldst_o
   );
 
   `include "common_cells/registers.svh"
@@ -92,6 +92,7 @@ module ara_macro import ara_pkg::*; import rvv_pkg::*; #(
   logic         sldu_ready_i, sldu_ready_o;
 
   vew_e vew_ar, vew_aw;
+  vlen_t vl_ldst;
   id_cluster_t cluster_id;
   num_cluster_t num_clusters;
 
@@ -123,6 +124,7 @@ module ara_macro import ara_pkg::*; import rvv_pkg::*; #(
 
   `FF(vew_ar_o, vew_ar, vew_e'(1'b0), clk_i, rst_ni);
   `FF(vew_aw_o, vew_aw, vew_e'(1'b0), clk_i, rst_ni);
+  `FF(vl_ldst_o, vl_ldst, '0, clk_i, rst_ni);
   `FF(cluster_id, cluster_id_i, '0, clk_i, rst_ni);
   `FF(num_clusters, num_clusters_i, '0, clk_i, rst_ni);
   
@@ -258,6 +260,7 @@ module ara_macro import ara_pkg::*; import rvv_pkg::*; #(
 
     .vew_ar_o        (vew_ar           ),
     .vew_aw_o        (vew_aw           ),
+    .vl_ldst_o       (vl_ldst          ),
     
     // To Ring Routers
     .ring_data_o         (sldu_o             ), 
diff --git a/hardware/src/lane/lane_sequencer.sv b/hardware/src/lane/lane_sequencer.sv
index e74bd1e..dd83b33 100644
--- a/hardware/src/lane/lane_sequencer.sv
+++ b/hardware/src/lane/lane_sequencer.sv
@@ -38,6 +38,9 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
     input  logic                 [NrVInsn-1:0]            mfpu_vinsn_done_i
   );
 
+  // vlen_t num_el_check;
+  // vlen_t cluster_stride_check;
+
   id_cluster_t max_cluster_id; 
   assign max_cluster_id = (1 << num_clusters_i) - 1;
 
@@ -574,6 +577,8 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
               automatic vlen_t num_el = (cluster_stride * NrLanes * 8) >> pe_req_i.vtype.vsew;
               operand_request_i[SlideAddrGenA].vl =
               (pe_req.vl - num_el + NrLanes - 1) / NrLanes;
+              // cluster_stride_check = cluster_stride;
+              // num_el_check = num_el;
             end
             VSLIDEDOWN: begin
               // Extra elements to ask, because of the stride
diff --git a/hardware/src/sldu/sldu.sv b/hardware/src/sldu/sldu.sv
index 06a21b3..6eec7e1 100644
--- a/hardware/src/sldu/sldu.sv
+++ b/hardware/src/sldu/sldu.sv
@@ -726,7 +726,7 @@ module sldu import ara_pkg::*; import rvv_pkg::*; #(
               issue_cnt_d = vinsn_issue_q.vl << int'(vinsn_issue_q.vtype.vsew);
 
               // Initialize be-enable-generation ancillary signals
-              output_limit_d = issue_cnt_d;
+              output_limit_d = vinsn_issue_q.vl_ldst << int'(vinsn_issue_q.vtype.vsew);
                            
               // issue_cnt_d -= ((cluster_strides + cluster_id_i) >> num_clusters_i) * 8 * NrLanes;   
 
@@ -767,7 +767,8 @@ module sldu import ara_pkg::*; import rvv_pkg::*; #(
               //               ((vinsn_issue_q.vl << int'(vinsn_issue_q.vtype.vsew)) + 8*NrLanes);
               issue_cnt_d = (vinsn_issue_q.use_scalar_op || (vinsn_issue_q.stride == 0)) ? (vinsn_issue_q.vl << int'(vinsn_issue_q.vtype.vsew)) : 
                             ((vinsn_issue_q.vl << int'(vinsn_issue_q.vtype.vsew)) + 8*NrLanes);
-              output_limit_d = vinsn_issue_q.vl << int'(vinsn_issue_q.vtype.vsew);
+              // output_limit_d = vinsn_issue_q.vl << int'(vinsn_issue_q.vtype.vsew);
+              output_limit_d = vinsn_issue_q.vl_ldst << int'(vinsn_issue_q.vtype.vsew);
 
             end
             // Ordered sum reductions
@@ -818,17 +819,23 @@ module sldu import ara_pkg::*; import rvv_pkg::*; #(
           out_en = out_en_flat & ({8*NrLanes{vinsn_issue_q.vm | (vinsn_issue_q.vfu inside {VFU_Alu, VFU_MFpu})}} | mask_q);
 
           // Write in the correct bytes
-          if (init_queue_q && !slidedown_extra_flit) begin
+          if (init_queue_q) begin
             // To initialize the queue only once with the local shifted data
             // The ring data is written later on top of the initialized data
             for (int lane = 0; lane < NrLanes; lane++)
               for (int b = 0; b < 8; b++)
                 if (out_en[lane][b]) begin
-                  result_queue_d[result_queue_write_pnt_q][lane].wdata[8*b +: 8] = sld_op_dst[lane][8*b +: 8];
+                  // If this is the last extra operand flit that is used for highest few elements of SLIDEDOWN, we dont update the wdata
+                  if (!slidedown_extra_flit) begin
+                    result_queue_d[result_queue_write_pnt_q][lane].wdata[8*b +: 8] = sld_op_dst[lane][8*b +: 8];
+                  end
                   result_queue_d[result_queue_write_pnt_q][lane].be[b]           = 1'b1;
                 end else begin
                   // Unchanged policy
-                  result_queue_d[result_queue_write_pnt_q][lane].wdata[8*b +: 8] = sldu_operand_ref[lane][8*b +: 8];
+                  // If this is the last extra operand flit that is used for highest few elements of SLIDEDOWN, we dont update the wdata
+                  if (!slidedown_extra_flit) begin
+                    result_queue_d[result_queue_write_pnt_q][lane].wdata[8*b +: 8] = sldu_operand_ref[lane][8*b +: 8];
+                  end
                   result_queue_d[result_queue_write_pnt_q][lane].be[b]           = 1'b1;
                 end
             init_queue_d = 1'b0;
@@ -1278,7 +1285,7 @@ module sldu import ara_pkg::*; import rvv_pkg::*; #(
               result_queue_cnt_d += 1;
             end
             result_queue_d[result_queue_write_pnt_q2][lane_id].id = vinsn_ring.id;
-            result_queue_d[result_queue_write_pnt_q2][lane_id].be = '1;
+            // result_queue_d[result_queue_write_pnt_q2][lane_id].be = '1;
             
             // For the edge clusters, We need to have the current ring packet and the previous ring packet
             // if (is_edge_cluster) begin
diff --git a/hardware/src/vlsu/addrgen.sv b/hardware/src/vlsu/addrgen.sv
index 68a6700..fb58cf9 100644
--- a/hardware/src/vlsu/addrgen.sv
+++ b/hardware/src/vlsu/addrgen.sv
@@ -28,6 +28,7 @@ module addrgen import ara_pkg::*; import rvv_pkg::*; #(
     output vew_e                           vew_aw_o,
     output logic                           axi_aw_valid_o,
     input  logic                           axi_aw_ready_i,
+    output vlen_t                          vl_ldst_o,
     // Interace with the dispatcher
     input  logic                           core_st_pending_i,
     // Interface with the main sequencer
@@ -198,7 +199,7 @@ module addrgen import ara_pkg::*; import rvv_pkg::*; #(
 
   axi_addr_t lookahead_addr_e_d, lookahead_addr_e_q;
   axi_addr_t lookahead_addr_se_d, lookahead_addr_se_q;
-  vlen_t lookahead_len_d, lookahead_len_q, lookahead_len_ldst_d, lookahead_len_ldst_q;
+  vlen_t lookahead_len_d, lookahead_len_q, lookahead_len_ldst_left_d, lookahead_len_ldst_left_q;
 
   logic [VLEN-1:0] vaddr_start;
 
@@ -209,7 +210,7 @@ module addrgen import ara_pkg::*; import rvv_pkg::*; #(
     lookahead_addr_e_d  = lookahead_addr_e_q;
     lookahead_addr_se_d = lookahead_addr_se_q;
     lookahead_len_d     = lookahead_len_q;
-    lookahead_len_ldst_d = lookahead_len_ldst_q;
+    lookahead_len_ldst_left_d = lookahead_len_ldst_left_q;
 
     // Running vector instructions
     vinsn_running_d = vinsn_running_q & pe_vinsn_running_i;
@@ -264,7 +265,7 @@ module addrgen import ara_pkg::*; import rvv_pkg::*; #(
           lookahead_len_d     = (pe_req_i.vl - pe_req_i.vstart) << unsigned'(pe_req_i.vtype.vsew[1:0]);
           // For synchronization among clusters, vl for vse is always multiplier of NrLanes*NrClusters, but actual write vl may 
           // be smaller. Here we tell vstu module how many data should not be written (i.e. set write enable to zero)
-          lookahead_len_ldst_d = (pe_req_i.vl - pe_req_i.vl_ldst) << unsigned'(pe_req_i.vtype.vsew[1:0]);
+          lookahead_len_ldst_left_d = (pe_req_i.vl - pe_req_i.vl_ldst) << unsigned'(pe_req_i.vtype.vsew[1:0]);
 
           case (pe_req_i.op)
             VLXE, VSXE: begin
@@ -354,7 +355,7 @@ module addrgen import ara_pkg::*; import rvv_pkg::*; #(
           // Unit-strided loads/stores trigger incremental AXI bursts.
           is_burst: (pe_req_q.op inside {VLE, VSE}),
           vstart  : pe_req_q.vstart,
-          vl_ldst : lookahead_len_ldst_q
+          vl_ldst : lookahead_len_ldst_left_q
         };
 
         // Ara does not support misaligned AXI requests
@@ -417,7 +418,7 @@ module addrgen import ara_pkg::*; import rvv_pkg::*; #(
           // Unit-strided loads/stores trigger incremental AXI bursts.
           is_burst: 1'b0,
           vstart  : pe_req_q.vstart,
-          vl_ldst : lookahead_len_ldst_q
+          vl_ldst : lookahead_len_ldst_left_q
         };
         addrgen_req_valid = 1'b1;
 
@@ -632,7 +633,7 @@ module addrgen import ara_pkg::*; import rvv_pkg::*; #(
       lookahead_addr_e_q         <= '0;
       lookahead_addr_se_q        <= '0;
       lookahead_len_q            <= '0;
-      lookahead_len_ldst_q       <= '0;
+      lookahead_len_ldst_left_q       <= '0;
     end else begin
       state_q            <= state_d;
       pe_req_q           <= pe_req_d;
@@ -646,7 +647,7 @@ module addrgen import ara_pkg::*; import rvv_pkg::*; #(
       lookahead_addr_e_q         <= lookahead_addr_e_d;
       lookahead_addr_se_q        <= lookahead_addr_se_d;
       lookahead_len_q            <= lookahead_len_d;
-      lookahead_len_ldst_q       <= lookahead_len_ldst_d;
+      lookahead_len_ldst_left_q       <= lookahead_len_ldst_left_d;
     end
   end
 
@@ -1113,6 +1114,9 @@ module addrgen import ara_pkg::*; import rvv_pkg::*; #(
               end : if_idx_addr_valid_q
             end : indexed_data
 
+            vew_ar_o = vew_e'(axi_addrgen_q.vew);
+            vew_aw_o = vew_e'(axi_addrgen_q.vew);
+            vl_ldst_o = pe_req_q.vl;
             if (axi_addrgen_q.is_burst) begin : unit_stride // UNIT-STRIDED ACCESS
               // AR Channel
               axi_ar_valid_o = axi_addrgen_q.is_load;
diff --git a/hardware/src/vlsu/align_stage.sv b/hardware/src/vlsu/align_stage.sv
index 1a470ff..fbfd37e 100644
--- a/hardware/src/vlsu/align_stage.sv
+++ b/hardware/src/vlsu/align_stage.sv
@@ -28,11 +28,12 @@ module align_stage import ara_pkg::*; import rvv_pkg::*;  #(
   // Clock and Reset
   input  logic              clk_i,
   input  logic              rst_ni,
-  // Interfaces with Ariane
-  input  accelerator_req_t               acc_req_i,
-  // From global_ldst
-  input  logic                        ar_addrgen_ack_i,
-  input  logic                        aw_addrgen_ack_i,
+
+  // vew information to align stage
+  input vew_e                           vew_ar_i,
+  input vew_e                           vew_aw_i,
+  input vlen_t                          vl_ldst_rd_i,
+  input vlen_t                          vl_ldst_wr_i,
   
   input  axi_req_t axi_req_i,
   output axi_req_t axi_req_o, 
@@ -43,24 +44,8 @@ module align_stage import ara_pkg::*; import rvv_pkg::*;  #(
 
 localparam int unsigned MAXVL_CL = VLEN * NrClusters;
 typedef logic [$clog2(MAXVL_CL+1)-1:0] vlen_cl_t;
-vlen_cl_t vl_ld, vl_st, rd_vl_d, rd_vl_q; 
-vtype_t vtype;
-
-global_dispatcher #(
-  .NrLanes      (NrLanes   ),
-  .NrClusters   (NrClusters),
-  .vlen_cl_t    (vlen_cl_t )
-) i_global_dispatcher (
-  .clk_i            (clk_i),
-  .rst_ni           (rst_ni),
-  .acc_req_i        (acc_req_i),
-  .acc_req_ready_o  (),
-  .ar_addrgen_ack_i (ar_addrgen_ack_i),
-  .aw_addrgen_ack_i (aw_addrgen_ack_i),
-  .vl_ld_o          (vl_ld),
-  .vl_st_o          (vl_st),
-  .vtype_o          (vtype)
-);
+
+vlen_cl_t rd_vl_d, rd_vl_q; 
 
 localparam int unsigned NumTrackers=8;
 typedef logic [$clog2(NumTrackers)-1:0] pnt_t; 
@@ -205,12 +190,13 @@ always_comb begin
   if (axi_req_i.ar_valid && axi_resp_o.ar_ready) begin
     automatic int       burst        = axi_req_i.ar.len + 1;
     automatic int       axi_bytes    = AxiDataWidth/8;
-    automatic vlen_cl_t vlen_request = ((burst << $clog2(AxiDataWidth/8)) - (axi_req_i.ar.addr[$clog2(AxiDataWidth/8)-1:0])) >> vtype.vsew;
+    automatic vlen_cl_t vlen_request = ((burst << $clog2(AxiDataWidth/8)) - (axi_req_i.ar.addr[$clog2(AxiDataWidth/8)-1:0])) >> vew_ar_i;
+    // automatic vlen_cl_t vlen_request = (burst << axi_req_i.ar.size) >> vew_ar_i;
     rd_vl_d = rd_vl_q + vlen_request;
 
     tracker_d[w_pnt_tracker_q].addr  = axi_req_i.ar.addr;
-    tracker_d[w_pnt_tracker_q].len   = vl_ld;
-    tracker_d[w_pnt_tracker_q].vew   = vtype.vsew;
+    tracker_d[w_pnt_tracker_q].len   = vl_ldst_rd_i << $clog2(NrClusters);
+    tracker_d[w_pnt_tracker_q].vew   = vew_ar_i;
     for (int s=0; s < NumStages; s++)
       tracker_d[w_pnt_tracker_q].num_requests[s] += 1;
     
@@ -224,7 +210,7 @@ always_comb begin
     end
 
     // If last request
-    if (rd_vl_d >= vl_ld) begin
+    if (rd_vl_d >= (vl_ldst_rd_i << $clog2(NrClusters))) begin
       rd_vl_d = 0;
       w_pnt_tracker_d = w_pnt_tracker_q + 1;
       if (w_pnt_tracker_q == NumTrackers-1) begin 
@@ -379,7 +365,8 @@ always_comb begin
   if (axi_req_i.aw_valid && axi_resp_o.aw_ready) begin
     automatic int       burst        = axi_req_i.aw.len + 1;
     automatic int       axi_bytes    = AxiDataWidth/8;
-    automatic vlen_cl_t vlen_request = ((burst << $clog2(AxiDataWidth/8)) - (axi_req_i.aw.addr[$clog2(AxiDataWidth/8)-1:0])) >> vtype.vsew;
+    // automatic vlen_cl_t vlen_request = ((burst << $clog2(AxiDataWidth/8)) - (axi_req_i.aw.addr[$clog2(AxiDataWidth/8)-1:0])) >> vew_aw_i;
+    automatic vlen_cl_t vlen_request = (burst << axi_req_i.aw.size) >> vew_aw_i;
     wr_vl_d = wr_vl_q + vlen_request;
     
     wr_track_d[wr_pnt_q].len           = axi_req_i.aw.len;
@@ -387,7 +374,7 @@ always_comb begin
 
     wr_cnt_d += 1;
     wr_pnt_d = (wr_pnt_q == NumTrackers-1) ? 0 : wr_pnt_q + 1;
-    if (wr_vl_d >= vl_st) begin
+    if (wr_vl_d >= (vl_ldst_wr_i << $clog2(NrClusters))) begin
       wr_vl_d = 0;
       b_pnt_d = (b_pnt_q == NumTrackers-1) ? 0 : b_pnt_q + 1;
     end
diff --git a/hardware/src/vlsu/global_dispatcher.sv b/hardware/src/vlsu/global_dispatcher.sv
deleted file mode 100644
index aaffbc1..0000000
--- a/hardware/src/vlsu/global_dispatcher.sv
+++ /dev/null
@@ -1,172 +0,0 @@
-// Copyright 2024-2025 ETH Zurich and University of Bologna.
-// Solderpad Hardware License, Version 0.51, see LICENSE for details.
-// SPDX-License-Identifier: SHL-0.51
-//
-// Author: Navaneeth Kunhi Purayil <nkunhi@iis.ee.ethz.ch>
-//
-// Description:
-// Global Dispatcher unit that receives request from CVA6 to decode the 
-// vl and vtype of the current configuration for LdSt requests.
-
-module global_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
-    parameter int unsigned NrLanes    = 0,  // Number of parallel vector lanes.
-    parameter int unsigned NrClusters = 0,
-    parameter type         vlen_cl_t  = logic
-)
-(
-    // Clock and reset
-    input  logic                                 clk_i,
-    input  logic                                 rst_ni,
-    // Interfaces with Ariane
-    input  accelerator_req_t                     acc_req_i,
-    output logic                                 acc_req_ready_o,
-
-    // Interface with GLSU
-    // To prevent vl_ld/vl_st from changing before the undergoing ld/st finishes
-    input  logic                                 ar_addrgen_ack_i,
-    input  logic                                 aw_addrgen_ack_i,
-
-    output vlen_cl_t vl_ld_o,
-    output vlen_cl_t vl_st_o,
-    output vtype_t   vtype_o
-);
-  `include "common_cells/registers.svh"
-
-  vlen_cl_t  vl_st_d, vl_st_q;
-  vlen_cl_t  vl_ld_d, vl_ld_q;
-  vtype_t    vtype_d, vtype_q;
-  logic      acc_req_ready_d, acc_req_ready_q;
-
-  always_ff @(posedge clk_i or negedge rst_ni) begin
-    if(~rst_ni) begin
-        vl_ld_q <= 0;
-        vl_st_q <= 0;
-        vtype_q <= '{vill: 1'b1, default: '0};
-        acc_req_ready_q <= 1'b1;
-    end else begin
-        vl_ld_q <= vl_ld_d;
-        vl_st_q <= vl_st_d;
-        vtype_q <= vtype_d;
-        acc_req_ready_q <= acc_req_ready_d;
-    end
-  end
-
-  assign vl_ld_o = vl_ld_q;
-  assign vl_st_o = vl_st_q;
-  assign vtype_o = vtype_q;
-//   assign acc_req_ready_o = acc_req_ready_d;
-  assign acc_req_ready_o = 1'b1;
-  
-  // Converts between the XLEN-bit vtype CSR and its internal representation
-  function automatic vtype_t vtype_xlen(riscv::xlen_t xlen);
-    vtype_xlen = '{
-      vill  : xlen[riscv::XLEN-1],
-      vma   : xlen[7],
-      vta   : xlen[6],
-      vsew  : vew_e'(xlen[5:3]),
-      vlmul : vlmul_e'(xlen[2:0])
-    };
-  endfunction : vtype_xlen
-
-  always_comb begin
-    vl_ld_d = vl_ld_q;
-    vl_st_d = vl_st_q;
-    vtype_d = vtype_q;
-    acc_req_ready_d = acc_req_ready_q;
-
-    if ((!acc_req_ready_q) && (ar_addrgen_ack_i || aw_addrgen_ack_i)) begin
-        acc_req_ready_d = 1'b1;
-    end
-
-    if (acc_req_i.req_valid && acc_req_ready_q) begin
-        automatic rvv_instruction_t insn = rvv_instruction_t'(acc_req_i.insn.instr);
-        // Decode the instructions based on their opcode
-        unique case (acc_req_i.insn.itype.opcode)
-            riscv::OpcodeLoadFp: begin
-                acc_req_ready_d = 1'b0;
-            end
-            riscv::OpcodeStoreFp: begin
-                acc_req_ready_d = 1'b0;
-            end
-            riscv::OpcodeVec: begin
-                acc_req_ready_d = 1'b1;
-                unique case (insn.varith_type.func3)
-                    OPCFG: begin
-                        // Update vtype
-                        if (insn.vsetvli_type.func1 == 1'b0) begin // vsetvli
-                            vtype_d = vtype_xlen(riscv::xlen_t'(insn.vsetvli_type.zimm11));
-                        end else if (insn.vsetivli_type.func2 == 2'b11) begin // vsetivli
-                            vtype_d = vtype_xlen(riscv::xlen_t'(insn.vsetivli_type.zimm10));
-                        end else if (insn.vsetvl_type.func7 == 7'b100_0000) begin // vsetvl
-                            vtype_d = vtype_xlen(riscv::xlen_t'(acc_req_i.rs2[7:0]));
-                        end
-
-                        // Check whether the updated vtype makes sense
-                        if ((vtype_d.vsew > rvv_pkg::vew_e'($clog2(ELENB))) || // SEW <= ELEN
-                            (vtype_d.vlmul == LMUL_RSVD) ||                    // reserved value
-                            // LMUL >= SEW/ELEN
-                            (signed'($clog2(ELENB)) + signed'(vtype_d.vlmul) < signed'(vtype_d.vsew))) begin
-                            vtype_d = '{vill: 1'b1, default: '0};
-                            vl_ld_d    = '0;
-                            vl_st_d    = '0;
-                        end
-
-                        // Update the vector length
-                        else begin
-                            // Maximum vector length. VLMAX = LMUL * VLEN / SEW.
-                            automatic int unsigned vlmax = (VLENB << $clog2(NrClusters)) >> vtype_d.vsew;
-                            unique case (vtype_d.vlmul)
-                                LMUL_1  : vlmax <<= 0;
-                                LMUL_2  : vlmax <<= 1;
-                                LMUL_4  : vlmax <<= 2;
-                                LMUL_8  : vlmax <<= 3;
-                                // Fractional LMUL
-                                LMUL_1_2: vlmax >>= 1;
-                                LMUL_1_4: vlmax >>= 2;
-                                LMUL_1_8: vlmax >>= 3;
-                                default:;
-                            endcase
-
-                            if (insn.vsetivli_type.func2 == 2'b11) begin // vsetivli
-                                vl_ld_d = vlen_t'(insn.vsetivli_type.uimm5);
-                                vl_st_d = vlen_t'(insn.vsetivli_type.uimm5);
-                            end else begin // vsetvl || vsetvli
-                                if (insn.vsetvl_type.rs1 == '0 && insn.vsetvl_type.rd == '0) begin
-                                    // Do not update the vector length
-                                    vl_ld_d = vl_ld_q;
-                                    vl_st_d = vl_st_q;
-                                end else if (insn.vsetvl_type.rs1 == '0 && insn.vsetvl_type.rd != '0) begin
-                                    // Set the vector length to vlmax
-                                    vl_ld_d = vlmax;
-                                    vl_st_d = vlmax;
-                                end else begin
-                                    // vl_st_d = ((|acc_req_i.rs1[$bits(acc_req_i.rs1)-1:$bits(vl_st_d)]) ||
-                                    //   (vlen_cl_t'(acc_req_i.rs1) > vlmax)) ? vlmax : vlen_cl_t'(acc_req_i.rs1);
-
-                                    // Normal stripmining
-                                    // vl_d = ((|acc_req_i.rs1[$bits(acc_req_i.rs1)-1:$bits(vl_d)]) ||
-                                    //     (vlen_t'(acc_req_i.rs1) > vlmax)) ? vlmax : vlen_t'(acc_req_i.rs1);
-                                    if (((|acc_req_i.rs1[$bits(acc_req_i.rs1)-1:$bits(vl_ld_d)]) ||
-                                        (vlen_cl_t'(acc_req_i.rs1) > vlmax))) begin
-                                        vl_ld_d = vlmax;
-                                    end else if (|vlen_cl_t'(acc_req_i.rs1[$clog2(NrClusters * NrLanes)-1:0])) begin
-                                        vl_ld_d = vlen_cl_t'(((acc_req_i.rs1 >> $clog2(NrClusters * NrLanes)) + 1) << $clog2(NrClusters * NrLanes));
-                                    end else begin
-                                        vl_ld_d = vlen_cl_t'(acc_req_i.rs1);
-                                    end
-
-                                    vl_st_d = vl_ld_d;
-                                end
-                            end
-                        end
-                    end
-                    default: ;
-                endcase
-            end
-            default: acc_req_ready_d = 1'b1;
-        endcase
-    end
-  end
-
-
-endmodule
\ No newline at end of file
diff --git a/hardware/src/vlsu/global_ldst.sv b/hardware/src/vlsu/global_ldst.sv
index 772bb47..5a92256 100644
--- a/hardware/src/vlsu/global_ldst.sv
+++ b/hardware/src/vlsu/global_ldst.sv
@@ -30,70 +30,62 @@ module global_ldst import ara_pkg::*; import rvv_pkg::*;  #(
 
   // Interfaces with Ariane
   input  accelerator_req_t               acc_req_i,
-  output logic                           acc_req_ready_o,
   
   // To ARA
   input  cluster_axi_req_t   [NrClusters-1:0] axi_req_i,
   output cluster_axi_resp_t  [NrClusters-1:0] axi_resp_o,
 
-  // To shuffle stage and align stage
-  output logic                          ar_addrgen_ack_o,
-  output logic                          aw_addrgen_ack_o,
+  input vew_e                           vew_ar_i,
+  input vew_e                           vew_aw_i,
+  input vlen_t                          vl_ldst_i,
+
+  // vew information to align stage
+  output vew_e                           vew_ar_o,
+  output vew_e                           vew_aw_o,
+  output vlen_t                          vl_ldst_rd_o,
+  output vlen_t                          vl_ldst_wr_o,
   
   // To System AXI 
   input  axi_resp_t                     axi_resp_i,
   output axi_req_t                      axi_req_o
 );
 
-localparam int unsigned MAXVL_CL = VLEN * NrClusters;
-typedef logic [$clog2(MAXVL_CL+1)-1:0] vlen_cl_t;
-vlen_cl_t vl_ld, vl_st; 
-vtype_t vtype;
-
-logic ar_addrgen_ack, aw_addrgen_ack;
-assign ar_addrgen_ack_o = ar_addrgen_ack;
-assign aw_addrgen_ack_o = aw_addrgen_ack;
-
-global_dispatcher #(
-  .NrLanes      (NrLanes   ),
-  .NrClusters   (NrClusters),
-  .vlen_cl_t    (vlen_cl_t )
-) i_global_dispatcher (
-  .clk_i            (clk_i),
-  .rst_ni           (rst_ni),
-  .acc_req_i        (acc_req_i),
-  .acc_req_ready_o  (acc_req_ready_o),
-  .ar_addrgen_ack_i (ar_addrgen_ack),
-  .aw_addrgen_ack_i (aw_addrgen_ack),
-  .vl_ld_o          (vl_ld),
-  .vl_st_o          (vl_st),
-  .vtype_o          (vtype)
-);
-
 import cf_math_pkg::idx_width;
 import axi_pkg::aligned_addr;
+import axi_pkg::beat_lower_byte;
+import axi_pkg::beat_upper_byte;
 import axi_pkg::BURST_INCR;
 import axi_pkg::CACHE_MODIFIABLE;
 
-logic w_ready_q, w_ready_d; // If this unit is ready to receive data from ARA
-logic w_valid_d, w_valid_q; // If this unit has a walid write data to System 
-// logic w_last_d, w_last_q;   // If this is a last write packer
+localparam clog2_AxiStrobeWidth = $clog2(AxiDataWidth/8);
+localparam int unsigned MAXVL_CL = VLEN * NrClusters;
+
+typedef logic [$clog2(MAXVL_CL+1)-1:0] vlen_cl_t;
+
+typedef struct packed {
+  axi_pkg::largest_addr_t addr;
+  axi_pkg::size_t size;
+  axi_pkg::len_t len;
+  logic is_load;
+  vlen_cl_t vl_ldst;
+  vew_e vsew;
+} addrgen_cluster_axi_req_t;
+
+logic ar_addrgen_ack, aw_addrgen_ack;
 
 // Pointers to clusters to which data has to be written or read from
 logic [$clog2(NrClusters)-1:0] cluster_start_r_d, cluster_start_r_q, cluster_start_wr_d, cluster_start_wr_q;
+vew_e vew_ar_d, vew_ar_q, vew_aw_d, vew_aw_q;
+vlen_t vl_ldst_rd_d, vl_ldst_rd_q, vl_ldst_wr_d, vl_ldst_wr_q;
 
 cluster_axi_resp_t [NrClusters-1:0] cluster_axi_resp_data_d, cluster_axi_resp_data_q;
-cluster_axi_resp_t [NrClusters-1:0] cluster_axi_resp_data_shuffle;
 cluster_axi_req_t  [NrClusters-1:0] axi_req_data_d, axi_req_data_q; 
 
 // For Shuffling
-logic [NrClusters-1:0] data_valid;
 logic [NrClusters-1:0] w_cluster_valid;
 logic [NrClusters-1:0] w_cluster_ready_d, w_cluster_ready_q;
 logic [NrClusters-1:0] w_cluster_last_d, w_cluster_last_q; 
 
-int len_r, len_w;
-
 // Handle unaligned AXI
 cluster_axi_req_t req_d, req_q;
 axi_req_t req_final;
@@ -104,114 +96,402 @@ axi_req_t req_wrmem;
 logic w_req_valid_d, w_req_valid_q, w_req_ready;
 vlen_cl_t vl_w_d, vl_w_q, vl_w_done;
 
-always_ff @(posedge clk_i or negedge rst_ni) begin
-  if(~rst_ni) begin
-    r_req_valid_q <= 1'b0;
-    req_q         <= '0;
-    vl_req_q      <= '0;
+// AXI burst length
+logic [8:0] w_burst_length;
+// NOTE: all these variables could be narrowed to the minimum number of bits
+logic [12:0] num_beats;
 
-    w_req_valid_q <= 1'b0;
-    vl_w_q        <= '0;
+/////////////////////////////////////
+//  Support for misaligned stores  //
+/////////////////////////////////////
+
+// Narrower AXI Data Byte-Width used for misaligned stores
+logic [clog2_AxiStrobeWidth-1:0]            narrow_axi_data_bwidth;
+// Helper signal to calculate the narrow_axi_data_bwidth
+// It carries information about the misalignment of the start address w.r.t. the AxiDataWidth
+logic [clog2_AxiStrobeWidth-1:0]            axi_addr_misalignment;
+// Number of trailing 0s of axi_addr_misalignment
+logic [idx_width(clog2_AxiStrobeWidth)-1:0] zeroes_cnt;
+
+// If this is the first beat of the write signal
+logic first_beat_d, first_beat_q;
+// A counter of how many beats are left in the current AXI burst
+axi_pkg::len_t wr_axi_len_d, wr_axi_len_q;
+// A pointer to which byte in the full VRF word we are reading data from.
+logic [idx_width(ClusterAxiDataWidth*NrClusters/8):0] wr_data_pnt_d, wr_data_pnt_q;
+
+// Get the misalignment information for this vector memory instruction
+assign axi_addr_misalignment = req_d.aw.addr[clog2_AxiStrobeWidth-1:0];
+
+int unsigned wr_data_seq_byte;
+
+vlen_cl_t wr_issue_cnt_bytes_d, wr_issue_cnt_bytes_q;
+
+vlen_cl_t wr_vinsn_valid_bytes;
+logic [idx_width(ClusterAxiDataWidth*NrClusters/8):0] wr_data_valid_bytes;
+logic [idx_width(AxiDataWidth/8):0] wr_axi_valid_bytes;
+logic [idx_width(AxiDataWidth/8):0] wr_valid_bytes;
+
+logic [ClusterAxiDataWidth*NrClusters-1:0] wr_data_coalesce;
+logic [ClusterAxiDataWidth*NrClusters/8-1:0] wr_strb_coalesce;
+
+logic [idx_width(ClusterAxiDataWidth*NrClusters/8):0] data_eff_write_bytes;
+
+// Have a valid write data to send to System AXI
+generate
+  for (genvar i=0; i<NrClusters; i++) begin
+    assign wr_data_coalesce[i*ClusterAxiDataWidth +: ClusterAxiDataWidth] = axi_req_data_d[i].w.data;
+    assign wr_strb_coalesce[i*ClusterAxiDataWidth/8 +: ClusterAxiDataWidth/8] = axi_req_data_d[i].w.strb;
+  end
+endgenerate
+
+// Calculate the maximum number of Bytes we can send in a store-misaligned beat.
+// This number must be a power of 2 not to get misaligned wrt the pack of data that the
+// store unit receives from the lanes
+lzc #(
+  .WIDTH(clog2_AxiStrobeWidth),
+  .MODE (1'b0                  )
+) i_lzc (
+  .in_i   (axi_addr_misalignment),
+  .cnt_o  (zeroes_cnt           ),
+  .empty_o(/* Unconnected */    )
+);
+
+// Effective AXI data width for misaligned stores
+assign narrow_axi_data_bwidth = (AxiDataWidth/8) >> (clog2_AxiStrobeWidth - zeroes_cnt);
+
+//////////////////////////////
+//  AXI Request Generation  //
+//////////////////////////////
+
+enum logic [2:0] {
+  AXI_ADDRGEN_IDLE,
+  AXI_ADDRGEN_WAITING_CORE_STORE_PENDING,
+  AXI_ADDRGEN_AXI_DW_STORE_MISALIGNED,    // Misaligned vector store to AxiDataWidth/8, needs special treatement
+  AXI_ADDRGEN_REQUESTING                  // Perform AW/AR transactions and push addrgen_req to VSTU/VLDU
+} axi_addrgen_state_d, axi_addrgen_state_q;
+
+axi_addr_t wr_aligned_start_addr_d, wr_aligned_start_addr_q;
+axi_addr_t wr_aligned_next_start_addr_d, wr_aligned_next_start_addr_q, wr_aligned_next_start_addr_temp;
+axi_addr_t wr_aligned_end_addr_d, wr_aligned_end_addr_q, wr_aligned_end_addr_temp;
+
+// MSb of the next-next page (page selector for page 2 positions after the current one)
+logic [($bits(wr_aligned_start_addr_d)-12)-1:0] wr_next_2page_msb_d, wr_next_2page_msb_q;
+
+logic [clog2_AxiStrobeWidth:0]            eff_axi_dw_d, eff_axi_dw_q;
+logic [idx_width(clog2_AxiStrobeWidth):0] eff_axi_dw_log_d, eff_axi_dw_log_q;
+
+function automatic void set_end_addr (
+    input  logic [($bits(axi_addr_t)-12)-1:0]       next_2page_msb,
+    input  vlen_cl_t                                  num_bytes,
+    input  axi_addr_t                                 addr,
+    input  logic [clog2_AxiStrobeWidth:0]             eff_axi_dw,
+    input  logic [idx_width(clog2_AxiStrobeWidth):0]  eff_axi_dw_log,
+    input  axi_addr_t                                 aligned_start_addr,
+    output axi_addr_t                                 aligned_end_addr,
+    output axi_addr_t                                 aligned_next_start_addr
+);
+
+  automatic int unsigned max_burst_bytes = 256 << eff_axi_dw_log;
+
+  // The final address can be found similarly...
+  if (num_bytes >= max_burst_bytes) begin
+      aligned_next_start_addr = aligned_addr(addr + max_burst_bytes, eff_axi_dw_log);
   end else begin
-    r_req_valid_q <= r_req_valid_d;
-    req_q         <= req_d;
-    vl_req_q      <= vl_req_d;
+      aligned_next_start_addr = aligned_addr(addr + num_bytes - 1, eff_axi_dw_log) + eff_axi_dw;
+  end
+  aligned_end_addr = aligned_next_start_addr - 1;
 
-    w_req_valid_q <= w_req_valid_d;
-    vl_w_q        <= vl_w_d;
+  // But since AXI requests are aligned in 4 KiB pages, aligned_end_addr must be in the
+  // same page as aligned_start_addr
+  if (aligned_start_addr[AxiAddrWidth-1:12] != aligned_end_addr[AxiAddrWidth-1:12]) begin
+      aligned_end_addr        = {aligned_start_addr[AxiAddrWidth-1:12], 12'hFFF};
+      aligned_next_start_addr = {                     next_2page_msb  , 12'h000};
   end
-end
+endfunction
+
+//////////////////////////////
+//  Address Queue for Store //
+//////////////////////////////
+
+// Address queue for the vector load/store units
+addrgen_cluster_axi_req_t axi_addrgen_queue;
+addrgen_cluster_axi_req_t axi_addrgen_req;
+logic             axi_addrgen_queue_push;
+logic             axi_addrgen_queue_full;
+logic             axi_addrgen_queue_empty;
+logic             axi_addrgen_queue_pop;
+logic             axi_addrgen_req_ready;
+logic             axi_addrgen_req_valid;
+
+assign axi_addrgen_queue_pop = axi_addrgen_req_ready;
+
+fifo_v3 #(
+  .DEPTH(VaddrgenInsnQueueDepth     ),
+  .dtype(addrgen_cluster_axi_req_t  )
+) i_addrgen_req_queue (
+  .clk_i     (clk_i                                                    ),
+  .rst_ni    (rst_ni                                                   ),
+  .flush_i   (1'b0                                                     ),
+  .testmode_i(1'b0                                                     ),
+  .data_i    (axi_addrgen_queue                                        ),
+  .push_i    (axi_addrgen_queue_push                                   ),
+  .full_o    (axi_addrgen_queue_full                                   ),
+  .data_o    (axi_addrgen_req                                          ),
+  .pop_i     (axi_addrgen_queue_pop                                    ),
+  .empty_o   (axi_addrgen_queue_empty                                  ),
+  .usage_o   (/* Unused */                                             )
+);
+
+assign axi_addrgen_req_valid = !axi_addrgen_queue_empty;
+
+// These are updated only when a new aw/ar is accepted
+assign vew_ar_o = vew_ar_d;
+assign vew_aw_o = vew_aw_d;
+assign vl_ldst_rd_o = vl_ldst_rd_d;
+assign vl_ldst_wr_o = vl_ldst_wr_d;
+
 
-logic [8:0] w_burst_length, wr_length_check;
 
 always_comb begin : p_global_ldst
-  
+  // Maintain state
+  axi_addrgen_state_d = axi_addrgen_state_q;
   // Copy data between ARA<->System
   // Combine Request from Lane Groups
   // Here using Cluster-0 as the request and ignoring the other requests.
   // aw channel
   req_d = req_q;
+
+  wr_aligned_start_addr_d = wr_aligned_start_addr_q;
+  wr_aligned_next_start_addr_d = wr_aligned_next_start_addr_q;
+  wr_aligned_end_addr_d = wr_aligned_end_addr_q;
+
+  wr_aligned_next_start_addr_temp = wr_aligned_next_start_addr_q;
+  wr_aligned_end_addr_temp = wr_aligned_end_addr_q;
+
+  wr_next_2page_msb_d = wr_next_2page_msb_q;
+
+  eff_axi_dw_d = eff_axi_dw_q;
+  eff_axi_dw_log_d = eff_axi_dw_log_q;
+
   w_req_valid_d = w_req_valid_q;
   w_req_ready = ~w_req_valid_q;
   vl_w_d = vl_w_q;
+  vew_aw_d = vew_aw_q;
+
+  wr_axi_len_d = wr_axi_len_q;
+  wr_issue_cnt_bytes_d = wr_issue_cnt_bytes_q;
+  wr_data_pnt_d = wr_data_pnt_q;
+
+  vl_ldst_wr_d = vl_ldst_wr_q;
+  vl_ldst_rd_d = vl_ldst_rd_q;
 
   ar_addrgen_ack = 1'b0;
   aw_addrgen_ack = 1'b0;
 
   req_wrmem = '0; 
   req_wrmem.aw_valid = 1'b0; 
-  
+
+  axi_addrgen_queue = '0;
+  axi_addrgen_queue_push = 1'b0;
+
+
+  wr_data_seq_byte = 0;
+
   if (axi_req_i[0].aw_valid && w_req_ready) begin
     req_d.aw = axi_req_i[0].aw;
     w_req_valid_d = 1'b1;
-    vl_w_d = vl_st;
+    vew_aw_d = vew_aw_i;
+    vl_ldst_wr_d = vl_ldst_i;
+    // vl in terms of byte
+    vl_w_d = (vl_ldst_i << $clog2(NrClusters)) << vew_aw_i;
   end
 
-  if (w_req_valid_d==1'b1 && axi_resp_i.aw_ready) begin
-    // automatic logic [8:0] w_burst_length;
-    automatic axi_addr_t wr_aligned_start_addr_d, wr_aligned_next_start_addr_d, wr_aligned_end_addr_d;
-    automatic logic [($bits(wr_aligned_start_addr_d) - 12)-1:0] wr_next_2page_msb_d;
+  case (axi_addrgen_state_q)
+      AXI_ADDRGEN_IDLE: begin
+        // The start address is found by aligning the original request address by the width of
+        // the memory interface.
+        wr_aligned_start_addr_d = aligned_addr(req_d.aw.addr, clog2_AxiStrobeWidth);
+        // Pre-calculate the next_2page_msb. This should not require much energy if the addr
+        // has zeroes in the upper positions.
+        // We can use this also for the misaligned address calculation, as the next 2 page msb
+        // will be the same either way.
+        wr_next_2page_msb_d = wr_aligned_start_addr_d[AxiAddrWidth-1:12] + 1;
+        // The final address can be found similarly...
+        set_end_addr (
+          wr_next_2page_msb_d,
+          vl_w_d,
+          req_d.aw.addr,
+          AxiDataWidth/8,
+          clog2_AxiStrobeWidth,
+          wr_aligned_start_addr_d,
+          wr_aligned_end_addr_d,
+          wr_aligned_next_start_addr_d
+        );
+
+        if (w_req_valid_d==1'b1) begin
+          axi_addrgen_state_d = acc_req_i.store_pending ? AXI_ADDRGEN_WAITING_CORE_STORE_PENDING : AXI_ADDRGEN_REQUESTING;
+
+          eff_axi_dw_log_d = clog2_AxiStrobeWidth;
+
+          if (req_d.aw.addr[clog2_AxiStrobeWidth-1:0] != '0) begin
+            // Calculate the start and the end addresses in the AXI_ADDRGEN_AXI_DW_STORE_MISALIGNED state
+            axi_addrgen_state_d = AXI_ADDRGEN_AXI_DW_STORE_MISALIGNED;
+
+            eff_axi_dw_d     = {1'b0, narrow_axi_data_bwidth};
+            eff_axi_dw_log_d = zeroes_cnt;
+          end else begin
+            eff_axi_dw_d     = AxiDataWidth/8;
+            eff_axi_dw_log_d = clog2_AxiStrobeWidth;
+          end
+        end
+      end
 
-    req_wrmem.aw        = req_d.aw;             // Copy request state
-    req_wrmem.aw.size   = size_axi;
-    req_wrmem.aw.cache  = CACHE_MODIFIABLE;
-    req_wrmem.aw.burst  = BURST_INCR;
-    req_wrmem.aw_valid = 1'b1;
+      AXI_ADDRGEN_AXI_DW_STORE_MISALIGNED: begin
+        axi_addrgen_state_d = acc_req_i.store_pending ? AXI_ADDRGEN_WAITING_CORE_STORE_PENDING : AXI_ADDRGEN_REQUESTING;
+
+        // The start address is found by aligning the original request address by the width of
+        // the memory interface.
+        wr_aligned_start_addr_d = aligned_addr(req_q.aw.addr, eff_axi_dw_log_q);
+
+        set_end_addr (
+          wr_next_2page_msb_q,
+          vl_w_d,
+          req_q.aw.addr,
+          eff_axi_dw_q,
+          eff_axi_dw_log_q,
+          wr_aligned_start_addr_d,
+          wr_aligned_end_addr_d,
+          wr_aligned_next_start_addr_d
+        );
+      end
 
-    // Check if the address is unaligned for AxiDataWidth bits
-    wr_aligned_start_addr_d = aligned_addr(req_wrmem.aw.addr, size_axi);
-    wr_aligned_next_start_addr_d = aligned_addr(req_wrmem.aw.addr + (vl_w_d << vtype.vsew) -1, size_axi) + AxiDataWidth/8;
-    wr_aligned_end_addr_d = wr_aligned_next_start_addr_d - 1;
-    wr_next_2page_msb_d = wr_aligned_start_addr_d[AxiAddrWidth-1:12] + 1;
-    // 1 - Check for 4KB page boundary
-    if (wr_aligned_start_addr_d[AxiAddrWidth-1:12] != wr_aligned_end_addr_d[AxiAddrWidth-1:12]) begin
-      wr_aligned_end_addr_d        = {wr_aligned_start_addr_d[AxiAddrWidth-1:12], 12'hFFF};
-      wr_aligned_next_start_addr_d = {                       wr_next_2page_msb_d, 12'h000};
-    end
-    // 2 - AXI bursts are at most 256 beats long.
-    w_burst_length = MaxAxiBurst;
-    wr_length_check = ((wr_aligned_end_addr_d - wr_aligned_start_addr_d) >> size_axi) + 1;
-    if (w_burst_length > (((wr_aligned_end_addr_d - wr_aligned_start_addr_d) >> size_axi) + 1)) begin
-      w_burst_length = ((wr_aligned_end_addr_d - wr_aligned_start_addr_d) >> size_axi) + 1;
-    end else begin
-      wr_aligned_next_start_addr_d = wr_aligned_start_addr_d + ((w_burst_length) << size_axi);
-      wr_aligned_end_addr_d = wr_aligned_next_start_addr_d - 1;
-    end
+      AXI_ADDRGEN_WAITING_CORE_STORE_PENDING: begin
+        if (!acc_req_i.store_pending) begin
+          axi_addrgen_state_d = AXI_ADDRGEN_REQUESTING;
+        end
+      end
+
+      AXI_ADDRGEN_REQUESTING : begin
+        automatic logic axi_aw_ready = axi_resp_i.aw_ready;
+        automatic logic [12:0] num_bytes; // Cannot consume more than 4 KiB
+        automatic vlen_cl_t remaining_bytes;
+
+        // Pre-calculate the next_2page_msb. This should not require much energy if the addr
+        // has zeroes in the upper positions.
+        wr_next_2page_msb_d = wr_aligned_next_start_addr_q[AxiAddrWidth-1:12] + 1;
+
+        // Pre-calculate the bytes used in a unit-strided access and the remaining bytes to ask.
+        // The proper way to do so would be aligned_end_addr_q[11:0] + 1 - req_q.aw.addr[11:0].
+        // Avoid explicit computation of aligned_next_start_addr + 1 with a trick that works if
+        // aligned_next_start_addr <= 12'hFFF.
+        if (wr_aligned_end_addr_q[11:0] != 12'hFFF) begin
+          num_bytes = wr_aligned_next_start_addr_q[11:0] - req_q.aw.addr[11:0];
+        end else begin
+        // Special case: aligned_next_start_addr > 12'hFFF.
+          num_bytes = 13'h1000 - req_q.aw.addr[11:0];
+        end
+        remaining_bytes = vl_w_q - num_bytes;
+        if (vl_w_q < num_bytes) begin
+          remaining_bytes = 0;
+        end
+
+        if (!axi_addrgen_queue_full && axi_aw_ready) begin
+          automatic axi_addr_t paddr;
+
+          // Mux target address
+          paddr = req_q.aw.addr;
+
+          // 1 - AXI bursts are at most 256 beats long.
+          w_burst_length = 256;
+          // 2 - The AXI burst length cannot be longer than the number of beats required
+          //     to access the memory regions between aligned_start_addr and
+          //     aligned_end_addr
+          num_beats = ((wr_aligned_end_addr_q[11:0] - wr_aligned_start_addr_q[11:0]) >> eff_axi_dw_log_q) + 1;
+          if (w_burst_length > num_beats) begin
+            w_burst_length = num_beats;
+          end
+
+          // AW Channel
+          req_wrmem.aw = '{
+            addr   : paddr,
+            len    : w_burst_length - 1,
+            // If misaligned store access, reduce the effective AXI width
+            // This hurts performance
+            size   : eff_axi_dw_log_q,
+            cache  : CACHE_MODIFIABLE,
+            burst  : BURST_INCR,
+            default: '0
+          };
+
+          // Send this request to the load/store units
+          axi_addrgen_queue = '{
+            addr         : paddr,
+            len          : w_burst_length - 1,
+            size         : eff_axi_dw_log_q,
+            vl_ldst      : w_burst_length << eff_axi_dw_log_q,
+            vsew         : vew_aw_q,
+            default: '0
+          };
+
+          // Calculate the addresses for the next iteration
+          // TODO: test this for SEW!=64, otherwise this computation is never used
+          // The start address is found by aligning the original request address by the width of
+          // the memory interface. In our case, we have it already.
+          set_end_addr (
+            wr_next_2page_msb_d,
+            vl_w_q - num_bytes,
+            wr_aligned_next_start_addr_q,
+            eff_axi_dw_q,
+            eff_axi_dw_log_q,
+            wr_aligned_next_start_addr_q,
+            wr_aligned_end_addr_temp,
+            wr_aligned_next_start_addr_temp
+          );
+
+          // AW Channel
+          req_wrmem.aw_valid  = 1'b1;
+          // Send this request to the load/store units
+          axi_addrgen_queue_push = 1'b1;
+          // We pre-calculated the values already
+          vl_w_d = remaining_bytes;
+          req_d.aw.addr = wr_aligned_next_start_addr_q;
+
+          wr_aligned_start_addr_d      = req_d.aw.addr;
+          wr_aligned_end_addr_d        = wr_aligned_end_addr_temp;
+          wr_aligned_next_start_addr_d = wr_aligned_next_start_addr_temp;
+
+          // Finished generating AXI requests
+          if (vl_w_d == 0) begin
+            w_req_valid_d = 1'b0;
+            aw_addrgen_ack = 1'b1;
+            axi_addrgen_state_d = AXI_ADDRGEN_IDLE;
+          end
+        end
+      end
+    endcase
+
+    axi_req_o.aw = req_wrmem.aw;
+    axi_req_o.aw_valid = req_wrmem.aw_valid;
 
-    req_wrmem.aw.len = w_burst_length - 1;
 
-    vl_w_done = (wr_aligned_next_start_addr_d - req_d.aw.addr) >> int'(vtype.vsew);
-    if (vl_w_d > vl_w_done) begin
-      vl_w_d -= vl_w_done;
-      req_d.aw.addr = wr_aligned_next_start_addr_d;     // Update request state
-      w_req_valid_d = 1'b1;
-    end else begin
-      w_req_valid_d = 1'b0;
-      aw_addrgen_ack = 1'b1;
-    end
-  end
-  axi_req_o.aw = req_wrmem.aw;
-  axi_req_o.aw_valid = req_wrmem.aw_valid;
-
-  // axi_req_o.aw = axi_req_i[0].aw;
-  // len_w = (axi_req_i[0].aw.len + 1) << axi_req_i[0].aw.size << $clog2(NrClusters) >> size_axi;
-  // axi_req_o.aw.len = len_w ? len_w-1 : 0;
-  // axi_req_o.aw.size = size_axi;
-  // axi_req_o.aw_valid = axi_req_i[0].aw_valid;
-  
   // Alignment is only done for the read request channel AR
   // ar channel
   r_req_valid_d = r_req_valid_q;
+  vew_ar_d = vew_ar_q;
   r_req_ready = ~r_req_valid_q;     // As long as a request is valid, not ready to receive another request
   vl_req_d = vl_req_q;
 
   req_final = '0;                   // Request to be send on AXI
   req_final.ar_valid = 1'b0;
 
-  if (axi_req_i[0].ar_valid && r_req_ready) begin 
+  if (axi_req_i[0].ar_valid && r_req_ready && axi_resp_i.ar_ready) begin 
     req_d.ar = axi_req_i[0].ar;
     r_req_valid_d = 1'b1;
-    vl_req_d = vl_ld;
+    // vl In terms of element number 
+    vl_req_d = vl_ldst_i << $clog2(NrClusters);
+    vew_ar_d = vew_ar_i;
+    vl_ldst_rd_d = vl_ldst_i;
   end
 
   if (r_req_valid_d==1'b1 && axi_resp_i.ar_ready) begin
@@ -227,7 +507,7 @@ always_comb begin : p_global_ldst
 
     // Check if the address is unaligned for AxiDataWidth bits
     aligned_start_addr_d = aligned_addr(req_final.ar.addr, size_axi);
-    aligned_next_start_addr_d = aligned_addr(req_final.ar.addr + (vl_req_d << vtype.vsew) -1, size_axi) + AxiDataWidth/8;
+    aligned_next_start_addr_d = aligned_addr(req_final.ar.addr + (vl_req_d << vew_ar_d) -1, size_axi) + AxiDataWidth/8;
     aligned_end_addr_d = aligned_next_start_addr_d - 1;
     next_2page_msb_d = aligned_start_addr_d[AxiAddrWidth-1:12] + 1;
     // 1 - Check for 4KB page boundary
@@ -247,7 +527,7 @@ always_comb begin : p_global_ldst
     end
 
     req_final.ar.len = burst_length - 1;
-    vl_done = (aligned_next_start_addr_d - req_d.ar.addr) >> int'(vtype.vsew);
+    vl_done = (aligned_next_start_addr_d - req_d.ar.addr) >> int'(vew_ar_d);
     if (vl_req_d > vl_done) begin
       vl_req_d -= vl_done;
       req_d.ar.addr = aligned_next_start_addr_d;     // Update request state
@@ -261,18 +541,6 @@ always_comb begin : p_global_ldst
   axi_req_o.ar = req_final.ar;
   axi_req_o.ar_valid = req_final.ar_valid;
   
-  // axi_req_o.ar = axi_req_i[0].ar;
-  // len_r = (axi_req_i[0].ar.len + 1) << axi_req_i[0].ar.size << $clog2(NrClusters) >> size_axi;
-  // axi_req_o.ar.len = len_r ? len_r-1 : 0;
-  // axi_req_o.ar.size = size_axi;
-  // axi_req_o.ar_valid = axi_req_i[0].ar_valid;
-
-
-
-
-
-
-  
   // b channel
   axi_req_o.b_ready = 1'b1;
   for (int i=0; i<NrClusters; i++)
@@ -327,95 +595,172 @@ always_comb begin : p_global_ldst
   end
 
   /////////// Handle BW mismatch between System and ARA for Write Request
+  axi_req_data_d = axi_req_data_q;
+  first_beat_d   = first_beat_q;
+
+  axi_req_o.w_valid = 1'b0;
+  axi_req_o.w       = '0;
+
+  axi_addrgen_req_ready = 1'b0;
 
   for (int i=0; i<NrClusters; i++) begin
     w_cluster_valid[i] = axi_req_i[i].w_valid;
     w_cluster_ready_d[i] = w_cluster_ready_q[i] ? ~axi_req_i[i].w_valid : w_cluster_ready_q[i];
   end
 
-  cluster_start_wr_d = cluster_start_wr_q;
-  axi_req_data_d = axi_req_data_q;
-  
-  w_valid_d = w_valid_q;
-  w_ready_d = w_ready_q;
-  // If we are ready to receive data, receive new request
-  // otherwise assign previous request state.
   for (int i=0; i<NrClusters; i++) begin
     axi_req_data_d[i] = w_cluster_ready_q[i] ? axi_req_i[i] : axi_req_data_q[i];
     w_cluster_last_d[i] = w_cluster_ready_q[i] ? axi_req_i[0].w.last : w_cluster_last_q[i];  // Only expecting last signal from cluster-0
   end
-  // w_last_d = w_ready_q ? axi_req_i[0].w.last : w_last_q;
 
-  //if (axi_req_i[0].w_valid) begin : p_valid_write_data
-  if (&w_cluster_valid) begin : p_valid_write_data
-    // If Total BW of all clusters == System AXI BW, we can support full write
-    // BW, otherwise set not ready to receive data.
-    w_ready_d = is_full_bw ? axi_resp_i.w_ready : 1'b0;
-    w_valid_d = 1'b1;
-  end : p_valid_write_data
+  if (axi_addrgen_req_valid && axi_resp_i.w_ready) begin
+    // Bytes valid in the current W beat
+    automatic shortint unsigned lower_byte = beat_lower_byte(axi_addrgen_req.addr,
+      axi_addrgen_req.size, axi_addrgen_req.len, BURST_INCR, AxiDataWidth/8, wr_axi_len_q);
+    automatic shortint unsigned upper_byte = beat_upper_byte(axi_addrgen_req.addr,
+      axi_addrgen_req.size, axi_addrgen_req.len, BURST_INCR, AxiDataWidth/8, wr_axi_len_q);
 
-  axi_req_o.w_valid = 1'b0;
-  axi_req_o.w = '0;
-  
-  if (w_valid_d) begin
-    // Have a valid write data to send to System AXI
-    for (int i=0; i<(AxiDataWidth/ClusterAxiDataWidth); i++) begin
-      axi_req_o.w.data[i*ClusterAxiDataWidth +: ClusterAxiDataWidth] = axi_req_data_d[cluster_start_wr_q + i].w.data;
-      axi_req_o.w.strb[i*ClusterAxiDataWidth/8 +: ClusterAxiDataWidth/8] = axi_req_data_d[cluster_start_wr_q + i].w.strb;
-      axi_req_o.w.user = axi_req_data_d[cluster_start_wr_q + i].w.user;
+    if (first_beat_q) begin
+      wr_issue_cnt_bytes_d = axi_addrgen_req.vl_ldst;
     end
-    axi_req_o.w_valid = 1'b1;
-    axi_req_o.w.last = 1'b0;
-    
-    if (axi_resp_i.w_ready) begin
-      // If downstream AXI is ready to receive request only then update the
-      // pointer to cluster data.
-      cluster_start_wr_d = cluster_start_wr_q + (AxiDataWidth/ClusterAxiDataWidth);
-      if (cluster_start_wr_q == (NrClusters - (AxiDataWidth/ClusterAxiDataWidth))) begin
-        cluster_start_wr_d = 0;
-        w_ready_d = 1'b1; // Once all write data from all clusters sent, then we are ready to receive data from clusters.
-        w_cluster_ready_d = '1; 
-        w_valid_d = 1'b0; // We don't have valid data anymore
-        if (&w_cluster_last_d) begin
-          axi_req_o.w.last = 1'b1;
-          // w_last_d = 1'b0;
-          w_cluster_last_d = '0; 
+
+    // Account for the issued bytes
+    // How many bytes are valid in this VRF word
+    wr_data_valid_bytes  = AxiDataWidth/8 - wr_data_pnt_q;
+    // How many bytes are valid in this AXI word
+    wr_axi_valid_bytes   = upper_byte - lower_byte + 1;
+
+    wr_valid_bytes = (wr_data_valid_bytes  < wr_axi_valid_bytes) ? wr_data_valid_bytes    : wr_axi_valid_bytes;
+
+    if (&w_cluster_valid) begin
+      first_beat_d  = 1'b0;
+      wr_data_pnt_d = wr_data_pnt_q + wr_valid_bytes;
+
+      // Copy data from the operands into the W channel
+      for (int unsigned axi_byte = 0; axi_byte < AxiDataWidth/8; axi_byte++) begin
+        // Is this byte a valid byte in the W beat?
+        if (axi_byte >= lower_byte && axi_byte <= upper_byte) begin
+          // Map axy_byte to the corresponding byte in the VRF word (sequential)
+          wr_data_seq_byte = axi_byte - lower_byte + wr_data_pnt_q;
+          // Copy data
+          axi_req_o.w.data[8*axi_byte +: 8] = wr_data_coalesce[8*wr_data_seq_byte +: 8];
+          axi_req_o.w.strb[axi_byte]        = wr_strb_coalesce[wr_data_seq_byte];
+          // To check if we write any x data into the memory
+          if ($isunknown(axi_req_o.w.data[8*axi_byte +: 8]) && axi_req_o.w.strb[axi_byte]) begin
+            $error("ASSERTION FAILED: data is X when valid=1");
+          end
+          // Currently directly wired to cluster 0 user signal, can be changed according to needs
+          axi_req_o.w.user                  = axi_req_data_d[0].w.user;
         end
       end
+
+      // Send the W beat
+      axi_req_o.w_valid = 1'b1;
+      // Account for the beat we sent
+      wr_axi_len_d  = wr_axi_len_q + 1;
+      // We wrote all the beats for this AW burst
+      if ($unsigned(wr_axi_len_d) == axi_pkg::len_t'($unsigned(axi_addrgen_req.len) + 1)) begin : beats_complete
+        axi_req_o.w.last        = 1'b1;
+        // Ask for another burst by the address generator
+        axi_addrgen_req_ready   = 1'b1;
+        // Prepare for the first beat for next aw req
+        first_beat_d         = 1'b1;
+        // Reset AXI pointers
+        wr_axi_len_d            = '0;
+      end : beats_complete
+
+      // We consumed a whole word from the lanes
+      if (wr_data_pnt_d == (ClusterAxiDataWidth*NrClusters/8)) begin
+        // Reset the pointer in the VRF word
+        wr_data_pnt_d         = '0;
+
+        // Acknowledge the operands from the clusters
+        w_cluster_ready_d = '1; 
+        // Account for the results that were issued
+        data_eff_write_bytes = ClusterAxiDataWidth*NrClusters/8;
+
+        wr_issue_cnt_bytes_d = wr_issue_cnt_bytes_q - data_eff_write_bytes;
+        if (wr_issue_cnt_bytes_q < data_eff_write_bytes) begin : issue_cnt_bytes_overflow
+          wr_issue_cnt_bytes_d = '0;
+        end : issue_cnt_bytes_overflow
+      end
     end
   end
 
   for (int i=0; i<NrClusters; i++) begin
-    axi_resp_o[i].w_ready = w_cluster_ready_q[i];
+    axi_resp_o[i].w_ready = w_cluster_ready_d[i];
   end
-
 end : p_global_ldst
 
 always_ff @(posedge clk_i or negedge rst_ni) begin
   if(~rst_ni) begin
+    r_req_valid_q <= 1'b0;
+    req_q         <= '0;
+    vl_req_q      <= '0;
+    vew_ar_q      <= vew_e'(0);
+    vew_aw_q      <= vew_e'(0);
+    vl_ldst_rd_q  <= '0;
+    vl_ldst_wr_q  <= '0;
+
+    w_req_valid_q <= 1'b0;
+    vl_w_q        <= '0;
+
     cluster_axi_resp_data_q <= '0;
     cluster_start_r_q <= 0;
 
-    w_valid_q <= 1'b0;
-    // w_last_q <= 1'b0;
     cluster_start_wr_q <= 0;
     axi_req_data_q <= '0;
-    w_ready_q <= 1'b1;
 
     w_cluster_ready_q <= '1;
     w_cluster_last_q  <= '0;
+
+    axi_addrgen_state_q <= AXI_ADDRGEN_IDLE;
+
+    wr_aligned_start_addr_q <= '0;
+    wr_aligned_next_start_addr_q <= '0;
+    wr_aligned_end_addr_q <= '0;
+    wr_next_2page_msb_q <= '0;
+    eff_axi_dw_q <= '0;
+    eff_axi_dw_log_q <= '0;
+
+    first_beat_q <= 1'b1;
+    wr_axi_len_q <= '0;
+    wr_issue_cnt_bytes_q <= '0;
+    wr_data_pnt_q <= '0;
   end else begin
+    r_req_valid_q <= r_req_valid_d;
+    req_q         <= req_d;
+    vl_req_q      <= vl_req_d;
+    vew_ar_q      <= vew_ar_d;
+    vew_aw_q      <= vew_aw_d;
+    vl_ldst_rd_q  <= vl_ldst_rd_d;
+    vl_ldst_wr_q  <= vl_ldst_wr_d;
+
+    w_req_valid_q <= w_req_valid_d;
+    vl_w_q        <= vl_w_d;
+
     cluster_axi_resp_data_q <= cluster_axi_resp_data_d;
     cluster_start_r_q <= cluster_start_r_d;
 
-    w_valid_q <= w_valid_d;
-    // w_last_q <= w_last_d;
     cluster_start_wr_q <= cluster_start_wr_d;
     axi_req_data_q <= axi_req_data_d;
-    w_ready_q <= w_ready_d;
 
     w_cluster_ready_q <= w_cluster_ready_d;
     w_cluster_last_q  <= w_cluster_last_d; 
+
+    axi_addrgen_state_q <= axi_addrgen_state_d;
+
+    wr_aligned_start_addr_q <= wr_aligned_start_addr_d;
+    wr_aligned_next_start_addr_q <= wr_aligned_next_start_addr_d;
+    wr_aligned_end_addr_q <= wr_aligned_end_addr_d;
+    wr_next_2page_msb_q <= wr_next_2page_msb_d;
+    eff_axi_dw_q <= eff_axi_dw_d;
+    eff_axi_dw_log_q <= eff_axi_dw_log_d;
+
+    first_beat_q <= first_beat_d;
+    wr_axi_len_q <= wr_axi_len_d;
+    wr_issue_cnt_bytes_q <= wr_issue_cnt_bytes_d;
+    wr_data_pnt_q <= wr_data_pnt_d;
   end
 end
 
diff --git a/hardware/src/vlsu/shuffle_stage.sv b/hardware/src/vlsu/shuffle_stage.sv
index aa16741..abe0056 100644
--- a/hardware/src/vlsu/shuffle_stage.sv
+++ b/hardware/src/vlsu/shuffle_stage.sv
@@ -27,43 +27,19 @@ module shuffle_stage import ara_pkg::*; import rvv_pkg::*;  #(
   // Clock and Reset
   input  logic              clk_i,
   input  logic              rst_ni,
-
-  // Interfaces with Ariane
-  input  accelerator_req_t               acc_req_i,
-  // From global_ldst
-  input  logic                        ar_addrgen_ack_i,
-  input  logic                        aw_addrgen_ack_i,
+  
+  input vew_e vew_ar_i,
+  input vew_e vew_aw_i,
   
   input   axi_req_t  [NrClusters-1:0] axi_req_i,
   output  axi_req_t  [NrClusters-1:0] axi_req_o,
 
   input   axi_resp_t [NrClusters-1:0] axi_resp_i,
   output  axi_resp_t [NrClusters-1:0] axi_resp_o
-
-  // input vew_e vew_ar_i,
-  // input vew_e vew_aw_i
 );
 
 localparam int unsigned MAXVL_CL = VLEN * NrClusters;
 typedef logic [$clog2(MAXVL_CL+1)-1:0] vlen_cl_t;
-// vlen_cl_t vl, vl_d, vl_q; 
-vtype_t vtype;
-
-global_dispatcher #(
-  .NrLanes      (NrLanes   ),
-  .NrClusters   (NrClusters),
-  .vlen_cl_t    (vlen_cl_t )
-) i_global_dispatcher (
-  .clk_i            (clk_i),
-  .rst_ni           (rst_ni),
-  .acc_req_i        (acc_req_i),
-  .acc_req_ready_o  (),
-  .ar_addrgen_ack_i (ar_addrgen_ack_i),
-  .aw_addrgen_ack_i (aw_addrgen_ack_i),
-  .vl_ld_o          (),
-  .vl_st_o          (),
-  .vtype_o          (vtype)
-);
 
 typedef struct packed {
   axi_addr_t addr;
@@ -104,8 +80,8 @@ logic [NrClusters-1:0] r_ready_i, r_valid_o;
 logic [NrClusters-1:0] w_valid_i, w_ready_o;
 
 logic rd_full, wr_full;
-assign rd_full = (rd_cnt_q == NumTrackers);
-assign wr_full = (wr_cnt_q == NumTrackers);
+assign rd_full = (rd_cnt_q >= NumTrackers);
+assign wr_full = (wr_cnt_q >= NumTrackers);
 
 // To handle cases where vlsu of each cluster is ready to 
 // receive read resp or not.
@@ -317,29 +293,29 @@ always_comb begin
 
   // If a request arrives, add to tracker.
   if (axi_req_i[0].ar_valid & axi_resp_o[0].ar_ready) begin
-    rd_tracker_d[rd_accept_pnt_q].vew = vtype.vsew; //vew_ar_i;
+    rd_tracker_d[rd_accept_pnt_q].vew = vew_ar_i; //vew_ar_i;
     for (int c=0; c<NrClusters; c++)
       rd_tracker_d[rd_accept_pnt_q].len[c] = axi_req_i[0].ar.len+1;
     rd_accept_pnt_d = (rd_accept_pnt_q == NumTrackers-1) ? '0 : rd_accept_pnt_q + 1;
     rd_cnt_d += 1;
 
     for (int s=0; s<NumStages; s++) begin
-      rd_tracker_d[rd_accept_pnt_q].shuffle_en[s] = (s >= vtype.vsew) ? 1'b1 : 1'b0;
+      rd_tracker_d[rd_accept_pnt_q].shuffle_en[s] = (s >= vew_ar_i) ? 1'b1 : 1'b0;
     end
-    rd_tracker_d[rd_accept_pnt_q].buffer_en = NumStages < vtype.vsew ? 1'b1 : 1'b0;
+    rd_tracker_d[rd_accept_pnt_q].buffer_en = NumStages < vew_ar_i ? 1'b1 : 1'b0;
   end
 
   if (axi_req_i[0].aw_valid & axi_resp_o[0].aw_ready) begin
-    wr_tracker_d[wr_accept_pnt_q].vew = vtype.vsew; //vew_aw_i;
+    wr_tracker_d[wr_accept_pnt_q].vew = vew_aw_i; //vew_aw_i;
     for (int c=0; c<NrClusters; c++)
       wr_tracker_d[wr_accept_pnt_q].len[c] = axi_req_i[0].aw.len+1;
     wr_accept_pnt_d = (wr_accept_pnt_q == NumTrackers-1) ? '0 : wr_accept_pnt_q + 1; 
     wr_cnt_d += 1;
 
     for (int s=0; s<NumStages; s++) begin
-      wr_tracker_d[wr_accept_pnt_q].shuffle_en[s] = (s >= vtype.vsew) ? 1'b1 : 1'b0;
+      wr_tracker_d[wr_accept_pnt_q].shuffle_en[s] = (s >= vew_aw_i) ? 1'b1 : 1'b0;
     end
-    wr_tracker_d[wr_accept_pnt_q].buffer_en = NumStages < vtype.vsew ? 1'b1 : 1'b0;
+    wr_tracker_d[wr_accept_pnt_q].buffer_en = NumStages < vew_aw_i ? 1'b1 : 1'b0;
   end
 
   // Update counters for shuffle stage
diff --git a/hardware/src/vlsu/vldu.sv b/hardware/src/vlsu/vldu.sv
index 505f13d..d9faf51 100644
--- a/hardware/src/vlsu/vldu.sv
+++ b/hardware/src/vlsu/vldu.sv
@@ -351,9 +351,18 @@ module vldu import ara_pkg::*; import rvv_pkg::*; #(
             // Copy data and byte strobe
             result_queue_d[result_queue_write_pnt_q][vrf_lane].wdata[8*vrf_offset +: 8] =
               axi_r_i.data[8*axi_byte +: 8];
-            result_queue_d[result_queue_write_pnt_q][vrf_lane].be[vrf_offset] =
-              vinsn_issue_q.vm || mask_q[vrf_lane][vrf_offset];
+            // result_queue_d[result_queue_write_pnt_q][vrf_lane].be[vrf_offset] =
+            //   vinsn_issue_q.vm || mask_q[vrf_lane][vrf_offset];
           end : is_vrf_byte
+
+          if (vrf_seq_byte_cnt < (issue_cnt_bytes_q - axi_addrgen_req_i.vl_ldst) && vrf_seq_byte < (NrLanes * DataWidthB)) begin
+            // At which lane, and what is the byte offset in that lane, of the byte vrf_byte?
+            automatic int unsigned vrf_offset = vrf_byte[2:0];
+            // Make sure this index wraps around the number of lane
+            automatic int unsigned vrf_lane = (vrf_byte >> 3);
+            // Some data might not be written due to the actual vl non-multiple of NrLanes*NrClusters
+            result_queue_d[result_queue_write_pnt_q][vrf_lane].be[vrf_offset] = (vinsn_issue_q.vm || mask_i[vrf_lane][vrf_offset]);
+          end
         end : axi_r_to_result_queue
 
         for (int unsigned lane = 0; lane < NrLanes; lane++) begin : compute_vrf_addr
diff --git a/hardware/src/vlsu/vlsu.sv b/hardware/src/vlsu/vlsu.sv
index 476e4b6..0f9d899 100644
--- a/hardware/src/vlsu/vlsu.sv
+++ b/hardware/src/vlsu/vlsu.sv
@@ -31,6 +31,7 @@ module vlsu import ara_pkg::*; import rvv_pkg::*; #(
     output axi_req_t                axi_req_o,
     output vew_e                    vew_ar_o,
     output vew_e                    vew_aw_o,
+    output vlen_t                   vl_ldst_o,
     input  axi_resp_t               axi_resp_i,
     // Interface with the dispatcher
     input  logic                    core_st_pending_i,
@@ -136,6 +137,7 @@ module vlsu import ara_pkg::*; import rvv_pkg::*; #(
     .vew_ar_o                   (vew_ar                     ), 
     .axi_ar_valid_o             (axi_req.ar_valid           ),
     .axi_ar_ready_i             (axi_resp.ar_ready          ),
+    .vl_ldst_o                  (vl_ldst_o                  ),
     // Interface with dispatcher
     .core_st_pending_i          (core_st_pending_i          ),
     // Interface with the sequencer
diff --git a/hardware/src/vlsu/vstu.sv b/hardware/src/vlsu/vstu.sv
index e7e10e4..2d9dff5 100644
--- a/hardware/src/vlsu/vstu.sv
+++ b/hardware/src/vlsu/vstu.sv
@@ -168,8 +168,9 @@ module vstu import ara_pkg::*; import rvv_pkg::*; #(
   axi_pkg::len_t len_d, len_q;
   // - A pointer to which byte in the full VRF word we are reading data from.
   logic [idx_width(DataWidth*NrLanes/8):0] vrf_pnt_d, vrf_pnt_q;
+
+  // Some data might not be written due to the actual vl non-multiple of NrLanes*NrClusters
   logic [DataWidth * NrLanes / 8 - 1 : 0] st_strb_en;
-  assign st_strb_en = ('1 >> axi_addrgen_req_i.vl_ldst);
 
   always_comb begin: p_vstu
     // Maintain state
@@ -222,6 +223,22 @@ module vstu import ara_pkg::*; import rvv_pkg::*; #(
 
       // How many bytes are we committing?
       automatic logic [idx_width(DataWidth*NrLanes/8):0] valid_bytes;
+
+      // Account for the beat we sent
+      len_d      = len_q + 1;
+      // st_strb_en is all 1s by default
+      st_strb_en = '1; 
+      // We wrote all the beats for this AW burst
+      if ($unsigned(len_d) == axi_pkg::len_t'($unsigned(axi_addrgen_req_i.len) + 1)) begin
+        axi_w_o.last            = 1'b1;
+        // // Some data might not be written due to the actual vl non-multiple of NrLanes*NrClusters
+        // st_strb_en = ('1 >> axi_addrgen_req_i.vl_ldst);
+        // Ask for another burst by the address generator
+        axi_addrgen_req_ready_o = 1'b1;
+        // Reset AXI pointers
+        len_d                   = '0;
+      end
+
       valid_bytes = issue_cnt_q < NrLanes * 8     ? vinsn_valid_bytes : vrf_valid_bytes;
       valid_bytes = valid_bytes < axi_valid_bytes ? valid_bytes       : axi_valid_bytes;
 
@@ -243,23 +260,19 @@ module vstu import ara_pkg::*; import rvv_pkg::*; #(
 
           // Copy data
           axi_w_o.data[8*axi_byte +: 8] = stu_operand[vrf_lane][8*vrf_offset +: 8];
-          axi_w_o.strb[axi_byte]        = (vinsn_issue_q.vm || mask_i[vrf_lane][vrf_offset]) && st_strb_en[vrf_seq_byte];
           // axi_w_o.strb[axi_byte]        = (vinsn_issue_q.vm || mask_i[vrf_lane][vrf_offset]);
         end
+
+        if (vrf_seq_byte < (issue_cnt_q - axi_addrgen_req_i.vl_ldst)) begin
+          automatic int vrf_lane   = vrf_byte >> 3;
+          automatic int vrf_offset = vrf_byte[2:0];
+          // Some data might not be written due to the actual vl non-multiple of NrLanes*NrClusters
+          axi_w_o.strb[axi_byte]        = (vinsn_issue_q.vm || mask_i[vrf_lane][vrf_offset]);
+        end
       end
 
       // Send the W beat
       axi_w_valid_o = 1'b1;
-      // Account for the beat we sent
-      len_d         = len_q + 1;
-      // We wrote all the beats for this AW burst
-      if ($unsigned(len_d) == axi_pkg::len_t'($unsigned(axi_addrgen_req_i.len) + 1)) begin
-        axi_w_o.last            = 1'b1;
-        // Ask for another burst by the address generator
-        axi_addrgen_req_ready_o = 1'b1;
-        // Reset AXI pointers
-        len_d                   = '0;
-      end
 
       // We consumed a whole word from the lanes
       if (vrf_pnt_d == NrLanes*8 || vrf_pnt_d == issue_cnt_q) begin

From 1d9fe95d64311be082d975b57e4d3b568e41cd56 Mon Sep 17 00:00:00 2001
From: Hong Pang <hopang@larain5.ee.ethz.ch>
Date: Thu, 30 Oct 2025 14:22:07 +0100
Subject: [PATCH 05/37] [HW] Fix bugs on multi-driven signals

---
 hardware/src/ara_cluster.sv | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/hardware/src/ara_cluster.sv b/hardware/src/ara_cluster.sv
index 8684d9f..6205892 100644
--- a/hardware/src/ara_cluster.sv
+++ b/hardware/src/ara_cluster.sv
@@ -399,12 +399,12 @@ module ara_cluster import ara_pkg::*; import rvv_pkg::*;  #(
         .mst_req_o   (ldst_axi_req[cluster]),
         .mst_resp_i  (ldst_axi_resp[cluster])
       );
-
-    `FF(vew_ar_cut_glsu, vew_ar_cut, vew_e'(1'b0), clk_i, rst_ni);
-    `FF(vew_aw_cut_glsu, vew_aw_cut, vew_e'(1'b0), clk_i, rst_ni);
-    `FF(vl_ldst_cut_glsu, vl_ldst_cut, '0, clk_i, rst_ni);
   end
 
+  `FF(vew_ar_cut_glsu, vew_ar_cut, vew_e'(1'b0), clk_i, rst_ni);
+  `FF(vew_aw_cut_glsu, vew_aw_cut, vew_e'(1'b0), clk_i, rst_ni);
+  `FF(vl_ldst_cut_glsu, vl_ldst_cut, '0, clk_i, rst_ni);
+
   // Global Ld/St Unit
   global_ldst #(
     .NrLanes            (NrLanes            ),

From 26513fe8ec57b859d3ef9e411a719a30686333c2 Mon Sep 17 00:00:00 2001
From: Hong Pang <hopang@larain5.ee.ethz.ch>
Date: Mon, 3 Nov 2025 19:12:37 +0100
Subject: [PATCH 06/37] [CI] Add CI and riscv-test

---
 .github/pull_request_template.md              |   23 +
 .github/workflows/ci.yml                      |  751 ++
 .github/workflows/sphinx.yml                  |   22 +
 apps/riscv-tests/LICENSE                      |   24 +
 apps/riscv-tests/Makefile.in                  |   45 +
 apps/riscv-tests/README.md                    |  177 +
 apps/riscv-tests/benchmarks/Makefile          |   98 +
 apps/riscv-tests/benchmarks/common/crt.S      |  225 +
 apps/riscv-tests/benchmarks/common/syscalls.c |  469 ++
 apps/riscv-tests/benchmarks/common/test.ld    |   66 +
 apps/riscv-tests/benchmarks/common/util.h     |   90 +
 .../benchmarks/dhrystone/dhrystone.c          |  185 +
 .../benchmarks/dhrystone/dhrystone.h          |  477 ++
 .../benchmarks/dhrystone/dhrystone_main.c     |  332 +
 apps/riscv-tests/benchmarks/median/dataset1.h |   53 +
 apps/riscv-tests/benchmarks/median/median.c   |   42 +
 apps/riscv-tests/benchmarks/median/median.h   |   11 +
 .../benchmarks/median/median_gendata.pl       |  140 +
 .../benchmarks/median/median_main.c           |   40 +
 apps/riscv-tests/benchmarks/mm/common.h       |   36 +
 apps/riscv-tests/benchmarks/mm/gen.scala      |   81 +
 apps/riscv-tests/benchmarks/mm/mm.c           |  152 +
 apps/riscv-tests/benchmarks/mm/mm_main.c      |   72 +
 apps/riscv-tests/benchmarks/mm/rb.h           |  210 +
 .../benchmarks/mt-matmul/dataset.h            |   63 +
 .../riscv-tests/benchmarks/mt-matmul/matmul.c |   23 +
 .../benchmarks/mt-matmul/matmul_gendata.pl    |  205 +
 .../benchmarks/mt-matmul/mt-matmul.c          |   57 +
 .../riscv-tests/benchmarks/mt-vvadd/dataset.h |  173 +
 .../benchmarks/mt-vvadd/mt-vvadd.c            |   78 +
 apps/riscv-tests/benchmarks/mt-vvadd/vvadd.c  |   18 +
 .../benchmarks/mt-vvadd/vvadd_gendata.pl      |  139 +
 .../benchmarks/multiply/dataset1.h            |   32 +
 .../benchmarks/multiply/multiply.c            |   24 +
 .../benchmarks/multiply/multiply.h            |   11 +
 .../benchmarks/multiply/multiply_gendata.pl   |  142 +
 .../benchmarks/multiply/multiply_main.c       |   45 +
 apps/riscv-tests/benchmarks/pmp/pmp.c         |  212 +
 apps/riscv-tests/benchmarks/qsort/dataset1.h  |  219 +
 .../benchmarks/qsort/qsort_gendata.pl         |  132 +
 .../riscv-tests/benchmarks/qsort/qsort_main.c |  153 +
 apps/riscv-tests/benchmarks/readme.txt        |   48 +
 apps/riscv-tests/benchmarks/rsort/dataset1.h  |  219 +
 apps/riscv-tests/benchmarks/rsort/rsort.c     |  122 +
 apps/riscv-tests/benchmarks/spmv/dataset1.h   | 6312 +++++++++++++++++
 .../benchmarks/spmv/spmv_gendata.scala        |   48 +
 apps/riscv-tests/benchmarks/spmv/spmv_main.c  |   52 +
 .../benchmarks/towers/towers_main.c           |  234 +
 .../benchmarks/vvadd/dataset1-large.h         |  167 +
 apps/riscv-tests/benchmarks/vvadd/dataset1.h  |   62 +
 .../benchmarks/vvadd/vvadd_gendata.pl         |  139 +
 .../riscv-tests/benchmarks/vvadd/vvadd_main.c |   48 +
 apps/riscv-tests/configure                    | 3694 ++++++++++
 apps/riscv-tests/configure.ac                 |   16 +
 apps/riscv-tests/debug/Makefile               |   35 +
 apps/riscv-tests/debug/README.md              |   58 +
 apps/riscv-tests/debug/gdbserver.py           | 1607 +++++
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 apps/riscv-tests/debug/testlib.py             | 1194 ++++
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 .../isa/macros/scalar/test_macros.h           |  649 ++
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 apps/riscv-tests/isa/rv64ua/amomax_w.S        |   48 +
 apps/riscv-tests/isa/rv64ua/amomaxu_d.S       |   48 +
 apps/riscv-tests/isa/rv64ua/amomaxu_w.S       |   48 +
 apps/riscv-tests/isa/rv64ua/amomin_d.S        |   48 +
 apps/riscv-tests/isa/rv64ua/amomin_w.S        |   48 +
 apps/riscv-tests/isa/rv64ua/amominu_d.S       |   49 +
 apps/riscv-tests/isa/rv64ua/amominu_w.S       |   49 +
 apps/riscv-tests/isa/rv64ua/amoor_d.S         |   48 +
 apps/riscv-tests/isa/rv64ua/amoor_w.S         |   48 +
 apps/riscv-tests/isa/rv64ua/amoswap_d.S       |   48 +
 apps/riscv-tests/isa/rv64ua/amoswap_w.S       |   48 +
 apps/riscv-tests/isa/rv64ua/amoxor_d.S        |   48 +
 apps/riscv-tests/isa/rv64ua/amoxor_w.S        |   48 +
 apps/riscv-tests/isa/rv64ua/lrsc.S            |  102 +
 apps/riscv-tests/isa/rv64uc/Makefrag          |   11 +
 apps/riscv-tests/isa/rv64uc/rvc.S             |  154 +
 apps/riscv-tests/isa/rv64ud/Makefrag          |   12 +
 apps/riscv-tests/isa/rv64ud/fadd.S            |   50 +
 apps/riscv-tests/isa/rv64ud/fclass.S          |   46 +
 apps/riscv-tests/isa/rv64ud/fcmp.S            |   56 +
 apps/riscv-tests/isa/rv64ud/fcvt.S            |   79 +
 apps/riscv-tests/isa/rv64ud/fcvt_w.S          |  114 +
 apps/riscv-tests/isa/rv64ud/fdiv.S            |   54 +
 apps/riscv-tests/isa/rv64ud/fmadd.S           |   51 +
 apps/riscv-tests/isa/rv64ud/fmin.S            |   60 +
 apps/riscv-tests/isa/rv64ud/ldst.S            |   42 +
 apps/riscv-tests/isa/rv64ud/move.S            |  113 +
 apps/riscv-tests/isa/rv64ud/recoding.S        |   67 +
 apps/riscv-tests/isa/rv64ud/structural.S      |   58 +
 apps/riscv-tests/isa/rv64uf/Makefrag          |   12 +
 apps/riscv-tests/isa/rv64uf/fadd.S            |   44 +
 apps/riscv-tests/isa/rv64uf/fclass.S          |   40 +
 apps/riscv-tests/isa/rv64uf/fcmp.S            |   50 +
 apps/riscv-tests/isa/rv64uf/fcvt.S            |   43 +
 apps/riscv-tests/isa/rv64uf/fcvt_w.S          |  105 +
 apps/riscv-tests/isa/rv64uf/fdiv.S            |   40 +
 apps/riscv-tests/isa/rv64uf/fmadd.S           |   45 +
 apps/riscv-tests/isa/rv64uf/fmin.S            |   54 +
 apps/riscv-tests/isa/rv64uf/ldst.S            |   38 +
 apps/riscv-tests/isa/rv64uf/move.S            |   58 +
 apps/riscv-tests/isa/rv64uf/recoding.S        |   46 +
 apps/riscv-tests/isa/rv64ui/Makefrag          |   27 +
 apps/riscv-tests/isa/rv64ui/add.S             |   85 +
 apps/riscv-tests/isa/rv64ui/addi.S            |   71 +
 apps/riscv-tests/isa/rv64ui/addiw.S           |   71 +
 apps/riscv-tests/isa/rv64ui/addw.S            |   85 +
 apps/riscv-tests/isa/rv64ui/and.S             |   69 +
 apps/riscv-tests/isa/rv64ui/andi.S            |   55 +
 apps/riscv-tests/isa/rv64ui/auipc.S           |   39 +
 apps/riscv-tests/isa/rv64ui/beq.S             |   73 +
 apps/riscv-tests/isa/rv64ui/bge.S             |   76 +
 apps/riscv-tests/isa/rv64ui/bgeu.S            |   76 +
 apps/riscv-tests/isa/rv64ui/blt.S             |   73 +
 apps/riscv-tests/isa/rv64ui/bltu.S            |   73 +
 apps/riscv-tests/isa/rv64ui/bne.S             |   73 +
 apps/riscv-tests/isa/rv64ui/fence_i.S         |   62 +
 apps/riscv-tests/isa/rv64ui/jal.S             |   59 +
 apps/riscv-tests/isa/rv64ui/jalr.S            |   86 +
 apps/riscv-tests/isa/rv64ui/lb.S              |   92 +
 apps/riscv-tests/isa/rv64ui/lbu.S             |   92 +
 apps/riscv-tests/isa/rv64ui/ld.S              |   92 +
 apps/riscv-tests/isa/rv64ui/lh.S              |   92 +
 apps/riscv-tests/isa/rv64ui/lhu.S             |   92 +
 apps/riscv-tests/isa/rv64ui/lui.S             |   36 +
 apps/riscv-tests/isa/rv64ui/lw.S              |   92 +
 apps/riscv-tests/isa/rv64ui/lwu.S             |   92 +
 apps/riscv-tests/isa/rv64ui/or.S              |   69 +
 apps/riscv-tests/isa/rv64ui/ori.S             |   55 +
 apps/riscv-tests/isa/rv64ui/sb.S              |   96 +
 apps/riscv-tests/isa/rv64ui/sd.S              |   92 +
 apps/riscv-tests/isa/rv64ui/sh.S              |   96 +
 apps/riscv-tests/isa/rv64ui/simple.S          |   27 +
 apps/riscv-tests/isa/rv64ui/sll.S             |   96 +
 apps/riscv-tests/isa/rv64ui/slli.S            |   74 +
 apps/riscv-tests/isa/rv64ui/slliw.S           |   75 +
 apps/riscv-tests/isa/rv64ui/sllw.S            |   97 +
 apps/riscv-tests/isa/rv64ui/slt.S             |   84 +
 apps/riscv-tests/isa/rv64ui/slti.S            |   70 +
 apps/riscv-tests/isa/rv64ui/sltiu.S           |   70 +
 apps/riscv-tests/isa/rv64ui/sltu.S            |   84 +
 apps/riscv-tests/isa/rv64ui/sra.S             |   90 +
 apps/riscv-tests/isa/rv64ui/srai.S            |   68 +
 apps/riscv-tests/isa/rv64ui/sraiw.S           |   78 +
 apps/riscv-tests/isa/rv64ui/sraw.S            |   97 +
 apps/riscv-tests/isa/rv64ui/srl.S             |   93 +
 apps/riscv-tests/isa/rv64ui/srli.S            |   71 +
 apps/riscv-tests/isa/rv64ui/srliw.S           |   75 +
 apps/riscv-tests/isa/rv64ui/srlw.S            |   97 +
 apps/riscv-tests/isa/rv64ui/sub.S             |   83 +
 apps/riscv-tests/isa/rv64ui/subw.S            |   83 +
 apps/riscv-tests/isa/rv64ui/sw.S              |   92 +
 apps/riscv-tests/isa/rv64ui/xor.S             |   69 +
 apps/riscv-tests/isa/rv64ui/xori.S            |   55 +
 apps/riscv-tests/isa/rv64um/Makefrag          |   13 +
 apps/riscv-tests/isa/rv64um/div.S             |   41 +
 apps/riscv-tests/isa/rv64um/divu.S            |   41 +
 apps/riscv-tests/isa/rv64um/divuw.S           |   41 +
 apps/riscv-tests/isa/rv64um/divw.S            |   41 +
 apps/riscv-tests/isa/rv64um/mul.S             |   78 +
 apps/riscv-tests/isa/rv64um/mulh.S            |   72 +
 apps/riscv-tests/isa/rv64um/mulhsu.S          |   72 +
 apps/riscv-tests/isa/rv64um/mulhu.S           |   75 +
 apps/riscv-tests/isa/rv64um/mulw.S            |   72 +
 apps/riscv-tests/isa/rv64um/rem.S             |   41 +
 apps/riscv-tests/isa/rv64um/remu.S            |   41 +
 apps/riscv-tests/isa/rv64um/remuw.S           |   41 +
 apps/riscv-tests/isa/rv64um/remw.S            |   42 +
 apps/riscv-tests/isa/rv64uv/Makefrag          |  188 +
 apps/riscv-tests/isa/rv64uv/vaadd.c           |   59 +
 apps/riscv-tests/isa/rv64uv/vaaddu.c          |   59 +
 apps/riscv-tests/isa/rv64uv/vadc.c            |  103 +
 apps/riscv-tests/isa/rv64uv/vadd.c            |  202 +
 apps/riscv-tests/isa/rv64uv/vand.c            |  309 +
 apps/riscv-tests/isa/rv64uv/vasub.c           |   54 +
 apps/riscv-tests/isa/rv64uv/vasubu.c          |   54 +
 apps/riscv-tests/isa/rv64uv/vcompress.c       |  183 +
 apps/riscv-tests/isa/rv64uv/vcpop.c           |  111 +
 apps/riscv-tests/isa/rv64uv/vdiv.c            |  232 +
 apps/riscv-tests/isa/rv64uv/vdivu.c           |  232 +
 apps/riscv-tests/isa/rv64uv/vfadd.c           |  463 ++
 apps/riscv-tests/isa/rv64uv/vfclass.c         |   90 +
 apps/riscv-tests/isa/rv64uv/vfcvt.c           |  834 +++
 apps/riscv-tests/isa/rv64uv/vfdiv.c           |  355 +
 apps/riscv-tests/isa/rv64uv/vfirst.c          |   43 +
 apps/riscv-tests/isa/rv64uv/vfmacc.c          |  356 +
 apps/riscv-tests/isa/rv64uv/vfmadd.c          |  433 ++
 apps/riscv-tests/isa/rv64uv/vfmax.c           |  351 +
 apps/riscv-tests/isa/rv64uv/vfmerge.c         |   94 +
 apps/riscv-tests/isa/rv64uv/vfmin.c           |  348 +
 apps/riscv-tests/isa/rv64uv/vfmsac.c          |  454 ++
 apps/riscv-tests/isa/rv64uv/vfmsub.c          |  453 ++
 apps/riscv-tests/isa/rv64uv/vfmul.c           |  350 +
 apps/riscv-tests/isa/rv64uv/vfmv.c            |   68 +
 apps/riscv-tests/isa/rv64uv/vfmvfs.c          |   90 +
 apps/riscv-tests/isa/rv64uv/vfmvsf.c          |   69 +
 apps/riscv-tests/isa/rv64uv/vfncvt.c          |  773 ++
 apps/riscv-tests/isa/rv64uv/vfnmacc.c         |  456 ++
 apps/riscv-tests/isa/rv64uv/vfnmadd.c         |  458 ++
 apps/riscv-tests/isa/rv64uv/vfnmsac.c         |  455 ++
 apps/riscv-tests/isa/rv64uv/vfnmsub.c         |  454 ++
 apps/riscv-tests/isa/rv64uv/vfrdiv.c          |  179 +
 apps/riscv-tests/isa/rv64uv/vfrec7.c          |  121 +
 apps/riscv-tests/isa/rv64uv/vfredmax.c        |  348 +
 apps/riscv-tests/isa/rv64uv/vfredmin.c        |  348 +
 apps/riscv-tests/isa/rv64uv/vfredosum.c       |  348 +
 apps/riscv-tests/isa/rv64uv/vfredusum.c       |  348 +
 apps/riscv-tests/isa/rv64uv/vfrsqrt7.c        |   71 +
 apps/riscv-tests/isa/rv64uv/vfrsub.c          |  167 +
 apps/riscv-tests/isa/rv64uv/vfsgnj.c          |  408 ++
 apps/riscv-tests/isa/rv64uv/vfsgnjn.c         |  350 +
 apps/riscv-tests/isa/rv64uv/vfsgnjx.c         |  348 +
 apps/riscv-tests/isa/rv64uv/vfslide1down.c    |  107 +
 apps/riscv-tests/isa/rv64uv/vfslide1up.c      |   90 +
 apps/riscv-tests/isa/rv64uv/vfsqrt.c          |  142 +
 apps/riscv-tests/isa/rv64uv/vfsub.c           |  349 +
 apps/riscv-tests/isa/rv64uv/vfwadd.c          |  523 ++
 apps/riscv-tests/isa/rv64uv/vfwcvt.c          |  656 ++
 apps/riscv-tests/isa/rv64uv/vfwmacc.c         |  351 +
 apps/riscv-tests/isa/rv64uv/vfwmsac.c         |  353 +
 apps/riscv-tests/isa/rv64uv/vfwmul.c          |  254 +
 apps/riscv-tests/isa/rv64uv/vfwnmacc.c        |  352 +
 apps/riscv-tests/isa/rv64uv/vfwnmsac.c        |  347 +
 apps/riscv-tests/isa/rv64uv/vfwredosum.c      |  268 +
 apps/riscv-tests/isa/rv64uv/vfwredusum.c      |  272 +
 apps/riscv-tests/isa/rv64uv/vfwsub.c          |  519 ++
 apps/riscv-tests/isa/rv64uv/vid.c             |   42 +
 apps/riscv-tests/isa/rv64uv/viota.c           |  280 +
 apps/riscv-tests/isa/rv64uv/vl.c              |   79 +
 apps/riscv-tests/isa/rv64uv/vl1r.c            |  439 ++
 apps/riscv-tests/isa/rv64uv/vl_nocheck.c      |   68 +
 apps/riscv-tests/isa/rv64uv/vle1.c            |   45 +
 apps/riscv-tests/isa/rv64uv/vle16.c           |  294 +
 apps/riscv-tests/isa/rv64uv/vle32.c           |  311 +
 apps/riscv-tests/isa/rv64uv/vle64.c           |  315 +
 apps/riscv-tests/isa/rv64uv/vle8.c            |  274 +
 apps/riscv-tests/isa/rv64uv/vle_vse_hazards.c |  222 +
 apps/riscv-tests/isa/rv64uv/vlff.c            |   91 +
 apps/riscv-tests/isa/rv64uv/vls.c             |  190 +
 apps/riscv-tests/isa/rv64uv/vlseg.c           |  391 +
 apps/riscv-tests/isa/rv64uv/vlsseg.c          | 1678 +++++
 apps/riscv-tests/isa/rv64uv/vluxei.c          |  206 +
 apps/riscv-tests/isa/rv64uv/vluxseg.c         |  145 +
 apps/riscv-tests/isa/rv64uv/vlx.c             |  101 +
 apps/riscv-tests/isa/rv64uv/vmacc.c           |  292 +
 apps/riscv-tests/isa/rv64uv/vmadc.c           |  238 +
 apps/riscv-tests/isa/rv64uv/vmadd.c           |  292 +
 apps/riscv-tests/isa/rv64uv/vmand.c           |   79 +
 apps/riscv-tests/isa/rv64uv/vmandnot.c        |   68 +
 apps/riscv-tests/isa/rv64uv/vmax.c            |  181 +
 apps/riscv-tests/isa/rv64uv/vmaxu.c           |  181 +
 apps/riscv-tests/isa/rv64uv/vmerge.c          |  113 +
 apps/riscv-tests/isa/rv64uv/vmfeq.c           |  503 ++
 apps/riscv-tests/isa/rv64uv/vmfge.c           |  134 +
 apps/riscv-tests/isa/rv64uv/vmfgt.c           |  134 +
 apps/riscv-tests/isa/rv64uv/vmfle.c           |  273 +
 apps/riscv-tests/isa/rv64uv/vmflt.c           |  279 +
 apps/riscv-tests/isa/rv64uv/vmfne.c           |  503 ++
 apps/riscv-tests/isa/rv64uv/vmin.c            |  181 +
 apps/riscv-tests/isa/rv64uv/vminu.c           |  176 +
 apps/riscv-tests/isa/rv64uv/vmnand.c          |   68 +
 apps/riscv-tests/isa/rv64uv/vmnor.c           |   68 +
 apps/riscv-tests/isa/rv64uv/vmor.c            |   68 +
 apps/riscv-tests/isa/rv64uv/vmornot.c         |   68 +
 apps/riscv-tests/isa/rv64uv/vmsbc.c           |  168 +
 apps/riscv-tests/isa/rv64uv/vmsbf.c           |  160 +
 apps/riscv-tests/isa/rv64uv/vmseq.c           |  365 +
 apps/riscv-tests/isa/rv64uv/vmsgt.c           |  168 +
 apps/riscv-tests/isa/rv64uv/vmsgtu.c          |  168 +
 apps/riscv-tests/isa/rv64uv/vmsif.c           |   75 +
 apps/riscv-tests/isa/rv64uv/vmsle.c           |  237 +
 apps/riscv-tests/isa/rv64uv/vmsleu.c          |  237 +
 apps/riscv-tests/isa/rv64uv/vmslt.c           |  163 +
 apps/riscv-tests/isa/rv64uv/vmsltu.c          |  163 +
 apps/riscv-tests/isa/rv64uv/vmsne.c           |  306 +
 apps/riscv-tests/isa/rv64uv/vmsof.c           |   43 +
 apps/riscv-tests/isa/rv64uv/vmul.c            |  232 +
 apps/riscv-tests/isa/rv64uv/vmulh.c           |  232 +
 apps/riscv-tests/isa/rv64uv/vmulhsu.c         |  232 +
 apps/riscv-tests/isa/rv64uv/vmulhu.c          |  232 +
 apps/riscv-tests/isa/rv64uv/vmv.c             |  104 +
 apps/riscv-tests/isa/rv64uv/vmvnrr.c          |  146 +
 apps/riscv-tests/isa/rv64uv/vmvsx.c           |   75 +
 apps/riscv-tests/isa/rv64uv/vmvxs.c           |   72 +
 apps/riscv-tests/isa/rv64uv/vmxnor.c          |   68 +
 apps/riscv-tests/isa/rv64uv/vmxor.c           |   68 +
 apps/riscv-tests/isa/rv64uv/vnclip.c          |   78 +
 apps/riscv-tests/isa/rv64uv/vnclipu.c         |   78 +
 apps/riscv-tests/isa/rv64uv/vnmsac.c          |  292 +
 apps/riscv-tests/isa/rv64uv/vnmsub.c          |  292 +
 apps/riscv-tests/isa/rv64uv/vnsra.c           |  242 +
 apps/riscv-tests/isa/rv64uv/vnsrl.c           |  242 +
 apps/riscv-tests/isa/rv64uv/vor.c             |  309 +
 apps/riscv-tests/isa/rv64uv/vpopc_m.c         |   29 +
 apps/riscv-tests/isa/rv64uv/vredand.c         |   93 +
 apps/riscv-tests/isa/rv64uv/vredmax.c         |   79 +
 apps/riscv-tests/isa/rv64uv/vredmaxu.c        |  106 +
 apps/riscv-tests/isa/rv64uv/vredmin.c         |   78 +
 apps/riscv-tests/isa/rv64uv/vredminu.c        |   78 +
 apps/riscv-tests/isa/rv64uv/vredor.c          |   93 +
 apps/riscv-tests/isa/rv64uv/vredsum.c         |  178 +
 apps/riscv-tests/isa/rv64uv/vredxor.c         |   44 +
 apps/riscv-tests/isa/rv64uv/vrem.c            |  232 +
 apps/riscv-tests/isa/rv64uv/vremu.c           |  232 +
 apps/riscv-tests/isa/rv64uv/vrgather.c        |  340 +
 apps/riscv-tests/isa/rv64uv/vrsub.c           |  136 +
 apps/riscv-tests/isa/rv64uv/vs.c              |   93 +
 apps/riscv-tests/isa/rv64uv/vs1r.c            |  162 +
 apps/riscv-tests/isa/rv64uv/vsadd.c           |   99 +
 apps/riscv-tests/isa/rv64uv/vsaddu.c          |  113 +
 apps/riscv-tests/isa/rv64uv/vsbc.c            |   76 +
 apps/riscv-tests/isa/rv64uv/vse1.c            |   57 +
 apps/riscv-tests/isa/rv64uv/vse16.c           |  360 +
 apps/riscv-tests/isa/rv64uv/vse32.c           |  412 ++
 apps/riscv-tests/isa/rv64uv/vse64.c           |  436 ++
 apps/riscv-tests/isa/rv64uv/vse8.c            |  333 +
 apps/riscv-tests/isa/rv64uv/vsetivli.c        |  466 ++
 apps/riscv-tests/isa/rv64uv/vsetvl.c          |  497 ++
 apps/riscv-tests/isa/rv64uv/vsetvli.c         |  498 ++
 apps/riscv-tests/isa/rv64uv/vsext.c           |  106 +
 apps/riscv-tests/isa/rv64uv/vslide1down.c     |  102 +
 apps/riscv-tests/isa/rv64uv/vslide1up.c       |   78 +
 apps/riscv-tests/isa/rv64uv/vslidedown.c      |  181 +
 apps/riscv-tests/isa/rv64uv/vslideup.c        |  166 +
 apps/riscv-tests/isa/rv64uv/vsll.c            |  316 +
 apps/riscv-tests/isa/rv64uv/vsmul.c           |   59 +
 apps/riscv-tests/isa/rv64uv/vsra.c            |  316 +
 apps/riscv-tests/isa/rv64uv/vsrl.c            |  316 +
 apps/riscv-tests/isa/rv64uv/vss.c             |  146 +
 apps/riscv-tests/isa/rv64uv/vsseg.c           |  407 ++
 apps/riscv-tests/isa/rv64uv/vssra.c           |   79 +
 apps/riscv-tests/isa/rv64uv/vssrl.c           |   79 +
 apps/riscv-tests/isa/rv64uv/vssseg.c          |  425 ++
 apps/riscv-tests/isa/rv64uv/vssub.c           |   68 +
 apps/riscv-tests/isa/rv64uv/vssubu.c          |   55 +
 apps/riscv-tests/isa/rv64uv/vsub.c            |  136 +
 apps/riscv-tests/isa/rv64uv/vsux.c            |  104 +
 apps/riscv-tests/isa/rv64uv/vsuxei.c          |  141 +
 apps/riscv-tests/isa/rv64uv/vsuxseg.c         |  196 +
 apps/riscv-tests/isa/rv64uv/vsx.c             |  102 +
 apps/riscv-tests/isa/rv64uv/vwadd.c           |  228 +
 apps/riscv-tests/isa/rv64uv/vwaddu.c          |  231 +
 apps/riscv-tests/isa/rv64uv/vwmacc.c          |  248 +
 apps/riscv-tests/isa/rv64uv/vwmaccsu.c        |  248 +
 apps/riscv-tests/isa/rv64uv/vwmaccu.c         |  248 +
 apps/riscv-tests/isa/rv64uv/vwmaccus.c        |  127 +
 apps/riscv-tests/isa/rv64uv/vwmul.c           |  182 +
 apps/riscv-tests/isa/rv64uv/vwmulsu.c         |  182 +
 apps/riscv-tests/isa/rv64uv/vwmulu.c          |  182 +
 apps/riscv-tests/isa/rv64uv/vwredsum.c        |  153 +
 apps/riscv-tests/isa/rv64uv/vwredsumu.c       |  153 +
 apps/riscv-tests/isa/rv64uv/vwsub.c           |  234 +
 apps/riscv-tests/isa/rv64uv/vwsubu.c          |  234 +
 apps/riscv-tests/isa/rv64uv/vxor.c            |  309 +
 apps/riscv-tests/isa/rv64uv/vzext.c           |  115 +
 apps/riscv-tests/mt/.gitignore                |    6 +
 apps/riscv-tests/mt/Makefile                  |  162 +
 apps/riscv-tests/mt/ad_matmul.c               |   37 +
 apps/riscv-tests/mt/ae_matmul.c               |  110 +
 apps/riscv-tests/mt/af_matmul.c               |   79 +
 apps/riscv-tests/mt/ag_matmul.c               |   79 +
 apps/riscv-tests/mt/ai_matmul.c               |   72 +
 apps/riscv-tests/mt/ak_matmul.c               |   62 +
 apps/riscv-tests/mt/al_matmul.c               |  123 +
 apps/riscv-tests/mt/am_matmul.c               |   64 +
 apps/riscv-tests/mt/an_matmul.c               |   40 +
 apps/riscv-tests/mt/ap_matmul.c               |   29 +
 apps/riscv-tests/mt/aq_matmul.c               |   30 +
 apps/riscv-tests/mt/ar_matmul.c               |   41 +
 apps/riscv-tests/mt/at_matmul.c               |  164 +
 apps/riscv-tests/mt/av_matmul.c               |  259 +
 apps/riscv-tests/mt/ay_matmul.c               |   60 +
 apps/riscv-tests/mt/az_matmul.c               |  181 +
 apps/riscv-tests/mt/bb_matmul.c               |   35 +
 apps/riscv-tests/mt/bc_matmul.c               |  137 +
 apps/riscv-tests/mt/bf_matmul.c               |  127 +
 apps/riscv-tests/mt/bh_matmul.c               |   97 +
 apps/riscv-tests/mt/bj_matmul.c               |   97 +
 apps/riscv-tests/mt/bk_matmul.c               |   92 +
 apps/riscv-tests/mt/bm_matmul.c               |  205 +
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diff --git a/.github/pull_request_template.md b/.github/pull_request_template.md
new file mode 100644
index 0000000..9a8774c
--- /dev/null
+++ b/.github/pull_request_template.md
@@ -0,0 +1,23 @@
+Description of PR that completes issue here...
+
+## Changelog
+
+### Fixed
+
+- Description of changes
+
+### Added
+
+- Description of changes
+
+### Changed
+
+- Description of changes
+
+## Checklist
+
+- [ ] Automated tests pass
+- [ ] Changelog updated
+- [ ] Code style guideline is observed
+
+Please check our [contributing guidelines](CONTRIBUTING.md) before opening a Pull Request.
diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
new file mode 100644
index 0000000..9a64d12
--- /dev/null
+++ b/.github/workflows/ci.yml
@@ -0,0 +1,751 @@
+# Copyright 2021 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+#
+# Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+
+# Run functional regression checks
+name: ci
+on: [push, pull_request]
+variables:
+  TOOL_DIR=/usr/scratch2/tokyo/mperotti/tools/arathon/install
+
+# Only allow one workflow per PR/Branch (the last one)
+# https://docs.github.com/en/actions/learn-github-actions/expressions
+# https://docs.github.com/en/actions/learn-github-actions/contexts#github-context
+# https://docs.github.com/en/actions/using-jobs/using-concurrency
+concurrency:
+  # github.workflow: name of the workflow
+  # github.event.pull_request.number || github.ref: pull request number or branch name if not a pull request
+  group: ${{ github.workflow }}-${{ github.event.pull_request.number || github.ref }}
+  # Cancel in-progress runs when a new workflow with the same group name is triggered
+  cancel-in-progress: true
+
+jobs:
+
+#####################
+#  Toolchain stage  #
+#####################
+
+  tc-llvm:
+    runs-on: ubuntu-22.04
+    steps:
+    # LLVM and GCC installations require plenty of disk space
+    - name: Free Disk Space (Ubuntu)
+      uses: jlumbroso/free-disk-space@main
+      with:
+        # this might remove tools that are actually needed,
+        # if set to "true" but frees about 6 GB
+        tool-cache: false
+
+        # all of these default to true, but feel free to set to
+        # "false" if necessary for your workflow
+        android: true
+        dotnet: true
+        haskell: true
+        large-packages: true
+        docker-images: true
+        swap-storage: true
+    # - uses: actions/checkout@v4
+    # - name: Recover the submodule commit hash
+    #   id: recover_hash
+    #   run: |
+    #     git submodule status toolchain/riscv-llvm | cut -d' ' -f1
+    #     echo "tc-llvm-hash=`git submodule status toolchain/riscv-llvm | cut -d' ' -f1`" >> $GITHUB_ENV
+    - name: Cache the LLVM toolchain
+      uses: actions/cache@v4
+      id: tc-llvm-cache
+      env:
+        cache-name: cache-llvm
+      with:
+        path: install/riscv-llvm
+        key: ${{ runner.os }}-build-${{ env.cache-name }}-${{ env.tc-llvm-hash }}
+        restore-keys:
+          ${{ runner.os }}-build-${{ env.cache-name }}-${{ env.tc-llvm-hash }}
+    # - name: Download the LLVM toolchain
+    #   if: steps.tc-llvm-cache.outputs.cache-hit != 'true'
+    #   run: git submodule update --init --recursive --checkout -- toolchain/riscv-llvm
+    # - name: Download Newlib
+    #   if: steps.tc-llvm-cache.outputs.cache-hit != 'true'
+    #   run: git submodule update --init --recursive --checkout -- toolchain/newlib
+    # - name: Compile LLVM
+    #   if: steps.tc-llvm-cache.outputs.cache-hit != 'true'
+    #   run: |
+    #     sudo apt-get install libmpc-dev
+    #     sudo apt-get install -y ninja-build
+    #     CC=gcc CXX=g++ make toolchain-llvm
+    - name: Copy LLVM tools
+      run: cp -Lr ${TOOL_DIR}/riscv-llvm install
+    - name: Tar LLVM
+      run: tar -cvf tc-llvm.tar install/riscv-llvm
+    - name: Upload LLVM
+      uses: actions/upload-artifact@v4
+      with:
+        name: tc-llvm
+        path: tc-llvm.tar
+
+  tc-gcc:
+    runs-on: ubuntu-22.04
+    steps:
+    # LLVM and GCC installations require plenty of disk space
+    - name: Free Disk Space (Ubuntu)
+      uses: jlumbroso/free-disk-space@main
+      with:
+        # this might remove tools that are actually needed,
+        # if set to "true" but frees about 6 GB
+        tool-cache: false
+
+        # all of these default to true, but feel free to set to
+        # "false" if necessary for your workflow
+        android: true
+        dotnet: true
+        haskell: true
+        large-packages: true
+        docker-images: true
+        swap-storage: true
+    # - uses: actions/checkout@v4
+    # - name: Recover the submodule commit hash
+    #   id: recover_hash
+    #   run: |
+    #     git submodule status toolchain/riscv-gnu-toolchain | cut -d' ' -f1
+    #     echo "tc-gcc-hash=`git submodule status toolchain/riscv-gnu-toolchain | cut -d' ' -f1`" >> $GITHUB_ENV
+    - name: Cache the GCC toolchain
+      uses: actions/cache@v4
+      id: tc-gcc-cache
+      env:
+        cache-name: cache-gcc
+      with:
+        path: install/riscv-gcc
+        key: ${{ runner.os }}-build-${{ env.cache-name }}-${{ env.tc-gcc-hash }}
+        restore-keys:
+          ${{ runner.os }}-build-${{ env.cache-name }}-${{ env.tc-gcc-hash }}
+    # - name: Download the GCC toolchain
+    #   if: steps.tc-gcc-cache.outputs.cache-hit != 'true'
+    #   run: git submodule update --init --recursive --checkout -- toolchain/riscv-gnu-toolchain
+    # - name: Compile GCC
+    #   if: steps.tc-gcc-cache.outputs.cache-hit != 'true'
+    #   run: |
+    #     sudo apt-get install libmpc-dev
+    #     CC=gcc CXX=g++ make toolchain-gcc
+    - name: Copy GCC tools
+      run: cp -Lr ${TOOL_DIR}/riscv-gcc install
+    - name: Tar GCC
+      run: tar -cvf tc-gcc.tar install/riscv-gcc
+    - name: Upload GCC
+      uses: actions/upload-artifact@v4
+      with:
+        name: tc-gcc
+        path: tc-gcc.tar
+
+  tc-isa-sim:
+    runs-on: ubuntu-22.04
+    steps:
+    # - uses: actions/checkout@v4
+    # - name: Recover the submodule commit hash
+    #   id: recover_hash
+    #   run: |
+    #     git submodule status toolchain/riscv-isa-sim | cut -d' ' -f1
+    #     echo "tc-isa-sim-hash=`git submodule status toolchain/riscv-isa-sim | cut -d' ' -f1`" >> $GITHUB_ENV
+    - name: Cache Spike
+      uses: actions/cache@v4
+      id: tc-isa-sim-cache
+      env:
+        cache-name: cache-spike
+      with:
+        path: install/riscv-isa-sim
+        key: ${{ runner.os }}-build-${{ env.cache-name }}-${{ env.tc-isa-sim-hash }}
+        restore-keys:
+          ${{ runner.os }}-build-${{ env.cache-name }}-${{ env.tc-isa-sim-hash }}
+    # - name: Download Spike
+    #   if: steps.tc-isa-sim-cache.outputs.cache-hit != 'true'
+    #   run: |
+    #     git submodule update --init --recursive -- toolchain/riscv-isa-sim
+    #     git submodule foreach --recursive git reset --hard
+    # - name: Compile Spike
+    #   if: steps.tc-isa-sim-cache.outputs.cache-hit != 'true'
+    #   run: make riscv-isa-sim
+    - name: Copy Spike
+      run: cp -Lr ${TOOL_DIR}/riscv-isa-sim install
+    - name: Tar Spike
+      run: tar -cvf tc-isa-sim.tar install/riscv-isa-sim
+    - name: Upload Spike
+      uses: actions/upload-artifact@v4
+      with:
+        name: tc-isa-sim
+        path: tc-isa-sim.tar
+
+  tc-verilator:
+    runs-on: ubuntu-22.04
+    steps:
+    # - uses: actions/checkout@v4
+    # - name: Recover the submodule commit hash
+    #   id: recover_hash
+    #   run: |
+    #     git submodule status toolchain/verilator | cut -d' ' -f1
+    #     echo "tc-verilator-hash=`git submodule status toolchain/verilator | cut -d' ' -f1`" >> $GITHUB_ENV
+    - name: Cache Verilator
+      uses: actions/cache@v4
+      id: tc-verilator-cache
+      env:
+        cache-name: cache-verilator
+      with:
+        path: install/verilator
+        key: ${{ runner.os }}-build-llvm10-${{ env.cache-name }}-${{ env.tc-verilator-hash }}
+        restore-keys:
+          ${{ runner.os }}-build-llvm10-${{ env.cache-name }}-${{ env.tc-verilator-hash }}
+    # - name: Download Verilator
+    #   if: steps.tc-verilator-cache.outputs.cache-hit != 'true'
+    #   run: |
+    #     git submodule update --init --recursive -- toolchain/verilator
+    # - name: Compile Verilator
+    #   if: steps.tc-verilator-cache.outputs.cache-hit != 'true'
+    #   run: |
+    #     sudo apt-get install flex libfl-dev help2man
+    #     make verilator
+    - name: Copy Verilator
+      run: cp -Lr ${TOOL_DIR}/verilator install
+    - name: Tar Verilator
+      run: tar -cvf tc-verilator.tar install/verilator
+    - name: Upload Verilator
+      uses: actions/upload-artifact@v4
+      with:
+        name: tc-verilator
+        path: tc-verilator.tar
+
+###################
+#  Compile stage  #
+###################
+
+  compile-apps:
+    runs-on: ubuntu-22.04
+    strategy:
+      max-parallel: 1
+      matrix:
+        ara_config: [2_lanes, 4_lanes, 8_lanes, 16_lanes]
+    needs: tc-llvm
+    steps:
+    - uses: actions/checkout@v4
+    - uses: actions/setup-python@v4
+      with:
+        python-version: 3.12.0
+    - name: Install Python requirements
+      run: pip install -r python-requirements.txt
+    - name: Download Spike
+      run: |
+        git submodule update --init --recursive -- toolchain/riscv-isa-sim
+        git submodule foreach --recursive git reset --hard
+    - name: Download the LLVM toolchain
+      uses: actions/download-artifact@v4
+      with:
+        name: tc-llvm
+    - name: Untar LLVM
+      run: tar xvf tc-llvm.tar
+    - name: Compile applications
+      run: config=${{ matrix.ara_config }} make -C apps
+    - name: Upload applications
+      uses: actions/upload-artifact@v4
+      with:
+        name: compile-apps-${{ matrix.ara_config }}
+        path: apps/bin
+
+  compile-riscv-tests:
+    runs-on: ubuntu-22.04
+    strategy:
+      max-parallel: 1
+      matrix:
+        ara_config: [2_lanes, 4_lanes, 8_lanes, 16_lanes]
+    needs: ["tc-llvm", "tc-gcc", "tc-isa-sim"]
+    steps:
+    - uses: actions/checkout@v4
+    - name: Download Spike
+      run: |
+        git submodule update --init --recursive -- toolchain/riscv-isa-sim
+        git submodule foreach --recursive git reset --hard
+    - name: Get Spike artifacts
+      uses: actions/download-artifact@v4
+      with:
+        name: tc-isa-sim
+    - name: Untar Spike
+      run: tar xvf tc-isa-sim.tar
+    - name: Get LLVM toolchain artifacts
+      uses: actions/download-artifact@v4
+      with:
+        name: tc-llvm
+    - name: Untar LLVM
+      run: tar xvf tc-llvm.tar
+    - name: Get GCC toolchain artifacts
+      uses: actions/download-artifact@v4
+      with:
+        name: tc-gcc
+    - name: Untar GCC
+      run: tar xvf tc-gcc.tar
+    - name: Compile applications
+      run: config=${{ matrix.ara_config }} make -C apps riscv_tests
+    - name: Upload applications
+      uses: actions/upload-artifact@v4
+      with:
+        name: compile-riscv-tests-${{ matrix.ara_config }}
+        path: apps/bin
+
+  compile-ara:
+    runs-on: ubuntu-22.04
+    strategy:
+      max-parallel: 1
+      matrix:
+        ara_config: [2_lanes, 4_lanes, 8_lanes, 16_lanes]
+    needs: ["tc-verilator", "tc-isa-sim"]
+    steps:
+    - uses: actions/checkout@v4
+    - name: Download Spike
+      run: |
+        git submodule update --init --recursive -- toolchain/riscv-isa-sim
+        git submodule foreach --recursive git reset --hard
+    - name: Get Spike artifacts
+      uses: actions/download-artifact@v4
+      with:
+        name: tc-isa-sim
+    - name: Untar Spike
+      run: tar xvf tc-isa-sim.tar
+    - name: Get Verilator artifacts
+      uses: actions/download-artifact@v4
+      with:
+        name: tc-verilator
+    - name: Untar Verilator
+      run: tar xvf tc-verilator.tar
+    - name: Set the Verilator root directory
+      run: |
+        echo VERILATOR_ROOT="$GITHUB_WORKSPACE/install/verilator" >> $GITHUB_ENV
+        VERILATOR_ROOT="$GITHUB_WORKSPACE/install/verilator"
+        ln -s $VERILATOR_ROOT/share/verilator/include $VERILATOR_ROOT/include
+        ln -s $VERILATOR_ROOT/share/verilator/bin/verilator_includer $VERILATOR_ROOT/bin/verilator_includer
+    - name: Download RTL submodules
+      run: make -C hardware checkout
+    - name: Compile Verilated model of Ara
+      run: |
+        sudo apt-get install libelf-dev
+        make -C hardware apply-patches
+        config=${{ matrix.ara_config }} make -C hardware verilate
+    - name: Tar Verilated model of Ara
+      run: tar -cvf ara.tar hardware/build/verilator hardware/bender
+    - name: Upload Ara Verilated model
+      uses: actions/upload-artifact@v4
+      with:
+        name: compile-ara-${{ matrix.ara_config }}
+        path: ara.tar
+
+####################
+#  Simulate stage  #
+####################
+
+  simulate:
+    runs-on: ubuntu-22.04
+    strategy:
+      max-parallel: 1
+      matrix:
+        app:        [hello_world, imatmul, fmatmul, iconv2d, fconv2d, fconv3d, jacobi2d, dropout, fft, dwt, exp, softmax, dotproduct, fdotproduct, pathfinder, roi_align, lavamd]
+        ara_config: [2_lanes, 4_lanes, 8_lanes, 16_lanes]
+    needs: ["compile-ara", "compile-apps"]
+    steps:
+    - uses: actions/checkout@v4
+    - name: Get Spike artifacts
+      uses: actions/download-artifact@v4
+      with:
+        name: tc-isa-sim
+    - name: Untar Spike
+      run: tar xvf tc-isa-sim.tar
+    - name: Get Verilated model of Ara
+      uses: actions/download-artifact@v4
+      with:
+        name: compile-ara-${{ matrix.ara_config }}
+    - name: Untar Verilated model of Ara
+      run: tar xvf ara.tar
+    - name: Get applications
+      uses: actions/download-artifact@v4
+      with:
+        name: compile-apps-${{ matrix.ara_config }}
+        path: apps/bin
+    - name: Run test
+      run: config=${{ matrix.ara_config }} app=${{ matrix.app }} make -C hardware simv
+
+########################
+#  RISC-V Tests stage  #
+########################
+
+  # riscv-tests-simv:
+  #   runs-on: ubuntu-22.04
+  #   strategy:
+  #     max-parallel: 1
+  #     matrix:
+  #       ara_config: [2_lanes, 4_lanes, 8_lanes, 16_lanes]
+  #   needs: ["compile-ara", "compile-riscv-tests"]
+  #   steps:
+  #   - uses: actions/checkout@v4
+  #   - name: Get Spike artifacts
+  #     uses: actions/download-artifact@v4
+  #     with:
+  #       name: tc-isa-sim
+  #   - name: Untar Spike
+  #     run: tar xvf tc-isa-sim.tar
+  #   - name: Get Verilated model of Ara
+  #     uses: actions/download-artifact@v4
+  #     with:
+  #       name: compile-ara-${{ matrix.ara_config }}
+  #   - name: Untar Verilated model of Ara
+  #     run: tar xvf ara.tar
+  #   - name: Get RISC-V tests
+  #     uses: actions/download-artifact@v4
+  #     with:
+  #       name: compile-riscv-tests-${{ matrix.ara_config }}
+  #       path: apps/bin
+  #   - name: Run tests
+  #     run: config=${{ matrix.ara_config }} make -C hardware -j8 riscv_tests_simv
+
+  # riscv-tests-spike:
+  #   runs-on: ubuntu-22.04
+  #   needs: ["tc-isa-sim", "compile-riscv-tests"]
+  #   steps:
+  #   - uses: actions/checkout@v4
+  #   - name: Get Spike artifacts
+  #     uses: actions/download-artifact@v4
+  #     with:
+  #       name: tc-isa-sim
+  #   - name: Untar Spike
+  #     run: tar xvf tc-isa-sim.tar
+  #   - name: Download the LLVM toolchain
+  #     uses: actions/download-artifact@v4
+  #     with:
+  #       name: tc-llvm
+  #   - name: Untar LLVM
+  #     run: tar xvf tc-llvm.tar
+  #   - name: Download the GCC toolchain
+  #     uses: actions/download-artifact@v4
+  #     with:
+  #       name: tc-gcc
+  #   - name: Untar GCC
+  #     run: tar xvf tc-gcc.tar
+  #   - name: Run tests
+  #     run: |
+  #       make -C apps/riscv-tests/isa clean
+  #       make -C apps riscv_tests_spike
+  #   - name: Upload dumps
+  #     uses: actions/upload-artifact@v4
+  #     with:
+  #       name: riscv-tests-spike
+  #       path: |
+  #         apps/riscv-tests/isa/*.dump
+  #         apps/riscv-tests/isa/*.out32
+
+###################
+#  Linting stage  #
+###################
+
+  check-license:
+    runs-on: ubuntu-22.04
+    steps:
+    - uses: actions/checkout@v4
+    - uses: actions/setup-python@v4
+      with:
+        python-version: 3.12.0
+    - name: Install Python requirements
+      run: pip install -r python-requirements.txt
+    - name: Check license
+      run: python scripts/licence-checker.py --config scripts/licence-checker.hjson hardware
+
+  check-clang-format:
+    runs-on: ubuntu-22.04
+    needs: ['tc-llvm']
+    steps:
+    - uses: actions/checkout@v4
+    - uses: actions/setup-python@v4
+      with:
+        python-version: 3.12.0
+    - name: Install Python requirements
+      run: pip install -r python-requirements.txt
+    - name: Download the LLVM toolchain
+      uses: actions/download-artifact@v4
+      with:
+        name: tc-llvm
+    - name: Untar LLVM
+      run: tar xvf tc-llvm.tar
+    - name: Run clang-format
+      run: |
+        for file in `find apps -type f -name "*.[c|h|cpp|hpp]" ! -path "*rivec-bmarks*" | grep -vP "apps/riscv-tests"`; do
+          ./scripts/run-clang-format.py --clang-format-executable install/riscv-llvm/bin/clang-format $file || EXIT_STATUS=$?
+        done
+        for file in `find apps/riscv-tests/isa/rv64uv -type f -name "*.[c|h|cpp|hpp]"`; do
+          ./scripts/run-clang-format.py --clang-format-executable install/riscv-llvm/bin/clang-format $file || EXIT_STATUS=$?
+        done
+        exit $EXIT_STATUS
+
+  check-trailing-whitespaces:
+    runs-on: ubuntu-22.04
+    steps:
+    - uses: actions/checkout@v4
+      with:
+        fetch-depth: 0
+    - name: Determine base commit
+      run: |
+        if [[ -n $GITHUB_BASE_REF ]]; then
+          # Make sure we have the latest version of the target branch
+          git fetch origin $GITHUB_BASE_REF
+          echo "base=origin/$GITHUB_BASE_REF" >> $GITHUB_ENV
+        else
+          echo "base=HEAD~1" >> $GITHUB_ENV
+        fi
+    # Don't check the `patches` directory! Trailing whitespaces
+    # are mandatory there if they exist.
+    - name: Check for trailing whitespaces and tabs
+      run: |
+        bash -O extglob -c                       \
+        "git diff --check $base HEAD --          \
+        apps/!(rivec-bmarks) config .github *.md \
+        Bender.* Makefile hardware/!(patches)"
+
+#####################
+#  Benchmark stage  #
+#####################
+
+  # benchmark:
+  #   runs-on: ubuntu-22.04
+  #   strategy:
+  #     max-parallel: 1
+  #     matrix:
+  #       ara_config: [2_lanes, 4_lanes, 8_lanes, 16_lanes]
+  #   needs: ["compile-ara", "compile-apps"]
+  #   steps:
+  #   - uses: actions/checkout@v4
+  #   - uses: actions/setup-python@v4
+  #     with:
+  #       python-version: 3.12.0
+  #   - name: Install Python requirements
+  #     run: pip install -r python-requirements.txt
+  #   - name: Download the LLVM toolchain
+  #     uses: actions/download-artifact@v4
+  #     with:
+  #       name: tc-llvm
+  #   - name: Untar LLVM
+  #     run: tar xvf tc-llvm.tar
+  #   - name: Get Spike artifacts
+  #     uses: actions/download-artifact@v4
+  #     with:
+  #       name: tc-isa-sim
+  #   - name: Untar Spike
+  #     run: tar xvf tc-isa-sim.tar
+  #   - name: Get Verilated model of Ara
+  #     uses: actions/download-artifact@v4
+  #     with:
+  #       name: compile-ara-${{ matrix.ara_config }}
+  #   - name: Untar Verilated model of Ara
+  #     run: tar xvf ara.tar
+  #   - name: Benchmark Ara
+  #     run: config=${{ matrix.ara_config }} ./scripts/benchmark.sh ci
+  #   - name: Tar [f]dotproduct runtime results
+  #     run: |
+  #       tar -cvf dotproducts-${{ matrix.ara_config }}.tar *dotproduct*.benchmark
+  #       rm *dotproduct*.benchmark
+  #   - name: Tar runtime results
+  #     run: |
+  #       tar -cvf benchmarks-${{ matrix.ara_config }}.tar *.benchmark
+  #   - name: Upload [f]dotproduct runtime results
+  #     uses: actions/upload-artifact@v4
+  #     with:
+  #       name: dotproducts-${{ matrix.ara_config }}
+  #       path: dotproducts-${{ matrix.ara_config }}.tar
+  #   - name: Upload runtime results
+  #     uses: actions/upload-artifact@v4
+  #     with:
+  #       name: benchmark-${{ matrix.ara_config }}
+  #       path: benchmarks-${{ matrix.ara_config }}.tar
+
+  # roofline:
+  #   runs-on: ubuntu-22.04
+  #   needs: benchmark
+  #   steps:
+  #   - uses: actions/checkout@v4
+  #   - uses: actions/setup-python@v4
+  #     with:
+  #       python-version: 3.12.0
+  #   - name: Install Python requirements
+  #     run: pip install -r python-requirements.txt
+  #   - uses: actions/checkout@v4
+  #   - name: Get [f]dotproduct results (2 lanes)
+  #     uses: actions/download-artifact@v4
+  #     with:
+  #       name: dotproducts-2_lanes
+  #   - name: Get [f]dotproduct results (4 lanes)
+  #     uses: actions/download-artifact@v4
+  #     with:
+  #       name: dotproducts-4_lanes
+  #   - name: Get [f]dotproduct results (8 lanes)
+  #     uses: actions/download-artifact@v4
+  #     with:
+  #       name: dotproducts-8_lanes
+  #   - name: Get [f]dotproduct results (16 lanes)
+  #     uses: actions/download-artifact@v4
+  #     with:
+  #       name: dotproducts-16_lanes
+  #   - name: Get benchmark results (2 lanes)
+  #     uses: actions/download-artifact@v4
+  #     with:
+  #       name: benchmark-2_lanes
+  #   - name: Get benchmark results (4 lanes)
+  #     uses: actions/download-artifact@v4
+  #     with:
+  #       name: benchmark-4_lanes
+  #   - name: Get benchmark results (8 lanes)
+  #     uses: actions/download-artifact@v4
+  #     with:
+  #       name: benchmark-8_lanes
+  #   - name: Get benchmark results (16 lanes)
+  #     uses: actions/download-artifact@v4
+  #     with:
+  #       name: benchmark-16_lanes
+  #   - name: Untar the [f]dotproduct results
+  #     run: |
+  #       tar xvf dotproducts-2_lanes.tar
+  #       tar xvf dotproducts-4_lanes.tar
+  #       tar xvf dotproducts-8_lanes.tar
+  #       tar xvf dotproducts-16_lanes.tar
+  #   - name: Untar the results
+  #     run: |
+  #       tar xvf benchmarks-2_lanes.tar
+  #       tar xvf benchmarks-4_lanes.tar
+  #       tar xvf benchmarks-8_lanes.tar
+  #       tar xvf benchmarks-16_lanes.tar
+  #   - name: Install gnuplot
+  #     run: |
+  #       sudo apt-get update
+  #       sudo apt-get install gnuplot
+  #   - name: Plot [f]dotproduct plots
+  #     run: |
+  #       for kernel in fdotproduct dotproduct; do
+  #         > ${kernel}.benchmark
+  #         for nr_lanes in 2 4 8 16; do
+  #           cat ${kernel}_${nr_lanes}_bar_plots.benchmark >> ${kernel}.benchmark
+  #         done
+  #         python scripts/process_dotp.py ${kernel} ${kernel}.benchmark ${kernel}
+  #         tar -cvf ${kernel}.tar $(find . -name "${kernel}_*.png")
+  #       done
+  #   - name: Plot the rooflines
+  #     run: gnuplot -c scripts/benchmark.gnuplot
+  #   - name: Upload the imatmul roofline
+  #     uses: actions/upload-artifact@v4
+  #     with:
+  #       name: imatmul_roofline
+  #       path: imatmul.png
+  #   - name: Upload the fmatmul roofline
+  #     uses: actions/upload-artifact@v4
+  #     with:
+  #       name: fmatmul_roofline
+  #       path: fmatmul.png
+  #   - name: Upload the iconv2d roofline
+  #     uses: actions/upload-artifact@v4
+  #     with:
+  #       name: iconv2d_roofline
+  #       path: iconv2d.png
+  #   - name: Upload the fconv2d roofline
+  #     uses: actions/upload-artifact@v4
+  #     with:
+  #       name: fconv2d_roofline
+  #       path: fconv2d.png
+  #   - name: Upload the fconv3d roofline
+  #     uses: actions/upload-artifact@v4
+  #     with:
+  #       name: fconv3d_roofline
+  #       path: fconv3d.png
+  #   - name: Upload the jacobi2d roofline
+  #     uses: actions/upload-artifact@v4
+  #     with:
+  #       name: jacobi2d_roofline
+  #       path: jacobi2d.png
+  #   - name: Upload the dropout roofline
+  #     uses: actions/upload-artifact@v4
+  #     with:
+  #       name: dropout_roofline
+  #       path: dropout.png
+  #   - name: Upload the fft roofline
+  #     uses: actions/upload-artifact@v4
+  #     with:
+  #       name: fft_roofline
+  #       path: fft.png
+  #   - name: Upload the dwt roofline
+  #     uses: actions/upload-artifact@v4
+  #     with:
+  #       name: dwt_roofline
+  #       path: dwt.png
+  #   - name: Upload the exp roofline
+  #     uses: actions/upload-artifact@v4
+  #     with:
+  #       name: exp_roofline
+  #       path: exp.png
+  #   - name: Upload the softmax roofline
+  #     uses: actions/upload-artifact@v4
+  #     with:
+  #       name: softmax_roofline
+  #       path: softmax.png
+  #   - name: Upload the fdotproduct roofline
+  #     uses: actions/upload-artifact@v4
+  #     with:
+  #       name: fdotproduct_plots
+  #       path: fdotproduct.tar
+  #   - name: Upload the dotproduct roofline
+  #     uses: actions/upload-artifact@v4
+  #     with:
+  #       name: dotproduct_plots
+  #       path: dotproduct.tar
+  #   - name: Upload the pathfinder roofline
+  #     uses: actions/upload-artifact@v4
+  #     with:
+  #       name: pathfinder_roofline
+  #       path: pathfinder.png
+  #   - name: Upload the roi_align roofline
+  #     uses: actions/upload-artifact@v4
+  #     with:
+  #       name: roi_align_roofline
+  #       path: roi_align.png
+  #   - name: Upload the lavamd roofline
+  #     uses: actions/upload-artifact@v4
+  #     with:
+  #       name: lavamd_roofline
+  #       path: lavamd.png
+
+####################
+#  Clean-up stage  #
+####################
+
+  clean-up:
+    runs-on: ubuntu-22.04
+    if: always()
+    # needs: ["simulate", "riscv-tests-spike", "riscv-tests-simv"]
+    needs: ["simulate"]
+    steps:
+      - uses: actions/checkout@v4
+      - name: Delete artifacts
+        uses: geekyeggo/delete-artifact@v5
+        with:
+          name: |
+            tc-llvm
+            tc-gcc
+            tc-isa-sim
+            tc-verilator
+            riscv-tests-spike
+
+  clean-up-compile-runs:
+    runs-on: ubuntu-22.04
+    strategy:
+      max-parallel: 1
+      matrix:
+        ara_config: [2_lanes, 4_lanes, 8_lanes, 16_lanes]
+    if: always()
+    # needs: ["simulate", "riscv-tests-spike", "riscv-tests-simv"]
+    needs: ["simulate"]
+    steps:
+      - uses: actions/checkout@v4
+      - name: Delete artifacts
+        uses: geekyeggo/delete-artifact@v5
+        with:
+          name: |
+            compile-ara-${{ matrix.ara_config }}
+            compile-apps-${{ matrix.ara_config }}
+            compile-riscv-tests-${{ matrix.ara_config }}
+            benchmark-${{ matrix.ara_config }}
diff --git a/.github/workflows/sphinx.yml b/.github/workflows/sphinx.yml
new file mode 100644
index 0000000..caa1b74
--- /dev/null
+++ b/.github/workflows/sphinx.yml
@@ -0,0 +1,22 @@
+name: Sphinx build
+
+on: push
+
+jobs:
+  build:
+    runs-on: ubuntu-latest
+    steps:
+    - uses: actions/checkout@v4
+    - name: Build HTML
+      uses: ammaraskar/sphinx-action@master
+    - name: Upload artifacts
+      uses: actions/upload-artifact@v4
+      with:
+        name: html-docs
+        path: docs/build/html/
+    - name: Deploy
+      uses: peaceiris/actions-gh-pages@v4
+      if: github.ref == 'refs/heads/main'
+      with:
+        github_token: ${{ secrets.GITHUB_TOKEN }}
+        publish_dir: docs/build/html
diff --git a/apps/riscv-tests/LICENSE b/apps/riscv-tests/LICENSE
new file mode 100644
index 0000000..48fe522
--- /dev/null
+++ b/apps/riscv-tests/LICENSE
@@ -0,0 +1,24 @@
+Copyright (c) 2012-2015, The Regents of the University of California (Regents).
+All Rights Reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+1. Redistributions of source code must retain the above copyright
+   notice, this list of conditions and the following disclaimer.
+2. Redistributions in binary form must reproduce the above copyright
+   notice, this list of conditions and the following disclaimer in the
+   documentation and/or other materials provided with the distribution.
+3. Neither the name of the Regents nor the
+   names of its contributors may be used to endorse or promote products
+   derived from this software without specific prior written permission.
+
+IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,
+SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING
+OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS
+BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED
+HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE
+MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
diff --git a/apps/riscv-tests/Makefile.in b/apps/riscv-tests/Makefile.in
new file mode 100644
index 0000000..f00c8a2
--- /dev/null
+++ b/apps/riscv-tests/Makefile.in
@@ -0,0 +1,45 @@
+prefix          := @prefix@
+abs_top_src_dir := @abs_top_srcdir@
+XLEN            := @XLEN@
+target_alias    := @target_alias@
+ifeq ($(target_alias),)
+RISCV_PREFIX_VAR :=
+else
+RISCV_PREFIX_VAR := RISCV_PREFIX=@target_alias@-
+endif
+instbasedir     := $(DESTDIR)$(prefix)
+bmarkdir        := $(abs_top_src_dir)/benchmarks
+isa_src_dir     := $(abs_top_src_dir)/isa
+debug_src_dir   := $(abs_top_src_dir)/debug
+
+all: benchmarks isa
+
+install: all
+	install -d $(instbasedir)/share/riscv-tests/isa
+	install -d $(instbasedir)/share/riscv-tests/benchmarks
+	install -p -m 644 `find isa -maxdepth 1 -type f` $(instbasedir)/share/riscv-tests/isa
+	install -p -m 644 `find benchmarks -maxdepth 1 -type f` $(instbasedir)/share/riscv-tests/benchmarks
+
+benchmarks:
+	mkdir -p benchmarks
+	$(MAKE) -C benchmarks -f $(bmarkdir)/Makefile src_dir=$(bmarkdir) XLEN=$(XLEN) $(RISCV_PREFIX_VAR)
+
+isa:
+	mkdir -p isa
+	$(MAKE) -C isa -f $(isa_src_dir)/Makefile src_dir=$(isa_src_dir) XLEN=$(XLEN) $(RISCV_PREFIX_VAR)
+
+debug-check:
+	mkdir -p debug
+	$(MAKE) -C debug -f $(debug_src_dir)/Makefile src_dir=$(debug_src_dir) XLEN=$(XLEN)
+
+debug-check-fast:
+	mkdir -p debug
+	$(MAKE) -C debug -f $(debug_src_dir)/Makefile src_dir=$(debug_src_dir) XLEN=$(XLEN) spike$(XLEN)
+
+clean:
+	[ ! -d isa ]        || $(MAKE) -C isa -f $(isa_src_dir)/Makefile src_dir=$(isa_src_dir) clean
+	[ ! -d benchmarks ] || $(MAKE) -C benchmarks -f $(bmarkdir)/Makefile src_dir=$(bmarkdir) clean
+	[ ! -d debug ]      || $(MAKE) -C debug -f $(debug_src_dir)/Makefile src_dir=$(debug_src_dir) clean
+
+.PHONY: benchmarks isa clean
+
diff --git a/apps/riscv-tests/README.md b/apps/riscv-tests/README.md
new file mode 100644
index 0000000..850878a
--- /dev/null
+++ b/apps/riscv-tests/README.md
@@ -0,0 +1,177 @@
+riscv-tests
+================
+
+About
+-----------
+
+This repository hosts unit tests for RISC-V processors.
+
+Building from repository
+-----------------------------
+
+We assume that the RISCV environment variable is set to the RISC-V tools
+install path, and that the riscv-gnu-toolchain package is installed.
+
+    $ git clone https://github.com/riscv/riscv-tests
+    $ cd riscv-tests
+    $ git submodule update --init --recursive
+    $ autoconf
+    $ ./configure --prefix=$RISCV/target
+    $ make
+    $ make install
+
+The rest of this document describes the format of test programs for the RISC-V
+architecture.
+
+Test Virtual Machines
+-------------------------
+
+To allow maximum reuse of a given test, each test program is constrained to
+only use features of a given *test virtual machine* or TVM. A TVM hides
+differences between alternative implementations by defining:
+
+* The set of registers and instructions that can be used. 
+* Which portions of memory can be accessed.
+* The way the test program starts and ends execution. 
+* The way that test data is input.
+* The way that test results are output.
+
+The following table shows the TVMs currently defined for RISC-V. All of these
+TVMs only support a single hardware thread.
+
+TVM Name | Description
+--- | ---
+`rv32ui` | RV32 user-level, integer only
+`rv32si` | RV32 supervisor-level, integer only
+`rv64ui` | RV64 user-level, integer only
+`rv64uf` | RV64 user-level, integer and floating-point
+`rv64uv` | RV64 user-level, integer, floating-point, and vector
+`rv64si` | RV64 supervisor-level, integer only
+`rv64sv` | RV64 supervisor-level, integer and vector
+
+A test program for RISC-V is written within a single assembly language file,
+which is passed through the C preprocessor, and all regular assembly
+directives can be used. An example test program is shown below. Each test
+program should first include the `riscv test.h` header file, which defines the
+macros used by the TVM. The header file will have different contents depending
+on the target environment for which the test will be built.  One of the goals
+of the various TVMs is to allow the same test program to be compiled and run
+on very different target environments yet still produce the same results. The
+following table shows the target environment currently defined.
+
+Target Environment Name | Description
+--- | ---
+`p` | virtual memory is disabled, only core 0 boots up
+`pm` | virtual memory is disabled, all cores boot up
+`pt` | virtual memory is disabled, timer interrupt fires every 100 cycles
+`v` | virtual memory is enabled
+
+Each test program must next specify for which TVM it is designed by including
+the appropriate TVM macro, `RVTEST_RV64U` in this example. This specification
+can change the way in which subsequent macros are interpreted, and supports
+a static check of the TVM functionality used by the program.
+
+The test program will begin execution at the first instruction after
+`RVTEST_CODE_BEGIN`, and continue until execution reaches an `RVTEST_PASS`
+macro or the `RVTEST_CODE_END` macro, which is implicitly a success. A test
+can explicitly fail by invoking the `RVTEST_FAIL` macro.
+
+The example program contains self-checking code to test the result of the add.
+However, self-checks rely on correct functioning of the processor instructions
+used to implement the self check (e.g., the branch) and so cannot be the only
+testing strategy.
+
+All tests should also contain a test data section, delimited by
+`RVTEST_DATA_BEGIN` and `RVTEST_DATA_END`. There is no alignment guarantee for
+the start of the test data section, so regular assembler alignment
+instructions should be used to ensure desired alignment of data values. This
+region of memory will be captured at the end of the test to act as a signature
+from the test. The signature can be compared with that from a run on the
+golden model.
+
+Any given test environment for running tests should also include a timeout
+facility, which will class a test as failing if it does not successfully
+complete a test within a reasonable time bound.
+
+    #include "riscv_test.h"
+
+    RVTEST_RV64U        # Define TVM used by program.
+
+    # Test code region.
+    RVTEST_CODE_BEGIN   # Start of test code.
+            lw      x2, testdata
+            addi    x2, 1         # Should be 42 into $2.
+            sw      x2, result    # Store result into memory overwriting 1s.
+            li      x3, 42        # Desired result.
+            bne     x2, x3, fail  # Fail out if doesn't match.
+            RVTEST_PASS           # Signal success.
+    fail:
+            RVTEST_FAIL
+    RVTEST_CODE_END     # End of test code.
+
+    # Input data section.
+    # This section is optional, and this data is NOT saved in the output.
+    .data
+            .align 3
+    testdata:
+            .dword 41
+
+    # Output data section.
+    RVTEST_DATA_BEGIN   # Start of test output data region.
+            .align 3
+    result:
+            .dword -1
+    RVTEST_DATA_END     # End of test output data region.
+
+User-Level TVMs
+--------------------
+
+Test programs for the `rv32u*` and `rv64u*` TVMs can contain all instructions
+from the respective base user-level ISA (RV32 or RV64), except for those with
+the SYSTEM major opcode (syscall, break, rdcycle, rdtime, rdinstret). All user
+registers (pc, x0-x31, f0-f31, fsr) can be accessed.
+
+The `rv32ui` and `rv64ui` TVMs are integer-only subsets of `rv32u` and `rv64u`
+respectively. These subsets can not use any floating-point instructions (major
+opcodes: LOAD-FP, STORE-FP, MADD, MSUB, NMSUB, NMADD, OP-FP), and hence cannot
+access the floating-point register state (f0-f31 and fsr). The integer-only
+TVMs are useful for initial processor bringup and to test simpler
+implementations that lack a hardware FPU.
+
+Note that any `rv32ui` test program is also valid for the `rv32u` TVM, and
+similarly `rv64ui` is a strict subset of `rv64u`. To allow a given test to run
+on the widest possible set of implementations, it is desirable to write any
+given test to run on the smallest or least capable TVM possible. For example,
+any simple tests of integer functionality should be written for the `rv64ui`
+TVM, as the same test can then be run on RV64 implementations with or without a
+hardware FPU. As another example, all tests for these base user-level TVMs will
+also be valid for more advanced processors with instruction-set extensions.
+
+At the start of execution, the values of all registers are undefined. All
+branch and jump destinations must be to labels within the test code region of
+the assembler source file. The code and data sections will be relocated
+differently for the various implementations of the test environment, and so
+test program results shall not depend on absolute addresses of instructions or
+data memory. The test build environment should support randomization of the
+section relocation to provide better coverage and to ensure test signatures do
+not contain absolute addresses.
+
+Supervisor-Level TVMs
+--------------------------
+
+The supervisor-level TVMs allow testing of supervisor-level state and
+instructions.  As with the user-level TVMs, we provide integer-only
+supervisor-level TVMs indicated with a trailing `i`.
+
+History and Acknowledgements
+---------------------------------
+
+This style of test virtual machine originated with the T0 (Torrent-0) vector
+microprocessor project at UC Berkeley and ICSI, begun in 1992. The main
+developers of this test strategy were Krste Asanovic and David Johnson. A
+precursor to `torture` was `rantor` developed by Phil Kohn at ICSI.
+
+A variant of this testing approach was also used for the Scale vector-thread
+processor at MIT, begun in 2000. Ronny Krashinsky and Christopher Batten were
+the principal architects of the Scale chip. Jeffrey Cohen and Mark Hampton
+developed a version of torture capable of generating vector-thread code.
diff --git a/apps/riscv-tests/benchmarks/Makefile b/apps/riscv-tests/benchmarks/Makefile
new file mode 100644
index 0000000..cc32714
--- /dev/null
+++ b/apps/riscv-tests/benchmarks/Makefile
@@ -0,0 +1,98 @@
+#=======================================================================
+# UCB VLSI FLOW: Makefile for riscv-bmarks
+#-----------------------------------------------------------------------
+# Yunsup Lee (yunsup@cs.berkeley.edu)
+#
+
+XLEN ?= 64
+
+default: all
+
+src_dir = .
+
+instname = riscv-bmarks
+instbasedir = $(UCB_VLSI_HOME)/install
+
+#--------------------------------------------------------------------
+# Sources
+#--------------------------------------------------------------------
+
+bmarks = \
+	median \
+	qsort \
+	rsort \
+	towers \
+	vvadd \
+	multiply \
+	mm \
+	dhrystone \
+	spmv \
+	mt-vvadd \
+	mt-matmul \
+	pmp \
+
+#--------------------------------------------------------------------
+# Build rules
+#--------------------------------------------------------------------
+
+RISCV_PREFIX ?= riscv$(XLEN)-unknown-elf-
+RISCV_GCC ?= $(RISCV_PREFIX)gcc
+RISCV_GCC_OPTS ?= -DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -ffast-math -fno-common -fno-builtin-printf
+RISCV_LINK ?= $(RISCV_GCC) -T $(src_dir)/common/test.ld $(incs)
+RISCV_LINK_OPTS ?= -static -nostdlib -nostartfiles -lm -lgcc -T $(src_dir)/common/test.ld
+RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data
+RISCV_SIM ?= spike --isa=rv$(XLEN)gc
+
+incs  += -I$(src_dir)/../env -I$(src_dir)/common $(addprefix -I$(src_dir)/, $(bmarks))
+objs  :=
+
+define compile_template
+$(1).riscv: $(wildcard $(src_dir)/$(1)/*) $(wildcard $(src_dir)/common/*)
+	$$(RISCV_GCC) $$(incs) $$(RISCV_GCC_OPTS) -o $$@ $(wildcard $(src_dir)/$(1)/*.c) $(wildcard $(src_dir)/common/*.c) $(wildcard $(src_dir)/common/*.S) $$(RISCV_LINK_OPTS)
+endef
+
+$(foreach bmark,$(bmarks),$(eval $(call compile_template,$(bmark))))
+
+#------------------------------------------------------------
+# Build and run benchmarks on riscv simulator
+
+bmarks_riscv_bin  = $(addsuffix .riscv,  $(bmarks))
+bmarks_riscv_dump = $(addsuffix .riscv.dump, $(bmarks))
+bmarks_riscv_out  = $(addsuffix .riscv.out,  $(bmarks))
+
+$(bmarks_riscv_dump): %.riscv.dump: %.riscv
+	$(RISCV_OBJDUMP) $< > $@
+
+$(bmarks_riscv_out): %.riscv.out: %.riscv
+	$(RISCV_SIM) $< > $@
+
+riscv: $(bmarks_riscv_dump)
+run: $(bmarks_riscv_out)
+
+junk += $(bmarks_riscv_bin) $(bmarks_riscv_dump) $(bmarks_riscv_hex) $(bmarks_riscv_out)
+
+#------------------------------------------------------------
+# Default
+
+all: riscv
+
+#------------------------------------------------------------
+# Install
+
+date_suffix = $(shell date +%Y-%m-%d_%H-%M)
+install_dir = $(instbasedir)/$(instname)-$(date_suffix)
+latest_install = $(shell ls -1 -d $(instbasedir)/$(instname)* | tail -n 1)
+
+install:
+	mkdir $(install_dir)
+	cp -r $(bmarks_riscv_bin) $(bmarks_riscv_dump) $(install_dir)
+
+install-link:
+	rm -rf $(instbasedir)/$(instname)
+	ln -s $(latest_install) $(instbasedir)/$(instname)
+
+#------------------------------------------------------------
+# Clean up
+
+clean:
+	rm -rf $(objs) $(junk)
diff --git a/apps/riscv-tests/benchmarks/common/crt.S b/apps/riscv-tests/benchmarks/common/crt.S
new file mode 100644
index 0000000..018f929
--- /dev/null
+++ b/apps/riscv-tests/benchmarks/common/crt.S
@@ -0,0 +1,225 @@
+# See LICENSE for license details.
+
+#include "encoding.h"
+
+#if __riscv_xlen == 64
+# define LREG ld
+# define SREG sd
+# define REGBYTES 8
+#else
+# define LREG lw
+# define SREG sw
+# define REGBYTES 4
+#endif
+
+  .section ".text.init"
+  .globl _start
+_start:
+  li  x1, 0
+  li  x2, 0
+  li  x3, 0
+  li  x4, 0
+  li  x5, 0
+  li  x6, 0
+  li  x7, 0
+  li  x8, 0
+  li  x9, 0
+  li  x10,0
+  li  x11,0
+  li  x12,0
+  li  x13,0
+  li  x14,0
+  li  x15,0
+  li  x16,0
+  li  x17,0
+  li  x18,0
+  li  x19,0
+  li  x20,0
+  li  x21,0
+  li  x22,0
+  li  x23,0
+  li  x24,0
+  li  x25,0
+  li  x26,0
+  li  x27,0
+  li  x28,0
+  li  x29,0
+  li  x30,0
+  li  x31,0
+
+  # enable FPU and accelerator if present
+  li t0, MSTATUS_FS | MSTATUS_XS
+  csrs mstatus, t0
+
+  # make sure XLEN agrees with compilation choice
+  li t0, 1
+  slli t0, t0, 31
+#if __riscv_xlen == 64
+  bgez t0, 1f
+#else
+  bltz t0, 1f
+#endif
+2:
+  li a0, 1
+  sw a0, tohost, t0
+  j 2b
+1:
+
+#ifdef __riscv_flen
+  # initialize FPU if we have one
+  la t0, 1f
+  csrw mtvec, t0
+
+  fssr    x0
+  fmv.s.x f0, x0
+  fmv.s.x f1, x0
+  fmv.s.x f2, x0
+  fmv.s.x f3, x0
+  fmv.s.x f4, x0
+  fmv.s.x f5, x0
+  fmv.s.x f6, x0
+  fmv.s.x f7, x0
+  fmv.s.x f8, x0
+  fmv.s.x f9, x0
+  fmv.s.x f10,x0
+  fmv.s.x f11,x0
+  fmv.s.x f12,x0
+  fmv.s.x f13,x0
+  fmv.s.x f14,x0
+  fmv.s.x f15,x0
+  fmv.s.x f16,x0
+  fmv.s.x f17,x0
+  fmv.s.x f18,x0
+  fmv.s.x f19,x0
+  fmv.s.x f20,x0
+  fmv.s.x f21,x0
+  fmv.s.x f22,x0
+  fmv.s.x f23,x0
+  fmv.s.x f24,x0
+  fmv.s.x f25,x0
+  fmv.s.x f26,x0
+  fmv.s.x f27,x0
+  fmv.s.x f28,x0
+  fmv.s.x f29,x0
+  fmv.s.x f30,x0
+  fmv.s.x f31,x0
+1:
+#endif
+
+  # initialize trap vector
+  la t0, trap_entry
+  csrw mtvec, t0
+
+  # initialize global pointer
+.option push
+.option norelax
+  la gp, __global_pointer$
+.option pop
+
+  la  tp, _end + 63
+  and tp, tp, -64
+
+  # get core id
+  csrr a0, mhartid
+  # for now, assume only 1 core
+  li a1, 1
+1:bgeu a0, a1, 1b
+
+  # give each core 128KB of stack + TLS
+#define STKSHIFT 17
+  add sp, a0, 1
+  sll sp, sp, STKSHIFT
+  add sp, sp, tp
+  sll a2, a0, STKSHIFT
+  add tp, tp, a2
+
+  j _init
+
+  .align 2
+trap_entry:
+  addi sp, sp, -272
+
+  SREG x1, 1*REGBYTES(sp)
+  SREG x2, 2*REGBYTES(sp)
+  SREG x3, 3*REGBYTES(sp)
+  SREG x4, 4*REGBYTES(sp)
+  SREG x5, 5*REGBYTES(sp)
+  SREG x6, 6*REGBYTES(sp)
+  SREG x7, 7*REGBYTES(sp)
+  SREG x8, 8*REGBYTES(sp)
+  SREG x9, 9*REGBYTES(sp)
+  SREG x10, 10*REGBYTES(sp)
+  SREG x11, 11*REGBYTES(sp)
+  SREG x12, 12*REGBYTES(sp)
+  SREG x13, 13*REGBYTES(sp)
+  SREG x14, 14*REGBYTES(sp)
+  SREG x15, 15*REGBYTES(sp)
+  SREG x16, 16*REGBYTES(sp)
+  SREG x17, 17*REGBYTES(sp)
+  SREG x18, 18*REGBYTES(sp)
+  SREG x19, 19*REGBYTES(sp)
+  SREG x20, 20*REGBYTES(sp)
+  SREG x21, 21*REGBYTES(sp)
+  SREG x22, 22*REGBYTES(sp)
+  SREG x23, 23*REGBYTES(sp)
+  SREG x24, 24*REGBYTES(sp)
+  SREG x25, 25*REGBYTES(sp)
+  SREG x26, 26*REGBYTES(sp)
+  SREG x27, 27*REGBYTES(sp)
+  SREG x28, 28*REGBYTES(sp)
+  SREG x29, 29*REGBYTES(sp)
+  SREG x30, 30*REGBYTES(sp)
+  SREG x31, 31*REGBYTES(sp)
+
+  csrr a0, mcause
+  csrr a1, mepc
+  mv a2, sp
+  jal handle_trap
+  csrw mepc, a0
+
+  # Remain in M-mode after eret
+  li t0, MSTATUS_MPP
+  csrs mstatus, t0
+
+  LREG x1, 1*REGBYTES(sp)
+  LREG x2, 2*REGBYTES(sp)
+  LREG x3, 3*REGBYTES(sp)
+  LREG x4, 4*REGBYTES(sp)
+  LREG x5, 5*REGBYTES(sp)
+  LREG x6, 6*REGBYTES(sp)
+  LREG x7, 7*REGBYTES(sp)
+  LREG x8, 8*REGBYTES(sp)
+  LREG x9, 9*REGBYTES(sp)
+  LREG x10, 10*REGBYTES(sp)
+  LREG x11, 11*REGBYTES(sp)
+  LREG x12, 12*REGBYTES(sp)
+  LREG x13, 13*REGBYTES(sp)
+  LREG x14, 14*REGBYTES(sp)
+  LREG x15, 15*REGBYTES(sp)
+  LREG x16, 16*REGBYTES(sp)
+  LREG x17, 17*REGBYTES(sp)
+  LREG x18, 18*REGBYTES(sp)
+  LREG x19, 19*REGBYTES(sp)
+  LREG x20, 20*REGBYTES(sp)
+  LREG x21, 21*REGBYTES(sp)
+  LREG x22, 22*REGBYTES(sp)
+  LREG x23, 23*REGBYTES(sp)
+  LREG x24, 24*REGBYTES(sp)
+  LREG x25, 25*REGBYTES(sp)
+  LREG x26, 26*REGBYTES(sp)
+  LREG x27, 27*REGBYTES(sp)
+  LREG x28, 28*REGBYTES(sp)
+  LREG x29, 29*REGBYTES(sp)
+  LREG x30, 30*REGBYTES(sp)
+  LREG x31, 31*REGBYTES(sp)
+
+  addi sp, sp, 272
+  mret
+
+.section ".tohost","aw",@progbits
+.align 6
+.globl tohost
+tohost: .dword 0
+.align 6
+.globl fromhost
+fromhost: .dword 0
diff --git a/apps/riscv-tests/benchmarks/common/syscalls.c b/apps/riscv-tests/benchmarks/common/syscalls.c
new file mode 100644
index 0000000..4d20be9
--- /dev/null
+++ b/apps/riscv-tests/benchmarks/common/syscalls.c
@@ -0,0 +1,469 @@
+// See LICENSE for license details.
+
+#include <stdint.h>
+#include <string.h>
+#include <stdarg.h>
+#include <stdio.h>
+#include <limits.h>
+#include <sys/signal.h>
+#include "util.h"
+
+#define SYS_write 64
+
+#undef strcmp
+
+extern volatile uint64_t tohost;
+extern volatile uint64_t fromhost;
+
+static uintptr_t syscall(uintptr_t which, uint64_t arg0, uint64_t arg1, uint64_t arg2)
+{
+  volatile uint64_t magic_mem[8] __attribute__((aligned(64)));
+  magic_mem[0] = which;
+  magic_mem[1] = arg0;
+  magic_mem[2] = arg1;
+  magic_mem[3] = arg2;
+  __sync_synchronize();
+
+  tohost = (uintptr_t)magic_mem;
+  while (fromhost == 0)
+    ;
+  fromhost = 0;
+
+  __sync_synchronize();
+  return magic_mem[0];
+}
+
+#define NUM_COUNTERS 2
+static uintptr_t counters[NUM_COUNTERS];
+static char* counter_names[NUM_COUNTERS];
+
+void setStats(int enable)
+{
+  int i = 0;
+#define READ_CTR(name) do { \
+    while (i >= NUM_COUNTERS) ; \
+    uintptr_t csr = read_csr(name); \
+    if (!enable) { csr -= counters[i]; counter_names[i] = #name; } \
+    counters[i++] = csr; \
+  } while (0)
+
+  READ_CTR(mcycle);
+  READ_CTR(minstret);
+
+#undef READ_CTR
+}
+
+void __attribute__((noreturn)) tohost_exit(uintptr_t code)
+{
+  tohost = (code << 1) | 1;
+  while (1);
+}
+
+uintptr_t __attribute__((weak)) handle_trap(uintptr_t cause, uintptr_t epc, uintptr_t regs[32])
+{
+  tohost_exit(1337);
+}
+
+void exit(int code)
+{
+  tohost_exit(code);
+}
+
+void abort()
+{
+  exit(128 + SIGABRT);
+}
+
+void printstr(const char* s)
+{
+  syscall(SYS_write, 1, (uintptr_t)s, strlen(s));
+}
+
+void __attribute__((weak)) thread_entry(int cid, int nc)
+{
+  // multi-threaded programs override this function.
+  // for the case of single-threaded programs, only let core 0 proceed.
+  while (cid != 0);
+}
+
+int __attribute__((weak)) main(int argc, char** argv)
+{
+  // single-threaded programs override this function.
+  printstr("Implement main(), foo!\n");
+  return -1;
+}
+
+static void init_tls()
+{
+  register void* thread_pointer asm("tp");
+  extern char _tdata_begin, _tdata_end, _tbss_end;
+  size_t tdata_size = &_tdata_end - &_tdata_begin;
+  memcpy(thread_pointer, &_tdata_begin, tdata_size);
+  size_t tbss_size = &_tbss_end - &_tdata_end;
+  memset(thread_pointer + tdata_size, 0, tbss_size);
+}
+
+void _init(int cid, int nc)
+{
+  init_tls();
+  thread_entry(cid, nc);
+
+  // only single-threaded programs should ever get here.
+  int ret = main(0, 0);
+
+  char buf[NUM_COUNTERS * 32] __attribute__((aligned(64)));
+  char* pbuf = buf;
+  for (int i = 0; i < NUM_COUNTERS; i++)
+    if (counters[i])
+      pbuf += sprintf(pbuf, "%s = %ld\n", counter_names[i], counters[i]);
+  if (pbuf != buf)
+    printstr(buf);
+
+  exit(ret);
+}
+
+#undef putchar
+int putchar(int ch)
+{
+  static __thread char buf[64] __attribute__((aligned(64)));
+  static __thread int buflen = 0;
+
+  buf[buflen++] = ch;
+
+  if (ch == '\n' || buflen == sizeof(buf))
+  {
+    syscall(SYS_write, 1, (uintptr_t)buf, buflen);
+    buflen = 0;
+  }
+
+  return 0;
+}
+
+void printhex(uint64_t x)
+{
+  char str[17];
+  int i;
+  for (i = 0; i < 16; i++)
+  {
+    str[15-i] = (x & 0xF) + ((x & 0xF) < 10 ? '0' : 'a'-10);
+    x >>= 4;
+  }
+  str[16] = 0;
+
+  printstr(str);
+}
+
+static inline void printnum(void (*putch)(int, void**), void **putdat,
+                    unsigned long long num, unsigned base, int width, int padc)
+{
+  unsigned digs[sizeof(num)*CHAR_BIT];
+  int pos = 0;
+
+  while (1)
+  {
+    digs[pos++] = num % base;
+    if (num < base)
+      break;
+    num /= base;
+  }
+
+  while (width-- > pos)
+    putch(padc, putdat);
+
+  while (pos-- > 0)
+    putch(digs[pos] + (digs[pos] >= 10 ? 'a' - 10 : '0'), putdat);
+}
+
+static unsigned long long getuint(va_list *ap, int lflag)
+{
+  if (lflag >= 2)
+    return va_arg(*ap, unsigned long long);
+  else if (lflag)
+    return va_arg(*ap, unsigned long);
+  else
+    return va_arg(*ap, unsigned int);
+}
+
+static long long getint(va_list *ap, int lflag)
+{
+  if (lflag >= 2)
+    return va_arg(*ap, long long);
+  else if (lflag)
+    return va_arg(*ap, long);
+  else
+    return va_arg(*ap, int);
+}
+
+static void vprintfmt(void (*putch)(int, void**), void **putdat, const char *fmt, va_list ap)
+{
+  register const char* p;
+  const char* last_fmt;
+  register int ch, err;
+  unsigned long long num;
+  int base, lflag, width, precision, altflag;
+  char padc;
+
+  while (1) {
+    while ((ch = *(unsigned char *) fmt) != '%') {
+      if (ch == '\0')
+        return;
+      fmt++;
+      putch(ch, putdat);
+    }
+    fmt++;
+
+    // Process a %-escape sequence
+    last_fmt = fmt;
+    padc = ' ';
+    width = -1;
+    precision = -1;
+    lflag = 0;
+    altflag = 0;
+  reswitch:
+    switch (ch = *(unsigned char *) fmt++) {
+
+    // flag to pad on the right
+    case '-':
+      padc = '-';
+      goto reswitch;
+
+    // flag to pad with 0's instead of spaces
+    case '0':
+      padc = '0';
+      goto reswitch;
+
+    // width field
+    case '1':
+    case '2':
+    case '3':
+    case '4':
+    case '5':
+    case '6':
+    case '7':
+    case '8':
+    case '9':
+      for (precision = 0; ; ++fmt) {
+        precision = precision * 10 + ch - '0';
+        ch = *fmt;
+        if (ch < '0' || ch > '9')
+          break;
+      }
+      goto process_precision;
+
+    case '*':
+      precision = va_arg(ap, int);
+      goto process_precision;
+
+    case '.':
+      if (width < 0)
+        width = 0;
+      goto reswitch;
+
+    case '#':
+      altflag = 1;
+      goto reswitch;
+
+    process_precision:
+      if (width < 0)
+        width = precision, precision = -1;
+      goto reswitch;
+
+    // long flag (doubled for long long)
+    case 'l':
+      lflag++;
+      goto reswitch;
+
+    // character
+    case 'c':
+      putch(va_arg(ap, int), putdat);
+      break;
+
+    // string
+    case 's':
+      if ((p = va_arg(ap, char *)) == NULL)
+        p = "(null)";
+      if (width > 0 && padc != '-')
+        for (width -= strnlen(p, precision); width > 0; width--)
+          putch(padc, putdat);
+      for (; (ch = *p) != '\0' && (precision < 0 || --precision >= 0); width--) {
+        putch(ch, putdat);
+        p++;
+      }
+      for (; width > 0; width--)
+        putch(' ', putdat);
+      break;
+
+    // (signed) decimal
+    case 'd':
+      num = getint(&ap, lflag);
+      if ((long long) num < 0) {
+        putch('-', putdat);
+        num = -(long long) num;
+      }
+      base = 10;
+      goto signed_number;
+
+    // unsigned decimal
+    case 'u':
+      base = 10;
+      goto unsigned_number;
+
+    // (unsigned) octal
+    case 'o':
+      // should do something with padding so it's always 3 octits
+      base = 8;
+      goto unsigned_number;
+
+    // pointer
+    case 'p':
+      static_assert(sizeof(long) == sizeof(void*));
+      lflag = 1;
+      putch('0', putdat);
+      putch('x', putdat);
+      /* fall through to 'x' */
+
+    // (unsigned) hexadecimal
+    case 'x':
+      base = 16;
+    unsigned_number:
+      num = getuint(&ap, lflag);
+    signed_number:
+      printnum(putch, putdat, num, base, width, padc);
+      break;
+
+    // escaped '%' character
+    case '%':
+      putch(ch, putdat);
+      break;
+
+    // unrecognized escape sequence - just print it literally
+    default:
+      putch('%', putdat);
+      fmt = last_fmt;
+      break;
+    }
+  }
+}
+
+int printf(const char* fmt, ...)
+{
+  va_list ap;
+  va_start(ap, fmt);
+
+  vprintfmt((void*)putchar, 0, fmt, ap);
+
+  va_end(ap);
+  return 0; // incorrect return value, but who cares, anyway?
+}
+
+void sprintf_putch(int ch, void** data)
+{
+  char** pstr = (char**)data;
+  **pstr = ch;
+  (*pstr)++;
+}
+
+int sprintf(char* str, const char* fmt, ...)
+{
+  va_list ap;
+  char* str0 = str;
+  va_start(ap, fmt);
+
+  vprintfmt(sprintf_putch, (void**)&str, fmt, ap);
+  *str = 0;
+
+  va_end(ap);
+  return str - str0;
+}
+
+void* memcpy(void* dest, const void* src, size_t len)
+{
+  if ((((uintptr_t)dest | (uintptr_t)src | len) & (sizeof(uintptr_t)-1)) == 0) {
+    const uintptr_t* s = src;
+    uintptr_t *d = dest;
+    while (d < (uintptr_t*)(dest + len))
+      *d++ = *s++;
+  } else {
+    const char* s = src;
+    char *d = dest;
+    while (d < (char*)(dest + len))
+      *d++ = *s++;
+  }
+  return dest;
+}
+
+void* memset(void* dest, int byte, size_t len)
+{
+  if ((((uintptr_t)dest | len) & (sizeof(uintptr_t)-1)) == 0) {
+    uintptr_t word = byte & 0xFF;
+    word |= word << 8;
+    word |= word << 16;
+    word |= word << 16 << 16;
+
+    uintptr_t *d = dest;
+    while (d < (uintptr_t*)(dest + len))
+      *d++ = word;
+  } else {
+    char *d = dest;
+    while (d < (char*)(dest + len))
+      *d++ = byte;
+  }
+  return dest;
+}
+
+size_t strlen(const char *s)
+{
+  const char *p = s;
+  while (*p)
+    p++;
+  return p - s;
+}
+
+size_t strnlen(const char *s, size_t n)
+{
+  const char *p = s;
+  while (n-- && *p)
+    p++;
+  return p - s;
+}
+
+int strcmp(const char* s1, const char* s2)
+{
+  unsigned char c1, c2;
+
+  do {
+    c1 = *s1++;
+    c2 = *s2++;
+  } while (c1 != 0 && c1 == c2);
+
+  return c1 - c2;
+}
+
+char* strcpy(char* dest, const char* src)
+{
+  char* d = dest;
+  while ((*d++ = *src++))
+    ;
+  return dest;
+}
+
+long atol(const char* str)
+{
+  long res = 0;
+  int sign = 0;
+
+  while (*str == ' ')
+    str++;
+
+  if (*str == '-' || *str == '+') {
+    sign = *str == '-';
+    str++;
+  }
+
+  while (*str) {
+    res *= 10;
+    res += *str++ - '0';
+  }
+
+  return sign ? -res : res;
+}
diff --git a/apps/riscv-tests/benchmarks/common/test.ld b/apps/riscv-tests/benchmarks/common/test.ld
new file mode 100644
index 0000000..a50b017
--- /dev/null
+++ b/apps/riscv-tests/benchmarks/common/test.ld
@@ -0,0 +1,66 @@
+/*======================================================================*/
+/* Proxy kernel linker script                                           */
+/*======================================================================*/
+/* This is the linker script used when building the proxy kernel. */
+
+/*----------------------------------------------------------------------*/
+/* Setup                                                                */
+/*----------------------------------------------------------------------*/
+
+/* The OUTPUT_ARCH command specifies the machine architecture where the
+   argument is one of the names used in the BFD library. More
+   specifically one of the entires in bfd/cpu-mips.c */
+
+OUTPUT_ARCH( "riscv" )
+ENTRY(_start)
+
+/*----------------------------------------------------------------------*/
+/* Sections                                                             */
+/*----------------------------------------------------------------------*/
+
+SECTIONS
+{
+
+  /* text: test code section */
+  . = 0x80000000;
+  .text.init : { *(.text.init) }
+
+  . = ALIGN(0x1000);
+  .tohost : { *(.tohost) }
+
+  . = ALIGN(0x1000);
+  .text : { *(.text) }
+
+  /* data segment */
+  .data : { *(.data) }
+
+  .sdata : {
+    __global_pointer$ = . + 0x800;
+    *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*)
+    *(.sdata .sdata.* .gnu.linkonce.s.*)
+  }
+
+  /* bss segment */
+  .sbss : {
+    *(.sbss .sbss.* .gnu.linkonce.sb.*)
+    *(.scommon)
+  }
+  .bss : { *(.bss) }
+
+  /* thread-local data segment */
+  .tdata :
+  {
+    _tdata_begin = .;
+    *(.tdata)
+    _tdata_end = .;
+  }
+  .tbss :
+  {
+    *(.tbss)
+    _tbss_end = .;
+  }
+
+  /* End of uninitalized data segement */
+  _end = .;
+}
+
diff --git a/apps/riscv-tests/benchmarks/common/util.h b/apps/riscv-tests/benchmarks/common/util.h
new file mode 100644
index 0000000..081cfd6
--- /dev/null
+++ b/apps/riscv-tests/benchmarks/common/util.h
@@ -0,0 +1,90 @@
+// See LICENSE for license details.
+
+#ifndef __UTIL_H
+#define __UTIL_H
+
+extern void setStats(int enable);
+
+#include <stdint.h>
+
+#define static_assert(cond) switch(0) { case 0: case !!(long)(cond): ; }
+
+static int verify(int n, const volatile int* test, const int* verify)
+{
+  int i;
+  // Unrolled for faster verification
+  for (i = 0; i < n/2*2; i+=2)
+  {
+    int t0 = test[i], t1 = test[i+1];
+    int v0 = verify[i], v1 = verify[i+1];
+    if (t0 != v0) return i+1;
+    if (t1 != v1) return i+2;
+  }
+  if (n % 2 != 0 && test[n-1] != verify[n-1])
+    return n;
+  return 0;
+}
+
+static int verifyDouble(int n, const volatile double* test, const double* verify)
+{
+  int i;
+  // Unrolled for faster verification
+  for (i = 0; i < n/2*2; i+=2)
+  {
+    double t0 = test[i], t1 = test[i+1];
+    double v0 = verify[i], v1 = verify[i+1];
+    int eq1 = t0 == v0, eq2 = t1 == v1;
+    if (!(eq1 & eq2)) return i+1+eq1;
+  }
+  if (n % 2 != 0 && test[n-1] != verify[n-1])
+    return n;
+  return 0;
+}
+
+static void __attribute__((noinline)) barrier(int ncores)
+{
+  static volatile int sense;
+  static volatile int count;
+  static __thread int threadsense;
+
+  __sync_synchronize();
+
+  threadsense = !threadsense;
+  if (__sync_fetch_and_add(&count, 1) == ncores-1)
+  {
+    count = 0;
+    sense = threadsense;
+  }
+  else while(sense != threadsense)
+    ;
+
+  __sync_synchronize();
+}
+
+static uint64_t lfsr(uint64_t x)
+{
+  uint64_t bit = (x ^ (x >> 1)) & 1;
+  return (x >> 1) | (bit << 62);
+}
+
+static uintptr_t insn_len(uintptr_t pc)
+{
+  return (*(unsigned short*)pc & 3) ? 4 : 2;
+}
+
+#ifdef __riscv
+#include "encoding.h"
+#endif
+
+#define stringify_1(s) #s
+#define stringify(s) stringify_1(s)
+#define stats(code, iter) do { \
+    unsigned long _c = -read_csr(mcycle), _i = -read_csr(minstret); \
+    code; \
+    _c += read_csr(mcycle), _i += read_csr(minstret); \
+    if (cid == 0) \
+      printf("\n%s: %ld cycles, %ld.%ld cycles/iter, %ld.%ld CPI\n", \
+             stringify(code), _c, _c/iter, 10*_c/iter%10, _c/_i, 10*_c/_i%10); \
+  } while(0)
+
+#endif //__UTIL_H
diff --git a/apps/riscv-tests/benchmarks/dhrystone/dhrystone.c b/apps/riscv-tests/benchmarks/dhrystone/dhrystone.c
new file mode 100644
index 0000000..38e3376
--- /dev/null
+++ b/apps/riscv-tests/benchmarks/dhrystone/dhrystone.c
@@ -0,0 +1,185 @@
+// See LICENSE for license details.
+
+#pragma GCC optimize ("no-inline")
+
+#include "dhrystone.h"
+
+#ifndef REG
+#define REG
+        /* REG becomes defined as empty */
+        /* i.e. no register variables   */
+#else
+#undef REG
+#define REG register
+#endif
+
+extern  int     Int_Glob;
+extern  char    Ch_1_Glob;
+
+
+Proc_6 (Enum_Val_Par, Enum_Ref_Par)
+/*********************************/
+    /* executed once */
+    /* Enum_Val_Par == Ident_3, Enum_Ref_Par becomes Ident_2 */
+
+Enumeration  Enum_Val_Par;
+Enumeration *Enum_Ref_Par;
+{
+  *Enum_Ref_Par = Enum_Val_Par;
+  if (! Func_3 (Enum_Val_Par))
+    /* then, not executed */
+    *Enum_Ref_Par = Ident_4;
+  switch (Enum_Val_Par)
+  {
+    case Ident_1: 
+      *Enum_Ref_Par = Ident_1;
+      break;
+    case Ident_2: 
+      if (Int_Glob > 100)
+        /* then */
+      *Enum_Ref_Par = Ident_1;
+      else *Enum_Ref_Par = Ident_4;
+      break;
+    case Ident_3: /* executed */
+      *Enum_Ref_Par = Ident_2;
+      break;
+    case Ident_4: break;
+    case Ident_5: 
+      *Enum_Ref_Par = Ident_3;
+      break;
+  } /* switch */
+} /* Proc_6 */
+
+
+Proc_7 (Int_1_Par_Val, Int_2_Par_Val, Int_Par_Ref)
+/**********************************************/
+    /* executed three times                                      */ 
+    /* first call:      Int_1_Par_Val == 2, Int_2_Par_Val == 3,  */
+    /*                  Int_Par_Ref becomes 7                    */
+    /* second call:     Int_1_Par_Val == 10, Int_2_Par_Val == 5, */
+    /*                  Int_Par_Ref becomes 17                   */
+    /* third call:      Int_1_Par_Val == 6, Int_2_Par_Val == 10, */
+    /*                  Int_Par_Ref becomes 18                   */
+One_Fifty       Int_1_Par_Val;
+One_Fifty       Int_2_Par_Val;
+One_Fifty      *Int_Par_Ref;
+{
+  One_Fifty Int_Loc;
+
+  Int_Loc = Int_1_Par_Val + 2;
+  *Int_Par_Ref = Int_2_Par_Val + Int_Loc;
+} /* Proc_7 */
+
+
+Proc_8 (Arr_1_Par_Ref, Arr_2_Par_Ref, Int_1_Par_Val, Int_2_Par_Val)
+/*********************************************************************/
+    /* executed once      */
+    /* Int_Par_Val_1 == 3 */
+    /* Int_Par_Val_2 == 7 */
+Arr_1_Dim       Arr_1_Par_Ref;
+Arr_2_Dim       Arr_2_Par_Ref;
+int             Int_1_Par_Val;
+int             Int_2_Par_Val;
+{
+  REG One_Fifty Int_Index;
+  REG One_Fifty Int_Loc;
+
+  Int_Loc = Int_1_Par_Val + 5;
+  Arr_1_Par_Ref [Int_Loc] = Int_2_Par_Val;
+  Arr_1_Par_Ref [Int_Loc+1] = Arr_1_Par_Ref [Int_Loc];
+  Arr_1_Par_Ref [Int_Loc+30] = Int_Loc;
+  for (Int_Index = Int_Loc; Int_Index <= Int_Loc+1; ++Int_Index)
+    Arr_2_Par_Ref [Int_Loc] [Int_Index] = Int_Loc;
+  Arr_2_Par_Ref [Int_Loc] [Int_Loc-1] += 1;
+  Arr_2_Par_Ref [Int_Loc+20] [Int_Loc] = Arr_1_Par_Ref [Int_Loc];
+  Int_Glob = 5;
+} /* Proc_8 */
+
+
+Enumeration Func_1 (Ch_1_Par_Val, Ch_2_Par_Val)
+/*************************************************/
+    /* executed three times                                         */
+    /* first call:      Ch_1_Par_Val == 'H', Ch_2_Par_Val == 'R'    */
+    /* second call:     Ch_1_Par_Val == 'A', Ch_2_Par_Val == 'C'    */
+    /* third call:      Ch_1_Par_Val == 'B', Ch_2_Par_Val == 'C'    */
+
+Capital_Letter   Ch_1_Par_Val;
+Capital_Letter   Ch_2_Par_Val;
+{
+  Capital_Letter        Ch_1_Loc;
+  Capital_Letter        Ch_2_Loc;
+
+  Ch_1_Loc = Ch_1_Par_Val;
+  Ch_2_Loc = Ch_1_Loc;
+  if (Ch_2_Loc != Ch_2_Par_Val)
+    /* then, executed */
+    return (Ident_1);
+  else  /* not executed */
+  {
+    Ch_1_Glob = Ch_1_Loc;
+    return (Ident_2);
+   }
+} /* Func_1 */
+
+
+Boolean Func_2 (Str_1_Par_Ref, Str_2_Par_Ref)
+/*************************************************/
+    /* executed once */
+    /* Str_1_Par_Ref == "DHRYSTONE PROGRAM, 1'ST STRING" */
+    /* Str_2_Par_Ref == "DHRYSTONE PROGRAM, 2'ND STRING" */
+
+Str_30  Str_1_Par_Ref;
+Str_30  Str_2_Par_Ref;
+{
+  REG One_Thirty        Int_Loc;
+      Capital_Letter    Ch_Loc;
+
+  Int_Loc = 2;
+  while (Int_Loc <= 2) /* loop body executed once */
+    if (Func_1 (Str_1_Par_Ref[Int_Loc],
+                Str_2_Par_Ref[Int_Loc+1]) == Ident_1)
+      /* then, executed */
+    {
+      Ch_Loc = 'A';
+      Int_Loc += 1;
+    } /* if, while */
+  if (Ch_Loc >= 'W' && Ch_Loc < 'Z')
+    /* then, not executed */
+    Int_Loc = 7;
+  if (Ch_Loc == 'R')
+    /* then, not executed */
+    return (true);
+  else /* executed */
+  {
+    if (strcmp (Str_1_Par_Ref, Str_2_Par_Ref) > 0)
+      /* then, not executed */
+    {
+      Int_Loc += 7;
+      Int_Glob = Int_Loc;
+      return (true);
+    }
+    else /* executed */
+      return (false);
+  } /* if Ch_Loc */
+} /* Func_2 */
+
+
+Boolean Func_3 (Enum_Par_Val)
+/***************************/
+    /* executed once        */
+    /* Enum_Par_Val == Ident_3 */
+Enumeration Enum_Par_Val;
+{
+  Enumeration Enum_Loc;
+
+  Enum_Loc = Enum_Par_Val;
+  if (Enum_Loc == Ident_3)
+    /* then, executed */
+    return (true);
+  else /* not executed */
+    return (false);
+} /* Func_3 */
+
+void debug_printf(const char* str, ...)
+{
+}
diff --git a/apps/riscv-tests/benchmarks/dhrystone/dhrystone.h b/apps/riscv-tests/benchmarks/dhrystone/dhrystone.h
new file mode 100644
index 0000000..e350c17
--- /dev/null
+++ b/apps/riscv-tests/benchmarks/dhrystone/dhrystone.h
@@ -0,0 +1,477 @@
+// See LICENSE for license details.
+
+#ifndef _DHRYSTONE_H
+#define _DHRYSTONE_H
+
+/****************** "DHRYSTONE" Benchmark Program ***************************/
+#define Version "C, Version 2.2"
+/*  File:       dhry_1.c (part 2 of 3)
+ *  Author:     Reinhold P. Weicker
+ *              Siemens Nixdorf, Paderborn/Germany
+ *              weicker@specbench.org
+ *  Date:       May 25, 1988
+ *  Modified:	Steven Pemberton, CWI, Amsterdam; Steven.Pemberton@cwi.nl
+ *  Date:       October, 1993; March 1995
+ *              Included both files into one source, that gets compiled
+ *              in two passes. Made program auto-compiling, and auto-running,
+ *              and generally made it much easier to use.
+ *
+ *              Original Version (in Ada) published in
+ *              "Communications of the ACM" vol. 27., no. 10 (Oct. 1984),
+ *              pp. 1013 - 1030, together with the statistics
+ *              on which the distribution of statements etc. is based.
+ *
+ *              In this C version, the following C library functions are used:
+ *              - strcpy, strcmp (inside the measurement loop)
+ *              - printf, scanf (outside the measurement loop)
+ *              In addition, Berkeley UNIX system calls "times ()" or "time ()"
+ *              are used for execution time measurement. For measurements
+ *              on other systems, these calls have to be changed.
+ *
+ *  Collection of Results:
+ *              Reinhold Weicker (address see above) and
+ *              
+ *              Rick Richardson
+ *              PC Research. Inc.
+ *              94 Apple Orchard Drive
+ *              Tinton Falls, NJ 07724
+ *                      Phone:  (201) 389-8963 (9-17 EST)               
+ *                      Usenet: ...!uunet!pcrat!rick
+ *
+ *      Please send results to Rick Richardson and/or Reinhold Weicker.
+ *      Complete information should be given on hardware and software used.
+ *      Hardware information includes: Machine type, CPU, type and size
+ *      of caches; for microprocessors: clock frequency, memory speed
+ *      (number of wait states).
+ *      Software information includes: Compiler (and runtime library)
+ *      manufacturer and version, compilation switches, OS version.
+ *      The Operating System version may give an indication about the compiler;
+ *      Dhrystone itself performs no OS calls in the measurement loop.
+ *
+ *      The complete output generated by the program should be mailed
+ *      such that at least some checks for correctness can be made.
+ *
+ ***************************************************************************
+ *
+ * Defines:     The following "Defines" are possible:
+ *      -DREG          (default: Not defined)
+ *              As an approximation to what an average C programmer
+ *              might do, causes the "register" storage class to be applied
+ *              - for local variables, if they are used (dynamically)
+ *                five or more times
+ *              - for parameters if they are used (dynamically)
+ *                six or more times
+ *              Note that an optimal "register" strategy is
+ *              compiler-dependent, and that "register" declarations
+ *              do not necessarily lead to faster execution.
+ *      -DNOSTRUCTASSIGN        (default: Not defined)
+ *              Define if the C compiler does not support
+ *              assignment of structures.
+ *      -DNOENUMS               (default: Not defined)
+ *              Define if the C compiler does not support
+ *              enumeration types.
+ *      -DTIMES                 (default)
+ *      -DTIME
+ *              The "times" function of UNIX (returning process times)
+ *              or the "time" function (returning wallclock time)
+ *              is used for measurement. 
+ *              For single user machines, "time ()" is adequate. For
+ *              multi-user machines where you cannot get single-user
+ *              access, use the "times ()" function. If you have
+ *              neither, use a stopwatch in the dead of night.
+ *              "printf"s are provided marking the points "Start Timer"
+ *              and "Stop Timer". DO NOT use the UNIX "time(1)"
+ *              command, as this will measure the total time to
+ *              run this program, which will (erroneously) include
+ *              the time to allocate storage (malloc) and to perform
+ *              the initialization.
+ *      -DHZ=nnn
+ *              In Berkeley UNIX, the function "times" returns process
+ *              time in 1/HZ seconds, with HZ = 60 for most systems.
+ *              CHECK YOUR SYSTEM DESCRIPTION BEFORE YOU JUST APPLY
+ *              A VALUE.
+ *
+ ***************************************************************************
+ *
+ *  History:	Version C/2.1 was made for two reasons:
+ *
+ *	1) There was an obvious need for a common C version of
+ *      Dhrystone, since C is at present the most popular system
+ *      programming language for the class of processors
+ *      (microcomputers, minicomputers) where Dhrystone is used most.
+ *      There should be, as far as possible, only one C version of
+ *      Dhrystone such that results can be compared without
+ *      restrictions. In the past, the C versions distributed
+ *      by Rick Richardson (Version 1.1) and by Reinhold Weicker
+ *      had small (though not significant) differences.
+ *
+ *      2) As far as it is possible without changes to the Dhrystone
+ *      statistics, optimizing compilers should be prevented from
+ *      removing significant statements.
+ *
+ *      This C version has been developed in cooperation with
+ *      Rick Richardson (Tinton Falls, NJ), it incorporates many
+ *      ideas from the "Version 1.1" distributed previously by
+ *      him over the UNIX network Usenet.
+ *      I also thank Chaim Benedelac (National Semiconductor),
+ *      David Ditzel (SUN), Earl Killian and John Mashey (MIPS),
+ *      Alan Smith and Rafael Saavedra-Barrera (UC at Berkeley)
+ *      for their help with comments on earlier versions of the
+ *      benchmark.
+ *
+ *  Changes:    In the initialization part, this version follows mostly
+ *      Rick Richardson's version distributed via Usenet, not the
+ *      version distributed earlier via floppy disk by Reinhold Weicker.
+ *      As a concession to older compilers, names have been made
+ *      unique within the first 8 characters.
+ *      Inside the measurement loop, this version follows the
+ *      version previously distributed by Reinhold Weicker.
+ *
+ *      At several places in the benchmark, code has been added,
+ *      but within the measurement loop only in branches that 
+ *      are not executed. The intention is that optimizing compilers
+ *      should be prevented from moving code out of the measurement
+ *      loop, or from removing code altogether. Since the statements
+ *      that are executed within the measurement loop have NOT been
+ *      changed, the numbers defining the "Dhrystone distribution"
+ *      (distribution of statements, operand types and locality)
+ *      still hold. Except for sophisticated optimizing compilers,
+ *      execution times for this version should be the same as
+ *      for previous versions.
+ *
+ *      Since it has proven difficult to subtract the time for the
+ *      measurement loop overhead in a correct way, the loop check
+ *      has been made a part of the benchmark. This does have
+ *      an impact - though a very minor one - on the distribution
+ *      statistics which have been updated for this version.
+ *
+ *      All changes within the measurement loop are described
+ *      and discussed in the companion paper "Rationale for
+ *      Dhrystone version 2".
+ *
+ *      Because of the self-imposed limitation that the order and
+ *      distribution of the executed statements should not be
+ *      changed, there are still cases where optimizing compilers
+ *      may not generate code for some statements. To a certain
+ *      degree, this is unavoidable for small synthetic benchmarks.
+ *      Users of the benchmark are advised to check code listings
+ *      whether code is generated for all statements of Dhrystone.
+ *
+ *      Version 2.1 is identical to version 2.0 distributed via
+ *      the UNIX network Usenet in March 1988 except that it corrects
+ *      some minor deficiencies that were found by users of version 2.0.
+ *      The only change within the measurement loop is that a
+ *      non-executed "else" part was added to the "if" statement in
+ *      Func_3, and a non-executed "else" part removed from Proc_3.
+ *
+ * Version C/2.2, Steven Pemberton, October 1993
+ *	Functionally, identical to version 2.2; the changes are in
+ *	how you compile and use it:
+ *	- Everything is in one file now, but compiled in 2 passes
+ *	- Compile (and run) by running the file through the shell: 'sh dhry.c"
+ *	- Uses the system definition of HZ if one can be found
+ *	- HZ must be defined, otherwise it won't compile (no defaults here)
+ *	- The (uninteresting) output is printed to stderr (dhry2 > /dev/null)
+ *	- The number of loops is passed as a parameter, rather than read
+ *	  (dhry2 500000)
+ *	- If the number of loops is insufficient to get a good result,
+ *	  it repeats it with loops*10 until it is enough (rather than just
+ *	  stopping)
+ *	- Output says which sort of clock it is using, and the HZ value
+ *	- You can use -DREG instead of the -DREG=register of previous versions
+ *	- Some stylistic cleanups.
+ *		
+ ***************************************************************************
+ *
+ *  Compilation model and measurement (IMPORTANT):
+ *
+ *  The following "ground rules" apply for measurements:
+ *  - Separate compilation
+ *  - No procedure merging
+ *  - Otherwise, compiler optimizations are allowed but should be indicated
+ *  - Default results are those without register declarations
+ *  See the companion paper "Rationale for Dhrystone Version 2" for a more
+ *  detailed discussion of these ground rules.
+ *
+ *  For 16-Bit processors (e.g. 80186, 80286), times for all compilation
+ *  models ("small", "medium", "large" etc.) should be given if possible,
+ *  together with a definition of these models for the compiler system used.
+ *
+ **************************************************************************
+ *
+ *  Dhrystone (C version) statistics:
+ *
+ *  [Comment from the first distribution, updated for version 2.
+ *   Note that because of language differences, the numbers are slightly
+ *   different from the Ada version.]
+ *
+ *  The following program contains statements of a high level programming
+ *  language (here: C) in a distribution considered representative:           
+ *
+ *    assignments                  52 (51.0 %)
+ *    control statements           33 (32.4 %)
+ *    procedure, function calls    17 (16.7 %)
+ *
+ *  103 statements are dynamically executed. The program is balanced with
+ *  respect to the three aspects:                                             
+ *
+ *    - statement type
+ *    - operand type
+ *    - operand locality
+ *         operand global, local, parameter, or constant.                     
+ *
+ *  The combination of these three aspects is balanced only approximately.    
+ *
+ *  1. Statement Type:                                                        
+ *  -----------------             number
+ *
+ *     V1 = V2                     9
+ *       (incl. V1 = F(..)
+ *     V = Constant               12
+ *     Assignment,                 7
+ *       with array element
+ *     Assignment,                 6
+ *       with record component
+ *                                --
+ *                                34       34
+ *
+ *     X = Y +|-|"&&"|"|" Z        5
+ *     X = Y +|-|"==" Constant     6
+ *     X = X +|- 1                 3
+ *     X = Y *|/ Z                 2
+ *     X = Expression,             1
+ *           two operators
+ *     X = Expression,             1
+ *           three operators
+ *                                --
+ *                                18       18
+ *
+ *     if ....                    14
+ *       with "else"      7
+ *       without "else"   7
+ *           executed        3
+ *           not executed    4
+ *     for ...                     7  |  counted every time
+ *     while ...                   4  |  the loop condition
+ *     do ... while                1  |  is evaluated
+ *     switch ...                  1
+ *     break                       1
+ *     declaration with            1
+ *       initialization
+ *                                --
+ *                                34       34
+ *
+ *     P (...)  procedure call    11
+ *       user procedure      10
+ *       library procedure    1
+ *     X = F (...)
+ *             function  call      6
+ *       user function        5                                         
+ *       library function     1                                               
+ *                                --                                          
+ *                                17       17
+ *                                        ---
+ *                                        103
+ *
+ *    The average number of parameters in procedure or function calls
+ *    is 1.82 (not counting the function values aX *
+ *
+ *  2. Operators
+ *  ------------
+ *                          number    approximate
+ *                                    percentage
+ *
+ *    Arithmetic             32          50.8                                 
+ *
+ *       +                     21          33.3                              
+ *       -                      7          11.1                              
+ *       *                      3           4.8
+ *       / (int div)            1           1.6
+ *
+ *    Comparison             27           42.8
+ *
+ *       ==                     9           14.3
+ *       /=                     4            6.3
+ *       >                      1            1.6
+ *       <                      3            4.8
+ *       >=                     1            1.6
+ *       <=                     9           14.3
+ *
+ *    Logic                   4            6.3
+ *
+ *       && (AND-THEN)          1            1.6
+ *       |  (OR)                1            1.6
+ *       !  (NOT)               2            3.2
+ * 
+ *                           --          -----
+ *                           63          100.1
+ *
+ *
+ *  3. Operand Type (counted once per operand reference):
+ *  ---------------
+ *                          number    approximate
+ *                                    percentage
+ *
+ *     Integer               175        72.3 %
+ *     Character              45        18.6 %
+ *     Pointer                12         5.0 %
+ *     String30                6         2.5 %
+ *     Array                   2         0.8 %
+ *     Record                  2         0.8 %
+ *                           ---       -------
+ *                           242       100.0 %
+ *
+ *  When there is an access path leading to the final operand (e.g. a record
+ *  component), only the final data type on the access path is counted.       
+ *
+ *
+ *  4. Operand Locality:                                                      
+ *  -------------------
+ *                                number    approximate
+ *                                          percentage
+ *
+ *     local variable              114        47.1 %
+ *     global variable              22         9.1 %
+ *     parameter                    45        18.6 %
+ *        value                        23         9.5 %
+ *        reference                    22         9.1 %
+ *     function result               6         2.5 %
+ *     constant                     55        22.7 %
+ *                                 ---       -------
+ *                                 242       100.0 %
+ *
+ *  The program does not compute anything meaningful, but it is syntactically
+ *  and semantically correct. All variables have a value assigned to them
+ *  before they are used as a source operand.
+ *
+ *  There has been no explicit effort to account for the effects of a
+ *  cache, or to balance the use of long or short displacements for code or
+ *  data.
+ *
+ ***************************************************************************
+ */
+
+/* Compiler and system dependent definitions: */
+
+/* variables for time measurement: */
+
+#ifdef TIME
+
+#define CLOCK_TYPE "time()"
+#undef HZ
+#define HZ	(1) /* time() returns time in seconds */
+extern long     time(); /* see library function "time"  */
+#define Too_Small_Time 2 /* Measurements should last at least 2 seconds */
+#define Start_Timer() Begin_Time = time ( (long *) 0)
+#define Stop_Timer()  End_Time   = time ( (long *) 0)
+
+#else
+
+#ifdef MSC_CLOCK /* Use Microsoft C hi-res clock */
+
+#undef HZ
+#undef TIMES
+#include <time.h>
+#define HZ	CLK_TCK
+#define CLOCK_TYPE "MSC clock()"
+extern clock_t	clock();
+#define Too_Small_Time (2*HZ)
+#define Start_Timer() Begin_Time = clock()
+#define Stop_Timer()  End_Time   = clock()
+
+#elif defined(__riscv)
+
+#define HZ 1000000
+#define Too_Small_Time 1
+#define CLOCK_TYPE "rdcycle()"
+#define Start_Timer() Begin_Time = read_csr(mcycle)
+#define Stop_Timer() End_Time = read_csr(mcycle)
+
+#else
+                /* Use times(2) time function unless    */
+                /* explicitly defined otherwise         */
+#define CLOCK_TYPE "times()"
+#include <sys/types.h>
+#include <sys/times.h>
+#ifndef HZ	/* Added by SP 900619 */
+#include <sys/param.h> /* If your system doesn't have this, use -DHZ=xxx */
+#else
+	*** You must define HZ!!! ***
+#endif /* HZ */
+#ifndef PASS2
+struct tms      time_info;
+#endif
+/*extern  int     times ();*/
+                /* see library function "times" */
+#define Too_Small_Time (2*HZ)
+                /* Measurements should last at least about 2 seconds */
+#define Start_Timer() times(&time_info); Begin_Time=(long)time_info.tms_utime
+#define Stop_Timer()  times(&time_info); End_Time = (long)time_info.tms_utime
+
+#endif /* MSC_CLOCK */
+#endif /* TIME */
+
+
+#define Mic_secs_Per_Second     1000000
+#define NUMBER_OF_RUNS		500 /* Default number of runs */
+
+#ifdef  NOSTRUCTASSIGN
+#define structassign(d, s)      memcpy(&(d), &(s), sizeof(d))
+#else
+#define structassign(d, s)      d = s
+#endif
+
+#ifdef  NOENUM
+#define Ident_1 0
+#define Ident_2 1
+#define Ident_3 2
+#define Ident_4 3
+#define Ident_5 4
+  typedef int   Enumeration;
+#else
+  typedef       enum    {Ident_1, Ident_2, Ident_3, Ident_4, Ident_5}
+                Enumeration;
+#endif
+        /* for boolean and enumeration types in Ada, Pascal */
+
+/* General definitions: */
+
+#include <stdio.h>
+#include <string.h>
+                /* for strcpy, strcmp */
+
+#define Null 0 
+                /* Value of a Null pointer */
+#define true  1
+#define false 0
+
+typedef int     One_Thirty;
+typedef int     One_Fifty;
+typedef char    Capital_Letter;
+typedef int     Boolean;
+typedef char    Str_30 [31];
+typedef int     Arr_1_Dim [50];
+typedef int     Arr_2_Dim [50] [50];
+
+typedef struct record 
+    {
+    struct record *Ptr_Comp;
+    Enumeration    Discr;
+    union {
+          struct {
+                  Enumeration Enum_Comp;
+                  int         Int_Comp;
+                  char        Str_Comp [31];
+                  } var_1;
+          struct {
+                  Enumeration E_Comp_2;
+                  char        Str_2_Comp [31];
+                  } var_2;
+          struct {
+                  char        Ch_1_Comp;
+                  char        Ch_2_Comp;
+                  } var_3;
+          } variant;
+      } Rec_Type, *Rec_Pointer;
+
+#endif
diff --git a/apps/riscv-tests/benchmarks/dhrystone/dhrystone_main.c b/apps/riscv-tests/benchmarks/dhrystone/dhrystone_main.c
new file mode 100644
index 0000000..9c7bcf5
--- /dev/null
+++ b/apps/riscv-tests/benchmarks/dhrystone/dhrystone_main.c
@@ -0,0 +1,332 @@
+// See LICENSE for license details.
+
+//**************************************************************************
+// Dhrystone bencmark
+//--------------------------------------------------------------------------
+//
+// This is the classic Dhrystone synthetic integer benchmark.
+//
+
+#pragma GCC optimize ("no-inline")
+
+#include "dhrystone.h"
+
+void debug_printf(const char* str, ...);
+
+#include "util.h"
+
+#include <alloca.h>
+
+/* Global Variables: */
+
+Rec_Pointer     Ptr_Glob,
+                Next_Ptr_Glob;
+int             Int_Glob;
+Boolean         Bool_Glob;
+char            Ch_1_Glob,
+                Ch_2_Glob;
+int             Arr_1_Glob [50];
+int             Arr_2_Glob [50] [50];
+
+Enumeration     Func_1 ();
+  /* forward declaration necessary since Enumeration may not simply be int */
+
+#ifndef REG
+        Boolean Reg = false;
+#define REG
+        /* REG becomes defined as empty */
+        /* i.e. no register variables   */
+#else
+        Boolean Reg = true;
+#undef REG
+#define REG register
+#endif
+
+Boolean		Done;
+
+long            Begin_Time,
+                End_Time,
+                User_Time;
+long            Microseconds,
+                Dhrystones_Per_Second;
+
+/* end of variables for time measurement */
+
+
+int main (int argc, char** argv)
+/*****/
+  /* main program, corresponds to procedures        */
+  /* Main and Proc_0 in the Ada version             */
+{
+        One_Fifty       Int_1_Loc;
+  REG   One_Fifty       Int_2_Loc;
+        One_Fifty       Int_3_Loc;
+  REG   char            Ch_Index;
+        Enumeration     Enum_Loc;
+        Str_30          Str_1_Loc;
+        Str_30          Str_2_Loc;
+  REG   int             Run_Index;
+  REG   int             Number_Of_Runs;
+
+  /* Arguments */
+  Number_Of_Runs = NUMBER_OF_RUNS;
+
+  /* Initializations */
+
+  Next_Ptr_Glob = (Rec_Pointer) alloca (sizeof (Rec_Type));
+  Ptr_Glob = (Rec_Pointer) alloca (sizeof (Rec_Type));
+
+  Ptr_Glob->Ptr_Comp                    = Next_Ptr_Glob;
+  Ptr_Glob->Discr                       = Ident_1;
+  Ptr_Glob->variant.var_1.Enum_Comp     = Ident_3;
+  Ptr_Glob->variant.var_1.Int_Comp      = 40;
+  strcpy (Ptr_Glob->variant.var_1.Str_Comp, 
+          "DHRYSTONE PROGRAM, SOME STRING");
+  strcpy (Str_1_Loc, "DHRYSTONE PROGRAM, 1'ST STRING");
+
+  Arr_2_Glob [8][7] = 10;
+        /* Was missing in published program. Without this statement,    */
+        /* Arr_2_Glob [8][7] would have an undefined value.             */
+        /* Warning: With 16-Bit processors and Number_Of_Runs > 32000,  */
+        /* overflow may occur for this array element.                   */
+
+  debug_printf("\n");
+  debug_printf("Dhrystone Benchmark, Version %s\n", Version);
+  if (Reg)
+  {
+    debug_printf("Program compiled with 'register' attribute\n");
+  }
+  else
+  {
+    debug_printf("Program compiled without 'register' attribute\n");
+  }
+  debug_printf("Using %s, HZ=%d\n", CLOCK_TYPE, HZ);
+  debug_printf("\n");
+
+  Done = false;
+  while (!Done) {
+    debug_printf("Trying %d runs through Dhrystone:\n", Number_Of_Runs);
+
+    /***************/
+    /* Start timer */
+    /***************/
+
+    setStats(1);
+    Start_Timer();
+
+    for (Run_Index = 1; Run_Index <= Number_Of_Runs; ++Run_Index)
+    {
+
+      Proc_5();
+      Proc_4();
+	/* Ch_1_Glob == 'A', Ch_2_Glob == 'B', Bool_Glob == true */
+      Int_1_Loc = 2;
+      Int_2_Loc = 3;
+      strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 2'ND STRING");
+      Enum_Loc = Ident_2;
+      Bool_Glob = ! Func_2 (Str_1_Loc, Str_2_Loc);
+	/* Bool_Glob == 1 */
+      while (Int_1_Loc < Int_2_Loc)  /* loop body executed once */
+      {
+	Int_3_Loc = 5 * Int_1_Loc - Int_2_Loc;
+	  /* Int_3_Loc == 7 */
+	Proc_7 (Int_1_Loc, Int_2_Loc, &Int_3_Loc);
+	  /* Int_3_Loc == 7 */
+	Int_1_Loc += 1;
+      } /* while */
+	/* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */
+      Proc_8 (Arr_1_Glob, Arr_2_Glob, Int_1_Loc, Int_3_Loc);
+	/* Int_Glob == 5 */
+      Proc_1 (Ptr_Glob);
+      for (Ch_Index = 'A'; Ch_Index <= Ch_2_Glob; ++Ch_Index)
+			       /* loop body executed twice */
+      {
+	if (Enum_Loc == Func_1 (Ch_Index, 'C'))
+	    /* then, not executed */
+	  {
+	  Proc_6 (Ident_1, &Enum_Loc);
+	  strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 3'RD STRING");
+	  Int_2_Loc = Run_Index;
+	  Int_Glob = Run_Index;
+	  }
+      }
+	/* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */
+      Int_2_Loc = Int_2_Loc * Int_1_Loc;
+      Int_1_Loc = Int_2_Loc / Int_3_Loc;
+      Int_2_Loc = 7 * (Int_2_Loc - Int_3_Loc) - Int_1_Loc;
+	/* Int_1_Loc == 1, Int_2_Loc == 13, Int_3_Loc == 7 */
+      Proc_2 (&Int_1_Loc);
+	/* Int_1_Loc == 5 */
+
+    } /* loop "for Run_Index" */
+
+    /**************/
+    /* Stop timer */
+    /**************/
+
+    Stop_Timer();
+    setStats(0);
+
+    User_Time = End_Time - Begin_Time;
+
+    if (User_Time < Too_Small_Time)
+    {
+      printf("Measured time too small to obtain meaningful results\n");
+      Number_Of_Runs = Number_Of_Runs * 10;
+      printf("\n");
+    } else Done = true;
+  }
+
+  debug_printf("Final values of the variables used in the benchmark:\n");
+  debug_printf("\n");
+  debug_printf("Int_Glob:            %d\n", Int_Glob);
+  debug_printf("        should be:   %d\n", 5);
+  debug_printf("Bool_Glob:           %d\n", Bool_Glob);
+  debug_printf("        should be:   %d\n", 1);
+  debug_printf("Ch_1_Glob:           %c\n", Ch_1_Glob);
+  debug_printf("        should be:   %c\n", 'A');
+  debug_printf("Ch_2_Glob:           %c\n", Ch_2_Glob);
+  debug_printf("        should be:   %c\n", 'B');
+  debug_printf("Arr_1_Glob[8]:       %d\n", Arr_1_Glob[8]);
+  debug_printf("        should be:   %d\n", 7);
+  debug_printf("Arr_2_Glob[8][7]:    %d\n", Arr_2_Glob[8][7]);
+  debug_printf("        should be:   Number_Of_Runs + 10\n");
+  debug_printf("Ptr_Glob->\n");
+  debug_printf("  Ptr_Comp:          %d\n", (long) Ptr_Glob->Ptr_Comp);
+  debug_printf("        should be:   (implementation-dependent)\n");
+  debug_printf("  Discr:             %d\n", Ptr_Glob->Discr);
+  debug_printf("        should be:   %d\n", 0);
+  debug_printf("  Enum_Comp:         %d\n", Ptr_Glob->variant.var_1.Enum_Comp);
+  debug_printf("        should be:   %d\n", 2);
+  debug_printf("  Int_Comp:          %d\n", Ptr_Glob->variant.var_1.Int_Comp);
+  debug_printf("        should be:   %d\n", 17);
+  debug_printf("  Str_Comp:          %s\n", Ptr_Glob->variant.var_1.Str_Comp);
+  debug_printf("        should be:   DHRYSTONE PROGRAM, SOME STRING\n");
+  debug_printf("Next_Ptr_Glob->\n");
+  debug_printf("  Ptr_Comp:          %d\n", (long) Next_Ptr_Glob->Ptr_Comp);
+  debug_printf("        should be:   (implementation-dependent), same as above\n");
+  debug_printf("  Discr:             %d\n", Next_Ptr_Glob->Discr);
+  debug_printf("        should be:   %d\n", 0);
+  debug_printf("  Enum_Comp:         %d\n", Next_Ptr_Glob->variant.var_1.Enum_Comp);
+  debug_printf("        should be:   %d\n", 1);
+  debug_printf("  Int_Comp:          %d\n", Next_Ptr_Glob->variant.var_1.Int_Comp);
+  debug_printf("        should be:   %d\n", 18);
+  debug_printf("  Str_Comp:          %s\n",
+                                Next_Ptr_Glob->variant.var_1.Str_Comp);
+  debug_printf("        should be:   DHRYSTONE PROGRAM, SOME STRING\n");
+  debug_printf("Int_1_Loc:           %d\n", Int_1_Loc);
+  debug_printf("        should be:   %d\n", 5);
+  debug_printf("Int_2_Loc:           %d\n", Int_2_Loc);
+  debug_printf("        should be:   %d\n", 13);
+  debug_printf("Int_3_Loc:           %d\n", Int_3_Loc);
+  debug_printf("        should be:   %d\n", 7);
+  debug_printf("Enum_Loc:            %d\n", Enum_Loc);
+  debug_printf("        should be:   %d\n", 1);
+  debug_printf("Str_1_Loc:           %s\n", Str_1_Loc);
+  debug_printf("        should be:   DHRYSTONE PROGRAM, 1'ST STRING\n");
+  debug_printf("Str_2_Loc:           %s\n", Str_2_Loc);
+  debug_printf("        should be:   DHRYSTONE PROGRAM, 2'ND STRING\n");
+  debug_printf("\n");
+
+
+  Microseconds = ((User_Time / Number_Of_Runs) * Mic_secs_Per_Second) / HZ;
+  Dhrystones_Per_Second = (HZ * Number_Of_Runs) / User_Time;
+
+  printf("Microseconds for one run through Dhrystone: %ld\n", Microseconds);
+  printf("Dhrystones per Second:                      %ld\n", Dhrystones_Per_Second);
+
+  return 0;
+}
+
+
+Proc_1 (Ptr_Val_Par)
+/******************/
+
+REG Rec_Pointer Ptr_Val_Par;
+    /* executed once */
+{
+  REG Rec_Pointer Next_Record = Ptr_Val_Par->Ptr_Comp;  
+                                        /* == Ptr_Glob_Next */
+  /* Local variable, initialized with Ptr_Val_Par->Ptr_Comp,    */
+  /* corresponds to "rename" in Ada, "with" in Pascal           */
+  
+  structassign (*Ptr_Val_Par->Ptr_Comp, *Ptr_Glob); 
+  Ptr_Val_Par->variant.var_1.Int_Comp = 5;
+  Next_Record->variant.var_1.Int_Comp 
+        = Ptr_Val_Par->variant.var_1.Int_Comp;
+  Next_Record->Ptr_Comp = Ptr_Val_Par->Ptr_Comp;
+  Proc_3 (&Next_Record->Ptr_Comp);
+    /* Ptr_Val_Par->Ptr_Comp->Ptr_Comp 
+                        == Ptr_Glob->Ptr_Comp */
+  if (Next_Record->Discr == Ident_1)
+    /* then, executed */
+  {
+    Next_Record->variant.var_1.Int_Comp = 6;
+    Proc_6 (Ptr_Val_Par->variant.var_1.Enum_Comp, 
+           &Next_Record->variant.var_1.Enum_Comp);
+    Next_Record->Ptr_Comp = Ptr_Glob->Ptr_Comp;
+    Proc_7 (Next_Record->variant.var_1.Int_Comp, 10, 
+           &Next_Record->variant.var_1.Int_Comp);
+  }
+  else /* not executed */
+    structassign (*Ptr_Val_Par, *Ptr_Val_Par->Ptr_Comp);
+} /* Proc_1 */
+
+
+Proc_2 (Int_Par_Ref)
+/******************/
+    /* executed once */
+    /* *Int_Par_Ref == 1, becomes 4 */
+
+One_Fifty   *Int_Par_Ref;
+{
+  One_Fifty  Int_Loc;  
+  Enumeration   Enum_Loc;
+
+  Int_Loc = *Int_Par_Ref + 10;
+  do /* executed once */
+    if (Ch_1_Glob == 'A')
+      /* then, executed */
+    {
+      Int_Loc -= 1;
+      *Int_Par_Ref = Int_Loc - Int_Glob;
+      Enum_Loc = Ident_1;
+    } /* if */
+  while (Enum_Loc != Ident_1); /* true */
+} /* Proc_2 */
+
+
+Proc_3 (Ptr_Ref_Par)
+/******************/
+    /* executed once */
+    /* Ptr_Ref_Par becomes Ptr_Glob */
+
+Rec_Pointer *Ptr_Ref_Par;
+
+{
+  if (Ptr_Glob != Null)
+    /* then, executed */
+    *Ptr_Ref_Par = Ptr_Glob->Ptr_Comp;
+  Proc_7 (10, Int_Glob, &Ptr_Glob->variant.var_1.Int_Comp);
+} /* Proc_3 */
+
+
+Proc_4 () /* without parameters */
+/*******/
+    /* executed once */
+{
+  Boolean Bool_Loc;
+
+  Bool_Loc = Ch_1_Glob == 'A';
+  Bool_Glob = Bool_Loc | Bool_Glob;
+  Ch_2_Glob = 'B';
+} /* Proc_4 */
+
+
+Proc_5 () /* without parameters */
+/*******/
+    /* executed once */
+{
+  Ch_1_Glob = 'A';
+  Bool_Glob = false;
+} /* Proc_5 */
diff --git a/apps/riscv-tests/benchmarks/median/dataset1.h b/apps/riscv-tests/benchmarks/median/dataset1.h
new file mode 100644
index 0000000..b1e1491
--- /dev/null
+++ b/apps/riscv-tests/benchmarks/median/dataset1.h
@@ -0,0 +1,53 @@
+// See LICENSE for license details.
+
+
+#define DATA_SIZE 400
+
+int input_data[DATA_SIZE] =
+{
+   41, 454, 833, 335, 564,   1, 187, 989, 749, 365, 350, 572, 132,  64, 949, 153, 584, 216, 805, 140,
+  621, 210,   6, 572, 931, 339, 890, 593, 392, 898, 694, 228, 961,  12, 110, 883, 116, 750, 296, 646,
+  426, 500, 314, 436, 659, 701, 774, 812, 319, 981, 678, 150, 875, 696, 376, 564, 474, 272, 938, 258,
+  539, 647, 569, 509, 203,  88, 280, 703, 759, 669, 606, 375, 511, 551, 657, 936, 195, 592,  81, 569,
+  267, 952, 229, 800, 337, 584, 944, 643, 902, 368, 241, 489, 913, 328, 826, 313, 933, 592, 985, 388,
+  195, 543, 960, 649, 566, 979, 350, 997, 649, 814, 657,  79, 181, 208, 111, 998, 859, 629,  65, 847,
+  288, 704, 349, 997, 141, 253, 905, 715, 886, 430, 264, 415, 576, 538, 979, 700, 761,   4, 241, 494,
+  478, 100, 499, 864, 403, 693, 222, 416, 444, 296, 721, 285, 676, 620, 317,  78, 224, 351, 937, 540,
+  288, 646, 119, 169, 615, 527, 606, 289, 389, 796, 351, 801, 455, 720, 278, 758, 367, 745, 358,  92,
+  584, 989,  62, 271, 985, 853, 403, 788, 346, 531, 517, 222, 559, 461, 908, 241, 775, 358, 255, 332,
+  778, 684, 598, 740, 143, 446,  33, 311, 125, 743, 941, 557, 933, 479, 799, 557, 553, 925, 431, 796,
+  648, 357, 952, 891, 287, 666,  19, 514,  49, 557,  86, 870,  95, 853, 441, 440, 587,  61, 614, 678,
+  382, 396, 280,   9, 808,  17, 971, 170, 819, 291, 344, 380, 450, 536, 512, 185, 965, 917, 347, 539,
+  808, 983, 882, 887, 537,  54, 946, 612, 701, 951, 356, 479, 567, 151, 891,   7,  22, 641, 568, 335,
+  665, 730, 423,  95, 434, 728, 158, 280,   2, 395,  84, 688, 247, 911,  49, 476, 435, 815, 792, 729,
+  869, 265, 486, 127, 414, 236, 369, 214, 548, 180, 518,   6, 888, 503, 682, 596, 284, 173, 264, 643,
+  499, 346, 290, 599, 897,  68, 215, 849, 731, 658, 688, 619, 251, 121, 786, 131, 555, 828, 302, 667,
+  528, 433, 544, 487, 322, 753, 947, 125, 287, 626, 824,  14, 304,  10, 788, 403, 733, 106, 959, 703,
+  366, 818, 722, 964, 294, 406, 975, 874, 653, 856, 748,  86,  91,  60, 378, 660, 105, 667, 102, 153,
+  381, 121, 651,  98, 825, 412, 840, 236, 356,  12, 148, 423,  54, 965, 140, 216, 955, 621, 343, 361
+};
+
+int verify_data[DATA_SIZE] =
+{
+    0, 454, 454, 564, 335, 187, 187, 749, 749, 365, 365, 350, 132, 132, 153, 584, 216, 584, 216, 621,
+  210, 210, 210, 572, 572, 890, 593, 593, 593, 694, 694, 694, 228, 110, 110, 116, 750, 296, 646, 426,
+  500, 426, 436, 436, 659, 701, 774, 774, 812, 678, 678, 678, 696, 696, 564, 474, 474, 474, 272, 539,
+  539, 569, 569, 509, 203, 203, 280, 703, 703, 669, 606, 511, 511, 551, 657, 657, 592, 195, 569, 267,
+  569, 267, 800, 337, 584, 584, 643, 902, 643, 368, 368, 489, 489, 826, 328, 826, 592, 933, 592, 388,
+  388, 543, 649, 649, 649, 566, 979, 649, 814, 657, 657, 181, 181, 181, 208, 859, 859, 629, 629, 288,
+  704, 349, 704, 349, 253, 253, 715, 886, 715, 430, 415, 415, 538, 576, 700, 761, 700, 241, 241, 478,
+  478, 478, 499, 499, 693, 403, 416, 416, 416, 444, 296, 676, 620, 620, 317, 224, 224, 351, 540, 540,
+  540, 288, 169, 169, 527, 606, 527, 389, 389, 389, 796, 455, 720, 455, 720, 367, 745, 367, 358, 358,
+  584, 584, 271, 271, 853, 853, 788, 403, 531, 517, 517, 517, 461, 559, 461, 775, 358, 358, 332, 332,
+  684, 684, 684, 598, 446, 143, 311, 125, 311, 743, 743, 933, 557, 799, 557, 557, 557, 553, 796, 648,
+  648, 648, 891, 891, 666, 287, 514,  49, 514,  86, 557,  95, 853, 441, 441, 441, 440, 587, 614, 614,
+  396, 382, 280, 280,  17, 808, 170, 819, 291, 344, 344, 380, 450, 512, 512, 512, 917, 917, 539, 539,
+  808, 882, 887, 882, 537, 537, 612, 701, 701, 701, 479, 479, 479, 567, 151,  22,  22, 568, 568, 568,
+  665, 665, 423, 423, 434, 434, 280, 158, 280,  84, 395, 247, 688, 247, 476, 435, 476, 792, 792, 792,
+  729, 486, 265, 414, 236, 369, 236, 369, 214, 518, 180, 518, 503, 682, 596, 596, 284, 264, 264, 499,
+  499, 346, 346, 599, 599, 215, 215, 731, 731, 688, 658, 619, 251, 251, 131, 555, 555, 555, 667, 528,
+  528, 528, 487, 487, 487, 753, 753, 287, 287, 626, 626, 304,  14, 304, 403, 733, 403, 733, 703, 703,
+  703, 722, 818, 722, 406, 406, 874, 874, 856, 748, 748,  91,  86,  91, 378, 378, 660, 105, 153, 153,
+  153, 381, 121, 651, 412, 825, 412, 356, 236, 148, 148, 148, 423, 140, 216, 216, 621, 621, 361,   0
+};
+
diff --git a/apps/riscv-tests/benchmarks/median/median.c b/apps/riscv-tests/benchmarks/median/median.c
new file mode 100644
index 0000000..1999185
--- /dev/null
+++ b/apps/riscv-tests/benchmarks/median/median.c
@@ -0,0 +1,42 @@
+// See LICENSE for license details.
+
+//**************************************************************************
+// Median filter (c version)
+//--------------------------------------------------------------------------
+
+void median( int n, int input[], int results[] )
+{
+  int A, B, C, i;
+
+  // Zero the ends
+  results[0]   = 0;
+  results[n-1] = 0;
+
+  // Do the filter
+  for ( i = 1; i < (n-1); i++ ) {
+
+    A = input[i-1];
+    B = input[i];
+    C = input[i+1];
+
+    if ( A < B ) {
+      if ( B < C )
+        results[i] = B;
+      else if ( C < A )
+        results[i] = A;
+      else
+        results[i] = C;
+    }
+
+    else {
+      if ( A < C )
+        results[i] = A;
+      else if ( C < B )
+        results[i] = B;
+      else
+        results[i] = C;
+    }
+
+  }
+
+}
diff --git a/apps/riscv-tests/benchmarks/median/median.h b/apps/riscv-tests/benchmarks/median/median.h
new file mode 100644
index 0000000..7f9791c
--- /dev/null
+++ b/apps/riscv-tests/benchmarks/median/median.h
@@ -0,0 +1,11 @@
+// See LICENSE for license details.
+
+//**************************************************************************
+// Median filters
+//--------------------------------------------------------------------------
+
+// Simple C version
+void median( int n, int input[], int results[] );
+
+// Simple assembly version
+void median_asm( int n, int input[], int results[] );
diff --git a/apps/riscv-tests/benchmarks/median/median_gendata.pl b/apps/riscv-tests/benchmarks/median/median_gendata.pl
new file mode 100755
index 0000000..373904e
--- /dev/null
+++ b/apps/riscv-tests/benchmarks/median/median_gendata.pl
@@ -0,0 +1,140 @@
+#!/usr/bin/perl -w
+#==========================================================================
+# median_gendata.pl
+#
+# Author : Christopher Batten (cbatten@mit.edu)
+# Date   : May 9, 2005
+#
+(our $usageMsg = <<'ENDMSG') =~ s/^\#//gm;
+#
+# Simple script which creates an input data set and the reference data
+# for the median benchmark.
+#
+ENDMSG
+
+use strict "vars";
+use warnings;
+no  warnings("once");
+use Getopt::Long;
+
+#--------------------------------------------------------------------------
+# Command line processing
+#--------------------------------------------------------------------------
+
+our %opts;
+
+sub usage()
+{
+
+  print "\n";
+  print " Usage: median_gendata.pl [options] \n";
+  print "\n";
+  print " Options:\n";
+  print "  --help  print this message\n";
+  print "  --size  size of input data [750]\n";
+  print "  --seed  random seed [1]\n";
+  print "$usageMsg";
+
+  exit();
+}
+
+sub processCommandLine()
+{
+
+  $opts{"help"} = 0;
+  $opts{"size"} = 750;
+  $opts{"seed"} = 1;
+  Getopt::Long::GetOptions( \%opts, 'help|?', 'size:i', 'seed:i' ) or usage();
+  $opts{"help"} and usage();
+
+}
+
+#--------------------------------------------------------------------------
+# Helper Functions
+#--------------------------------------------------------------------------
+
+sub printArray
+{
+  my $arrayName = $_[0];
+  my $arrayRef  = $_[1];
+
+  my $numCols = 20;
+  my $arrayLen = scalar(@{$arrayRef});
+
+  print "int ".$arrayName."[DATA_SIZE] = \n";
+  print "{\n";
+
+  if ( $arrayLen <= $numCols ) {
+    print "  ";
+    for ( my $i = 0; $i < $arrayLen; $i++ ) {
+      print sprintf("%3d",$arrayRef->[$i]);
+      if ( $i != $arrayLen-1 ) {
+        print ", ";
+      }
+    }
+    print "\n";
+  }
+
+  else {
+    my $numRows = int($arrayLen/$numCols);
+    for ( my $j = 0; $j < $numRows; $j++ ) {
+      print "  ";
+      for ( my $i = 0; $i < $numCols; $i++ ) {
+        my $index = $j*$numCols + $i;
+        print sprintf("%3d",$arrayRef->[$index]);
+        if ( $index != $arrayLen-1 ) {
+          print ", ";
+        }
+      }
+      print "\n";
+    }
+
+    if ( $arrayLen > ($numRows*$numCols) ) {
+      print "  ";
+      for ( my $i = 0; $i < ($arrayLen-($numRows*$numCols)); $i++ ) {
+        my $index = $numCols*$numRows + $i;
+        print sprintf("%3d",$arrayRef->[$index]);
+        if ( $index != $arrayLen-1 ) {
+          print ", ";
+        }
+      }
+      print "\n";
+    }
+
+  }
+
+  print  "};\n\n";
+}
+
+#--------------------------------------------------------------------------
+# Main
+#--------------------------------------------------------------------------
+
+sub main()
+{
+
+  processCommandLine();
+  srand($opts{"seed"});
+
+  my @values;
+  for ( my $i = 0; $i < $opts{"size"}; $i++ ) {
+    push( @values, int(rand(999)) );
+  }
+
+  my @median;
+  $median[0] = 0;
+  $median[$opts{"size"}-1] = 0;
+  for ( my $i = 1; $i < $opts{"size"}-1; $i++ ) {
+    my @tempList = ( $values[$i-1], $values[$i], $values[$i+1] );
+    my @sorted = sort { $a <=> $b } @tempList;
+    $median[$i] = $sorted[1];
+  }
+
+  print "\n\#define DATA_SIZE ".$opts{"size"}." \n\n";
+  printArray( "input_data", \@values );
+  printArray( "verify_data", \@median );
+
+}
+
+main();
+
diff --git a/apps/riscv-tests/benchmarks/median/median_main.c b/apps/riscv-tests/benchmarks/median/median_main.c
new file mode 100644
index 0000000..b62ecd1
--- /dev/null
+++ b/apps/riscv-tests/benchmarks/median/median_main.c
@@ -0,0 +1,40 @@
+// See LICENSE for license details.
+
+//**************************************************************************
+// Median filter bencmark
+//--------------------------------------------------------------------------
+//
+// This benchmark performs a 1D three element median filter. The
+// input data (and reference data) should be generated using the
+// median_gendata.pl perl script and dumped to a file named
+// dataset1.h.
+
+#include "util.h"
+
+#include "median.h"
+
+//--------------------------------------------------------------------------
+// Input/Reference Data
+
+#include "dataset1.h"
+
+//--------------------------------------------------------------------------
+// Main
+
+int main( int argc, char* argv[] )
+{
+  int results_data[DATA_SIZE];
+
+#if PREALLOCATE
+  // If needed we preallocate everything in the caches
+  median( DATA_SIZE, input_data, results_data );
+#endif
+
+  // Do the filter
+  setStats(1);
+  median( DATA_SIZE, input_data, results_data );
+  setStats(0);
+
+  // Check the results
+  return verify( DATA_SIZE, results_data, verify_data );
+}
diff --git a/apps/riscv-tests/benchmarks/mm/common.h b/apps/riscv-tests/benchmarks/mm/common.h
new file mode 100644
index 0000000..01b9f3f
--- /dev/null
+++ b/apps/riscv-tests/benchmarks/mm/common.h
@@ -0,0 +1,36 @@
+// See LICENSE for license details.
+
+#ifndef _MM_H
+#define _MM_H
+
+#include <string.h>
+#include <stdint.h>
+#include <math.h>
+
+#ifdef SP
+typedef float t;
+#define fma fmaf
+#else
+typedef double t;
+#endif
+
+#define inline inline __attribute__((always_inline))
+
+#define alloca_aligned(s, a) ((void*)(((uintptr_t)alloca((s)+(a)-1)+(a)-1)&~((a)-1)))
+
+#include "rb.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void mm(size_t m, size_t n, size_t p,
+        t* a, size_t lda, t* b, size_t ldb, t* c, size_t ldc);
+
+#ifdef __cplusplus
+}
+#endif
+
+//void rb(t* a, t* b, t* c, size_t lda, size_t ldb, size_t ldc);
+
+#endif
diff --git a/apps/riscv-tests/benchmarks/mm/gen.scala b/apps/riscv-tests/benchmarks/mm/gen.scala
new file mode 100644
index 0000000..982daa8
--- /dev/null
+++ b/apps/riscv-tests/benchmarks/mm/gen.scala
@@ -0,0 +1,81 @@
+import scala.sys.process._
+object MMGen {
+  implicit def i2s(i: Int) = i.toString
+  def writeFile(name: String, contents: String) = {
+    val f = new java.io.FileWriter(name)
+    f.write(contents)
+    f.close
+  }
+
+  var indent = 0
+  def spacing = "  " * indent
+  def assign(lhs: String, rhs: String) =
+    spacing + lhs + " = " + rhs + ";\n"
+  def init(t: String, n: String, v: String) =
+    assign(t+" "+n, v)
+  def open_block(s: String = "") = {
+    val result = (if (s != "") spacing + s else "") + spacing + "{\n"
+    indent = indent + 1
+    result
+  }
+  def close_block = {
+    indent = indent - 1
+    spacing + "}\n"
+  }
+
+  def ar(m: String, i: String) = m+"["+i+"]"
+  def r(a: String, b: String*) = (a :: b.toList).reduceLeft(_+"_"+_)
+
+  def rb(m: Int, n: Int, p: Int) = {
+    var s = open_block("static inline void kloop(size_t p, t* a0, size_t lda, t* b0, size_t ldb, t* c, size_t ldc)\n")
+
+    for (i <- 0 until m)
+      s += init("t*", r("c", i), "&"+ar("c", "ldc*"+i))
+    for (i <- 0 until m; j <- 0 until n)
+      s += init("t", r("c", i, j), ar(r("c", i), j))
+
+    def doit(m: Int, n: Int, p: Int) = {
+      for (i <- 0 until m)
+        s += init("t*", r("a", i), "&"+ar("a", "lda*"+i))
+      for (k <- 0 until p)
+        s += init("t*", r("b", k), "&"+ar("b", "ldb*"+k))
+      for (k <- 0 until p; i <- 0 until m; j <- 0 until n)
+        s += assign(r("c", i, j), "fma(" + ar(r("a", i), k) + ", " + ar(r("b", k), j) + ", " + r("c", i, j) + ")")
+    }
+
+    s += open_block("for (t *a = a0, *b = b0; a < a0 + p/RBK*RBK; a += RBK, b += RBK*ldb)\n")
+    doit(m, n, p)
+    s += close_block
+
+    s += open_block("for (t *a = a0 + p/RBK*RBK, *b = b0 + p/RBK*RBK*ldb; a < a0 + p; a++, b += ldb)\n")
+    doit(m, n, 1)
+    s += close_block
+
+    for (i <- 0 until m; j <- 0 until n)
+      s += assign(ar(r("c", i), j), r("c", i, j))
+    s += close_block
+
+    s
+  }
+  def gcd(a: Int, b: Int): Int = if (b == 0) a else gcd(b, a%b)
+  def lcm(a: Int, b: Int): Int = a*b/gcd(a, b)
+  def lcm(a: Seq[Int]): Int = {
+    if (a.tail.isEmpty) a.head
+    else lcm(a.head, lcm(a.tail))
+  }
+  def test1(m: Int, n: Int, p: Int, m1: Int, n1: Int, p1: Int) = {
+    val decl = "static const int RBM = "+m+", RBN = "+n+", RBK = "+p+";\n" +
+               "static const int CBM = "+m1+", CBN = "+n1+", CBK = "+p1+";\n"
+    writeFile("rb.h", decl + rb(m, n, p))
+    //"make"!!
+
+    "make run"!
+
+    ("cp a.out " + Seq("b", m, n, p, m1, n1, p1, "run").reduce(_+"."+_))!
+  }
+  def main(args: Array[String]): Unit = {
+    test1(4, 5, 6, 24, 25, 24)
+    //for (i <- 4 to 6; j <- 4 to 6; k <- 4 to 6)
+    //  test1(i, j, k, if (i == 5) 35 else 36, if (j == 5) 35 else 36, if (k == 5) 35 else 36)
+  }
+}
diff --git a/apps/riscv-tests/benchmarks/mm/mm.c b/apps/riscv-tests/benchmarks/mm/mm.c
new file mode 100644
index 0000000..e5edd8a
--- /dev/null
+++ b/apps/riscv-tests/benchmarks/mm/mm.c
@@ -0,0 +1,152 @@
+// See LICENSE for license details.
+
+#include "common.h"
+#include <assert.h>
+#include <math.h>
+#include <stdint.h>
+#include <alloca.h>
+
+#define MIN(a, b) ((a) < (b) ? (a) : (b))
+
+static void mm_naive(size_t m, size_t n, size_t p,
+                            t* a, size_t lda, t* b, size_t ldb, t* c, size_t ldc)
+{
+  for (size_t i = 0; i < m; i++)
+  {
+    for (size_t j = 0; j < n; j++)
+    {
+      t s0 = c[i*ldc+j], s1 = 0, s2 = 0, s3 = 0;
+      for (size_t k = 0; k < p/4*4; k+=4)
+      {
+        s0 = fma(a[i*lda+k+0], b[(k+0)*ldb+j], s0);
+        s1 = fma(a[i*lda+k+1], b[(k+1)*ldb+j], s1);
+        s2 = fma(a[i*lda+k+2], b[(k+2)*ldb+j], s2);
+        s3 = fma(a[i*lda+k+3], b[(k+3)*ldb+j], s3);
+      }
+      for (size_t k = p/4*4; k < p; k++)
+        s0 = fma(a[i*lda+k], b[k*ldb+j], s0);
+      c[i*ldc+j] = (s0 + s1) + (s2 + s3);
+    }
+  }
+}
+
+static inline void mm_rb(size_t m, size_t n, size_t p,
+                         t* a, size_t lda, t* b, size_t ldb, t* c, size_t ldc)
+{
+  size_t mb = m/RBM*RBM, nb = n/RBN*RBN;
+  for (size_t i = 0; i < mb; i += RBM)
+  {
+    for (size_t j = 0; j < nb; j += RBN)
+      kloop(p, a+i*lda, lda, b+j, ldb, c+i*ldc+j, ldc);
+    mm_naive(RBM, n - nb, p, a+i*lda, lda, b+nb, ldb, c+i*ldc+nb, ldc);
+  }
+  mm_naive(m - mb, n, p, a+mb*lda, lda, b, ldb, c+mb*ldc, ldc);
+}
+
+static inline void repack(t* a, size_t lda, const t* a0, size_t lda0, size_t m, size_t p)
+{
+  for (size_t i = 0; i < m; i++)
+  {
+    for (size_t j = 0; j < p/8*8; j+=8)
+    {
+      t t0 = a0[i*lda0+j+0];
+      t t1 = a0[i*lda0+j+1];
+      t t2 = a0[i*lda0+j+2];
+      t t3 = a0[i*lda0+j+3];
+      t t4 = a0[i*lda0+j+4];
+      t t5 = a0[i*lda0+j+5];
+      t t6 = a0[i*lda0+j+6];
+      t t7 = a0[i*lda0+j+7];
+      a[i*lda+j+0] = t0;
+      a[i*lda+j+1] = t1;
+      a[i*lda+j+2] = t2;
+      a[i*lda+j+3] = t3;
+      a[i*lda+j+4] = t4;
+      a[i*lda+j+5] = t5;
+      a[i*lda+j+6] = t6;
+      a[i*lda+j+7] = t7;
+    }
+    for (size_t j = p/8*8; j < p; j++)
+      a[i*lda+j] = a0[i*lda0+j];
+  }
+}
+
+static void mm_cb(size_t m, size_t n, size_t p,
+                  t* a, size_t lda, t* b, size_t ldb, t* c, size_t ldc)
+{
+  size_t nmb = m/CBM, nnb = n/CBN, npb = p/CBK;
+  size_t mb = nmb*CBM, nb = nnb*CBN, pb = npb*CBK;
+  //t a1[mb*pb], b1[pb*nb], c1[mb*nb];
+  t* a1 = (t*)alloca_aligned(sizeof(t)*mb*pb, 8192);
+  t* b1 = (t*)alloca_aligned(sizeof(t)*pb*nb, 8192);
+  t* c1 = (t*)alloca_aligned(sizeof(t)*mb*nb, 8192);
+
+    for (size_t i = 0; i < mb; i += CBM)
+      for (size_t j = 0; j < pb; j += CBK)
+        repack(a1 + (npb*(i/CBM) + j/CBK)*(CBM*CBK), CBK, a + i*lda + j, lda, CBM, CBK);
+
+  for (size_t i = 0; i < pb; i += CBK)
+    for (size_t j = 0; j < nb; j += CBN)
+      repack(b1 + (nnb*(i/CBK) + j/CBN)*(CBK*CBN), CBN, b + i*ldb + j, ldb, CBK, CBN);
+
+    for (size_t i = 0; i < mb; i += CBM)
+      for (size_t j = 0; j < nb; j += CBN)
+        repack(c1 + (nnb*(i/CBM) + j/CBN)*(CBM*CBN), CBN, c + i*ldc + j, ldc, CBM, CBN);
+
+  for (size_t i = 0; i < mb; i += CBM)
+  {
+    for (size_t j = 0; j < nb; j += CBN)
+    {
+      for (size_t k = 0; k < pb; k += CBK)
+      {
+        mm_rb(CBM, CBN, CBK,
+              a1 + (npb*(i/CBM) + k/CBK)*(CBM*CBK), CBK,
+              b1 + (nnb*(k/CBK) + j/CBN)*(CBK*CBN), CBN,
+              c1 + (nnb*(i/CBM) + j/CBN)*(CBM*CBN), CBN);
+      }
+      if (pb < p)
+      {
+        mm_rb(CBM, CBN, p - pb,
+              a + i*lda + pb, lda,
+              b + pb*ldb + j, ldb,
+              c1 + (nnb*(i/CBM) + j/CBN)*(CBM*CBN), CBN);
+      }
+    }
+    if (nb < n)
+    {
+      for (size_t k = 0; k < p; k += CBK)
+      {
+        mm_rb(CBM, n - nb, MIN(p - k, CBK),
+              a + i*lda + k, lda,
+              b + k*ldb + nb, ldb,
+              c + i*ldc + nb, ldc);
+      }
+    }
+  }
+  if (mb < m)
+  {
+    for (size_t j = 0; j < n; j += CBN)
+    {
+      for (size_t k = 0; k < p; k += CBK)
+      {
+        mm_rb(m - mb, MIN(n - j, CBN), MIN(p - k, CBK),
+              a + mb*lda + k, lda,
+              b + k*ldb + j, ldb,
+              c + mb*ldc + j, ldc);
+      }
+    }
+  }
+
+    for (size_t i = 0; i < mb; i += CBM)
+      for (size_t j = 0; j < nb; j += CBN)
+        repack(c + i*ldc + j, ldc, c1 + (nnb*(i/CBM) + j/CBN)*(CBM*CBN), CBN, CBM, CBN);
+}
+
+void mm(size_t m, size_t n, size_t p,
+        t* a, size_t lda, t* b, size_t ldb, t* c, size_t ldc)
+{
+  if (__builtin_expect(m <= 2*CBM && n <= 2*CBN && p <= 2*CBK, 1))
+    mm_rb(m, n, p, a, lda, b, ldb, c, ldc);
+  else
+    mm_cb(m, n, p, a, lda, b, ldb, c, ldc);
+}
diff --git a/apps/riscv-tests/benchmarks/mm/mm_main.c b/apps/riscv-tests/benchmarks/mm/mm_main.c
new file mode 100644
index 0000000..133b5a2
--- /dev/null
+++ b/apps/riscv-tests/benchmarks/mm/mm_main.c
@@ -0,0 +1,72 @@
+// See LICENSE for license details.
+
+#include "common.h"
+#include <assert.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include "util.h"
+
+#pragma GCC optimize ("unroll-loops")
+
+void thread_entry(int cid, int nc)
+{
+  const int R = 8;
+  int m, n, p;
+  uint64_t s = 0xdeadbeefU;
+  
+  m = CBM;
+  n = CBN;
+  p = CBK;
+
+  t a[m*p];
+  t b[p*n];
+  t c[m*n];
+
+  for (size_t i = 0; i < m; i++)
+    for (size_t j = 0; j < p; j++)
+      a[i*p+j] = (t)(s = lfsr(s));
+  for (size_t i = 0; i < p; i++)
+    for (size_t j = 0; j < n; j++)
+      b[i*n+j] = (t)(s = lfsr(s));
+  memset(c, 0, m*n*sizeof(c[0]));
+
+  size_t instret, cycles;
+  for (int i = 0; i < R; i++)
+  {
+    instret = -read_csr(minstret);
+    cycles = -read_csr(mcycle);
+    mm(m, n, p, a, p, b, n, c, n);
+    instret += read_csr(minstret);
+    cycles += read_csr(mcycle);
+  }
+
+  asm volatile("fence");
+
+  printf("C%d: reg block %dx%dx%d, cache block %dx%dx%d\n",
+         cid, RBM, RBN, RBK, CBM, CBN, CBK);
+  printf("C%d: %d instructions\n", cid, (int)(instret));
+  printf("C%d: %d cycles\n", cid, (int)(cycles));
+  printf("C%d: %d flops\n", cid, 2*m*n*p);
+  printf("C%d: %d Mflops @ 1 GHz\n", cid, 2000*m*n*p/(cycles));
+
+#if 1
+  for (size_t i = 0; i < m; i++)
+  {
+    for (size_t j = 0; j < n; j++)
+    {
+      t s = 0;
+      for (size_t k = 0; k < p; k++)
+        s += a[i*p+k] * b[k*n+j];
+      s *= R;
+      if (fabs(c[i*n+j]-s) > fabs(1e-6*s))
+      {
+        printf("C%d: c[%lu][%lu] %f != %f\n", cid, i, j, c[i*n+j], s);
+        exit(1);
+      }
+    }
+  }
+#endif
+
+  barrier(nc);
+  exit(0);
+}
diff --git a/apps/riscv-tests/benchmarks/mm/rb.h b/apps/riscv-tests/benchmarks/mm/rb.h
new file mode 100644
index 0000000..421c964
--- /dev/null
+++ b/apps/riscv-tests/benchmarks/mm/rb.h
@@ -0,0 +1,210 @@
+static const int RBM = 4, RBN = 5, RBK = 6;
+static const int CBM = 24, CBN = 25, CBK = 24;
+static inline void kloop(size_t p, t* a0, size_t lda, t* b0, size_t ldb, t* c, size_t ldc)
+{
+  t* c_0 = &c[ldc*0];
+  t* c_1 = &c[ldc*1];
+  t* c_2 = &c[ldc*2];
+  t* c_3 = &c[ldc*3];
+  t c_0_0 = c_0[0];
+  t c_0_1 = c_0[1];
+  t c_0_2 = c_0[2];
+  t c_0_3 = c_0[3];
+  t c_0_4 = c_0[4];
+  t c_1_0 = c_1[0];
+  t c_1_1 = c_1[1];
+  t c_1_2 = c_1[2];
+  t c_1_3 = c_1[3];
+  t c_1_4 = c_1[4];
+  t c_2_0 = c_2[0];
+  t c_2_1 = c_2[1];
+  t c_2_2 = c_2[2];
+  t c_2_3 = c_2[3];
+  t c_2_4 = c_2[4];
+  t c_3_0 = c_3[0];
+  t c_3_1 = c_3[1];
+  t c_3_2 = c_3[2];
+  t c_3_3 = c_3[3];
+  t c_3_4 = c_3[4];
+  for (t *a = a0, *b = b0; a < a0 + p/RBK*RBK; a += RBK, b += RBK*ldb)
+  {
+    t* a_0 = &a[lda*0];
+    t* a_1 = &a[lda*1];
+    t* a_2 = &a[lda*2];
+    t* a_3 = &a[lda*3];
+    t* b_0 = &b[ldb*0];
+    t* b_1 = &b[ldb*1];
+    t* b_2 = &b[ldb*2];
+    t* b_3 = &b[ldb*3];
+    t* b_4 = &b[ldb*4];
+    t* b_5 = &b[ldb*5];
+    c_0_0 = fma(a_0[0], b_0[0], c_0_0);
+    c_0_1 = fma(a_0[0], b_0[1], c_0_1);
+    c_0_2 = fma(a_0[0], b_0[2], c_0_2);
+    c_0_3 = fma(a_0[0], b_0[3], c_0_3);
+    c_0_4 = fma(a_0[0], b_0[4], c_0_4);
+    c_1_0 = fma(a_1[0], b_0[0], c_1_0);
+    c_1_1 = fma(a_1[0], b_0[1], c_1_1);
+    c_1_2 = fma(a_1[0], b_0[2], c_1_2);
+    c_1_3 = fma(a_1[0], b_0[3], c_1_3);
+    c_1_4 = fma(a_1[0], b_0[4], c_1_4);
+    c_2_0 = fma(a_2[0], b_0[0], c_2_0);
+    c_2_1 = fma(a_2[0], b_0[1], c_2_1);
+    c_2_2 = fma(a_2[0], b_0[2], c_2_2);
+    c_2_3 = fma(a_2[0], b_0[3], c_2_3);
+    c_2_4 = fma(a_2[0], b_0[4], c_2_4);
+    c_3_0 = fma(a_3[0], b_0[0], c_3_0);
+    c_3_1 = fma(a_3[0], b_0[1], c_3_1);
+    c_3_2 = fma(a_3[0], b_0[2], c_3_2);
+    c_3_3 = fma(a_3[0], b_0[3], c_3_3);
+    c_3_4 = fma(a_3[0], b_0[4], c_3_4);
+    c_0_0 = fma(a_0[1], b_1[0], c_0_0);
+    c_0_1 = fma(a_0[1], b_1[1], c_0_1);
+    c_0_2 = fma(a_0[1], b_1[2], c_0_2);
+    c_0_3 = fma(a_0[1], b_1[3], c_0_3);
+    c_0_4 = fma(a_0[1], b_1[4], c_0_4);
+    c_1_0 = fma(a_1[1], b_1[0], c_1_0);
+    c_1_1 = fma(a_1[1], b_1[1], c_1_1);
+    c_1_2 = fma(a_1[1], b_1[2], c_1_2);
+    c_1_3 = fma(a_1[1], b_1[3], c_1_3);
+    c_1_4 = fma(a_1[1], b_1[4], c_1_4);
+    c_2_0 = fma(a_2[1], b_1[0], c_2_0);
+    c_2_1 = fma(a_2[1], b_1[1], c_2_1);
+    c_2_2 = fma(a_2[1], b_1[2], c_2_2);
+    c_2_3 = fma(a_2[1], b_1[3], c_2_3);
+    c_2_4 = fma(a_2[1], b_1[4], c_2_4);
+    c_3_0 = fma(a_3[1], b_1[0], c_3_0);
+    c_3_1 = fma(a_3[1], b_1[1], c_3_1);
+    c_3_2 = fma(a_3[1], b_1[2], c_3_2);
+    c_3_3 = fma(a_3[1], b_1[3], c_3_3);
+    c_3_4 = fma(a_3[1], b_1[4], c_3_4);
+    c_0_0 = fma(a_0[2], b_2[0], c_0_0);
+    c_0_1 = fma(a_0[2], b_2[1], c_0_1);
+    c_0_2 = fma(a_0[2], b_2[2], c_0_2);
+    c_0_3 = fma(a_0[2], b_2[3], c_0_3);
+    c_0_4 = fma(a_0[2], b_2[4], c_0_4);
+    c_1_0 = fma(a_1[2], b_2[0], c_1_0);
+    c_1_1 = fma(a_1[2], b_2[1], c_1_1);
+    c_1_2 = fma(a_1[2], b_2[2], c_1_2);
+    c_1_3 = fma(a_1[2], b_2[3], c_1_3);
+    c_1_4 = fma(a_1[2], b_2[4], c_1_4);
+    c_2_0 = fma(a_2[2], b_2[0], c_2_0);
+    c_2_1 = fma(a_2[2], b_2[1], c_2_1);
+    c_2_2 = fma(a_2[2], b_2[2], c_2_2);
+    c_2_3 = fma(a_2[2], b_2[3], c_2_3);
+    c_2_4 = fma(a_2[2], b_2[4], c_2_4);
+    c_3_0 = fma(a_3[2], b_2[0], c_3_0);
+    c_3_1 = fma(a_3[2], b_2[1], c_3_1);
+    c_3_2 = fma(a_3[2], b_2[2], c_3_2);
+    c_3_3 = fma(a_3[2], b_2[3], c_3_3);
+    c_3_4 = fma(a_3[2], b_2[4], c_3_4);
+    c_0_0 = fma(a_0[3], b_3[0], c_0_0);
+    c_0_1 = fma(a_0[3], b_3[1], c_0_1);
+    c_0_2 = fma(a_0[3], b_3[2], c_0_2);
+    c_0_3 = fma(a_0[3], b_3[3], c_0_3);
+    c_0_4 = fma(a_0[3], b_3[4], c_0_4);
+    c_1_0 = fma(a_1[3], b_3[0], c_1_0);
+    c_1_1 = fma(a_1[3], b_3[1], c_1_1);
+    c_1_2 = fma(a_1[3], b_3[2], c_1_2);
+    c_1_3 = fma(a_1[3], b_3[3], c_1_3);
+    c_1_4 = fma(a_1[3], b_3[4], c_1_4);
+    c_2_0 = fma(a_2[3], b_3[0], c_2_0);
+    c_2_1 = fma(a_2[3], b_3[1], c_2_1);
+    c_2_2 = fma(a_2[3], b_3[2], c_2_2);
+    c_2_3 = fma(a_2[3], b_3[3], c_2_3);
+    c_2_4 = fma(a_2[3], b_3[4], c_2_4);
+    c_3_0 = fma(a_3[3], b_3[0], c_3_0);
+    c_3_1 = fma(a_3[3], b_3[1], c_3_1);
+    c_3_2 = fma(a_3[3], b_3[2], c_3_2);
+    c_3_3 = fma(a_3[3], b_3[3], c_3_3);
+    c_3_4 = fma(a_3[3], b_3[4], c_3_4);
+    c_0_0 = fma(a_0[4], b_4[0], c_0_0);
+    c_0_1 = fma(a_0[4], b_4[1], c_0_1);
+    c_0_2 = fma(a_0[4], b_4[2], c_0_2);
+    c_0_3 = fma(a_0[4], b_4[3], c_0_3);
+    c_0_4 = fma(a_0[4], b_4[4], c_0_4);
+    c_1_0 = fma(a_1[4], b_4[0], c_1_0);
+    c_1_1 = fma(a_1[4], b_4[1], c_1_1);
+    c_1_2 = fma(a_1[4], b_4[2], c_1_2);
+    c_1_3 = fma(a_1[4], b_4[3], c_1_3);
+    c_1_4 = fma(a_1[4], b_4[4], c_1_4);
+    c_2_0 = fma(a_2[4], b_4[0], c_2_0);
+    c_2_1 = fma(a_2[4], b_4[1], c_2_1);
+    c_2_2 = fma(a_2[4], b_4[2], c_2_2);
+    c_2_3 = fma(a_2[4], b_4[3], c_2_3);
+    c_2_4 = fma(a_2[4], b_4[4], c_2_4);
+    c_3_0 = fma(a_3[4], b_4[0], c_3_0);
+    c_3_1 = fma(a_3[4], b_4[1], c_3_1);
+    c_3_2 = fma(a_3[4], b_4[2], c_3_2);
+    c_3_3 = fma(a_3[4], b_4[3], c_3_3);
+    c_3_4 = fma(a_3[4], b_4[4], c_3_4);
+    c_0_0 = fma(a_0[5], b_5[0], c_0_0);
+    c_0_1 = fma(a_0[5], b_5[1], c_0_1);
+    c_0_2 = fma(a_0[5], b_5[2], c_0_2);
+    c_0_3 = fma(a_0[5], b_5[3], c_0_3);
+    c_0_4 = fma(a_0[5], b_5[4], c_0_4);
+    c_1_0 = fma(a_1[5], b_5[0], c_1_0);
+    c_1_1 = fma(a_1[5], b_5[1], c_1_1);
+    c_1_2 = fma(a_1[5], b_5[2], c_1_2);
+    c_1_3 = fma(a_1[5], b_5[3], c_1_3);
+    c_1_4 = fma(a_1[5], b_5[4], c_1_4);
+    c_2_0 = fma(a_2[5], b_5[0], c_2_0);
+    c_2_1 = fma(a_2[5], b_5[1], c_2_1);
+    c_2_2 = fma(a_2[5], b_5[2], c_2_2);
+    c_2_3 = fma(a_2[5], b_5[3], c_2_3);
+    c_2_4 = fma(a_2[5], b_5[4], c_2_4);
+    c_3_0 = fma(a_3[5], b_5[0], c_3_0);
+    c_3_1 = fma(a_3[5], b_5[1], c_3_1);
+    c_3_2 = fma(a_3[5], b_5[2], c_3_2);
+    c_3_3 = fma(a_3[5], b_5[3], c_3_3);
+    c_3_4 = fma(a_3[5], b_5[4], c_3_4);
+  }
+  for (t *a = a0 + p/RBK*RBK, *b = b0 + p/RBK*RBK*ldb; a < a0 + p; a++, b += ldb)
+  {
+    t* a_0 = &a[lda*0];
+    t* a_1 = &a[lda*1];
+    t* a_2 = &a[lda*2];
+    t* a_3 = &a[lda*3];
+    t* b_0 = &b[ldb*0];
+    c_0_0 = fma(a_0[0], b_0[0], c_0_0);
+    c_0_1 = fma(a_0[0], b_0[1], c_0_1);
+    c_0_2 = fma(a_0[0], b_0[2], c_0_2);
+    c_0_3 = fma(a_0[0], b_0[3], c_0_3);
+    c_0_4 = fma(a_0[0], b_0[4], c_0_4);
+    c_1_0 = fma(a_1[0], b_0[0], c_1_0);
+    c_1_1 = fma(a_1[0], b_0[1], c_1_1);
+    c_1_2 = fma(a_1[0], b_0[2], c_1_2);
+    c_1_3 = fma(a_1[0], b_0[3], c_1_3);
+    c_1_4 = fma(a_1[0], b_0[4], c_1_4);
+    c_2_0 = fma(a_2[0], b_0[0], c_2_0);
+    c_2_1 = fma(a_2[0], b_0[1], c_2_1);
+    c_2_2 = fma(a_2[0], b_0[2], c_2_2);
+    c_2_3 = fma(a_2[0], b_0[3], c_2_3);
+    c_2_4 = fma(a_2[0], b_0[4], c_2_4);
+    c_3_0 = fma(a_3[0], b_0[0], c_3_0);
+    c_3_1 = fma(a_3[0], b_0[1], c_3_1);
+    c_3_2 = fma(a_3[0], b_0[2], c_3_2);
+    c_3_3 = fma(a_3[0], b_0[3], c_3_3);
+    c_3_4 = fma(a_3[0], b_0[4], c_3_4);
+  }
+  c_0[0] = c_0_0;
+  c_0[1] = c_0_1;
+  c_0[2] = c_0_2;
+  c_0[3] = c_0_3;
+  c_0[4] = c_0_4;
+  c_1[0] = c_1_0;
+  c_1[1] = c_1_1;
+  c_1[2] = c_1_2;
+  c_1[3] = c_1_3;
+  c_1[4] = c_1_4;
+  c_2[0] = c_2_0;
+  c_2[1] = c_2_1;
+  c_2[2] = c_2_2;
+  c_2[3] = c_2_3;
+  c_2[4] = c_2_4;
+  c_3[0] = c_3_0;
+  c_3[1] = c_3_1;
+  c_3[2] = c_3_2;
+  c_3[3] = c_3_3;
+  c_3[4] = c_3_4;
+}
diff --git a/apps/riscv-tests/benchmarks/mt-matmul/dataset.h b/apps/riscv-tests/benchmarks/mt-matmul/dataset.h
new file mode 100644
index 0000000..72fbc28
--- /dev/null
+++ b/apps/riscv-tests/benchmarks/mt-matmul/dataset.h
@@ -0,0 +1,63 @@
+// See LICENSE for license details.
+
+#ifndef __DATASET_H
+#define __DATASET_H
+#define ARRAY_SIZE 256 
+
+
+#define DIM_SIZE 16 
+
+
+typedef int data_t;static data_t input1_data[ARRAY_SIZE] = 
+{
+    0,   3,   2,   0,   3,   1,   0,   3,   2,   3,   2,   0,   3,   3,   1,   2,   3,   0,   0,   1, 
+    1,   1,   2,   3,   1,   2,   3,   1,   1,   3,   2,   2,   0,   1,   3,   2,   2,   2,   0,   0, 
+    1,   0,   1,   3,   3,   0,   3,   3,   3,   3,   0,   3,   2,   1,   2,   2,   0,   0,   3,   0, 
+    1,   1,   0,   3,   3,   1,   2,   3,   3,   0,   1,   2,   1,   0,   1,   2,   2,   1,   0,   3, 
+    1,   0,   2,   2,   1,   1,   1,   1,   1,   1,   2,   0,   3,   1,   1,   2,   2,   3,   3,   1, 
+    3,   2,   0,   0,   0,   3,   3,   3,   2,   1,   2,   3,   1,   0,   0,   0,   0,   1,   2,   2, 
+    1,   1,   3,   3,   3,   1,   1,   2,   3,   1,   3,   3,   2,   3,   2,   1,   2,   3,   0,   2, 
+    2,   1,   1,   0,   0,   0,   0,   0,   1,   3,   3,   1,   1,   1,   2,   2,   3,   2,   1,   1, 
+    1,   1,   3,   0,   2,   2,   1,   3,   2,   1,   2,   2,   1,   3,   1,   3,   1,   3,   2,   3, 
+    1,   2,   1,   3,   2,   2,   0,   1,   0,   0,   1,   2,   3,   3,   1,   0,   0,   0,   3,   1, 
+    2,   3,   2,   3,   2,   0,   0,   0,   0,   0,   3,   1,   3,   0,   0,   0,   3,   1,   1,   1, 
+    1,   2,   1,   2,   3,   2,   0,   0,   2,   2,   3,   0,   3,   0,   0,   3,   0,   3,   1,   3, 
+    3,   1,   1,   1,   2,   2,   1,   3,   0,   3,   3,   1,   0,   0,   3,   2
+};
+
+static data_t input2_data[ARRAY_SIZE] = 
+{
+    1,   1,   0,   3,   1,   2,   0,   0,   0,   0,   0,   2,   1,   2,   3,   0,   0,   3,   3,   2, 
+    2,   1,   2,   3,   3,   0,   2,   2,   1,   1,   2,   2,   0,   2,   2,   1,   2,   3,   2,   2, 
+    3,   3,   2,   2,   1,   1,   1,   1,   2,   1,   2,   2,   3,   3,   3,   0,   0,   3,   2,   3, 
+    2,   3,   1,   2,   1,   1,   2,   2,   0,   1,   0,   3,   2,   1,   1,   1,   2,   0,   1,   2, 
+    2,   0,   2,   1,   3,   3,   2,   3,   2,   0,   3,   1,   3,   3,   2,   0,   1,   0,   1,   1, 
+    2,   2,   1,   1,   2,   2,   1,   2,   3,   3,   1,   3,   2,   2,   2,   3,   3,   1,   0,   2, 
+    1,   0,   0,   0,   1,   1,   2,   0,   3,   2,   3,   3,   0,   2,   3,   1,   0,   0,   2,   1, 
+    2,   0,   2,   1,   1,   2,   3,   1,   3,   2,   1,   0,   0,   0,   0,   0,   2,   2,   0,   2, 
+    1,   2,   0,   3,   2,   2,   0,   0,   3,   2,   1,   1,   3,   0,   2,   0,   0,   1,   0,   2, 
+    3,   3,   1,   3,   3,   0,   0,   2,   2,   0,   0,   0,   1,   0,   0,   1,   3,   0,   2,   1, 
+    3,   2,   2,   1,   3,   2,   0,   1,   2,   2,   3,   2,   1,   1,   1,   1,   3,   0,   1,   3, 
+    2,   2,   3,   1,   1,   2,   0,   2,   1,   1,   2,   3,   1,   0,   1,   0,   1,   1,   0,   0, 
+    2,   0,   3,   0,   3,   0,   3,   2,   2,   3,   3,   2,   1,   0,   2,   2
+};
+
+static data_t verify_data[ARRAY_SIZE] = 
+{
+   36,  44,  57,  50,  54,  36,  38,  46,  55,  25,  38,  34,  51,  30,  40,  32,  37,  34,  38,  52, 
+   51,  40,  28,  32,  41,  22,  26,  35,  49,  35,  42,  23,  26,  26,  33,  36,  52,  40,  45,  49, 
+   50,  34,  41,  35,  44,  25,  23,  23,  31,  29,  39,  46,  50,  36,  31,  32,  42,  32,  34,  41, 
+   44,  33,  43,  30,  31,  28,  39,  46,  50,  40,  35,  37,  43,  35,  33,  43,  43,  29,  37,  29, 
+   27,  22,  30,  33,  43,  31,  32,  25,  36,  31,  31,  29,  40,  28,  26,  22,  29,  42,  48,  51, 
+   65,  52,  43,  54,  63,  34,  42,  44,  56,  33,  38,  32,  26,  22,  23,  38,  49,  32,  26,  30, 
+   43,  22,  24,  27,  45,  24,  26,  17,  35,  35,  47,  51,  59,  59,  43,  42,  43,  28,  37,  43, 
+   56,  48,  36,  32,  28,  19,  28,  34,  46,  34,  28,  34,  45,  20,  29,  28,  50,  32,  26,  21, 
+   37,  38,  51,  50,  55,  45,  38,  49,  56,  28,  38,  40,  50,  29,  44,  26,  32,  35,  50,  43, 
+   53,  44,  41,  41,  34,  24,  35,  34,  39,  33,  34,  29,  21,  33,  31,  45,  48,  42,  27,  29, 
+   40,  17,  21,  32,  45,  30,  29,  26,  26,  27,  38,  33,  29,  31,  32,  31,  35,  25,  29,  29, 
+   34,  15,  25,  23,  34,  28,  44,  45,  41,  41,  37,  45,  45,  17,  34,  44,  46,  30,  43,  29, 
+   31,  36,  37,  50,  54,  44,  28,  40,  38,  22,  27,  28,  45,  32,  36,  22
+};
+
+
+#endif //__DATASET_H
\ No newline at end of file
diff --git a/apps/riscv-tests/benchmarks/mt-matmul/matmul.c b/apps/riscv-tests/benchmarks/mt-matmul/matmul.c
new file mode 100644
index 0000000..6d7b978
--- /dev/null
+++ b/apps/riscv-tests/benchmarks/mt-matmul/matmul.c
@@ -0,0 +1,23 @@
+// See LICENSE for license details.
+
+#include "dataset.h"
+#include "util.h"
+#include <stddef.h>
+
+#pragma GCC optimize ("unroll-loops")
+
+void matmul(const size_t coreid, const size_t ncores, const size_t lda,  const data_t A[], const data_t B[], data_t C[])
+{
+  size_t i, j, k;
+  size_t block = lda / ncores;
+  size_t start = block * coreid;
+ 
+  for (i = 0; i < lda; i++) {
+    for (j = start; j < (start+block); j++) {
+      data_t sum = 0;
+      for (k = 0; k < lda; k++)
+        sum += A[j*lda + k] * B[k*lda + i];
+      C[i + j*lda] = sum;
+    }
+  }
+}
diff --git a/apps/riscv-tests/benchmarks/mt-matmul/matmul_gendata.pl b/apps/riscv-tests/benchmarks/mt-matmul/matmul_gendata.pl
new file mode 100755
index 0000000..798d992
--- /dev/null
+++ b/apps/riscv-tests/benchmarks/mt-matmul/matmul_gendata.pl
@@ -0,0 +1,205 @@
+#!/usr/bin/perl -w
+#==========================================================================
+# matmul_gendata.pl
+#
+# Author : Christopher Batten (cbatten@mit.edu)
+# Date   : April 29, 2005
+#
+(our $usageMsg = <<'ENDMSG') =~ s/^\#//gm;
+#
+# Simple script which creates an input data set and the reference data
+# for the matmul benchmark.
+#
+ENDMSG
+
+use strict "vars";
+use warnings;
+no  warnings("once");
+use Getopt::Long;
+
+#--------------------------------------------------------------------------
+# Command line processing
+#--------------------------------------------------------------------------
+
+our %opts;
+
+sub usage()
+{
+
+  print "\n";
+  print " Usage: matmul_gendata.pl [options] \n";
+  print "\n";
+  print " Options:\n";
+  print "  --help  print this message\n";
+  print "  --size  size of input data [1000]\n";
+  print "  --seed  random seed [1]\n";
+  print "$usageMsg";
+
+  exit();
+}
+
+sub processCommandLine()
+{
+
+  $opts{"help"} = 0;
+  $opts{"size"} = 1000;
+  $opts{"seed"} = 1;
+  Getopt::Long::GetOptions( \%opts, 'help|?', 'size:i', 'seed:i' ) or usage();
+  $opts{"help"} and usage();
+
+}
+
+#--------------------------------------------------------------------------
+# Helper Functions
+#--------------------------------------------------------------------------
+
+sub printArray
+{
+  my $arrayName = $_[0];
+  my $arrayRef  = $_[1];
+
+  my $numCols = 20;
+  my $arrayLen = scalar(@{$arrayRef});
+
+  print "static data_t ".$arrayName."[ARRAY_SIZE] = \n";
+  print "{\n";
+
+  if ( $arrayLen <= $numCols ) {
+    print "  ";
+    for ( my $i = 0; $i < $arrayLen; $i++ ) {
+      print sprintf("%3d",$arrayRef->[$i]);
+      if ( $i != $arrayLen-1 ) {
+        print ", ";
+      }
+    }
+    print "\n";
+  }
+
+  else {
+    my $numRows = int($arrayLen/$numCols);
+    for ( my $j = 0; $j < $numRows; $j++ ) {
+      print "  ";
+      for ( my $i = 0; $i < $numCols; $i++ ) {
+        my $index = $j*$numCols + $i;
+        print sprintf("%3d",$arrayRef->[$index]);
+        if ( $index != $arrayLen-1 ) {
+          print ", ";
+        }
+      }
+      print "\n";
+    }
+
+    if ( $arrayLen > ($numRows*$numCols) ) {
+      print "  ";
+      for ( my $i = 0; $i < ($arrayLen-($numRows*$numCols)); $i++ ) {
+        my $index = $numCols*$numRows + $i;
+        print sprintf("%3d",$arrayRef->[$index]);
+        if ( $index != $arrayLen-1 ) {
+          print ", ";
+        }
+      }
+      print "\n";
+    }
+
+  }
+
+  print  "};\n\n";
+}
+
+
+
+#--------------------------------------------------------------------------
+# Matmul
+#--------------------------------------------------------------------------
+
+# http://answers.oreilly.com/topic/418-how-to-multiply-matrices-in-perl/
+
+sub mmult {
+    my ($m1,$m2) = @_;
+    my ($m1rows,$m1cols) = matdim($m1);
+    my ($m2rows,$m2cols) = matdim($m2);
+
+    my $result = [  ];
+    my ($i, $j, $k);
+
+    for $i (range($m1rows)) {
+        for $j (range($m2cols)) {
+            for $k (range($m1cols)) {
+                $result->[$i][$j] += $m1->[$i][$k] * $m2->[$k][$j];
+            }
+        }
+    }
+    return $result;
+}
+
+sub range { 0 .. ($_[0] - 1) }
+
+
+sub veclen {
+    my $ary_ref = $_[0];
+    my $type = ref $ary_ref;
+    if ($type ne "ARRAY") { die "$type is bad array ref for $ary_ref" }
+    return scalar(@$ary_ref);
+}
+
+sub matdim {
+    my $matrix = $_[0];
+    my $rows = veclen($matrix);
+    my $cols = veclen($matrix->[0]);
+    return ($rows, $cols);
+}
+
+#--------------------------------------------------------------------------
+# Main
+#--------------------------------------------------------------------------
+
+sub main()
+{
+
+  processCommandLine();
+  srand($opts{"seed"});
+
+  # create random input arrays
+  my $mat_values1;
+  my $mat_values2;
+  for ( my $i = 0; $i < $opts{"size"}; $i++ ) {
+    for ( my $j = 0; $j < $opts{"size"}; $j++ ) {
+      $mat_values1->[$i][$j] = int(rand(4));
+      $mat_values2->[$i][$j] = int(rand(4));
+    }
+  }
+
+  # perform matmul
+  my $mat_results = mmult( $mat_values1, $mat_values2 );
+  
+  # translate 2d arrays to 1d-somethings (I don't know how to code in perl - Chris)
+  my @values1;
+  my @values2;
+  my @results;
+  for ( my $i = 0; $i < $opts{"size"}; $i++ ) {
+    for ( my $j = 0; $j < $opts{"size"}; $j++ ) {
+    my $value1 = $mat_values1->[$i][$j];
+    my $value2 = $mat_values2->[$i][$j];
+    my $result = $mat_results->[$i][$j];
+    push( @values1, $value1 );
+    push( @values2, $value2 );
+    push( @results, $result );
+    }
+  }
+
+  print "\n#ifndef __DATASET_H";
+  print "\n#define __DATASET_H";
+  print "\n\#define ARRAY_SIZE ".($opts{"size"}*$opts{"size"})." \n\n";
+  print "\n\#define DIM_SIZE ".$opts{"size"}." \n\n";
+  print "\ntypedef int data_t;";
+   
+  printArray( "input1_data", \@values1 );
+  printArray( "input2_data", \@values2 );
+  printArray( "verify_data", \@results);
+
+  print "\n#endif //__DATASET_H";
+ 
+}
+
+main();
+
diff --git a/apps/riscv-tests/benchmarks/mt-matmul/mt-matmul.c b/apps/riscv-tests/benchmarks/mt-matmul/mt-matmul.c
new file mode 100644
index 0000000..dbb7562
--- /dev/null
+++ b/apps/riscv-tests/benchmarks/mt-matmul/mt-matmul.c
@@ -0,0 +1,57 @@
+// See LICENSE for license details.
+
+//**************************************************************************
+// Multi-threaded Matrix Multiply benchmark
+//--------------------------------------------------------------------------
+// TA     : Christopher Celio
+// Student: 
+//
+//
+// This benchmark multiplies two 2-D arrays together and writes the results to
+// a third vector. The input data (and reference data) should be generated
+// using the matmul_gendata.pl perl script and dumped to a file named
+// dataset.h. 
+
+//--------------------------------------------------------------------------
+// Includes 
+
+#include <string.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <stddef.h>
+
+
+//--------------------------------------------------------------------------
+// Input/Reference Data
+
+#include "dataset.h"
+ 
+
+//--------------------------------------------------------------------------
+// Basic Utilities and Multi-thread Support
+
+#include "util.h"
+
+   
+//--------------------------------------------------------------------------
+// matmul function
+ 
+extern void matmul(const size_t coreid, const size_t ncores, const size_t lda,  const data_t A[], const data_t B[], data_t C[] );
+
+
+//--------------------------------------------------------------------------
+// Main
+//
+// all threads start executing thread_entry(). Use their "coreid" to
+// differentiate between threads (each thread is running on a separate core).
+  
+void thread_entry(int cid, int nc)
+{
+   static data_t results_data[ARRAY_SIZE];
+
+   stats(matmul(cid, nc, DIM_SIZE, input1_data, input2_data, results_data); barrier(nc), DIM_SIZE/DIM_SIZE/DIM_SIZE);
+ 
+   int res = verify(ARRAY_SIZE, results_data, verify_data);
+
+   exit(res);
+}
diff --git a/apps/riscv-tests/benchmarks/mt-vvadd/dataset.h b/apps/riscv-tests/benchmarks/mt-vvadd/dataset.h
new file mode 100644
index 0000000..a421b7b
--- /dev/null
+++ b/apps/riscv-tests/benchmarks/mt-vvadd/dataset.h
@@ -0,0 +1,173 @@
+// See LICENSE for license details.
+
+#ifndef __DATASET_H
+#define __DATASET_H
+
+#define DATA_SIZE 1000 
+
+typedef double data_t;
+
+static data_t input1_data[DATA_SIZE] = 
+{
+  0.00, 15.00, 10.00, 3.00, 14.00, 6.00, 2.00, 18.00, 11.00, 15.00, 11.00, 0.00, 17.00, 16.00, 7.00, 13.00, 18.00, 2.00, 2.00, 5.00, 
+  8.00, 5.00, 12.00, 14.00, 6.00, 12.00, 16.00, 7.00, 9.00, 17.00, 10.00, 10.00, 3.00, 5.00, 14.00, 11.00, 9.00, 12.00, 3.00, 1.00, 
+  5.00, 4.00, 6.00, 17.00, 17.00, 4.00, 17.00, 15.00, 17.00, 18.00, 3.00, 18.00, 10.00, 6.00, 12.00, 12.00, 3.00, 2.00, 16.00, 1.00, 
+  5.00, 6.00, 2.00, 17.00, 16.00, 5.00, 10.00, 18.00, 14.00, 4.00, 9.00, 9.00, 7.00, 4.00, 8.00, 13.00, 12.00, 6.00, 4.00, 17.00, 
+  5.00, 2.00, 11.00, 11.00, 7.00, 6.00, 8.00, 5.00, 6.00, 6.00, 11.00, 1.00, 18.00, 7.00, 6.00, 9.00, 10.00, 17.00, 14.00, 4.00, 
+  14.00, 11.00, 2.00, 0.00, 2.00, 17.00, 17.00, 15.00, 10.00, 8.00, 12.00, 18.00, 5.00, 0.00, 0.00, 1.00, 1.00, 8.00, 11.00, 11.00, 
+  7.00, 5.00, 15.00, 18.00, 15.00, 6.00, 8.00, 9.00, 18.00, 6.00, 15.00, 16.00, 10.00, 18.00, 13.00, 6.00, 10.00, 16.00, 0.00, 10.00, 
+  12.00, 8.00, 8.00, 3.00, 0.00, 1.00, 4.00, 0.00, 8.00, 15.00, 16.00, 9.00, 7.00, 7.00, 10.00, 9.00, 16.00, 12.00, 5.00, 5.00, 
+  9.00, 5.00, 17.00, 4.00, 13.00, 13.00, 4.00, 14.00, 10.00, 5.00, 10.00, 10.00, 6.00, 18.00, 5.00, 15.00, 5.00, 15.00, 13.00, 18.00, 
+  6.00, 13.00, 5.00, 18.00, 12.00, 14.00, 1.00, 7.00, 2.00, 1.00, 7.00, 12.00, 15.00, 15.00, 6.00, 2.00, 1.00, 2.00, 18.00, 6.00, 
+  10.00, 14.00, 9.00, 15.00, 11.00, 0.00, 3.00, 1.00, 2.00, 2.00, 14.00, 7.00, 18.00, 0.00, 2.00, 2.00, 16.00, 8.00, 4.00, 5.00, 
+  7.00, 11.00, 7.00, 10.00, 14.00, 10.00, 3.00, 0.00, 13.00, 9.00, 14.00, 0.00, 14.00, 1.00, 3.00, 16.00, 2.00, 14.00, 6.00, 17.00, 
+  17.00, 6.00, 9.00, 8.00, 9.00, 12.00, 5.00, 14.00, 2.00, 16.00, 17.00, 5.00, 4.00, 0.00, 14.00, 10.00, 6.00, 15.00, 15.00, 14.00, 
+  5.00, 1.00, 8.00, 8.00, 13.00, 8.00, 0.00, 4.00, 7.00, 9.00, 13.00, 16.00, 9.00, 14.00, 9.00, 13.00, 0.00, 7.00, 16.00, 17.00, 
+  18.00, 10.00, 13.00, 8.00, 4.00, 9.00, 13.00, 0.00, 6.00, 4.00, 6.00, 4.00, 10.00, 14.00, 14.00, 9.00, 15.00, 15.00, 3.00, 3.00, 
+  12.00, 0.00, 3.00, 2.00, 16.00, 1.00, 7.00, 2.00, 16.00, 2.00, 2.00, 0.00, 14.00, 3.00, 3.00, 10.00, 4.00, 10.00, 3.00, 4.00, 
+  13.00, 14.00, 13.00, 0.00, 1.00, 15.00, 16.00, 9.00, 7.00, 9.00, 0.00, 11.00, 1.00, 1.00, 15.00, 17.00, 12.00, 16.00, 15.00, 4.00, 
+  8.00, 2.00, 10.00, 10.00, 0.00, 18.00, 17.00, 7.00, 7.00, 2.00, 10.00, 17.00, 9.00, 7.00, 5.00, 3.00, 8.00, 11.00, 6.00, 9.00, 
+  13.00, 0.00, 3.00, 5.00, 2.00, 5.00, 7.00, 4.00, 9.00, 2.00, 13.00, 17.00, 14.00, 12.00, 1.00, 3.00, 7.00, 17.00, 0.00, 14.00, 
+  16.00, 2.00, 2.00, 1.00, 2.00, 15.00, 16.00, 8.00, 2.00, 4.00, 15.00, 15.00, 10.00, 6.00, 11.00, 9.00, 15.00, 17.00, 3.00, 8.00, 
+  15.00, 3.00, 10.00, 15.00, 8.00, 14.00, 16.00, 15.00, 15.00, 14.00, 1.00, 7.00, 4.00, 18.00, 2.00, 13.00, 11.00, 15.00, 7.00, 10.00, 
+  13.00, 10.00, 7.00, 14.00, 18.00, 4.00, 18.00, 4.00, 3.00, 9.00, 1.00, 13.00, 15.00, 2.00, 5.00, 15.00, 12.00, 10.00, 2.00, 0.00, 
+  10.00, 15.00, 0.00, 11.00, 14.00, 11.00, 14.00, 9.00, 1.00, 18.00, 14.00, 18.00, 15.00, 5.00, 1.00, 15.00, 18.00, 14.00, 3.00, 15.00, 
+  11.00, 2.00, 15.00, 0.00, 13.00, 1.00, 4.00, 14.00, 14.00, 5.00, 2.00, 13.00, 17.00, 8.00, 7.00, 6.00, 5.00, 10.00, 14.00, 14.00, 
+  17.00, 0.00, 0.00, 17.00, 18.00, 15.00, 10.00, 16.00, 18.00, 5.00, 9.00, 10.00, 18.00, 7.00, 11.00, 5.00, 4.00, 16.00, 2.00, 8.00, 
+  13.00, 1.00, 12.00, 3.00, 4.00, 6.00, 15.00, 12.00, 0.00, 6.00, 18.00, 12.00, 14.00, 18.00, 3.00, 2.00, 3.00, 5.00, 3.00, 14.00, 
+  18.00, 12.00, 10.00, 11.00, 8.00, 4.00, 10.00, 10.00, 9.00, 18.00, 14.00, 3.00, 7.00, 17.00, 12.00, 0.00, 10.00, 9.00, 17.00, 3.00, 
+  0.00, 4.00, 6.00, 16.00, 14.00, 12.00, 13.00, 13.00, 18.00, 7.00, 0.00, 1.00, 9.00, 7.00, 12.00, 6.00, 18.00, 8.00, 9.00, 13.00, 
+  13.00, 17.00, 10.00, 16.00, 1.00, 10.00, 17.00, 16.00, 2.00, 18.00, 4.00, 2.00, 6.00, 1.00, 1.00, 1.00, 8.00, 14.00, 6.00, 6.00, 
+  13.00, 14.00, 13.00, 6.00, 5.00, 10.00, 11.00, 11.00, 16.00, 1.00, 5.00, 9.00, 13.00, 8.00, 10.00, 2.00, 12.00, 15.00, 5.00, 14.00, 
+  3.00, 7.00, 9.00, 18.00, 2.00, 11.00, 16.00, 4.00, 5.00, 10.00, 17.00, 10.00, 3.00, 4.00, 14.00, 18.00, 13.00, 6.00, 8.00, 11.00, 
+  14.00, 3.00, 5.00, 6.00, 6.00, 5.00, 13.00, 0.00, 9.00, 9.00, 1.00, 7.00, 5.00, 5.00, 1.00, 6.00, 18.00, 11.00, 17.00, 7.00, 
+  1.00, 10.00, 5.00, 12.00, 6.00, 16.00, 16.00, 5.00, 1.00, 10.00, 10.00, 15.00, 7.00, 18.00, 8.00, 17.00, 3.00, 5.00, 3.00, 14.00, 
+  0.00, 16.00, 12.00, 0.00, 14.00, 17.00, 16.00, 2.00, 18.00, 13.00, 10.00, 13.00, 4.00, 14.00, 2.00, 3.00, 4.00, 8.00, 17.00, 0.00, 
+  6.00, 11.00, 5.00, 3.00, 3.00, 2.00, 15.00, 13.00, 10.00, 4.00, 1.00, 11.00, 6.00, 17.00, 1.00, 0.00, 18.00, 3.00, 3.00, 11.00, 
+  7.00, 7.00, 11.00, 14.00, 7.00, 16.00, 11.00, 10.00, 8.00, 6.00, 11.00, 5.00, 17.00, 10.00, 7.00, 8.00, 14.00, 2.00, 9.00, 17.00, 
+  15.00, 13.00, 10.00, 6.00, 0.00, 15.00, 11.00, 10.00, 11.00, 18.00, 2.00, 5.00, 17.00, 18.00, 11.00, 15.00, 3.00, 17.00, 9.00, 17.00, 
+  8.00, 6.00, 2.00, 4.00, 2.00, 11.00, 15.00, 2.00, 18.00, 3.00, 9.00, 7.00, 15.00, 9.00, 14.00, 10.00, 9.00, 6.00, 13.00, 8.00, 
+  15.00, 14.00, 0.00, 11.00, 5.00, 2.00, 12.00, 14.00, 10.00, 16.00, 9.00, 7.00, 9.00, 17.00, 4.00, 4.00, 7.00, 8.00, 4.00, 4.00, 
+  9.00, 7.00, 3.00, 5.00, 11.00, 11.00, 10.00, 13.00, 3.00, 14.00, 15.00, 8.00, 1.00, 1.00, 3.00, 0.00, 16.00, 9.00, 6.00, 1.00, 
+  0.00, 2.00, 0.00, 6.00, 13.00, 12.00, 5.00, 18.00, 1.00, 11.00, 17.00, 11.00, 16.00, 14.00, 14.00, 9.00, 11.00, 9.00, 17.00, 15.00, 
+  5.00, 18.00, 2.00, 11.00, 10.00, 16.00, 18.00, 5.00, 11.00, 12.00, 11.00, 18.00, 7.00, 6.00, 8.00, 3.00, 4.00, 3.00, 16.00, 4.00, 
+  6.00, 2.00, 15.00, 6.00, 7.00, 16.00, 0.00, 7.00, 11.00, 10.00, 3.00, 0.00, 14.00, 16.00, 15.00, 15.00, 12.00, 7.00, 1.00, 4.00, 
+  8.00, 4.00, 12.00, 0.00, 7.00, 8.00, 1.00, 1.00, 14.00, 15.00, 9.00, 8.00, 6.00, 6.00, 4.00, 7.00, 8.00, 13.00, 10.00, 5.00, 
+  8.00, 11.00, 2.00, 16.00, 7.00, 17.00, 5.00, 2.00, 17.00, 0.00, 18.00, 6.00, 7.00, 4.00, 4.00, 12.00, 0.00, 18.00, 8.00, 4.00, 
+  7.00, 0.00, 11.00, 1.00, 11.00, 17.00, 18.00, 15.00, 8.00, 11.00, 15.00, 9.00, 12.00, 1.00, 5.00, 6.00, 1.00, 18.00, 14.00, 7.00, 
+  16.00, 16.00, 10.00, 3.00, 13.00, 0.00, 12.00, 9.00, 18.00, 14.00, 15.00, 4.00, 11.00, 15.00, 15.00, 8.00, 16.00, 11.00, 13.00, 12.00, 
+  1.00, 13.00, 14.00, 2.00, 11.00, 0.00, 17.00, 11.00, 12.00, 6.00, 4.00, 4.00, 11.00, 13.00, 10.00, 2.00, 10.00, 14.00, 0.00, 6.00, 
+  18.00, 10.00, 7.00, 14.00, 12.00, 9.00, 4.00, 16.00, 17.00, 8.00, 14.00, 9.00, 0.00, 4.00, 15.00, 13.00, 8.00, 13.00, 13.00, 8.00, 
+  15.00, 6.00, 11.00, 4.00, 2.00, 6.00, 5.00, 14.00, 5.00, 17.00, 12.00, 11.00, 17.00, 4.00, 13.00, 7.00, 16.00, 12.00, 7.00, 18.00
+};
+
+static data_t input2_data[DATA_SIZE] = 
+{
+  8.00, 6.00, 0.00, 18.00, 6.00, 10.00, 1.00, 2.00, 4.00, 2.00, 4.00, 10.00, 6.00, 11.00, 17.00, 4.00, 0.00, 16.00, 14.00, 12.00, 
+  9.00, 8.00, 13.00, 15.00, 18.00, 2.00, 13.00, 10.00, 5.00, 4.00, 12.00, 9.00, 1.00, 13.00, 12.00, 7.00, 10.00, 17.00, 11.00, 10.00, 
+  18.00, 15.00, 11.00, 12.00, 7.00, 9.00, 6.00, 5.00, 11.00, 7.00, 10.00, 12.00, 18.00, 18.00, 15.00, 1.00, 3.00, 18.00, 11.00, 16.00, 
+  13.00, 18.00, 4.00, 13.00, 8.00, 7.00, 10.00, 13.00, 0.00, 9.00, 1.00, 16.00, 13.00, 7.00, 5.00, 5.00, 11.00, 1.00, 6.00, 10.00, 
+  12.00, 3.00, 10.00, 5.00, 15.00, 15.00, 13.00, 14.00, 14.00, 1.00, 18.00, 5.00, 16.00, 14.00, 10.00, 4.00, 8.00, 4.00, 6.00, 6.00, 
+  13.00, 14.00, 8.00, 5.00, 14.00, 10.00, 9.00, 10.00, 17.00, 15.00, 6.00, 16.00, 12.00, 9.00, 10.00, 16.00, 16.00, 8.00, 1.00, 12.00, 
+  7.00, 0.00, 0.00, 3.00, 5.00, 7.00, 10.00, 3.00, 17.00, 10.00, 18.00, 16.00, 1.00, 11.00, 18.00, 9.00, 2.00, 0.00, 12.00, 6.00, 
+  13.00, 1.00, 13.00, 5.00, 7.00, 13.00, 17.00, 9.00, 15.00, 13.00, 5.00, 2.00, 4.00, 4.00, 3.00, 0.00, 9.00, 11.00, 3.00, 12.00, 
+  6.00, 11.00, 1.00, 16.00, 12.00, 11.00, 2.00, 2.00, 15.00, 12.00, 8.00, 9.00, 14.00, 2.00, 11.00, 0.00, 0.00, 7.00, 2.00, 13.00, 
+  15.00, 18.00, 7.00, 16.00, 16.00, 1.00, 1.00, 12.00, 12.00, 2.00, 2.00, 1.00, 7.00, 4.00, 0.00, 8.00, 18.00, 4.00, 11.00, 6.00, 
+  17.00, 13.00, 12.00, 5.00, 16.00, 12.00, 0.00, 9.00, 10.00, 10.00, 18.00, 12.00, 8.00, 7.00, 5.00, 8.00, 16.00, 3.00, 9.00, 18.00, 
+  12.00, 13.00, 18.00, 6.00, 8.00, 12.00, 2.00, 12.00, 8.00, 8.00, 9.00, 18.00, 8.00, 0.00, 9.00, 2.00, 6.00, 7.00, 0.00, 3.00, 
+  11.00, 2.00, 18.00, 2.00, 16.00, 1.00, 16.00, 11.00, 11.00, 16.00, 16.00, 11.00, 7.00, 4.00, 14.00, 10.00, 5.00, 8.00, 4.00, 14.00, 
+  17.00, 13.00, 13.00, 3.00, 1.00, 14.00, 1.00, 7.00, 0.00, 2.00, 7.00, 14.00, 4.00, 9.00, 14.00, 3.00, 9.00, 13.00, 13.00, 3.00, 
+  3.00, 17.00, 0.00, 18.00, 4.00, 8.00, 6.00, 9.00, 4.00, 2.00, 0.00, 14.00, 3.00, 3.00, 14.00, 8.00, 6.00, 7.00, 2.00, 12.00, 
+  5.00, 14.00, 6.00, 12.00, 2.00, 16.00, 1.00, 15.00, 7.00, 18.00, 0.00, 0.00, 13.00, 13.00, 12.00, 11.00, 16.00, 15.00, 14.00, 8.00, 
+  9.00, 10.00, 8.00, 8.00, 13.00, 13.00, 13.00, 10.00, 1.00, 15.00, 4.00, 0.00, 12.00, 1.00, 8.00, 12.00, 1.00, 18.00, 12.00, 18.00, 
+  9.00, 1.00, 11.00, 5.00, 13.00, 7.00, 1.00, 13.00, 5.00, 8.00, 17.00, 11.00, 13.00, 15.00, 9.00, 3.00, 17.00, 18.00, 9.00, 3.00, 
+  15.00, 11.00, 12.00, 0.00, 2.00, 15.00, 3.00, 0.00, 13.00, 1.00, 14.00, 14.00, 15.00, 8.00, 6.00, 0.00, 0.00, 11.00, 17.00, 0.00, 
+  1.00, 8.00, 6.00, 6.00, 10.00, 6.00, 18.00, 12.00, 7.00, 18.00, 4.00, 6.00, 15.00, 18.00, 7.00, 5.00, 8.00, 6.00, 6.00, 7.00, 
+  4.00, 4.00, 10.00, 17.00, 12.00, 13.00, 11.00, 15.00, 12.00, 18.00, 7.00, 12.00, 17.00, 10.00, 14.00, 12.00, 2.00, 7.00, 17.00, 3.00, 
+  8.00, 6.00, 3.00, 9.00, 3.00, 7.00, 7.00, 15.00, 18.00, 5.00, 13.00, 13.00, 15.00, 10.00, 0.00, 11.00, 10.00, 1.00, 5.00, 16.00, 
+  2.00, 7.00, 14.00, 12.00, 7.00, 17.00, 17.00, 11.00, 0.00, 5.00, 16.00, 14.00, 1.00, 9.00, 8.00, 8.00, 3.00, 17.00, 0.00, 8.00, 
+  6.00, 5.00, 7.00, 6.00, 17.00, 3.00, 3.00, 8.00, 3.00, 12.00, 17.00, 5.00, 14.00, 3.00, 11.00, 5.00, 17.00, 2.00, 15.00, 1.00, 
+  18.00, 11.00, 12.00, 0.00, 0.00, 14.00, 7.00, 17.00, 15.00, 10.00, 18.00, 10.00, 11.00, 7.00, 12.00, 10.00, 17.00, 2.00, 18.00, 9.00, 
+  11.00, 4.00, 17.00, 10.00, 15.00, 12.00, 4.00, 1.00, 5.00, 10.00, 4.00, 2.00, 11.00, 3.00, 4.00, 15.00, 16.00, 10.00, 2.00, 2.00, 
+  15.00, 16.00, 0.00, 13.00, 16.00, 9.00, 1.00, 7.00, 3.00, 10.00, 7.00, 2.00, 12.00, 8.00, 1.00, 5.00, 0.00, 16.00, 4.00, 14.00, 
+  13.00, 16.00, 3.00, 0.00, 10.00, 6.00, 3.00, 9.00, 1.00, 3.00, 0.00, 13.00, 12.00, 17.00, 11.00, 4.00, 15.00, 15.00, 12.00, 4.00, 
+  4.00, 2.00, 16.00, 6.00, 11.00, 17.00, 14.00, 7.00, 4.00, 14.00, 8.00, 8.00, 3.00, 18.00, 17.00, 17.00, 12.00, 10.00, 11.00, 1.00, 
+  8.00, 13.00, 1.00, 14.00, 0.00, 9.00, 0.00, 7.00, 9.00, 0.00, 7.00, 12.00, 0.00, 18.00, 10.00, 1.00, 5.00, 13.00, 13.00, 2.00, 
+  10.00, 4.00, 2.00, 6.00, 0.00, 16.00, 2.00, 15.00, 13.00, 6.00, 8.00, 5.00, 6.00, 15.00, 12.00, 6.00, 6.00, 7.00, 8.00, 1.00, 
+  11.00, 9.00, 7.00, 18.00, 14.00, 4.00, 9.00, 6.00, 4.00, 2.00, 10.00, 13.00, 6.00, 17.00, 2.00, 11.00, 7.00, 3.00, 8.00, 9.00, 
+  2.00, 6.00, 18.00, 12.00, 18.00, 13.00, 8.00, 1.00, 11.00, 4.00, 13.00, 14.00, 16.00, 8.00, 6.00, 18.00, 14.00, 15.00, 9.00, 11.00, 
+  2.00, 13.00, 4.00, 3.00, 3.00, 15.00, 14.00, 3.00, 13.00, 12.00, 14.00, 16.00, 18.00, 12.00, 5.00, 11.00, 2.00, 3.00, 15.00, 1.00, 
+  12.00, 1.00, 15.00, 13.00, 12.00, 18.00, 4.00, 17.00, 13.00, 7.00, 11.00, 13.00, 7.00, 10.00, 1.00, 3.00, 18.00, 6.00, 10.00, 3.00, 
+  9.00, 16.00, 12.00, 10.00, 6.00, 6.00, 7.00, 16.00, 16.00, 16.00, 17.00, 18.00, 8.00, 18.00, 0.00, 6.00, 17.00, 13.00, 14.00, 8.00, 
+  0.00, 7.00, 5.00, 13.00, 8.00, 12.00, 14.00, 9.00, 10.00, 10.00, 9.00, 9.00, 8.00, 6.00, 0.00, 14.00, 16.00, 8.00, 7.00, 16.00, 
+  10.00, 3.00, 1.00, 9.00, 11.00, 2.00, 6.00, 18.00, 5.00, 4.00, 2.00, 11.00, 10.00, 17.00, 16.00, 2.00, 12.00, 15.00, 14.00, 6.00, 
+  6.00, 17.00, 3.00, 10.00, 9.00, 18.00, 18.00, 6.00, 11.00, 16.00, 18.00, 17.00, 7.00, 14.00, 1.00, 16.00, 7.00, 9.00, 11.00, 12.00, 
+  10.00, 6.00, 1.00, 16.00, 9.00, 18.00, 0.00, 9.00, 16.00, 10.00, 14.00, 6.00, 9.00, 14.00, 15.00, 7.00, 12.00, 8.00, 1.00, 1.00, 
+  1.00, 17.00, 17.00, 17.00, 18.00, 1.00, 15.00, 18.00, 16.00, 16.00, 11.00, 7.00, 4.00, 15.00, 3.00, 14.00, 13.00, 14.00, 9.00, 2.00, 
+  4.00, 8.00, 14.00, 7.00, 0.00, 12.00, 14.00, 15.00, 8.00, 2.00, 11.00, 5.00, 6.00, 16.00, 6.00, 4.00, 16.00, 7.00, 9.00, 5.00, 
+  1.00, 0.00, 16.00, 10.00, 9.00, 6.00, 5.00, 8.00, 15.00, 13.00, 7.00, 18.00, 18.00, 8.00, 0.00, 15.00, 4.00, 6.00, 14.00, 3.00, 
+  3.00, 2.00, 9.00, 14.00, 18.00, 13.00, 10.00, 15.00, 0.00, 11.00, 16.00, 7.00, 16.00, 18.00, 0.00, 12.00, 6.00, 13.00, 12.00, 12.00, 
+  5.00, 3.00, 5.00, 16.00, 13.00, 16.00, 8.00, 5.00, 12.00, 8.00, 8.00, 0.00, 2.00, 9.00, 18.00, 11.00, 8.00, 4.00, 14.00, 6.00, 
+  17.00, 2.00, 6.00, 8.00, 11.00, 13.00, 6.00, 18.00, 17.00, 6.00, 8.00, 0.00, 1.00, 14.00, 18.00, 4.00, 0.00, 4.00, 3.00, 3.00, 
+  16.00, 8.00, 16.00, 1.00, 2.00, 0.00, 15.00, 14.00, 10.00, 9.00, 15.00, 3.00, 5.00, 18.00, 5.00, 6.00, 7.00, 3.00, 7.00, 2.00, 
+  6.00, 12.00, 10.00, 10.00, 18.00, 16.00, 0.00, 9.00, 17.00, 10.00, 9.00, 14.00, 15.00, 5.00, 8.00, 15.00, 3.00, 15.00, 14.00, 11.00, 
+  6.00, 6.00, 14.00, 0.00, 14.00, 0.00, 7.00, 12.00, 8.00, 7.00, 1.00, 3.00, 6.00, 10.00, 12.00, 1.00, 16.00, 5.00, 5.00, 6.00, 
+  17.00, 15.00, 15.00, 9.00, 4.00, 18.00, 17.00, 13.00, 12.00, 9.00, 7.00, 10.00, 2.00, 5.00, 8.00, 18.00, 1.00, 15.00, 8.00, 0.00
+};
+
+static data_t verify_data[DATA_SIZE] = 
+{
+  8.00, 21.00, 10.00, 21.00, 20.00, 16.00, 3.00, 20.00, 15.00, 17.00, 15.00, 10.00, 23.00, 27.00, 24.00, 17.00, 18.00, 18.00, 16.00, 17.00, 
+  17.00, 13.00, 25.00, 29.00, 24.00, 14.00, 29.00, 17.00, 14.00, 21.00, 22.00, 19.00, 4.00, 18.00, 26.00, 18.00, 19.00, 29.00, 14.00, 11.00, 
+  23.00, 19.00, 17.00, 29.00, 24.00, 13.00, 23.00, 20.00, 28.00, 25.00, 13.00, 30.00, 28.00, 24.00, 27.00, 13.00, 6.00, 20.00, 27.00, 17.00, 
+  18.00, 24.00, 6.00, 30.00, 24.00, 12.00, 20.00, 31.00, 14.00, 13.00, 10.00, 25.00, 20.00, 11.00, 13.00, 18.00, 23.00, 7.00, 10.00, 27.00, 
+  17.00, 5.00, 21.00, 16.00, 22.00, 21.00, 21.00, 19.00, 20.00, 7.00, 29.00, 6.00, 34.00, 21.00, 16.00, 13.00, 18.00, 21.00, 20.00, 10.00, 
+  27.00, 25.00, 10.00, 5.00, 16.00, 27.00, 26.00, 25.00, 27.00, 23.00, 18.00, 34.00, 17.00, 9.00, 10.00, 17.00, 17.00, 16.00, 12.00, 23.00, 
+  14.00, 5.00, 15.00, 21.00, 20.00, 13.00, 18.00, 12.00, 35.00, 16.00, 33.00, 32.00, 11.00, 29.00, 31.00, 15.00, 12.00, 16.00, 12.00, 16.00, 
+  25.00, 9.00, 21.00, 8.00, 7.00, 14.00, 21.00, 9.00, 23.00, 28.00, 21.00, 11.00, 11.00, 11.00, 13.00, 9.00, 25.00, 23.00, 8.00, 17.00, 
+  15.00, 16.00, 18.00, 20.00, 25.00, 24.00, 6.00, 16.00, 25.00, 17.00, 18.00, 19.00, 20.00, 20.00, 16.00, 15.00, 5.00, 22.00, 15.00, 31.00, 
+  21.00, 31.00, 12.00, 34.00, 28.00, 15.00, 2.00, 19.00, 14.00, 3.00, 9.00, 13.00, 22.00, 19.00, 6.00, 10.00, 19.00, 6.00, 29.00, 12.00, 
+  27.00, 27.00, 21.00, 20.00, 27.00, 12.00, 3.00, 10.00, 12.00, 12.00, 32.00, 19.00, 26.00, 7.00, 7.00, 10.00, 32.00, 11.00, 13.00, 23.00, 
+  19.00, 24.00, 25.00, 16.00, 22.00, 22.00, 5.00, 12.00, 21.00, 17.00, 23.00, 18.00, 22.00, 1.00, 12.00, 18.00, 8.00, 21.00, 6.00, 20.00, 
+  28.00, 8.00, 27.00, 10.00, 25.00, 13.00, 21.00, 25.00, 13.00, 32.00, 33.00, 16.00, 11.00, 4.00, 28.00, 20.00, 11.00, 23.00, 19.00, 28.00, 
+  22.00, 14.00, 21.00, 11.00, 14.00, 22.00, 1.00, 11.00, 7.00, 11.00, 20.00, 30.00, 13.00, 23.00, 23.00, 16.00, 9.00, 20.00, 29.00, 20.00, 
+  21.00, 27.00, 13.00, 26.00, 8.00, 17.00, 19.00, 9.00, 10.00, 6.00, 6.00, 18.00, 13.00, 17.00, 28.00, 17.00, 21.00, 22.00, 5.00, 15.00, 
+  17.00, 14.00, 9.00, 14.00, 18.00, 17.00, 8.00, 17.00, 23.00, 20.00, 2.00, 0.00, 27.00, 16.00, 15.00, 21.00, 20.00, 25.00, 17.00, 12.00, 
+  22.00, 24.00, 21.00, 8.00, 14.00, 28.00, 29.00, 19.00, 8.00, 24.00, 4.00, 11.00, 13.00, 2.00, 23.00, 29.00, 13.00, 34.00, 27.00, 22.00, 
+  17.00, 3.00, 21.00, 15.00, 13.00, 25.00, 18.00, 20.00, 12.00, 10.00, 27.00, 28.00, 22.00, 22.00, 14.00, 6.00, 25.00, 29.00, 15.00, 12.00, 
+  28.00, 11.00, 15.00, 5.00, 4.00, 20.00, 10.00, 4.00, 22.00, 3.00, 27.00, 31.00, 29.00, 20.00, 7.00, 3.00, 7.00, 28.00, 17.00, 14.00, 
+  17.00, 10.00, 8.00, 7.00, 12.00, 21.00, 34.00, 20.00, 9.00, 22.00, 19.00, 21.00, 25.00, 24.00, 18.00, 14.00, 23.00, 23.00, 9.00, 15.00, 
+  19.00, 7.00, 20.00, 32.00, 20.00, 27.00, 27.00, 30.00, 27.00, 32.00, 8.00, 19.00, 21.00, 28.00, 16.00, 25.00, 13.00, 22.00, 24.00, 13.00, 
+  21.00, 16.00, 10.00, 23.00, 21.00, 11.00, 25.00, 19.00, 21.00, 14.00, 14.00, 26.00, 30.00, 12.00, 5.00, 26.00, 22.00, 11.00, 7.00, 16.00, 
+  12.00, 22.00, 14.00, 23.00, 21.00, 28.00, 31.00, 20.00, 1.00, 23.00, 30.00, 32.00, 16.00, 14.00, 9.00, 23.00, 21.00, 31.00, 3.00, 23.00, 
+  17.00, 7.00, 22.00, 6.00, 30.00, 4.00, 7.00, 22.00, 17.00, 17.00, 19.00, 18.00, 31.00, 11.00, 18.00, 11.00, 22.00, 12.00, 29.00, 15.00, 
+  35.00, 11.00, 12.00, 17.00, 18.00, 29.00, 17.00, 33.00, 33.00, 15.00, 27.00, 20.00, 29.00, 14.00, 23.00, 15.00, 21.00, 18.00, 20.00, 17.00, 
+  24.00, 5.00, 29.00, 13.00, 19.00, 18.00, 19.00, 13.00, 5.00, 16.00, 22.00, 14.00, 25.00, 21.00, 7.00, 17.00, 19.00, 15.00, 5.00, 16.00, 
+  33.00, 28.00, 10.00, 24.00, 24.00, 13.00, 11.00, 17.00, 12.00, 28.00, 21.00, 5.00, 19.00, 25.00, 13.00, 5.00, 10.00, 25.00, 21.00, 17.00, 
+  13.00, 20.00, 9.00, 16.00, 24.00, 18.00, 16.00, 22.00, 19.00, 10.00, 0.00, 14.00, 21.00, 24.00, 23.00, 10.00, 33.00, 23.00, 21.00, 17.00, 
+  17.00, 19.00, 26.00, 22.00, 12.00, 27.00, 31.00, 23.00, 6.00, 32.00, 12.00, 10.00, 9.00, 19.00, 18.00, 18.00, 20.00, 24.00, 17.00, 7.00, 
+  21.00, 27.00, 14.00, 20.00, 5.00, 19.00, 11.00, 18.00, 25.00, 1.00, 12.00, 21.00, 13.00, 26.00, 20.00, 3.00, 17.00, 28.00, 18.00, 16.00, 
+  13.00, 11.00, 11.00, 24.00, 2.00, 27.00, 18.00, 19.00, 18.00, 16.00, 25.00, 15.00, 9.00, 19.00, 26.00, 24.00, 19.00, 13.00, 16.00, 12.00, 
+  25.00, 12.00, 12.00, 24.00, 20.00, 9.00, 22.00, 6.00, 13.00, 11.00, 11.00, 20.00, 11.00, 22.00, 3.00, 17.00, 25.00, 14.00, 25.00, 16.00, 
+  3.00, 16.00, 23.00, 24.00, 24.00, 29.00, 24.00, 6.00, 12.00, 14.00, 23.00, 29.00, 23.00, 26.00, 14.00, 35.00, 17.00, 20.00, 12.00, 25.00, 
+  2.00, 29.00, 16.00, 3.00, 17.00, 32.00, 30.00, 5.00, 31.00, 25.00, 24.00, 29.00, 22.00, 26.00, 7.00, 14.00, 6.00, 11.00, 32.00, 1.00, 
+  18.00, 12.00, 20.00, 16.00, 15.00, 20.00, 19.00, 30.00, 23.00, 11.00, 12.00, 24.00, 13.00, 27.00, 2.00, 3.00, 36.00, 9.00, 13.00, 14.00, 
+  16.00, 23.00, 23.00, 24.00, 13.00, 22.00, 18.00, 26.00, 24.00, 22.00, 28.00, 23.00, 25.00, 28.00, 7.00, 14.00, 31.00, 15.00, 23.00, 25.00, 
+  15.00, 20.00, 15.00, 19.00, 8.00, 27.00, 25.00, 19.00, 21.00, 28.00, 11.00, 14.00, 25.00, 24.00, 11.00, 29.00, 19.00, 25.00, 16.00, 33.00, 
+  18.00, 9.00, 3.00, 13.00, 13.00, 13.00, 21.00, 20.00, 23.00, 7.00, 11.00, 18.00, 25.00, 26.00, 30.00, 12.00, 21.00, 21.00, 27.00, 14.00, 
+  21.00, 31.00, 3.00, 21.00, 14.00, 20.00, 30.00, 20.00, 21.00, 32.00, 27.00, 24.00, 16.00, 31.00, 5.00, 20.00, 14.00, 17.00, 15.00, 16.00, 
+  19.00, 13.00, 4.00, 21.00, 20.00, 29.00, 10.00, 22.00, 19.00, 24.00, 29.00, 14.00, 10.00, 15.00, 18.00, 7.00, 28.00, 17.00, 7.00, 2.00, 
+  1.00, 19.00, 17.00, 23.00, 31.00, 13.00, 20.00, 36.00, 17.00, 27.00, 28.00, 18.00, 20.00, 29.00, 17.00, 23.00, 24.00, 23.00, 26.00, 17.00, 
+  9.00, 26.00, 16.00, 18.00, 10.00, 28.00, 32.00, 20.00, 19.00, 14.00, 22.00, 23.00, 13.00, 22.00, 14.00, 7.00, 20.00, 10.00, 25.00, 9.00, 
+  7.00, 2.00, 31.00, 16.00, 16.00, 22.00, 5.00, 15.00, 26.00, 23.00, 10.00, 18.00, 32.00, 24.00, 15.00, 30.00, 16.00, 13.00, 15.00, 7.00, 
+  11.00, 6.00, 21.00, 14.00, 25.00, 21.00, 11.00, 16.00, 14.00, 26.00, 25.00, 15.00, 22.00, 24.00, 4.00, 19.00, 14.00, 26.00, 22.00, 17.00, 
+  13.00, 14.00, 7.00, 32.00, 20.00, 33.00, 13.00, 7.00, 29.00, 8.00, 26.00, 6.00, 9.00, 13.00, 22.00, 23.00, 8.00, 22.00, 22.00, 10.00, 
+  24.00, 2.00, 17.00, 9.00, 22.00, 30.00, 24.00, 33.00, 25.00, 17.00, 23.00, 9.00, 13.00, 15.00, 23.00, 10.00, 1.00, 22.00, 17.00, 10.00, 
+  32.00, 24.00, 26.00, 4.00, 15.00, 0.00, 27.00, 23.00, 28.00, 23.00, 30.00, 7.00, 16.00, 33.00, 20.00, 14.00, 23.00, 14.00, 20.00, 14.00, 
+  7.00, 25.00, 24.00, 12.00, 29.00, 16.00, 17.00, 20.00, 29.00, 16.00, 13.00, 18.00, 26.00, 18.00, 18.00, 17.00, 13.00, 29.00, 14.00, 17.00, 
+  24.00, 16.00, 21.00, 14.00, 26.00, 9.00, 11.00, 28.00, 25.00, 15.00, 15.00, 12.00, 6.00, 14.00, 27.00, 14.00, 24.00, 18.00, 18.00, 14.00, 
+  32.00, 21.00, 26.00, 13.00, 6.00, 24.00, 22.00, 27.00, 17.00, 26.00, 19.00, 21.00, 19.00, 9.00, 21.00, 25.00, 17.00, 27.00, 15.00, 18.00
+};
+
+
+#endif //__DATASET_H
diff --git a/apps/riscv-tests/benchmarks/mt-vvadd/mt-vvadd.c b/apps/riscv-tests/benchmarks/mt-vvadd/mt-vvadd.c
new file mode 100644
index 0000000..54c9602
--- /dev/null
+++ b/apps/riscv-tests/benchmarks/mt-vvadd/mt-vvadd.c
@@ -0,0 +1,78 @@
+// See LICENSE for license details.
+
+//**************************************************************************
+// Vector-vector add benchmark
+//--------------------------------------------------------------------------
+// Author  : Andrew Waterman
+// TA      : Christopher Celio
+// Student : 
+//
+// This benchmark adds two vectors and writes the results to a
+// third vector. The input data (and reference data) should be
+// generated using the vvadd_gendata.pl perl script and dumped
+// to a file named dataset.h 
+
+//--------------------------------------------------------------------------
+// Includes 
+
+#include <string.h>
+#include <stdlib.h>
+#include <stdio.h>
+
+
+//--------------------------------------------------------------------------
+// Input/Reference Data
+
+#include "dataset.h"
+ 
+  
+//--------------------------------------------------------------------------
+// Basic Utilities and Multi-thread Support
+
+#include "util.h"
+   
+ 
+//--------------------------------------------------------------------------
+// vvadd function
+
+extern void __attribute__((noinline)) vvadd(int coreid, int ncores, size_t n, const data_t* x, const data_t* y, data_t* z);
+
+
+//--------------------------------------------------------------------------
+// Main
+//
+// all threads start executing thread_entry(). Use their "coreid" to
+// differentiate between threads (each thread is running on a separate core).
+  
+void thread_entry(int cid, int nc)
+{
+   // static allocates data in the binary, which is visible to both threads
+   static data_t results_data[DATA_SIZE];
+   
+   // First do out-of-place vvadd
+   barrier(nc);
+   stats(vvadd(cid, nc, DATA_SIZE, input1_data, input2_data, results_data); barrier(nc), DATA_SIZE);
+ 
+   if(cid == 0) {
+     int res = verifyDouble(DATA_SIZE, results_data, verify_data);
+     if(res) exit(res);
+   }
+
+   // Second do in-place vvadd
+   // Copying input
+   size_t i;
+   if(cid == 0) {
+     for (i = 0; i < DATA_SIZE; i++)
+           results_data[i] = input1_data[i];
+   }
+   barrier(nc);
+   stats(vvadd(cid, nc, DATA_SIZE, results_data, input2_data, results_data); barrier(nc), DATA_SIZE);
+ 
+   if(cid == 0) {
+     int res = verifyDouble(DATA_SIZE, results_data, verify_data);
+     if(res) exit(res);
+   }
+   
+   barrier(nc);
+   exit(0);
+}
diff --git a/apps/riscv-tests/benchmarks/mt-vvadd/vvadd.c b/apps/riscv-tests/benchmarks/mt-vvadd/vvadd.c
new file mode 100644
index 0000000..5b74dd0
--- /dev/null
+++ b/apps/riscv-tests/benchmarks/mt-vvadd/vvadd.c
@@ -0,0 +1,18 @@
+// See LICENSE for license details.
+
+#include "stdlib.h"
+#include "dataset.h"
+
+//--------------------------------------------------------------------------
+// vvadd function
+
+void __attribute__((noinline)) vvadd(int coreid, int ncores, size_t n, const data_t* x, const data_t* y, data_t* z)
+{
+   size_t i;
+
+   // interleave accesses
+   for (i = coreid; i < n; i+=ncores)
+   {
+      z[i] = x[i] + y[i];
+   }
+}
diff --git a/apps/riscv-tests/benchmarks/mt-vvadd/vvadd_gendata.pl b/apps/riscv-tests/benchmarks/mt-vvadd/vvadd_gendata.pl
new file mode 100755
index 0000000..a9fceac
--- /dev/null
+++ b/apps/riscv-tests/benchmarks/mt-vvadd/vvadd_gendata.pl
@@ -0,0 +1,139 @@
+#!/usr/bin/perl -w
+#==========================================================================
+# vvadd_gendata.pl
+#
+# Author : Christopher Batten (cbatten@mit.edu)
+# Date   : April 29, 2005
+#
+(our $usageMsg = <<'ENDMSG') =~ s/^\#//gm;
+#
+# Simple script which creates an input data set and the reference data
+# for the vvadd benchmark.
+#
+ENDMSG
+
+use strict "vars";
+use warnings;
+no  warnings("once");
+use Getopt::Long;
+
+#--------------------------------------------------------------------------
+# Command line processing
+#--------------------------------------------------------------------------
+
+our %opts;
+
+sub usage()
+{
+
+  print "\n";
+  print " Usage: vvadd_gendata.pl [options] \n";
+  print "\n";
+  print " Options:\n";
+  print "  --help  print this message\n";
+  print "  --size  size of input data [1000]\n";
+  print "  --seed  random seed [1]\n";
+  print "$usageMsg";
+
+  exit();
+}
+
+sub processCommandLine()
+{
+
+  $opts{"help"} = 0;
+  $opts{"size"} = 1000;
+  $opts{"seed"} = 1;
+  Getopt::Long::GetOptions( \%opts, 'help|?', 'size:i', 'seed:i' ) or usage();
+  $opts{"help"} and usage();
+
+}
+
+#--------------------------------------------------------------------------
+# Helper Functions
+#--------------------------------------------------------------------------
+
+sub printArray
+{
+  my $arrayName = $_[0];
+  my $arrayRef  = $_[1];
+
+  my $numCols = 20;
+  my $arrayLen = scalar(@{$arrayRef});
+
+  print "static data_t ".$arrayName."[DATA_SIZE] = \n";
+  print "{\n";
+
+  if ( $arrayLen <= $numCols ) {
+    print "  ";
+    for ( my $i = 0; $i < $arrayLen; $i++ ) {
+      print sprintf("%3.2f",$arrayRef->[$i]);
+      if ( $i != $arrayLen-1 ) {
+        print ", ";
+      }
+    }
+    print "\n";
+  }
+
+  else {
+    my $numRows = int($arrayLen/$numCols);
+    for ( my $j = 0; $j < $numRows; $j++ ) {
+      print "  ";
+      for ( my $i = 0; $i < $numCols; $i++ ) {
+        my $index = $j*$numCols + $i;
+        print sprintf("%3.2f",$arrayRef->[$index]);
+        if ( $index != $arrayLen-1 ) {
+          print ", ";
+        }
+      }
+      print "\n";
+    }
+
+    if ( $arrayLen > ($numRows*$numCols) ) {
+      print "  ";
+      for ( my $i = 0; $i < ($arrayLen-($numRows*$numCols)); $i++ ) {
+        my $index = $numCols*$numRows + $i;
+        print sprintf("%3.2f",$arrayRef->[$index]);
+        if ( $index != $arrayLen-1 ) {
+          print ", ";
+        }
+      }
+      print "\n";
+    }
+
+  }
+
+  print  "};\n\n";
+}
+
+#--------------------------------------------------------------------------
+# Main
+#--------------------------------------------------------------------------
+
+sub main()
+{
+
+  processCommandLine();
+  srand($opts{"seed"});
+
+  my @values1;
+  my @values2;
+  my @sum;
+  for ( my $i = 0; $i < $opts{"size"}; $i++ ) {
+    my $value1 = int(rand(19));
+    my $value2 = int(rand(19));
+    push( @values1, $value1 );
+    push( @values2, $value2 );
+    push( @sum, $value1 + $value2 );
+  }
+
+
+  print "\n\#define DATA_SIZE ".$opts{"size"}." \n\n";
+  printArray( "input1_data", \@values1 );
+  printArray( "input2_data", \@values2 );
+  printArray( "verify_data", \@sum );
+
+}
+
+main();
+
diff --git a/apps/riscv-tests/benchmarks/multiply/dataset1.h b/apps/riscv-tests/benchmarks/multiply/dataset1.h
new file mode 100644
index 0000000..2b0850e
--- /dev/null
+++ b/apps/riscv-tests/benchmarks/multiply/dataset1.h
@@ -0,0 +1,32 @@
+// See LICENSE for license details.
+
+
+#define DATA_SIZE 100 
+
+int input_data1[DATA_SIZE] = 
+{
+   41, 454, 833, 335, 564,   1, 187, 989, 749, 365, 350, 572, 132,  64, 949, 153, 584, 216, 805, 140, 
+  621, 210,   6, 572, 931, 339, 890, 593, 392, 898, 694, 228, 961,  12, 110, 883, 116, 750, 296, 646, 
+  426, 500, 314, 436, 659, 701, 774, 812, 319, 981, 678, 150, 875, 696, 376, 564, 474, 272, 938, 258, 
+  539, 647, 569, 509, 203,  88, 280, 703, 759, 669, 606, 375, 511, 551, 657, 936, 195, 592,  81, 569, 
+  267, 952, 229, 800, 337, 584, 944, 643, 902, 368, 241, 489, 913, 328, 826, 313, 933, 592, 985, 388
+};
+
+int input_data2[DATA_SIZE] = 
+{
+  195, 543, 960, 649, 566, 979, 350, 997, 649, 814, 657,  79, 181, 208, 111, 998, 859, 629,  65, 847, 
+  288, 704, 349, 997, 141, 253, 905, 715, 886, 430, 264, 415, 576, 538, 979, 700, 761,   4, 241, 494, 
+  478, 100, 499, 864, 403, 693, 222, 416, 444, 296, 721, 285, 676, 620, 317,  78, 224, 351, 937, 540, 
+  288, 646, 119, 169, 615, 527, 606, 289, 389, 796, 351, 801, 455, 720, 278, 758, 367, 745, 358,  92, 
+  584, 989,  62, 271, 985, 853, 403, 788, 346, 531, 517, 222, 559, 461, 908, 241, 775, 358, 255, 332
+};
+
+int verify_data[DATA_SIZE] = 
+{
+  7995, 246522, 799680, 217415, 319224, 979, 65450, 986033, 486101, 297110, 229950, 45188, 23892, 13312, 105339, 152694, 501656, 135864, 52325, 118580, 
+  178848, 147840, 2094, 570284, 131271, 85767, 805450, 423995, 347312, 386140, 183216, 94620, 553536, 6456, 107690, 618100, 88276, 3000, 71336, 319124, 
+  203628, 50000, 156686, 376704, 265577, 485793, 171828, 337792, 141636, 290376, 488838, 42750, 591500, 431520, 119192, 43992, 106176, 95472, 878906, 139320, 
+  155232, 417962, 67711, 86021, 124845, 46376, 169680, 203167, 295251, 532524, 212706, 300375, 232505, 396720, 182646, 709488, 71565, 441040, 28998, 52348, 
+  155928, 941528, 14198, 216800, 331945, 498152, 380432, 506684, 312092, 195408, 124597, 108558, 510367, 151208, 750008, 75433, 723075, 211936, 251175, 128816
+};
+
diff --git a/apps/riscv-tests/benchmarks/multiply/multiply.c b/apps/riscv-tests/benchmarks/multiply/multiply.c
new file mode 100644
index 0000000..3a0b903
--- /dev/null
+++ b/apps/riscv-tests/benchmarks/multiply/multiply.c
@@ -0,0 +1,24 @@
+// See LICENSE for license details.
+
+// *************************************************************************
+// multiply function (c version)
+// -------------------------------------------------------------------------
+
+int multiply( int x, int y )
+{
+
+ int i;
+ int result = 0;
+
+ for (i = 0; i < 32; i++) {
+   if ((x & 0x1) == 1)
+     result = result + y;
+       
+   x = x >> 1;
+   y = y << 1;
+ } 
+ 
+ return result;
+
+}
+
diff --git a/apps/riscv-tests/benchmarks/multiply/multiply.h b/apps/riscv-tests/benchmarks/multiply/multiply.h
new file mode 100644
index 0000000..b2b1cf7
--- /dev/null
+++ b/apps/riscv-tests/benchmarks/multiply/multiply.h
@@ -0,0 +1,11 @@
+// See LICENSE for license details.
+
+//**************************************************************************
+// Software multiply function
+//--------------------------------------------------------------------------
+
+// Simple C version
+int multiply(int x, int y);
+
+// Simple assembly version
+int multiply_asm(int x, int y);
diff --git a/apps/riscv-tests/benchmarks/multiply/multiply_gendata.pl b/apps/riscv-tests/benchmarks/multiply/multiply_gendata.pl
new file mode 100755
index 0000000..b8d8ed5
--- /dev/null
+++ b/apps/riscv-tests/benchmarks/multiply/multiply_gendata.pl
@@ -0,0 +1,142 @@
+#!/usr/bin/perl -w
+#==========================================================================
+# multiply_gendata.pl
+#
+# Author : Christopher Batten (cbatten@mit.edu)
+# Date   : May 9, 2005
+#
+(our $usageMsg = <<'ENDMSG') =~ s/^\#//gm;
+#
+# Simple script which creates an input data set and the reference data 
+# for the multiply benchmark.
+#
+ENDMSG
+
+use strict "vars";
+use warnings;
+no  warnings("once");
+use Getopt::Long;
+
+#--------------------------------------------------------------------------
+# Command line processing
+#--------------------------------------------------------------------------
+
+our %opts;
+
+sub usage()
+{
+
+  print "\n";
+  print " Usage: multiply_gendata.pl [options] \n";
+  print "\n";
+  print " Options:\n";
+  print "  --help  print this message\n";
+  print "  --size  size of input data [750]\n";
+  print "  --seed  random seed [1]\n";
+  print "$usageMsg";
+
+  exit();
+}
+
+sub processCommandLine()
+{
+
+  $opts{"help"} = 0;
+  $opts{"size"} = 750;
+  $opts{"seed"} = 1;
+  Getopt::Long::GetOptions( \%opts, 'help|?', 'size:i', 'seed:i' ) or usage();
+  $opts{"help"} and usage();
+
+}
+
+#--------------------------------------------------------------------------
+# Helper Functions
+#--------------------------------------------------------------------------
+
+sub printArray
+{
+  my $arrayName = $_[0];
+  my $arrayRef  = $_[1];
+
+  my $numCols = 20;
+  my $arrayLen = scalar(@{$arrayRef});
+
+  print "int ".$arrayName."[DATA_SIZE] = \n";
+  print "{\n";
+
+  if ( $arrayLen <= $numCols ) {
+    print "  ";
+    for ( my $i = 0; $i < $arrayLen; $i++ ) {
+      print sprintf("%3d",$arrayRef->[$i]);
+      if ( $i != $arrayLen-1 ) {
+        print ", ";
+      }
+    }
+    print "\n";
+  }
+  
+  else {
+    my $numRows = int($arrayLen/$numCols);
+    for ( my $j = 0; $j < $numRows; $j++ ) {
+      print "  ";
+      for ( my $i = 0; $i < $numCols; $i++ ) {
+        my $index = $j*$numCols + $i;
+        print sprintf("%3d",$arrayRef->[$index]);
+        if ( $index != $arrayLen-1 ) {
+          print ", ";
+        }
+      }
+      print "\n";
+    }
+
+    if ( $arrayLen > ($numRows*$numCols) ) {
+      print "  ";
+      for ( my $i = 0; $i < ($arrayLen-($numRows*$numCols)); $i++ ) {
+        my $index = $numCols*$numRows + $i;
+        print sprintf("%3d",$arrayRef->[$index]);
+        if ( $index != $arrayLen-1 ) {
+          print ", ";
+        }
+      }
+      print "\n";
+    }
+
+  }
+
+  print  "};\n\n";
+}
+
+#--------------------------------------------------------------------------
+# Main
+#--------------------------------------------------------------------------
+
+sub main()
+{
+
+  processCommandLine();
+  srand($opts{"seed"});
+  
+  my @values1;
+  for ( my $i = 0; $i < $opts{"size"}; $i++ ) {
+    push( @values1, int(rand(999)) );
+  }
+  
+  my @values2;
+  for ( my $i = 0; $i < $opts{"size"}; $i++ ) {
+    push( @values2, int(rand(999)) );
+  }
+
+  my @multiply;
+  for ( my $i = 0; $i < $opts{"size"}; $i++ ) {
+    $multiply[$i] = $values1[$i] * $values2[$i];
+  }
+
+  print "\n\#define DATA_SIZE ".$opts{"size"}." \n\n";
+  printArray( "input_data1", \@values1 );
+  printArray( "input_data2", \@values2 );
+  printArray( "verify_data", \@multiply );
+
+}
+
+main();
+
diff --git a/apps/riscv-tests/benchmarks/multiply/multiply_main.c b/apps/riscv-tests/benchmarks/multiply/multiply_main.c
new file mode 100644
index 0000000..ea225eb
--- /dev/null
+++ b/apps/riscv-tests/benchmarks/multiply/multiply_main.c
@@ -0,0 +1,45 @@
+// See LICENSE for license details.
+
+// *************************************************************************
+// multiply filter bencmark
+// -------------------------------------------------------------------------
+//
+// This benchmark tests the software multiply implemenation. The
+// input data (and reference data) should be generated using the
+// multiply_gendata.pl perl script and dumped to a file named
+// dataset1.h
+
+#include "util.h"
+
+#include "multiply.h"
+
+//--------------------------------------------------------------------------
+// Input/Reference Data
+
+#include "dataset1.h"
+
+//--------------------------------------------------------------------------
+// Main
+
+int main( int argc, char* argv[] )
+{
+  int i;
+  int results_data[DATA_SIZE];
+
+#if PREALLOCATE
+  for (i = 0; i < DATA_SIZE; i++)
+  {
+    results_data[i] = multiply( input_data1[i], input_data2[i] );
+  }
+#endif
+
+  setStats(1);
+  for (i = 0; i < DATA_SIZE; i++)
+  {
+    results_data[i] = multiply( input_data1[i], input_data2[i] );
+  }
+  setStats(0);
+
+  // Check the results
+  return verify( DATA_SIZE, results_data, verify_data );
+}
diff --git a/apps/riscv-tests/benchmarks/pmp/pmp.c b/apps/riscv-tests/benchmarks/pmp/pmp.c
new file mode 100644
index 0000000..ec07e4a
--- /dev/null
+++ b/apps/riscv-tests/benchmarks/pmp/pmp.c
@@ -0,0 +1,212 @@
+// See LICENSE for license details.
+
+// Test of PMP functionality.
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include "util.h"
+
+volatile int trap_expected;
+volatile int granule;
+
+#define INLINE inline __attribute__((always_inline))
+
+uintptr_t handle_trap(uintptr_t cause, uintptr_t epc, uintptr_t regs[32])
+{
+  if (cause == CAUSE_ILLEGAL_INSTRUCTION)
+    exit(0); // no PMP support
+
+  if (!trap_expected || cause != CAUSE_LOAD_ACCESS)
+    exit(1);
+  trap_expected = 0;
+  return epc + insn_len(epc);
+}
+
+#define SCRATCH RISCV_PGSIZE
+uintptr_t scratch[RISCV_PGSIZE / sizeof(uintptr_t)] __attribute__((aligned(RISCV_PGSIZE)));
+uintptr_t l1pt[RISCV_PGSIZE / sizeof(uintptr_t)] __attribute__((aligned(RISCV_PGSIZE)));
+uintptr_t l2pt[RISCV_PGSIZE / sizeof(uintptr_t)] __attribute__((aligned(RISCV_PGSIZE)));
+#if __riscv_xlen == 64
+uintptr_t l3pt[RISCV_PGSIZE / sizeof(uintptr_t)] __attribute__((aligned(RISCV_PGSIZE)));
+#else
+#define l3pt l2pt
+#endif
+
+static void init_pt()
+{
+  l1pt[0] = ((uintptr_t)l2pt >> RISCV_PGSHIFT << PTE_PPN_SHIFT) | PTE_V;
+  l3pt[SCRATCH / RISCV_PGSIZE] = ((uintptr_t)scratch >> RISCV_PGSHIFT << PTE_PPN_SHIFT) | PTE_A | PTE_D | PTE_V | PTE_R | PTE_W;
+#if __riscv_xlen == 64
+  l2pt[0] = ((uintptr_t)l3pt >> RISCV_PGSHIFT << PTE_PPN_SHIFT) | PTE_V;
+  uintptr_t vm_choice = SATP_MODE_SV39;
+#else
+  uintptr_t vm_choice = SATP_MODE_SV32;
+#endif
+  write_csr(sptbr, ((uintptr_t)l1pt >> RISCV_PGSHIFT) |
+                   (vm_choice * (SATP_MODE & ~(SATP_MODE<<1))));
+  write_csr(pmpaddr2, -1);
+  write_csr(pmpcfg0, (PMP_NAPOT | PMP_R) << 16);
+}
+
+INLINE uintptr_t va2pa(uintptr_t va)
+{
+  if (va < SCRATCH || va >= SCRATCH + RISCV_PGSIZE)
+    exit(3);
+  return va - SCRATCH + (uintptr_t)scratch;
+}
+
+typedef struct {
+  uintptr_t cfg;
+  uintptr_t a0;
+  uintptr_t a1;
+} pmpcfg_t;
+
+INLINE int pmp_ok(pmpcfg_t p, uintptr_t addr, uintptr_t size)
+{
+  if ((p.cfg & PMP_A) == 0)
+    return 1;
+
+  if ((p.cfg & PMP_A) != PMP_TOR) {
+    uintptr_t range = 1;
+
+    if ((p.cfg & PMP_A) == PMP_NAPOT) {
+      range <<= 1;
+      for (uintptr_t i = 1; i; i <<= 1) {
+        if ((p.a1 & i) == 0)
+          break;
+        p.a1 &= ~i;
+        range <<= 1;
+      }
+    }
+
+    p.a0 = p.a1;
+    p.a1 = p.a0 + range;
+  }
+
+  p.a0 *= granule;
+  p.a1 *= granule;
+  addr = va2pa(addr);
+
+  uintptr_t hits = 0;
+  for (uintptr_t i = 0; i < size; i += granule) {
+    if (p.a0 <= addr + i && addr + i < p.a1)
+      hits += granule;
+  }
+
+  return hits == 0 || hits >= size;
+}
+
+INLINE void test_one(uintptr_t addr, uintptr_t size)
+{
+  uintptr_t new_mstatus = (read_csr(mstatus) & ~MSTATUS_MPP) | (MSTATUS_MPP & (MSTATUS_MPP >> 1)) | MSTATUS_MPRV;
+  switch (size) {
+    case 1: asm volatile ("csrrw %0, mstatus, %0; lb x0, (%1); csrw mstatus, %0" : "+&r" (new_mstatus) : "r" (addr)); break;
+    case 2: asm volatile ("csrrw %0, mstatus, %0; lh x0, (%1); csrw mstatus, %0" : "+&r" (new_mstatus) : "r" (addr)); break;
+    case 4: asm volatile ("csrrw %0, mstatus, %0; lw x0, (%1); csrw mstatus, %0" : "+&r" (new_mstatus) : "r" (addr)); break;
+#if __riscv_xlen >= 64
+    case 8: asm volatile ("csrrw %0, mstatus, %0; ld x0, (%1); csrw mstatus, %0" : "+&r" (new_mstatus) : "r" (addr)); break;
+#endif
+    default: __builtin_unreachable();
+  }
+}
+
+INLINE void test_all_sizes(pmpcfg_t p, uintptr_t addr)
+{
+  for (size_t size = 1; size <= sizeof(uintptr_t); size *= 2) {
+    if (addr & (size - 1))
+      continue;
+    trap_expected = !pmp_ok(p, addr, size);
+    test_one(addr, size);
+    if (trap_expected)
+      exit(2);
+  }
+}
+
+INLINE void test_range_once(pmpcfg_t p, uintptr_t base, uintptr_t range)
+{
+  for (uintptr_t addr = base; addr < base + range; addr += granule)
+    test_all_sizes(p, addr);
+}
+
+INLINE pmpcfg_t set_pmp(pmpcfg_t p)
+{
+  uintptr_t cfg0 = read_csr(pmpcfg0);
+  write_csr(pmpcfg0, cfg0 & ~0xff00);
+  write_csr(pmpaddr0, p.a0);
+  write_csr(pmpaddr1, p.a1);
+  write_csr(pmpcfg0, ((p.cfg << 8) & 0xff00) | (cfg0 & ~0xff00));
+  asm volatile ("sfence.vma" ::: "memory");
+  return p;
+}
+
+INLINE pmpcfg_t set_pmp_range(uintptr_t base, uintptr_t range)
+{
+  pmpcfg_t p;
+  p.cfg = PMP_TOR | PMP_R;
+  p.a0 = base >> PMP_SHIFT;
+  p.a1 = (base + range) >> PMP_SHIFT;
+  return set_pmp(p);
+}
+
+INLINE pmpcfg_t set_pmp_napot(uintptr_t base, uintptr_t range)
+{
+  pmpcfg_t p;
+  p.cfg = PMP_R | (range > granule ? PMP_NAPOT : PMP_NA4);
+  p.a0 = 0;
+  p.a1 = (base + (range/2 - 1)) >> PMP_SHIFT;
+  return set_pmp(p);
+}
+
+static void test_range(uintptr_t addr, uintptr_t range)
+{
+  pmpcfg_t p = set_pmp_range(va2pa(addr), range);
+  test_range_once(p, addr, range);
+
+  if ((range & (range - 1)) == 0 && (addr & (range - 1)) == 0) {
+    p = set_pmp_napot(va2pa(addr), range);
+    test_range_once(p, addr, range);
+  }
+}
+
+static void test_ranges(uintptr_t addr, uintptr_t size)
+{
+  for (uintptr_t range = granule; range <= size; range += granule)
+    test_range(addr, range);
+}
+
+static void exhaustive_test(uintptr_t addr, uintptr_t size)
+{
+  for (uintptr_t base = addr; base < addr + size; base += granule)
+    test_ranges(base, size - (base - addr));
+}
+
+static void detect_granule()
+{
+  write_csr(pmpcfg0, NULL);
+  write_csr(pmpaddr0, 0xffffffffffffffffULL);
+  uintptr_t ret = read_csr(pmpaddr0);
+  int g = 2;
+  for(uintptr_t i = 1; i; i<<=1) {
+    if((ret & i) != 0) 
+      break;
+    g++;
+  }
+  granule = 1UL << g;
+}
+
+int main()
+{
+  detect_granule();
+  init_pt();
+
+  const int max_exhaustive = 32;
+  exhaustive_test(SCRATCH, max_exhaustive);
+  exhaustive_test(SCRATCH + RISCV_PGSIZE - max_exhaustive, max_exhaustive);
+
+  test_range(SCRATCH, RISCV_PGSIZE);
+  test_range(SCRATCH, RISCV_PGSIZE / 2);
+  test_range(SCRATCH + RISCV_PGSIZE / 2, RISCV_PGSIZE / 2);
+
+  return 0;
+}
diff --git a/apps/riscv-tests/benchmarks/qsort/dataset1.h b/apps/riscv-tests/benchmarks/qsort/dataset1.h
new file mode 100644
index 0000000..dd1c634
--- /dev/null
+++ b/apps/riscv-tests/benchmarks/qsort/dataset1.h
@@ -0,0 +1,219 @@
+// See LICENSE for license details.
+
+
+#define DATA_SIZE 2048 
+
+type input_data[DATA_SIZE] = 
+{
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+  2055783490, 980863365, 1308872551, 1010427073, 1399854717, 1217804021, 934700736, 878744414
+};
+
+type verify_data[DATA_SIZE] = 
+{
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+  1013901419, 1016469330, 1016615447, 1020037994, 1021014457, 1022861633, 1025117441, 1026342885, 1026380990, 1027758817, 1027760887, 1028529524, 1028820236, 1028937430, 1029176122, 1029338154, 1029832956, 1031625002, 1032748996, 1032914339, 
+  1033910502, 1035075488, 1035956563, 1037521069, 1038018856, 1038830638, 1042790263, 1042942541, 1043920511, 1044088643, 1045627895, 1045658065, 1047336724, 1048943084, 1049475248, 1050373352, 1050512245, 1051184301, 1054066034, 1057003814, 
+  1058677375, 1058937717, 1061864942, 1063657548, 1063743848, 1063768444, 1063839036, 1065136414, 1065481253, 1066014062, 1066787659, 1067775613, 1068587688, 1068798385, 1069450170, 1073695485, 1073871430, 1074205225, 1075762632, 1076198976, 
+  1078197595, 1079859867, 1082499152, 1082864732, 1082881617, 1085326591, 1087195269, 1087245613, 1087251698, 1087556673, 1087742330, 1089408490, 1089710430, 1090104632, 1090386021, 1090443335, 1092382563, 1092881031, 1094283114, 1094531762, 
+  1095403694, 1099847920, 1100041120, 1100089300, 1101722351, 1101933540, 1102423908, 1102603775, 1103013140, 1106678970, 1110387095, 1111213862, 1112056034, 1112731797, 1113693824, 1120963974, 1121432739, 1121800211, 1121960111, 1122768484, 
+  1123331233, 1123555638, 1125104871, 1125822965, 1126017956, 1127173529, 1127911377, 1128895624, 1130850177, 1131661227, 1132597050, 1133473813, 1133910514, 1134185180, 1135793759, 1136264020, 1136356724, 1137511396, 1139018167, 1139159604, 
+  1140008063, 1140728569, 1143168018, 1143511498, 1143853106, 1144017176, 1144669754, 1147341731, 1147793249, 1148699143, 1149113346, 1150780072, 1152335090, 1152416171, 1154842325, 1155459206, 1155544307, 1156824624, 1157666831, 1159675637, 
+  1159745061, 1159898528, 1160036198, 1160186023, 1160285859, 1160333307, 1160537912, 1161580432, 1162679490, 1165446977, 1166227930, 1167207852, 1168465459, 1169327477, 1170510314, 1170759710, 1171051384, 1171925835, 1172290275, 1173840088, 
+  1173889730, 1174587016, 1175004233, 1175885101, 1178086274, 1178260876, 1179525294, 1180063064, 1180525723, 1181191604, 1183464058, 1184561748, 1185825535, 1188076819, 1188748563, 1189141368, 1189323192, 1190890142, 1191079043, 1191513656, 
+  1192155877, 1194041213, 1194709162, 1198213061, 1198254803, 1198857033, 1199317660, 1201124879, 1201152163, 1201659316, 1202009920, 1202162389, 1203377492, 1203897636, 1204992245, 1205522527, 1205895814, 1206302514, 1209784819, 1209991461, 
+  1212628403, 1212974417, 1214379246, 1214950832, 1215063385, 1215103809, 1216475831, 1217804021, 1218522465, 1220523503, 1220915309, 1221108420, 1221726287, 1222554291, 1223475486, 1223572435, 1223583276, 1228817775, 1230449468, 1231111410, 
+  1231149357, 1231249235, 1231639101, 1231932661, 1232567659, 1232992084, 1233022905, 1234157881, 1234944834, 1239665569, 1240287664, 1245819051, 1247518755, 1249086623, 1249183285, 1250360726, 1255524953, 1256015513, 1256152080, 1256372950, 
+  1257507406, 1260859787, 1262399341, 1267173039, 1269707634, 1271370220, 1273223611, 1273955724, 1274190723, 1274436639, 1275331596, 1275500498, 1276205250, 1278053582, 1278777407, 1278794420, 1279061703, 1279981214, 1281443423, 1285258674, 
+  1286989824, 1287171290, 1287830283, 1288684086, 1289308008, 1290629443, 1290969161, 1291025252, 1291070368, 1291438802, 1292049996, 1292413659, 1293091635, 1294873695, 1296857499, 1298200648, 1299667896, 1302272656, 1302724177, 1303736105, 
+  1305071296, 1308872551, 1310177444, 1312064004, 1312471120, 1313115559, 1313640711, 1313871880, 1316120929, 1317077622, 1317201705, 1318032594, 1318900244, 1319798607, 1321897861, 1322281086, 1322696419, 1323798820, 1324123626, 1324723894, 
+  1325008187, 1325083914, 1326017288, 1328272543, 1328885292, 1331383316, 1331593955, 1332379148, 1332467446, 1332620900, 1332937015, 1333790305, 1334857284, 1335236478, 1335298265, 1335652095, 1335861008, 1336108161, 1336513734, 1337406065, 
+  1338090388, 1339293088, 1340949553, 1344125357, 1345014111, 1345378476, 1345873587, 1345987999, 1347284277, 1348361229, 1348373925, 1350653461, 1352833750, 1353144470, 1353999206, 1355086853, 1355391150, 1356847855, 1361012693, 1361078114, 
+  1365423458, 1367731096, 1368235387, 1370528050, 1372169786, 1373978529, 1374125186, 1375470750, 1377995642, 1379259015, 1379460673, 1379995885, 1382429941, 1382484003, 1382551511, 1382893830, 1383307838, 1383640563, 1384314543, 1385675177, 
+  1386258142, 1386366954, 1387039848, 1387864976, 1388759892, 1389787451, 1389954587, 1390040163, 1390274260, 1390306889, 1390477985, 1390656632, 1391095995, 1391827090, 1392162662, 1394929399, 1395155215, 1395289708, 1396662140, 1399673078, 
+  1399854717, 1400070607, 1400929335, 1401058771, 1401980800, 1402735006, 1403206383, 1403771494, 1404727477, 1405668251, 1405763119, 1407094080, 1408805003, 1409001936, 1412540552, 1413860940, 1414141069, 1414160501, 1415390230, 1417415680, 
+  1417601340, 1420810050, 1424797596, 1424859828, 1426483935, 1427504270, 1428223489, 1430821640, 1431492783, 1431814151, 1434046375, 1434633879, 1435859758, 1437147036, 1440145706, 1441811554, 1444048519, 1444076976, 1445225855, 1445279202, 
+  1445352642, 1447469119, 1447876480, 1450892344, 1451277631, 1451442832, 1453397990, 1455316979, 1455756978, 1457464894, 1459100749, 1459138745, 1459500136, 1459620801, 1462192184, 1462501905, 1462778368, 1462921857, 1463269859, 1466632447, 
+  1466679625, 1467376771, 1468486929, 1470285405, 1471131758, 1471461419, 1471598258, 1472567100, 1473166451, 1473735214, 1475638246, 1480273562, 1480324438, 1480437960, 1482983072, 1485740112, 1486594282, 1487620835, 1489699243, 1491477359, 
+  1492071476, 1492488573, 1496078411, 1496277718, 1497680539, 1497926365, 1498554338, 1500102591, 1501181424, 1502266386, 1502480836, 1502557594, 1504023310, 1505022272, 1505475223, 1506716966, 1507433029, 1508705426, 1510133268, 1512135729, 
+  1512163910, 1513255537, 1514278798, 1514582723, 1514792012, 1515262458, 1515528736, 1515933932, 1519017268, 1520667645, 1520886946, 1521350211, 1522316172, 1524006589, 1524491858, 1525451290, 1527022962, 1528031307, 1533447203, 1533496974, 
+  1534330971, 1536213818, 1537459540, 1538069400, 1538391713, 1539560507, 1541125975, 1541132933, 1541546082, 1545555937, 1546057655, 1546104436, 1547662666, 1548588723, 1548804416, 1550012286, 1550159640, 1550525411, 1550721460, 1551661799, 
+  1553547892, 1554106660, 1555325521, 1555660285, 1558244592, 1558695709, 1560142576, 1561212123, 1561251584, 1561422777, 1561730727, 1563717683, 1564061243, 1565610678, 1565700239, 1566878909, 1568176414, 1568395337, 1568900638, 1569479928, 
+  1570645300, 1571598133, 1572212863, 1575380740, 1577034674, 1577955754, 1579725218, 1581062145, 1581118537, 1581801257, 1584408128, 1585050246, 1588222158, 1588715179, 1589194592, 1590461855, 1590771096, 1593359038, 1593837351, 1594621666, 
+  1596042792, 1596821127, 1597506096, 1598436917, 1599565995, 1599876594, 1600023202, 1600493361, 1601134240, 1601247294, 1601617797, 1602517354, 1602827413, 1602967659, 1603428054, 1604330946, 1604357658, 1605294199, 1605369007, 1607204293, 
+  1607515830, 1607628402, 1607677838, 1609955669, 1610244183, 1610539590, 1611500622, 1611558740, 1611680320, 1612593993, 1612609979, 1614780688, 1617229086, 1618378831, 1619598456, 1619641914, 1620562432, 1620803320, 1622692876, 1622758049, 
+  1624653209, 1627355806, 1628387880, 1628389501, 1629633514, 1629914848, 1630293700, 1630776459, 1631405417, 1631935240, 1633512617, 1634445325, 1635952299, 1636203720, 1636860706, 1640952769, 1642338733, 1642884452, 1643991754, 1644353864, 
+  1645969422, 1646704157, 1648575360, 1649344003, 1649392096, 1650899832, 1652108025, 1653332243, 1655277291, 1656527154, 1657001479, 1658037573, 1659079595, 1659137391, 1660678300, 1663100626, 1663890071, 1665914525, 1666074170, 1667102296, 
+  1667679197, 1672192305, 1673314595, 1674045273, 1675300017, 1675494182, 1677449797, 1678967663, 1679324299, 1679777458, 1680251429, 1680294422, 1681866717, 1682700783, 1683915700, 1684018729, 1685350721, 1685880008, 1686215900, 1686479103, 
+  1686570783, 1687540458, 1687941280, 1688652157, 1689946986, 1690167792, 1691486500, 1691676526, 1695191950, 1695617313, 1697686200, 1702425249, 1704561346, 1705378439, 1705905941, 1706528514, 1708002892, 1708106609, 1708126014, 1709019727, 
+  1709697877, 1709823304, 1710305778, 1711569347, 1711718534, 1711761015, 1711765426, 1712269139, 1712341869, 1713188647, 1713475126, 1714295540, 1715279374, 1715379173, 1715402379, 1716853034, 1719009954, 1719573683, 1721767511, 1723143470, 
+  1725541486, 1726987516, 1727583308, 1730333306, 1730721241, 1731949250, 1732028080, 1733366374, 1733982669, 1737931879, 1738353358, 1740099311, 1740778973, 1740783613, 1742032331, 1742434188, 1745247524, 1745393357, 1745543275, 1746273091, 
+  1746476698, 1746904676, 1747861289, 1749972876, 1750197960, 1750443194, 1750955971, 1752088215, 1752318678, 1752598186, 1753125385, 1754447491, 1755204784, 1757028186, 1758748737, 1760851607, 1761289401, 1763785295, 1764436465, 1765354961, 
+  1765830270, 1767380006, 1768795266, 1770497338, 1771614266, 1771924274, 1772760484, 1774218355, 1774652096, 1774796872, 1775331228, 1775608361, 1775805177, 1776471922, 1776794410, 1778544166, 1781233744, 1781891230, 1783233173, 1783943137, 
+  1784682542, 1787338655, 1787391786, 1788389051, 1790557628, 1792756324, 1793190956, 1793747608, 1797641070, 1799210492, 1800186189, 1800522575, 1802197319, 1802327778, 1803183394, 1806061681, 1807085904, 1807172811, 1808237662, 1811088032, 
+  1815408878, 1816641611, 1817156134, 1820281480, 1821482472, 1821559709, 1822279764, 1822612008, 1823053058, 1826590258, 1826628136, 1826880531, 1827651881, 1833543700, 1833603743, 1834161399, 1834254978, 1834285819, 1834318089, 1834388383, 
+  1834852613, 1835203128, 1835860030, 1835977906, 1836119534, 1837280287, 1838218199, 1839063567, 1840896199, 1846605728, 1847908587, 1848681194, 1849495275, 1849657867, 1849675857, 1852181952, 1855359256, 1858637614, 1858933377, 1859683061, 
+  1860435620, 1860839427, 1862876260, 1864952910, 1866094167, 1868151949, 1868289345, 1869264274, 1870214195, 1870859970, 1871060346, 1871684562, 1873900475, 1874026715, 1874855959, 1876255297, 1878253960, 1878434988, 1879635915, 1880483834, 
+  1880577483, 1881253854, 1883168929, 1883999260, 1886317932, 1890889527, 1890938638, 1891630185, 1891904961, 1892370478, 1893095488, 1896952705, 1897691227, 1897907456, 1898582764, 1900162831, 1900613055, 1901537567, 1902501708, 1902595458, 
+  1904243956, 1904514273, 1904576737, 1904770864, 1905279500, 1906345724, 1907793490, 1908093581, 1909681194, 1910978116, 1912065710, 1913489530, 1913581092, 1913926325, 1914764659, 1914809801, 1915435344, 1916602098, 1918354829, 1920182565, 
+  1924603748, 1926717418, 1927367009, 1928309762, 1928550562, 1930662128, 1930880552, 1931282005, 1931493432, 1932108837, 1933532372, 1933923245, 1935271536, 1936668087, 1938258683, 1939683211, 1942089394, 1943137808, 1943651015, 1944679691, 
+  1945110368, 1946004194, 1948121717, 1949896838, 1950124297, 1951228823, 1952177514, 1952364329, 1952805989, 1953450944, 1953919896, 1955436051, 1957728250, 1957877704, 1958396887, 1959222232, 1959292396, 1961619988, 1961647235, 1962689485, 
+  1963053072, 1965358941, 1965855212, 1967705762, 1968608155, 1968623233, 1969729134, 1970797151, 1971484382, 1971654864, 1977865396, 1980923963, 1981481446, 1983379601, 1984143440, 1984152603, 1985895474, 1986921372, 1989240516, 1992941115, 
+  1994402695, 1997381015, 2001056977, 2002881120, 2004664325, 2004770236, 2005021017, 2005653265, 2005817027, 2006320950, 2006856683, 2009244921, 2010549018, 2011827638, 2014090929, 2014129292, 2015847175, 2016161810, 2016464961, 2017191527, 
+  2018336444, 2022291557, 2022973269, 2023498746, 2024853642, 2027445678, 2027814180, 2027828650, 2027909489, 2028116487, 2029133999, 2029909894, 2033003588, 2033828953, 2034767768, 2036061488, 2036750157, 2037182006, 2038925801, 2039012903, 
+  2041942843, 2042861943, 2044016080, 2045407567, 2045821218, 2046759770, 2047006719, 2047769687, 2048205721, 2048560397, 2049698913, 2052321529, 2052328978, 2052343947, 2053899162, 2054212564, 2055783490, 2060969286, 2061144988, 2063408339, 
+  2064145552, 2064308502, 2066440075, 2066865713, 2067100479, 2067499753, 2068343250, 2068743361, 2069178089, 2070467093, 2072440819, 2073482870, 2074840378, 2074896270, 2076612603, 2077667592, 2078528215, 2079492652, 2080735477, 2081544705, 
+  2082760612, 2084953915, 2085323316, 2087660971, 2088576982, 2088786920, 2088955494, 2089981667, 2090025563, 2090543533, 2090570016, 2090684129, 2091626028, 2093472294, 2094085507, 2094159153, 2094591332, 2094864173, 2097057488, 2098829619, 
+  2100497812, 2103236982, 2105321510, 2105638337, 2105718728, 2105814934, 2108439398, 2109052886, 2109530615, 2109851473, 2113434968, 2114587535, 2115445751, 2116495484, 2117880007, 2118203528, 2118433006, 2118805956, 2118821565, 2119425672, 
+  2122262571, 2122852959, 2123379476, 2124749673, 2125958841, 2126029304, 2126940990, 2126963607, 2128078174, 2128826472, 2129513521, 2129930580, 2130252471, 2130879949, 2131761201, 2131797509, 2133066804, 2135673182, 2139976479, 2140091269, 
+  2140756121, 2141591317, 2142357746, 2143324534, 2143343312, 2143968639, 2145073408, 2145930822
+};
+
diff --git a/apps/riscv-tests/benchmarks/qsort/qsort_gendata.pl b/apps/riscv-tests/benchmarks/qsort/qsort_gendata.pl
new file mode 100755
index 0000000..92fc8fa
--- /dev/null
+++ b/apps/riscv-tests/benchmarks/qsort/qsort_gendata.pl
@@ -0,0 +1,132 @@
+#!/usr/bin/perl -w
+#==========================================================================
+# qsort_gendata.pl
+#
+# Author : Christopher Batten (cbatten@mit.edu)
+# Date   : April 29, 2005
+#
+(our $usageMsg = <<'ENDMSG') =~ s/^\#//gm;
+#
+# Simple script which creates an input data set and the reference data
+# for the qsort benchmark.
+#
+ENDMSG
+
+use strict "vars";
+use warnings;
+no  warnings("once");
+use Getopt::Long;
+
+#--------------------------------------------------------------------------
+# Command line processing
+#--------------------------------------------------------------------------
+
+our %opts;
+
+sub usage()
+{
+
+  print "\n";
+  print " Usage: qsort_gendata.pl [options] \n";
+  print "\n";
+  print " Options:\n";
+  print "  --help  print this message\n";
+  print "  --size  size of input data [250]\n";
+  print "  --seed  random seed [1]\n";
+  print "$usageMsg";
+
+  exit();
+}
+
+sub processCommandLine()
+{
+
+  $opts{"help"} = 0;
+  $opts{"size"} = 250;
+  $opts{"seed"} = 1;
+  Getopt::Long::GetOptions( \%opts, 'help|?', 'size:i', 'seed:i' ) or usage();
+  $opts{"help"} and usage();
+
+}
+
+#--------------------------------------------------------------------------
+# Helper Functions
+#--------------------------------------------------------------------------
+
+sub printArray
+{
+  my $arrayName = $_[0];
+  my $arrayRef  = $_[1];
+
+  my $numCols = 20;
+  my $arrayLen = scalar(@{$arrayRef});
+
+  print "type ".$arrayName."[DATA_SIZE] = \n";
+  print "{\n";
+
+  if ( $arrayLen <= $numCols ) {
+    print "  ";
+    for ( my $i = 0; $i < $arrayLen; $i++ ) {
+      print sprintf("%3d",$arrayRef->[$i]);
+      if ( $i != $arrayLen-1 ) {
+        print ", ";
+      }
+    }
+    print "\n";
+  }
+
+  else {
+    my $numRows = int($arrayLen/$numCols);
+    for ( my $j = 0; $j < $numRows; $j++ ) {
+      print "  ";
+      for ( my $i = 0; $i < $numCols; $i++ ) {
+        my $index = $j*$numCols + $i;
+        print sprintf("%3d",$arrayRef->[$index]);
+        if ( $index != $arrayLen-1 ) {
+          print ", ";
+        }
+      }
+      print "\n";
+    }
+
+    if ( $arrayLen > ($numRows*$numCols) ) {
+      print "  ";
+      for ( my $i = 0; $i < ($arrayLen-($numRows*$numCols)); $i++ ) {
+        my $index = $numCols*$numRows + $i;
+        print sprintf("%3d",$arrayRef->[$index]);
+        if ( $index != $arrayLen-1 ) {
+          print ", ";
+        }
+      }
+      print "\n";
+    }
+
+  }
+
+  print  "};\n\n";
+}
+
+#--------------------------------------------------------------------------
+# Main
+#--------------------------------------------------------------------------
+
+sub main()
+{
+
+  processCommandLine();
+  srand($opts{"seed"});
+
+  my @values;
+  for ( my $i = 0; $i < $opts{"size"}; $i++ ) {
+    push( @values, int(rand((1<<31)-1)) );
+  }
+  my @sorted = sort { $a <=> $b } @values;
+
+  print "\n\#define DATA_SIZE ".$opts{"size"}." \n\n";
+  printArray( "input_data", \@values );
+  printArray( "verify_data", \@sorted );
+
+}
+
+main();
+
diff --git a/apps/riscv-tests/benchmarks/qsort/qsort_main.c b/apps/riscv-tests/benchmarks/qsort/qsort_main.c
new file mode 100644
index 0000000..18adc25
--- /dev/null
+++ b/apps/riscv-tests/benchmarks/qsort/qsort_main.c
@@ -0,0 +1,153 @@
+// See LICENSE for license details.
+
+//**************************************************************************
+// Quicksort benchmark
+//--------------------------------------------------------------------------
+//
+// This benchmark uses quicksort to sort an array of integers. The
+// implementation is largely adapted from Numerical Recipes for C. The
+// input data (and reference data) should be generated using the
+// qsort_gendata.pl perl script and dumped to a file named
+// dataset1.h.
+
+#include "util.h"
+#include <string.h>
+#include <assert.h>
+
+// The INSERTION_THRESHOLD is the size of the subarray when the
+// algorithm switches to using an insertion sort instead of
+// quick sort.
+
+#define INSERTION_THRESHOLD 10
+
+// NSTACK is the required auxiliary storage.
+// It must be at least 2*lg(DATA_SIZE)
+
+#define NSTACK 50
+
+//--------------------------------------------------------------------------
+// Input/Reference Data
+
+#define type int
+#include "dataset1.h"
+
+// Swap macro for swapping two values.
+
+#define SWAP(a,b) do { typeof(a) temp=(a);(a)=(b);(b)=temp; } while (0)
+#define SWAP_IF_GREATER(a, b) do { if ((a) > (b)) SWAP(a, b); } while (0)
+
+//--------------------------------------------------------------------------
+// Quicksort function
+
+static void insertion_sort(size_t n, type arr[])
+{
+  type *i, *j;
+  type value;
+  for (i = arr+1; i < arr+n; i++)
+  {
+    value = *i;
+    j = i;
+    while (value < *(j-1))
+    {
+      *j = *(j-1);
+      if (--j == arr)
+        break;
+    }
+    *j = value;
+  }
+}
+
+static void selection_sort(size_t n, type arr[])
+{
+  for (type* i = arr; i < arr+n-1; i++)
+    for (type* j = i+1; j < arr+n; j++)
+      SWAP_IF_GREATER(*i, *j);
+}
+
+void sort(size_t n, type arr[])
+{
+  type* ir = arr+n;
+  type* l = arr+1;
+  type* stack[NSTACK];
+  type** stackp = stack;
+
+  for (;;)
+  {
+    // Insertion sort when subarray small enough.
+    if ( ir-l < INSERTION_THRESHOLD )
+    {
+      insertion_sort(ir - l + 1, l - 1);
+
+      if ( stackp == stack ) break;
+
+      // Pop stack and begin a new round of partitioning.
+      ir = *stackp--;
+      l = *stackp--;
+    }
+    else
+    {
+      // Choose median of left, center, and right elements as
+      // partitioning element a. Also rearrange so that a[l-1] <= a[l] <= a[ir-].
+      SWAP(arr[((l-arr) + (ir-arr))/2-1], l[0]);
+      SWAP_IF_GREATER(l[-1], ir[-1]);
+      SWAP_IF_GREATER(l[0], ir[-1]);
+      SWAP_IF_GREATER(l[-1], l[0]);
+
+      // Initialize pointers for partitioning.
+      type* i = l+1;
+      type* j = ir;
+
+      // Partitioning element.
+      type a = l[0];
+
+      for (;;) {                    // Beginning of innermost loop.
+        while (*i++ < a);           // Scan up to find element > a.
+        while (*(j-- - 2) > a);     // Scan down to find element < a.
+        if (j < i) break;           // Pointers crossed. Partitioning complete.
+        SWAP(i[-1], j[-1]);         // Exchange elements.
+      }                             // End of innermost loop.
+
+      // Insert partitioning element.
+      l[0] = j[-1];
+      j[-1] = a;
+      stackp += 2;
+
+      // Push pointers to larger subarray on stack,
+      // process smaller subarray immediately.
+
+      if ( ir-i+1 >= j-l )
+      {
+        stackp[0] = ir;
+        stackp[-1] = i;
+        ir = j-1;
+      }
+      else
+      {
+        stackp[0] = j-1;
+        stackp[-1] = l;
+        l = i;
+      }
+    }
+  }
+}
+
+//--------------------------------------------------------------------------
+// Main
+
+int main( int argc, char* argv[] )
+{
+#if PREALLOCATE
+  // If needed we preallocate everything in the caches
+  sort(DATA_SIZE, verify_data);
+  if (verify(DATA_SIZE, input_data, input_data))
+    return 1;
+#endif
+
+  // Do the sort
+  setStats(1);
+  sort( DATA_SIZE, input_data );
+  setStats(0);
+
+  // Check the results
+  return verify( DATA_SIZE, input_data, verify_data );
+}
diff --git a/apps/riscv-tests/benchmarks/readme.txt b/apps/riscv-tests/benchmarks/readme.txt
new file mode 100644
index 0000000..d90fe2d
--- /dev/null
+++ b/apps/riscv-tests/benchmarks/readme.txt
@@ -0,0 +1,48 @@
+*************************************************************************
+Benchmarks for RISCV Processor
+-------------------------------------------------------------------------
+
+The benchmarks make use of the RISCV C compiler toolchain. You will need
+to include a bmark.mk makefile fragment in each benchmark directory. The
+fragment should include the object files and a rule to actually link
+these object files into an executable. There are a couple important
+points to make about the toolchain.
+
+ + The toolchain sets the stack pointer to memory address 0x20000 so your
+   main memory _must_ be larger than 0x20000 bytes or else the stack will
+   get wrapped around and overwrite program data.
+
+ + The stack grows down from 0x20000 and your program is loaded at 0x1000.
+   If you have a very large program and have lots of very big arrays
+   declared on the stack your stack could overwrite your program. Be aware.
+
+ + You cannot use standard clib functions (like memcopy or strcat). You
+   cannot use system calls and thus cannot use printf.
+
+ + You cannot access the simulated command line - ie you cannot use argc
+   and argv within main.
+
+ + You may have to increase the timeout check in your test harness to
+   allow longer programs to run (you can do this from the command line
+   option +max-cycles with the standard test harness)
+
+ + The compiler loads the program at 0x1000. It does not insert exception
+   setup code. So if you are careful with what C you use it will only
+   generate code in the riscv lab1 subset. If you use multiplies, shorts,
+   and chars it could generate mul, lh, and lb instructions. Be aware.
+
+ + You can write assembly in C - you need to do this to write tohost to 1
+   to indicate when the benchmark is done. Look at the example
+   benchmarks to see how this is done. You can find more information
+   about how to write assembly in C here:
+   http://gcc.gnu.org/onlinedocs/gcc/Extended-Asm.html
+
+ + Debugging C compiled code on the RISCV processor is a real pain. It is
+   hard to associate the assembly with the C code and there is no
+   debugger. So if you encounter a bug in your processor when running a C
+   benchmark you can try to debug it, but you might have better luck
+   adding more assembly tests to your test suite.
+
+ + To avoid having the compiler try and use a global pointer (ie using
+   register 28 to point to a space where small global variables are
+   stored) you need to use the -G 0 command line option.
diff --git a/apps/riscv-tests/benchmarks/rsort/dataset1.h b/apps/riscv-tests/benchmarks/rsort/dataset1.h
new file mode 100644
index 0000000..dd1c634
--- /dev/null
+++ b/apps/riscv-tests/benchmarks/rsort/dataset1.h
@@ -0,0 +1,219 @@
+// See LICENSE for license details.
+
+
+#define DATA_SIZE 2048 
+
+type input_data[DATA_SIZE] = 
+{
+  89400484, 976015092, 1792756324, 721524505, 1214379246, 3794415, 402845420, 2126940990, 1611680320, 786566648, 754215794, 1231249235, 284658041, 137796456, 2041942843, 329767814, 1255524953, 465119445, 1731949250, 301663421, 
+  1335861008, 452888789, 14125900, 1231149357, 2002881120, 730845665, 1913581092, 1275331596, 843738737, 1931282005, 1492488573, 490920543, 2066865713, 25885333, 238278880, 1898582764, 250731366, 1612593993, 637659983, 1388759892, 
+  916073297, 1075762632, 675549432, 937987129, 1417415680, 1508705426, 1663890071, 1746476698, 686797873, 2109530615, 1459500136, 324215873, 1881253854, 1496277718, 810387144, 1212974417, 1020037994, 585169793, 2017191527, 556328195, 
+  1160036198, 1391095995, 1223583276, 1094283114, 436580096, 190215907, 603159718, 1513255537, 1631935240, 1440145706, 1303736105, 806638567, 1100041120, 1185825535, 1414141069, 2014090929, 419476096, 1273955724, 175753599, 1223475486, 
+  574236644, 2046759770, 492507266, 1721767511, 726141970, 1256152080, 2029909894, 1382429941, 1939683211, 791188057, 519699747, 1051184301, 1962689485, 706913763, 1776471922, 672906535, 2005817027, 1274190723, 2119425672, 835063788, 
+  421198539, 1169327477, 2064145552, 1396662140, 1218522465, 2105638337, 754247044, 2143968639, 1395289708, 1750443194, 1412540552, 170281493, 389233190, 448284065, 240618723, 2145930822, 1846605728, 1353999206, 140536987, 1821559709, 
+  619972089, 1514278798, 750919339, 2143343312, 304427548, 545066288, 1946004194, 1538069400, 1904770864, 924541465, 567779677, 893302687, 1239665569, 1157666831, 2105814934, 1505475223, 1636203720, 9736243, 518073650, 1063743848, 
+  1029176122, 215018112, 1073871430, 1858933377, 866478506, 1491477359, 477407584, 895562064, 954441852, 638167485, 1550159640, 614612685, 1453397990, 1334857284, 683536723, 168771888, 481561285, 755798022, 2016161810, 1162679490, 
+  619428858, 1390306889, 256860662, 365275089, 1322281086, 1134185180, 1302724177, 621921213, 837554186, 1711761015, 754896618, 1723143470, 978247260, 1548804416, 598016845, 1631405417, 790929190, 1602517354, 770957259, 198186681, 
+  1256015513, 2126029304, 135012885, 583112200, 2118203528, 1834388383, 866964848, 1695191950, 745183293, 1143511498, 1112731797, 478721193, 1202162389, 991159735, 1952364329, 519344323, 1667102296, 770412991, 548632788, 714042223, 
+  1674045273, 1471598258, 1286989824, 1590771096, 308832070, 959354209, 72802865, 670621648, 269167950, 1598436917, 2023498746, 1198213061, 2006856683, 1029832956, 1719009954, 1198254803, 1188748563, 1989240516, 927524181, 1711765426, 
+  1394929399, 769005536, 2047006719, 1915435344, 618681206, 1431814151, 42021322, 1106678970, 107160610, 1199317660, 185592115, 1870214195, 205008108, 1834318089, 948686793, 946311527, 1262399341, 131405125, 1321897861, 1459138745, 
+  821481684, 852388468, 603907009, 20643769, 1737931879, 37141933, 2088576982, 366700722, 1761289401, 625991894, 741078359, 817417567, 969305448, 1152416171, 1101933540, 399456957, 2074896270, 1971484382, 747592875, 1160333307, 
+  1738353358, 2113434968, 1896952705, 1908093581, 1155544307, 117766047, 2034767768, 1316120929, 1507433029, 2045407567, 765386206, 1031625002, 1220915309, 325667019, 1916602098, 16411608, 47463938, 1379995885, 1221108420, 721046824, 
+  1431492783, 1569479928, 909415369, 204514903, 933673987, 1565700239, 341674967, 602907378, 5309142, 849489374, 180599971, 1480437960, 532467027, 1958396887, 106223060, 1025117441, 935689637, 1752088215, 1704561346, 1568395337, 
+  1868289345, 569949159, 1045658065, 274746405, 890461390, 507848158, 793505636, 460893030, 1179525294, 388855203, 1113693824, 13887419, 1909681194, 1082499152, 1466632447, 1281443423, 612289854, 373305330, 568652142, 1383640563, 
+  1073695485, 745777837, 624939139, 1289308008, 1928550562, 148113917, 462743614, 1826880531, 1571598133, 1415390230, 1480273562, 1331593955, 540006359, 261556590, 1690167792, 283430575, 1194709162, 1781233744, 649754857, 1434046375, 
+  1135793759, 932423857, 1170759710, 1048943084, 692845661, 1620562432, 2036750157, 270410557, 617995659, 1347284277, 1771614266, 30992839, 655445946, 22762734, 1695617313, 867628573, 1577034674, 227870124, 2063408339, 1512163910, 
+  787913688, 1758748737, 1553547892, 2072440819, 632611704, 873623623, 2097057488, 1879635915, 1404727477, 1840896199, 1609955669, 186112992, 196401930, 130001148, 814302898, 1420810050, 226906236, 1435859758, 221330186, 329049266, 
+  820933470, 260792255, 1401058771, 210908782, 1774652096, 886978116, 1807085904, 508041515, 767233910, 26687179, 318750634, 910677024, 117260224, 2074840378, 301350822, 464795711, 2053899162, 1335298265, 737518341, 777433215, 
+  1147341731, 1981481446, 1628389501, 1537459540, 1121432739, 1392162662, 1800522575, 644293952, 1273223611, 1906345724, 28256901, 1467376771, 372465453, 78348530, 135678410, 1061864942, 260267972, 1184561748, 287497702, 1154842325, 
+  1629914848, 2084953915, 799717076, 1382484003, 2045821218, 933603111, 84924801, 892939912, 279252402, 651750790, 238566180, 942977997, 1822612008, 1849675857, 939497524, 436630343, 549253917, 1028937430, 579174666, 2124749673, 
+  880456526, 1451442832, 1350653461, 1546104436, 858045289, 2129513521, 1181191604, 727587915, 1619598456, 969076419, 1212628403, 1361078114, 368541415, 333906659, 41714278, 1390274260, 1563717683, 973769771, 1078197595, 918378387, 
+  1672192305, 1094531762, 92620223, 2125958841, 1620803320, 915948205, 174965839, 27377406, 435236973, 1038830638, 1834161399, 305750851, 330474090, 730422541, 1634445325, 840106059, 767880329, 109526756, 2027814180, 367923081, 
+  1983379601, 1293091635, 705851791, 226723092, 1067775613, 2082760612, 951663731, 260670135, 1111213862, 1891630185, 1379259015, 176024101, 594814862, 1870859970, 1689946986, 1290969161, 244975305, 1296857499, 1811088032, 1873900475, 
+  1949896838, 1907793490, 592006699, 1312471120, 509744705, 869853078, 70894786, 503368137, 1686479103, 1602967659, 1214950832, 1131661227, 768185796, 592234826, 1727583308, 949222447, 1760851607, 487888229, 1614780688, 1618378831, 
+  602368560, 2028116487, 183679578, 1561251584, 986240059, 1525451290, 977907387, 432609664, 1528031307, 116766659, 987761406, 1630293700, 90063199, 114202152, 543952312, 855107605, 812328969, 88823122, 1092881031, 304131252, 
+  1505022272, 894769708, 1849495275, 1607515830, 1032748996, 472872107, 1593359038, 1027760887, 1074205225, 1657001479, 1524491858, 387061281, 107095939, 1038018856, 798445606, 1486594282, 1878434988, 1558695709, 2033003588, 373226849, 
+  2133066804, 399991238, 1132597050, 1965358941, 1551661799, 3522194, 935939763, 2070467093, 500734709, 533101409, 1068798385, 998931662, 1500102591, 779093898, 66579049, 1121960111, 749415493, 502323961, 538932155, 259768753, 
+  753296935, 87897457, 539429964, 1675300017, 1232992084, 420106224, 1685350721, 346598567, 1610244183, 1597506096, 1079859867, 944382193, 1770497338, 764935753, 1776794410, 866854601, 365854486, 304211060, 344860208, 1361012693, 
+  1450892344, 622170346, 70003859, 1681866717, 435288306, 687941098, 308700094, 1367731096, 1834285819, 255226842, 193873940, 1833603743, 848402819, 152273285, 231181585, 1754447491, 1838218199, 834410115, 229905664, 2052321529, 
+  338532526, 77482422, 12937811, 35859252, 1645969422, 1501181424, 438711458, 1496078411, 419109342, 1455756978, 1234944834, 1287171290, 470090505, 1900162831, 1130850177, 1772760484, 381571915, 1605369007, 514914429, 994291574, 
+  1502557594, 1099847920, 1627355806, 1148699143, 1519017268, 946489895, 106595511, 921573402, 181567810, 1575380740, 1719573683, 1561730727, 1920182565, 1510133268, 1102603775, 1175885101, 802730854, 185979744, 1058937717, 1716853034, 
+  31596852, 462857778, 1335652095, 47036070, 178901145, 1399673078, 222529745, 128036841, 1708126014, 923768127, 1980923963, 1413860940, 1382551511, 208160226, 1892370478, 2091626028, 1793190956, 1417601340, 515811664, 2076612603, 
+  993525189, 1127173529, 245334962, 134453363, 1206302514, 1344125357, 1139159604, 651536866, 22136821, 1536213818, 2143324534, 879878312, 1944679691, 119285206, 832081018, 1566878909, 876130333, 656954306, 226726100, 937976428, 
+  1202009920, 1938258683, 2014129292, 1274436639, 1102423908, 1485740112, 879552408, 1712269139, 650513248, 1068587688, 434850545, 382422699, 919736727, 2022291557, 1319798607, 2139976479, 772059719, 1033910502, 1120963974, 340231765, 
+  1471131758, 1767380006, 47452797, 1313871880, 399114073, 1462921857, 671848647, 31574181, 230340298, 239990424, 590690783, 1714295540, 833019845, 398244682, 522160389, 900852, 1045627895, 1545555937, 226986415, 208433088, 
+  1502480836, 1611500622, 1933923245, 1588715179, 1655277291, 1749972876, 1386258142, 935490932, 173822937, 702380578, 348131466, 81402251, 875481479, 72939206, 2033828953, 1302272656, 64795664, 2010549018, 1652108025, 58217952, 
+  1871684562, 190536346, 244709448, 949010757, 320137025, 729474445, 133790520, 740536012, 316479300, 1191513656, 1802197319, 785398708, 1816641611, 2052328978, 930367387, 1374125186, 303845878, 852835634, 454359988, 2131761201, 
+  1757028186, 536063430, 1765354961, 726869128, 1209784819, 1790557628, 783427298, 2094085507, 1323798820, 846127236, 1065481253, 572240371, 1745543275, 1011417836, 1970797151, 748527394, 343119399, 723323690, 925975225, 901789102, 
+  1726987516, 535828217, 387611445, 464171383, 1170510314, 1166227930, 1807172811, 1942089394, 985305323, 1368235387, 1691486500, 1568900638, 1876255297, 1249183285, 1710305778, 1763785295, 1733366374, 1444076976, 1629633514, 2105321510, 
+  225091211, 898893218, 863551327, 1441811554, 546340809, 1977865396, 2116495484, 1221726287, 293109484, 1601617797, 1568176414, 1424797596, 1256372950, 298799048, 1708002892, 829450571, 891710357, 1994402695, 1136264020, 372280769, 
+  1520667645, 983043723, 1191079043, 680172541, 813511681, 395360213, 1648575360, 1026342885, 2100497812, 422047044, 509116230, 859612092, 2037182006, 895080280, 494367164, 1732028080, 355614494, 2141591317, 1087251698, 580692625, 
+  225934851, 1581062145, 1515262458, 1497680539, 1711718534, 1774796872, 301673313, 1136356724, 653050943, 109035776, 1709823304, 1340949553, 1365423458, 1155459206, 1203897636, 188016786, 256210446, 633075975, 19227407, 1864952910, 
+  1143853106, 237020443, 1750197960, 856837002, 80321564, 1679324299, 1257507406, 1390040163, 1590461855, 806384435, 1331383316, 2027828650, 1649392096, 1928309762, 1027758817, 1267173039, 123889599, 95752736, 2060969286, 619461174, 
+  1686215900, 1817156134, 2118821565, 1596821127, 1800186189, 212821393, 661318748, 1123331233, 146002907, 953877041, 1771924274, 929351822, 2142357746, 356638683, 1610539590, 2001056977, 368889391, 62209567, 1775608361, 992410365, 
+  1336108161, 696448050, 333820982, 585804640, 1775805177, 809604334, 93191015, 732444124, 1492071476, 1930662128, 174082258, 340442582, 507936866, 362748128, 1607204293, 953383750, 1599876594, 416457166, 571635069, 1356847855, 
+  267174620, 2011827638, 1572212863, 589049769, 2024853642, 1680251429, 914906004, 398911194, 795915364, 1332467446, 688483428, 628445699, 578787063, 2006320950, 1167207852, 336213879, 1640952769, 1778544166, 1617229086, 190807078, 
+  1968608155, 2122852959, 31153367, 1353144470, 2196420, 1395155215, 1948121717, 69118708, 2140091269, 2530146, 1740778973, 1601247294, 1205895814, 858150908, 1878253960, 1967705762, 2090543533, 1702425249, 622114437, 1192155877, 
+  1095403694, 2115445751, 1201124879, 1140728569, 2085323316, 1291025252, 871908043, 863647665, 1245819051, 1468486929, 631022494, 1161580432, 539942311, 1943137808, 1826628136, 259775677, 277497333, 2140756121, 973493986, 1121800211, 
+  1539560507, 1337406065, 186178768, 482917205, 1459100749, 1924603748, 390743779, 1140008063, 517767440, 1764436465, 722260205, 1400929335, 1706528514, 486165509, 1379460673, 206653795, 3159407, 565150174, 688338919, 1223572435, 
+  2122262571, 513009937, 1390656632, 271906847, 1622692876, 1313115559, 2061144988, 411864717, 437710825, 513582947, 305489695, 1713188647, 387273799, 1901537567, 644842409, 1231932661, 356672421, 232170581, 1636860706, 302219842, 
+  2094591332, 1697686200, 1390477985, 1833543700, 1203377492, 50968578, 1332379148, 1514582723, 909273561, 1914809801, 560663378, 1032914339, 1216475831, 113462155, 1165446977, 800591831, 1058677375, 432102601, 2131797509, 1175004233, 
+  1602827413, 878884686, 446372159, 257728183, 800661980, 1387864976, 2004770236, 999229412, 1428223489, 175843632, 74887898, 630393584, 1147793249, 112648605, 1028529524, 1891904961, 1953919896, 481563348, 436476038, 1601134240, 
+  72319656, 1581118537, 460420451, 1904576737, 786297537, 359735266, 1918354829, 4031164, 1679777458, 1144017176, 1462192184, 690865719, 1515933932, 363508800, 1480324438, 1044088643, 2036061488, 218671081, 830595166, 381933797, 
+  108346070, 92271196, 217762975, 1522316172, 1021014457, 1407094080, 857894203, 1968623233, 1459620801, 1345014111, 709651138, 520511102, 2048560397, 1768795266, 1013901419, 1709697877, 1026380990, 1377995642, 1560142576, 542609105, 
+  1534330971, 528024121, 2015847175, 325324443, 1137511396, 1883999260, 1871060346, 715940689, 167653495, 1292049996, 1172290275, 2018336444, 1951228823, 1666074170, 1834852613, 854475547, 308857120, 502558280, 2105718728, 1624653209, 
+  514214340, 976063110, 227427283, 912381406, 785989696, 451448729, 212046016, 2068743361, 117280545, 1936668087, 210748671, 1984152603, 945948973, 1409001936, 1644353864, 1139018167, 678475375, 1279061703, 723930558, 195379046, 
+  1498554338, 999346398, 1665914525, 1473735214, 1561422777, 151416112, 697817760, 1622758049, 607761482, 69889880, 1152335090, 1063657548, 1338090388, 55461678, 1278053582, 837024327, 1914764659, 1049475248, 161502390, 80404202, 
+  624714335, 879380479, 1066787659, 1375470750, 1561212123, 59384706, 966363087, 2044016080, 1178086274, 1159745061, 291298358, 173062659, 1385675177, 652078020, 1802327778, 1555660285, 623909040, 1579725218, 1649344003, 270814499, 
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+};
+
+type verify_data[DATA_SIZE] = 
+{
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+  777433215, 778702716, 778834747, 779093898, 783427298, 785398708, 785989696, 786297537, 786566648, 787106123, 787537653, 787842886, 787913688, 790256415, 790929190, 791188057, 791384486, 793505636, 795915364, 797060176, 
+  798445606, 799527371, 799717076, 800591831, 800661980, 801046035, 801610475, 801824335, 802730854, 804368379, 806384435, 806638567, 806673335, 809604334, 810387144, 810516965, 812094461, 812288356, 812328969, 813511681, 
+  814302898, 815110420, 817417567, 820933470, 821481684, 822635252, 823532901, 827496819, 829450571, 829844031, 830595166, 831270563, 831273447, 832081018, 833019845, 834410115, 835063788, 835506582, 836307572, 836983022, 
+  837024327, 837554186, 839507573, 840106059, 843738737, 844057079, 845698678, 846127236, 846650758, 847255974, 848141854, 848402819, 849489374, 851322111, 851716534, 852338021, 852388468, 852835634, 853545598, 854475547, 
+  855107605, 856621012, 856837002, 857894203, 858045289, 858150908, 859385989, 859612092, 860360715, 863551327, 863647665, 866097476, 866478506, 866854601, 866964848, 867628573, 869853078, 871908043, 873623623, 873976891, 
+  874153641, 875481479, 876130333, 878692218, 878744414, 878884686, 879380479, 879552408, 879878312, 880456526, 880688023, 881982271, 882282387, 882484999, 885873448, 886978116, 887841601, 890461390, 891710357, 892574149, 
+  892939912, 893302687, 893597382, 893957771, 894769708, 894937325, 895080280, 895562064, 898893218, 901789102, 904287249, 906899219, 907401151, 907554175, 909273561, 909415369, 910677024, 912381406, 914906004, 915948205, 
+  916073297, 917508270, 918378387, 919736727, 921573402, 922186026, 923478775, 923768127, 924541465, 925604268, 925975225, 926200942, 926939064, 927045887, 927524181, 928179911, 928836931, 929351822, 930367387, 932423857, 
+  933603111, 933673987, 934048997, 934700736, 935490932, 935573751, 935689637, 935939763, 937081176, 937976428, 937987129, 939497524, 941471466, 942977997, 943871886, 944382193, 945948973, 946311527, 946425090, 946489895, 
+  948686793, 949010757, 949222447, 950009818, 951256529, 951663731, 952824381, 953383750, 953877041, 954441852, 954915740, 954942098, 957037315, 958774566, 959354209, 960982228, 964348374, 965490116, 965562483, 966363087, 
+  968848252, 969076419, 969305448, 969358207, 969500483, 970194422, 972058766, 973367349, 973490494, 973493986, 973769771, 976015092, 976063110, 977454680, 977907387, 978247260, 980702956, 980863365, 983043723, 985305323, 
+  986240059, 987761406, 988431201, 991159735, 991874801, 992410365, 993525189, 993786972, 994291574, 997649666, 998931662, 999229412, 999346398, 999899279, 1007042224, 1010427073, 1011417836, 1011473945, 1011596733, 1012611702, 
+  1013901419, 1016469330, 1016615447, 1020037994, 1021014457, 1022861633, 1025117441, 1026342885, 1026380990, 1027758817, 1027760887, 1028529524, 1028820236, 1028937430, 1029176122, 1029338154, 1029832956, 1031625002, 1032748996, 1032914339, 
+  1033910502, 1035075488, 1035956563, 1037521069, 1038018856, 1038830638, 1042790263, 1042942541, 1043920511, 1044088643, 1045627895, 1045658065, 1047336724, 1048943084, 1049475248, 1050373352, 1050512245, 1051184301, 1054066034, 1057003814, 
+  1058677375, 1058937717, 1061864942, 1063657548, 1063743848, 1063768444, 1063839036, 1065136414, 1065481253, 1066014062, 1066787659, 1067775613, 1068587688, 1068798385, 1069450170, 1073695485, 1073871430, 1074205225, 1075762632, 1076198976, 
+  1078197595, 1079859867, 1082499152, 1082864732, 1082881617, 1085326591, 1087195269, 1087245613, 1087251698, 1087556673, 1087742330, 1089408490, 1089710430, 1090104632, 1090386021, 1090443335, 1092382563, 1092881031, 1094283114, 1094531762, 
+  1095403694, 1099847920, 1100041120, 1100089300, 1101722351, 1101933540, 1102423908, 1102603775, 1103013140, 1106678970, 1110387095, 1111213862, 1112056034, 1112731797, 1113693824, 1120963974, 1121432739, 1121800211, 1121960111, 1122768484, 
+  1123331233, 1123555638, 1125104871, 1125822965, 1126017956, 1127173529, 1127911377, 1128895624, 1130850177, 1131661227, 1132597050, 1133473813, 1133910514, 1134185180, 1135793759, 1136264020, 1136356724, 1137511396, 1139018167, 1139159604, 
+  1140008063, 1140728569, 1143168018, 1143511498, 1143853106, 1144017176, 1144669754, 1147341731, 1147793249, 1148699143, 1149113346, 1150780072, 1152335090, 1152416171, 1154842325, 1155459206, 1155544307, 1156824624, 1157666831, 1159675637, 
+  1159745061, 1159898528, 1160036198, 1160186023, 1160285859, 1160333307, 1160537912, 1161580432, 1162679490, 1165446977, 1166227930, 1167207852, 1168465459, 1169327477, 1170510314, 1170759710, 1171051384, 1171925835, 1172290275, 1173840088, 
+  1173889730, 1174587016, 1175004233, 1175885101, 1178086274, 1178260876, 1179525294, 1180063064, 1180525723, 1181191604, 1183464058, 1184561748, 1185825535, 1188076819, 1188748563, 1189141368, 1189323192, 1190890142, 1191079043, 1191513656, 
+  1192155877, 1194041213, 1194709162, 1198213061, 1198254803, 1198857033, 1199317660, 1201124879, 1201152163, 1201659316, 1202009920, 1202162389, 1203377492, 1203897636, 1204992245, 1205522527, 1205895814, 1206302514, 1209784819, 1209991461, 
+  1212628403, 1212974417, 1214379246, 1214950832, 1215063385, 1215103809, 1216475831, 1217804021, 1218522465, 1220523503, 1220915309, 1221108420, 1221726287, 1222554291, 1223475486, 1223572435, 1223583276, 1228817775, 1230449468, 1231111410, 
+  1231149357, 1231249235, 1231639101, 1231932661, 1232567659, 1232992084, 1233022905, 1234157881, 1234944834, 1239665569, 1240287664, 1245819051, 1247518755, 1249086623, 1249183285, 1250360726, 1255524953, 1256015513, 1256152080, 1256372950, 
+  1257507406, 1260859787, 1262399341, 1267173039, 1269707634, 1271370220, 1273223611, 1273955724, 1274190723, 1274436639, 1275331596, 1275500498, 1276205250, 1278053582, 1278777407, 1278794420, 1279061703, 1279981214, 1281443423, 1285258674, 
+  1286989824, 1287171290, 1287830283, 1288684086, 1289308008, 1290629443, 1290969161, 1291025252, 1291070368, 1291438802, 1292049996, 1292413659, 1293091635, 1294873695, 1296857499, 1298200648, 1299667896, 1302272656, 1302724177, 1303736105, 
+  1305071296, 1308872551, 1310177444, 1312064004, 1312471120, 1313115559, 1313640711, 1313871880, 1316120929, 1317077622, 1317201705, 1318032594, 1318900244, 1319798607, 1321897861, 1322281086, 1322696419, 1323798820, 1324123626, 1324723894, 
+  1325008187, 1325083914, 1326017288, 1328272543, 1328885292, 1331383316, 1331593955, 1332379148, 1332467446, 1332620900, 1332937015, 1333790305, 1334857284, 1335236478, 1335298265, 1335652095, 1335861008, 1336108161, 1336513734, 1337406065, 
+  1338090388, 1339293088, 1340949553, 1344125357, 1345014111, 1345378476, 1345873587, 1345987999, 1347284277, 1348361229, 1348373925, 1350653461, 1352833750, 1353144470, 1353999206, 1355086853, 1355391150, 1356847855, 1361012693, 1361078114, 
+  1365423458, 1367731096, 1368235387, 1370528050, 1372169786, 1373978529, 1374125186, 1375470750, 1377995642, 1379259015, 1379460673, 1379995885, 1382429941, 1382484003, 1382551511, 1382893830, 1383307838, 1383640563, 1384314543, 1385675177, 
+  1386258142, 1386366954, 1387039848, 1387864976, 1388759892, 1389787451, 1389954587, 1390040163, 1390274260, 1390306889, 1390477985, 1390656632, 1391095995, 1391827090, 1392162662, 1394929399, 1395155215, 1395289708, 1396662140, 1399673078, 
+  1399854717, 1400070607, 1400929335, 1401058771, 1401980800, 1402735006, 1403206383, 1403771494, 1404727477, 1405668251, 1405763119, 1407094080, 1408805003, 1409001936, 1412540552, 1413860940, 1414141069, 1414160501, 1415390230, 1417415680, 
+  1417601340, 1420810050, 1424797596, 1424859828, 1426483935, 1427504270, 1428223489, 1430821640, 1431492783, 1431814151, 1434046375, 1434633879, 1435859758, 1437147036, 1440145706, 1441811554, 1444048519, 1444076976, 1445225855, 1445279202, 
+  1445352642, 1447469119, 1447876480, 1450892344, 1451277631, 1451442832, 1453397990, 1455316979, 1455756978, 1457464894, 1459100749, 1459138745, 1459500136, 1459620801, 1462192184, 1462501905, 1462778368, 1462921857, 1463269859, 1466632447, 
+  1466679625, 1467376771, 1468486929, 1470285405, 1471131758, 1471461419, 1471598258, 1472567100, 1473166451, 1473735214, 1475638246, 1480273562, 1480324438, 1480437960, 1482983072, 1485740112, 1486594282, 1487620835, 1489699243, 1491477359, 
+  1492071476, 1492488573, 1496078411, 1496277718, 1497680539, 1497926365, 1498554338, 1500102591, 1501181424, 1502266386, 1502480836, 1502557594, 1504023310, 1505022272, 1505475223, 1506716966, 1507433029, 1508705426, 1510133268, 1512135729, 
+  1512163910, 1513255537, 1514278798, 1514582723, 1514792012, 1515262458, 1515528736, 1515933932, 1519017268, 1520667645, 1520886946, 1521350211, 1522316172, 1524006589, 1524491858, 1525451290, 1527022962, 1528031307, 1533447203, 1533496974, 
+  1534330971, 1536213818, 1537459540, 1538069400, 1538391713, 1539560507, 1541125975, 1541132933, 1541546082, 1545555937, 1546057655, 1546104436, 1547662666, 1548588723, 1548804416, 1550012286, 1550159640, 1550525411, 1550721460, 1551661799, 
+  1553547892, 1554106660, 1555325521, 1555660285, 1558244592, 1558695709, 1560142576, 1561212123, 1561251584, 1561422777, 1561730727, 1563717683, 1564061243, 1565610678, 1565700239, 1566878909, 1568176414, 1568395337, 1568900638, 1569479928, 
+  1570645300, 1571598133, 1572212863, 1575380740, 1577034674, 1577955754, 1579725218, 1581062145, 1581118537, 1581801257, 1584408128, 1585050246, 1588222158, 1588715179, 1589194592, 1590461855, 1590771096, 1593359038, 1593837351, 1594621666, 
+  1596042792, 1596821127, 1597506096, 1598436917, 1599565995, 1599876594, 1600023202, 1600493361, 1601134240, 1601247294, 1601617797, 1602517354, 1602827413, 1602967659, 1603428054, 1604330946, 1604357658, 1605294199, 1605369007, 1607204293, 
+  1607515830, 1607628402, 1607677838, 1609955669, 1610244183, 1610539590, 1611500622, 1611558740, 1611680320, 1612593993, 1612609979, 1614780688, 1617229086, 1618378831, 1619598456, 1619641914, 1620562432, 1620803320, 1622692876, 1622758049, 
+  1624653209, 1627355806, 1628387880, 1628389501, 1629633514, 1629914848, 1630293700, 1630776459, 1631405417, 1631935240, 1633512617, 1634445325, 1635952299, 1636203720, 1636860706, 1640952769, 1642338733, 1642884452, 1643991754, 1644353864, 
+  1645969422, 1646704157, 1648575360, 1649344003, 1649392096, 1650899832, 1652108025, 1653332243, 1655277291, 1656527154, 1657001479, 1658037573, 1659079595, 1659137391, 1660678300, 1663100626, 1663890071, 1665914525, 1666074170, 1667102296, 
+  1667679197, 1672192305, 1673314595, 1674045273, 1675300017, 1675494182, 1677449797, 1678967663, 1679324299, 1679777458, 1680251429, 1680294422, 1681866717, 1682700783, 1683915700, 1684018729, 1685350721, 1685880008, 1686215900, 1686479103, 
+  1686570783, 1687540458, 1687941280, 1688652157, 1689946986, 1690167792, 1691486500, 1691676526, 1695191950, 1695617313, 1697686200, 1702425249, 1704561346, 1705378439, 1705905941, 1706528514, 1708002892, 1708106609, 1708126014, 1709019727, 
+  1709697877, 1709823304, 1710305778, 1711569347, 1711718534, 1711761015, 1711765426, 1712269139, 1712341869, 1713188647, 1713475126, 1714295540, 1715279374, 1715379173, 1715402379, 1716853034, 1719009954, 1719573683, 1721767511, 1723143470, 
+  1725541486, 1726987516, 1727583308, 1730333306, 1730721241, 1731949250, 1732028080, 1733366374, 1733982669, 1737931879, 1738353358, 1740099311, 1740778973, 1740783613, 1742032331, 1742434188, 1745247524, 1745393357, 1745543275, 1746273091, 
+  1746476698, 1746904676, 1747861289, 1749972876, 1750197960, 1750443194, 1750955971, 1752088215, 1752318678, 1752598186, 1753125385, 1754447491, 1755204784, 1757028186, 1758748737, 1760851607, 1761289401, 1763785295, 1764436465, 1765354961, 
+  1765830270, 1767380006, 1768795266, 1770497338, 1771614266, 1771924274, 1772760484, 1774218355, 1774652096, 1774796872, 1775331228, 1775608361, 1775805177, 1776471922, 1776794410, 1778544166, 1781233744, 1781891230, 1783233173, 1783943137, 
+  1784682542, 1787338655, 1787391786, 1788389051, 1790557628, 1792756324, 1793190956, 1793747608, 1797641070, 1799210492, 1800186189, 1800522575, 1802197319, 1802327778, 1803183394, 1806061681, 1807085904, 1807172811, 1808237662, 1811088032, 
+  1815408878, 1816641611, 1817156134, 1820281480, 1821482472, 1821559709, 1822279764, 1822612008, 1823053058, 1826590258, 1826628136, 1826880531, 1827651881, 1833543700, 1833603743, 1834161399, 1834254978, 1834285819, 1834318089, 1834388383, 
+  1834852613, 1835203128, 1835860030, 1835977906, 1836119534, 1837280287, 1838218199, 1839063567, 1840896199, 1846605728, 1847908587, 1848681194, 1849495275, 1849657867, 1849675857, 1852181952, 1855359256, 1858637614, 1858933377, 1859683061, 
+  1860435620, 1860839427, 1862876260, 1864952910, 1866094167, 1868151949, 1868289345, 1869264274, 1870214195, 1870859970, 1871060346, 1871684562, 1873900475, 1874026715, 1874855959, 1876255297, 1878253960, 1878434988, 1879635915, 1880483834, 
+  1880577483, 1881253854, 1883168929, 1883999260, 1886317932, 1890889527, 1890938638, 1891630185, 1891904961, 1892370478, 1893095488, 1896952705, 1897691227, 1897907456, 1898582764, 1900162831, 1900613055, 1901537567, 1902501708, 1902595458, 
+  1904243956, 1904514273, 1904576737, 1904770864, 1905279500, 1906345724, 1907793490, 1908093581, 1909681194, 1910978116, 1912065710, 1913489530, 1913581092, 1913926325, 1914764659, 1914809801, 1915435344, 1916602098, 1918354829, 1920182565, 
+  1924603748, 1926717418, 1927367009, 1928309762, 1928550562, 1930662128, 1930880552, 1931282005, 1931493432, 1932108837, 1933532372, 1933923245, 1935271536, 1936668087, 1938258683, 1939683211, 1942089394, 1943137808, 1943651015, 1944679691, 
+  1945110368, 1946004194, 1948121717, 1949896838, 1950124297, 1951228823, 1952177514, 1952364329, 1952805989, 1953450944, 1953919896, 1955436051, 1957728250, 1957877704, 1958396887, 1959222232, 1959292396, 1961619988, 1961647235, 1962689485, 
+  1963053072, 1965358941, 1965855212, 1967705762, 1968608155, 1968623233, 1969729134, 1970797151, 1971484382, 1971654864, 1977865396, 1980923963, 1981481446, 1983379601, 1984143440, 1984152603, 1985895474, 1986921372, 1989240516, 1992941115, 
+  1994402695, 1997381015, 2001056977, 2002881120, 2004664325, 2004770236, 2005021017, 2005653265, 2005817027, 2006320950, 2006856683, 2009244921, 2010549018, 2011827638, 2014090929, 2014129292, 2015847175, 2016161810, 2016464961, 2017191527, 
+  2018336444, 2022291557, 2022973269, 2023498746, 2024853642, 2027445678, 2027814180, 2027828650, 2027909489, 2028116487, 2029133999, 2029909894, 2033003588, 2033828953, 2034767768, 2036061488, 2036750157, 2037182006, 2038925801, 2039012903, 
+  2041942843, 2042861943, 2044016080, 2045407567, 2045821218, 2046759770, 2047006719, 2047769687, 2048205721, 2048560397, 2049698913, 2052321529, 2052328978, 2052343947, 2053899162, 2054212564, 2055783490, 2060969286, 2061144988, 2063408339, 
+  2064145552, 2064308502, 2066440075, 2066865713, 2067100479, 2067499753, 2068343250, 2068743361, 2069178089, 2070467093, 2072440819, 2073482870, 2074840378, 2074896270, 2076612603, 2077667592, 2078528215, 2079492652, 2080735477, 2081544705, 
+  2082760612, 2084953915, 2085323316, 2087660971, 2088576982, 2088786920, 2088955494, 2089981667, 2090025563, 2090543533, 2090570016, 2090684129, 2091626028, 2093472294, 2094085507, 2094159153, 2094591332, 2094864173, 2097057488, 2098829619, 
+  2100497812, 2103236982, 2105321510, 2105638337, 2105718728, 2105814934, 2108439398, 2109052886, 2109530615, 2109851473, 2113434968, 2114587535, 2115445751, 2116495484, 2117880007, 2118203528, 2118433006, 2118805956, 2118821565, 2119425672, 
+  2122262571, 2122852959, 2123379476, 2124749673, 2125958841, 2126029304, 2126940990, 2126963607, 2128078174, 2128826472, 2129513521, 2129930580, 2130252471, 2130879949, 2131761201, 2131797509, 2133066804, 2135673182, 2139976479, 2140091269, 
+  2140756121, 2141591317, 2142357746, 2143324534, 2143343312, 2143968639, 2145073408, 2145930822
+};
+
diff --git a/apps/riscv-tests/benchmarks/rsort/rsort.c b/apps/riscv-tests/benchmarks/rsort/rsort.c
new file mode 100644
index 0000000..7ffc12a
--- /dev/null
+++ b/apps/riscv-tests/benchmarks/rsort/rsort.c
@@ -0,0 +1,122 @@
+// See LICENSE for license details.
+
+//**************************************************************************
+// Quicksort benchmark
+//--------------------------------------------------------------------------
+//
+// This benchmark uses quicksort to sort an array of integers. The
+// implementation is largely adapted from Numerical Recipes for C. The
+// input data (and reference data) should be generated using the
+// qsort_gendata.pl perl script and dumped to a file named
+// dataset1.h
+
+#include "util.h"
+#include <string.h>
+#include <limits.h>
+
+//--------------------------------------------------------------------------
+// Input/Reference Data
+
+#define type unsigned int
+#include "dataset1.h"
+
+#define LOG_BASE 8
+#define BASE (1 << LOG_BASE)
+
+#if 0
+# define fetch_add(ptr, inc) __sync_fetch_and_add(ptr, inc)
+#else
+# define fetch_add(ptr, inc) ((*(ptr) += (inc)) - (inc))
+#endif
+
+void sort(size_t n, type* arrIn, type* scratchIn)
+{
+  size_t log_exp = 0;
+  size_t buckets[BASE];
+  size_t *bucket = buckets;
+  asm("":"+r"(bucket));
+  type *arr = arrIn, *scratch = scratchIn, *p;
+  size_t *b;
+ 
+  while (log_exp < CHAR_BIT * sizeof(type))
+  {
+    for (b = bucket; b < bucket + BASE; b++)
+      *b = 0;
+
+    for (p = arr; p < &arr[n-3]; p += 4)
+    {
+      type a0 = p[0];
+      type a1 = p[1];
+      type a2 = p[2];
+      type a3 = p[3];
+      fetch_add(&bucket[(a0 >> log_exp) % BASE], 1);
+      fetch_add(&bucket[(a1 >> log_exp) % BASE], 1);
+      fetch_add(&bucket[(a2 >> log_exp) % BASE], 1);
+      fetch_add(&bucket[(a3 >> log_exp) % BASE], 1);
+    }
+    for ( ; p < &arr[n]; p++)
+      bucket[(*p >> log_exp) % BASE]++;
+
+    size_t prev = bucket[0];
+    prev += fetch_add(&bucket[1], prev);
+    for (b = &bucket[2]; b < bucket + BASE; b += 2)
+    {
+      prev += fetch_add(&b[0], prev);
+      prev += fetch_add(&b[1], prev);
+    }
+    static_assert(BASE % 2 == 0);
+
+    for (p = &arr[n-1]; p >= &arr[3]; p -= 4)
+    {
+      type a0 = p[-0];
+      type a1 = p[-1];
+      type a2 = p[-2];
+      type a3 = p[-3];
+      size_t* pb0 = &bucket[(a0 >> log_exp) % BASE];
+      size_t* pb1 = &bucket[(a1 >> log_exp) % BASE];
+      size_t* pb2 = &bucket[(a2 >> log_exp) % BASE];
+      size_t* pb3 = &bucket[(a3 >> log_exp) % BASE];
+      type* s0 = scratch + fetch_add(pb0, -1);
+      type* s1 = scratch + fetch_add(pb1, -1);
+      type* s2 = scratch + fetch_add(pb2, -1);
+      type* s3 = scratch + fetch_add(pb3, -1);
+      s0[-1] = a0;
+      s1[-1] = a1;
+      s2[-1] = a2;
+      s3[-1] = a3;
+    }
+    for ( ; p >= &arr[0]; p--)
+      scratch[--bucket[(*p >> log_exp) % BASE]] = *p;
+
+    type* tmp = arr;
+    arr = scratch;
+    scratch = tmp;
+
+    log_exp += LOG_BASE;
+  }
+  if (arr != arrIn)
+    memcpy(arr, scratch, n*sizeof(type));
+}
+
+//--------------------------------------------------------------------------
+// Main
+
+int main( int argc, char* argv[] )
+{
+  static type scratch[DATA_SIZE];
+
+#if PREALLOCATE
+  // If needed we preallocate everything in the caches
+  sort(DATA_SIZE, verify_data, scratch);
+  if (verify(DATA_SIZE, input_data, input_data))
+    return 1;
+#endif
+
+  // Do the sort
+  setStats(1);
+  sort(DATA_SIZE, input_data, scratch);
+  setStats(0);
+
+  // Check the results
+  return verify( DATA_SIZE, input_data, verify_data );
+}
diff --git a/apps/riscv-tests/benchmarks/spmv/dataset1.h b/apps/riscv-tests/benchmarks/spmv/dataset1.h
new file mode 100644
index 0000000..52e49c5
--- /dev/null
+++ b/apps/riscv-tests/benchmarks/spmv/dataset1.h
@@ -0,0 +1,6312 @@
+#define R 500
+#define C 500
+#define NNZ 2399
+const double val[2399] = {
+  566,
+  508,
+  850,
+  780,
+  944,
+  598,
+  772,
+  880,
+  764,
+  656,
+  138,
+  757,
+  929,
+  234,
+  168,
+  629,
+  639,
+  434,
+  849,
+  793,
+  203,
+  811,
+  250,
+  770,
+  322,
+  535,
+  826,
+  609,
+  899,
+  926,
+  211,
+  755,
+  900,
+  691,
+  386,
+  821,
+  454,
+  791,
+  849,
+  256,
+  821,
+  29,
+  679,
+  944,
+  55,
+  689,
+  453,
+  631,
+  799,
+  854,
+  545,
+  97,
+  337,
+  258,
+  695,
+  667,
+  581,
+  104,
+  491,
+  517,
+  761,
+  369,
+  316,
+  42,
+  86,
+  432,
+  954,
+  736,
+  333,
+  321,
+  184,
+  920,
+  258,
+  949,
+  604,
+  907,
+  70,
+  453,
+  796,
+  102,
+  3,
+  105,
+  371,
+  388,
+  153,
+  908,
+  176,
+  567,
+  334,
+  973,
+  911,
+  323,
+  681,
+  300,
+  265,
+  711,
+  871,
+  870,
+  463,
+  969,
+  535,
+  688,
+  276,
+  908,
+  384,
+  988,
+  256,
+  416,
+  258,
+  523,
+  80,
+  911,
+  241,
+  191,
+  411,
+  127,
+  894,
+  259,
+  664,
+  129,
+  609,
+  146,
+  763,
+  109,
+  369,
+  881,
+  878,
+  224,
+  635,
+  498,
+  460,
+  363,
+  481,
+  222,
+  761,
+  489,
+  753,
+  62,
+  261,
+  389,
+  351,
+  189,
+  319,
+  557,
+  5,
+  485,
+  806,
+  119,
+  366,
+  85,
+  123,
+  918,
+  66,
+  205,
+  786,
+  313,
+  555,
+  22,
+  760,
+  904,
+  255,
+  912,
+  950,
+  676,
+  342,
+  736,
+  251,
+  170,
+  923,
+  790,
+  312,
+  716,
+  648,
+  57,
+  676,
+  972,
+  250,
+  215,
+  792,
+  798,
+  915,
+  61,
+  381,
+  897,
+  686,
+  568,
+  393,
+  969,
+  893,
+  205,
+  721,
+  684,
+  38,
+  667,
+  704,
+  750,
+  364,
+  123,
+  158,
+  892,
+  306,
+  409,
+  188,
+  394,
+  554,
+  602,
+  59,
+  9,
+  987,
+  897,
+  332,
+  873,
+  770,
+  632,
+  434,
+  598,
+  599,
+  207,
+  211,
+  410,
+  768,
+  708,
+  462,
+  687,
+  300,
+  864,
+  839,
+  183,
+  21,
+  282,
+  990,
+  578,
+  952,
+  42,
+  149,
+  235,
+  777,
+  156,
+  568,
+  400,
+  783,
+  238,
+  390,
+  108,
+  422,
+  392,
+  414,
+  338,
+  524,
+  535,
+  893,
+  160,
+  163,
+  798,
+  836,
+  662,
+  181,
+  946,
+  774,
+  113,
+  438,
+  721,
+  631,
+  577,
+  739,
+  62,
+  928,
+  523,
+  352,
+  603,
+  974,
+  291,
+  47,
+  875,
+  260,
+  754,
+  13,
+  890,
+  989,
+  104,
+  22,
+  36,
+  803,
+  39,
+  241,
+  95,
+  589,
+  603,
+  230,
+  471,
+  978,
+  617,
+  603,
+  652,
+  21,
+  755,
+  294,
+  753,
+  609,
+  494,
+  93,
+  387,
+  243,
+  128,
+  777,
+  636,
+  303,
+  665,
+  761,
+  355,
+  611,
+  605,
+  627,
+  834,
+  616,
+  59,
+  109,
+  268,
+  638,
+  117,
+  338,
+  89,
+  95,
+  4,
+  64,
+  575,
+  300,
+  783,
+  453,
+  878,
+  939,
+  984,
+  338,
+  344,
+  138,
+  291,
+  440,
+  748,
+  277,
+  628,
+  511,
+  894,
+  68,
+  412,
+  958,
+  540,
+  672,
+  935,
+  316,
+  519,
+  4,
+  613,
+  501,
+  908,
+  984,
+  820,
+  424,
+  726,
+  592,
+  526,
+  869,
+  330,
+  419,
+  28,
+  540,
+  143,
+  279,
+  79,
+  712,
+  760,
+  306,
+  806,
+  507,
+  807,
+  716,
+  729,
+  163,
+  151,
+  256,
+  873,
+  90,
+  374,
+  89,
+  122,
+  819,
+  253,
+  961,
+  62,
+  208,
+  830,
+  365,
+  231,
+  905,
+  961,
+  340,
+  928,
+  911,
+  83,
+  118,
+  864,
+  310,
+  699,
+  138,
+  221,
+  928,
+  130,
+  775,
+  425,
+  783,
+  519,
+  852,
+  187,
+  795,
+  772,
+  627,
+  709,
+  81,
+  264,
+  359,
+  149,
+  692,
+  178,
+  247,
+  51,
+  869,
+  30,
+  659,
+  190,
+  494,
+  80,
+  531,
+  883,
+  557,
+  170,
+  759,
+  331,
+  588,
+  939,
+  953,
+  407,
+  453,
+  223,
+  919,
+  147,
+  666,
+  165,
+  204,
+  924,
+  178,
+  361,
+  766,
+  455,
+  232,
+  86,
+  194,
+  536,
+  942,
+  671,
+  595,
+  420,
+  543,
+  490,
+  570,
+  547,
+  273,
+  465,
+  776,
+  845,
+  753,
+  591,
+  22,
+  320,
+  569,
+  964,
+  701,
+  483,
+  100,
+  757,
+  514,
+  850,
+  50,
+  451,
+  993,
+  79,
+  79,
+  790,
+  410,
+  409,
+  494,
+  245,
+  881,
+  676,
+  484,
+  821,
+  183,
+  45,
+  343,
+  76,
+  423,
+  855,
+  188,
+  16,
+  355,
+  159,
+  255,
+  705,
+  147,
+  400,
+  997,
+  264,
+  831,
+  644,
+  390,
+  395,
+  485,
+  457,
+  879,
+  478,
+  900,
+  187,
+  699,
+  559,
+  681,
+  947,
+  137,
+  637,
+  150,
+  700,
+  729,
+  166,
+  120,
+  325,
+  841,
+  956,
+  74,
+  576,
+  532,
+  396,
+  157,
+  327,
+  601,
+  707,
+  681,
+  813,
+  593,
+  452,
+  45,
+  936,
+  466,
+  706,
+  546,
+  265,
+  769,
+  71,
+  862,
+  37,
+  764,
+  111,
+  468,
+  844,
+  693,
+  740,
+  128,
+  19,
+  579,
+  894,
+  928,
+  160,
+  787,
+  438,
+  814,
+  274,
+  675,
+  128,
+  451,
+  626,
+  879,
+  931,
+  894,
+  57,
+  181,
+  839,
+  121,
+  728,
+  410,
+  793,
+  292,
+  566,
+  472,
+  893,
+  579,
+  986,
+  159,
+  585,
+  34,
+  485,
+  279,
+  634,
+  353,
+  626,
+  504,
+  574,
+  19,
+  54,
+  489,
+  829,
+  768,
+  246,
+  421,
+  116,
+  267,
+  801,
+  299,
+  279,
+  397,
+  331,
+  396,
+  11,
+  80,
+  682,
+  752,
+  101,
+  832,
+  673,
+  521,
+  42,
+  883,
+  663,
+  905,
+  284,
+  218,
+  59,
+  888,
+  86,
+  623,
+  878,
+  117,
+  157,
+  70,
+  309,
+  877,
+  803,
+  529,
+  666,
+  274,
+  192,
+  667,
+  558,
+  938,
+  383,
+  542,
+  237,
+  377,
+  674,
+  783,
+  638,
+  609,
+  419,
+  359,
+  309,
+  53,
+  65,
+  277,
+  526,
+  853,
+  659,
+  263,
+  280,
+  332,
+  940,
+  336,
+  748,
+  645,
+  227,
+  475,
+  945,
+  924,
+  845,
+  253,
+  798,
+  49,
+  241,
+  761,
+  379,
+  423,
+  680,
+  837,
+  116,
+  378,
+  416,
+  553,
+  802,
+  839,
+  339,
+  424,
+  40,
+  101,
+  744,
+  934,
+  119,
+  217,
+  478,
+  850,
+  998,
+  513,
+  320,
+  966,
+  306,
+  774,
+  442,
+  417,
+  646,
+  652,
+  15,
+  637,
+  199,
+  653,
+  516,
+  380,
+  983,
+  281,
+  196,
+  973,
+  604,
+  378,
+  824,
+  773,
+  835,
+  724,
+  450,
+  321,
+  446,
+  778,
+  935,
+  296,
+  752,
+  27,
+  824,
+  933,
+  145,
+  708,
+  691,
+  433,
+  627,
+  511,
+  619,
+  415,
+  263,
+  680,
+  880,
+  201,
+  700,
+  440,
+  579,
+  545,
+  445,
+  483,
+  499,
+  953,
+  518,
+  77,
+  237,
+  980,
+  923,
+  809,
+  532,
+  877,
+  965,
+  865,
+  597,
+  773,
+  378,
+  177,
+  101,
+  899,
+  448,
+  430,
+  217,
+  403,
+  21,
+  837,
+  410,
+  345,
+  606,
+  373,
+  179,
+  310,
+  634,
+  894,
+  512,
+  289,
+  946,
+  243,
+  725,
+  458,
+  680,
+  579,
+  304,
+  199,
+  721,
+  22,
+  452,
+  761,
+  945,
+  547,
+  418,
+  137,
+  209,
+  622,
+  174,
+  468,
+  223,
+  525,
+  84,
+  470,
+  266,
+  812,
+  950,
+  18,
+  983,
+  319,
+  843,
+  423,
+  862,
+  469,
+  957,
+  919,
+  387,
+  900,
+  382,
+  561,
+  337,
+  711,
+  352,
+  206,
+  737,
+  412,
+  40,
+  17,
+  851,
+  825,
+  910,
+  839,
+  207,
+  879,
+  588,
+  77,
+  867,
+  255,
+  577,
+  1,
+  609,
+  473,
+  88,
+  249,
+  491,
+  180,
+  594,
+  872,
+  870,
+  528,
+  68,
+  31,
+  208,
+  854,
+  190,
+  32,
+  200,
+  225,
+  322,
+  869,
+  425,
+  62,
+  653,
+  919,
+  138,
+  246,
+  501,
+  995,
+  133,
+  852,
+  903,
+  694,
+  482,
+  818,
+  820,
+  922,
+  839,
+  870,
+  391,
+  880,
+  478,
+  602,
+  774,
+  989,
+  139,
+  457,
+  114,
+  282,
+  632,
+  245,
+  452,
+  987,
+  920,
+  134,
+  94,
+  409,
+  124,
+  389,
+  36,
+  434,
+  885,
+  486,
+  269,
+  510,
+  487,
+  644,
+  122,
+  773,
+  13,
+  326,
+  369,
+  252,
+  407,
+  599,
+  182,
+  319,
+  229,
+  684,
+  895,
+  760,
+  703,
+  982,
+  282,
+  645,
+  835,
+  415,
+  182,
+  792,
+  681,
+  113,
+  659,
+  312,
+  998,
+  954,
+  655,
+  588,
+  3,
+  268,
+  125,
+  832,
+  346,
+  832,
+  972,
+  488,
+  709,
+  491,
+  913,
+  441,
+  187,
+  177,
+  90,
+  55,
+  959,
+  126,
+  73,
+  409,
+  606,
+  732,
+  985,
+  833,
+  381,
+  542,
+  559,
+  375,
+  829,
+  50,
+  432,
+  549,
+  996,
+  517,
+  3,
+  366,
+  33,
+  737,
+  451,
+  111,
+  380,
+  362,
+  884,
+  511,
+  199,
+  262,
+  647,
+  531,
+  717,
+  810,
+  675,
+  946,
+  614,
+  425,
+  282,
+  31,
+  436,
+  695,
+  701,
+  653,
+  629,
+  284,
+  109,
+  237,
+  909,
+  269,
+  495,
+  386,
+  327,
+  620,
+  947,
+  782,
+  663,
+  471,
+  818,
+  517,
+  768,
+  494,
+  249,
+  815,
+  725,
+  822,
+  614,
+  324,
+  22,
+  675,
+  118,
+  143,
+  929,
+  498,
+  368,
+  469,
+  482,
+  964,
+  554,
+  999,
+  265,
+  686,
+  782,
+  754,
+  247,
+  125,
+  960,
+  808,
+  788,
+  647,
+  623,
+  615,
+  727,
+  573,
+  813,
+  200,
+  371,
+  141,
+  733,
+  450,
+  515,
+  940,
+  304,
+  13,
+  522,
+  489,
+  948,
+  906,
+  529,
+  500,
+  98,
+  719,
+  174,
+  269,
+  170,
+  609,
+  789,
+  169,
+  645,
+  514,
+  438,
+  254,
+  103,
+  938,
+  306,
+  608,
+  367,
+  889,
+  667,
+  621,
+  276,
+  346,
+  736,
+  210,
+  13,
+  356,
+  914,
+  377,
+  613,
+  714,
+  949,
+  386,
+  770,
+  738,
+  310,
+  382,
+  145,
+  163,
+  470,
+  34,
+  855,
+  951,
+  672,
+  192,
+  942,
+  936,
+  429,
+  906,
+  378,
+  159,
+  665,
+  208,
+  223,
+  575,
+  977,
+  937,
+  81,
+  24,
+  484,
+  941,
+  128,
+  544,
+  811,
+  905,
+  110,
+  707,
+  806,
+  996,
+  509,
+  283,
+  493,
+  846,
+  466,
+  356,
+  807,
+  993,
+  616,
+  790,
+  163,
+  7,
+  931,
+  661,
+  353,
+  499,
+  186,
+  309,
+  107,
+  556,
+  104,
+  702,
+  61,
+  963,
+  255,
+  279,
+  454,
+  941,
+  817,
+  447,
+  786,
+  788,
+  372,
+  919,
+  14,
+  113,
+  41,
+  412,
+  744,
+  372,
+  282,
+  648,
+  248,
+  484,
+  830,
+  104,
+  742,
+  425,
+  802,
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+  711,
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+  460,
+  556,
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+  890,
+  502,
+  473,
+  8,
+  288,
+  57,
+  356,
+  721,
+  112,
+  817,
+  282,
+  123,
+  680,
+  344,
+  21,
+  935,
+  60,
+  287,
+  444,
+  267,
+  30,
+  447,
+  310,
+  922,
+  284,
+  442,
+  651,
+  454,
+  924,
+  771,
+  611,
+  852,
+  986,
+  367,
+  399,
+  115,
+  370,
+  326,
+  765,
+  323,
+  640,
+  906,
+  242,
+  526,
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+  899,
+  624,
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+  796,
+  252,
+  431,
+  99,
+  626,
+  870,
+  928,
+  935,
+  229,
+  286,
+  20,
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+  539,
+  533,
+  379,
+  64,
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+  317,
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+  904,
+  318,
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+  958,
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+  905,
+  849,
+  718,
+  338,
+  342,
+  730,
+  22,
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+  544,
+  25,
+  348,
+  39,
+  719,
+  705,
+  596,
+  908,
+  805,
+  594,
+  7,
+  47,
+  744,
+  148,
+  177,
+  476,
+  866,
+  849,
+  88,
+  246,
+  438,
+  523,
+  156,
+  886,
+  758,
+  605,
+  39,
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+  29,
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+  98,
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+  190,
+  164,
+  969,
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+  995,
+  331,
+  492,
+  399,
+  824,
+  14,
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+  831,
+  597,
+  670,
+  857,
+  120,
+  873,
+  171,
+  890,
+  905,
+  637,
+  115,
+  605,
+  336,
+  114,
+  828,
+  284,
+  303,
+  883,
+  158,
+  494,
+  153,
+  549,
+  232,
+  556,
+  695,
+  58,
+  29,
+  504,
+  252,
+  77,
+  35,
+  646,
+  137,
+  448,
+  400,
+  468,
+  237,
+  258,
+  857,
+  150,
+  981,
+  756,
+  616,
+  138,
+  188,
+  386,
+  721,
+  370,
+  71,
+  911,
+  73,
+  967,
+  568,
+  504,
+  164,
+  770,
+  100,
+  179,
+  753,
+  551,
+  67,
+  657,
+  652,
+  243,
+  444,
+  398,
+  865,
+  772,
+  427,
+  338,
+  592,
+  63,
+  536,
+  519,
+  721,
+  83,
+  212,
+  451,
+  148,
+  117,
+  98,
+  888,
+  61,
+  734,
+  672,
+  502,
+  723,
+  783,
+  345,
+  338,
+  740,
+  909,
+  505,
+  839,
+  975,
+  654,
+  804,
+  611,
+  69,
+  11,
+  523,
+  629,
+  404,
+  856,
+  620,
+  442,
+  578,
+  574,
+  149,
+  135,
+  970,
+  938,
+  492,
+  713,
+  886,
+  639,
+  454,
+  376,
+  594,
+  374,
+  530,
+  634,
+  168,
+  566,
+  809,
+  268,
+  110,
+  766,
+  381,
+  754,
+  592,
+  582,
+  283,
+  0,
+  298,
+  246,
+  854,
+  1,
+  663,
+  430,
+  801,
+  700,
+  519,
+  357,
+  169,
+  8,
+  136,
+  246,
+  613,
+  300,
+  148,
+  884,
+  563,
+  392,
+  99,
+  846,
+  824,
+  322,
+  293,
+  341,
+  555,
+  193,
+  718,
+  570,
+  822,
+  222,
+  854,
+  12,
+  226,
+  16,
+  516,
+  920,
+  639,
+  838,
+  670,
+  529,
+  485,
+  959,
+  912,
+  543,
+  706,
+  877,
+  863,
+  852,
+  351,
+  912,
+  640,
+  705,
+  697,
+  687,
+  241,
+  287,
+  290,
+  930,
+  964,
+  1
+};
+const int idx[2399] = {
+  220,
+  336,
+  347,
+  422,
+  44,
+  128,
+  145,
+  234,
+  259,
+  315,
+  64,
+  103,
+  378,
+  469,
+  477,
+  33,
+  108,
+  126,
+  173,
+  196,
+  328,
+  331,
+  52,
+  55,
+  109,
+  306,
+  337,
+  412,
+  443,
+  364,
+  456,
+  487,
+  496,
+  299,
+  23,
+  259,
+  67,
+  196,
+  409,
+  51,
+  77,
+  147,
+  301,
+  362,
+  26,
+  106,
+  239,
+  39,
+  81,
+  118,
+  187,
+  290,
+  339,
+  395,
+  443,
+  36,
+  45,
+  195,
+  210,
+  244,
+  273,
+  22,
+  92,
+  215,
+  306,
+  364,
+  66,
+  216,
+  5,
+  25,
+  145,
+  171,
+  330,
+  401,
+  412,
+  75,
+  148,
+  180,
+  204,
+  231,
+  432,
+  443,
+  100,
+  232,
+  400,
+  467,
+  114,
+  284,
+  300,
+  330,
+  370,
+  49,
+  135,
+  183,
+  191,
+  268,
+  423,
+  491,
+  104,
+  280,
+  393,
+  442,
+  443,
+  461,
+  136,
+  175,
+  205,
+  216,
+  466,
+  5,
+  85,
+  429,
+  491,
+  0,
+  36,
+  78,
+  95,
+  161,
+  169,
+  219,
+  231,
+  250,
+  336,
+  341,
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+  431,
+  473,
+  78,
+  290,
+  351,
+  189,
+  304,
+  498,
+  336,
+  10,
+  219,
+  257,
+  402,
+  437,
+  65,
+  69,
+  168,
+  198,
+  65,
+  241,
+  242,
+  290,
+  360,
+  402,
+  254,
+  256,
+  398,
+  407,
+  66,
+  97,
+  164,
+  222,
+  316,
+  390,
+  429,
+  24,
+  81,
+  133,
+  207,
+  313,
+  67,
+  108,
+  204,
+  303,
+  494,
+  43,
+  194,
+  198,
+  285,
+  294,
+  347,
+  356,
+  394,
+  83,
+  92,
+  147,
+  167,
+  386,
+  20,
+  225,
+  400,
+  172,
+  363,
+  99,
+  64,
+  373,
+  377,
+  6,
+  63,
+  206,
+  107,
+  149,
+  230,
+  428,
+  41,
+  56,
+  77,
+  78,
+  311,
+  413,
+  476,
+  477,
+  81,
+  130,
+  145,
+  167,
+  247,
+  416,
+  56,
+  289,
+  339,
+  27,
+  47,
+  132,
+  309,
+  392,
+  36,
+  55,
+  73,
+  352,
+  358,
+  25,
+  58,
+  352,
+  430,
+  58,
+  171,
+  221,
+  334,
+  379,
+  453,
+  288,
+  479,
+  109,
+  134,
+  143,
+  174,
+  285,
+  313,
+  468,
+  495,
+  258,
+  289,
+  334,
+  382,
+  483,
+  46,
+  136,
+  264,
+  417,
+  458,
+  36,
+  59,
+  88,
+  173,
+  310,
+  316,
+  354,
+  471,
+  46,
+  225,
+  262,
+  335,
+  364,
+  468,
+  121,
+  341,
+  349,
+  7,
+  14,
+  21,
+  99,
+  135,
+  142,
+  207,
+  209,
+  272,
+  294,
+  456,
+  491,
+  208,
+  248,
+  321,
+  43,
+  129,
+  188,
+  362,
+  191,
+  279,
+  294,
+  307,
+  324,
+  362,
+  140,
+  422,
+  56,
+  169,
+  188,
+  232,
+  328,
+  449,
+  14,
+  134,
+  369,
+  375,
+  48,
+  164,
+  224,
+  260,
+  20,
+  93,
+  157,
+  219,
+  262,
+  274,
+  362,
+  473,
+  484,
+  103,
+  125,
+  140,
+  174,
+  175,
+  191,
+  226,
+  358,
+  408,
+  450,
+  20,
+  94,
+  289,
+  310,
+  311,
+  448,
+  478,
+  36,
+  175,
+  185,
+  337,
+  391,
+  48,
+  72,
+  184,
+  233,
+  345,
+  485,
+  231,
+  242,
+  339,
+  451,
+  456,
+  152,
+  158,
+  398,
+  458,
+  488,
+  151,
+  240,
+  357,
+  1,
+  33,
+  139,
+  141,
+  177,
+  223,
+  289,
+  479,
+  90,
+  115,
+  461,
+  480,
+  24,
+  26,
+  44,
+  72,
+  213,
+  361,
+  445,
+  34,
+  119,
+  470,
+  19,
+  56,
+  405,
+  464,
+  47,
+  112,
+  163,
+  235,
+  342,
+  462,
+  103,
+  192,
+  225,
+  23,
+  458,
+  68,
+  270,
+  363,
+  422,
+  427,
+  449,
+  450,
+  477,
+  105,
+  131,
+  139,
+  198,
+  212,
+  413,
+  429,
+  435,
+  43,
+  278,
+  19,
+  113,
+  192,
+  327,
+  347,
+  44,
+  67,
+  160,
+  225,
+  263,
+  330,
+  344,
+  158,
+  274,
+  303,
+  317,
+  350,
+  379,
+  409,
+  33,
+  53,
+  217,
+  273,
+  304,
+  352,
+  461,
+  495,
+  101,
+  168,
+  370,
+  395,
+  458,
+  156,
+  301,
+  319,
+  324,
+  347,
+  73,
+  127,
+  253,
+  272,
+  128,
+  212,
+  237,
+  257,
+  351,
+  77,
+  106,
+  216,
+  270,
+  368,
+  371,
+  400,
+  223,
+  355,
+  384,
+  30,
+  268,
+  307,
+  368,
+  79,
+  300,
+  317,
+  327,
+  15,
+  376,
+  31,
+  80,
+  160,
+  206,
+  227,
+  103,
+  231,
+  435,
+  481,
+  499,
+  182,
+  186,
+  189,
+  442,
+  7,
+  59,
+  65,
+  117,
+  225,
+  298,
+  304,
+  364,
+  457,
+  489,
+  186,
+  198,
+  265,
+  309,
+  336,
+  391,
+  457,
+  314,
+  418,
+  81,
+  133,
+  186,
+  190,
+  227,
+  258,
+  277,
+  419,
+  492,
+  82,
+  222,
+  239,
+  315,
+  71,
+  92,
+  122,
+  220,
+  252,
+  272,
+  311,
+  391,
+  433,
+  97,
+  137,
+  244,
+  267,
+  426,
+  34,
+  202,
+  234,
+  426,
+  428,
+  51,
+  109,
+  267,
+  377,
+  382,
+  107,
+  166,
+  203,
+  337,
+  0,
+  127,
+  247,
+  404,
+  64,
+  94,
+  373,
+  430,
+  448,
+  17,
+  37,
+  57,
+  102,
+  352,
+  354,
+  114,
+  174,
+  193,
+  241,
+  284,
+  74,
+  94,
+  213,
+  238,
+  475,
+  476,
+  140,
+  247,
+  280,
+  302,
+  328,
+  49,
+  197,
+  201,
+  222,
+  280,
+  457,
+  167,
+  445,
+  465,
+  478,
+  499,
+  25,
+  215,
+  438,
+  8,
+  129,
+  153,
+  171,
+  316,
+  328,
+  158,
+  215,
+  303,
+  328,
+  353,
+  479,
+  62,
+  251,
+  271,
+  4,
+  119,
+  262,
+  303,
+  311,
+  405,
+  419,
+  277,
+  461,
+  236,
+  248,
+  445,
+  15,
+  108,
+  227,
+  309,
+  362,
+  378,
+  424,
+  78,
+  94,
+  109,
+  118,
+  124,
+  247,
+  253,
+  315,
+  478,
+  13,
+  154,
+  170,
+  331,
+  365,
+  386,
+  264,
+  268,
+  300,
+  305,
+  429,
+  463,
+  499,
+  52,
+  105,
+  135,
+  181,
+  111,
+  156,
+  183,
+  231,
+  350,
+  388,
+  461,
+  291,
+  360,
+  80,
+  106,
+  138,
+  197,
+  242,
+  255,
+  260,
+  381,
+  415,
+  447,
+  499,
+  41,
+  266,
+  341,
+  391,
+  410,
+  448,
+  495,
+  58,
+  146,
+  286,
+  351,
+  419,
+  436,
+  464,
+  483,
+  251,
+  252,
+  444,
+  492,
+  184,
+  200,
+  57,
+  75,
+  170,
+  186,
+  187,
+  275,
+  314,
+  364,
+  407,
+  162,
+  173,
+  232,
+  211,
+  355,
+  445,
+  448,
+  308,
+  98,
+  280,
+  397,
+  431,
+  112,
+  122,
+  157,
+  209,
+  338,
+  388,
+  429,
+  112,
+  213,
+  349,
+  470,
+  69,
+  70,
+  119,
+  222,
+  251,
+  453,
+  81,
+  173,
+  482,
+  105,
+  147,
+  10,
+  229,
+  462,
+  467,
+  98,
+  421,
+  479,
+  203,
+  498,
+  499,
+  93,
+  130,
+  142,
+  270,
+  278,
+  336,
+  419,
+  73,
+  134,
+  142,
+  177,
+  192,
+  335,
+  490,
+  45,
+  140,
+  143,
+  195,
+  274,
+  284,
+  324,
+  56,
+  94,
+  171,
+  28,
+  135,
+  258,
+  277,
+  284,
+  333,
+  370,
+  421,
+  432,
+  465,
+  31,
+  46,
+  222,
+  331,
+  387,
+  432,
+  18,
+  56,
+  82,
+  95,
+  258,
+  261,
+  356,
+  378,
+  484,
+  60,
+  285,
+  298,
+  347,
+  0,
+  200,
+  307,
+  372,
+  2,
+  89,
+  201,
+  291,
+  298,
+  382,
+  455,
+  121,
+  145,
+  155,
+  47,
+  226,
+  236,
+  396,
+  398,
+  137,
+  311,
+  381,
+  429,
+  45,
+  109,
+  141,
+  173,
+  207,
+  464,
+  471,
+  499,
+  37,
+  45,
+  268,
+  447,
+  496,
+  41,
+  163,
+  387,
+  484,
+  30,
+  48,
+  91,
+  146,
+  261,
+  313,
+  401,
+  11,
+  78,
+  122,
+  144,
+  450,
+  499,
+  75,
+  82,
+  131,
+  218,
+  257,
+  285,
+  294,
+  362,
+  442,
+  213,
+  255,
+  291,
+  492,
+  63,
+  80,
+  282,
+  418,
+  1,
+  60,
+  87,
+  102,
+  111,
+  180,
+  272,
+  281,
+  324,
+  380,
+  458,
+  185,
+  216,
+  475,
+  12,
+  62,
+  109,
+  143,
+  195,
+  257,
+  271,
+  324,
+  385,
+  410,
+  226,
+  330,
+  404,
+  54,
+  158,
+  374,
+  221,
+  320,
+  340,
+  86,
+  93,
+  236,
+  94,
+  159,
+  238,
+  242,
+  318,
+  356,
+  40,
+  75,
+  168,
+  211,
+  294,
+  32,
+  164,
+  174,
+  198,
+  421,
+  13,
+  102,
+  314,
+  379,
+  418,
+  439,
+  485,
+  6,
+  53,
+  104,
+  123,
+  208,
+  436,
+  452,
+  59,
+  141,
+  204,
+  402,
+  498,
+  134,
+  335,
+  429,
+  240,
+  391,
+  461,
+  14,
+  16,
+  46,
+  371,
+  376,
+  37,
+  172,
+  227,
+  343,
+  397,
+  435,
+  39,
+  136,
+  202,
+  262,
+  339,
+  445,
+  474,
+  145,
+  272,
+  342,
+  121,
+  127,
+  12,
+  125,
+  155,
+  186,
+  234,
+  64,
+  96,
+  97,
+  108,
+  213,
+  350,
+  410,
+  485,
+  35,
+  56,
+  57,
+  167,
+  169,
+  399,
+  478,
+  60,
+  103,
+  307,
+  92,
+  104,
+  150,
+  211,
+  260,
+  8,
+  64,
+  73,
+  222,
+  273,
+  423,
+  179,
+  184,
+  190,
+  193,
+  265,
+  271,
+  305,
+  318,
+  344,
+  14,
+  75,
+  124,
+  317,
+  343,
+  404,
+  4,
+  141,
+  167,
+  212,
+  496
+};
+const double x[500] = {
+  737,
+  519,
+  538,
+  486,
+  557,
+  31,
+  651,
+  101,
+  310,
+  729,
+  721,
+  164,
+  577,
+  411,
+  104,
+  891,
+  988,
+  370,
+  788,
+  898,
+  576,
+  674,
+  7,
+  10,
+  91,
+  253,
+  9,
+  54,
+  105,
+  36,
+  799,
+  188,
+  651,
+  92,
+  766,
+  394,
+  8,
+  823,
+  242,
+  334,
+  639,
+  462,
+  111,
+  847,
+  919,
+  681,
+  392,
+  657,
+  358,
+  203,
+  453,
+  897,
+  965,
+  316,
+  759,
+  894,
+  893,
+  44,
+  743,
+  736,
+  970,
+  473,
+  229,
+  120,
+  485,
+  174,
+  405,
+  514,
+  984,
+  200,
+  723,
+  867,
+  259,
+  997,
+  191,
+  340,
+  75,
+  763,
+  579,
+  216,
+  154,
+  331,
+  338,
+  184,
+  786,
+  56,
+  235,
+  880,
+  810,
+  544,
+  522,
+  358,
+  219,
+  566,
+  632,
+  422,
+  636,
+  760,
+  657,
+  117,
+  138,
+  228,
+  163,
+  336,
+  572,
+  722,
+  438,
+  280,
+  234,
+  454,
+  967,
+  148,
+  325,
+  142,
+  790,
+  3,
+  497,
+  770,
+  936,
+  101,
+  696,
+  108,
+  255,
+  140,
+  320,
+  29,
+  36,
+  228,
+  468,
+  24,
+  183,
+  844,
+  513,
+  856,
+  102,
+  9,
+  526,
+  50,
+  73,
+  366,
+  599,
+  246,
+  662,
+  473,
+  651,
+  568,
+  575,
+  972,
+  352,
+  341,
+  897,
+  15,
+  73,
+  764,
+  768,
+  879,
+  886,
+  906,
+  718,
+  621,
+  529,
+  282,
+  339,
+  165,
+  137,
+  999,
+  215,
+  33,
+  639,
+  999,
+  906,
+  210,
+  62,
+  655,
+  996,
+  675,
+  552,
+  333,
+  176,
+  426,
+  891,
+  638,
+  571,
+  715,
+  18,
+  708,
+  795,
+  26,
+  31,
+  250,
+  18,
+  949,
+  183,
+  968,
+  394,
+  580,
+  766,
+  686,
+  162,
+  134,
+  185,
+  943,
+  919,
+  577,
+  539,
+  180,
+  750,
+  285,
+  591,
+  881,
+  381,
+  118,
+  852,
+  696,
+  617,
+  941,
+  767,
+  592,
+  650,
+  74,
+  961,
+  881,
+  891,
+  71,
+  905,
+  575,
+  598,
+  523,
+  477,
+  561,
+  948,
+  762,
+  570,
+  773,
+  146,
+  894,
+  203,
+  610,
+  471,
+  669,
+  189,
+  473,
+  650,
+  606,
+  385,
+  288,
+  360,
+  648,
+  115,
+  836,
+  139,
+  530,
+  248,
+  331,
+  286,
+  849,
+  812,
+  356,
+  884,
+  33,
+  57,
+  147,
+  297,
+  826,
+  916,
+  581,
+  0,
+  918,
+  81,
+  12,
+  956,
+  309,
+  550,
+  15,
+  243,
+  294,
+  893,
+  290,
+  227,
+  826,
+  843,
+  789,
+  744,
+  494,
+  742,
+  643,
+  126,
+  861,
+  444,
+  506,
+  417,
+  215,
+  246,
+  9,
+  244,
+  283,
+  595,
+  635,
+  494,
+  612,
+  737,
+  311,
+  896,
+  834,
+  222,
+  121,
+  595,
+  680,
+  309,
+  729,
+  263,
+  142,
+  804,
+  262,
+  343,
+  179,
+  649,
+  118,
+  360,
+  536,
+  669,
+  429,
+  359,
+  667,
+  313,
+  671,
+  506,
+  951,
+  461,
+  291,
+  359,
+  237,
+  727,
+  143,
+  968,
+  769,
+  97,
+  842,
+  752,
+  803,
+  299,
+  154,
+  384,
+  23,
+  567,
+  339,
+  778,
+  492,
+  116,
+  320,
+  967,
+  526,
+  66,
+  761,
+  908,
+  345,
+  885,
+  193,
+  894,
+  547,
+  124,
+  18,
+  254,
+  947,
+  192,
+  111,
+  384,
+  204,
+  338,
+  574,
+  749,
+  816,
+  717,
+  457,
+  353,
+  163,
+  979,
+  896,
+  679,
+  342,
+  932,
+  100,
+  216,
+  531,
+  320,
+  122,
+  594,
+  956,
+  638,
+  450,
+  733,
+  643,
+  293,
+  891,
+  633,
+  901,
+  815,
+  676,
+  307,
+  144,
+  286,
+  106,
+  182,
+  605,
+  575,
+  129,
+  390,
+  212,
+  843,
+  225,
+  544,
+  468,
+  203,
+  223,
+  862,
+  795,
+  36,
+  348,
+  743,
+  528,
+  904,
+  126,
+  802,
+  82,
+  156,
+  369,
+  986,
+  332,
+  977,
+  570,
+  421,
+  345,
+  401,
+  480,
+  63,
+  518,
+  667,
+  31,
+  909,
+  552,
+  994,
+  314,
+  891,
+  642,
+  439,
+  132,
+  670,
+  402,
+  263,
+  140,
+  549,
+  905,
+  712,
+  299,
+  986,
+  86,
+  709,
+  786,
+  47,
+  679,
+  864,
+  13,
+  140,
+  659,
+  479,
+  838,
+  988,
+  846,
+  855,
+  367,
+  935,
+  657,
+  453,
+  400,
+  851,
+  749,
+  500,
+  673,
+  523,
+  708,
+  568,
+  76,
+  18,
+  589,
+  689,
+  195,
+  504,
+  402,
+  835,
+  705,
+  187,
+  615,
+  482,
+  160,
+  609,
+  761,
+  907,
+  294,
+  538,
+  545
+};
+const int ptr[501] = {
+  0,
+  4,
+  8,
+  10,
+  15,
+  22,
+  29,
+  33,
+  34,
+  36,
+  39,
+  44,
+  44,
+  47,
+  55,
+  61,
+  66,
+  68,
+  75,
+  82,
+  86,
+  91,
+  98,
+  104,
+  109,
+  113,
+  126,
+  131,
+  134,
+  136,
+  143,
+  153,
+  159,
+  168,
+  170,
+  174,
+  176,
+  180,
+  187,
+  192,
+  198,
+  200,
+  204,
+  211,
+  213,
+  222,
+  225,
+  228,
+  233,
+  241,
+  247,
+  253,
+  256,
+  262,
+  264,
+  270,
+  274,
+  277,
+  283,
+  288,
+  294,
+  301,
+  307,
+  312,
+  315,
+  319,
+  325,
+  329,
+  332,
+  338,
+  340,
+  342,
+  348,
+  353,
+  359,
+  362,
+  366,
+  368,
+  374,
+  387,
+  393,
+  400,
+  403,
+  406,
+  412,
+  420,
+  425,
+  428,
+  433,
+  441,
+  442,
+  448,
+  456,
+  462,
+  468,
+  469,
+  477,
+  479,
+  485,
+  490,
+  495,
+  501,
+  508,
+  513,
+  518,
+  524,
+  532,
+  535,
+  538,
+  542,
+  546,
+  552,
+  561,
+  563,
+  567,
+  571,
+  574,
+  576,
+  581,
+  584,
+  588,
+  592,
+  593,
+  597,
+  599,
+  607,
+  612,
+  615,
+  619,
+  626,
+  633,
+  640,
+  646,
+  650,
+  653,
+  659,
+  665,
+  670,
+  673,
+  678,
+  685,
+  691,
+  697,
+  703,
+  708,
+  712,
+  717,
+  719,
+  722,
+  725,
+  732,
+  736,
+  738,
+  742,
+  747,
+  753,
+  757,
+  763,
+  767,
+  769,
+  769,
+  777,
+  780,
+  784,
+  790,
+  797,
+  807,
+  810,
+  813,
+  815,
+  817,
+  822,
+  829,
+  830,
+  835,
+  844,
+  848,
+  851,
+  854,
+  862,
+  864,
+  873,
+  876,
+  881,
+  884,
+  888,
+  895,
+  899,
+  901,
+  904,
+  908,
+  912,
+  919,
+  927,
+  931,
+  937,
+  941,
+  944,
+  948,
+  950,
+  955,
+  960,
+  963,
+  970,
+  975,
+  979,
+  983,
+  985,
+  992,
+  993,
+  998,
+  1001,
+  1008,
+  1012,
+  1014,
+  1018,
+  1023,
+  1030,
+  1036,
+  1040,
+  1045,
+  1052,
+  1058,
+  1061,
+  1066,
+  1069,
+  1071,
+  1077,
+  1080,
+  1084,
+  1087,
+  1090,
+  1092,
+  1095,
+  1100,
+  1102,
+  1110,
+  1117,
+  1122,
+  1130,
+  1133,
+  1138,
+  1142,
+  1144,
+  1146,
+  1153,
+  1158,
+  1160,
+  1167,
+  1172,
+  1176,
+  1179,
+  1183,
+  1188,
+  1191,
+  1193,
+  1196,
+  1204,
+  1210,
+  1216,
+  1219,
+  1221,
+  1225,
+  1229,
+  1234,
+  1236,
+  1239,
+  1244,
+  1248,
+  1253,
+  1256,
+  1264,
+  1268,
+  1271,
+  1272,
+  1275,
+  1278,
+  1284,
+  1287,
+  1291,
+  1296,
+  1300,
+  1304,
+  1306,
+  1313,
+  1317,
+  1322,
+  1326,
+  1332,
+  1336,
+  1344,
+  1349,
+  1356,
+  1363,
+  1368,
+  1369,
+  1378,
+  1381,
+  1385,
+  1388,
+  1395,
+  1399,
+  1407,
+  1414,
+  1422,
+  1425,
+  1433,
+  1435,
+  1438,
+  1439,
+  1445,
+  1448,
+  1450,
+  1453,
+  1456,
+  1470,
+  1472,
+  1475,
+  1481,
+  1487,
+  1491,
+  1494,
+  1497,
+  1498,
+  1503,
+  1507,
+  1513,
+  1517,
+  1524,
+  1529,
+  1534,
+  1542,
+  1547,
+  1550,
+  1550,
+  1552,
+  1553,
+  1556,
+  1559,
+  1563,
+  1571,
+  1577,
+  1580,
+  1585,
+  1590,
+  1594,
+  1598,
+  1600,
+  1602,
+  1610,
+  1615,
+  1620,
+  1628,
+  1634,
+  1637,
+  1649,
+  1652,
+  1656,
+  1662,
+  1664,
+  1670,
+  1674,
+  1678,
+  1687,
+  1697,
+  1704,
+  1709,
+  1715,
+  1720,
+  1725,
+  1728,
+  1736,
+  1740,
+  1747,
+  1750,
+  1754,
+  1760,
+  1763,
+  1765,
+  1773,
+  1781,
+  1783,
+  1788,
+  1795,
+  1802,
+  1810,
+  1815,
+  1820,
+  1824,
+  1829,
+  1836,
+  1839,
+  1843,
+  1847,
+  1849,
+  1854,
+  1859,
+  1863,
+  1873,
+  1880,
+  1882,
+  1891,
+  1895,
+  1899,
+  1904,
+  1909,
+  1914,
+  1919,
+  1923,
+  1927,
+  1932,
+  1938,
+  1943,
+  1949,
+  1954,
+  1960,
+  1965,
+  1968,
+  1974,
+  1980,
+  1983,
+  1990,
+  1992,
+  1995,
+  2002,
+  2011,
+  2017,
+  2024,
+  2028,
+  2035,
+  2037,
+  2048,
+  2055,
+  2063,
+  2067,
+  2069,
+  2078,
+  2081,
+  2085,
+  2086,
+  2090,
+  2097,
+  2101,
+  2107,
+  2110,
+  2112,
+  2116,
+  2119,
+  2122,
+  2129,
+  2136,
+  2143,
+  2146,
+  2156,
+  2162,
+  2171,
+  2175,
+  2179,
+  2186,
+  2189,
+  2194,
+  2198,
+  2206,
+  2211,
+  2215,
+  2222,
+  2228,
+  2237,
+  2241,
+  2245,
+  2256,
+  2259,
+  2269,
+  2272,
+  2275,
+  2278,
+  2279,
+  2281,
+  2287,
+  2292,
+  2297,
+  2304,
+  2311,
+  2316,
+  2319,
+  2322,
+  2327,
+  2333,
+  2340,
+  2343,
+  2345,
+  2350,
+  2358,
+  2365,
+  2365,
+  2368,
+  2373,
+  2379,
+  2388,
+  2394,
+  2399
+};
+const double verify_data[500] = {
+  1636962,
+  1714376,
+  142636,
+  1151015,
+  1672341,
+  2790420,
+  1447201,
+  422892,
+  30953,
+  1030287,
+  1335188,
+  0,
+  605334,
+  2278445,
+  858848,
+  245423,
+  950882,
+  705076,
+  1312024,
+  1084284,
+  1837558,
+  1201746,
+  2360392,
+  1488940,
+  688178,
+  2632122,
+  1481444,
+  660854,
+  346453,
+  982949,
+  1400599,
+  1093225,
+  2856372,
+  1078398,
+  1074402,
+  579548,
+  1820752,
+  2638601,
+  2072665,
+  749887,
+  687788,
+  478788,
+  1482258,
+  1207317,
+  1397243,
+  794364,
+  1002505,
+  1651686,
+  1028801,
+  1189726,
+  1513197,
+  1214956,
+  738475,
+  633771,
+  1207042,
+  680857,
+  899314,
+  2277406,
+  773143,
+  1986687,
+  907216,
+  907940,
+  1539019,
+  1043338,
+  681730,
+  219905,
+  1397298,
+  2184201,
+  1537202,
+  266744,
+  563005,
+  1827909,
+  1105928,
+  2286680,
+  887533,
+  343193,
+  238910,
+  1678393,
+  2600003,
+  417502,
+  1551071,
+  798273,
+  398719,
+  2056881,
+  1296314,
+  917292,
+  190534,
+  882078,
+  1979139,
+  50621,
+  1048185,
+  1967771,
+  1911887,
+  1895897,
+  23343,
+  2658748,
+  285864,
+  1027049,
+  975769,
+  2488413,
+  832738,
+  844130,
+  1379856,
+  1785889,
+  2463463,
+  782430,
+  982466,
+  609500,
+  706251,
+  1981399,
+  1861430,
+  2146667,
+  250104,
+  1166284,
+  1295022,
+  189599,
+  855191,
+  1005718,
+  969658,
+  707377,
+  561273,
+  86496,
+  717937,
+  97767,
+  1893638,
+  779229,
+  429727,
+  99564,
+  1863565,
+  2267656,
+  950026,
+  780700,
+  581248,
+  393282,
+  2134865,
+  1244700,
+  1894843,
+  954212,
+  1439102,
+  779512,
+  1459287,
+  881497,
+  2202043,
+  1447401,
+  1249637,
+  765168,
+  488244,
+  837127,
+  1236555,
+  2281259,
+  1995666,
+  25783,
+  534020,
+  1486259,
+  1268571,
+  875283,
+  744594,
+  1410335,
+  757320,
+  0,
+  1922627,
+  399058,
+  1490594,
+  1475527,
+  1587557,
+  1695667,
+  644546,
+  536038,
+  224304,
+  414120,
+  2029077,
+  3930385,
+  377416,
+  1059074,
+  1960417,
+  1439575,
+  368749,
+  460183,
+  2479302,
+  105204,
+  1426355,
+  649313,
+  2194338,
+  918200,
+  1591449,
+  2229266,
+  434520,
+  684504,
+  1009270,
+  222922,
+  600674,
+  1011867,
+  1321434,
+  836127,
+  2493805,
+  1448674,
+  1269364,
+  1304961,
+  98554,
+  2423810,
+  1570229,
+  302458,
+  2806045,
+  1534004,
+  1463827,
+  1085011,
+  120989,
+  1701753,
+  110302,
+  938429,
+  1186733,
+  2255246,
+  425960,
+  376311,
+  341394,
+  1061333,
+  2025091,
+  522270,
+  598604,
+  1000824,
+  2254049,
+  1857539,
+  346425,
+  1345187,
+  550497,
+  1251096,
+  943720,
+  681558,
+  555972,
+  779590,
+  299796,
+  1445763,
+  459865,
+  774572,
+  489448,
+  2407693,
+  1574903,
+  1630452,
+  1907397,
+  555045,
+  1902494,
+  1172223,
+  142555,
+  445864,
+  1376151,
+  1200389,
+  327553,
+  1548402,
+  1106503,
+  888650,
+  41081,
+  1245270,
+  845610,
+  1232215,
+  387441,
+  434475,
+  1204003,
+  1333189,
+  1672468,
+  567827,
+  11392,
+  631046,
+  1299298,
+  719608,
+  714169,
+  362247,
+  1308257,
+  530903,
+  398202,
+  885445,
+  2606806,
+  1354354,
+  438760,
+  194928,
+  712863,
+  1010340,
+  2245646,
+  376041,
+  876890,
+  1683404,
+  955032,
+  1065455,
+  925034,
+  1731713,
+  1152271,
+  2093865,
+  1221433,
+  629438,
+  2054936,
+  2643313,
+  1322567,
+  1492288,
+  1844514,
+  1802382,
+  871,
+  1350044,
+  967406,
+  756881,
+  574442,
+  1295864,
+  1815978,
+  2822668,
+  2201377,
+  2729436,
+  616018,
+  2318346,
+  332717,
+  289665,
+  97812,
+  1881483,
+  1003188,
+  702530,
+  409314,
+  645118,
+  3645947,
+  723792,
+  503126,
+  1609036,
+  1647277,
+  587437,
+  735899,
+  666552,
+  27354,
+  1045106,
+  397951,
+  1087090,
+  1173872,
+  1629962,
+  1334261,
+  1855668,
+  2856970,
+  1341188,
+  336968,
+  0,
+  521349,
+  53118,
+  881926,
+  154917,
+  942966,
+  1237636,
+  820836,
+  579583,
+  1436861,
+  2025006,
+  634434,
+  829152,
+  298073,
+  205380,
+  1622350,
+  1171051,
+  848451,
+  2417009,
+  2016092,
+  390510,
+  2721874,
+  359761,
+  309038,
+  1061522,
+  297026,
+  1311767,
+  305305,
+  854945,
+  1773244,
+  2656339,
+  896058,
+  1069160,
+  1552917,
+  1421821,
+  440874,
+  216699,
+  1654864,
+  521705,
+  807422,
+  1242602,
+  1329872,
+  308130,
+  526463,
+  27937,
+  1450630,
+  1621987,
+  799154,
+  1378289,
+  2519996,
+  1149046,
+  579937,
+  1841561,
+  1895047,
+  1009234,
+  1922198,
+  2570006,
+  409696,
+  442495,
+  277484,
+  979605,
+  1392287,
+  1023715,
+  1881778,
+  2432703,
+  2297384,
+  542451,
+  1368100,
+  833048,
+  1038108,
+  742376,
+  1542317,
+  2230186,
+  1249077,
+  884020,
+  1286059,
+  1102407,
+  1651393,
+  1787846,
+  1370154,
+  2734166,
+  2935249,
+  447485,
+  736859,
+  828966,
+  1547038,
+  765990,
+  1427773,
+  255456,
+  134871,
+  1597546,
+  2173052,
+  1187286,
+  2364828,
+  1220233,
+  1760369,
+  75080,
+  2799969,
+  1363310,
+  2347168,
+  272279,
+  33698,
+  1192053,
+  342501,
+  356092,
+  136578,
+  1701048,
+  2216796,
+  1340150,
+  1852854,
+  580862,
+  407410,
+  1860346,
+  200649,
+  954363,
+  955621,
+  2234154,
+  2007706,
+  646339,
+  2712491,
+  1259244,
+  2368138,
+  1550431,
+  1160903,
+  987838,
+  650293,
+  833228,
+  368144,
+  1998925,
+  1733716,
+  1050000,
+  1061635,
+  1144649,
+  1260205,
+  851043,
+  1417512,
+  2826918,
+  1059350,
+  1522135,
+  1039943,
+  703837,
+  1035006,
+  19505,
+  211545,
+  1461101,
+  1238659,
+  1414306,
+  1151385,
+  2169011,
+  1101116,
+  1118290,
+  335296,
+  1502266,
+  1405699,
+  1762457,
+  530338,
+  246108,
+  484583,
+  2164048,
+  1614511,
+  0,
+  1446940,
+  575450,
+  2043329,
+  2057251,
+  774670,
+  1084124
+};
diff --git a/apps/riscv-tests/benchmarks/spmv/spmv_gendata.scala b/apps/riscv-tests/benchmarks/spmv/spmv_gendata.scala
new file mode 100644
index 0000000..f777445
--- /dev/null
+++ b/apps/riscv-tests/benchmarks/spmv/spmv_gendata.scala
@@ -0,0 +1,48 @@
+#!/usr/bin/env scala
+!#
+
+val m = args(0).toInt
+val n = args(1).toInt
+val approx_nnz = args(2).toInt
+
+val pnnz = approx_nnz.toDouble/(m*n)
+val idx = collection.mutable.ArrayBuffer[Int]()
+val p = collection.mutable.ArrayBuffer(0)
+
+for (i <- 0 until m) {
+  for (j <- 0 until n) {
+    if (util.Random.nextDouble < pnnz)
+      idx += j
+  }
+  p += idx.length
+}
+
+val nnz = idx.length
+val v = Array.tabulate(n)(i => util.Random.nextInt(1000))
+val d = Array.tabulate(nnz)(i => util.Random.nextInt(1000))
+
+def printVec(t: String, name: String, data: Seq[Int]) = {
+  println("const " + t + " " + name + "[" + data.length + "] = {")
+  println("  "+data.map(_.toString).reduceLeft(_+",\n  "+_))
+  println("};")
+}
+
+def spmv(p: Seq[Int], d: Seq[Int], idx: Seq[Int], v: Seq[Int]) = {
+  val y = collection.mutable.ArrayBuffer[Int]()
+  for (i <- 0 until p.length-1) {
+    var yi = 0
+    for (k <- p(i) until p(i+1))
+      yi = yi + d(k)*v(idx(k))
+    y += yi
+  }
+  y
+}
+
+println("#define R " + m)
+println("#define C " + n)
+println("#define NNZ " + nnz)
+printVec("double", "val", d)
+printVec("int", "idx", idx)
+printVec("double", "x", v)
+printVec("int", "ptr", p)
+printVec("double", "verify_data", spmv(p, d, idx, v))
diff --git a/apps/riscv-tests/benchmarks/spmv/spmv_main.c b/apps/riscv-tests/benchmarks/spmv/spmv_main.c
new file mode 100644
index 0000000..5232f68
--- /dev/null
+++ b/apps/riscv-tests/benchmarks/spmv/spmv_main.c
@@ -0,0 +1,52 @@
+// See LICENSE for license details.
+
+//**************************************************************************
+// Double-precision sparse matrix-vector multiplication benchmark
+//--------------------------------------------------------------------------
+
+#include "util.h"
+
+//--------------------------------------------------------------------------
+// Input/Reference Data
+
+#include "dataset1.h"
+
+void spmv(int r, const double* val, const int* idx, const double* x,
+          const int* ptr, double* y)
+{
+  for (int i = 0; i < r; i++)
+  {
+    int k;
+    double yi0 = 0, yi1 = 0, yi2 = 0, yi3 = 0;
+    for (k = ptr[i]; k < ptr[i+1]-3; k+=4)
+    {
+      yi0 += val[k+0]*x[idx[k+0]];
+      yi1 += val[k+1]*x[idx[k+1]];
+      yi2 += val[k+2]*x[idx[k+2]];
+      yi3 += val[k+3]*x[idx[k+3]];
+    }
+    for ( ; k < ptr[i+1]; k++)
+    {
+      yi0 += val[k]*x[idx[k]];
+    }
+    y[i] = (yi0+yi1)+(yi2+yi3);
+  }
+}
+
+//--------------------------------------------------------------------------
+// Main
+
+int main( int argc, char* argv[] )
+{
+  double y[R];
+
+#if PREALLOCATE
+  spmv(R, val, idx, x, ptr, y);
+#endif
+
+  setStats(1);
+  spmv(R, val, idx, x, ptr, y);
+  setStats(0);
+
+  return verifyDouble(R, y, verify_data);
+}
diff --git a/apps/riscv-tests/benchmarks/towers/towers_main.c b/apps/riscv-tests/benchmarks/towers/towers_main.c
new file mode 100644
index 0000000..8c2355a
--- /dev/null
+++ b/apps/riscv-tests/benchmarks/towers/towers_main.c
@@ -0,0 +1,234 @@
+// See LICENSE for license details.
+
+//**************************************************************************
+// Towers of Hanoi benchmark
+//--------------------------------------------------------------------------
+//
+// Towers of Hanoi is a classic puzzle problem. The game consists of
+// three pegs and a set of discs. Each disc is a different size, and
+// initially all of the discs are on the left most peg with the smallest
+// disc on top and the largest disc on the bottom. The goal is to move all
+// of the discs onto the right most peg. The catch is that you are only
+// allowed to move one disc at a time and you can never place a larger
+// disc on top of a smaller disc.
+//
+// This implementation starts with NUM_DISC discs and uses a recursive
+// algorithm to sovel the puzzle.
+
+#include "util.h"
+
+// This is the number of discs in the puzzle.
+
+#define NUM_DISCS  7
+
+//--------------------------------------------------------------------------
+// List data structure and functions
+
+struct Node
+{
+  int val;
+  struct Node* next;
+};
+
+struct List
+{
+  int size;
+  struct Node* head;
+};
+
+struct List g_nodeFreeList;
+struct Node g_nodePool[NUM_DISCS];
+
+int list_getSize( struct List* list )
+{
+  return list->size;
+}
+
+void list_init( struct List* list )
+{
+  list->size = 0;
+  list->head = 0;
+}
+
+void list_push( struct List* list, int val )
+{
+  struct Node* newNode;
+
+  // Pop the next free node off the free list
+  newNode = g_nodeFreeList.head;
+  g_nodeFreeList.head = g_nodeFreeList.head->next;
+
+  // Push the new node onto the given list
+  newNode->next = list->head;
+  list->head = newNode;
+
+  // Assign the value
+  list->head->val = val;
+
+  // Increment size
+  list->size++;
+
+}
+
+int list_pop( struct List* list )
+{
+  struct Node* freedNode;
+  int val;
+
+  // Get the value from the->head of given list
+  val = list->head->val;
+
+  // Pop the head node off the given list
+  freedNode = list->head;
+  list->head = list->head->next;
+
+  // Push the freed node onto the free list
+  freedNode->next = g_nodeFreeList.head;
+  g_nodeFreeList.head = freedNode;
+
+  // Decrement size
+  list->size--;
+
+  return val;
+}
+
+void list_clear( struct List* list )
+{
+  while ( list_getSize(list) > 0 )
+    list_pop(list);
+}
+
+//--------------------------------------------------------------------------
+// Tower data structure and functions
+
+struct Towers
+{
+  int numDiscs;
+  int numMoves;
+  struct List pegA;
+  struct List pegB;
+  struct List pegC;
+};
+
+void towers_init( struct Towers* this, int n )
+{
+  int i;
+
+  this->numDiscs = n;
+  this->numMoves = 0;
+
+  list_init( &(this->pegA) );
+  list_init( &(this->pegB) );
+  list_init( &(this->pegC) );
+
+  for ( i = 0; i < n; i++ )
+    list_push( &(this->pegA), n-i );
+
+}
+
+void towers_clear( struct Towers* this )
+{
+
+  list_clear( &(this->pegA) );
+  list_clear( &(this->pegB) );
+  list_clear( &(this->pegC) );
+
+  towers_init( this, this->numDiscs );
+
+}
+
+void towers_solve_h( struct Towers* this, int n,
+                     struct List* startPeg,
+                     struct List* tempPeg,
+                     struct List* destPeg )
+{
+  int val;
+
+  if ( n == 1 ) {
+    val = list_pop(startPeg);
+    list_push(destPeg,val);
+    this->numMoves++;
+  }
+  else {
+    towers_solve_h( this, n-1, startPeg, destPeg,  tempPeg );
+    towers_solve_h( this, 1,   startPeg, tempPeg,  destPeg );
+    towers_solve_h( this, n-1, tempPeg,  startPeg, destPeg );
+  }
+
+}
+
+void towers_solve( struct Towers* this )
+{
+  towers_solve_h( this, this->numDiscs, &(this->pegA), &(this->pegB), &(this->pegC) );
+}
+
+int towers_verify( struct Towers* this )
+{
+  struct Node* ptr;
+  int numDiscs = 0;
+
+  if ( list_getSize(&this->pegA) != 0 ) {
+    return 2;
+  }
+
+  if ( list_getSize(&this->pegB) != 0 ) {
+    return 3;
+  }
+
+  if ( list_getSize(&this->pegC) != this->numDiscs ) {
+    return 4;
+  }
+
+  for ( ptr = this->pegC.head; ptr != 0; ptr = ptr->next ) {
+    numDiscs++;
+    if ( ptr->val != numDiscs ) {
+      return 5;
+    }
+  }
+
+  if ( this->numMoves != ((1 << this->numDiscs) - 1) ) {
+    return 6;
+  }
+
+  return 0;
+}
+
+//--------------------------------------------------------------------------
+// Main
+
+int main( int argc, char* argv[] )
+{
+  struct Towers towers;
+  int i;
+
+  // Initialize free list
+
+  list_init( &g_nodeFreeList );
+  g_nodeFreeList.head = &(g_nodePool[0]);
+  g_nodeFreeList.size = NUM_DISCS;
+  g_nodePool[NUM_DISCS-1].next = 0;
+  g_nodePool[NUM_DISCS-1].val = 99;
+  for ( i = 0; i < (NUM_DISCS-1); i++ ) {
+    g_nodePool[i].next = &(g_nodePool[i+1]);
+    g_nodePool[i].val = i;
+  }
+
+  towers_init( &towers, NUM_DISCS );
+
+  // If needed we preallocate everything in the caches
+
+#if PREALLOCATE
+  towers_solve( &towers );
+#endif
+
+  // Solve it
+
+  towers_clear( &towers );
+  setStats(1);
+  towers_solve( &towers );
+  setStats(0);
+
+  // Check the results
+  return towers_verify( &towers );
+}
+
diff --git a/apps/riscv-tests/benchmarks/vvadd/dataset1-large.h b/apps/riscv-tests/benchmarks/vvadd/dataset1-large.h
new file mode 100644
index 0000000..5a008c1
--- /dev/null
+++ b/apps/riscv-tests/benchmarks/vvadd/dataset1-large.h
@@ -0,0 +1,167 @@
+// See LICENSE for license details.
+
+
+#define DATA_SIZE 1000
+
+int input1_data[DATA_SIZE] =
+{
+   41, 833, 564, 187, 749, 350, 132, 949, 584, 805, 621,   6, 931, 890, 392, 694, 961, 110, 116, 296,
+  426, 314, 659, 774, 319, 678, 875, 376, 474, 938, 539, 569, 203, 280, 759, 606, 511, 657, 195,  81,
+  267, 229, 337, 944, 902, 241, 913, 826, 933, 985, 195, 960, 566, 350, 649, 657, 181, 111, 859,  65,
+  288, 349, 141, 905, 886, 264, 576, 979, 761, 241, 478, 499, 403, 222, 444, 721, 676, 317, 224, 937,
+  288, 119, 615, 606, 389, 351, 455, 278, 367, 358, 584,  62, 985, 403, 346, 517, 559, 908, 775, 255,
+  778, 598, 143,  33, 125, 941, 933, 799, 553, 431, 648, 952, 287,  19,  49,  86,  95, 441, 587, 614,
+  382, 280, 808, 971, 819, 344, 450, 512, 965, 347, 808, 882, 537, 946, 701, 356, 567, 891,  22, 568,
+  665, 423, 434, 158,   2,  84, 247,  49, 435, 792, 869, 486, 414, 369, 548, 518, 888, 682, 284, 264,
+  499, 290, 897, 215, 731, 688, 251, 786, 555, 302, 528, 544, 322, 947, 287, 824, 304, 788, 733, 959,
+  366, 722, 294, 975, 653, 748,  91, 378, 105, 102, 381, 651, 825, 840, 356, 148,  54, 140, 955, 343,
+  533, 757, 521, 837, 592,  13, 173,  63, 121, 133, 758, 372, 951,  39, 129, 110, 847, 437, 255, 269,
+  409, 628, 399, 549, 753, 564, 171,  19, 727, 501, 777,  43, 753,  81, 202, 853, 153, 760, 357, 943,
+  922, 328, 496, 442, 516, 641, 276, 786, 113, 842, 907, 275, 237,  32, 784, 565, 357, 803, 819, 751,
+  280,  85, 458, 454, 710, 459,  41, 253, 377, 508, 700, 860, 480, 741, 499, 709,  49, 371, 873, 945,
+  992, 526, 721, 435, 232, 497, 697,  30, 348, 250, 350, 250, 573, 784, 749, 502, 823, 826, 170, 160,
+  674,  32, 202, 143, 853,  90, 394, 107, 855, 106, 157,   6, 765, 204, 194, 574, 218, 526, 177, 239,
+  698, 757, 706,  49,  84, 799, 893, 512, 373, 492,  14, 621,  83, 103, 794, 921, 643, 880, 834, 239,
+  462, 114, 561, 529,  10, 997, 904, 387, 407, 105, 559, 936, 512, 409, 302, 202, 427, 613, 359, 521,
+  684,  22, 185, 312, 107, 274, 387, 242, 486, 105, 698, 899, 770, 644,  80, 161, 407, 946,  30, 768,
+  870, 113, 148,  62, 147, 838, 845, 432, 141, 211, 817, 821, 562, 364, 615, 495, 812, 916, 159, 430,
+  803, 180, 544, 840, 458, 786, 872, 795, 806, 758, 104, 401, 254, 984, 136, 729, 584, 794, 414, 528,
+  707, 554, 378, 766, 977, 236, 947, 229, 165, 505, 105, 704, 796, 140, 303, 795, 635, 560, 119,   8,
+  532, 814,  37, 584, 739, 619, 767, 478,  57, 958, 784, 985, 837, 307,  67, 824, 996, 749, 171, 826,
+  621, 155, 826,  43, 694,  80, 236, 747, 744, 265, 124, 731, 941, 425, 370, 320, 269, 542, 763, 752,
+  915,  14,   1, 906, 995, 809, 560, 873, 972, 289, 509, 558, 970, 405, 579, 293, 251, 849, 129, 452,
+  716,  86, 678, 181, 240, 335, 793, 641,   1, 320, 987, 646, 754, 958, 203, 142, 180, 299, 165, 761,
+  974, 646, 559, 619, 422, 260, 565, 542, 492, 991, 745, 207, 372, 932, 664,  34, 533, 478, 908, 203,
+   33, 214, 365, 892, 781, 680, 705, 688, 947, 386,  50, 101, 474, 399, 679, 330, 952, 471, 477, 725,
+  713, 937, 529, 870,  77, 545, 907, 853, 143, 979, 239, 105, 365,  98,  54,  98, 440, 764, 315, 336,
+  697, 774, 726, 324, 282, 536, 622, 594, 890,  75, 290, 496, 726, 449, 548, 135, 644, 838, 290, 767,
+  162, 415, 491, 985, 116, 617, 859, 235, 282, 571, 913, 560, 194, 242, 782, 985, 728, 344, 430, 613,
+  759, 176, 309, 333, 354, 310, 699,  46, 487, 503, 100, 393, 268, 314,  75, 345, 987, 600, 908, 384,
+   92, 545, 277, 668, 351, 853, 863, 312, 100, 532, 567, 836, 370, 989, 461, 912, 182, 268, 160, 771,
+   22, 854, 644,  17, 779, 911, 855, 137, 983, 717, 565, 719, 253, 785, 154, 196, 253, 447, 899,   5,
+  325, 616, 309, 175, 159, 123, 838, 715, 550, 230,  82, 627, 324, 927, 103,  17, 966, 159, 177, 593,
+  372, 393, 599, 745, 377, 865, 591, 553, 440, 345, 593, 290, 908, 544, 377, 456, 781, 110, 495, 896,
+  806, 700, 548, 340,  29, 829, 630, 546, 613, 972, 116, 313, 904, 971, 607, 794, 169, 896, 507, 916,
+  431, 339, 147, 224, 112, 580, 834, 134, 948, 201, 488, 396, 797, 478, 769, 574, 485, 339, 721, 451,
+  821, 744,   0, 594, 277, 120, 680, 757, 555, 847, 517, 379, 505, 904, 246, 243, 394, 430, 214, 244,
+  524, 399, 172, 304, 620, 594, 535, 698, 159, 750, 809, 454,  75,  93, 167,  16, 853, 494, 324,  78,
+   52, 112,  10, 342, 730, 680, 287, 961,  92, 626, 912, 616, 860, 744, 744, 478, 615, 508, 914, 810,
+  288, 974, 129, 581, 548, 868, 981, 270, 623, 653, 626, 990, 386, 323, 472, 164, 239, 189, 865, 231,
+  356, 152, 825, 328, 390, 848,  38, 402, 616, 546, 206,   2, 783, 890, 815, 831, 665, 410,  94, 246,
+  422, 211, 675,   9, 374, 426,  64,  53, 758, 811, 500, 437, 335, 328, 237, 415, 468, 684, 565, 305,
+  449, 597, 136, 882, 383, 938, 268, 115, 908,  50, 952, 366, 397, 257, 231, 667,  35, 990, 443, 213,
+  389,  13, 621,  52, 612, 934, 953, 828, 462, 621, 812, 522, 672,  57, 313, 352,  55, 972, 753, 416,
+  879, 864, 572, 163, 721,  12, 643, 507, 968, 781, 840, 242, 630, 810, 795, 435, 885, 599, 696, 643,
+   93, 710, 785, 112, 581,  12, 923, 615, 652, 359, 261, 233, 609, 686, 539, 118, 560, 739,  20, 317,
+  976, 573, 386, 772, 663, 504, 212, 888, 907, 420, 737, 516,  25, 219, 797, 716, 452, 692, 683, 459,
+  815, 323, 612, 247, 116, 352, 281, 738, 290, 909, 645, 625, 932, 220, 685, 373, 876, 646, 412, 955
+};
+
+int input2_data[DATA_SIZE] =
+{
+  454, 335,   1, 989, 365, 572,  64, 153, 216, 140, 210, 572, 339, 593, 898, 228,  12, 883, 750, 646,
+  500, 436, 701, 812, 981, 150, 696, 564, 272, 258, 647, 509,  88, 703, 669, 375, 551, 936, 592, 569,
+  952, 800, 584, 643, 368, 489, 328, 313, 592, 388, 543, 649, 979, 997, 814,  79, 208, 998, 629, 847,
+  704, 997, 253, 715, 430, 415, 538, 700,   4, 494, 100, 864, 693, 416, 296, 285, 620,  78, 351, 540,
+  646, 169, 527, 289, 796, 801, 720, 758, 745,  92, 989, 271, 853, 788, 531, 222, 461, 241, 358, 332,
+  684, 740, 446, 311, 743, 557, 479, 557, 925, 796, 357, 891, 666, 514, 557, 870, 853, 440,  61, 678,
+  396,   9,  17, 170, 291, 380, 536, 185, 917, 539, 983, 887,  54, 612, 951, 479, 151,   7, 641, 335,
+  730,  95, 728, 280, 395, 688, 911, 476, 815, 729, 265, 127, 236, 214, 180,   6, 503, 596, 173, 643,
+  346, 599,  68, 849, 658, 619, 121, 131, 828, 667, 433, 487, 753, 125, 626,  14,  10, 403, 106, 703,
+  818, 964, 406, 874, 856,  86,  60, 660, 667, 153, 121,  98, 412, 236,  12, 423, 965, 216, 621, 361,
+  921, 715, 647, 299, 886, 682,  36, 493, 551, 537, 969, 643, 434, 415, 303, 438, 860, 203, 478, 988,
+  675, 719, 990, 338, 450, 633, 155, 646, 452, 427, 509, 988, 426,  12, 483, 142, 339, 390,  50, 171,
+  601, 105, 968, 121, 879,  81, 870, 600, 603, 871, 887, 610, 404, 234, 745, 526, 275, 441, 226, 752,
+  943, 726, 709, 201,  54, 758,  53, 397,  41, 141, 416, 747, 219, 478, 770, 180, 482, 691, 725, 173,
+  186, 914,   1, 963, 247, 464, 362, 521, 233, 120,  40, 779, 195, 161, 743, 439, 355, 403, 141, 633,
+  289, 782, 320, 636, 118, 852,  70, 816, 388, 954,  36,  16, 698, 695, 677, 598, 883, 824, 746, 462,
+  511, 534, 440, 428, 732, 726, 702, 547,  86, 798, 215,  21, 651,  59, 429, 657,  96, 973, 659, 966,
+  524,  62, 625, 303, 714, 409,  55, 728, 305, 436, 901, 592, 691, 796, 497, 177, 940, 995, 480, 158,
+  822, 611, 680,  14, 111, 797, 185,   0, 718,  96, 749, 739, 814, 435, 326,  37,  33, 605, 935,  27,
+   88, 441, 339, 344, 554, 365, 954, 639, 396, 991, 249, 338, 832, 974, 393, 266, 470, 348, 336, 419,
+  249, 215, 542, 903, 636, 729, 581, 820, 671, 979, 418, 670, 920, 568, 745, 662, 139, 385, 927, 173,
+  457, 316, 183, 477, 196, 399, 416, 805, 996, 270, 735, 696, 825, 528,  50, 623, 537,  87, 294, 867,
+  110, 398, 781, 646, 375, 943, 897, 589,  44, 288, 845, 742,  99, 522, 443, 432, 165, 930,  28, 461,
+  323, 272, 376, 340, 898, 158, 168, 443, 193, 631, 935, 274, 781, 185, 619, 292, 933, 156, 827,  88,
+  987, 629, 649,  32,   1, 744, 399, 915, 791, 554, 984, 530, 600, 401, 683, 540, 903, 120, 995, 521,
+  622, 224, 895, 530, 820, 651, 226,  96, 262, 569, 238, 126, 610, 191, 238, 796, 884, 573, 108, 140,
+  789, 852,  23, 704, 890, 480,  52, 372, 201, 546, 408, 119, 645, 464,  81, 293,  52, 880, 224, 744,
+  735, 886, 167,   1, 532, 321, 169, 485, 101, 177,  42, 708, 654, 915, 625, 242, 822, 795, 641, 252,
+  245, 151, 876, 333, 601, 938, 775, 397, 233, 755, 454, 424, 210, 962, 900, 923, 655, 529, 595,  90,
+  464, 685,  70, 754,  32, 494,  25, 389, 488,  37, 409, 639,  27, 950, 539,  80, 303, 723, 734, 125,
+  552, 248, 107, 362,  48, 869, 144, 841, 724, 335, 470, 263, 343, 809, 677, 339, 336, 410, 465,  56,
+  590, 485, 406, 993, 746, 238, 525, 336, 256, 134, 546, 722, 367, 943, 106, 629, 396, 208, 429, 523,
+  130, 355, 990, 673, 991, 719, 449,  84, 616, 211, 707, 737, 847, 452, 316, 974, 746, 796, 522, 618,
+  115, 727, 226, 165, 200, 830, 742, 187, 705, 671, 785, 886, 962, 657, 293, 620, 144, 173, 796,  72,
+  678,  80, 793, 685, 637, 967, 241, 898, 693, 372, 601, 721, 398, 553,  72, 174, 978, 325, 558, 185,
+  505, 859, 651, 573, 321, 349, 400, 890, 844, 885, 933, 980, 448, 989,  50, 332, 900, 716, 747, 444,
+    6, 394, 285, 703, 450, 652, 771, 485, 534, 559, 481, 507, 434, 343,  42, 784, 865, 421, 415, 871,
+  539, 162, 105, 481, 595, 115, 350, 964, 287, 232, 154, 602, 539, 943, 872, 121, 652, 811, 747, 362,
+  340, 910, 206, 572, 505, 973, 961, 354, 627, 849, 971, 910, 410, 770,  63, 874, 396, 482, 619, 646,
+  557, 328,  67, 884, 512, 972,   6, 513, 882, 562, 764, 366, 506, 786, 831, 382, 638, 452,  72,  83,
+   59, 932, 929, 924, 961,  69, 797, 985, 854, 885, 600, 389, 232, 793, 179, 773, 689, 775, 494, 139,
+  234, 431, 780, 371,  22, 653, 741, 815, 428, 139, 603, 315, 344, 889, 317, 260, 861, 377, 511, 304,
+   70,  35, 854, 576, 490, 326, 303, 431, 813, 708, 388, 962, 967, 442,  49, 831, 251, 321, 741, 179,
+  176, 117, 523, 764, 952, 704, 531, 804,  23, 611, 846, 375, 854, 971,  24, 639, 318, 723, 662, 647,
+  281, 158, 294, 885, 734, 866, 471, 296, 673, 472, 439,   5, 155, 506, 948, 600, 445, 222, 784, 349,
+  943, 150, 366, 444, 604, 720, 340, 972, 911, 321, 435,  50,  78, 761, 950, 238,  27, 226, 201, 176,
+  877, 450, 879,  99, 143,  31, 812, 771, 527, 488, 797, 194, 293, 966, 276, 345, 413, 197, 386, 116,
+  322, 680, 538, 553, 960, 874,  48, 506, 898, 539, 495, 764, 805, 286, 432, 836, 192, 825, 778, 586,
+  359, 352, 746,  11, 749,   5, 408, 643, 441, 368,  97, 169, 359, 527, 672,  69, 880, 298, 300, 327,
+  923, 829, 816, 497, 243, 981, 917, 713, 653, 503, 406, 543, 108, 304, 464, 954,  86, 802, 446,  28
+};
+
+int verify_data[DATA_SIZE] =
+{
+  495, 1168, 565, 1176, 1114, 922, 196, 1102, 800, 945, 831, 578, 1270, 1483, 1290, 922, 973, 993, 866, 942,
+  926, 750, 1360, 1586, 1300, 828, 1571, 940, 746, 1196, 1186, 1078, 291, 983, 1428, 981, 1062, 1593, 787, 650,
+  1219, 1029, 921, 1587, 1270, 730, 1241, 1139, 1525, 1373, 738, 1609, 1545, 1347, 1463, 736, 389, 1109, 1488, 912,
+  992, 1346, 394, 1620, 1316, 679, 1114, 1679, 765, 735, 578, 1363, 1096, 638, 740, 1006, 1296, 395, 575, 1477,
+  934, 288, 1142, 895, 1185, 1152, 1175, 1036, 1112, 450, 1573, 333, 1838, 1191, 877, 739, 1020, 1149, 1133, 587,
+  1462, 1338, 589, 344, 868, 1498, 1412, 1356, 1478, 1227, 1005, 1843, 953, 533, 606, 956, 948, 881, 648, 1292,
+  778, 289, 825, 1141, 1110, 724, 986, 697, 1882, 886, 1791, 1769, 591, 1558, 1652, 835, 718, 898, 663, 903,
+  1395, 518, 1162, 438, 397, 772, 1158, 525, 1250, 1521, 1134, 613, 650, 583, 728, 524, 1391, 1278, 457, 907,
+  845, 889, 965, 1064, 1389, 1307, 372, 917, 1383, 969, 961, 1031, 1075, 1072, 913, 838, 314, 1191, 839, 1662,
+  1184, 1686, 700, 1849, 1509, 834, 151, 1038, 772, 255, 502, 749, 1237, 1076, 368, 571, 1019, 356, 1576, 704,
+  1454, 1472, 1168, 1136, 1478, 695, 209, 556, 672, 670, 1727, 1015, 1385, 454, 432, 548, 1707, 640, 733, 1257,
+  1084, 1347, 1389, 887, 1203, 1197, 326, 665, 1179, 928, 1286, 1031, 1179,  93, 685, 995, 492, 1150, 407, 1114,
+  1523, 433, 1464, 563, 1395, 722, 1146, 1386, 716, 1713, 1794, 885, 641, 266, 1529, 1091, 632, 1244, 1045, 1503,
+  1223, 811, 1167, 655, 764, 1217,  94, 650, 418, 649, 1116, 1607, 699, 1219, 1269, 889, 531, 1062, 1598, 1118,
+  1178, 1440, 722, 1398, 479, 961, 1059, 551, 581, 370, 390, 1029, 768, 945, 1492, 941, 1178, 1229, 311, 793,
+  963, 814, 522, 779, 971, 942, 464, 923, 1243, 1060, 193,  22, 1463, 899, 871, 1172, 1101, 1350, 923, 701,
+  1209, 1291, 1146, 477, 816, 1525, 1595, 1059, 459, 1290, 229, 642, 734, 162, 1223, 1578, 739, 1853, 1493, 1205,
+  986, 176, 1186, 832, 724, 1406, 959, 1115, 712, 541, 1460, 1528, 1203, 1205, 799, 379, 1367, 1608, 839, 679,
+  1506, 633, 865, 326, 218, 1071, 572, 242, 1204, 201, 1447, 1638, 1584, 1079, 406, 198, 440, 1551, 965, 795,
+  958, 554, 487, 406, 701, 1203, 1799, 1071, 537, 1202, 1066, 1159, 1394, 1338, 1008, 761, 1282, 1264, 495, 849,
+  1052, 395, 1086, 1743, 1094, 1515, 1453, 1615, 1477, 1737, 522, 1071, 1174, 1552, 881, 1391, 723, 1179, 1341, 701,
+  1164, 870, 561, 1243, 1173, 635, 1363, 1034, 1161, 775, 840, 1400, 1621, 668, 353, 1418, 1172, 647, 413, 875,
+  642, 1212, 818, 1230, 1114, 1562, 1664, 1067, 101, 1246, 1629, 1727, 936, 829, 510, 1256, 1161, 1679, 199, 1287,
+  944, 427, 1202, 383, 1592, 238, 404, 1190, 937, 896, 1059, 1005, 1722, 610, 989, 612, 1202, 698, 1590, 840,
+  1902, 643, 650, 938, 996, 1553, 959, 1788, 1763, 843, 1493, 1088, 1570, 806, 1262, 833, 1154, 969, 1124, 973,
+  1338, 310, 1573, 711, 1060, 986, 1019, 737, 263, 889, 1225, 772, 1364, 1149, 441, 938, 1064, 872, 273, 901,
+  1763, 1498, 582, 1323, 1312, 740, 617, 914, 693, 1537, 1153, 326, 1017, 1396, 745, 327, 585, 1358, 1132, 947,
+  768, 1100, 532, 893, 1313, 1001, 874, 1173, 1048, 563,  92, 809, 1128, 1314, 1304, 572, 1774, 1266, 1118, 977,
+  958, 1088, 1405, 1203, 678, 1483, 1682, 1250, 376, 1734, 693, 529, 575, 1060, 954, 1021, 1095, 1293, 910, 426,
+  1161, 1459, 796, 1078, 314, 1030, 647, 983, 1378, 112, 699, 1135, 753, 1399, 1087, 215, 947, 1561, 1024, 892,
+  714, 663, 598, 1347, 164, 1486, 1003, 1076, 1006, 906, 1383, 823, 537, 1051, 1459, 1324, 1064, 754, 895, 669,
+  1349, 661, 715, 1326, 1100, 548, 1224, 382, 743, 637, 646, 1115, 635, 1257, 181, 974, 1383, 808, 1337, 907,
+  222, 900, 1267, 1341, 1342, 1572, 1312, 396, 716, 743, 1274, 1573, 1217, 1441, 777, 1886, 928, 1064, 682, 1389,
+  137, 1581, 870, 182, 979, 1741, 1597, 324, 1688, 1388, 1350, 1605, 1215, 1442, 447, 816, 397, 620, 1695,  77,
+  1003, 696, 1102, 860, 796, 1090, 1079, 1613, 1243, 602, 683, 1348, 722, 1480, 175, 191, 1944, 484, 735, 778,
+  877, 1252, 1250, 1318, 698, 1214, 991, 1443, 1284, 1230, 1526, 1270, 1356, 1533, 427, 788, 1681, 826, 1242, 1340,
+  812, 1094, 833, 1043, 479, 1481, 1401, 1031, 1147, 1531, 597, 820, 1338, 1314, 649, 1578, 1034, 1317, 922, 1787,
+  970, 501, 252, 705, 707, 695, 1184, 1098, 1235, 433, 642, 998, 1336, 1421, 1641, 695, 1137, 1150, 1468, 813,
+  1161, 1654, 206, 1166, 782, 1093, 1641, 1111, 1182, 1696, 1488, 1289, 915, 1674, 309, 1117, 790, 912, 833, 890,
+  1081, 727, 239, 1188, 1132, 1566, 541, 1211, 1041, 1312, 1573, 820, 581, 879, 998, 398, 1491, 946, 396, 161,
+  111, 1044, 939, 1266, 1691, 749, 1084, 1946, 946, 1511, 1512, 1005, 1092, 1537, 923, 1251, 1304, 1283, 1408, 949,
+  522, 1405, 909, 952, 570, 1521, 1722, 1085, 1051, 792, 1229, 1305, 730, 1212, 789, 424, 1100, 566, 1376, 535,
+  426, 187, 1679, 904, 880, 1174, 341, 833, 1429, 1254, 594, 964, 1750, 1332, 864, 1662, 916, 731, 835, 425,
+  598, 328, 1198, 773, 1326, 1130, 595, 857, 781, 1422, 1346, 812, 1189, 1299, 261, 1054, 786, 1407, 1227, 952,
+  730, 755, 430, 1767, 1117, 1804, 739, 411, 1581, 522, 1391, 371, 552, 763, 1179, 1267, 480, 1212, 1227, 562,
+  1332, 163, 987, 496, 1216, 1654, 1293, 1800, 1373, 942, 1247, 572, 750, 818, 1263, 590,  82, 1198, 954, 592,
+  1756, 1314, 1451, 262, 864,  43, 1455, 1278, 1495, 1269, 1637, 436, 923, 1776, 1071, 780, 1298, 796, 1082, 759,
+  415, 1390, 1323, 665, 1541, 886, 971, 1121, 1550, 898, 756, 997, 1414, 972, 971, 954, 752, 1564, 798, 903,
+  1335, 925, 1132, 783, 1412, 509, 620, 1531, 1348, 788, 834, 685, 384, 746, 1469, 785, 1332, 990, 983, 786,
+  1738, 1152, 1428, 744, 359, 1333, 1198, 1451, 943, 1412, 1051, 1168, 1040, 524, 1149, 1327, 962, 1448, 858, 983
+};
+
diff --git a/apps/riscv-tests/benchmarks/vvadd/dataset1.h b/apps/riscv-tests/benchmarks/vvadd/dataset1.h
new file mode 100644
index 0000000..a34cb96
--- /dev/null
+++ b/apps/riscv-tests/benchmarks/vvadd/dataset1.h
@@ -0,0 +1,62 @@
+// See LICENSE for license details.
+
+
+#define DATA_SIZE 300
+
+int input1_data[DATA_SIZE] =
+{
+   41, 833, 564, 187, 749, 350, 132, 949, 584, 805, 621,   6, 931, 890, 392, 694, 961, 110, 116, 296,
+  426, 314, 659, 774, 319, 678, 875, 376, 474, 938, 539, 569, 203, 280, 759, 606, 511, 657, 195,  81,
+  267, 229, 337, 944, 902, 241, 913, 826, 933, 985, 195, 960, 566, 350, 649, 657, 181, 111, 859,  65,
+  288, 349, 141, 905, 886, 264, 576, 979, 761, 241, 478, 499, 403, 222, 444, 721, 676, 317, 224, 937,
+  288, 119, 615, 606, 389, 351, 455, 278, 367, 358, 584,  62, 985, 403, 346, 517, 559, 908, 775, 255,
+  778, 598, 143,  33, 125, 941, 933, 799, 553, 431, 648, 952, 287,  19,  49,  86,  95, 441, 587, 614,
+  382, 280, 808, 971, 819, 344, 450, 512, 965, 347, 808, 882, 537, 946, 701, 356, 567, 891,  22, 568,
+  665, 423, 434, 158,   2,  84, 247,  49, 435, 792, 869, 486, 414, 369, 548, 518, 888, 682, 284, 264,
+  499, 290, 897, 215, 731, 688, 251, 786, 555, 302, 528, 544, 322, 947, 287, 824, 304, 788, 733, 959,
+  366, 722, 294, 975, 653, 748,  91, 378, 105, 102, 381, 651, 825, 840, 356, 148,  54, 140, 955, 343,
+  533, 757, 521, 837, 592,  13, 173,  63, 121, 133, 758, 372, 951,  39, 129, 110, 847, 437, 255, 269,
+  409, 628, 399, 549, 753, 564, 171,  19, 727, 501, 777,  43, 753,  81, 202, 853, 153, 760, 357, 943,
+  922, 328, 496, 442, 516, 641, 276, 786, 113, 842, 907, 275, 237,  32, 784, 565, 357, 803, 819, 751,
+  280,  85, 458, 454, 710, 459,  41, 253, 377, 508, 700, 860, 480, 741, 499, 709,  49, 371, 873, 945,
+  992, 526, 721, 435, 232, 497, 697,  30, 348, 250, 350, 250, 573, 784, 749, 502, 823, 826, 170, 160
+};
+
+int input2_data[DATA_SIZE] =
+{
+  454, 335,   1, 989, 365, 572,  64, 153, 216, 140, 210, 572, 339, 593, 898, 228,  12, 883, 750, 646,
+  500, 436, 701, 812, 981, 150, 696, 564, 272, 258, 647, 509,  88, 703, 669, 375, 551, 936, 592, 569,
+  952, 800, 584, 643, 368, 489, 328, 313, 592, 388, 543, 649, 979, 997, 814,  79, 208, 998, 629, 847,
+  704, 997, 253, 715, 430, 415, 538, 700,   4, 494, 100, 864, 693, 416, 296, 285, 620,  78, 351, 540,
+  646, 169, 527, 289, 796, 801, 720, 758, 745,  92, 989, 271, 853, 788, 531, 222, 461, 241, 358, 332,
+  684, 740, 446, 311, 743, 557, 479, 557, 925, 796, 357, 891, 666, 514, 557, 870, 853, 440,  61, 678,
+  396,   9,  17, 170, 291, 380, 536, 185, 917, 539, 983, 887,  54, 612, 951, 479, 151,   7, 641, 335,
+  730,  95, 728, 280, 395, 688, 911, 476, 815, 729, 265, 127, 236, 214, 180,   6, 503, 596, 173, 643,
+  346, 599,  68, 849, 658, 619, 121, 131, 828, 667, 433, 487, 753, 125, 626,  14,  10, 403, 106, 703,
+  818, 964, 406, 874, 856,  86,  60, 660, 667, 153, 121,  98, 412, 236,  12, 423, 965, 216, 621, 361,
+  921, 715, 647, 299, 886, 682,  36, 493, 551, 537, 969, 643, 434, 415, 303, 438, 860, 203, 478, 988,
+  675, 719, 990, 338, 450, 633, 155, 646, 452, 427, 509, 988, 426,  12, 483, 142, 339, 390,  50, 171,
+  601, 105, 968, 121, 879,  81, 870, 600, 603, 871, 887, 610, 404, 234, 745, 526, 275, 441, 226, 752,
+  943, 726, 709, 201,  54, 758,  53, 397,  41, 141, 416, 747, 219, 478, 770, 180, 482, 691, 725, 173,
+  186, 914,   1, 963, 247, 464, 362, 521, 233, 120,  40, 779, 195, 161, 743, 439, 355, 403, 141, 633
+};
+
+int verify_data[DATA_SIZE] =
+{
+  495, 1168, 565, 1176, 1114, 922, 196, 1102, 800, 945, 831, 578, 1270, 1483, 1290, 922, 973, 993, 866, 942,
+  926, 750, 1360, 1586, 1300, 828, 1571, 940, 746, 1196, 1186, 1078, 291, 983, 1428, 981, 1062, 1593, 787, 650,
+  1219, 1029, 921, 1587, 1270, 730, 1241, 1139, 1525, 1373, 738, 1609, 1545, 1347, 1463, 736, 389, 1109, 1488, 912,
+  992, 1346, 394, 1620, 1316, 679, 1114, 1679, 765, 735, 578, 1363, 1096, 638, 740, 1006, 1296, 395, 575, 1477,
+  934, 288, 1142, 895, 1185, 1152, 1175, 1036, 1112, 450, 1573, 333, 1838, 1191, 877, 739, 1020, 1149, 1133, 587,
+  1462, 1338, 589, 344, 868, 1498, 1412, 1356, 1478, 1227, 1005, 1843, 953, 533, 606, 956, 948, 881, 648, 1292,
+  778, 289, 825, 1141, 1110, 724, 986, 697, 1882, 886, 1791, 1769, 591, 1558, 1652, 835, 718, 898, 663, 903,
+  1395, 518, 1162, 438, 397, 772, 1158, 525, 1250, 1521, 1134, 613, 650, 583, 728, 524, 1391, 1278, 457, 907,
+  845, 889, 965, 1064, 1389, 1307, 372, 917, 1383, 969, 961, 1031, 1075, 1072, 913, 838, 314, 1191, 839, 1662,
+  1184, 1686, 700, 1849, 1509, 834, 151, 1038, 772, 255, 502, 749, 1237, 1076, 368, 571, 1019, 356, 1576, 704,
+  1454, 1472, 1168, 1136, 1478, 695, 209, 556, 672, 670, 1727, 1015, 1385, 454, 432, 548, 1707, 640, 733, 1257,
+  1084, 1347, 1389, 887, 1203, 1197, 326, 665, 1179, 928, 1286, 1031, 1179,  93, 685, 995, 492, 1150, 407, 1114,
+  1523, 433, 1464, 563, 1395, 722, 1146, 1386, 716, 1713, 1794, 885, 641, 266, 1529, 1091, 632, 1244, 1045, 1503,
+  1223, 811, 1167, 655, 764, 1217,  94, 650, 418, 649, 1116, 1607, 699, 1219, 1269, 889, 531, 1062, 1598, 1118,
+  1178, 1440, 722, 1398, 479, 961, 1059, 551, 581, 370, 390, 1029, 768, 945, 1492, 941, 1178, 1229, 311, 793
+};
+
diff --git a/apps/riscv-tests/benchmarks/vvadd/vvadd_gendata.pl b/apps/riscv-tests/benchmarks/vvadd/vvadd_gendata.pl
new file mode 100755
index 0000000..f23cdf4
--- /dev/null
+++ b/apps/riscv-tests/benchmarks/vvadd/vvadd_gendata.pl
@@ -0,0 +1,139 @@
+#!/usr/bin/perl -w
+#==========================================================================
+# vvadd_gendata.pl
+#
+# Author : Christopher Batten (cbatten@mit.edu)
+# Date   : April 29, 2005
+#
+(our $usageMsg = <<'ENDMSG') =~ s/^\#//gm;
+#
+# Simple script which creates an input data set and the reference data
+# for the vvadd benchmark.
+#
+ENDMSG
+
+use strict "vars";
+use warnings;
+no  warnings("once");
+use Getopt::Long;
+
+#--------------------------------------------------------------------------
+# Command line processing
+#--------------------------------------------------------------------------
+
+our %opts;
+
+sub usage()
+{
+
+  print "\n";
+  print " Usage: vvadd_gendata.pl [options] \n";
+  print "\n";
+  print " Options:\n";
+  print "  --help  print this message\n";
+  print "  --size  size of input data [1000]\n";
+  print "  --seed  random seed [1]\n";
+  print "$usageMsg";
+
+  exit();
+}
+
+sub processCommandLine()
+{
+
+  $opts{"help"} = 0;
+  $opts{"size"} = 1000;
+  $opts{"seed"} = 1;
+  Getopt::Long::GetOptions( \%opts, 'help|?', 'size:i', 'seed:i' ) or usage();
+  $opts{"help"} and usage();
+
+}
+
+#--------------------------------------------------------------------------
+# Helper Functions
+#--------------------------------------------------------------------------
+
+sub printArray
+{
+  my $arrayName = $_[0];
+  my $arrayRef  = $_[1];
+
+  my $numCols = 20;
+  my $arrayLen = scalar(@{$arrayRef});
+
+  print "int ".$arrayName."[DATA_SIZE] = \n";
+  print "{\n";
+
+  if ( $arrayLen <= $numCols ) {
+    print "  ";
+    for ( my $i = 0; $i < $arrayLen; $i++ ) {
+      print sprintf("%3d",$arrayRef->[$i]);
+      if ( $i != $arrayLen-1 ) {
+        print ", ";
+      }
+    }
+    print "\n";
+  }
+
+  else {
+    my $numRows = int($arrayLen/$numCols);
+    for ( my $j = 0; $j < $numRows; $j++ ) {
+      print "  ";
+      for ( my $i = 0; $i < $numCols; $i++ ) {
+        my $index = $j*$numCols + $i;
+        print sprintf("%3d",$arrayRef->[$index]);
+        if ( $index != $arrayLen-1 ) {
+          print ", ";
+        }
+      }
+      print "\n";
+    }
+
+    if ( $arrayLen > ($numRows*$numCols) ) {
+      print "  ";
+      for ( my $i = 0; $i < ($arrayLen-($numRows*$numCols)); $i++ ) {
+        my $index = $numCols*$numRows + $i;
+        print sprintf("%3d",$arrayRef->[$index]);
+        if ( $index != $arrayLen-1 ) {
+          print ", ";
+        }
+      }
+      print "\n";
+    }
+
+  }
+
+  print  "};\n\n";
+}
+
+#--------------------------------------------------------------------------
+# Main
+#--------------------------------------------------------------------------
+
+sub main()
+{
+
+  processCommandLine();
+  srand($opts{"seed"});
+
+  my @values1;
+  my @values2;
+  my @sum;
+  for ( my $i = 0; $i < $opts{"size"}; $i++ ) {
+    my $value1 = int(rand(999));
+    my $value2 = int(rand(999));
+    push( @values1, $value1 );
+    push( @values2, $value2 );
+    push( @sum, $value1 + $value2 );
+  }
+
+
+  print "\n\#define DATA_SIZE ".$opts{"size"}." \n\n";
+  printArray( "input1_data", \@values1 );
+  printArray( "input2_data", \@values2 );
+  printArray( "verify_data", \@sum );
+
+}
+
+main();
+
diff --git a/apps/riscv-tests/benchmarks/vvadd/vvadd_main.c b/apps/riscv-tests/benchmarks/vvadd/vvadd_main.c
new file mode 100644
index 0000000..d8ff01c
--- /dev/null
+++ b/apps/riscv-tests/benchmarks/vvadd/vvadd_main.c
@@ -0,0 +1,48 @@
+// See LICENSE for license details.
+
+//**************************************************************************
+// Vector-vector add benchmark
+//--------------------------------------------------------------------------
+//
+// This benchmark uses adds to vectors and writes the results to a
+// third vector. The input data (and reference data) should be
+// generated using the vvadd_gendata.pl perl script and dumped
+// to a file named dataset1.h.
+ 
+#include "util.h"
+
+//--------------------------------------------------------------------------
+// Input/Reference Data
+
+#include "dataset1.h"
+
+//--------------------------------------------------------------------------
+// vvadd function
+
+void vvadd( int n, int a[], int b[], int c[] )
+{
+  int i;
+  for ( i = 0; i < n; i++ )
+    c[i] = a[i] + b[i];
+}
+
+//--------------------------------------------------------------------------
+// Main
+
+int main( int argc, char* argv[] )
+{
+  int results_data[DATA_SIZE];
+
+#if PREALLOCATE
+  // If needed we preallocate everything in the caches
+  vvadd( DATA_SIZE, input1_data, input2_data, results_data );
+#endif
+
+  // Do the vvadd
+  setStats(1);
+  vvadd( DATA_SIZE, input1_data, input2_data, results_data );
+  setStats(0);
+
+  // Check the results
+  return verify( DATA_SIZE, results_data, verify_data );
+}
diff --git a/apps/riscv-tests/configure b/apps/riscv-tests/configure
new file mode 100755
index 0000000..db0969e
--- /dev/null
+++ b/apps/riscv-tests/configure
@@ -0,0 +1,3694 @@
+#! /bin/sh
+# Guess values for system-dependent variables and create Makefiles.
+# Generated by GNU Autoconf 2.69 for riscv-tests 1.0.
+#
+#
+# Copyright (C) 1992-1996, 1998-2012 Free Software Foundation, Inc.
+#
+#
+# This configure script is free software; the Free Software Foundation
+# gives unlimited permission to copy, distribute and modify it.
+## -------------------- ##
+## M4sh Initialization. ##
+## -------------------- ##
+
+# Be more Bourne compatible
+DUALCASE=1; export DUALCASE # for MKS sh
+if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then :
+  emulate sh
+  NULLCMD=:
+  # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which
+  # is contrary to our usage.  Disable this feature.
+  alias -g '${1+"$@"}'='"$@"'
+  setopt NO_GLOB_SUBST
+else
+  case `(set -o) 2>/dev/null` in #(
+  *posix*) :
+    set -o posix ;; #(
+  *) :
+     ;;
+esac
+fi
+
+
+as_nl='
+'
+export as_nl
+# Printing a long string crashes Solaris 7 /usr/bin/printf.
+as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\'
+as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo
+as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo
+# Prefer a ksh shell builtin over an external printf program on Solaris,
+# but without wasting forks for bash or zsh.
+if test -z "$BASH_VERSION$ZSH_VERSION" \
+    && (test "X`print -r -- $as_echo`" = "X$as_echo") 2>/dev/null; then
+  as_echo='print -r --'
+  as_echo_n='print -rn --'
+elif (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then
+  as_echo='printf %s\n'
+  as_echo_n='printf %s'
+else
+  if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then
+    as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"'
+    as_echo_n='/usr/ucb/echo -n'
+  else
+    as_echo_body='eval expr "X$1" : "X\\(.*\\)"'
+    as_echo_n_body='eval
+      arg=$1;
+      case $arg in #(
+      *"$as_nl"*)
+	expr "X$arg" : "X\\(.*\\)$as_nl";
+	arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;;
+      esac;
+      expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl"
+    '
+    export as_echo_n_body
+    as_echo_n='sh -c $as_echo_n_body as_echo'
+  fi
+  export as_echo_body
+  as_echo='sh -c $as_echo_body as_echo'
+fi
+
+# The user is always right.
+if test "${PATH_SEPARATOR+set}" != set; then
+  PATH_SEPARATOR=:
+  (PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && {
+    (PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 ||
+      PATH_SEPARATOR=';'
+  }
+fi
+
+
+# IFS
+# We need space, tab and new line, in precisely that order.  Quoting is
+# there to prevent editors from complaining about space-tab.
+# (If _AS_PATH_WALK were called with IFS unset, it would disable word
+# splitting by setting IFS to empty value.)
+IFS=" ""	$as_nl"
+
+# Find who we are.  Look in the path if we contain no directory separator.
+as_myself=
+case $0 in #((
+  *[\\/]* ) as_myself=$0 ;;
+  *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+    test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break
+  done
+IFS=$as_save_IFS
+
+     ;;
+esac
+# We did not find ourselves, most probably we were run as `sh COMMAND'
+# in which case we are not to be found in the path.
+if test "x$as_myself" = x; then
+  as_myself=$0
+fi
+if test ! -f "$as_myself"; then
+  $as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2
+  exit 1
+fi
+
+# Unset variables that we do not need and which cause bugs (e.g. in
+# pre-3.0 UWIN ksh).  But do not cause bugs in bash 2.01; the "|| exit 1"
+# suppresses any "Segmentation fault" message there.  '((' could
+# trigger a bug in pdksh 5.2.14.
+for as_var in BASH_ENV ENV MAIL MAILPATH
+do eval test x\${$as_var+set} = xset \
+  && ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || :
+done
+PS1='$ '
+PS2='> '
+PS4='+ '
+
+# NLS nuisances.
+LC_ALL=C
+export LC_ALL
+LANGUAGE=C
+export LANGUAGE
+
+# CDPATH.
+(unset CDPATH) >/dev/null 2>&1 && unset CDPATH
+
+# Use a proper internal environment variable to ensure we don't fall
+  # into an infinite loop, continuously re-executing ourselves.
+  if test x"${_as_can_reexec}" != xno && test "x$CONFIG_SHELL" != x; then
+    _as_can_reexec=no; export _as_can_reexec;
+    # We cannot yet assume a decent shell, so we have to provide a
+# neutralization value for shells without unset; and this also
+# works around shells that cannot unset nonexistent variables.
+# Preserve -v and -x to the replacement shell.
+BASH_ENV=/dev/null
+ENV=/dev/null
+(unset BASH_ENV) >/dev/null 2>&1 && unset BASH_ENV ENV
+case $- in # ((((
+  *v*x* | *x*v* ) as_opts=-vx ;;
+  *v* ) as_opts=-v ;;
+  *x* ) as_opts=-x ;;
+  * ) as_opts= ;;
+esac
+exec $CONFIG_SHELL $as_opts "$as_myself" ${1+"$@"}
+# Admittedly, this is quite paranoid, since all the known shells bail
+# out after a failed `exec'.
+$as_echo "$0: could not re-execute with $CONFIG_SHELL" >&2
+as_fn_exit 255
+  fi
+  # We don't want this to propagate to other subprocesses.
+          { _as_can_reexec=; unset _as_can_reexec;}
+if test "x$CONFIG_SHELL" = x; then
+  as_bourne_compatible="if test -n \"\${ZSH_VERSION+set}\" && (emulate sh) >/dev/null 2>&1; then :
+  emulate sh
+  NULLCMD=:
+  # Pre-4.2 versions of Zsh do word splitting on \${1+\"\$@\"}, which
+  # is contrary to our usage.  Disable this feature.
+  alias -g '\${1+\"\$@\"}'='\"\$@\"'
+  setopt NO_GLOB_SUBST
+else
+  case \`(set -o) 2>/dev/null\` in #(
+  *posix*) :
+    set -o posix ;; #(
+  *) :
+     ;;
+esac
+fi
+"
+  as_required="as_fn_return () { (exit \$1); }
+as_fn_success () { as_fn_return 0; }
+as_fn_failure () { as_fn_return 1; }
+as_fn_ret_success () { return 0; }
+as_fn_ret_failure () { return 1; }
+
+exitcode=0
+as_fn_success || { exitcode=1; echo as_fn_success failed.; }
+as_fn_failure && { exitcode=1; echo as_fn_failure succeeded.; }
+as_fn_ret_success || { exitcode=1; echo as_fn_ret_success failed.; }
+as_fn_ret_failure && { exitcode=1; echo as_fn_ret_failure succeeded.; }
+if ( set x; as_fn_ret_success y && test x = \"\$1\" ); then :
+
+else
+  exitcode=1; echo positional parameters were not saved.
+fi
+test x\$exitcode = x0 || exit 1
+test -x / || exit 1"
+  as_suggested="  as_lineno_1=";as_suggested=$as_suggested$LINENO;as_suggested=$as_suggested" as_lineno_1a=\$LINENO
+  as_lineno_2=";as_suggested=$as_suggested$LINENO;as_suggested=$as_suggested" as_lineno_2a=\$LINENO
+  eval 'test \"x\$as_lineno_1'\$as_run'\" != \"x\$as_lineno_2'\$as_run'\" &&
+  test \"x\`expr \$as_lineno_1'\$as_run' + 1\`\" = \"x\$as_lineno_2'\$as_run'\"' || exit 1"
+  if (eval "$as_required") 2>/dev/null; then :
+  as_have_required=yes
+else
+  as_have_required=no
+fi
+  if test x$as_have_required = xyes && (eval "$as_suggested") 2>/dev/null; then :
+
+else
+  as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+as_found=false
+for as_dir in /bin$PATH_SEPARATOR/usr/bin$PATH_SEPARATOR$PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+  as_found=:
+  case $as_dir in #(
+	 /*)
+	   for as_base in sh bash ksh sh5; do
+	     # Try only shells that exist, to save several forks.
+	     as_shell=$as_dir/$as_base
+	     if { test -f "$as_shell" || test -f "$as_shell.exe"; } &&
+		    { $as_echo "$as_bourne_compatible""$as_required" | as_run=a "$as_shell"; } 2>/dev/null; then :
+  CONFIG_SHELL=$as_shell as_have_required=yes
+		   if { $as_echo "$as_bourne_compatible""$as_suggested" | as_run=a "$as_shell"; } 2>/dev/null; then :
+  break 2
+fi
+fi
+	   done;;
+       esac
+  as_found=false
+done
+$as_found || { if { test -f "$SHELL" || test -f "$SHELL.exe"; } &&
+	      { $as_echo "$as_bourne_compatible""$as_required" | as_run=a "$SHELL"; } 2>/dev/null; then :
+  CONFIG_SHELL=$SHELL as_have_required=yes
+fi; }
+IFS=$as_save_IFS
+
+
+      if test "x$CONFIG_SHELL" != x; then :
+  export CONFIG_SHELL
+             # We cannot yet assume a decent shell, so we have to provide a
+# neutralization value for shells without unset; and this also
+# works around shells that cannot unset nonexistent variables.
+# Preserve -v and -x to the replacement shell.
+BASH_ENV=/dev/null
+ENV=/dev/null
+(unset BASH_ENV) >/dev/null 2>&1 && unset BASH_ENV ENV
+case $- in # ((((
+  *v*x* | *x*v* ) as_opts=-vx ;;
+  *v* ) as_opts=-v ;;
+  *x* ) as_opts=-x ;;
+  * ) as_opts= ;;
+esac
+exec $CONFIG_SHELL $as_opts "$as_myself" ${1+"$@"}
+# Admittedly, this is quite paranoid, since all the known shells bail
+# out after a failed `exec'.
+$as_echo "$0: could not re-execute with $CONFIG_SHELL" >&2
+exit 255
+fi
+
+    if test x$as_have_required = xno; then :
+  $as_echo "$0: This script requires a shell more modern than all"
+  $as_echo "$0: the shells that I found on your system."
+  if test x${ZSH_VERSION+set} = xset ; then
+    $as_echo "$0: In particular, zsh $ZSH_VERSION has bugs and should"
+    $as_echo "$0: be upgraded to zsh 4.3.4 or later."
+  else
+    $as_echo "$0: Please tell bug-autoconf@gnu.org about your system,
+$0: including any error possibly output before this
+$0: message. Then install a modern shell, or manually run
+$0: the script under such a shell if you do have one."
+  fi
+  exit 1
+fi
+fi
+fi
+SHELL=${CONFIG_SHELL-/bin/sh}
+export SHELL
+# Unset more variables known to interfere with behavior of common tools.
+CLICOLOR_FORCE= GREP_OPTIONS=
+unset CLICOLOR_FORCE GREP_OPTIONS
+
+## --------------------- ##
+## M4sh Shell Functions. ##
+## --------------------- ##
+# as_fn_unset VAR
+# ---------------
+# Portably unset VAR.
+as_fn_unset ()
+{
+  { eval $1=; unset $1;}
+}
+as_unset=as_fn_unset
+
+# as_fn_set_status STATUS
+# -----------------------
+# Set $? to STATUS, without forking.
+as_fn_set_status ()
+{
+  return $1
+} # as_fn_set_status
+
+# as_fn_exit STATUS
+# -----------------
+# Exit the shell with STATUS, even in a "trap 0" or "set -e" context.
+as_fn_exit ()
+{
+  set +e
+  as_fn_set_status $1
+  exit $1
+} # as_fn_exit
+
+# as_fn_mkdir_p
+# -------------
+# Create "$as_dir" as a directory, including parents if necessary.
+as_fn_mkdir_p ()
+{
+
+  case $as_dir in #(
+  -*) as_dir=./$as_dir;;
+  esac
+  test -d "$as_dir" || eval $as_mkdir_p || {
+    as_dirs=
+    while :; do
+      case $as_dir in #(
+      *\'*) as_qdir=`$as_echo "$as_dir" | sed "s/'/'\\\\\\\\''/g"`;; #'(
+      *) as_qdir=$as_dir;;
+      esac
+      as_dirs="'$as_qdir' $as_dirs"
+      as_dir=`$as_dirname -- "$as_dir" ||
+$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
+	 X"$as_dir" : 'X\(//\)[^/]' \| \
+	 X"$as_dir" : 'X\(//\)$' \| \
+	 X"$as_dir" : 'X\(/\)' \| . 2>/dev/null ||
+$as_echo X"$as_dir" |
+    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{
+	    s//\1/
+	    q
+	  }
+	  /^X\(\/\/\)[^/].*/{
+	    s//\1/
+	    q
+	  }
+	  /^X\(\/\/\)$/{
+	    s//\1/
+	    q
+	  }
+	  /^X\(\/\).*/{
+	    s//\1/
+	    q
+	  }
+	  s/.*/./; q'`
+      test -d "$as_dir" && break
+    done
+    test -z "$as_dirs" || eval "mkdir $as_dirs"
+  } || test -d "$as_dir" || as_fn_error $? "cannot create directory $as_dir"
+
+
+} # as_fn_mkdir_p
+
+# as_fn_executable_p FILE
+# -----------------------
+# Test if FILE is an executable regular file.
+as_fn_executable_p ()
+{
+  test -f "$1" && test -x "$1"
+} # as_fn_executable_p
+# as_fn_append VAR VALUE
+# ----------------------
+# Append the text in VALUE to the end of the definition contained in VAR. Take
+# advantage of any shell optimizations that allow amortized linear growth over
+# repeated appends, instead of the typical quadratic growth present in naive
+# implementations.
+if (eval "as_var=1; as_var+=2; test x\$as_var = x12") 2>/dev/null; then :
+  eval 'as_fn_append ()
+  {
+    eval $1+=\$2
+  }'
+else
+  as_fn_append ()
+  {
+    eval $1=\$$1\$2
+  }
+fi # as_fn_append
+
+# as_fn_arith ARG...
+# ------------------
+# Perform arithmetic evaluation on the ARGs, and store the result in the
+# global $as_val. Take advantage of shells that can avoid forks. The arguments
+# must be portable across $(()) and expr.
+if (eval "test \$(( 1 + 1 )) = 2") 2>/dev/null; then :
+  eval 'as_fn_arith ()
+  {
+    as_val=$(( $* ))
+  }'
+else
+  as_fn_arith ()
+  {
+    as_val=`expr "$@" || test $? -eq 1`
+  }
+fi # as_fn_arith
+
+
+# as_fn_error STATUS ERROR [LINENO LOG_FD]
+# ----------------------------------------
+# Output "`basename $0`: error: ERROR" to stderr. If LINENO and LOG_FD are
+# provided, also output the error to LOG_FD, referencing LINENO. Then exit the
+# script with STATUS, using 1 if that was 0.
+as_fn_error ()
+{
+  as_status=$1; test $as_status -eq 0 && as_status=1
+  if test "$4"; then
+    as_lineno=${as_lineno-"$3"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
+    $as_echo "$as_me:${as_lineno-$LINENO}: error: $2" >&$4
+  fi
+  $as_echo "$as_me: error: $2" >&2
+  as_fn_exit $as_status
+} # as_fn_error
+
+if expr a : '\(a\)' >/dev/null 2>&1 &&
+   test "X`expr 00001 : '.*\(...\)'`" = X001; then
+  as_expr=expr
+else
+  as_expr=false
+fi
+
+if (basename -- /) >/dev/null 2>&1 && test "X`basename -- / 2>&1`" = "X/"; then
+  as_basename=basename
+else
+  as_basename=false
+fi
+
+if (as_dir=`dirname -- /` && test "X$as_dir" = X/) >/dev/null 2>&1; then
+  as_dirname=dirname
+else
+  as_dirname=false
+fi
+
+as_me=`$as_basename -- "$0" ||
+$as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \
+	 X"$0" : 'X\(//\)$' \| \
+	 X"$0" : 'X\(/\)' \| . 2>/dev/null ||
+$as_echo X/"$0" |
+    sed '/^.*\/\([^/][^/]*\)\/*$/{
+	    s//\1/
+	    q
+	  }
+	  /^X\/\(\/\/\)$/{
+	    s//\1/
+	    q
+	  }
+	  /^X\/\(\/\).*/{
+	    s//\1/
+	    q
+	  }
+	  s/.*/./; q'`
+
+# Avoid depending upon Character Ranges.
+as_cr_letters='abcdefghijklmnopqrstuvwxyz'
+as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ'
+as_cr_Letters=$as_cr_letters$as_cr_LETTERS
+as_cr_digits='0123456789'
+as_cr_alnum=$as_cr_Letters$as_cr_digits
+
+
+  as_lineno_1=$LINENO as_lineno_1a=$LINENO
+  as_lineno_2=$LINENO as_lineno_2a=$LINENO
+  eval 'test "x$as_lineno_1'$as_run'" != "x$as_lineno_2'$as_run'" &&
+  test "x`expr $as_lineno_1'$as_run' + 1`" = "x$as_lineno_2'$as_run'"' || {
+  # Blame Lee E. McMahon (1931-1989) for sed's syntax.  :-)
+  sed -n '
+    p
+    /[$]LINENO/=
+  ' <$as_myself |
+    sed '
+      s/[$]LINENO.*/&-/
+      t lineno
+      b
+      :lineno
+      N
+      :loop
+      s/[$]LINENO\([^'$as_cr_alnum'_].*\n\)\(.*\)/\2\1\2/
+      t loop
+      s/-\n.*//
+    ' >$as_me.lineno &&
+  chmod +x "$as_me.lineno" ||
+    { $as_echo "$as_me: error: cannot create $as_me.lineno; rerun with a POSIX shell" >&2; as_fn_exit 1; }
+
+  # If we had to re-execute with $CONFIG_SHELL, we're ensured to have
+  # already done that, so ensure we don't try to do so again and fall
+  # in an infinite loop.  This has already happened in practice.
+  _as_can_reexec=no; export _as_can_reexec
+  # Don't try to exec as it changes $[0], causing all sort of problems
+  # (the dirname of $[0] is not the place where we might find the
+  # original and so on.  Autoconf is especially sensitive to this).
+  . "./$as_me.lineno"
+  # Exit status is that of the last command.
+  exit
+}
+
+ECHO_C= ECHO_N= ECHO_T=
+case `echo -n x` in #(((((
+-n*)
+  case `echo 'xy\c'` in
+  *c*) ECHO_T='	';;	# ECHO_T is single tab character.
+  xy)  ECHO_C='\c';;
+  *)   echo `echo ksh88 bug on AIX 6.1` > /dev/null
+       ECHO_T='	';;
+  esac;;
+*)
+  ECHO_N='-n';;
+esac
+
+rm -f conf$$ conf$$.exe conf$$.file
+if test -d conf$$.dir; then
+  rm -f conf$$.dir/conf$$.file
+else
+  rm -f conf$$.dir
+  mkdir conf$$.dir 2>/dev/null
+fi
+if (echo >conf$$.file) 2>/dev/null; then
+  if ln -s conf$$.file conf$$ 2>/dev/null; then
+    as_ln_s='ln -s'
+    # ... but there are two gotchas:
+    # 1) On MSYS, both `ln -s file dir' and `ln file dir' fail.
+    # 2) DJGPP < 2.04 has no symlinks; `ln -s' creates a wrapper executable.
+    # In both cases, we have to default to `cp -pR'.
+    ln -s conf$$.file conf$$.dir 2>/dev/null && test ! -f conf$$.exe ||
+      as_ln_s='cp -pR'
+  elif ln conf$$.file conf$$ 2>/dev/null; then
+    as_ln_s=ln
+  else
+    as_ln_s='cp -pR'
+  fi
+else
+  as_ln_s='cp -pR'
+fi
+rm -f conf$$ conf$$.exe conf$$.dir/conf$$.file conf$$.file
+rmdir conf$$.dir 2>/dev/null
+
+if mkdir -p . 2>/dev/null; then
+  as_mkdir_p='mkdir -p "$as_dir"'
+else
+  test -d ./-p && rmdir ./-p
+  as_mkdir_p=false
+fi
+
+as_test_x='test -x'
+as_executable_p=as_fn_executable_p
+
+# Sed expression to map a string onto a valid CPP name.
+as_tr_cpp="eval sed 'y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g'"
+
+# Sed expression to map a string onto a valid variable name.
+as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'"
+
+
+test -n "$DJDIR" || exec 7<&0 </dev/null
+exec 6>&1
+
+# Name of the host.
+# hostname on some systems (SVR3.2, old GNU/Linux) returns a bogus exit status,
+# so uname gets run too.
+ac_hostname=`(hostname || uname -n) 2>/dev/null | sed 1q`
+
+#
+# Initializations.
+#
+ac_default_prefix=/usr/local
+ac_clean_files=
+ac_config_libobj_dir=.
+LIBOBJS=
+cross_compiling=no
+subdirs=
+MFLAGS=
+MAKEFLAGS=
+
+# Identity of this package.
+PACKAGE_NAME='riscv-tests'
+PACKAGE_TARNAME='riscv-tests'
+PACKAGE_VERSION='1.0'
+PACKAGE_STRING='riscv-tests 1.0'
+PACKAGE_BUGREPORT=''
+PACKAGE_URL=''
+
+ac_subst_vars='LTLIBOBJS
+LIBOBJS
+XLEN
+OBJEXT
+EXEEXT
+ac_ct_CC
+CPPFLAGS
+LDFLAGS
+CFLAGS
+CC
+target_alias
+host_alias
+build_alias
+LIBS
+ECHO_T
+ECHO_N
+ECHO_C
+DEFS
+mandir
+localedir
+libdir
+psdir
+pdfdir
+dvidir
+htmldir
+infodir
+docdir
+oldincludedir
+includedir
+localstatedir
+sharedstatedir
+sysconfdir
+datadir
+datarootdir
+libexecdir
+sbindir
+bindir
+program_transform_name
+prefix
+exec_prefix
+PACKAGE_URL
+PACKAGE_BUGREPORT
+PACKAGE_STRING
+PACKAGE_VERSION
+PACKAGE_TARNAME
+PACKAGE_NAME
+PATH_SEPARATOR
+SHELL'
+ac_subst_files=''
+ac_user_opts='
+enable_option_checking
+with_xlen
+'
+      ac_precious_vars='build_alias
+host_alias
+target_alias
+CC
+CFLAGS
+LDFLAGS
+LIBS
+CPPFLAGS'
+
+
+# Initialize some variables set by options.
+ac_init_help=
+ac_init_version=false
+ac_unrecognized_opts=
+ac_unrecognized_sep=
+# The variables have the same names as the options, with
+# dashes changed to underlines.
+cache_file=/dev/null
+exec_prefix=NONE
+no_create=
+no_recursion=
+prefix=NONE
+program_prefix=NONE
+program_suffix=NONE
+program_transform_name=s,x,x,
+silent=
+site=
+srcdir=
+verbose=
+x_includes=NONE
+x_libraries=NONE
+
+# Installation directory options.
+# These are left unexpanded so users can "make install exec_prefix=/foo"
+# and all the variables that are supposed to be based on exec_prefix
+# by default will actually change.
+# Use braces instead of parens because sh, perl, etc. also accept them.
+# (The list follows the same order as the GNU Coding Standards.)
+bindir='${exec_prefix}/bin'
+sbindir='${exec_prefix}/sbin'
+libexecdir='${exec_prefix}/libexec'
+datarootdir='${prefix}/share'
+datadir='${datarootdir}'
+sysconfdir='${prefix}/etc'
+sharedstatedir='${prefix}/com'
+localstatedir='${prefix}/var'
+includedir='${prefix}/include'
+oldincludedir='/usr/include'
+docdir='${datarootdir}/doc/${PACKAGE_TARNAME}'
+infodir='${datarootdir}/info'
+htmldir='${docdir}'
+dvidir='${docdir}'
+pdfdir='${docdir}'
+psdir='${docdir}'
+libdir='${exec_prefix}/lib'
+localedir='${datarootdir}/locale'
+mandir='${datarootdir}/man'
+
+ac_prev=
+ac_dashdash=
+for ac_option
+do
+  # If the previous option needs an argument, assign it.
+  if test -n "$ac_prev"; then
+    eval $ac_prev=\$ac_option
+    ac_prev=
+    continue
+  fi
+
+  case $ac_option in
+  *=?*) ac_optarg=`expr "X$ac_option" : '[^=]*=\(.*\)'` ;;
+  *=)   ac_optarg= ;;
+  *)    ac_optarg=yes ;;
+  esac
+
+  # Accept the important Cygnus configure options, so we can diagnose typos.
+
+  case $ac_dashdash$ac_option in
+  --)
+    ac_dashdash=yes ;;
+
+  -bindir | --bindir | --bindi | --bind | --bin | --bi)
+    ac_prev=bindir ;;
+  -bindir=* | --bindir=* | --bindi=* | --bind=* | --bin=* | --bi=*)
+    bindir=$ac_optarg ;;
+
+  -build | --build | --buil | --bui | --bu)
+    ac_prev=build_alias ;;
+  -build=* | --build=* | --buil=* | --bui=* | --bu=*)
+    build_alias=$ac_optarg ;;
+
+  -cache-file | --cache-file | --cache-fil | --cache-fi \
+  | --cache-f | --cache- | --cache | --cach | --cac | --ca | --c)
+    ac_prev=cache_file ;;
+  -cache-file=* | --cache-file=* | --cache-fil=* | --cache-fi=* \
+  | --cache-f=* | --cache-=* | --cache=* | --cach=* | --cac=* | --ca=* | --c=*)
+    cache_file=$ac_optarg ;;
+
+  --config-cache | -C)
+    cache_file=config.cache ;;
+
+  -datadir | --datadir | --datadi | --datad)
+    ac_prev=datadir ;;
+  -datadir=* | --datadir=* | --datadi=* | --datad=*)
+    datadir=$ac_optarg ;;
+
+  -datarootdir | --datarootdir | --datarootdi | --datarootd | --dataroot \
+  | --dataroo | --dataro | --datar)
+    ac_prev=datarootdir ;;
+  -datarootdir=* | --datarootdir=* | --datarootdi=* | --datarootd=* \
+  | --dataroot=* | --dataroo=* | --dataro=* | --datar=*)
+    datarootdir=$ac_optarg ;;
+
+  -disable-* | --disable-*)
+    ac_useropt=`expr "x$ac_option" : 'x-*disable-\(.*\)'`
+    # Reject names that are not valid shell variable names.
+    expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null &&
+      as_fn_error $? "invalid feature name: $ac_useropt"
+    ac_useropt_orig=$ac_useropt
+    ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'`
+    case $ac_user_opts in
+      *"
+"enable_$ac_useropt"
+"*) ;;
+      *) ac_unrecognized_opts="$ac_unrecognized_opts$ac_unrecognized_sep--disable-$ac_useropt_orig"
+	 ac_unrecognized_sep=', ';;
+    esac
+    eval enable_$ac_useropt=no ;;
+
+  -docdir | --docdir | --docdi | --doc | --do)
+    ac_prev=docdir ;;
+  -docdir=* | --docdir=* | --docdi=* | --doc=* | --do=*)
+    docdir=$ac_optarg ;;
+
+  -dvidir | --dvidir | --dvidi | --dvid | --dvi | --dv)
+    ac_prev=dvidir ;;
+  -dvidir=* | --dvidir=* | --dvidi=* | --dvid=* | --dvi=* | --dv=*)
+    dvidir=$ac_optarg ;;
+
+  -enable-* | --enable-*)
+    ac_useropt=`expr "x$ac_option" : 'x-*enable-\([^=]*\)'`
+    # Reject names that are not valid shell variable names.
+    expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null &&
+      as_fn_error $? "invalid feature name: $ac_useropt"
+    ac_useropt_orig=$ac_useropt
+    ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'`
+    case $ac_user_opts in
+      *"
+"enable_$ac_useropt"
+"*) ;;
+      *) ac_unrecognized_opts="$ac_unrecognized_opts$ac_unrecognized_sep--enable-$ac_useropt_orig"
+	 ac_unrecognized_sep=', ';;
+    esac
+    eval enable_$ac_useropt=\$ac_optarg ;;
+
+  -exec-prefix | --exec_prefix | --exec-prefix | --exec-prefi \
+  | --exec-pref | --exec-pre | --exec-pr | --exec-p | --exec- \
+  | --exec | --exe | --ex)
+    ac_prev=exec_prefix ;;
+  -exec-prefix=* | --exec_prefix=* | --exec-prefix=* | --exec-prefi=* \
+  | --exec-pref=* | --exec-pre=* | --exec-pr=* | --exec-p=* | --exec-=* \
+  | --exec=* | --exe=* | --ex=*)
+    exec_prefix=$ac_optarg ;;
+
+  -gas | --gas | --ga | --g)
+    # Obsolete; use --with-gas.
+    with_gas=yes ;;
+
+  -help | --help | --hel | --he | -h)
+    ac_init_help=long ;;
+  -help=r* | --help=r* | --hel=r* | --he=r* | -hr*)
+    ac_init_help=recursive ;;
+  -help=s* | --help=s* | --hel=s* | --he=s* | -hs*)
+    ac_init_help=short ;;
+
+  -host | --host | --hos | --ho)
+    ac_prev=host_alias ;;
+  -host=* | --host=* | --hos=* | --ho=*)
+    host_alias=$ac_optarg ;;
+
+  -htmldir | --htmldir | --htmldi | --htmld | --html | --htm | --ht)
+    ac_prev=htmldir ;;
+  -htmldir=* | --htmldir=* | --htmldi=* | --htmld=* | --html=* | --htm=* \
+  | --ht=*)
+    htmldir=$ac_optarg ;;
+
+  -includedir | --includedir | --includedi | --included | --include \
+  | --includ | --inclu | --incl | --inc)
+    ac_prev=includedir ;;
+  -includedir=* | --includedir=* | --includedi=* | --included=* | --include=* \
+  | --includ=* | --inclu=* | --incl=* | --inc=*)
+    includedir=$ac_optarg ;;
+
+  -infodir | --infodir | --infodi | --infod | --info | --inf)
+    ac_prev=infodir ;;
+  -infodir=* | --infodir=* | --infodi=* | --infod=* | --info=* | --inf=*)
+    infodir=$ac_optarg ;;
+
+  -libdir | --libdir | --libdi | --libd)
+    ac_prev=libdir ;;
+  -libdir=* | --libdir=* | --libdi=* | --libd=*)
+    libdir=$ac_optarg ;;
+
+  -libexecdir | --libexecdir | --libexecdi | --libexecd | --libexec \
+  | --libexe | --libex | --libe)
+    ac_prev=libexecdir ;;
+  -libexecdir=* | --libexecdir=* | --libexecdi=* | --libexecd=* | --libexec=* \
+  | --libexe=* | --libex=* | --libe=*)
+    libexecdir=$ac_optarg ;;
+
+  -localedir | --localedir | --localedi | --localed | --locale)
+    ac_prev=localedir ;;
+  -localedir=* | --localedir=* | --localedi=* | --localed=* | --locale=*)
+    localedir=$ac_optarg ;;
+
+  -localstatedir | --localstatedir | --localstatedi | --localstated \
+  | --localstate | --localstat | --localsta | --localst | --locals)
+    ac_prev=localstatedir ;;
+  -localstatedir=* | --localstatedir=* | --localstatedi=* | --localstated=* \
+  | --localstate=* | --localstat=* | --localsta=* | --localst=* | --locals=*)
+    localstatedir=$ac_optarg ;;
+
+  -mandir | --mandir | --mandi | --mand | --man | --ma | --m)
+    ac_prev=mandir ;;
+  -mandir=* | --mandir=* | --mandi=* | --mand=* | --man=* | --ma=* | --m=*)
+    mandir=$ac_optarg ;;
+
+  -nfp | --nfp | --nf)
+    # Obsolete; use --without-fp.
+    with_fp=no ;;
+
+  -no-create | --no-create | --no-creat | --no-crea | --no-cre \
+  | --no-cr | --no-c | -n)
+    no_create=yes ;;
+
+  -no-recursion | --no-recursion | --no-recursio | --no-recursi \
+  | --no-recurs | --no-recur | --no-recu | --no-rec | --no-re | --no-r)
+    no_recursion=yes ;;
+
+  -oldincludedir | --oldincludedir | --oldincludedi | --oldincluded \
+  | --oldinclude | --oldinclud | --oldinclu | --oldincl | --oldinc \
+  | --oldin | --oldi | --old | --ol | --o)
+    ac_prev=oldincludedir ;;
+  -oldincludedir=* | --oldincludedir=* | --oldincludedi=* | --oldincluded=* \
+  | --oldinclude=* | --oldinclud=* | --oldinclu=* | --oldincl=* | --oldinc=* \
+  | --oldin=* | --oldi=* | --old=* | --ol=* | --o=*)
+    oldincludedir=$ac_optarg ;;
+
+  -prefix | --prefix | --prefi | --pref | --pre | --pr | --p)
+    ac_prev=prefix ;;
+  -prefix=* | --prefix=* | --prefi=* | --pref=* | --pre=* | --pr=* | --p=*)
+    prefix=$ac_optarg ;;
+
+  -program-prefix | --program-prefix | --program-prefi | --program-pref \
+  | --program-pre | --program-pr | --program-p)
+    ac_prev=program_prefix ;;
+  -program-prefix=* | --program-prefix=* | --program-prefi=* \
+  | --program-pref=* | --program-pre=* | --program-pr=* | --program-p=*)
+    program_prefix=$ac_optarg ;;
+
+  -program-suffix | --program-suffix | --program-suffi | --program-suff \
+  | --program-suf | --program-su | --program-s)
+    ac_prev=program_suffix ;;
+  -program-suffix=* | --program-suffix=* | --program-suffi=* \
+  | --program-suff=* | --program-suf=* | --program-su=* | --program-s=*)
+    program_suffix=$ac_optarg ;;
+
+  -program-transform-name | --program-transform-name \
+  | --program-transform-nam | --program-transform-na \
+  | --program-transform-n | --program-transform- \
+  | --program-transform | --program-transfor \
+  | --program-transfo | --program-transf \
+  | --program-trans | --program-tran \
+  | --progr-tra | --program-tr | --program-t)
+    ac_prev=program_transform_name ;;
+  -program-transform-name=* | --program-transform-name=* \
+  | --program-transform-nam=* | --program-transform-na=* \
+  | --program-transform-n=* | --program-transform-=* \
+  | --program-transform=* | --program-transfor=* \
+  | --program-transfo=* | --program-transf=* \
+  | --program-trans=* | --program-tran=* \
+  | --progr-tra=* | --program-tr=* | --program-t=*)
+    program_transform_name=$ac_optarg ;;
+
+  -pdfdir | --pdfdir | --pdfdi | --pdfd | --pdf | --pd)
+    ac_prev=pdfdir ;;
+  -pdfdir=* | --pdfdir=* | --pdfdi=* | --pdfd=* | --pdf=* | --pd=*)
+    pdfdir=$ac_optarg ;;
+
+  -psdir | --psdir | --psdi | --psd | --ps)
+    ac_prev=psdir ;;
+  -psdir=* | --psdir=* | --psdi=* | --psd=* | --ps=*)
+    psdir=$ac_optarg ;;
+
+  -q | -quiet | --quiet | --quie | --qui | --qu | --q \
+  | -silent | --silent | --silen | --sile | --sil)
+    silent=yes ;;
+
+  -sbindir | --sbindir | --sbindi | --sbind | --sbin | --sbi | --sb)
+    ac_prev=sbindir ;;
+  -sbindir=* | --sbindir=* | --sbindi=* | --sbind=* | --sbin=* \
+  | --sbi=* | --sb=*)
+    sbindir=$ac_optarg ;;
+
+  -sharedstatedir | --sharedstatedir | --sharedstatedi \
+  | --sharedstated | --sharedstate | --sharedstat | --sharedsta \
+  | --sharedst | --shareds | --shared | --share | --shar \
+  | --sha | --sh)
+    ac_prev=sharedstatedir ;;
+  -sharedstatedir=* | --sharedstatedir=* | --sharedstatedi=* \
+  | --sharedstated=* | --sharedstate=* | --sharedstat=* | --sharedsta=* \
+  | --sharedst=* | --shareds=* | --shared=* | --share=* | --shar=* \
+  | --sha=* | --sh=*)
+    sharedstatedir=$ac_optarg ;;
+
+  -site | --site | --sit)
+    ac_prev=site ;;
+  -site=* | --site=* | --sit=*)
+    site=$ac_optarg ;;
+
+  -srcdir | --srcdir | --srcdi | --srcd | --src | --sr)
+    ac_prev=srcdir ;;
+  -srcdir=* | --srcdir=* | --srcdi=* | --srcd=* | --src=* | --sr=*)
+    srcdir=$ac_optarg ;;
+
+  -sysconfdir | --sysconfdir | --sysconfdi | --sysconfd | --sysconf \
+  | --syscon | --sysco | --sysc | --sys | --sy)
+    ac_prev=sysconfdir ;;
+  -sysconfdir=* | --sysconfdir=* | --sysconfdi=* | --sysconfd=* | --sysconf=* \
+  | --syscon=* | --sysco=* | --sysc=* | --sys=* | --sy=*)
+    sysconfdir=$ac_optarg ;;
+
+  -target | --target | --targe | --targ | --tar | --ta | --t)
+    ac_prev=target_alias ;;
+  -target=* | --target=* | --targe=* | --targ=* | --tar=* | --ta=* | --t=*)
+    target_alias=$ac_optarg ;;
+
+  -v | -verbose | --verbose | --verbos | --verbo | --verb)
+    verbose=yes ;;
+
+  -version | --version | --versio | --versi | --vers | -V)
+    ac_init_version=: ;;
+
+  -with-* | --with-*)
+    ac_useropt=`expr "x$ac_option" : 'x-*with-\([^=]*\)'`
+    # Reject names that are not valid shell variable names.
+    expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null &&
+      as_fn_error $? "invalid package name: $ac_useropt"
+    ac_useropt_orig=$ac_useropt
+    ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'`
+    case $ac_user_opts in
+      *"
+"with_$ac_useropt"
+"*) ;;
+      *) ac_unrecognized_opts="$ac_unrecognized_opts$ac_unrecognized_sep--with-$ac_useropt_orig"
+	 ac_unrecognized_sep=', ';;
+    esac
+    eval with_$ac_useropt=\$ac_optarg ;;
+
+  -without-* | --without-*)
+    ac_useropt=`expr "x$ac_option" : 'x-*without-\(.*\)'`
+    # Reject names that are not valid shell variable names.
+    expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null &&
+      as_fn_error $? "invalid package name: $ac_useropt"
+    ac_useropt_orig=$ac_useropt
+    ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'`
+    case $ac_user_opts in
+      *"
+"with_$ac_useropt"
+"*) ;;
+      *) ac_unrecognized_opts="$ac_unrecognized_opts$ac_unrecognized_sep--without-$ac_useropt_orig"
+	 ac_unrecognized_sep=', ';;
+    esac
+    eval with_$ac_useropt=no ;;
+
+  --x)
+    # Obsolete; use --with-x.
+    with_x=yes ;;
+
+  -x-includes | --x-includes | --x-include | --x-includ | --x-inclu \
+  | --x-incl | --x-inc | --x-in | --x-i)
+    ac_prev=x_includes ;;
+  -x-includes=* | --x-includes=* | --x-include=* | --x-includ=* | --x-inclu=* \
+  | --x-incl=* | --x-inc=* | --x-in=* | --x-i=*)
+    x_includes=$ac_optarg ;;
+
+  -x-libraries | --x-libraries | --x-librarie | --x-librari \
+  | --x-librar | --x-libra | --x-libr | --x-lib | --x-li | --x-l)
+    ac_prev=x_libraries ;;
+  -x-libraries=* | --x-libraries=* | --x-librarie=* | --x-librari=* \
+  | --x-librar=* | --x-libra=* | --x-libr=* | --x-lib=* | --x-li=* | --x-l=*)
+    x_libraries=$ac_optarg ;;
+
+  -*) as_fn_error $? "unrecognized option: \`$ac_option'
+Try \`$0 --help' for more information"
+    ;;
+
+  *=*)
+    ac_envvar=`expr "x$ac_option" : 'x\([^=]*\)='`
+    # Reject names that are not valid shell variable names.
+    case $ac_envvar in #(
+      '' | [0-9]* | *[!_$as_cr_alnum]* )
+      as_fn_error $? "invalid variable name: \`$ac_envvar'" ;;
+    esac
+    eval $ac_envvar=\$ac_optarg
+    export $ac_envvar ;;
+
+  *)
+    # FIXME: should be removed in autoconf 3.0.
+    $as_echo "$as_me: WARNING: you should use --build, --host, --target" >&2
+    expr "x$ac_option" : ".*[^-._$as_cr_alnum]" >/dev/null &&
+      $as_echo "$as_me: WARNING: invalid host type: $ac_option" >&2
+    : "${build_alias=$ac_option} ${host_alias=$ac_option} ${target_alias=$ac_option}"
+    ;;
+
+  esac
+done
+
+if test -n "$ac_prev"; then
+  ac_option=--`echo $ac_prev | sed 's/_/-/g'`
+  as_fn_error $? "missing argument to $ac_option"
+fi
+
+if test -n "$ac_unrecognized_opts"; then
+  case $enable_option_checking in
+    no) ;;
+    fatal) as_fn_error $? "unrecognized options: $ac_unrecognized_opts" ;;
+    *)     $as_echo "$as_me: WARNING: unrecognized options: $ac_unrecognized_opts" >&2 ;;
+  esac
+fi
+
+# Check all directory arguments for consistency.
+for ac_var in	exec_prefix prefix bindir sbindir libexecdir datarootdir \
+		datadir sysconfdir sharedstatedir localstatedir includedir \
+		oldincludedir docdir infodir htmldir dvidir pdfdir psdir \
+		libdir localedir mandir
+do
+  eval ac_val=\$$ac_var
+  # Remove trailing slashes.
+  case $ac_val in
+    */ )
+      ac_val=`expr "X$ac_val" : 'X\(.*[^/]\)' \| "X$ac_val" : 'X\(.*\)'`
+      eval $ac_var=\$ac_val;;
+  esac
+  # Be sure to have absolute directory names.
+  case $ac_val in
+    [\\/$]* | ?:[\\/]* )  continue;;
+    NONE | '' ) case $ac_var in *prefix ) continue;; esac;;
+  esac
+  as_fn_error $? "expected an absolute directory name for --$ac_var: $ac_val"
+done
+
+# There might be people who depend on the old broken behavior: `$host'
+# used to hold the argument of --host etc.
+# FIXME: To remove some day.
+build=$build_alias
+host=$host_alias
+target=$target_alias
+
+# FIXME: To remove some day.
+if test "x$host_alias" != x; then
+  if test "x$build_alias" = x; then
+    cross_compiling=maybe
+  elif test "x$build_alias" != "x$host_alias"; then
+    cross_compiling=yes
+  fi
+fi
+
+ac_tool_prefix=
+test -n "$host_alias" && ac_tool_prefix=$host_alias-
+
+test "$silent" = yes && exec 6>/dev/null
+
+
+ac_pwd=`pwd` && test -n "$ac_pwd" &&
+ac_ls_di=`ls -di .` &&
+ac_pwd_ls_di=`cd "$ac_pwd" && ls -di .` ||
+  as_fn_error $? "working directory cannot be determined"
+test "X$ac_ls_di" = "X$ac_pwd_ls_di" ||
+  as_fn_error $? "pwd does not report name of working directory"
+
+
+# Find the source files, if location was not specified.
+if test -z "$srcdir"; then
+  ac_srcdir_defaulted=yes
+  # Try the directory containing this script, then the parent directory.
+  ac_confdir=`$as_dirname -- "$as_myself" ||
+$as_expr X"$as_myself" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
+	 X"$as_myself" : 'X\(//\)[^/]' \| \
+	 X"$as_myself" : 'X\(//\)$' \| \
+	 X"$as_myself" : 'X\(/\)' \| . 2>/dev/null ||
+$as_echo X"$as_myself" |
+    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{
+	    s//\1/
+	    q
+	  }
+	  /^X\(\/\/\)[^/].*/{
+	    s//\1/
+	    q
+	  }
+	  /^X\(\/\/\)$/{
+	    s//\1/
+	    q
+	  }
+	  /^X\(\/\).*/{
+	    s//\1/
+	    q
+	  }
+	  s/.*/./; q'`
+  srcdir=$ac_confdir
+  if test ! -r "$srcdir/$ac_unique_file"; then
+    srcdir=..
+  fi
+else
+  ac_srcdir_defaulted=no
+fi
+if test ! -r "$srcdir/$ac_unique_file"; then
+  test "$ac_srcdir_defaulted" = yes && srcdir="$ac_confdir or .."
+  as_fn_error $? "cannot find sources ($ac_unique_file) in $srcdir"
+fi
+ac_msg="sources are in $srcdir, but \`cd $srcdir' does not work"
+ac_abs_confdir=`(
+	cd "$srcdir" && test -r "./$ac_unique_file" || as_fn_error $? "$ac_msg"
+	pwd)`
+# When building in place, set srcdir=.
+if test "$ac_abs_confdir" = "$ac_pwd"; then
+  srcdir=.
+fi
+# Remove unnecessary trailing slashes from srcdir.
+# Double slashes in file names in object file debugging info
+# mess up M-x gdb in Emacs.
+case $srcdir in
+*/) srcdir=`expr "X$srcdir" : 'X\(.*[^/]\)' \| "X$srcdir" : 'X\(.*\)'`;;
+esac
+for ac_var in $ac_precious_vars; do
+  eval ac_env_${ac_var}_set=\${${ac_var}+set}
+  eval ac_env_${ac_var}_value=\$${ac_var}
+  eval ac_cv_env_${ac_var}_set=\${${ac_var}+set}
+  eval ac_cv_env_${ac_var}_value=\$${ac_var}
+done
+
+#
+# Report the --help message.
+#
+if test "$ac_init_help" = "long"; then
+  # Omit some internal or obsolete options to make the list less imposing.
+  # This message is too long to be a string in the A/UX 3.1 sh.
+  cat <<_ACEOF
+\`configure' configures riscv-tests 1.0 to adapt to many kinds of systems.
+
+Usage: $0 [OPTION]... [VAR=VALUE]...
+
+To assign environment variables (e.g., CC, CFLAGS...), specify them as
+VAR=VALUE.  See below for descriptions of some of the useful variables.
+
+Defaults for the options are specified in brackets.
+
+Configuration:
+  -h, --help              display this help and exit
+      --help=short        display options specific to this package
+      --help=recursive    display the short help of all the included packages
+  -V, --version           display version information and exit
+  -q, --quiet, --silent   do not print \`checking ...' messages
+      --cache-file=FILE   cache test results in FILE [disabled]
+  -C, --config-cache      alias for \`--cache-file=config.cache'
+  -n, --no-create         do not create output files
+      --srcdir=DIR        find the sources in DIR [configure dir or \`..']
+
+Installation directories:
+  --prefix=PREFIX         install architecture-independent files in PREFIX
+                          [$ac_default_prefix]
+  --exec-prefix=EPREFIX   install architecture-dependent files in EPREFIX
+                          [PREFIX]
+
+By default, \`make install' will install all the files in
+\`$ac_default_prefix/bin', \`$ac_default_prefix/lib' etc.  You can specify
+an installation prefix other than \`$ac_default_prefix' using \`--prefix',
+for instance \`--prefix=\$HOME'.
+
+For better control, use the options below.
+
+Fine tuning of the installation directories:
+  --bindir=DIR            user executables [EPREFIX/bin]
+  --sbindir=DIR           system admin executables [EPREFIX/sbin]
+  --libexecdir=DIR        program executables [EPREFIX/libexec]
+  --sysconfdir=DIR        read-only single-machine data [PREFIX/etc]
+  --sharedstatedir=DIR    modifiable architecture-independent data [PREFIX/com]
+  --localstatedir=DIR     modifiable single-machine data [PREFIX/var]
+  --libdir=DIR            object code libraries [EPREFIX/lib]
+  --includedir=DIR        C header files [PREFIX/include]
+  --oldincludedir=DIR     C header files for non-gcc [/usr/include]
+  --datarootdir=DIR       read-only arch.-independent data root [PREFIX/share]
+  --datadir=DIR           read-only architecture-independent data [DATAROOTDIR]
+  --infodir=DIR           info documentation [DATAROOTDIR/info]
+  --localedir=DIR         locale-dependent data [DATAROOTDIR/locale]
+  --mandir=DIR            man documentation [DATAROOTDIR/man]
+  --docdir=DIR            documentation root [DATAROOTDIR/doc/riscv-tests]
+  --htmldir=DIR           html documentation [DOCDIR]
+  --dvidir=DIR            dvi documentation [DOCDIR]
+  --pdfdir=DIR            pdf documentation [DOCDIR]
+  --psdir=DIR             ps documentation [DOCDIR]
+_ACEOF
+
+  cat <<\_ACEOF
+_ACEOF
+fi
+
+if test -n "$ac_init_help"; then
+  case $ac_init_help in
+     short | recursive ) echo "Configuration of riscv-tests 1.0:";;
+   esac
+  cat <<\_ACEOF
+
+Optional Packages:
+  --with-PACKAGE[=ARG]    use PACKAGE [ARG=yes]
+  --without-PACKAGE       do not use PACKAGE (same as --with-PACKAGE=no)
+  --with-xlen=XLEN        Set XLEN, the X-register bit width (default is 64)
+
+Some influential environment variables:
+  CC          C compiler command
+  CFLAGS      C compiler flags
+  LDFLAGS     linker flags, e.g. -L<lib dir> if you have libraries in a
+              nonstandard directory <lib dir>
+  LIBS        libraries to pass to the linker, e.g. -l<library>
+  CPPFLAGS    (Objective) C/C++ preprocessor flags, e.g. -I<include dir> if
+              you have headers in a nonstandard directory <include dir>
+
+Use these variables to override the choices made by `configure' or to help
+it to find libraries and programs with nonstandard names/locations.
+
+Report bugs to the package provider.
+_ACEOF
+ac_status=$?
+fi
+
+if test "$ac_init_help" = "recursive"; then
+  # If there are subdirs, report their specific --help.
+  for ac_dir in : $ac_subdirs_all; do test "x$ac_dir" = x: && continue
+    test -d "$ac_dir" ||
+      { cd "$srcdir" && ac_pwd=`pwd` && srcdir=. && test -d "$ac_dir"; } ||
+      continue
+    ac_builddir=.
+
+case "$ac_dir" in
+.) ac_dir_suffix= ac_top_builddir_sub=. ac_top_build_prefix= ;;
+*)
+  ac_dir_suffix=/`$as_echo "$ac_dir" | sed 's|^\.[\\/]||'`
+  # A ".." for each directory in $ac_dir_suffix.
+  ac_top_builddir_sub=`$as_echo "$ac_dir_suffix" | sed 's|/[^\\/]*|/..|g;s|/||'`
+  case $ac_top_builddir_sub in
+  "") ac_top_builddir_sub=. ac_top_build_prefix= ;;
+  *)  ac_top_build_prefix=$ac_top_builddir_sub/ ;;
+  esac ;;
+esac
+ac_abs_top_builddir=$ac_pwd
+ac_abs_builddir=$ac_pwd$ac_dir_suffix
+# for backward compatibility:
+ac_top_builddir=$ac_top_build_prefix
+
+case $srcdir in
+  .)  # We are building in place.
+    ac_srcdir=.
+    ac_top_srcdir=$ac_top_builddir_sub
+    ac_abs_top_srcdir=$ac_pwd ;;
+  [\\/]* | ?:[\\/]* )  # Absolute name.
+    ac_srcdir=$srcdir$ac_dir_suffix;
+    ac_top_srcdir=$srcdir
+    ac_abs_top_srcdir=$srcdir ;;
+  *) # Relative name.
+    ac_srcdir=$ac_top_build_prefix$srcdir$ac_dir_suffix
+    ac_top_srcdir=$ac_top_build_prefix$srcdir
+    ac_abs_top_srcdir=$ac_pwd/$srcdir ;;
+esac
+ac_abs_srcdir=$ac_abs_top_srcdir$ac_dir_suffix
+
+    cd "$ac_dir" || { ac_status=$?; continue; }
+    # Check for guested configure.
+    if test -f "$ac_srcdir/configure.gnu"; then
+      echo &&
+      $SHELL "$ac_srcdir/configure.gnu" --help=recursive
+    elif test -f "$ac_srcdir/configure"; then
+      echo &&
+      $SHELL "$ac_srcdir/configure" --help=recursive
+    else
+      $as_echo "$as_me: WARNING: no configuration information is in $ac_dir" >&2
+    fi || ac_status=$?
+    cd "$ac_pwd" || { ac_status=$?; break; }
+  done
+fi
+
+test -n "$ac_init_help" && exit $ac_status
+if $ac_init_version; then
+  cat <<\_ACEOF
+riscv-tests configure 1.0
+generated by GNU Autoconf 2.69
+
+Copyright (C) 2012 Free Software Foundation, Inc.
+This configure script is free software; the Free Software Foundation
+gives unlimited permission to copy, distribute and modify it.
+_ACEOF
+  exit
+fi
+
+## ------------------------ ##
+## Autoconf initialization. ##
+## ------------------------ ##
+
+# ac_fn_c_try_compile LINENO
+# --------------------------
+# Try to compile conftest.$ac_ext, and return whether this succeeded.
+ac_fn_c_try_compile ()
+{
+  as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
+  rm -f conftest.$ac_objext
+  if { { ac_try="$ac_compile"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
+$as_echo "$ac_try_echo"; } >&5
+  (eval "$ac_compile") 2>conftest.err
+  ac_status=$?
+  if test -s conftest.err; then
+    grep -v '^ *+' conftest.err >conftest.er1
+    cat conftest.er1 >&5
+    mv -f conftest.er1 conftest.err
+  fi
+  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+  test $ac_status = 0; } && {
+	 test -z "$ac_c_werror_flag" ||
+	 test ! -s conftest.err
+       } && test -s conftest.$ac_objext; then :
+  ac_retval=0
+else
+  $as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+	ac_retval=1
+fi
+  eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno
+  as_fn_set_status $ac_retval
+
+} # ac_fn_c_try_compile
+cat >config.log <<_ACEOF
+This file contains any messages produced by compilers while
+running configure, to aid debugging if configure makes a mistake.
+
+It was created by riscv-tests $as_me 1.0, which was
+generated by GNU Autoconf 2.69.  Invocation command line was
+
+  $ $0 $@
+
+_ACEOF
+exec 5>>config.log
+{
+cat <<_ASUNAME
+## --------- ##
+## Platform. ##
+## --------- ##
+
+hostname = `(hostname || uname -n) 2>/dev/null | sed 1q`
+uname -m = `(uname -m) 2>/dev/null || echo unknown`
+uname -r = `(uname -r) 2>/dev/null || echo unknown`
+uname -s = `(uname -s) 2>/dev/null || echo unknown`
+uname -v = `(uname -v) 2>/dev/null || echo unknown`
+
+/usr/bin/uname -p = `(/usr/bin/uname -p) 2>/dev/null || echo unknown`
+/bin/uname -X     = `(/bin/uname -X) 2>/dev/null     || echo unknown`
+
+/bin/arch              = `(/bin/arch) 2>/dev/null              || echo unknown`
+/usr/bin/arch -k       = `(/usr/bin/arch -k) 2>/dev/null       || echo unknown`
+/usr/convex/getsysinfo = `(/usr/convex/getsysinfo) 2>/dev/null || echo unknown`
+/usr/bin/hostinfo      = `(/usr/bin/hostinfo) 2>/dev/null      || echo unknown`
+/bin/machine           = `(/bin/machine) 2>/dev/null           || echo unknown`
+/usr/bin/oslevel       = `(/usr/bin/oslevel) 2>/dev/null       || echo unknown`
+/bin/universe          = `(/bin/universe) 2>/dev/null          || echo unknown`
+
+_ASUNAME
+
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+    $as_echo "PATH: $as_dir"
+  done
+IFS=$as_save_IFS
+
+} >&5
+
+cat >&5 <<_ACEOF
+
+
+## ----------- ##
+## Core tests. ##
+## ----------- ##
+
+_ACEOF
+
+
+# Keep a trace of the command line.
+# Strip out --no-create and --no-recursion so they do not pile up.
+# Strip out --silent because we don't want to record it for future runs.
+# Also quote any args containing shell meta-characters.
+# Make two passes to allow for proper duplicate-argument suppression.
+ac_configure_args=
+ac_configure_args0=
+ac_configure_args1=
+ac_must_keep_next=false
+for ac_pass in 1 2
+do
+  for ac_arg
+  do
+    case $ac_arg in
+    -no-create | --no-c* | -n | -no-recursion | --no-r*) continue ;;
+    -q | -quiet | --quiet | --quie | --qui | --qu | --q \
+    | -silent | --silent | --silen | --sile | --sil)
+      continue ;;
+    *\'*)
+      ac_arg=`$as_echo "$ac_arg" | sed "s/'/'\\\\\\\\''/g"` ;;
+    esac
+    case $ac_pass in
+    1) as_fn_append ac_configure_args0 " '$ac_arg'" ;;
+    2)
+      as_fn_append ac_configure_args1 " '$ac_arg'"
+      if test $ac_must_keep_next = true; then
+	ac_must_keep_next=false # Got value, back to normal.
+      else
+	case $ac_arg in
+	  *=* | --config-cache | -C | -disable-* | --disable-* \
+	  | -enable-* | --enable-* | -gas | --g* | -nfp | --nf* \
+	  | -q | -quiet | --q* | -silent | --sil* | -v | -verb* \
+	  | -with-* | --with-* | -without-* | --without-* | --x)
+	    case "$ac_configure_args0 " in
+	      "$ac_configure_args1"*" '$ac_arg' "* ) continue ;;
+	    esac
+	    ;;
+	  -* ) ac_must_keep_next=true ;;
+	esac
+      fi
+      as_fn_append ac_configure_args " '$ac_arg'"
+      ;;
+    esac
+  done
+done
+{ ac_configure_args0=; unset ac_configure_args0;}
+{ ac_configure_args1=; unset ac_configure_args1;}
+
+# When interrupted or exit'd, cleanup temporary files, and complete
+# config.log.  We remove comments because anyway the quotes in there
+# would cause problems or look ugly.
+# WARNING: Use '\'' to represent an apostrophe within the trap.
+# WARNING: Do not start the trap code with a newline, due to a FreeBSD 4.0 bug.
+trap 'exit_status=$?
+  # Save into config.log some information that might help in debugging.
+  {
+    echo
+
+    $as_echo "## ---------------- ##
+## Cache variables. ##
+## ---------------- ##"
+    echo
+    # The following way of writing the cache mishandles newlines in values,
+(
+  for ac_var in `(set) 2>&1 | sed -n '\''s/^\([a-zA-Z_][a-zA-Z0-9_]*\)=.*/\1/p'\''`; do
+    eval ac_val=\$$ac_var
+    case $ac_val in #(
+    *${as_nl}*)
+      case $ac_var in #(
+      *_cv_*) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: cache variable $ac_var contains a newline" >&5
+$as_echo "$as_me: WARNING: cache variable $ac_var contains a newline" >&2;} ;;
+      esac
+      case $ac_var in #(
+      _ | IFS | as_nl) ;; #(
+      BASH_ARGV | BASH_SOURCE) eval $ac_var= ;; #(
+      *) { eval $ac_var=; unset $ac_var;} ;;
+      esac ;;
+    esac
+  done
+  (set) 2>&1 |
+    case $as_nl`(ac_space='\'' '\''; set) 2>&1` in #(
+    *${as_nl}ac_space=\ *)
+      sed -n \
+	"s/'\''/'\''\\\\'\'''\''/g;
+	  s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='\''\\2'\''/p"
+      ;; #(
+    *)
+      sed -n "/^[_$as_cr_alnum]*_cv_[_$as_cr_alnum]*=/p"
+      ;;
+    esac |
+    sort
+)
+    echo
+
+    $as_echo "## ----------------- ##
+## Output variables. ##
+## ----------------- ##"
+    echo
+    for ac_var in $ac_subst_vars
+    do
+      eval ac_val=\$$ac_var
+      case $ac_val in
+      *\'\''*) ac_val=`$as_echo "$ac_val" | sed "s/'\''/'\''\\\\\\\\'\'''\''/g"`;;
+      esac
+      $as_echo "$ac_var='\''$ac_val'\''"
+    done | sort
+    echo
+
+    if test -n "$ac_subst_files"; then
+      $as_echo "## ------------------- ##
+## File substitutions. ##
+## ------------------- ##"
+      echo
+      for ac_var in $ac_subst_files
+      do
+	eval ac_val=\$$ac_var
+	case $ac_val in
+	*\'\''*) ac_val=`$as_echo "$ac_val" | sed "s/'\''/'\''\\\\\\\\'\'''\''/g"`;;
+	esac
+	$as_echo "$ac_var='\''$ac_val'\''"
+      done | sort
+      echo
+    fi
+
+    if test -s confdefs.h; then
+      $as_echo "## ----------- ##
+## confdefs.h. ##
+## ----------- ##"
+      echo
+      cat confdefs.h
+      echo
+    fi
+    test "$ac_signal" != 0 &&
+      $as_echo "$as_me: caught signal $ac_signal"
+    $as_echo "$as_me: exit $exit_status"
+  } >&5
+  rm -f core *.core core.conftest.* &&
+    rm -f -r conftest* confdefs* conf$$* $ac_clean_files &&
+    exit $exit_status
+' 0
+for ac_signal in 1 2 13 15; do
+  trap 'ac_signal='$ac_signal'; as_fn_exit 1' $ac_signal
+done
+ac_signal=0
+
+# confdefs.h avoids OS command line length limits that DEFS can exceed.
+rm -f -r conftest* confdefs.h
+
+$as_echo "/* confdefs.h */" > confdefs.h
+
+# Predefined preprocessor variables.
+
+cat >>confdefs.h <<_ACEOF
+#define PACKAGE_NAME "$PACKAGE_NAME"
+_ACEOF
+
+cat >>confdefs.h <<_ACEOF
+#define PACKAGE_TARNAME "$PACKAGE_TARNAME"
+_ACEOF
+
+cat >>confdefs.h <<_ACEOF
+#define PACKAGE_VERSION "$PACKAGE_VERSION"
+_ACEOF
+
+cat >>confdefs.h <<_ACEOF
+#define PACKAGE_STRING "$PACKAGE_STRING"
+_ACEOF
+
+cat >>confdefs.h <<_ACEOF
+#define PACKAGE_BUGREPORT "$PACKAGE_BUGREPORT"
+_ACEOF
+
+cat >>confdefs.h <<_ACEOF
+#define PACKAGE_URL "$PACKAGE_URL"
+_ACEOF
+
+
+# Let the site file select an alternate cache file if it wants to.
+# Prefer an explicitly selected file to automatically selected ones.
+ac_site_file1=NONE
+ac_site_file2=NONE
+if test -n "$CONFIG_SITE"; then
+  # We do not want a PATH search for config.site.
+  case $CONFIG_SITE in #((
+    -*)  ac_site_file1=./$CONFIG_SITE;;
+    */*) ac_site_file1=$CONFIG_SITE;;
+    *)   ac_site_file1=./$CONFIG_SITE;;
+  esac
+elif test "x$prefix" != xNONE; then
+  ac_site_file1=$prefix/share/config.site
+  ac_site_file2=$prefix/etc/config.site
+else
+  ac_site_file1=$ac_default_prefix/share/config.site
+  ac_site_file2=$ac_default_prefix/etc/config.site
+fi
+for ac_site_file in "$ac_site_file1" "$ac_site_file2"
+do
+  test "x$ac_site_file" = xNONE && continue
+  if test /dev/null != "$ac_site_file" && test -r "$ac_site_file"; then
+    { $as_echo "$as_me:${as_lineno-$LINENO}: loading site script $ac_site_file" >&5
+$as_echo "$as_me: loading site script $ac_site_file" >&6;}
+    sed 's/^/| /' "$ac_site_file" >&5
+    . "$ac_site_file" \
+      || { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
+$as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
+as_fn_error $? "failed to load site script $ac_site_file
+See \`config.log' for more details" "$LINENO" 5; }
+  fi
+done
+
+if test -r "$cache_file"; then
+  # Some versions of bash will fail to source /dev/null (special files
+  # actually), so we avoid doing that.  DJGPP emulates it as a regular file.
+  if test /dev/null != "$cache_file" && test -f "$cache_file"; then
+    { $as_echo "$as_me:${as_lineno-$LINENO}: loading cache $cache_file" >&5
+$as_echo "$as_me: loading cache $cache_file" >&6;}
+    case $cache_file in
+      [\\/]* | ?:[\\/]* ) . "$cache_file";;
+      *)                      . "./$cache_file";;
+    esac
+  fi
+else
+  { $as_echo "$as_me:${as_lineno-$LINENO}: creating cache $cache_file" >&5
+$as_echo "$as_me: creating cache $cache_file" >&6;}
+  >$cache_file
+fi
+
+# Check that the precious variables saved in the cache have kept the same
+# value.
+ac_cache_corrupted=false
+for ac_var in $ac_precious_vars; do
+  eval ac_old_set=\$ac_cv_env_${ac_var}_set
+  eval ac_new_set=\$ac_env_${ac_var}_set
+  eval ac_old_val=\$ac_cv_env_${ac_var}_value
+  eval ac_new_val=\$ac_env_${ac_var}_value
+  case $ac_old_set,$ac_new_set in
+    set,)
+      { $as_echo "$as_me:${as_lineno-$LINENO}: error: \`$ac_var' was set to \`$ac_old_val' in the previous run" >&5
+$as_echo "$as_me: error: \`$ac_var' was set to \`$ac_old_val' in the previous run" >&2;}
+      ac_cache_corrupted=: ;;
+    ,set)
+      { $as_echo "$as_me:${as_lineno-$LINENO}: error: \`$ac_var' was not set in the previous run" >&5
+$as_echo "$as_me: error: \`$ac_var' was not set in the previous run" >&2;}
+      ac_cache_corrupted=: ;;
+    ,);;
+    *)
+      if test "x$ac_old_val" != "x$ac_new_val"; then
+	# differences in whitespace do not lead to failure.
+	ac_old_val_w=`echo x $ac_old_val`
+	ac_new_val_w=`echo x $ac_new_val`
+	if test "$ac_old_val_w" != "$ac_new_val_w"; then
+	  { $as_echo "$as_me:${as_lineno-$LINENO}: error: \`$ac_var' has changed since the previous run:" >&5
+$as_echo "$as_me: error: \`$ac_var' has changed since the previous run:" >&2;}
+	  ac_cache_corrupted=:
+	else
+	  { $as_echo "$as_me:${as_lineno-$LINENO}: warning: ignoring whitespace changes in \`$ac_var' since the previous run:" >&5
+$as_echo "$as_me: warning: ignoring whitespace changes in \`$ac_var' since the previous run:" >&2;}
+	  eval $ac_var=\$ac_old_val
+	fi
+	{ $as_echo "$as_me:${as_lineno-$LINENO}:   former value:  \`$ac_old_val'" >&5
+$as_echo "$as_me:   former value:  \`$ac_old_val'" >&2;}
+	{ $as_echo "$as_me:${as_lineno-$LINENO}:   current value: \`$ac_new_val'" >&5
+$as_echo "$as_me:   current value: \`$ac_new_val'" >&2;}
+      fi;;
+  esac
+  # Pass precious variables to config.status.
+  if test "$ac_new_set" = set; then
+    case $ac_new_val in
+    *\'*) ac_arg=$ac_var=`$as_echo "$ac_new_val" | sed "s/'/'\\\\\\\\''/g"` ;;
+    *) ac_arg=$ac_var=$ac_new_val ;;
+    esac
+    case " $ac_configure_args " in
+      *" '$ac_arg' "*) ;; # Avoid dups.  Use of quotes ensures accuracy.
+      *) as_fn_append ac_configure_args " '$ac_arg'" ;;
+    esac
+  fi
+done
+if $ac_cache_corrupted; then
+  { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
+$as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
+  { $as_echo "$as_me:${as_lineno-$LINENO}: error: changes in the environment can compromise the build" >&5
+$as_echo "$as_me: error: changes in the environment can compromise the build" >&2;}
+  as_fn_error $? "run \`make distclean' and/or \`rm $cache_file' and start over" "$LINENO" 5
+fi
+## -------------------- ##
+## Main body of script. ##
+## -------------------- ##
+
+ac_ext=c
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
+ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
+ac_compiler_gnu=$ac_cv_c_compiler_gnu
+
+
+
+cross_compiling=yes
+ac_ext=c
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
+ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
+ac_compiler_gnu=$ac_cv_c_compiler_gnu
+if test -n "$ac_tool_prefix"; then
+  # Extract the first word of "${ac_tool_prefix}gcc", so it can be a program name with args.
+set dummy ${ac_tool_prefix}gcc; ac_word=$2
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
+$as_echo_n "checking for $ac_word... " >&6; }
+if ${ac_cv_prog_CC+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  if test -n "$CC"; then
+  ac_cv_prog_CC="$CC" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+    for ac_exec_ext in '' $ac_executable_extensions; do
+  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+    ac_cv_prog_CC="${ac_tool_prefix}gcc"
+    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
+    break 2
+  fi
+done
+  done
+IFS=$as_save_IFS
+
+fi
+fi
+CC=$ac_cv_prog_CC
+if test -n "$CC"; then
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5
+$as_echo "$CC" >&6; }
+else
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+fi
+
+
+fi
+if test -z "$ac_cv_prog_CC"; then
+  ac_ct_CC=$CC
+  # Extract the first word of "gcc", so it can be a program name with args.
+set dummy gcc; ac_word=$2
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
+$as_echo_n "checking for $ac_word... " >&6; }
+if ${ac_cv_prog_ac_ct_CC+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  if test -n "$ac_ct_CC"; then
+  ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+    for ac_exec_ext in '' $ac_executable_extensions; do
+  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+    ac_cv_prog_ac_ct_CC="gcc"
+    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
+    break 2
+  fi
+done
+  done
+IFS=$as_save_IFS
+
+fi
+fi
+ac_ct_CC=$ac_cv_prog_ac_ct_CC
+if test -n "$ac_ct_CC"; then
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CC" >&5
+$as_echo "$ac_ct_CC" >&6; }
+else
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+fi
+
+  if test "x$ac_ct_CC" = x; then
+    CC=""
+  else
+    case $cross_compiling:$ac_tool_warned in
+yes:)
+{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5
+$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;}
+ac_tool_warned=yes ;;
+esac
+    CC=$ac_ct_CC
+  fi
+else
+  CC="$ac_cv_prog_CC"
+fi
+
+if test -z "$CC"; then
+          if test -n "$ac_tool_prefix"; then
+    # Extract the first word of "${ac_tool_prefix}cc", so it can be a program name with args.
+set dummy ${ac_tool_prefix}cc; ac_word=$2
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
+$as_echo_n "checking for $ac_word... " >&6; }
+if ${ac_cv_prog_CC+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  if test -n "$CC"; then
+  ac_cv_prog_CC="$CC" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+    for ac_exec_ext in '' $ac_executable_extensions; do
+  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+    ac_cv_prog_CC="${ac_tool_prefix}cc"
+    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
+    break 2
+  fi
+done
+  done
+IFS=$as_save_IFS
+
+fi
+fi
+CC=$ac_cv_prog_CC
+if test -n "$CC"; then
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5
+$as_echo "$CC" >&6; }
+else
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+fi
+
+
+  fi
+fi
+if test -z "$CC"; then
+  # Extract the first word of "cc", so it can be a program name with args.
+set dummy cc; ac_word=$2
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
+$as_echo_n "checking for $ac_word... " >&6; }
+if ${ac_cv_prog_CC+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  if test -n "$CC"; then
+  ac_cv_prog_CC="$CC" # Let the user override the test.
+else
+  ac_prog_rejected=no
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+    for ac_exec_ext in '' $ac_executable_extensions; do
+  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+    if test "$as_dir/$ac_word$ac_exec_ext" = "/usr/ucb/cc"; then
+       ac_prog_rejected=yes
+       continue
+     fi
+    ac_cv_prog_CC="cc"
+    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
+    break 2
+  fi
+done
+  done
+IFS=$as_save_IFS
+
+if test $ac_prog_rejected = yes; then
+  # We found a bogon in the path, so make sure we never use it.
+  set dummy $ac_cv_prog_CC
+  shift
+  if test $# != 0; then
+    # We chose a different compiler from the bogus one.
+    # However, it has the same basename, so the bogon will be chosen
+    # first if we set CC to just the basename; use the full file name.
+    shift
+    ac_cv_prog_CC="$as_dir/$ac_word${1+' '}$@"
+  fi
+fi
+fi
+fi
+CC=$ac_cv_prog_CC
+if test -n "$CC"; then
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5
+$as_echo "$CC" >&6; }
+else
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+fi
+
+
+fi
+if test -z "$CC"; then
+  if test -n "$ac_tool_prefix"; then
+  for ac_prog in cl.exe
+  do
+    # Extract the first word of "$ac_tool_prefix$ac_prog", so it can be a program name with args.
+set dummy $ac_tool_prefix$ac_prog; ac_word=$2
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
+$as_echo_n "checking for $ac_word... " >&6; }
+if ${ac_cv_prog_CC+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  if test -n "$CC"; then
+  ac_cv_prog_CC="$CC" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+    for ac_exec_ext in '' $ac_executable_extensions; do
+  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+    ac_cv_prog_CC="$ac_tool_prefix$ac_prog"
+    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
+    break 2
+  fi
+done
+  done
+IFS=$as_save_IFS
+
+fi
+fi
+CC=$ac_cv_prog_CC
+if test -n "$CC"; then
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5
+$as_echo "$CC" >&6; }
+else
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+fi
+
+
+    test -n "$CC" && break
+  done
+fi
+if test -z "$CC"; then
+  ac_ct_CC=$CC
+  for ac_prog in cl.exe
+do
+  # Extract the first word of "$ac_prog", so it can be a program name with args.
+set dummy $ac_prog; ac_word=$2
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5
+$as_echo_n "checking for $ac_word... " >&6; }
+if ${ac_cv_prog_ac_ct_CC+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  if test -n "$ac_ct_CC"; then
+  ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+    for ac_exec_ext in '' $ac_executable_extensions; do
+  if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+    ac_cv_prog_ac_ct_CC="$ac_prog"
+    $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5
+    break 2
+  fi
+done
+  done
+IFS=$as_save_IFS
+
+fi
+fi
+ac_ct_CC=$ac_cv_prog_ac_ct_CC
+if test -n "$ac_ct_CC"; then
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CC" >&5
+$as_echo "$ac_ct_CC" >&6; }
+else
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+fi
+
+
+  test -n "$ac_ct_CC" && break
+done
+
+  if test "x$ac_ct_CC" = x; then
+    CC=""
+  else
+    case $cross_compiling:$ac_tool_warned in
+yes:)
+{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5
+$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;}
+ac_tool_warned=yes ;;
+esac
+    CC=$ac_ct_CC
+  fi
+fi
+
+fi
+
+
+test -z "$CC" && { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
+$as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
+as_fn_error $? "no acceptable C compiler found in \$PATH
+See \`config.log' for more details" "$LINENO" 5; }
+
+# Provide some information about the compiler.
+$as_echo "$as_me:${as_lineno-$LINENO}: checking for C compiler version" >&5
+set X $ac_compile
+ac_compiler=$2
+for ac_option in --version -v -V -qversion; do
+  { { ac_try="$ac_compiler $ac_option >&5"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
+$as_echo "$ac_try_echo"; } >&5
+  (eval "$ac_compiler $ac_option >&5") 2>conftest.err
+  ac_status=$?
+  if test -s conftest.err; then
+    sed '10a\
+... rest of stderr output deleted ...
+         10q' conftest.err >conftest.er1
+    cat conftest.er1 >&5
+  fi
+  rm -f conftest.er1 conftest.err
+  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+  test $ac_status = 0; }
+done
+
+cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+int
+main ()
+{
+
+  ;
+  return 0;
+}
+_ACEOF
+ac_clean_files_save=$ac_clean_files
+ac_clean_files="$ac_clean_files a.out a.out.dSYM a.exe b.out"
+# Try to create an executable without -o first, disregard a.out.
+# It will help us diagnose broken compilers, and finding out an intuition
+# of exeext.
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the C compiler works" >&5
+$as_echo_n "checking whether the C compiler works... " >&6; }
+ac_link_default=`$as_echo "$ac_link" | sed 's/ -o *conftest[^ ]*//'`
+
+# The possible output files:
+ac_files="a.out conftest.exe conftest a.exe a_out.exe b.out conftest.*"
+
+ac_rmfiles=
+for ac_file in $ac_files
+do
+  case $ac_file in
+    *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) ;;
+    * ) ac_rmfiles="$ac_rmfiles $ac_file";;
+  esac
+done
+rm -f $ac_rmfiles
+
+if { { ac_try="$ac_link_default"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
+$as_echo "$ac_try_echo"; } >&5
+  (eval "$ac_link_default") 2>&5
+  ac_status=$?
+  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+  test $ac_status = 0; }; then :
+  # Autoconf-2.13 could set the ac_cv_exeext variable to `no'.
+# So ignore a value of `no', otherwise this would lead to `EXEEXT = no'
+# in a Makefile.  We should not override ac_cv_exeext if it was cached,
+# so that the user can short-circuit this test for compilers unknown to
+# Autoconf.
+for ac_file in $ac_files ''
+do
+  test -f "$ac_file" || continue
+  case $ac_file in
+    *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj )
+	;;
+    [ab].out )
+	# We found the default executable, but exeext='' is most
+	# certainly right.
+	break;;
+    *.* )
+	if test "${ac_cv_exeext+set}" = set && test "$ac_cv_exeext" != no;
+	then :; else
+	   ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'`
+	fi
+	# We set ac_cv_exeext here because the later test for it is not
+	# safe: cross compilers may not add the suffix if given an `-o'
+	# argument, so we may need to know it at that point already.
+	# Even if this section looks crufty: it has the advantage of
+	# actually working.
+	break;;
+    * )
+	break;;
+  esac
+done
+test "$ac_cv_exeext" = no && ac_cv_exeext=
+
+else
+  ac_file=''
+fi
+if test -z "$ac_file"; then :
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5
+$as_echo "no" >&6; }
+$as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+{ { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
+$as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
+as_fn_error 77 "C compiler cannot create executables
+See \`config.log' for more details" "$LINENO" 5; }
+else
+  { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5
+$as_echo "yes" >&6; }
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for C compiler default output file name" >&5
+$as_echo_n "checking for C compiler default output file name... " >&6; }
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_file" >&5
+$as_echo "$ac_file" >&6; }
+ac_exeext=$ac_cv_exeext
+
+rm -f -r a.out a.out.dSYM a.exe conftest$ac_cv_exeext b.out
+ac_clean_files=$ac_clean_files_save
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for suffix of executables" >&5
+$as_echo_n "checking for suffix of executables... " >&6; }
+if { { ac_try="$ac_link"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
+$as_echo "$ac_try_echo"; } >&5
+  (eval "$ac_link") 2>&5
+  ac_status=$?
+  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+  test $ac_status = 0; }; then :
+  # If both `conftest.exe' and `conftest' are `present' (well, observable)
+# catch `conftest.exe'.  For instance with Cygwin, `ls conftest' will
+# work properly (i.e., refer to `conftest.exe'), while it won't with
+# `rm'.
+for ac_file in conftest.exe conftest conftest.*; do
+  test -f "$ac_file" || continue
+  case $ac_file in
+    *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) ;;
+    *.* ) ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'`
+	  break;;
+    * ) break;;
+  esac
+done
+else
+  { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
+$as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
+as_fn_error $? "cannot compute suffix of executables: cannot compile and link
+See \`config.log' for more details" "$LINENO" 5; }
+fi
+rm -f conftest conftest$ac_cv_exeext
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_exeext" >&5
+$as_echo "$ac_cv_exeext" >&6; }
+
+rm -f conftest.$ac_ext
+EXEEXT=$ac_cv_exeext
+ac_exeext=$EXEEXT
+cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+#include <stdio.h>
+int
+main ()
+{
+FILE *f = fopen ("conftest.out", "w");
+ return ferror (f) || fclose (f) != 0;
+
+  ;
+  return 0;
+}
+_ACEOF
+ac_clean_files="$ac_clean_files conftest.out"
+# Check that the compiler produces executables we can run.  If not, either
+# the compiler is broken, or we cross compile.
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are cross compiling" >&5
+$as_echo_n "checking whether we are cross compiling... " >&6; }
+if test "$cross_compiling" != yes; then
+  { { ac_try="$ac_link"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
+$as_echo "$ac_try_echo"; } >&5
+  (eval "$ac_link") 2>&5
+  ac_status=$?
+  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+  test $ac_status = 0; }
+  if { ac_try='./conftest$ac_cv_exeext'
+  { { case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
+$as_echo "$ac_try_echo"; } >&5
+  (eval "$ac_try") 2>&5
+  ac_status=$?
+  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+  test $ac_status = 0; }; }; then
+    cross_compiling=no
+  else
+    if test "$cross_compiling" = maybe; then
+	cross_compiling=yes
+    else
+	{ { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
+$as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
+as_fn_error $? "cannot run C compiled programs.
+If you meant to cross compile, use \`--host'.
+See \`config.log' for more details" "$LINENO" 5; }
+    fi
+  fi
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $cross_compiling" >&5
+$as_echo "$cross_compiling" >&6; }
+
+rm -f conftest.$ac_ext conftest$ac_cv_exeext conftest.out
+ac_clean_files=$ac_clean_files_save
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for suffix of object files" >&5
+$as_echo_n "checking for suffix of object files... " >&6; }
+if ${ac_cv_objext+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+int
+main ()
+{
+
+  ;
+  return 0;
+}
+_ACEOF
+rm -f conftest.o conftest.obj
+if { { ac_try="$ac_compile"
+case "(($ac_try" in
+  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
+  *) ac_try_echo=$ac_try;;
+esac
+eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\""
+$as_echo "$ac_try_echo"; } >&5
+  (eval "$ac_compile") 2>&5
+  ac_status=$?
+  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+  test $ac_status = 0; }; then :
+  for ac_file in conftest.o conftest.obj conftest.*; do
+  test -f "$ac_file" || continue;
+  case $ac_file in
+    *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM ) ;;
+    *) ac_cv_objext=`expr "$ac_file" : '.*\.\(.*\)'`
+       break;;
+  esac
+done
+else
+  $as_echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+{ { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5
+$as_echo "$as_me: error: in \`$ac_pwd':" >&2;}
+as_fn_error $? "cannot compute suffix of object files: cannot compile
+See \`config.log' for more details" "$LINENO" 5; }
+fi
+rm -f conftest.$ac_cv_objext conftest.$ac_ext
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_objext" >&5
+$as_echo "$ac_cv_objext" >&6; }
+OBJEXT=$ac_cv_objext
+ac_objext=$OBJEXT
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are using the GNU C compiler" >&5
+$as_echo_n "checking whether we are using the GNU C compiler... " >&6; }
+if ${ac_cv_c_compiler_gnu+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+int
+main ()
+{
+#ifndef __GNUC__
+       choke me
+#endif
+
+  ;
+  return 0;
+}
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  ac_compiler_gnu=yes
+else
+  ac_compiler_gnu=no
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+ac_cv_c_compiler_gnu=$ac_compiler_gnu
+
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_c_compiler_gnu" >&5
+$as_echo "$ac_cv_c_compiler_gnu" >&6; }
+if test $ac_compiler_gnu = yes; then
+  GCC=yes
+else
+  GCC=
+fi
+ac_test_CFLAGS=${CFLAGS+set}
+ac_save_CFLAGS=$CFLAGS
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $CC accepts -g" >&5
+$as_echo_n "checking whether $CC accepts -g... " >&6; }
+if ${ac_cv_prog_cc_g+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  ac_save_c_werror_flag=$ac_c_werror_flag
+   ac_c_werror_flag=yes
+   ac_cv_prog_cc_g=no
+   CFLAGS="-g"
+   cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+int
+main ()
+{
+
+  ;
+  return 0;
+}
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  ac_cv_prog_cc_g=yes
+else
+  CFLAGS=""
+      cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+int
+main ()
+{
+
+  ;
+  return 0;
+}
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+
+else
+  ac_c_werror_flag=$ac_save_c_werror_flag
+	 CFLAGS="-g"
+	 cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+int
+main ()
+{
+
+  ;
+  return 0;
+}
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  ac_cv_prog_cc_g=yes
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+   ac_c_werror_flag=$ac_save_c_werror_flag
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cc_g" >&5
+$as_echo "$ac_cv_prog_cc_g" >&6; }
+if test "$ac_test_CFLAGS" = set; then
+  CFLAGS=$ac_save_CFLAGS
+elif test $ac_cv_prog_cc_g = yes; then
+  if test "$GCC" = yes; then
+    CFLAGS="-g -O2"
+  else
+    CFLAGS="-g"
+  fi
+else
+  if test "$GCC" = yes; then
+    CFLAGS="-O2"
+  else
+    CFLAGS=
+  fi
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $CC option to accept ISO C89" >&5
+$as_echo_n "checking for $CC option to accept ISO C89... " >&6; }
+if ${ac_cv_prog_cc_c89+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  ac_cv_prog_cc_c89=no
+ac_save_CC=$CC
+cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+#include <stdarg.h>
+#include <stdio.h>
+struct stat;
+/* Most of the following tests are stolen from RCS 5.7's src/conf.sh.  */
+struct buf { int x; };
+FILE * (*rcsopen) (struct buf *, struct stat *, int);
+static char *e (p, i)
+     char **p;
+     int i;
+{
+  return p[i];
+}
+static char *f (char * (*g) (char **, int), char **p, ...)
+{
+  char *s;
+  va_list v;
+  va_start (v,p);
+  s = g (p, va_arg (v,int));
+  va_end (v);
+  return s;
+}
+
+/* OSF 4.0 Compaq cc is some sort of almost-ANSI by default.  It has
+   function prototypes and stuff, but not '\xHH' hex character constants.
+   These don't provoke an error unfortunately, instead are silently treated
+   as 'x'.  The following induces an error, until -std is added to get
+   proper ANSI mode.  Curiously '\x00'!='x' always comes out true, for an
+   array size at least.  It's necessary to write '\x00'==0 to get something
+   that's true only with -std.  */
+int osf4_cc_array ['\x00' == 0 ? 1 : -1];
+
+/* IBM C 6 for AIX is almost-ANSI by default, but it replaces macro parameters
+   inside strings and character constants.  */
+#define FOO(x) 'x'
+int xlc6_cc_array[FOO(a) == 'x' ? 1 : -1];
+
+int test (int i, double x);
+struct s1 {int (*f) (int a);};
+struct s2 {int (*f) (double a);};
+int pairnames (int, char **, FILE *(*)(struct buf *, struct stat *, int), int, int);
+int argc;
+char **argv;
+int
+main ()
+{
+return f (e, argv, 0) != argv[0]  ||  f (e, argv, 1) != argv[1];
+  ;
+  return 0;
+}
+_ACEOF
+for ac_arg in '' -qlanglvl=extc89 -qlanglvl=ansi -std \
+	-Ae "-Aa -D_HPUX_SOURCE" "-Xc -D__EXTENSIONS__"
+do
+  CC="$ac_save_CC $ac_arg"
+  if ac_fn_c_try_compile "$LINENO"; then :
+  ac_cv_prog_cc_c89=$ac_arg
+fi
+rm -f core conftest.err conftest.$ac_objext
+  test "x$ac_cv_prog_cc_c89" != "xno" && break
+done
+rm -f conftest.$ac_ext
+CC=$ac_save_CC
+
+fi
+# AC_CACHE_VAL
+case "x$ac_cv_prog_cc_c89" in
+  x)
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: none needed" >&5
+$as_echo "none needed" >&6; } ;;
+  xno)
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: unsupported" >&5
+$as_echo "unsupported" >&6; } ;;
+  *)
+    CC="$CC $ac_cv_prog_cc_c89"
+    { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cc_c89" >&5
+$as_echo "$ac_cv_prog_cc_c89" >&6; } ;;
+esac
+if test "x$ac_cv_prog_cc_c89" != xno; then :
+
+fi
+
+ac_ext=c
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
+ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
+ac_compiler_gnu=$ac_cv_c_compiler_gnu
+
+
+
+# Check whether --with-xlen was given.
+if test "${with_xlen+set}" = set; then :
+  withval=$with_xlen; XLEN=$withval
+
+else
+  XLEN=64
+
+
+fi
+
+
+
+ac_config_files="$ac_config_files Makefile"
+
+cat >confcache <<\_ACEOF
+# This file is a shell script that caches the results of configure
+# tests run on this system so they can be shared between configure
+# scripts and configure runs, see configure's option --config-cache.
+# It is not useful on other systems.  If it contains results you don't
+# want to keep, you may remove or edit it.
+#
+# config.status only pays attention to the cache file if you give it
+# the --recheck option to rerun configure.
+#
+# `ac_cv_env_foo' variables (set or unset) will be overridden when
+# loading this file, other *unset* `ac_cv_foo' will be assigned the
+# following values.
+
+_ACEOF
+
+# The following way of writing the cache mishandles newlines in values,
+# but we know of no workaround that is simple, portable, and efficient.
+# So, we kill variables containing newlines.
+# Ultrix sh set writes to stderr and can't be redirected directly,
+# and sets the high bit in the cache file unless we assign to the vars.
+(
+  for ac_var in `(set) 2>&1 | sed -n 's/^\([a-zA-Z_][a-zA-Z0-9_]*\)=.*/\1/p'`; do
+    eval ac_val=\$$ac_var
+    case $ac_val in #(
+    *${as_nl}*)
+      case $ac_var in #(
+      *_cv_*) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: cache variable $ac_var contains a newline" >&5
+$as_echo "$as_me: WARNING: cache variable $ac_var contains a newline" >&2;} ;;
+      esac
+      case $ac_var in #(
+      _ | IFS | as_nl) ;; #(
+      BASH_ARGV | BASH_SOURCE) eval $ac_var= ;; #(
+      *) { eval $ac_var=; unset $ac_var;} ;;
+      esac ;;
+    esac
+  done
+
+  (set) 2>&1 |
+    case $as_nl`(ac_space=' '; set) 2>&1` in #(
+    *${as_nl}ac_space=\ *)
+      # `set' does not quote correctly, so add quotes: double-quote
+      # substitution turns \\\\ into \\, and sed turns \\ into \.
+      sed -n \
+	"s/'/'\\\\''/g;
+	  s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='\\2'/p"
+      ;; #(
+    *)
+      # `set' quotes correctly as required by POSIX, so do not add quotes.
+      sed -n "/^[_$as_cr_alnum]*_cv_[_$as_cr_alnum]*=/p"
+      ;;
+    esac |
+    sort
+) |
+  sed '
+     /^ac_cv_env_/b end
+     t clear
+     :clear
+     s/^\([^=]*\)=\(.*[{}].*\)$/test "${\1+set}" = set || &/
+     t end
+     s/^\([^=]*\)=\(.*\)$/\1=${\1=\2}/
+     :end' >>confcache
+if diff "$cache_file" confcache >/dev/null 2>&1; then :; else
+  if test -w "$cache_file"; then
+    if test "x$cache_file" != "x/dev/null"; then
+      { $as_echo "$as_me:${as_lineno-$LINENO}: updating cache $cache_file" >&5
+$as_echo "$as_me: updating cache $cache_file" >&6;}
+      if test ! -f "$cache_file" || test -h "$cache_file"; then
+	cat confcache >"$cache_file"
+      else
+        case $cache_file in #(
+        */* | ?:*)
+	  mv -f confcache "$cache_file"$$ &&
+	  mv -f "$cache_file"$$ "$cache_file" ;; #(
+        *)
+	  mv -f confcache "$cache_file" ;;
+	esac
+      fi
+    fi
+  else
+    { $as_echo "$as_me:${as_lineno-$LINENO}: not updating unwritable cache $cache_file" >&5
+$as_echo "$as_me: not updating unwritable cache $cache_file" >&6;}
+  fi
+fi
+rm -f confcache
+
+test "x$prefix" = xNONE && prefix=$ac_default_prefix
+# Let make expand exec_prefix.
+test "x$exec_prefix" = xNONE && exec_prefix='${prefix}'
+
+# Transform confdefs.h into DEFS.
+# Protect against shell expansion while executing Makefile rules.
+# Protect against Makefile macro expansion.
+#
+# If the first sed substitution is executed (which looks for macros that
+# take arguments), then branch to the quote section.  Otherwise,
+# look for a macro that doesn't take arguments.
+ac_script='
+:mline
+/\\$/{
+ N
+ s,\\\n,,
+ b mline
+}
+t clear
+:clear
+s/^[	 ]*#[	 ]*define[	 ][	 ]*\([^	 (][^	 (]*([^)]*)\)[	 ]*\(.*\)/-D\1=\2/g
+t quote
+s/^[	 ]*#[	 ]*define[	 ][	 ]*\([^	 ][^	 ]*\)[	 ]*\(.*\)/-D\1=\2/g
+t quote
+b any
+:quote
+s/[	 `~#$^&*(){}\\|;'\''"<>?]/\\&/g
+s/\[/\\&/g
+s/\]/\\&/g
+s/\$/$$/g
+H
+:any
+${
+	g
+	s/^\n//
+	s/\n/ /g
+	p
+}
+'
+DEFS=`sed -n "$ac_script" confdefs.h`
+
+
+ac_libobjs=
+ac_ltlibobjs=
+U=
+for ac_i in : $LIBOBJS; do test "x$ac_i" = x: && continue
+  # 1. Remove the extension, and $U if already installed.
+  ac_script='s/\$U\././;s/\.o$//;s/\.obj$//'
+  ac_i=`$as_echo "$ac_i" | sed "$ac_script"`
+  # 2. Prepend LIBOBJDIR.  When used with automake>=1.10 LIBOBJDIR
+  #    will be set to the directory where LIBOBJS objects are built.
+  as_fn_append ac_libobjs " \${LIBOBJDIR}$ac_i\$U.$ac_objext"
+  as_fn_append ac_ltlibobjs " \${LIBOBJDIR}$ac_i"'$U.lo'
+done
+LIBOBJS=$ac_libobjs
+
+LTLIBOBJS=$ac_ltlibobjs
+
+
+
+: "${CONFIG_STATUS=./config.status}"
+ac_write_fail=0
+ac_clean_files_save=$ac_clean_files
+ac_clean_files="$ac_clean_files $CONFIG_STATUS"
+{ $as_echo "$as_me:${as_lineno-$LINENO}: creating $CONFIG_STATUS" >&5
+$as_echo "$as_me: creating $CONFIG_STATUS" >&6;}
+as_write_fail=0
+cat >$CONFIG_STATUS <<_ASEOF || as_write_fail=1
+#! $SHELL
+# Generated by $as_me.
+# Run this file to recreate the current configuration.
+# Compiler output produced by configure, useful for debugging
+# configure, is in config.log if it exists.
+
+debug=false
+ac_cs_recheck=false
+ac_cs_silent=false
+
+SHELL=\${CONFIG_SHELL-$SHELL}
+export SHELL
+_ASEOF
+cat >>$CONFIG_STATUS <<\_ASEOF || as_write_fail=1
+## -------------------- ##
+## M4sh Initialization. ##
+## -------------------- ##
+
+# Be more Bourne compatible
+DUALCASE=1; export DUALCASE # for MKS sh
+if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then :
+  emulate sh
+  NULLCMD=:
+  # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which
+  # is contrary to our usage.  Disable this feature.
+  alias -g '${1+"$@"}'='"$@"'
+  setopt NO_GLOB_SUBST
+else
+  case `(set -o) 2>/dev/null` in #(
+  *posix*) :
+    set -o posix ;; #(
+  *) :
+     ;;
+esac
+fi
+
+
+as_nl='
+'
+export as_nl
+# Printing a long string crashes Solaris 7 /usr/bin/printf.
+as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\'
+as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo
+as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo
+# Prefer a ksh shell builtin over an external printf program on Solaris,
+# but without wasting forks for bash or zsh.
+if test -z "$BASH_VERSION$ZSH_VERSION" \
+    && (test "X`print -r -- $as_echo`" = "X$as_echo") 2>/dev/null; then
+  as_echo='print -r --'
+  as_echo_n='print -rn --'
+elif (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then
+  as_echo='printf %s\n'
+  as_echo_n='printf %s'
+else
+  if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then
+    as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"'
+    as_echo_n='/usr/ucb/echo -n'
+  else
+    as_echo_body='eval expr "X$1" : "X\\(.*\\)"'
+    as_echo_n_body='eval
+      arg=$1;
+      case $arg in #(
+      *"$as_nl"*)
+	expr "X$arg" : "X\\(.*\\)$as_nl";
+	arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;;
+      esac;
+      expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl"
+    '
+    export as_echo_n_body
+    as_echo_n='sh -c $as_echo_n_body as_echo'
+  fi
+  export as_echo_body
+  as_echo='sh -c $as_echo_body as_echo'
+fi
+
+# The user is always right.
+if test "${PATH_SEPARATOR+set}" != set; then
+  PATH_SEPARATOR=:
+  (PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && {
+    (PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 ||
+      PATH_SEPARATOR=';'
+  }
+fi
+
+
+# IFS
+# We need space, tab and new line, in precisely that order.  Quoting is
+# there to prevent editors from complaining about space-tab.
+# (If _AS_PATH_WALK were called with IFS unset, it would disable word
+# splitting by setting IFS to empty value.)
+IFS=" ""	$as_nl"
+
+# Find who we are.  Look in the path if we contain no directory separator.
+as_myself=
+case $0 in #((
+  *[\\/]* ) as_myself=$0 ;;
+  *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+  IFS=$as_save_IFS
+  test -z "$as_dir" && as_dir=.
+    test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break
+  done
+IFS=$as_save_IFS
+
+     ;;
+esac
+# We did not find ourselves, most probably we were run as `sh COMMAND'
+# in which case we are not to be found in the path.
+if test "x$as_myself" = x; then
+  as_myself=$0
+fi
+if test ! -f "$as_myself"; then
+  $as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2
+  exit 1
+fi
+
+# Unset variables that we do not need and which cause bugs (e.g. in
+# pre-3.0 UWIN ksh).  But do not cause bugs in bash 2.01; the "|| exit 1"
+# suppresses any "Segmentation fault" message there.  '((' could
+# trigger a bug in pdksh 5.2.14.
+for as_var in BASH_ENV ENV MAIL MAILPATH
+do eval test x\${$as_var+set} = xset \
+  && ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || :
+done
+PS1='$ '
+PS2='> '
+PS4='+ '
+
+# NLS nuisances.
+LC_ALL=C
+export LC_ALL
+LANGUAGE=C
+export LANGUAGE
+
+# CDPATH.
+(unset CDPATH) >/dev/null 2>&1 && unset CDPATH
+
+
+# as_fn_error STATUS ERROR [LINENO LOG_FD]
+# ----------------------------------------
+# Output "`basename $0`: error: ERROR" to stderr. If LINENO and LOG_FD are
+# provided, also output the error to LOG_FD, referencing LINENO. Then exit the
+# script with STATUS, using 1 if that was 0.
+as_fn_error ()
+{
+  as_status=$1; test $as_status -eq 0 && as_status=1
+  if test "$4"; then
+    as_lineno=${as_lineno-"$3"} as_lineno_stack=as_lineno_stack=$as_lineno_stack
+    $as_echo "$as_me:${as_lineno-$LINENO}: error: $2" >&$4
+  fi
+  $as_echo "$as_me: error: $2" >&2
+  as_fn_exit $as_status
+} # as_fn_error
+
+
+# as_fn_set_status STATUS
+# -----------------------
+# Set $? to STATUS, without forking.
+as_fn_set_status ()
+{
+  return $1
+} # as_fn_set_status
+
+# as_fn_exit STATUS
+# -----------------
+# Exit the shell with STATUS, even in a "trap 0" or "set -e" context.
+as_fn_exit ()
+{
+  set +e
+  as_fn_set_status $1
+  exit $1
+} # as_fn_exit
+
+# as_fn_unset VAR
+# ---------------
+# Portably unset VAR.
+as_fn_unset ()
+{
+  { eval $1=; unset $1;}
+}
+as_unset=as_fn_unset
+# as_fn_append VAR VALUE
+# ----------------------
+# Append the text in VALUE to the end of the definition contained in VAR. Take
+# advantage of any shell optimizations that allow amortized linear growth over
+# repeated appends, instead of the typical quadratic growth present in naive
+# implementations.
+if (eval "as_var=1; as_var+=2; test x\$as_var = x12") 2>/dev/null; then :
+  eval 'as_fn_append ()
+  {
+    eval $1+=\$2
+  }'
+else
+  as_fn_append ()
+  {
+    eval $1=\$$1\$2
+  }
+fi # as_fn_append
+
+# as_fn_arith ARG...
+# ------------------
+# Perform arithmetic evaluation on the ARGs, and store the result in the
+# global $as_val. Take advantage of shells that can avoid forks. The arguments
+# must be portable across $(()) and expr.
+if (eval "test \$(( 1 + 1 )) = 2") 2>/dev/null; then :
+  eval 'as_fn_arith ()
+  {
+    as_val=$(( $* ))
+  }'
+else
+  as_fn_arith ()
+  {
+    as_val=`expr "$@" || test $? -eq 1`
+  }
+fi # as_fn_arith
+
+
+if expr a : '\(a\)' >/dev/null 2>&1 &&
+   test "X`expr 00001 : '.*\(...\)'`" = X001; then
+  as_expr=expr
+else
+  as_expr=false
+fi
+
+if (basename -- /) >/dev/null 2>&1 && test "X`basename -- / 2>&1`" = "X/"; then
+  as_basename=basename
+else
+  as_basename=false
+fi
+
+if (as_dir=`dirname -- /` && test "X$as_dir" = X/) >/dev/null 2>&1; then
+  as_dirname=dirname
+else
+  as_dirname=false
+fi
+
+as_me=`$as_basename -- "$0" ||
+$as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \
+	 X"$0" : 'X\(//\)$' \| \
+	 X"$0" : 'X\(/\)' \| . 2>/dev/null ||
+$as_echo X/"$0" |
+    sed '/^.*\/\([^/][^/]*\)\/*$/{
+	    s//\1/
+	    q
+	  }
+	  /^X\/\(\/\/\)$/{
+	    s//\1/
+	    q
+	  }
+	  /^X\/\(\/\).*/{
+	    s//\1/
+	    q
+	  }
+	  s/.*/./; q'`
+
+# Avoid depending upon Character Ranges.
+as_cr_letters='abcdefghijklmnopqrstuvwxyz'
+as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ'
+as_cr_Letters=$as_cr_letters$as_cr_LETTERS
+as_cr_digits='0123456789'
+as_cr_alnum=$as_cr_Letters$as_cr_digits
+
+ECHO_C= ECHO_N= ECHO_T=
+case `echo -n x` in #(((((
+-n*)
+  case `echo 'xy\c'` in
+  *c*) ECHO_T='	';;	# ECHO_T is single tab character.
+  xy)  ECHO_C='\c';;
+  *)   echo `echo ksh88 bug on AIX 6.1` > /dev/null
+       ECHO_T='	';;
+  esac;;
+*)
+  ECHO_N='-n';;
+esac
+
+rm -f conf$$ conf$$.exe conf$$.file
+if test -d conf$$.dir; then
+  rm -f conf$$.dir/conf$$.file
+else
+  rm -f conf$$.dir
+  mkdir conf$$.dir 2>/dev/null
+fi
+if (echo >conf$$.file) 2>/dev/null; then
+  if ln -s conf$$.file conf$$ 2>/dev/null; then
+    as_ln_s='ln -s'
+    # ... but there are two gotchas:
+    # 1) On MSYS, both `ln -s file dir' and `ln file dir' fail.
+    # 2) DJGPP < 2.04 has no symlinks; `ln -s' creates a wrapper executable.
+    # In both cases, we have to default to `cp -pR'.
+    ln -s conf$$.file conf$$.dir 2>/dev/null && test ! -f conf$$.exe ||
+      as_ln_s='cp -pR'
+  elif ln conf$$.file conf$$ 2>/dev/null; then
+    as_ln_s=ln
+  else
+    as_ln_s='cp -pR'
+  fi
+else
+  as_ln_s='cp -pR'
+fi
+rm -f conf$$ conf$$.exe conf$$.dir/conf$$.file conf$$.file
+rmdir conf$$.dir 2>/dev/null
+
+
+# as_fn_mkdir_p
+# -------------
+# Create "$as_dir" as a directory, including parents if necessary.
+as_fn_mkdir_p ()
+{
+
+  case $as_dir in #(
+  -*) as_dir=./$as_dir;;
+  esac
+  test -d "$as_dir" || eval $as_mkdir_p || {
+    as_dirs=
+    while :; do
+      case $as_dir in #(
+      *\'*) as_qdir=`$as_echo "$as_dir" | sed "s/'/'\\\\\\\\''/g"`;; #'(
+      *) as_qdir=$as_dir;;
+      esac
+      as_dirs="'$as_qdir' $as_dirs"
+      as_dir=`$as_dirname -- "$as_dir" ||
+$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
+	 X"$as_dir" : 'X\(//\)[^/]' \| \
+	 X"$as_dir" : 'X\(//\)$' \| \
+	 X"$as_dir" : 'X\(/\)' \| . 2>/dev/null ||
+$as_echo X"$as_dir" |
+    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{
+	    s//\1/
+	    q
+	  }
+	  /^X\(\/\/\)[^/].*/{
+	    s//\1/
+	    q
+	  }
+	  /^X\(\/\/\)$/{
+	    s//\1/
+	    q
+	  }
+	  /^X\(\/\).*/{
+	    s//\1/
+	    q
+	  }
+	  s/.*/./; q'`
+      test -d "$as_dir" && break
+    done
+    test -z "$as_dirs" || eval "mkdir $as_dirs"
+  } || test -d "$as_dir" || as_fn_error $? "cannot create directory $as_dir"
+
+
+} # as_fn_mkdir_p
+if mkdir -p . 2>/dev/null; then
+  as_mkdir_p='mkdir -p "$as_dir"'
+else
+  test -d ./-p && rmdir ./-p
+  as_mkdir_p=false
+fi
+
+
+# as_fn_executable_p FILE
+# -----------------------
+# Test if FILE is an executable regular file.
+as_fn_executable_p ()
+{
+  test -f "$1" && test -x "$1"
+} # as_fn_executable_p
+as_test_x='test -x'
+as_executable_p=as_fn_executable_p
+
+# Sed expression to map a string onto a valid CPP name.
+as_tr_cpp="eval sed 'y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g'"
+
+# Sed expression to map a string onto a valid variable name.
+as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'"
+
+
+exec 6>&1
+## ----------------------------------- ##
+## Main body of $CONFIG_STATUS script. ##
+## ----------------------------------- ##
+_ASEOF
+test $as_write_fail = 0 && chmod +x $CONFIG_STATUS || ac_write_fail=1
+
+cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
+# Save the log message, to keep $0 and so on meaningful, and to
+# report actual input values of CONFIG_FILES etc. instead of their
+# values after options handling.
+ac_log="
+This file was extended by riscv-tests $as_me 1.0, which was
+generated by GNU Autoconf 2.69.  Invocation command line was
+
+  CONFIG_FILES    = $CONFIG_FILES
+  CONFIG_HEADERS  = $CONFIG_HEADERS
+  CONFIG_LINKS    = $CONFIG_LINKS
+  CONFIG_COMMANDS = $CONFIG_COMMANDS
+  $ $0 $@
+
+on `(hostname || uname -n) 2>/dev/null | sed 1q`
+"
+
+_ACEOF
+
+case $ac_config_files in *"
+"*) set x $ac_config_files; shift; ac_config_files=$*;;
+esac
+
+
+
+cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+# Files that config.status was made for.
+config_files="$ac_config_files"
+
+_ACEOF
+
+cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
+ac_cs_usage="\
+\`$as_me' instantiates files and other configuration actions
+from templates according to the current configuration.  Unless the files
+and actions are specified as TAGs, all are instantiated by default.
+
+Usage: $0 [OPTION]... [TAG]...
+
+  -h, --help       print this help, then exit
+  -V, --version    print version number and configuration settings, then exit
+      --config     print configuration, then exit
+  -q, --quiet, --silent
+                   do not print progress messages
+  -d, --debug      don't remove temporary files
+      --recheck    update $as_me by reconfiguring in the same conditions
+      --file=FILE[:TEMPLATE]
+                   instantiate the configuration file FILE
+
+Configuration files:
+$config_files
+
+Report bugs to the package provider."
+
+_ACEOF
+cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+ac_cs_config="`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`"
+ac_cs_version="\\
+riscv-tests config.status 1.0
+configured by $0, generated by GNU Autoconf 2.69,
+  with options \\"\$ac_cs_config\\"
+
+Copyright (C) 2012 Free Software Foundation, Inc.
+This config.status script is free software; the Free Software Foundation
+gives unlimited permission to copy, distribute and modify it."
+
+ac_pwd='$ac_pwd'
+srcdir='$srcdir'
+test -n "\$AWK" || AWK=awk
+_ACEOF
+
+cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
+# The default lists apply if the user does not specify any file.
+ac_need_defaults=:
+while test $# != 0
+do
+  case $1 in
+  --*=?*)
+    ac_option=`expr "X$1" : 'X\([^=]*\)='`
+    ac_optarg=`expr "X$1" : 'X[^=]*=\(.*\)'`
+    ac_shift=:
+    ;;
+  --*=)
+    ac_option=`expr "X$1" : 'X\([^=]*\)='`
+    ac_optarg=
+    ac_shift=:
+    ;;
+  *)
+    ac_option=$1
+    ac_optarg=$2
+    ac_shift=shift
+    ;;
+  esac
+
+  case $ac_option in
+  # Handling of the options.
+  -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r)
+    ac_cs_recheck=: ;;
+  --version | --versio | --versi | --vers | --ver | --ve | --v | -V )
+    $as_echo "$ac_cs_version"; exit ;;
+  --config | --confi | --conf | --con | --co | --c )
+    $as_echo "$ac_cs_config"; exit ;;
+  --debug | --debu | --deb | --de | --d | -d )
+    debug=: ;;
+  --file | --fil | --fi | --f )
+    $ac_shift
+    case $ac_optarg in
+    *\'*) ac_optarg=`$as_echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"` ;;
+    '') as_fn_error $? "missing file argument" ;;
+    esac
+    as_fn_append CONFIG_FILES " '$ac_optarg'"
+    ac_need_defaults=false;;
+  --he | --h |  --help | --hel | -h )
+    $as_echo "$ac_cs_usage"; exit ;;
+  -q | -quiet | --quiet | --quie | --qui | --qu | --q \
+  | -silent | --silent | --silen | --sile | --sil | --si | --s)
+    ac_cs_silent=: ;;
+
+  # This is an error.
+  -*) as_fn_error $? "unrecognized option: \`$1'
+Try \`$0 --help' for more information." ;;
+
+  *) as_fn_append ac_config_targets " $1"
+     ac_need_defaults=false ;;
+
+  esac
+  shift
+done
+
+ac_configure_extra_args=
+
+if $ac_cs_silent; then
+  exec 6>/dev/null
+  ac_configure_extra_args="$ac_configure_extra_args --silent"
+fi
+
+_ACEOF
+cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+if \$ac_cs_recheck; then
+  set X $SHELL '$0' $ac_configure_args \$ac_configure_extra_args --no-create --no-recursion
+  shift
+  \$as_echo "running CONFIG_SHELL=$SHELL \$*" >&6
+  CONFIG_SHELL='$SHELL'
+  export CONFIG_SHELL
+  exec "\$@"
+fi
+
+_ACEOF
+cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
+exec 5>>config.log
+{
+  echo
+  sed 'h;s/./-/g;s/^.../## /;s/...$/ ##/;p;x;p;x' <<_ASBOX
+## Running $as_me. ##
+_ASBOX
+  $as_echo "$ac_log"
+} >&5
+
+_ACEOF
+cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+_ACEOF
+
+cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
+
+# Handling of arguments.
+for ac_config_target in $ac_config_targets
+do
+  case $ac_config_target in
+    "Makefile") CONFIG_FILES="$CONFIG_FILES Makefile" ;;
+
+  *) as_fn_error $? "invalid argument: \`$ac_config_target'" "$LINENO" 5;;
+  esac
+done
+
+
+# If the user did not use the arguments to specify the items to instantiate,
+# then the envvar interface is used.  Set only those that are not.
+# We use the long form for the default assignment because of an extremely
+# bizarre bug on SunOS 4.1.3.
+if $ac_need_defaults; then
+  test "${CONFIG_FILES+set}" = set || CONFIG_FILES=$config_files
+fi
+
+# Have a temporary directory for convenience.  Make it in the build tree
+# simply because there is no reason against having it here, and in addition,
+# creating and moving files from /tmp can sometimes cause problems.
+# Hook for its removal unless debugging.
+# Note that there is a small window in which the directory will not be cleaned:
+# after its creation but before its name has been assigned to `$tmp'.
+$debug ||
+{
+  tmp= ac_tmp=
+  trap 'exit_status=$?
+  : "${ac_tmp:=$tmp}"
+  { test ! -d "$ac_tmp" || rm -fr "$ac_tmp"; } && exit $exit_status
+' 0
+  trap 'as_fn_exit 1' 1 2 13 15
+}
+# Create a (secure) tmp directory for tmp files.
+
+{
+  tmp=`(umask 077 && mktemp -d "./confXXXXXX") 2>/dev/null` &&
+  test -d "$tmp"
+}  ||
+{
+  tmp=./conf$$-$RANDOM
+  (umask 077 && mkdir "$tmp")
+} || as_fn_error $? "cannot create a temporary directory in ." "$LINENO" 5
+ac_tmp=$tmp
+
+# Set up the scripts for CONFIG_FILES section.
+# No need to generate them if there are no CONFIG_FILES.
+# This happens for instance with `./config.status config.h'.
+if test -n "$CONFIG_FILES"; then
+
+
+ac_cr=`echo X | tr X '\015'`
+# On cygwin, bash can eat \r inside `` if the user requested igncr.
+# But we know of no other shell where ac_cr would be empty at this
+# point, so we can use a bashism as a fallback.
+if test "x$ac_cr" = x; then
+  eval ac_cr=\$\'\\r\'
+fi
+ac_cs_awk_cr=`$AWK 'BEGIN { print "a\rb" }' </dev/null 2>/dev/null`
+if test "$ac_cs_awk_cr" = "a${ac_cr}b"; then
+  ac_cs_awk_cr='\\r'
+else
+  ac_cs_awk_cr=$ac_cr
+fi
+
+echo 'BEGIN {' >"$ac_tmp/subs1.awk" &&
+_ACEOF
+
+
+{
+  echo "cat >conf$$subs.awk <<_ACEOF" &&
+  echo "$ac_subst_vars" | sed 's/.*/&!$&$ac_delim/' &&
+  echo "_ACEOF"
+} >conf$$subs.sh ||
+  as_fn_error $? "could not make $CONFIG_STATUS" "$LINENO" 5
+ac_delim_num=`echo "$ac_subst_vars" | grep -c '^'`
+ac_delim='%!_!# '
+for ac_last_try in false false false false false :; do
+  . ./conf$$subs.sh ||
+    as_fn_error $? "could not make $CONFIG_STATUS" "$LINENO" 5
+
+  ac_delim_n=`sed -n "s/.*$ac_delim\$/X/p" conf$$subs.awk | grep -c X`
+  if test $ac_delim_n = $ac_delim_num; then
+    break
+  elif $ac_last_try; then
+    as_fn_error $? "could not make $CONFIG_STATUS" "$LINENO" 5
+  else
+    ac_delim="$ac_delim!$ac_delim _$ac_delim!! "
+  fi
+done
+rm -f conf$$subs.sh
+
+cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+cat >>"\$ac_tmp/subs1.awk" <<\\_ACAWK &&
+_ACEOF
+sed -n '
+h
+s/^/S["/; s/!.*/"]=/
+p
+g
+s/^[^!]*!//
+:repl
+t repl
+s/'"$ac_delim"'$//
+t delim
+:nl
+h
+s/\(.\{148\}\)..*/\1/
+t more1
+s/["\\]/\\&/g; s/^/"/; s/$/\\n"\\/
+p
+n
+b repl
+:more1
+s/["\\]/\\&/g; s/^/"/; s/$/"\\/
+p
+g
+s/.\{148\}//
+t nl
+:delim
+h
+s/\(.\{148\}\)..*/\1/
+t more2
+s/["\\]/\\&/g; s/^/"/; s/$/"/
+p
+b
+:more2
+s/["\\]/\\&/g; s/^/"/; s/$/"\\/
+p
+g
+s/.\{148\}//
+t delim
+' <conf$$subs.awk | sed '
+/^[^""]/{
+  N
+  s/\n//
+}
+' >>$CONFIG_STATUS || ac_write_fail=1
+rm -f conf$$subs.awk
+cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+_ACAWK
+cat >>"\$ac_tmp/subs1.awk" <<_ACAWK &&
+  for (key in S) S_is_set[key] = 1
+  FS = ""
+
+}
+{
+  line = $ 0
+  nfields = split(line, field, "@")
+  substed = 0
+  len = length(field[1])
+  for (i = 2; i < nfields; i++) {
+    key = field[i]
+    keylen = length(key)
+    if (S_is_set[key]) {
+      value = S[key]
+      line = substr(line, 1, len) "" value "" substr(line, len + keylen + 3)
+      len += length(value) + length(field[++i])
+      substed = 1
+    } else
+      len += 1 + keylen
+  }
+
+  print line
+}
+
+_ACAWK
+_ACEOF
+cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
+if sed "s/$ac_cr//" < /dev/null > /dev/null 2>&1; then
+  sed "s/$ac_cr\$//; s/$ac_cr/$ac_cs_awk_cr/g"
+else
+  cat
+fi < "$ac_tmp/subs1.awk" > "$ac_tmp/subs.awk" \
+  || as_fn_error $? "could not setup config files machinery" "$LINENO" 5
+_ACEOF
+
+# VPATH may cause trouble with some makes, so we remove sole $(srcdir),
+# ${srcdir} and @srcdir@ entries from VPATH if srcdir is ".", strip leading and
+# trailing colons and then remove the whole line if VPATH becomes empty
+# (actually we leave an empty line to preserve line numbers).
+if test "x$srcdir" = x.; then
+  ac_vpsub='/^[	 ]*VPATH[	 ]*=[	 ]*/{
+h
+s///
+s/^/:/
+s/[	 ]*$/:/
+s/:\$(srcdir):/:/g
+s/:\${srcdir}:/:/g
+s/:@srcdir@:/:/g
+s/^:*//
+s/:*$//
+x
+s/\(=[	 ]*\).*/\1/
+G
+s/\n//
+s/^[^=]*=[	 ]*$//
+}'
+fi
+
+cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
+fi # test -n "$CONFIG_FILES"
+
+
+eval set X "  :F $CONFIG_FILES      "
+shift
+for ac_tag
+do
+  case $ac_tag in
+  :[FHLC]) ac_mode=$ac_tag; continue;;
+  esac
+  case $ac_mode$ac_tag in
+  :[FHL]*:*);;
+  :L* | :C*:*) as_fn_error $? "invalid tag \`$ac_tag'" "$LINENO" 5;;
+  :[FH]-) ac_tag=-:-;;
+  :[FH]*) ac_tag=$ac_tag:$ac_tag.in;;
+  esac
+  ac_save_IFS=$IFS
+  IFS=:
+  set x $ac_tag
+  IFS=$ac_save_IFS
+  shift
+  ac_file=$1
+  shift
+
+  case $ac_mode in
+  :L) ac_source=$1;;
+  :[FH])
+    ac_file_inputs=
+    for ac_f
+    do
+      case $ac_f in
+      -) ac_f="$ac_tmp/stdin";;
+      *) # Look for the file first in the build tree, then in the source tree
+	 # (if the path is not absolute).  The absolute path cannot be DOS-style,
+	 # because $ac_f cannot contain `:'.
+	 test -f "$ac_f" ||
+	   case $ac_f in
+	   [\\/$]*) false;;
+	   *) test -f "$srcdir/$ac_f" && ac_f="$srcdir/$ac_f";;
+	   esac ||
+	   as_fn_error 1 "cannot find input file: \`$ac_f'" "$LINENO" 5;;
+      esac
+      case $ac_f in *\'*) ac_f=`$as_echo "$ac_f" | sed "s/'/'\\\\\\\\''/g"`;; esac
+      as_fn_append ac_file_inputs " '$ac_f'"
+    done
+
+    # Let's still pretend it is `configure' which instantiates (i.e., don't
+    # use $as_me), people would be surprised to read:
+    #    /* config.h.  Generated by config.status.  */
+    configure_input='Generated from '`
+	  $as_echo "$*" | sed 's|^[^:]*/||;s|:[^:]*/|, |g'
+	`' by configure.'
+    if test x"$ac_file" != x-; then
+      configure_input="$ac_file.  $configure_input"
+      { $as_echo "$as_me:${as_lineno-$LINENO}: creating $ac_file" >&5
+$as_echo "$as_me: creating $ac_file" >&6;}
+    fi
+    # Neutralize special characters interpreted by sed in replacement strings.
+    case $configure_input in #(
+    *\&* | *\|* | *\\* )
+       ac_sed_conf_input=`$as_echo "$configure_input" |
+       sed 's/[\\\\&|]/\\\\&/g'`;; #(
+    *) ac_sed_conf_input=$configure_input;;
+    esac
+
+    case $ac_tag in
+    *:-:* | *:-) cat >"$ac_tmp/stdin" \
+      || as_fn_error $? "could not create $ac_file" "$LINENO" 5 ;;
+    esac
+    ;;
+  esac
+
+  ac_dir=`$as_dirname -- "$ac_file" ||
+$as_expr X"$ac_file" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
+	 X"$ac_file" : 'X\(//\)[^/]' \| \
+	 X"$ac_file" : 'X\(//\)$' \| \
+	 X"$ac_file" : 'X\(/\)' \| . 2>/dev/null ||
+$as_echo X"$ac_file" |
+    sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{
+	    s//\1/
+	    q
+	  }
+	  /^X\(\/\/\)[^/].*/{
+	    s//\1/
+	    q
+	  }
+	  /^X\(\/\/\)$/{
+	    s//\1/
+	    q
+	  }
+	  /^X\(\/\).*/{
+	    s//\1/
+	    q
+	  }
+	  s/.*/./; q'`
+  as_dir="$ac_dir"; as_fn_mkdir_p
+  ac_builddir=.
+
+case "$ac_dir" in
+.) ac_dir_suffix= ac_top_builddir_sub=. ac_top_build_prefix= ;;
+*)
+  ac_dir_suffix=/`$as_echo "$ac_dir" | sed 's|^\.[\\/]||'`
+  # A ".." for each directory in $ac_dir_suffix.
+  ac_top_builddir_sub=`$as_echo "$ac_dir_suffix" | sed 's|/[^\\/]*|/..|g;s|/||'`
+  case $ac_top_builddir_sub in
+  "") ac_top_builddir_sub=. ac_top_build_prefix= ;;
+  *)  ac_top_build_prefix=$ac_top_builddir_sub/ ;;
+  esac ;;
+esac
+ac_abs_top_builddir=$ac_pwd
+ac_abs_builddir=$ac_pwd$ac_dir_suffix
+# for backward compatibility:
+ac_top_builddir=$ac_top_build_prefix
+
+case $srcdir in
+  .)  # We are building in place.
+    ac_srcdir=.
+    ac_top_srcdir=$ac_top_builddir_sub
+    ac_abs_top_srcdir=$ac_pwd ;;
+  [\\/]* | ?:[\\/]* )  # Absolute name.
+    ac_srcdir=$srcdir$ac_dir_suffix;
+    ac_top_srcdir=$srcdir
+    ac_abs_top_srcdir=$srcdir ;;
+  *) # Relative name.
+    ac_srcdir=$ac_top_build_prefix$srcdir$ac_dir_suffix
+    ac_top_srcdir=$ac_top_build_prefix$srcdir
+    ac_abs_top_srcdir=$ac_pwd/$srcdir ;;
+esac
+ac_abs_srcdir=$ac_abs_top_srcdir$ac_dir_suffix
+
+
+  case $ac_mode in
+  :F)
+  #
+  # CONFIG_FILE
+  #
+
+_ACEOF
+
+cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
+# If the template does not know about datarootdir, expand it.
+# FIXME: This hack should be removed a few years after 2.60.
+ac_datarootdir_hack=; ac_datarootdir_seen=
+ac_sed_dataroot='
+/datarootdir/ {
+  p
+  q
+}
+/@datadir@/p
+/@docdir@/p
+/@infodir@/p
+/@localedir@/p
+/@mandir@/p'
+case `eval "sed -n \"\$ac_sed_dataroot\" $ac_file_inputs"` in
+*datarootdir*) ac_datarootdir_seen=yes;;
+*@datadir@*|*@docdir@*|*@infodir@*|*@localedir@*|*@mandir@*)
+  { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $ac_file_inputs seems to ignore the --datarootdir setting" >&5
+$as_echo "$as_me: WARNING: $ac_file_inputs seems to ignore the --datarootdir setting" >&2;}
+_ACEOF
+cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+  ac_datarootdir_hack='
+  s&@datadir@&$datadir&g
+  s&@docdir@&$docdir&g
+  s&@infodir@&$infodir&g
+  s&@localedir@&$localedir&g
+  s&@mandir@&$mandir&g
+  s&\\\${datarootdir}&$datarootdir&g' ;;
+esac
+_ACEOF
+
+# Neutralize VPATH when `$srcdir' = `.'.
+# Shell code in configure.ac might set extrasub.
+# FIXME: do we really want to maintain this feature?
+cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1
+ac_sed_extra="$ac_vpsub
+$extrasub
+_ACEOF
+cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1
+:t
+/@[a-zA-Z_][a-zA-Z_0-9]*@/!b
+s|@configure_input@|$ac_sed_conf_input|;t t
+s&@top_builddir@&$ac_top_builddir_sub&;t t
+s&@top_build_prefix@&$ac_top_build_prefix&;t t
+s&@srcdir@&$ac_srcdir&;t t
+s&@abs_srcdir@&$ac_abs_srcdir&;t t
+s&@top_srcdir@&$ac_top_srcdir&;t t
+s&@abs_top_srcdir@&$ac_abs_top_srcdir&;t t
+s&@builddir@&$ac_builddir&;t t
+s&@abs_builddir@&$ac_abs_builddir&;t t
+s&@abs_top_builddir@&$ac_abs_top_builddir&;t t
+$ac_datarootdir_hack
+"
+eval sed \"\$ac_sed_extra\" "$ac_file_inputs" | $AWK -f "$ac_tmp/subs.awk" \
+  >$ac_tmp/out || as_fn_error $? "could not create $ac_file" "$LINENO" 5
+
+test -z "$ac_datarootdir_hack$ac_datarootdir_seen" &&
+  { ac_out=`sed -n '/\${datarootdir}/p' "$ac_tmp/out"`; test -n "$ac_out"; } &&
+  { ac_out=`sed -n '/^[	 ]*datarootdir[	 ]*:*=/p' \
+      "$ac_tmp/out"`; test -z "$ac_out"; } &&
+  { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $ac_file contains a reference to the variable \`datarootdir'
+which seems to be undefined.  Please make sure it is defined" >&5
+$as_echo "$as_me: WARNING: $ac_file contains a reference to the variable \`datarootdir'
+which seems to be undefined.  Please make sure it is defined" >&2;}
+
+  rm -f "$ac_tmp/stdin"
+  case $ac_file in
+  -) cat "$ac_tmp/out" && rm -f "$ac_tmp/out";;
+  *) rm -f "$ac_file" && mv "$ac_tmp/out" "$ac_file";;
+  esac \
+  || as_fn_error $? "could not create $ac_file" "$LINENO" 5
+ ;;
+
+
+
+  esac
+
+done # for ac_tag
+
+
+as_fn_exit 0
+_ACEOF
+ac_clean_files=$ac_clean_files_save
+
+test $ac_write_fail = 0 ||
+  as_fn_error $? "write failure creating $CONFIG_STATUS" "$LINENO" 5
+
+
+# configure is writing to config.log, and then calls config.status.
+# config.status does its own redirection, appending to config.log.
+# Unfortunately, on DOS this fails, as config.log is still kept open
+# by configure, so config.status won't be able to write to it; its
+# output is simply discarded.  So we exec the FD to /dev/null,
+# effectively closing config.log, so it can be properly (re)opened and
+# appended to by config.status.  When coming back to configure, we
+# need to make the FD available again.
+if test "$no_create" != yes; then
+  ac_cs_success=:
+  ac_config_status_args=
+  test "$silent" = yes &&
+    ac_config_status_args="$ac_config_status_args --quiet"
+  exec 5>/dev/null
+  $SHELL $CONFIG_STATUS $ac_config_status_args || ac_cs_success=false
+  exec 5>>config.log
+  # Use ||, not &&, to avoid exiting from the if with $? = 1, which
+  # would make configure fail if this is the last instruction.
+  $ac_cs_success || as_fn_exit 1
+fi
+if test -n "$ac_unrecognized_opts" && test "$enable_option_checking" != no; then
+  { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: unrecognized options: $ac_unrecognized_opts" >&5
+$as_echo "$as_me: WARNING: unrecognized options: $ac_unrecognized_opts" >&2;}
+fi
+
diff --git a/apps/riscv-tests/configure.ac b/apps/riscv-tests/configure.ac
new file mode 100644
index 0000000..ebfd649
--- /dev/null
+++ b/apps/riscv-tests/configure.ac
@@ -0,0 +1,16 @@
+AC_INIT(riscv-tests, 1.0)
+
+cross_compiling=yes
+AC_PROG_CC
+
+AC_ARG_WITH(xlen,
+        [AS_HELP_STRING([--with-xlen=XLEN],
+                [Set XLEN, the X-register bit width (default is 64)])],
+        AC_SUBST(XLEN, $withval),
+        AC_SUBST(XLEN, 64)
+        )
+
+
+AC_OUTPUT(
+    Makefile
+)
diff --git a/apps/riscv-tests/debug/Makefile b/apps/riscv-tests/debug/Makefile
new file mode 100644
index 0000000..3efdea8
--- /dev/null
+++ b/apps/riscv-tests/debug/Makefile
@@ -0,0 +1,35 @@
+RISCV_SIM ?= spike
+XLEN ?= 64
+
+src_dir ?= .
+GDBSERVER_PY = $(src_dir)/gdbserver.py
+TESTS = $(shell $(GDBSERVER_PY) --list-tests $(src_dir)/targets/RISC-V/spike32.py)
+
+default: spike$(XLEN) spike$(XLEN)-2
+
+all-tests: spike32 spike32-2 spike32-2-rtos spike32-2-hwthread \
+	spike64 spike64-2 spike64-2-rtos spike64-2-hwthread
+
+all:	pylint all-tests
+
+run.%:
+	echo $@
+	$(GDBSERVER_PY) \
+		$(src_dir)/targets/RISC-V/$(word 2, $(subst ., ,$@)).py \
+		$(word 3, $(subst ., ,$@)) \
+		--isolate \
+		--print-failures \
+		--sim_cmd $(RISCV)/bin/$(RISCV_SIM) \
+		--server_cmd $(RISCV)/bin/openocd
+
+# Target to check all the multicore options.
+multi-tests: spike32-2 spike64-2-rtos spike32-2-hwthread
+
+pylint:
+	pylint --rcfile=pylint.rc `git ls-files '*.py'`
+
+spike%:	$(foreach test, $(TESTS), run.spike%.$(test))
+	echo Finished $@
+
+clean:
+	rm -f *.pyc
diff --git a/apps/riscv-tests/debug/README.md b/apps/riscv-tests/debug/README.md
new file mode 100644
index 0000000..7dd6790
--- /dev/null
+++ b/apps/riscv-tests/debug/README.md
@@ -0,0 +1,58 @@
+Debug Tests
+===========
+
+Debugging requires many system components to all work together. The tests here
+perform an end-to-end test, communicating with gdb and OpenOCD.
+If a simulator or hardware passes all these tests, then you can be pretty
+confident that the actual debug interface is functioning correctly.
+
+Requirements
+============
+The following should be in the user's path:
+* riscv64-unknown-elf-gcc (`rvv-0.9.x` branch for riscv-gnu-toolchain should
+  work if master does not have vector support yet)
+* riscv64-unknown-elf-gdb (can be overridden with `--gdb` when running
+  gdbserver.py manually), which should be the latest from
+  git://sourceware.org/git/binutils-gdb.git.
+* spike (can be overridden with `--sim_cmd` when running gdbserver.py
+  manually), which should be the latest from
+  https://github.com/riscv/riscv-isa-sim.git.
+* openocd (can be overridden with `--server_cmd` when running gdbserver.py
+  manually), which should be the latest from
+  https://github.com/riscv/riscv-openocd.git.
+
+Usage
+=====
+To run a quick smoke test against spike, run `make`. For a more comprehensive
+test against a variety of spike configurations, run `make all`.
+
+To run tests against hardware, or a specific spike configuration, manually
+invoke gdbserver.py: `./gdbserver.py targets/<file>.py`
+
+You can run just a single test by specifying any part of its name on the
+command line, eg: `./gdbserver.py targets/RISC-V/spike64.py S0` runs
+SimpleS0Test.  Once that test has failed, you can look at the log file to get
+an idea of what might have gone wrong.
+
+For custom targets, you can create a .py file anywhere and pass its path on the
+command line. The Targets class in `targets.py` contains documentation on what
+every variable means.
+
+Log Files
+=========
+
+All output from tests ends up in the `logs/` subdirectory, with one log file
+per test. If a test fails, this is where to look.
+
+Debug Tips
+==========
+
+You can see what spike is doing by adding `-l` to the spike command, eg.:
+`./gdbserver.py --sim_cmd "$RISCV/bin/spike -l" targets/RISC-V/spike32.py Breakpoint`
+
+You can see what OpenOCD is doing by adding `-d` to the OpenOCD command, eg.:
+`./gdbserver.py --server_cmd "openocd -d" targets/RISC-V/spike32.py Breakpoint`
+
+You can run gdb under valgrind by passing --gdb, eg.: `./gdbserver.py
+--gdb "valgrind riscv64-unknown-elf-gdb" targets/RISC-V/spike64.py
+DownloadTest`
diff --git a/apps/riscv-tests/debug/gdbserver.py b/apps/riscv-tests/debug/gdbserver.py
new file mode 100755
index 0000000..5a0c378
--- /dev/null
+++ b/apps/riscv-tests/debug/gdbserver.py
@@ -0,0 +1,1607 @@
+#!/usr/bin/env python3
+
+import argparse
+import binascii
+import random
+import struct
+import sys
+import tempfile
+import time
+import os
+
+import targets
+import testlib
+from testlib import assertEqual, assertNotEqual, assertIn, assertNotIn
+from testlib import assertGreater, assertRegex, assertLess
+from testlib import GdbTest, GdbSingleHartTest, TestFailed
+from testlib import assertTrue, TestNotApplicable, CompileError
+
+MSTATUS_UIE = 0x00000001
+MSTATUS_SIE = 0x00000002
+MSTATUS_HIE = 0x00000004
+MSTATUS_MIE = 0x00000008
+MSTATUS_UPIE = 0x00000010
+MSTATUS_SPIE = 0x00000020
+MSTATUS_HPIE = 0x00000040
+MSTATUS_MPIE = 0x00000080
+MSTATUS_SPP = 0x00000100
+MSTATUS_HPP = 0x00000600
+MSTATUS_MPP = 0x00001800
+MSTATUS_FS = 0x00006000
+MSTATUS_XS = 0x00018000
+MSTATUS_MPRV = 0x00020000
+MSTATUS_PUM = 0x00040000
+MSTATUS_MXR = 0x00080000
+MSTATUS_VM = 0x1F000000
+MSTATUS32_SD = 0x80000000
+MSTATUS64_SD = 0x8000000000000000
+
+# pylint: disable=abstract-method
+
+def ihex_line(address, record_type, data):
+    assert len(data) < 128
+    line = ":%02X%04X%02X" % (len(data), address, record_type)
+    check = len(data)
+    check += address % 256
+    check += address >> 8
+    check += record_type
+    for char in data:
+        value = ord(char)
+        check += value
+        line += "%02X" % value
+    line += "%02X\n" % ((256-check)%256)
+    return line
+
+def srec_parse(line):
+    assert line.startswith(b'S')
+    typ = line[:2]
+    count = int(line[2:4], 16)
+    data = ""
+    if typ == b'S0':
+        # header
+        return 0, 0, 0
+    elif typ == b'S3':
+        # data with 32-bit address
+        # Any higher bits were chopped off.
+        address = int(line[4:12], 16)
+        for i in range(6, count+1):
+            data += "%c" % int(line[2*i:2*i+2], 16)
+        # Ignore the checksum.
+        return 3, address, data
+    elif typ == b'S7':
+        # ignore execution start field
+        return 7, 0, 0
+    else:
+        raise TestFailed("Unsupported SREC type %r." % typ)
+
+def readable_binary_string(s):
+    return "".join("%02x" % ord(c) for c in s)
+
+class SimpleRegisterTest(GdbTest):
+    def check_reg(self, name, alias):
+        a = random.randrange(1<<self.hart.xlen)
+        b = random.randrange(1<<self.hart.xlen)
+        self.gdb.p("$%s=0x%x" % (name, a))
+        assertEqual(self.gdb.p("$%s" % alias), a)
+        self.gdb.stepi()
+        assertEqual(self.gdb.p("$%s" % name), a)
+        assertEqual(self.gdb.p("$%s" % alias), a)
+        self.gdb.p("$%s=0x%x" % (alias, b))
+        assertEqual(self.gdb.p("$%s" % name), b)
+        self.gdb.stepi()
+        assertEqual(self.gdb.p("$%s" % name), b)
+        assertEqual(self.gdb.p("$%s" % alias), b)
+
+    def setup(self):
+        self.write_nop_program(5)
+
+class SimpleS0Test(SimpleRegisterTest):
+    def test(self):
+        self.check_reg("s0", "x8")
+
+class SimpleS1Test(SimpleRegisterTest):
+    def test(self):
+        self.check_reg("s1", "x9")
+
+class SimpleT0Test(SimpleRegisterTest):
+    def test(self):
+        self.check_reg("t0", "x5")
+
+class SimpleT1Test(SimpleRegisterTest):
+    def test(self):
+        self.check_reg("t1", "x6")
+
+class SimpleV13Test(SimpleRegisterTest):
+    def test(self):
+        if self.hart.extensionSupported('V'):
+            vlenb = self.gdb.p("$vlenb")
+            # Can't write quadwords, because gdb won't parse a 128-bit hex
+            # value.
+            written = {}
+            for name, byte_count in (('b', 1), ('s', 2), ('w', 4), ('l', 8)):
+                written[name] = {}
+                for i in range(vlenb // byte_count):
+                    written[name][i] = random.randrange(256 ** byte_count)
+                    self.gdb.p("$v13.%s[%d]=0x%x" % (name, i, written[name][i]))
+                self.gdb.stepi()
+                self.gdb.p("$v13")
+                for i in range(vlenb // byte_count):
+                    assertEqual(self.gdb.p("$v13.%s[%d]" % (name, i)),
+                            written[name][i])
+        else:
+            output = self.gdb.p_raw("$v13")
+            assertRegex(output, r"void|Could not fetch register.*")
+
+class SimpleF18Test(SimpleRegisterTest):
+    def check_reg(self, name, alias):
+        if self.hart.extensionSupported('F'):
+            mstatus_fs = 0x00006000
+            self.gdb.p("$mstatus=$mstatus|0x%x" % mstatus_fs)
+            self.gdb.stepi()
+            a = random.random()
+            b = random.random()
+            self.gdb.p_fpr("$%s=%f" % (name, a))
+            assertLess(abs((self.gdb.p_fpr("$%s" % alias)) - a), .001)
+            self.gdb.stepi()
+            assertLess(abs((self.gdb.p_fpr("$%s" % name)) - a), .001)
+            assertLess(abs((self.gdb.p_fpr("$%s" % alias)) - a), .001)
+            self.gdb.p_fpr("$%s=%f" % (alias, b))
+            assertLess(abs((self.gdb.p_fpr("$%s" % name)) - b), .001)
+            self.gdb.stepi()
+            assertLess(abs((self.gdb.p_fpr("$%s" % name)) - b), .001)
+            assertLess(abs((self.gdb.p_fpr("$%s" % alias)) - b), .001)
+
+            size = self.gdb.p("sizeof($%s)" % name)
+            if self.hart.extensionSupported('D'):
+                assertEqual(size, 8)
+            else:
+                assertEqual(size, 4)
+        else:
+            output = self.gdb.p_raw("$" + name)
+            assertRegex(output, r"void|Could not fetch register.*")
+            output = self.gdb.p_raw("$" + alias)
+            assertRegex(output, r"void|Could not fetch register.*")
+
+    def test(self):
+        self.check_reg("f18", "fs2")
+
+class CustomRegisterTest(SimpleRegisterTest):
+    def early_applicable(self):
+        return self.target.implements_custom_test
+
+    def check_custom(self, magic):
+        regs = {k: v for k, v in self.gdb.info_registers("all").items()
+                if k.startswith("custom")}
+        assertEqual(set(regs.keys()),
+                set(("custom1",
+                    "custom12345",
+                    "custom12346",
+                    "custom12347",
+                    "custom12348")))
+        for name, value in regs.items():
+            number = int(name[6:])
+            if number % 2:
+                expect = number + magic
+                assertIn(value, (expect, expect + (1<<32)))
+            else:
+                assertIn("Could not fetch register", value)
+
+    def test(self):
+        self.check_custom(0)
+
+        # Now test writing
+        magic = 6667
+        self.gdb.p("$custom12345=%d" % (12345 + magic))
+        self.gdb.stepi()
+
+        self.check_custom(magic)
+
+class SimpleNoExistTest(GdbTest):
+    def test(self):
+        try:
+            self.gdb.p("$csr2288")
+            assert False, "Reading csr2288 should have failed"
+        except testlib.CouldNotFetch:
+            pass
+        try:
+            self.gdb.p("$csr2288=5")
+            assert False, "Writing csr2288 should have failed"
+        except testlib.CouldNotFetch:
+            pass
+
+class SimpleMemoryTest(GdbTest):
+    def access_test(self, size, data_type):
+        assertEqual(self.gdb.p("sizeof(%s)" % data_type), size)
+        a = 0x86753095555aaaa & ((1<<(size*8))-1)
+        b = 0xdeadbeef12345678 & ((1<<(size*8))-1)
+        addrA = self.hart.ram
+        addrB = self.hart.ram + self.hart.ram_size - size
+        self.gdb.p("*((%s*)0x%x) = 0x%x" % (data_type, addrA, a))
+        self.gdb.p("*((%s*)0x%x) = 0x%x" % (data_type, addrB, b))
+        assertEqual(self.gdb.p("*((%s*)0x%x)" % (data_type, addrA)), a)
+        assertEqual(self.gdb.p("*((%s*)0x%x)" % (data_type, addrB)), b)
+
+class MemTest8(SimpleMemoryTest):
+    def test(self):
+        self.access_test(1, 'char')
+
+class MemTest16(SimpleMemoryTest):
+    def test(self):
+        self.access_test(2, 'short')
+
+class MemTest32(SimpleMemoryTest):
+    def test(self):
+        self.access_test(4, 'int')
+
+class MemTest64(SimpleMemoryTest):
+    def test(self):
+        self.access_test(8, 'long long')
+
+# FIXME: I'm not passing back invalid addresses correctly in read/write memory.
+#class MemTestReadInvalid(SimpleMemoryTest):
+#    def test(self):
+#        # This test relies on 'gdb_report_data_abort enable' being executed in
+#        # the openocd.cfg file.
+#        try:
+#            self.gdb.p("*((int*)0xdeadbeef)")
+#            assert False, "Read should have failed."
+#        except testlib.CannotAccess as e:
+#            assertEqual(e.address, 0xdeadbeef)
+#        self.gdb.p("*((int*)0x%x)" % self.hart.ram)
+#
+#class MemTestWriteInvalid(SimpleMemoryTest):
+#    def test(self):
+#        # This test relies on 'gdb_report_data_abort enable' being executed in
+#        # the openocd.cfg file.
+#        try:
+#            self.gdb.p("*((int*)0xdeadbeef)=8675309")
+#            assert False, "Write should have failed."
+#        except testlib.CannotAccess as e:
+#            assertEqual(e.address, 0xdeadbeef)
+#        self.gdb.p("*((int*)0x%x)=6874742" % self.hart.ram)
+
+class MemTestBlockReadInvalid(GdbTest):
+    zero_values = "00 00 00 00 00 00 00 00"
+    real_values = "EF BE AD DE 78 56 34 12"
+
+    def early_applicable(self):
+        return self.target.invalid_memory_returns_zero
+
+    def test(self):
+        self.gdb.p("*((int*)0x%x) = 0xdeadbeef" % (self.hart.ram + 0))
+        self.gdb.p("*((int*)0x%x) = 0x12345678" % (self.hart.ram + 4))
+
+        # read before start of memory
+        self.memory_test(self.hart.ram - 8,
+                         self.hart.ram,
+                         self.zero_values)
+
+        # read across start of memory
+        self.memory_test(self.hart.ram - 8,
+                         self.hart.ram + 8,
+                         self.zero_values + " " + self.real_values)
+
+        # read after start of memory
+        self.memory_test(self.hart.ram,
+                         self.hart.ram + 8,
+                         self.real_values)
+
+        self.gdb.p("*((int*)0x%x) = 0xdeadbeef" %
+                (self.hart.ram + self.hart.ram_size - 8))
+        self.gdb.p("*((int*)0x%x) = 0x12345678" %
+                (self.hart.ram + self.hart.ram_size - 4))
+
+        # read before end of memory
+        self.memory_test(self.hart.ram + self.hart.ram_size - 8,
+                         self.hart.ram + self.hart.ram_size,
+                         self.real_values)
+
+        # read across end of memory
+        self.memory_test(self.hart.ram + self.hart.ram_size - 8,
+                         self.hart.ram + self.hart.ram_size + 8,
+                         self.real_values + " " + self.zero_values)
+
+        # read after end of memory
+        self.memory_test(self.hart.ram + self.hart.ram_size,
+                         self.hart.ram + self.hart.ram_size + 8,
+                         self.zero_values)
+
+    def memory_test(self, start_addr, end_addr, expected_values):
+        dump = tempfile.NamedTemporaryFile(suffix=".simdata")
+        self.gdb.command("dump verilog memory %s 0x%x 0x%x" %
+                (dump.name, start_addr, end_addr))
+        self.gdb.command("shell cat %s" % dump.name)
+        line = dump.readline()
+        line = dump.readline()
+        assertEqual(line.strip(), expected_values)
+
+class MemTestBlock(GdbTest):
+    length = 1024
+    line_length = 16
+
+    def write(self, temporary_file):
+        data = ""
+        for i in range(self.length // self.line_length):
+            line_data = "".join(["%c" % random.randrange(256)
+                for _ in range(self.line_length)])
+            data += line_data
+            temporary_file.write(ihex_line(i * self.line_length, 0,
+                line_data).encode())
+        temporary_file.flush()
+        return data
+
+    def spot_check_memory(self, data):
+        increment = 19 * 4
+        for offset in list(range(0, self.length, increment)) + [self.length-4]:
+            value = self.gdb.p("*((int*)0x%x)" % (self.hart.ram + offset))
+            written = ord(data[offset]) | \
+                    (ord(data[offset+1]) << 8) | \
+                    (ord(data[offset+2]) << 16) | \
+                    (ord(data[offset+3]) << 24)
+            assertEqual(value, written)
+
+    def test_block(self, extra_delay):
+        a = tempfile.NamedTemporaryFile(suffix=".ihex")
+        data = self.write(a)
+
+        self.gdb.command("shell cat %s" % a.name)
+        self.gdb.command("restore %s 0x%x" % (a.name, self.hart.ram),
+                reset_delays=50 + extra_delay)
+        self.spot_check_memory(data)
+
+        b = tempfile.NamedTemporaryFile(suffix=".srec")
+        self.gdb.command("dump srec memory %s 0x%x 0x%x" % (b.name,
+            self.hart.ram, self.hart.ram + self.length), ops=self.length / 32,
+            reset_delays=100 + extra_delay)
+        self.gdb.command("shell cat %s" % b.name)
+        highest_seen = 0
+        for line in b:
+            record_type, address, line_data = srec_parse(line)
+            if record_type == 3:
+                offset = address - (self.hart.ram & 0xffffffff)
+                written_data = data[offset:offset+len(line_data)]
+                highest_seen += len(line_data)
+                if line_data != written_data:
+                    raise TestFailed(
+                            "Data mismatch at 0x%x (offset 0x%x); wrote %s but "
+                            "read %s" % (
+                                self.hart.ram + offset, offset,
+                                readable_binary_string(written_data),
+                                readable_binary_string(line_data)))
+        assertEqual(highest_seen, self.length)
+
+# Run memory block tests with different reset delays, so hopefully we hit busy
+# at every possible relevant time.
+class MemTestBlock0(MemTestBlock):
+    def test(self):
+        return self.test_block(0)
+
+class MemTestBlock1(MemTestBlock):
+    def test(self):
+        return self.test_block(1)
+
+class MemTestBlock2(MemTestBlock):
+    def test(self):
+        return self.test_block(2)
+
+class InstantHaltTest(GdbTest):
+    def test(self):
+        """Assert that reset is really resetting what it should."""
+        self.gdb.command("monitor reset halt")
+        self.gdb.command("flushregs")
+        threads = self.gdb.threads()
+        pcs = []
+        for t in threads:
+            self.gdb.thread(t)
+            pcs.append(self.gdb.p("$pc"))
+        for pc in pcs:
+            assertIn(pc, self.hart.reset_vectors)
+        # mcycle and minstret have no defined reset value.
+        mstatus = self.gdb.p("$mstatus")
+        assertEqual(mstatus & (MSTATUS_MIE | MSTATUS_MPRV |
+            MSTATUS_VM), 0)
+
+class InstantChangePc(GdbTest):
+    def test(self):
+        """Change the PC right as we come out of reset."""
+        # 0x13 is nop
+        self.gdb.command("monitor reset halt")
+        self.gdb.command("flushregs")
+        self.gdb.command("p *((int*) 0x%x)=0x13" % self.hart.ram)
+        self.gdb.command("p *((int*) 0x%x)=0x13" % (self.hart.ram + 4))
+        self.gdb.command("p *((int*) 0x%x)=0x13" % (self.hart.ram + 8))
+        self.gdb.p("$pc=0x%x" % self.hart.ram)
+        self.gdb.stepi()
+        assertEqual((self.hart.ram + 4), self.gdb.p("$pc"))
+        self.gdb.stepi()
+        assertEqual((self.hart.ram + 8), self.gdb.p("$pc"))
+
+class ProgramTest(GdbSingleHartTest):
+    # Include malloc so that gdb can make function calls. I suspect this malloc
+    # will silently blow through the memory set aside for it, so be careful.
+    compile_args = ("programs/counting_loop.c", "-DDEFINE_MALLOC",
+            "-DDEFINE_FREE")
+
+    def setup(self):
+        self.gdb.load()
+
+    def exit(self, expected_result=10):
+        self.gdb.command("delete")
+        self.gdb.b("_exit")
+        output = self.gdb.c()
+        assertIn("Breakpoint", output)
+        assertIn("_exit", output)
+        assertEqual(self.gdb.p("status"), expected_result)
+
+class ProgramHwWatchpoint(ProgramTest):
+    def test(self):
+        mainbp = self.gdb.b("main")
+        output = self.gdb.c()
+        assertIn("Breakpoint", output)
+        assertIn("main", output)
+        self.gdb.command("delete %d" % mainbp)
+        self.gdb.watch("counter == 5")
+        # Watchpoint hits when counter becomes 5.
+        output = self.gdb.c()
+        assertEqual(self.gdb.p("counter"), 5)
+        # Watchpoint hits when counter no longer is 5.
+        output = self.gdb.c()
+        assertEqual(self.gdb.p("counter"), 6)
+        # The watchpoint is going out of scope
+        output = self.gdb.c()
+        assertIn("Watchpoint", output)
+        assertIn("deleted", output)
+        self.exit()
+
+class ProgramSwWatchpoint(ProgramTest):
+    def test(self):
+        self.gdb.b("main")
+        output = self.gdb.c()
+        assertIn("Breakpoint", output)
+        assertIn("main", output)
+        self.gdb.swatch("counter == 5")
+        # The watchpoint is triggered when the expression changes
+        output = self.gdb.c()
+        assertIn("Watchpoint", output)
+        assertIn("counter == 5", output)
+        output = self.gdb.p_raw("counter")
+        assertIn("5", output)
+        output = self.gdb.c()
+        assertIn("Watchpoint", output)
+        assertIn("counter == 5", output)
+        output = self.gdb.p_raw("counter")
+        assertIn("6", output)
+        output = self.gdb.c()
+        # The watchpoint is going out of scope
+        assertIn("Watchpoint", output)
+        assertIn("deleted", output)
+        self.exit()
+
+class DebugTest(GdbSingleHartTest):
+    # Include malloc so that gdb can make function calls. I suspect this malloc
+    # will silently blow through the memory set aside for it, so be careful.
+    compile_args = ("programs/debug.c", "programs/checksum.c",
+            "programs/tiny-malloc.c", "-DDEFINE_MALLOC", "-DDEFINE_FREE")
+
+    def setup(self):
+        self.gdb.load()
+        self.gdb.b("_exit")
+
+    def exit(self, expected_result=0xc86455d4):
+        output = self.gdb.c()
+        assertIn("Breakpoint", output)
+        assertIn("_exit", output)
+        assertEqual(self.gdb.p("status"), expected_result)
+
+class DebugCompareSections(DebugTest):
+    def test(self):
+        output = self.gdb.command("compare-sections", ops=10)
+        matched = 0
+        for line in output.splitlines():
+            if line.startswith("Section"):
+                assert line.endswith("matched.")
+                matched += 1
+        assertGreater(matched, 1)
+
+class DebugFunctionCall(DebugTest):
+    def test(self):
+        self.gdb.b("main:start")
+        self.gdb.c()
+        assertEqual(self.gdb.p('fib(6)', ops=10), 8)
+        assertEqual(self.gdb.p('fib(7)', ops=10), 13)
+        self.exit()
+
+class DebugChangeString(DebugTest):
+    def test(self):
+        text = "This little piggy went to the market."
+        self.gdb.b("main:start")
+        self.gdb.c()
+        self.gdb.p('fox = "%s"' % text)
+        self.exit(0x43b497b8)
+
+class DebugTurbostep(DebugTest):
+    def test(self):
+        """Single step a bunch of times."""
+        self.gdb.b("main:start")
+        self.gdb.c()
+        self.gdb.command("p i=0")
+        last_pc = None
+        advances = 0
+        jumps = 0
+        for _ in range(10):
+            self.gdb.stepi()
+            pc = self.gdb.p("$pc")
+            assertNotEqual(last_pc, pc)
+            if last_pc and pc > last_pc and pc - last_pc <= 4:
+                advances += 1
+            else:
+                jumps += 1
+            last_pc = pc
+        # Some basic sanity that we're not running between breakpoints or
+        # something.
+        assertGreater(jumps, 1)
+        assertGreater(advances, 5)
+
+class DebugExit(DebugTest):
+    def test(self):
+        self.exit()
+
+class DebugSymbols(DebugTest):
+    def test(self):
+        bp = self.gdb.b("main")
+        output = self.gdb.c()
+        assertIn(", main ", output)
+        self.gdb.command("delete %d" % bp)
+        bp = self.gdb.b("rot13")
+        output = self.gdb.c()
+        assertIn(", rot13 ", output)
+        self.gdb.command("delete %d" % bp)
+
+class DebugBreakpoint(DebugTest):
+    def test(self):
+        self.gdb.b("rot13")
+        # The breakpoint should be hit exactly 2 times.
+        for _ in range(2):
+            output = self.gdb.c()
+            self.gdb.p("$pc")
+            assertIn("Breakpoint ", output)
+            assertIn("rot13 ", output)
+        self.exit()
+
+class Hwbp1(DebugTest):
+    def test(self):
+        if self.hart.instruction_hardware_breakpoint_count < 1:
+            raise TestNotApplicable
+
+        if not self.hart.honors_tdata1_hmode:
+            # Run to main before setting the breakpoint, because startup code
+            # will otherwise clear the trigger that we set.
+            self.gdb.b("main")
+            self.gdb.c()
+
+        self.gdb.command("delete")
+        self.gdb.hbreak("rot13")
+        # The breakpoint should be hit exactly 2 times.
+        for _ in range(2):
+            output = self.gdb.c()
+            self.gdb.p("$pc")
+            assertRegex(output, r"[bB]reakpoint")
+            assertIn("rot13 ", output)
+        self.gdb.b("_exit")
+        self.exit()
+
+def MCONTROL_TYPE(xlen):
+    return 0xf<<((xlen)-4)
+def MCONTROL_DMODE(xlen):
+    return 1<<((xlen)-5)
+def MCONTROL_MASKMAX(xlen):
+    return 0x3<<((xlen)-11)
+
+MCONTROL_SELECT = (1<<19)
+MCONTROL_TIMING = (1<<18)
+MCONTROL_ACTION = (0x3f<<12)
+MCONTROL_CHAIN = (1<<11)
+MCONTROL_MATCH = (0xf<<7)
+MCONTROL_M = (1<<6)
+MCONTROL_H = (1<<5)
+MCONTROL_S = (1<<4)
+MCONTROL_U = (1<<3)
+MCONTROL_EXECUTE = (1<<2)
+MCONTROL_STORE = (1<<1)
+MCONTROL_LOAD = (1<<0)
+
+MCONTROL_TYPE_NONE = 0
+MCONTROL_TYPE_MATCH = 2
+
+MCONTROL_ACTION_DEBUG_EXCEPTION = 0
+MCONTROL_ACTION_DEBUG_MODE = 1
+MCONTROL_ACTION_TRACE_START = 2
+MCONTROL_ACTION_TRACE_STOP = 3
+MCONTROL_ACTION_TRACE_EMIT = 4
+
+MCONTROL_MATCH_EQUAL = 0
+MCONTROL_MATCH_NAPOT = 1
+MCONTROL_MATCH_GE = 2
+MCONTROL_MATCH_LT = 3
+MCONTROL_MATCH_MASK_LOW = 4
+MCONTROL_MATCH_MASK_HIGH = 5
+
+def set_field(reg, mask, val):
+    return ((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask))
+
+class HwbpManual(DebugTest):
+    """Make sure OpenOCD behaves "normal" when the user sets a trigger by
+    writing the trigger registers themselves directly."""
+    def early_applicable(self):
+        return self.target.support_manual_hwbp and \
+            self.hart.instruction_hardware_breakpoint_count >= 1
+
+    def test(self):
+        if not self.hart.honors_tdata1_hmode:
+            # Run to main before setting the breakpoint, because startup code
+            # will otherwise clear the trigger that we set.
+            self.gdb.b("main")
+            self.gdb.c()
+
+        self.gdb.command("delete")
+        #self.gdb.hbreak("rot13")
+        tdata1 = MCONTROL_DMODE(self.hart.xlen)
+        tdata1 = set_field(tdata1, MCONTROL_ACTION, MCONTROL_ACTION_DEBUG_MODE)
+        tdata1 = set_field(tdata1, MCONTROL_MATCH, MCONTROL_MATCH_EQUAL)
+        tdata1 |= MCONTROL_M | MCONTROL_S | MCONTROL_U | MCONTROL_EXECUTE
+
+        tselect = 0
+        while True:
+            self.gdb.p("$tselect=%d" % tselect)
+            value = self.gdb.p("$tselect")
+            if value != tselect:
+                raise TestNotApplicable
+            self.gdb.p("$tdata1=0x%x" % tdata1)
+            value = self.gdb.p("$tselect")
+            if value == tdata1:
+                break
+            self.gdb.p("$tdata1=0")
+            tselect += 1
+
+        self.gdb.p("$tdata2=&rot13")
+        # The breakpoint should be hit exactly 2 times.
+        for _ in range(2):
+            output = self.gdb.c(ops=2)
+            self.gdb.p("$pc")
+            assertRegex(output, r"[bB]reakpoint")
+            assertIn("rot13 ", output)
+        self.gdb.p("$tdata2=&crc32a")
+        self.gdb.c()
+        before = self.gdb.p("$pc")
+        assertEqual(before, self.gdb.p("&crc32a"))
+        self.gdb.stepi()
+        after = self.gdb.p("$pc")
+        assertNotEqual(before, after)
+
+        self.gdb.b("_exit")
+        self.exit()
+
+
+class Hwbp2(DebugTest):
+    def test(self):
+        if self.hart.instruction_hardware_breakpoint_count < 2:
+            raise TestNotApplicable
+
+        self.gdb.command("delete")
+        self.gdb.hbreak("main")
+        self.gdb.hbreak("rot13")
+        # We should hit 3 breakpoints.
+        for expected in ("main", "rot13", "rot13"):
+            output = self.gdb.c()
+            self.gdb.p("$pc")
+            assertRegex(output, r"[bB]reakpoint")
+            assertIn("%s " % expected, output)
+        self.gdb.command("delete")
+        self.gdb.b("_exit")
+        self.exit()
+
+class TooManyHwbp(DebugTest):
+    def test(self):
+        for i in range(30):
+            self.gdb.hbreak("*rot13 + %d" % (i * 4))
+
+        output = self.gdb.c(checkOutput=False)
+        assertIn("Cannot insert hardware breakpoint", output)
+        # There used to be a bug where this would fail if done twice in a row.
+        output = self.gdb.c(checkOutput=False)
+        assertIn("Cannot insert hardware breakpoint", output)
+        # Clean up, otherwise the hardware breakpoints stay set and future
+        # tests may fail.
+        self.gdb.command("delete")
+        self.gdb.b("_exit")
+        self.exit()
+
+class Registers(DebugTest):
+    def test(self):
+        # Get to a point in the code where some registers have actually been
+        # used.
+        self.gdb.b("rot13")
+        self.gdb.c()
+        self.gdb.c()
+        # Try both forms to test gdb.
+        for cmd in ("info all-registers", "info registers all"):
+            output = self.gdb.command(cmd, ops=20)
+            for reg in ('zero', 'ra', 'sp', 'gp', 'tp'):
+                assertIn(reg, output)
+            for line in output.splitlines():
+                assertRegex(line, r"^\S")
+
+        #TODO
+        # mcpuid is one of the few registers that should have the high bit set
+        # (for rv64).
+        # Leave this commented out until gdb and spike agree on the encoding of
+        # mcpuid (which is going to be renamed to misa in any case).
+        #assertRegex(output, ".*mcpuid *0x80")
+
+        #TODO:
+        # The instret register should always be changing.
+        #last_instret = None
+        #for _ in range(5):
+        #    instret = self.gdb.p("$instret")
+        #    assertNotEqual(instret, last_instret)
+        #    last_instret = instret
+        #    self.gdb.stepi()
+
+        self.exit()
+
+class UserInterrupt(DebugTest):
+    def test(self):
+        """Sending gdb ^C while the program is running should cause it to
+        halt."""
+        self.gdb.b("main:start")
+        self.gdb.c()
+        self.gdb.p("i=123")
+        self.gdb.c(wait=False)
+        time.sleep(2)
+        output = self.gdb.interrupt()
+        assert "main" in output
+        assertGreater(self.gdb.p("j"), 10)
+        self.gdb.p("i=0")
+        self.exit()
+
+class RepeatReadTest(DebugTest):
+    def early_applicable(self):
+        return self.target.supports_clint_mtime
+
+    def test(self):
+        self.gdb.b("main:start")
+        self.gdb.c()
+        mtime_addr = 0x02000000 + 0xbff8
+        count = 1024
+        output = self.gdb.command("monitor riscv repeat_read %d 0x%x 4" %
+                (count, mtime_addr))
+        values = []
+        for line in output.splitlines():
+            # Ignore warnings
+            if line.startswith("Batch memory"):
+                continue
+            for v in line.split():
+                values.append(int(v, 16))
+
+        assertEqual(len(values), count)
+        # mtime should only ever increase, unless it wraps
+        slop = 0x100000
+        for i in range(1, len(values)):
+            if values[i] < values[i-1]:
+                # wrapped
+                assertLess(values[i], slop)
+            else:
+                assertGreater(values[i], values[i-1])
+                assertLess(values[i], values[i-1] + slop)
+
+        output = self.gdb.command("monitor riscv repeat_read 0 0x%x 4" %
+                mtime_addr)
+        assertEqual(output, "")
+
+class Semihosting(GdbSingleHartTest):
+    # Include malloc so that gdb can assign a string.
+    compile_args = ("programs/semihosting.c", "programs/tiny-malloc.c",
+                    "-DDEFINE_MALLOC", "-DDEFINE_FREE")
+
+    def early_applicable(self):
+        return self.target.test_semihosting
+
+    def setup(self):
+        self.gdb.load()
+        self.parkOtherHarts()
+        self.gdb.b("_exit")
+
+    def exit(self, expected_result=0):
+        output = self.gdb.c()
+        assertIn("Breakpoint", output)
+        assertIn("_exit", output)
+        assertEqual(self.gdb.p("status"), expected_result)
+
+    def test(self):
+        """Sending gdb ^C while the program is running should cause it to
+        halt."""
+        temp = tempfile.NamedTemporaryFile(suffix=".data")
+
+        self.gdb.b("main:begin")
+        self.gdb.c()
+        self.gdb.p('filename="%s"' % temp.name)
+        self.exit()
+
+        contents = open(temp.name, "r").readlines()
+        assertIn("Hello, world!\n", contents)
+
+class InterruptTest(GdbSingleHartTest):
+    compile_args = ("programs/interrupt.c",)
+
+    def early_applicable(self):
+        return self.target.supports_clint_mtime
+
+    def setup(self):
+        self.gdb.load()
+
+    def test(self):
+        self.gdb.b("main")
+        output = self.gdb.c()
+        assertIn(" main ", output)
+        self.gdb.b("trap_entry")
+        output = self.gdb.c()
+        assertIn(" trap_entry ", output)
+        assertEqual(self.gdb.p("$mip") & 0x80, 0x80)
+        assertEqual(self.gdb.p("interrupt_count"), 0)
+        # You'd expect local to still be 0, but it looks like spike doesn't
+        # jump to the interrupt handler immediately after the write to
+        # mtimecmp.
+        assertLess(self.gdb.p("local"), 1000)
+        self.gdb.command("delete breakpoints")
+        for _ in range(10):
+            self.gdb.c(wait=False)
+            time.sleep(2)
+            self.gdb.interrupt()
+            interrupt_count = self.gdb.p("interrupt_count")
+            local = self.gdb.p("local")
+            if interrupt_count > 1000 and \
+                    local > 1000:
+                return
+
+        assertGreater(interrupt_count, 1000)
+        assertGreater(local, 1000)
+
+    def postMortem(self):
+        GdbSingleHartTest.postMortem(self)
+        self.gdb.p("*((long long*) 0x200bff8)")
+        self.gdb.p("*((long long*) 0x2004000)")
+        self.gdb.p("interrupt_count")
+        self.gdb.p("local")
+
+class MulticoreRegTest(GdbTest):
+    compile_args = ("programs/infinite_loop.S", "-DMULTICORE")
+
+    def early_applicable(self):
+        return len(self.target.harts) > 1
+
+    def setup(self):
+        self.gdb.load()
+        for hart in self.target.harts:
+            self.gdb.select_hart(hart)
+            self.gdb.p("$pc=_start")
+
+    def test(self):
+        # Run to main
+        for hart in self.target.harts:
+            self.gdb.select_hart(hart)
+            self.gdb.b("main")
+            self.gdb.c()
+            assertIn("main", self.gdb.where())
+            self.gdb.command("delete breakpoints")
+
+        # Run through the entire loop.
+        for hart in self.target.harts:
+            self.gdb.select_hart(hart)
+            self.gdb.b("main_end")
+            self.gdb.c()
+            assertIn("main_end", self.gdb.where())
+
+        hart_ids = []
+        for hart in self.target.harts:
+            self.gdb.select_hart(hart)
+            # Check register values.
+            x1 = self.gdb.p("$x1")
+            hart_id = self.gdb.p("$mhartid")
+            assertEqual(x1, hart_id << 8)
+            assertNotIn(hart_id, hart_ids)
+            hart_ids.append(hart_id)
+            for n in range(2, 32):
+                value = self.gdb.p("$x%d" % n)
+                assertEqual(value, (hart_ids[-1] << 8) + n - 1)
+
+        # Confirmed that we read different register values for different harts.
+        # Write a new value to x1, and run through the add sequence again.
+
+        for hart in self.target.harts:
+            self.gdb.select_hart(hart)
+            self.gdb.p("$x1=0x%x" % (hart.index * 0x1000))
+            self.gdb.p("$pc=main_post_csrr")
+            self.gdb.c()
+        for hart in self.target.harts:
+            self.gdb.select_hart(hart)
+            assertIn("main", self.gdb.where())
+            # Check register values.
+            for n in range(1, 32):
+                value = self.gdb.p("$x%d" % n)
+                assertEqual(value, hart.index * 0x1000 + n - 1)
+
+#class MulticoreRunHaltStepiTest(GdbTest):
+#    compile_args = ("programs/multicore.c", "-DMULTICORE")
+#
+#    def early_applicable(self):
+#        return len(self.target.harts) > 1
+#
+#    def setup(self):
+#        self.gdb.load()
+#        for hart in self.target.harts:
+#            self.gdb.select_hart(hart)
+#            self.gdb.p("$mhartid")
+#            self.gdb.p("$pc=_start")
+#
+#    def test(self):
+#        previous_hart_count = [0 for h in self.target.harts]
+#        previous_interrupt_count = [0 for h in self.target.harts]
+#        # Check 10 times
+#        for i in range(10):
+#            # 3 attempts for each time we want the check to pass
+#            for attempt in range(3):
+#                self.gdb.global_command("echo round %d attempt %d\\n" % (i,
+#                    attempt))
+#                self.gdb.c_all(wait=False)
+#                time.sleep(2)
+#                self.gdb.interrupt_all()
+#                hart_count = self.gdb.p("hart_count")
+#                interrupt_count = self.gdb.p("interrupt_count")
+#                ok = True
+#                for i, h in enumerate(self.target.harts):
+#                    if hart_count[i] <= previous_hart_count[i]:
+#                        ok = False
+#                        break
+#                    if interrupt_count[i] <= previous_interrupt_count[i]:
+#                        ok = False
+#                        break
+#                    self.gdb.p("$mie")
+#                    self.gdb.p("$mip")
+#                    self.gdb.p("$mstatus")
+#                    self.gdb.p("$priv")
+#                    self.gdb.p("buf", fmt="")
+#                    self.gdb.select_hart(h)
+#                    pc = self.gdb.p("$pc")
+#                    self.gdb.stepi()
+#                    stepped_pc = self.gdb.p("$pc")
+#                    assertNotEqual(pc, stepped_pc)
+#                previous_hart_count = hart_count
+#                previous_interrupt_count = interrupt_count
+#                if ok:
+#                    break
+#            else:
+#                assert False, \
+#                        "hart count or interrupt didn't increment as expected"
+
+class MulticoreRunAllHaltOne(GdbTest):
+    compile_args = ("programs/multicore.c", "-DMULTICORE")
+
+    def early_applicable(self):
+        return len(self.target.harts) > 1
+
+    def setup(self):
+        self.gdb.select_hart(self.target.harts[0])
+        self.gdb.load()
+        for hart in self.target.harts:
+            self.gdb.select_hart(hart)
+            self.gdb.p("$pc=_start")
+
+    def test(self):
+        if not self.gdb.one_hart_per_gdb():
+            raise TestNotApplicable
+
+        # Run harts in reverse order
+        for h in reversed(self.target.harts):
+            self.gdb.select_hart(h)
+            self.gdb.c(wait=False)
+
+        self.gdb.interrupt()
+        # Give OpenOCD time to call poll() on both harts, which is what causes
+        # the bug.
+        time.sleep(1)
+        self.gdb.p("buf", fmt="")
+
+class MulticoreRtosSwitchActiveHartTest(GdbTest):
+    compile_args = ("programs/multicore.c", "-DMULTICORE")
+
+    def early_applicable(self):
+        return len(self.target.harts) > 1
+
+    def setup(self):
+        self.gdb.select_hart(self.target.harts[0])
+        self.gdb.load()
+        for hart in self.target.harts:
+            self.gdb.select_hart(hart)
+            self.gdb.p("$pc=_start")
+
+    def test(self):
+        if self.gdb.one_hart_per_gdb():
+            raise TestNotApplicable
+
+        # Set breakpoint near '_start' label to increase the chances of a
+        # situation when all harts hit breakpoint immediately and
+        # simultaneously.
+        self.gdb.b("set_trap_handler")
+
+        # Check that all harts hit breakpoint one by one.
+        for _ in range(len(self.target.harts)):
+            output = self.gdb.c()
+            assertIn("hit Breakpoint", output)
+            assertIn("set_trap_handler", output)
+            assertNotIn("received signal SIGTRAP", output)
+
+class SmpSimultaneousRunHalt(GdbTest):
+    compile_args = ("programs/run_halt_timing.S", "-DMULTICORE")
+
+    def early_applicable(self):
+        return len(self.target.harts) > 1 and self.target.support_hasel
+
+    def setup(self):
+        self.gdb.select_hart(self.target.harts[0])
+        self.gdb.load()
+        for hart in self.target.harts:
+            self.gdb.select_hart(hart)
+            self.gdb.p("$pc=_start")
+
+    def test(self):
+        if self.gdb.one_hart_per_gdb() or not self.server.smp():
+            raise TestNotApplicable
+
+        old_mtime = set()
+        for _ in range(5):
+            self.gdb.c_all(wait=False)
+            time.sleep(2)
+            self.gdb.interrupt_all()
+
+            mtime_value = []
+            counter = []
+            for hart in self.target.harts:
+                self.gdb.select_hart(hart)
+                mv = self.gdb.p("$s2")
+                assertNotIn(mv, old_mtime,
+                        "mtime doesn't appear to be changing at all")
+                mtime_value.append(mv)
+                c = self.gdb.p("$s0")
+                assertNotEqual(c, 0,
+                        "counter didn't increment; code didn't run?")
+                counter.append(c)
+                # Reset the counter for the next round.
+                self.gdb.p("$s0=0")
+
+            old_mtime.update(mtime_value)
+
+            mtime_spread = max(mtime_value) - min(mtime_value)
+            print("mtime_spread:", mtime_spread)
+            counter_spread = max(counter) - min(counter)
+            print("counter_spread:", counter_spread)
+
+            assertLess(mtime_spread, 101 * (len(self.target.harts) - 1),
+                    "Harts don't halt around the same time.")
+            # spike executes normal code 5000 instructions at a time, so we
+            # expect 5k instructions to be executed on one hart before the
+            # other gets to go. Our loop (unoptimized) is quite a few
+            # instructions, but allow for 5k anyway.
+            assertLess(counter_spread, 5001 * (len(self.target.harts) - 1),
+                    "Harts don't resume around the same time.")
+
+class StepTest(GdbSingleHartTest):
+    compile_args = ("programs/step.S", )
+
+    def setup(self):
+        self.gdb.load()
+        self.gdb.b("main")
+        self.gdb.c()
+
+    def test(self):
+        main_address = self.gdb.p("$pc")
+        if self.hart.extensionSupported("c"):
+            sequence = (4, 8, 0xc, 0xe, 0x14, 0x18, 0x22, 0x1c, 0x24, 0x24)
+        else:
+            sequence = (4, 8, 0xc, 0x10, 0x18, 0x1c, 0x28, 0x20, 0x2c, 0x2c)
+        for expected in sequence:
+            self.gdb.stepi()
+            pc = self.gdb.p("$pc")
+            assertEqual("%x" % (pc - main_address), "%x" % expected)
+
+class JumpHbreak(GdbSingleHartTest):
+    """'jump' resumes execution at location. Execution stops again immediately
+    if there is a breakpoint there.
+    That second line can be trouble."""
+    compile_args = ("programs/trigger.S", )
+
+    def early_applicable(self):
+        return self.hart.instruction_hardware_breakpoint_count >= 1
+
+    def setup(self):
+        self.gdb.load()
+        self.gdb.hbreak("main")
+        self.gdb.c()
+        self.gdb.command("delete 1")
+
+    def test(self):
+        self.gdb.b("read_loop")
+        self.gdb.command("hbreak just_before_read_loop")
+        output = self.gdb.command("jump just_before_read_loop")
+        assertRegex(output, r"Breakpoint \d, just_before_read_loop ")
+        output = self.gdb.c()
+        assertRegex(output, r"Breakpoint \d, read_loop ")
+
+class TriggerTest(GdbSingleHartTest):
+    compile_args = ("programs/trigger.S", )
+    def setup(self):
+        self.gdb.load()
+        self.gdb.b("main")
+        self.gdb.c()
+        self.gdb.command("delete")
+
+    def exit(self):
+        self.gdb.command("delete")
+        self.gdb.b("_exit")
+        output = self.gdb.c()
+        assertIn("Breakpoint", output)
+        assertIn("_exit", output)
+
+class TriggerExecuteInstant(TriggerTest):
+    """Test an execute breakpoint on the first instruction executed out of
+    debug mode."""
+    def test(self):
+        main_address = self.gdb.p("$pc")
+        self.gdb.command("hbreak *0x%x" % (main_address + 4))
+        self.gdb.c()
+        assertEqual(self.gdb.p("$pc"), main_address+4)
+
+# FIXME: Triggers aren't quite working yet
+#class TriggerLoadAddress(TriggerTest):
+#    def test(self):
+#        self.gdb.command("rwatch *((&data)+1)")
+#        output = self.gdb.c()
+#        assertIn("read_loop", output)
+#        assertEqual(self.gdb.p("$a0"),
+#                self.gdb.p("(&data)+1"))
+#        self.exit()
+
+class TriggerLoadAddressInstant(TriggerTest):
+    """Test a load address breakpoint on the first instruction executed out of
+    debug mode."""
+    def test(self):
+        self.gdb.command("b just_before_read_loop")
+        self.gdb.c()
+        read_loop = self.gdb.p("&read_loop")
+        read_again = self.gdb.p("&read_again")
+        data = self.gdb.p("&data")
+        self.gdb.command("rwatch *0x%x" % data)
+        self.gdb.c()
+        # Accept hitting the breakpoint before or after the load instruction.
+        assertIn(self.gdb.p("$pc"), [read_loop, read_loop + 4])
+        assertEqual(self.gdb.p("$a0"), self.gdb.p("&data"))
+
+        self.gdb.c()
+        assertIn(self.gdb.p("$pc"), [read_again, read_again + 4])
+        assertEqual(self.gdb.p("$a0"), self.gdb.p("&data"))
+
+# FIXME: Triggers aren't quite working yet
+#class TriggerStoreAddress(TriggerTest):
+#    def test(self):
+#        self.gdb.command("watch *((&data)+3)")
+#        output = self.gdb.c()
+#        assertIn("write_loop", output)
+#        assertEqual(self.gdb.p("$a0"),
+#                self.gdb.p("(&data)+3"))
+#        self.exit()
+
+class TriggerStoreAddressInstant(TriggerTest):
+    def test(self):
+        """Test a store address breakpoint on the first instruction executed out
+        of debug mode."""
+        self.gdb.command("b just_before_write_loop")
+        self.gdb.c()
+        write_loop = self.gdb.p("&write_loop")
+        data = self.gdb.p("&data")
+        self.gdb.command("watch *0x%x" % data)
+        self.gdb.c()
+
+        # Accept hitting the breakpoint before or after the store instruction.
+        assertIn(self.gdb.p("$pc"), [write_loop, write_loop + 4])
+        assertEqual(self.gdb.p("$a0"), self.gdb.p("&data"))
+
+class TriggerDmode(TriggerTest):
+    def early_applicable(self):
+        return self.hart.honors_tdata1_hmode
+
+    def check_triggers(self, tdata1_lsbs, tdata2):
+        dmode = 1 << (self.hart.xlen-5)
+
+        triggers = []
+
+        if self.hart.xlen == 32:
+            xlen_type = 'int'
+        elif self.hart.xlen == 64:
+            xlen_type = 'long long'
+        else:
+            raise NotImplementedError
+
+        dmode_count = 0
+        i = 0
+        for i in range(16):
+            tdata1 = self.gdb.p("((%s *)&data)[%d]" % (xlen_type, 2*i))
+            if tdata1 == 0:
+                break
+            tdata2 = self.gdb.p("((%s *)&data)[%d]" % (xlen_type, 2*i+1))
+
+            if tdata1 & dmode:
+                dmode_count += 1
+            else:
+                assertEqual(tdata1 & 0xffff, tdata1_lsbs)
+                assertEqual(tdata2, tdata2)
+
+        assertGreater(i, 1)
+        assertEqual(dmode_count, 1)
+
+        return triggers
+
+    def test(self):
+        # If we want this test to run from flash, we can't have any software
+        # breakpoints set.
+
+        self.gdb.command("hbreak write_load_trigger")
+        self.gdb.p("$pc=write_store_trigger")
+        output = self.gdb.c()
+        assertIn("write_load_trigger", output)
+        self.check_triggers((1<<6) | (1<<1), 0xdeadbee0)
+        self.gdb.command("delete")
+        self.gdb.command("hbreak clear_triggers")
+        output = self.gdb.c()
+        assertIn("clear_triggers", output)
+        self.check_triggers((1<<6) | (1<<0), 0xfeedac00)
+        self.gdb.command("delete")
+        self.exit()
+
+class RegsTest(GdbSingleHartTest):
+    compile_args = ("programs/regs.S", )
+    def setup(self):
+        self.gdb.load()
+        main_bp = self.gdb.b("main")
+        output = self.gdb.c()
+        assertIn("Breakpoint ", output)
+        assertIn("main", output)
+        self.gdb.command("delete %d" % main_bp)
+        self.gdb.b("handle_trap")
+
+class WriteGprs(RegsTest):
+    def test(self):
+        if self.hart.extensionSupported('E'):
+            regs = [("x%d" % n) for n in range(2, 16)]
+        else:
+            regs = [("x%d" % n) for n in range(2, 32)]
+
+        self.gdb.p("$pc=write_regs")
+        for i, r in enumerate(regs):
+            self.gdb.p("$%s=%d" % (r, (0xdeadbeef<<i)+17))
+        self.gdb.p("$x1=&data")
+        self.gdb.command("b all_done")
+        output = self.gdb.c()
+        assertIn("Breakpoint ", output)
+
+        # Just to get this data in the log.
+        self.gdb.command("x/30gx &data")
+        self.gdb.command("info registers")
+        for n in range(len(regs)):
+            assertEqual(self.gdb.x("(char*)(&data)+%d" % (8*n), 'g'),
+                    ((0xdeadbeef<<n)+17) & ((1<<self.hart.xlen)-1))
+
+class WriteCsrs(RegsTest):
+    def test(self):
+        # As much a test of gdb as of the simulator.
+        self.gdb.p("$mscratch=0")
+        self.gdb.stepi()
+        assertEqual(self.gdb.p("$mscratch"), 0)
+        self.gdb.p("$mscratch=123")
+        self.gdb.stepi()
+        assertEqual(self.gdb.p("$mscratch"), 123)
+
+        self.gdb.p("$pc=write_regs")
+        self.gdb.p("$x1=&data")
+        self.gdb.command("b all_done")
+        self.gdb.command("c")
+
+        assertEqual(123, self.gdb.p("$mscratch"))
+        assertEqual(123, self.gdb.p("$x1"))
+        assertEqual(123, self.gdb.p("$csr832"))
+
+class DownloadTest(GdbTest):
+    def setup(self):
+        # pylint: disable=attribute-defined-outside-init
+        length = min(2**18, max(2**10, self.hart.ram_size - 2048))
+        # TODO: remove the next line so we get a bit more code to download. The
+        # line above that allows for more data runs into some error I don't
+        # have time to track down right now.
+        length = min(2**14, max(2**10, self.hart.ram_size - 2048))
+        self.download_c = tempfile.NamedTemporaryFile(prefix="download_",
+                suffix=".c", delete=False)
+        self.download_c.write(b"#include <stdint.h>\n")
+        self.download_c.write(
+                b"unsigned int crc32a(uint8_t *message, unsigned int size);\n")
+        self.download_c.write(b"uint32_t length = %d;\n" % length)
+        self.download_c.write(b"uint8_t d[%d] = {\n" % length)
+        self.crc = 0
+        assert length % 16 == 0
+        for i in range(length // 16):
+            self.download_c.write(("  /* 0x%04x */ " % (i * 16)).encode())
+            for _ in range(16):
+                value = random.randrange(1<<8)
+                self.download_c.write(("0x%02x, " % value).encode())
+                self.crc = binascii.crc32(struct.pack("B", value), self.crc)
+            self.download_c.write(b"\n")
+        self.download_c.write(b"};\n")
+        self.download_c.write(b"uint8_t *data = &d[0];\n")
+        self.download_c.write(
+                b"uint32_t main() { return crc32a(data, length); }\n")
+        self.download_c.flush()
+
+        if self.crc < 0:
+            self.crc += 2**32
+
+        self.binary = self.target.compile(self.hart, self.download_c.name,
+                "programs/checksum.c")
+        self.gdb.global_command("file %s" % self.binary)
+
+    def test(self):
+        self.gdb.load()
+        self.parkOtherHarts()
+        self.gdb.command("b _exit")
+        self.gdb.c(ops=100)
+        assertEqual(self.gdb.p("status"), self.crc)
+        os.unlink(self.download_c.name)
+
+#class MprvTest(GdbSingleHartTest):
+#    compile_args = ("programs/mprv.S", )
+#    def setup(self):
+#        self.gdb.load()
+#
+#    def test(self):
+#        """Test that the debugger can access memory when MPRV is set."""
+#        self.gdb.c(wait=False)
+#        time.sleep(0.5)
+#        self.gdb.interrupt()
+#        output = self.gdb.command("p/x *(int*)(((char*)&data)-0x80000000)")
+#        assertIn("0xbead", output)
+
+class PrivTest(GdbSingleHartTest):
+    compile_args = ("programs/priv.S", )
+    def setup(self):
+        # pylint: disable=attribute-defined-outside-init
+        self.gdb.load()
+
+        misa = self.hart.misa
+        self.supported = set()
+        if misa & (1<<20):
+            self.supported.add(0)
+        if misa & (1<<18):
+            self.supported.add(1)
+        if misa & (1<<7):
+            self.supported.add(2)
+        self.supported.add(3)
+
+        self.disable_pmp()
+
+        # Ensure Virtual Memory is disabled if applicable (SATP register is not
+        # reset)
+        try:
+            self.gdb.p("$satp=0")
+        except testlib.CouldNotFetch:
+            # SATP only exists if you have S mode.
+            pass
+
+class PrivRw(PrivTest):
+    def test(self):
+        """Test reading/writing priv."""
+        self.write_nop_program(4)
+        for privilege in range(4):
+            self.gdb.p("$priv=%d" % privilege)
+            self.gdb.stepi()
+            actual = self.gdb.p("$priv")
+            assertIn(actual, self.supported)
+            if privilege in self.supported:
+                assertEqual(actual, privilege)
+
+class PrivChange(PrivTest):
+    def test(self):
+        """Test that the core's privilege level actually changes."""
+
+        if 0 not in self.supported:
+            raise TestNotApplicable
+
+        self.gdb.b("main")
+        self.gdb.c()
+
+        # Machine mode
+        self.gdb.p("$priv=3")
+        main_address = self.gdb.p("$pc")
+        self.gdb.stepi()
+        assertEqual("%x" % self.gdb.p("$pc"), "%x" % (main_address+4))
+
+        # User mode
+        self.gdb.p("$priv=0")
+        self.gdb.stepi()
+        # Should have taken an exception, so be nowhere near main.
+        pc = self.gdb.p("$pc")
+        assertTrue(pc < main_address or pc > main_address + 0x100)
+
+class CheckMisa(GdbTest):
+    """Make sure the misa we're using is actually what the target exposes."""
+    def test(self):
+        for hart in self.target.harts:
+            self.gdb.select_hart(hart)
+            misa = self.gdb.p("$misa")
+            assertEqual(misa, hart.misa)
+
+class TranslateTest(GdbTest):
+    compile_args = ("programs/translate.c", )
+
+    def setup(self):
+        self.disable_pmp()
+
+        self.gdb.load()
+        self.gdb.b("main")
+        output = self.gdb.c()
+        assertRegex(output, r"\bmain\b")
+
+    def check_satp(self, mode):
+        if self.hart.xlen == 32:
+            satp = mode << 31
+        else:
+            satp = mode << 60
+        try:
+            self.gdb.p("$satp=0x%x" % satp)
+        except testlib.CouldNotFetch:
+            raise TestNotApplicable
+        readback = self.gdb.p("$satp")
+        self.gdb.p("$satp=0")
+        if readback != satp:
+            raise TestNotApplicable
+
+    def test_translation(self):
+        self.gdb.b("error")
+        self.gdb.b("handle_trap")
+        self.gdb.b("main:active")
+        output = self.gdb.c()
+        assertRegex(output, r"\bmain\b")
+        assertEqual(0xdeadbeef, self.gdb.p("physical[0]"))
+        assertEqual(0x55667788, self.gdb.p("physical[1]"))
+        assertEqual(0xdeadbeef, self.gdb.p("virtual[0]"))
+        assertEqual(0x55667788, self.gdb.p("virtual[1]"))
+
+SATP_MODE_OFF = 0
+SATP_MODE_SV32 = 1
+SATP_MODE_SV39 = 8
+SATP_MODE_SV48 = 9
+SATP_MODE_SV57 = 10
+SATP_MODE_SV64 = 11
+
+class Sv32Test(TranslateTest):
+    def early_applicable(self):
+        return self.hart.xlen == 32
+
+    def test(self):
+        self.check_satp(SATP_MODE_SV32)
+        self.gdb.p("vms=&sv32")
+        self.test_translation()
+
+class Sv39Test(TranslateTest):
+    def early_applicable(self):
+        return self.hart.xlen > 32
+
+    def test(self):
+        self.check_satp(SATP_MODE_SV39)
+        self.gdb.p("vms=&sv39")
+        self.test_translation()
+
+class Sv48Test(TranslateTest):
+    def early_applicable(self):
+        return self.hart.xlen > 32
+
+    def test(self):
+        self.check_satp(SATP_MODE_SV48)
+        self.gdb.p("vms=&sv48")
+        self.test_translation()
+
+class VectorTest(GdbSingleHartTest):
+    compile_args = ("programs/vectors.S", )
+
+    def early_applicable(self):
+        if not self.hart.extensionSupported('V'):
+            return False
+        # If the compiler can't build this test, say it's not applicable. At
+        # some time all compilers will support the V extension, but we're not
+        # there yet.
+        try:
+            self.compile()
+        except CompileError as e:
+            if b"Error: unknown CSR `vlenb'" in e.stderr:
+                return False
+        return True
+
+    def setup(self):
+        self.gdb.load()
+        self.gdb.b("main")
+        self.gdb.c()
+
+    def test(self):
+        vlenb = self.gdb.p("$vlenb")
+        self.gdb.command("delete")
+        self.gdb.b("_exit")
+        self.gdb.b("trap_entry")
+
+        self.gdb.b("test0")
+
+        output = self.gdb.c()
+        assertIn("Breakpoint", output)
+        assertIn("test0", output)
+
+        assertEqual(self.gdb.p("$a0"), 0)
+        a = self.gdb.x("&a", 'b', vlenb)
+        b = self.gdb.x("&b", 'b', vlenb)
+        v4 = self.gdb.p("$v4")
+        assertEqual(a, b)
+        assertEqual(b, v4["b"])
+        assertEqual(0, self.gdb.p("$a0"))
+
+        self.gdb.b("test1")
+
+        output = self.gdb.c()
+        assertIn("Breakpoint", output)
+        assertIn("test1", output)
+
+        assertEqual(self.gdb.p("$a0"), 0)
+        b = self.gdb.x("&b", 'b', vlenb)
+        c = self.gdb.x("&c", 'b', vlenb)
+        v4 = self.gdb.p("$v4")
+        assertEqual(b, c)
+        assertEqual(c, v4["b"])
+        assertEqual(0, self.gdb.p("$a0"))
+
+        output = self.gdb.c()
+        assertIn("Breakpoint", output)
+        assertIn("_exit", output)
+        assertEqual(self.gdb.p("status"), 0)
+
+parsed = None
+def main():
+    parser = argparse.ArgumentParser(
+            description="Test that gdb can talk to a RISC-V target.",
+            epilog="""
+            Example command line from the real world:
+            Run all RegsTest cases against a physical FPGA, with custom openocd command:
+            ./gdbserver.py --freedom-e300 --server_cmd "$HOME/SiFive/openocd/src/openocd -s $HOME/SiFive/openocd/tcl -d" Simple
+            """)
+    targets.add_target_options(parser)
+
+    testlib.add_test_run_options(parser)
+
+    # TODO: remove global
+    global parsed   # pylint: disable=global-statement
+    parsed = parser.parse_args()
+    target = targets.target(parsed)
+    testlib.print_log_names = parsed.print_log_names
+
+    module = sys.modules[__name__]
+
+    return testlib.run_all_tests(module, target, parsed)
+
+# TROUBLESHOOTING TIPS
+# If a particular test fails, run just that one test, eg.:
+# ./gdbserver.py MprvTest.test_mprv
+# Then inspect gdb.log and spike.log to see what happened in more detail.
+
+if __name__ == '__main__':
+    sys.exit(main())
diff --git a/apps/riscv-tests/debug/openocd.py b/apps/riscv-tests/debug/openocd.py
new file mode 100755
index 0000000..1b7c8fd
--- /dev/null
+++ b/apps/riscv-tests/debug/openocd.py
@@ -0,0 +1,85 @@
+#!/usr/bin/env python
+
+"""Test that OpenOCD can talk to a RISC-V target."""
+
+import argparse
+import sys
+
+import targets
+import testlib
+from testlib import assertIn, assertEqual
+
+class OpenOcdTest(testlib.BaseTest):
+    def __init__(self, target):
+        testlib.BaseTest.__init__(self, target)
+        self.gdb = None
+
+    def early_applicable(self):
+        return self.target.openocd_config
+
+    def setup(self):
+        # pylint: disable=attribute-defined-outside-init
+        self.cli = testlib.OpenocdCli()
+        self.cli.command("halt")
+
+    def write_nops(self, count):
+        for address in range(self.target.ram, self.target.ram + 4 * count, 4):
+            # 0x13 is nop
+            self.cli.command("mww 0x%x 0x13" % address)
+
+class RegTest(OpenOcdTest):
+    def test(self):
+        self.write_nops(4)
+
+        regs = self.cli.reg()
+        assertIn("x18", regs)
+
+        self.cli.command("reg x18 0x11782")
+        self.cli.command("step 0x%x" % self.target.ram)
+
+        assertEqual(self.cli.reg("x18"), 0x11782)
+
+class StepTest(OpenOcdTest):
+    def test(self):
+        self.write_nops(4)
+
+        self.cli.command("step 0x%x" % self.target.ram)
+        for i in range(4):
+            pc = self.cli.reg("pc")
+            assertEqual(pc, self.target.ram + 4 * (i+1))
+            self.cli.command("step")
+
+class ResumeTest(OpenOcdTest):
+    def test(self):
+        self.write_nops(16)
+
+        self.cli.command("bp 0x%x 4" % (self.target.ram + 12))
+        self.cli.command("bp 0x%x 4" % (self.target.ram + 24))
+
+        self.cli.command("resume 0x%x" % self.target.ram)
+        assertEqual(self.cli.reg("pc"), self.target.ram + 12)
+
+        self.cli.command("resume")
+        assertEqual(self.cli.reg("pc"), self.target.ram + 24)
+
+        self.cli.command("resume 0x%x" % self.target.ram)
+        assertEqual(self.cli.reg("pc"), self.target.ram + 12)
+
+def main():
+    parser = argparse.ArgumentParser(
+            description="Test that OpenOCD can talk to a RISC-V target.")
+    targets.add_target_options(parser)
+    testlib.add_test_run_options(parser)
+
+    parsed = parser.parse_args()
+
+    target = parsed.target(parsed.server_cmd, parsed.sim_cmd, parsed.isolate)
+    if parsed.xlen:
+        target.xlen = parsed.xlen
+
+    module = sys.modules[__name__]
+
+    return testlib.run_all_tests(module, target, parsed)
+
+if __name__ == '__main__':
+    sys.exit(main())
diff --git a/apps/riscv-tests/debug/programs/checksum.c b/apps/riscv-tests/debug/programs/checksum.c
new file mode 100644
index 0000000..e076f8a
--- /dev/null
+++ b/apps/riscv-tests/debug/programs/checksum.c
@@ -0,0 +1,38 @@
+#include <stdint.h>
+
+// CRC code from http://www.hackersdelight.org/hdcodetxt/crc.c.txt
+
+// Reverses (reflects) bits in a 32-bit word.
+unsigned reverse(unsigned x) {
+   x = ((x & 0x55555555) <<  1) | ((x >>  1) & 0x55555555);
+   x = ((x & 0x33333333) <<  2) | ((x >>  2) & 0x33333333);
+   x = ((x & 0x0F0F0F0F) <<  4) | ((x >>  4) & 0x0F0F0F0F);
+   x = (x << 24) | ((x & 0xFF00) << 8) |
+       ((x >> 8) & 0xFF00) | (x >> 24);
+   return x;
+}
+
+// ----------------------------- crc32a --------------------------------
+
+/* This is the basic CRC algorithm with no optimizations. It follows the
+logic circuit as closely as possible. */
+
+unsigned int crc32a(uint8_t *message, unsigned int size) {
+   int i, j;
+   unsigned int byte, crc;
+
+   i = 0;
+   crc = 0xFFFFFFFF;
+   while (i < size) {
+      byte = message[i];            // Get next byte.
+      byte = reverse(byte);         // 32-bit reversal.
+      for (j = 0; j <= 7; j++) {    // Do eight times.
+         if ((int)(crc ^ byte) < 0)
+              crc = (crc << 1) ^ 0x04C11DB7;
+         else crc = crc << 1;
+         byte = byte << 1;          // Ready next msg bit.
+      }
+      i = i + 1;
+   }
+   return reverse(~crc);
+}
diff --git a/apps/riscv-tests/debug/programs/counting_loop.c b/apps/riscv-tests/debug/programs/counting_loop.c
new file mode 100644
index 0000000..7c7d600
--- /dev/null
+++ b/apps/riscv-tests/debug/programs/counting_loop.c
@@ -0,0 +1,17 @@
+#include <stdio.h>
+#include <string.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+int main()
+{
+    int sum = 0;
+    int counter = 0;
+
+    while (counter < 10) {
+        counter = counter + 1;
+        sum = sum + counter;
+    }
+
+    return counter;
+}
diff --git a/apps/riscv-tests/debug/programs/debug.c b/apps/riscv-tests/debug/programs/debug.c
new file mode 100644
index 0000000..8a4aa73
--- /dev/null
+++ b/apps/riscv-tests/debug/programs/debug.c
@@ -0,0 +1,69 @@
+#include <stdio.h>
+#include <string.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+unsigned int crc32a(uint8_t *message, unsigned int size);
+
+unsigned int fib(unsigned int n)
+{
+    if (n == 0) {
+        return 0;
+    }
+
+    unsigned int a = 0;
+    unsigned int b = 1;
+
+    for (unsigned int i = 1; i < n; i++) {
+        unsigned int next = a + b;
+        a = b;
+        b = next;
+    }
+
+    return b;
+}
+
+void rot13(char *buf)
+{
+    while (*buf) {
+        if ((*buf >= 'a' && *buf <= 'm') ||
+                (*buf >= 'A' && *buf <= 'M')) {
+            *buf += 13;
+        } else if ((*buf >= 'n' && *buf <= 'z') ||
+                (*buf >= 'N' && *buf <= 'Z')) {
+            *buf -= 13;
+        }
+        buf++;
+    }
+}
+
+size_t strlen(const char *buf)
+{
+    int len = 0;
+    while (buf[len])
+        len++;
+    return len;
+}
+
+extern void *__malloc_freelist;
+
+int main()
+{
+    __malloc_freelist = 0;
+
+    volatile int i = 0;
+    int j = 0;
+    char fox[] = "The quick brown fox jumps of the lazy dog.";
+    unsigned int checksum = 0;
+
+start:
+    while (i)
+        j++;
+
+    rot13(fox);
+    checksum ^= crc32a(fox, strlen(fox));
+    rot13(fox);
+    checksum ^= crc32a(fox, strlen(fox));
+
+    return checksum;
+}
diff --git a/apps/riscv-tests/debug/programs/encoding.h b/apps/riscv-tests/debug/programs/encoding.h
new file mode 120000
index 0000000..56fa44a
--- /dev/null
+++ b/apps/riscv-tests/debug/programs/encoding.h
@@ -0,0 +1 @@
+../../env/encoding.h
\ No newline at end of file
diff --git a/apps/riscv-tests/debug/programs/entry.S b/apps/riscv-tests/debug/programs/entry.S
new file mode 100755
index 0000000..3796b3b
--- /dev/null
+++ b/apps/riscv-tests/debug/programs/entry.S
@@ -0,0 +1,207 @@
+#include "encoding.h"
+
+#define STACK_SIZE (90 * XLEN / 8)
+
+#if XLEN == 64
+# define LREG ld
+# define SREG sd
+# define REGBYTES 8
+#else
+# define LREG lw
+# define SREG sw
+# define REGBYTES 4
+#endif
+
+  .section      .text.entry
+  .globl _start
+_start:
+  j handle_reset
+
+nmi_vector:
+  j nmi_vector
+
+trap_vector:
+  j trap_entry
+
+handle_reset:
+  // If misa doesn't exist (or is following an old spec where it has a
+  // different number), skip the next block.
+  la t0, 3f
+  csrw mtvec, t0
+  csrwi mstatus, 0
+
+  // make sure these registers exist by seeing if either S or U bits
+  // are set before attempting to zero them out.
+  csrr   t1, misa
+  addi   t2, x0, 1 	
+  slli   t2, t2, 20 // U_EXTENSION
+  and    t2, t1, t2
+  bne    x0, t2, 1f
+  addi   t2, x0, 1
+  slli   t2, t2, 18 // S_EXTENSION	
+  and    t2, t1, t2
+  bne    x0, t2, 1f
+  j 2f
+1:
+  csrwi mideleg, 0
+  csrwi medeleg, 0
+2:
+  csrwi mie, 0
+3:
+  la t0, trap_entry
+  csrw mtvec, t0
+  csrwi mstatus, 0
+
+  # initialize global pointer
+.option push
+.option norelax
+  la gp, __global_pointer$
+.option pop
+
+  # Initialize stack pointer.
+  la    sp, stack_bottom
+  # Give each hart STACK_SIZE of stack.
+  # Assume hart IDs are contiguous and start at 0.
+  li    t1, STACK_SIZE
+  csrr  t0, CSR_MHARTID
+  # Don't use mul instruction because not all harts support it.
+  addi  t0, t0, 1
+1:
+  add   sp, sp, t1
+  addi  t0, t0, -1
+  bnez  t0, 1b
+
+  # Clear all hardware triggers
+  li    t0, ~0
+1:
+  addi  t0, t0, 1
+  csrw  CSR_TSELECT, t0
+  csrw  CSR_TDATA1, zero
+  csrr  t1, CSR_TSELECT
+  beq   t0, t1, 1b
+
+#ifdef MULTICORE
+  csrr  t0, CSR_MHARTID
+  bnez  t0, wait_until_initialized
+#endif
+
+  la    t0, __bss_start
+  la    t1, __bss_end
+1:
+  bge   t0, t1, 2f
+  sb    zero, 0(t0)
+  addi  t0, t0, 1
+  j     1b
+2:
+#ifdef MULTICORE
+  la    t0, initialized
+  li    t1, 1
+  sw    t1, 0(t0)
+
+wait_until_initialized:      # Wait for hart 0 to perform initialization.
+  la    t0, initialized
+1:
+  lw    t1, 0(t0)
+  beqz  t1, 1b
+#endif
+
+  # perform the rest of initialization in C
+  j     _init
+
+
+.align 2
+trap_entry:
+  addi sp, sp, -32*REGBYTES
+
+  SREG x1, 1*REGBYTES(sp)
+  SREG x2, 2*REGBYTES(sp)
+  SREG x3, 3*REGBYTES(sp)
+  SREG x4, 4*REGBYTES(sp)
+  SREG x5, 5*REGBYTES(sp)
+  SREG x6, 6*REGBYTES(sp)
+  SREG x7, 7*REGBYTES(sp)
+  SREG x8, 8*REGBYTES(sp)
+  SREG x9, 9*REGBYTES(sp)
+  SREG x10, 10*REGBYTES(sp)
+  SREG x11, 11*REGBYTES(sp)
+  SREG x12, 12*REGBYTES(sp)
+  SREG x13, 13*REGBYTES(sp)
+  SREG x14, 14*REGBYTES(sp)
+  SREG x15, 15*REGBYTES(sp)
+#ifndef RV32E
+  SREG x16, 16*REGBYTES(sp)
+  SREG x17, 17*REGBYTES(sp)
+  SREG x18, 18*REGBYTES(sp)
+  SREG x19, 19*REGBYTES(sp)
+  SREG x20, 20*REGBYTES(sp)
+  SREG x21, 21*REGBYTES(sp)
+  SREG x22, 22*REGBYTES(sp)
+  SREG x23, 23*REGBYTES(sp)
+  SREG x24, 24*REGBYTES(sp)
+  SREG x25, 25*REGBYTES(sp)
+  SREG x26, 26*REGBYTES(sp)
+  SREG x27, 27*REGBYTES(sp)
+  SREG x28, 28*REGBYTES(sp)
+  SREG x29, 29*REGBYTES(sp)
+  SREG x30, 30*REGBYTES(sp)
+  SREG x31, 31*REGBYTES(sp)
+#endif
+
+  csrr a0, mcause
+  csrr a1, mepc
+  mv a2, sp
+  jal handle_trap
+  csrw mepc, a0
+
+  # Remain in M-mode after mret
+  li t0, MSTATUS_MPP
+  csrs mstatus, t0
+
+  LREG x1, 1*REGBYTES(sp)
+  LREG x2, 2*REGBYTES(sp)
+  LREG x3, 3*REGBYTES(sp)
+  LREG x4, 4*REGBYTES(sp)
+  LREG x5, 5*REGBYTES(sp)
+  LREG x6, 6*REGBYTES(sp)
+  LREG x7, 7*REGBYTES(sp)
+  LREG x8, 8*REGBYTES(sp)
+  LREG x9, 9*REGBYTES(sp)
+  LREG x10, 10*REGBYTES(sp)
+  LREG x11, 11*REGBYTES(sp)
+  LREG x12, 12*REGBYTES(sp)
+  LREG x13, 13*REGBYTES(sp)
+  LREG x14, 14*REGBYTES(sp)
+  LREG x15, 15*REGBYTES(sp)
+#ifndef RV32E
+  LREG x16, 16*REGBYTES(sp)
+  LREG x17, 17*REGBYTES(sp)
+  LREG x18, 18*REGBYTES(sp)
+  LREG x19, 19*REGBYTES(sp)
+  LREG x20, 20*REGBYTES(sp)
+  LREG x21, 21*REGBYTES(sp)
+  LREG x22, 22*REGBYTES(sp)
+  LREG x23, 23*REGBYTES(sp)
+  LREG x24, 24*REGBYTES(sp)
+  LREG x25, 25*REGBYTES(sp)
+  LREG x26, 26*REGBYTES(sp)
+  LREG x27, 27*REGBYTES(sp)
+  LREG x28, 28*REGBYTES(sp)
+  LREG x29, 29*REGBYTES(sp)
+  LREG x30, 30*REGBYTES(sp)
+  LREG x31, 31*REGBYTES(sp)
+#endif
+
+  addi sp, sp, 32*REGBYTES
+  mret
+
+loop_forever:
+  j loop_forever
+
+  // Fill the stack with data so we can see if it was overrun.
+  .section .data
+  .align 4
+stack_bottom:
+  .fill NHARTS * STACK_SIZE/4, 4, 0x22446688
+stack_top:
+initialized:
+  .word 0
diff --git a/apps/riscv-tests/debug/programs/infinite_loop.S b/apps/riscv-tests/debug/programs/infinite_loop.S
new file mode 100644
index 0000000..5cc377c
--- /dev/null
+++ b/apps/riscv-tests/debug/programs/infinite_loop.S
@@ -0,0 +1,44 @@
+#include "encoding.h"
+
+        .global main
+        .global main_end
+        .global main_post_csrr
+
+        // Load constants into all registers so we can test no register are
+        // clobbered after attaching.
+main:
+        csrr    x1, CSR_MHARTID
+        slli    x1, x1, 8
+main_post_csrr:
+        addi    x2, x1, 1
+        addi    x3, x2, 1
+        addi    x4, x3, 1
+        addi    x5, x4, 1
+        addi    x6, x5, 1
+        addi    x7, x6, 1
+        addi    x8, x7, 1
+        addi    x9, x8, 1
+        addi    x10, x9, 1
+        addi    x11, x10, 1
+        addi    x12, x11, 1
+        addi    x13, x12, 1
+        addi    x14, x13, 1
+        addi    x15, x14, 1
+        addi    x16, x15, 1
+        addi    x17, x16, 1
+        addi    x18, x17, 1
+        addi    x19, x18, 1
+        addi    x20, x19, 1
+        addi    x21, x20, 1
+        addi    x22, x21, 1
+        addi    x23, x22, 1
+        addi    x24, x23, 1
+        addi    x25, x24, 1
+        addi    x26, x25, 1
+        addi    x27, x26, 1
+        addi    x28, x27, 1
+        addi    x29, x28, 1
+        addi    x30, x29, 1
+        addi    x31, x30, 1
+main_end:
+        j       main
diff --git a/apps/riscv-tests/debug/programs/init.c b/apps/riscv-tests/debug/programs/init.c
new file mode 100644
index 0000000..e3efc8e
--- /dev/null
+++ b/apps/riscv-tests/debug/programs/init.c
@@ -0,0 +1,47 @@
+#include "init.h"
+#include "encoding.h"
+
+int main(void);
+
+trap_handler_t trap_handler[NHARTS] = {0};
+
+void set_trap_handler(trap_handler_t handler)
+{
+    unsigned hartid = read_csr(mhartid);
+    trap_handler[hartid] = handler;
+}
+
+void enable_timer_interrupts()
+{
+    set_csr(mie, MIP_MTIP);
+    set_csr(mstatus, MSTATUS_MIE);
+}
+
+void handle_trap(unsigned int mcause, void *mepc, void *sp)
+{
+    unsigned hartid = read_csr(mhartid);
+    if (trap_handler[hartid]) {
+        trap_handler[hartid](hartid, mcause, mepc, sp);
+        return;
+    }
+
+    while (1)
+        ;
+}
+
+void _exit(int status)
+{
+    // Make sure gcc doesn't inline _exit, so we can actually set a breakpoint
+    // on it.
+    volatile int i = 42;
+    while (i)
+        ;
+    // _exit isn't supposed to return.
+    while (1)
+        ;
+}
+
+void _init()
+{
+    _exit(main());
+}
diff --git a/apps/riscv-tests/debug/programs/init.h b/apps/riscv-tests/debug/programs/init.h
new file mode 100644
index 0000000..06d5384
--- /dev/null
+++ b/apps/riscv-tests/debug/programs/init.h
@@ -0,0 +1,12 @@
+#ifndef INIT_H
+#define INIT_H
+
+#define MTIME           (*(volatile long long *)(0x02000000 + 0xbff8))
+#define MTIMECMP        ((volatile long long *)(0x02000000 + 0x4000))
+
+typedef void* (*trap_handler_t)(unsigned hartid, unsigned mcause, void *mepc,
+        void *sp);
+void set_trap_handler(trap_handler_t handler);
+void enable_timer_interrupts();
+
+#endif
diff --git a/apps/riscv-tests/debug/programs/interrupt.c b/apps/riscv-tests/debug/programs/interrupt.c
new file mode 100644
index 0000000..8378576
--- /dev/null
+++ b/apps/riscv-tests/debug/programs/interrupt.c
@@ -0,0 +1,32 @@
+#include "init.h"
+#include "encoding.h"
+
+static volatile unsigned interrupt_count;
+static volatile unsigned local;
+
+static unsigned delta = 0x100;
+void *increment_count(unsigned hartid, unsigned mcause, void *mepc, void *sp)
+{
+    interrupt_count++;
+    // There is no guarantee that the interrupt is cleared immediately when
+    // MTIMECMP is written, so stick around here until that happens.
+    while (read_csr(mip) & MIP_MTIP) {
+        MTIMECMP[hartid] = MTIME + delta;
+    }
+    return mepc;
+}
+
+int main()
+{
+    interrupt_count = 0;
+    local = 0;
+    unsigned hartid = read_csr(mhartid);
+
+    set_trap_handler(increment_count);
+    MTIMECMP[hartid] = MTIME - 1;
+    enable_timer_interrupts();
+
+    while (1) {
+        local++;
+    }
+}
diff --git a/apps/riscv-tests/debug/programs/mprv.S b/apps/riscv-tests/debug/programs/mprv.S
new file mode 100644
index 0000000..8ec261e
--- /dev/null
+++ b/apps/riscv-tests/debug/programs/mprv.S
@@ -0,0 +1,46 @@
+#include "encoding.h"
+#define PGSHIFT         12
+
+        .global         main
+
+        .section        .text
+main:
+        # Set up a page table entry that maps 0x0... to 0x8...
+        la      t0, page_table
+        srli    t0, t0, PGSHIFT
+        csrw    CSR_SATP, t0
+
+        # update mstatus
+        csrr    t1, CSR_MSTATUS
+#if XLEN == 32
+        li      t0, (MSTATUS_MPRV | (SATP_MODE_SV32 << 24))
+#else
+        li      t0, (MSTATUS_MPRV | (SATP_MODE_SV39 << 24))
+#endif
+        #li      t0, ((VM_SV39 << 24))
+        or      t1, t0, t1
+        csrw    CSR_MSTATUS, t1
+
+        la      t0, (loop - 0x80000000)
+        csrw    CSR_MEPC, t0
+
+        # Exit supervisor mode, entering user mode at loop.
+        mret
+
+loop:
+        la      t0, data
+        lw      t1, 0(t0)
+        j       loop
+
+        .section        .data
+data:
+        .word   0xbead
+
+        .balign 0x1000
+page_table:
+#if XLEN == 32
+        .word   ((0x80000000 >> 2) | PTE_V | PTE_R | PTE_W | PTE_X | PTE_G | PTE_U)
+#else
+        .word   ((0x80000000 >> 2) | PTE_V | PTE_R | PTE_W | PTE_X | PTE_G | PTE_U)
+        .word   0
+#endif
diff --git a/apps/riscv-tests/debug/programs/multicore.c b/apps/riscv-tests/debug/programs/multicore.c
new file mode 100644
index 0000000..a51ee4a
--- /dev/null
+++ b/apps/riscv-tests/debug/programs/multicore.c
@@ -0,0 +1,89 @@
+#include <stdint.h>
+
+#include "init.h"
+#include "encoding.h"
+
+typedef struct {
+    int counter;
+} atomic_t;
+
+static inline int atomic_xchg(atomic_t *v, int n)
+{
+    register int c;
+
+    __asm__ __volatile__ (
+            "amoswap.w.aqrl %0, %2, %1"
+            : "=r" (c), "+A" (v->counter)
+            : "r" (n));
+    return c;
+}
+
+static inline void mb(void)
+{
+    __asm__ __volatile__ ("fence");
+}
+
+void get_lock(atomic_t *lock)
+{
+    while (atomic_xchg(lock, 1) == 1)
+        ;
+    mb();
+}
+
+void put_lock(atomic_t *lock)
+{
+    mb();
+    atomic_xchg(lock, 0);
+}
+
+static atomic_t buf_lock = { .counter = 0 };
+static char buf[32];
+static int buf_initialized;
+static unsigned hart_count[NHARTS];
+static unsigned interrupt_count[NHARTS];
+
+static unsigned delta = 0x100;
+void *increment_count(unsigned hartid, unsigned mcause, void *mepc, void *sp)
+{
+    interrupt_count[hartid]++;
+    MTIMECMP[hartid] = MTIME + delta;
+    return mepc;
+}
+
+int main()
+{
+    uint32_t hartid = read_csr(mhartid);
+    hart_count[hartid] = 0;
+    interrupt_count[hartid] = 0;
+
+    set_trap_handler(increment_count);
+    // Despite being memory-mapped, there appears to be one mtimecmp
+    // register per hart. The spec does not address this.
+    MTIMECMP[hartid] = MTIME + delta;
+    enable_timer_interrupts();
+
+    while (1) {
+        get_lock(&buf_lock);
+
+        if (!buf_initialized) {
+            for (unsigned i = 0; i < sizeof(buf); i++) {
+                buf[i] = 'A' + (i % 26);
+            }
+            buf_initialized = 1;
+        }
+
+        char first = buf[0];
+        int offset = (first & ~0x20) - 'A';
+        for (unsigned i = 0; i < sizeof(buf); i++) {
+            while (buf[i] != (first - offset + ((offset + i) % 26)))
+                ;
+
+            if (hartid & 1)
+                buf[i] = 'A' + ((i + hartid + hart_count[hartid]) % 26);
+            else
+                buf[i] = 'a' + ((i + hartid + hart_count[hartid]) % 26);
+        }
+        put_lock(&buf_lock);
+        hart_count[hartid]++;
+    }
+}
diff --git a/apps/riscv-tests/debug/programs/priv.S b/apps/riscv-tests/debug/programs/priv.S
new file mode 100644
index 0000000..75481be
--- /dev/null
+++ b/apps/riscv-tests/debug/programs/priv.S
@@ -0,0 +1,11 @@
+#include "encoding.h"
+
+        .global         main
+
+        .section        .text
+main:
+        # MISA is only readable from machine mode
+        csrr    t0, CSR_MISA
+        csrr    t0, CSR_MISA
+        csrr    t0, CSR_MISA
+        csrr    t0, CSR_MISA
diff --git a/apps/riscv-tests/debug/programs/regs.S b/apps/riscv-tests/debug/programs/regs.S
new file mode 100644
index 0000000..cfa1179
--- /dev/null
+++ b/apps/riscv-tests/debug/programs/regs.S
@@ -0,0 +1,60 @@
+#if XLEN == 64
+# define LREG ld
+# define SREG sd
+# define REGBYTES 8
+#else
+# define LREG lw
+# define SREG sw
+# define REGBYTES 4
+#endif
+
+#include "encoding.h"
+
+        .global main
+main:
+        nop
+        j       main
+
+write_regs:
+        SREG    x2, 0(x1)
+        SREG    x3, 8(x1)
+        SREG    x4, 16(x1)
+        SREG    x5, 24(x1)
+        SREG    x6, 32(x1)
+        SREG    x7, 40(x1)
+        SREG    x8, 48(x1)
+        SREG    x9, 56(x1)
+        SREG    x10, 64(x1)
+        SREG    x11, 72(x1)
+        SREG    x12, 80(x1)
+        SREG    x13, 88(x1)
+        SREG    x14, 96(x1)
+        SREG    x15, 104(x1)
+#ifndef RV32E
+        SREG    x16, 112(x1)
+        SREG    x17, 120(x1)
+        SREG    x18, 128(x1)
+        SREG    x19, 136(x1)
+        SREG    x20, 144(x1)
+        SREG    x21, 152(x1)
+        SREG    x22, 160(x1)
+        SREG    x23, 168(x1)
+        SREG    x24, 176(x1)
+        SREG    x25, 184(x1)
+        SREG    x26, 192(x1)
+        SREG    x27, 200(x1)
+        SREG    x28, 208(x1)
+        SREG    x29, 216(x1)
+        SREG    x30, 224(x1)
+        SREG    x31, 232(x1)
+#endif
+
+        csrr    x1, CSR_MSCRATCH
+
+all_done:
+        j       all_done
+
+        .section .bss
+        .balign  16
+data:
+        .fill   64, 8, 0
diff --git a/apps/riscv-tests/debug/programs/run_halt_timing.S b/apps/riscv-tests/debug/programs/run_halt_timing.S
new file mode 100644
index 0000000..ce4000a
--- /dev/null
+++ b/apps/riscv-tests/debug/programs/run_halt_timing.S
@@ -0,0 +1,18 @@
+#if XLEN == 64
+# define LREG ld
+# define SREG sd
+# define REGBYTES 8
+#else
+# define LREG lw
+# define SREG sw
+# define REGBYTES 4
+#endif
+
+        .global main
+main:
+        li      s0, 0
+        li      s1, 0x0200bff8
+loop:
+        addi    s0, s0, 1
+        LREG    s2, 0(s1)
+        j       loop
diff --git a/apps/riscv-tests/debug/programs/semihosting.c b/apps/riscv-tests/debug/programs/semihosting.c
new file mode 100644
index 0000000..2ceea8c
--- /dev/null
+++ b/apps/riscv-tests/debug/programs/semihosting.c
@@ -0,0 +1,73 @@
+#include <stdint.h>
+
+#include "semihosting.h"
+
+size_t strlen(const char *buf)
+{
+    int len = 0;
+    while (buf[len])
+        len++;
+    return len;
+}
+
+#define O_RDONLY         0
+#define O_WRONLY         1
+#define O_RDWR           2
+#define O_RDWR           2
+#define O_TRUNC		0x0800
+
+int errno;
+
+/* These semihosting functions came from the Freedom Metal source. */
+static int open(const char *name, int flags, int mode) {
+    int semiflags = 0;
+
+    switch (flags & (O_RDONLY | O_WRONLY | O_RDWR)) {
+    case O_RDONLY:
+        semiflags = 0; /* 'r' */
+        break;
+    case O_WRONLY:
+        if (flags & O_TRUNC)
+            semiflags = 4; /* 'w' */
+        else
+            semiflags = 8; /* 'a' */
+        break;
+    default:
+        if (flags & O_TRUNC)
+            semiflags = 6; /* 'w+' */
+        else
+            semiflags = 10; /* 'a+' */
+        break;
+    }
+
+    volatile semihostparam_t arg = {.param1 = (uintptr_t)name,
+                                    .param2 = (uintptr_t)semiflags,
+                                    .param3 = (uintptr_t)strlen(name)};
+
+    int ret = (int)semihost_call_host(SEMIHOST_SYS_OPEN, (uintptr_t)&arg);
+    if (ret == -1)
+        errno = semihost_call_host(SEMIHOST_SYS_ERRNO, 0);
+    return ret;
+}
+
+static ssize_t write(int file, const void *ptr, size_t len)
+{
+    volatile semihostparam_t arg = {.param1 = (uintptr_t)file,
+                                    .param2 = (uintptr_t)ptr,
+                                    .param3 = (uintptr_t)len};
+    ssize_t ret =
+        (ssize_t)semihost_call_host(SEMIHOST_SYS_WRITE, (uintptr_t)&arg);
+
+    return (len - ret);
+}
+
+int main()
+{
+    char *filename = NULL;
+    const char *message = "Hello, world!\n";
+    int fd;
+
+begin:
+    fd = open(filename, O_WRONLY, 0644);
+    write(fd, message, strlen(message));
+}
\ No newline at end of file
diff --git a/apps/riscv-tests/debug/programs/semihosting.h b/apps/riscv-tests/debug/programs/semihosting.h
new file mode 100644
index 0000000..201e414
--- /dev/null
+++ b/apps/riscv-tests/debug/programs/semihosting.h
@@ -0,0 +1,82 @@
+#include <sys/types.h>
+
+#ifndef _SEMIHOSTING_H_
+#define _SEMIHOSTING_H_
+
+// ----------------------------------------------------------------------------
+
+// Semihosting operations.
+enum Semihost_Sys_Op {
+    // Regular operations
+    SEMIHOST_SYS_CLOCK = 0x10,
+    SEMIHOST_SYS_CLOSE = 0x02,
+    SEMIHOST_SYS_ELAPSED = 0x30,
+    SEMIHOST_SYS_ERRNO = 0x13,
+    SEMIHOST_SYS_EXIT = 0x18,
+    SEMIHOST_SYS_EXIT_EXTENDED = 0x20,
+    SEMIHOST_SYS_FLEN = 0x0C,
+    SEMIHOST_SYS_GET_CMDLINE = 0x15,
+    SEMIHOST_SYS_HEAPINFO = 0x16,
+    SEMIHOST_SYS_ISERROR = 0x08,
+    SEMIHOST_SYS_ISTTY = 0x09,
+    SEMIHOST_SYS_OPEN = 0x01,
+    SEMIHOST_SYS_READ = 0x06,
+    SEMIHOST_SYS_READC = 0x07,
+    SEMIHOST_SYS_REMOVE = 0x0E,
+    SEMIHOST_SYS_RENAME = 0x0F,
+    SEMIHOST_SYS_SEEK = 0x0A,
+    SEMIHOST_SYS_SYSTEM = 0x12,
+    SEMIHOST_SYS_TICKFREQ = 0x31,
+    SEMIHOST_SYS_TIME = 0x11,
+    SEMIHOST_SYS_TMPNAM = 0x0D,
+    SEMIHOST_SYS_WRITE = 0x05,
+    SEMIHOST_SYS_WRITEC = 0x03,
+    SEMIHOST_SYS_WRITE0 = 0x04,
+};
+
+enum ADP_Code {
+    ADP_Stopped_BranchThroughZero = 0x20000,
+    ADP_Stopped_UndefinedInstr = 0x20001,
+    ADP_Stopped_SoftwareInterrupt = 0x20002,
+    ADP_Stopped_PrefetchAbort = 0x20003,
+    ADP_Stopped_DataAbort = 0x20004,
+    ADP_Stopped_AddressException = 0x20005,
+    ADP_Stopped_IRQ = 0x20006,
+    ADP_Stopped_FIQ = 0x20007,
+    ADP_Stopped_BreakPoint = 0x20020,
+    ADP_Stopped_WatchPoint = 0x20021,
+    ADP_Stopped_StepComplete = 0x20022,
+    ADP_Stopped_RunTimeErrorUnknown = 0x20023,
+    ADP_Stopped_InternalError = 0x20024,
+    ADP_Stopped_UserInterruption = 0x20025,
+    ADP_Stopped_ApplicationExit = 0x20026,
+    ADP_Stopped_StackOverflow = 0x20027,
+    ADP_Stopped_DivisionByZero = 0x20028,
+    ADP_Stopped_OSSpecific = 0x20029,
+};
+
+typedef struct {
+    uintptr_t param1;
+    uintptr_t param2;
+    uintptr_t param3;
+} semihostparam_t;
+
+static inline uintptr_t __attribute__((always_inline))
+semihost_call_host(uintptr_t op, uintptr_t arg) {
+    register uintptr_t r0 asm("a0") = op;
+    register uintptr_t r1 asm("a1") = arg;
+
+    asm volatile(".option push               \n"
+                 ".option norvc              \n"
+                 " slli    zero,zero,0x1f    \n"
+                 " ebreak                    \n"
+                 " srai    zero,zero,0x7     \n"
+                 ".option pop                \n"
+
+                 : "=r"(r0)         /* Outputs */
+                 : "r"(r0), "r"(r1) /* Inputs */
+                 : "memory");
+    return r0;
+}
+
+#endif
\ No newline at end of file
diff --git a/apps/riscv-tests/debug/programs/step.S b/apps/riscv-tests/debug/programs/step.S
new file mode 100644
index 0000000..3e7b42e
--- /dev/null
+++ b/apps/riscv-tests/debug/programs/step.S
@@ -0,0 +1,28 @@
+// Test stepping over a variety of instructions.
+
+        .global main
+
+main:
+        la      t0, trap_entry          // 0, 4
+        csrw    mtvec, t0               // 0x8
+
+        li      t0, 5                   // 0xc
+        beq     zero, zero, one         // 0x10
+        nop                             // 0x14
+one:
+        beq     zero, t0, one           // 0x18
+        // Use t0 instead of ra to force a 32-bit opcode in C mode. Otherwise
+        // 32-bit and 64-bit binaries end up with different instructions (I
+        // didn't pursue this).
+        jal     t0, two                 // 0x1c
+
+three:
+        .word   0                       // 0x20
+        nop                             // 0x24
+
+two:
+        jr      t0                      // 0x28
+
+        .align  2
+trap_entry:
+        j       trap_entry              // 0x2c
diff --git a/apps/riscv-tests/debug/programs/tiny-malloc.c b/apps/riscv-tests/debug/programs/tiny-malloc.c
new file mode 100644
index 0000000..699660c
--- /dev/null
+++ b/apps/riscv-tests/debug/programs/tiny-malloc.c
@@ -0,0 +1,600 @@
+// https://github.com/32bitmicro/newlib-nano-1.0/blob/master/newlib/libc/machine/xstormy16/tiny-malloc.c
+
+/* A replacement malloc with:
+   - Much reduced code size;
+   - Smaller RAM footprint;
+   - The ability to handle downward-growing heaps;
+   but
+   - Slower;
+   - Probably higher memory fragmentation;
+   - Doesn't support threads (but, if it did support threads,
+     it wouldn't need a global lock, only a compare-and-swap instruction);
+   - Assumes the maximum alignment required is the alignment of a pointer;
+   - Assumes that memory is already there and doesn't need to be allocated.
+
+* Synopsis of public routines
+
+  malloc(size_t n);
+     Return a pointer to a newly allocated chunk of at least n bytes, or null
+     if no space is available.
+  free(void* p);
+     Release the chunk of memory pointed to by p, or no effect if p is null.
+  realloc(void* p, size_t n);
+     Return a pointer to a chunk of size n that contains the same data
+     as does chunk p up to the minimum of (n, p's size) bytes, or null
+     if no space is available. The returned pointer may or may not be
+     the same as p. If p is null, equivalent to malloc.  Unless the
+     #define REALLOC_ZERO_BYTES_FREES below is set, realloc with a
+     size argument of zero (re)allocates a minimum-sized chunk.
+  memalign(size_t alignment, size_t n);
+     Return a pointer to a newly allocated chunk of n bytes, aligned
+     in accord with the alignment argument, which must be a power of
+     two.  Will fail if 'alignment' is too large.
+  calloc(size_t unit, size_t quantity);
+     Returns a pointer to quantity * unit bytes, with all locations
+     set to zero.
+  cfree(void* p);
+     Equivalent to free(p).
+  malloc_trim(size_t pad);
+     Release all but pad bytes of freed top-most memory back 
+     to the system. Return 1 if successful, else 0.
+  malloc_usable_size(void* p);
+     Report the number usable allocated bytes associated with allocated
+     chunk p. This may or may not report more bytes than were requested,
+     due to alignment and minimum size constraints.
+  malloc_stats();
+     Prints brief summary statistics on stderr.
+  mallinfo()
+     Returns (by copy) a struct containing various summary statistics.
+  mallopt(int parameter_number, int parameter_value)
+     Changes one of the tunable parameters described below. Returns
+     1 if successful in changing the parameter, else 0.  Actually, returns 0
+     always, as no parameter can be changed.
+*/
+
+#ifdef __xstormy16__
+#define MALLOC_DIRECTION -1
+#endif
+
+#ifndef MALLOC_DIRECTION
+#define MALLOC_DIRECTION 1
+#endif
+
+#include <stddef.h>
+
+void* malloc(size_t);
+void    free(void*);
+void* realloc(void*, size_t);
+void* memalign(size_t, size_t);
+void* valloc(size_t);
+void* pvalloc(size_t);
+void* calloc(size_t, size_t);
+void    cfree(void*);
+int     malloc_trim(size_t);
+size_t  malloc_usable_size(void*);
+void    malloc_stats(void);
+int     mallopt(int, int);
+struct mallinfo mallinfo(void);
+
+typedef struct freelist_entry {
+  size_t size;
+  struct freelist_entry *next;
+} *fle;
+
+extern void * __malloc_end;
+extern fle __malloc_freelist;
+
+/* Return the number of bytes that need to be added to X to make it
+   aligned to an ALIGN boundary.  ALIGN must be a power of 2.  */
+#define M_ALIGN(x, align) (-(size_t)(x) & ((align) - 1))
+
+/* Return the number of bytes that need to be subtracted from X to make it
+   aligned to an ALIGN boundary.  ALIGN must be a power of 2.  */
+#define M_ALIGN_SUB(x, align) ((size_t)(x) & ((align) - 1))
+
+extern char *__malloc_start;
+
+/* This is the minimum gap allowed between __malloc_end and the top of
+   the stack.  This is only checked for when __malloc_end is
+   decreased; if instead the stack grows into the heap, silent data
+   corruption will result.  */
+#define MALLOC_MINIMUM_GAP 32
+
+#ifdef __xstormy16__
+register void * stack_pointer asm ("r15");
+#define MALLOC_LIMIT stack_pointer
+#else
+#define MALLOC_LIMIT __builtin_frame_address (0)
+#endif
+
+#if MALLOC_DIRECTION < 0
+#define CAN_ALLOC_P(required)				\
+  (((size_t) __malloc_end - (size_t)MALLOC_LIMIT	\
+    - MALLOC_MINIMUM_GAP) >= (required))
+#else
+#define CAN_ALLOC_P(required)				\
+  (((size_t)MALLOC_LIMIT - (size_t) __malloc_end	\
+    - MALLOC_MINIMUM_GAP) >= (required))
+#endif
+
+/* real_size is the size we actually have to allocate, allowing for
+   overhead and alignment.  */
+#define REAL_SIZE(sz)						\
+  ((sz) < sizeof (struct freelist_entry) - sizeof (size_t)	\
+   ? sizeof (struct freelist_entry)				\
+   : sz + sizeof (size_t) + M_ALIGN(sz, sizeof (size_t)))
+
+#ifdef DEFINE_MALLOC
+
+void * __malloc_end = &__malloc_start;
+fle __malloc_freelist;
+
+void *
+malloc (size_t sz)
+{
+  fle *nextfree;
+  fle block;
+
+  /* real_size is the size we actually have to allocate, allowing for
+     overhead and alignment.  */
+  size_t real_size = REAL_SIZE (sz);
+
+  /* Look for the first block on the freelist that is large enough.  */
+  for (nextfree = &__malloc_freelist; 
+       *nextfree; 
+       nextfree = &(*nextfree)->next)  
+    {
+      block = *nextfree;
+      
+      if (block->size >= real_size)
+	{
+	  /* If the block found is just the right size, remove it from
+	     the free list.  Otherwise, split it.  */
+	  if (block->size < real_size + sizeof (struct freelist_entry))
+	    {
+	      *nextfree = block->next;
+	      return (void *)&block->next;
+	    }
+	  else
+	    {
+	      size_t newsize = block->size - real_size;
+	      fle newnext = block->next;
+	      *nextfree = (fle)((size_t)block + real_size);
+	      (*nextfree)->size = newsize;
+	      (*nextfree)->next = newnext;
+	      goto done;
+	    }
+	}
+
+      /* If this is the last block on the freelist, and it was too small,
+	 enlarge it.  */
+      if (! block->next
+	  && __malloc_end == (void *)((size_t)block + block->size))
+	{
+	  size_t moresize = real_size - block->size;
+	  if (! CAN_ALLOC_P (moresize))
+	    return NULL;
+	  
+	  *nextfree = NULL;
+	  if (MALLOC_DIRECTION < 0)
+	    {
+	      block = __malloc_end = (void *)((size_t)block - moresize);
+	    }
+	  else
+	    {
+	      __malloc_end = (void *)((size_t)block + real_size);
+	    }
+
+	  goto done;
+	}
+    }
+
+  /* No free space at the end of the free list.  Allocate new space
+     and use that.  */
+
+  if (! CAN_ALLOC_P (real_size))
+    return NULL;
+
+  if (MALLOC_DIRECTION > 0)
+    {
+      block = __malloc_end;
+      __malloc_end = (void *)((size_t)__malloc_end + real_size);
+    }
+  else
+    {
+      block = __malloc_end = (void *)((size_t)__malloc_end - real_size);
+    }
+ done:
+  block->size = real_size;
+  return (void *)&block->next;
+}
+
+#endif
+
+#ifdef DEFINE_FREE
+
+void
+free (void *block_p)
+{
+  fle *nextfree;
+  fle block = (fle)((size_t) block_p - offsetof (struct freelist_entry, next));
+
+  if (block_p == NULL)
+    return;
+  
+  /* Look on the freelist to see if there's a free block just before
+     or just after this block.  */
+  for (nextfree = &__malloc_freelist; 
+       *nextfree; 
+       nextfree = &(*nextfree)->next)
+    {
+      fle thisblock = *nextfree;
+      if ((size_t)thisblock + thisblock->size == (size_t) block)
+	{
+	  thisblock->size += block->size;
+	  if (MALLOC_DIRECTION > 0
+	      && thisblock->next
+	      && (size_t) block + block->size == (size_t) thisblock->next)
+	    {
+	      thisblock->size += thisblock->next->size;
+	      thisblock->next = thisblock->next->next;
+	    }
+	  return;
+	}
+      else if ((size_t) thisblock == (size_t) block + block->size)
+	{
+	  if (MALLOC_DIRECTION < 0
+	      && thisblock->next
+	      && (size_t) block == ((size_t) thisblock->next 
+				    + thisblock->next->size))
+	    {
+	      *nextfree = thisblock->next;
+	      thisblock->next->size += block->size + thisblock->size;
+	    }
+	  else
+	    {
+	      block->size += thisblock->size;
+	      block->next = thisblock->next;
+	      *nextfree = block;
+	    }
+	  return;
+	}
+      else if ((MALLOC_DIRECTION > 0
+		&& (size_t) thisblock > (size_t) block)
+	       || (MALLOC_DIRECTION < 0
+		   && (size_t) thisblock < (size_t) block))
+	break;
+    }
+
+  block->next = *nextfree;
+  *nextfree = block;
+  return;
+}
+#endif
+
+#ifdef DEFINE_REALLOC
+void *
+realloc (void *block_p, size_t sz)
+{
+  fle block = (fle)((size_t) block_p - offsetof (struct freelist_entry, next));
+  size_t real_size = REAL_SIZE (sz);
+  size_t old_real_size;
+
+  if (block_p == NULL)
+    return malloc (sz);
+
+  old_real_size = block->size;
+
+  /* Perhaps we need to allocate more space.  */
+  if (old_real_size < real_size)
+    {
+      void *result;
+      size_t old_size = old_real_size - sizeof (size_t);
+      
+      /* Need to allocate, copy, and free.  */
+      result = malloc (sz);
+      if (result == NULL)
+	return NULL;
+      memcpy (result, block_p, old_size < sz ? old_size : sz);
+      free (block_p);
+      return result;
+    }
+  /* Perhaps we can free some space.  */
+  if (old_real_size - real_size >= sizeof (struct freelist_entry))
+    {
+      fle newblock = (fle)((size_t)block + real_size);
+      block->size = real_size;
+      newblock->size = old_real_size - real_size;
+      free (&newblock->next);
+    }
+  return block_p;
+}
+#endif
+
+#ifdef DEFINE_CALLOC
+void *
+calloc (size_t n, size_t elem_size)
+{
+  void *result;
+  size_t sz = n * elem_size;
+  result = malloc (sz);
+  if (result != NULL)
+    memset (result, 0, sz);
+  return result;
+}
+#endif
+
+#ifdef DEFINE_CFREE
+void
+cfree (void *p)
+{
+  free (p);
+}
+#endif
+
+#ifdef DEFINE_MEMALIGN
+void *
+memalign (size_t align, size_t sz)
+{
+  fle *nextfree;
+  fle block;
+
+  /* real_size is the size we actually have to allocate, allowing for
+     overhead and alignment.  */
+  size_t real_size = REAL_SIZE (sz);
+
+  /* Some sanity checking on 'align'. */
+  if ((align & (align - 1)) != 0
+      || align <= 0)
+    return NULL;
+
+  /* Look for the first block on the freelist that is large enough.  */
+  /* One tricky part is this: We want the result to be a valid pointer
+     to free.  That means that there has to be room for a size_t
+     before the block.  If there's additional space before the block,
+     it should go on the freelist, or it'll be lost---we could add it
+     to the size of the block before it in memory, but finding the
+     previous block is expensive.  */
+  for (nextfree = &__malloc_freelist; 
+       ; 
+       nextfree = &(*nextfree)->next)  
+    {
+      size_t before_size;
+      size_t old_size;
+
+      /* If we've run out of free blocks, allocate more space.  */
+      if (! *nextfree)
+	{
+	  old_size = real_size;
+	  if (MALLOC_DIRECTION < 0)
+	    {
+	      old_size += M_ALIGN_SUB (((size_t)__malloc_end 
+					- old_size + sizeof (size_t)),
+				       align);
+	      if (! CAN_ALLOC_P (old_size))
+		return NULL;
+	      block = __malloc_end = (void *)((size_t)__malloc_end - old_size);
+	    }
+	  else
+	    {
+	      block = __malloc_end;
+	      old_size += M_ALIGN ((size_t)__malloc_end + sizeof (size_t),
+				   align);
+	      if (! CAN_ALLOC_P (old_size))
+		return NULL;
+	      __malloc_end = (void *)((size_t)__malloc_end + old_size);
+	    }
+	  *nextfree = block;
+	  block->size = old_size;
+	  block->next = NULL;
+	}
+      else
+	{
+	  block = *nextfree;
+	  old_size = block->size;
+	}
+      
+
+      before_size = M_ALIGN (&block->next, align);
+      if (before_size != 0)
+	before_size = sizeof (*block) + M_ALIGN (&(block+1)->next, align);
+
+      /* If this is the last block on the freelist, and it is too small,
+	 enlarge it.  */
+      if (! block->next
+	  && old_size < real_size + before_size
+	  && __malloc_end == (void *)((size_t)block + block->size))
+	{
+	  if (MALLOC_DIRECTION < 0)
+	    {
+	      size_t moresize = real_size - block->size;
+	      moresize += M_ALIGN_SUB ((size_t)&block->next - moresize, align);
+	      if (! CAN_ALLOC_P (moresize))
+		return NULL;
+	      block = __malloc_end = (void *)((size_t)block - moresize);
+	      block->next = NULL;
+	      block->size = old_size = old_size + moresize;
+	      before_size = 0;
+	    }
+	  else
+	    {
+	      if (! CAN_ALLOC_P (before_size + real_size - block->size))
+		return NULL;
+	      __malloc_end = (void *)((size_t)block + before_size + real_size);
+	      block->size = old_size = before_size + real_size;
+	    }
+
+	  /* Two out of the four cases below will now be possible; which
+	     two depends on MALLOC_DIRECTION.  */
+	}
+
+      if (old_size >= real_size + before_size)
+	{
+	  /* This block will do.  If there needs to be space before it, 
+	     split the block.  */
+	  if (before_size != 0)
+	    {
+	      fle old_block = block;
+
+	      old_block->size = before_size;
+	      block = (fle)((size_t)block + before_size);
+	      
+	      /* If there's no space after the block, we're now nearly
+                 done; just make a note of the size required.  
+	         Otherwise, we need to create a new free space block.  */
+	      if (old_size - before_size 
+		  <= real_size + sizeof (struct freelist_entry))
+		{
+		  block->size = old_size - before_size;
+		  return (void *)&block->next;
+		}
+	      else 
+		{
+		  fle new_block;
+		  new_block = (fle)((size_t)block + real_size);
+		  new_block->size = old_size - before_size - real_size;
+		  if (MALLOC_DIRECTION > 0)
+		    {
+		      new_block->next = old_block->next;
+		      old_block->next = new_block;
+		    }
+		  else
+		    {
+		      new_block->next = old_block;
+		      *nextfree = new_block;
+		    }
+		  goto done;
+		}
+	    }
+	  else
+	    {
+	      /* If the block found is just the right size, remove it from
+		 the free list.  Otherwise, split it.  */
+	      if (old_size <= real_size + sizeof (struct freelist_entry))
+		{
+		  *nextfree = block->next;
+		  return (void *)&block->next;
+		}
+	      else
+		{
+		  size_t newsize = old_size - real_size;
+		  fle newnext = block->next;
+		  *nextfree = (fle)((size_t)block + real_size);
+		  (*nextfree)->size = newsize;
+		  (*nextfree)->next = newnext;
+		  goto done;
+		}
+	    }
+	}
+    }
+
+ done:
+  block->size = real_size;
+  return (void *)&block->next;
+}
+#endif
+
+#ifdef DEFINE_VALLOC
+void *
+valloc (size_t sz)
+{
+  return memalign (128, sz);
+}
+#endif
+#ifdef DEFINE_PVALLOC
+void *
+pvalloc (size_t sz)
+{
+  return memalign (128, sz + M_ALIGN (sz, 128));
+}
+#endif
+
+#ifdef DEFINE_MALLINFO
+#include "malloc.h"
+
+struct mallinfo 
+mallinfo (void)
+{
+  struct mallinfo r;
+  fle fr;
+  size_t free_size;
+  size_t total_size;
+  size_t free_blocks;
+
+  memset (&r, 0, sizeof (r));
+
+  free_size = 0;
+  free_blocks = 0;
+  for (fr = __malloc_freelist; fr; fr = fr->next)
+    {
+      free_size += fr->size;
+      free_blocks++;
+      if (! fr->next)
+	{
+	  int atend;
+	  if (MALLOC_DIRECTION > 0)
+	    atend = (void *)((size_t)fr + fr->size) == __malloc_end;
+	  else
+	    atend = (void *)fr == __malloc_end;
+	  if (atend)
+	    r.keepcost = fr->size;
+	}
+    }
+
+  if (MALLOC_DIRECTION > 0)
+    total_size = (char *)__malloc_end - (char *)&__malloc_start;
+  else
+    total_size = (char *)&__malloc_start - (char *)__malloc_end;
+  
+#ifdef DEBUG
+  /* Fixme: should walk through all the in-use blocks and see if
+     they're valid.  */
+#endif
+
+  r.arena = total_size;
+  r.fordblks = free_size;
+  r.uordblks = total_size - free_size;
+  r.ordblks = free_blocks;
+  return r;
+}
+#endif
+
+#ifdef DEFINE_MALLOC_STATS
+#include "malloc.h"
+#include <stdio.h>
+
+void 
+malloc_stats(void)
+{
+  struct mallinfo i;
+  FILE *fp;
+  
+  fp = stderr;
+  i = mallinfo();
+  fprintf (fp, "malloc has reserved %u bytes between %p and %p\n",
+	   i.arena, &__malloc_start, __malloc_end);
+  fprintf (fp, "there are %u bytes free in %u chunks\n",
+	   i.fordblks, i.ordblks);
+  fprintf (fp, "of which %u bytes are at the end of the reserved space\n",
+	   i.keepcost);
+  fprintf (fp, "and %u bytes are in use.\n", i.uordblks);
+}
+#endif
+
+#ifdef DEFINE_MALLOC_USABLE_SIZE
+size_t 
+malloc_usable_size (void *block_p)
+{
+  fle block = (fle)((size_t) block_p - offsetof (struct freelist_entry, next));
+  return block->size - sizeof (size_t);
+}
+#endif
+
+#ifdef DEFINE_MALLOPT
+int
+mallopt (int n, int v)
+{
+  (void)n; (void)v;
+  return 0;
+}
+#endif
diff --git a/apps/riscv-tests/debug/programs/translate.c b/apps/riscv-tests/debug/programs/translate.c
new file mode 100644
index 0000000..c0424bf
--- /dev/null
+++ b/apps/riscv-tests/debug/programs/translate.c
@@ -0,0 +1,188 @@
+#include <stdint.h>
+
+#include "encoding.h"
+
+#define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
+#define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
+
+#if __riscv_xlen == 64
+# define SATP_PPN SATP64_PPN
+typedef uint64_t reg_t;
+#else
+# define SATP_PPN SATP32_PPN
+typedef uint32_t reg_t;
+#endif
+
+static char page_buffer[4096 * 8];
+static char *page_buffer_next = page_buffer;
+
+typedef struct {
+    unsigned mode;
+    unsigned levels;
+    unsigned ppn_width_bits[5];
+    unsigned ppn_offset_bits[5];
+    unsigned entry_width_bytes;
+    unsigned vpn_width_bits;
+    unsigned vaddr_bits;
+} virtual_memory_system_t;
+
+static virtual_memory_system_t sv32 = {
+    .mode = SATP_MODE_SV32,
+    .levels = 2,
+    .ppn_width_bits = {12, 10, 10},
+    .ppn_offset_bits = {0, 12, 22},
+    .entry_width_bytes = 4,
+    .vpn_width_bits = 10,
+    .vaddr_bits = 32
+};
+
+static virtual_memory_system_t sv39 = {
+    .mode = SATP_MODE_SV39,
+    .levels = 3,
+    .ppn_width_bits = {12, 9, 9, 26},
+    .ppn_offset_bits = {0, 12, 21, 30},
+    .entry_width_bytes = 8,
+    .vpn_width_bits = 9,
+    .vaddr_bits = 39
+};
+
+static virtual_memory_system_t sv48 = {
+    .mode = SATP_MODE_SV48,
+    .levels = 4,
+    .ppn_width_bits = {12, 9, 9, 9, 26},
+    .ppn_offset_bits = {0, 12, 21, 30, 39},
+    .entry_width_bytes = 8,
+    .vpn_width_bits = 9,
+    .vaddr_bits = 48
+};
+
+static virtual_memory_system_t *vms;
+
+void error()
+{
+    while (1)
+        ;
+}
+
+void assert(int condition)
+{
+    if (!condition)
+        error();
+}
+
+// Return a 4Kb, aligned, page.
+void *get_page()
+{
+    page_buffer_next = (char *) (((unsigned long) page_buffer_next + 4095) & ~0xfff);
+    while (page_buffer_next + 4096 >= page_buffer + sizeof(page_buffer))
+        ;
+    void *result = page_buffer_next;
+    page_buffer_next += 4096;
+    return result;
+}
+
+reg_t entry(char *table, unsigned index)
+{
+    if (vms->entry_width_bytes == 4)
+        return ((uint32_t *) table)[index];
+    else if (vms->entry_width_bytes == 8)
+        return ((uint64_t *) table)[index];
+    else
+        assert(0);
+}
+
+void entry_set(char *table, unsigned index, uint64_t value)
+{
+    if (vms->entry_width_bytes == 4)
+        ((uint32_t *) table)[index] = value;
+    else if (vms->entry_width_bytes == 8)
+        ((uint64_t *) table)[index] = value;
+    else
+        assert(0);
+}
+
+// Set up 1-to-1 for this entire table.
+void setup_page_table(char *table, unsigned level, uint64_t physical)
+{
+    for (unsigned i = 0; i < (1<<vms->vpn_width_bits); i++) {
+        uint64_t pte = PTE_V | PTE_R | PTE_W | PTE_X | PTE_U | PTE_A | PTE_D;
+        // Add in portion of physical address.
+        pte |= physical & (((1LL<<vms->vpn_width_bits)-1) <<
+                (PTE_PPN_SHIFT + (level+1) * vms->vpn_width_bits));
+        // Add in the index.
+        pte |= ((reg_t) i) << (PTE_PPN_SHIFT + level * vms->vpn_width_bits);
+        entry_set(table, i, pte);
+    }
+}
+
+// Return contents of vpn field for the given virtual address and level.
+unsigned vpn(uint64_t virtual, unsigned level)
+{
+    virtual >>= 12 + vms->vpn_width_bits * level;
+    return virtual & ((1<<vms->vpn_width_bits)-1);
+}
+ 
+// Add an entry to the given table, at the given level (0 for 4Kb page).
+void add_entry(char *table, unsigned level, uint64_t virtual, uint64_t physical)
+{
+    unsigned current_level = vms->levels - 1;
+    while (1) {
+        unsigned index = vpn(virtual, current_level);
+        if (current_level <= level) {
+            // Add the new entry.
+            entry_set(table, index, PTE_V | PTE_R | PTE_W | PTE_X | PTE_U | PTE_A | PTE_D |
+                    ((physical >> 2) & ~((1 <<
+                            (PTE_PPN_SHIFT + current_level * vms->vpn_width_bits)) - 1)));
+            return;
+        }
+        reg_t pte = entry(table, index);
+        if (!(pte & PTE_V) ||
+                ((pte & PTE_R) && (pte & PTE_W))) {
+            // Create a new page
+            void *new_page = get_page();
+            setup_page_table(new_page, current_level - 1, virtual);
+            entry_set(table, index, PTE_V | PTE_U | PTE_A | PTE_D |
+                    ((((reg_t) new_page) >> 2) & ~((1 << 10) - 1)));
+            table = new_page;
+        } else {
+            table = (char *) (pte & ~0xfff);
+        }
+        current_level--;
+    }
+}
+
+int main()
+{
+    void *master_table = get_page();
+    setup_page_table(master_table, vms->levels-1, 0);
+    uint32_t *physical = get_page();
+    //uint32_t *virtual = (uint32_t *) (((reg_t) physical) ^ ((reg_t) 0x40000000));
+    uint32_t *virtual = (uint32_t *) (((reg_t) physical) ^ (((reg_t) 0xf) << (vms->vaddr_bits - 4)));
+    // Virtual addresses must be sign-extended.
+    if (vms->vaddr_bits < sizeof(virtual) * 8 && (reg_t) virtual & ((reg_t) 1<<(vms->vaddr_bits-1)))
+        virtual = (uint32_t *) (
+                (reg_t) virtual | ~(((reg_t) 1 << vms->vaddr_bits) - 1));
+    add_entry(master_table, 0, (reg_t) virtual, (reg_t) physical);
+
+    unsigned long satp = set_field(0, SATP_MODE, vms->mode);
+    satp = set_field(satp, SATP_PPN, ((unsigned long) master_table) >> 12);
+    write_csr(satp, satp);
+    satp = read_csr(satp);
+    if (get_field(satp, SATP_MODE) != vms->mode)
+        error();
+
+    reg_t mstatus = read_csr(mstatus);
+    mstatus |= MSTATUS_MPRV;
+    write_csr(mstatus, mstatus);
+
+    // Address translation is enabled.
+    physical[0] = 0xdeadbeef;
+    assert(virtual[0] == physical[0]);
+    virtual[1] = 0x55667788;
+    assert(virtual[1] == physical[1]);
+
+active:
+end:
+    while (1)
+        ;
+}
diff --git a/apps/riscv-tests/debug/programs/trigger.S b/apps/riscv-tests/debug/programs/trigger.S
new file mode 100644
index 0000000..2ccfd21
--- /dev/null
+++ b/apps/riscv-tests/debug/programs/trigger.S
@@ -0,0 +1,113 @@
+#include "encoding.h"
+
+#if XLEN == 64
+# define LREG ld
+# define SREG sd
+# define REGBYTES 8
+#else
+# define LREG lw
+# define SREG sw
+# define REGBYTES 4
+#endif
+
+        .global         main
+
+        .section        .text
+main:
+
+        la      a0, data
+        li      t0, 0
+just_before_read_loop:
+        li      t2, 16
+read_loop:
+        lw      t1, 0(a0)
+        addi    t1, t1, 1
+        addi    t0, t0, 1
+read_again:
+        lw      t1, 0(a0)
+        addi    a0, a0, 4
+        blt     t0, t2, read_loop
+
+        la      a0, data
+just_before_write_loop:
+        li      t0, 1
+write_loop:
+        sw      t0, 0(a0)
+        addi    t0, t0, 1
+        addi    a0, a0, 4
+        blt     t0, t2, write_loop
+
+        j       main_exit
+
+write_store_trigger:
+        li      a0, (1<<6) | (1<<1)
+        li      a1, 0xdeadbee0
+        jal     write_triggers
+        la      a0, data
+        jal     read_triggers
+
+write_load_trigger:
+        li      a0, (1<<6) | (1<<0)
+        li      a1, 0xfeedac00
+        jal     write_triggers
+        la      a0, data
+        jal     read_triggers
+
+// Clear triggers so the next test can use them.
+clear_triggers:
+        li      a0, 0
+        jal     write_triggers
+
+main_exit:
+        li      a0, 0
+        j       _exit
+
+write_triggers:
+        // a0: value to write to each tdata1
+        // a1: value to write to each tdata2
+        li      t0, 0
+2:
+        csrw    CSR_TSELECT, t0
+        csrr    t1, CSR_TSELECT
+        bne     t0, t1, 1f
+        addi    t0, t0, 1
+        csrw    CSR_TDATA2, a1
+        csrw    CSR_TDATA1, a0
+        j       2b
+1:      ret
+
+read_triggers:
+        // a0: address where data should be written
+        li      t0, 0
+2:
+        csrw    CSR_TSELECT, t0
+        csrr    t1, CSR_TSELECT
+        bne     t0, t1, 1f
+        addi    t0, t0, 1
+        csrr    t1, CSR_TDATA1
+        SREG    t1, 0(a0)
+        csrr    t1, CSR_TDATA2
+        SREG    t1, REGBYTES(a0)
+        addi    a0, a0, 2*REGBYTES
+        j       2b
+1:      SREG    zero, 0(a0)
+        ret
+
+        .section .data
+        .align  3
+data:   .word   0x40
+        .word   0x41
+        .word   0x42
+        .word   0x43
+        .word   0x44
+        .word   0x45
+        .word   0x46
+        .word   0x47
+        .word   0x48
+        .word   0x49
+        .word   0x4a
+        .word   0x4b
+        .word   0x4c
+        .word   0x4d
+        .word   0x4e
+        .word   0x4f
diff --git a/apps/riscv-tests/debug/programs/vectors.S b/apps/riscv-tests/debug/programs/vectors.S
new file mode 100644
index 0000000..53e53be
--- /dev/null
+++ b/apps/riscv-tests/debug/programs/vectors.S
@@ -0,0 +1,159 @@
+#include "encoding.h"
+
+#if XLEN == 64
+# define LREG ld
+# define SREG sd
+# define REGBYTES 8
+#else
+# define LREG lw
+# define SREG sw
+# define REGBYTES 4
+#endif
+
+#define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
+#define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
+
+        .global main
+        .global main_end
+        .global main_post_csrr
+
+        // Load constants into all registers so we can test no register are
+        // clobbered after attaching.
+main:
+        SREG    ra, 0(sp)
+        addi    sp, sp, REGBYTES
+
+        // Set VS=1
+        csrr    t0, CSR_MSTATUS
+        li      t1, set_field(0, MSTATUS_VS, 1)
+        or      t0, t0, t1
+        csrw    CSR_MSTATUS, t0
+
+        // copy a to b
+        la      a0, a
+        jal     vector_load_v4
+        la      a0, b
+        jal     shift_store_v4
+
+        // assert a == b
+        la      a0, a
+        la      a1, b
+        jal     check_equal
+test0:
+        bne     a0, zero, return_from_main
+
+        // copy b to c
+        la      a0, b
+        jal     shift_load_v4
+        la      a0, c
+        jal     vector_store_v4
+
+        // assert b == c
+        la      a0, b
+        la      a1, c
+        jal     check_equal
+test1:
+        bne     a0, zero, return_from_main
+
+return_from_main:
+        addi    sp, sp, -REGBYTES
+        LREG    ra, 0(sp)
+        ret
+
+vector_load_v4:
+        // a0: point to memory to load from
+        csrr    s0, vlenb
+        vsetvli zero, s0, e8, m1  # Vectors of 8b
+        vle8.v v4, 0(a0)          # Load bytes
+        ret
+
+vector_store_v4:
+        // a0: point to memory to store to
+        csrr    s0, vlenb
+        vsetvli zero, s0, e8, m1  # Vectors of 8b
+        vse8.v v4, 0(a0)          # Load bytes
+        ret
+
+shift_load_v4:
+        // a0: pointer to memory to load from
+
+        // Configure all elements in the chain
+        csrr    s0, vlenb
+#if XLEN == 32
+        vsetvli zero, s0, e32
+#else
+        vsetvli zero, s0, e64
+#endif
+
+        // Figure out how long the chain is.
+        csrr    s0, vlenb
+        li      s1, XLEN/8
+        divu    s0, s0, s1
+
+1:
+        LREG    s2, 0(a0)
+        vslide1down.vx  v4, v4, s2
+        addi    a0, a0, REGBYTES
+        addi    s0, s0, -1
+        bne     s0, zero, 1b
+
+        ret
+
+shift_store_v4:
+        // a0: pointer to memory to store to
+
+        // Configure all elements in the chain
+        csrr    s0, vlenb
+#if XLEN == 32
+        vsetvli zero, s0, e32
+#else
+        vsetvli zero, s0, e64
+#endif
+
+        // Figure out how long the chain is.
+        csrr    s0, vlenb
+        li      s1, XLEN/8
+        divu    s0, s0, s1
+
+1:
+        vmv.x.s s2, v4
+        SREG    s2, 0(a0)
+        vslide1down.vx  v4, v4, s2
+        addi    a0, a0, REGBYTES
+        addi    s0, s0, -1
+        bne     s0, zero, 1b
+
+        ret
+
+check_equal:
+        csrr    s0, vlenb
+1:
+        lb      s1, 0(a0)
+        lb      s2, 0(a1)
+        bne     s1, s2, 2f
+        addi    a0, a0, 1
+        addi    a1, a1, 1
+        addi    s0, s0, -1
+        bne     s0, zero, 1b
+        li      a0, 0   // equal
+        ret
+2:      // unequal
+        li      a0, 1
+        ret
+
+        .data
+        .align  6
+a:      .word   0xaa00, 0xaa01, 0xaa02, 0xaa03, 0xaa04, 0xaa05, 0xaa06, 0xaa07
+        .word   0xaa08, 0xaa09, 0xaa0a, 0xaa0b, 0xaa0c, 0xaa0d, 0xaa0e, 0xaa0f
+        .word   0xaa10, 0xaa11, 0xaa12, 0xaa13, 0xaa14, 0xaa15, 0xaa16, 0xaa17
+        .word   0xaa18, 0xaa19, 0xaa1a, 0xaa1b, 0xaa1c, 0xaa1d, 0xaa1e, 0xaa1f
+
+b:      .word   0xbb00, 0xbb01, 0xbb02, 0xbb03, 0xbb04, 0xbb05, 0xbb06, 0xbb07
+        .word   0xbb08, 0xbb09, 0xbb0b, 0xbb0b, 0xbb0c, 0xbb0d, 0xbb0e, 0xbb0f
+        .word   0xbb10, 0xbb11, 0xbb13, 0xbb13, 0xbb14, 0xbb15, 0xbb16, 0xbb17
+        .word   0xbb18, 0xbb19, 0xbb1b, 0xbb1b, 0xbb1c, 0xbb1d, 0xbb1e, 0xbb1f
+
+c:      .word   0xcc00, 0xcc01, 0xcc02, 0xcc03, 0xcc04, 0xcc05, 0xcc06, 0xcc07
+        .word   0xcc08, 0xcc09, 0xcc0c, 0xcc0c, 0xcc0c, 0xcc0d, 0xcc0e, 0xcc0f
+        .word   0xcc10, 0xcc11, 0xcc13, 0xcc13, 0xcc14, 0xcc15, 0xcc16, 0xcc17
+        .word   0xcc18, 0xcc19, 0xcc1c, 0xcc1c, 0xcc1c, 0xcc1d, 0xcc1e, 0xcc1f
\ No newline at end of file
diff --git a/apps/riscv-tests/debug/pylint.rc b/apps/riscv-tests/debug/pylint.rc
new file mode 100644
index 0000000..cf07149
--- /dev/null
+++ b/apps/riscv-tests/debug/pylint.rc
@@ -0,0 +1,341 @@
+[MASTER]
+
+# Specify a configuration file.
+#rcfile=
+
+# Python code to execute, usually for sys.path manipulation such as
+# pygtk.require().
+#init-hook=
+
+# Profiled execution.
+profile=no
+
+# Add files or directories to the blacklist. They should be base names, not
+# paths.
+ignore=.git
+
+# Pickle collected data for later comparisons.
+persistent=yes
+
+# List of plugins (as comma separated values of python modules names) to load,
+# usually to register additional checkers.
+load-plugins=
+
+# Allow loading of arbitrary C extensions. Extensions are imported into the
+# active Python interpreter and may run arbitrary code.
+unsafe-load-any-extension=no
+
+# A comma-separated list of package or module names from where C extensions may
+# be loaded. Extensions are loading into the active Python interpreter and may
+# run arbitrary code
+extension-pkg-whitelist=
+
+
+[MESSAGES CONTROL]
+
+# Enable the message, report, category or checker with the given id(s). You can
+# either give multiple identifier separated by comma (,) or put this option
+# multiple time. See also the "--disable" option for examples.
+#enable=
+
+# Disable the message, report, category or checker with the given id(s). You
+# can either give multiple identifiers separated by comma (,) or put this
+# option multiple times (only on the command line, not in the configuration
+# file where it should appear only once).You can also use "--disable=all" to
+# disable everything first and then reenable specific checks. For example, if
+# you want to run only the similarities checker, you can use "--disable=all
+# --enable=similarities". If you want to run only the classes checker, but have
+# no Warning level messages displayed, use"--disable=all --enable=classes
+# --disable=W"
+disable=bad-continuation, missing-docstring, invalid-name, locally-disabled,
+    too-few-public-methods, too-many-arguments, fixme, duplicate-code,
+    no-else-return
+
+
+[REPORTS]
+
+# Set the output format. Available formats are text, parseable, colorized, msvs
+# (visual studio) and html. You can also give a reporter class, eg
+# mypackage.mymodule.MyReporterClass.
+output-format=text
+
+# Put messages in a separate file for each module / package specified on the
+# command line instead of printing them on stdout. Reports (if any) will be
+# written in a file name "pylint_global.[txt|html]".
+files-output=no
+
+# Tells whether to display a full report or only the messages
+reports=no
+
+# Python expression which should return a note less than 10 (10 is the highest
+# note). You have access to the variables errors warning, statement which
+# respectively contain the number of errors / warnings messages and the total
+# number of statements analyzed. This is used by the global evaluation report
+# (RP0004).
+evaluation=10.0 - ((float(5 * error + warning + refactor + convention) / statement) * 10)
+
+# Add a comment according to your evaluation note. This is used by the global
+# evaluation report (RP0004).
+comment=no
+
+# Template used to display messages. This is a python new-style format string
+# used to format the message information. See doc for all details
+#msg-template=
+
+
+[MISCELLANEOUS]
+
+# List of note tags to take in consideration, separated by a comma.
+notes=FIXME,XXX,TODO
+
+
+[SIMILARITIES]
+
+# Minimum lines number of a similarity.
+min-similarity-lines=4
+
+# Ignore comments when computing similarities.
+ignore-comments=yes
+
+# Ignore docstrings when computing similarities.
+ignore-docstrings=yes
+
+# Ignore imports when computing similarities.
+ignore-imports=no
+
+
+[VARIABLES]
+
+# Tells whether we should check for unused import in __init__ files.
+init-import=no
+
+# A regular expression matching the name of dummy variables (i.e. expectedly
+# not used).
+dummy-variables-rgx=_$|dummy
+
+# List of additional names supposed to be defined in builtins. Remember that
+# you should avoid to define new builtins when possible.
+additional-builtins=
+
+
+[TYPECHECK]
+
+# Tells whether missing members accessed in mixin class should be ignored. A
+# mixin class is detected if its name ends with "mixin" (case insensitive).
+ignore-mixin-members=yes
+
+# List of module names for which member attributes should not be checked
+# (useful for modules/projects where namespaces are manipulated during runtime
+# and thus existing member attributes cannot be deduced by static analysis
+ignored-modules=
+
+# List of classes names for which member attributes should not be checked
+# (useful for classes with attributes dynamically set).
+ignored-classes=SQLObject
+
+# When zope mode is activated, add a predefined set of Zope acquired attributes
+# to generated-members.
+zope=no
+
+# List of members which are set dynamically and missed by pylint inference
+# system, and so shouldn't trigger E0201 when accessed. Python regular
+# expressions are accepted.
+generated-members=REQUEST,acl_users,aq_parent
+
+
+[FORMAT]
+
+# Maximum number of characters on a single line.
+max-line-length=80
+
+# Regexp for a line that is allowed to be longer than the limit.
+ignore-long-lines=^\s*(# )?<?https?://\S+>?$
+
+# Allow the body of an if to be on the same line as the test if there is no
+# else.
+single-line-if-stmt=no
+
+# List of optional constructs for which whitespace checking is disabled
+no-space-check=trailing-comma,dict-separator
+
+# Maximum number of lines in a module
+max-module-lines=10000
+
+# String used as indentation unit. This is usually " " (4 spaces) or "\t" (1
+# tab).
+indent-string='    '
+
+# Number of spaces of indent required inside a hanging or continued line.
+indent-after-paren=4
+
+
+[LOGGING]
+
+# Logging modules to check that the string format arguments are in logging
+# function parameter format
+logging-modules=logging
+
+
+[BASIC]
+
+# Required attributes for module, separated by a comma
+#required-attributes=
+
+# List of builtins function names that should not be used, separated by a comma
+bad-functions=map,filter,apply,input,file
+
+# Good variable names which should always be accepted, separated by a comma
+good-names=i,j,k,ex,Run,_
+
+# Bad variable names which should always be refused, separated by a comma
+bad-names=foo,bar,baz,toto,tutu,tata
+
+# Colon-delimited sets of names that determine each other's naming style when
+# the name regexes allow several styles.
+name-group=
+
+# Include a hint for the correct naming format with invalid-name
+include-naming-hint=no
+
+# Regular expression matching correct function names
+function-rgx=[a-z_][a-z0-9_]{2,30}$
+
+# Naming hint for function names
+function-name-hint=[a-z_][a-z0-9_]{2,30}$
+
+# Regular expression matching correct variable names
+variable-rgx=[a-z_][a-z0-9_]{2,30}$
+
+# Naming hint for variable names
+variable-name-hint=[a-z_][a-z0-9_]{2,30}$
+
+# Regular expression matching correct constant names
+const-rgx=(([A-Z_][A-Z0-9_]*)|(__.*__))$
+
+# Naming hint for constant names
+const-name-hint=(([A-Z_][A-Z0-9_]*)|(__.*__))$
+
+# Regular expression matching correct attribute names
+attr-rgx=[a-z_][a-z0-9_]{2,30}$
+
+# Naming hint for attribute names
+attr-name-hint=[a-z_][a-z0-9_]{2,30}$
+
+# Regular expression matching correct argument names
+argument-rgx=[a-z_][a-z0-9_]{2,30}$
+
+# Naming hint for argument names
+argument-name-hint=[a-z_][a-z0-9_]{2,30}$
+
+# Regular expression matching correct class attribute names
+class-attribute-rgx=([A-Za-z_][A-Za-z0-9_]{2,30}|(__.*__))$
+
+# Naming hint for class attribute names
+class-attribute-name-hint=([A-Za-z_][A-Za-z0-9_]{2,30}|(__.*__))$
+
+# Regular expression matching correct inline iteration names
+inlinevar-rgx=[A-Za-z_][A-Za-z0-9_]*$
+
+# Naming hint for inline iteration names
+inlinevar-name-hint=[A-Za-z_][A-Za-z0-9_]*$
+
+# Regular expression matching correct class names
+class-rgx=[A-Z_][a-zA-Z0-9]+$
+
+# Naming hint for class names
+class-name-hint=[A-Z_][a-zA-Z0-9]+$
+
+# Regular expression matching correct module names
+module-rgx=(([a-z_][a-z0-9_]*)|([A-Z][a-zA-Z0-9]+))$
+
+# Naming hint for module names
+module-name-hint=(([a-z_][a-z0-9_]*)|([A-Z][a-zA-Z0-9]+))$
+
+# Regular expression matching correct method names
+method-rgx=[a-z_][a-z0-9_]{2,30}$
+
+# Naming hint for method names
+method-name-hint=[a-z_][a-z0-9_]{2,30}$
+
+# Regular expression which should only match function or class names that do
+# not require a docstring.
+no-docstring-rgx=__.*__
+
+# Minimum line length for functions/classes that require docstrings, shorter
+# ones are exempt.
+docstring-min-length=-1
+
+
+[IMPORTS]
+
+# Deprecated modules which should not be used, separated by a comma
+deprecated-modules=regsub,TERMIOS,Bastion,rexec
+
+# Create a graph of every (i.e. internal and external) dependencies in the
+# given file (report RP0402 must not be disabled)
+import-graph=
+
+# Create a graph of external dependencies in the given file (report RP0402 must
+# not be disabled)
+ext-import-graph=
+
+# Create a graph of internal dependencies in the given file (report RP0402 must
+# not be disabled)
+int-import-graph=
+
+
+[CLASSES]
+
+# List of interface methods to ignore, separated by a comma. This is used for
+# instance to not check methods defines in Zope's Interface base class.
+#ignore-iface-methods=isImplementedBy,deferred,extends,names,namesAndDescriptions,queryDescriptionFor,getBases,getDescriptionFor,getDoc,getName,getTaggedValue,getTaggedValueTags,isEqualOrExtendedBy,setTaggedValue,isImplementedByInstancesOf,adaptWith,is_implemented_by
+
+# List of method names used to declare (i.e. assign) instance attributes.
+defining-attr-methods=__init__,__new__,setUp
+
+# List of valid names for the first argument in a class method.
+valid-classmethod-first-arg=cls
+
+# List of valid names for the first argument in a metaclass class method.
+valid-metaclass-classmethod-first-arg=mcs
+
+
+[DESIGN]
+
+# Maximum number of arguments for function / method
+max-args=5
+
+# Argument names that match this expression will be ignored. Default to name
+# with leading underscore
+ignored-argument-names=_.*
+
+# Maximum number of locals for function / method body
+max-locals=15
+
+# Maximum number of return / yield for function / method body
+max-returns=6
+
+# Maximum number of branch for function / method body
+max-branches=12
+
+# Maximum number of statements in function / method body
+max-statements=50
+
+# Maximum number of parents for a class (see R0901).
+max-parents=7
+
+# Maximum number of attributes for a class (see R0902).
+max-attributes=7
+
+# Minimum number of public methods for a class (see R0903).
+min-public-methods=2
+
+# Maximum number of public methods for a class (see R0904).
+max-public-methods=20
+
+
+[EXCEPTIONS]
+
+# Exceptions that will emit a warning when being caught. Defaults to
+# "Exception"
+overgeneral-exceptions=Exception
diff --git a/apps/riscv-tests/debug/requirements.txt b/apps/riscv-tests/debug/requirements.txt
new file mode 100644
index 0000000..8fbeb99
--- /dev/null
+++ b/apps/riscv-tests/debug/requirements.txt
@@ -0,0 +1 @@
+pexpect>=4.0.0
diff --git a/apps/riscv-tests/debug/targets.py b/apps/riscv-tests/debug/targets.py
new file mode 100644
index 0000000..8b64e14
--- /dev/null
+++ b/apps/riscv-tests/debug/targets.py
@@ -0,0 +1,227 @@
+import importlib
+import os.path
+import sys
+import tempfile
+
+import testlib
+
+class Hart:
+    # XLEN of the hart. May be overridden with --32 or --64 command line
+    # options.
+    xlen = 0
+
+    # Will be autodetected (by running ExamineTarget) if left unset. Set to
+    # save a little time.
+    misa = None
+
+    # Path to linker script relative to the .py file where the target is
+    # defined. Defaults to <name>.lds.
+    link_script_path = None
+
+    # Implements dmode in tdata1 as described in the spec. Harts that need
+    # this value set to False are not compliant with the spec (but still usable
+    # as long as running code doesn't try to mess with triggers set by an
+    # external debugger).
+    honors_tdata1_hmode = True
+
+    # Address where a r/w/x block of RAM starts, together with its size.
+    ram = None
+    ram_size = None
+
+    # Number of instruction triggers the hart supports.
+    instruction_hardware_breakpoint_count = 0
+
+    # Defaults to target-<index>
+    name = None
+
+    # When reset, the PC must be at one of the values listed here.
+    # This is a list because on some boards the reset vector depends on
+    # jumpers.
+    reset_vectors = []
+
+    def extensionSupported(self, letter):
+        # target.misa is set by testlib.ExamineTarget
+        if self.misa:
+            return self.misa & (1 << (ord(letter.upper()) - ord('A')))
+        return False
+
+class Target:
+    # pylint: disable=too-many-instance-attributes
+
+    # List of Hart object instances, one for each hart in the target.
+    harts = []
+
+    # Name of the target. Defaults to the name of the class.
+    name = None
+
+    # GDB remotetimeout setting.
+    timeout_sec = 2
+
+    # Timeout waiting for the server to start up. This is different than the
+    # GDB timeout, which is how long GDB waits for commands to execute.
+    # The server_timeout is how long this script waits for the server to be
+    # ready for GDB connections.
+    server_timeout_sec = 60
+
+    # Path to OpenOCD configuration file relative to the .py file where the
+    # target is defined. Defaults to <name>.cfg.
+    openocd_config_path = None
+
+    # List of commands that should be executed in gdb after connecting but
+    # before starting the test.
+    gdb_setup = []
+
+    # Supports mtime at 0x2004000
+    supports_clint_mtime = True
+
+    # Implements custom debug registers like spike does. It seems unlikely any
+    # hardware will every do that.
+    implements_custom_test = False
+
+    # When true it indicates that reading invalid memory doesn't return an error
+    invalid_memory_returns_zero = False
+
+    # Supports simultaneous resume through hasel.
+    support_hasel = True
+
+    # Tests whose names are mentioned in this list will be skipped and marked
+    # as not applicable. This is a crude mechanism that can be handy, but in
+    # general it's better to define some property like those above that
+    # describe behavior of this target, and tests can use that to decide
+    # whether they are applicable or not.
+    skip_tests = []
+
+    # Set False if semihosting should not be tested in this configuration,
+    # because it doesn't work and isn't expected to work.
+    test_semihosting = True
+
+    # Set False if manual hwbps (breakpoints set by directly writing tdata*)
+    # isn't supposed to work.
+    support_manual_hwbp = True
+
+    # Internal variables:
+    directory = None
+    temporary_files = []
+
+    def __init__(self, path, parsed):
+        # Path to module.
+        self.path = path
+        self.directory = os.path.dirname(path)
+        self.server_cmd = parsed.server_cmd
+        self.sim_cmd = parsed.sim_cmd
+        self.temporary_binary = None
+        Target.isolate = parsed.isolate
+        if not self.name:
+            self.name = type(self).__name__
+        # Default OpenOCD config file to <name>.cfg
+        if not self.openocd_config_path:
+            self.openocd_config_path = "%s.cfg" % self.name
+        self.openocd_config_path = os.path.join(self.directory,
+                self.openocd_config_path)
+        for i, hart in enumerate(self.harts):
+            hart.index = i
+            if not hasattr(hart, 'id'):
+                hart.id = i
+            if not hart.name:
+                hart.name = "%s-%d" % (self.name, i)
+            # Default link script to <name>.lds
+            if not hart.link_script_path:
+                hart.link_script_path = "%s.lds" % self.name
+            hart.link_script_path = os.path.join(self.directory,
+                    hart.link_script_path)
+
+    def create(self):
+        """Create the target out of thin air, eg. start a simulator."""
+
+    def server(self):
+        """Start the debug server that gdb connects to, eg. OpenOCD."""
+        return testlib.Openocd(server_cmd=self.server_cmd,
+                config=self.openocd_config_path,
+                timeout=self.server_timeout_sec)
+
+    def compile(self, hart, *sources):
+        binary_name = "%s_%s-%d" % (
+                self.name,
+                os.path.basename(os.path.splitext(sources[0])[0]),
+                hart.xlen)
+        if Target.isolate:
+            self.temporary_binary = tempfile.NamedTemporaryFile(
+                    prefix=binary_name + "_")
+            binary_name = self.temporary_binary.name
+            Target.temporary_files.append(self.temporary_binary)
+
+        args = list(sources) + [
+                "programs/entry.S", "programs/init.c",
+                "-DNHARTS=%d" % len(self.harts),
+                "-I", "../env",
+                "-T", hart.link_script_path,
+                "-nostartfiles",
+                "-mcmodel=medany",
+                "-DXLEN=%d" % hart.xlen,
+                "-o", binary_name]
+
+        if hart.extensionSupported('e'):
+            args.append("-march=rv32e")
+            args.append("-mabi=ilp32e")
+            args.append("-DRV32E")
+        else:
+            march = "rv%dima" % hart.xlen
+            for letter in "fdcv":
+                if hart.extensionSupported(letter):
+                    march += letter
+            args.append("-march=%s" % march)
+            if hart.xlen == 32:
+                args.append("-mabi=ilp32")
+            else:
+                args.append("-mabi=lp%d" % hart.xlen)
+
+        testlib.compile(args)
+        return binary_name
+
+def add_target_options(parser):
+    parser.add_argument("target", help=".py file that contains definition for "
+            "the target to test with.")
+    parser.add_argument("--sim_cmd",
+            help="The command to use to start the actual target (e.g. "
+            "simulation)", default="spike")
+    parser.add_argument("--server_cmd",
+            help="The command to use to start the debug server (e.g. OpenOCD)")
+
+    xlen_group = parser.add_mutually_exclusive_group()
+    xlen_group.add_argument("--32", action="store_const", const=32,
+            dest="xlen", default=0, help="Force the target to be 32-bit.")
+    xlen_group.add_argument("--64", action="store_const", const=64,
+            dest="xlen", default=0, help="Force the target to be 64-bit.")
+
+    parser.add_argument("--isolate", action="store_true",
+            help="Try to run in such a way that multiple instances can run at "
+            "the same time. This may make it harder to debug a failure if it "
+            "does occur.")
+
+def target(parsed):
+    directory = os.path.dirname(parsed.target)
+    filename = os.path.basename(parsed.target)
+    module_name = os.path.splitext(filename)[0]
+
+    sys.path.append(directory)
+    module = importlib.import_module(module_name)
+    found = []
+    for name in dir(module):
+        definition = getattr(module, name)
+        if isinstance(definition, type) and issubclass(definition, Target):
+            found.append(definition)
+    assert len(found) == 1, "%s does not define exactly one subclass of " \
+            "targets.Target" % parsed.target
+
+    t = found[0](parsed.target, parsed)
+    assert t.harts, "%s doesn't have any harts defined!" % t.name
+    if parsed.xlen > 0:
+        for h in t.harts:
+            if h.xlen == 0:
+                h.xlen = parsed.xlen
+            elif h.xlen != parsed.xlen:
+                raise Exception("The target hart specified an XLEN of %d, but "\
+                        "the command line specified an XLEN of %d. They must "\
+                        "match." % (h.xlen, parsed.xlen))
+
+    return t
diff --git a/apps/riscv-tests/debug/targets/RISC-V/spike-1.cfg b/apps/riscv-tests/debug/targets/RISC-V/spike-1.cfg
new file mode 100644
index 0000000..3bc32d1
--- /dev/null
+++ b/apps/riscv-tests/debug/targets/RISC-V/spike-1.cfg
@@ -0,0 +1,30 @@
+adapter_khz     10000
+
+interface remote_bitbang
+remote_bitbang_host $::env(REMOTE_BITBANG_HOST)
+remote_bitbang_port $::env(REMOTE_BITBANG_PORT)
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+$_TARGETNAME configure -work-area-phys $::env(WORK_AREA) -work-area-size 8096 -work-area-backup 1
+
+
+gdb_report_data_abort enable
+gdb_report_register_access_error enable
+
+# Expose an unimplemented CSR so we can test non-existent register access
+# behavior.
+riscv expose_csrs 2288
+riscv expose_custom 1,12345-12348
+
+init
+
+set challenge [riscv authdata_read]
+riscv authdata_write [expr $challenge + 1]
+
+halt
+
+arm semihosting enable
diff --git a/apps/riscv-tests/debug/targets/RISC-V/spike-2-hwthread.cfg b/apps/riscv-tests/debug/targets/RISC-V/spike-2-hwthread.cfg
new file mode 100644
index 0000000..c378a45
--- /dev/null
+++ b/apps/riscv-tests/debug/targets/RISC-V/spike-2-hwthread.cfg
@@ -0,0 +1,38 @@
+# Connect to a mult-icore RISC-V target, exposing each hart as a thread.
+adapter_khz     10000
+
+interface remote_bitbang
+remote_bitbang_host $::env(REMOTE_BITBANG_HOST)
+remote_bitbang_port $::env(REMOTE_BITBANG_PORT)
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
+
+set _TARGETNAME_0 $_CHIPNAME.cpu0
+set _TARGETNAME_1 $_CHIPNAME.cpu1
+target create $_TARGETNAME_0 riscv -chain-position $_CHIPNAME.cpu -rtos hwthread
+target create $_TARGETNAME_1 riscv -chain-position $_CHIPNAME.cpu -coreid 1
+target smp $_TARGETNAME_0 $_TARGETNAME_1
+
+gdb_report_data_abort enable
+gdb_report_register_access_error enable
+
+# Expose an unimplemented CSR so we can test non-existent register access
+# behavior.
+foreach t [target names] {
+    targets $t
+    riscv expose_csrs 2288
+    riscv expose_custom 1,12345-12348
+}
+
+init
+
+set challenge [riscv authdata_read]
+riscv authdata_write [expr $challenge + 1]
+
+halt
+
+foreach t [target names] {
+    targets $t
+    arm semihosting enable
+}
diff --git a/apps/riscv-tests/debug/targets/RISC-V/spike-2.cfg b/apps/riscv-tests/debug/targets/RISC-V/spike-2.cfg
new file mode 100644
index 0000000..640fba9
--- /dev/null
+++ b/apps/riscv-tests/debug/targets/RISC-V/spike-2.cfg
@@ -0,0 +1,36 @@
+# Connect to a mult-icore RISC-V target, exposing each hart as a thread.
+adapter_khz     10000
+
+interface remote_bitbang
+remote_bitbang_host $::env(REMOTE_BITBANG_HOST)
+remote_bitbang_port $::env(REMOTE_BITBANG_PORT)
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
+
+set _TARGETNAME_0 $_CHIPNAME.cpu0
+set _TARGETNAME_1 $_CHIPNAME.cpu1
+target create $_TARGETNAME_0 riscv -chain-position $_CHIPNAME.cpu -coreid 0
+target create $_TARGETNAME_1 riscv -chain-position $_CHIPNAME.cpu -coreid 1
+
+gdb_report_data_abort enable
+gdb_report_register_access_error enable
+
+# Expose an unimplemented CSR so we can test non-existent register access
+# behavior.
+foreach t [target names] {
+    targets $t
+    riscv expose_csrs 2288
+    riscv expose_custom 1,12345-12348
+}
+
+init
+
+set challenge [riscv authdata_read]
+riscv authdata_write [expr $challenge + 1]
+
+foreach t [target names] {
+    targets $t
+    halt
+    arm semihosting enable
+}
diff --git a/apps/riscv-tests/debug/targets/RISC-V/spike-rtos.cfg b/apps/riscv-tests/debug/targets/RISC-V/spike-rtos.cfg
new file mode 100644
index 0000000..395a9f8
--- /dev/null
+++ b/apps/riscv-tests/debug/targets/RISC-V/spike-rtos.cfg
@@ -0,0 +1,29 @@
+# Connect to a mult-icore RISC-V target, exposing each hart as a thread.
+adapter_khz     10000
+
+interface remote_bitbang
+remote_bitbang_host $::env(REMOTE_BITBANG_HOST)
+remote_bitbang_port $::env(REMOTE_BITBANG_PORT)
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
+
+enable_rtos_riscv
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
+
+gdb_report_data_abort enable
+gdb_report_register_access_error enable
+
+# Expose an unimplemented CSR so we can test non-existent register access
+# behavior.
+riscv expose_csrs 2288
+riscv expose_custom 1,12345-12348
+
+init
+
+set challenge [riscv authdata_read]
+riscv authdata_write [expr $challenge + 1]
+
+halt
diff --git a/apps/riscv-tests/debug/targets/RISC-V/spike32-2-hwthread.py b/apps/riscv-tests/debug/targets/RISC-V/spike32-2-hwthread.py
new file mode 100644
index 0000000..2ad2998
--- /dev/null
+++ b/apps/riscv-tests/debug/targets/RISC-V/spike32-2-hwthread.py
@@ -0,0 +1,15 @@
+import targets
+import testlib
+
+import spike32  # pylint: disable=import-error
+
+class spike32_2(targets.Target):
+    harts = [spike32.spike32_hart(misa=0x40341101),
+            spike32.spike32_hart(misa=0x40341101)]
+    openocd_config_path = "spike-2-hwthread.cfg"
+    timeout_sec = 5
+    implements_custom_test = True
+
+    def create(self):
+        return testlib.Spike(self, isa="RV32IMAV", support_hasel=True,
+                support_haltgroups=False)
diff --git a/apps/riscv-tests/debug/targets/RISC-V/spike32-2-rtos.py b/apps/riscv-tests/debug/targets/RISC-V/spike32-2-rtos.py
new file mode 100644
index 0000000..ce0d56d
--- /dev/null
+++ b/apps/riscv-tests/debug/targets/RISC-V/spike32-2-rtos.py
@@ -0,0 +1,19 @@
+import targets
+import testlib
+
+import spike32  # pylint: disable=import-error
+
+class spike32_2(targets.Target):
+    harts = [spike32.spike32_hart(misa=0x40141129),
+            spike32.spike32_hart(misa=0x40141129)]
+    openocd_config_path = "spike-rtos.cfg"
+    timeout_sec = 30
+    implements_custom_test = True
+    support_hasel = False
+    test_semihosting = False
+    support_manual_hwbp = False # not supported with `-rtos riscv`
+
+    def create(self):
+        return testlib.Spike(self, progbufsize=0, dmi_rti=4,
+                support_hasel=False, support_abstract_csr=True,
+                support_haltgroups=False)
diff --git a/apps/riscv-tests/debug/targets/RISC-V/spike32-2.py b/apps/riscv-tests/debug/targets/RISC-V/spike32-2.py
new file mode 100644
index 0000000..ca198d7
--- /dev/null
+++ b/apps/riscv-tests/debug/targets/RISC-V/spike32-2.py
@@ -0,0 +1,15 @@
+import targets
+import testlib
+
+import spike32  # pylint: disable=import-error
+
+class spike32_2(targets.Target):
+    harts = [spike32.spike32_hart(misa=0x40141125),
+            spike32.spike32_hart(misa=0x40141125)]
+    openocd_config_path = "spike-2.cfg"
+    timeout_sec = 30
+    implements_custom_test = True
+
+    def create(self):
+        return testlib.Spike(self, isa="RV32IMAFC", progbufsize=0, dmi_rti=4,
+                support_abstract_csr=True, support_haltgroups=False)
diff --git a/apps/riscv-tests/debug/targets/RISC-V/spike32.lds b/apps/riscv-tests/debug/targets/RISC-V/spike32.lds
new file mode 100755
index 0000000..84216db
--- /dev/null
+++ b/apps/riscv-tests/debug/targets/RISC-V/spike32.lds
@@ -0,0 +1,38 @@
+OUTPUT_ARCH( "riscv" )
+
+SECTIONS
+{
+  /* Leave some space for pk's data structures, which includes tohost/fromhost
+   * which are special addresses we ought to leave alone.  */
+  . = 0x10010000;
+  .text : 
+  {
+    *(.text.entry)
+    *(.text)
+  }
+
+  /* data segment */
+  .data : { *(.data) }
+
+  .sdata : {
+    __global_pointer$ = . + 0x800;
+    *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
+    *(.srodata*)
+    *(.sdata .sdata.* .gnu.linkonce.s.*)
+  }
+
+  /* bss segment */
+  __bss_start = .;
+  .sbss : {
+    *(.sbss .sbss.* .gnu.linkonce.sb.*)
+    *(.scommon)
+  }
+  .bss : { *(.bss) }
+  __bss_end = .;
+
+  __malloc_start = .;
+  . = . + 512;
+
+  /* End of uninitalized data segement */
+  _end = .;
+}
diff --git a/apps/riscv-tests/debug/targets/RISC-V/spike32.py b/apps/riscv-tests/debug/targets/RISC-V/spike32.py
new file mode 100644
index 0000000..b261f6c
--- /dev/null
+++ b/apps/riscv-tests/debug/targets/RISC-V/spike32.py
@@ -0,0 +1,26 @@
+import targets
+import testlib
+
+class spike32_hart(targets.Hart):
+    xlen = 32
+    ram = 0x10000000
+    ram_size = 0x10000000
+    instruction_hardware_breakpoint_count = 4
+    reset_vectors = [0x1000]
+    link_script_path = "spike32.lds"
+
+    def __init__(self, misa):
+        self.misa = misa
+
+class spike32(targets.Target):
+    harts = [spike32_hart(misa=0x4034112d)]
+    openocd_config_path = "spike-1.cfg"
+    timeout_sec = 30
+    implements_custom_test = True
+
+    def create(self):
+        # 64-bit FPRs on 32-bit target
+        return testlib.Spike(self, isa="RV32IMAFDCV", dmi_rti=4,
+                support_abstract_csr=True, support_haltgroups=False,
+                # elen must be at least 64 because D is supported.
+                elen=64)
diff --git a/apps/riscv-tests/debug/targets/RISC-V/spike64-2-hwthread.py b/apps/riscv-tests/debug/targets/RISC-V/spike64-2-hwthread.py
new file mode 100644
index 0000000..5d8d6e6
--- /dev/null
+++ b/apps/riscv-tests/debug/targets/RISC-V/spike64-2-hwthread.py
@@ -0,0 +1,14 @@
+import targets
+import testlib
+
+import spike64  # pylint: disable=import-error
+
+class spike64_2(targets.Target):
+    harts = [spike64.spike64_hart(misa=0x8000000000141129),
+            spike64.spike64_hart(misa=0x8000000000141129)]
+    openocd_config_path = "spike-2-hwthread.cfg"
+    timeout_sec = 5
+    implements_custom_test = True
+
+    def create(self):
+        return testlib.Spike(self)
diff --git a/apps/riscv-tests/debug/targets/RISC-V/spike64-2-rtos.py b/apps/riscv-tests/debug/targets/RISC-V/spike64-2-rtos.py
new file mode 100644
index 0000000..2062f6d
--- /dev/null
+++ b/apps/riscv-tests/debug/targets/RISC-V/spike64-2-rtos.py
@@ -0,0 +1,18 @@
+import targets
+import testlib
+
+import spike64  # pylint: disable=import-error
+
+class spike64_2_rtos(targets.Target):
+    harts = [spike64.spike64_hart(misa=0x8000000000141129),
+            spike64.spike64_hart(misa=0x8000000000141129)]
+    openocd_config_path = "spike-rtos.cfg"
+    timeout_sec = 60
+    implements_custom_test = True
+    support_hasel = False
+    test_semihosting = False
+    support_manual_hwbp = False # not supported with `-rtos riscv`
+
+    def create(self):
+        return testlib.Spike(self, abstract_rti=30, support_hasel=False,
+                support_abstract_csr=False)
diff --git a/apps/riscv-tests/debug/targets/RISC-V/spike64-2.py b/apps/riscv-tests/debug/targets/RISC-V/spike64-2.py
new file mode 100644
index 0000000..5dc0e7b
--- /dev/null
+++ b/apps/riscv-tests/debug/targets/RISC-V/spike64-2.py
@@ -0,0 +1,21 @@
+import targets
+import testlib
+
+import spike64  # pylint: disable=import-error
+
+class spike64_2(targets.Target):
+    harts = [spike64.spike64_hart(misa=0x8000000000341129),
+            spike64.spike64_hart(misa=0x8000000000341129)]
+    openocd_config_path = "spike-2.cfg"
+    # Increased timeout because we use abstract_rti to artificially slow things
+    # down.
+    timeout_sec = 20
+    implements_custom_test = True
+    support_hasel = False
+
+    def create(self):
+        # TODO: It would be nice to test with slen=128, but spike currently
+        # requires vlen==slen.
+        return testlib.Spike(self, isa="RV64IMAFDV", abstract_rti=30,
+                support_hasel=False, support_abstract_csr=False,
+                vlen=512, elen=64, slen=512)
diff --git a/apps/riscv-tests/debug/targets/RISC-V/spike64.lds b/apps/riscv-tests/debug/targets/RISC-V/spike64.lds
new file mode 100755
index 0000000..2e7d65d
--- /dev/null
+++ b/apps/riscv-tests/debug/targets/RISC-V/spike64.lds
@@ -0,0 +1,36 @@
+OUTPUT_ARCH( "riscv" )
+
+SECTIONS
+{
+  . = 0x1212340000;
+  .text : 
+  {
+    *(.text.entry)
+    *(.text)
+  }
+
+  /* data segment */
+  .data : { *(.data) }
+
+  .sdata : {
+    __global_pointer$ = . + 0x800;
+    *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
+    *(.srodata*)
+    *(.sdata .sdata.* .gnu.linkonce.s.*)
+  }
+
+  /* bss segment */
+  __bss_start = .;
+  .sbss : {
+    *(.sbss .sbss.* .gnu.linkonce.sb.*)
+    *(.scommon)
+  }
+  .bss : { *(.bss) }
+  __bss_end = .;
+
+  __malloc_start = .;
+  . = . + 512;
+
+  /* End of uninitalized data segement */
+  _end = .;
+}
diff --git a/apps/riscv-tests/debug/targets/RISC-V/spike64.py b/apps/riscv-tests/debug/targets/RISC-V/spike64.py
new file mode 100644
index 0000000..ec43a11
--- /dev/null
+++ b/apps/riscv-tests/debug/targets/RISC-V/spike64.py
@@ -0,0 +1,24 @@
+import targets
+import testlib
+
+class spike64_hart(targets.Hart):
+    xlen = 64
+    ram = 0x1212340000
+    ram_size = 0x10000000
+    instruction_hardware_breakpoint_count = 4
+    reset_vectors = [0x1000]
+    link_script_path = "spike64.lds"
+
+    def __init__(self, misa=0x8000000000141125):
+        self.misa = misa
+
+class spike64(targets.Target):
+    harts = [spike64_hart()]
+    openocd_config_path = "spike-1.cfg"
+    timeout_sec = 30
+    implements_custom_test = True
+
+    def create(self):
+        # 32-bit FPRs only
+        return testlib.Spike(self, isa="RV64IMAFC", progbufsize=0,
+                abstract_rti=30, support_abstract_csr=True)
diff --git a/apps/riscv-tests/debug/targets/SiFive/Freedom/E300.py b/apps/riscv-tests/debug/targets/SiFive/Freedom/E300.py
new file mode 100644
index 0000000..5f1c418
--- /dev/null
+++ b/apps/riscv-tests/debug/targets/SiFive/Freedom/E300.py
@@ -0,0 +1,13 @@
+import targets
+
+class E300Hart(targets.Hart):
+    xlen = 32
+    ram = 0x80000000
+    ram_size = 64 * 1024
+    instruction_hardware_breakpoint_count = 2
+    link_script_path = "Freedom.lds"
+
+class E300(targets.Target):
+    openocd_config_path = "Freedom.cfg"
+    harts = [E300Hart()]
+    invalid_memory_returns_zero = True
diff --git a/apps/riscv-tests/debug/targets/SiFive/Freedom/Freedom.cfg b/apps/riscv-tests/debug/targets/SiFive/Freedom/Freedom.cfg
new file mode 100644
index 0000000..8947bf5
--- /dev/null
+++ b/apps/riscv-tests/debug/targets/SiFive/Freedom/Freedom.cfg
@@ -0,0 +1,14 @@
+adapter_khz     10000
+
+source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg]
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
+
+init
+
+halt
+echo "Ready for Remote Connections"
diff --git a/apps/riscv-tests/debug/targets/SiFive/Freedom/Freedom.lds b/apps/riscv-tests/debug/targets/SiFive/Freedom/Freedom.lds
new file mode 100644
index 0000000..9354d3f
--- /dev/null
+++ b/apps/riscv-tests/debug/targets/SiFive/Freedom/Freedom.lds
@@ -0,0 +1,36 @@
+OUTPUT_ARCH( "riscv" )
+
+SECTIONS
+{
+  . = 0x80000000;
+  .text : 
+  {
+    *(.text.entry)
+    *(.text)
+  }
+
+  /* data segment */
+  .data : { *(.data) }
+
+  .sdata : {
+    __global_pointer$ = . + 0x800;
+    *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
+    *(.srodata*)
+    *(.sdata .sdata.* .gnu.linkonce.s.*)
+  }
+
+  /* bss segment */
+  __bss_start = .;
+  .sbss : {
+    *(.sbss .sbss.* .gnu.linkonce.sb.*)
+    *(.scommon)
+  }
+  .bss : { *(.bss) }
+  __bss_end = .;
+
+  __malloc_start = .;
+  . = . + 512;
+
+  /* End of uninitalized data segement */
+  _end = .;
+}
diff --git a/apps/riscv-tests/debug/targets/SiFive/Freedom/U500.py b/apps/riscv-tests/debug/targets/SiFive/Freedom/U500.py
new file mode 100644
index 0000000..4442af7
--- /dev/null
+++ b/apps/riscv-tests/debug/targets/SiFive/Freedom/U500.py
@@ -0,0 +1,13 @@
+import targets
+
+class U500Hart(targets.Hart):
+    xlen = 64
+    ram = 0x80000000
+    ram_size = 64 * 1024
+    instruction_hardware_breakpoint_count = 2
+    link_script_path = "Freedom.lds"
+
+class U500(targets.Target):
+    openocd_config_path = "Freedom.cfg"
+    harts = [U500Hart()]
+    invalid_memory_returns_zero = True
diff --git a/apps/riscv-tests/debug/targets/SiFive/Freedom/U500Sim.py b/apps/riscv-tests/debug/targets/SiFive/Freedom/U500Sim.py
new file mode 100644
index 0000000..065ab08
--- /dev/null
+++ b/apps/riscv-tests/debug/targets/SiFive/Freedom/U500Sim.py
@@ -0,0 +1,17 @@
+import targets
+import testlib
+
+class U500Hart(targets.Hart):
+    xlen = 64
+    ram = 0x80000000
+    ram_size = 256 * 1024 * 1024
+    instruction_hardware_breakpoint_count = 2
+    link_script_path = "Freedom.lds"
+
+class U500Sim(targets.Target):
+    timeout_sec = 6000
+    openocd_config_path = "Freedom.cfg"
+    harts = [U500Hart()]
+
+    def target(self):
+        return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)
diff --git a/apps/riscv-tests/debug/targets/SiFive/HiFive1-flash.lds b/apps/riscv-tests/debug/targets/SiFive/HiFive1-flash.lds
new file mode 100644
index 0000000..e4074be
--- /dev/null
+++ b/apps/riscv-tests/debug/targets/SiFive/HiFive1-flash.lds
@@ -0,0 +1,44 @@
+OUTPUT_ARCH( "riscv" )
+
+MEMORY
+{
+    flash (rxl) : ORIGIN = 0x20400000, LENGTH = 128K
+    ram (wx) : ORIGIN = 0x80000000, LENGTH = 16K
+}
+
+SECTIONS
+{
+  flash_text : {
+    *(.text.entry)
+    *(.text)
+  } >flash
+
+  /* data segment */
+  .data : { *(.data) } >ram
+
+  .sdata : {
+    __global_pointer$ = . + 0x800;
+    *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
+    *(.srodata*)
+    *(.sdata .sdata.* .gnu.linkonce.s.*)
+  } >ram
+
+  /* bss segment */
+  __bss_start = .;
+  .sbss : {
+    *(.sbss .sbss.* .gnu.linkonce.sb.*)
+    *(.scommon)
+  } >ram
+  .bss : { *(.bss) } >ram
+  __bss_end = .;
+
+  __malloc_start = .;
+  . = . + 512;
+
+  /* End of uninitalized data segement */
+  _end = .;
+}
+
+ENTRY(_start)
+
+ASSERT(_end < 0x80004000, "program is too large")
diff --git a/apps/riscv-tests/debug/targets/SiFive/HiFive1-flash.py b/apps/riscv-tests/debug/targets/SiFive/HiFive1-flash.py
new file mode 100644
index 0000000..06dfcfc
--- /dev/null
+++ b/apps/riscv-tests/debug/targets/SiFive/HiFive1-flash.py
@@ -0,0 +1,15 @@
+import targets
+
+# Like HiFive1, but put code in flash
+
+class HiFive1FlashHart(targets.Hart):
+    xlen = 32
+    ram = 0x80000000
+    ram_size = 16 * 1024
+    instruction_hardware_breakpoint_count = 2
+    misa = 0x40001105
+    link_script_path = "HiFive1-flash.lds"
+
+class HiFive1Flash(targets.Target):
+    harts = [HiFive1FlashHart()]
+    openocd_config_path = "HiFive1.cfg"
diff --git a/apps/riscv-tests/debug/targets/SiFive/HiFive1.cfg b/apps/riscv-tests/debug/targets/SiFive/HiFive1.cfg
new file mode 100644
index 0000000..333c82e
--- /dev/null
+++ b/apps/riscv-tests/debug/targets/SiFive/HiFive1.cfg
@@ -0,0 +1,33 @@
+adapter_khz     10000
+
+interface ftdi
+ftdi_device_desc "Dual RS232-HS"
+ftdi_vid_pid 0x0403 0x6010
+
+ftdi_layout_init 0x0008 0x001b
+ftdi_layout_signal nSRST -oe 0x0020
+
+# ...
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 8096 -work-area-backup 1
+#-rtos riscv
+
+gdb_report_data_abort enable
+gdb_report_register_access_error enable
+
+# Expose an unimplemented CSR so we can test non-existent register access
+# behavior.
+riscv expose_csrs 2288
+
+flash bank my_first_flash fespi 0x20000000 0 0 0 $_TARGETNAME
+init
+#reset
+halt
+flash protect 0 64 last off
+
+echo "Ready for Remote Connections"
diff --git a/apps/riscv-tests/debug/targets/SiFive/HiFive1.lds b/apps/riscv-tests/debug/targets/SiFive/HiFive1.lds
new file mode 100644
index 0000000..a37ca0c
--- /dev/null
+++ b/apps/riscv-tests/debug/targets/SiFive/HiFive1.lds
@@ -0,0 +1,38 @@
+OUTPUT_ARCH( "riscv" )
+
+SECTIONS
+{
+  . = 0x80000000;
+  .text : 
+  {
+    *(.text.entry)
+    *(.text)
+  }
+
+  /* data segment */
+  .data : { *(.data) }
+
+  .sdata : {
+    __global_pointer$ = . + 0x800;
+    *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
+    *(.srodata*)
+    *(.sdata .sdata.* .gnu.linkonce.s.*)
+  }
+
+  /* bss segment */
+  __bss_start = .;
+  .sbss : {
+    *(.sbss .sbss.* .gnu.linkonce.sb.*)
+    *(.scommon)
+  }
+  .bss : { *(.bss) }
+  __bss_end = .;
+
+  __malloc_start = .;
+  . = . + 512;
+
+  /* End of uninitalized data segement */
+  _end = .;
+}
+
+ASSERT(_end < 0x80004000, "program is too large")
diff --git a/apps/riscv-tests/debug/targets/SiFive/HiFive1.py b/apps/riscv-tests/debug/targets/SiFive/HiFive1.py
new file mode 100644
index 0000000..3cb508c
--- /dev/null
+++ b/apps/riscv-tests/debug/targets/SiFive/HiFive1.py
@@ -0,0 +1,11 @@
+import targets
+
+class HiFive1Hart(targets.Hart):
+    xlen = 32
+    ram = 0x80000000
+    ram_size = 16 * 1024
+    instruction_hardware_breakpoint_count = 2
+    misa = 0x40001105
+
+class HiFive1(targets.Target):
+    harts = [HiFive1Hart()]
diff --git a/apps/riscv-tests/debug/targets/SiFive/HiFiveUnleashed-flash.lds b/apps/riscv-tests/debug/targets/SiFive/HiFiveUnleashed-flash.lds
new file mode 100644
index 0000000..fa30c6a
--- /dev/null
+++ b/apps/riscv-tests/debug/targets/SiFive/HiFiveUnleashed-flash.lds
@@ -0,0 +1,41 @@
+OUTPUT_ARCH( "riscv" )
+
+SECTIONS
+{
+  . = 0x20000000;
+  .text :
+  {
+    *(.text.entry)
+    *(.text)
+  }
+  _text_end = .;
+
+  . = 0x80000000;
+  /* data segment */
+  .data : { *(.data) }
+
+  .sdata : {
+    __global_pointer$ = . + 0x800;
+    *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
+    *(.srodata*)
+    *(.sdata .sdata.* .gnu.linkonce.s.*)
+  }
+
+  /* bss segment */
+  __bss_start = .;
+  .sbss : {
+    *(.sbss .sbss.* .gnu.linkonce.sb.*)
+    *(.scommon)
+  }
+  .bss : { *(.bss) }
+  __bss_end = .;
+
+  __malloc_start = .;
+  . = . + 512;
+
+  /* End of uninitalized data segement */
+  _end = .;
+}
+
+ASSERT(_text_end < 0x20100000, "program is too large")
+ASSERT(_end < 0x80100000, "program is too large")
diff --git a/apps/riscv-tests/debug/targets/SiFive/HiFiveUnleashed-flash.py b/apps/riscv-tests/debug/targets/SiFive/HiFiveUnleashed-flash.py
new file mode 100644
index 0000000..cb2741e
--- /dev/null
+++ b/apps/riscv-tests/debug/targets/SiFive/HiFiveUnleashed-flash.py
@@ -0,0 +1,22 @@
+import targets
+
+class E51(targets.Hart):
+    xlen = 64
+    ram = 0x80000000
+    ram_size = 1024 * 1024
+    instruction_hardware_breakpoint_count = 2
+    link_script_path = "HiFiveUnleashed-flash.lds"
+    reset_vectors = [0x1004]
+
+class U54(targets.Hart):
+    xlen = 64
+    ram = 0x80000000
+    ram_size = 1024 * 1024
+    instruction_hardware_breakpoint_count = 2
+    link_script_path = "HiFiveUnleashed-flash.lds"
+    reset_vectors = [0x1004]
+
+class HiFiveUnleashedFlash(targets.Target):
+    support_hasel = False
+    harts = [E51(), U54(), U54(), U54(), U54()]
+    openocd_config_path = "HiFiveUnleashed.cfg"
diff --git a/apps/riscv-tests/debug/targets/SiFive/HiFiveUnleashed.cfg b/apps/riscv-tests/debug/targets/SiFive/HiFiveUnleashed.cfg
new file mode 100644
index 0000000..3aa5538
--- /dev/null
+++ b/apps/riscv-tests/debug/targets/SiFive/HiFiveUnleashed.cfg
@@ -0,0 +1,64 @@
+adapter_khz     10000
+
+interface ftdi
+ftdi_device_desc "Dual RS232-HS"
+ftdi_vid_pid 0x0403 0x6010
+
+ftdi_layout_init 0x0008 0x001b
+ftdi_layout_signal nSRST -oe 0x0020
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000913
+
+set _TARGETNAME_0 $_CHIPNAME.cpu0
+set _TARGETNAME_1 $_CHIPNAME.cpu1
+set _TARGETNAME_2 $_CHIPNAME.cpu2
+set _TARGETNAME_3 $_CHIPNAME.cpu3
+set _TARGETNAME_4 $_CHIPNAME.cpu4
+target create $_TARGETNAME_0 riscv -chain-position $_CHIPNAME.cpu -rtos hwthread
+target create $_TARGETNAME_1 riscv -chain-position $_CHIPNAME.cpu -coreid 1
+target create $_TARGETNAME_2 riscv -chain-position $_CHIPNAME.cpu -coreid 2
+target create $_TARGETNAME_3 riscv -chain-position $_CHIPNAME.cpu -coreid 3
+target create $_TARGETNAME_4 riscv -chain-position $_CHIPNAME.cpu -coreid 4
+target smp $_TARGETNAME_0 $_TARGETNAME_1 $_TARGETNAME_2 $_TARGETNAME_3 $_TARGETNAME_4
+
+#set _TARGETNAME_0 $_CHIPNAME.cpu
+#target create $_TARGETNAME_0 riscv -chain-position $_TARGETNAME_0 -rtos riscv
+
+$_TARGETNAME_0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
+
+
+gdb_report_data_abort enable
+gdb_report_register_access_error enable
+
+# Expose an unimplemented CSR so we can test non-existent register access
+# behavior.
+riscv expose_csrs 2288
+
+flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME_0 0x10040000
+init
+
+# Clear reset on these events, because that messes with memory which we don't
+# want in these tests. We want gdb be able to "download" to flash as well as
+# RAM, and then simply execute the program.
+# This must happen after init, where blank events get overwritten with reset.
+set targets [target names]
+foreach t $targets {
+    $t configure -event gdb-flash-erase-start ""
+    $t configure -event gdb-flash-write-end ""
+}
+
+reset halt
+
+# Use a modified bootloader to configure the hardware, especially the DDR controller.
+load_image targets/SiFive/HiFiveUnleashed_setup.bin 0x08000000
+foreach t [target names] {
+    targets $t
+    reg pc 0x08000000
+}
+resume
+wait_halt
+
+# Uncomment this if you want to be able to clobber your SPI Flash, which
+# probably you don't since you can do it through Linux
+#flash protect 0 0 last off
diff --git a/apps/riscv-tests/debug/targets/SiFive/HiFiveUnleashed.lds b/apps/riscv-tests/debug/targets/SiFive/HiFiveUnleashed.lds
new file mode 100644
index 0000000..9298153
--- /dev/null
+++ b/apps/riscv-tests/debug/targets/SiFive/HiFiveUnleashed.lds
@@ -0,0 +1,38 @@
+OUTPUT_ARCH( "riscv" )
+
+SECTIONS
+{
+  . = 0x80000000;
+  .text : 
+  {
+    *(.text.entry)
+    *(.text)
+  }
+
+  /* data segment */
+  .data : { *(.data) }
+
+  .sdata : {
+    __global_pointer$ = . + 0x800;
+    *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
+    *(.srodata*)
+    *(.sdata .sdata.* .gnu.linkonce.s.*)
+  }
+
+  /* bss segment */
+  __bss_start = .;
+  .sbss : {
+    *(.sbss .sbss.* .gnu.linkonce.sb.*)
+    *(.scommon)
+  }
+  .bss : { *(.bss) }
+  __bss_end = .;
+
+  __malloc_start = .;
+  . = . + 512;
+
+  /* End of uninitalized data segement */
+  _end = .;
+}
+
+ASSERT(_end < 0x80100000, "program is too large")
diff --git a/apps/riscv-tests/debug/targets/SiFive/HiFiveUnleashed.py b/apps/riscv-tests/debug/targets/SiFive/HiFiveUnleashed.py
new file mode 100644
index 0000000..9bf7cae
--- /dev/null
+++ b/apps/riscv-tests/debug/targets/SiFive/HiFiveUnleashed.py
@@ -0,0 +1,21 @@
+import targets
+
+class E51(targets.Hart):
+    xlen = 64
+    ram = 0x80000000
+    ram_size = 1024 * 1024
+    instruction_hardware_breakpoint_count = 2
+    reset_vectors = [0x1004]
+    misa = 0x8000000000101105
+
+class U54(targets.Hart):
+    xlen = 64
+    ram = 0x80000000
+    ram_size = 1024 * 1024
+    instruction_hardware_breakpoint_count = 2
+    reset_vectors = [0x1004]
+    misa = 0x800000000014112d
+
+class HiFiveUnleashed(targets.Target):
+    support_hasel = False
+    harts = [E51(), U54(), U54(), U54(), U54()]
diff --git a/apps/riscv-tests/debug/targets/SiFive/HiFiveUnleashed_setup.bin b/apps/riscv-tests/debug/targets/SiFive/HiFiveUnleashed_setup.bin
new file mode 100755
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diff --git a/apps/riscv-tests/debug/testlib.py b/apps/riscv-tests/debug/testlib.py
new file mode 100644
index 0000000..1b90caa
--- /dev/null
+++ b/apps/riscv-tests/debug/testlib.py
@@ -0,0 +1,1194 @@
+import collections
+import os
+import os.path
+import random
+import re
+import shlex
+import subprocess
+import sys
+import tempfile
+import time
+import traceback
+import pipes
+
+import pexpect
+
+print_log_names = False
+real_stdout = sys.stdout
+
+# Note that gdb comes with its own testsuite. I was unable to figure out how to
+# run that testsuite against the spike simulator.
+
+def find_file(path):
+    for directory in (os.getcwd(), os.path.dirname(__file__)):
+        fullpath = os.path.join(directory, path)
+        relpath = os.path.relpath(fullpath)
+        if len(relpath) >= len(fullpath):
+            relpath = fullpath
+        if os.path.exists(relpath):
+            return relpath
+    return None
+
+class CompileError(Exception):
+    def __init__(self, stdout, stderr):
+        super().__init__()
+        self.stdout = stdout
+        self.stderr = stderr
+
+gcc_cmd = None
+def compile(args): # pylint: disable=redefined-builtin
+    if gcc_cmd:
+        cmd = [gcc_cmd]
+    else:
+        cmd = ["riscv64-unknown-elf-gcc"]
+    cmd.append("-g")
+    for arg in args:
+        found = find_file(arg)
+        if found:
+            cmd.append(found)
+        else:
+            cmd.append(arg)
+    header("Compile")
+    print("+", " ".join(cmd))
+    process = subprocess.Popen(cmd, stdout=subprocess.PIPE,
+                               stderr=subprocess.PIPE)
+    stdout, stderr = process.communicate()
+    if process.returncode:
+        print(stdout.decode('ascii'), end=" ")
+        print(stderr.decode('ascii'), end=" ")
+        header("")
+        raise CompileError(stdout, stderr)
+
+class Spike:
+    # pylint: disable=too-many-instance-attributes
+    # pylint: disable=too-many-locals
+    def __init__(self, target, halted=False, timeout=None, with_jtag_gdb=True,
+            isa=None, progbufsize=None, dmi_rti=None, abstract_rti=None,
+            support_hasel=True, support_abstract_csr=True,
+            support_haltgroups=True, vlen=128, elen=64, slen=128):
+        """Launch spike. Return tuple of its process and the port it's running
+        on."""
+        self.process = None
+        self.isa = isa
+        self.progbufsize = progbufsize
+        self.dmi_rti = dmi_rti
+        self.abstract_rti = abstract_rti
+        self.support_abstract_csr = support_abstract_csr
+        self.support_hasel = support_hasel
+        self.support_haltgroups = support_haltgroups
+        self.vlen = vlen
+        self.elen = elen
+        self.slen = slen
+
+        if target.harts:
+            harts = target.harts
+        else:
+            harts = [target]
+
+        cmd = self.command(target, harts, halted, timeout, with_jtag_gdb)
+        self.infinite_loop = target.compile(harts[0],
+                "programs/checksum.c", "programs/tiny-malloc.c",
+                "programs/infinite_loop.S", "-DDEFINE_MALLOC", "-DDEFINE_FREE")
+        cmd.append(self.infinite_loop)
+        self.logfile = tempfile.NamedTemporaryFile(prefix="spike-",
+                suffix=".log")
+        self.logname = self.logfile.name
+        if print_log_names:
+            real_stdout.write("Temporary spike log: %s\n" % self.logname)
+        self.logfile.write(("+ %s\n" % " ".join(cmd)).encode())
+        self.logfile.flush()
+        self.process = subprocess.Popen(cmd, stdin=subprocess.PIPE,
+                stdout=self.logfile, stderr=self.logfile)
+
+        if with_jtag_gdb:
+            self.port = None
+            for _ in range(30):
+                m = re.search(r"Listening for remote bitbang connection on "
+                        r"port (\d+).", open(self.logname).read())
+                if m:
+                    self.port = int(m.group(1))
+                    os.environ['REMOTE_BITBANG_PORT'] = m.group(1)
+                    break
+                time.sleep(0.11)
+            if not self.port:
+                print_log(self.logname)
+                raise Exception("Didn't get spike message about bitbang "
+                        "connection")
+
+    # pylint: disable=too-many-branches
+    def command(self, target, harts, halted, timeout, with_jtag_gdb):
+        # pylint: disable=no-self-use
+        if target.sim_cmd:
+            cmd = shlex.split(target.sim_cmd)
+        else:
+            cmd = ["spike"]
+
+        cmd += ["-p%d" % len(harts)]
+
+        assert len(set(t.xlen for t in harts)) == 1, \
+                "All spike harts must have the same XLEN"
+
+        if self.isa:
+            isa = self.isa
+        else:
+            isa = "RV%dG" % harts[0].xlen
+
+        cmd += ["--isa", isa]
+        cmd += ["--dm-auth"]
+
+        if not self.progbufsize is None:
+            cmd += ["--dm-progsize", str(self.progbufsize)]
+            cmd += ["--dm-sba", "32"]
+
+        if not self.dmi_rti is None:
+            cmd += ["--dmi-rti", str(self.dmi_rti)]
+
+        if not self.abstract_rti is None:
+            cmd += ["--dm-abstract-rti", str(self.abstract_rti)]
+
+        if not self.support_abstract_csr:
+            cmd.append("--dm-no-abstract-csr")
+
+        if not self.support_hasel:
+            cmd.append("--dm-no-hasel")
+
+        if not self.support_haltgroups:
+            cmd.append("--dm-no-halt-groups")
+
+        if 'V' in isa[2:]:
+            cmd.append("--varch=vlen:%d,elen:%d,slen:%d" % (self.vlen,
+                self.elen, self.slen))
+
+        assert len(set(t.ram for t in harts)) == 1, \
+                "All spike harts must have the same RAM layout"
+        assert len(set(t.ram_size for t in harts)) == 1, \
+                "All spike harts must have the same RAM layout"
+        os.environ['WORK_AREA'] = '0x%x' % harts[0].ram
+        cmd += ["-m0x%x:0x%x" % (harts[0].ram, harts[0].ram_size)]
+
+        if timeout:
+            cmd = ["timeout", str(timeout)] + cmd
+
+        if halted:
+            cmd.append('-H')
+        if with_jtag_gdb:
+            cmd += ['--rbb-port', '0']
+            os.environ['REMOTE_BITBANG_HOST'] = 'localhost'
+
+        return cmd
+
+    def __del__(self):
+        if self.process:
+            try:
+                self.process.kill()
+                self.process.wait()
+            except OSError:
+                pass
+
+    def wait(self, *args, **kwargs):
+        return self.process.wait(*args, **kwargs)
+
+class VcsSim:
+    logfile = tempfile.NamedTemporaryFile(prefix='simv', suffix='.log')
+    logname = logfile.name
+
+    def __init__(self, sim_cmd=None, debug=False, timeout=300):
+        if sim_cmd:
+            cmd = shlex.split(sim_cmd)
+        else:
+            cmd = ["simv"]
+        cmd += ["+jtag_vpi_enable"]
+        if debug:
+            cmd[0] = cmd[0] + "-debug"
+            cmd += ["+vcdplusfile=output/gdbserver.vpd"]
+
+        logfile = open(self.logname, "w")
+        if print_log_names:
+            real_stdout.write("Temporary VCS log: %s\n" % self.logname)
+        logfile.write("+ %s\n" % " ".join(cmd))
+        logfile.flush()
+
+        listenfile = open(self.logname, "r")
+        listenfile.seek(0, 2)
+        self.process = subprocess.Popen(cmd, stdin=subprocess.PIPE,
+                stdout=logfile, stderr=logfile)
+        done = False
+        start = time.time()
+        while not done:
+            # Fail if VCS exits early
+            exit_code = self.process.poll()
+            if exit_code is not None:
+                raise RuntimeError('VCS simulator exited early with status %d'
+                                   % exit_code)
+
+            line = listenfile.readline()
+            if not line:
+                time.sleep(1)
+            match = re.match(r"^Listening on port (\d+)$", line)
+            if match:
+                done = True
+                self.port = int(match.group(1))
+                os.environ['JTAG_VPI_PORT'] = str(self.port)
+
+            if (time.time() - start) > timeout:
+                raise Exception("Timed out waiting for VCS to listen for JTAG "
+                        "vpi")
+
+    def __del__(self):
+        try:
+            self.process.kill()
+            self.process.wait()
+        except OSError:
+            pass
+
+class Openocd:
+    logfile = tempfile.NamedTemporaryFile(prefix='openocd', suffix='.log')
+    logname = logfile.name
+
+    def __init__(self, server_cmd=None, config=None, debug=False, timeout=60):
+        self.timeout = timeout
+
+        if server_cmd:
+            cmd = shlex.split(server_cmd)
+        else:
+            cmd = ["openocd"]
+            if debug:
+                cmd.append("-d")
+
+        # This command needs to come before any config scripts on the command
+        # line, since they are executed in order.
+        cmd += [
+            # Tell OpenOCD to bind gdb to an unused, ephemeral port.
+            "--command",
+            "gdb_port 0",
+            # Disable tcl and telnet servers, since they are unused and because
+            # the port numbers will conflict if multiple OpenOCD processes are
+            # running on the same server.
+            "--command",
+            "tcl_port disabled",
+            "--command",
+            "telnet_port disabled",
+        ]
+
+        if config:
+            self.config_file = find_file(config)
+            if self.config_file is None:
+                print("Unable to read file", config)
+                sys.exit(1)
+
+            cmd += ["-f", self.config_file]
+        if debug:
+            cmd.append("-d")
+
+        raw_logfile = open(Openocd.logname, "wb")
+        try:
+            spike_dasm = subprocess.Popen("spike-dasm", stdin=subprocess.PIPE,
+                    stdout=raw_logfile, stderr=raw_logfile)
+            logfile = spike_dasm.stdin
+        except FileNotFoundError:
+            logfile = raw_logfile
+        if print_log_names:
+            real_stdout.write("Temporary OpenOCD log: %s\n" % Openocd.logname)
+        env_entries = ("REMOTE_BITBANG_HOST", "REMOTE_BITBANG_PORT",
+                "WORK_AREA")
+        env_entries = [key for key in env_entries if key in os.environ]
+        logfile.write(("+ %s%s\n" % (
+            "".join("%s=%s " % (key, os.environ[key]) for key in env_entries),
+            " ".join(map(pipes.quote, cmd)))).encode())
+        logfile.flush()
+
+        self.gdb_ports = []
+        self.process = self.start(cmd, logfile)
+
+    def start(self, cmd, logfile):
+        process = subprocess.Popen(cmd, stdin=subprocess.PIPE,
+                stdout=logfile, stderr=logfile)
+
+        try:
+            # Wait for OpenOCD to have made it through riscv_examine(). When
+            # using OpenOCD to communicate with a simulator this may take a
+            # long time, and gdb will time out when trying to connect if we
+            # attempt too early.
+            start = time.time()
+            messaged = False
+            fd = open(Openocd.logname, "r")
+            while True:
+                line = fd.readline()
+                if not line:
+                    if not process.poll() is None:
+                        raise Exception("OpenOCD exited early.")
+                    time.sleep(0.1)
+                    continue
+
+                m = re.search(r"Listening on port (\d+) for gdb connections",
+                        line)
+                if m:
+                    self.gdb_ports.append(int(m.group(1)))
+
+                if "telnet server disabled" in line:
+                    return process
+
+                if not messaged and time.time() - start > 1:
+                    messaged = True
+                    print("Waiting for OpenOCD to start...")
+                if (time.time() - start) > self.timeout:
+                    raise Exception("Timed out waiting for OpenOCD to "
+                            "listen for gdb")
+
+        except Exception:
+            print_log(Openocd.logname)
+            raise
+
+    def __del__(self):
+        try:
+            self.process.terminate()
+            start = time.time()
+            while time.time() < start + 10:
+                if self.process.poll():
+                    break
+            else:
+                self.process.kill()
+        except (OSError, AttributeError):
+            pass
+
+    def smp(self):
+        """Return true iff OpenOCD internally sees the harts as part of an SMP
+        group."""
+        for line in open(self.config_file, "r"):
+            if "target smp" in line:
+                return True
+        return False
+
+class OpenocdCli:
+    def __init__(self, port=4444):
+        self.child = pexpect.spawn(
+                "sh -c 'telnet localhost %d | tee openocd-cli.log'" % port)
+        self.child.expect("> ")
+
+    def command(self, cmd):
+        self.child.sendline(cmd)
+        self.child.expect(cmd)
+        self.child.expect("\n")
+        self.child.expect("> ")
+        return self.child.before.strip("\t\r\n \0").decode("utf-8")
+
+    def reg(self, reg=''):
+        output = self.command("reg %s" % reg)
+        matches = re.findall(r"(\w+) \(/\d+\): (0x[0-9A-F]+)", output)
+        values = {r: int(v, 0) for r, v in matches}
+        if reg:
+            return values[reg]
+        return values
+
+    def load_image(self, image):
+        output = self.command("load_image %s" % image)
+        if 'invalid ELF file, only 32bits files are supported' in output:
+            raise TestNotApplicable(output)
+
+class CannotAccess(Exception):
+    def __init__(self, address):
+        Exception.__init__(self)
+        self.address = address
+
+class CannotInsertBreakpoint(Exception):
+    def __init__(self, number):
+        Exception.__init__(self)
+        self.number = number
+
+class CouldNotFetch(Exception):
+    def __init__(self, regname, explanation):
+        Exception.__init__(self)
+        self.regname = regname
+        self.explanation = explanation
+
+class NoSymbol(Exception):
+    def __init__(self, symbol):
+        Exception.__init__(self)
+        self.symbol = symbol
+
+Thread = collections.namedtuple('Thread', ('id', 'description', 'target_id',
+    'name', 'frame'))
+
+class Repeat:
+    def __init__(self, count):
+        self.count = count
+
+def tokenize(text):
+    index = 0
+    while index < len(text):
+        for regex, fn in (
+                (r"[\s]+", lambda m: None),
+                (r"[,{}=]", lambda m: m.group(0)),
+                (r"0x[\da-fA-F]+", lambda m: int(m.group(0)[2:], 16)),
+                (r"-?\d*\.\d+(e[-+]\d+)?", lambda m: float(m.group(0))),
+                (r"-?\d+", lambda m: int(m.group(0))),
+                (r"-?nan\(0x[a-f0-9]+\)", lambda m: float("nan")),
+                (r"<repeats (\d+) times>", lambda m: Repeat(int(m.group(1)))),
+                (r"Could not fetch register \"(\w+)\"; (.*)$",
+                    lambda m: CouldNotFetch(m.group(1), m.group(2))),
+                (r"Cannot access memory at address (0x[0-9a-f]+)",
+                    lambda m: CannotAccess(int(m.group(1), 0))),
+                (r"Cannot insert breakpoint (\d+).",
+                    lambda m: CannotInsertBreakpoint(int(m.group(1)))),
+                (r'No symbol "(\w+)" in current context.',
+                    lambda m: NoSymbol(m.group(1))),
+                (r'"([^"]*)"', lambda m: m.group(1)),
+                (r"[a-zA-Z][a-zA-Z\d]*", lambda m: m.group(0)),
+                ):
+            m = re.match(regex, text[index:])
+            if m:
+                index += len(m.group(0))
+                token = fn(m)
+                if not token is None:
+                    yield token
+                break
+        else:
+            raise Exception(repr(text[index:]))
+
+def parse_dict(tokens):
+    assert tokens[0] == "{"
+    tokens.pop(0)
+    result = {}
+    while True:
+        key = tokens.pop(0)
+        assert tokens.pop(0) == "="
+        value = parse_tokens(tokens)
+        result[key] = value
+        token = tokens.pop(0)
+        if token == "}":
+            return result
+        assert token == ","
+
+def parse_list(tokens):
+    assert tokens[0] == "{"
+    tokens.pop(0)
+    result = []
+    while True:
+        result.append(tokens.pop(0))
+        token = tokens.pop(0)
+        if isinstance(token, Repeat):
+            result += [result[-1]] * (token.count - 1)
+            token = tokens.pop(0)
+        if token == "}":
+            return result
+        assert token == ","
+
+def parse_dict_or_list(tokens):
+    assert tokens[0] == "{"
+    if tokens[2] == "=":
+        return parse_dict(tokens)
+    else:
+        return parse_list(tokens)
+
+def parse_tokens(tokens):
+    if isinstance(tokens[0], Exception):
+        raise tokens[0]
+    if isinstance(tokens[0], (float, int)):
+        return tokens.pop(0)
+    if tokens[0] == "{":
+        return parse_dict_or_list(tokens)
+    if isinstance(tokens[0], str):
+        return tokens.pop(0)
+    raise Exception("Unsupported tokens: %r" % tokens)
+
+def parse_rhs(text):
+    tokens = list(tokenize(text))
+    result = parse_tokens(tokens)
+    if tokens:
+        raise Exception("Unexpected input: %r" % tokens)
+    return result
+
+class Gdb:
+    """A single gdb class which can interact with one or more gdb instances."""
+
+    # pylint: disable=too-many-public-methods
+    # pylint: disable=too-many-instance-attributes
+
+    reset_delays = (127, 181, 17, 13, 83, 151, 31, 67, 131, 167, 23, 41, 61,
+            11, 149, 107, 163, 73, 47, 43, 173, 7, 109, 101, 103, 191, 2, 139,
+            97, 193, 157, 3, 29, 79, 113, 5, 89, 19, 37, 71, 179, 59, 137, 53)
+
+    def __init__(self, ports,
+            cmd="riscv64-unknown-elf-gdb",
+            timeout=60, binary=None):
+        assert ports
+
+        self.ports = ports
+        self.cmd = cmd
+        self.timeout = timeout
+        self.binary = binary
+
+        self.reset_delay_index = 0
+        self.stack = []
+        self.harts = {}
+
+        self.logfiles = []
+        self.children = []
+        for port in ports:
+            logfile = tempfile.NamedTemporaryFile(prefix="gdb@%d-" % port,
+                    suffix=".log")
+            self.logfiles.append(logfile)
+            if print_log_names:
+                real_stdout.write("Temporary gdb log: %s\n" % logfile.name)
+            child = pexpect.spawn(cmd)
+            child.logfile = logfile
+            child.logfile.write(("+ %s\n" % cmd).encode())
+            self.children.append(child)
+        self.active_child = self.children[0]
+
+    def connect(self):
+        for port, child in zip(self.ports, self.children):
+            self.select_child(child)
+            self.wait()
+            self.command("set style enabled off")
+            self.command("set confirm off")
+            self.command("set width 0")
+            self.command("set height 0")
+            # Force consistency.
+            self.command("set print entry-values no")
+            self.command("set remotetimeout %d" % self.timeout)
+            self.command("target extended-remote localhost:%d" % port, ops=10)
+            if self.binary:
+                self.command("file %s" % self.binary)
+            threads = self.threads()
+            for t in threads:
+                hartid = None
+                if t.name:
+                    m = re.search(r"Hart (\d+)", t.name)
+                    if m:
+                        hartid = int(m.group(1))
+                if hartid is None:
+                    if self.harts:
+                        hartid = max(self.harts) + 1
+                    else:
+                        hartid = 0
+                # solo: True iff this is the only thread on this child
+                self.harts[hartid] = {'child': child,
+                        'thread': t,
+                        'solo': len(threads) == 1}
+
+    def __del__(self):
+        for child in self.children:
+            del child
+
+    def one_hart_per_gdb(self):
+        return all(h['solo'] for h in self.harts.values())
+
+    def lognames(self):
+        return [logfile.name for logfile in self.logfiles]
+
+    def select_child(self, child):
+        self.active_child = child
+
+    def select_hart(self, hart):
+        h = self.harts[hart.id]
+        self.select_child(h['child'])
+        if not h['solo']:
+            output = self.command("thread %s" % h['thread'].id, ops=5)
+            assert "Unknown" not in output
+
+    def push_state(self):
+        self.stack.append({
+            'active_child': self.active_child
+            })
+
+    def pop_state(self):
+        state = self.stack.pop()
+        self.active_child = state['active_child']
+
+    def wait(self):
+        """Wait for prompt."""
+        self.active_child.expect(r"\(gdb\)")
+
+    def command(self, command, ops=1, reset_delays=0):
+        """ops is the estimated number of operations gdb will have to perform
+        to perform this command. It is used to compute a timeout based on
+        self.timeout."""
+        if not reset_delays is None:
+            if reset_delays == 0:
+                reset_delays = self.reset_delays[self.reset_delay_index]
+                self.reset_delay_index = (self.reset_delay_index + 1) % \
+                        len(self.reset_delays)
+            self.command("monitor riscv reset_delays %d" % reset_delays,
+                    reset_delays=None)
+        timeout = ops * self.timeout
+        self.active_child.sendline(command)
+        self.active_child.expect("\n", timeout=timeout)
+        self.active_child.expect(r"\(gdb\)", timeout=timeout)
+        return self.active_child.before.strip().decode("utf-8")
+
+    def global_command(self, command):
+        """Execute this command on every gdb that we control."""
+        with PrivateState(self):
+            for child in self.children:
+                self.select_child(child)
+                self.command(command)
+
+    def c(self, wait=True, sync=True, checkOutput=True, ops=20):
+        """
+        Dumb c command.
+        In RTOS mode, gdb will resume all harts.
+        In multi-gdb mode, this command will just go to the current gdb, so
+        will only resume one hart.
+        """
+        if sync:
+            sync = ""
+        else:
+            sync = "&"
+        if wait:
+            output = self.command("c%s" % sync, ops=ops)
+            if checkOutput:
+                assert "Continuing" in output
+                assert "Could not insert hardware" not in output
+            return output
+        else:
+            self.active_child.sendline("c%s" % sync)
+            self.active_child.expect("Continuing", timeout=ops * self.timeout)
+            return ""
+
+    def c_all(self, wait=True):
+        """
+        Resume every hart.
+
+        This function works fine when using multiple gdb sessions, but the
+        caller must be careful when using it nonetheless. gdb's behavior is to
+        not set breakpoints until just before the hart is resumed, and then
+        clears them as soon as the hart halts. That means that you can't set
+        one software breakpoint, and expect multiple harts to hit it. It's
+        possible that the first hart completes set/run/halt/clear before the
+        second hart even gets to resume, so it will never hit the breakpoint.
+        """
+        with PrivateState(self):
+            for child in self.children:
+                child.sendline("c")
+                child.expect("Continuing")
+
+            if wait:
+                for child in self.children:
+                    child.expect(r"\(gdb\)")
+
+    def interrupt(self, ops=1):
+        self.active_child.send("\003")
+        self.active_child.expect(r"\(gdb\)", timeout=self.timeout * ops)
+        return self.active_child.before.strip().decode()
+
+    def interrupt_all(self):
+        for child in self.children:
+            self.select_child(child)
+            self.interrupt()
+
+    def x(self, address, size='w', count=1):
+        output = self.command("x/%d%s %s" % (count, size, address))
+        values = []
+        for line in output.splitlines():
+            for value in line.split(':')[1].strip().split():
+                values.append(int(value, 0))
+        if len(values) == 1:
+            return values[0]
+        return values
+
+    def p_raw(self, obj):
+        output = self.command("p %s" % obj)
+        m = re.search("Cannot access memory at address (0x[0-9a-f]+)", output)
+        if m:
+            raise CannotAccess(int(m.group(1), 0))
+        return output.split('=', 1)[-1].strip()
+
+    def p(self, obj, fmt="/x", ops=1):
+        output = self.command("p%s %s" % (fmt, obj), ops=ops).splitlines()[-1]
+        rhs = output.split('=', 1)[-1]
+        return parse_rhs(rhs)
+
+    def p_fpr(self, obj, ops=1):
+        result = self.p(obj, fmt="", ops=ops)
+        if isinstance(result, dict):
+            return result['double']
+        return result
+
+    def p_string(self, obj):
+        output = self.command("p %s" % obj)
+        value = shlex.split(output.split('=')[-1].strip())[1]
+        return value
+
+    def info_registers(self, group):
+        output = self.command("info registers %s" % group, ops=5)
+        result = {}
+        for line in output.splitlines():
+            m = re.match(r"(\w+)\s+({.*})(?:\s+(\(.*\)))?", line)
+            if m:
+                parts = m.groups()
+            else:
+                parts = line.split()
+            name = parts[0]
+            if "Could not fetch" in line:
+                result[name] = " ".join(parts[1:])
+            else:
+                result[name] = parse_rhs(parts[1])
+        return result
+
+    def stepi(self):
+        output = self.command("stepi", ops=10)
+        return output
+
+    def load(self):
+        output = self.command("load", ops=1000)
+        assert "failed" not in  output
+        assert "Transfer rate" in output
+        output = self.command("compare-sections", ops=1000)
+        assert "matched" in output
+        assert "MIS" not in output
+
+    def b(self, location):
+        output = self.command("b %s" % location, ops=5)
+        assert "not defined" not in output
+        assert "Breakpoint" in output
+        m = re.search(r"Breakpoint (\d+),? ", output)
+        assert m, output
+        return int(m.group(1))
+
+    def hbreak(self, location):
+        output = self.command("hbreak %s" % location, ops=5)
+        assert "not defined" not in output
+        assert "Hardware assisted breakpoint" in output
+        return output
+
+    def watch(self, expr):
+        output = self.command("watch %s" % expr, ops=5)
+        assert "not defined" not in output
+        assert "atchpoint" in output
+        return output
+
+    def swatch(self, expr):
+        self.command("show can-use-hw-watchpoints")
+        self.command("set can-use-hw-watchpoints 0")
+        output = self.command("watch %s" % expr, ops=5)
+        assert "not defined" not in output
+        assert "atchpoint" in output
+        self.command("set can-use-hw-watchpoints 1")
+        return output
+
+    def threads(self):
+        output = self.command("info threads", ops=100)
+        threads = []
+        for line in output.splitlines():
+            m = re.match(
+                    r"[\s\*]*(\d+)\s*"
+                    r"(Remote target|Thread (\d+)\s*\(Name: ([^\)]+))"
+                    r"\s*(.*)", line)
+            if m:
+                threads.append(Thread(*m.groups()))
+        assert threads
+        #>>>if not threads:
+        #>>>    threads.append(Thread('1', '1', 'Default', '???'))
+        return threads
+
+    def thread(self, thread):
+        return self.command("thread %s" % thread.id)
+
+    def where(self):
+        return self.command("where 1")
+
+class PrivateState:
+    def __init__(self, gdb):
+        self.gdb = gdb
+
+    def __enter__(self):
+        self.gdb.push_state()
+
+    def __exit__(self, _type, _value, _traceback):
+        self.gdb.pop_state()
+
+def run_all_tests(module, target, parsed):
+    todo = []
+    for name in dir(module):
+        definition = getattr(module, name)
+        if isinstance(definition, type) and hasattr(definition, 'test') and \
+                (not parsed.test or any(test in name for test in parsed.test)):
+            todo.append((name, definition, None))
+
+    if parsed.list_tests:
+        for name, definition, hart in todo:
+            print(name)
+        return 0
+
+    try:
+        os.makedirs(parsed.logs)
+    except OSError:
+        # There's a race where multiple instances of the test program might
+        # decide to create the logs directory at the same time.
+        pass
+
+    overall_start = time.time()
+
+    global gdb_cmd  # pylint: disable=global-statement
+    gdb_cmd = parsed.gdb
+    global gcc_cmd  # pylint: disable=global-statement
+    gcc_cmd = parsed.gcc
+
+    examine_added = False
+    for hart in target.harts:
+        if parsed.misaval:
+            hart.misa = int(parsed.misaval, 16)
+            print("Using $misa from command line: 0x%x" % hart.misa)
+        elif hart.misa:
+            print("Using $misa from hart definition: 0x%x" % hart.misa)
+        elif not examine_added:
+            todo.insert(0, ("ExamineTarget", ExamineTarget, None))
+            examine_added = True
+
+    results, count = run_tests(parsed, target, todo)
+
+    header("ran %d tests in %.0fs" % (count, time.time() - overall_start),
+            dash=':')
+
+    return print_results(results)
+
+good_results = set(('pass', 'not_applicable'))
+def run_tests(parsed, target, todo):
+    results = {}
+    count = 0
+
+    for name, definition, hart in todo:
+        log_name = os.path.join(parsed.logs, "%s-%s-%s.log" %
+                (time.strftime("%Y%m%d-%H%M%S"), type(target).__name__, name))
+        log_fd = open(log_name, 'w')
+        print("[%s] Starting > %s" % (name, log_name))
+        instance = definition(target, hart)
+        sys.stdout.flush()
+        log_fd.write("Test: %s\n" % name)
+        log_fd.write("Target: %s\n" % type(target).__name__)
+        start = time.time()
+        global real_stdout  # pylint: disable=global-statement
+        real_stdout = sys.stdout
+        sys.stdout = log_fd
+        try:
+            result = instance.run()
+            log_fd.write("Result: %s\n" % result)
+            log_fd.write("Logfile: %s\n" % log_name)
+            log_fd.write("Reproduce: %s %s %s\n" % (sys.argv[0], parsed.target,
+                name))
+        finally:
+            sys.stdout = real_stdout
+            log_fd.write("Time elapsed: %.2fs\n" % (time.time() - start))
+            log_fd.flush()
+        print("[%s] %s in %.2fs" % (name, result, time.time() - start))
+        if result not in good_results and parsed.print_failures:
+            sys.stdout.write(open(log_name).read())
+        sys.stdout.flush()
+        results.setdefault(result, []).append((name, log_name))
+        count += 1
+        if result not in good_results and parsed.fail_fast:
+            break
+
+    return results, count
+
+def print_results(results):
+    result = 0
+    for key, value in results.items():
+        print("%d tests returned %s" % (len(value), key))
+        if key not in good_results:
+            result = 1
+            for name, log_name in value:
+                print("   %s > %s" % (name, log_name))
+
+    return result
+
+def add_test_run_options(parser):
+    parser.add_argument("--logs", default="logs",
+            help="Store logs in the specified directory.")
+    parser.add_argument("--fail-fast", "-f", action="store_true",
+            help="Exit as soon as any test fails.")
+    parser.add_argument("--print-failures", action="store_true",
+            help="When a test fails, print the log file to stdout.")
+    parser.add_argument("--print-log-names", "--pln", action="store_true",
+            help="Print names of temporary log files as soon as they are "
+            "created.")
+    parser.add_argument("--list-tests", action="store_true",
+            help="Print out a list of tests, and exit immediately.")
+    parser.add_argument("test", nargs='*',
+            help="Run only tests that are named here.")
+    parser.add_argument("--gcc",
+            help="The command to use to start gcc.")
+    parser.add_argument("--gdb",
+            help="The command to use to start gdb.")
+    parser.add_argument("--misaval",
+            help="Don't run ExamineTarget, just assume the misa value which is "
+            "specified.")
+
+def header(title, dash='-', length=78):
+    if title:
+        dashes = dash * (length - 4 - len(title))
+        before = dashes[:len(dashes)//2]
+        after = dashes[len(dashes)//2:]
+        print("%s[ %s ]%s" % (before, title, after))
+    else:
+        print(dash * length)
+
+def print_log_handle(name, handle):
+    header(name)
+    for l in handle:
+        sys.stdout.write(l)
+    print()
+
+def print_log(path):
+    print_log_handle(path, open(path, "r"))
+
+class BaseTest:
+    compiled = {}
+
+    def __init__(self, target, hart=None):
+        self.target = target
+        if hart:
+            self.hart = hart
+        else:
+            self.hart = random.choice(target.harts)
+        self.server = None
+        self.target_process = None
+        self.binary = None
+        self.start = 0
+        self.logs = []
+
+    def early_applicable(self):
+        """Return a false value if the test has determined it cannot run
+        without ever needing to talk to the target or server."""
+        # pylint: disable=no-self-use
+        return True
+
+    def setup(self):
+        pass
+
+    def compile(self):
+        compile_args = getattr(self, 'compile_args', None)
+        if compile_args:
+            if compile_args not in BaseTest.compiled:
+                BaseTest.compiled[compile_args] = \
+                        self.target.compile(self.hart, *compile_args)
+        self.binary = BaseTest.compiled.get(compile_args)
+
+    def classSetup(self):
+        self.compile()
+        self.target_process = self.target.create()
+        if self.target_process:
+            self.logs.append(self.target_process.logname)
+        try:
+            self.server = self.target.server()
+            self.logs.append(self.server.logname)
+        except Exception:
+            for log in self.logs:
+                print_log(log)
+            raise
+
+    def classTeardown(self):
+        del self.server
+        del self.target_process
+
+    def postMortem(self):
+        pass
+
+    def run(self):
+        """
+        If compile_args is set, compile a program and set self.binary.
+
+        Call setup().
+
+        Then call test() and return the result, displaying relevant information
+        if an exception is raised.
+        """
+
+        sys.stdout.flush()
+
+        if self.__class__.__name__ in self.target.skip_tests or \
+                not self.early_applicable():
+            return "not_applicable"
+
+        self.start = time.time()
+
+        try:
+            self.classSetup()
+            self.setup()
+            result = self.test()    # pylint: disable=no-member
+        except TestNotApplicable:
+            result = "not_applicable"
+        except Exception as e: # pylint: disable=broad-except
+            if isinstance(e, TestFailed):
+                result = "fail"
+            else:
+                result = "exception"
+            if isinstance(e, TestFailed):
+                # pylint: disable=no-member
+                header("Message")
+                print(e.message)
+            header("Traceback")
+            traceback.print_exc(file=sys.stdout)
+            try:
+                self.postMortem()
+            except Exception as e:  # pylint: disable=broad-except
+                header("postMortem Exception")
+                print(e)
+                traceback.print_exc(file=sys.stdout)
+            return result
+
+        finally:
+            # Get handles to logs before the files are deleted.
+            logs = []
+            for log in self.logs:
+                logs.append((log, open(log, "r")))
+
+            self.classTeardown()
+            for name, handle in logs:
+                print_log_handle(name, handle)
+            header("End of logs")
+
+        if not result:
+            result = 'pass'
+        return result
+
+gdb_cmd = None
+class GdbTest(BaseTest):
+    def __init__(self, target, hart=None):
+        BaseTest.__init__(self, target, hart=hart)
+        self.gdb = None
+
+    def write_nop_program(self, count):
+        for i in range(count):
+            # 0x13 is nop
+            self.gdb.command("p *((int*) 0x%x)=0x13" % (self.hart.ram + i * 4))
+        self.gdb.p("$pc=0x%x" % self.hart.ram)
+
+    def classSetup(self):
+        BaseTest.classSetup(self)
+
+        if gdb_cmd:
+            self.gdb = Gdb(self.server.gdb_ports, gdb_cmd,
+                    timeout=self.target.timeout_sec, binary=self.binary)
+        else:
+            self.gdb = Gdb(self.server.gdb_ports,
+                    timeout=self.target.timeout_sec, binary=self.binary)
+
+        self.logs += self.gdb.lognames()
+        self.gdb.connect()
+
+        self.gdb.global_command("set remotetimeout %d" %
+            self.target.timeout_sec)
+
+        for cmd in self.target.gdb_setup:
+            self.gdb.command(cmd)
+
+        self.gdb.select_hart(self.hart)
+
+        # FIXME: OpenOCD doesn't handle PRIV now
+        #self.gdb.p("$priv=3")
+
+    def postMortem(self):
+        if not self.gdb:
+            return
+        self.gdb.interrupt()
+        self.gdb.command("info breakpoints", reset_delays=None)
+        self.gdb.command("disassemble", ops=20, reset_delays=None)
+        self.gdb.command("info registers all", ops=20, reset_delays=None)
+        self.gdb.command("flush regs", reset_delays=None)
+        self.gdb.command("info threads", ops=20, reset_delays=None)
+
+    def classTeardown(self):
+        del self.gdb
+        BaseTest.classTeardown(self)
+
+    def parkOtherHarts(self):
+        """Park harts besides the currently selected one in loop_forever()."""
+        for hart in self.target.harts:
+            # Park all harts that we're not using in a safe place.
+            if hart != self.hart:
+                self.gdb.select_hart(hart)
+                self.gdb.p("$pc=loop_forever")
+
+        self.gdb.select_hart(self.hart)
+
+    def disable_pmp(self):
+        # Disable physical memory protection by allowing U mode access to all
+        # memory.
+        try:
+            self.gdb.p("$pmpcfg0=0xf")  # TOR, R, W, X
+            self.gdb.p("$pmpaddr0=0x%x" %
+                    ((self.hart.ram + self.hart.ram_size) >> 2))
+        except CouldNotFetch:
+            # PMP registers are optional
+            pass
+
+class GdbSingleHartTest(GdbTest):
+    def classSetup(self):
+        GdbTest.classSetup(self)
+        self.parkOtherHarts()
+
+class ExamineTarget(GdbTest):
+    def test(self):
+        for hart in self.target.harts:
+            self.gdb.select_hart(hart)
+
+            hart.misa = self.gdb.p("$misa")
+
+            txt = "RV"
+            misa_xlen = 0
+            if ((hart.misa & 0xFFFFFFFF) >> 30) == 1:
+                misa_xlen = 32
+            elif ((hart.misa & 0xFFFFFFFFFFFFFFFF) >> 62) == 2:
+                misa_xlen = 64
+            elif ((hart.misa & 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF) >> 126) == 3:
+                misa_xlen = 128
+            else:
+                raise TestFailed("Couldn't determine XLEN from $misa (0x%x)" %
+                        self.hart.misa)
+
+            if misa_xlen != hart.xlen:
+                raise TestFailed("MISA reported XLEN of %d but we were "\
+                        "expecting XLEN of %d\n" % (misa_xlen, hart.xlen))
+
+            txt += ("%d" % misa_xlen)
+
+            for i in range(26):
+                if hart.misa & (1<<i):
+                    txt += chr(i + ord('A'))
+            print(txt, end=" ")
+
+class TestFailed(Exception):
+    def __init__(self, message, comment=None):
+        Exception.__init__(self)
+        self.message = message
+        if comment:
+            self.message += ": %s" % comment
+
+class TestNotApplicable(Exception):
+    def __init__(self, message=""):
+        Exception.__init__(self)
+        self.message = message
+
+def assertEqual(a, b):
+    if a != b:
+        raise TestFailed("%r != %r" % (a, b))
+
+def assertNotEqual(a, b, comment=None):
+    if a == b:
+        raise TestFailed("%r == %r" % (a, b), comment)
+
+def assertIn(a, b):
+    if a not in b:
+        raise TestFailed("%r not in %r" % (a, b))
+
+def assertNotIn(a, b, comment=None):
+    if a in b:
+        raise TestFailed("%r in %r" % (a, b), comment)
+
+def assertGreater(a, b):
+    if not a > b:
+        raise TestFailed("%r not greater than %r" % (a, b))
+
+def assertLess(a, b, comment=None):
+    if not a < b:
+        raise TestFailed("%r not less than %r" % (a, b), comment)
+
+def assertTrue(a):
+    if not a:
+        raise TestFailed("%r is not True" % a)
+
+def assertRegex(text, regexp):
+    if not re.search(regexp, text):
+        raise TestFailed("can't find %r in %r" % (regexp, text))
diff --git a/apps/riscv-tests/env/LICENSE b/apps/riscv-tests/env/LICENSE
new file mode 100644
index 0000000..48fe522
--- /dev/null
+++ b/apps/riscv-tests/env/LICENSE
@@ -0,0 +1,24 @@
+Copyright (c) 2012-2015, The Regents of the University of California (Regents).
+All Rights Reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+1. Redistributions of source code must retain the above copyright
+   notice, this list of conditions and the following disclaimer.
+2. Redistributions in binary form must reproduce the above copyright
+   notice, this list of conditions and the following disclaimer in the
+   documentation and/or other materials provided with the distribution.
+3. Neither the name of the Regents nor the
+   names of its contributors may be used to endorse or promote products
+   derived from this software without specific prior written permission.
+
+IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,
+SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING
+OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS
+BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED
+HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE
+MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
diff --git a/apps/riscv-tests/env/encoding.h b/apps/riscv-tests/env/encoding.h
new file mode 100644
index 0000000..584bc27
--- /dev/null
+++ b/apps/riscv-tests/env/encoding.h
@@ -0,0 +1,2828 @@
+/* See LICENSE for license details. */
+
+#ifndef RISCV_CSR_ENCODING_H
+#define RISCV_CSR_ENCODING_H
+
+#define MSTATUS_UIE         0x00000001
+#define MSTATUS_SIE         0x00000002
+#define MSTATUS_HIE         0x00000004
+#define MSTATUS_MIE         0x00000008
+#define MSTATUS_UPIE        0x00000010
+#define MSTATUS_SPIE        0x00000020
+#define MSTATUS_HPIE        0x00000040
+#define MSTATUS_MPIE        0x00000080
+#define MSTATUS_SPP         0x00000100
+#define MSTATUS_VS          0x00000600
+#define MSTATUS_MPP         0x00001800
+#define MSTATUS_FS          0x00006000
+#define MSTATUS_XS          0x00018000
+#define MSTATUS_MPRV        0x00020000
+#define MSTATUS_SUM         0x00040000
+#define MSTATUS_MXR         0x00080000
+#define MSTATUS_TVM         0x00100000
+#define MSTATUS_TW          0x00200000
+#define MSTATUS_TSR         0x00400000
+#define MSTATUS32_SD        0x80000000
+#define MSTATUS_UXL         0x0000000300000000
+#define MSTATUS_SXL         0x0000000C00000000
+#define MSTATUS64_SD        0x8000000000000000
+
+#define SSTATUS_UIE         0x00000001
+#define SSTATUS_SIE         0x00000002
+#define SSTATUS_UPIE        0x00000010
+#define SSTATUS_SPIE        0x00000020
+#define SSTATUS_SPP         0x00000100
+#define SSTATUS_VS          0x00000600
+#define SSTATUS_FS          0x00006000
+#define SSTATUS_XS          0x00018000
+#define SSTATUS_SUM         0x00040000
+#define SSTATUS_MXR         0x00080000
+#define SSTATUS32_SD        0x80000000
+#define SSTATUS_UXL         0x0000000300000000
+#define SSTATUS64_SD        0x8000000000000000
+
+#define USTATUS_UIE         0x00000001
+#define USTATUS_UPIE        0x00000010
+
+#define DCSR_XDEBUGVER      (3U<<30)
+#define DCSR_NDRESET        (1<<29)
+#define DCSR_FULLRESET      (1<<28)
+#define DCSR_EBREAKM        (1<<15)
+#define DCSR_EBREAKH        (1<<14)
+#define DCSR_EBREAKS        (1<<13)
+#define DCSR_EBREAKU        (1<<12)
+#define DCSR_STOPCYCLE      (1<<10)
+#define DCSR_STOPTIME       (1<<9)
+#define DCSR_CAUSE          (7<<6)
+#define DCSR_DEBUGINT       (1<<5)
+#define DCSR_HALT           (1<<3)
+#define DCSR_STEP           (1<<2)
+#define DCSR_PRV            (3<<0)
+
+#define DCSR_CAUSE_NONE     0
+#define DCSR_CAUSE_SWBP     1
+#define DCSR_CAUSE_HWBP     2
+#define DCSR_CAUSE_DEBUGINT 3
+#define DCSR_CAUSE_STEP     4
+#define DCSR_CAUSE_HALT     5
+
+#define MCONTROL_TYPE(xlen)    (0xfULL<<((xlen)-4))
+#define MCONTROL_DMODE(xlen)   (1ULL<<((xlen)-5))
+#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11))
+
+#define MCONTROL_SELECT     (1<<19)
+#define MCONTROL_TIMING     (1<<18)
+#define MCONTROL_ACTION     (0x3f<<12)
+#define MCONTROL_CHAIN      (1<<11)
+#define MCONTROL_MATCH      (0xf<<7)
+#define MCONTROL_M          (1<<6)
+#define MCONTROL_H          (1<<5)
+#define MCONTROL_S          (1<<4)
+#define MCONTROL_U          (1<<3)
+#define MCONTROL_EXECUTE    (1<<2)
+#define MCONTROL_STORE      (1<<1)
+#define MCONTROL_LOAD       (1<<0)
+
+#define MCONTROL_TYPE_NONE      0
+#define MCONTROL_TYPE_MATCH     2
+
+#define MCONTROL_ACTION_DEBUG_EXCEPTION   0
+#define MCONTROL_ACTION_DEBUG_MODE        1
+#define MCONTROL_ACTION_TRACE_START       2
+#define MCONTROL_ACTION_TRACE_STOP        3
+#define MCONTROL_ACTION_TRACE_EMIT        4
+
+#define MCONTROL_MATCH_EQUAL     0
+#define MCONTROL_MATCH_NAPOT     1
+#define MCONTROL_MATCH_GE        2
+#define MCONTROL_MATCH_LT        3
+#define MCONTROL_MATCH_MASK_LOW  4
+#define MCONTROL_MATCH_MASK_HIGH 5
+
+#define MIP_USIP            (1 << IRQ_U_SOFT)
+#define MIP_SSIP            (1 << IRQ_S_SOFT)
+#define MIP_HSIP            (1 << IRQ_H_SOFT)
+#define MIP_MSIP            (1 << IRQ_M_SOFT)
+#define MIP_UTIP            (1 << IRQ_U_TIMER)
+#define MIP_STIP            (1 << IRQ_S_TIMER)
+#define MIP_HTIP            (1 << IRQ_H_TIMER)
+#define MIP_MTIP            (1 << IRQ_M_TIMER)
+#define MIP_UEIP            (1 << IRQ_U_EXT)
+#define MIP_SEIP            (1 << IRQ_S_EXT)
+#define MIP_HEIP            (1 << IRQ_H_EXT)
+#define MIP_MEIP            (1 << IRQ_M_EXT)
+
+#define SIP_SSIP MIP_SSIP
+#define SIP_STIP MIP_STIP
+
+#define PRV_U 0
+#define PRV_S 1
+#define PRV_H 2
+#define PRV_M 3
+
+#define SATP32_MODE 0x80000000
+#define SATP32_ASID 0x7FC00000
+#define SATP32_PPN  0x003FFFFF
+#define SATP64_MODE 0xF000000000000000
+#define SATP64_ASID 0x0FFFF00000000000
+#define SATP64_PPN  0x00000FFFFFFFFFFF
+
+#define SATP_MODE_OFF  0
+#define SATP_MODE_SV32 1
+#define SATP_MODE_SV39 8
+#define SATP_MODE_SV48 9
+#define SATP_MODE_SV57 10
+#define SATP_MODE_SV64 11
+
+#define PMP_R     0x01
+#define PMP_W     0x02
+#define PMP_X     0x04
+#define PMP_A     0x18
+#define PMP_L     0x80
+#define PMP_SHIFT 2
+
+#define PMP_TOR   0x08
+#define PMP_NA4   0x10
+#define PMP_NAPOT 0x18
+
+#define IRQ_U_SOFT   0
+#define IRQ_S_SOFT   1
+#define IRQ_H_SOFT   2
+#define IRQ_M_SOFT   3
+#define IRQ_U_TIMER  4
+#define IRQ_S_TIMER  5
+#define IRQ_H_TIMER  6
+#define IRQ_M_TIMER  7
+#define IRQ_U_EXT    8
+#define IRQ_S_EXT    9
+#define IRQ_H_EXT    10
+#define IRQ_M_EXT    11
+#define IRQ_COP      12
+#define IRQ_HOST     13
+
+#define DEFAULT_RSTVEC     0x00001000
+#define CLINT_BASE         0x02000000
+#define CLINT_SIZE         0x000c0000
+#define EXT_IO_BASE        0x40000000
+#define DRAM_BASE          0x80000000
+
+/* page table entry (PTE) fields */
+#define PTE_V     0x001 /* Valid */
+#define PTE_R     0x002 /* Read */
+#define PTE_W     0x004 /* Write */
+#define PTE_X     0x008 /* Execute */
+#define PTE_U     0x010 /* User */
+#define PTE_G     0x020 /* Global */
+#define PTE_A     0x040 /* Accessed */
+#define PTE_D     0x080 /* Dirty */
+#define PTE_SOFT  0x300 /* Reserved for Software */
+
+#define PTE_PPN_SHIFT 10
+
+#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)
+
+#ifdef __riscv
+
+#if __riscv_xlen == 64
+# define MSTATUS_SD MSTATUS64_SD
+# define SSTATUS_SD SSTATUS64_SD
+# define RISCV_PGLEVEL_BITS 9
+# define SATP_MODE SATP64_MODE
+#else
+# define MSTATUS_SD MSTATUS32_SD
+# define SSTATUS_SD SSTATUS32_SD
+# define RISCV_PGLEVEL_BITS 10
+# define SATP_MODE SATP32_MODE
+#endif
+#define RISCV_PGSHIFT 12
+#define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
+
+#ifndef __ASSEMBLER__
+
+#ifdef __GNUC__
+
+#define read_csr(reg) ({ unsigned long __tmp; \
+  asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
+  __tmp; })
+
+#define write_csr(reg, val) ({ \
+  asm volatile ("csrw " #reg ", %0" :: "rK"(val)); })
+
+#define swap_csr(reg, val) ({ unsigned long __tmp; \
+  asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \
+  __tmp; })
+
+#define set_csr(reg, bit) ({ unsigned long __tmp; \
+  asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \
+  __tmp; })
+
+#define clear_csr(reg, bit) ({ unsigned long __tmp; \
+  asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \
+  __tmp; })
+
+#define rdtime() read_csr(time)
+#define rdcycle() read_csr(cycle)
+#define rdinstret() read_csr(instret)
+
+#endif
+
+#endif
+
+#endif
+
+#endif
+/* Automatically generated by parse_opcodes.  */
+#ifndef RISCV_ENCODING_H
+#define RISCV_ENCODING_H
+#define MATCH_SLLI_RV32 0x1013
+#define MASK_SLLI_RV32  0xfe00707f
+#define MATCH_SRLI_RV32 0x5013
+#define MASK_SRLI_RV32  0xfe00707f
+#define MATCH_SRAI_RV32 0x40005013
+#define MASK_SRAI_RV32  0xfe00707f
+#define MATCH_FRFLAGS 0x102073
+#define MASK_FRFLAGS  0xfffff07f
+#define MATCH_FSFLAGS 0x101073
+#define MASK_FSFLAGS  0xfff0707f
+#define MATCH_FSFLAGSI 0x105073
+#define MASK_FSFLAGSI  0xfff0707f
+#define MATCH_FRRM 0x202073
+#define MASK_FRRM  0xfffff07f
+#define MATCH_FSRM 0x201073
+#define MASK_FSRM  0xfff0707f
+#define MATCH_FSRMI 0x205073
+#define MASK_FSRMI  0xfff0707f
+#define MATCH_FSCSR 0x301073
+#define MASK_FSCSR  0xfff0707f
+#define MATCH_FRCSR 0x302073
+#define MASK_FRCSR  0xfffff07f
+#define MATCH_RDCYCLE 0xc0002073
+#define MASK_RDCYCLE  0xfffff07f
+#define MATCH_RDTIME 0xc0102073
+#define MASK_RDTIME  0xfffff07f
+#define MATCH_RDINSTRET 0xc0202073
+#define MASK_RDINSTRET  0xfffff07f
+#define MATCH_RDCYCLEH 0xc8002073
+#define MASK_RDCYCLEH  0xfffff07f
+#define MATCH_RDTIMEH 0xc8102073
+#define MASK_RDTIMEH  0xfffff07f
+#define MATCH_RDINSTRETH 0xc8202073
+#define MASK_RDINSTRETH  0xfffff07f
+#define MATCH_SCALL 0x73
+#define MASK_SCALL  0xffffffff
+#define MATCH_SBREAK 0x100073
+#define MASK_SBREAK  0xffffffff
+#define MATCH_FMV_X_S 0xe0000053
+#define MASK_FMV_X_S  0xfff0707f
+#define MATCH_FMV_S_X 0xf0000053
+#define MASK_FMV_S_X  0xfff0707f
+#define MATCH_FENCE_TSO 0x8330000f
+#define MASK_FENCE_TSO  0xfff0707f
+#define MATCH_PAUSE 0x100000f
+#define MASK_PAUSE  0xffffffff
+#define MATCH_BEQ 0x63
+#define MASK_BEQ  0x707f
+#define MATCH_BNE 0x1063
+#define MASK_BNE  0x707f
+#define MATCH_BLT 0x4063
+#define MASK_BLT  0x707f
+#define MATCH_BGE 0x5063
+#define MASK_BGE  0x707f
+#define MATCH_BLTU 0x6063
+#define MASK_BLTU  0x707f
+#define MATCH_BGEU 0x7063
+#define MASK_BGEU  0x707f
+#define MATCH_JALR 0x67
+#define MASK_JALR  0x707f
+#define MATCH_JAL 0x6f
+#define MASK_JAL  0x7f
+#define MATCH_LUI 0x37
+#define MASK_LUI  0x7f
+#define MATCH_AUIPC 0x17
+#define MASK_AUIPC  0x7f
+#define MATCH_ADDI 0x13
+#define MASK_ADDI  0x707f
+#define MATCH_SLLI 0x1013
+#define MASK_SLLI  0xfc00707f
+#define MATCH_SLTI 0x2013
+#define MASK_SLTI  0x707f
+#define MATCH_SLTIU 0x3013
+#define MASK_SLTIU  0x707f
+#define MATCH_XORI 0x4013
+#define MASK_XORI  0x707f
+#define MATCH_SRLI 0x5013
+#define MASK_SRLI  0xfc00707f
+#define MATCH_SRAI 0x40005013
+#define MASK_SRAI  0xfc00707f
+#define MATCH_ORI 0x6013
+#define MASK_ORI  0x707f
+#define MATCH_ANDI 0x7013
+#define MASK_ANDI  0x707f
+#define MATCH_ADD 0x33
+#define MASK_ADD  0xfe00707f
+#define MATCH_SUB 0x40000033
+#define MASK_SUB  0xfe00707f
+#define MATCH_SLL 0x1033
+#define MASK_SLL  0xfe00707f
+#define MATCH_SLT 0x2033
+#define MASK_SLT  0xfe00707f
+#define MATCH_SLTU 0x3033
+#define MASK_SLTU  0xfe00707f
+#define MATCH_XOR 0x4033
+#define MASK_XOR  0xfe00707f
+#define MATCH_SRL 0x5033
+#define MASK_SRL  0xfe00707f
+#define MATCH_SRA 0x40005033
+#define MASK_SRA  0xfe00707f
+#define MATCH_OR 0x6033
+#define MASK_OR  0xfe00707f
+#define MATCH_AND 0x7033
+#define MASK_AND  0xfe00707f
+#define MATCH_LB 0x3
+#define MASK_LB  0x707f
+#define MATCH_LH 0x1003
+#define MASK_LH  0x707f
+#define MATCH_LW 0x2003
+#define MASK_LW  0x707f
+#define MATCH_LBU 0x4003
+#define MASK_LBU  0x707f
+#define MATCH_LHU 0x5003
+#define MASK_LHU  0x707f
+#define MATCH_SB 0x23
+#define MASK_SB  0x707f
+#define MATCH_SH 0x1023
+#define MASK_SH  0x707f
+#define MATCH_SW 0x2023
+#define MASK_SW  0x707f
+#define MATCH_FENCE 0xf
+#define MASK_FENCE  0x707f
+#define MATCH_FENCE_I 0x100f
+#define MASK_FENCE_I  0x707f
+#define MATCH_ADDIW 0x1b
+#define MASK_ADDIW  0x707f
+#define MATCH_SLLIW 0x101b
+#define MASK_SLLIW  0xfe00707f
+#define MATCH_SRLIW 0x501b
+#define MASK_SRLIW  0xfe00707f
+#define MATCH_SRAIW 0x4000501b
+#define MASK_SRAIW  0xfe00707f
+#define MATCH_ADDW 0x3b
+#define MASK_ADDW  0xfe00707f
+#define MATCH_SUBW 0x4000003b
+#define MASK_SUBW  0xfe00707f
+#define MATCH_SLLW 0x103b
+#define MASK_SLLW  0xfe00707f
+#define MATCH_SRLW 0x503b
+#define MASK_SRLW  0xfe00707f
+#define MATCH_SRAW 0x4000503b
+#define MASK_SRAW  0xfe00707f
+#define MATCH_LD 0x3003
+#define MASK_LD  0x707f
+#define MATCH_LWU 0x6003
+#define MASK_LWU  0x707f
+#define MATCH_SD 0x3023
+#define MASK_SD  0x707f
+#define MATCH_MUL 0x2000033
+#define MASK_MUL  0xfe00707f
+#define MATCH_MULH 0x2001033
+#define MASK_MULH  0xfe00707f
+#define MATCH_MULHSU 0x2002033
+#define MASK_MULHSU  0xfe00707f
+#define MATCH_MULHU 0x2003033
+#define MASK_MULHU  0xfe00707f
+#define MATCH_DIV 0x2004033
+#define MASK_DIV  0xfe00707f
+#define MATCH_DIVU 0x2005033
+#define MASK_DIVU  0xfe00707f
+#define MATCH_REM 0x2006033
+#define MASK_REM  0xfe00707f
+#define MATCH_REMU 0x2007033
+#define MASK_REMU  0xfe00707f
+#define MATCH_MULW 0x200003b
+#define MASK_MULW  0xfe00707f
+#define MATCH_DIVW 0x200403b
+#define MASK_DIVW  0xfe00707f
+#define MATCH_DIVUW 0x200503b
+#define MASK_DIVUW  0xfe00707f
+#define MATCH_REMW 0x200603b
+#define MASK_REMW  0xfe00707f
+#define MATCH_REMUW 0x200703b
+#define MASK_REMUW  0xfe00707f
+#define MATCH_AMOADD_W 0x202f
+#define MASK_AMOADD_W  0xf800707f
+#define MATCH_AMOXOR_W 0x2000202f
+#define MASK_AMOXOR_W  0xf800707f
+#define MATCH_AMOOR_W 0x4000202f
+#define MASK_AMOOR_W  0xf800707f
+#define MATCH_AMOAND_W 0x6000202f
+#define MASK_AMOAND_W  0xf800707f
+#define MATCH_AMOMIN_W 0x8000202f
+#define MASK_AMOMIN_W  0xf800707f
+#define MATCH_AMOMAX_W 0xa000202f
+#define MASK_AMOMAX_W  0xf800707f
+#define MATCH_AMOMINU_W 0xc000202f
+#define MASK_AMOMINU_W  0xf800707f
+#define MATCH_AMOMAXU_W 0xe000202f
+#define MASK_AMOMAXU_W  0xf800707f
+#define MATCH_AMOSWAP_W 0x800202f
+#define MASK_AMOSWAP_W  0xf800707f
+#define MATCH_LR_W 0x1000202f
+#define MASK_LR_W  0xf9f0707f
+#define MATCH_SC_W 0x1800202f
+#define MASK_SC_W  0xf800707f
+#define MATCH_AMOADD_D 0x302f
+#define MASK_AMOADD_D  0xf800707f
+#define MATCH_AMOXOR_D 0x2000302f
+#define MASK_AMOXOR_D  0xf800707f
+#define MATCH_AMOOR_D 0x4000302f
+#define MASK_AMOOR_D  0xf800707f
+#define MATCH_AMOAND_D 0x6000302f
+#define MASK_AMOAND_D  0xf800707f
+#define MATCH_AMOMIN_D 0x8000302f
+#define MASK_AMOMIN_D  0xf800707f
+#define MATCH_AMOMAX_D 0xa000302f
+#define MASK_AMOMAX_D  0xf800707f
+#define MATCH_AMOMINU_D 0xc000302f
+#define MASK_AMOMINU_D  0xf800707f
+#define MATCH_AMOMAXU_D 0xe000302f
+#define MASK_AMOMAXU_D  0xf800707f
+#define MATCH_AMOSWAP_D 0x800302f
+#define MASK_AMOSWAP_D  0xf800707f
+#define MATCH_LR_D 0x1000302f
+#define MASK_LR_D  0xf9f0707f
+#define MATCH_SC_D 0x1800302f
+#define MASK_SC_D  0xf800707f
+#define MATCH_FADD_S 0x53
+#define MASK_FADD_S  0xfe00007f
+#define MATCH_FSUB_S 0x8000053
+#define MASK_FSUB_S  0xfe00007f
+#define MATCH_FMUL_S 0x10000053
+#define MASK_FMUL_S  0xfe00007f
+#define MATCH_FDIV_S 0x18000053
+#define MASK_FDIV_S  0xfe00007f
+#define MATCH_FSGNJ_S 0x20000053
+#define MASK_FSGNJ_S  0xfe00707f
+#define MATCH_FSGNJN_S 0x20001053
+#define MASK_FSGNJN_S  0xfe00707f
+#define MATCH_FSGNJX_S 0x20002053
+#define MASK_FSGNJX_S  0xfe00707f
+#define MATCH_FMIN_S 0x28000053
+#define MASK_FMIN_S  0xfe00707f
+#define MATCH_FMAX_S 0x28001053
+#define MASK_FMAX_S  0xfe00707f
+#define MATCH_FSQRT_S 0x58000053
+#define MASK_FSQRT_S  0xfff0007f
+#define MATCH_FLE_S 0xa0000053
+#define MASK_FLE_S  0xfe00707f
+#define MATCH_FLT_S 0xa0001053
+#define MASK_FLT_S  0xfe00707f
+#define MATCH_FEQ_S 0xa0002053
+#define MASK_FEQ_S  0xfe00707f
+#define MATCH_FCVT_W_S 0xc0000053
+#define MASK_FCVT_W_S  0xfff0007f
+#define MATCH_FCVT_WU_S 0xc0100053
+#define MASK_FCVT_WU_S  0xfff0007f
+#define MATCH_FMV_X_W 0xe0000053
+#define MASK_FMV_X_W  0xfff0707f
+#define MATCH_FCLASS_S 0xe0001053
+#define MASK_FCLASS_S  0xfff0707f
+#define MATCH_FCVT_S_W 0xd0000053
+#define MASK_FCVT_S_W  0xfff0007f
+#define MATCH_FCVT_S_WU 0xd0100053
+#define MASK_FCVT_S_WU  0xfff0007f
+#define MATCH_FMV_W_X 0xf0000053
+#define MASK_FMV_W_X  0xfff0707f
+#define MATCH_FLW 0x2007
+#define MASK_FLW  0x707f
+#define MATCH_FSW 0x2027
+#define MASK_FSW  0x707f
+#define MATCH_FMADD_S 0x43
+#define MASK_FMADD_S  0x600007f
+#define MATCH_FMSUB_S 0x47
+#define MASK_FMSUB_S  0x600007f
+#define MATCH_FNMSUB_S 0x4b
+#define MASK_FNMSUB_S  0x600007f
+#define MATCH_FNMADD_S 0x4f
+#define MASK_FNMADD_S  0x600007f
+#define MATCH_FCVT_L_S 0xc0200053
+#define MASK_FCVT_L_S  0xfff0007f
+#define MATCH_FCVT_LU_S 0xc0300053
+#define MASK_FCVT_LU_S  0xfff0007f
+#define MATCH_FCVT_S_L 0xd0200053
+#define MASK_FCVT_S_L  0xfff0007f
+#define MATCH_FCVT_S_LU 0xd0300053
+#define MASK_FCVT_S_LU  0xfff0007f
+#define MATCH_FADD_D 0x2000053
+#define MASK_FADD_D  0xfe00007f
+#define MATCH_FSUB_D 0xa000053
+#define MASK_FSUB_D  0xfe00007f
+#define MATCH_FMUL_D 0x12000053
+#define MASK_FMUL_D  0xfe00007f
+#define MATCH_FDIV_D 0x1a000053
+#define MASK_FDIV_D  0xfe00007f
+#define MATCH_FSGNJ_D 0x22000053
+#define MASK_FSGNJ_D  0xfe00707f
+#define MATCH_FSGNJN_D 0x22001053
+#define MASK_FSGNJN_D  0xfe00707f
+#define MATCH_FSGNJX_D 0x22002053
+#define MASK_FSGNJX_D  0xfe00707f
+#define MATCH_FMIN_D 0x2a000053
+#define MASK_FMIN_D  0xfe00707f
+#define MATCH_FMAX_D 0x2a001053
+#define MASK_FMAX_D  0xfe00707f
+#define MATCH_FCVT_S_D 0x40100053
+#define MASK_FCVT_S_D  0xfff0007f
+#define MATCH_FCVT_D_S 0x42000053
+#define MASK_FCVT_D_S  0xfff0007f
+#define MATCH_FSQRT_D 0x5a000053
+#define MASK_FSQRT_D  0xfff0007f
+#define MATCH_FLE_D 0xa2000053
+#define MASK_FLE_D  0xfe00707f
+#define MATCH_FLT_D 0xa2001053
+#define MASK_FLT_D  0xfe00707f
+#define MATCH_FEQ_D 0xa2002053
+#define MASK_FEQ_D  0xfe00707f
+#define MATCH_FCVT_W_D 0xc2000053
+#define MASK_FCVT_W_D  0xfff0007f
+#define MATCH_FCVT_WU_D 0xc2100053
+#define MASK_FCVT_WU_D  0xfff0007f
+#define MATCH_FCLASS_D 0xe2001053
+#define MASK_FCLASS_D  0xfff0707f
+#define MATCH_FCVT_D_W 0xd2000053
+#define MASK_FCVT_D_W  0xfff0007f
+#define MATCH_FCVT_D_WU 0xd2100053
+#define MASK_FCVT_D_WU  0xfff0007f
+#define MATCH_FLD 0x3007
+#define MASK_FLD  0x707f
+#define MATCH_FSD 0x3027
+#define MASK_FSD  0x707f
+#define MATCH_FMADD_D 0x2000043
+#define MASK_FMADD_D  0x600007f
+#define MATCH_FMSUB_D 0x2000047
+#define MASK_FMSUB_D  0x600007f
+#define MATCH_FNMSUB_D 0x200004b
+#define MASK_FNMSUB_D  0x600007f
+#define MATCH_FNMADD_D 0x200004f
+#define MASK_FNMADD_D  0x600007f
+#define MATCH_FCVT_L_D 0xc2200053
+#define MASK_FCVT_L_D  0xfff0007f
+#define MATCH_FCVT_LU_D 0xc2300053
+#define MASK_FCVT_LU_D  0xfff0007f
+#define MATCH_FMV_X_D 0xe2000053
+#define MASK_FMV_X_D  0xfff0707f
+#define MATCH_FCVT_D_L 0xd2200053
+#define MASK_FCVT_D_L  0xfff0007f
+#define MATCH_FCVT_D_LU 0xd2300053
+#define MASK_FCVT_D_LU  0xfff0007f
+#define MATCH_FMV_D_X 0xf2000053
+#define MASK_FMV_D_X  0xfff0707f
+#define MATCH_FADD_Q 0x6000053
+#define MASK_FADD_Q  0xfe00007f
+#define MATCH_FSUB_Q 0xe000053
+#define MASK_FSUB_Q  0xfe00007f
+#define MATCH_FMUL_Q 0x16000053
+#define MASK_FMUL_Q  0xfe00007f
+#define MATCH_FDIV_Q 0x1e000053
+#define MASK_FDIV_Q  0xfe00007f
+#define MATCH_FSGNJ_Q 0x26000053
+#define MASK_FSGNJ_Q  0xfe00707f
+#define MATCH_FSGNJN_Q 0x26001053
+#define MASK_FSGNJN_Q  0xfe00707f
+#define MATCH_FSGNJX_Q 0x26002053
+#define MASK_FSGNJX_Q  0xfe00707f
+#define MATCH_FMIN_Q 0x2e000053
+#define MASK_FMIN_Q  0xfe00707f
+#define MATCH_FMAX_Q 0x2e001053
+#define MASK_FMAX_Q  0xfe00707f
+#define MATCH_FCVT_S_Q 0x40300053
+#define MASK_FCVT_S_Q  0xfff0007f
+#define MATCH_FCVT_Q_S 0x46000053
+#define MASK_FCVT_Q_S  0xfff0007f
+#define MATCH_FCVT_D_Q 0x42300053
+#define MASK_FCVT_D_Q  0xfff0007f
+#define MATCH_FCVT_Q_D 0x46100053
+#define MASK_FCVT_Q_D  0xfff0007f
+#define MATCH_FSQRT_Q 0x5e000053
+#define MASK_FSQRT_Q  0xfff0007f
+#define MATCH_FLE_Q 0xa6000053
+#define MASK_FLE_Q  0xfe00707f
+#define MATCH_FLT_Q 0xa6001053
+#define MASK_FLT_Q  0xfe00707f
+#define MATCH_FEQ_Q 0xa6002053
+#define MASK_FEQ_Q  0xfe00707f
+#define MATCH_FCVT_W_Q 0xc6000053
+#define MASK_FCVT_W_Q  0xfff0007f
+#define MATCH_FCVT_WU_Q 0xc6100053
+#define MASK_FCVT_WU_Q  0xfff0007f
+#define MATCH_FCLASS_Q 0xe6001053
+#define MASK_FCLASS_Q  0xfff0707f
+#define MATCH_FCVT_Q_W 0xd6000053
+#define MASK_FCVT_Q_W  0xfff0007f
+#define MATCH_FCVT_Q_WU 0xd6100053
+#define MASK_FCVT_Q_WU  0xfff0007f
+#define MATCH_FLQ 0x4007
+#define MASK_FLQ  0x707f
+#define MATCH_FSQ 0x4027
+#define MASK_FSQ  0x707f
+#define MATCH_FMADD_Q 0x6000043
+#define MASK_FMADD_Q  0x600007f
+#define MATCH_FMSUB_Q 0x6000047
+#define MASK_FMSUB_Q  0x600007f
+#define MATCH_FNMSUB_Q 0x600004b
+#define MASK_FNMSUB_Q  0x600007f
+#define MATCH_FNMADD_Q 0x600004f
+#define MASK_FNMADD_Q  0x600007f
+#define MATCH_FCVT_L_Q 0xc6200053
+#define MASK_FCVT_L_Q  0xfff0007f
+#define MATCH_FCVT_LU_Q 0xc6300053
+#define MASK_FCVT_LU_Q  0xfff0007f
+#define MATCH_FCVT_Q_L 0xd6200053
+#define MASK_FCVT_Q_L  0xfff0007f
+#define MATCH_FCVT_Q_LU 0xd6300053
+#define MASK_FCVT_Q_LU  0xfff0007f
+#define MATCH_FMV_X_Q 0xe6000053
+#define MASK_FMV_X_Q  0xfff0707f
+#define MATCH_FMV_Q_X 0xf6000053
+#define MASK_FMV_Q_X  0xfff0707f
+#define MATCH_ECALL 0x73
+#define MASK_ECALL  0xffffffff
+#define MATCH_EBREAK 0x100073
+#define MASK_EBREAK  0xffffffff
+#define MATCH_URET 0x200073
+#define MASK_URET  0xffffffff
+#define MATCH_SRET 0x10200073
+#define MASK_SRET  0xffffffff
+#define MATCH_MRET 0x30200073
+#define MASK_MRET  0xffffffff
+#define MATCH_DRET 0x7b200073
+#define MASK_DRET  0xffffffff
+#define MATCH_SFENCE_VMA 0x12000073
+#define MASK_SFENCE_VMA  0xfe007fff
+#define MATCH_WFI 0x10500073
+#define MASK_WFI  0xffffffff
+#define MATCH_CSRRW 0x1073
+#define MASK_CSRRW  0x707f
+#define MATCH_CSRRS 0x2073
+#define MASK_CSRRS  0x707f
+#define MATCH_CSRRC 0x3073
+#define MASK_CSRRC  0x707f
+#define MATCH_CSRRWI 0x5073
+#define MASK_CSRRWI  0x707f
+#define MATCH_CSRRSI 0x6073
+#define MASK_CSRRSI  0x707f
+#define MATCH_CSRRCI 0x7073
+#define MASK_CSRRCI  0x707f
+#define MATCH_HFENCE_VVMA 0x22000073
+#define MASK_HFENCE_VVMA  0xfe007fff
+#define MATCH_HFENCE_GVMA 0x62000073
+#define MASK_HFENCE_GVMA  0xfe007fff
+#define MATCH_C_NOP 0x1
+#define MASK_C_NOP  0xffff
+#define MATCH_C_ADDI16SP 0x6101
+#define MASK_C_ADDI16SP  0xef83
+#define MATCH_C_JR 0x8002
+#define MASK_C_JR  0xf07f
+#define MATCH_C_JALR 0x9002
+#define MASK_C_JALR  0xf07f
+#define MATCH_C_EBREAK 0x9002
+#define MASK_C_EBREAK  0xffff
+#define MATCH_C_ADDI4SPN 0x0
+#define MASK_C_ADDI4SPN  0xe003
+#define MATCH_C_FLD 0x2000
+#define MASK_C_FLD  0xe003
+#define MATCH_C_LW 0x4000
+#define MASK_C_LW  0xe003
+#define MATCH_C_FLW 0x6000
+#define MASK_C_FLW  0xe003
+#define MATCH_C_FSD 0xa000
+#define MASK_C_FSD  0xe003
+#define MATCH_C_SW 0xc000
+#define MASK_C_SW  0xe003
+#define MATCH_C_FSW 0xe000
+#define MASK_C_FSW  0xe003
+#define MATCH_C_ADDI 0x1
+#define MASK_C_ADDI  0xe003
+#define MATCH_C_JAL 0x2001
+#define MASK_C_JAL  0xe003
+#define MATCH_C_LI 0x4001
+#define MASK_C_LI  0xe003
+#define MATCH_C_LUI 0x6001
+#define MASK_C_LUI  0xe003
+#define MATCH_C_SRLI 0x8001
+#define MASK_C_SRLI  0xec03
+#define MATCH_C_SRAI 0x8401
+#define MASK_C_SRAI  0xec03
+#define MATCH_C_ANDI 0x8801
+#define MASK_C_ANDI  0xec03
+#define MATCH_C_SUB 0x8c01
+#define MASK_C_SUB  0xfc63
+#define MATCH_C_XOR 0x8c21
+#define MASK_C_XOR  0xfc63
+#define MATCH_C_OR 0x8c41
+#define MASK_C_OR  0xfc63
+#define MATCH_C_AND 0x8c61
+#define MASK_C_AND  0xfc63
+#define MATCH_C_J 0xa001
+#define MASK_C_J  0xe003
+#define MATCH_C_BEQZ 0xc001
+#define MASK_C_BEQZ  0xe003
+#define MATCH_C_BNEZ 0xe001
+#define MASK_C_BNEZ  0xe003
+#define MATCH_C_SLLI 0x2
+#define MASK_C_SLLI  0xe003
+#define MATCH_C_FLDSP 0x2002
+#define MASK_C_FLDSP  0xe003
+#define MATCH_C_LWSP 0x4002
+#define MASK_C_LWSP  0xe003
+#define MATCH_C_FLWSP 0x6002
+#define MASK_C_FLWSP  0xe003
+#define MATCH_C_MV 0x8002
+#define MASK_C_MV  0xf003
+#define MATCH_C_ADD 0x9002
+#define MASK_C_ADD  0xf003
+#define MATCH_C_FSDSP 0xa002
+#define MASK_C_FSDSP  0xe003
+#define MATCH_C_SWSP 0xc002
+#define MASK_C_SWSP  0xe003
+#define MATCH_C_FSWSP 0xe002
+#define MASK_C_FSWSP  0xe003
+#define MATCH_C_SRLI_RV32 0x8001
+#define MASK_C_SRLI_RV32  0xfc03
+#define MATCH_C_SRAI_RV32 0x8401
+#define MASK_C_SRAI_RV32  0xfc03
+#define MATCH_C_SLLI_RV32 0x2
+#define MASK_C_SLLI_RV32  0xf003
+#define MATCH_C_LD 0x6000
+#define MASK_C_LD  0xe003
+#define MATCH_C_SD 0xe000
+#define MASK_C_SD  0xe003
+#define MATCH_C_SUBW 0x9c01
+#define MASK_C_SUBW  0xfc63
+#define MATCH_C_ADDW 0x9c21
+#define MASK_C_ADDW  0xfc63
+#define MATCH_C_ADDIW 0x2001
+#define MASK_C_ADDIW  0xe003
+#define MATCH_C_LDSP 0x6002
+#define MASK_C_LDSP  0xe003
+#define MATCH_C_SDSP 0xe002
+#define MASK_C_SDSP  0xe003
+#define MATCH_C_LQ 0x2000
+#define MASK_C_LQ  0xe003
+#define MATCH_C_SQ 0xa000
+#define MASK_C_SQ  0xe003
+#define MATCH_C_LQSP 0x2002
+#define MASK_C_LQSP  0xe003
+#define MATCH_C_SQSP 0xa002
+#define MASK_C_SQSP  0xe003
+#define MATCH_CUSTOM0 0xb
+#define MASK_CUSTOM0  0x707f
+#define MATCH_CUSTOM0_RS1 0x200b
+#define MASK_CUSTOM0_RS1  0x707f
+#define MATCH_CUSTOM0_RS1_RS2 0x300b
+#define MASK_CUSTOM0_RS1_RS2  0x707f
+#define MATCH_CUSTOM0_RD 0x400b
+#define MASK_CUSTOM0_RD  0x707f
+#define MATCH_CUSTOM0_RD_RS1 0x600b
+#define MASK_CUSTOM0_RD_RS1  0x707f
+#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b
+#define MASK_CUSTOM0_RD_RS1_RS2  0x707f
+#define MATCH_CUSTOM1 0x2b
+#define MASK_CUSTOM1  0x707f
+#define MATCH_CUSTOM1_RS1 0x202b
+#define MASK_CUSTOM1_RS1  0x707f
+#define MATCH_CUSTOM1_RS1_RS2 0x302b
+#define MASK_CUSTOM1_RS1_RS2  0x707f
+#define MATCH_CUSTOM1_RD 0x402b
+#define MASK_CUSTOM1_RD  0x707f
+#define MATCH_CUSTOM1_RD_RS1 0x602b
+#define MASK_CUSTOM1_RD_RS1  0x707f
+#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b
+#define MASK_CUSTOM1_RD_RS1_RS2  0x707f
+#define MATCH_CUSTOM2 0x5b
+#define MASK_CUSTOM2  0x707f
+#define MATCH_CUSTOM2_RS1 0x205b
+#define MASK_CUSTOM2_RS1  0x707f
+#define MATCH_CUSTOM2_RS1_RS2 0x305b
+#define MASK_CUSTOM2_RS1_RS2  0x707f
+#define MATCH_CUSTOM2_RD 0x405b
+#define MASK_CUSTOM2_RD  0x707f
+#define MATCH_CUSTOM2_RD_RS1 0x605b
+#define MASK_CUSTOM2_RD_RS1  0x707f
+#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b
+#define MASK_CUSTOM2_RD_RS1_RS2  0x707f
+#define MATCH_CUSTOM3 0x7b
+#define MASK_CUSTOM3  0x707f
+#define MATCH_CUSTOM3_RS1 0x207b
+#define MASK_CUSTOM3_RS1  0x707f
+#define MATCH_CUSTOM3_RS1_RS2 0x307b
+#define MASK_CUSTOM3_RS1_RS2  0x707f
+#define MATCH_CUSTOM3_RD 0x407b
+#define MASK_CUSTOM3_RD  0x707f
+#define MATCH_CUSTOM3_RD_RS1 0x607b
+#define MASK_CUSTOM3_RD_RS1  0x707f
+#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
+#define MASK_CUSTOM3_RD_RS1_RS2  0x707f
+#define MATCH_VSETVLI 0x7057
+#define MASK_VSETVLI  0x8000707f
+#define MATCH_VSETVL 0x80007057
+#define MASK_VSETVL  0xfe00707f
+#define MATCH_VLB_V 0x10000007
+#define MASK_VLB_V  0x1df0707f
+#define MATCH_VLH_V 0x10005007
+#define MASK_VLH_V  0x1df0707f
+#define MATCH_VLW_V 0x10006007
+#define MASK_VLW_V  0x1df0707f
+#define MATCH_VLE_V 0x7007
+#define MASK_VLE_V  0x1df0707f
+#define MATCH_VLBU_V 0x7
+#define MASK_VLBU_V  0x1df0707f
+#define MATCH_VLHU_V 0x5007
+#define MASK_VLHU_V  0x1df0707f
+#define MATCH_VLWU_V 0x6007
+#define MASK_VLWU_V  0x1df0707f
+#define MATCH_VSB_V 0x27
+#define MASK_VSB_V  0x1df0707f
+#define MATCH_VSH_V 0x5027
+#define MASK_VSH_V  0x1df0707f
+#define MATCH_VSW_V 0x6027
+#define MASK_VSW_V  0x1df0707f
+#define MATCH_VSE_V 0x7027
+#define MASK_VSE_V  0x1df0707f
+#define MATCH_VLSB_V 0x18000007
+#define MASK_VLSB_V  0x1c00707f
+#define MATCH_VLSH_V 0x18005007
+#define MASK_VLSH_V  0x1c00707f
+#define MATCH_VLSW_V 0x18006007
+#define MASK_VLSW_V  0x1c00707f
+#define MATCH_VLSE_V 0x8007007
+#define MASK_VLSE_V  0x1c00707f
+#define MATCH_VLSBU_V 0x8000007
+#define MASK_VLSBU_V  0x1c00707f
+#define MATCH_VLSHU_V 0x8005007
+#define MASK_VLSHU_V  0x1c00707f
+#define MATCH_VLSWU_V 0x8006007
+#define MASK_VLSWU_V  0x1c00707f
+#define MATCH_VSSB_V 0x8000027
+#define MASK_VSSB_V  0x1c00707f
+#define MATCH_VSSH_V 0x8005027
+#define MASK_VSSH_V  0x1c00707f
+#define MATCH_VSSW_V 0x8006027
+#define MASK_VSSW_V  0x1c00707f
+#define MATCH_VSSE_V 0x8007027
+#define MASK_VSSE_V  0x1c00707f
+#define MATCH_VLXB_V 0x1c000007
+#define MASK_VLXB_V  0x1c00707f
+#define MATCH_VLXH_V 0x1c005007
+#define MASK_VLXH_V  0x1c00707f
+#define MATCH_VLXW_V 0x1c006007
+#define MASK_VLXW_V  0x1c00707f
+#define MATCH_VLXE_V 0xc007007
+#define MASK_VLXE_V  0x1c00707f
+#define MATCH_VLXBU_V 0xc000007
+#define MASK_VLXBU_V  0x1c00707f
+#define MATCH_VLXHU_V 0xc005007
+#define MASK_VLXHU_V  0x1c00707f
+#define MATCH_VLXWU_V 0xc006007
+#define MASK_VLXWU_V  0x1c00707f
+#define MATCH_VSXB_V 0xc000027
+#define MASK_VSXB_V  0x1c00707f
+#define MATCH_VSXH_V 0xc005027
+#define MASK_VSXH_V  0x1c00707f
+#define MATCH_VSXW_V 0xc006027
+#define MASK_VSXW_V  0x1c00707f
+#define MATCH_VSXE_V 0xc007027
+#define MASK_VSXE_V  0x1c00707f
+#define MATCH_VSUXB_V 0x1c000027
+#define MASK_VSUXB_V  0xfc00707f
+#define MATCH_VSUXH_V 0x1c005027
+#define MASK_VSUXH_V  0xfc00707f
+#define MATCH_VSUXW_V 0x1c006027
+#define MASK_VSUXW_V  0xfc00707f
+#define MATCH_VSUXE_V 0x1c007027
+#define MASK_VSUXE_V  0xfc00707f
+#define MATCH_VLBFF_V 0x11000007
+#define MASK_VLBFF_V  0x1df0707f
+#define MATCH_VLHFF_V 0x11005007
+#define MASK_VLHFF_V  0x1df0707f
+#define MATCH_VLWFF_V 0x11006007
+#define MASK_VLWFF_V  0x1df0707f
+#define MATCH_VLEFF_V 0x1007007
+#define MASK_VLEFF_V  0x1df0707f
+#define MATCH_VLBUFF_V 0x1000007
+#define MASK_VLBUFF_V  0x1df0707f
+#define MATCH_VLHUFF_V 0x1005007
+#define MASK_VLHUFF_V  0x1df0707f
+#define MATCH_VLWUFF_V 0x1006007
+#define MASK_VLWUFF_V  0x1df0707f
+#define MATCH_VL1R_V 0x2807007
+#define MASK_VL1R_V  0xfff0707f
+#define MATCH_VS1R_V 0x2807027
+#define MASK_VS1R_V  0xfff0707f
+#define MATCH_VFADD_VF 0x5057
+#define MASK_VFADD_VF  0xfc00707f
+#define MATCH_VFSUB_VF 0x8005057
+#define MASK_VFSUB_VF  0xfc00707f
+#define MATCH_VFMIN_VF 0x10005057
+#define MASK_VFMIN_VF  0xfc00707f
+#define MATCH_VFMAX_VF 0x18005057
+#define MASK_VFMAX_VF  0xfc00707f
+#define MATCH_VFSGNJ_VF 0x20005057
+#define MASK_VFSGNJ_VF  0xfc00707f
+#define MATCH_VFSGNJN_VF 0x24005057
+#define MASK_VFSGNJN_VF  0xfc00707f
+#define MATCH_VFSGNJX_VF 0x28005057
+#define MASK_VFSGNJX_VF  0xfc00707f
+#define MATCH_VFSLIDE1UP_VF 0x38005057
+#define MASK_VFSLIDE1UP_VF  0xfc00707f
+#define MATCH_VFSLIDE1DOWN_VF 0x3c005057
+#define MASK_VFSLIDE1DOWN_VF  0xfc00707f
+#define MATCH_VFMV_S_F 0x42005057
+#define MASK_VFMV_S_F  0xfff0707f
+#define MATCH_VFMERGE_VFM 0x5c005057
+#define MASK_VFMERGE_VFM  0xfe00707f
+#define MATCH_VFMV_V_F 0x5e005057
+#define MASK_VFMV_V_F  0xfff0707f
+#define MATCH_VMFEQ_VF 0x60005057
+#define MASK_VMFEQ_VF  0xfc00707f
+#define MATCH_VMFLE_VF 0x64005057
+#define MASK_VMFLE_VF  0xfc00707f
+#define MATCH_VMFLT_VF 0x6c005057
+#define MASK_VMFLT_VF  0xfc00707f
+#define MATCH_VMFNE_VF 0x70005057
+#define MASK_VMFNE_VF  0xfc00707f
+#define MATCH_VMFGT_VF 0x74005057
+#define MASK_VMFGT_VF  0xfc00707f
+#define MATCH_VMFGE_VF 0x7c005057
+#define MASK_VMFGE_VF  0xfc00707f
+#define MATCH_VFDIV_VF 0x80005057
+#define MASK_VFDIV_VF  0xfc00707f
+#define MATCH_VFRDIV_VF 0x84005057
+#define MASK_VFRDIV_VF  0xfc00707f
+#define MATCH_VFMUL_VF 0x90005057
+#define MASK_VFMUL_VF  0xfc00707f
+#define MATCH_VFRSUB_VF 0x9c005057
+#define MASK_VFRSUB_VF  0xfc00707f
+#define MATCH_VFMADD_VF 0xa0005057
+#define MASK_VFMADD_VF  0xfc00707f
+#define MATCH_VFNMADD_VF 0xa4005057
+#define MASK_VFNMADD_VF  0xfc00707f
+#define MATCH_VFMSUB_VF 0xa8005057
+#define MASK_VFMSUB_VF  0xfc00707f
+#define MATCH_VFNMSUB_VF 0xac005057
+#define MASK_VFNMSUB_VF  0xfc00707f
+#define MATCH_VFMACC_VF 0xb0005057
+#define MASK_VFMACC_VF  0xfc00707f
+#define MATCH_VFNMACC_VF 0xb4005057
+#define MASK_VFNMACC_VF  0xfc00707f
+#define MATCH_VFMSAC_VF 0xb8005057
+#define MASK_VFMSAC_VF  0xfc00707f
+#define MATCH_VFNMSAC_VF 0xbc005057
+#define MASK_VFNMSAC_VF  0xfc00707f
+#define MATCH_VFWADD_VF 0xc0005057
+#define MASK_VFWADD_VF  0xfc00707f
+#define MATCH_VFWSUB_VF 0xc8005057
+#define MASK_VFWSUB_VF  0xfc00707f
+#define MATCH_VFWADD_WF 0xd0005057
+#define MASK_VFWADD_WF  0xfc00707f
+#define MATCH_VFWSUB_WF 0xd8005057
+#define MASK_VFWSUB_WF  0xfc00707f
+#define MATCH_VFWMUL_VF 0xe0005057
+#define MASK_VFWMUL_VF  0xfc00707f
+#define MATCH_VFWMACC_VF 0xf0005057
+#define MASK_VFWMACC_VF  0xfc00707f
+#define MATCH_VFWNMACC_VF 0xf4005057
+#define MASK_VFWNMACC_VF  0xfc00707f
+#define MATCH_VFWMSAC_VF 0xf8005057
+#define MASK_VFWMSAC_VF  0xfc00707f
+#define MATCH_VFWNMSAC_VF 0xfc005057
+#define MASK_VFWNMSAC_VF  0xfc00707f
+#define MATCH_VFADD_VV 0x1057
+#define MASK_VFADD_VV  0xfc00707f
+#define MATCH_VFREDSUM_VS 0x4001057
+#define MASK_VFREDSUM_VS  0xfc00707f
+#define MATCH_VFSUB_VV 0x8001057
+#define MASK_VFSUB_VV  0xfc00707f
+#define MATCH_VFREDOSUM_VS 0xc001057
+#define MASK_VFREDOSUM_VS  0xfc00707f
+#define MATCH_VFMIN_VV 0x10001057
+#define MASK_VFMIN_VV  0xfc00707f
+#define MATCH_VFREDMIN_VS 0x14001057
+#define MASK_VFREDMIN_VS  0xfc00707f
+#define MATCH_VFMAX_VV 0x18001057
+#define MASK_VFMAX_VV  0xfc00707f
+#define MATCH_VFREDMAX_VS 0x1c001057
+#define MASK_VFREDMAX_VS  0xfc00707f
+#define MATCH_VFSGNJ_VV 0x20001057
+#define MASK_VFSGNJ_VV  0xfc00707f
+#define MATCH_VFSGNJN_VV 0x24001057
+#define MASK_VFSGNJN_VV  0xfc00707f
+#define MATCH_VFSGNJX_VV 0x28001057
+#define MASK_VFSGNJX_VV  0xfc00707f
+#define MATCH_VFMV_F_S 0x42001057
+#define MASK_VFMV_F_S  0xfe0ff07f
+#define MATCH_VMFEQ_VV 0x60001057
+#define MASK_VMFEQ_VV  0xfc00707f
+#define MATCH_VMFLE_VV 0x64001057
+#define MASK_VMFLE_VV  0xfc00707f
+#define MATCH_VMFLT_VV 0x6c001057
+#define MASK_VMFLT_VV  0xfc00707f
+#define MATCH_VMFNE_VV 0x70001057
+#define MASK_VMFNE_VV  0xfc00707f
+#define MATCH_VFDIV_VV 0x80001057
+#define MASK_VFDIV_VV  0xfc00707f
+#define MATCH_VFMUL_VV 0x90001057
+#define MASK_VFMUL_VV  0xfc00707f
+#define MATCH_VFMADD_VV 0xa0001057
+#define MASK_VFMADD_VV  0xfc00707f
+#define MATCH_VFNMADD_VV 0xa4001057
+#define MASK_VFNMADD_VV  0xfc00707f
+#define MATCH_VFMSUB_VV 0xa8001057
+#define MASK_VFMSUB_VV  0xfc00707f
+#define MATCH_VFNMSUB_VV 0xac001057
+#define MASK_VFNMSUB_VV  0xfc00707f
+#define MATCH_VFMACC_VV 0xb0001057
+#define MASK_VFMACC_VV  0xfc00707f
+#define MATCH_VFNMACC_VV 0xb4001057
+#define MASK_VFNMACC_VV  0xfc00707f
+#define MATCH_VFMSAC_VV 0xb8001057
+#define MASK_VFMSAC_VV  0xfc00707f
+#define MATCH_VFNMSAC_VV 0xbc001057
+#define MASK_VFNMSAC_VV  0xfc00707f
+#define MATCH_VFCVT_XU_F_V 0x88001057
+#define MASK_VFCVT_XU_F_V  0xfc0ff07f
+#define MATCH_VFCVT_X_F_V 0x88009057
+#define MASK_VFCVT_X_F_V  0xfc0ff07f
+#define MATCH_VFCVT_F_XU_V 0x88011057
+#define MASK_VFCVT_F_XU_V  0xfc0ff07f
+#define MATCH_VFCVT_F_X_V 0x88019057
+#define MASK_VFCVT_F_X_V  0xfc0ff07f
+#define MATCH_VFCVT_RTZ_XU_F_V 0x88031057
+#define MASK_VFCVT_RTZ_XU_F_V  0xfc0ff07f
+#define MATCH_VFCVT_RTZ_X_F_V 0x88039057
+#define MASK_VFCVT_RTZ_X_F_V  0xfc0ff07f
+#define MATCH_VFWCVT_XU_F_V 0x88041057
+#define MASK_VFWCVT_XU_F_V  0xfc0ff07f
+#define MATCH_VFWCVT_X_F_V 0x88049057
+#define MASK_VFWCVT_X_F_V  0xfc0ff07f
+#define MATCH_VFWCVT_F_XU_V 0x88051057
+#define MASK_VFWCVT_F_XU_V  0xfc0ff07f
+#define MATCH_VFWCVT_F_X_V 0x88059057
+#define MASK_VFWCVT_F_X_V  0xfc0ff07f
+#define MATCH_VFWCVT_F_F_V 0x88061057
+#define MASK_VFWCVT_F_F_V  0xfc0ff07f
+#define MATCH_VFWCVT_RTZ_XU_F_V 0x88071057
+#define MASK_VFWCVT_RTZ_XU_F_V  0xfc0ff07f
+#define MATCH_VFWCVT_RTZ_X_F_V 0x88079057
+#define MASK_VFWCVT_RTZ_X_F_V  0xfc0ff07f
+#define MATCH_VFNCVT_XU_F_W 0x88081057
+#define MASK_VFNCVT_XU_F_W  0xfc0ff07f
+#define MATCH_VFNCVT_X_F_W 0x88089057
+#define MASK_VFNCVT_X_F_W  0xfc0ff07f
+#define MATCH_VFNCVT_F_XU_W 0x88091057
+#define MASK_VFNCVT_F_XU_W  0xfc0ff07f
+#define MATCH_VFNCVT_F_X_W 0x88099057
+#define MASK_VFNCVT_F_X_W  0xfc0ff07f
+#define MATCH_VFNCVT_F_F_W 0x880a1057
+#define MASK_VFNCVT_F_F_W  0xfc0ff07f
+#define MATCH_VFNCVT_ROD_F_F_W 0x880a9057
+#define MASK_VFNCVT_ROD_F_F_W  0xfc0ff07f
+#define MATCH_VFNCVT_RTZ_XU_F_W 0x880b1057
+#define MASK_VFNCVT_RTZ_XU_F_W  0xfc0ff07f
+#define MATCH_VFNCVT_RTZ_X_F_W 0x880b9057
+#define MASK_VFNCVT_RTZ_X_F_W  0xfc0ff07f
+#define MATCH_VFSQRT_V 0x8c001057
+#define MASK_VFSQRT_V  0xfc0ff07f
+#define MATCH_VFCLASS_V 0x8c081057
+#define MASK_VFCLASS_V  0xfc0ff07f
+#define MATCH_VFWADD_VV 0xc0001057
+#define MASK_VFWADD_VV  0xfc00707f
+#define MATCH_VFWREDSUM_VS 0xc4001057
+#define MASK_VFWREDSUM_VS  0xfc00707f
+#define MATCH_VFWSUB_VV 0xc8001057
+#define MASK_VFWSUB_VV  0xfc00707f
+#define MATCH_VFWREDOSUM_VS 0xcc001057
+#define MASK_VFWREDOSUM_VS  0xfc00707f
+#define MATCH_VFWADD_WV 0xd0001057
+#define MASK_VFWADD_WV  0xfc00707f
+#define MATCH_VFWSUB_WV 0xd8001057
+#define MASK_VFWSUB_WV  0xfc00707f
+#define MATCH_VFWMUL_VV 0xe0001057
+#define MASK_VFWMUL_VV  0xfc00707f
+#define MATCH_VFDOT_VV 0xe4001057
+#define MASK_VFDOT_VV  0xfc00707f
+#define MATCH_VFWMACC_VV 0xf0001057
+#define MASK_VFWMACC_VV  0xfc00707f
+#define MATCH_VFWNMACC_VV 0xf4001057
+#define MASK_VFWNMACC_VV  0xfc00707f
+#define MATCH_VFWMSAC_VV 0xf8001057
+#define MASK_VFWMSAC_VV  0xfc00707f
+#define MATCH_VFWNMSAC_VV 0xfc001057
+#define MASK_VFWNMSAC_VV  0xfc00707f
+#define MATCH_VADD_VX 0x4057
+#define MASK_VADD_VX  0xfc00707f
+#define MATCH_VSUB_VX 0x8004057
+#define MASK_VSUB_VX  0xfc00707f
+#define MATCH_VRSUB_VX 0xc004057
+#define MASK_VRSUB_VX  0xfc00707f
+#define MATCH_VMINU_VX 0x10004057
+#define MASK_VMINU_VX  0xfc00707f
+#define MATCH_VMIN_VX 0x14004057
+#define MASK_VMIN_VX  0xfc00707f
+#define MATCH_VMAXU_VX 0x18004057
+#define MASK_VMAXU_VX  0xfc00707f
+#define MATCH_VMAX_VX 0x1c004057
+#define MASK_VMAX_VX  0xfc00707f
+#define MATCH_VAND_VX 0x24004057
+#define MASK_VAND_VX  0xfc00707f
+#define MATCH_VOR_VX 0x28004057
+#define MASK_VOR_VX  0xfc00707f
+#define MATCH_VXOR_VX 0x2c004057
+#define MASK_VXOR_VX  0xfc00707f
+#define MATCH_VRGATHER_VX 0x30004057
+#define MASK_VRGATHER_VX  0xfc00707f
+#define MATCH_VSLIDEUP_VX 0x38004057
+#define MASK_VSLIDEUP_VX  0xfc00707f
+#define MATCH_VSLIDEDOWN_VX 0x3c004057
+#define MASK_VSLIDEDOWN_VX  0xfc00707f
+#define MATCH_VADC_VXM 0x40004057
+#define MASK_VADC_VXM  0xfe00707f
+#define MATCH_VMADC_VXM 0x44004057
+#define MASK_VMADC_VXM  0xfc00707f
+#define MATCH_VSBC_VXM 0x48004057
+#define MASK_VSBC_VXM  0xfe00707f
+#define MATCH_VMSBC_VXM 0x4c004057
+#define MASK_VMSBC_VXM  0xfc00707f
+#define MATCH_VMERGE_VXM 0x5c004057
+#define MASK_VMERGE_VXM  0xfe00707f
+#define MATCH_VMV_V_X 0x5e004057
+#define MASK_VMV_V_X  0xfff0707f
+#define MATCH_VMSEQ_VX 0x60004057
+#define MASK_VMSEQ_VX  0xfc00707f
+#define MATCH_VMSNE_VX 0x64004057
+#define MASK_VMSNE_VX  0xfc00707f
+#define MATCH_VMSLTU_VX 0x68004057
+#define MASK_VMSLTU_VX  0xfc00707f
+#define MATCH_VMSLT_VX 0x6c004057
+#define MASK_VMSLT_VX  0xfc00707f
+#define MATCH_VMSLEU_VX 0x70004057
+#define MASK_VMSLEU_VX  0xfc00707f
+#define MATCH_VMSLE_VX 0x74004057
+#define MASK_VMSLE_VX  0xfc00707f
+#define MATCH_VMSGTU_VX 0x78004057
+#define MASK_VMSGTU_VX  0xfc00707f
+#define MATCH_VMSGT_VX 0x7c004057
+#define MASK_VMSGT_VX  0xfc00707f
+#define MATCH_VSADDU_VX 0x80004057
+#define MASK_VSADDU_VX  0xfc00707f
+#define MATCH_VSADD_VX 0x84004057
+#define MASK_VSADD_VX  0xfc00707f
+#define MATCH_VSSUBU_VX 0x88004057
+#define MASK_VSSUBU_VX  0xfc00707f
+#define MATCH_VSSUB_VX 0x8c004057
+#define MASK_VSSUB_VX  0xfc00707f
+#define MATCH_VSLL_VX 0x94004057
+#define MASK_VSLL_VX  0xfc00707f
+#define MATCH_VSMUL_VX 0x9c004057
+#define MASK_VSMUL_VX  0xfc00707f
+#define MATCH_VSRL_VX 0xa0004057
+#define MASK_VSRL_VX  0xfc00707f
+#define MATCH_VSRA_VX 0xa4004057
+#define MASK_VSRA_VX  0xfc00707f
+#define MATCH_VSSRL_VX 0xa8004057
+#define MASK_VSSRL_VX  0xfc00707f
+#define MATCH_VSSRA_VX 0xac004057
+#define MASK_VSSRA_VX  0xfc00707f
+#define MATCH_VNSRL_WX 0xb0004057
+#define MASK_VNSRL_WX  0xfc00707f
+#define MATCH_VNSRA_WX 0xb4004057
+#define MASK_VNSRA_WX  0xfc00707f
+#define MATCH_VNCLIPU_WX 0xb8004057
+#define MASK_VNCLIPU_WX  0xfc00707f
+#define MATCH_VNCLIP_WX 0xbc004057
+#define MASK_VNCLIP_WX  0xfc00707f
+#define MATCH_VQMACCU_VX 0xf0004057
+#define MASK_VQMACCU_VX  0xfc00707f
+#define MATCH_VQMACC_VX 0xf4004057
+#define MASK_VQMACC_VX  0xfc00707f
+#define MATCH_VQMACCUS_VX 0xf8004057
+#define MASK_VQMACCUS_VX  0xfc00707f
+#define MATCH_VQMACCSU_VX 0xfc004057
+#define MASK_VQMACCSU_VX  0xfc00707f
+#define MATCH_VADD_VV 0x57
+#define MASK_VADD_VV  0xfc00707f
+#define MATCH_VSUB_VV 0x8000057
+#define MASK_VSUB_VV  0xfc00707f
+#define MATCH_VMINU_VV 0x10000057
+#define MASK_VMINU_VV  0xfc00707f
+#define MATCH_VMIN_VV 0x14000057
+#define MASK_VMIN_VV  0xfc00707f
+#define MATCH_VMAXU_VV 0x18000057
+#define MASK_VMAXU_VV  0xfc00707f
+#define MATCH_VMAX_VV 0x1c000057
+#define MASK_VMAX_VV  0xfc00707f
+#define MATCH_VAND_VV 0x24000057
+#define MASK_VAND_VV  0xfc00707f
+#define MATCH_VOR_VV 0x28000057
+#define MASK_VOR_VV  0xfc00707f
+#define MATCH_VXOR_VV 0x2c000057
+#define MASK_VXOR_VV  0xfc00707f
+#define MATCH_VRGATHER_VV 0x30000057
+#define MASK_VRGATHER_VV  0xfc00707f
+#define MATCH_VADC_VVM 0x40000057
+#define MASK_VADC_VVM  0xfe00707f
+#define MATCH_VMADC_VVM 0x44000057
+#define MASK_VMADC_VVM  0xfc00707f
+#define MATCH_VSBC_VVM 0x48000057
+#define MASK_VSBC_VVM  0xfe00707f
+#define MATCH_VMSBC_VVM 0x4c000057
+#define MASK_VMSBC_VVM  0xfc00707f
+#define MATCH_VMERGE_VVM 0x5c000057
+#define MASK_VMERGE_VVM  0xfe00707f
+#define MATCH_VMV_V_V 0x5e000057
+#define MASK_VMV_V_V  0xfff0707f
+#define MATCH_VMSEQ_VV 0x60000057
+#define MASK_VMSEQ_VV  0xfc00707f
+#define MATCH_VMSNE_VV 0x64000057
+#define MASK_VMSNE_VV  0xfc00707f
+#define MATCH_VMSLTU_VV 0x68000057
+#define MASK_VMSLTU_VV  0xfc00707f
+#define MATCH_VMSLT_VV 0x6c000057
+#define MASK_VMSLT_VV  0xfc00707f
+#define MATCH_VMSLEU_VV 0x70000057
+#define MASK_VMSLEU_VV  0xfc00707f
+#define MATCH_VMSLE_VV 0x74000057
+#define MASK_VMSLE_VV  0xfc00707f
+#define MATCH_VSADDU_VV 0x80000057
+#define MASK_VSADDU_VV  0xfc00707f
+#define MATCH_VSADD_VV 0x84000057
+#define MASK_VSADD_VV  0xfc00707f
+#define MATCH_VSSUBU_VV 0x88000057
+#define MASK_VSSUBU_VV  0xfc00707f
+#define MATCH_VSSUB_VV 0x8c000057
+#define MASK_VSSUB_VV  0xfc00707f
+#define MATCH_VSLL_VV 0x94000057
+#define MASK_VSLL_VV  0xfc00707f
+#define MATCH_VSMUL_VV 0x9c000057
+#define MASK_VSMUL_VV  0xfc00707f
+#define MATCH_VSRL_VV 0xa0000057
+#define MASK_VSRL_VV  0xfc00707f
+#define MATCH_VSRA_VV 0xa4000057
+#define MASK_VSRA_VV  0xfc00707f
+#define MATCH_VSSRL_VV 0xa8000057
+#define MASK_VSSRL_VV  0xfc00707f
+#define MATCH_VSSRA_VV 0xac000057
+#define MASK_VSSRA_VV  0xfc00707f
+#define MATCH_VNSRL_WV 0xb0000057
+#define MASK_VNSRL_WV  0xfc00707f
+#define MATCH_VNSRA_WV 0xb4000057
+#define MASK_VNSRA_WV  0xfc00707f
+#define MATCH_VNCLIPU_WV 0xb8000057
+#define MASK_VNCLIPU_WV  0xfc00707f
+#define MATCH_VNCLIP_WV 0xbc000057
+#define MASK_VNCLIP_WV  0xfc00707f
+#define MATCH_VWREDSUMU_VS 0xc0000057
+#define MASK_VWREDSUMU_VS  0xfc00707f
+#define MATCH_VWREDSUM_VS 0xc4000057
+#define MASK_VWREDSUM_VS  0xfc00707f
+#define MATCH_VDOTU_VV 0xe0000057
+#define MASK_VDOTU_VV  0xfc00707f
+#define MATCH_VDOT_VV 0xe4000057
+#define MASK_VDOT_VV  0xfc00707f
+#define MATCH_VQMACCU_VV 0xf0000057
+#define MASK_VQMACCU_VV  0xfc00707f
+#define MATCH_VQMACC_VV 0xf4000057
+#define MASK_VQMACC_VV  0xfc00707f
+#define MATCH_VQMACCSU_VV 0xfc000057
+#define MASK_VQMACCSU_VV  0xfc00707f
+#define MATCH_VADD_VI 0x3057
+#define MASK_VADD_VI  0xfc00707f
+#define MATCH_VRSUB_VI 0xc003057
+#define MASK_VRSUB_VI  0xfc00707f
+#define MATCH_VAND_VI 0x24003057
+#define MASK_VAND_VI  0xfc00707f
+#define MATCH_VOR_VI 0x28003057
+#define MASK_VOR_VI  0xfc00707f
+#define MATCH_VXOR_VI 0x2c003057
+#define MASK_VXOR_VI  0xfc00707f
+#define MATCH_VRGATHER_VI 0x30003057
+#define MASK_VRGATHER_VI  0xfc00707f
+#define MATCH_VSLIDEUP_VI 0x38003057
+#define MASK_VSLIDEUP_VI  0xfc00707f
+#define MATCH_VSLIDEDOWN_VI 0x3c003057
+#define MASK_VSLIDEDOWN_VI  0xfc00707f
+#define MATCH_VADC_VIM 0x40003057
+#define MASK_VADC_VIM  0xfe00707f
+#define MATCH_VMADC_VIM 0x44003057
+#define MASK_VMADC_VIM  0xfc00707f
+#define MATCH_VMERGE_VIM 0x5c003057
+#define MASK_VMERGE_VIM  0xfe00707f
+#define MATCH_VMV_V_I 0x5e003057
+#define MASK_VMV_V_I  0xfff0707f
+#define MATCH_VMSEQ_VI 0x60003057
+#define MASK_VMSEQ_VI  0xfc00707f
+#define MATCH_VMSNE_VI 0x64003057
+#define MASK_VMSNE_VI  0xfc00707f
+#define MATCH_VMSLEU_VI 0x70003057
+#define MASK_VMSLEU_VI  0xfc00707f
+#define MATCH_VMSLE_VI 0x74003057
+#define MASK_VMSLE_VI  0xfc00707f
+#define MATCH_VMSGTU_VI 0x78003057
+#define MASK_VMSGTU_VI  0xfc00707f
+#define MATCH_VMSGT_VI 0x7c003057
+#define MASK_VMSGT_VI  0xfc00707f
+#define MATCH_VSADDU_VI 0x80003057
+#define MASK_VSADDU_VI  0xfc00707f
+#define MATCH_VSADD_VI 0x84003057
+#define MASK_VSADD_VI  0xfc00707f
+#define MATCH_VSLL_VI 0x94003057
+#define MASK_VSLL_VI  0xfc00707f
+#define MATCH_VMV1R_V 0x9e003057
+#define MASK_VMV1R_V  0xfe0ff07f
+#define MATCH_VMV2R_V 0x9e00b057
+#define MASK_VMV2R_V  0xfe0ff07f
+#define MATCH_VMV4R_V 0x9e01b057
+#define MASK_VMV4R_V  0xfe0ff07f
+#define MATCH_VMV8R_V 0x9e03b057
+#define MASK_VMV8R_V  0xfe0ff07f
+#define MATCH_VSRL_VI 0xa0003057
+#define MASK_VSRL_VI  0xfc00707f
+#define MATCH_VSRA_VI 0xa4003057
+#define MASK_VSRA_VI  0xfc00707f
+#define MATCH_VSSRL_VI 0xa8003057
+#define MASK_VSSRL_VI  0xfc00707f
+#define MATCH_VSSRA_VI 0xac003057
+#define MASK_VSSRA_VI  0xfc00707f
+#define MATCH_VNSRL_WI 0xb0003057
+#define MASK_VNSRL_WI  0xfc00707f
+#define MATCH_VNSRA_WI 0xb4003057
+#define MASK_VNSRA_WI  0xfc00707f
+#define MATCH_VNCLIPU_WI 0xb8003057
+#define MASK_VNCLIPU_WI  0xfc00707f
+#define MATCH_VNCLIP_WI 0xbc003057
+#define MASK_VNCLIP_WI  0xfc00707f
+#define MATCH_VREDSUM_VS 0x2057
+#define MASK_VREDSUM_VS  0xfc00707f
+#define MATCH_VREDAND_VS 0x4002057
+#define MASK_VREDAND_VS  0xfc00707f
+#define MATCH_VREDOR_VS 0x8002057
+#define MASK_VREDOR_VS  0xfc00707f
+#define MATCH_VREDXOR_VS 0xc002057
+#define MASK_VREDXOR_VS  0xfc00707f
+#define MATCH_VREDMINU_VS 0x10002057
+#define MASK_VREDMINU_VS  0xfc00707f
+#define MATCH_VREDMIN_VS 0x14002057
+#define MASK_VREDMIN_VS  0xfc00707f
+#define MATCH_VREDMAXU_VS 0x18002057
+#define MASK_VREDMAXU_VS  0xfc00707f
+#define MATCH_VREDMAX_VS 0x1c002057
+#define MASK_VREDMAX_VS  0xfc00707f
+#define MATCH_VAADDU_VV 0x20002057
+#define MASK_VAADDU_VV  0xfc00707f
+#define MATCH_VAADD_VV 0x24002057
+#define MASK_VAADD_VV  0xfc00707f
+#define MATCH_VASUBU_VV 0x28002057
+#define MASK_VASUBU_VV  0xfc00707f
+#define MATCH_VASUB_VV 0x2c002057
+#define MASK_VASUB_VV  0xfc00707f
+#define MATCH_VMV_X_S 0x42002057
+#define MASK_VMV_X_S  0xfe0ff07f
+#define MATCH_VCOMPRESS_VM 0x5e002057
+#define MASK_VCOMPRESS_VM  0xfe00707f
+#define MATCH_VMANDNOT_MM 0x60002057
+#define MASK_VMANDNOT_MM  0xfc00707f
+#define MATCH_VMAND_MM 0x64002057
+#define MASK_VMAND_MM  0xfc00707f
+#define MATCH_VMOR_MM 0x68002057
+#define MASK_VMOR_MM  0xfc00707f
+#define MATCH_VMXOR_MM 0x6c002057
+#define MASK_VMXOR_MM  0xfc00707f
+#define MATCH_VMORNOT_MM 0x70002057
+#define MASK_VMORNOT_MM  0xfc00707f
+#define MATCH_VMNAND_MM 0x74002057
+#define MASK_VMNAND_MM  0xfc00707f
+#define MATCH_VMNOR_MM 0x78002057
+#define MASK_VMNOR_MM  0xfc00707f
+#define MATCH_VMXNOR_MM 0x7c002057
+#define MASK_VMXNOR_MM  0xfc00707f
+#define MATCH_VMSBF_M 0x5000a057
+#define MASK_VMSBF_M  0xfc0ff07f
+#define MATCH_VMSOF_M 0x50012057
+#define MASK_VMSOF_M  0xfc0ff07f
+#define MATCH_VMSIF_M 0x5001a057
+#define MASK_VMSIF_M  0xfc0ff07f
+#define MATCH_VIOTA_M 0x50082057
+#define MASK_VIOTA_M  0xfc0ff07f
+#define MATCH_VID_V 0x5008a057
+#define MASK_VID_V  0xfdfff07f
+#define MATCH_VPOPC_M 0x40082057
+#define MASK_VPOPC_M  0xfc0ff07f
+#define MATCH_VFIRST_M 0x4008a057
+#define MASK_VFIRST_M  0xfc0ff07f
+#define MATCH_VDIVU_VV 0x80002057
+#define MASK_VDIVU_VV  0xfc00707f
+#define MATCH_VDIV_VV 0x84002057
+#define MASK_VDIV_VV  0xfc00707f
+#define MATCH_VREMU_VV 0x88002057
+#define MASK_VREMU_VV  0xfc00707f
+#define MATCH_VREM_VV 0x8c002057
+#define MASK_VREM_VV  0xfc00707f
+#define MATCH_VMULHU_VV 0x90002057
+#define MASK_VMULHU_VV  0xfc00707f
+#define MATCH_VMUL_VV 0x94002057
+#define MASK_VMUL_VV  0xfc00707f
+#define MATCH_VMULHSU_VV 0x98002057
+#define MASK_VMULHSU_VV  0xfc00707f
+#define MATCH_VMULH_VV 0x9c002057
+#define MASK_VMULH_VV  0xfc00707f
+#define MATCH_VMADD_VV 0xa4002057
+#define MASK_VMADD_VV  0xfc00707f
+#define MATCH_VNMSUB_VV 0xac002057
+#define MASK_VNMSUB_VV  0xfc00707f
+#define MATCH_VMACC_VV 0xb4002057
+#define MASK_VMACC_VV  0xfc00707f
+#define MATCH_VNMSAC_VV 0xbc002057
+#define MASK_VNMSAC_VV  0xfc00707f
+#define MATCH_VWADDU_VV 0xc0002057
+#define MASK_VWADDU_VV  0xfc00707f
+#define MATCH_VWADD_VV 0xc4002057
+#define MASK_VWADD_VV  0xfc00707f
+#define MATCH_VWSUBU_VV 0xc8002057
+#define MASK_VWSUBU_VV  0xfc00707f
+#define MATCH_VWSUB_VV 0xcc002057
+#define MASK_VWSUB_VV  0xfc00707f
+#define MATCH_VWADDU_WV 0xd0002057
+#define MASK_VWADDU_WV  0xfc00707f
+#define MATCH_VWADD_WV 0xd4002057
+#define MASK_VWADD_WV  0xfc00707f
+#define MATCH_VWSUBU_WV 0xd8002057
+#define MASK_VWSUBU_WV  0xfc00707f
+#define MATCH_VWSUB_WV 0xdc002057
+#define MASK_VWSUB_WV  0xfc00707f
+#define MATCH_VWMULU_VV 0xe0002057
+#define MASK_VWMULU_VV  0xfc00707f
+#define MATCH_VWMULSU_VV 0xe8002057
+#define MASK_VWMULSU_VV  0xfc00707f
+#define MATCH_VWMUL_VV 0xec002057
+#define MASK_VWMUL_VV  0xfc00707f
+#define MATCH_VWMACCU_VV 0xf0002057
+#define MASK_VWMACCU_VV  0xfc00707f
+#define MATCH_VWMACC_VV 0xf4002057
+#define MASK_VWMACC_VV  0xfc00707f
+#define MATCH_VWMACCSU_VV 0xfc002057
+#define MASK_VWMACCSU_VV  0xfc00707f
+#define MATCH_VAADDU_VX 0x20006057
+#define MASK_VAADDU_VX  0xfc00707f
+#define MATCH_VAADD_VX 0x24006057
+#define MASK_VAADD_VX  0xfc00707f
+#define MATCH_VASUBU_VX 0x28006057
+#define MASK_VASUBU_VX  0xfc00707f
+#define MATCH_VASUB_VX 0x2c006057
+#define MASK_VASUB_VX  0xfc00707f
+#define MATCH_VMV_S_X 0x42006057
+#define MASK_VMV_S_X  0xfff0707f
+#define MATCH_VSLIDE1UP_VX 0x38006057
+#define MASK_VSLIDE1UP_VX  0xfc00707f
+#define MATCH_VSLIDE1DOWN_VX 0x3c006057
+#define MASK_VSLIDE1DOWN_VX  0xfc00707f
+#define MATCH_VDIVU_VX 0x80006057
+#define MASK_VDIVU_VX  0xfc00707f
+#define MATCH_VDIV_VX 0x84006057
+#define MASK_VDIV_VX  0xfc00707f
+#define MATCH_VREMU_VX 0x88006057
+#define MASK_VREMU_VX  0xfc00707f
+#define MATCH_VREM_VX 0x8c006057
+#define MASK_VREM_VX  0xfc00707f
+#define MATCH_VMULHU_VX 0x90006057
+#define MASK_VMULHU_VX  0xfc00707f
+#define MATCH_VMUL_VX 0x94006057
+#define MASK_VMUL_VX  0xfc00707f
+#define MATCH_VMULHSU_VX 0x98006057
+#define MASK_VMULHSU_VX  0xfc00707f
+#define MATCH_VMULH_VX 0x9c006057
+#define MASK_VMULH_VX  0xfc00707f
+#define MATCH_VMADD_VX 0xa4006057
+#define MASK_VMADD_VX  0xfc00707f
+#define MATCH_VNMSUB_VX 0xac006057
+#define MASK_VNMSUB_VX  0xfc00707f
+#define MATCH_VMACC_VX 0xb4006057
+#define MASK_VMACC_VX  0xfc00707f
+#define MATCH_VNMSAC_VX 0xbc006057
+#define MASK_VNMSAC_VX  0xfc00707f
+#define MATCH_VWADDU_VX 0xc0006057
+#define MASK_VWADDU_VX  0xfc00707f
+#define MATCH_VWADD_VX 0xc4006057
+#define MASK_VWADD_VX  0xfc00707f
+#define MATCH_VWSUBU_VX 0xc8006057
+#define MASK_VWSUBU_VX  0xfc00707f
+#define MATCH_VWSUB_VX 0xcc006057
+#define MASK_VWSUB_VX  0xfc00707f
+#define MATCH_VWADDU_WX 0xd0006057
+#define MASK_VWADDU_WX  0xfc00707f
+#define MATCH_VWADD_WX 0xd4006057
+#define MASK_VWADD_WX  0xfc00707f
+#define MATCH_VWSUBU_WX 0xd8006057
+#define MASK_VWSUBU_WX  0xfc00707f
+#define MATCH_VWSUB_WX 0xdc006057
+#define MASK_VWSUB_WX  0xfc00707f
+#define MATCH_VWMULU_VX 0xe0006057
+#define MASK_VWMULU_VX  0xfc00707f
+#define MATCH_VWMULSU_VX 0xe8006057
+#define MASK_VWMULSU_VX  0xfc00707f
+#define MATCH_VWMUL_VX 0xec006057
+#define MASK_VWMUL_VX  0xfc00707f
+#define MATCH_VWMACCU_VX 0xf0006057
+#define MASK_VWMACCU_VX  0xfc00707f
+#define MATCH_VWMACC_VX 0xf4006057
+#define MASK_VWMACC_VX  0xfc00707f
+#define MATCH_VWMACCUS_VX 0xf8006057
+#define MASK_VWMACCUS_VX  0xfc00707f
+#define MATCH_VWMACCSU_VX 0xfc006057
+#define MASK_VWMACCSU_VX  0xfc00707f
+#define MATCH_VAMOSWAPW_V 0x800602f
+#define MASK_VAMOSWAPW_V  0xf800707f
+#define MATCH_VAMOADDW_V 0x602f
+#define MASK_VAMOADDW_V  0xf800707f
+#define MATCH_VAMOXORW_V 0x2000602f
+#define MASK_VAMOXORW_V  0xf800707f
+#define MATCH_VAMOANDW_V 0x6000602f
+#define MASK_VAMOANDW_V  0xf800707f
+#define MATCH_VAMOORW_V 0x4000602f
+#define MASK_VAMOORW_V  0xf800707f
+#define MATCH_VAMOMINW_V 0x8000602f
+#define MASK_VAMOMINW_V  0xf800707f
+#define MATCH_VAMOMAXW_V 0xa000602f
+#define MASK_VAMOMAXW_V  0xf800707f
+#define MATCH_VAMOMINUW_V 0xc000602f
+#define MASK_VAMOMINUW_V  0xf800707f
+#define MATCH_VAMOMAXUW_V 0xe000602f
+#define MASK_VAMOMAXUW_V  0xf800707f
+#define MATCH_VAMOSWAPE_V 0x800702f
+#define MASK_VAMOSWAPE_V  0xf800707f
+#define MATCH_VAMOADDE_V 0x702f
+#define MASK_VAMOADDE_V  0xf800707f
+#define MATCH_VAMOXORE_V 0x2000702f
+#define MASK_VAMOXORE_V  0xf800707f
+#define MATCH_VAMOANDE_V 0x6000702f
+#define MASK_VAMOANDE_V  0xf800707f
+#define MATCH_VAMOORE_V 0x4000702f
+#define MASK_VAMOORE_V  0xf800707f
+#define MATCH_VAMOMINE_V 0x8000702f
+#define MASK_VAMOMINE_V  0xf800707f
+#define MATCH_VAMOMAXE_V 0xa000702f
+#define MASK_VAMOMAXE_V  0xf800707f
+#define MATCH_VAMOMINUE_V 0xc000702f
+#define MASK_VAMOMINUE_V  0xf800707f
+#define MATCH_VAMOMAXUE_V 0xe000702f
+#define MASK_VAMOMAXUE_V  0xf800707f
+#define MATCH_VMVNFR_V 0x9e003057
+#define MASK_VMVNFR_V  0xfe00707f
+#define CSR_FFLAGS 0x1
+#define CSR_FRM 0x2
+#define CSR_FCSR 0x3
+#define CSR_USTATUS 0x0
+#define CSR_UIE 0x4
+#define CSR_UTVEC 0x5
+#define CSR_VSTART 0x8
+#define CSR_VXSAT 0x9
+#define CSR_VXRM 0xa
+#define CSR_VCSR 0xf
+#define CSR_USCRATCH 0x40
+#define CSR_UEPC 0x41
+#define CSR_UCAUSE 0x42
+#define CSR_UTVAL 0x43
+#define CSR_UIP 0x44
+#define CSR_CYCLE 0xc00
+#define CSR_TIME 0xc01
+#define CSR_INSTRET 0xc02
+#define CSR_HPMCOUNTER3 0xc03
+#define CSR_HPMCOUNTER4 0xc04
+#define CSR_HPMCOUNTER5 0xc05
+#define CSR_HPMCOUNTER6 0xc06
+#define CSR_HPMCOUNTER7 0xc07
+#define CSR_HPMCOUNTER8 0xc08
+#define CSR_HPMCOUNTER9 0xc09
+#define CSR_HPMCOUNTER10 0xc0a
+#define CSR_HPMCOUNTER11 0xc0b
+#define CSR_HPMCOUNTER12 0xc0c
+#define CSR_HPMCOUNTER13 0xc0d
+#define CSR_HPMCOUNTER14 0xc0e
+#define CSR_HPMCOUNTER15 0xc0f
+#define CSR_HPMCOUNTER16 0xc10
+#define CSR_HPMCOUNTER17 0xc11
+#define CSR_HPMCOUNTER18 0xc12
+#define CSR_HPMCOUNTER19 0xc13
+#define CSR_HPMCOUNTER20 0xc14
+#define CSR_HPMCOUNTER21 0xc15
+#define CSR_HPMCOUNTER22 0xc16
+#define CSR_HPMCOUNTER23 0xc17
+#define CSR_HPMCOUNTER24 0xc18
+#define CSR_HPMCOUNTER25 0xc19
+#define CSR_HPMCOUNTER26 0xc1a
+#define CSR_HPMCOUNTER27 0xc1b
+#define CSR_HPMCOUNTER28 0xc1c
+#define CSR_HPMCOUNTER29 0xc1d
+#define CSR_HPMCOUNTER30 0xc1e
+#define CSR_HPMCOUNTER31 0xc1f
+#define CSR_VL 0xc20
+#define CSR_VTYPE 0xc21
+#define CSR_VLENB 0xc22
+#define CSR_SSTATUS 0x100
+#define CSR_SEDELEG 0x102
+#define CSR_SIDELEG 0x103
+#define CSR_SIE 0x104
+#define CSR_STVEC 0x105
+#define CSR_SCOUNTEREN 0x106
+#define CSR_SSCRATCH 0x140
+#define CSR_SEPC 0x141
+#define CSR_SCAUSE 0x142
+#define CSR_STVAL 0x143
+#define CSR_SIP 0x144
+#define CSR_SATP 0x180
+#define CSR_VSSTATUS 0x200
+#define CSR_VSIE 0x204
+#define CSR_VSTVEC 0x205
+#define CSR_VSSCRATCH 0x240
+#define CSR_VSEPC 0x241
+#define CSR_VSCAUSE 0x242
+#define CSR_VSTVAL 0x243
+#define CSR_VSIP 0x244
+#define CSR_VSATP 0x280
+#define CSR_HSTATUS 0x600
+#define CSR_HEDELEG 0x602
+#define CSR_HIDELEG 0x603
+#define CSR_HIE 0x604
+#define CSR_HTIMEDELTA 0x605
+#define CSR_HCOUNTEREN 0x606
+#define CSR_HGEIE 0x607
+#define CSR_HTVAL 0x643
+#define CSR_HIP 0x644
+#define CSR_HVIP 0x645
+#define CSR_HTINST 0x64a
+#define CSR_HGATP 0x680
+#define CSR_HGEIP 0xe12
+#define CSR_UTVT 0x7
+#define CSR_UNXTI 0x45
+#define CSR_UINTSTATUS 0x46
+#define CSR_USCRATCHCSW 0x48
+#define CSR_USCRATCHCSWL 0x49
+#define CSR_STVT 0x107
+#define CSR_SNXTI 0x145
+#define CSR_SINTSTATUS 0x146
+#define CSR_SSCRATCHCSW 0x148
+#define CSR_SSCRATCHCSWL 0x149
+#define CSR_MTVT 0x307
+#define CSR_MNXTI 0x345
+#define CSR_MINTSTATUS 0x346
+#define CSR_MSCRATCHCSW 0x348
+#define CSR_MSCRATCHCSWL 0x349
+#define CSR_MSTATUS 0x300
+#define CSR_MISA 0x301
+#define CSR_MEDELEG 0x302
+#define CSR_MIDELEG 0x303
+#define CSR_MIE 0x304
+#define CSR_MTVEC 0x305
+#define CSR_MCOUNTEREN 0x306
+#define CSR_MCOUNTINHIBIT 0x320
+#define CSR_MSCRATCH 0x340
+#define CSR_MEPC 0x341
+#define CSR_MCAUSE 0x342
+#define CSR_MTVAL 0x343
+#define CSR_MIP 0x344
+#define CSR_MTINST 0x34a
+#define CSR_MTVAL2 0x34b
+#define CSR_PMPCFG0 0x3a0
+#define CSR_PMPCFG1 0x3a1
+#define CSR_PMPCFG2 0x3a2
+#define CSR_PMPCFG3 0x3a3
+#define CSR_PMPADDR0 0x3b0
+#define CSR_PMPADDR1 0x3b1
+#define CSR_PMPADDR2 0x3b2
+#define CSR_PMPADDR3 0x3b3
+#define CSR_PMPADDR4 0x3b4
+#define CSR_PMPADDR5 0x3b5
+#define CSR_PMPADDR6 0x3b6
+#define CSR_PMPADDR7 0x3b7
+#define CSR_PMPADDR8 0x3b8
+#define CSR_PMPADDR9 0x3b9
+#define CSR_PMPADDR10 0x3ba
+#define CSR_PMPADDR11 0x3bb
+#define CSR_PMPADDR12 0x3bc
+#define CSR_PMPADDR13 0x3bd
+#define CSR_PMPADDR14 0x3be
+#define CSR_PMPADDR15 0x3bf
+#define CSR_TSELECT 0x7a0
+#define CSR_TDATA1 0x7a1
+#define CSR_TDATA2 0x7a2
+#define CSR_TDATA3 0x7a3
+#define CSR_DCSR 0x7b0
+#define CSR_DPC 0x7b1
+#define CSR_DSCRATCH0 0x7b2
+#define CSR_DSCRATCH1 0x7b3
+#define CSR_MCYCLE 0xb00
+#define CSR_MINSTRET 0xb02
+#define CSR_MHPMCOUNTER3 0xb03
+#define CSR_MHPMCOUNTER4 0xb04
+#define CSR_MHPMCOUNTER5 0xb05
+#define CSR_MHPMCOUNTER6 0xb06
+#define CSR_MHPMCOUNTER7 0xb07
+#define CSR_MHPMCOUNTER8 0xb08
+#define CSR_MHPMCOUNTER9 0xb09
+#define CSR_MHPMCOUNTER10 0xb0a
+#define CSR_MHPMCOUNTER11 0xb0b
+#define CSR_MHPMCOUNTER12 0xb0c
+#define CSR_MHPMCOUNTER13 0xb0d
+#define CSR_MHPMCOUNTER14 0xb0e
+#define CSR_MHPMCOUNTER15 0xb0f
+#define CSR_MHPMCOUNTER16 0xb10
+#define CSR_MHPMCOUNTER17 0xb11
+#define CSR_MHPMCOUNTER18 0xb12
+#define CSR_MHPMCOUNTER19 0xb13
+#define CSR_MHPMCOUNTER20 0xb14
+#define CSR_MHPMCOUNTER21 0xb15
+#define CSR_MHPMCOUNTER22 0xb16
+#define CSR_MHPMCOUNTER23 0xb17
+#define CSR_MHPMCOUNTER24 0xb18
+#define CSR_MHPMCOUNTER25 0xb19
+#define CSR_MHPMCOUNTER26 0xb1a
+#define CSR_MHPMCOUNTER27 0xb1b
+#define CSR_MHPMCOUNTER28 0xb1c
+#define CSR_MHPMCOUNTER29 0xb1d
+#define CSR_MHPMCOUNTER30 0xb1e
+#define CSR_MHPMCOUNTER31 0xb1f
+#define CSR_MHPMEVENT3 0x323
+#define CSR_MHPMEVENT4 0x324
+#define CSR_MHPMEVENT5 0x325
+#define CSR_MHPMEVENT6 0x326
+#define CSR_MHPMEVENT7 0x327
+#define CSR_MHPMEVENT8 0x328
+#define CSR_MHPMEVENT9 0x329
+#define CSR_MHPMEVENT10 0x32a
+#define CSR_MHPMEVENT11 0x32b
+#define CSR_MHPMEVENT12 0x32c
+#define CSR_MHPMEVENT13 0x32d
+#define CSR_MHPMEVENT14 0x32e
+#define CSR_MHPMEVENT15 0x32f
+#define CSR_MHPMEVENT16 0x330
+#define CSR_MHPMEVENT17 0x331
+#define CSR_MHPMEVENT18 0x332
+#define CSR_MHPMEVENT19 0x333
+#define CSR_MHPMEVENT20 0x334
+#define CSR_MHPMEVENT21 0x335
+#define CSR_MHPMEVENT22 0x336
+#define CSR_MHPMEVENT23 0x337
+#define CSR_MHPMEVENT24 0x338
+#define CSR_MHPMEVENT25 0x339
+#define CSR_MHPMEVENT26 0x33a
+#define CSR_MHPMEVENT27 0x33b
+#define CSR_MHPMEVENT28 0x33c
+#define CSR_MHPMEVENT29 0x33d
+#define CSR_MHPMEVENT30 0x33e
+#define CSR_MHPMEVENT31 0x33f
+#define CSR_MVENDORID 0xf11
+#define CSR_MARCHID 0xf12
+#define CSR_MIMPID 0xf13
+#define CSR_MHARTID 0xf14
+#define CSR_HTIMEDELTAH 0x615
+#define CSR_CYCLEH 0xc80
+#define CSR_TIMEH 0xc81
+#define CSR_INSTRETH 0xc82
+#define CSR_HPMCOUNTER3H 0xc83
+#define CSR_HPMCOUNTER4H 0xc84
+#define CSR_HPMCOUNTER5H 0xc85
+#define CSR_HPMCOUNTER6H 0xc86
+#define CSR_HPMCOUNTER7H 0xc87
+#define CSR_HPMCOUNTER8H 0xc88
+#define CSR_HPMCOUNTER9H 0xc89
+#define CSR_HPMCOUNTER10H 0xc8a
+#define CSR_HPMCOUNTER11H 0xc8b
+#define CSR_HPMCOUNTER12H 0xc8c
+#define CSR_HPMCOUNTER13H 0xc8d
+#define CSR_HPMCOUNTER14H 0xc8e
+#define CSR_HPMCOUNTER15H 0xc8f
+#define CSR_HPMCOUNTER16H 0xc90
+#define CSR_HPMCOUNTER17H 0xc91
+#define CSR_HPMCOUNTER18H 0xc92
+#define CSR_HPMCOUNTER19H 0xc93
+#define CSR_HPMCOUNTER20H 0xc94
+#define CSR_HPMCOUNTER21H 0xc95
+#define CSR_HPMCOUNTER22H 0xc96
+#define CSR_HPMCOUNTER23H 0xc97
+#define CSR_HPMCOUNTER24H 0xc98
+#define CSR_HPMCOUNTER25H 0xc99
+#define CSR_HPMCOUNTER26H 0xc9a
+#define CSR_HPMCOUNTER27H 0xc9b
+#define CSR_HPMCOUNTER28H 0xc9c
+#define CSR_HPMCOUNTER29H 0xc9d
+#define CSR_HPMCOUNTER30H 0xc9e
+#define CSR_HPMCOUNTER31H 0xc9f
+#define CSR_MSTATUSH 0x310
+#define CSR_MCYCLEH 0xb80
+#define CSR_MINSTRETH 0xb82
+#define CSR_MHPMCOUNTER3H 0xb83
+#define CSR_MHPMCOUNTER4H 0xb84
+#define CSR_MHPMCOUNTER5H 0xb85
+#define CSR_MHPMCOUNTER6H 0xb86
+#define CSR_MHPMCOUNTER7H 0xb87
+#define CSR_MHPMCOUNTER8H 0xb88
+#define CSR_MHPMCOUNTER9H 0xb89
+#define CSR_MHPMCOUNTER10H 0xb8a
+#define CSR_MHPMCOUNTER11H 0xb8b
+#define CSR_MHPMCOUNTER12H 0xb8c
+#define CSR_MHPMCOUNTER13H 0xb8d
+#define CSR_MHPMCOUNTER14H 0xb8e
+#define CSR_MHPMCOUNTER15H 0xb8f
+#define CSR_MHPMCOUNTER16H 0xb90
+#define CSR_MHPMCOUNTER17H 0xb91
+#define CSR_MHPMCOUNTER18H 0xb92
+#define CSR_MHPMCOUNTER19H 0xb93
+#define CSR_MHPMCOUNTER20H 0xb94
+#define CSR_MHPMCOUNTER21H 0xb95
+#define CSR_MHPMCOUNTER22H 0xb96
+#define CSR_MHPMCOUNTER23H 0xb97
+#define CSR_MHPMCOUNTER24H 0xb98
+#define CSR_MHPMCOUNTER25H 0xb99
+#define CSR_MHPMCOUNTER26H 0xb9a
+#define CSR_MHPMCOUNTER27H 0xb9b
+#define CSR_MHPMCOUNTER28H 0xb9c
+#define CSR_MHPMCOUNTER29H 0xb9d
+#define CSR_MHPMCOUNTER30H 0xb9e
+#define CSR_MHPMCOUNTER31H 0xb9f
+#define CAUSE_MISALIGNED_FETCH 0x0
+#define CAUSE_FETCH_ACCESS 0x1
+#define CAUSE_ILLEGAL_INSTRUCTION 0x2
+#define CAUSE_BREAKPOINT 0x3
+#define CAUSE_MISALIGNED_LOAD 0x4
+#define CAUSE_LOAD_ACCESS 0x5
+#define CAUSE_MISALIGNED_STORE 0x6
+#define CAUSE_STORE_ACCESS 0x7
+#define CAUSE_USER_ECALL 0x8
+#define CAUSE_SUPERVISOR_ECALL 0x9
+#define CAUSE_HYPERVISOR_ECALL 0xa
+#define CAUSE_MACHINE_ECALL 0xb
+#define CAUSE_FETCH_PAGE_FAULT 0xc
+#define CAUSE_LOAD_PAGE_FAULT 0xd
+#define CAUSE_STORE_PAGE_FAULT 0xf
+#endif
+#ifdef DECLARE_INSN
+DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32)
+DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32)
+DECLARE_INSN(srai_rv32, MATCH_SRAI_RV32, MASK_SRAI_RV32)
+DECLARE_INSN(frflags, MATCH_FRFLAGS, MASK_FRFLAGS)
+DECLARE_INSN(fsflags, MATCH_FSFLAGS, MASK_FSFLAGS)
+DECLARE_INSN(fsflagsi, MATCH_FSFLAGSI, MASK_FSFLAGSI)
+DECLARE_INSN(frrm, MATCH_FRRM, MASK_FRRM)
+DECLARE_INSN(fsrm, MATCH_FSRM, MASK_FSRM)
+DECLARE_INSN(fsrmi, MATCH_FSRMI, MASK_FSRMI)
+DECLARE_INSN(fscsr, MATCH_FSCSR, MASK_FSCSR)
+DECLARE_INSN(frcsr, MATCH_FRCSR, MASK_FRCSR)
+DECLARE_INSN(rdcycle, MATCH_RDCYCLE, MASK_RDCYCLE)
+DECLARE_INSN(rdtime, MATCH_RDTIME, MASK_RDTIME)
+DECLARE_INSN(rdinstret, MATCH_RDINSTRET, MASK_RDINSTRET)
+DECLARE_INSN(rdcycleh, MATCH_RDCYCLEH, MASK_RDCYCLEH)
+DECLARE_INSN(rdtimeh, MATCH_RDTIMEH, MASK_RDTIMEH)
+DECLARE_INSN(rdinstreth, MATCH_RDINSTRETH, MASK_RDINSTRETH)
+DECLARE_INSN(scall, MATCH_SCALL, MASK_SCALL)
+DECLARE_INSN(sbreak, MATCH_SBREAK, MASK_SBREAK)
+DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S)
+DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X)
+DECLARE_INSN(fence_tso, MATCH_FENCE_TSO, MASK_FENCE_TSO)
+DECLARE_INSN(pause, MATCH_PAUSE, MASK_PAUSE)
+DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
+DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
+DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
+DECLARE_INSN(bge, MATCH_BGE, MASK_BGE)
+DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU)
+DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU)
+DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR)
+DECLARE_INSN(jal, MATCH_JAL, MASK_JAL)
+DECLARE_INSN(lui, MATCH_LUI, MASK_LUI)
+DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC)
+DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI)
+DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
+DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI)
+DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU)
+DECLARE_INSN(xori, MATCH_XORI, MASK_XORI)
+DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI)
+DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)
+DECLARE_INSN(ori, MATCH_ORI, MASK_ORI)
+DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI)
+DECLARE_INSN(add, MATCH_ADD, MASK_ADD)
+DECLARE_INSN(sub, MATCH_SUB, MASK_SUB)
+DECLARE_INSN(sll, MATCH_SLL, MASK_SLL)
+DECLARE_INSN(slt, MATCH_SLT, MASK_SLT)
+DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU)
+DECLARE_INSN(xor, MATCH_XOR, MASK_XOR)
+DECLARE_INSN(srl, MATCH_SRL, MASK_SRL)
+DECLARE_INSN(sra, MATCH_SRA, MASK_SRA)
+DECLARE_INSN(or, MATCH_OR, MASK_OR)
+DECLARE_INSN(and, MATCH_AND, MASK_AND)
+DECLARE_INSN(lb, MATCH_LB, MASK_LB)
+DECLARE_INSN(lh, MATCH_LH, MASK_LH)
+DECLARE_INSN(lw, MATCH_LW, MASK_LW)
+DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)
+DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)
+DECLARE_INSN(sb, MATCH_SB, MASK_SB)
+DECLARE_INSN(sh, MATCH_SH, MASK_SH)
+DECLARE_INSN(sw, MATCH_SW, MASK_SW)
+DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)
+DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)
+DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW)
+DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)
+DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW)
+DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW)
+DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW)
+DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW)
+DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW)
+DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW)
+DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW)
+DECLARE_INSN(ld, MATCH_LD, MASK_LD)
+DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU)
+DECLARE_INSN(sd, MATCH_SD, MASK_SD)
+DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
+DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH)
+DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
+DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU)
+DECLARE_INSN(div, MATCH_DIV, MASK_DIV)
+DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU)
+DECLARE_INSN(rem, MATCH_REM, MASK_REM)
+DECLARE_INSN(remu, MATCH_REMU, MASK_REMU)
+DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW)
+DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
+DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
+DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
+DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
+DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)
+DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W)
+DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)
+DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W)
+DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W)
+DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W)
+DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W)
+DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W)
+DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W)
+DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W)
+DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W)
+DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D)
+DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D)
+DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D)
+DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D)
+DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D)
+DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D)
+DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D)
+DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D)
+DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D)
+DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D)
+DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D)
+DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S)
+DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
+DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)
+DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S)
+DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S)
+DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S)
+DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S)
+DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S)
+DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S)
+DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S)
+DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
+DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
+DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
+DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
+DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
+DECLARE_INSN(fmv_x_w, MATCH_FMV_X_W, MASK_FMV_X_W)
+DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
+DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
+DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
+DECLARE_INSN(fmv_w_x, MATCH_FMV_W_X, MASK_FMV_W_X)
+DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
+DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
+DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
+DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
+DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
+DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S)
+DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
+DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)
+DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
+DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)
+DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D)
+DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D)
+DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D)
+DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D)
+DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D)
+DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D)
+DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D)
+DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D)
+DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)
+DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
+DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
+DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
+DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
+DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
+DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
+DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)
+DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
+DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
+DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)
+DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
+DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
+DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
+DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
+DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
+DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
+DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
+DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
+DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
+DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
+DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
+DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
+DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
+DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q)
+DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q)
+DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q)
+DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q)
+DECLARE_INSN(fsgnj_q, MATCH_FSGNJ_Q, MASK_FSGNJ_Q)
+DECLARE_INSN(fsgnjn_q, MATCH_FSGNJN_Q, MASK_FSGNJN_Q)
+DECLARE_INSN(fsgnjx_q, MATCH_FSGNJX_Q, MASK_FSGNJX_Q)
+DECLARE_INSN(fmin_q, MATCH_FMIN_Q, MASK_FMIN_Q)
+DECLARE_INSN(fmax_q, MATCH_FMAX_Q, MASK_FMAX_Q)
+DECLARE_INSN(fcvt_s_q, MATCH_FCVT_S_Q, MASK_FCVT_S_Q)
+DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S)
+DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q)
+DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D)
+DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q)
+DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q)
+DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q)
+DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q)
+DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q)
+DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q)
+DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q)
+DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W)
+DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU)
+DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ)
+DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ)
+DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q)
+DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q)
+DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q)
+DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q)
+DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q)
+DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q)
+DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L)
+DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU)
+DECLARE_INSN(fmv_x_q, MATCH_FMV_X_Q, MASK_FMV_X_Q)
+DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X)
+DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL)
+DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK)
+DECLARE_INSN(uret, MATCH_URET, MASK_URET)
+DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
+DECLARE_INSN(mret, MATCH_MRET, MASK_MRET)
+DECLARE_INSN(dret, MATCH_DRET, MASK_DRET)
+DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA)
+DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
+DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
+DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
+DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
+DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
+DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
+DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
+DECLARE_INSN(hfence_vvma, MATCH_HFENCE_VVMA, MASK_HFENCE_VVMA)
+DECLARE_INSN(hfence_gvma, MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA)
+DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP)
+DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP)
+DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR)
+DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR)
+DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK)
+DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN)
+DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD)
+DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW)
+DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW)
+DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD)
+DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW)
+DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW)
+DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI)
+DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL)
+DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI)
+DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI)
+DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI)
+DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI)
+DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI)
+DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB)
+DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR)
+DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR)
+DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND)
+DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J)
+DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ)
+DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ)
+DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI)
+DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP)
+DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP)
+DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP)
+DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV)
+DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD)
+DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP)
+DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP)
+DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP)
+DECLARE_INSN(c_srli_rv32, MATCH_C_SRLI_RV32, MASK_C_SRLI_RV32)
+DECLARE_INSN(c_srai_rv32, MATCH_C_SRAI_RV32, MASK_C_SRAI_RV32)
+DECLARE_INSN(c_slli_rv32, MATCH_C_SLLI_RV32, MASK_C_SLLI_RV32)
+DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD)
+DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD)
+DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW)
+DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW)
+DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW)
+DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP)
+DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
+DECLARE_INSN(c_lq, MATCH_C_LQ, MASK_C_LQ)
+DECLARE_INSN(c_sq, MATCH_C_SQ, MASK_C_SQ)
+DECLARE_INSN(c_lqsp, MATCH_C_LQSP, MASK_C_LQSP)
+DECLARE_INSN(c_sqsp, MATCH_C_SQSP, MASK_C_SQSP)
+DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0)
+DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1)
+DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2)
+DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD)
+DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1)
+DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2)
+DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1)
+DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1)
+DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2)
+DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD)
+DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1)
+DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2)
+DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2)
+DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1)
+DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2)
+DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD)
+DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1)
+DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2)
+DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3)
+DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1)
+DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)
+DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
+DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
+DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
+DECLARE_INSN(vsetvli, MATCH_VSETVLI, MASK_VSETVLI)
+DECLARE_INSN(vsetvl, MATCH_VSETVL, MASK_VSETVL)
+DECLARE_INSN(vlb_v, MATCH_VLB_V, MASK_VLB_V)
+DECLARE_INSN(vlh_v, MATCH_VLH_V, MASK_VLH_V)
+DECLARE_INSN(vlw_v, MATCH_VLW_V, MASK_VLW_V)
+DECLARE_INSN(vle_v, MATCH_VLE_V, MASK_VLE_V)
+DECLARE_INSN(vlbu_v, MATCH_VLBU_V, MASK_VLBU_V)
+DECLARE_INSN(vlhu_v, MATCH_VLHU_V, MASK_VLHU_V)
+DECLARE_INSN(vlwu_v, MATCH_VLWU_V, MASK_VLWU_V)
+DECLARE_INSN(vsb_v, MATCH_VSB_V, MASK_VSB_V)
+DECLARE_INSN(vsh_v, MATCH_VSH_V, MASK_VSH_V)
+DECLARE_INSN(vsw_v, MATCH_VSW_V, MASK_VSW_V)
+DECLARE_INSN(vse_v, MATCH_VSE_V, MASK_VSE_V)
+DECLARE_INSN(vlsb_v, MATCH_VLSB_V, MASK_VLSB_V)
+DECLARE_INSN(vlsh_v, MATCH_VLSH_V, MASK_VLSH_V)
+DECLARE_INSN(vlsw_v, MATCH_VLSW_V, MASK_VLSW_V)
+DECLARE_INSN(vlse_v, MATCH_VLSE_V, MASK_VLSE_V)
+DECLARE_INSN(vlsbu_v, MATCH_VLSBU_V, MASK_VLSBU_V)
+DECLARE_INSN(vlshu_v, MATCH_VLSHU_V, MASK_VLSHU_V)
+DECLARE_INSN(vlswu_v, MATCH_VLSWU_V, MASK_VLSWU_V)
+DECLARE_INSN(vssb_v, MATCH_VSSB_V, MASK_VSSB_V)
+DECLARE_INSN(vssh_v, MATCH_VSSH_V, MASK_VSSH_V)
+DECLARE_INSN(vssw_v, MATCH_VSSW_V, MASK_VSSW_V)
+DECLARE_INSN(vsse_v, MATCH_VSSE_V, MASK_VSSE_V)
+DECLARE_INSN(vlxb_v, MATCH_VLXB_V, MASK_VLXB_V)
+DECLARE_INSN(vlxh_v, MATCH_VLXH_V, MASK_VLXH_V)
+DECLARE_INSN(vlxw_v, MATCH_VLXW_V, MASK_VLXW_V)
+DECLARE_INSN(vlxe_v, MATCH_VLXE_V, MASK_VLXE_V)
+DECLARE_INSN(vlxbu_v, MATCH_VLXBU_V, MASK_VLXBU_V)
+DECLARE_INSN(vlxhu_v, MATCH_VLXHU_V, MASK_VLXHU_V)
+DECLARE_INSN(vlxwu_v, MATCH_VLXWU_V, MASK_VLXWU_V)
+DECLARE_INSN(vsxb_v, MATCH_VSXB_V, MASK_VSXB_V)
+DECLARE_INSN(vsxh_v, MATCH_VSXH_V, MASK_VSXH_V)
+DECLARE_INSN(vsxw_v, MATCH_VSXW_V, MASK_VSXW_V)
+DECLARE_INSN(vsxe_v, MATCH_VSXE_V, MASK_VSXE_V)
+DECLARE_INSN(vsuxb_v, MATCH_VSUXB_V, MASK_VSUXB_V)
+DECLARE_INSN(vsuxh_v, MATCH_VSUXH_V, MASK_VSUXH_V)
+DECLARE_INSN(vsuxw_v, MATCH_VSUXW_V, MASK_VSUXW_V)
+DECLARE_INSN(vsuxe_v, MATCH_VSUXE_V, MASK_VSUXE_V)
+DECLARE_INSN(vlbff_v, MATCH_VLBFF_V, MASK_VLBFF_V)
+DECLARE_INSN(vlhff_v, MATCH_VLHFF_V, MASK_VLHFF_V)
+DECLARE_INSN(vlwff_v, MATCH_VLWFF_V, MASK_VLWFF_V)
+DECLARE_INSN(vleff_v, MATCH_VLEFF_V, MASK_VLEFF_V)
+DECLARE_INSN(vlbuff_v, MATCH_VLBUFF_V, MASK_VLBUFF_V)
+DECLARE_INSN(vlhuff_v, MATCH_VLHUFF_V, MASK_VLHUFF_V)
+DECLARE_INSN(vlwuff_v, MATCH_VLWUFF_V, MASK_VLWUFF_V)
+DECLARE_INSN(vl1r_v, MATCH_VL1R_V, MASK_VL1R_V)
+DECLARE_INSN(vs1r_v, MATCH_VS1R_V, MASK_VS1R_V)
+DECLARE_INSN(vfadd_vf, MATCH_VFADD_VF, MASK_VFADD_VF)
+DECLARE_INSN(vfsub_vf, MATCH_VFSUB_VF, MASK_VFSUB_VF)
+DECLARE_INSN(vfmin_vf, MATCH_VFMIN_VF, MASK_VFMIN_VF)
+DECLARE_INSN(vfmax_vf, MATCH_VFMAX_VF, MASK_VFMAX_VF)
+DECLARE_INSN(vfsgnj_vf, MATCH_VFSGNJ_VF, MASK_VFSGNJ_VF)
+DECLARE_INSN(vfsgnjn_vf, MATCH_VFSGNJN_VF, MASK_VFSGNJN_VF)
+DECLARE_INSN(vfsgnjx_vf, MATCH_VFSGNJX_VF, MASK_VFSGNJX_VF)
+DECLARE_INSN(vfslide1up_vf, MATCH_VFSLIDE1UP_VF, MASK_VFSLIDE1UP_VF)
+DECLARE_INSN(vfslide1down_vf, MATCH_VFSLIDE1DOWN_VF, MASK_VFSLIDE1DOWN_VF)
+DECLARE_INSN(vfmv_s_f, MATCH_VFMV_S_F, MASK_VFMV_S_F)
+DECLARE_INSN(vfmerge_vfm, MATCH_VFMERGE_VFM, MASK_VFMERGE_VFM)
+DECLARE_INSN(vfmv_v_f, MATCH_VFMV_V_F, MASK_VFMV_V_F)
+DECLARE_INSN(vmfeq_vf, MATCH_VMFEQ_VF, MASK_VMFEQ_VF)
+DECLARE_INSN(vmfle_vf, MATCH_VMFLE_VF, MASK_VMFLE_VF)
+DECLARE_INSN(vmflt_vf, MATCH_VMFLT_VF, MASK_VMFLT_VF)
+DECLARE_INSN(vmfne_vf, MATCH_VMFNE_VF, MASK_VMFNE_VF)
+DECLARE_INSN(vmfgt_vf, MATCH_VMFGT_VF, MASK_VMFGT_VF)
+DECLARE_INSN(vmfge_vf, MATCH_VMFGE_VF, MASK_VMFGE_VF)
+DECLARE_INSN(vfdiv_vf, MATCH_VFDIV_VF, MASK_VFDIV_VF)
+DECLARE_INSN(vfrdiv_vf, MATCH_VFRDIV_VF, MASK_VFRDIV_VF)
+DECLARE_INSN(vfmul_vf, MATCH_VFMUL_VF, MASK_VFMUL_VF)
+DECLARE_INSN(vfrsub_vf, MATCH_VFRSUB_VF, MASK_VFRSUB_VF)
+DECLARE_INSN(vfmadd_vf, MATCH_VFMADD_VF, MASK_VFMADD_VF)
+DECLARE_INSN(vfnmadd_vf, MATCH_VFNMADD_VF, MASK_VFNMADD_VF)
+DECLARE_INSN(vfmsub_vf, MATCH_VFMSUB_VF, MASK_VFMSUB_VF)
+DECLARE_INSN(vfnmsub_vf, MATCH_VFNMSUB_VF, MASK_VFNMSUB_VF)
+DECLARE_INSN(vfmacc_vf, MATCH_VFMACC_VF, MASK_VFMACC_VF)
+DECLARE_INSN(vfnmacc_vf, MATCH_VFNMACC_VF, MASK_VFNMACC_VF)
+DECLARE_INSN(vfmsac_vf, MATCH_VFMSAC_VF, MASK_VFMSAC_VF)
+DECLARE_INSN(vfnmsac_vf, MATCH_VFNMSAC_VF, MASK_VFNMSAC_VF)
+DECLARE_INSN(vfwadd_vf, MATCH_VFWADD_VF, MASK_VFWADD_VF)
+DECLARE_INSN(vfwsub_vf, MATCH_VFWSUB_VF, MASK_VFWSUB_VF)
+DECLARE_INSN(vfwadd_wf, MATCH_VFWADD_WF, MASK_VFWADD_WF)
+DECLARE_INSN(vfwsub_wf, MATCH_VFWSUB_WF, MASK_VFWSUB_WF)
+DECLARE_INSN(vfwmul_vf, MATCH_VFWMUL_VF, MASK_VFWMUL_VF)
+DECLARE_INSN(vfwmacc_vf, MATCH_VFWMACC_VF, MASK_VFWMACC_VF)
+DECLARE_INSN(vfwnmacc_vf, MATCH_VFWNMACC_VF, MASK_VFWNMACC_VF)
+DECLARE_INSN(vfwmsac_vf, MATCH_VFWMSAC_VF, MASK_VFWMSAC_VF)
+DECLARE_INSN(vfwnmsac_vf, MATCH_VFWNMSAC_VF, MASK_VFWNMSAC_VF)
+DECLARE_INSN(vfadd_vv, MATCH_VFADD_VV, MASK_VFADD_VV)
+DECLARE_INSN(vfredsum_vs, MATCH_VFREDSUM_VS, MASK_VFREDSUM_VS)
+DECLARE_INSN(vfsub_vv, MATCH_VFSUB_VV, MASK_VFSUB_VV)
+DECLARE_INSN(vfredosum_vs, MATCH_VFREDOSUM_VS, MASK_VFREDOSUM_VS)
+DECLARE_INSN(vfmin_vv, MATCH_VFMIN_VV, MASK_VFMIN_VV)
+DECLARE_INSN(vfredmin_vs, MATCH_VFREDMIN_VS, MASK_VFREDMIN_VS)
+DECLARE_INSN(vfmax_vv, MATCH_VFMAX_VV, MASK_VFMAX_VV)
+DECLARE_INSN(vfredmax_vs, MATCH_VFREDMAX_VS, MASK_VFREDMAX_VS)
+DECLARE_INSN(vfsgnj_vv, MATCH_VFSGNJ_VV, MASK_VFSGNJ_VV)
+DECLARE_INSN(vfsgnjn_vv, MATCH_VFSGNJN_VV, MASK_VFSGNJN_VV)
+DECLARE_INSN(vfsgnjx_vv, MATCH_VFSGNJX_VV, MASK_VFSGNJX_VV)
+DECLARE_INSN(vfmv_f_s, MATCH_VFMV_F_S, MASK_VFMV_F_S)
+DECLARE_INSN(vmfeq_vv, MATCH_VMFEQ_VV, MASK_VMFEQ_VV)
+DECLARE_INSN(vmfle_vv, MATCH_VMFLE_VV, MASK_VMFLE_VV)
+DECLARE_INSN(vmflt_vv, MATCH_VMFLT_VV, MASK_VMFLT_VV)
+DECLARE_INSN(vmfne_vv, MATCH_VMFNE_VV, MASK_VMFNE_VV)
+DECLARE_INSN(vfdiv_vv, MATCH_VFDIV_VV, MASK_VFDIV_VV)
+DECLARE_INSN(vfmul_vv, MATCH_VFMUL_VV, MASK_VFMUL_VV)
+DECLARE_INSN(vfmadd_vv, MATCH_VFMADD_VV, MASK_VFMADD_VV)
+DECLARE_INSN(vfnmadd_vv, MATCH_VFNMADD_VV, MASK_VFNMADD_VV)
+DECLARE_INSN(vfmsub_vv, MATCH_VFMSUB_VV, MASK_VFMSUB_VV)
+DECLARE_INSN(vfnmsub_vv, MATCH_VFNMSUB_VV, MASK_VFNMSUB_VV)
+DECLARE_INSN(vfmacc_vv, MATCH_VFMACC_VV, MASK_VFMACC_VV)
+DECLARE_INSN(vfnmacc_vv, MATCH_VFNMACC_VV, MASK_VFNMACC_VV)
+DECLARE_INSN(vfmsac_vv, MATCH_VFMSAC_VV, MASK_VFMSAC_VV)
+DECLARE_INSN(vfnmsac_vv, MATCH_VFNMSAC_VV, MASK_VFNMSAC_VV)
+DECLARE_INSN(vfcvt_xu_f_v, MATCH_VFCVT_XU_F_V, MASK_VFCVT_XU_F_V)
+DECLARE_INSN(vfcvt_x_f_v, MATCH_VFCVT_X_F_V, MASK_VFCVT_X_F_V)
+DECLARE_INSN(vfcvt_f_xu_v, MATCH_VFCVT_F_XU_V, MASK_VFCVT_F_XU_V)
+DECLARE_INSN(vfcvt_f_x_v, MATCH_VFCVT_F_X_V, MASK_VFCVT_F_X_V)
+DECLARE_INSN(vfcvt_rtz_xu_f_v, MATCH_VFCVT_RTZ_XU_F_V, MASK_VFCVT_RTZ_XU_F_V)
+DECLARE_INSN(vfcvt_rtz_x_f_v, MATCH_VFCVT_RTZ_X_F_V, MASK_VFCVT_RTZ_X_F_V)
+DECLARE_INSN(vfwcvt_xu_f_v, MATCH_VFWCVT_XU_F_V, MASK_VFWCVT_XU_F_V)
+DECLARE_INSN(vfwcvt_x_f_v, MATCH_VFWCVT_X_F_V, MASK_VFWCVT_X_F_V)
+DECLARE_INSN(vfwcvt_f_xu_v, MATCH_VFWCVT_F_XU_V, MASK_VFWCVT_F_XU_V)
+DECLARE_INSN(vfwcvt_f_x_v, MATCH_VFWCVT_F_X_V, MASK_VFWCVT_F_X_V)
+DECLARE_INSN(vfwcvt_f_f_v, MATCH_VFWCVT_F_F_V, MASK_VFWCVT_F_F_V)
+DECLARE_INSN(vfwcvt_rtz_xu_f_v, MATCH_VFWCVT_RTZ_XU_F_V, MASK_VFWCVT_RTZ_XU_F_V)
+DECLARE_INSN(vfwcvt_rtz_x_f_v, MATCH_VFWCVT_RTZ_X_F_V, MASK_VFWCVT_RTZ_X_F_V)
+DECLARE_INSN(vfncvt_xu_f_w, MATCH_VFNCVT_XU_F_W, MASK_VFNCVT_XU_F_W)
+DECLARE_INSN(vfncvt_x_f_w, MATCH_VFNCVT_X_F_W, MASK_VFNCVT_X_F_W)
+DECLARE_INSN(vfncvt_f_xu_w, MATCH_VFNCVT_F_XU_W, MASK_VFNCVT_F_XU_W)
+DECLARE_INSN(vfncvt_f_x_w, MATCH_VFNCVT_F_X_W, MASK_VFNCVT_F_X_W)
+DECLARE_INSN(vfncvt_f_f_w, MATCH_VFNCVT_F_F_W, MASK_VFNCVT_F_F_W)
+DECLARE_INSN(vfncvt_rod_f_f_w, MATCH_VFNCVT_ROD_F_F_W, MASK_VFNCVT_ROD_F_F_W)
+DECLARE_INSN(vfncvt_rtz_xu_f_w, MATCH_VFNCVT_RTZ_XU_F_W, MASK_VFNCVT_RTZ_XU_F_W)
+DECLARE_INSN(vfncvt_rtz_x_f_w, MATCH_VFNCVT_RTZ_X_F_W, MASK_VFNCVT_RTZ_X_F_W)
+DECLARE_INSN(vfsqrt_v, MATCH_VFSQRT_V, MASK_VFSQRT_V)
+DECLARE_INSN(vfclass_v, MATCH_VFCLASS_V, MASK_VFCLASS_V)
+DECLARE_INSN(vfwadd_vv, MATCH_VFWADD_VV, MASK_VFWADD_VV)
+DECLARE_INSN(vfwredsum_vs, MATCH_VFWREDSUM_VS, MASK_VFWREDSUM_VS)
+DECLARE_INSN(vfwsub_vv, MATCH_VFWSUB_VV, MASK_VFWSUB_VV)
+DECLARE_INSN(vfwredosum_vs, MATCH_VFWREDOSUM_VS, MASK_VFWREDOSUM_VS)
+DECLARE_INSN(vfwadd_wv, MATCH_VFWADD_WV, MASK_VFWADD_WV)
+DECLARE_INSN(vfwsub_wv, MATCH_VFWSUB_WV, MASK_VFWSUB_WV)
+DECLARE_INSN(vfwmul_vv, MATCH_VFWMUL_VV, MASK_VFWMUL_VV)
+DECLARE_INSN(vfdot_vv, MATCH_VFDOT_VV, MASK_VFDOT_VV)
+DECLARE_INSN(vfwmacc_vv, MATCH_VFWMACC_VV, MASK_VFWMACC_VV)
+DECLARE_INSN(vfwnmacc_vv, MATCH_VFWNMACC_VV, MASK_VFWNMACC_VV)
+DECLARE_INSN(vfwmsac_vv, MATCH_VFWMSAC_VV, MASK_VFWMSAC_VV)
+DECLARE_INSN(vfwnmsac_vv, MATCH_VFWNMSAC_VV, MASK_VFWNMSAC_VV)
+DECLARE_INSN(vadd_vx, MATCH_VADD_VX, MASK_VADD_VX)
+DECLARE_INSN(vsub_vx, MATCH_VSUB_VX, MASK_VSUB_VX)
+DECLARE_INSN(vrsub_vx, MATCH_VRSUB_VX, MASK_VRSUB_VX)
+DECLARE_INSN(vminu_vx, MATCH_VMINU_VX, MASK_VMINU_VX)
+DECLARE_INSN(vmin_vx, MATCH_VMIN_VX, MASK_VMIN_VX)
+DECLARE_INSN(vmaxu_vx, MATCH_VMAXU_VX, MASK_VMAXU_VX)
+DECLARE_INSN(vmax_vx, MATCH_VMAX_VX, MASK_VMAX_VX)
+DECLARE_INSN(vand_vx, MATCH_VAND_VX, MASK_VAND_VX)
+DECLARE_INSN(vor_vx, MATCH_VOR_VX, MASK_VOR_VX)
+DECLARE_INSN(vxor_vx, MATCH_VXOR_VX, MASK_VXOR_VX)
+DECLARE_INSN(vrgather_vx, MATCH_VRGATHER_VX, MASK_VRGATHER_VX)
+DECLARE_INSN(vslideup_vx, MATCH_VSLIDEUP_VX, MASK_VSLIDEUP_VX)
+DECLARE_INSN(vslidedown_vx, MATCH_VSLIDEDOWN_VX, MASK_VSLIDEDOWN_VX)
+DECLARE_INSN(vadc_vxm, MATCH_VADC_VXM, MASK_VADC_VXM)
+DECLARE_INSN(vmadc_vxm, MATCH_VMADC_VXM, MASK_VMADC_VXM)
+DECLARE_INSN(vsbc_vxm, MATCH_VSBC_VXM, MASK_VSBC_VXM)
+DECLARE_INSN(vmsbc_vxm, MATCH_VMSBC_VXM, MASK_VMSBC_VXM)
+DECLARE_INSN(vmerge_vxm, MATCH_VMERGE_VXM, MASK_VMERGE_VXM)
+DECLARE_INSN(vmv_v_x, MATCH_VMV_V_X, MASK_VMV_V_X)
+DECLARE_INSN(vmseq_vx, MATCH_VMSEQ_VX, MASK_VMSEQ_VX)
+DECLARE_INSN(vmsne_vx, MATCH_VMSNE_VX, MASK_VMSNE_VX)
+DECLARE_INSN(vmsltu_vx, MATCH_VMSLTU_VX, MASK_VMSLTU_VX)
+DECLARE_INSN(vmslt_vx, MATCH_VMSLT_VX, MASK_VMSLT_VX)
+DECLARE_INSN(vmsleu_vx, MATCH_VMSLEU_VX, MASK_VMSLEU_VX)
+DECLARE_INSN(vmsle_vx, MATCH_VMSLE_VX, MASK_VMSLE_VX)
+DECLARE_INSN(vmsgtu_vx, MATCH_VMSGTU_VX, MASK_VMSGTU_VX)
+DECLARE_INSN(vmsgt_vx, MATCH_VMSGT_VX, MASK_VMSGT_VX)
+DECLARE_INSN(vsaddu_vx, MATCH_VSADDU_VX, MASK_VSADDU_VX)
+DECLARE_INSN(vsadd_vx, MATCH_VSADD_VX, MASK_VSADD_VX)
+DECLARE_INSN(vssubu_vx, MATCH_VSSUBU_VX, MASK_VSSUBU_VX)
+DECLARE_INSN(vssub_vx, MATCH_VSSUB_VX, MASK_VSSUB_VX)
+DECLARE_INSN(vsll_vx, MATCH_VSLL_VX, MASK_VSLL_VX)
+DECLARE_INSN(vsmul_vx, MATCH_VSMUL_VX, MASK_VSMUL_VX)
+DECLARE_INSN(vsrl_vx, MATCH_VSRL_VX, MASK_VSRL_VX)
+DECLARE_INSN(vsra_vx, MATCH_VSRA_VX, MASK_VSRA_VX)
+DECLARE_INSN(vssrl_vx, MATCH_VSSRL_VX, MASK_VSSRL_VX)
+DECLARE_INSN(vssra_vx, MATCH_VSSRA_VX, MASK_VSSRA_VX)
+DECLARE_INSN(vnsrl_wx, MATCH_VNSRL_WX, MASK_VNSRL_WX)
+DECLARE_INSN(vnsra_wx, MATCH_VNSRA_WX, MASK_VNSRA_WX)
+DECLARE_INSN(vnclipu_wx, MATCH_VNCLIPU_WX, MASK_VNCLIPU_WX)
+DECLARE_INSN(vnclip_wx, MATCH_VNCLIP_WX, MASK_VNCLIP_WX)
+DECLARE_INSN(vqmaccu_vx, MATCH_VQMACCU_VX, MASK_VQMACCU_VX)
+DECLARE_INSN(vqmacc_vx, MATCH_VQMACC_VX, MASK_VQMACC_VX)
+DECLARE_INSN(vqmaccus_vx, MATCH_VQMACCUS_VX, MASK_VQMACCUS_VX)
+DECLARE_INSN(vqmaccsu_vx, MATCH_VQMACCSU_VX, MASK_VQMACCSU_VX)
+DECLARE_INSN(vadd_vv, MATCH_VADD_VV, MASK_VADD_VV)
+DECLARE_INSN(vsub_vv, MATCH_VSUB_VV, MASK_VSUB_VV)
+DECLARE_INSN(vminu_vv, MATCH_VMINU_VV, MASK_VMINU_VV)
+DECLARE_INSN(vmin_vv, MATCH_VMIN_VV, MASK_VMIN_VV)
+DECLARE_INSN(vmaxu_vv, MATCH_VMAXU_VV, MASK_VMAXU_VV)
+DECLARE_INSN(vmax_vv, MATCH_VMAX_VV, MASK_VMAX_VV)
+DECLARE_INSN(vand_vv, MATCH_VAND_VV, MASK_VAND_VV)
+DECLARE_INSN(vor_vv, MATCH_VOR_VV, MASK_VOR_VV)
+DECLARE_INSN(vxor_vv, MATCH_VXOR_VV, MASK_VXOR_VV)
+DECLARE_INSN(vrgather_vv, MATCH_VRGATHER_VV, MASK_VRGATHER_VV)
+DECLARE_INSN(vadc_vvm, MATCH_VADC_VVM, MASK_VADC_VVM)
+DECLARE_INSN(vmadc_vvm, MATCH_VMADC_VVM, MASK_VMADC_VVM)
+DECLARE_INSN(vsbc_vvm, MATCH_VSBC_VVM, MASK_VSBC_VVM)
+DECLARE_INSN(vmsbc_vvm, MATCH_VMSBC_VVM, MASK_VMSBC_VVM)
+DECLARE_INSN(vmerge_vvm, MATCH_VMERGE_VVM, MASK_VMERGE_VVM)
+DECLARE_INSN(vmv_v_v, MATCH_VMV_V_V, MASK_VMV_V_V)
+DECLARE_INSN(vmseq_vv, MATCH_VMSEQ_VV, MASK_VMSEQ_VV)
+DECLARE_INSN(vmsne_vv, MATCH_VMSNE_VV, MASK_VMSNE_VV)
+DECLARE_INSN(vmsltu_vv, MATCH_VMSLTU_VV, MASK_VMSLTU_VV)
+DECLARE_INSN(vmslt_vv, MATCH_VMSLT_VV, MASK_VMSLT_VV)
+DECLARE_INSN(vmsleu_vv, MATCH_VMSLEU_VV, MASK_VMSLEU_VV)
+DECLARE_INSN(vmsle_vv, MATCH_VMSLE_VV, MASK_VMSLE_VV)
+DECLARE_INSN(vsaddu_vv, MATCH_VSADDU_VV, MASK_VSADDU_VV)
+DECLARE_INSN(vsadd_vv, MATCH_VSADD_VV, MASK_VSADD_VV)
+DECLARE_INSN(vssubu_vv, MATCH_VSSUBU_VV, MASK_VSSUBU_VV)
+DECLARE_INSN(vssub_vv, MATCH_VSSUB_VV, MASK_VSSUB_VV)
+DECLARE_INSN(vsll_vv, MATCH_VSLL_VV, MASK_VSLL_VV)
+DECLARE_INSN(vsmul_vv, MATCH_VSMUL_VV, MASK_VSMUL_VV)
+DECLARE_INSN(vsrl_vv, MATCH_VSRL_VV, MASK_VSRL_VV)
+DECLARE_INSN(vsra_vv, MATCH_VSRA_VV, MASK_VSRA_VV)
+DECLARE_INSN(vssrl_vv, MATCH_VSSRL_VV, MASK_VSSRL_VV)
+DECLARE_INSN(vssra_vv, MATCH_VSSRA_VV, MASK_VSSRA_VV)
+DECLARE_INSN(vnsrl_wv, MATCH_VNSRL_WV, MASK_VNSRL_WV)
+DECLARE_INSN(vnsra_wv, MATCH_VNSRA_WV, MASK_VNSRA_WV)
+DECLARE_INSN(vnclipu_wv, MATCH_VNCLIPU_WV, MASK_VNCLIPU_WV)
+DECLARE_INSN(vnclip_wv, MATCH_VNCLIP_WV, MASK_VNCLIP_WV)
+DECLARE_INSN(vwredsumu_vs, MATCH_VWREDSUMU_VS, MASK_VWREDSUMU_VS)
+DECLARE_INSN(vwredsum_vs, MATCH_VWREDSUM_VS, MASK_VWREDSUM_VS)
+DECLARE_INSN(vdotu_vv, MATCH_VDOTU_VV, MASK_VDOTU_VV)
+DECLARE_INSN(vdot_vv, MATCH_VDOT_VV, MASK_VDOT_VV)
+DECLARE_INSN(vqmaccu_vv, MATCH_VQMACCU_VV, MASK_VQMACCU_VV)
+DECLARE_INSN(vqmacc_vv, MATCH_VQMACC_VV, MASK_VQMACC_VV)
+DECLARE_INSN(vqmaccsu_vv, MATCH_VQMACCSU_VV, MASK_VQMACCSU_VV)
+DECLARE_INSN(vadd_vi, MATCH_VADD_VI, MASK_VADD_VI)
+DECLARE_INSN(vrsub_vi, MATCH_VRSUB_VI, MASK_VRSUB_VI)
+DECLARE_INSN(vand_vi, MATCH_VAND_VI, MASK_VAND_VI)
+DECLARE_INSN(vor_vi, MATCH_VOR_VI, MASK_VOR_VI)
+DECLARE_INSN(vxor_vi, MATCH_VXOR_VI, MASK_VXOR_VI)
+DECLARE_INSN(vrgather_vi, MATCH_VRGATHER_VI, MASK_VRGATHER_VI)
+DECLARE_INSN(vslideup_vi, MATCH_VSLIDEUP_VI, MASK_VSLIDEUP_VI)
+DECLARE_INSN(vslidedown_vi, MATCH_VSLIDEDOWN_VI, MASK_VSLIDEDOWN_VI)
+DECLARE_INSN(vadc_vim, MATCH_VADC_VIM, MASK_VADC_VIM)
+DECLARE_INSN(vmadc_vim, MATCH_VMADC_VIM, MASK_VMADC_VIM)
+DECLARE_INSN(vmerge_vim, MATCH_VMERGE_VIM, MASK_VMERGE_VIM)
+DECLARE_INSN(vmv_v_i, MATCH_VMV_V_I, MASK_VMV_V_I)
+DECLARE_INSN(vmseq_vi, MATCH_VMSEQ_VI, MASK_VMSEQ_VI)
+DECLARE_INSN(vmsne_vi, MATCH_VMSNE_VI, MASK_VMSNE_VI)
+DECLARE_INSN(vmsleu_vi, MATCH_VMSLEU_VI, MASK_VMSLEU_VI)
+DECLARE_INSN(vmsle_vi, MATCH_VMSLE_VI, MASK_VMSLE_VI)
+DECLARE_INSN(vmsgtu_vi, MATCH_VMSGTU_VI, MASK_VMSGTU_VI)
+DECLARE_INSN(vmsgt_vi, MATCH_VMSGT_VI, MASK_VMSGT_VI)
+DECLARE_INSN(vsaddu_vi, MATCH_VSADDU_VI, MASK_VSADDU_VI)
+DECLARE_INSN(vsadd_vi, MATCH_VSADD_VI, MASK_VSADD_VI)
+DECLARE_INSN(vsll_vi, MATCH_VSLL_VI, MASK_VSLL_VI)
+DECLARE_INSN(vmv1r_v, MATCH_VMV1R_V, MASK_VMV1R_V)
+DECLARE_INSN(vmv2r_v, MATCH_VMV2R_V, MASK_VMV2R_V)
+DECLARE_INSN(vmv4r_v, MATCH_VMV4R_V, MASK_VMV4R_V)
+DECLARE_INSN(vmv8r_v, MATCH_VMV8R_V, MASK_VMV8R_V)
+DECLARE_INSN(vsrl_vi, MATCH_VSRL_VI, MASK_VSRL_VI)
+DECLARE_INSN(vsra_vi, MATCH_VSRA_VI, MASK_VSRA_VI)
+DECLARE_INSN(vssrl_vi, MATCH_VSSRL_VI, MASK_VSSRL_VI)
+DECLARE_INSN(vssra_vi, MATCH_VSSRA_VI, MASK_VSSRA_VI)
+DECLARE_INSN(vnsrl_wi, MATCH_VNSRL_WI, MASK_VNSRL_WI)
+DECLARE_INSN(vnsra_wi, MATCH_VNSRA_WI, MASK_VNSRA_WI)
+DECLARE_INSN(vnclipu_wi, MATCH_VNCLIPU_WI, MASK_VNCLIPU_WI)
+DECLARE_INSN(vnclip_wi, MATCH_VNCLIP_WI, MASK_VNCLIP_WI)
+DECLARE_INSN(vredsum_vs, MATCH_VREDSUM_VS, MASK_VREDSUM_VS)
+DECLARE_INSN(vredand_vs, MATCH_VREDAND_VS, MASK_VREDAND_VS)
+DECLARE_INSN(vredor_vs, MATCH_VREDOR_VS, MASK_VREDOR_VS)
+DECLARE_INSN(vredxor_vs, MATCH_VREDXOR_VS, MASK_VREDXOR_VS)
+DECLARE_INSN(vredminu_vs, MATCH_VREDMINU_VS, MASK_VREDMINU_VS)
+DECLARE_INSN(vredmin_vs, MATCH_VREDMIN_VS, MASK_VREDMIN_VS)
+DECLARE_INSN(vredmaxu_vs, MATCH_VREDMAXU_VS, MASK_VREDMAXU_VS)
+DECLARE_INSN(vredmax_vs, MATCH_VREDMAX_VS, MASK_VREDMAX_VS)
+DECLARE_INSN(vaaddu_vv, MATCH_VAADDU_VV, MASK_VAADDU_VV)
+DECLARE_INSN(vaadd_vv, MATCH_VAADD_VV, MASK_VAADD_VV)
+DECLARE_INSN(vasubu_vv, MATCH_VASUBU_VV, MASK_VASUBU_VV)
+DECLARE_INSN(vasub_vv, MATCH_VASUB_VV, MASK_VASUB_VV)
+DECLARE_INSN(vmv_x_s, MATCH_VMV_X_S, MASK_VMV_X_S)
+DECLARE_INSN(vcompress_vm, MATCH_VCOMPRESS_VM, MASK_VCOMPRESS_VM)
+DECLARE_INSN(vmandnot_mm, MATCH_VMANDNOT_MM, MASK_VMANDNOT_MM)
+DECLARE_INSN(vmand_mm, MATCH_VMAND_MM, MASK_VMAND_MM)
+DECLARE_INSN(vmor_mm, MATCH_VMOR_MM, MASK_VMOR_MM)
+DECLARE_INSN(vmxor_mm, MATCH_VMXOR_MM, MASK_VMXOR_MM)
+DECLARE_INSN(vmornot_mm, MATCH_VMORNOT_MM, MASK_VMORNOT_MM)
+DECLARE_INSN(vmnand_mm, MATCH_VMNAND_MM, MASK_VMNAND_MM)
+DECLARE_INSN(vmnor_mm, MATCH_VMNOR_MM, MASK_VMNOR_MM)
+DECLARE_INSN(vmxnor_mm, MATCH_VMXNOR_MM, MASK_VMXNOR_MM)
+DECLARE_INSN(vmsbf_m, MATCH_VMSBF_M, MASK_VMSBF_M)
+DECLARE_INSN(vmsof_m, MATCH_VMSOF_M, MASK_VMSOF_M)
+DECLARE_INSN(vmsif_m, MATCH_VMSIF_M, MASK_VMSIF_M)
+DECLARE_INSN(viota_m, MATCH_VIOTA_M, MASK_VIOTA_M)
+DECLARE_INSN(vid_v, MATCH_VID_V, MASK_VID_V)
+DECLARE_INSN(vpopc_m, MATCH_VPOPC_M, MASK_VPOPC_M)
+DECLARE_INSN(vfirst_m, MATCH_VFIRST_M, MASK_VFIRST_M)
+DECLARE_INSN(vdivu_vv, MATCH_VDIVU_VV, MASK_VDIVU_VV)
+DECLARE_INSN(vdiv_vv, MATCH_VDIV_VV, MASK_VDIV_VV)
+DECLARE_INSN(vremu_vv, MATCH_VREMU_VV, MASK_VREMU_VV)
+DECLARE_INSN(vrem_vv, MATCH_VREM_VV, MASK_VREM_VV)
+DECLARE_INSN(vmulhu_vv, MATCH_VMULHU_VV, MASK_VMULHU_VV)
+DECLARE_INSN(vmul_vv, MATCH_VMUL_VV, MASK_VMUL_VV)
+DECLARE_INSN(vmulhsu_vv, MATCH_VMULHSU_VV, MASK_VMULHSU_VV)
+DECLARE_INSN(vmulh_vv, MATCH_VMULH_VV, MASK_VMULH_VV)
+DECLARE_INSN(vmadd_vv, MATCH_VMADD_VV, MASK_VMADD_VV)
+DECLARE_INSN(vnmsub_vv, MATCH_VNMSUB_VV, MASK_VNMSUB_VV)
+DECLARE_INSN(vmacc_vv, MATCH_VMACC_VV, MASK_VMACC_VV)
+DECLARE_INSN(vnmsac_vv, MATCH_VNMSAC_VV, MASK_VNMSAC_VV)
+DECLARE_INSN(vwaddu_vv, MATCH_VWADDU_VV, MASK_VWADDU_VV)
+DECLARE_INSN(vwadd_vv, MATCH_VWADD_VV, MASK_VWADD_VV)
+DECLARE_INSN(vwsubu_vv, MATCH_VWSUBU_VV, MASK_VWSUBU_VV)
+DECLARE_INSN(vwsub_vv, MATCH_VWSUB_VV, MASK_VWSUB_VV)
+DECLARE_INSN(vwaddu_wv, MATCH_VWADDU_WV, MASK_VWADDU_WV)
+DECLARE_INSN(vwadd_wv, MATCH_VWADD_WV, MASK_VWADD_WV)
+DECLARE_INSN(vwsubu_wv, MATCH_VWSUBU_WV, MASK_VWSUBU_WV)
+DECLARE_INSN(vwsub_wv, MATCH_VWSUB_WV, MASK_VWSUB_WV)
+DECLARE_INSN(vwmulu_vv, MATCH_VWMULU_VV, MASK_VWMULU_VV)
+DECLARE_INSN(vwmulsu_vv, MATCH_VWMULSU_VV, MASK_VWMULSU_VV)
+DECLARE_INSN(vwmul_vv, MATCH_VWMUL_VV, MASK_VWMUL_VV)
+DECLARE_INSN(vwmaccu_vv, MATCH_VWMACCU_VV, MASK_VWMACCU_VV)
+DECLARE_INSN(vwmacc_vv, MATCH_VWMACC_VV, MASK_VWMACC_VV)
+DECLARE_INSN(vwmaccsu_vv, MATCH_VWMACCSU_VV, MASK_VWMACCSU_VV)
+DECLARE_INSN(vaaddu_vx, MATCH_VAADDU_VX, MASK_VAADDU_VX)
+DECLARE_INSN(vaadd_vx, MATCH_VAADD_VX, MASK_VAADD_VX)
+DECLARE_INSN(vasubu_vx, MATCH_VASUBU_VX, MASK_VASUBU_VX)
+DECLARE_INSN(vasub_vx, MATCH_VASUB_VX, MASK_VASUB_VX)
+DECLARE_INSN(vmv_s_x, MATCH_VMV_S_X, MASK_VMV_S_X)
+DECLARE_INSN(vslide1up_vx, MATCH_VSLIDE1UP_VX, MASK_VSLIDE1UP_VX)
+DECLARE_INSN(vslide1down_vx, MATCH_VSLIDE1DOWN_VX, MASK_VSLIDE1DOWN_VX)
+DECLARE_INSN(vdivu_vx, MATCH_VDIVU_VX, MASK_VDIVU_VX)
+DECLARE_INSN(vdiv_vx, MATCH_VDIV_VX, MASK_VDIV_VX)
+DECLARE_INSN(vremu_vx, MATCH_VREMU_VX, MASK_VREMU_VX)
+DECLARE_INSN(vrem_vx, MATCH_VREM_VX, MASK_VREM_VX)
+DECLARE_INSN(vmulhu_vx, MATCH_VMULHU_VX, MASK_VMULHU_VX)
+DECLARE_INSN(vmul_vx, MATCH_VMUL_VX, MASK_VMUL_VX)
+DECLARE_INSN(vmulhsu_vx, MATCH_VMULHSU_VX, MASK_VMULHSU_VX)
+DECLARE_INSN(vmulh_vx, MATCH_VMULH_VX, MASK_VMULH_VX)
+DECLARE_INSN(vmadd_vx, MATCH_VMADD_VX, MASK_VMADD_VX)
+DECLARE_INSN(vnmsub_vx, MATCH_VNMSUB_VX, MASK_VNMSUB_VX)
+DECLARE_INSN(vmacc_vx, MATCH_VMACC_VX, MASK_VMACC_VX)
+DECLARE_INSN(vnmsac_vx, MATCH_VNMSAC_VX, MASK_VNMSAC_VX)
+DECLARE_INSN(vwaddu_vx, MATCH_VWADDU_VX, MASK_VWADDU_VX)
+DECLARE_INSN(vwadd_vx, MATCH_VWADD_VX, MASK_VWADD_VX)
+DECLARE_INSN(vwsubu_vx, MATCH_VWSUBU_VX, MASK_VWSUBU_VX)
+DECLARE_INSN(vwsub_vx, MATCH_VWSUB_VX, MASK_VWSUB_VX)
+DECLARE_INSN(vwaddu_wx, MATCH_VWADDU_WX, MASK_VWADDU_WX)
+DECLARE_INSN(vwadd_wx, MATCH_VWADD_WX, MASK_VWADD_WX)
+DECLARE_INSN(vwsubu_wx, MATCH_VWSUBU_WX, MASK_VWSUBU_WX)
+DECLARE_INSN(vwsub_wx, MATCH_VWSUB_WX, MASK_VWSUB_WX)
+DECLARE_INSN(vwmulu_vx, MATCH_VWMULU_VX, MASK_VWMULU_VX)
+DECLARE_INSN(vwmulsu_vx, MATCH_VWMULSU_VX, MASK_VWMULSU_VX)
+DECLARE_INSN(vwmul_vx, MATCH_VWMUL_VX, MASK_VWMUL_VX)
+DECLARE_INSN(vwmaccu_vx, MATCH_VWMACCU_VX, MASK_VWMACCU_VX)
+DECLARE_INSN(vwmacc_vx, MATCH_VWMACC_VX, MASK_VWMACC_VX)
+DECLARE_INSN(vwmaccus_vx, MATCH_VWMACCUS_VX, MASK_VWMACCUS_VX)
+DECLARE_INSN(vwmaccsu_vx, MATCH_VWMACCSU_VX, MASK_VWMACCSU_VX)
+DECLARE_INSN(vamoswapw_v, MATCH_VAMOSWAPW_V, MASK_VAMOSWAPW_V)
+DECLARE_INSN(vamoaddw_v, MATCH_VAMOADDW_V, MASK_VAMOADDW_V)
+DECLARE_INSN(vamoxorw_v, MATCH_VAMOXORW_V, MASK_VAMOXORW_V)
+DECLARE_INSN(vamoandw_v, MATCH_VAMOANDW_V, MASK_VAMOANDW_V)
+DECLARE_INSN(vamoorw_v, MATCH_VAMOORW_V, MASK_VAMOORW_V)
+DECLARE_INSN(vamominw_v, MATCH_VAMOMINW_V, MASK_VAMOMINW_V)
+DECLARE_INSN(vamomaxw_v, MATCH_VAMOMAXW_V, MASK_VAMOMAXW_V)
+DECLARE_INSN(vamominuw_v, MATCH_VAMOMINUW_V, MASK_VAMOMINUW_V)
+DECLARE_INSN(vamomaxuw_v, MATCH_VAMOMAXUW_V, MASK_VAMOMAXUW_V)
+DECLARE_INSN(vamoswape_v, MATCH_VAMOSWAPE_V, MASK_VAMOSWAPE_V)
+DECLARE_INSN(vamoadde_v, MATCH_VAMOADDE_V, MASK_VAMOADDE_V)
+DECLARE_INSN(vamoxore_v, MATCH_VAMOXORE_V, MASK_VAMOXORE_V)
+DECLARE_INSN(vamoande_v, MATCH_VAMOANDE_V, MASK_VAMOANDE_V)
+DECLARE_INSN(vamoore_v, MATCH_VAMOORE_V, MASK_VAMOORE_V)
+DECLARE_INSN(vamomine_v, MATCH_VAMOMINE_V, MASK_VAMOMINE_V)
+DECLARE_INSN(vamomaxe_v, MATCH_VAMOMAXE_V, MASK_VAMOMAXE_V)
+DECLARE_INSN(vamominue_v, MATCH_VAMOMINUE_V, MASK_VAMOMINUE_V)
+DECLARE_INSN(vamomaxue_v, MATCH_VAMOMAXUE_V, MASK_VAMOMAXUE_V)
+DECLARE_INSN(vmvnfr_v, MATCH_VMVNFR_V, MASK_VMVNFR_V)
+#endif
+#ifdef DECLARE_CSR
+DECLARE_CSR(fflags, CSR_FFLAGS)
+DECLARE_CSR(frm, CSR_FRM)
+DECLARE_CSR(fcsr, CSR_FCSR)
+DECLARE_CSR(ustatus, CSR_USTATUS)
+DECLARE_CSR(uie, CSR_UIE)
+DECLARE_CSR(utvec, CSR_UTVEC)
+DECLARE_CSR(vstart, CSR_VSTART)
+DECLARE_CSR(vxsat, CSR_VXSAT)
+DECLARE_CSR(vxrm, CSR_VXRM)
+DECLARE_CSR(vcsr, CSR_VCSR)
+DECLARE_CSR(uscratch, CSR_USCRATCH)
+DECLARE_CSR(uepc, CSR_UEPC)
+DECLARE_CSR(ucause, CSR_UCAUSE)
+DECLARE_CSR(utval, CSR_UTVAL)
+DECLARE_CSR(uip, CSR_UIP)
+DECLARE_CSR(cycle, CSR_CYCLE)
+DECLARE_CSR(time, CSR_TIME)
+DECLARE_CSR(instret, CSR_INSTRET)
+DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3)
+DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4)
+DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5)
+DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6)
+DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7)
+DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8)
+DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9)
+DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10)
+DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11)
+DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12)
+DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13)
+DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14)
+DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15)
+DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16)
+DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17)
+DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18)
+DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19)
+DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20)
+DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21)
+DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22)
+DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23)
+DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24)
+DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25)
+DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26)
+DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27)
+DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28)
+DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29)
+DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30)
+DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31)
+DECLARE_CSR(vl, CSR_VL)
+DECLARE_CSR(vtype, CSR_VTYPE)
+DECLARE_CSR(vlenb, CSR_VLENB)
+DECLARE_CSR(sstatus, CSR_SSTATUS)
+DECLARE_CSR(sedeleg, CSR_SEDELEG)
+DECLARE_CSR(sideleg, CSR_SIDELEG)
+DECLARE_CSR(sie, CSR_SIE)
+DECLARE_CSR(stvec, CSR_STVEC)
+DECLARE_CSR(scounteren, CSR_SCOUNTEREN)
+DECLARE_CSR(sscratch, CSR_SSCRATCH)
+DECLARE_CSR(sepc, CSR_SEPC)
+DECLARE_CSR(scause, CSR_SCAUSE)
+DECLARE_CSR(stval, CSR_STVAL)
+DECLARE_CSR(sip, CSR_SIP)
+DECLARE_CSR(satp, CSR_SATP)
+DECLARE_CSR(vsstatus, CSR_VSSTATUS)
+DECLARE_CSR(vsie, CSR_VSIE)
+DECLARE_CSR(vstvec, CSR_VSTVEC)
+DECLARE_CSR(vsscratch, CSR_VSSCRATCH)
+DECLARE_CSR(vsepc, CSR_VSEPC)
+DECLARE_CSR(vscause, CSR_VSCAUSE)
+DECLARE_CSR(vstval, CSR_VSTVAL)
+DECLARE_CSR(vsip, CSR_VSIP)
+DECLARE_CSR(vsatp, CSR_VSATP)
+DECLARE_CSR(hstatus, CSR_HSTATUS)
+DECLARE_CSR(hedeleg, CSR_HEDELEG)
+DECLARE_CSR(hideleg, CSR_HIDELEG)
+DECLARE_CSR(hie, CSR_HIE)
+DECLARE_CSR(htimedelta, CSR_HTIMEDELTA)
+DECLARE_CSR(hcounteren, CSR_HCOUNTEREN)
+DECLARE_CSR(hgeie, CSR_HGEIE)
+DECLARE_CSR(htval, CSR_HTVAL)
+DECLARE_CSR(hip, CSR_HIP)
+DECLARE_CSR(hvip, CSR_HVIP)
+DECLARE_CSR(htinst, CSR_HTINST)
+DECLARE_CSR(hgatp, CSR_HGATP)
+DECLARE_CSR(hgeip, CSR_HGEIP)
+DECLARE_CSR(utvt, CSR_UTVT)
+DECLARE_CSR(unxti, CSR_UNXTI)
+DECLARE_CSR(uintstatus, CSR_UINTSTATUS)
+DECLARE_CSR(uscratchcsw, CSR_USCRATCHCSW)
+DECLARE_CSR(uscratchcswl, CSR_USCRATCHCSWL)
+DECLARE_CSR(stvt, CSR_STVT)
+DECLARE_CSR(snxti, CSR_SNXTI)
+DECLARE_CSR(sintstatus, CSR_SINTSTATUS)
+DECLARE_CSR(sscratchcsw, CSR_SSCRATCHCSW)
+DECLARE_CSR(sscratchcswl, CSR_SSCRATCHCSWL)
+DECLARE_CSR(mtvt, CSR_MTVT)
+DECLARE_CSR(mnxti, CSR_MNXTI)
+DECLARE_CSR(mintstatus, CSR_MINTSTATUS)
+DECLARE_CSR(mscratchcsw, CSR_MSCRATCHCSW)
+DECLARE_CSR(mscratchcswl, CSR_MSCRATCHCSWL)
+DECLARE_CSR(mstatus, CSR_MSTATUS)
+DECLARE_CSR(misa, CSR_MISA)
+DECLARE_CSR(medeleg, CSR_MEDELEG)
+DECLARE_CSR(mideleg, CSR_MIDELEG)
+DECLARE_CSR(mie, CSR_MIE)
+DECLARE_CSR(mtvec, CSR_MTVEC)
+DECLARE_CSR(mcounteren, CSR_MCOUNTEREN)
+DECLARE_CSR(mcountinhibit, CSR_MCOUNTINHIBIT)
+DECLARE_CSR(mscratch, CSR_MSCRATCH)
+DECLARE_CSR(mepc, CSR_MEPC)
+DECLARE_CSR(mcause, CSR_MCAUSE)
+DECLARE_CSR(mtval, CSR_MTVAL)
+DECLARE_CSR(mip, CSR_MIP)
+DECLARE_CSR(mtinst, CSR_MTINST)
+DECLARE_CSR(mtval2, CSR_MTVAL2)
+DECLARE_CSR(pmpcfg0, CSR_PMPCFG0)
+DECLARE_CSR(pmpcfg1, CSR_PMPCFG1)
+DECLARE_CSR(pmpcfg2, CSR_PMPCFG2)
+DECLARE_CSR(pmpcfg3, CSR_PMPCFG3)
+DECLARE_CSR(pmpaddr0, CSR_PMPADDR0)
+DECLARE_CSR(pmpaddr1, CSR_PMPADDR1)
+DECLARE_CSR(pmpaddr2, CSR_PMPADDR2)
+DECLARE_CSR(pmpaddr3, CSR_PMPADDR3)
+DECLARE_CSR(pmpaddr4, CSR_PMPADDR4)
+DECLARE_CSR(pmpaddr5, CSR_PMPADDR5)
+DECLARE_CSR(pmpaddr6, CSR_PMPADDR6)
+DECLARE_CSR(pmpaddr7, CSR_PMPADDR7)
+DECLARE_CSR(pmpaddr8, CSR_PMPADDR8)
+DECLARE_CSR(pmpaddr9, CSR_PMPADDR9)
+DECLARE_CSR(pmpaddr10, CSR_PMPADDR10)
+DECLARE_CSR(pmpaddr11, CSR_PMPADDR11)
+DECLARE_CSR(pmpaddr12, CSR_PMPADDR12)
+DECLARE_CSR(pmpaddr13, CSR_PMPADDR13)
+DECLARE_CSR(pmpaddr14, CSR_PMPADDR14)
+DECLARE_CSR(pmpaddr15, CSR_PMPADDR15)
+DECLARE_CSR(tselect, CSR_TSELECT)
+DECLARE_CSR(tdata1, CSR_TDATA1)
+DECLARE_CSR(tdata2, CSR_TDATA2)
+DECLARE_CSR(tdata3, CSR_TDATA3)
+DECLARE_CSR(dcsr, CSR_DCSR)
+DECLARE_CSR(dpc, CSR_DPC)
+DECLARE_CSR(dscratch0, CSR_DSCRATCH0)
+DECLARE_CSR(dscratch1, CSR_DSCRATCH1)
+DECLARE_CSR(mcycle, CSR_MCYCLE)
+DECLARE_CSR(minstret, CSR_MINSTRET)
+DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3)
+DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4)
+DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5)
+DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6)
+DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7)
+DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8)
+DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9)
+DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10)
+DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11)
+DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12)
+DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13)
+DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14)
+DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15)
+DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16)
+DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17)
+DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18)
+DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19)
+DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20)
+DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21)
+DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22)
+DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23)
+DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24)
+DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25)
+DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26)
+DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27)
+DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28)
+DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29)
+DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30)
+DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31)
+DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3)
+DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4)
+DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5)
+DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6)
+DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7)
+DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8)
+DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9)
+DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10)
+DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11)
+DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12)
+DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13)
+DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14)
+DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15)
+DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16)
+DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17)
+DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18)
+DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19)
+DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20)
+DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21)
+DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22)
+DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23)
+DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24)
+DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25)
+DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26)
+DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27)
+DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28)
+DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29)
+DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30)
+DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31)
+DECLARE_CSR(mvendorid, CSR_MVENDORID)
+DECLARE_CSR(marchid, CSR_MARCHID)
+DECLARE_CSR(mimpid, CSR_MIMPID)
+DECLARE_CSR(mhartid, CSR_MHARTID)
+DECLARE_CSR(htimedeltah, CSR_HTIMEDELTAH)
+DECLARE_CSR(cycleh, CSR_CYCLEH)
+DECLARE_CSR(timeh, CSR_TIMEH)
+DECLARE_CSR(instreth, CSR_INSTRETH)
+DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H)
+DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H)
+DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H)
+DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H)
+DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H)
+DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H)
+DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H)
+DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H)
+DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H)
+DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H)
+DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H)
+DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H)
+DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H)
+DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H)
+DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H)
+DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H)
+DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H)
+DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H)
+DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H)
+DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H)
+DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H)
+DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H)
+DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H)
+DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H)
+DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H)
+DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H)
+DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H)
+DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H)
+DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H)
+DECLARE_CSR(mstatush, CSR_MSTATUSH)
+DECLARE_CSR(mcycleh, CSR_MCYCLEH)
+DECLARE_CSR(minstreth, CSR_MINSTRETH)
+DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H)
+DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H)
+DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H)
+DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H)
+DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H)
+DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H)
+DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H)
+DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H)
+DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H)
+DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H)
+DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H)
+DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H)
+DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H)
+DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H)
+DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H)
+DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H)
+DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H)
+DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H)
+DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H)
+DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H)
+DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H)
+DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H)
+DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H)
+DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H)
+DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H)
+DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H)
+DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H)
+DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H)
+DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H)
+#endif
+#ifdef DECLARE_CAUSE
+DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)
+DECLARE_CAUSE("fetch access", CAUSE_FETCH_ACCESS)
+DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION)
+DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT)
+DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD)
+DECLARE_CAUSE("load access", CAUSE_LOAD_ACCESS)
+DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE)
+DECLARE_CAUSE("store access", CAUSE_STORE_ACCESS)
+DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL)
+DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL)
+DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL)
+DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL)
+DECLARE_CAUSE("fetch page fault", CAUSE_FETCH_PAGE_FAULT)
+DECLARE_CAUSE("load page fault", CAUSE_LOAD_PAGE_FAULT)
+DECLARE_CAUSE("store page fault", CAUSE_STORE_PAGE_FAULT)
+#endif
diff --git a/apps/riscv-tests/env/p/link.ld b/apps/riscv-tests/env/p/link.ld
new file mode 100644
index 0000000..b3e315e
--- /dev/null
+++ b/apps/riscv-tests/env/p/link.ld
@@ -0,0 +1,17 @@
+OUTPUT_ARCH( "riscv" )
+ENTRY(_start)
+
+SECTIONS
+{
+  . = 0x80000000;
+  .text.init : { *(.text.init) }
+  . = ALIGN(0x1000);
+  .tohost : { *(.tohost) }
+  . = ALIGN(0x1000);
+  .text : { *(.text) }
+  . = ALIGN(0x1000);
+  .data : { *(.data) }
+  .bss : { *(.bss) }
+  _end = .;
+}
+
diff --git a/apps/riscv-tests/env/p/riscv_test.h b/apps/riscv-tests/env/p/riscv_test.h
new file mode 100644
index 0000000..2b6ff83
--- /dev/null
+++ b/apps/riscv-tests/env/p/riscv_test.h
@@ -0,0 +1,269 @@
+// See LICENSE for license details.
+
+#ifndef _ENV_PHYSICAL_SINGLE_CORE_H
+#define _ENV_PHYSICAL_SINGLE_CORE_H
+
+#include "../encoding.h"
+
+//-----------------------------------------------------------------------
+// Begin Macro
+//-----------------------------------------------------------------------
+
+#define RVTEST_RV64U                                                    \
+  .macro init;                                                          \
+  .endm
+
+#define RVTEST_RV64UF                                                   \
+  .macro init;                                                          \
+  RVTEST_FP_ENABLE;                                                     \
+  .endm
+
+#define RVTEST_RV64UV                                                   \
+  .macro init;                                                          \
+  RVTEST_VECTOR_ENABLE;                                                 \
+  .endm
+
+#define RVTEST_RV32U                                                    \
+  .macro init;                                                          \
+  .endm
+
+#define RVTEST_RV32UF                                                   \
+  .macro init;                                                          \
+  RVTEST_FP_ENABLE;                                                     \
+  .endm
+
+#define RVTEST_RV32UV                                                   \
+  .macro init;                                                          \
+  RVTEST_VECTOR_ENABLE;                                                 \
+  .endm
+
+#define RVTEST_RV64M                                                    \
+  .macro init;                                                          \
+  RVTEST_ENABLE_MACHINE;                                                \
+  .endm
+
+#define RVTEST_RV64S                                                    \
+  .macro init;                                                          \
+  RVTEST_ENABLE_SUPERVISOR;                                             \
+  .endm
+
+#define RVTEST_RV32M                                                    \
+  .macro init;                                                          \
+  RVTEST_ENABLE_MACHINE;                                                \
+  .endm
+
+#define RVTEST_RV32S                                                    \
+  .macro init;                                                          \
+  RVTEST_ENABLE_SUPERVISOR;                                             \
+  .endm
+
+#if __riscv_xlen == 64
+# define CHECK_XLEN li a0, 1; slli a0, a0, 31; bgez a0, 1f; RVTEST_PASS; 1:
+#else
+# define CHECK_XLEN li a0, 1; slli a0, a0, 31; bltz a0, 1f; RVTEST_PASS; 1:
+#endif
+
+#define INIT_XREG                                                       \
+  li x1, 0;                                                             \
+  li x2, 0;                                                             \
+  li x3, 0;                                                             \
+  li x4, 0;                                                             \
+  li x5, 0;                                                             \
+  li x6, 0;                                                             \
+  li x7, 0;                                                             \
+  li x8, 0;                                                             \
+  li x9, 0;                                                             \
+  li x10, 0;                                                            \
+  li x11, 0;                                                            \
+  li x12, 0;                                                            \
+  li x13, 0;                                                            \
+  li x14, 0;                                                            \
+  li x15, 0;                                                            \
+  li x16, 0;                                                            \
+  li x17, 0;                                                            \
+  li x18, 0;                                                            \
+  li x19, 0;                                                            \
+  li x20, 0;                                                            \
+  li x21, 0;                                                            \
+  li x22, 0;                                                            \
+  li x23, 0;                                                            \
+  li x24, 0;                                                            \
+  li x25, 0;                                                            \
+  li x26, 0;                                                            \
+  li x27, 0;                                                            \
+  li x28, 0;                                                            \
+  li x29, 0;                                                            \
+  li x30, 0;                                                            \
+  li x31, 0;
+
+#define INIT_PMP                                                        \
+  la t0, 1f;                                                            \
+  csrw mtvec, t0;                                                       \
+  /* Set up a PMP to permit all accesses */                             \
+  li t0, (1 << (31 + (__riscv_xlen / 64) * (53 - 31))) - 1;             \
+  csrw pmpaddr0, t0;                                                    \
+  li t0, PMP_NAPOT | PMP_R | PMP_W | PMP_X;                             \
+  csrw pmpcfg0, t0;                                                     \
+  .align 2;                                                             \
+1:
+
+#define INIT_SATP                                                      \
+  la t0, 1f;                                                            \
+  csrw mtvec, t0;                                                       \
+  csrwi sptbr, 0;                                                       \
+  .align 2;                                                             \
+1:
+
+#define DELEGATE_NO_TRAPS                                               \
+  csrwi mie, 0;                                                         \
+  la t0, 1f;                                                            \
+  csrw mtvec, t0;                                                       \
+  csrwi medeleg, 0;                                                     \
+  csrwi mideleg, 0;                                                     \
+  .align 2;                                                             \
+1:
+
+#define RVTEST_ENABLE_SUPERVISOR                                        \
+  li a0, MSTATUS_MPP & (MSTATUS_MPP >> 1);                              \
+  csrs mstatus, a0;                                                     \
+  li a0, SIP_SSIP | SIP_STIP;                                           \
+  csrs mideleg, a0;                                                     \
+
+#define RVTEST_ENABLE_MACHINE                                           \
+  li a0, MSTATUS_MPP;                                                   \
+  csrs mstatus, a0;                                                     \
+
+#define RVTEST_FP_ENABLE                                                \
+  li a0, MSTATUS_FS & (MSTATUS_FS >> 1);                                \
+  csrs mstatus, a0;                                                     \
+  csrwi fcsr, 0
+
+#define RVTEST_VECTOR_ENABLE                                            \
+  li a0, (MSTATUS_VS & (MSTATUS_VS >> 1)) |                             \
+         (MSTATUS_FS & (MSTATUS_FS >> 1));                              \
+  csrs mstatus, a0;                                                     \
+  csrwi fcsr, 0;                                                        \
+  csrwi vcsr, 0;
+
+#define RISCV_MULTICORE_DISABLE                                         \
+  csrr a0, mhartid;                                                     \
+  1: bnez a0, 1b
+
+#define EXTRA_TVEC_USER
+#define EXTRA_TVEC_MACHINE
+#define EXTRA_INIT
+#define EXTRA_INIT_TIMER
+
+#define INTERRUPT_HANDLER j other_exception /* No interrupts should occur */
+
+#define RVTEST_CODE_BEGIN                                               \
+        .section .text.init;                                            \
+        .align  6;                                                      \
+        .weak stvec_handler;                                            \
+        .weak mtvec_handler;                                            \
+        .globl _start;                                                  \
+_start:                                                                 \
+        /* reset vector */                                              \
+        j reset_vector;                                                 \
+        .align 2;                                                       \
+trap_vector:                                                            \
+        /* test whether the test came from pass/fail */                 \
+        csrr t5, mcause;                                                \
+        li t6, CAUSE_USER_ECALL;                                        \
+        beq t5, t6, write_tohost;                                       \
+        li t6, CAUSE_SUPERVISOR_ECALL;                                  \
+        beq t5, t6, write_tohost;                                       \
+        li t6, CAUSE_MACHINE_ECALL;                                     \
+        beq t5, t6, write_tohost;                                       \
+        /* if an mtvec_handler is defined, jump to it */                \
+        la t5, mtvec_handler;                                           \
+        beqz t5, 1f;                                                    \
+        jr t5;                                                          \
+        /* was it an interrupt or an exception? */                      \
+  1:    csrr t5, mcause;                                                \
+        bgez t5, handle_exception;                                      \
+        INTERRUPT_HANDLER;                                              \
+handle_exception:                                                       \
+        /* we don't know how to handle whatever the exception was */    \
+  other_exception:                                                      \
+        /* some unhandlable exception occurred */                       \
+  1:    ori TESTNUM, TESTNUM, 1337;                                     \
+  write_tohost:                                                         \
+        sw TESTNUM, tohost, t5;                                         \
+        j write_tohost;                                                 \
+reset_vector:                                                           \
+        INIT_XREG;                                                      \
+        RISCV_MULTICORE_DISABLE;                                        \
+        INIT_SATP;                                                      \
+        INIT_PMP;                                                       \
+        DELEGATE_NO_TRAPS;                                              \
+        li TESTNUM, 0;                                                  \
+        la t0, trap_vector;                                             \
+        csrw mtvec, t0;                                                 \
+        CHECK_XLEN;                                                     \
+        /* if an stvec_handler is defined, delegate exceptions to it */ \
+        la t0, stvec_handler;                                           \
+        beqz t0, 1f;                                                    \
+        csrw stvec, t0;                                                 \
+        li t0, (1 << CAUSE_LOAD_PAGE_FAULT) |                           \
+               (1 << CAUSE_STORE_PAGE_FAULT) |                          \
+               (1 << CAUSE_FETCH_PAGE_FAULT) |                          \
+               (1 << CAUSE_MISALIGNED_FETCH) |                          \
+               (1 << CAUSE_USER_ECALL) |                                \
+               (1 << CAUSE_BREAKPOINT);                                 \
+        csrw medeleg, t0;                                               \
+1:      csrwi mstatus, 0;                                               \
+        init;                                                           \
+        EXTRA_INIT;                                                     \
+        EXTRA_INIT_TIMER;                                               \
+        la t0, 1f;                                                      \
+        csrw mepc, t0;                                                  \
+        csrr a0, mhartid;                                               \
+        mret;                                                           \
+1:
+
+//-----------------------------------------------------------------------
+// End Macro
+//-----------------------------------------------------------------------
+
+#define RVTEST_CODE_END                                                 \
+        unimp
+
+//-----------------------------------------------------------------------
+// Pass/Fail Macro
+//-----------------------------------------------------------------------
+
+#define RVTEST_PASS                                                     \
+        fence;                                                          \
+        li TESTNUM, 1;                                                  \
+        li a7, 93;                                                      \
+        li a0, 0;                                                       \
+        ecall
+
+#define TESTNUM gp
+#define RVTEST_FAIL                                                     \
+        fence;                                                          \
+1:      beqz TESTNUM, 1b;                                               \
+        sll TESTNUM, TESTNUM, 1;                                        \
+        or TESTNUM, TESTNUM, 1;                                         \
+        li a7, 93;                                                      \
+        addi a0, TESTNUM, 0;                                            \
+        ecall
+
+//-----------------------------------------------------------------------
+// Data Section Macro
+//-----------------------------------------------------------------------
+
+#define EXTRA_DATA
+
+#define RVTEST_DATA_BEGIN                                               \
+        EXTRA_DATA                                                      \
+        .pushsection .tohost,"aw",@progbits;                            \
+        .align 6; .global tohost; tohost: .dword 0;                     \
+        .align 6; .global fromhost; fromhost: .dword 0;                 \
+        .popsection;                                                    \
+        .align 4; .global begin_signature; begin_signature:
+
+#define RVTEST_DATA_END .align 4; .global end_signature; end_signature:
+
+#endif
diff --git a/apps/riscv-tests/env/pm/link.ld b/apps/riscv-tests/env/pm/link.ld
new file mode 120000
index 0000000..86b45f9
--- /dev/null
+++ b/apps/riscv-tests/env/pm/link.ld
@@ -0,0 +1 @@
+../p/link.ld
\ No newline at end of file
diff --git a/apps/riscv-tests/env/pm/riscv_test.h b/apps/riscv-tests/env/pm/riscv_test.h
new file mode 100644
index 0000000..38a0e86
--- /dev/null
+++ b/apps/riscv-tests/env/pm/riscv_test.h
@@ -0,0 +1,11 @@
+// See LICENSE for license details.
+
+#ifndef _ENV_PHYSICAL_MULTI_CORE_H
+#define _ENV_PHYSICAL_MULTI_CORE_H
+
+#include "../p/riscv_test.h"
+
+#undef RISCV_MULTICORE_DISABLE
+#define RISCV_MULTICORE_DISABLE
+
+#endif
diff --git a/apps/riscv-tests/env/pt/link.ld b/apps/riscv-tests/env/pt/link.ld
new file mode 120000
index 0000000..86b45f9
--- /dev/null
+++ b/apps/riscv-tests/env/pt/link.ld
@@ -0,0 +1 @@
+../p/link.ld
\ No newline at end of file
diff --git a/apps/riscv-tests/env/pt/riscv_test.h b/apps/riscv-tests/env/pt/riscv_test.h
new file mode 100644
index 0000000..34c2a33
--- /dev/null
+++ b/apps/riscv-tests/env/pt/riscv_test.h
@@ -0,0 +1,69 @@
+// See LICENSE for license details.
+
+#ifndef _ENV_PHYSICAL_SINGLE_CORE_TIMER_H
+#define _ENV_PHYSICAL_SINGLE_CORE_TIMER_H
+
+#include "../p/riscv_test.h"
+
+#define TIMER_INTERVAL 2
+
+#undef EXTRA_INIT_TIMER
+#define EXTRA_INIT_TIMER                                                \
+        li a0, MIP_MTIP;                                                \
+        csrs mie, a0;                                                   \
+        csrr a0, mtime;                                                 \
+        addi a0, a0, TIMER_INTERVAL;                                    \
+        csrw mtimecmp, a0;                                              \
+
+#if SSTATUS_XS != 0x18000
+# error
+#endif
+#define XS_SHIFT 15
+
+#undef INTERRUPT_HANDLER
+#define INTERRUPT_HANDLER                                               \
+        slli t5, t5, 1;                                                 \
+        srli t5, t5, 1;                                                 \
+        add t5, t5, -IRQ_M_TIMER;                                       \
+        bnez t5, other_exception; /* other interrups shouldn't happen */\
+        csrr t5, mtime;                                                 \
+        addi t5, t5, TIMER_INTERVAL;                                    \
+        csrw mtimecmp, t5;                                              \
+        mret;                                                           \
+
+//-----------------------------------------------------------------------
+// Data Section Macro
+//-----------------------------------------------------------------------
+
+#undef EXTRA_DATA
+#define EXTRA_DATA                                                      \
+        .align 3;                                                       \
+regspill:                                                               \
+        .dword 0xdeadbeefcafebabe;                                      \
+        .dword 0xdeadbeefcafebabe;                                      \
+        .dword 0xdeadbeefcafebabe;                                      \
+        .dword 0xdeadbeefcafebabe;                                      \
+        .dword 0xdeadbeefcafebabe;                                      \
+        .dword 0xdeadbeefcafebabe;                                      \
+        .dword 0xdeadbeefcafebabe;                                      \
+        .dword 0xdeadbeefcafebabe;                                      \
+        .dword 0xdeadbeefcafebabe;                                      \
+        .dword 0xdeadbeefcafebabe;                                      \
+        .dword 0xdeadbeefcafebabe;                                      \
+        .dword 0xdeadbeefcafebabe;                                      \
+        .dword 0xdeadbeefcafebabe;                                      \
+        .dword 0xdeadbeefcafebabe;                                      \
+        .dword 0xdeadbeefcafebabe;                                      \
+        .dword 0xdeadbeefcafebabe;                                      \
+        .dword 0xdeadbeefcafebabe;                                      \
+        .dword 0xdeadbeefcafebabe;                                      \
+        .dword 0xdeadbeefcafebabe;                                      \
+        .dword 0xdeadbeefcafebabe;                                      \
+        .dword 0xdeadbeefcafebabe;                                      \
+        .dword 0xdeadbeefcafebabe;                                      \
+        .dword 0xdeadbeefcafebabe;                                      \
+        .dword 0xdeadbeefcafebabe;                                      \
+evac:                                                                   \
+        .skip 32768;                                                    \
+
+#endif
diff --git a/apps/riscv-tests/env/v/entry.S b/apps/riscv-tests/env/v/entry.S
new file mode 100644
index 0000000..fa492e6
--- /dev/null
+++ b/apps/riscv-tests/env/v/entry.S
@@ -0,0 +1,162 @@
+#include "riscv_test.h"
+
+#if __riscv_xlen == 64
+# define STORE    sd
+# define LOAD     ld
+# define REGBYTES 8
+#else
+# define STORE    sw
+# define LOAD     lw
+# define REGBYTES 4
+#endif
+
+#define STACK_TOP (_end + 4096)
+
+  .section ".text.init","ax",@progbits
+  .globl _start
+  .align 2
+_start:
+  j handle_reset
+
+  /* NMI vector */
+  .align 2
+nmi_vector:
+  j wtf
+
+  .align 2
+trap_vector:
+  j wtf
+
+handle_reset:
+  li x1, 0
+  li x2, 0
+  li x3, 0
+  li x4, 0
+  li x5, 0
+  li x6, 0
+  li x7, 0
+  li x8, 0
+  li x9, 0
+  li x10, 0
+  li x11, 0
+  li x12, 0
+  li x13, 0
+  li x14, 0
+  li x15, 0
+  li x16, 0
+  li x17, 0
+  li x18, 0
+  li x19, 0
+  li x20, 0
+  li x21, 0
+  li x22, 0
+  li x23, 0
+  li x24, 0
+  li x25, 0
+  li x26, 0
+  li x27, 0
+  li x28, 0
+  li x29, 0
+  li x30, 0
+  li x31, 0
+
+  la t0, trap_vector
+  csrw mtvec, t0
+  la sp, STACK_TOP - SIZEOF_TRAPFRAME_T
+  csrr t0, mhartid
+  slli t0, t0, 12
+  add sp, sp, t0
+  csrw mscratch, sp
+  call extra_boot
+  la a0, userstart
+  j vm_boot
+
+  .globl  pop_tf
+pop_tf:
+  LOAD  t0,33*REGBYTES(a0)
+  csrw  sepc,t0
+  LOAD  x1,1*REGBYTES(a0)
+  LOAD  x2,2*REGBYTES(a0)
+  LOAD  x3,3*REGBYTES(a0)
+  LOAD  x4,4*REGBYTES(a0)
+  LOAD  x5,5*REGBYTES(a0)
+  LOAD  x6,6*REGBYTES(a0)
+  LOAD  x7,7*REGBYTES(a0)
+  LOAD  x8,8*REGBYTES(a0)
+  LOAD  x9,9*REGBYTES(a0)
+  LOAD  x11,11*REGBYTES(a0)
+  LOAD  x12,12*REGBYTES(a0)
+  LOAD  x13,13*REGBYTES(a0)
+  LOAD  x14,14*REGBYTES(a0)
+  LOAD  x15,15*REGBYTES(a0)
+  LOAD  x16,16*REGBYTES(a0)
+  LOAD  x17,17*REGBYTES(a0)
+  LOAD  x18,18*REGBYTES(a0)
+  LOAD  x19,19*REGBYTES(a0)
+  LOAD  x20,20*REGBYTES(a0)
+  LOAD  x21,21*REGBYTES(a0)
+  LOAD  x22,22*REGBYTES(a0)
+  LOAD  x23,23*REGBYTES(a0)
+  LOAD  x24,24*REGBYTES(a0)
+  LOAD  x25,25*REGBYTES(a0)
+  LOAD  x26,26*REGBYTES(a0)
+  LOAD  x27,27*REGBYTES(a0)
+  LOAD  x28,28*REGBYTES(a0)
+  LOAD  x29,29*REGBYTES(a0)
+  LOAD  x30,30*REGBYTES(a0)
+  LOAD  x31,31*REGBYTES(a0)
+  LOAD  a0,10*REGBYTES(a0)
+  sret
+
+  .global  trap_entry
+  .align 2
+trap_entry:
+  csrrw sp, sscratch, sp
+
+  # save gprs
+  STORE  x1,1*REGBYTES(sp)
+  STORE  x3,3*REGBYTES(sp)
+  STORE  x4,4*REGBYTES(sp)
+  STORE  x5,5*REGBYTES(sp)
+  STORE  x6,6*REGBYTES(sp)
+  STORE  x7,7*REGBYTES(sp)
+  STORE  x8,8*REGBYTES(sp)
+  STORE  x9,9*REGBYTES(sp)
+  STORE  x10,10*REGBYTES(sp)
+  STORE  x11,11*REGBYTES(sp)
+  STORE  x12,12*REGBYTES(sp)
+  STORE  x13,13*REGBYTES(sp)
+  STORE  x14,14*REGBYTES(sp)
+  STORE  x15,15*REGBYTES(sp)
+  STORE  x16,16*REGBYTES(sp)
+  STORE  x17,17*REGBYTES(sp)
+  STORE  x18,18*REGBYTES(sp)
+  STORE  x19,19*REGBYTES(sp)
+  STORE  x20,20*REGBYTES(sp)
+  STORE  x21,21*REGBYTES(sp)
+  STORE  x22,22*REGBYTES(sp)
+  STORE  x23,23*REGBYTES(sp)
+  STORE  x24,24*REGBYTES(sp)
+  STORE  x25,25*REGBYTES(sp)
+  STORE  x26,26*REGBYTES(sp)
+  STORE  x27,27*REGBYTES(sp)
+  STORE  x28,28*REGBYTES(sp)
+  STORE  x29,29*REGBYTES(sp)
+  STORE  x30,30*REGBYTES(sp)
+  STORE  x31,31*REGBYTES(sp)
+
+  csrrw  t0,sscratch,sp
+  STORE  t0,2*REGBYTES(sp)
+
+  # get sr, epc, badvaddr, cause
+  csrr   t0,sstatus
+  STORE  t0,32*REGBYTES(sp)
+  csrr   t0,sepc
+  STORE  t0,33*REGBYTES(sp)
+  csrr   t0,sbadaddr
+  STORE  t0,34*REGBYTES(sp)
+  csrr   t0,scause
+  STORE  t0,35*REGBYTES(sp)
+
+  move  a0, sp
+  j handle_trap
diff --git a/apps/riscv-tests/env/v/link.ld b/apps/riscv-tests/env/v/link.ld
new file mode 120000
index 0000000..86b45f9
--- /dev/null
+++ b/apps/riscv-tests/env/v/link.ld
@@ -0,0 +1 @@
+../p/link.ld
\ No newline at end of file
diff --git a/apps/riscv-tests/env/v/riscv_test.h b/apps/riscv-tests/env/v/riscv_test.h
new file mode 100644
index 0000000..c74e05d
--- /dev/null
+++ b/apps/riscv-tests/env/v/riscv_test.h
@@ -0,0 +1,80 @@
+// See LICENSE for license details.
+
+#ifndef _ENV_VIRTUAL_SINGLE_CORE_H
+#define _ENV_VIRTUAL_SINGLE_CORE_H
+
+#include "../p/riscv_test.h"
+
+//-----------------------------------------------------------------------
+// Begin Macro
+//-----------------------------------------------------------------------
+
+#undef RVTEST_FP_ENABLE
+#define RVTEST_FP_ENABLE fssr x0
+
+#undef RVTEST_VECTOR_ENABLE
+#define RVTEST_VECTOR_ENABLE                                            \
+  csrwi fcsr, 0;                                                        \
+  csrwi vcsr, 0;
+
+#undef RVTEST_CODE_BEGIN
+#define RVTEST_CODE_BEGIN                                               \
+        .text;                                                          \
+        .global extra_boot;                                             \
+extra_boot:                                                             \
+        EXTRA_INIT                                                      \
+        ret;                                                            \
+        .global userstart;                                              \
+userstart:                                                              \
+        init
+
+//-----------------------------------------------------------------------
+// Pass/Fail Macro
+//-----------------------------------------------------------------------
+
+#undef RVTEST_PASS
+#define RVTEST_PASS li a0, 1; scall
+
+#undef RVTEST_FAIL
+#define RVTEST_FAIL sll a0, TESTNUM, 1; 1:beqz a0, 1b; or a0, a0, 1; scall;
+
+//-----------------------------------------------------------------------
+// Data Section Macro
+//-----------------------------------------------------------------------
+
+#undef RVTEST_DATA_END
+#define RVTEST_DATA_END
+
+//-----------------------------------------------------------------------
+// Supervisor mode definitions and macros
+//-----------------------------------------------------------------------
+
+#define MAX_TEST_PAGES 63 // this must be the period of the LFSR below
+#define LFSR_NEXT(x) (((((x)^((x)>>1)) & 1) << 5) | ((x) >> 1))
+
+#define PGSHIFT 12
+#define PGSIZE (1UL << PGSHIFT)
+
+#define SIZEOF_TRAPFRAME_T ((__riscv_xlen / 8) * 36)
+
+#ifndef __ASSEMBLER__
+
+typedef unsigned long pte_t;
+#define LEVELS (sizeof(pte_t) == sizeof(uint64_t) ? 3 : 2)
+#define PTIDXBITS (PGSHIFT - (sizeof(pte_t) == 8 ? 3 : 2))
+#define VPN_BITS (PTIDXBITS * LEVELS)
+#define VA_BITS (VPN_BITS + PGSHIFT)
+#define PTES_PER_PT (1UL << RISCV_PGLEVEL_BITS)
+#define MEGAPAGE_SIZE (PTES_PER_PT * PGSIZE)
+
+typedef struct
+{
+  long gpr[32];
+  long sr;
+  long epc;
+  long badvaddr;
+  long cause;
+} trapframe_t;
+#endif
+
+#endif
diff --git a/apps/riscv-tests/env/v/string.c b/apps/riscv-tests/env/v/string.c
new file mode 100644
index 0000000..4ffedc0
--- /dev/null
+++ b/apps/riscv-tests/env/v/string.c
@@ -0,0 +1,114 @@
+#include <string.h>
+#include <stdint.h>
+#include <ctype.h>
+
+void* memcpy(void* dest, const void* src, size_t len)
+{
+  if ((((uintptr_t)dest | (uintptr_t)src | len) & (sizeof(uintptr_t)-1)) == 0) {
+    const uintptr_t* s = src;
+    uintptr_t *d = dest;
+    while (d < (uintptr_t*)(dest + len))
+      *d++ = *s++;
+  } else {
+    const char* s = src;
+    char *d = dest;
+    while (d < (char*)(dest + len))
+      *d++ = *s++;
+  }
+  return dest;
+}
+
+void* memset(void* dest, int byte, size_t len)
+{
+  if ((((uintptr_t)dest | len) & (sizeof(uintptr_t)-1)) == 0) {
+    uintptr_t word = byte & 0xFF;
+    word |= word << 8;
+    word |= word << 16;
+    word |= word << 16 << 16;
+
+    uintptr_t *d = dest;
+    while (d < (uintptr_t*)(dest + len))
+      *d++ = word;
+  } else {
+    char *d = dest;
+    while (d < (char*)(dest + len))
+      *d++ = byte;
+  }
+  return dest;
+}
+
+size_t strlen(const char *s)
+{
+  const char *p = s;
+  while (*p)
+    p++;
+  return p - s;
+}
+
+int strcmp(const char* s1, const char* s2)
+{
+  unsigned char c1, c2;
+
+  do {
+    c1 = *s1++;
+    c2 = *s2++;
+  } while (c1 != 0 && c1 == c2);
+
+  return c1 - c2;
+}
+
+int memcmp(const void* s1, const void* s2, size_t n)
+{
+  if ((((uintptr_t)s1 | (uintptr_t)s2) & (sizeof(uintptr_t)-1)) == 0) {
+    const uintptr_t* u1 = s1;
+    const uintptr_t* u2 = s2;
+    const uintptr_t* end = u1 + (n / sizeof(uintptr_t));
+    while (u1 < end) {
+      if (*u1 != *u2)
+        break;
+      u1++;
+      u2++;
+    }
+    n -= (const void*)u1 - s1;
+    s1 = u1;
+    s2 = u2;
+  }
+
+  while (n--) {
+    unsigned char c1 = *(const unsigned char*)s1++;
+    unsigned char c2 = *(const unsigned char*)s2++;
+    if (c1 != c2)
+      return c1 - c2;
+  }
+
+  return 0;
+}
+
+char* strcpy(char* dest, const char* src)
+{
+  char* d = dest;
+  while ((*d++ = *src++))
+    ;
+  return dest;
+}
+
+long atol(const char* str)
+{
+  long res = 0;
+  int sign = 0;
+
+  while (*str == ' ')
+    str++;
+
+  if (*str == '-' || *str == '+') {
+    sign = *str == '-';
+    str++;
+  }
+
+  while (*str) {
+    res *= 10;
+    res += *str++ - '0';
+  }
+
+  return sign ? -res : res;
+}
diff --git a/apps/riscv-tests/env/v/vm.c b/apps/riscv-tests/env/v/vm.c
new file mode 100644
index 0000000..71700f5
--- /dev/null
+++ b/apps/riscv-tests/env/v/vm.c
@@ -0,0 +1,300 @@
+// See LICENSE for license details.
+
+#include <stdint.h>
+#include <string.h>
+#include <stdio.h>
+
+#include "riscv_test.h"
+
+#if __riscv_xlen == 32
+# define SATP_MODE_CHOICE SATP_MODE_SV32
+#elif defined(Sv48)
+# define SATP_MODE_CHOICE SATP_MODE_SV48
+#else
+# define SATP_MODE_CHOICE SATP_MODE_SV39
+#endif
+
+void trap_entry();
+void pop_tf(trapframe_t*);
+
+extern volatile uint64_t tohost;
+extern volatile uint64_t fromhost;
+
+static void do_tohost(uint64_t tohost_value)
+{
+  while (tohost)
+    fromhost = 0;
+  tohost = tohost_value;
+}
+
+#define pa2kva(pa) ((void*)(pa) - DRAM_BASE - MEGAPAGE_SIZE)
+#define uva2kva(pa) ((void*)(pa) - MEGAPAGE_SIZE)
+
+#define flush_page(addr) asm volatile ("sfence.vma %0" : : "r" (addr) : "memory")
+
+static uint64_t lfsr63(uint64_t x)
+{
+  uint64_t bit = (x ^ (x >> 1)) & 1;
+  return (x >> 1) | (bit << 62);
+}
+
+static void cputchar(int x)
+{
+  do_tohost(0x0101000000000000 | (unsigned char)x);
+}
+
+static void cputstring(const char* s)
+{
+  while (*s)
+    cputchar(*s++);
+}
+
+static void terminate(int code)
+{
+  do_tohost(code);
+  while (1);
+}
+
+void wtf()
+{
+  terminate(841);
+}
+
+#define stringify1(x) #x
+#define stringify(x) stringify1(x)
+#define assert(x) do { \
+  if (x) break; \
+  cputstring("Assertion failed: " stringify(x) "\n"); \
+  terminate(3); \
+} while(0)
+
+#define l1pt pt[0]
+#define user_l2pt pt[1]
+#if SATP_MODE_CHOICE == SATP_MODE_SV48
+# define NPT 6
+# define kernel_l2pt pt[2]
+# define kernel_l3pt pt[3]
+# define user_l3pt pt[4]
+# define user_llpt pt[5]
+#elif SATP_MODE_CHOICE == SATP_MODE_SV39
+# define NPT 4
+# define kernel_l2pt pt[2]
+# define user_llpt pt[3]
+#elif SATP_MODE_CHOICE == SATP_MODE_SV32
+# define NPT 2
+# define user_llpt user_l2pt
+#else
+# error Unknown SATP_MODE_CHOICE
+#endif
+pte_t pt[NPT][PTES_PER_PT] __attribute__((aligned(PGSIZE)));
+
+typedef struct { pte_t addr; void* next; } freelist_t;
+
+freelist_t user_mapping[MAX_TEST_PAGES];
+freelist_t freelist_nodes[MAX_TEST_PAGES];
+freelist_t *freelist_head, *freelist_tail;
+
+void printhex(uint64_t x)
+{
+  char str[17];
+  for (int i = 0; i < 16; i++)
+  {
+    str[15-i] = (x & 0xF) + ((x & 0xF) < 10 ? '0' : 'a'-10);
+    x >>= 4;
+  }
+  str[16] = 0;
+
+  cputstring(str);
+}
+
+static void evict(unsigned long addr)
+{
+  assert(addr >= PGSIZE && addr < MAX_TEST_PAGES * PGSIZE);
+  addr = addr/PGSIZE*PGSIZE;
+
+  freelist_t* node = &user_mapping[addr/PGSIZE];
+  if (node->addr)
+  {
+    // check accessed and dirty bits
+    assert(user_llpt[addr/PGSIZE] & PTE_A);
+    uintptr_t sstatus = set_csr(sstatus, SSTATUS_SUM);
+    if (memcmp((void*)addr, uva2kva(addr), PGSIZE)) {
+      assert(user_llpt[addr/PGSIZE] & PTE_D);
+      memcpy((void*)addr, uva2kva(addr), PGSIZE);
+    }
+    write_csr(sstatus, sstatus);
+
+    user_mapping[addr/PGSIZE].addr = 0;
+
+    if (freelist_tail == 0)
+      freelist_head = freelist_tail = node;
+    else
+    {
+      freelist_tail->next = node;
+      freelist_tail = node;
+    }
+  }
+}
+
+void handle_fault(uintptr_t addr, uintptr_t cause)
+{
+  assert(addr >= PGSIZE && addr < MAX_TEST_PAGES * PGSIZE);
+  addr = addr/PGSIZE*PGSIZE;
+
+  if (user_llpt[addr/PGSIZE]) {
+    if (!(user_llpt[addr/PGSIZE] & PTE_A)) {
+      user_llpt[addr/PGSIZE] |= PTE_A;
+    } else {
+      assert(!(user_llpt[addr/PGSIZE] & PTE_D) && cause == CAUSE_STORE_PAGE_FAULT);
+      user_llpt[addr/PGSIZE] |= PTE_D;
+    }
+    flush_page(addr);
+    return;
+  }
+
+  freelist_t* node = freelist_head;
+  assert(node);
+  freelist_head = node->next;
+  if (freelist_head == freelist_tail)
+    freelist_tail = 0;
+
+  uintptr_t new_pte = (node->addr >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_W | PTE_X;
+  user_llpt[addr/PGSIZE] = new_pte | PTE_A | PTE_D;
+  flush_page(addr);
+
+  assert(user_mapping[addr/PGSIZE].addr == 0);
+  user_mapping[addr/PGSIZE] = *node;
+
+  uintptr_t sstatus = set_csr(sstatus, SSTATUS_SUM);
+  memcpy((void*)addr, uva2kva(addr), PGSIZE);
+  write_csr(sstatus, sstatus);
+
+  user_llpt[addr/PGSIZE] = new_pte;
+  flush_page(addr);
+
+  __builtin___clear_cache(0,0);
+}
+
+void handle_trap(trapframe_t* tf)
+{
+  if (tf->cause == CAUSE_USER_ECALL)
+  {
+    int n = tf->gpr[10];
+
+    for (long i = 1; i < MAX_TEST_PAGES; i++)
+      evict(i*PGSIZE);
+
+    terminate(n);
+  }
+  else if (tf->cause == CAUSE_ILLEGAL_INSTRUCTION)
+  {
+    assert(tf->epc % 4 == 0);
+
+    int* fssr;
+    asm ("jal %0, 1f; fssr x0; 1:" : "=r"(fssr));
+
+    if (*(int*)tf->epc == *fssr)
+      terminate(1); // FP test on non-FP hardware.  "succeed."
+    else
+      assert(!"illegal instruction");
+    tf->epc += 4;
+  }
+  else if (tf->cause == CAUSE_FETCH_PAGE_FAULT || tf->cause == CAUSE_LOAD_PAGE_FAULT || tf->cause == CAUSE_STORE_PAGE_FAULT)
+    handle_fault(tf->badvaddr, tf->cause);
+  else
+    assert(!"unexpected exception");
+
+  pop_tf(tf);
+}
+
+static void coherence_torture()
+{
+  // cause coherence misses without affecting program semantics
+  uint64_t random = ENTROPY;
+  while (1) {
+    uintptr_t paddr = DRAM_BASE + ((random % (2 * (MAX_TEST_PAGES + 1) * PGSIZE)) & -4);
+#ifdef __riscv_atomic
+    if (random & 1) // perform a no-op write
+      asm volatile ("amoadd.w zero, zero, (%0)" :: "r"(paddr));
+    else // perform a read
+#endif
+      asm volatile ("lw zero, (%0)" :: "r"(paddr));
+    random = lfsr63(random);
+  }
+}
+
+void vm_boot(uintptr_t test_addr)
+{
+  uint64_t random = ENTROPY;
+  if (read_csr(mhartid) > 0)
+    coherence_torture();
+
+  _Static_assert(SIZEOF_TRAPFRAME_T == sizeof(trapframe_t), "???");
+
+#if (MAX_TEST_PAGES > PTES_PER_PT) || (DRAM_BASE % MEGAPAGE_SIZE) != 0
+# error
+#endif
+  // map user to lowermost megapage
+  l1pt[0] = ((pte_t)user_l2pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V;
+  // map kernel to uppermost megapage
+#if SATP_MODE_CHOICE == SATP_MODE_SV48
+  l1pt[PTES_PER_PT-1] = ((pte_t)kernel_l2pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V;
+  kernel_l2pt[PTES_PER_PT-1] = ((pte_t)kernel_l3pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V;
+  kernel_l3pt[PTES_PER_PT-1] = (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D;
+  user_l2pt[0] = ((pte_t)user_l3pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V;
+  user_l3pt[0] = ((pte_t)user_llpt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V;
+#elif SATP_MODE_CHOICE == SATP_MODE_SV39
+  l1pt[PTES_PER_PT-1] = ((pte_t)kernel_l2pt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V;
+  kernel_l2pt[PTES_PER_PT-1] = (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D;
+  user_l2pt[0] = ((pte_t)user_llpt >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V;
+#elif SATP_MODE_CHOICE == SATP_MODE_SV32
+  l1pt[PTES_PER_PT-1] = (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D;
+#else
+# error
+#endif
+  uintptr_t vm_choice = SATP_MODE_CHOICE;
+  uintptr_t sptbr_value = ((uintptr_t)l1pt >> PGSHIFT)
+                        | (vm_choice * (SATP_MODE & ~(SATP_MODE<<1)));
+  write_csr(sptbr, sptbr_value);
+  if (read_csr(sptbr) != sptbr_value)
+    assert(!"unsupported satp mode");
+
+  // Set up PMPs if present, ignoring illegal instruction trap if not.
+  uintptr_t pmpc = PMP_NAPOT | PMP_R | PMP_W | PMP_X;
+  uintptr_t pmpa = ((uintptr_t)1 << (__riscv_xlen == 32 ? 31 : 53)) - 1;
+  asm volatile ("la t0, 1f\n\t"
+                "csrrw t0, mtvec, t0\n\t"
+                "csrw pmpaddr0, %1\n\t"
+                "csrw pmpcfg0, %0\n\t"
+                ".align 2\n\t"
+                "1: csrw mtvec, t0"
+                : : "r" (pmpc), "r" (pmpa) : "t0");
+
+  // set up supervisor trap handling
+  write_csr(stvec, pa2kva(trap_entry));
+  write_csr(sscratch, pa2kva(read_csr(mscratch)));
+  write_csr(medeleg,
+    (1 << CAUSE_USER_ECALL) |
+    (1 << CAUSE_FETCH_PAGE_FAULT) |
+    (1 << CAUSE_LOAD_PAGE_FAULT) |
+    (1 << CAUSE_STORE_PAGE_FAULT));
+  // FPU on; accelerator on; vector unit on
+  write_csr(mstatus, MSTATUS_FS | MSTATUS_XS | MSTATUS_VS);
+  write_csr(mie, 0);
+
+  random = 1 + (random % MAX_TEST_PAGES);
+  freelist_head = pa2kva((void*)&freelist_nodes[0]);
+  freelist_tail = pa2kva(&freelist_nodes[MAX_TEST_PAGES-1]);
+  for (long i = 0; i < MAX_TEST_PAGES; i++)
+  {
+    freelist_nodes[i].addr = DRAM_BASE + (MAX_TEST_PAGES + random)*PGSIZE;
+    freelist_nodes[i].next = pa2kva(&freelist_nodes[i+1]);
+    random = LFSR_NEXT(random);
+  }
+  freelist_nodes[MAX_TEST_PAGES-1].next = 0;
+
+  trapframe_t tf;
+  memset(&tf, 0, sizeof(tf));
+  tf.epc = test_addr - DRAM_BASE;
+  pop_tf(&tf);
+}
diff --git a/apps/riscv-tests/isa/.gitignore b/apps/riscv-tests/isa/.gitignore
new file mode 100644
index 0000000..c93c5ff
--- /dev/null
+++ b/apps/riscv-tests/isa/.gitignore
@@ -0,0 +1 @@
+rv*-*
diff --git a/apps/riscv-tests/isa/Makefile b/apps/riscv-tests/isa/Makefile
new file mode 100644
index 0000000..6813427
--- /dev/null
+++ b/apps/riscv-tests/isa/Makefile
@@ -0,0 +1,152 @@
+#=======================================================================
+# Makefile for riscv-tests/isa
+#-----------------------------------------------------------------------
+
+XLEN ?= 64
+
+src_dir := .
+
+ifeq ($(XLEN),64)
+include $(src_dir)/rv64ui/Makefrag
+include $(src_dir)/rv64uc/Makefrag
+include $(src_dir)/rv64um/Makefrag
+include $(src_dir)/rv64ua/Makefrag
+include $(src_dir)/rv64uf/Makefrag
+include $(src_dir)/rv64ud/Makefrag
+include $(src_dir)/rv64uv/Makefrag
+include $(src_dir)/rv64si/Makefrag
+include $(src_dir)/rv64mi/Makefrag
+endif
+include $(src_dir)/rv32ui/Makefrag
+include $(src_dir)/rv32uc/Makefrag
+include $(src_dir)/rv32um/Makefrag
+include $(src_dir)/rv32ua/Makefrag
+include $(src_dir)/rv32uf/Makefrag
+include $(src_dir)/rv32ud/Makefrag
+include $(src_dir)/rv32si/Makefrag
+include $(src_dir)/rv32mi/Makefrag
+
+default: all
+
+#--------------------------------------------------------------------
+# Build rules
+#--------------------------------------------------------------------
+
+# Original GCC variables
+RISCV_PREFIX ?= riscv$(XLEN)-unknown-elf-
+RISCV_GCC ?= $(RISCV_PREFIX)gcc
+RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
+RISCV_GCC_OPTS_C ?= -O2
+
+# Added LLVM variables
+RISCV_LLVM ?= clang -fuse-ld=lld
+RISCV_CC_OPTS ?= -mcmodel=medany -fvisibility=hidden -mno-relax -nostdlib -nostartfiles
+RISCV_CC_OPTS_C ?= -O2 -mno-relax -nostdlib -nostartfiles -fno-vectorize -mllvm -scalable-vectorization=off -mllvm -riscv-v-vector-bits-min=0 -mno-implicit-float
+RISCV_CC_DEFS_C ?= $(ARA_DEFINES)
+LLVM_V_VERSION ?= v_zfh_zvfh
+
+# Original objdump + spike variables
+RISCV_OBJDUMP ?= llvm-objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data
+RISCV_SIM ?= spike
+
+vpath %.S $(src_dir)
+
+#------------------------------------------------------------
+# Build assembly tests
+
+%.dump: %
+	$(RISCV_OBJDUMP) $< > $@
+
+%.out: %
+	$(RISCV_SIM) --isa=rv64gcv --varch="vlen:4096,elen:64" $< 2> $@
+
+%.out32: %
+	$(RISCV_SIM) --isa=rv32gcv $< 2> $@
+
+%.cout: %
+	$(RISCV_SIM) --isa=rv64gcv_zfh --varch="vlen:4096,elen:64" $< 2> $@
+
+%.cout32: %
+	$(RISCV_SIM) --isa=rv32gcv $< 2> $@
+
+define compile_template
+
+$$($(1)_p_tests): $(1)-p-%: $(1)/%.S
+	$$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -I$(src_dir)/../env/p -I$(src_dir)/macros/scalar -I$(src_dir)/macros/vector -T$(src_dir)/../env/p/link.ld $$< -o $$@
+$(1)_tests += $$($(1)_p_tests)
+
+$$($(1)_v_tests): $(1)-v-%: $(1)/%.S
+	$$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -DENTROPY=0x$$(shell echo \$$@ | md5sum | cut -c 1-7) -std=gnu99 -O2 -I$(src_dir)/../env/v -I$(src_dir)/macros/scalar -I$(src_dir)/macros/vector -T$(src_dir)/../env/v/link.ld $(src_dir)/../env/v/entry.S $(src_dir)/../env/v/*.c $$< -o $$@
+$(1)_tests += $$($(1)_v_tests)
+
+$(1)_tests_dump = $$(addsuffix .dump, $$($(1)_tests))
+
+$(1): $$($(1)_tests_dump)
+
+.PHONY: $(1)
+
+tests += $$($(1)_tests)
+
+endef
+
+define compile_template_c
+
+$$($(1)_p_tests): $(1)-p-%: $(1)/%.c ../benchmarks/common/crt.S ../benchmarks/common/syscalls.c
+	$$(RISCV_LLVM) $$(RISCV_CC_OPTS_C) $$(RISCV_CC_DEFS_C) $(2)$$(LLVM_V_VERSION) $(3) -mcmodel=medany -std=gnu99 -O2 -ffast-math -fno-common -fno-builtin-printf -I../benchmarks/../env -I../benchmarks/common -I$(src_dir)/macros/scalar -I$(src_dir)/macros/vector -DPREALLOCATE=1 -D__FLOAT_SUPPORT__ -D__SPIKE__=1 $$(RISCV_LD_OPTS) -static -O2 -nostdlib -T../benchmarks/common/test.ld -o $$@ $$^
+$(1)_tests += $$($(1)_p_tests)
+
+$$($(1)_v_tests): $(1)-v-%: $(1)/%.c ../benchmarks/common/crt.S ../benchmarks/common/syscalls.c
+	$$(RISCV_LLVM) $$(RISCV_CC_OPTS_C) $$(RISCV_CC_DEFS_C) $(2)$$(LLVM_V_VERSION) $(3) -mcmodel=medany -std=gnu99 -O2 -ffast-math -fno-common -fno-builtin-printf -I../benchmarks/../env -I../benchmarks/common -I$(src_dir)/macros/scalar -I$(src_dir)/macros/vector -DPREALLOCATE=1 -D__FLOAT_SUPPORT__ -D__SPIKE__=1 $$(RISCV_LD_OPTS) -static -O2 -nostdlib -T../benchmarks/common/test.ld -o $$@ $$^
+$(1)_tests += $$($(1)_v_tests)
+
+$(1)_tests_dump = $$(addsuffix .dump, $$($(1)_tests))
+
+$(1): $$($(1)_tests_dump)
+
+.PHONY: $(1)
+
+tests += $$($(1)_tests)
+
+endef
+
+$(eval $(call compile_template,rv32ui,-march=rv32g -mabi=ilp32))
+$(eval $(call compile_template,rv32uc,-march=rv32g -mabi=ilp32))
+$(eval $(call compile_template,rv32um,-march=rv32g -mabi=ilp32))
+$(eval $(call compile_template,rv32ua,-march=rv32g -mabi=ilp32))
+$(eval $(call compile_template,rv32uf,-march=rv32g -mabi=ilp32))
+$(eval $(call compile_template,rv32ud,-march=rv32g -mabi=ilp32))
+$(eval $(call compile_template,rv32si,-march=rv32g -mabi=ilp32))
+$(eval $(call compile_template,rv32mi,-march=rv32g -mabi=ilp32))
+ifeq ($(XLEN),64)
+$(eval $(call compile_template,rv64ui,-march=rv64g -mabi=lp64))
+$(eval $(call compile_template,rv64uc,-march=rv64g -mabi=lp64))
+$(eval $(call compile_template,rv64um,-march=rv64g -mabi=lp64))
+$(eval $(call compile_template,rv64ua,-march=rv64g -mabi=lp64))
+$(eval $(call compile_template,rv64uf,-march=rv64g -mabi=lp64))
+$(eval $(call compile_template,rv64ud,-march=rv64g -mabi=lp64))
+$(eval $(call compile_template_c,rv64uv,-march=rv64g, -mabi=lp64))
+$(eval $(call compile_template,rv64si,-march=rv64g -mabi=lp64))
+$(eval $(call compile_template,rv64mi,-march=rv64g -mabi=lp64))
+endif
+
+tests_dump = $(addsuffix .dump, $(tests))
+tests_hex = $(addsuffix .hex, $(tests))
+tests_out = $(addsuffix .out, $(spike_tests))
+tests32_out = $(addsuffix .out32, $(spike32_tests))
+tests_cout = $(addsuffix .cout, $(spike_ctests))
+tests32_cout = $(addsuffix .cout32, $(spike32_ctests))
+
+run: $(tests_out) $(tests32_out) $(tests_cout) $(tests32_cout)
+
+junk += $(tests) $(tests_dump) $(tests_hex) $(tests_out) $(tests32_out) $(tests_cout) $(tests32_cout)
+
+#------------------------------------------------------------
+# Default
+
+all: $(tests_dump)
+
+#------------------------------------------------------------
+# Clean up
+
+clean:
+	rm -rf $(junk)
diff --git a/apps/riscv-tests/isa/macros/scalar/test_macros.h b/apps/riscv-tests/isa/macros/scalar/test_macros.h
new file mode 100644
index 0000000..ed4cab0
--- /dev/null
+++ b/apps/riscv-tests/isa/macros/scalar/test_macros.h
@@ -0,0 +1,649 @@
+// See LICENSE for license details.
+
+#ifndef __TEST_MACROS_SCALAR_H
+#define __TEST_MACROS_SCALAR_H
+
+
+#-----------------------------------------------------------------------
+# Helper macros
+#-----------------------------------------------------------------------
+
+#define MASK_XLEN(x) ((x) & ((1 << (__riscv_xlen - 1) << 1) - 1))
+
+#define TEST_CASE( testnum, testreg, correctval, code... ) \
+test_ ## testnum: \
+    code; \
+    li  x7, MASK_XLEN(correctval); \
+    li  TESTNUM, testnum; \
+    bne testreg, x7, fail;
+
+# We use a macro hack to simpify code generation for various numbers
+# of bubble cycles.
+
+#define TEST_INSERT_NOPS_0
+#define TEST_INSERT_NOPS_1  nop; TEST_INSERT_NOPS_0
+#define TEST_INSERT_NOPS_2  nop; TEST_INSERT_NOPS_1
+#define TEST_INSERT_NOPS_3  nop; TEST_INSERT_NOPS_2
+#define TEST_INSERT_NOPS_4  nop; TEST_INSERT_NOPS_3
+#define TEST_INSERT_NOPS_5  nop; TEST_INSERT_NOPS_4
+#define TEST_INSERT_NOPS_6  nop; TEST_INSERT_NOPS_5
+#define TEST_INSERT_NOPS_7  nop; TEST_INSERT_NOPS_6
+#define TEST_INSERT_NOPS_8  nop; TEST_INSERT_NOPS_7
+#define TEST_INSERT_NOPS_9  nop; TEST_INSERT_NOPS_8
+#define TEST_INSERT_NOPS_10 nop; TEST_INSERT_NOPS_9
+
+
+#-----------------------------------------------------------------------
+# RV64UI MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests for instructions with immediate operand
+#-----------------------------------------------------------------------
+
+#define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11))
+
+#define TEST_IMM_OP( testnum, inst, result, val1, imm ) \
+    TEST_CASE( testnum, x14, result, \
+      li  x1, MASK_XLEN(val1); \
+      inst x14, x1, SEXT_IMM(imm); \
+    )
+
+#define TEST_IMM_SRC1_EQ_DEST( testnum, inst, result, val1, imm ) \
+    TEST_CASE( testnum, x1, result, \
+      li  x1, MASK_XLEN(val1); \
+      inst x1, x1, SEXT_IMM(imm); \
+    )
+
+#define TEST_IMM_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
+    TEST_CASE( testnum, x6, result, \
+      li  x4, 0; \
+1:    li  x1, MASK_XLEN(val1); \
+      inst x14, x1, SEXT_IMM(imm); \
+      TEST_INSERT_NOPS_ ## nop_cycles \
+      addi  x6, x14, 0; \
+      addi  x4, x4, 1; \
+      li  x5, 2; \
+      bne x4, x5, 1b \
+    )
+
+#define TEST_IMM_SRC1_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
+    TEST_CASE( testnum, x14, result, \
+      li  x4, 0; \
+1:    li  x1, MASK_XLEN(val1); \
+      TEST_INSERT_NOPS_ ## nop_cycles \
+      inst x14, x1, SEXT_IMM(imm); \
+      addi  x4, x4, 1; \
+      li  x5, 2; \
+      bne x4, x5, 1b \
+    )
+
+#define TEST_IMM_ZEROSRC1( testnum, inst, result, imm ) \
+    TEST_CASE( testnum, x1, result, \
+      inst x1, x0, SEXT_IMM(imm); \
+    )
+
+#define TEST_IMM_ZERODEST( testnum, inst, val1, imm ) \
+    TEST_CASE( testnum, x0, 0, \
+      li  x1, MASK_XLEN(val1); \
+      inst x0, x1, SEXT_IMM(imm); \
+    )
+
+#-----------------------------------------------------------------------
+# Tests for an instruction with register operands
+#-----------------------------------------------------------------------
+
+#define TEST_R_OP( testnum, inst, result, val1 ) \
+    TEST_CASE( testnum, x14, result, \
+      li  x1, val1; \
+      inst x14, x1; \
+    )
+
+#define TEST_R_SRC1_EQ_DEST( testnum, inst, result, val1 ) \
+    TEST_CASE( testnum, x1, result, \
+      li  x1, val1; \
+      inst x1, x1; \
+    )
+
+#define TEST_R_DEST_BYPASS( testnum, nop_cycles, inst, result, val1 ) \
+    TEST_CASE( testnum, x6, result, \
+      li  x4, 0; \
+1:    li  x1, val1; \
+      inst x14, x1; \
+      TEST_INSERT_NOPS_ ## nop_cycles \
+      addi  x6, x14, 0; \
+      addi  x4, x4, 1; \
+      li  x5, 2; \
+      bne x4, x5, 1b \
+    )
+
+#-----------------------------------------------------------------------
+# Tests for an instruction with register-register operands
+#-----------------------------------------------------------------------
+
+#define TEST_RR_OP( testnum, inst, result, val1, val2 ) \
+    TEST_CASE( testnum, x14, result, \
+      li  x1, MASK_XLEN(val1); \
+      li  x2, MASK_XLEN(val2); \
+      inst x14, x1, x2; \
+    )
+
+#define TEST_RR_SRC1_EQ_DEST( testnum, inst, result, val1, val2 ) \
+    TEST_CASE( testnum, x1, result, \
+      li  x1, MASK_XLEN(val1); \
+      li  x2, MASK_XLEN(val2); \
+      inst x1, x1, x2; \
+    )
+
+#define TEST_RR_SRC2_EQ_DEST( testnum, inst, result, val1, val2 ) \
+    TEST_CASE( testnum, x2, result, \
+      li  x1, MASK_XLEN(val1); \
+      li  x2, MASK_XLEN(val2); \
+      inst x2, x1, x2; \
+    )
+
+#define TEST_RR_SRC12_EQ_DEST( testnum, inst, result, val1 ) \
+    TEST_CASE( testnum, x1, result, \
+      li  x1, MASK_XLEN(val1); \
+      inst x1, x1, x1; \
+    )
+
+#define TEST_RR_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, val2 ) \
+    TEST_CASE( testnum, x6, result, \
+      li  x4, 0; \
+1:    li  x1, MASK_XLEN(val1); \
+      li  x2, MASK_XLEN(val2); \
+      inst x14, x1, x2; \
+      TEST_INSERT_NOPS_ ## nop_cycles \
+      addi  x6, x14, 0; \
+      addi  x4, x4, 1; \
+      li  x5, 2; \
+      bne x4, x5, 1b \
+    )
+
+#define TEST_RR_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
+    TEST_CASE( testnum, x14, result, \
+      li  x4, 0; \
+1:    li  x1, MASK_XLEN(val1); \
+      TEST_INSERT_NOPS_ ## src1_nops \
+      li  x2, MASK_XLEN(val2); \
+      TEST_INSERT_NOPS_ ## src2_nops \
+      inst x14, x1, x2; \
+      addi  x4, x4, 1; \
+      li  x5, 2; \
+      bne x4, x5, 1b \
+    )
+
+#define TEST_RR_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \
+    TEST_CASE( testnum, x14, result, \
+      li  x4, 0; \
+1:    li  x2, MASK_XLEN(val2); \
+      TEST_INSERT_NOPS_ ## src1_nops \
+      li  x1, MASK_XLEN(val1); \
+      TEST_INSERT_NOPS_ ## src2_nops \
+      inst x14, x1, x2; \
+      addi  x4, x4, 1; \
+      li  x5, 2; \
+      bne x4, x5, 1b \
+    )
+
+#define TEST_RR_ZEROSRC1( testnum, inst, result, val ) \
+    TEST_CASE( testnum, x2, result, \
+      li x1, MASK_XLEN(val); \
+      inst x2, x0, x1; \
+    )
+
+#define TEST_RR_ZEROSRC2( testnum, inst, result, val ) \
+    TEST_CASE( testnum, x2, result, \
+      li x1, MASK_XLEN(val); \
+      inst x2, x1, x0; \
+    )
+
+#define TEST_RR_ZEROSRC12( testnum, inst, result ) \
+    TEST_CASE( testnum, x1, result, \
+      inst x1, x0, x0; \
+    )
+
+#define TEST_RR_ZERODEST( testnum, inst, val1, val2 ) \
+    TEST_CASE( testnum, x0, 0, \
+      li x1, MASK_XLEN(val1); \
+      li x2, MASK_XLEN(val2); \
+      inst x0, x1, x2; \
+    )
+
+#-----------------------------------------------------------------------
+# Test memory instructions
+#-----------------------------------------------------------------------
+
+#define TEST_LD_OP( testnum, inst, result, offset, base ) \
+    TEST_CASE( testnum, x14, result, \
+      la  x1, base; \
+      inst x14, offset(x1); \
+    )
+
+#define TEST_ST_OP( testnum, load_inst, store_inst, result, offset, base ) \
+    TEST_CASE( testnum, x14, result, \
+      la  x1, base; \
+      li  x2, result; \
+      store_inst x2, offset(x1); \
+      load_inst x14, offset(x1); \
+    )
+
+#define TEST_LD_DEST_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \
+test_ ## testnum: \
+    li  TESTNUM, testnum; \
+    li  x4, 0; \
+1:  la  x1, base; \
+    inst x14, offset(x1); \
+    TEST_INSERT_NOPS_ ## nop_cycles \
+    addi  x6, x14, 0; \
+    li  x7, result; \
+    bne x6, x7, fail; \
+    addi  x4, x4, 1; \
+    li  x5, 2; \
+    bne x4, x5, 1b; \
+
+#define TEST_LD_SRC1_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \
+test_ ## testnum: \
+    li  TESTNUM, testnum; \
+    li  x4, 0; \
+1:  la  x1, base; \
+    TEST_INSERT_NOPS_ ## nop_cycles \
+    inst x14, offset(x1); \
+    li  x7, result; \
+    bne x14, x7, fail; \
+    addi  x4, x4, 1; \
+    li  x5, 2; \
+    bne x4, x5, 1b \
+
+#define TEST_ST_SRC12_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \
+test_ ## testnum: \
+    li  TESTNUM, testnum; \
+    li  x4, 0; \
+1:  li  x1, result; \
+    TEST_INSERT_NOPS_ ## src1_nops \
+    la  x2, base; \
+    TEST_INSERT_NOPS_ ## src2_nops \
+    store_inst x1, offset(x2); \
+    load_inst x14, offset(x2); \
+    li  x7, result; \
+    bne x14, x7, fail; \
+    addi  x4, x4, 1; \
+    li  x5, 2; \
+    bne x4, x5, 1b \
+
+#define TEST_ST_SRC21_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \
+test_ ## testnum: \
+    li  TESTNUM, testnum; \
+    li  x4, 0; \
+1:  la  x2, base; \
+    TEST_INSERT_NOPS_ ## src1_nops \
+    li  x1, result; \
+    TEST_INSERT_NOPS_ ## src2_nops \
+    store_inst x1, offset(x2); \
+    load_inst x14, offset(x2); \
+    li  x7, result; \
+    bne x14, x7, fail; \
+    addi  x4, x4, 1; \
+    li  x5, 2; \
+    bne x4, x5, 1b \
+
+#define TEST_BR2_OP_TAKEN( testnum, inst, val1, val2 ) \
+test_ ## testnum: \
+    li  TESTNUM, testnum; \
+    li  x1, val1; \
+    li  x2, val2; \
+    inst x1, x2, 2f; \
+    bne x0, TESTNUM, fail; \
+1:  bne x0, TESTNUM, 3f; \
+2:  inst x1, x2, 1b; \
+    bne x0, TESTNUM, fail; \
+3:
+
+#define TEST_BR2_OP_NOTTAKEN( testnum, inst, val1, val2 ) \
+test_ ## testnum: \
+    li  TESTNUM, testnum; \
+    li  x1, val1; \
+    li  x2, val2; \
+    inst x1, x2, 1f; \
+    bne x0, TESTNUM, 2f; \
+1:  bne x0, TESTNUM, fail; \
+2:  inst x1, x2, 1b; \
+3:
+
+#define TEST_BR2_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
+test_ ## testnum: \
+    li  TESTNUM, testnum; \
+    li  x4, 0; \
+1:  li  x1, val1; \
+    TEST_INSERT_NOPS_ ## src1_nops \
+    li  x2, val2; \
+    TEST_INSERT_NOPS_ ## src2_nops \
+    inst x1, x2, fail; \
+    addi  x4, x4, 1; \
+    li  x5, 2; \
+    bne x4, x5, 1b \
+
+#define TEST_BR2_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \
+test_ ## testnum: \
+    li  TESTNUM, testnum; \
+    li  x4, 0; \
+1:  li  x2, val2; \
+    TEST_INSERT_NOPS_ ## src1_nops \
+    li  x1, val1; \
+    TEST_INSERT_NOPS_ ## src2_nops \
+    inst x1, x2, fail; \
+    addi  x4, x4, 1; \
+    li  x5, 2; \
+    bne x4, x5, 1b \
+
+#-----------------------------------------------------------------------
+# Test jump instructions
+#-----------------------------------------------------------------------
+
+#define TEST_JR_SRC1_BYPASS( testnum, nop_cycles, inst ) \
+test_ ## testnum: \
+    li  TESTNUM, testnum; \
+    li  x4, 0; \
+1:  la  x6, 2f; \
+    TEST_INSERT_NOPS_ ## nop_cycles \
+    inst x6; \
+    bne x0, TESTNUM, fail; \
+2:  addi  x4, x4, 1; \
+    li  x5, 2; \
+    bne x4, x5, 1b \
+
+#define TEST_JALR_SRC1_BYPASS( testnum, nop_cycles, inst ) \
+test_ ## testnum: \
+    li  TESTNUM, testnum; \
+    li  x4, 0; \
+1:  la  x6, 2f; \
+    TEST_INSERT_NOPS_ ## nop_cycles \
+    inst x13, x6, 0; \
+    bne x0, TESTNUM, fail; \
+2:  addi  x4, x4, 1; \
+    li  x5, 2; \
+    bne x4, x5, 1b \
+
+
+#-----------------------------------------------------------------------
+# RV64UF MACROS
+#-----------------------------------------------------------------------
+
+#-----------------------------------------------------------------------
+# Tests floating-point instructions
+#-----------------------------------------------------------------------
+
+#define qNaNf 0f:7fc00000
+#define sNaNf 0f:7f800001
+#define qNaN 0d:7ff8000000000000
+#define sNaN 0d:7ff0000000000001
+
+#define TEST_FP_OP_S_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
+test_ ## testnum: \
+  li  TESTNUM, testnum; \
+  la  a0, test_ ## testnum ## _data ;\
+  flw f0, 0(a0); \
+  flw f1, 4(a0); \
+  flw f2, 8(a0); \
+  lw  a3, 12(a0); \
+  code; \
+  fsflags a1, x0; \
+  li a2, flags; \
+  bne a0, a3, fail; \
+  bne a1, a2, fail; \
+  .pushsection .data; \
+  .align 2; \
+  test_ ## testnum ## _data: \
+  .float val1; \
+  .float val2; \
+  .float val3; \
+  .result; \
+  .popsection
+
+#define TEST_FP_OP_D_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
+test_ ## testnum: \
+  li  TESTNUM, testnum; \
+  la  a0, test_ ## testnum ## _data ;\
+  fld f0, 0(a0); \
+  fld f1, 8(a0); \
+  fld f2, 16(a0); \
+  ld  a3, 24(a0); \
+  code; \
+  fsflags a1, x0; \
+  li a2, flags; \
+  bne a0, a3, fail; \
+  bne a1, a2, fail; \
+  .pushsection .data; \
+  .align 3; \
+  test_ ## testnum ## _data: \
+  .double val1; \
+  .double val2; \
+  .double val3; \
+  .result; \
+  .popsection
+
+// TODO: assign a separate mem location for the comparison address?
+#define TEST_FP_OP_D32_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
+test_ ## testnum: \
+  li  TESTNUM, testnum; \
+  la  a0, test_ ## testnum ## _data ;\
+  fld f0, 0(a0); \
+  fld f1, 8(a0); \
+  fld f2, 16(a0); \
+  lw  a3, 24(a0); \
+  lw  t1, 28(a0); \
+  code; \
+  fsflags a1, x0; \
+  li a2, flags; \
+  bne a0, a3, fail; \
+  bne t1, t2, fail; \
+  bne a1, a2, fail; \
+  .pushsection .data; \
+  .align 3; \
+  test_ ## testnum ## _data: \
+  .double val1; \
+  .double val2; \
+  .double val3; \
+  .result; \
+  .popsection
+
+#define TEST_FCVT_S_D32( testnum, result, val1 ) \
+  TEST_FP_OP_D32_INTERNAL( testnum, 0, double result, val1, 0.0, 0.0, \
+                    fcvt.s.d f3, f0; fcvt.d.s f3, f3; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
+
+#define TEST_FCVT_S_D( testnum, result, val1 ) \
+  TEST_FP_OP_D_INTERNAL( testnum, 0, double result, val1, 0.0, 0.0, \
+                    fcvt.s.d f3, f0; fcvt.d.s f3, f3; fmv.x.d a0, f3)
+
+#define TEST_FCVT_D_S( testnum, result, val1 ) \
+  TEST_FP_OP_S_INTERNAL( testnum, 0, float result, val1, 0.0, 0.0, \
+                    fcvt.d.s f3, f0; fcvt.s.d f3, f3; fmv.x.s a0, f3)
+
+#define TEST_FP_OP1_S( testnum, inst, flags, result, val1 ) \
+  TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, 0.0, 0.0, \
+                    inst f3, f0; fmv.x.s a0, f3)
+
+#define TEST_FP_OP1_D32( testnum, inst, flags, result, val1 ) \
+  TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, val1, 0.0, 0.0, \
+                    inst f3, f0; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
+// ^: store computation result in address from a0, load high-word into t2
+
+#define TEST_FP_OP1_D( testnum, inst, flags, result, val1 ) \
+  TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, 0.0, 0.0, \
+                    inst f3, f0; fmv.x.d a0, f3)
+
+#define TEST_FP_OP1_S_DWORD_RESULT( testnum, inst, flags, result, val1 ) \
+  TEST_FP_OP_S_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
+                    inst f3, f0; fmv.x.s a0, f3)
+
+#define TEST_FP_OP1_D32_DWORD_RESULT( testnum, inst, flags, result, val1 ) \
+  TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
+                    inst f3, f0; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
+// ^: store computation result in address from a0, load high-word into t2
+
+#define TEST_FP_OP1_D_DWORD_RESULT( testnum, inst, flags, result, val1 ) \
+  TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
+                    inst f3, f0; fmv.x.d a0, f3)
+
+#define TEST_FP_OP2_S( testnum, inst, flags, result, val1, val2 ) \
+  TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, 0.0, \
+                    inst f3, f0, f1; fmv.x.s a0, f3)
+
+#define TEST_FP_OP2_D32( testnum, inst, flags, result, val1, val2 ) \
+  TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, val1, val2, 0.0, \
+                    inst f3, f0, f1; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
+// ^: store computation result in address from a0, load high-word into t2
+
+#define TEST_FP_OP2_D( testnum, inst, flags, result, val1, val2 ) \
+  TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, val2, 0.0, \
+                    inst f3, f0, f1; fmv.x.d a0, f3)
+
+#define TEST_FP_OP3_S( testnum, inst, flags, result, val1, val2, val3 ) \
+  TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, val3, \
+                    inst f3, f0, f1, f2; fmv.x.s a0, f3)
+
+#define TEST_FP_OP3_D32( testnum, inst, flags, result, val1, val2, val3 ) \
+  TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, val1, val2, val3, \
+                    inst f3, f0, f1, f2; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0))
+// ^: store computation result in address from a0, load high-word into t2
+
+#define TEST_FP_OP3_D( testnum, inst, flags, result, val1, val2, val3 ) \
+  TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, val2, val3, \
+                    inst f3, f0, f1, f2; fmv.x.d a0, f3)
+
+#define TEST_FP_INT_OP_S( testnum, inst, flags, result, val1, rm ) \
+  TEST_FP_OP_S_INTERNAL( testnum, flags, word result, val1, 0.0, 0.0, \
+                    inst a0, f0, rm)
+
+#define TEST_FP_INT_OP_D32( testnum, inst, flags, result, val1, rm ) \
+  TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
+                    inst a0, f0, f1; li t2, 0)
+
+#define TEST_FP_INT_OP_D( testnum, inst, flags, result, val1, rm ) \
+  TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
+                    inst a0, f0, rm)
+
+#define TEST_FP_CMP_OP_S( testnum, inst, flags, result, val1, val2 ) \
+  TEST_FP_OP_S_INTERNAL( testnum, flags, word result, val1, val2, 0.0, \
+                    inst a0, f0, f1)
+
+#define TEST_FP_CMP_OP_D32( testnum, inst, flags, result, val1, val2 ) \
+  TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, val1, val2, 0.0, \
+                    inst a0, f0, f1; li t2, 0)
+
+#define TEST_FP_CMP_OP_D( testnum, inst, flags, result, val1, val2 ) \
+  TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, val2, 0.0, \
+                    inst a0, f0, f1)
+
+#define TEST_FCLASS_S(testnum, correct, input) \
+  TEST_CASE(testnum, a0, correct, li a0, input; fmv.s.x fa0, a0; \
+                    fclass.s a0, fa0)
+
+#define TEST_FCLASS_D32(testnum, correct, input) \
+  TEST_CASE(testnum, a0, correct, \
+            la a0, test_ ## testnum ## _data ;\
+            fld fa0, 0(a0); \
+            fclass.d a0, fa0) \
+    .pushsection .data; \
+    .align 3; \
+    test_ ## testnum ## _data: \
+    .dword input; \
+    .popsection
+
+#define TEST_FCLASS_D(testnum, correct, input) \
+  TEST_CASE(testnum, a0, correct, li a0, input; fmv.d.x fa0, a0; \
+                    fclass.d a0, fa0)
+
+#define TEST_INT_FP_OP_S( testnum, inst, result, val1 ) \
+test_ ## testnum: \
+  li  TESTNUM, testnum; \
+  la  a0, test_ ## testnum ## _data ;\
+  lw  a3, 0(a0); \
+  li  a0, val1; \
+  inst f0, a0; \
+  fsflags x0; \
+  fmv.x.s a0, f0; \
+  bne a0, a3, fail; \
+  .pushsection .data; \
+  .align 2; \
+  test_ ## testnum ## _data: \
+  .float result; \
+  .popsection
+
+#define TEST_INT_FP_OP_D32( testnum, inst, result, val1 ) \
+test_ ## testnum: \
+  li  TESTNUM, testnum; \
+  la  a0, test_ ## testnum ## _data ;\
+  lw  a3, 0(a0); \
+  lw  a4, 4(a0); \
+  li  a1, val1; \
+  inst f0, a1; \
+  \
+  fsd f0, 0(a0); \
+  lw a1, 4(a0); \
+  lw a0, 0(a0); \
+  \
+  fsflags x0; \
+  bne a0, a3, fail; \
+  bne a1, a4, fail; \
+  .pushsection .data; \
+  .align 3; \
+  test_ ## testnum ## _data: \
+  .double result; \
+  .popsection
+
+#define TEST_INT_FP_OP_D( testnum, inst, result, val1 ) \
+test_ ## testnum: \
+  li  TESTNUM, testnum; \
+  la  a0, test_ ## testnum ## _data ;\
+  ld  a3, 0(a0); \
+  li  a0, val1; \
+  inst f0, a0; \
+  fsflags x0; \
+  fmv.x.d a0, f0; \
+  bne a0, a3, fail; \
+  .pushsection .data; \
+  .align 3; \
+  test_ ## testnum ## _data: \
+  .double result; \
+  .popsection
+
+// We need some special handling here to allow 64-bit comparison in 32-bit arch
+// TODO: find a better name and clean up when intended for general usage?
+#define TEST_CASE_D32( testnum, testreg1, testreg2, correctval, code... ) \
+test_ ## testnum: \
+    code; \
+    la  x15, test_ ## testnum ## _data ; \
+    lw  x7, 0(x15); \
+    lw  x15, 4(x15); \
+    li  TESTNUM, testnum; \
+    bne testreg1, x7, fail;\
+    bne testreg2, x15, fail;\
+    .pushsection .data; \
+    .align 3; \
+    test_ ## testnum ## _data: \
+    .dword correctval; \
+    .popsection
+
+// ^ x14 is used in some other macros, to avoid issues we use x15 for upper word
+
+#-----------------------------------------------------------------------
+# Pass and fail code (assumes test num is in TESTNUM)
+#-----------------------------------------------------------------------
+
+#define TEST_PASSFAIL \
+        bne x0, TESTNUM, pass; \
+fail: \
+        RVTEST_FAIL; \
+pass: \
+        RVTEST_PASS \
+
+
+#-----------------------------------------------------------------------
+# Test data section
+#-----------------------------------------------------------------------
+
+#define TEST_DATA
+
+#endif
diff --git a/apps/riscv-tests/isa/macros/vector/dataset.h b/apps/riscv-tests/isa/macros/vector/dataset.h
new file mode 100644
index 0000000..cfad940
--- /dev/null
+++ b/apps/riscv-tests/isa/macros/vector/dataset.h
@@ -0,0 +1,48 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+
+#ifndef __DATASET_H__
+#define __DATASET_H__
+
+#define SIZE 1024
+#define L_SIZE 1024
+
+static volatile uint64_t Au64[SIZE] __attribute__((aligned(128)));
+static volatile uint32_t Au32[SIZE] __attribute__((aligned(128)));
+static volatile uint16_t Au16[SIZE] __attribute__((aligned(128)));
+static volatile uint8_t  Au8 [SIZE] __attribute__((aligned(128)));
+static volatile int64_t  Ai64[SIZE] __attribute__((aligned(128)));
+static volatile int32_t  Ai32[SIZE] __attribute__((aligned(128)));
+static volatile int16_t  Ai16[SIZE] __attribute__((aligned(128)));
+static volatile int8_t   Ai8 [SIZE] __attribute__((aligned(128)));
+static volatile uint64_t Af64[SIZE] __attribute__((aligned(128)));
+static volatile uint32_t Af32[SIZE] __attribute__((aligned(128)));
+static volatile uint16_t Af16[SIZE] __attribute__((aligned(128)));
+
+static volatile uint64_t Ru64[SIZE] __attribute__((aligned(128)));
+static volatile uint32_t Ru32[SIZE] __attribute__((aligned(128)));
+static volatile uint16_t Ru16[SIZE] __attribute__((aligned(128)));
+static volatile uint8_t  Ru8 [SIZE] __attribute__((aligned(128)));
+static volatile int64_t  Ri64[SIZE] __attribute__((aligned(128)));
+static volatile int32_t  Ri32[SIZE] __attribute__((aligned(128)));
+static volatile int16_t  Ri16[SIZE] __attribute__((aligned(128)));
+static volatile int8_t   Ri8 [SIZE] __attribute__((aligned(128)));
+static volatile uint64_t Rf64[SIZE] __attribute__((aligned(128)));
+static volatile uint32_t Rf32[SIZE] __attribute__((aligned(128)));
+static volatile uint16_t Rf16[SIZE] __attribute__((aligned(128)));
+
+static volatile uint64_t Lu64[L_SIZE] __attribute__((aligned(128)));
+static volatile uint32_t Lu32[L_SIZE] __attribute__((aligned(128)));
+static volatile uint16_t Lu16[L_SIZE] __attribute__((aligned(128)));
+static volatile uint8_t  Lu8 [L_SIZE] __attribute__((aligned(128)));
+
+static volatile uint64_t Xf64[1] __attribute__((aligned(128)));
+static volatile uint32_t Xf32[1] __attribute__((aligned(128)));
+static volatile uint16_t Xf16[1] __attribute__((aligned(128)));
+
+#undef SIZE
+
+#endif  // __DATASET__H__
diff --git a/apps/riscv-tests/isa/macros/vector/float_conversion.h b/apps/riscv-tests/isa/macros/vector/float_conversion.h
new file mode 100644
index 0000000..d0f5586
--- /dev/null
+++ b/apps/riscv-tests/isa/macros/vector/float_conversion.h
@@ -0,0 +1,133 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+
+typedef union {
+  uint64_t i;
+  uint16_t h;
+  float    f;
+  double   d;
+} v_fconv;
+
+static inline v_fconv _i(uint64_t i) {
+  v_fconv r;
+  r.i   = i;
+  return  r;
+}
+
+static inline v_fconv _h(float f) {
+  /*Copyright (c) 2005-2021, NumPy Developers.
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without
+    modification, are permitted provided that the following conditions are
+    met:
+
+    * Redistributions of source code must retain the above copyright
+    notice, this list of conditions and the following disclaimer.
+
+    * Redistributions in binary form must reproduce the above
+    copyright notice, this list of conditions and the following
+    disclaimer in the documentation and/or other materials provided
+    with the distribution.
+
+    * Neither the name of the NumPy Developers nor the names of any
+    contributors may be used to endorse or promote products derived
+    from this software without specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+    "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+    LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+    A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+    OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+    SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+    LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+    DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+    THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+    (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+    OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.*/
+
+  // Source: https://github.com/numpy/numpy/blob/master/numpy/core/src/npymath/halffloat.c
+
+  v_fconv r;
+  r.f = f;
+
+  uint32_t f_exp, f_sig;
+  uint16_t h_sgn, h_exp, h_sig;
+
+  h_sgn = (uint16_t) ((r.i&0x80000000u) >> 16);
+  f_exp = (r.i&0x7f800000u);
+
+  /* Exponent overflow/NaN converts to signed inf/NaN */
+  if (f_exp >= 0x47800000u) {
+    if (f_exp == 0x7f800000u) {
+      /* Inf or NaN */
+      f_sig = (r.i&0x007fffffu);
+      if (f_sig != 0) {
+        /* NaN - propagate the flag in the significand... */
+        uint16_t ret = (uint16_t) (0x7c00u + (f_sig >> 13));
+        /* ...but make sure it stays a NaN */
+        if (ret == 0x7c00u) {
+          ret++;
+        }
+        r.i = (uint16_t) h_sgn + ret;
+        return r;
+      } else {
+        /* signed inf */
+        r.i = (uint16_t) (h_sgn + 0x7c00u);
+        return r;
+      }
+    } else {
+      r.i = (uint16_t) (h_sgn + 0x7c00u);
+      return r;
+    }
+  }
+
+  /* Exponent underflow converts to a subnormal half or signed zero */
+  if (f_exp <= 0x38000000u) {
+    /*
+     * Signed zeros, subnormal floats, and floats with small
+     * exponents all convert to signed zero half-floats.
+     */
+    if (f_exp < 0x33000000u) {
+      r.i = h_sgn;
+      return r;
+    }
+    /* Make the subnormal significand */
+    f_exp >>= 23;
+    f_sig = (0x00800000u + (r.i&0x007fffffu));
+    f_sig >>= (113 - f_exp);
+    f_sig += 0x00001000u;
+    h_sig = (uint16_t) (f_sig >> 13);
+    /*
+     * If the rounding causes a bit to spill into h_exp, it will
+     * increment h_exp from zero to one and h_sig will be zero.
+     * This is the correct result.
+     */
+    r.i = (uint16_t) (h_sgn + h_sig);
+    return r;
+  }
+
+  /* Regular case with no overflow or underflow */
+  h_exp = (uint16_t) ((f_exp - 0x38000000u) >> 13);
+  /* Handle rounding by adding 1 to the bit beyond half precision */
+  f_sig = (r.i&0x007fffffu);
+  f_sig += 0x00001000u;
+  h_sig = (uint16_t) (f_sig >> 13);
+  r.i = (uint16_t) h_sgn + h_exp + h_sig;
+  return  r;
+}
+
+static inline v_fconv _f(float f) {
+  v_fconv r;
+  r.f   = f;
+  return  r;
+}
+
+static inline v_fconv _d(double d) {
+  v_fconv r;
+  r.d   = d;
+  return  r;
+}
diff --git a/apps/riscv-tests/isa/macros/vector/float_macros.h b/apps/riscv-tests/isa/macros/vector/float_macros.h
new file mode 100644
index 0000000..ceb6df6
--- /dev/null
+++ b/apps/riscv-tests/isa/macros/vector/float_macros.h
@@ -0,0 +1,159 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Matteo Perotti <mperotti@iis.ee.ethz.ch>
+
+#ifndef __FLOAT_MACROS_H__
+#define __FLOAT_MACROS_H__
+
+#include <stdint.h>
+
+// Zero encoding is common to all the formats
+#define pZero  0x0
+
+// 16-bit IEEE 754 floats
+#define qNaNh  0x7e00
+#define sNaNh  0x7c01
+#define pInfh  0x7c00
+#define mInfh  0xfc00
+#define pMaxh  0x7bff
+#define mMaxh  0xfbff
+#define mZeroh 0x8000
+
+// 32-bit IEEE 754 floats
+#define qNaNf  0x7fc00000
+#define sNaNf  0x7f800001
+#define pInff  0x7f800000
+#define mInff  0xff800000
+#define pMaxf  0x7f7fffff
+#define mMaxf  0xff7fffff
+#define mZerof 0x80000000
+
+// 64-bit IEEE 754 floats
+#define qNaNd  0x7ff8000000000000
+#define sNaNd  0x7ff0000000000001
+#define pInfd  0x7ff0000000000000
+#define mInfd  0xfff0000000000000
+#define pMaxd  0x7fefffffffffffff
+#define mMaxd  0xffefffffffffffff
+#define mZerod 0x8000000000000000
+
+// Fflags
+#define NV 0b10000 // Invalid Operation (e.g. Inf - Inf, or 0/0)
+#define DZ 0b01000 // Divide by Zero    (e.g. x/0, x != 0)
+#define OF 0b00100 // Overflow          (e.g. pMaxf + pMaxf)
+#define UF 0b00010 // Underflow         (e.g. pMinf/3)
+#define NX 0b00001 // Inexact           (e.g. 2/3)
+
+// MSTATUS.FS helpers
+#define MSTATUS_FS_MASK  0x6000
+#define MSTATUS_FS_INIT  0x2000
+#define MSTATUS_FS_CLEAN 0x4000
+#define MSTATUS_FS_DIRTY 0x6000
+
+// Rounding Mode in fcsr
+#define RM_RNE 0x0
+#define RM_RTZ 0x1
+#define RM_RDN 0x2
+#define RM_RUP 0x3
+#define RM_RMM 0x4
+
+// vfclass output
+#define CLASS_mInf  0x001
+#define CLASS_mNorm 0x002
+#define CLASS_mSub  0x004
+#define CLASS_mZero 0x008
+#define CLASS_pZero 0x010
+#define CLASS_pSub  0x020
+#define CLASS_pNorm 0x040
+#define CLASS_pInf  0x080
+#define CLASS_sNAN  0x100
+#define CLASS_qNAN  0x200
+
+typedef union double_hex {
+  double      d;
+  uint64_t ui64;
+} double_hex;
+
+// Check fcsr.fflags against an expected FFLAGS value
+#define CHECK_FFLAGS(FFLAGS)                                                                             \
+  do {                                                                                                   \
+    uint64_t gold_ff = FFLAGS;                                                                           \
+    uint64_t      ff;                                                                                    \
+    asm volatile ("frflags %0" : "=r" (ff));                                                             \
+    if (ff != gold_ff) {                                                                                 \
+      printf("fflags check FAILED. Current fflags is 0x%02lx, while expecting 0x%02lx.\n", ff, gold_ff); \
+      num_failed++;                                                                                      \
+      return;                                                                                            \
+    }                                                                                                    \
+  } while(0)
+
+// Change rounding-mode
+#define CHANGE_RM(NEW_RM)                                                                              \
+  do {                                                                                                 \
+    asm volatile ("fsrm %0" :: "r" (NEW_RM));                                                          \
+  } while(0)
+
+// Check fcsr.fflags against an expected FFLAGS value
+#define CLEAR_FFLAGS asm volatile ("fsflags %0" :: "r" (0))
+
+// !!!!! mstatus is not accessible in user-mode !!!!!
+// Make mstatus.FS Clean
+#define CLEAR_FS                                                                                                                                  \
+  do {                                                                                                                                            \
+    uint64_t old_mstatus;                                                                                                                         \
+    uint64_t new_mstatus;                                                                                                                         \
+    asm volatile ("csrrs %0, mstatus, x0" : "=r"  (old_mstatus));                                                                                 \
+    new_mstatus = old_mstatus & ~((uint64_t) MSTATUS_FS_MASK);                                                                                    \
+    new_mstatus |= MSTATUS_FS_CLEAN;                                                                                                              \
+    asm volatile ("csrrw x0, mstatus, %0" :: "r" (new_mstatus));                                                                                  \
+  } while(0)
+// Check if mstatus.FS is Clean
+#define CHECK_FS_CLEAN                                                                                                                            \
+  do {                                                                                                                                            \
+    uint64_t fs;                                                                                                                                  \
+    asm volatile ("csrrs %0, mstatus, x0" : "=r" (fs));                                                                                           \
+    if ((fs & MSTATUS_FS_MASK) != MSTATUS_FS_CLEAN) {                                                                                             \
+      printf("mstatus.FS check FAILED. Current mstatus.FS is 0x%02x, while expecting 0x%02x (Clean).\n", fs & MSTATUS_FS_MASK, MSTATUS_FS_CLEAN); \
+      num_failed++;                                                                                                                               \
+      return;                                                                                                                                     \
+    }                                                                                                                                             \
+  } while(0)
+// Check if mstatus.FS is Dirty
+#define CHECK_FS_DIRTY                                                                                                                            \
+  do {                                                                                                                                            \
+    uint64_t fs;                                                                                                                                  \
+    asm volatile ("csrrs %0, mstatus, x0" : "=r" (fs));                                                                                           \
+    if ((fs & MSTATUS_FS_MASK) != MSTATUS_FS_DIRTY) {                                                                                             \
+      printf("mstatus.FS check FAILED. Current mstatus.FS is 0x%02x, while expecting 0x%02x (Dirty).\n", fs & MSTATUS_FS_MASK, MSTATUS_FS_DIRTY); \
+      num_failed++;                                                                                                                               \
+      return;                                                                                                                                     \
+    }                                                                                                                                             \
+  } while(0)
+
+// NaN-Box a 16-bit IEEE 754 half float in a 64-bit double
+// This is useful if we want to specify the IEEE 754 encoding of a floating-point variable
+#define BOX_HALF_IN_DOUBLE(VAR_NAME, VAL_16B)                             \
+  do {                                                                    \
+    double_hex nan_boxed_val;                                             \
+    nan_boxed_val.ui64 = ((uint64_t) 0xffffffffffff << 16) | VAL_16B;     \
+    VAR_NAME = nan_boxed_val.d;                                           \
+  } while(0)
+
+#define BOX_FLOAT_IN_DOUBLE(VAR_NAME, VAL_32B)                        \
+  do {                                                                \
+    double_hex nan_boxed_val;                                         \
+    nan_boxed_val.ui64 = ((uint64_t) 0xffffffff << 32) | VAL_32B;     \
+    VAR_NAME = nan_boxed_val.d;                                       \
+  } while(0)
+
+#define BOX_DOUBLE_IN_DOUBLE(VAR_NAME, VAL_64B) \
+  do {                                          \
+    double_hex nan_boxed_val;                   \
+    nan_boxed_val.ui64 = VAL_64B;               \
+    VAR_NAME = nan_boxed_val.d;                 \
+  } while(0)
+
+#endif // __FLOAT_MACROS_H__
diff --git a/apps/riscv-tests/isa/macros/vector/long_array.h b/apps/riscv-tests/isa/macros/vector/long_array.h
new file mode 100644
index 0000000..fb76918
--- /dev/null
+++ b/apps/riscv-tests/isa/macros/vector/long_array.h
@@ -0,0 +1,722 @@
+#include "vector_macros.h"
+#define AXI_DWIDTH 128
+static volatile uint8_t LONG_I8[1024] __attribute__((aligned(AXI_DWIDTH))) = {
+    0x2a, 0xbb, 0x34, 0xad, 0x40, 0x13, 0x8e, 0xf1, 0xf8, 0xe3, 0xac, 0x97,
+    0x2b, 0xb2, 0x16, 0x44, 0x78, 0x75, 0x1a, 0xc7, 0x48, 0x84, 0x67, 0xce,
+    0x8b, 0x6f, 0x0b, 0xcc, 0xb6, 0x3f, 0x8d, 0x81, 0x6f, 0xde, 0x87, 0xb9,
+    0x82, 0x67, 0x3c, 0xff, 0x71, 0xce, 0x25, 0xbd, 0x74, 0x86, 0x8f, 0x4e,
+    0xb1, 0x77, 0xf6, 0x82, 0x2f, 0x34, 0xcf, 0x13, 0xec, 0xba, 0x38, 0x11,
+    0xba, 0x67, 0xe9, 0xe6, 0x62, 0x74, 0xb1, 0x92, 0x9f, 0x30, 0xc7, 0x95,
+    0x4a, 0xd7, 0x33, 0x38, 0x21, 0xd4, 0xb6, 0xb8, 0xfa, 0xfa, 0xc5, 0x2a,
+    0xfd, 0x97, 0x69, 0x3c, 0x4b, 0x64, 0x0d, 0x1d, 0x5f, 0x0d, 0x12, 0xb9,
+    0x9a, 0x6c, 0xfb, 0x1e, 0xcc, 0x25, 0x2f, 0xe6, 0x1e, 0x2,  0x1d, 0x2,
+    0x2d, 0x8b, 0x32, 0x5d, 0x1d, 0x2b, 0xe5, 0x1e, 0x1c, 0x64, 0x5f, 0xb6,
+    0xcd, 0x4,  0x2e, 0xe2, 0x6d, 0x3d, 0xb4, 0xc5, 0xae, 0x9,  0x6b, 0xaf,
+    0x74, 0x60, 0xba, 0x7a, 0x8b, 0x79, 0xa0, 0xd0, 0xef, 0x21, 0xce, 0xeb,
+    0xa6, 0xb2, 0xb8, 0x6b, 0xf9, 0x71, 0xea, 0x85, 0xc1, 0xb9, 0xa3, 0x7c,
+    0xf1, 0x6c, 0x8c, 0x4f, 0xb6, 0x81, 0x96, 0xf8, 0xe7, 0xc7, 0xfa, 0x71,
+    0x2e, 0x9c, 0x65, 0xe6, 0x83, 0xfc, 0xa9, 0xaf, 0x45, 0x20, 0x17, 0x4f,
+    0xc6, 0xba, 0x5a, 0x0e, 0xb9, 0xc6, 0x2d, 0xdc, 0xb8, 0x82, 0x5c, 0x8a,
+    0xca, 0x13, 0x8f, 0xc3, 0xad, 0xd9, 0xd9, 0x22, 0x79, 0x34, 0x32, 0xa7,
+    0x81, 0xf1, 0x4d, 0x83, 0x0d, 0x27, 0xaa, 0xbf, 0xdc, 0x86, 0x7f, 0x24,
+    0x73, 0x1e, 0x1a, 0xdb, 0x19, 0x8f, 0x16, 0x5a, 0x3b, 0xdc, 0x8f, 0x1b,
+    0x9f, 0x38, 0xa7, 0x31, 0x23, 0xc7, 0x29, 0xfe, 0x9b, 0xb9, 0x58, 0x42,
+    0x94, 0xdb, 0x2c, 0x34, 0x9e, 0x6d, 0x42, 0x46, 0xde, 0x60, 0x22, 0xdb,
+    0x9c, 0x2f, 0x0,  0xc8, 0x1e, 0x97, 0xf4, 0xb8, 0x18, 0xd4, 0xd8, 0x67,
+    0x15, 0x3f, 0x29, 0x8f, 0x4f, 0xe1, 0x77, 0x23, 0xc1, 0xdc, 0x2e, 0x73,
+    0xcb, 0xdf, 0xf5, 0xc0, 0x19, 0x32, 0xb7, 0xbf, 0x70, 0xf9, 0xe8, 0xe3,
+    0xf5, 0x2c, 0x31, 0x98, 0x64, 0x5,  0x0b, 0x3e, 0xcd, 0x5f, 0xb6, 0x51,
+    0x8d, 0x5d, 0xbc, 0x5b, 0x87, 0xfe, 0xb3, 0x89, 0xd4, 0x9d, 0x9,  0x10,
+    0xb7, 0x62, 0x79, 0x82, 0xb9, 0x30, 0xa9, 0x43, 0xaa, 0x0d, 0xfc, 0xef,
+    0xd7, 0xec, 0xaa, 0x46, 0x14, 0xd3, 0xa8, 0x22, 0x91, 0xb8, 0xde, 0x6c,
+    0xfc, 0x6a, 0x2b, 0xc4, 0x96, 0x11, 0x47, 0x4b, 0xdf, 0x9d, 0xfb, 0xda,
+    0xc1, 0xfa, 0x4b, 0x48, 0x69, 0x5b, 0x9a, 0x6b, 0xf4, 0x33, 0xaf, 0xfd,
+    0x61, 0x7,  0x8b, 0x59, 0x6c, 0xc0, 0x9e, 0xc9, 0xa1, 0x0,  0x58, 0x5f,
+    0xa2, 0x69, 0x9c, 0x35, 0x19, 0x0e, 0x54, 0x5a, 0xba, 0x23, 0x1b, 0x0,
+    0xa8, 0x58, 0xac, 0xd1, 0x5f, 0x85, 0xc3, 0x0b, 0x9d, 0xe9, 0x22, 0x17,
+    0x62, 0xf0, 0x4,  0xb3, 0xa8, 0x89, 0xf0, 0x68, 0x69, 0xff, 0x2f, 0x99,
+    0x0d, 0xdb, 0x8e, 0x12, 0xea, 0x2f, 0x5a, 0xd2, 0xfd, 0xe6, 0x7d, 0x97,
+    0xcd, 0xe0, 0xa8, 0xd9, 0xcf, 0xc7, 0x1e, 0x5e, 0x73, 0x5,  0x5c, 0x15,
+    0xc7, 0x99, 0x6e, 0x51, 0x81, 0x55, 0x49, 0x95, 0xcf, 0xdf, 0x80, 0x4e,
+    0xb1, 0x34, 0x81, 0x91, 0x7f, 0xa2, 0x13, 0xf3, 0xc0, 0xa4, 0x2,  0x81,
+    0xd8, 0xde, 0xd1, 0xbf, 0xc1, 0xb9, 0x0f, 0x6d, 0x5b, 0x3b, 0xf3, 0xfe,
+    0xc6, 0xca, 0x48, 0xad, 0xcb, 0x39, 0xea, 0x12, 0x4e, 0x70, 0x5b, 0x24,
+    0x2e, 0x36, 0xb2, 0xf2, 0x9c, 0x7e, 0xf6, 0x0b, 0x5e, 0xb3, 0x26, 0x77,
+    0x96, 0xa9, 0x1,  0x48, 0x23, 0x11, 0x9c, 0xc4, 0x36, 0x37, 0x5b, 0xd8,
+    0xfb, 0xeb, 0x9a, 0x99, 0xf2, 0xb6, 0xe1, 0xbe, 0x1,  0x9a, 0x7c, 0x58,
+    0x33, 0xa2, 0x79, 0x42, 0x13, 0x5,  0xfe, 0x87, 0x9d, 0xa3, 0x27, 0x76,
+    0xda, 0x11, 0xe4, 0x78, 0x7,  0x79, 0x6e, 0x0,  0x8b, 0xf6, 0xc0, 0x72,
+    0x2c, 0x28, 0x33, 0xa0, 0xa1, 0x37, 0xda, 0x36, 0xad, 0xa3, 0xe4, 0x91,
+    0x68, 0x79, 0x6c, 0xf9, 0xe5, 0x31, 0xea, 0x3c, 0xda, 0x9,  0x15, 0xa6,
+    0xef, 0x4a, 0x22, 0xdc, 0x73, 0xa8, 0xbd, 0x4a, 0x50, 0x66, 0x5b, 0xb6,
+    0x9a, 0xc6, 0xa6, 0xc4, 0x7c, 0xc8, 0x4c, 0x5f, 0xbc, 0x95, 0xfc, 0x10,
+    0x37, 0x84, 0x76, 0x4d, 0xfd, 0x52, 0xff, 0x0f, 0x98, 0x20, 0xa4, 0xb2,
+    0xc8, 0x45, 0xc4, 0x56, 0xbf, 0x2,  0x5f, 0x6,  0xc9, 0x6b, 0xb3, 0x5a,
+    0xe4, 0x4d, 0x6e, 0x53, 0x24, 0x40, 0x7b, 0x3b, 0x57, 0x1d, 0x71, 0x49,
+    0x71, 0xaf, 0x68, 0x7e, 0xe1, 0xa8, 0xea, 0xaf, 0xde, 0x8a, 0xa7, 0xdf,
+    0x16, 0xe3, 0xab, 0x7b, 0x1d, 0x7c, 0x35, 0xc8, 0x79, 0xa6, 0x1b, 0x87,
+    0xee, 0xd5, 0x19, 0x9c, 0x73, 0x3,  0x8,  0xd3, 0xc0, 0xb6, 0xee, 0x29,
+    0x86, 0xdf, 0x57, 0x66, 0x18, 0xcf, 0x5d, 0x5d, 0xb7, 0x22, 0x62, 0x9e,
+    0x9f, 0x32, 0xa6, 0xdd, 0x66, 0x25, 0x6,  0x37, 0x85, 0x4a, 0x9,  0xf0,
+    0xf7, 0x94, 0xcd, 0xa9, 0x9e, 0xa6, 0x14, 0x44, 0xbf, 0x87, 0xa2, 0x9c,
+    0xf4, 0x55, 0x67, 0x27, 0x49, 0x48, 0x69, 0xc4, 0x16, 0xa5, 0x84, 0x95,
+    0x37, 0x44, 0xb3, 0xb1, 0x89, 0x8e, 0x58, 0xea, 0x17, 0x19, 0x6d, 0xbd,
+    0x87, 0xee, 0x7,  0x58, 0x65, 0xbc, 0x42, 0x18, 0x37, 0xf7, 0xa8, 0x7a,
+    0x4b, 0xc1, 0xce, 0x49, 0xb3, 0x6c, 0x4a, 0x77, 0x19, 0x70, 0x11, 0x60,
+    0x92, 0xd6, 0x6a, 0x6f, 0x41, 0x51, 0x23, 0x61, 0x5b, 0x9f, 0xd3, 0x16,
+    0xd7, 0xdd, 0x34, 0x80, 0xb0, 0x3f, 0x48, 0x54, 0x1b, 0x98, 0x8d, 0x76,
+    0x51, 0x99, 0x4a, 0x9,  0xfb, 0xd0, 0xd9, 0x85, 0x18, 0xc5, 0xb2, 0x37,
+    0x24, 0x1a, 0xf6, 0x41, 0x42, 0x1f, 0x1f, 0x31, 0x61, 0x4f, 0x11, 0xb2,
+    0xe2, 0x5e, 0x65, 0x88, 0x2e, 0xfb, 0xa2, 0x90, 0x1c, 0x1b, 0x59, 0xe3,
+    0x35, 0xcf, 0x97, 0xe3, 0xe2, 0x43, 0xa9, 0x7c, 0x14, 0xb4, 0x0d, 0x2c,
+    0x41, 0x90, 0x8d, 0x13, 0x0a, 0xd2, 0xd1, 0x3,  0x37, 0x24, 0x19, 0x57,
+    0xb0, 0xc8, 0x0b, 0xdf, 0xb3, 0xd3, 0x3a, 0x14, 0x23, 0x5c, 0xee, 0x62,
+    0x18, 0x6,  0x4e, 0x36, 0x44, 0xdc, 0xcd, 0xbb, 0xf8, 0x69, 0x61, 0x52,
+    0x95, 0xea, 0x33, 0x68, 0x4f, 0xae, 0xce, 0x6f, 0xf1, 0x6d, 0x31, 0x3b,
+    0xab, 0x25, 0x28, 0x31, 0x6,  0xe4, 0xa7, 0x12, 0xab, 0xfb, 0x3f, 0x7,
+    0xff, 0xb6, 0x8f, 0xa2, 0xae, 0x20, 0x34, 0x47, 0xba, 0xa3, 0x93, 0x8c,
+    0xcc, 0xad, 0x35, 0x9a, 0x72, 0xea, 0x40, 0x20, 0x25, 0x6b, 0x81, 0x0d,
+    0xc3, 0x1,  0xd7, 0x74, 0x3e, 0xc4, 0xca, 0xef, 0x81, 0x31, 0x0f, 0x5d,
+    0xf9, 0x2f, 0x4a, 0x43, 0x4c, 0x35, 0x19, 0x2e, 0x7b, 0x48, 0x71, 0x13,
+    0x79, 0x69, 0x49, 0x21, 0x4,  0x52, 0x4d, 0x2a, 0xf0, 0xa6, 0xb6, 0x3d,
+    0xd7, 0x0e, 0x2c, 0xb9, 0xff, 0xb2, 0x9d, 0x96, 0x19, 0xdb, 0x10, 0xbe,
+    0x78, 0x1e, 0x4d, 0x5f, 0x28, 0x3b, 0x61, 0xcb, 0x76, 0x3,  0xc5, 0xdb,
+    0x87, 0x72, 0x45, 0x4d, 0x82, 0x98, 0x7f, 0xea, 0xd6, 0x43, 0xeb, 0x5a,
+    0xa3, 0x3b, 0xb1, 0x92, 0x89, 0x30, 0xf8, 0xeb, 0x72, 0xcf, 0x54, 0xe5,
+    0xe1, 0x5c, 0x0d, 0xf5, 0xee, 0xe8, 0x92, 0xca, 0x58, 0x98, 0x0f, 0x36,
+    0xe9, 0xe0, 0x5e, 0x2,  0x5f, 0x47, 0xe6, 0x13, 0xee, 0x8,  0xe4, 0x49,
+    0x6b, 0x9e, 0x34, 0xb0, 0xe8, 0x85, 0xaa, 0x4a, 0xf6, 0xf8, 0x42, 0xda,
+    0xaf, 0x3d, 0xf0, 0x97};
+
+static volatile uint16_t LONG_I16[1024] __attribute__((aligned(AXI_DWIDTH))) = {
+    0x05c8, 0x60a1, 0xc277, 0x3862, 0x38a5, 0x657b, 0xa9bc, 0x766a, 0x4787,
+    0xf49d, 0xdb62, 0x3226, 0x9ced, 0xbcfb, 0x82f5, 0x38c5, 0x5cdf, 0xcecd,
+    0xa58c, 0xfa68, 0xb3ab, 0x20d8, 0x2f42, 0x939e, 0x770a, 0x1295, 0x06fa,
+    0xdd27, 0x040a, 0x1a0d, 0x082e, 0xa62b, 0xb056, 0x9f3a, 0x0e05, 0x5262,
+    0x53d6, 0x99ab, 0xd888, 0xdeff, 0x9d33, 0xddd3, 0xf914, 0x59bd, 0xdd8b,
+    0xf028, 0x68eb, 0x5e2a, 0x69ba, 0xa24e, 0x642a, 0x1360, 0x4784, 0x6b2b,
+    0xfc7b, 0x83c7, 0x805e, 0x5665, 0xf4e9, 0xc83b, 0x3a49, 0x3f3b, 0x365e,
+    0xb648, 0xa6b1, 0x84f7, 0xb227, 0xca26, 0xa732, 0xfc36, 0x033d, 0xb446,
+    0xaca1, 0x1f47, 0x3f55, 0x49d7, 0xaf46, 0x8f42, 0xd634, 0x3227, 0x7b79,
+    0x73bb, 0x9e94, 0x9849, 0x3729, 0xe01c, 0x6240, 0x4138, 0x093b, 0x9949,
+    0xe94d, 0x01b4, 0x19fd, 0xdb17, 0xcc54, 0x498d, 0xd9bf, 0xe16b, 0x943b,
+    0xa4e5, 0xd2fe, 0x891d, 0xda14, 0x5ed8, 0x7d02, 0xddb1, 0xefe5, 0x99b7,
+    0x659e, 0xfae9, 0x5887, 0xde77, 0x136f, 0x88f3, 0x0554, 0xe77d, 0x912e,
+    0x3c8b, 0x6e5f, 0x86ec, 0xc847, 0x2820, 0x5086, 0x448d, 0xbd06, 0x3817,
+    0xedbe, 0xb229, 0xddcc, 0xa9ce, 0x8245, 0xb06e, 0x1fb1, 0xeaf7, 0x61de,
+    0x115f, 0x1b58, 0x6f16, 0xc513, 0x5f9f, 0x9c08, 0x1173, 0x699f, 0xc00e,
+    0xe8d5, 0x0ed4, 0x6023, 0xf121, 0xb07c, 0xb0a9, 0x3f1c, 0x474d, 0xbaa6,
+    0x0d09, 0xddd4, 0xf5de, 0x3573, 0x69f2, 0x1790, 0xfd70, 0x7b2a, 0x8ae4,
+    0xfe06, 0x9066, 0x82be, 0xf0d3, 0x1fa6, 0x38a3, 0x0bb3, 0x172c, 0x183b,
+    0x52e7, 0x77d3, 0xf4ab, 0x1978, 0x1797, 0x4be4, 0xf98b, 0x89bd, 0x3e7d,
+    0x6cba, 0xb0bb, 0x19a4, 0x482c, 0xaa90, 0xf235, 0x25eb, 0x12bf, 0xf2ad,
+    0x84bd, 0x9ad8, 0x754b, 0x4e17, 0xf79d, 0xb67f, 0x127e, 0xe511, 0x4132,
+    0xeda7, 0x3f08, 0xefef, 0x5b00, 0x1910, 0x678f, 0x8d26, 0x5ae2, 0xdec6,
+    0x8ca5, 0x6756, 0x22c9, 0x2ad8, 0x85cf, 0xbd84, 0x050d, 0xf66b, 0xfa3f,
+    0x4c23, 0x2768, 0xef35, 0x7248, 0x0db2, 0x7240, 0xa41c, 0x789b, 0x0edc,
+    0x48fe, 0x40ff, 0x8435, 0x7ee8, 0x879a, 0x5245, 0x71aa, 0xbffb, 0xdf45,
+    0xe361, 0xb234, 0x465c, 0x60af, 0x07b8, 0xf4af, 0xa785, 0x66c2, 0x13db,
+    0x6928, 0xdf53, 0x30d0, 0xccf3, 0xc725, 0x38f6, 0xcd92, 0x3bc9, 0xbc2e,
+    0xcd73, 0x2824, 0x53ca, 0xd979, 0x4b6d, 0xd79d, 0x4123, 0xdd8a, 0x7dfd,
+    0xd802, 0x7718, 0x6e91, 0x6588, 0x45cf, 0x6f4e, 0xa431, 0x4296, 0xeafe,
+    0x7319, 0x624b, 0x25fb, 0x31d2, 0x54e1, 0xe0d1, 0x767c, 0xf0f9, 0xdb9d,
+    0x2611, 0xb352, 0xe521, 0x091a, 0x4b82, 0xe5fe, 0xafac, 0x6f8c, 0x8e66,
+    0x07f2, 0x0a8f, 0x524e, 0x08e3, 0xb3ef, 0x6667, 0x80ed, 0x31a0, 0x4bc2,
+    0xfc29, 0xf5d8, 0xc00e, 0x620d, 0xab89, 0x2d1c, 0xd922, 0x8a1d, 0x4758,
+    0x843e, 0x5677, 0x69b9, 0xfd68, 0xc044, 0xe042, 0x12fb, 0x734f, 0xa9c1,
+    0x3101, 0xc1ce, 0xe411, 0x2739, 0xbed5, 0x571c, 0xa03c, 0x67c5, 0xf559,
+    0x8d02, 0x4c56, 0x7d2d, 0x0797, 0x64ba, 0x5f95, 0x3653, 0x9bc4, 0x2d2e,
+    0x38bf, 0x75c2, 0x6db6, 0x3fcc, 0x7016, 0x146c, 0x094f, 0x1cee, 0xade1,
+    0x71e2, 0x1311, 0x9606, 0x5899, 0x0f77, 0x0de0, 0x39d7, 0xa028, 0xd2c4,
+    0x3f12, 0xf60a, 0x4a12, 0xcee6, 0x7778, 0xc1ba, 0xa2d6, 0x8d53, 0x0c25,
+    0xf6c0, 0x4f9d, 0x5c20, 0xe006, 0x8d42, 0x1e30, 0x8cc9, 0xe335, 0x0c4a,
+    0xc6b0, 0x6526, 0x7da6, 0xfcdc, 0x24e9, 0xecb4, 0xf36e, 0x5fc6, 0xe811,
+    0x498d, 0xd99c, 0xb3a4, 0xd1c6, 0x0029, 0x4976, 0x7108, 0xf4bc, 0x60c1,
+    0x86d7, 0x33e2, 0x1950, 0xaead, 0xb892, 0xa3b3, 0x7850, 0x19e8, 0x5e30,
+    0xaaab, 0xe18e, 0x1652, 0x8db1, 0xd6dd, 0x1c3f, 0xe906, 0xf2e1, 0x60e5,
+    0x1ce0, 0xfd1a, 0xf74a, 0xabd8, 0x9885, 0x18ef, 0xe64a, 0xe791, 0xc42d,
+    0x8010, 0x1f34, 0xfa91, 0x36e3, 0x7ca3, 0xfb85, 0xb8a9, 0x6bd4, 0x8985,
+    0x86af, 0x247c, 0x25f0, 0x56a9, 0x87ab, 0x54e0, 0x75af, 0xd782, 0x886d,
+    0xfe3f, 0x9f68, 0x5357, 0x7f4e, 0x92f6, 0x4266, 0x5176, 0xd657, 0xc6a7,
+    0x9738, 0x2f4c, 0xb40b, 0xe857, 0x12a3, 0xf4b1, 0x0ab4, 0x9eeb, 0xed88,
+    0x8df4, 0x30c1, 0xf904, 0x5d83, 0xbbea, 0x5858, 0x1230, 0x99c7, 0x603e,
+    0xf8f9, 0x88ec, 0x29d1, 0x415b, 0xac9a, 0x8cc1, 0xbaf8, 0xd11f, 0x569c,
+    0x6e4f, 0x78a9, 0x14e9, 0xde4f, 0x76aa, 0x7e97, 0x9e43, 0x0df2, 0x3157,
+    0x5df4, 0x335e, 0x0a7a, 0xe7c3, 0x4631, 0xc2be, 0x8e78, 0xd26e, 0x40a9,
+    0x00d3, 0xd0cb, 0xba96, 0x8414, 0x150f, 0x845d, 0x37ff, 0x2465, 0x3d72,
+    0xb6ca, 0xa623, 0xb525, 0x1466, 0x98f0, 0x30ae, 0x9a66, 0x9978, 0x3ff7,
+    0xdd7b, 0x5d83, 0x287b, 0xbcac, 0x708b, 0x9f85, 0x6ba7, 0x4b45, 0x6ff9,
+    0xb18d, 0xd137, 0xf108, 0x371d, 0x78cc, 0x16ee, 0xc10e, 0xea24, 0x56dd,
+    0xda45, 0xc8d1, 0xa2ac, 0x1430, 0x8804, 0xca53, 0x9b14, 0x128a, 0x106f,
+    0x1e8f, 0xd25c, 0x74c1, 0x4ceb, 0xca33, 0x2dfa, 0x53a7, 0x668a, 0x2338,
+    0xd0bd, 0x5ba0, 0x796c, 0xbe89, 0x2737, 0x7eae, 0x47f5, 0x5675, 0x165c,
+    0x546b, 0x3682, 0x1b3e, 0x04e8, 0x13d1, 0xa73b, 0x1b9d, 0xe520, 0xe89b,
+    0xcc4b, 0xc6d0, 0xe5d0, 0x15f8, 0x2d3d, 0x6fa0, 0x4a1d, 0x86ec, 0xb10d,
+    0x6766, 0xef18, 0x7664, 0xfdf0, 0xefb7, 0x1301, 0x5972, 0xde95, 0x7763,
+    0x7359, 0x86ed, 0x937d, 0x62c6, 0x3fe6, 0x15a8, 0x2cf4, 0x67c1, 0x8b1c,
+    0xfac9, 0x38cb, 0xd1f7, 0x6777, 0x57fc, 0xa8d9, 0x734f, 0x9f44, 0x7e06,
+    0x94de, 0xfbcd, 0x1f2e, 0x9de5, 0xba7b, 0xaae4, 0x597c, 0xc908, 0x991c,
+    0x5ba1, 0x56a7, 0x3935, 0xa728, 0x3883, 0xfce5, 0x32cc, 0x9afe, 0x0ef8,
+    0x18c0, 0xcb6c, 0xe4d7, 0x7184, 0xecab, 0x3c14, 0x802d, 0xfe5b, 0x2581,
+    0x40e4, 0xa4ef, 0xcb8e, 0x53a6, 0xc27b, 0xc604, 0xe5f8, 0x6c63, 0x1400,
+    0xf529, 0x0303, 0x8a5d, 0xf26b, 0xfa14, 0x7f48, 0x852f, 0x4b93, 0xd96b,
+    0x10ea, 0x332e, 0x72b3, 0x84a6, 0x4cd2, 0xbd3d, 0x1649, 0x6edb, 0x85e1,
+    0x4cbc, 0x1b3f, 0x2057, 0xe0b5, 0x0b23, 0x3b49, 0xa634, 0xf2a3, 0xbbdc,
+    0xb528, 0x5102, 0x42e9, 0xaf96, 0x0e61, 0xc393, 0x0614, 0xd3f4, 0x1329,
+    0xea3d, 0xbeeb, 0x1d4b, 0x082b, 0x0a49, 0x331a, 0xe8fc, 0x57d7, 0xc4e5,
+    0x5500, 0x8bc1, 0xa259, 0x8d4d, 0x8d8c, 0xcf01, 0x3ef0, 0xd1da, 0xf7e5,
+    0xc55c, 0x062c, 0xaa7d, 0x967a, 0xb694, 0xfab0, 0x279e, 0x3efe, 0xcecc,
+    0xd074, 0xd240, 0xbaba, 0x59d5, 0x44e4, 0xc97e, 0xd88c, 0xb3c3, 0x8145,
+    0x0312, 0x8f1c, 0xc165, 0x0ec3, 0xc773, 0x9b8c, 0x56c1, 0xf293, 0x3a87,
+    0xb577, 0x5423, 0xea97, 0xf94e, 0x795c, 0x3480, 0x419c, 0xec6e, 0x3f14,
+    0x6cda, 0x95c9, 0xb0a2, 0x0e27, 0xc572, 0xfc95, 0x2840, 0x30f1, 0x285d,
+    0x4934, 0x5ccb, 0x5a71, 0xf4d5, 0x9448, 0xdf84, 0xb00d, 0x3e72, 0xbf8a,
+    0x45d1, 0x7a94, 0xc9fa, 0xd41b, 0x279a, 0x0b74, 0xb8d7, 0x983b, 0x18ac,
+    0xa78e, 0x3f83, 0x397a, 0xa9ba, 0x7e7a, 0x62bc, 0x461a, 0x16f1, 0xeb72,
+    0xfde1, 0x9a3c, 0xb8f0, 0xa683, 0x6031, 0x82f0, 0xe01d, 0xe109, 0x71f4,
+    0xd215, 0x8794, 0xf622, 0xc5ba, 0x40ca, 0x20dd, 0x1333, 0x30ef, 0x51d8,
+    0x6627, 0x66d5, 0xad8e, 0xef11, 0xf93b, 0x68c7, 0xde9f, 0xa107, 0xf6b7,
+    0x2080, 0x8e4a, 0x5570, 0x945c, 0x83b4, 0xa5b1, 0x925e, 0x7818, 0x7006,
+    0xf0a1, 0x450a, 0xc7d0, 0xe348, 0xd405, 0x3a77, 0xd98b, 0xc755, 0x7ad5,
+    0xb1bc, 0x7f59, 0x8d0b, 0x82e6, 0x9a52, 0x10dc, 0xc268, 0xafcc, 0x5f84,
+    0x629d, 0x9bea, 0x2eb6, 0x466b, 0xd4b3, 0x1ba3, 0xcfd8, 0xc856, 0xb32a,
+    0x9fa3, 0x6762, 0x61e2, 0xdcb2, 0xc67c, 0xd4cc, 0x93ec, 0xfc8e, 0xea59,
+    0x5e42, 0x4d74, 0xf566, 0xe148, 0xd538, 0xeba6, 0xc946, 0x7f79, 0x73e8,
+    0x0403, 0x1bad, 0xd856, 0xb382, 0x77e9, 0xf88e, 0xb004, 0xa080, 0x1c0e,
+    0x7dce, 0xec47, 0x2aa5, 0x3218, 0xbb53, 0x673e, 0xe9cd, 0x92b0, 0x2452,
+    0x9b83, 0x7721, 0x0c2c, 0x9c90, 0x4cc6, 0xb17e, 0x77a5, 0xf070, 0xf8a5,
+    0x2edc, 0x1c5f, 0xc7d5, 0xad46, 0x933e, 0xe6b5, 0x6131, 0x0885, 0x511e,
+    0xabc1, 0xb239, 0x8adf, 0x2cab, 0xb149, 0x5922, 0xd99f, 0x65a5, 0x153f,
+    0x02a1, 0x11d9, 0xb82d, 0x8cd1, 0xb7e0, 0x78db, 0xd92d, 0x738a, 0x0a41,
+    0x8e6f, 0x67f6, 0x49ff, 0x0a42, 0x4243, 0x02ee, 0xa1ec, 0x306a, 0xd86f,
+    0x71bb, 0x7645, 0xa349, 0xcd18, 0x2f95, 0x147f, 0xee96, 0x6c36, 0x929f,
+    0x1bbb, 0x0814, 0xe8f7, 0x7344, 0x8397, 0xf269, 0x64b3, 0x60f2, 0x6a51,
+    0xd5bf, 0x4083, 0x439a, 0xd44e, 0xdca1, 0xaebd, 0x80cb, 0xe318, 0x67e8,
+    0x9a3d, 0x1014, 0x0017, 0x6f99, 0x28b4, 0x062f, 0x56e9, 0x75fb, 0x664d,
+    0xee67, 0x0aa0, 0xf38f, 0xab03, 0x0777, 0xc318, 0xd0a4, 0xb3c2, 0x566e,
+    0xaf15, 0x7296, 0x4fca, 0x3431, 0x6536, 0x1a4c, 0x3423, 0x4d25, 0x9877,
+    0x41a1, 0xb704, 0xdef9, 0xb22e, 0xcde0, 0x1def, 0x92d7, 0x0ce2, 0xf2c9,
+    0x84bf, 0x6fcd, 0x76a8, 0xdbdf, 0x41a3, 0x9337, 0xc8a7, 0xaa42, 0xa21e,
+    0x8844, 0xdf16, 0x4de9, 0x4584, 0x450a, 0x0ddc, 0x62ce, 0xf491, 0x8509,
+    0xc94c, 0x454f, 0x23a6, 0x5985, 0xf00b, 0x3836, 0xe524, 0x4dc1, 0x873a,
+    0x8b3f, 0xed5a, 0xc984, 0x3cf7, 0x854a, 0x7569, 0x3c93, 0xfc08, 0x3b0a,
+    0x59cb, 0x0558, 0x47ce, 0xb8c4, 0x0e07, 0xf780, 0x8723, 0x48c0, 0xaf0a,
+    0x9ba6, 0xc9ef, 0x55c4, 0x751e, 0x86ca, 0x15d7, 0x7868, 0xf984, 0x5ce6,
+    0xb0e3, 0xfab4, 0xb4af, 0xf721, 0x55b9, 0x1c10, 0xddf1};
+
+static volatile uint32_t LONG_I32[1024] __attribute__((aligned(AXI_DWIDTH))) = {
+    0xfb4164e6, 0x3481e187, 0x1ac57c0e, 0xd3913cf7, 0x41059a17, 0xef7e75e1,
+    0xfe210ff9, 0x7f6ac91e, 0x28e9650d, 0xb7885df2, 0x284b1afc, 0xfb4a1bf7,
+    0x617d65d4, 0x896d8b4f, 0x9c9c9363, 0x3b43b452, 0xabb915d7, 0x8698d89d,
+    0xd8a34f81, 0x863f4cca, 0x14d6ca22, 0xb0bf4e0a, 0xee1f91c4, 0x7c3a990f,
+    0x6eab68bd, 0x299c17f2, 0xcadf4216, 0xb1f82b82, 0x67c9f67f, 0x7b690aae,
+    0xa150c9d4, 0x15351675, 0x9cff4711, 0xe1817cb5, 0x2430a746, 0x03057f72,
+    0x171d9928, 0x09d1c92b, 0xcc77e581, 0x95929376, 0xaeadce6f, 0x789d357e,
+    0xfcbfc753, 0x01432b7b, 0x9e9478fa, 0xba2e81b9, 0x82b58cff, 0xd9f94cab,
+    0x6cb2edf5, 0x77487076, 0x4d02002d, 0x4a86378e, 0x68504041, 0xff7d13ee,
+    0x5ac9c780, 0x4c9ec46b, 0xd255423e, 0x490ad4be, 0x402e482e, 0x20a002bb,
+    0x3047c1be, 0xb6d5251f, 0xd44b670e, 0x237e7f10, 0xfac60317, 0x032f62ee,
+    0xbdeed490, 0x608ce228, 0x72c0007a, 0x2f649ab1, 0x648c3132, 0x29c2e261,
+    0x0bea8083, 0xcd7b169d, 0xd8650fc5, 0x0e539628, 0x7a4dca9f, 0x1a83111f,
+    0xb66efb6e, 0xb57e0806, 0x97429779, 0x3db5389e, 0x37eb587b, 0xed67e2b9,
+    0xd83725bc, 0xfa08dddf, 0xeda1f1d0, 0x300cb2c4, 0x40621713, 0x40bad650,
+    0x76774234, 0xdabcac54, 0xc3a8998e, 0x5679012d, 0xdfbf840c, 0x7fb19cef,
+    0x421cf0af, 0x205127bb, 0x7583bafe, 0xb841a0ad, 0x94c27ef1, 0x98ce86fa,
+    0x63a94985, 0x3be3aa2e, 0x15172f37, 0x2cd44ef0, 0x9965f864, 0x445089c7,
+    0x75bc26df, 0xf6eefe92, 0xf34c4396, 0x329bbaee, 0x4c8a5ce9, 0x88da6dad,
+    0xfd153397, 0x877c5b1a, 0x21cf83c2, 0x28eadf4c, 0x79e4ea97, 0x406520ac,
+    0x7ace596d, 0x97af1221, 0x1231fc0b, 0x25ed7519, 0x747b6cd8, 0x3a8f07e7,
+    0x2eceda51, 0x444e9a77, 0x602cd53d, 0x4dd07c56, 0x526cf01c, 0xc20a4814,
+    0xb957f851, 0xa17f5997, 0xb1301c23, 0x127449d7, 0x2019ff30, 0xcf4ae57a,
+    0x9d469972, 0xa79ee397, 0x46ad27c1, 0xc102cfab, 0x9839df44, 0xbe15ac43,
+    0x52429a74, 0x8498333c, 0x0323bb3b, 0x34759b37, 0x786294cf, 0xbd5b638e,
+    0x3ee76252, 0x29aa55cc, 0xf838fe3f, 0x3ebbcb2a, 0x8211b294, 0xd022967b,
+    0x4021661b, 0x567ce0c8, 0xe89c3fd8, 0x12a755b3, 0xb662102a, 0x5df38d95,
+    0x62d37025, 0x28966663, 0xb7a26439, 0x7aaf36db, 0xd78b2521, 0x70529f47,
+    0x685f3890, 0x9d8d013e, 0xcbe3ff49, 0xd46afdb6, 0xc2b04898, 0x559bf4f7,
+    0xd7c8eed2, 0x2715286a, 0x725c1503, 0x680e0b70, 0xbf041ae9, 0xd254a94d,
+    0x24781161, 0xd84f4a94, 0x079846af, 0x09b1493c, 0xa73bf5c1, 0xbfb15a17,
+    0x037d4fb8, 0x67a8f910, 0xc30f2963, 0x90ea7999, 0xcef7a60a, 0xcf4846e2,
+    0xea560dbc, 0x65918304, 0x5ec1f21c, 0x52d49030, 0x5b42b6d1, 0x9f863c02,
+    0x60a941bf, 0x9341e1c1, 0x0b8eb154, 0xe388daeb, 0xe4d32c38, 0x3a34dbfb,
+    0x88aa7015, 0x9df806df, 0x98bcc5ac, 0x9f0bcfef, 0xe426baf0, 0x0040e48c,
+    0x9edd30b2, 0x53ec8281, 0x2a2f521c, 0xba2341d4, 0x469344c9, 0x303383dc,
+    0xbcb454d6, 0x8bb0bec5, 0x03676a10, 0xc343c028, 0x2a93711a, 0x51e3d400,
+    0xcbd64ef6, 0x02b6d3e2, 0x657f9d43, 0xd041e607, 0x2a4081aa, 0x3d646621,
+    0x61b2b84e, 0x0d82184d, 0xe21a073b, 0xd0f44d3b, 0x83ff1551, 0xbf0be20c,
+    0xc0ec1cb8, 0x85031860, 0xfd917b19, 0x4bee6789, 0xc2d90f50, 0x5328b175,
+    0x33a8b947, 0xb8117d89, 0x0151019a, 0xdf1309e6, 0xeefba94b, 0xaf407e14,
+    0x01841f74, 0x072edc92, 0x67718fcb, 0x3325bc8e, 0x67723637, 0x4c57c32f,
+    0xec826139, 0x49da5f2b, 0x86aaad66, 0xcdf48c61, 0x1051c1ef, 0x73b124be,
+    0x3d91d1e4, 0x42edf18a, 0xfb65c395, 0x2d320a4a, 0x249295ee, 0xd8a0b7da,
+    0xbdda8975, 0x6cacaa51, 0x6a95ad3c, 0x70ea1e1e, 0x860d04a5, 0x7fe5968c,
+    0x8e94d9d2, 0xe1776758, 0x03f2b8a4, 0x6d177309, 0x5e5d1658, 0x8226f111,
+    0x5e05e9e9, 0x03523a16, 0x0a486558, 0x7802572c, 0xf4b2ece6, 0x25334aab,
+    0x76ec5f3a, 0x91c188dd, 0x17602398, 0xf937ba21, 0xb4150e39, 0xfd69cb60,
+    0xa6db1804, 0x40e59e9c, 0xd0a66868, 0x940433eb, 0x0493232c, 0x8c6332a5,
+    0x603c2378, 0x8892f964, 0x9332413a, 0xd73f6d38, 0x9eb00bf6, 0x6d3f6f14,
+    0x9cb277c2, 0x0a8f9f0e, 0x274ba4cf, 0x8b6bcd6a, 0xcf628996, 0x153697aa,
+    0x637d2a08, 0x2575efc2, 0xe610cb7a, 0xfdc2463d, 0x2a79b1d2, 0x3eb854f5,
+    0x8d62d4b4, 0xc0be0d46, 0x20d5923d, 0x3302d755, 0xe3fe3f04, 0x35f41e8e,
+    0xc038ad3a, 0x0c3b1fe9, 0x63f01783, 0x860d0433, 0x0764210f, 0x8a089d41,
+    0x345db32a, 0x73a001bd, 0x2511eac3, 0xe6662996, 0xca424b60, 0x3f28df70,
+    0x2e4235b7, 0x94ecaa8d, 0x5e0dbfae, 0x05d48830, 0xaeb4f71e, 0xc34cbb15,
+    0x12e7551b, 0xdb32f1cd, 0x020ca7f6, 0x947109b4, 0x31ecb208, 0xde042987,
+    0x1766916a, 0x767947c7, 0x7356d7a5, 0x99af1544, 0xe4f08a91, 0xe295f986,
+    0xc4ab8b16, 0xb928323c, 0x17b8d6a8, 0xf87b6f1d, 0xff8b1b74, 0xeedc69d6,
+    0x466a95ce, 0x2123486a, 0xb09b7da6, 0x0c77b31c, 0xcb81435c, 0x0d5709f4,
+    0xf908fe1b, 0x7827dec6, 0x9654e061, 0xe533cf13, 0xd1eb1a88, 0x41ce8521,
+    0x472b0b22, 0xf2760080, 0x7cd0c1a5, 0x37a9458a, 0x25bfb15d, 0x15e3abeb,
+    0xe4038b26, 0xff4d2cde, 0x008d5210, 0x08fbf24d, 0x02bb941b, 0x7a7076a3,
+    0x4ff9ff8e, 0x3f83c03e, 0xe3968330, 0x321a0467, 0x9500f585, 0x44d174e6,
+    0x44e093ca, 0x13042152, 0xd784bc78, 0x6f35fa1e, 0xb1f169b7, 0x5decd01b,
+    0x135d20d4, 0xf02f73a0, 0x1d1c3fe5, 0x7619a9bf, 0xa28e7823, 0xc1106044,
+    0xb2dc46bd, 0x4806d55f, 0x64e990d6, 0x472c895e, 0x4e9b7283, 0x8c3362c9,
+    0x8a078a8d, 0xc2424042, 0x1fa3e0e0, 0x79d90528, 0x2853d8ac, 0xd5afa3d6,
+    0x3670e59c, 0x2d3cc396, 0xf4479882, 0x5e8511e7, 0x9216bbe3, 0x13fd475e,
+    0xc51c4183, 0x44938b14, 0x475131a1, 0x21f15f5c, 0x856470ea, 0x7c3c81de,
+    0x2479d636, 0x507443eb, 0xffd9c527, 0x8812ad05, 0x9ed97b93, 0x52490a02,
+    0xa6ed5452, 0xe8ddec31, 0xaf6c7d4d, 0x522da798, 0xbc83d67d, 0x961da9f2,
+    0x944ad080, 0xf9713e9f, 0xf3495078, 0x9fa49ebb, 0x10dba1f0, 0x893716fd,
+    0x9b0ae830, 0xa64b41a0, 0xbef91268, 0x0b6c14c8, 0x08e39616, 0xa6acfb78,
+    0xdcea059f, 0x887450d5, 0x57bc0908, 0xaed44e07, 0x6472bbe9, 0x51ac69b0,
+    0x95fae493, 0x689c9553, 0x2c16d5ca, 0xab54a6ba, 0x4b983d38, 0x65ec59f4,
+    0xd9a7aafe, 0x9d58d2ee, 0x520ad3b8, 0xf494ab7e, 0x3937b9da, 0xb8b1e32b,
+    0xe646bfa1, 0x4e27136d, 0xb67bf1ec, 0xf4329e4c, 0x787e23fb, 0x0c1735c1,
+    0x6ec010ff, 0xecaec95d, 0xae6f8818, 0xd82adbe9, 0x2f43a4d0, 0xa58929d8,
+    0x13f9a8e5, 0x1fd9795b, 0x5a0899ad, 0x1c2e93c3, 0xa7a3ba2e, 0xf84f24aa,
+    0xc838132e, 0x400eea14, 0x14066d7c, 0x2e14b597, 0x068ecff1, 0xf1de4ca2,
+    0x12728915, 0x9456e5a7, 0x44b73462, 0x8570f45a, 0x5147b71f, 0x9fec40d5,
+    0x810eac29, 0x752e6e6e, 0x2163fcf7, 0x2f86c06d, 0x008c883d, 0x1103334c,
+    0x64604d87, 0xda684940, 0x14db1948, 0xdd5166a6, 0xda9c3b68, 0x47e3c57c,
+    0x071aa5d5, 0x5b279146, 0x7f40674a, 0x43c43b58, 0xb9a00920, 0x2e9c6395,
+    0x6ede2f7f, 0xdd87b364, 0xb078f1e3, 0xe03188df, 0x34fdfdea, 0xfa5d5b6c,
+    0x7238598b, 0x2152fc58, 0xbd593666, 0x110790de, 0x3aeeea53, 0x871b9b30,
+    0x2e62ee2a, 0x87073223, 0xe7a8ec3d, 0x997ce0d2, 0x5e098f1a, 0x449af7a4,
+    0x7160a663, 0x184dbcdd, 0xafcc6519, 0x411e4012, 0x4c757e42, 0x24a5aac6,
+    0x989f5803, 0xe57658e9, 0xf21e713c, 0x9585a4c5, 0xa6d3abd4, 0xa49eba26,
+    0x5c488bfe, 0xed82c154, 0xf6a5643b, 0xa5ac8cc8, 0xff160035, 0x2c26e8af,
+    0x7decaaa5, 0xb636eb2a, 0x5ab81b73, 0x3908cbbc, 0x8df7a726, 0xce3c50bb,
+    0xd9f1d082, 0x530bcf08, 0x57fd848f, 0x642affea, 0x5a2bd422, 0x8f9a2823,
+    0x01bfa7a1, 0xc876c080, 0x23b5706d, 0x0b301308, 0xb11d1c47, 0xfb717d95,
+    0x48fd147e, 0x688ae8e6, 0xc76a7815, 0x853814a6, 0x0911627c, 0x67d7d038,
+    0x9b981e85, 0x332e64b9, 0xd73390cc, 0x9d5c9347, 0x64b73aa4, 0x66fda1dd,
+    0x9bf7d9be, 0xb2aa046c, 0x227d564f, 0xef7c5d66, 0x74153519, 0x33b79c47,
+    0x5678141d, 0x0425e8d2, 0x89151438, 0x610898f7, 0x8f4e6fec, 0x3b209567,
+    0x2fa8fbe1, 0xf4de930e, 0x0fe098ed, 0x784c4bf6, 0x2e5a8aa9, 0xae2d8329,
+    0x4a75bcf4, 0xe869b0d6, 0xc25f3374, 0x9c40e4ad, 0xa45a09a2, 0x71e412e5,
+    0x82fa90c7, 0xc8f3f3d7, 0x8bd65e1c, 0x9428ab27, 0xfb0f0bb0, 0xed2bf565,
+    0x025f8172, 0xef1f23bd, 0x527aa7db, 0x82a9eaa2, 0x3ecf5a54, 0x7b46a656,
+    0x83ba908c, 0x029a1d56, 0x1ad4802d, 0x0b6d0a16, 0x85676492, 0x5603720b,
+    0x93d57ab8, 0xa511234a, 0xaf0622d5, 0x92cb4015, 0xc99b3d9b, 0xc28c681e,
+    0x9ca6141a, 0xc675ed6c, 0xdf2354cc, 0x4b94f874, 0xac031dc6, 0x4dc8c88a,
+    0x8e957384, 0xce4c06f6, 0x41d81338, 0xedf18fa0, 0x7496b2c3, 0x1d22d10e,
+    0xada0df5c, 0x567818f1, 0xed69beee, 0xd3538bee, 0x87015a7e, 0xf096af02,
+    0x0f74ea22, 0xf97c3941, 0xbc92e90d, 0x64c37c02, 0x323b8567, 0x64a0388e,
+    0x672072ef, 0x606c1d74, 0x3261f7cb, 0x2fc0bdff, 0x06e8d5b7, 0x5a089662,
+    0x7dbb1fb6, 0x8640f66f, 0x0eebab49, 0x41f391b3, 0x405465ea, 0xdcf54a80,
+    0x7b2607bd, 0x620a96f6, 0x1761b04c, 0x71602fb5, 0xc75677aa, 0xcc0b979f,
+    0x68d7ad59, 0x8097096c, 0x036dda70, 0x5cc96868, 0xdf34fd5c, 0x358de617,
+    0xd6cee2fe, 0x2298a0cc, 0x7d51ede5, 0xef7ec9cb, 0xbd4a2269, 0x81cfeb67,
+    0x19ca0ca9, 0xd9341ac3, 0xe7eedbc4, 0x712d2b76, 0xf2fc13bd, 0x1eddc054,
+    0x157a1068, 0xf77354a9, 0x982a70dc, 0x7af178bc, 0xca78b6dc, 0x89f96f32,
+    0x6165ff46, 0x53cd4b2d, 0xd9d6bf4a, 0xe1cba818, 0x6943d30b, 0x49c15a0c,
+    0x7c6f9158, 0xb0de4aca, 0xee608c5d, 0xe588c493, 0xe77b48d4, 0x82d454a6,
+    0x1a4b0894, 0xc14840a8, 0xab9ce7dc, 0x3e103ccd, 0x9a0c5d0a, 0xa7b3beb4,
+    0x799ea004, 0x1858b310, 0x3d05000f, 0xc3315616, 0x76335d71, 0x2beb4718,
+    0x075e63c4, 0x49ce8254, 0x3b6e6d7b, 0x4eb9d856, 0x22257f0c, 0x8cf26342,
+    0xaa5bb8bf, 0x3a9350f7, 0x5b1a22b7, 0x321b3167, 0xf93ccaaa, 0x2ee34209,
+    0x08a40813, 0x3c9f0ab4, 0xe3625de4, 0x3a4ddf66, 0x3ed40aaa, 0x55c407c1,
+    0x0b8be44a, 0xc0ad17ce, 0x46ee41d8, 0x5d8308cc, 0xeb0cb1aa, 0xbf8c58af,
+    0x75d1e501, 0xc8dabac6, 0x9549fea7, 0x5299e2ed, 0x9b291dd4, 0x6d53d7b9,
+    0x6cd4edeb, 0x48478b5f, 0x0b039677, 0xe865413c, 0xe7101843, 0x8b8b76be,
+    0x158dacd7, 0x3853595c, 0xeb14d1b4, 0xad9019d1, 0x611fbb67, 0x15b98f69,
+    0xc6d2b4b9, 0xbae09260, 0xe475db51, 0xabfb48fb, 0x510e0d0d, 0xe312edaa,
+    0xeff0e709, 0x6e8a356a, 0xe491068e, 0x9aa3d5a5, 0x0bd3522c, 0xbc5c78b2,
+    0x810e16f7, 0x23930de9, 0x828faaaa, 0x7b090240, 0x49cad6bc, 0x5ba6b866,
+    0x9ad09cc8, 0xd8e94225, 0x4edf917b, 0x8b1ed082, 0x532e07a3, 0xe663e0cf,
+    0x8c32bde2, 0x93971dae, 0x62220180, 0x20086ecb, 0x0e45c5c8, 0x25d8dbea,
+    0x4eea9f76, 0xed571820, 0xf01d0c9d, 0xf4e803d5, 0x9fe78cfa, 0xfc2d84c3,
+    0x8d0811c3, 0xecd10843, 0x33e6078a, 0x2fae3bc4, 0xe2474238, 0x8d8705c5,
+    0x6c50f0ea, 0x8abaab5a, 0x32e56fd6, 0x2182980b, 0x87e6b96d, 0x3e4e2167,
+    0xc94ae51a, 0x6252eb57, 0x097d3e57, 0x8bb677d4, 0x8727f2f3, 0x21599432,
+    0xd2698100, 0x3bce3251, 0x32532c57, 0x8435d39a, 0xcc22b598, 0xf78214be,
+    0xdfb4ad33, 0x0b293f61, 0xb70de245, 0x49ed033f, 0x1b22d3d1, 0x275a5e2a,
+    0x6eda6823, 0x84ca3acf, 0xb2007d31, 0x550f4dc9, 0x6c41f89f, 0xbcf6a060,
+    0x5cacc20a, 0xe072b717, 0x3e5290b4, 0x57d714e9, 0xba015f77, 0x9f5c82b9,
+    0x9145d986, 0x1fbcb59f, 0xbc4c94fe, 0xe9630858, 0xbc836442, 0x6ecd8857,
+    0xe6849951, 0xebb538d5, 0x77834926, 0x93c14aaf, 0x3ea06c07, 0x7defe3ea,
+    0x7703d4d7, 0xa7bed2bc, 0x9f07caa9, 0xfbb38ec0, 0x93e4d78a, 0x9f962279,
+    0x46461a9c, 0x3469b86f, 0xa70f4f94, 0x5a636708, 0xc7c27941, 0xbd09a8c6,
+    0xfdbb0dc6, 0x8e356917, 0x40ac8185, 0x911d958e, 0x464557f8, 0x2144ceeb,
+    0xc91bd789, 0x3336ca40, 0x94c17309, 0xb9b5fd22, 0xa15d027d, 0xecf123ea,
+    0x24b341be, 0x15f99919, 0x0f7e5437, 0xc0a2e3b0, 0x85ad9be7, 0x1802995d,
+    0x6ffbdb36, 0xfee2f330, 0x82d97360, 0xce34d141, 0x92d485db, 0xa5355c91,
+    0xfa1e8722, 0xeb4d45de, 0xfb6d515e, 0xc314a653, 0x0d87eb60, 0xfd847790,
+    0x8b92e379, 0x0201eba2, 0x7b4b7452, 0xf584a6e1, 0x2b193f55, 0x7c8655b5,
+    0x2f7ddd10, 0x307135f2, 0xc2d95e86, 0x2a589931, 0x205cff1b, 0x3ef585cb,
+    0x87ed3660, 0x3d940695, 0x9b5bf90c, 0x3cc0a414, 0xaf7c64be, 0xb89d73bf,
+    0x0bfdee3c, 0x363434b2, 0x2a03aaa2, 0x9eeeaa79, 0x9d10e970, 0x2a53c383,
+    0xc279b64d, 0xa1fccfd4, 0x45beae3d, 0x10a0edf7, 0x115db88e, 0xf82c38c8,
+    0x3ea14f75, 0xcae52dfe, 0x0f7a30e8, 0x8097dad3, 0x6877021e, 0xf641ac74,
+    0xa1070496, 0xedf1dc86, 0x8f86118a, 0xc0885553, 0x674121f2, 0x703322e7,
+    0x3ce1c69c, 0x185f7483, 0xd903a5c1, 0x5443c629, 0x09be9c89, 0xc9287535,
+    0xa3756dbe, 0xada965c0, 0xb5cca18a, 0xf66126c8, 0x032d3228, 0xdcb35032,
+    0xb91d592c, 0x4f946c88, 0x48a4d566, 0x6c6a9877, 0x59008967, 0x4b4d064d,
+    0x02c9b04a, 0x69411188, 0xd9874bbb, 0x33a0ddd5, 0x88aaca79, 0x21170627,
+    0xef390ee3, 0x815ad6e4, 0x111058b4, 0x4c458220, 0xd0a582e8, 0x035b7606,
+    0x3983b039, 0x85672bd9, 0x35ffe70a, 0x17a907e1, 0xc93c655b, 0xeb2d3465,
+    0x4330c966, 0x865946cb, 0x591d81de, 0x2bb7e3a0, 0x0c3c47b7, 0x5fa46f27,
+    0x32b448b6, 0x0ae8b601, 0x52bd856b, 0xba2b65ff, 0x5095ef4e, 0xafcc8c2b,
+    0x764982c7, 0x7af2ccf1, 0xcd822340, 0x25d6277f, 0xdcebabda, 0x97d1309f,
+    0xa308c1a5, 0x2c057a68, 0x93f7c2e9, 0x953c9d03, 0x570a5aba, 0xc44800d3,
+    0x497e542d, 0xa5f7cd96, 0xf6a92a36, 0x5f3095df, 0x2364d5bd, 0x2e008680,
+    0x40025d58, 0x9270a8c0, 0xa7027802, 0x7fed9c46, 0x9a937b1b, 0x4c909c08,
+    0x54234050, 0x1a3ede20, 0x9e33f20e, 0x8945cc06, 0xa8f2d3ad, 0xc134ce4a,
+    0x0a8855c0, 0x2896bb3a, 0x4641661a, 0x5b9e308c, 0xa7af698a, 0x7d7677cb,
+    0xab025a5d, 0x9612a4d2, 0x52e6ab7d, 0x031e4c67, 0x7b365bc3, 0x8bc2b6e7,
+    0x6e6be6ca, 0x2a479be3, 0xaa0816c0, 0x445220a7};
+
+static volatile uint64_t LONG_I64[1024] __attribute__((aligned(AXI_DWIDTH))) = {
+    0x5b918a8884cfd5c3, 0x2c63b07fd926c9a6, 0xc86fa3cf7b49b1de,
+    0x29a920deaf293c91, 0x41dcd2ddad56ca9a, 0xc5903d04cdd5a80e,
+    0x3c9652849cfe9aa7, 0x45349b70a8ae9ebf, 0xcaf33ebac28cd71a,
+    0x63e1cac81153895e, 0x0b4b8c86937feae4, 0xa39bce9e797fed4d,
+    0xf81a244d5bcd0109, 0xa9b1402ee782d2ce, 0x5fec840fb9505fb2,
+    0x3a48b01cfe5103ca, 0xbacd4b67821f2584, 0x1d61f3d9f36d0bcf,
+    0x5cca3fc0f92a6875, 0x4d9b65e9be59f56a, 0xf6f55943b82f5763,
+    0x3131cf70faf884bf, 0x9b5bce0522a090e3, 0x2fdeb698c98eb085,
+    0x4a50e635c24c9bf6, 0x75af29be8cfdf207, 0xd70f6631640a1fe0,
+    0x088f1ddc23501599, 0x50f00f14446c4e77, 0x683dbab92f032d29,
+    0x2f4903e13da53013, 0x6f3c66daa92514bf, 0x9dda491ef7291a4f,
+    0xb2165e1b2565bb5e, 0x62c370b3e7a4d9a2, 0x32e2e11af3114cc2,
+    0xea4ca846a44af95d, 0x2eeb9b0d1e0be906, 0x0e534020e23f1751,
+    0xd741252cc5576730, 0x9f7d6eafe4be899e, 0xb7b8c4e9a986195f,
+    0x7c8bf91a434a6998, 0xd87c33e9f60145f6, 0xcab4596ea9d0d117,
+    0xdba10cc3c3e5becb, 0x98d65c8020821be8, 0xa5de178cdb2409be,
+    0x2381465286e67e5b, 0x7869d85c3921fa27, 0x8a184a4e1bf310f1,
+    0xd58d536a177b55f1, 0x88f9880e7a392d13, 0xab342cb424ad840c,
+    0x8e2ab46dd1384eb7, 0x9ccbacd87db5ba92, 0xcca2305e02df0d12,
+    0xca7ef22fdb3e6950, 0x5c3386e316633d50, 0xd4f1b8d07547fa00,
+    0x46112de027ab3941, 0x0352b799e8621f17, 0x2d2e6b8d48c6a6e4,
+    0xb30e7483f8386396, 0x576ee02125f29c9f, 0x634b9113c0f31e23,
+    0xdcfd18d55e16a625, 0x85821366b4359b41, 0xebed2527d906294d,
+    0xeb37c51961391a34, 0x29611108188bb315, 0x3cde4f975af5f699,
+    0x46a62bcbad70d2e7, 0x9e7f814251026f2b, 0x4eb6fbd2d3ee7ae4,
+    0x82a32a7817c12867, 0xef0c292f5ba84e39, 0x849d6d2140043616,
+    0x807662bf9250ffef, 0x617dcc030448e683, 0x21318bb975849005,
+    0x2e6fd54e323adb4f, 0x9b8d29b8573bae2b, 0x380170fec7c9f9fb,
+    0x97ba91161a6b0a11, 0xbdbadcc05dfba1ac, 0x4c4303eee211d8f2,
+    0xae19e1ea4cfde2d8, 0xef53f1a41256a801, 0xe0bbd4ca56b7d521,
+    0x007a8bc15f4439f8, 0x7bea6a86ad68e83b, 0x91771d1505f30447,
+    0x21b5b66b676370b6, 0xeb12967c8d5f2535, 0x024a5fa411e3ecfd,
+    0xb7eccd38a98b3167, 0x83bfb3ea114f5ab0, 0x2fca700107446ce3,
+    0x5c7f399432516311, 0x7891ee66c664f154, 0x968fad3eb7247bcc,
+    0xfc915930d85b4beb, 0x58f9820e127f4759, 0x3c0a4aa3384ac8db,
+    0xc1f5417d196b3e12, 0x7d680b6ade3118bb, 0x9b429210e51ed8e0,
+    0x4efc95809b8a33be, 0xd5d4e8db6379f920, 0x8169cef81957d8df,
+    0x1f7bfb9f7a8d08cc, 0x4954aa9d798f25cb, 0x83efcb9d744c569b,
+    0x7af5c3320086adbe, 0x29a325c89e39d09e, 0x89fafbbc0ed0eb63,
+    0xe5b4f470e74a827c, 0xa4c9860a38650ebc, 0xafa99ca8cd3b0479,
+    0x6ac38b32e224dcbc, 0x512e00840e525b87, 0x9347d163a35f45d6,
+    0x3edbc7c23cf71775, 0x90653291e03d9b5e, 0xe3cd8d583bf1d964,
+    0x89a9f4f73452dae3, 0x78b361688a6129d5, 0x18f7dbd2e56001f2,
+    0xbf5559bc1a38e0fc, 0x554402b1835e8a24, 0x5edece2d16dff1ef,
+    0xacfac3c20012a807, 0xf4c9cf11b0b7fa95, 0x2d8363001c324a75,
+    0xe1d6c92d9340477e, 0x2615cd69cd422e5c, 0x30389d7bd2042620,
+    0xe3177b389d6896ca, 0x4e060c4623e6099a, 0xd906ab7594a5d71f,
+    0x53fd1fa52bcf74fc, 0x7c94d1b8cb188376, 0x11a48a0723ee3913,
+    0x1facb83155f53636, 0x5eb3ffea0edd087b, 0x0622f72afbdfbca3,
+    0x69cb802769722ab3, 0x25bf8776b6a979ee, 0x71440fb9ff20476d,
+    0x5daf0362cf5dc719, 0xea45008bbfa46c58, 0x32453d3abc1c7355,
+    0x69189ed04d522fe1, 0xfe804475936727ed, 0xea3f393e0ac0a433,
+    0x8d7272247d3e90fc, 0x0d6e1dea0d11c028, 0xaf76da3e78f145e2,
+    0xb8f3ab388a018ee5, 0x0f165eb6d0319a52, 0xe13249edea658d7b,
+    0xbc0a6fce691e0102, 0x0e12af1ee5ade4b0, 0xea610e9eb6703d32,
+    0x47578a13eaeaaffd, 0x2da0a8786244df15, 0x210d7f3a93dc5051,
+    0xe38ce2beaa9df561, 0x26e88004fd89019a, 0xeb652159c7446897,
+    0xd84121357c2d51e0, 0x9ee6f9ab996c1f44, 0xb22b382489a7e293,
+    0x2274273daca04431, 0x50ded0d3251127f8, 0x4f2793954c49a0c5,
+    0xa5e8508ebeb3ade5, 0x9fe6de0208af82b3, 0x6447eb4a6f6b06a0,
+    0x10aba665c4945a3e, 0xf3e078bcabb63951, 0xb9bbb373a6444f5a,
+    0xed33263c3943db93, 0xa3700a2d92c2d894, 0xc3f1414355a195a0,
+    0x3bc25884f8431d94, 0x9ae4bfa78b6412d8, 0xf1f6719bfb757bce,
+    0x385310bdbae35867, 0x2bdc5498ad771aa7, 0x94c9c61b73834f3e,
+    0xa60de5473f490826, 0x0243abafc568251c, 0x5afc2d559e8f76fe,
+    0xdb20b5230ec9244d, 0x2bc97870ee6cc8c0, 0x1947bada4434dab9,
+    0x5613ab3641ad91b9, 0xeba21058ec2ff2cb, 0x0a3a3d7b5c440bbb,
+    0x2ab7c75d5e6deb6b, 0xdfb5c89688b10b83, 0xbf03be923fd248d0,
+    0xaa3d1aa687de91b6, 0x68ba39515047f07f, 0xb937732f5cf0d518,
+    0xe90fc2258f3a0804, 0xd5766f5d0ad1fcd9, 0x2bf31f13d3b10719,
+    0x2514563748562116, 0x2b28f2b01c41dfb4, 0x442d3ebb22f47b2c,
+    0xc78fca1d970df555, 0x17bbc8ef08b2e8ee, 0xb513d14b84478c2b,
+    0x11d5a72cbb02569f, 0x83e0bc6eaa124411, 0xb052613f6f7eba90,
+    0x05c3267c084c329a, 0x4bff9e077de409a2, 0xc9891309d9764f5f,
+    0x37999be7a4da1032, 0x50b19a9d1f90d54b, 0x3df1dd217804cf0f,
+    0x54b282a3e8c90705, 0x64866f19d48efaa4, 0x41da532592b91643,
+    0x2ae0aec368805686, 0xc1b59d3ab08f45a6, 0xe50a48628c44ce94,
+    0x1f162b028328e889, 0xd01900d2317dfc2a, 0xd322921695a28b07,
+    0x55c926c9838a082e, 0x2079ea6a651074fa, 0xae7b4cfeb5bd5d26,
+    0x35a663fe48103541, 0xa2b7ad38844a2b98, 0xa3b22db718f12e3e,
+    0x27f23af6b277f14b, 0x6d44d45855e5d8ef, 0x7b39bb538d3f745a,
+    0x24bda3840207a0ed, 0x92e633ece2262e25, 0x54ef36412802dd88,
+    0x7c8b762c273a80df, 0x6015c1dee6a3ae4d, 0xb4f61790c3779bcf,
+    0xc6aff9f3395af230, 0x7454ad25b2d4934b, 0xca4ae9464bc0aa34,
+    0x28a707585a860e6d, 0x5a0f0f6e9e516da5, 0x34dd0a662a75ac66,
+    0xe5d245d628150747, 0xdce669bd72c8ce43, 0xc17090bd81b074b3,
+    0xdd81ee7d0e6731ed, 0xd1a33f56f62cd509, 0xf86923ecd4480c7c,
+    0xab01d6df46344a8f, 0x86aaa5c4e25ca4a3, 0xafdca4a7d9f4be45,
+    0xc544a896527c19f8, 0x962046e3ea741062, 0x3901545858566b8f,
+    0xa78c261542c0119d, 0x38da855ff3c1b55a, 0x9ed91fc1683821f5,
+    0xec42cad2cf400232, 0x434a1bf96885a6d2, 0x78f25a1b6480c8e4,
+    0xd56dfb81ff3581ec, 0x7e8dd77101765b1a, 0xfafa27fdd7956236,
+    0x4c5572915cde90cd, 0x20d4a45b4b7f110e, 0x48c6f353953ed043,
+    0xdee6d91a76686087, 0x7543c1e533f95b08, 0x5a5bec46ab3f4dc2,
+    0x70e192f39bed62ce, 0x93fc5767ce19e6c5, 0xa7b7de071427a181,
+    0xfe2be507f257e9af, 0x2619ad87c431a8ed, 0x0ea0202340b07f68,
+    0x21486fc6cda7191e, 0x267bc68bcd423d9b, 0x384315bdec4c3cc7,
+    0x5f05352aeb2bc5b7, 0xed3e79d669b55863, 0x2446271a3c4c0400,
+    0x705fd524bcf25f5f, 0x8308c6504b610083, 0xea94c51b20600c4e,
+    0x0886edf395a86b81, 0x8f3ab3851ffea0af, 0xfbaebda3847c7ff2,
+    0x44fb007bd439be06, 0xb5c91681070d7f4c, 0x6bc1dec7d1f8e731,
+    0xe7cb0bd262c5edf1, 0x146b12d56ac906bf, 0x509fa7aa918c3cfa,
+    0x9988a880985d419c, 0x15a3a4c0306a6b1e, 0x2dfc494d9f8ffb8e,
+    0xd26bf57bfe66757b, 0x5c6fe4327cf3c5d4, 0x19f7686d6a24abd3,
+    0xce4ad2b6d32305bb, 0x2fb395c6a538f053, 0x19f34d013d6b81a0,
+    0x3a479586f28d848d, 0x42c52962c765400e, 0xce854d47ba7d298c,
+    0xfedffcdb87a19b5e, 0xe1e67806207377bb, 0x1e01e222ec3d9c8e,
+    0xa5a7c793007d69b9, 0xb37678242fac62c8, 0x6f464b554628d8e9,
+    0x2522a52b003723fa, 0x2a94080d206298c7, 0xf0e299627aec49f7,
+    0x02610fad2c52b586, 0x55ea3f51362f282a, 0xcd0a64a3f3889848,
+    0x9e930f8c444ad445, 0x094714a37c69871d, 0x1256ba783178c337,
+    0x342454c6cf03bad3, 0xdcd7d3dea53c5dd7, 0xb34c7d1fc84bd7cd,
+    0xa0ae00c63a10ab0b, 0xec2e16a4ca36a178, 0x319585e21583d3f8,
+    0xe6fbc514ab163a70, 0xd4f08282a99cdeda, 0x62d6545ec5ddaa5a,
+    0x41ac5a2b635cdcbd, 0x7316418b1efaa05a, 0xee2bf8cf1fef1226,
+    0x5548737a7aee00c3, 0x4ec53cbded0704b7, 0x308776126cc00e65,
+    0x1cb7b2537ab3e9b4, 0x9e76e8c71c1aadd3, 0xe4f88b1c4b6cb86f,
+    0xe0da8ed3d5f07756, 0xc4d31b3e13c80726, 0x87881e9a261bb4ab,
+    0xd5b0177cbd48aa74, 0xc6c63ccbaff07e3d, 0x481e8a564a5cca33,
+    0x208c54b70965ab69, 0x4baf88ae67ce72a5, 0xd3bbe1f95b716bde,
+    0xac76b1c85e48c386, 0x5be48528a19b94ae, 0xca7e315311faf75c,
+    0xe5378fdd264705cc, 0xce487129c79515b3, 0xd0fa02f288f62639,
+    0x098222cb25899065, 0xec30ffb0a4f0870c, 0x941a3141f2a65e26,
+    0x3e516aaf2056d29f, 0x20d5ce3c38aa691a, 0xe1477ab483496128,
+    0x1db7f9630c300a62, 0xd6665ec2133b37f0, 0x87d986925810d776,
+    0xc2fbdc28ceddceca, 0x23a41a25b4509d01, 0x7dc4f3941f222a0b,
+    0xb0784f1ed118aa44, 0x369678c116b35f6d, 0x2d37ce532e75c509,
+    0x1a592d227836870e, 0x95ef44296e4f6c66, 0x1a762a7cbc1da96a,
+    0x421b98edb628d26f, 0xfc699bac5f9fa9b2, 0x445e6a410c1bc920,
+    0xb490c64305d80d35, 0xed04b903df04b991, 0x7613e93f57a4410e,
+    0x18c1df73a9bc4dea, 0x44ac154955a6b15a, 0x020d02df317fccf0,
+    0xbf3c40af5fed7995, 0xbed7f25bc51ab6b5, 0xa3e1b4fc04457aea,
+    0xcd08cd512c677f70, 0xbea31a1ff9d1a9b1, 0x1af39c9048a3a01d,
+    0x8acd8919d68da4cf, 0x9995039e15467cc7, 0x87cd10e8ed4d0aa0,
+    0x90d704ca9d2f9b4c, 0xe1cef9007af1152d, 0x270d70c5b8be5d5a,
+    0xc5ef8050a8bdfa15, 0xe09d7109d5019d69, 0x5c4b9e6ecdd50d1d,
+    0xc3a10c28043ac553, 0x3d015bc159395006, 0x0b91ca617554a97c,
+    0xc93bca26654eb494, 0x5d8e03d6f461aecc, 0x3762ae071a5dcffb,
+    0x32e7a6dc2a0b33a7, 0xb3ad43176ef2843f, 0xbc57995db76bfee6,
+    0x1f4e8dcacea2949e, 0x1a3b8793411ac7bb, 0xa69ab1a9996393df,
+    0xf565527fba769559, 0x080f90f0d53c11d8, 0xb1d6b9fb5f2d8fea,
+    0x2ec4ab1ab88f30a5, 0x07c1e05cbce364f5, 0x8a693805bd1f3af4,
+    0x1a7c287961a8d22b, 0x7ecfa8e5105f3271, 0xdb5d6aed5a166250,
+    0x78907444fddd02ba, 0x6e0da51eca6e277f, 0x6efc4ec181d33e01,
+    0x5f01be94763c5832, 0x7fcaba62fd644048, 0xdbeb62a1f151e096,
+    0x4ecbb4ede2959f68, 0xf359a08c4c94c1ed, 0x97308cf6d5242bd6,
+    0xd422499d753b07d8, 0xe56c573849489272, 0x7069e4fb82999a6f,
+    0x20bbc9b8ff37e064, 0x3f71b9ca74fbfe15, 0x26e716e9602ba886,
+    0x11a5e4a1e68fba47, 0x22e89141042a4c92, 0x3d5f1092a5736d98,
+    0x441e3db7df136b81, 0xef4cd925628ffb7b, 0x965c67ea35eb6e04,
+    0x308da2aba329c892, 0xdf1680a37a136e4d, 0x23d99d23258f36d9,
+    0xbb76a13669829df8, 0xd90f44c7a92753d9, 0x04ad47193f3363ac,
+    0x30d6eadd1185cd74, 0xb88ee0e3e8094fb9, 0x08d245c5bd415dd5,
+    0x9bfbb1f5e3c37a06, 0xb3b1a4b2022b2b5e, 0xecac1662b8f270b5,
+    0x94a87d509027df85, 0xc80d269a650626d6, 0x55c79b8476022cc8,
+    0x4620ea4222276e23, 0x0d4e2ae285dfb42a, 0x8c738b0d2793fc2d,
+    0x58e0b352c7151cca, 0xb2cd277d0fbc10c5, 0xc5bba19d47051022,
+    0xcfd79787aa57f341, 0xadad360ebbcd1ab6, 0x08dd2162d889294f,
+    0xdccad621696c1fbf, 0xd02a8046ec910c21, 0x134e26deaa4edf89,
+    0xf77ea3f2a42d2fe5, 0x95384516840e40d5, 0xbe3ab13018d34a7d,
+    0x694c1c3b32bcca65, 0xde3f91e577bef081, 0xe4c4d4377c89c1c1,
+    0xd80a53cc0a04fc0d, 0xb5f58d4c52e8d7b4, 0x4f90b90f99360164,
+    0x9cb5665f2228efe7, 0x9af1dd636257ee2b, 0x56fb9281bc204866,
+    0x0788e6e8091ac743, 0x9a475c85a133eaec, 0x4bd4657fabe83918,
+    0xb6a3cf2883f57884, 0x0d880db8ef8d2be5, 0x11bc29b42519eac9,
+    0x99ca006a2fbea7de, 0xecc32f2287fd0e7d, 0xdcf6831165778e62,
+    0x68ccf3c6f25824e3, 0xfbc285c3271b3c4c, 0xe02eecbc46bff9f5,
+    0x632e45a0b434c8bd, 0xd12b4db5aa304c5e, 0xeafc6e594ebf60c4,
+    0xffa02db3b6e6edfc, 0x41762052d11615ca, 0x77a736208b082975,
+    0xc70239b91e07fd18, 0x65ec1acff78453d6, 0xf46cecad3d40293d,
+    0xc0d496427244ceb9, 0x270aca85f4214e55, 0x8b6ef4052b88171e,
+    0xfa2049cd7ceaa779, 0x8f4a9ede8b51fe6a, 0xa70aa214cafc7052,
+    0x020ea42d7fd98625, 0xeeeb29f9b316523f, 0xa6bbf588a1b4b83b,
+    0x2b35d571a093da58, 0x4e73b4977809a1bf, 0xca8a3a974d4fc3d8,
+    0x33370b2b5c51c2dc, 0x09e511111002aee8, 0x59c174d902cb00fa,
+    0xf20f33e6ff909b9d, 0x1017f494b9d56cd5, 0x2919cce721a71823,
+    0xfc4c724efd0cb620, 0xac5057904cefd58d, 0x27da534504b7a8f0,
+    0x4d8b3e3660fc59d8, 0x053d05b5424948b9, 0x1319351e2b8921fc,
+    0x89a73398b02d073b, 0x546fbe0025f9cfba, 0x11ca5ddcba7d8369,
+    0xe6fef6dccc2ca6f4, 0x3059baa46164304e, 0x800175f0fc9c6a19,
+    0xd4093c11113f78b8, 0x60a5bd87976e324c, 0x8238bf11d6495e40,
+    0xf6d4ace54d4a8068, 0x2947416027e0c92a, 0x91c5a03cb8ed0af6,
+    0x730d94f749d99ace, 0xe2f81bed68511676, 0x7bd571002fecdf2f,
+    0x16cf61f6ffae39d1, 0xbbef000d95e9830a, 0x07ad1acc4fc7ed84,
+    0x8afc8b4c0e406725, 0x4d2680571f2e6b35, 0x4a86bdde8651a2e6,
+    0x6f453a34e7174d33, 0x2b668a7e170bdb38, 0x30f5e66846fc64d3,
+    0xf05e2539c70e9398, 0x43ffe1444f702239, 0x4c8dcd67b7374573,
+    0xf900516979429fd8, 0xfc20f846d16f33b1, 0xf24e7ae7ccad14b0,
+    0x2aac532d5b2120ef, 0x624431a04b132a40, 0xe5af91ceb3eaf8d7,
+    0x55c1adcf397fe1dc, 0xff4c94620834592d, 0xa193192583743ab2,
+    0xc83196ed86a60156, 0x7a3b8b965edc7bd5, 0xab72caf7a8eaed8b,
+    0xcd29f59c3b64cbe0, 0xadc6965a047a89c8, 0xa33f770fe1bc6334,
+    0xed3bae805c4c5ec9, 0x1d20f4585421eee9, 0x5d5bdeea5469ca3d,
+    0x0692d341ab1e63e8, 0xa996e3725441f100, 0xc15619a7e8a3b3da,
+    0xc1e8c7574ab37528, 0x5d44111e04ff3446, 0x811d056e07ddfbd1,
+    0x94b6c519c555a356, 0xf891bf70e50ecd6d, 0x923d8689b85095c4,
+    0x1ccb4fba77c57327, 0x39ed880ba89a42e0, 0x4c274e58b8e47f91,
+    0xd9ca94178f5fc888, 0xaa0a7b13e823734f, 0xf01c09b840101f3a,
+    0x5bfe0201a923e954, 0x8e7ff7903aa630fa, 0xb4949208e0f23414,
+    0xe8ad80e69a99408e, 0x3fca41c8647ac441, 0x30cb6711ab7192c0,
+    0x4c79e616997b9287, 0xd8b7482cd515b938, 0x69ed40d0bf2f1141,
+    0xeafe2700b3b8366a, 0x12a314048b563bf7, 0x803284980fb63535,
+    0x93aa990d8772cf38, 0x8b0a12bc54f21419, 0xd9c8615cb86cf36c,
+    0xf7e5b77c1e427807, 0x410523bc55cb1365, 0x6d49bf694b2db039,
+    0x9f8c30ec828ceaac, 0x9544d042d69de203, 0xe10ff47eedc7cb7e,
+    0x6464a9cb0d8d79f0, 0x4418290ff3c06a9c, 0xd3ed63061493ea1a,
+    0xf447fcdc5a8dd364, 0xa099c45e9dfcf4c7, 0x960d921ca569ff40,
+    0x20ae4b0ebc23f222, 0x754f0768bf59d01a, 0xfccef54da65cce41,
+    0x6b314ab4b3ef190c, 0x1b87085b32099c02, 0xa34e17a3613d2488,
+    0xafff5fc13e9afda1, 0x324aed7f908e68ae, 0x1bbfd184dd51afe9,
+    0xcfef2428e5fe7c9b, 0x136041ebfc599a58, 0x020b894271fbb4cc,
+    0x1d856b409cbfc139, 0x61b99a2aa9c45786, 0x95eb845340aedef9,
+    0xe7398ec5329d5335, 0x32191d113cfd66df, 0xe96cc809e4d45b23,
+    0x2d2893ebf416dbad, 0xfa679ba2e0c83e74, 0x510edb3f5d47eaf8,
+    0x21e73cca9dfb248a, 0xd7463cf663f95ab3, 0xffd126a39a23b70e,
+    0xf9b23d23eca0402a, 0x7e1fe06e67564b7e, 0xffdc2b9da54577ff,
+    0xa9576f7dbe8e0a0f, 0x2784af230acb7bbf, 0x22a40e5caf25faf8,
+    0xee372c7bd40f2b6e, 0xace368ae6152be85, 0x7e83c208885a8141,
+    0x5c37a16f065389d7, 0x9da872095f561300, 0x87c90400e68d2e33,
+    0xb1f82162e128f0e3, 0xb136572f78aa6e37, 0xb042cbf86dd63e27,
+    0x339bf0b0813536ba, 0x655d596cce02ee3b, 0x042b6337eeb8e955,
+    0xa11005cbfd0986ef, 0xe7c3cf6b0a264d63, 0x31ba2370e2bd7e31,
+    0x4a4833157ba9af50, 0xc5fab4a8e6b804eb, 0x356e56419cb137a6,
+    0x68e86704bf0661dc, 0x98808cbc1e6a7dfd, 0x26c63f8e01a196ab,
+    0x36ba752c75b7bbb4, 0xbaf75ac4520406d7, 0xc44470371882d946,
+    0xfd034c9f8ea3eecd, 0x98b39020940d6e7e, 0x60c2949ebebee8ff,
+    0xc137b81fbf45bd26, 0x712cf9c4c585c321, 0xcaab336c4485a8f7,
+    0x0e12d2893e83d5fb, 0xf21ee79f41925cff, 0x04072dc4ff378eb1,
+    0x378f53b19e03acb8, 0xafa105f9be4cb216, 0x1fb67f27eb5f8037,
+    0x8c3b679454ed343d, 0x239816c9a84e935f, 0xc286e6179ba1a7e0,
+    0xddc47920651293ed, 0xa8c894881ce6d2c6, 0xa32fb43ab797870e,
+    0xf2d329ad495df0c6, 0x544bf4743a59ed3e, 0x71457aac1d6ede59,
+    0x8955249ae96da10f, 0xd99fd5200114492a, 0xbdeb230c816c788e,
+    0xa69f0d5d265d1d20, 0xa070854aac94ed29, 0x794a932cac3eb3e8,
+    0x3d33251f755153e7, 0x0158cc257e0c694f, 0x4b1ed9b0c9bad71b,
+    0x67d0ca7b48d0dcd5, 0xe84171ec0032cb43, 0x9f39068063aaa97c,
+    0xb03ff0116e4f38e6, 0xf66f82b70ab66dcb, 0xf2c2cd7b075cd068,
+    0x93a5754590e1fcaa, 0x1ef79a6d8f18ecc4, 0x9ae6b5a80bf94051,
+    0x6f99de111482a709, 0xeaf91dd5d0ec8035, 0x9bf394d1aa28db73,
+    0xef17554de7935427, 0x70f5fe4dbc6fc707, 0x27b4219f75a70b05,
+    0x73b7022b3501bc23, 0x3e21466b839fba5c, 0x34d3aafc4203983a,
+    0xcd66132eeb60d8cb, 0xd62983bb90730baf, 0x67ee29d542a643ce,
+    0xb6be0f9dfd96424f, 0x5b7491eb4c1dcf1a, 0xee4d0056f3ea2d11,
+    0x674f6421ae5a6311, 0x84a0d8da61f86739, 0xe517cdfde4bdcd45,
+    0x59053f156f0dadc9, 0x156489f29326d7bb, 0x8e947fa40f6bbc1c,
+    0x674ea187fe8c637d, 0xcd48172f989e579b, 0xab09ff8656c8d866,
+    0xf942d079725c8937, 0x9c3a3a633a08cbd3, 0x5a43a0f791d33a97,
+    0xac8cf68b81e93523, 0x0b03d245329e456f, 0x51bb997e8da8c27a,
+    0x19c2cdddf395b9fe, 0xeda21733dbc0484e, 0x86e74efe9949a83b,
+    0xcd0dfdd9c39ad75b, 0x11a6737c84881a09, 0xa21559360e3354a9,
+    0xda14097c82b67154, 0x6abd6387a33193cf, 0x98ca93546021efcb,
+    0x79d35bd38db2e74a, 0x676fded2b71f4d3e, 0xe953b0aacffea80c,
+    0x87b11cb1a2e37511, 0x215dbb363c478a64, 0xc3fabceee7c9e544,
+    0x35221b73fd1defd1, 0x3a6b4cefa8c2c7c7, 0x30dc92ad0bc42579,
+    0x8181031bfa8af0fe, 0x6878b8af51ba0bd9, 0xe6553c13b3d10513,
+    0x6a61058d5cc0013f, 0xaab7cc0a177e2188, 0xab5604f76dce29a5,
+    0xaffc0be51414b371, 0xa1ceccd3fe49ff08, 0xd6e440ac84d7ebe4,
+    0x8688268f0d65ff8c, 0x82901014067d34bf, 0xd9a912a6b9fee9fe,
+    0x1aad0f3bced28b0a, 0xcd4a4608383be2e8, 0xdecd83977a854753,
+    0x5f6b669dec55f221, 0x134285d1d2b1d78b, 0xa66e75043647618a,
+    0xa1307c7b0ea85caf, 0x987d2d763df4fb8a, 0x5ac1d6afc4dc9a51,
+    0x5ff3864eea982d0d, 0x04cb11dd578eb710, 0xd7489a43c744e514,
+    0x28c7063f5c6cd297, 0x35fad4eb306b0606, 0x354d77bcc8008d19,
+    0x27fb5da9a8fef0d1, 0x5312cd5416302df6, 0x0b1529ef2f7cae98,
+    0x2ae720b9ae6bd957, 0x6882e42038972e42, 0xdf2f128340a0f838,
+    0x0a8a195abc4477d5, 0xdb41740633f74803, 0xf8e7203221dc9a9e,
+    0x03d305a35f1e5ddc, 0x00dfe75a91b299b5, 0xf585eaf3b9fdd828,
+    0x1b848494c3dfec39, 0x5095571c97be3d02, 0x42c215e0584a01dd,
+    0xfe2c77ed51b24fd8, 0xa198e64503ea5baf, 0xb65f9fd0d4f12054,
+    0xfd61f26855830e43, 0x5b33dfec1eba0460, 0xf6b8518b54c6f2b2,
+    0xe01b4604317e4878, 0x6847860f5db0f39a, 0x9d25b8a2d29a0f70,
+    0xb9f9a6349c0f780c, 0x3dc1b490167d6aff, 0x33709acd0dbe247a,
+    0xd3d2ec182feede98, 0x480e5f88e2e20029, 0xebde03b861ef0769,
+    0xda395f6b02da66cb, 0xfb397f61375fa028, 0x0e29cadb5c1a7aa3,
+    0x685aab2fcf7fd87b, 0xedae44920f18ce64, 0x47b026a0b4701ebd,
+    0xf69160d0f4ecdc83, 0xe4004b605fbf0281, 0xb52520081ac027e8,
+    0x2fe3f5bcfce7cf96, 0xbf632bc8cc97dec1, 0xe638b2a8b6feb471,
+    0xda96f5005cd21dc9, 0x91376713417b0833, 0x6a8c562b2915eabf,
+    0x92088eaa1153a13b, 0xc1b07bce2d2bdc4f, 0x327514aea91eec26,
+    0x9c334d1b48e217df, 0x1c49928a15468661, 0x11c104e7fb22da80,
+    0x722ceca55e08e209, 0xa5e9633b1088eb7b, 0x32f2d27dfa922aab,
+    0x8dd8dd6558292ec2, 0x552a9d1422d01a04, 0xea6ee3a6c17eb0d5,
+    0x197f2e91090ed8c2, 0xbda4a3d62bb3b48a, 0xac8904e8d84ce60e,
+    0xf87ef221e26d4db0, 0x291f1b68fd0b4423, 0xa76e25e42fd8a011,
+    0x890e637f975c017b, 0xc39aa219aeafc163, 0x3110f535c1aaca0e,
+    0xd401483b933d7601, 0x014be950902bf03f, 0xbe675e6590fee069,
+    0x75926173c192b649, 0x2b0ae0c6be4ef6e7, 0xbbe333478564bf4b,
+    0xa5b8dc43e0064d74, 0xfd9d065cd2876b03, 0x5dade062b21e31c7,
+    0x22a26c627c20727f, 0xaca881bf5e268e94, 0x0d9ba3dc9800e4b9,
+    0x3c0c0944f2f67b8f, 0x7f36876e89206916, 0x7c21f7bbb56d15c7,
+    0xe5ceb33aceda84a0, 0x10d33b09656a49f1, 0xe9a5a28b672c4f44,
+    0x2af925e75c3b9e4c, 0x3341e4b20cf5f6ff, 0x148ae60d1fe37e6a,
+    0xd6c9367b3609a8b6, 0x26f3a5f955e79b7e, 0x129161c994655f6b,
+    0xe0469aa06fdaf054, 0x6e05865d823e7b5d, 0xa2ab2f9c6a07fe59,
+    0x6cd2f28bbc592343, 0x0feaae1e111199f2, 0x662c2cc7ad60fc98,
+    0x69bfa2c36710f904, 0x291ed974d6a110cf, 0xd8cf764a34693132,
+    0xd60146b00eb91440, 0x882e037569249143, 0x891c272f14b482b8,
+    0xc03bc245e52857f5, 0x585e768c723ec277, 0xe525e2fb8d5e10aa,
+    0x66b9143701092233, 0x58fb0f857e21c357, 0xec5e0c5d345567a1,
+    0xf3cdc120987b6946, 0xaa53f522fd7d4c69, 0x8446b5dd2b05f8b7,
+    0x2a330800b6c8cec4, 0x0500e4b0ab306d27, 0x7e7e3feb244bc6f0,
+    0x7725754e52c08de5, 0xe8c1d3d3064c0669, 0x951eb6f64090ebc4,
+    0x8bdbc77b8ced0013, 0x2f848fa5f48451b4, 0x69e0db1b07b8bf51,
+    0x1d86b68811a35227, 0x639fc646d0724f17, 0x01d7e80af04f0675,
+    0x3403fc54e1bd7652, 0x1cec014fbe639222, 0xe7560c098fcfdeca,
+    0x1ef70e6441bb4391, 0x4e7645df0eb94f80, 0x03cb44aa9606254a,
+    0xc76f734c2bab73e0, 0xbe11e3eda9f9b091, 0x700c348e7445c600,
+    0x92dd05baa051d366, 0xc3132ae5977216eb, 0x06c9fe31df261b26,
+    0xd297c34c451b5547, 0xdd7171b6b3554c86, 0xe908596beeb902ef,
+    0x4680dae676d529ad, 0xf3de8fb304fe553d, 0x288eaff8b5c4f3e9,
+    0xa53354434f9be8d6, 0x828db1d7c26c3e98, 0x21171864afa5db1b,
+    0x63ece114cd420ff0, 0xe57cdfd446bb3ade, 0x1fc96b013eb5feb2,
+    0x71f7fc36b0681d82, 0x2fd265740867f5c6, 0xfad2cbc9fe83ef1b,
+    0x5e2d2259a4de7526, 0x434a85c3fefbf4a6, 0x28f0d3ac94ea261d,
+    0xc913d0583a3d33dd, 0x4a955cc9d6acb29e, 0x08ef260e43ce8809,
+    0x919fe9643e16a3c5, 0xf988210bfb971fd3, 0x47a4db5fb8c2b434,
+    0x38fefaa8ffd2ec45, 0x49ad92c4e46d65a6, 0x4514353bb9f9125a,
+    0xdabe1b70ad163e5f, 0xd6c8c71217bc74bd, 0x02c29ac70c083f83,
+    0x67d0973f224b7fac, 0xb20223ae707d36df, 0x5c5ce4564bdb342d,
+    0x310a7c75cf8b86fa, 0x8e72ad037e6e6141, 0x0a0c8828fc87dc42,
+    0xd0cb73d0ff193022, 0x31e46c6c4130989e, 0xf783034f2bd03941,
+    0x5aa884e64531d778, 0xa27920db7f387203, 0x5dad7dfef8ddf3db,
+    0x69ae464882a727ac, 0xbceec35d736a9505, 0xce5d8d607b230532,
+    0x818ad5f0272227a7, 0x4b0733108d1f8406, 0x4ce75a7d229667cf,
+    0xaa33cba2dcaac470, 0xcaeffe576eed0c77, 0x99008bdc666e7666,
+    0xb85ea276201cfc79, 0xadd02de812da8ee4, 0x861cddd9ea9f3998,
+    0x0dce8b30690b253a, 0x42f1d027c7bcf4a1, 0xae2d41b2663d66c4,
+    0x732d72d4bfa3621c, 0x638e6722f4fd9345, 0x47dd4cae32cfcf85,
+    0x7df7059ea7401b5a, 0xeeed3fdb7a84992d, 0xc5668d82500a4450,
+    0xad653de727f1ddc5, 0x3acc8e41dab3b148, 0x11c34748fb20c06e,
+    0x624f4e52cda3a3ac, 0x4ebafae2db6f4bf0, 0x0982ba7003473f71,
+    0x0bbf4688b9430f62, 0x211b45673946ae5f, 0xb82a89a867c886af,
+    0x6b14e4faa48ed749, 0xb1fc3f8165fe7f8b, 0xdf99f8d1da8bad26,
+    0xebed4f38b454f054, 0xbca66527bbdcb772, 0xdda73b04152dcf84,
+    0x6a36786be0c04a82, 0x34c316321caa11a7, 0xc5e3660df39116ed,
+    0x326e398ab1a6e509, 0x8e71d0bc94352a9e, 0x25a6f235ee6d00de,
+    0xc19ea51bef734c98, 0x4119474d6198c8cc, 0x4172530345e8006d,
+    0x4b69dc8cf88ef19c, 0x7d08d0792f8d11f0, 0xc3f49a0ee311e74a,
+    0x02ead598a4373651, 0x46f73af1b1030158, 0x33fe85428bbfffe8,
+    0x5a73064171cf11f7, 0xaf853d7d05bd87e2, 0x33bb55d64fa80d25,
+    0x09d3d7d27d9ff5ac, 0x1aa733495dde2154, 0x4497cf7ee2edc63a,
+    0x42d269c685521f58};
diff --git a/apps/riscv-tests/isa/macros/vector/rvv_debug_macros.h b/apps/riscv-tests/isa/macros/vector/rvv_debug_macros.h
new file mode 100644
index 0000000..3686259
--- /dev/null
+++ b/apps/riscv-tests/isa/macros/vector/rvv_debug_macros.h
@@ -0,0 +1,106 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+
+#ifndef __RVV_DEBUG_MACROS__
+#define __RVV_DEBUG_MACROS__
+
+//Functions to print buffers
+#define PRINT_BUFFER_U64(A)                                    \
+  do {                                                         \
+  for(unsigned int i = 0; i < sizeof(A)/sizeof(uint64_t); i++) \
+    VPRINTF("%016x\n",A[i]);                                   \
+    MEMBARRIER;                                                \
+  } while(0)
+
+#define PRINT_BUFFER_U32(A)                                    \
+  do {                                                         \
+  for(unsigned int i = 0; i < sizeof(A)/sizeof(uint32_t); i++) \
+    VPRINTF("%08x\n",A[i]);                                    \
+    MEMBARRIER;                                                \
+  } while(0)
+
+#define PRINT_BUFFER_U16(A)                                    \
+  do {                                                         \
+  for(unsigned int i = 0; i < sizeof(A)/sizeof(uint16_t); i++) \
+    VPRINTF("%04x\n",A[i]);                                    \
+    MEMBARRIER;                                                \
+  } while(0)
+
+#define PRINT_BUFFER_U8(A)                                    \
+  do {                                                        \
+  for(unsigned int i = 0; i < sizeof(A)/sizeof(uint8_t); i++) \
+    VPRINTF("%02x\n",A[i]);                                   \
+    MEMBARRIER;                                               \
+  } while(0)
+
+#define PRINT_BUFFER_F64(A)                                   \
+  do {                                                        \
+  for(unsigned int i = 0; i < sizeof(A)/sizeof(double); i++)  \
+    VPRINTF("Buffer Debug %d: %.17g\n",i,A[i]);               \
+    MEMBARRIER;                                               \
+  } while(0)
+
+#define PRINT_BUFFER_F32(A)                                   \
+  do {                                                        \
+  for(unsigned int i = 0; i < sizeof(A)/sizeof(float); i++)   \
+    VPRINTF("Buffer Debug %d: %0.9g\n",i,A[i]);               \
+    MEMBARRIER;                                               \
+  } while(0)
+
+//Debuging Macros
+
+#define DEBUG_F64(register)               \
+  do {                                    \
+  double buffer ##register[VLEN_CUR];     \
+  VSTORE_64(register,buffer ##register);  \
+  PRINT_BUFFER_F64(buffer ##register);    \
+  } while(0)
+
+#define DEBUG_F32(register)               \
+  do {                                    \
+  float buffer ##register[VLEN_CUR];      \
+  VSTORE_32(register,buffer ##register);  \
+  PRINT_BUFFER_F32(buffer ##register);    \
+  } while(0)
+
+#define DEBUG_U8(register)               \
+  do {                                   \
+  uint8_t buffer ##register[VLEN_CUR];   \
+  VSTORE_8(register,buffer ##register);  \
+  PRINT_BUFFER_U8(buffer ##register);    \
+  } while(0)
+
+
+#define DEBUG_8(register) DEBUG_U8(register)
+
+#define DEBUG_U16(register)               \
+  do {                                    \
+  uint16_t buffer ##register[VLEN_CUR];   \
+  VSTORE_16(register,buffer ##register);  \
+  PRINT_BUFFER_U16(buffer ##register);    \
+  } while(0)
+
+#define DEBUG_16(register) DEBUG_U16(register)
+
+#define DEBUG_U32(register)               \
+  do {                                    \
+  uint32_t buffer ##register[VLEN_CUR];   \
+  VSTORE_32(register,buffer ##register);  \
+  PRINT_BUFFER_U32(buffer ##register);    \
+  } while(0)
+
+#define DEBUG_32(register) DEBUG_U32(register)
+
+#define DEBUG_U64(register)               \
+  do {                                    \
+  uint64_t buffer ##register[VLEN_CUR];   \
+  VSTORE_64(register,buffer ##register);  \
+  PRINT_BUFFER_U64(buffer ##register);    \
+  } while(0)
+
+#define DEBUG_64(register) DEBUG_U64(register)
+
+#endif // __RVV_DEBUG_MACROS__
diff --git a/apps/riscv-tests/isa/macros/vector/vector_macros.h b/apps/riscv-tests/isa/macros/vector/vector_macros.h
new file mode 100644
index 0000000..9193717
--- /dev/null
+++ b/apps/riscv-tests/isa/macros/vector/vector_macros.h
@@ -0,0 +1,301 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+
+#ifndef __VECTOR_MACROS_H__
+#define __VECTOR_MACROS_H__
+
+#include <stdint.h>
+#include "dataset.h"
+#include "rvv_debug_macros.h"
+#include "encoding.h"
+#include "float_conversion.h"
+
+#ifdef __SPIKE__
+#include <stdio.h>
+
+// We need to activate the FP and V extensions manually
+#define enable_vec() do { asm volatile ("csrs mstatus, %[bits];" :: [bits] "r" (MSTATUS_VS & (MSTATUS_VS >> 1))); } while (0);
+#define enable_fp()  do { asm volatile ("csrs mstatus, %[bits];" :: [bits] "r" (MSTATUS_FS & (MSTATUS_FS >> 1))); } while (0);
+#else
+#include <printf.h>
+
+// The FP and V extensions are activated in the crt0 script
+#define enable_vec()
+#define enable_fp()
+#endif
+
+/**************
+ *  Counters  *
+ **************/
+
+// Counter for how many tests have failed
+int num_failed;
+// Pointer to the current test case
+int test_case;
+
+/************
+ *  Macros  *
+ ************/
+
+#define read_vtype(buf) do { asm volatile ("csrr %[BUF], vtype" : [BUF] "=r" (buf)); } while (0);
+#define read_vl(buf)    do { asm volatile ("csrr %[BUF], vl" : [BUF] "=r" (buf)); } while (0);
+#define read_vxsat(buf) do { asm volatile ("csrr %[BUF], vxsat" : [BUF] "=r" (buf)); } while (0);
+#define reset_vxsat     do { asm volatile ("csrw vxsat, %0" :: "rK"(0)); } while (0);
+#define set_vxrm(val) do { asm volatile ("csrw vxrm, %0" :: "rK"(val)); } while (0);
+
+#define vtype(golden_vtype, vlmul, vsew, vta, vma) (golden_vtype = vlmul << 0 | vsew << 3 | vta << 6 | vma << 7)
+
+// Checking vtype and vl value which is set by configuration setting instructions
+// by comparing with golden_vtype value used as a reference. Also check for
+// illegal values of vlmul and vsew which violtate: ELEN >= SEW/LMUL
+#define check_vtype_vl(casenum, vtype, golden_vtype, avl, vl, vsew, vlmul)                                                     \
+  printf("Checking vtype and vl #%d...\n", casenum); \
+  if((vlmul==5 && (vsew == 1 || vsew == 2 || vsew ==3)) || (vlmul==6 && (vsew == 2 || vsew ==3)) || (vlmul==7 && vsew==3)){   \
+  if((vtype != 0x8000000000000000) || (vl != 0)){    \
+  printf("FAILED. Got vtype = %lx, expected vtype = 8000000000000000. avl = %lx, vl = %lx.\n", vtype,avl, vl);     \
+  return;                                                  \
+  }}                                                        \
+  else if (vtype != golden_vtype || avl != vl) {                                                                        \
+    printf("FAILED. Got vtype = %lx, expected vtype = %lx. avl = %lx, vl = %lx.\n", vtype, golden_vtype, avl, vl); \
+    num_failed++;                                                                                                  \
+    return;                                                                                                        \
+  }                                                                                                                \
+  printf("PASSED.\n");
+
+#define check_vxsat(casenum, vxsat, golden_vxsat)                                                                  \
+  printf("Checking vxsat #%d...\n", casenum);                                                               \
+  if (vxsat != golden_vxsat) {                                                                        \
+    printf("FAILED. Got vxsat = %lx, expected vxsat = %lx.\n", vxsat, golden_vxsat); \
+    num_failed++;                                                                                                  \
+    return;                                                                                                        \
+  }                                                                                                                \
+  printf("PASSED.\n");
+
+// In order to avoid that scalar loads run ahead of vector stores,
+// we use an instruction to ensure that all vector stores have been
+// committed before continuing with scalar memory operations.
+#define MEMORY_BARRIER // asm volatile ("fence");
+
+// Zero-initialized variables can be problematic on bare-metal.
+// Therefore, initialize them during runtime.
+#define INIT_CHECK()  \
+  num_failed = 0;     \
+  test_case  = 0;     \
+
+// Check at the final of the execution whether all the tests passed or not.
+// Returns the number of failed tests.
+#define EXIT_CHECK()                                                \
+  do {                                                              \
+    MEMORY_BARRIER;                                                 \
+    if (num_failed > 0) {                                           \
+      printf("ERROR: %s failed %d tests!\n", __FILE__, num_failed); \
+      return num_failed;                                            \
+    }                                                               \
+    else {                                                          \
+      printf("PASSED: %s!\n", __FILE__);                            \
+      return 0;                                                     \
+    }                                                               \
+  } while(0);                                                       \
+
+// Check the result against a scalar golden value
+#define XCMP(casenum,act,exp)                                           \
+  printf("Checking the results of the test case %d:\n", casenum);       \
+  if (act != exp) {                                                     \
+    printf("Index %d FAILED. Got %d, expected %d.\n", casenum, act, exp);\
+    num_failed++;                                                       \
+    return;                                                             \
+  }                                                                     \
+  printf("PASSED.\n");                                                  \
+
+// Check the result against a floating-point scalar golden value
+#define FCMP(casenum,act,exp)                                           \
+  if(act != exp) {                                                      \
+    printf("Index %d FAILED. Got %lf, expected %lf.\n",casenum, act, exp);       \
+    num_failed++;                                                       \
+    return;                                                             \
+  }                                                                     \
+  printf("PASSED.\n");
+
+// Check the results against a vector of golden values
+#define VCMP(T,str,casenum,vexp,act...)                                               \
+  T vact[] = {act};                                                                   \
+  printf("Checking the results of the test case %d:\n", casenum);                     \
+  MEMORY_BARRIER;                                                                     \
+  for (unsigned int i = 0; i < sizeof(vact)/sizeof(T); i++) {                         \
+    if (vexp[i] != vact[i]) {                                                         \
+      printf("Index %d FAILED. Got "#str", expected "#str".\n", i, vexp[i], vact[i]); \
+      num_failed++;                                                                   \
+      return;                                                                         \
+    }                                                                                 \
+  }                                                                                   \
+  printf("PASSED.\n");
+
+//Macro used to compare large number of elements
+#define LVCMP(T,str,casenum,elements, vexp ,vact)                                     \
+  printf("Checking the results of the test case %d:\n", casenum);                     \
+  MEMORY_BARRIER;                                                                     \
+  for (unsigned int i = 0; i < elements; i++) {                                       \
+    if (vexp[i] != vact[i]) {                                                         \
+      printf("Index %d FAILED. Got "#str", expected "#str".\n", i, vexp[i], vact[i]); \
+      num_failed++;                                                                   \
+      return;                                                                         \
+    }                                                                                 \
+  }                                                                                   \
+  printf("PASSED.\n");
+
+
+// Check the results against an in-memory vector of golden values
+#define VMCMP(T,str,casenum,vexp,vgold,size)                                          \
+  printf("Checking the results of the test case %d:\n", casenum);                     \
+  MEMORY_BARRIER;                                                                     \
+  for (unsigned int i = 0; i < size; i++) {                                           \
+    if (vexp[i] != vgold[i]) {                                                        \
+      printf("Index %d FAILED. Got "#str", expected "#str".\n", i, vexp[i], vgold[i]);\
+      num_failed++;                                                                   \
+      return;                                                                         \
+    }                                                                                 \
+  }                                                                                   \
+  printf("PASSED.\n");
+
+// Macros to set vector length, type and multiplier
+// Don't use this to set VL == 0 since the compiler puts rs1 == x0
+#define VSET(VLEN,VTYPE,LMUL)                                                          \
+  do {                                                                                 \
+  asm volatile ("vsetvli t0, %[A]," #VTYPE "," #LMUL ", ta, ma \n" :: [A] "r" (VLEN)); \
+  } while(0)
+
+// Macros to set vector length equal to zero
+#define VSET_ZERO(VTYPE,LMUL)                                                              \
+  do {                                                                                     \
+    int vset_zero_buf;                                                                     \
+    asm volatile("li %0, 0" : "=r" (vset_zero_buf));                                       \
+    asm volatile("vsetvli x0, %0," #VTYPE "," #LMUL ", ta, ma \n" :: "r" (vset_zero_buf)); \
+  } while(0)
+
+#define VSETMAX(VTYPE,LMUL)                                                            \
+  do {                                                                                 \
+  int64_t scalar = -1;                                                                 \
+  asm volatile ("vsetvli t1, %[A]," #VTYPE "," #LMUL", ta, ma \n":: [A] "r" (scalar)); \
+  } while(0)
+
+// Macro to load a vector register with data from the stack
+#define VLOAD(datatype,loadtype,vreg,vec...)                                \
+  do {                                                                      \
+    volatile datatype V ##vreg[] = {vec};                                   \
+    MEMORY_BARRIER;                                                         \
+    asm volatile ("vl"#loadtype".v "#vreg", (%0)  \n":: [V] "r"(V ##vreg)); \
+  } while(0)
+
+// Macro to store a vector register into the pointer vec
+#define VSTORE(T, storetype, vreg, vec)                                   \
+  do {                                                                    \
+    T* vec ##_t = (T*) vec;                                               \
+    asm volatile ("vs"#storetype".v "#vreg", (%0)\n" : "+r" (vec ##_t));  \
+    MEMORY_BARRIER;                                                       \
+  } while(0)
+
+// Macro to reset the whole register back to zero
+#define VCLEAR(register)                                                                          \
+  do {                                                                                            \
+    MEMORY_BARRIER;                                                                               \
+    uint64_t vtype; uint64_t vl; uint64_t vlmax;                                                  \
+    asm volatile("csrr %[vtype], vtype" : [vtype] "=r" (vtype));                                  \
+    asm volatile("csrr %[vl], vl" : [vl] "=r" (vl));                                              \
+    asm volatile("vsetvl %[vlmax], zero, %[vtype]" : [vlmax] "=r" (vlmax) : [vtype] "r" (vtype)); \
+    asm volatile("vmv.v.i "#register", 0");                                                       \
+    asm volatile("vsetvl zero, %[vl], %[vtype]" :: [vl] "r" (vl), [vtype] "r" (vtype));           \
+  } while(0)
+
+#define VCLEAR_AT_ONE(register)                                                                   \
+  do {                                                                                            \
+    MEMORY_BARRIER;                                                                               \
+    uint64_t vtype; uint64_t vl; uint64_t vlmax;                                                  \
+    asm volatile("csrr %[vtype], vtype" : [vtype] "=r" (vtype));                                  \
+    asm volatile("csrr %[vl], vl" : [vl] "=r" (vl));                                              \
+    asm volatile("vsetvl %[vlmax], zero, %[vtype]" : [vlmax] "=r" (vlmax) : [vtype] "r" (vtype)); \
+    asm volatile("vmv.v.i "#register", -1");                                                       \
+    asm volatile("vsetvl zero, %[vl], %[vtype]" :: [vl] "r" (vl), [vtype] "r" (vtype));           \
+  } while(0)
+
+// Macro to initialize a vector with progressive values from a counter
+#define INIT_MEM_CNT(vec_name, size) \
+  counter = 0;                          \
+  for (int i = 0 ; i < size; i++) {     \
+    vec_name[i] = counter;              \
+    counter++;                          \
+  }                                     \
+
+// Macro to initialize a vector with zeroes
+// The vector is initialized on the stack, use this function with caution
+// Easy to go in the UART address space
+#define INIT_MEM_ZEROES(vec_name, size) \
+  for (int i = 0 ; i < size; i++) {        \
+    vec_name[i] = 0;                       \
+  }                                        \
+
+/***************************
+ *  Type-dependant macros  *
+ ***************************/
+
+// Vector comparison
+#define VCMP_U64(casenum,vect,act...) {VSTORE_U64(vect); VCMP(uint64_t,%x,casenum,Ru64,act)}
+#define VCMP_U32(casenum,vect,act...) {VSTORE_U32(vect); VCMP(uint32_t,%x,casenum,Ru32,act)}
+#define VCMP_U16(casenum,vect,act...) {VSTORE_U16(vect); VCMP(uint16_t,%x,casenum,Ru16,act)}
+#define VCMP_U8(casenum,vect,act...)  {VSTORE_U8(vect) ; VCMP(uint8_t, %x,casenum, Ru8,act)}
+
+#define LVCMP_U8(casenum,vect,act)   {uint64_t vl; read_vl(vl); VSTORE_L8(vect);     \
+                                       LVCMP(uint8_t, %x,casenum,vl, Lu8, act)}
+#define LVCMP_U16(casenum,vect,act)  {uint64_t vl; read_vl(vl); VSTORE_L16(vect);    \
+                                       LVCMP(uint16_t, %x,casenum,vl,Lu16,act)}
+#define LVCMP_U32(casenum,vect,act)  {uint64_t vl; read_vl(vl); VSTORE_L32(vect);    \
+                                       LVCMP(uint32_t, %x,casenum,vl,Lu32,act)}
+#define LVCMP_U64(casenum,vect,act)  {uint64_t vl; read_vl(vl); VSTORE_L64(vect);    \
+                                       LVCMP(uint64_t, %x,casenum,vl,Lu64,act)}
+
+#define VVCMP_U64(casenum,ptr64,act...) {VCMP(uint64_t,%x,casenum,ptr64,act)}
+#define VVCMP_U32(casenum,ptr32,act...) {VCMP(uint32_t,%x,casenum,ptr32,act)}
+#define VVCMP_U16(casenum,ptr16,act...) {VCMP(uint16_t,%x,casenum,ptr16,act)}
+#define VVCMP_U8(casenum,ptr8,act...)   {VCMP(uint8_t, %x,casenum,ptr8, act)}
+
+#define LVVCMP_U64(casenum,ptr64,act) {uint64_t vl; read_vl(vl); LVCMP(uint64_t,%x,casenum,vl, ptr64,act)}
+#define LVVCMP_U32(casenum,ptr32,act) {uint64_t vl; read_vl(vl); LVCMP(uint32_t,%x,casenum,vl, ptr32,act)}
+#define LVVCMP_U16(casenum,ptr16,act) {uint64_t vl; read_vl(vl); LVCMP(uint16_t,%x,casenum,vl, ptr16,act)}
+#define LVVCMP_U8(casenum,ptr8,act)   {uint64_t vl; read_vl(vl); LVCMP(uint8_t, %x,casenum,vl, ptr8, act)}
+
+#define VCMP_I64(casenum,vect,act...) {VSTORE_I64(vect); VCMP(int64_t,%ld, casenum,Ri64,act)}
+#define VCMP_I32(casenum,vect,act...) {VSTORE_I32(vect); VCMP(int32_t,%d,  casenum,Ri32,act)}
+#define VCMP_I16(casenum,vect,act...) {VSTORE_I16(vect); VCMP(int16_t,%hd, casenum,Ri16,act)}
+#define VCMP_I8(casenum,vect,act...)  {VSTORE_I8(vect);  VCMP(int8_t, %hhd,casenum,Ri8, act)}
+
+#define VCMP_F64(casenum,vect,act...) {VSTORE_F64(vect); VCMP(double,%lf,casenum,Rf64,act)}
+#define VCMP_F32(casenum,vect,act...) {VSTORE_F32(vect); VCMP(float, %f ,casenum,Rf32,act)}
+
+// Vector load
+#define VLOAD_64(vreg,vec...) VLOAD(uint64_t,e64,vreg,vec)
+#define VLOAD_32(vreg,vec...) VLOAD(uint32_t,e32,vreg,vec)
+#define VLOAD_16(vreg,vec...) VLOAD(uint16_t,e16,vreg,vec)
+#define VLOAD_8(vreg,vec...)  VLOAD(uint8_t, e8, vreg,vec)
+
+// Vector store
+#define VSTORE_U64(vreg) VSTORE(uint64_t,e64,vreg,Ru64)
+#define VSTORE_U32(vreg) VSTORE(uint32_t,e32,vreg,Ru32)
+#define VSTORE_U16(vreg) VSTORE(uint16_t,e16,vreg,Ru16)
+#define VSTORE_U8(vreg)  VSTORE(uint8_t ,e8 ,vreg,Ru8 )
+
+#define VSTORE_L64(vreg) VSTORE(uint64_t,e64,vreg,Lu64)
+#define VSTORE_L32(vreg) VSTORE(uint32_t,e32,vreg,Lu32)
+#define VSTORE_L16(vreg) VSTORE(uint16_t,e16,vreg,Lu16)
+#define VSTORE_L8(vreg)  VSTORE(uint8_t ,e8 ,vreg,Lu8 )
+
+#define VSTORE_I64(vreg) VSTORE(int64_t,e64,vreg,Ri64)
+#define VSTORE_I32(vreg) VSTORE(int32_t,e32,vreg,Ri32)
+#define VSTORE_I16(vreg) VSTORE(int16_t,e16,vreg,Ri16)
+#define VSTORE_I8(vreg)  VSTORE(int8_t ,e8 ,vreg,Ri8 )
+
+#define VSTORE_F64(vreg) VSTORE(double,e64,vreg,Rf64)
+#define VSTORE_F32(vreg) VSTORE(float, e32,vreg,Rf32)
+
+#endif // __VECTOR_MACROS_H__
diff --git a/apps/riscv-tests/isa/rv32mi/Makefrag b/apps/riscv-tests/isa/rv32mi/Makefrag
new file mode 100644
index 0000000..5ee7edc
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32mi/Makefrag
@@ -0,0 +1,18 @@
+#=======================================================================
+# Makefrag for rv32mi tests
+#-----------------------------------------------------------------------
+
+rv32mi_sc_tests = \
+	breakpoint \
+	csr \
+	mcsr \
+	illegal \
+	ma_fetch \
+	ma_addr \
+	scall \
+	sbreak \
+	shamt \
+
+rv32mi_p_tests = $(addprefix rv32mi-p-, $(rv32mi_sc_tests))
+
+spike32_tests += $(rv32mi_p_tests)
diff --git a/apps/riscv-tests/isa/rv32mi/breakpoint.S b/apps/riscv-tests/isa/rv32mi/breakpoint.S
new file mode 100644
index 0000000..ecbec6a
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32mi/breakpoint.S
@@ -0,0 +1,8 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64M
+#define RVTEST_RV64M RVTEST_RV32M
+#define __MACHINE_MODE
+
+#include "../rv64mi/breakpoint.S"
diff --git a/apps/riscv-tests/isa/rv32mi/csr.S b/apps/riscv-tests/isa/rv32mi/csr.S
new file mode 100644
index 0000000..6361f86
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32mi/csr.S
@@ -0,0 +1,8 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV32M
+#define __MACHINE_MODE
+
+#include "../rv64si/csr.S"
diff --git a/apps/riscv-tests/isa/rv32mi/illegal.S b/apps/riscv-tests/isa/rv32mi/illegal.S
new file mode 100644
index 0000000..e167c71
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32mi/illegal.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64M
+#define RVTEST_RV64M RVTEST_RV32M
+
+#include "../rv64mi/illegal.S"
diff --git a/apps/riscv-tests/isa/rv32mi/ma_addr.S b/apps/riscv-tests/isa/rv32mi/ma_addr.S
new file mode 100644
index 0000000..7575a3f
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32mi/ma_addr.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64M
+#define RVTEST_RV64M RVTEST_RV32M
+
+#include "../rv64mi/ma_addr.S"
diff --git a/apps/riscv-tests/isa/rv32mi/ma_fetch.S b/apps/riscv-tests/isa/rv32mi/ma_fetch.S
new file mode 100644
index 0000000..ec0e0f6
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32mi/ma_fetch.S
@@ -0,0 +1,8 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV32M
+#define __MACHINE_MODE
+
+#include "../rv64si/ma_fetch.S"
diff --git a/apps/riscv-tests/isa/rv32mi/mcsr.S b/apps/riscv-tests/isa/rv32mi/mcsr.S
new file mode 100644
index 0000000..0d5a5cd
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32mi/mcsr.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64M
+#define RVTEST_RV64M RVTEST_RV32M
+
+#include "../rv64mi/mcsr.S"
diff --git a/apps/riscv-tests/isa/rv32mi/sbreak.S b/apps/riscv-tests/isa/rv32mi/sbreak.S
new file mode 100644
index 0000000..c1b127d
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32mi/sbreak.S
@@ -0,0 +1,8 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV32M
+#define __MACHINE_MODE
+
+#include "../rv64si/sbreak.S"
diff --git a/apps/riscv-tests/isa/rv32mi/scall.S b/apps/riscv-tests/isa/rv32mi/scall.S
new file mode 100644
index 0000000..e5b3153
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32mi/scall.S
@@ -0,0 +1,8 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV32M
+#define __MACHINE_MODE
+
+#include "../rv64si/scall.S"
diff --git a/apps/riscv-tests/isa/rv32mi/shamt.S b/apps/riscv-tests/isa/rv32mi/shamt.S
new file mode 100644
index 0000000..622fde4
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32mi/shamt.S
@@ -0,0 +1,44 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# shamt.S
+#-----------------------------------------------------------------------------
+#
+# Test illegal shamt[5] of shift instruction in 32-bit ISA.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32M
+RVTEST_CODE_BEGIN
+
+  # Make sure slli with shamt[4] set is legal.
+  TEST_CASE( 2, a0, 65536, li a0, 1; slli a0, a0, 16);
+
+  # Make sure slli with shamt[5] set is not legal.
+  TEST_CASE( 3, x0, 1, .word 0x02051513); # slli a0, a0, 32
+
+  TEST_PASSFAIL
+
+.global mtvec_handler
+mtvec_handler:
+  # Trapping on test 3 is good.
+  # Note that since the test didn't complete, TESTNUM is smaller by 1.
+  li t0, 2
+  bne TESTNUM, t0, fail
+
+  # Make sure CAUSE indicates an illegal instructino.
+  csrr t0, mcause
+  li t1, CAUSE_ILLEGAL_INSTRUCTION
+  bne t0, t1, fail
+  j pass
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv32si/Makefrag b/apps/riscv-tests/isa/rv32si/Makefrag
new file mode 100644
index 0000000..f423788
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32si/Makefrag
@@ -0,0 +1,15 @@
+#=======================================================================
+# Makefrag for rv32si tests
+#-----------------------------------------------------------------------
+
+rv32si_sc_tests = \
+	csr \
+	dirty \
+	ma_fetch \
+	scall \
+	sbreak \
+	wfi \
+
+rv32si_p_tests = $(addprefix rv32si-p-, $(rv32si_sc_tests))
+
+spike32_tests += $(rv32si_p_tests)
diff --git a/apps/riscv-tests/isa/rv32si/csr.S b/apps/riscv-tests/isa/rv32si/csr.S
new file mode 100644
index 0000000..3c414c0
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32si/csr.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV32S
+
+#include "../rv64si/csr.S"
diff --git a/apps/riscv-tests/isa/rv32si/dirty.S b/apps/riscv-tests/isa/rv32si/dirty.S
new file mode 100644
index 0000000..bdbc1e4
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32si/dirty.S
@@ -0,0 +1,10 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64M
+#define RVTEST_RV64M RVTEST_RV32M
+
+#undef SATP_MODE_SV39
+#define SATP_MODE_SV39 SATP_MODE_SV32
+
+#include "../rv64si/dirty.S"
diff --git a/apps/riscv-tests/isa/rv32si/ma_fetch.S b/apps/riscv-tests/isa/rv32si/ma_fetch.S
new file mode 100644
index 0000000..2e5254f
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32si/ma_fetch.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV32S
+
+#include "../rv64si/ma_fetch.S"
diff --git a/apps/riscv-tests/isa/rv32si/sbreak.S b/apps/riscv-tests/isa/rv32si/sbreak.S
new file mode 100644
index 0000000..3dcfba2
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32si/sbreak.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV32S
+
+#include "../rv64si/sbreak.S"
diff --git a/apps/riscv-tests/isa/rv32si/scall.S b/apps/riscv-tests/isa/rv32si/scall.S
new file mode 100644
index 0000000..5b732c8
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32si/scall.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV32S
+
+#include "../rv64si/scall.S"
diff --git a/apps/riscv-tests/isa/rv32si/wfi.S b/apps/riscv-tests/isa/rv32si/wfi.S
new file mode 100644
index 0000000..8bc9279
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32si/wfi.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV32S
+
+#include "../rv64si/wfi.S"
diff --git a/apps/riscv-tests/isa/rv32ua/Makefrag b/apps/riscv-tests/isa/rv32ua/Makefrag
new file mode 100644
index 0000000..575dc6a
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ua/Makefrag
@@ -0,0 +1,12 @@
+#=======================================================================
+# Makefrag for rv32ua tests
+#-----------------------------------------------------------------------
+
+rv32ua_sc_tests = \
+	amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoxor_w amoswap_w \
+	lrsc \
+
+rv32ua_p_tests = $(addprefix rv32ua-p-, $(rv32ua_sc_tests))
+rv32ua_v_tests = $(addprefix rv32ua-v-, $(rv32ua_sc_tests))
+
+spike32_tests += $(rv32ua_p_tests) $(rv32ua_v_tests)
diff --git a/apps/riscv-tests/isa/rv32ua/amoadd_w.S b/apps/riscv-tests/isa/rv32ua/amoadd_w.S
new file mode 100644
index 0000000..df4560d
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ua/amoadd_w.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ua/amoadd_w.S"
diff --git a/apps/riscv-tests/isa/rv32ua/amoand_w.S b/apps/riscv-tests/isa/rv32ua/amoand_w.S
new file mode 100644
index 0000000..b824483
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ua/amoand_w.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ua/amoand_w.S"
diff --git a/apps/riscv-tests/isa/rv32ua/amomax_w.S b/apps/riscv-tests/isa/rv32ua/amomax_w.S
new file mode 100644
index 0000000..899d7d6
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ua/amomax_w.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ua/amomax_w.S"
diff --git a/apps/riscv-tests/isa/rv32ua/amomaxu_w.S b/apps/riscv-tests/isa/rv32ua/amomaxu_w.S
new file mode 100644
index 0000000..662f023
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ua/amomaxu_w.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ua/amomaxu_w.S"
diff --git a/apps/riscv-tests/isa/rv32ua/amomin_w.S b/apps/riscv-tests/isa/rv32ua/amomin_w.S
new file mode 100644
index 0000000..cbd88e6
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ua/amomin_w.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ua/amomin_w.S"
diff --git a/apps/riscv-tests/isa/rv32ua/amominu_w.S b/apps/riscv-tests/isa/rv32ua/amominu_w.S
new file mode 100644
index 0000000..acb0d79
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ua/amominu_w.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ua/amominu_w.S"
diff --git a/apps/riscv-tests/isa/rv32ua/amoor_w.S b/apps/riscv-tests/isa/rv32ua/amoor_w.S
new file mode 100644
index 0000000..0a2a57d
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ua/amoor_w.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ua/amoor_w.S"
diff --git a/apps/riscv-tests/isa/rv32ua/amoswap_w.S b/apps/riscv-tests/isa/rv32ua/amoswap_w.S
new file mode 100644
index 0000000..722b7bc
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ua/amoswap_w.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ua/amoswap_w.S"
diff --git a/apps/riscv-tests/isa/rv32ua/amoxor_w.S b/apps/riscv-tests/isa/rv32ua/amoxor_w.S
new file mode 100644
index 0000000..1858d7e
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ua/amoxor_w.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ua/amoxor_w.S"
diff --git a/apps/riscv-tests/isa/rv32ua/lrsc.S b/apps/riscv-tests/isa/rv32ua/lrsc.S
new file mode 100644
index 0000000..695a5c8
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ua/lrsc.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ua/lrsc.S"
diff --git a/apps/riscv-tests/isa/rv32uc/Makefrag b/apps/riscv-tests/isa/rv32uc/Makefrag
new file mode 100644
index 0000000..0586843
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32uc/Makefrag
@@ -0,0 +1,11 @@
+#=======================================================================
+# Makefrag for rv32uc tests
+#-----------------------------------------------------------------------
+
+rv32uc_sc_tests = \
+	rvc \
+
+rv32uc_p_tests = $(addprefix rv32uc-p-, $(rv32uc_sc_tests))
+rv32uc_v_tests = $(addprefix rv32uc-v-, $(rv32uc_sc_tests))
+
+spike32_tests += $(rv32uc_p_tests) $(rv32uc_v_tests)
diff --git a/apps/riscv-tests/isa/rv32uc/rvc.S b/apps/riscv-tests/isa/rv32uc/rvc.S
new file mode 100644
index 0000000..debbbd8
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32uc/rvc.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64uc/rvc.S"
diff --git a/apps/riscv-tests/isa/rv32ud/Makefrag b/apps/riscv-tests/isa/rv32ud/Makefrag
new file mode 100644
index 0000000..998078d
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ud/Makefrag
@@ -0,0 +1,15 @@
+#=======================================================================
+# Makefrag for rv32ud tests
+#-----------------------------------------------------------------------
+
+rv32ud_sc_tests = \
+	fadd fdiv fclass fcmp fcvt fcvt_w fmadd fmin \
+	ldst recoding \
+
+# TODO: use this line instead of the last of the previous once move and structural tests have been implemented
+#        ldst move structural recoding \
+
+rv32ud_p_tests = $(addprefix rv32ud-p-, $(rv32ud_sc_tests))
+rv32ud_v_tests = $(addprefix rv32ud-v-, $(rv32ud_sc_tests))
+
+spike32_tests += $(rv32ud_p_tests) $(rv32ud_v_tests)
diff --git a/apps/riscv-tests/isa/rv32ud/fadd.S b/apps/riscv-tests/isa/rv32ud/fadd.S
new file mode 100644
index 0000000..5fb9090
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ud/fadd.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64ud/fadd.S"
diff --git a/apps/riscv-tests/isa/rv32ud/fclass.S b/apps/riscv-tests/isa/rv32ud/fclass.S
new file mode 100644
index 0000000..c960ad6
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ud/fclass.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64ud/fclass.S"
diff --git a/apps/riscv-tests/isa/rv32ud/fcmp.S b/apps/riscv-tests/isa/rv32ud/fcmp.S
new file mode 100644
index 0000000..55d1c3a
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ud/fcmp.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64ud/fcmp.S"
diff --git a/apps/riscv-tests/isa/rv32ud/fcvt.S b/apps/riscv-tests/isa/rv32ud/fcvt.S
new file mode 100644
index 0000000..8811b6e
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ud/fcvt.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64ud/fcvt.S"
diff --git a/apps/riscv-tests/isa/rv32ud/fcvt_w.S b/apps/riscv-tests/isa/rv32ud/fcvt_w.S
new file mode 100644
index 0000000..3447530
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ud/fcvt_w.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64uf/fcvt_w.S"
diff --git a/apps/riscv-tests/isa/rv32ud/fdiv.S b/apps/riscv-tests/isa/rv32ud/fdiv.S
new file mode 100644
index 0000000..793e51a
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ud/fdiv.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64ud/fdiv.S"
diff --git a/apps/riscv-tests/isa/rv32ud/fmadd.S b/apps/riscv-tests/isa/rv32ud/fmadd.S
new file mode 100644
index 0000000..e60934c
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ud/fmadd.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64ud/fmadd.S"
diff --git a/apps/riscv-tests/isa/rv32ud/fmin.S b/apps/riscv-tests/isa/rv32ud/fmin.S
new file mode 100644
index 0000000..c80c880
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ud/fmin.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64ud/fmin.S"
diff --git a/apps/riscv-tests/isa/rv32ud/ldst.S b/apps/riscv-tests/isa/rv32ud/ldst.S
new file mode 100644
index 0000000..e39fe30
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ud/ldst.S
@@ -0,0 +1,42 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# ldst.S
+#-----------------------------------------------------------------------------
+#
+# This test verifies that flw, fld, fsw, and fsd work properly.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32UF
+RVTEST_CODE_BEGIN
+
+  la s0, tdat
+  TEST_CASE_D32(2, a0, a1, 0x40000000bf800000, fld f2, 0(s0); fsd f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0))
+  TEST_CASE_D32(3, a0, a1, 0x40000000bf800000, fld f2, 0(s0); fsw f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0))
+  TEST_CASE_D32(4, a0, a1, 0x40000000bf800000, flw f2, 0(s0); fsw f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0))
+  TEST_CASE_D32(5, a0, a1, 0xc080000040400000, fld f2, 8(s0); fsd f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0))
+  TEST_CASE_D32(6, a0, a1, 0xffffffff40400000, flw f2, 8(s0); fsd f2, 16(s0); lw a0, 16(s0); lw a1, 20(s0))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+tdat:
+.word 0xbf800000
+.word 0x40000000
+.word 0x40400000
+.word 0xc0800000
+.word 0xdeadbeef
+.word 0xcafebabe
+.word 0xabad1dea
+.word 0x1337d00d
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv32ud/move.S b/apps/riscv-tests/isa/rv32ud/move.S
new file mode 100644
index 0000000..4551ffd
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ud/move.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64ud/move.S"
diff --git a/apps/riscv-tests/isa/rv32ud/recoding.S b/apps/riscv-tests/isa/rv32ud/recoding.S
new file mode 100644
index 0000000..5dc0113
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ud/recoding.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64uf/recoding.S"
diff --git a/apps/riscv-tests/isa/rv32uf/Makefrag b/apps/riscv-tests/isa/rv32uf/Makefrag
new file mode 100644
index 0000000..7dde664
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32uf/Makefrag
@@ -0,0 +1,12 @@
+#=======================================================================
+# Makefrag for rv32uf tests
+#-----------------------------------------------------------------------
+
+rv32uf_sc_tests = \
+	fadd fdiv fclass fcmp fcvt fcvt_w fmadd fmin \
+	ldst move recoding \
+
+rv32uf_p_tests = $(addprefix rv32uf-p-, $(rv32uf_sc_tests))
+rv32uf_v_tests = $(addprefix rv32uf-v-, $(rv32uf_sc_tests))
+
+spike32_tests += $(rv32uf_p_tests) $(rv32uf_v_tests)
diff --git a/apps/riscv-tests/isa/rv32uf/fadd.S b/apps/riscv-tests/isa/rv32uf/fadd.S
new file mode 100644
index 0000000..b832c3d
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32uf/fadd.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64uf/fadd.S"
diff --git a/apps/riscv-tests/isa/rv32uf/fclass.S b/apps/riscv-tests/isa/rv32uf/fclass.S
new file mode 100644
index 0000000..19bbcc5
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32uf/fclass.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64uf/fclass.S"
diff --git a/apps/riscv-tests/isa/rv32uf/fcmp.S b/apps/riscv-tests/isa/rv32uf/fcmp.S
new file mode 100644
index 0000000..2dbf451
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32uf/fcmp.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64uf/fcmp.S"
diff --git a/apps/riscv-tests/isa/rv32uf/fcvt.S b/apps/riscv-tests/isa/rv32uf/fcvt.S
new file mode 100644
index 0000000..627f1f2
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32uf/fcvt.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64uf/fcvt.S"
diff --git a/apps/riscv-tests/isa/rv32uf/fcvt_w.S b/apps/riscv-tests/isa/rv32uf/fcvt_w.S
new file mode 100644
index 0000000..3447530
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32uf/fcvt_w.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64uf/fcvt_w.S"
diff --git a/apps/riscv-tests/isa/rv32uf/fdiv.S b/apps/riscv-tests/isa/rv32uf/fdiv.S
new file mode 100644
index 0000000..12aaa3d
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32uf/fdiv.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64uf/fdiv.S"
diff --git a/apps/riscv-tests/isa/rv32uf/fmadd.S b/apps/riscv-tests/isa/rv32uf/fmadd.S
new file mode 100644
index 0000000..8a5aacb
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32uf/fmadd.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64uf/fmadd.S"
diff --git a/apps/riscv-tests/isa/rv32uf/fmin.S b/apps/riscv-tests/isa/rv32uf/fmin.S
new file mode 100644
index 0000000..9231d01
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32uf/fmin.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64uf/fmin.S"
diff --git a/apps/riscv-tests/isa/rv32uf/ldst.S b/apps/riscv-tests/isa/rv32uf/ldst.S
new file mode 100644
index 0000000..01f7fef
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32uf/ldst.S
@@ -0,0 +1,38 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# ldst.S
+#-----------------------------------------------------------------------------
+#
+# This test verifies that flw, fld, fsw, and fsd work properly.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32UF
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a0, 0x40000000, la a1, tdat; flw f1, 4(a1); fsw f1, 20(a1); lw a0, 20(a1))
+  TEST_CASE(3, a0, 0xbf800000, la a1, tdat; flw f1, 0(a1); fsw f1, 24(a1); lw a0, 24(a1))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+tdat:
+.word 0xbf800000
+.word 0x40000000
+.word 0x40400000
+.word 0xc0800000
+.word 0xdeadbeef
+.word 0xcafebabe
+.word 0xabad1dea
+.word 0x1337d00d
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv32uf/move.S b/apps/riscv-tests/isa/rv32uf/move.S
new file mode 100644
index 0000000..949da6f
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32uf/move.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64uf/move.S"
diff --git a/apps/riscv-tests/isa/rv32uf/recoding.S b/apps/riscv-tests/isa/rv32uf/recoding.S
new file mode 100644
index 0000000..5dc0113
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32uf/recoding.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64UF
+#define RVTEST_RV64UF RVTEST_RV32UF
+
+#include "../rv64uf/recoding.S"
diff --git a/apps/riscv-tests/isa/rv32ui/Makefrag b/apps/riscv-tests/isa/rv32ui/Makefrag
new file mode 100644
index 0000000..7903b15
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ui/Makefrag
@@ -0,0 +1,27 @@
+#=======================================================================
+# Makefrag for rv32ui tests
+#-----------------------------------------------------------------------
+
+rv32ui_sc_tests = \
+	simple \
+	add addi \
+	and andi \
+	auipc \
+	beq bge bgeu blt bltu bne \
+	fence_i \
+	jal jalr \
+	lb lbu lh lhu lw \
+	lui \
+	or ori \
+	sb sh sw \
+	sll slli \
+	slt slti sltiu sltu \
+	sra srai \
+	srl srli \
+	sub \
+	xor xori \
+
+rv32ui_p_tests = $(addprefix rv32ui-p-, $(rv32ui_sc_tests))
+rv32ui_v_tests = $(addprefix rv32ui-v-, $(rv32ui_sc_tests))
+
+spike32_tests += $(rv32ui_p_tests) $(rv32ui_v_tests)
diff --git a/apps/riscv-tests/isa/rv32ui/add.S b/apps/riscv-tests/isa/rv32ui/add.S
new file mode 100644
index 0000000..3ab883d
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ui/add.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ui/add.S"
diff --git a/apps/riscv-tests/isa/rv32ui/addi.S b/apps/riscv-tests/isa/rv32ui/addi.S
new file mode 100644
index 0000000..fa80a68
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ui/addi.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ui/addi.S"
diff --git a/apps/riscv-tests/isa/rv32ui/and.S b/apps/riscv-tests/isa/rv32ui/and.S
new file mode 100644
index 0000000..4ee105b
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ui/and.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ui/and.S"
diff --git a/apps/riscv-tests/isa/rv32ui/andi.S b/apps/riscv-tests/isa/rv32ui/andi.S
new file mode 100644
index 0000000..e6b1529
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ui/andi.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ui/andi.S"
diff --git a/apps/riscv-tests/isa/rv32ui/auipc.S b/apps/riscv-tests/isa/rv32ui/auipc.S
new file mode 100644
index 0000000..0827f7d
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ui/auipc.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ui/auipc.S"
diff --git a/apps/riscv-tests/isa/rv32ui/beq.S b/apps/riscv-tests/isa/rv32ui/beq.S
new file mode 100644
index 0000000..7c3996d
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ui/beq.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ui/beq.S"
diff --git a/apps/riscv-tests/isa/rv32ui/bge.S b/apps/riscv-tests/isa/rv32ui/bge.S
new file mode 100644
index 0000000..d47c304
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ui/bge.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ui/bge.S"
diff --git a/apps/riscv-tests/isa/rv32ui/bgeu.S b/apps/riscv-tests/isa/rv32ui/bgeu.S
new file mode 100644
index 0000000..560ec45
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ui/bgeu.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ui/bgeu.S"
diff --git a/apps/riscv-tests/isa/rv32ui/blt.S b/apps/riscv-tests/isa/rv32ui/blt.S
new file mode 100644
index 0000000..72017dd
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ui/blt.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ui/blt.S"
diff --git a/apps/riscv-tests/isa/rv32ui/bltu.S b/apps/riscv-tests/isa/rv32ui/bltu.S
new file mode 100644
index 0000000..80f7468
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ui/bltu.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ui/bltu.S"
diff --git a/apps/riscv-tests/isa/rv32ui/bne.S b/apps/riscv-tests/isa/rv32ui/bne.S
new file mode 100644
index 0000000..ddb7d9f
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ui/bne.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ui/bne.S"
diff --git a/apps/riscv-tests/isa/rv32ui/fence_i.S b/apps/riscv-tests/isa/rv32ui/fence_i.S
new file mode 100644
index 0000000..cd1dbc3
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ui/fence_i.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ui/fence_i.S"
diff --git a/apps/riscv-tests/isa/rv32ui/jal.S b/apps/riscv-tests/isa/rv32ui/jal.S
new file mode 100644
index 0000000..93f407b
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ui/jal.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ui/jal.S"
diff --git a/apps/riscv-tests/isa/rv32ui/jalr.S b/apps/riscv-tests/isa/rv32ui/jalr.S
new file mode 100644
index 0000000..59f6425
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ui/jalr.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ui/jalr.S"
diff --git a/apps/riscv-tests/isa/rv32ui/lb.S b/apps/riscv-tests/isa/rv32ui/lb.S
new file mode 100644
index 0000000..6cf4d44
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ui/lb.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ui/lb.S"
diff --git a/apps/riscv-tests/isa/rv32ui/lbu.S b/apps/riscv-tests/isa/rv32ui/lbu.S
new file mode 100644
index 0000000..a479a0f
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ui/lbu.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ui/lbu.S"
diff --git a/apps/riscv-tests/isa/rv32ui/lh.S b/apps/riscv-tests/isa/rv32ui/lh.S
new file mode 100644
index 0000000..f1b2390
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ui/lh.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ui/lh.S"
diff --git a/apps/riscv-tests/isa/rv32ui/lhu.S b/apps/riscv-tests/isa/rv32ui/lhu.S
new file mode 100644
index 0000000..775765f
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ui/lhu.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ui/lhu.S"
diff --git a/apps/riscv-tests/isa/rv32ui/lui.S b/apps/riscv-tests/isa/rv32ui/lui.S
new file mode 100644
index 0000000..a127d61
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ui/lui.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ui/lui.S"
diff --git a/apps/riscv-tests/isa/rv32ui/lw.S b/apps/riscv-tests/isa/rv32ui/lw.S
new file mode 100644
index 0000000..3b747d8
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ui/lw.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ui/lw.S"
diff --git a/apps/riscv-tests/isa/rv32ui/or.S b/apps/riscv-tests/isa/rv32ui/or.S
new file mode 100644
index 0000000..1cf5674
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ui/or.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ui/or.S"
diff --git a/apps/riscv-tests/isa/rv32ui/ori.S b/apps/riscv-tests/isa/rv32ui/ori.S
new file mode 100644
index 0000000..3399649
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ui/ori.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ui/ori.S"
diff --git a/apps/riscv-tests/isa/rv32ui/sb.S b/apps/riscv-tests/isa/rv32ui/sb.S
new file mode 100644
index 0000000..b2f99ac
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ui/sb.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ui/sb.S"
diff --git a/apps/riscv-tests/isa/rv32ui/sh.S b/apps/riscv-tests/isa/rv32ui/sh.S
new file mode 100644
index 0000000..eb5a72d
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ui/sh.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ui/sh.S"
diff --git a/apps/riscv-tests/isa/rv32ui/simple.S b/apps/riscv-tests/isa/rv32ui/simple.S
new file mode 100644
index 0000000..20e5546
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ui/simple.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ui/simple.S"
diff --git a/apps/riscv-tests/isa/rv32ui/sll.S b/apps/riscv-tests/isa/rv32ui/sll.S
new file mode 100644
index 0000000..237df9e
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ui/sll.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ui/sll.S"
diff --git a/apps/riscv-tests/isa/rv32ui/slli.S b/apps/riscv-tests/isa/rv32ui/slli.S
new file mode 100644
index 0000000..5f950e1
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ui/slli.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ui/slli.S"
diff --git a/apps/riscv-tests/isa/rv32ui/slt.S b/apps/riscv-tests/isa/rv32ui/slt.S
new file mode 100644
index 0000000..64a3dd9
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ui/slt.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ui/slt.S"
diff --git a/apps/riscv-tests/isa/rv32ui/slti.S b/apps/riscv-tests/isa/rv32ui/slti.S
new file mode 100644
index 0000000..7484505
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ui/slti.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ui/slti.S"
diff --git a/apps/riscv-tests/isa/rv32ui/sltiu.S b/apps/riscv-tests/isa/rv32ui/sltiu.S
new file mode 100644
index 0000000..4185f9b
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ui/sltiu.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ui/sltiu.S"
diff --git a/apps/riscv-tests/isa/rv32ui/sltu.S b/apps/riscv-tests/isa/rv32ui/sltu.S
new file mode 100644
index 0000000..bd92b26
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ui/sltu.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ui/sltu.S"
diff --git a/apps/riscv-tests/isa/rv32ui/sra.S b/apps/riscv-tests/isa/rv32ui/sra.S
new file mode 100644
index 0000000..08abe19
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ui/sra.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ui/sra.S"
diff --git a/apps/riscv-tests/isa/rv32ui/srai.S b/apps/riscv-tests/isa/rv32ui/srai.S
new file mode 100644
index 0000000..b62a880
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ui/srai.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ui/srai.S"
diff --git a/apps/riscv-tests/isa/rv32ui/srl.S b/apps/riscv-tests/isa/rv32ui/srl.S
new file mode 100644
index 0000000..c0ac841
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ui/srl.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ui/srl.S"
diff --git a/apps/riscv-tests/isa/rv32ui/srli.S b/apps/riscv-tests/isa/rv32ui/srli.S
new file mode 100644
index 0000000..ef0203b
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ui/srli.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ui/srli.S"
diff --git a/apps/riscv-tests/isa/rv32ui/sub.S b/apps/riscv-tests/isa/rv32ui/sub.S
new file mode 100644
index 0000000..330f478
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ui/sub.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ui/sub.S"
diff --git a/apps/riscv-tests/isa/rv32ui/sw.S b/apps/riscv-tests/isa/rv32ui/sw.S
new file mode 100644
index 0000000..3098133
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ui/sw.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ui/sw.S"
diff --git a/apps/riscv-tests/isa/rv32ui/xor.S b/apps/riscv-tests/isa/rv32ui/xor.S
new file mode 100644
index 0000000..a9c1e41
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ui/xor.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ui/xor.S"
diff --git a/apps/riscv-tests/isa/rv32ui/xori.S b/apps/riscv-tests/isa/rv32ui/xori.S
new file mode 100644
index 0000000..9e71152
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32ui/xori.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
+
+#include "../rv64ui/xori.S"
diff --git a/apps/riscv-tests/isa/rv32um/Makefrag b/apps/riscv-tests/isa/rv32um/Makefrag
new file mode 100644
index 0000000..1391c6a
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32um/Makefrag
@@ -0,0 +1,13 @@
+#=======================================================================
+# Makefrag for rv32um tests
+#-----------------------------------------------------------------------
+
+rv32um_sc_tests = \
+	div divu \
+	mul mulh mulhsu mulhu \
+	rem remu \
+
+rv32um_p_tests = $(addprefix rv32um-p-, $(rv32um_sc_tests))
+rv32um_v_tests = $(addprefix rv32um-v-, $(rv32um_sc_tests))
+
+spike32_tests += $(rv32um_p_tests) $(rv32um_v_tests)
diff --git a/apps/riscv-tests/isa/rv32um/div.S b/apps/riscv-tests/isa/rv32um/div.S
new file mode 100644
index 0000000..24dc9ff
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32um/div.S
@@ -0,0 +1,41 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# div.S
+#-----------------------------------------------------------------------------
+#
+# Test div instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2, div,  3,  20,   6 );
+  TEST_RR_OP( 3, div, -3, -20,   6 );
+  TEST_RR_OP( 4, div, -3,  20,  -6 );
+  TEST_RR_OP( 5, div,  3, -20,  -6 );
+
+  TEST_RR_OP( 6, div, -1<<31, -1<<31,  1 );
+  TEST_RR_OP( 7, div, -1<<31, -1<<31, -1 );
+
+  TEST_RR_OP( 8, div, -1, -1<<31, 0 );
+  TEST_RR_OP( 9, div, -1,      1, 0 );
+  TEST_RR_OP(10, div, -1,      0, 0 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv32um/divu.S b/apps/riscv-tests/isa/rv32um/divu.S
new file mode 100644
index 0000000..cd348c9
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32um/divu.S
@@ -0,0 +1,41 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# divu.S
+#-----------------------------------------------------------------------------
+#
+# Test divu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2, divu,                   3,  20,   6 );
+  TEST_RR_OP( 3, divu,           715827879, -20,   6 );
+  TEST_RR_OP( 4, divu,                   0,  20,  -6 );
+  TEST_RR_OP( 5, divu,                   0, -20,  -6 );
+
+  TEST_RR_OP( 6, divu, -1<<31, -1<<31,  1 );
+  TEST_RR_OP( 7, divu,     0,  -1<<31, -1 );
+
+  TEST_RR_OP( 8, divu, -1, -1<<31, 0 );
+  TEST_RR_OP( 9, divu, -1,      1, 0 );
+  TEST_RR_OP(10, divu, -1,      0, 0 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv32um/mul.S b/apps/riscv-tests/isa/rv32um/mul.S
new file mode 100644
index 0000000..0368629
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32um/mul.S
@@ -0,0 +1,84 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# mul.S
+#-----------------------------------------------------------------------------
+#
+# Test mul instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP(32,  mul, 0x00001200, 0x00007e00, 0xb6db6db7 );
+  TEST_RR_OP(33,  mul, 0x00001240, 0x00007fc0, 0xb6db6db7 );
+
+  TEST_RR_OP( 2,  mul, 0x00000000, 0x00000000, 0x00000000 );
+  TEST_RR_OP( 3,  mul, 0x00000001, 0x00000001, 0x00000001 );
+  TEST_RR_OP( 4,  mul, 0x00000015, 0x00000003, 0x00000007 );
+
+  TEST_RR_OP( 5,  mul, 0x00000000, 0x00000000, 0xffff8000 );
+  TEST_RR_OP( 6,  mul, 0x00000000, 0x80000000, 0x00000000 );
+  TEST_RR_OP( 7,  mul, 0x00000000, 0x80000000, 0xffff8000 );
+
+  TEST_RR_OP(30,  mul, 0x0000ff7f, 0xaaaaaaab, 0x0002fe7d );
+  TEST_RR_OP(31,  mul, 0x0000ff7f, 0x0002fe7d, 0xaaaaaaab );
+
+  TEST_RR_OP(34,  mul, 0x00000000, 0xff000000, 0xff000000 );
+
+  TEST_RR_OP(35,  mul, 0x00000001, 0xffffffff, 0xffffffff );
+  TEST_RR_OP(36,  mul, 0xffffffff, 0xffffffff, 0x00000001 );
+  TEST_RR_OP(37,  mul, 0xffffffff, 0x00000001, 0xffffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 8, mul, 143, 13, 11 );
+  TEST_RR_SRC2_EQ_DEST( 9, mul, 154, 14, 11 );
+  TEST_RR_SRC12_EQ_DEST( 10, mul, 169, 13 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 11, 0, mul, 143, 13, 11 );
+  TEST_RR_DEST_BYPASS( 12, 1, mul, 154, 14, 11 );
+  TEST_RR_DEST_BYPASS( 13, 2, mul, 165, 15, 11 );
+
+  TEST_RR_SRC12_BYPASS( 14, 0, 0, mul, 143, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 15, 0, 1, mul, 154, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 16, 0, 2, mul, 165, 15, 11 );
+  TEST_RR_SRC12_BYPASS( 17, 1, 0, mul, 143, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 18, 1, 1, mul, 154, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 19, 2, 0, mul, 165, 15, 11 );
+
+  TEST_RR_SRC21_BYPASS( 20, 0, 0, mul, 143, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 21, 0, 1, mul, 154, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 22, 0, 2, mul, 165, 15, 11 );
+  TEST_RR_SRC21_BYPASS( 23, 1, 0, mul, 143, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 24, 1, 1, mul, 154, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 25, 2, 0, mul, 165, 15, 11 );
+
+  TEST_RR_ZEROSRC1( 26, mul, 0, 31 );
+  TEST_RR_ZEROSRC2( 27, mul, 0, 32 );
+  TEST_RR_ZEROSRC12( 28, mul, 0 );
+  TEST_RR_ZERODEST( 29, mul, 33, 34 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv32um/mulh.S b/apps/riscv-tests/isa/rv32um/mulh.S
new file mode 100644
index 0000000..e583f5f
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32um/mulh.S
@@ -0,0 +1,81 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# mulh.S
+#-----------------------------------------------------------------------------
+#
+# Test mulh instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  mulh, 0x00000000, 0x00000000, 0x00000000 );
+  TEST_RR_OP( 3,  mulh, 0x00000000, 0x00000001, 0x00000001 );
+  TEST_RR_OP( 4,  mulh, 0x00000000, 0x00000003, 0x00000007 );
+
+  TEST_RR_OP( 5,  mulh, 0x00000000, 0x00000000, 0xffff8000 );
+  TEST_RR_OP( 6,  mulh, 0x00000000, 0x80000000, 0x00000000 );
+  TEST_RR_OP( 7,  mulh, 0x00000000, 0x80000000, 0x00000000 );
+
+  TEST_RR_OP(30,  mulh, 0xffff0081, 0xaaaaaaab, 0x0002fe7d );
+  TEST_RR_OP(31,  mulh, 0xffff0081, 0x0002fe7d, 0xaaaaaaab );
+
+  TEST_RR_OP(32,  mulh, 0x00010000, 0xff000000, 0xff000000 );
+
+  TEST_RR_OP(33,  mulh, 0x00000000, 0xffffffff, 0xffffffff );
+  TEST_RR_OP(34,  mulh, 0xffffffff, 0xffffffff, 0x00000001 );
+  TEST_RR_OP(35,  mulh, 0xffffffff, 0x00000001, 0xffffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 8, mulh, 36608, 13<<20, 11<<20 );
+  TEST_RR_SRC2_EQ_DEST( 9, mulh, 39424, 14<<20, 11<<20 );
+  TEST_RR_SRC12_EQ_DEST( 10, mulh, 43264, 13<<20 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 11, 0, mulh, 36608, 13<<20, 11<<20 );
+  TEST_RR_DEST_BYPASS( 12, 1, mulh, 39424, 14<<20, 11<<20 );
+  TEST_RR_DEST_BYPASS( 13, 2, mulh, 42240, 15<<20, 11<<20 );
+
+  TEST_RR_SRC12_BYPASS( 14, 0, 0, mulh, 36608, 13<<20, 11<<20 );
+  TEST_RR_SRC12_BYPASS( 15, 0, 1, mulh, 39424, 14<<20, 11<<20 );
+  TEST_RR_SRC12_BYPASS( 16, 0, 2, mulh, 42240, 15<<20, 11<<20 );
+  TEST_RR_SRC12_BYPASS( 17, 1, 0, mulh, 36608, 13<<20, 11<<20 );
+  TEST_RR_SRC12_BYPASS( 18, 1, 1, mulh, 39424, 14<<20, 11<<20 );
+  TEST_RR_SRC12_BYPASS( 19, 2, 0, mulh, 42240, 15<<20, 11<<20 );
+
+  TEST_RR_SRC21_BYPASS( 20, 0, 0, mulh, 36608, 13<<20, 11<<20 );
+  TEST_RR_SRC21_BYPASS( 21, 0, 1, mulh, 39424, 14<<20, 11<<20 );
+  TEST_RR_SRC21_BYPASS( 22, 0, 2, mulh, 42240, 15<<20, 11<<20 );
+  TEST_RR_SRC21_BYPASS( 23, 1, 0, mulh, 36608, 13<<20, 11<<20 );
+  TEST_RR_SRC21_BYPASS( 24, 1, 1, mulh, 39424, 14<<20, 11<<20 );
+  TEST_RR_SRC21_BYPASS( 25, 2, 0, mulh, 42240, 15<<20, 11<<20 );
+
+  TEST_RR_ZEROSRC1( 26, mulh, 0, 31<<26 );
+  TEST_RR_ZEROSRC2( 27, mulh, 0, 32<<26 );
+  TEST_RR_ZEROSRC12( 28, mulh, 0 );
+  TEST_RR_ZERODEST( 29, mulh, 33<<20, 34<<20 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv32um/mulhsu.S b/apps/riscv-tests/isa/rv32um/mulhsu.S
new file mode 100644
index 0000000..28b3690
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32um/mulhsu.S
@@ -0,0 +1,83 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# mulhsu.S
+#-----------------------------------------------------------------------------
+#
+# Test mulhsu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  mulhsu, 0x00000000, 0x00000000, 0x00000000 );
+  TEST_RR_OP( 3,  mulhsu, 0x00000000, 0x00000001, 0x00000001 );
+  TEST_RR_OP( 4,  mulhsu, 0x00000000, 0x00000003, 0x00000007 );
+
+  TEST_RR_OP( 5,  mulhsu, 0x00000000, 0x00000000, 0xffff8000 );
+  TEST_RR_OP( 6,  mulhsu, 0x00000000, 0x80000000, 0x00000000 );
+  TEST_RR_OP( 7,  mulhsu, 0x80004000, 0x80000000, 0xffff8000 );
+
+  TEST_RR_OP(30,  mulhsu, 0xffff0081, 0xaaaaaaab, 0x0002fe7d );
+  TEST_RR_OP(31,  mulhsu, 0x0001fefe, 0x0002fe7d, 0xaaaaaaab );
+
+  TEST_RR_OP(32,  mulhsu, 0xff010000, 0xff000000, 0xff000000 );
+
+  TEST_RR_OP(33,  mulhsu, 0xffffffff, 0xffffffff, 0xffffffff );
+  TEST_RR_OP(34,  mulhsu, 0xffffffff, 0xffffffff, 0x00000001 );
+  TEST_RR_OP(35,  mulhsu, 0x00000000, 0x00000001, 0xffffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 8, mulhsu, 36608, 13<<20, 11<<20 );
+  TEST_RR_SRC2_EQ_DEST( 9, mulhsu, 39424, 14<<20, 11<<20 );
+  TEST_RR_SRC12_EQ_DEST( 10, mulhsu, 43264, 13<<20 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 11, 0, mulhsu, 36608, 13<<20, 11<<20 );
+  TEST_RR_DEST_BYPASS( 12, 1, mulhsu, 39424, 14<<20, 11<<20 );
+  TEST_RR_DEST_BYPASS( 13, 2, mulhsu, 42240, 15<<20, 11<<20 );
+
+  TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhsu, 36608, 13<<20, 11<<20 );
+  TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhsu, 39424, 14<<20, 11<<20 );
+  TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhsu, 42240, 15<<20, 11<<20 );
+  TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhsu, 36608, 13<<20, 11<<20 );
+  TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhsu, 39424, 14<<20, 11<<20 );
+  TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhsu, 42240, 15<<20, 11<<20 );
+
+  TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhsu, 36608, 13<<20, 11<<20 );
+  TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhsu, 39424, 14<<20, 11<<20 );
+  TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhsu, 42240, 15<<20, 11<<20 );
+  TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhsu, 36608, 13<<20, 11<<20 );
+  TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhsu, 39424, 14<<20, 11<<20 );
+  TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhsu, 42240, 15<<20, 11<<20 );
+
+  TEST_RR_ZEROSRC1( 26, mulhsu, 0, 31<<26 );
+  TEST_RR_ZEROSRC2( 27, mulhsu, 0, 32<<26 );
+  TEST_RR_ZEROSRC12( 28, mulhsu, 0 );
+  TEST_RR_ZERODEST( 29, mulhsu, 33<<20, 34<<20 );
+
+
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv32um/mulhu.S b/apps/riscv-tests/isa/rv32um/mulhu.S
new file mode 100644
index 0000000..601dcff
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32um/mulhu.S
@@ -0,0 +1,82 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# mulhu.S
+#-----------------------------------------------------------------------------
+#
+# Test mulhu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  mulhu, 0x00000000, 0x00000000, 0x00000000 );
+  TEST_RR_OP( 3,  mulhu, 0x00000000, 0x00000001, 0x00000001 );
+  TEST_RR_OP( 4,  mulhu, 0x00000000, 0x00000003, 0x00000007 );
+
+  TEST_RR_OP( 5,  mulhu, 0x00000000, 0x00000000, 0xffff8000 );
+  TEST_RR_OP( 6,  mulhu, 0x00000000, 0x80000000, 0x00000000 );
+  TEST_RR_OP( 7,  mulhu, 0x7fffc000, 0x80000000, 0xffff8000 );
+
+  TEST_RR_OP(30,  mulhu, 0x0001fefe, 0xaaaaaaab, 0x0002fe7d );
+  TEST_RR_OP(31,  mulhu, 0x0001fefe, 0x0002fe7d, 0xaaaaaaab );
+
+  TEST_RR_OP(32,  mulhu, 0xfe010000, 0xff000000, 0xff000000 );
+
+  TEST_RR_OP(33,  mulhu, 0xfffffffe, 0xffffffff, 0xffffffff );
+  TEST_RR_OP(34,  mulhu, 0x00000000, 0xffffffff, 0x00000001 );
+  TEST_RR_OP(35,  mulhu, 0x00000000, 0x00000001, 0xffffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 8, mulhu, 36608, 13<<20, 11<<20 );
+  TEST_RR_SRC2_EQ_DEST( 9, mulhu, 39424, 14<<20, 11<<20 );
+  TEST_RR_SRC12_EQ_DEST( 10, mulhu, 43264, 13<<20 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 11, 0, mulhu, 36608, 13<<20, 11<<20 );
+  TEST_RR_DEST_BYPASS( 12, 1, mulhu, 39424, 14<<20, 11<<20 );
+  TEST_RR_DEST_BYPASS( 13, 2, mulhu, 42240, 15<<20, 11<<20 );
+
+  TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhu, 36608, 13<<20, 11<<20 );
+  TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhu, 39424, 14<<20, 11<<20 );
+  TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhu, 42240, 15<<20, 11<<20 );
+  TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhu, 36608, 13<<20, 11<<20 );
+  TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhu, 39424, 14<<20, 11<<20 );
+  TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhu, 42240, 15<<20, 11<<20 );
+
+  TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhu, 36608, 13<<20, 11<<20 );
+  TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhu, 39424, 14<<20, 11<<20 );
+  TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhu, 42240, 15<<20, 11<<20 );
+  TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhu, 36608, 13<<20, 11<<20 );
+  TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhu, 39424, 14<<20, 11<<20 );
+  TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhu, 42240, 15<<20, 11<<20 );
+
+  TEST_RR_ZEROSRC1( 26, mulhu, 0, 31<<26 );
+  TEST_RR_ZEROSRC2( 27, mulhu, 0, 32<<26 );
+  TEST_RR_ZEROSRC12( 28, mulhu, 0 );
+  TEST_RR_ZERODEST( 29, mulhu, 33<<20, 34<<20 );
+
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv32um/rem.S b/apps/riscv-tests/isa/rv32um/rem.S
new file mode 100644
index 0000000..7955736
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32um/rem.S
@@ -0,0 +1,41 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# rem.S
+#-----------------------------------------------------------------------------
+#
+# Test rem instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2, rem,  2,  20,   6 );
+  TEST_RR_OP( 3, rem, -2, -20,   6 );
+  TEST_RR_OP( 4, rem,  2,  20,  -6 );
+  TEST_RR_OP( 5, rem, -2, -20,  -6 );
+
+  TEST_RR_OP( 6, rem,  0, -1<<31,  1 );
+  TEST_RR_OP( 7, rem,  0, -1<<31, -1 );
+
+  TEST_RR_OP( 8, rem, -1<<31, -1<<31, 0 );
+  TEST_RR_OP( 9, rem,      1,      1, 0 );
+  TEST_RR_OP(10, rem,      0,      0, 0 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv32um/remu.S b/apps/riscv-tests/isa/rv32um/remu.S
new file mode 100644
index 0000000..a96cfc1
--- /dev/null
+++ b/apps/riscv-tests/isa/rv32um/remu.S
@@ -0,0 +1,41 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# remu.S
+#-----------------------------------------------------------------------------
+#
+# Test remu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2, remu,   2,  20,   6 );
+  TEST_RR_OP( 3, remu,   2, -20,   6 );
+  TEST_RR_OP( 4, remu,  20,  20,  -6 );
+  TEST_RR_OP( 5, remu, -20, -20,  -6 );
+
+  TEST_RR_OP( 6, remu,      0, -1<<31,  1 );
+  TEST_RR_OP( 7, remu, -1<<31, -1<<31, -1 );
+
+  TEST_RR_OP( 8, remu, -1<<31, -1<<31, 0 );
+  TEST_RR_OP( 9, remu,      1,      1, 0 );
+  TEST_RR_OP(10, remu,      0,      0, 0 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64mi/Makefrag b/apps/riscv-tests/isa/rv64mi/Makefrag
new file mode 100644
index 0000000..c81c24e
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64mi/Makefrag
@@ -0,0 +1,18 @@
+#=======================================================================
+# Makefrag for rv64mi tests
+#-----------------------------------------------------------------------
+
+rv64mi_sc_tests = \
+	access \
+	breakpoint \
+	csr \
+	mcsr \
+	illegal \
+	ma_fetch \
+	ma_addr \
+	scall \
+	sbreak \
+
+rv64mi_p_tests = $(addprefix rv64mi-p-, $(rv64mi_sc_tests))
+
+spike_tests += $(rv64mi_p_tests)
diff --git a/apps/riscv-tests/isa/rv64mi/access.S b/apps/riscv-tests/isa/rv64mi/access.S
new file mode 100644
index 0000000..40a28d3
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64mi/access.S
@@ -0,0 +1,70 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# access.S
+#-----------------------------------------------------------------------------
+#
+# Test access-exception behavior.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64M
+RVTEST_CODE_BEGIN
+
+  .align 2
+
+  # Flipping just the MSB should result in an illegal address for RV64.
+  la t2, fail
+  li t0, 1 << (__riscv_xlen - 1)
+  xor t0, t0, t2
+
+  # jalr to an illegal address should commit (hence should write rd).
+  # after the pc is set to rs1, an access exception should be raised.
+  li TESTNUM, 2
+  li t1, CAUSE_FETCH_ACCESS
+  la s1, 1f
+  li t2, 0
+  jalr t2, t0
+1:
+
+  # A load to an illegal address should not commit.
+  li TESTNUM, 3
+  li t1, CAUSE_LOAD_ACCESS
+  la s1, 1f
+  mv t2, s1
+  lb t2, (t0)
+  j fail
+1:
+
+  j pass
+
+  TEST_PASSFAIL
+
+  .align 2
+  .global mtvec_handler
+mtvec_handler:
+  li a0, 2
+  beq TESTNUM, a0, 2f
+  li a0, 3
+  beq TESTNUM, a0, 2f
+  j fail
+
+2:
+  bne t2, s1, fail
+
+  csrr t2, mcause
+  bne t2, t1, fail
+
+  csrw mepc, s1
+  mret
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64mi/breakpoint.S b/apps/riscv-tests/isa/rv64mi/breakpoint.S
new file mode 100644
index 0000000..252a696
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64mi/breakpoint.S
@@ -0,0 +1,129 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# breakpoint.S
+#-----------------------------------------------------------------------------
+#
+# Test breakpoints, if they are implemented.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64M
+RVTEST_CODE_BEGIN
+
+  # Set up breakpoint to trap on M-mode fetches.
+  li TESTNUM, 2
+
+  # Skip tselect if hard-wired.
+  csrw tselect, x0
+  csrr a1, tselect
+  bne x0, a1, pass
+
+  la a2, 1f
+  csrw tdata2, a2
+  li a0, (2 << (__riscv_xlen - 4)) | MCONTROL_M | MCONTROL_EXECUTE
+  csrw tdata1, a0
+  # Skip if breakpoint type is unsupported.
+  csrr a1, tdata1
+  bne a0, a1, 2f
+  .align 2
+1:
+  # Trap handler should skip this instruction.
+  beqz x0, fail
+
+  # Make sure reads don't trap.
+  li TESTNUM, 3
+  lw a0, (a2)
+
+2:
+  # Set up breakpoint to trap on M-mode reads.
+  li TESTNUM, 4
+  li a0, (2 << (__riscv_xlen - 4)) | MCONTROL_M | MCONTROL_LOAD
+  csrw tdata1, a0
+  # Skip if breakpoint type is unsupported.
+  csrr a1, tdata1
+  bne a0, a1, 2f
+  la a2, data1
+  csrw tdata2, a2
+
+  # Trap handler should skip this instruction.
+  lw a2, (a2)
+  beqz a2, fail
+
+  # Make sure writes don't trap.
+  li TESTNUM, 5
+  sw x0, (a2)
+
+2:
+  # Set up breakpoint to trap on M-mode stores.
+  li TESTNUM, 6
+  li a0, (2 << (__riscv_xlen - 4)) |  MCONTROL_M | MCONTROL_STORE
+  csrw tdata1, a0
+  # Skip if breakpoint type is unsupported.
+  csrr a1, tdata1
+  bne a0, a1, 2f
+
+  # Trap handler should skip this instruction.
+  sw a2, (a2)
+
+  # Make sure store didn't succeed.
+  li TESTNUM, 7
+  lw a2, (a2)
+  bnez a2, fail
+
+  # Try to set up a second breakpoint.
+  li a0, 1
+  csrw tselect, a0
+  csrr a1, tselect
+  bne a0, a1, pass
+
+  li a0, (2 << (__riscv_xlen - 4)) | MCONTROL_M | MCONTROL_LOAD
+  csrw tdata1, a0
+  la a3, data2
+  csrw tdata2, a3
+
+  # Make sure the second breakpoint triggers.
+  li TESTNUM, 8
+  lw a3, (a3)
+  beqz a3, fail
+
+  # Make sure the first breakpoint still triggers.
+  li TESTNUM, 10
+  la a2, data1
+  sw a2, (a2)
+  li TESTNUM, 11
+  lw a2, (a2)
+  bnez a2, fail
+
+2:
+  TEST_PASSFAIL
+
+  .align 2
+  .global mtvec_handler
+mtvec_handler:
+  # Only even-numbered tests should trap.
+  andi t0, TESTNUM, 1
+  bnez t0, fail
+
+  li t0, CAUSE_BREAKPOINT
+  csrr t1, mcause
+  bne t0, t1, fail
+
+  csrr t0, mepc
+  addi t0, t0, 4
+  csrw mepc, t0
+  mret
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+data1: .word 0
+data2: .word 0
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64mi/csr.S b/apps/riscv-tests/isa/rv64mi/csr.S
new file mode 100644
index 0000000..77e7619
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64mi/csr.S
@@ -0,0 +1,8 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV64M
+#define __MACHINE_MODE
+
+#include "../rv64si/csr.S"
diff --git a/apps/riscv-tests/isa/rv64mi/illegal.S b/apps/riscv-tests/isa/rv64mi/illegal.S
new file mode 100644
index 0000000..5531570
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64mi/illegal.S
@@ -0,0 +1,195 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# illegal.S
+#-----------------------------------------------------------------------------
+#
+# Test illegal instruction trap.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64M
+RVTEST_CODE_BEGIN
+
+  .align 2
+  .option norvc
+
+  li TESTNUM, 2
+bad2:
+  .word 0
+  j fail
+
+  # Skip the rest of the test if S-mode is not present.
+  li t0, MSTATUS_MPP
+  csrc mstatus, t0
+  li t1, (MSTATUS_MPP & -MSTATUS_MPP) * PRV_S
+  csrs mstatus, t1
+  csrr t2, mstatus
+  and t2, t2, t0
+  bne t1, t2, pass
+
+  # Test vectored interrupts if they are supported.
+test_vectored_interrupts:
+  csrwi mip, MIP_SSIP
+  csrwi mie, MIP_SSIP
+  la t0, mtvec_handler + 1
+  csrrw s0, mtvec, t0
+  csrr t0, mtvec
+  andi t0, t0, 1
+  beqz t0, msip
+  csrsi mstatus, MSTATUS_MIE
+1:
+  j 1b
+msip:
+  csrw mtvec, s0
+
+  # Delegate supervisor software interrupts so WFI won't stall.
+  csrwi mideleg, MIP_SSIP
+  # Enter supervisor mode.
+  la t0, 1f
+  csrw mepc, t0
+  li t0, MSTATUS_MPP
+  csrc mstatus, t0
+  li t1, (MSTATUS_MPP & -MSTATUS_MPP) * PRV_S
+  csrs mstatus, t1
+  mret
+
+1:
+  # Make sure WFI doesn't trap when TW=0.
+  wfi
+bad3:
+  .word 0
+  j fail
+
+bad4:
+  # Make sure WFI does trap when TW=1.
+  wfi
+  j fail
+
+  # Make sure SFENCE.VMA and sptbr don't trap when TVM=0.
+  sfence.vma
+  csrr t0, sptbr
+bad5:
+  .word 0
+  j fail
+
+bad6:
+  # Make sure SFENCE.VMA and sptbr do trap when TVM=1.
+  sfence.vma
+  j fail
+bad7:
+  csrr t0, sptbr
+  j fail
+
+  # Make sure SRET doesn't trap when TSR=0.
+  la t0, bad8
+  csrw sepc, t0
+  li t0, SSTATUS_SPP
+  csrs sstatus, t0
+  li t0, SSTATUS_SPIE
+  csrc sstatus, t0
+  sret
+bad8:
+  .word 0
+  j fail
+
+  # Make sure SRET does trap when TSR=1.
+  la t0, 1f
+  csrw sepc, t0
+bad9:
+  sret
+1:
+  j fail
+
+  TEST_PASSFAIL
+
+  .align 8
+  .global mtvec_handler
+mtvec_handler:
+  j synchronous_exception
+  j msip
+  j fail
+  j fail
+  j fail
+  j fail
+  j fail
+  j fail
+  j fail
+  j fail
+  j fail
+  j fail
+  j fail
+  j fail
+  j fail
+  j fail
+
+synchronous_exception:
+  li t1, CAUSE_ILLEGAL_INSTRUCTION
+  csrr t0, mcause
+  bne t0, t1, fail
+  csrr t0, mepc
+
+  # Make sure mtval contains either 0 or the instruction word.
+  csrr t2, mbadaddr
+  beqz t2, 1f
+  lhu t1, 0(t0)
+  xor t2, t2, t1
+  lhu t1, 2(t0)
+  slli t1, t1, 16
+  xor t2, t2, t1
+  bnez t2, fail
+1:
+
+  la t1, bad2
+  beq t0, t1, 2f
+  la t1, bad3
+  beq t0, t1, 3f
+  la t1, bad4
+  beq t0, t1, 4f
+  la t1, bad5
+  beq t0, t1, 5f
+  la t1, bad6
+  beq t0, t1, 6f
+  la t1, bad7
+  beq t0, t1, 7f
+  la t1, bad8
+  beq t0, t1, 8f
+  la t1, bad9
+  beq t0, t1, 9f
+  j fail
+2:
+4:
+6:
+7:
+  addi t0, t0, 8
+  csrw mepc, t0
+  mret
+
+3:
+  li t1, MSTATUS_TW
+  csrs mstatus, t1
+  j 2b
+
+5:
+  li t1, MSTATUS_TVM
+  csrs mstatus, t1
+  j 2b
+
+8:
+  li t1, MSTATUS_TSR
+  csrs mstatus, t1
+  j 2b
+
+9:
+  j 2b
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64mi/ma_addr.S b/apps/riscv-tests/isa/rv64mi/ma_addr.S
new file mode 100644
index 0000000..721ac6a
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64mi/ma_addr.S
@@ -0,0 +1,126 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# ma_addr.S
+#-----------------------------------------------------------------------------
+#
+# Test misaligned ld/st trap.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64M
+RVTEST_CODE_BEGIN
+
+  .align 2
+  .option norvc
+
+  la s0, data
+
+  # indicate it's a load test
+  li s1, CAUSE_MISALIGNED_LOAD
+
+#define SEXT(x, n) ((-((x) >> ((n)-1)) << (n)) | ((x) & ((1 << (n))-1)))
+
+/* Check that a misaligned load either writes the correct value, or
+   takes an exception and performs no writeback.  */
+#define MISALIGNED_LOAD_TEST(testnum, insn, base, offset, res) \
+  li TESTNUM, testnum; \
+  la t2, 1f; \
+  addi t1, base, offset; \
+  insn t1, offset(base); \
+  li t2, res; \
+  bne t1, t2, fail; \
+1:
+
+  MISALIGNED_LOAD_TEST(2,  lh,  s0, 1, SEXT(0xbbcc, 16))
+  MISALIGNED_LOAD_TEST(3,  lhu, s0, 1, 0xbbcc)
+  MISALIGNED_LOAD_TEST(4,  lw,  s0, 1, SEXT(0x99aabbcc, 32))
+  MISALIGNED_LOAD_TEST(5,  lw,  s0, 2, SEXT(0x8899aabb, 32))
+  MISALIGNED_LOAD_TEST(6,  lw,  s0, 3, SEXT(0x778899aa, 32))
+
+#if __riscv_xlen == 64
+  MISALIGNED_LOAD_TEST(7,  lwu, s0, 1, 0x99aabbcc)
+  MISALIGNED_LOAD_TEST(8,  lwu, s0, 2, 0x8899aabb)
+  MISALIGNED_LOAD_TEST(9,  lwu, s0, 3, 0x778899aa)
+
+  MISALIGNED_LOAD_TEST(10, ld, s0, 1, 0x5566778899aabbcc)
+  MISALIGNED_LOAD_TEST(11, ld, s0, 2, 0x445566778899aabb)
+  MISALIGNED_LOAD_TEST(12, ld, s0, 3, 0x33445566778899aa)
+  MISALIGNED_LOAD_TEST(13, ld, s0, 4, 0x2233445566778899)
+  MISALIGNED_LOAD_TEST(14, ld, s0, 5, 0x1122334455667788)
+  MISALIGNED_LOAD_TEST(15, ld, s0, 6, 0xee11223344556677)
+  MISALIGNED_LOAD_TEST(16, ld, s0, 7, 0xffee112233445566)
+#endif
+
+  # indicate it's a store test
+  li s1, CAUSE_MISALIGNED_STORE
+
+/* Check that a misaligned store has some effect and takes no exception,
+   or takes no effect and generates an exception.  This is not very
+   thorough.  */
+#define MISALIGNED_STORE_TEST(testnum, insn, base, offset, size) \
+  li TESTNUM, testnum; \
+  la t2, 1f; \
+  addi t1, base, offset; \
+  insn x0, offset(base); \
+  lb t1, (offset - 1)(base); \
+  beqz t1, fail; \
+  lb t1, (offset + size)(base); \
+  beqz t1, fail; \
+  lb t1, (offset + 0)(base); \
+  bnez t1, fail; \
+  lb t1, (offset + size - 1)(base); \
+  bnez t1, fail; \
+1:
+
+  MISALIGNED_STORE_TEST(22,  sh,  s0, 1, 2)
+  MISALIGNED_STORE_TEST(23,  sw,  s0, 5, 4)
+  MISALIGNED_STORE_TEST(24,  sw,  s0, 10, 4)
+  MISALIGNED_STORE_TEST(25,  sw,  s0, 15, 4)
+
+#if __riscv_xlen == 64
+  MISALIGNED_STORE_TEST(26, sd, s0, 25, 8)
+  MISALIGNED_STORE_TEST(27, sd, s0, 34, 8)
+  MISALIGNED_STORE_TEST(28, sd, s0, 43, 8)
+  MISALIGNED_STORE_TEST(29, sd, s0, 52, 8)
+  MISALIGNED_STORE_TEST(30, sd, s0, 61, 8)
+  MISALIGNED_STORE_TEST(31, sd, s0, 70, 8)
+  MISALIGNED_STORE_TEST(32, sd, s0, 79, 8)
+#endif
+
+  TEST_PASSFAIL
+
+  .align 3
+  .global mtvec_handler
+mtvec_handler:
+  csrr t0, mcause
+  bne t0, s1, fail
+
+  csrr t0, mbadaddr
+  bne t0, t1, fail
+
+  lb t0, (t0)
+  beqz t0, fail
+
+  csrw mepc, t2
+  mret
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+data:
+  .align 3
+.word 0xaabbccdd
+.word 0x66778899
+.word 0x22334455
+.word 0xeeffee11
+.fill 0xff, 1, 80
+
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64mi/ma_fetch.S b/apps/riscv-tests/isa/rv64mi/ma_fetch.S
new file mode 100644
index 0000000..cfcb90c
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64mi/ma_fetch.S
@@ -0,0 +1,8 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV64M
+#define __MACHINE_MODE
+
+#include "../rv64si/ma_fetch.S"
diff --git a/apps/riscv-tests/isa/rv64mi/mcsr.S b/apps/riscv-tests/isa/rv64mi/mcsr.S
new file mode 100644
index 0000000..e0256e7
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64mi/mcsr.S
@@ -0,0 +1,45 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# mcsr.S
+#-----------------------------------------------------------------------------
+#
+# Test various M-mode CSRs.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64M
+RVTEST_CODE_BEGIN
+
+  # Check that mcpuid reports the correct XLEN
+#if __riscv_xlen == 64
+  TEST_CASE(2, a0, 0x2, csrr a0, misa; srl a0, a0, 62)
+#else
+  TEST_CASE(2, a0, 0x1, csrr a0, misa; srl a0, a0, 30)
+#endif
+
+  # Check that mhartid reports 0
+  TEST_CASE(3, a0, 0x0, csrr a0, mhartid)
+
+  # Check that reading the following CSRs doesn't cause an exception
+  csrr a0, mimpid
+  csrr a0, marchid
+  csrr a0, mvendorid
+
+  # Check that writing hte following CSRs doesn't cause an exception
+  li t0, 0
+  csrs mtvec, t0
+  csrs mepc, t0
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64mi/sbreak.S b/apps/riscv-tests/isa/rv64mi/sbreak.S
new file mode 100644
index 0000000..f36a9f8
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64mi/sbreak.S
@@ -0,0 +1,8 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV64M
+#define __MACHINE_MODE
+
+#include "../rv64si/sbreak.S"
diff --git a/apps/riscv-tests/isa/rv64mi/scall.S b/apps/riscv-tests/isa/rv64mi/scall.S
new file mode 100644
index 0000000..22e9eb5
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64mi/scall.S
@@ -0,0 +1,8 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV64M
+#define __MACHINE_MODE
+
+#include "../rv64si/scall.S"
diff --git a/apps/riscv-tests/isa/rv64si/Makefrag b/apps/riscv-tests/isa/rv64si/Makefrag
new file mode 100644
index 0000000..f01a332
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64si/Makefrag
@@ -0,0 +1,16 @@
+#=======================================================================
+# Makefrag for rv64si tests
+#-----------------------------------------------------------------------
+
+rv64si_sc_tests = \
+	csr \
+	dirty \
+	icache-alias \
+	ma_fetch \
+	scall \
+	wfi \
+	sbreak \
+
+rv64si_p_tests = $(addprefix rv64si-p-, $(rv64si_sc_tests))
+
+spike_tests += $(rv64si_p_tests)
diff --git a/apps/riscv-tests/isa/rv64si/csr.S b/apps/riscv-tests/isa/rv64si/csr.S
new file mode 100644
index 0000000..09494ef
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64si/csr.S
@@ -0,0 +1,154 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# csr.S
+#-----------------------------------------------------------------------------
+#
+# Test CSRRx and CSRRxI instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64S
+RVTEST_CODE_BEGIN
+
+#ifdef __MACHINE_MODE
+  #define sscratch mscratch
+  #define sstatus mstatus
+  #define scause mcause
+  #define sepc mepc
+  #define sret mret
+  #define stvec_handler mtvec_handler
+  #undef SSTATUS_SPP
+  #define SSTATUS_SPP MSTATUS_MPP
+#endif
+
+  # For RV64, make sure UXL encodes RV64.  (UXL does not exist for RV32.)
+#if __riscv_xlen == 64
+  # If running in M mode, use mstatus.MPP to check existence of U mode.
+  # Otherwise, if in S mode, then U mode must exist and we don't need to check.
+#ifdef __MACHINE_MODE
+  li t0, MSTATUS_MPP
+  csrc mstatus, t0
+  csrr t1, mstatus
+  and t0, t0, t1
+  bnez t0, 1f
+#endif
+  # If U mode is present, UXL should be 2 (XLEN = 64-bit)
+  TEST_CASE(18, a0, SSTATUS_UXL & (SSTATUS_UXL << 1), csrr a0, sstatus; li a1, SSTATUS_UXL; and a0, a0, a1)
+#ifdef __MACHINE_MODE
+  j 2f
+1:
+  # If U mode is not present, UXL should be 0
+  TEST_CASE(19, a0, 0, csrr a0, sstatus; li a1, SSTATUS_UXL; and a0, a0, a1)
+2:
+#endif
+#endif
+
+  TEST_CASE(20, a0,         0, csrw sscratch, zero; csrr a0, sscratch);
+  TEST_CASE(21, a0,         0, csrrwi a0, sscratch, 0; csrrwi a0, sscratch, 0xF);
+
+  csrwi sscratch, 3
+  TEST_CASE( 2, a0,         3, csrr a0, sscratch);
+  TEST_CASE( 3, a1,         3, csrrci a1, sscratch, 1);
+  TEST_CASE( 4, a2,         2, csrrsi a2, sscratch, 4);
+  TEST_CASE( 5, a3,         6, csrrwi a3, sscratch, 2);
+  TEST_CASE( 6, a1,         2, li a0, 0xbad1dea; csrrw a1, sscratch, a0);
+  TEST_CASE( 7, a1, 0xbad1dea, li a0, 0x0001dea; csrrc a1, sscratch, a0);
+  TEST_CASE( 8, a1, 0xbad0000, li a0, 0x000beef; csrrs a1, sscratch, a0);
+  TEST_CASE( 9, a0, 0xbadbeef, li a0, 0xbad1dea; csrrw a0, sscratch, a0);
+  TEST_CASE(10, a0, 0xbad1dea, li a0, 0x0001dea; csrrc a0, sscratch, a0);
+  TEST_CASE(11, a0, 0xbad0000, li a0, 0x000beef; csrrs a0, sscratch, a0);
+  TEST_CASE(12, a0, 0xbadbeef, csrr a0, sscratch);
+
+#ifdef __MACHINE_MODE
+  # Is F extension present?
+  csrr a0, misa
+  andi a0, a0, (1 << ('F' - 'A'))
+  beqz a0, 1f
+  # If so, make sure FP stores have no effect when mstatus.FS is off.
+  li a1, MSTATUS_FS
+  csrs mstatus, a1
+#ifdef __riscv_flen
+  fmv.s.x f0, x0
+  csrc mstatus, a1
+  la a1, fsw_data
+  TEST_CASE(13, a0, 1, fsw f0, (a1); lw a0, (a1));
+#else
+  # Fail if this test is compiled without F but executed on a core with F.
+  TEST_CASE(13, zero, 1)
+#endif
+1:
+
+  # Figure out if 'U' is set in misa
+  csrr a0, misa   # a0 = csr(misa)
+  srli a0, a0, 20 # a0 = a0 >> 20
+  andi a0, a0, 1  # a0 = a0 & 1
+  beqz a0, finish # if no user mode, skip the rest of these checks
+#endif /* __MACHINE_MODE */
+
+  # jump to user land
+  li t0, SSTATUS_SPP
+  csrc sstatus, t0
+  la t0, 1f
+  csrw sepc, t0
+  sret
+  1:
+
+  # Make sure writing the cycle counter causes an exception.
+  # Don't run in supervisor, as we don't delegate illegal instruction traps.
+#ifdef __MACHINE_MODE
+  TEST_CASE(14, a0, 255, li a0, 255; csrrw a0, cycle, x0);
+#endif
+
+  # Make sure reading status in user mode causes an exception.
+  # Don't run in supervisor, as we don't delegate illegal instruction traps.
+#ifdef __MACHINE_MODE
+  TEST_CASE(15, a0, 255, li a0, 255; csrr a0, sstatus)
+#else
+  TEST_CASE(15, x0, 0, nop)
+#endif
+
+finish:
+  RVTEST_PASS
+
+  # We should only fall through to this if scall failed.
+  TEST_PASSFAIL
+
+  .align 2
+  .global stvec_handler
+stvec_handler:
+  # Trapping on tests 13-15 is good news.
+  # Note that since the test didn't complete, TESTNUM is smaller by 1.
+  li t0, 12
+  bltu TESTNUM, t0, 1f
+  li t0, 14
+  bleu TESTNUM, t0, privileged
+1:
+
+  # catch RVTEST_PASS and kick it up to M-mode
+  csrr t0, scause
+  li t1, CAUSE_USER_ECALL
+  bne t0, t1, fail
+  RVTEST_PASS
+
+privileged:
+  # Make sure scause indicates a lack of privilege.
+  csrr t0, scause
+  li t1, CAUSE_ILLEGAL_INSTRUCTION
+  bne t0, t1, fail
+  # Return to user mode, but skip the trapping instruction.
+  csrr t0, sepc
+  addi t0, t0, 4
+  csrw sepc, t0
+  sret
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+fsw_data: .word 1
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64si/dirty.S b/apps/riscv-tests/isa/rv64si/dirty.S
new file mode 100644
index 0000000..15f3163
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64si/dirty.S
@@ -0,0 +1,133 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# dirty.S
+#-----------------------------------------------------------------------------
+#
+# Test VM referenced and dirty bits.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+#if (DRAM_BASE >> 30 << 30) != DRAM_BASE
+# error This test requires DRAM_BASE be SV39 superpage-aligned
+#endif 
+
+RVTEST_RV64M
+RVTEST_CODE_BEGIN
+
+  # Turn on VM
+  li a0, (SATP_MODE & ~(SATP_MODE<<1)) * SATP_MODE_SV39
+  la a1, page_table_1
+  srl a1, a1, RISCV_PGSHIFT
+  or a1, a1, a0
+  csrw sptbr, a1
+  sfence.vma
+
+  # Set up MPRV with MPP=S, so loads and stores use S-mode
+  li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_MPRV
+  csrs mstatus, a1
+
+  # Try a faulting store to make sure dirty bit is not set
+  li TESTNUM, 2
+  li t2, 1
+  sw t2, dummy - DRAM_BASE, a0
+
+  # Set SUM=1 so user memory access is permitted
+  li TESTNUM, 3
+  li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_SUM
+  csrs mstatus, a1
+
+  # Make sure SUM=1 works
+  lw t0, dummy - DRAM_BASE
+  bnez t0, die
+
+  # Try a non-faulting store to make sure dirty bit is set
+  sw t2, dummy - DRAM_BASE, a0
+
+  # Make sure it succeeded
+  lw t0, dummy - DRAM_BASE
+  bne t0, t2, die
+
+  # Leave MPRV
+  li t0, MSTATUS_MPRV
+  csrc mstatus, t0
+
+  # Make sure D bit is set
+  lw t0, page_table_1
+  li a0, PTE_A | PTE_D
+  and t0, t0, a0
+  bne t0, a0, die
+
+  # Enter MPRV again
+  li t0, MSTATUS_MPRV
+  csrs mstatus, t0
+
+  # Make sure that superpage entries trap when PPN LSBs are set.
+  li TESTNUM, 4
+  lw a0, page_table_1 - DRAM_BASE
+  or a0, a0, 1 << PTE_PPN_SHIFT
+  sw a0, page_table_1 - DRAM_BASE, t0
+  sfence.vma
+  sw a0, page_table_1 - DRAM_BASE, t0
+  j die
+  
+  RVTEST_PASS
+
+  TEST_PASSFAIL
+
+  .align 2
+  .global mtvec_handler
+mtvec_handler:
+  csrr t0, mcause
+  add t0, t0, -CAUSE_STORE_PAGE_FAULT
+  bnez t0, die
+
+  li t1, 2
+  bne TESTNUM, t1, 1f
+  # Make sure D bit is clear
+  lw t0, page_table_1
+  and t1, t0, PTE_D
+  bnez t1, die
+skip:
+  csrr t0, mepc
+  add t0, t0, 4
+  csrw mepc, t0
+  mret
+
+1:
+  li t1, 3
+  bne TESTNUM, t1, 1f
+  # The implementation doesn't appear to set D bits in HW.
+  # Make sure the D bit really is clear.
+  lw t0, page_table_1
+  and t1, t0, PTE_D
+  bnez t1, die
+  # Set the D bit.
+  or t0, t0, PTE_D
+  sw t0, page_table_1, t1
+  sfence.vma
+  mret
+
+1:
+  li t1, 4
+  bne TESTNUM, t1, 1f
+  j pass
+
+1:
+die:
+  RVTEST_FAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+.align 12
+page_table_1: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_W | PTE_X | PTE_A
+dummy: .dword 0
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64si/icache-alias.S b/apps/riscv-tests/isa/rv64si/icache-alias.S
new file mode 100644
index 0000000..9a8515e
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64si/icache-alias.S
@@ -0,0 +1,141 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# icache-alias.S
+#-----------------------------------------------------------------------------
+#
+# Test that instruction memory appears to be physically addressed, i.e.,
+# that disagreements in the low-order VPN and PPN bits don't cause the
+# wrong instruction to be fetched.  It also tests that changing a page
+# mapping takes effect without executing FENCE.I.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64M
+RVTEST_CODE_BEGIN
+
+  li TESTNUM, 2
+
+  # Set up intermediate page tables
+
+  la t0, page_table_3
+  srl t0, t0, RISCV_PGSHIFT - PTE_PPN_SHIFT
+  ori t0, t0, PTE_V
+  sd t0, page_table_2, t1
+
+  la t0, page_table_2
+  srl t0, t0, RISCV_PGSHIFT - PTE_PPN_SHIFT
+  ori t0, t0, PTE_V
+  sd t0, page_table_1, t1
+
+  # Set up leaf mappings where va[12] != pa[12]
+
+  la t0, code_page_1
+  srl t0, t0, RISCV_PGSHIFT - PTE_PPN_SHIFT
+  ori t0, t0, PTE_V | PTE_X | PTE_A
+  sd t0, page_table_3 + 8, t1
+
+  la t0, code_page_2
+  srl t0, t0, RISCV_PGSHIFT - PTE_PPN_SHIFT
+  ori t0, t0, PTE_V | PTE_X | PTE_A
+  sd t0, page_table_3 + 0, t1
+
+  # Turn on VM
+
+  li a0, (SATP_MODE & ~(SATP_MODE<<1)) * SATP_MODE_SV39
+  la a1, page_table_1
+  srl a1, a1, RISCV_PGSHIFT
+  or a1, a1, a0
+  csrw sptbr, a1
+  sfence.vma
+
+  # Enter supervisor mode and make sure correct page is accessed
+
+  la a2, 1f
+  csrwi mepc, 0
+  li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S)
+  csrs mstatus, a1
+  mret
+
+1:
+  li TESTNUM, 2
+  addi a0, a0, -321
+  bnez a0, fail
+
+  li TESTNUM, 3
+  la a2, 1f
+  li t0, RISCV_PGSIZE
+  csrw mepc, t0
+  mret
+
+1:
+  addi a0, a0, -123
+  bnez a0, fail
+
+  li TESTNUM, 4
+  la a2, 1f
+  csrwi mepc, 0
+  mret
+
+  .align 2
+1:
+  addi a0, a0, -321
+  bnez a0, fail
+
+  li TESTNUM, 5
+
+  # Change mapping and try again
+
+  la t0, code_page_1
+  srl t0, t0, RISCV_PGSHIFT - PTE_PPN_SHIFT
+  ori t0, t0, PTE_V | PTE_X | PTE_A
+  sd t0, page_table_3 + 0, t1
+  sfence.vma
+
+  la a2, 1f
+  csrwi mepc, 0
+  mret
+
+  .align 2
+1:
+  addi a0, a0, -123
+  bnez a0, fail
+
+  RVTEST_PASS
+
+  TEST_PASSFAIL
+
+  .align 2
+  .global mtvec_handler
+mtvec_handler:
+  csrr t0, mcause
+  add t0, t0, -CAUSE_STORE_PAGE_FAULT
+  bnez t0, fail
+
+  jr a2
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+.align 12
+page_table_1: .dword 0
+.align 12
+page_table_2: .dword 0
+.align 12
+page_table_3: .dword 0
+.align 13
+code_page_1:
+  li a0, 123
+  sw x0, (x0)
+.align 12
+code_page_2:
+  li a0, 321
+  sw x0, (x0)
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64si/ma_fetch.S b/apps/riscv-tests/isa/rv64si/ma_fetch.S
new file mode 100644
index 0000000..7d2adec
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64si/ma_fetch.S
@@ -0,0 +1,204 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# ma_fetch.S
+#-----------------------------------------------------------------------------
+#
+# Test misaligned fetch trap.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64S
+RVTEST_CODE_BEGIN
+
+#ifdef __MACHINE_MODE
+  #define sscratch mscratch
+  #define sstatus mstatus
+  #define scause mcause
+  #define sbadaddr mbadaddr
+  #define sepc mepc
+  #define sret mret
+  #define stvec_handler mtvec_handler
+#endif
+
+  .align 2
+  .option norvc
+
+  # Without RVC, the jalr should trap, and the handler will skip ahead.
+  # With RVC, the jalr should not trap, and "j fail" should get skipped.
+  li TESTNUM, 2
+  li t1, 0
+  la t0, 1f
+  jalr t1, t0, 2
+1:
+  .option rvc
+  c.j 1f
+  c.j 2f
+  .option norvc
+1:
+  j fail
+2:
+
+  // This test should pass, since JALR ignores the target LSB
+  li TESTNUM, 3
+  la t0, 1f
+  jalr t1, t0, 1
+1:
+  j 1f
+  j fail
+1:
+
+  li TESTNUM, 4
+  li t1, 0
+  la t0, 1f
+  jalr t1, t0, 3
+1:
+  .option rvc
+  c.j 1f
+  c.j 2f
+  .option norvc
+1:
+  j fail
+2:
+
+  # Like test 2, but with jal instead of jalr.
+  li TESTNUM, 5
+  li t1, 0
+  la t0, 1f
+  jal t1, 2f
+1:
+  .option rvc
+  c.j 1f
+2:
+  c.j 2f
+  .option norvc
+1:
+  j fail
+2:
+
+  # Like test 2, but with a taken branch instead of jalr.
+  li TESTNUM, 6
+  li t1, 0
+  la t0, 1f
+  beqz x0, 2f
+1:
+  .option rvc
+  c.j 1f
+2:
+  c.j 2f
+  .option norvc
+1:
+  j fail
+2:
+
+  # Not-taken branches should not trap, even without RVC.
+  li TESTNUM, 7
+  bnez x0, 1f
+  j 2f
+  .option rvc
+  c.j 1f
+1:
+  c.j 1f
+  .option norvc
+1:
+  j fail
+2:
+
+#ifdef __MACHINE_MODE
+  # RVC cannot be disabled if doing so would cause a misaligned instruction
+  # exception on the next instruction fetch. (This test assumes no other
+  # extensions that support misalignment are present.)
+  li TESTNUM, 8
+  csrr t2, misa
+  andi t2, t2, 1 << ('c' - 'a')
+  beqz t2, 2f
+
+  .option rvc
+  c.nop
+  csrci misa, 1 << ('c' - 'a')
+1:
+  c.nop
+  .option norvc
+
+  csrr t2, misa
+  andi t2, t2, 1 << ('c' - 'a')
+  beqz t2, fail
+
+  # When RVC is disabled, mret to a misaligned mepc should succeed,
+  # masking off mepc[1].
+  la t0, 1f
+  addi t0, t0, -2
+  csrw mepc, t0
+
+  # Try to disable RVC; if it can't be disabled, skip the test.
+  csrci misa, 1 << ('c' - 'a')
+  csrr t2, misa
+  andi t2, t2, 1 << ('c' - 'a')
+  bnez t2, 2f
+
+  li t2, MSTATUS_MPP
+  csrs mstatus, t2
+  mret
+
+  # mret should transfer control to this branch.  Otherwise, it will
+  # transfer control two bytes into the branch, which happens to be the
+  # illegal instruction c.unimp.
+  beqz x0, 1f
+1:
+  csrsi misa, 1 << ('c' - 'a')
+2:
+#endif
+
+  j pass
+
+  TEST_PASSFAIL
+
+  .align 2
+  .global stvec_handler
+stvec_handler:
+  # tests 2, 4, 5, 6, and 8 should trap
+  li a0, 2
+  beq TESTNUM, a0, 1f
+  li a0, 4
+  beq TESTNUM, a0, 1f
+  li a0, 5
+  beq TESTNUM, a0, 1f
+  li a0, 6
+  beq TESTNUM, a0, 1f
+  j fail
+1:
+
+  # verify that return address was not written
+  bnez t1, fail
+
+  # verify trap cause
+  li a1, CAUSE_MISALIGNED_FETCH
+  csrr a0, scause
+  bne a0, a1, fail
+
+  # verify that epc == &jalr (== t0 - 4)
+  csrr a1, sepc
+  addi a1, a1, 4
+  bne t0, a1, fail
+
+  # verify that badaddr == 0 or badaddr == t0+2.
+  csrr a0, sbadaddr
+  beqz a0, 1f
+  addi a0, a0, -2
+  bne a0, t0, fail
+1:
+
+  addi a1, a1, 12
+  csrw sepc, a1
+  sret
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64si/sbreak.S b/apps/riscv-tests/isa/rv64si/sbreak.S
new file mode 100644
index 0000000..31efff8
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64si/sbreak.S
@@ -0,0 +1,51 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# scall.S
+#-----------------------------------------------------------------------------
+#
+# Test syscall trap.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64S
+RVTEST_CODE_BEGIN
+
+#ifdef __MACHINE_MODE
+  #define sscratch mscratch
+  #define sstatus mstatus
+  #define scause mcause
+  #define sepc mepc
+  #define sret mret
+  #define stvec_handler mtvec_handler
+#endif
+
+  li TESTNUM, 2
+
+do_break:
+  sbreak
+  j fail
+
+  TEST_PASSFAIL
+
+  .align 2
+  .global stvec_handler
+stvec_handler:
+  li t1, CAUSE_BREAKPOINT
+  csrr t0, scause
+  bne t0, t1, fail
+  la t1, do_break
+  csrr t0, sepc
+  bne t0, t1, fail
+  j pass
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64si/scall.S b/apps/riscv-tests/isa/rv64si/scall.S
new file mode 100644
index 0000000..9956e03
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64si/scall.S
@@ -0,0 +1,83 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# scall.S
+#-----------------------------------------------------------------------------
+#
+# Test syscall trap.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64S
+RVTEST_CODE_BEGIN
+
+#ifdef __MACHINE_MODE
+  #define sscratch mscratch
+  #define sstatus mstatus
+  #define scause mcause
+  #define sepc mepc
+  #define sret mret
+  #define stvec_handler mtvec_handler
+  #undef SSTATUS_SPP
+  #define SSTATUS_SPP MSTATUS_MPP
+#endif
+
+  li TESTNUM, 2
+
+  # This is the expected trap code.
+  li t1, CAUSE_USER_ECALL
+
+#ifdef __MACHINE_MODE
+  # If running in M mode, use mstatus.MPP to check existence of U mode.
+  # Otherwise, if in S mode, then U mode must exist and we don't need to check.
+  li t0, MSTATUS_MPP
+  csrc mstatus, t0
+  csrr t2, mstatus
+  and t0, t0, t2
+  beqz t0, 1f
+
+  # If U mode doesn't exist, mcause should indicate ECALL from M mode.
+  li t1, CAUSE_MACHINE_ECALL
+#endif
+
+1:
+  li t0, SSTATUS_SPP
+  csrc sstatus, t0
+  la t0, 1f
+  csrw sepc, t0
+  sret
+1:
+
+  li TESTNUM, 1
+do_scall:
+  scall
+  j fail
+
+  TEST_PASSFAIL
+
+# Depending on the test environment, the M-mode version of this test might
+# not actually invoke the following handler.  Instead, the usual ECALL
+# handler in the test environment might detect the CAUSE_USER_ECALL or
+# CAUSE_MACHINE_ECALL exception and mark the test as having passed.
+# Either way, we'll get the coverage we desire: such a handler must check
+# both mcause and TESTNUM, just like the following handler.
+  .align 2
+  .global stvec_handler
+stvec_handler:
+  csrr t0, scause
+  bne t0, t1, fail
+  la t2, do_scall
+  csrr t0, sepc
+  bne t0, t2, fail
+  j pass
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64si/wfi.S b/apps/riscv-tests/isa/rv64si/wfi.S
new file mode 100644
index 0000000..0302034
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64si/wfi.S
@@ -0,0 +1,33 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# wfi.S
+#-----------------------------------------------------------------------------
+#
+# Test wait-for-interrupt instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64S
+RVTEST_CODE_BEGIN
+
+  # Make sure wfi doesn't halt the hart, even if interrupts are disabled
+  csrc sstatus, SSTATUS_SIE
+  csrs sie, SIP_SSIP
+  csrs sip, SIP_SSIP
+  wfi
+
+  RVTEST_PASS
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ua/Makefrag b/apps/riscv-tests/isa/rv64ua/Makefrag
new file mode 100644
index 0000000..3af8856
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ua/Makefrag
@@ -0,0 +1,13 @@
+#=======================================================================
+# Makefrag for rv64ua tests
+#-----------------------------------------------------------------------
+
+rv64ua_sc_tests = \
+	amoadd_d amoand_d amomax_d amomaxu_d amomin_d amominu_d amoor_d amoxor_d amoswap_d \
+	amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoxor_w amoswap_w \
+	lrsc \
+
+rv64ua_p_tests = $(addprefix rv64ua-p-, $(rv64ua_sc_tests))
+rv64ua_v_tests = $(addprefix rv64ua-v-, $(rv64ua_sc_tests))
+
+spike_tests += $(rv64ua_p_tests) $(rv64ua_v_tests)
diff --git a/apps/riscv-tests/isa/rv64ua/amoadd_d.S b/apps/riscv-tests/isa/rv64ua/amoadd_d.S
new file mode 100644
index 0000000..05b2f38
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ua/amoadd_d.S
@@ -0,0 +1,47 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoadd_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amoadd.d instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0xffffffff80000000, \
+    li a0, 0xffffffff80000000; \
+    li a1, 0xfffffffffffff800; \
+    la a3, amo_operand; \
+    sd a0, 0(a3); \
+    amoadd.d	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0xffffffff7ffff800, ld a5, 0(a3))
+
+  # try again after a cache miss
+  TEST_CASE(4, a4, 0xffffffff7ffff800, \
+    amoadd.d a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 0xffffffff7ffff000, ld a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
diff --git a/apps/riscv-tests/isa/rv64ua/amoadd_w.S b/apps/riscv-tests/isa/rv64ua/amoadd_w.S
new file mode 100644
index 0000000..d076d45
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ua/amoadd_w.S
@@ -0,0 +1,48 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoadd_w.S
+#-----------------------------------------------------------------------------
+#
+# Test amoadd.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0xffffffff80000000, \
+    li a0, 0xffffffff80000000; \
+    li a1, 0xfffffffffffff800; \
+    la a3, amo_operand; \
+    sw a0, 0(a3); \
+    amoadd.w	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0x000000007ffff800, lw a5, 0(a3))
+
+  # try again after a cache miss
+  TEST_CASE(4, a4, 0x000000007ffff800, \
+    li  a1, 0xffffffff80000000; \
+    amoadd.w a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 0xfffffffffffff800, lw a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+    .bss
+    .align 3
+amo_operand:
+    .dword 0
diff --git a/apps/riscv-tests/isa/rv64ua/amoand_d.S b/apps/riscv-tests/isa/rv64ua/amoand_d.S
new file mode 100644
index 0000000..c1148c0
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ua/amoand_d.S
@@ -0,0 +1,48 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoand_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amoand.d instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0xffffffff80000000, \
+    li a0, 0xffffffff80000000; \
+    li a1, 0xfffffffffffff800; \
+    la a3, amo_operand; \
+    sd a0, 0(a3); \
+    amoand.d	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3))
+
+  # try again after a cache miss
+  TEST_CASE(4, a4, 0xffffffff80000000, \
+    li  a1, 0x0000000080000000; \
+    amoand.d a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 0x0000000080000000, ld a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
diff --git a/apps/riscv-tests/isa/rv64ua/amoand_w.S b/apps/riscv-tests/isa/rv64ua/amoand_w.S
new file mode 100644
index 0000000..7fe3bd0
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ua/amoand_w.S
@@ -0,0 +1,48 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoand.w.S
+#-----------------------------------------------------------------------------
+#
+# Test amoand.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0xffffffff80000000, \
+    li a0, 0xffffffff80000000; \
+    li a1, 0xfffffffffffff800; \
+    la a3, amo_operand; \
+    sw a0, 0(a3); \
+    amoand.w	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3))
+
+  # try again after a cache miss
+  TEST_CASE(4, a4, 0xffffffff80000000, \
+    li  a1, 0x0000000080000000; \
+    amoand.w a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 0xffffffff80000000, lw a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
diff --git a/apps/riscv-tests/isa/rv64ua/amomax_d.S b/apps/riscv-tests/isa/rv64ua/amomax_d.S
new file mode 100644
index 0000000..b7f8703
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ua/amomax_d.S
@@ -0,0 +1,48 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amomax_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amomax.d instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0xffffffff80000000, \
+    li a0, 0xffffffff80000000; \
+    li a1, 0xfffffffffffff800; \
+    la a3, amo_operand; \
+    sd a0, 0(a3); \
+    amomax.d	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3))
+
+  TEST_CASE(4, a4, 0, \
+    li a1, 1; \
+    sd x0, 0(a3); \
+    amomax.d	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 1, ld a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
diff --git a/apps/riscv-tests/isa/rv64ua/amomax_w.S b/apps/riscv-tests/isa/rv64ua/amomax_w.S
new file mode 100644
index 0000000..f986205
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ua/amomax_w.S
@@ -0,0 +1,48 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amomax_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amomax.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0xffffffff80000000, \
+    li a0, 0xffffffff80000000; \
+    li a1, 0xfffffffffffff800; \
+    la a3, amo_operand; \
+    sw a0, 0(a3); \
+    amomax.w	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3))
+
+  TEST_CASE(4, a4, 0, \
+    li a1, 1; \
+    sw x0, 0(a3); \
+    amomax.w	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 1, lw a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
diff --git a/apps/riscv-tests/isa/rv64ua/amomaxu_d.S b/apps/riscv-tests/isa/rv64ua/amomaxu_d.S
new file mode 100644
index 0000000..227ac4c
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ua/amomaxu_d.S
@@ -0,0 +1,48 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amomaxu_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amomaxu.d instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0xffffffff80000000, \
+    li a0, 0xffffffff80000000; \
+    li a1, 0xfffffffffffff800; \
+    la a3, amo_operand; \
+    sd a0, 0(a3); \
+    amomaxu.d	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3))
+
+  TEST_CASE(4, a4, 0, \
+    li a1, 0xffffffffffffffff; \
+    sd x0, 0(a3); \
+    amomaxu.d	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 0xffffffffffffffff, ld a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
diff --git a/apps/riscv-tests/isa/rv64ua/amomaxu_w.S b/apps/riscv-tests/isa/rv64ua/amomaxu_w.S
new file mode 100644
index 0000000..eb27d07
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ua/amomaxu_w.S
@@ -0,0 +1,48 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amomaxu_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amomaxu.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0xffffffff80000000, \
+    li a0, 0xffffffff80000000; \
+    li a1, 0xfffffffffffff800; \
+    la a3, amo_operand; \
+    sw a0, 0(a3); \
+    amomaxu.w	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3))
+
+  TEST_CASE(4, a4, 0, \
+    li a1, 0xffffffffffffffff; \
+    sw x0, 0(a3); \
+    amomaxu.w	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 0xffffffffffffffff, lw a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
diff --git a/apps/riscv-tests/isa/rv64ua/amomin_d.S b/apps/riscv-tests/isa/rv64ua/amomin_d.S
new file mode 100644
index 0000000..ee6bbf3
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ua/amomin_d.S
@@ -0,0 +1,48 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amomin_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amomin.d instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0xffffffff80000000, \
+    li a0, 0xffffffff80000000; \
+    li a1, 0xfffffffffffff800; \
+    la a3, amo_operand; \
+    sd a0, 0(a3); \
+    amomin.d	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3))
+
+  TEST_CASE(4, a4, 0, \
+    li a1, 0xffffffffffffffff; \
+    sd x0, 0(a3); \
+    amomin.d	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 0xffffffffffffffff, ld a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
diff --git a/apps/riscv-tests/isa/rv64ua/amomin_w.S b/apps/riscv-tests/isa/rv64ua/amomin_w.S
new file mode 100644
index 0000000..1337d2c
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ua/amomin_w.S
@@ -0,0 +1,48 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amomin_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amomin.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0xffffffff80000000, \
+    li a0, 0xffffffff80000000; \
+    li a1, 0xfffffffffffff800; \
+    la a3, amo_operand; \
+    sw a0, 0(a3); \
+    amomin.w	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3))
+
+  TEST_CASE(4, a4, 0, \
+    li a1, 0xffffffffffffffff; \
+    sw x0, 0(a3); \
+    amomin.w	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 0xffffffffffffffff, lw a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
diff --git a/apps/riscv-tests/isa/rv64ua/amominu_d.S b/apps/riscv-tests/isa/rv64ua/amominu_d.S
new file mode 100644
index 0000000..08bfb5b
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ua/amominu_d.S
@@ -0,0 +1,49 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amominu_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amominu.d instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0xffffffff80000000, \
+    li a0, 0xffffffff80000000; \
+    li a1, 0xfffffffffffff800; \
+    la a3, amo_operand; \
+    sd a0, 0(a3); \
+    amominu.d	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3))
+
+  TEST_CASE(4, a4, 0, \
+    li a1, 0xffffffffffffffff; \
+    sd x0, 0(a3); \
+    amominu.d	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 0, ld a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
+  
diff --git a/apps/riscv-tests/isa/rv64ua/amominu_w.S b/apps/riscv-tests/isa/rv64ua/amominu_w.S
new file mode 100644
index 0000000..f45f856
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ua/amominu_w.S
@@ -0,0 +1,49 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amominu_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amominu.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0xffffffff80000000, \
+    li a0, 0xffffffff80000000; \
+    li a1, 0xfffffffffffff800; \
+    la a3, amo_operand; \
+    sw a0, 0(a3); \
+    amominu.w	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3))
+
+  TEST_CASE(4, a4, 0, \
+    li a1, 0xffffffffffffffff; \
+    sw x0, 0(a3); \
+    amominu.w	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 0, lw a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
+  
diff --git a/apps/riscv-tests/isa/rv64ua/amoor_d.S b/apps/riscv-tests/isa/rv64ua/amoor_d.S
new file mode 100644
index 0000000..6f71495
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ua/amoor_d.S
@@ -0,0 +1,48 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoor_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amoor.d instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0xffffffff80000000, \
+    li a0, 0xffffffff80000000; \
+    li a1, 0xfffffffffffff800; \
+    la a3, amo_operand; \
+    sd a0, 0(a3); \
+    amoor.d	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3))
+
+  # try again after a cache miss
+  TEST_CASE(4, a4, 0xfffffffffffff800, \
+    li  a1, 1; \
+    amoor.d a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 0xfffffffffffff801, ld a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
diff --git a/apps/riscv-tests/isa/rv64ua/amoor_w.S b/apps/riscv-tests/isa/rv64ua/amoor_w.S
new file mode 100644
index 0000000..e64b8c2
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ua/amoor_w.S
@@ -0,0 +1,48 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoor.w.S
+#-----------------------------------------------------------------------------
+#
+# Test amoor.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0xffffffff80000000, \
+    li a0, 0xffffffff80000000; \
+    li a1, 0xfffffffffffff800; \
+    la a3, amo_operand; \
+    sw a0, 0(a3); \
+    amoor.w	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3))
+
+  # try again after a cache miss
+  TEST_CASE(4, a4, 0xfffffffffffff800, \
+    li  a1, 1; \
+    amoor.w a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 0xfffffffffffff801, lw a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
diff --git a/apps/riscv-tests/isa/rv64ua/amoswap_d.S b/apps/riscv-tests/isa/rv64ua/amoswap_d.S
new file mode 100644
index 0000000..6b07d74
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ua/amoswap_d.S
@@ -0,0 +1,48 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoswap.d.S
+#-----------------------------------------------------------------------------
+#
+# Test amoswap.d instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0xffffffff80000000, \
+    li a0, 0xffffffff80000000; \
+    li a1, 0xfffffffffffff800; \
+    la a3, amo_operand; \
+    sd a0, 0(a3); \
+    amoswap.d	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3))
+
+  # try again after a cache miss
+  TEST_CASE(4, a4, 0xfffffffffffff800, \
+    li  a1, 0x0000000080000000; \
+    amoswap.d a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 0x0000000080000000, ld a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
diff --git a/apps/riscv-tests/isa/rv64ua/amoswap_w.S b/apps/riscv-tests/isa/rv64ua/amoswap_w.S
new file mode 100644
index 0000000..c4276dc
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ua/amoswap_w.S
@@ -0,0 +1,48 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoswap_w.S
+#-----------------------------------------------------------------------------
+#
+# Test amoswap.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0xffffffff80000000, \
+    li a0, 0xffffffff80000000; \
+    li a1, 0xfffffffffffff800; \
+    la a3, amo_operand; \
+    sw a0, 0(a3); \
+    amoswap.w	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3))
+
+  # try again after a cache miss
+  TEST_CASE(4, a4, 0xfffffffffffff800, \
+    li  a1, 0x0000000080000000; \
+    amoswap.w a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 0xffffffff80000000, lw a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
diff --git a/apps/riscv-tests/isa/rv64ua/amoxor_d.S b/apps/riscv-tests/isa/rv64ua/amoxor_d.S
new file mode 100644
index 0000000..8305434
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ua/amoxor_d.S
@@ -0,0 +1,48 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoxor_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amoxor.d instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0xffffffff80000000, \
+    li a0, 0xffffffff80000000; \
+    li a1, 0xfffffffffffff800; \
+    la a3, amo_operand; \
+    sd a0, 0(a3); \
+    amoxor.d	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0x000000007ffff800, ld a5, 0(a3))
+
+  # try again after a cache miss
+  TEST_CASE(4, a4, 0x000000007ffff800, \
+    li  a1, 1; \
+    amoxor.d a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 0x000000007ffff801, ld a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
diff --git a/apps/riscv-tests/isa/rv64ua/amoxor_w.S b/apps/riscv-tests/isa/rv64ua/amoxor_w.S
new file mode 100644
index 0000000..1b6fc48
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ua/amoxor_w.S
@@ -0,0 +1,48 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoxor_w.S
+#-----------------------------------------------------------------------------
+#
+# Test amoxor.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0xffffffff80000000, \
+    li a0, 0xffffffff80000000; \
+    li a1, 0xfffffffffffff800; \
+    la a3, amo_operand; \
+    sw a0, 0(a3); \
+    amoxor.w	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0x7ffff800, lw a5, 0(a3))
+
+  # try again after a cache miss
+  TEST_CASE(4, a4, 0x7ffff800, \
+    li  a1, 0xc0000001; \
+    amoxor.w a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 0xffffffffbffff801, lw a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
diff --git a/apps/riscv-tests/isa/rv64ua/lrsc.S b/apps/riscv-tests/isa/rv64ua/lrsc.S
new file mode 100644
index 0000000..c7589d7
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ua/lrsc.S
@@ -0,0 +1,102 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# lrsr.S
+#-----------------------------------------------------------------------------
+#
+# Test LR/SC instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+# get a unique core id
+la a0, coreid
+li a1, 1
+amoadd.w a2, a1, (a0)
+
+# for now, only run this on core 0
+1:li a3, 1
+bgeu a2, a3, 1b
+
+1: lw a1, (a0)
+bltu a1, a3, 1b
+
+# make sure that sc without a reservation fails.
+TEST_CASE( 2, a4, 1, \
+  la a0, foo; \
+  li a5, 0xdeadbeef; \
+  sc.w a4, a5, (a0); \
+)
+
+# make sure the failing sc did not commit into memory
+TEST_CASE( 3, a4, 0, \
+  lw a4, foo; \
+)
+
+# make sure that sc with the wrong reservation fails.
+# TODO is this actually mandatory behavior?
+TEST_CASE( 4, a4, 1, \
+  la a0, foo; \
+  la a1, fooTest3; \
+  lr.w a1, (a1); \
+  sc.w a4, a1, (a0); \
+)
+
+#define LOG_ITERATIONS 10
+
+# have each core add its coreid+1 to foo 1024 times
+la a0, foo
+li a1, 1<<LOG_ITERATIONS
+addi a2, a2, 1
+1: lr.w a4, (a0)
+add a4, a4, a2
+sc.w a4, a4, (a0)
+bnez a4, 1b
+add a1, a1, -1
+bnez a1, 1b
+
+# wait for all cores to finish
+la a0, barrier
+li a1, 1
+amoadd.w x0, a1, (a0)
+1: lw a1, (a0)
+blt a1, a3, 1b
+fence
+
+# expected result is 512*ncores*(ncores+1)
+TEST_CASE( 5, a0, 0, \
+  lw a0, foo; \
+  slli a1, a3, LOG_ITERATIONS-1; \
+1:sub a0, a0, a1; \
+  addi a3, a3, -1; \
+  bgez a3, 1b
+)
+
+# make sure that sc-after-successful-sc fails.
+TEST_CASE( 6, a1, 1, \
+  la a0, foo; \
+1:lr.w a1, (a0); \
+  sc.w a1, x0, (a0); \
+  bnez a1, 1b; \
+  sc.w a1, x0, (a0)
+)
+
+TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+coreid: .word 0
+barrier: .word 0
+foo: .word 0
+.skip 1024
+fooTest3: .word 0
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64uc/Makefrag b/apps/riscv-tests/isa/rv64uc/Makefrag
new file mode 100644
index 0000000..f5e49b7
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uc/Makefrag
@@ -0,0 +1,11 @@
+#=======================================================================
+# Makefrag for rv64uc tests
+#-----------------------------------------------------------------------
+
+rv64uc_sc_tests = \
+	rvc \
+
+rv64uc_p_tests = $(addprefix rv64uc-p-, $(rv64uc_sc_tests))
+rv64uc_v_tests = $(addprefix rv64uc-v-, $(rv64uc_sc_tests))
+
+spike_tests += $(rv64uc_p_tests) $(rv64uc_v_tests)
diff --git a/apps/riscv-tests/isa/rv64uc/rvc.S b/apps/riscv-tests/isa/rv64uc/rvc.S
new file mode 100644
index 0000000..3629d1d
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uc/rvc.S
@@ -0,0 +1,154 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# rvc.S
+#-----------------------------------------------------------------------------
+#
+# Test RVC corner cases.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  .align 2
+  .option push
+  .option norvc
+
+  #define RVC_TEST_CASE(n, r, v, code...) \
+    TEST_CASE (n, r, v, .option push; .option rvc; code; .align 2; .option pop)
+
+  // Make sure fetching a 4-byte instruction across a page boundary works.
+  li TESTNUM, 2
+  li a1, 666
+  TEST_CASE (2, a1, 667, \
+        j 1f; \
+        .align 3; \
+        data: \
+          .dword 0xfedcba9876543210; \
+          .dword 0xfedcba9876543210; \
+        .align 12; \
+        .skip 4094; \
+      1: addi a1, a1, 1)
+
+  li sp, 0x1234
+  RVC_TEST_CASE (3, a0, 0x1234 + 1020, c.addi4spn a0, sp, 1020)
+  RVC_TEST_CASE (4, sp, 0x1234 + 496, c.addi16sp sp, 496)
+  RVC_TEST_CASE (5, sp, 0x1234 + 496 - 512, c.addi16sp sp, -512)
+
+  la a1, data
+  RVC_TEST_CASE (6, a2, 0xfffffffffedcba99, c.lw a0, 4(a1); addi a0, a0, 1; c.sw a0, 4(a1); c.lw a2, 4(a1))
+#if __riscv_xlen == 64
+  RVC_TEST_CASE (7, a2, 0xfedcba9976543211, c.ld a0, 0(a1); addi a0, a0, 1; c.sd a0, 0(a1); c.ld a2, 0(a1))
+#endif
+
+  RVC_TEST_CASE (8, a0, -15, ori a0, x0, 1; c.addi a0, -16)
+  RVC_TEST_CASE (9, a5, -16, ori a5, x0, 1; c.li a5, -16)
+#if __riscv_xlen == 64
+  RVC_TEST_CASE (10, a0, 0x76543210, ld a0, (a1); c.addiw a0, -1)
+#endif
+
+  RVC_TEST_CASE (11, s0, 0xffffffffffffffe1, c.lui s0, 0xfffe1; c.srai s0, 12)
+#if __riscv_xlen == 64
+  RVC_TEST_CASE (12, s0, 0x000fffffffffffe1, c.lui s0, 0xfffe1; c.srli s0, 12)
+#else
+  RVC_TEST_CASE (12, s0, 0x000fffe1, c.lui s0, 0xfffe1; c.srli s0, 12)
+#endif
+  RVC_TEST_CASE (14, s0, ~0x11, c.li s0, -2; c.andi s0, ~0x10)
+  RVC_TEST_CASE (15, s1, 14, li s1, 20; li a0, 6; c.sub s1, a0)
+  RVC_TEST_CASE (16, s1, 18, li s1, 20; li a0, 6; c.xor s1, a0)
+  RVC_TEST_CASE (17, s1, 22, li s1, 20; li a0, 6; c.or s1, a0)
+  RVC_TEST_CASE (18, s1,  4, li s1, 20; li a0, 6; c.and s1, a0)
+#if __riscv_xlen == 64
+  RVC_TEST_CASE (19, s1, 0xffffffff80000000, li s1, 0x7fffffff; li a0, -1; c.subw s1, a0)
+  RVC_TEST_CASE (20, s1, 0xffffffff80000000, li s1, 0x7fffffff; li a0, 1; c.addw s1, a0)
+#endif
+  RVC_TEST_CASE (21, s0, 0x12340, li s0, 0x1234; c.slli s0, 4)
+
+  RVC_TEST_CASE (30, ra, 0, \
+        li ra, 0; \
+        c.j 1f; \
+        c.j 2f; \
+      1:c.j 1f; \
+      2:j fail; \
+      1:)
+
+  RVC_TEST_CASE (31, x0, 0, \
+        li a0, 0; \
+        c.beqz a0, 1f; \
+        c.j 2f; \
+      1:c.j 1f; \
+      2:j fail; \
+      1:)
+
+  RVC_TEST_CASE (32, x0, 0, \
+        li a0, 1; \
+        c.bnez a0, 1f; \
+        c.j 2f; \
+      1:c.j 1f; \
+      2:j fail; \
+      1:)
+
+  RVC_TEST_CASE (33, x0, 0, \
+        li a0, 1; \
+        c.beqz a0, 1f; \
+        c.j 2f; \
+      1:c.j fail; \
+      2:)
+
+  RVC_TEST_CASE (34, x0, 0, \
+        li a0, 0; \
+        c.bnez a0, 1f; \
+        c.j 2f; \
+      1:c.j fail; \
+      2:)
+
+  RVC_TEST_CASE (35, ra, 0, \
+        la t0, 1f; \
+        li ra, 0; \
+        c.jr t0; \
+        c.j 2f; \
+      1:c.j 1f; \
+      2:j fail; \
+      1:)
+
+  RVC_TEST_CASE (36, ra, -2, \
+        la t0, 1f; \
+        li ra, 0; \
+        c.jalr t0; \
+        c.j 2f; \
+      1:c.j 1f; \
+      2:j fail; \
+      1:sub ra, ra, t0)
+
+#if __riscv_xlen == 32
+  RVC_TEST_CASE (37, ra, -2, \
+        la t0, 1f; \
+        li ra, 0; \
+        c.jal 1f; \
+        c.j 2f; \
+      1:c.j 1f; \
+      2:j fail; \
+      1:sub ra, ra, t0)
+#endif
+
+  la sp, data
+  RVC_TEST_CASE (40, a2, 0xfffffffffedcba99, c.lwsp a0, 12(sp); addi a0, a0, 1; c.swsp a0, 12(sp); c.lwsp a2, 12(sp))
+#if __riscv_xlen == 64
+  RVC_TEST_CASE (41, a2, 0xfedcba9976543211, c.ldsp a0, 8(sp); addi a0, a0, 1; c.sdsp a0, 8(sp); c.ldsp a2, 8(sp))
+#endif
+
+  RVC_TEST_CASE (42, t0, 0x246, li a0, 0x123; c.mv t0, a0; c.add t0, a0)
+
+  .option pop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ud/Makefrag b/apps/riscv-tests/isa/rv64ud/Makefrag
new file mode 100644
index 0000000..9cffb5d
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ud/Makefrag
@@ -0,0 +1,12 @@
+#=======================================================================
+# Makefrag for rv64ud tests
+#-----------------------------------------------------------------------
+
+rv64ud_sc_tests = \
+	fadd fdiv fclass fcmp fcvt fcvt_w fmadd fmin \
+	ldst move structural recoding \
+
+rv64ud_p_tests = $(addprefix rv64ud-p-, $(rv64ud_sc_tests))
+rv64ud_v_tests = $(addprefix rv64ud-v-, $(rv64ud_sc_tests))
+
+spike_tests += $(rv64ud_p_tests) $(rv64ud_v_tests)
diff --git a/apps/riscv-tests/isa/rv64ud/fadd.S b/apps/riscv-tests/isa/rv64ud/fadd.S
new file mode 100644
index 0000000..51ca82d
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ud/fadd.S
@@ -0,0 +1,50 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fadd.S
+#-----------------------------------------------------------------------------
+#
+# Test f{add|sub|mul}.d instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+#if __riscv_xlen == 32
+    # Replace the function with the 32-bit variant defined in test_macros.h
+    #undef TEST_FP_OP2_D
+    #define TEST_FP_OP2_D TEST_FP_OP2_D32
+#endif
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_FP_OP2_D( 2,  fadd.d, 0,                3.5,        2.5,        1.0 );
+  TEST_FP_OP2_D( 3,  fadd.d, 1,              -1234,    -1235.1,        1.1 );
+  TEST_FP_OP2_D( 4,  fadd.d, 1,         3.14159266, 3.14159265, 0.00000001 );
+
+  TEST_FP_OP2_D( 5,  fsub.d, 0,                1.5,        2.5,        1.0 );
+  TEST_FP_OP2_D( 6,  fsub.d, 1,              -1234,    -1235.1,       -1.1 );
+  TEST_FP_OP2_D( 7,  fsub.d, 1, 3.1415926400000001, 3.14159265, 0.00000001 );
+
+  TEST_FP_OP2_D( 8,  fmul.d, 0,                2.5,        2.5,        1.0 );
+  TEST_FP_OP2_D( 9,  fmul.d, 1,            1358.61,    -1235.1,       -1.1 );
+  TEST_FP_OP2_D(10,  fmul.d, 1,      3.14159265e-8, 3.14159265, 0.00000001 );
+
+  # Is the canonical NaN generated for Inf - Inf?
+  TEST_FP_OP2_D(11,  fsub.d, 0x10, qNaN, Inf, Inf);
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ud/fclass.S b/apps/riscv-tests/isa/rv64ud/fclass.S
new file mode 100644
index 0000000..04a8947
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ud/fclass.S
@@ -0,0 +1,46 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fclass.S
+#-----------------------------------------------------------------------------
+#
+# Test fclass.d instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+#if __riscv_xlen == 32
+    # Replace the function with the 32-bit variant defined in test_macros.h
+    #undef TEST_FCLASS_D
+    #define TEST_FCLASS_D TEST_FCLASS_D32
+#endif
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_FCLASS_D( 2, 1 << 0, 0xfff0000000000000 )
+  TEST_FCLASS_D( 3, 1 << 1, 0xbff0000000000000 )
+  TEST_FCLASS_D( 4, 1 << 2, 0x800fffffffffffff )
+  TEST_FCLASS_D( 5, 1 << 3, 0x8000000000000000 )
+  TEST_FCLASS_D( 6, 1 << 4, 0x0000000000000000 )
+  TEST_FCLASS_D( 7, 1 << 5, 0x000fffffffffffff )
+  TEST_FCLASS_D( 8, 1 << 6, 0x3ff0000000000000 )
+  TEST_FCLASS_D( 9, 1 << 7, 0x7ff0000000000000 )
+  TEST_FCLASS_D(10, 1 << 8, 0x7ff0000000000001 )
+  TEST_FCLASS_D(11, 1 << 9, 0x7ff8000000000000 )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ud/fcmp.S b/apps/riscv-tests/isa/rv64ud/fcmp.S
new file mode 100644
index 0000000..7727a28
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ud/fcmp.S
@@ -0,0 +1,56 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fcmp.S
+#-----------------------------------------------------------------------------
+#
+# Test f{eq|lt|le}.d instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+#if __riscv_xlen == 32
+    # Replace the function with the 32-bit variant defined in test_macros.h
+    #undef TEST_FP_CMP_OP_D
+    #define TEST_FP_CMP_OP_D TEST_FP_CMP_OP_D32
+#endif
+
+  TEST_FP_CMP_OP_D( 2, feq.d, 0x00, 1, -1.36, -1.36)
+  TEST_FP_CMP_OP_D( 3, fle.d, 0x00, 1, -1.36, -1.36)
+  TEST_FP_CMP_OP_D( 4, flt.d, 0x00, 0, -1.36, -1.36)
+
+  TEST_FP_CMP_OP_D( 5, feq.d, 0x00, 0, -1.37, -1.36)
+  TEST_FP_CMP_OP_D( 6, fle.d, 0x00, 1, -1.37, -1.36)
+  TEST_FP_CMP_OP_D( 7, flt.d, 0x00, 1, -1.37, -1.36)
+
+  # Only sNaN should signal invalid for feq.
+  TEST_FP_CMP_OP_D( 8, feq.d, 0x00, 0, NaN, 0)
+  TEST_FP_CMP_OP_D( 9, feq.d, 0x00, 0, NaN, NaN)
+  TEST_FP_CMP_OP_D(10, feq.d, 0x10, 0, sNaN, 0)
+
+  # qNaN should signal invalid for fle/flt.
+  TEST_FP_CMP_OP_D(11, flt.d, 0x10, 0, NaN, 0)
+  TEST_FP_CMP_OP_D(12, flt.d, 0x10, 0, NaN, NaN)
+  TEST_FP_CMP_OP_D(13, flt.d, 0x10, 0, sNaN, 0)
+  TEST_FP_CMP_OP_D(14, fle.d, 0x10, 0, NaN, 0)
+  TEST_FP_CMP_OP_D(15, fle.d, 0x10, 0, NaN, NaN)
+  TEST_FP_CMP_OP_D(16, fle.d, 0x10, 0, sNaN, 0)
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ud/fcvt.S b/apps/riscv-tests/isa/rv64ud/fcvt.S
new file mode 100644
index 0000000..98916b1
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ud/fcvt.S
@@ -0,0 +1,79 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fcvt.S
+#-----------------------------------------------------------------------------
+#
+# Test fcvt.d.{wu|w|lu|l}, fcvt.s.d, and fcvt.d.s instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+#if __riscv_xlen == 32
+    # Replace the function with the 32-bit variant defined in test_macros.h
+    #undef TEST_INT_FP_OP_D
+    #define TEST_INT_FP_OP_D TEST_INT_FP_OP_D32
+
+    #undef TEST_FCVT_S_D
+    #define TEST_FCVT_S_D TEST_FCVT_S_D32
+#endif
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_INT_FP_OP_D(2,  fcvt.d.w,                   2.0,  2);
+  TEST_INT_FP_OP_D(3,  fcvt.d.w,                  -2.0, -2);
+
+  TEST_INT_FP_OP_D(4, fcvt.d.wu,                   2.0,  2);
+  TEST_INT_FP_OP_D(5, fcvt.d.wu,            4294967294, -2);
+
+#if __riscv_xlen >= 64
+  TEST_INT_FP_OP_D(6,  fcvt.d.l,                   2.0,  2);
+  TEST_INT_FP_OP_D(7,  fcvt.d.l,                  -2.0, -2);
+
+  TEST_INT_FP_OP_D(8, fcvt.d.lu,                   2.0,  2);
+  TEST_INT_FP_OP_D(9, fcvt.d.lu, 1.8446744073709552e19, -2);
+#endif
+
+  TEST_FCVT_S_D(10, -1.5, -1.5)
+  TEST_FCVT_D_S(11, -1.5, -1.5)
+
+#if __riscv_xlen >= 64
+  TEST_CASE(12, a0, 0x7ff8000000000000,
+    la a1, test_data_22;
+    ld a2, 0(a1);
+    fmv.d.x f2, a2;
+    fcvt.s.d f2, f2;
+    fcvt.d.s f2, f2;
+    fmv.x.d a0, f2;
+  )
+#else
+  TEST_CASE_D32(12, a0, a1, 0x7ff8000000000000,
+    la a1, test_data_22;
+    fld f2, 0(a1);
+    fcvt.s.d f2, f2;
+    fcvt.d.s f2, f2;
+    fsd f2, 0(a1);
+    lw a0, 0(a1);
+    lw a1, 4(a1)
+  )
+#endif
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+test_data_22:
+  .dword 0x7ffcffffffff8004
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ud/fcvt_w.S b/apps/riscv-tests/isa/rv64ud/fcvt_w.S
new file mode 100644
index 0000000..56cc29d
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ud/fcvt_w.S
@@ -0,0 +1,114 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fcvt_w.S
+#-----------------------------------------------------------------------------
+#
+# Test fcvt{wu|w|lu|l}.d instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_FP_INT_OP_D( 2,  fcvt.w.d, 0x01,         -1, -1.1, rtz);
+  TEST_FP_INT_OP_D( 3,  fcvt.w.d, 0x00,         -1, -1.0, rtz);
+  TEST_FP_INT_OP_D( 4,  fcvt.w.d, 0x01,          0, -0.9, rtz);
+  TEST_FP_INT_OP_D( 5,  fcvt.w.d, 0x01,          0,  0.9, rtz);
+  TEST_FP_INT_OP_D( 6,  fcvt.w.d, 0x00,          1,  1.0, rtz);
+  TEST_FP_INT_OP_D( 7,  fcvt.w.d, 0x01,          1,  1.1, rtz);
+  TEST_FP_INT_OP_D( 8,  fcvt.w.d, 0x10,     -1<<31, -3e9, rtz);
+  TEST_FP_INT_OP_D( 9,  fcvt.w.d, 0x10,  (1<<31)-1,  3e9, rtz);
+
+  TEST_FP_INT_OP_D(12, fcvt.wu.d, 0x10,          0, -3.0, rtz);
+  TEST_FP_INT_OP_D(13, fcvt.wu.d, 0x10,          0, -1.0, rtz);
+  TEST_FP_INT_OP_D(14, fcvt.wu.d, 0x01,          0, -0.9, rtz);
+  TEST_FP_INT_OP_D(15, fcvt.wu.d, 0x01,          0,  0.9, rtz);
+  TEST_FP_INT_OP_D(16, fcvt.wu.d, 0x00,          1,  1.0, rtz);
+  TEST_FP_INT_OP_D(17, fcvt.wu.d, 0x01,          1,  1.1, rtz);
+  TEST_FP_INT_OP_D(18, fcvt.wu.d, 0x10,          0, -3e9, rtz);
+  TEST_FP_INT_OP_D(19, fcvt.wu.d, 0x00, 0xffffffffb2d05e00, 3e9, rtz);
+
+#if __riscv_xlen >= 64
+  TEST_FP_INT_OP_D(22,  fcvt.l.d, 0x01,         -1, -1.1, rtz);
+  TEST_FP_INT_OP_D(23,  fcvt.l.d, 0x00,         -1, -1.0, rtz);
+  TEST_FP_INT_OP_D(24,  fcvt.l.d, 0x01,          0, -0.9, rtz);
+  TEST_FP_INT_OP_D(25,  fcvt.l.d, 0x01,          0,  0.9, rtz);
+  TEST_FP_INT_OP_D(26,  fcvt.l.d, 0x00,          1,  1.0, rtz);
+  TEST_FP_INT_OP_D(27,  fcvt.l.d, 0x01,          1,  1.1, rtz);
+  TEST_FP_INT_OP_D(28,  fcvt.l.d, 0x00,-3000000000, -3e9, rtz);
+  TEST_FP_INT_OP_D(29,  fcvt.l.d, 0x00, 3000000000,  3e9, rtz);
+  TEST_FP_INT_OP_D(20,  fcvt.l.d, 0x10,     -1<<63,-3e19, rtz);
+  TEST_FP_INT_OP_D(21,  fcvt.l.d, 0x10,  (1<<63)-1, 3e19, rtz);
+
+  TEST_FP_INT_OP_D(32, fcvt.lu.d, 0x10,          0, -3.0, rtz);
+  TEST_FP_INT_OP_D(33, fcvt.lu.d, 0x10,          0, -1.0, rtz);
+  TEST_FP_INT_OP_D(34, fcvt.lu.d, 0x01,          0, -0.9, rtz);
+  TEST_FP_INT_OP_D(35, fcvt.lu.d, 0x01,          0,  0.9, rtz);
+  TEST_FP_INT_OP_D(36, fcvt.lu.d, 0x00,          1,  1.0, rtz);
+  TEST_FP_INT_OP_D(37, fcvt.lu.d, 0x01,          1,  1.1, rtz);
+  TEST_FP_INT_OP_D(38, fcvt.lu.d, 0x10,          0, -3e9, rtz);
+  TEST_FP_INT_OP_D(39, fcvt.lu.d, 0x00, 3000000000,  3e9, rtz);
+#endif
+
+  # test negative NaN, negative infinity conversion
+  TEST_CASE(42, x1, 0x000000007fffffff, la x1, tdat_d; fld f1,  0(x1); fcvt.w.d x1, f1)
+#if __riscv_xlen >= 64
+  TEST_CASE(43, x1, 0x7fffffffffffffff, la x1, tdat_d; fld f1,  0(x1); fcvt.l.d x1, f1)
+#endif
+  TEST_CASE(44, x1, 0xffffffff80000000, la x1, tdat_d; fld f1, 16(x1); fcvt.w.d x1, f1)
+#if __riscv_xlen >= 64
+  TEST_CASE(45, x1, 0x8000000000000000, la x1, tdat_d; fld f1, 16(x1); fcvt.l.d x1, f1)
+#endif
+
+  # test positive NaN, positive infinity conversion
+  TEST_CASE(52, x1, 0x000000007fffffff, la x1, tdat_d; fld f1,  8(x1); fcvt.w.d x1, f1)
+#if __riscv_xlen >= 64
+  TEST_CASE(53, x1, 0x7fffffffffffffff, la x1, tdat_d; fld f1,  8(x1); fcvt.l.d x1, f1)
+#endif
+  TEST_CASE(54, x1, 0x000000007fffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.w.d x1, f1)
+#if __riscv_xlen >= 64
+  TEST_CASE(55, x1, 0x7fffffffffffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.l.d x1, f1)
+#endif
+
+  # test NaN, infinity conversions to unsigned integer
+  TEST_CASE(62, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1,  0(x1); fcvt.wu.d x1, f1)
+  TEST_CASE(63, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1,  8(x1); fcvt.wu.d x1, f1)
+  TEST_CASE(64, x1,                  0, la x1, tdat_d; fld f1, 16(x1); fcvt.wu.d x1, f1)
+  TEST_CASE(65, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.wu.d x1, f1)
+#if __riscv_xlen >= 64
+  TEST_CASE(66, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1,  0(x1); fcvt.lu.d x1, f1)
+  TEST_CASE(67, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1,  8(x1); fcvt.lu.d x1, f1)
+  TEST_CASE(68, x1,                  0, la x1, tdat_d; fld f1, 16(x1); fcvt.lu.d x1, f1)
+  TEST_CASE(69, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.lu.d x1, f1)
+#endif
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+# -NaN, NaN, -inf, +inf
+tdat:
+.word 0xffffffff
+.word 0x7fffffff
+.word 0xff800000
+.word 0x7f800000
+
+tdat_d:
+.dword 0xffffffffffffffff
+.dword 0x7fffffffffffffff
+.dword 0xfff0000000000000
+.dword 0x7ff0000000000000
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ud/fdiv.S b/apps/riscv-tests/isa/rv64ud/fdiv.S
new file mode 100644
index 0000000..f985fa1
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ud/fdiv.S
@@ -0,0 +1,54 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fdiv.S
+#-----------------------------------------------------------------------------
+#
+# Test f{div|sqrt}.d instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+#if __riscv_xlen == 32
+    # Replace the functions with the 32-bit variants defined in test_macros.h
+    #undef TEST_FP_OP2_D
+    #define TEST_FP_OP2_D TEST_FP_OP2_D32
+
+    #undef TEST_FP_OP1_D
+    #define TEST_FP_OP1_D TEST_FP_OP1_D32
+
+    #undef TEST_FP_OP1_D_DWORD_RESULT
+    #define TEST_FP_OP1_D_DWORD_RESULT TEST_FP_OP1_D32_DWORD_RESULT
+#endif
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_FP_OP2_D( 2,  fdiv.d, 1, 1.1557273520668288, 3.14159265, 2.71828182 );
+  TEST_FP_OP2_D( 3,  fdiv.d, 1,-0.9991093838555584,      -1234,     1235.1 );
+  TEST_FP_OP2_D( 4,  fdiv.d, 0,         3.14159265, 3.14159265,        1.0 );
+
+  TEST_FP_OP1_D( 5,  fsqrt.d, 1, 1.7724538498928541, 3.14159265 );
+  TEST_FP_OP1_D( 6,  fsqrt.d, 0,                100,      10000 );
+
+  TEST_FP_OP1_D_DWORD_RESULT(16,  fsqrt.d, 0x10,      0x7FF8000000000000,      -1.0 );
+
+  TEST_FP_OP1_D( 7,  fsqrt.d, 1, 13.076696830622021, 171.0);
+
+  TEST_FP_OP1_D( 8,  fsqrt.d, 1,0.00040099251863345283320230749702, 1.60795e-7);
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ud/fmadd.S b/apps/riscv-tests/isa/rv64ud/fmadd.S
new file mode 100644
index 0000000..1e3ba66
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ud/fmadd.S
@@ -0,0 +1,51 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fmadd.S
+#-----------------------------------------------------------------------------
+#
+# Test f[n]m{add|sub}.s and f[n]m{add|sub}.d instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+#if __riscv_xlen == 32
+    # Replace the function with the 32-bit variant defined in test_macros.h
+    #undef TEST_FP_OP3_D
+    #define TEST_FP_OP3_D TEST_FP_OP3_D32
+#endif
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_FP_OP3_D( 2,  fmadd.d, 0,                 3.5,  1.0,        2.5,        1.0 );
+  TEST_FP_OP3_D( 3,  fmadd.d, 1,  1236.1999999999999, -1.0,    -1235.1,        1.1 );
+  TEST_FP_OP3_D( 4,  fmadd.d, 0,               -12.0,  2.0,       -5.0,       -2.0 );
+
+  TEST_FP_OP3_D( 5, fnmadd.d, 0,                -3.5,  1.0,        2.5,        1.0 );
+  TEST_FP_OP3_D( 6, fnmadd.d, 1, -1236.1999999999999, -1.0,    -1235.1,        1.1 );
+  TEST_FP_OP3_D( 7, fnmadd.d, 0,                12.0,  2.0,       -5.0,       -2.0 );
+
+  TEST_FP_OP3_D( 8,  fmsub.d, 0,                 1.5,  1.0,        2.5,        1.0 );
+  TEST_FP_OP3_D( 9,  fmsub.d, 1,                1234, -1.0,    -1235.1,        1.1 );
+  TEST_FP_OP3_D(10,  fmsub.d, 0,                -8.0,  2.0,       -5.0,       -2.0 );
+
+  TEST_FP_OP3_D(11, fnmsub.d, 0,                -1.5,  1.0,        2.5,        1.0 );
+  TEST_FP_OP3_D(12, fnmsub.d, 1,               -1234, -1.0,    -1235.1,        1.1 );
+  TEST_FP_OP3_D(13, fnmsub.d, 0,                 8.0,  2.0,       -5.0,       -2.0 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ud/fmin.S b/apps/riscv-tests/isa/rv64ud/fmin.S
new file mode 100644
index 0000000..8f270a5
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ud/fmin.S
@@ -0,0 +1,60 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fmin.S
+#-----------------------------------------------------------------------------
+#
+# Test f{min|max}.d instructinos.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+#if __riscv_xlen == 32
+    # Replace the function with the 32-bit variant defined in test_macros.h
+    #undef TEST_FP_OP2_D
+    #define TEST_FP_OP2_D TEST_FP_OP2_D32
+#endif
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_FP_OP2_D( 2,  fmin.d, 0,        1.0,        2.5,        1.0 );
+  TEST_FP_OP2_D( 3,  fmin.d, 0,    -1235.1,    -1235.1,        1.1 );
+  TEST_FP_OP2_D( 4,  fmin.d, 0,    -1235.1,        1.1,    -1235.1 );
+  TEST_FP_OP2_D( 5,  fmin.d, 0,    -1235.1,        NaN,    -1235.1 );
+  TEST_FP_OP2_D( 6,  fmin.d, 0, 0.00000001, 3.14159265, 0.00000001 );
+  TEST_FP_OP2_D( 7,  fmin.d, 0,       -2.0,       -1.0,       -2.0 );
+
+  TEST_FP_OP2_D(12,  fmax.d, 0,        2.5,        2.5,        1.0 );
+  TEST_FP_OP2_D(13,  fmax.d, 0,        1.1,    -1235.1,        1.1 );
+  TEST_FP_OP2_D(14,  fmax.d, 0,        1.1,        1.1,    -1235.1 );
+  TEST_FP_OP2_D(15,  fmax.d, 0,    -1235.1,        NaN,    -1235.1 );
+  TEST_FP_OP2_D(16,  fmax.d, 0, 3.14159265, 3.14159265, 0.00000001 );
+  TEST_FP_OP2_D(17,  fmax.d, 0,       -1.0,       -1.0,       -2.0 );
+
+  # FMAX(sNaN, x) = x
+  TEST_FP_OP2_D(20,  fmax.d, 0x10, 1.0, sNaN, 1.0);
+  # FMAX(qNaN, qNaN) = canonical NaN
+  TEST_FP_OP2_D(21,  fmax.d, 0x00, qNaN, NaN, NaN);
+
+  # -0.0 < +0.0
+  TEST_FP_OP2_D(30,  fmin.d, 0,       -0.0,       -0.0,        0.0 );
+  TEST_FP_OP2_D(31,  fmin.d, 0,       -0.0,        0.0,       -0.0 );
+  TEST_FP_OP2_D(32,  fmax.d, 0,        0.0,       -0.0,        0.0 );
+  TEST_FP_OP2_D(33,  fmax.d, 0,        0.0,        0.0,       -0.0 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ud/ldst.S b/apps/riscv-tests/isa/rv64ud/ldst.S
new file mode 100644
index 0000000..9629341
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ud/ldst.S
@@ -0,0 +1,42 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# ldst.S
+#-----------------------------------------------------------------------------
+#
+# This test verifies that flw, fld, fsw, and fsd work properly.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+  la s0, tdat
+  TEST_CASE(2, a0, 0x40000000bf800000, fld f2, 0(s0); fsd f2, 16(s0); ld a0, 16(s0))
+  TEST_CASE(3, a0, 0x40000000bf800000, fld f2, 0(s0); fsw f2, 16(s0); ld a0, 16(s0))
+  TEST_CASE(4, a0, 0x40000000bf800000, flw f2, 0(s0); fsw f2, 16(s0); ld a0, 16(s0))
+  TEST_CASE(5, a0, 0xc080000040400000, fld f2, 8(s0); fsd f2, 16(s0); ld a0, 16(s0))
+  TEST_CASE(6, a0, 0xffffffff40400000, flw f2, 8(s0); fsd f2, 16(s0); ld a0, 16(s0))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+tdat:
+.word 0xbf800000
+.word 0x40000000
+.word 0x40400000
+.word 0xc0800000
+.word 0xdeadbeef
+.word 0xcafebabe
+.word 0xabad1dea
+.word 0x1337d00d
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ud/move.S b/apps/riscv-tests/isa/rv64ud/move.S
new file mode 100644
index 0000000..8911d95
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ud/move.S
@@ -0,0 +1,113 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# move.S
+#-----------------------------------------------------------------------------
+#
+# This test verifies that fmv.d.x, fmv.x.d, and fsgnj[x|n].d work properly.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+#TODO: make 32-bit compatible version
+#define TEST_FSGNJD(n, insn, new_sign, rs1_sign, rs2_sign) \
+  TEST_CASE(n, a0, 0x123456789abcdef0 | (-(new_sign) << 63), \
+    li a1, ((rs1_sign) << 63) | 0x123456789abcdef0; \
+    li a2, -(rs2_sign); \
+    fmv.d.x f1, a1; \
+    fmv.d.x f2, a2; \
+    insn f0, f1, f2; \
+    fmv.x.d a0, f0)
+
+  TEST_FSGNJD(10, fsgnj.d, 0, 0, 0)
+  TEST_FSGNJD(11, fsgnj.d, 1, 0, 1)
+  TEST_FSGNJD(12, fsgnj.d, 0, 1, 0)
+  TEST_FSGNJD(13, fsgnj.d, 1, 1, 1)
+
+  TEST_FSGNJD(20, fsgnjn.d, 1, 0, 0)
+  TEST_FSGNJD(21, fsgnjn.d, 0, 0, 1)
+  TEST_FSGNJD(22, fsgnjn.d, 1, 1, 0)
+  TEST_FSGNJD(23, fsgnjn.d, 0, 1, 1)
+
+  TEST_FSGNJD(30, fsgnjx.d, 0, 0, 0)
+  TEST_FSGNJD(31, fsgnjx.d, 1, 0, 1)
+  TEST_FSGNJD(32, fsgnjx.d, 1, 1, 0)
+  TEST_FSGNJD(33, fsgnjx.d, 0, 1, 1)
+
+// Test fsgnj.s in conjunction with double-precision moves
+#define TEST_FSGNJS(n, rd, rs1, rs2) \
+  TEST_CASE(n, a0, (rd) | (-((rd) >> 31) << 32), \
+    li a1, rs1; \
+    li a2, rs2; \
+    fmv.d.x f1, a1; \
+    fmv.d.x f2, a2; \
+    fsgnj.s f0, f1, f2; \
+    fmv.x.s a0, f0); \
+  TEST_CASE(1##n, a0, (rd) | 0xffffffff00000000, \
+    li a1, rs1; \
+    li a2, rs2; \
+    fmv.d.x f1, a1; \
+    fmv.d.x f2, a2; \
+    fsgnj.s f0, f1, f2; \
+    fmv.x.d a0, f0)
+
+  TEST_FSGNJS(40, 0x7fc00000, 0x7ffffffe12345678, 0)
+  TEST_FSGNJS(41, 0x7fc00000, 0xfffffffe12345678, 0)
+  TEST_FSGNJS(42, 0x7fc00000, 0x7fffffff12345678, 0)
+  TEST_FSGNJS(43, 0x12345678, 0xffffffff12345678, 0)
+
+  TEST_FSGNJS(50, 0x7fc00000, 0x7ffffffe12345678, 0x80000000)
+  TEST_FSGNJS(51, 0x7fc00000, 0xfffffffe12345678, 0x80000000)
+  TEST_FSGNJS(52, 0x7fc00000, 0x7fffffff12345678, 0x80000000)
+  TEST_FSGNJS(53, 0x12345678, 0xffffffff12345678, 0x80000000)
+
+  TEST_FSGNJS(60, 0xffc00000, 0x7ffffffe12345678, 0xffffffff80000000)
+  TEST_FSGNJS(61, 0xffc00000, 0xfffffffe12345678, 0xffffffff80000000)
+  TEST_FSGNJS(62, 0x92345678, 0xffffffff12345678, 0xffffffff80000000)
+  TEST_FSGNJS(63, 0x12345678, 0xffffffff12345678, 0x7fffffff80000000)
+
+// Test fsgnj.d in conjunction with single-precision moves
+#define TEST_FSGNJD_SP(n, isnan, rd, rs1, rs2) \
+  TEST_CASE(n, a0, ((rd) & 0xffffffff) | (-(((rd) >> 31) & 1) << 32), \
+    li a1, rs1; \
+    li a2, rs2; \
+    fmv.d.x f1, a1; \
+    fmv.d.x f2, a2; \
+    fsgnj.d f0, f1, f2; \
+    feq.s a0, f0, f0; \
+    addi a0, a0, -!(isnan); \
+    bnez a0, 1f; \
+    fmv.x.s a0, f0; \
+    1:); \
+  TEST_CASE(1##n, a0, rd, \
+    li a1, rs1; \
+    li a2, rs2; \
+    fmv.d.x f1, a1; \
+    fmv.d.x f2, a2; \
+    fsgnj.d f0, f1, f2; \
+    fmv.x.d a0, f0; \
+    1:)
+
+  TEST_FSGNJD_SP(70, 0, 0xffffffff11111111, 0xffffffff11111111, 0xffffffff11111111)
+  TEST_FSGNJD_SP(71, 1, 0x7fffffff11111111, 0xffffffff11111111, 0x7fffffff11111111)
+  TEST_FSGNJD_SP(72, 0, 0xffffffff11111111, 0xffffffff11111111, 0xffffffff91111111)
+  TEST_FSGNJD_SP(73, 0, 0xffffffff11111111, 0xffffffff11111111, 0x8000000000000000)
+  TEST_FSGNJD_SP(74, 0, 0xffffffff11111111, 0x7fffffff11111111, 0xffffffff11111111)
+  TEST_FSGNJD_SP(75, 1, 0x7fffffff11111111, 0x7fffffff11111111, 0x7fffffff11111111)
+  TEST_FSGNJD_SP(76, 0, 0xffffffff11111111, 0x7fffffff11111111, 0xffffffff91111111)
+  TEST_FSGNJD_SP(77, 0, 0xffffffff11111111, 0x7fffffff11111111, 0x8000000000000000)
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ud/recoding.S b/apps/riscv-tests/isa/rv64ud/recoding.S
new file mode 100644
index 0000000..69ad665
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ud/recoding.S
@@ -0,0 +1,67 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# recoding.S
+#-----------------------------------------------------------------------------
+#
+# Test corner cases of John Hauser's microarchitectural recoding scheme.
+# There are twice as many recoded values as IEEE-754 values; some of these
+# extras are redundant (e.g. Inf) and others are illegal (subnormals with
+# too many bits set).
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+  # Make sure infinities with different mantissas compare as equal.
+  fld f0, minf, a0
+  fld f1, three, a0
+  fmul.d f1, f1, f0
+  TEST_CASE( 2, a0, 1, feq.d a0, f0, f1)
+  TEST_CASE( 3, a0, 1, fle.d a0, f0, f1)
+  TEST_CASE( 4, a0, 0, flt.d a0, f0, f1)
+
+  # Likewise, but for zeroes.
+  fcvt.d.w f0, x0
+  li a0, 1
+  fcvt.d.w f1, a0
+  fmul.d f1, f1, f0
+  TEST_CASE(5, a0, 1, feq.d a0, f0, f1)
+  TEST_CASE(6, a0, 1, fle.d a0, f0, f1)
+  TEST_CASE(7, a0, 0, flt.d a0, f0, f1)
+
+  # When converting small doubles to single-precision subnormals,
+  # ensure that the extra precision is discarded.
+  flw f0, big, a0
+  fld f1, tiny, a0
+  fcvt.s.d f1, f1
+  fmul.s f0, f0, f1
+  fmv.x.s a0, f0
+  lw a1, small
+  TEST_CASE(10, a0, 0, sub a0, a0, a1)
+
+  # Make sure FSD+FLD correctly saves and restores a single-precision value.
+  flw f0, three, a0
+  fadd.s f1, f0, f0
+  fadd.s f0, f0, f0
+  fsd f0, tiny, a0
+  fld f0, tiny, a0
+  TEST_CASE(20, a0, 1, feq.s a0, f0, f1)
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+minf: .double -Inf
+three: .double 3.0
+big: .float 1221
+small: .float 2.9133121e-37
+tiny: .double 2.3860049081905093e-40
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ud/structural.S b/apps/riscv-tests/isa/rv64ud/structural.S
new file mode 100644
index 0000000..3cf87aa
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ud/structural.S
@@ -0,0 +1,58 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# structural.S
+#-----------------------------------------------------------------------------
+#
+# This test verifies that the FPU correctly obviates structural hazards on its
+# writeback port (e.g. fadd followed by fsgnj)
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+li x12, 1
+
+li x2, 0x3FF0000000000000
+li x1, 0x3F800000
+
+#define TEST(nops, errcode)     \
+  fmv.d.x  f4, x0    ;\
+  fmv.s.x  f3, x0    ;\
+  fmv.d.x  f2, x2    ;\
+  fmv.s.x  f1, x1    ;\
+  j 1f ;\
+  .align 5        ;\
+1:fmul.d  f4, f2, f2  ;\
+  nops          ;\
+  fsgnj.s f3, f1, f1 ;\
+  fmv.x.d  x4, f4    ;\
+  fmv.x.s  x5, f3    ;\
+  beq     x1, x5, 2f  ;\
+  RVTEST_FAIL ;\
+2:beq     x2, x4, 2f  ;\
+  RVTEST_FAIL; \
+2:fmv.d.x  f2, zero    ;\
+  fmv.s.x  f1, zero    ;\
+
+TEST(;,2)
+TEST(nop,4)
+TEST(nop;nop,6)
+TEST(nop;nop;nop,8)
+TEST(nop;nop;nop;nop,10)
+TEST(nop;nop;nop;nop;nop,12)
+TEST(nop;nop;nop;nop;nop;nop,14)
+
+RVTEST_PASS
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64uf/Makefrag b/apps/riscv-tests/isa/rv64uf/Makefrag
new file mode 100644
index 0000000..33c11db
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uf/Makefrag
@@ -0,0 +1,12 @@
+#=======================================================================
+# Makefrag for rv64uf tests
+#-----------------------------------------------------------------------
+
+rv64uf_sc_tests = \
+	fadd fdiv fclass fcmp fcvt fcvt_w fmadd fmin \
+	ldst move recoding \
+
+rv64uf_p_tests = $(addprefix rv64uf-p-, $(rv64uf_sc_tests))
+rv64uf_v_tests = $(addprefix rv64uf-v-, $(rv64uf_sc_tests))
+
+spike_tests += $(rv64uf_p_tests) $(rv64uf_v_tests)
diff --git a/apps/riscv-tests/isa/rv64uf/fadd.S b/apps/riscv-tests/isa/rv64uf/fadd.S
new file mode 100644
index 0000000..b6259df
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uf/fadd.S
@@ -0,0 +1,44 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fadd.S
+#-----------------------------------------------------------------------------
+#
+# Test f{add|sub|mul}.s instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_FP_OP2_S( 2,  fadd.s, 0,                3.5,        2.5,        1.0 );
+  TEST_FP_OP2_S( 3,  fadd.s, 1,              -1234,    -1235.1,        1.1 );
+  TEST_FP_OP2_S( 4,  fadd.s, 1,         3.14159265, 3.14159265, 0.00000001 );
+
+  TEST_FP_OP2_S( 5,  fsub.s, 0,                1.5,        2.5,        1.0 );
+  TEST_FP_OP2_S( 6,  fsub.s, 1,              -1234,    -1235.1,       -1.1 );
+  TEST_FP_OP2_S( 7,  fsub.s, 1,         3.14159265, 3.14159265, 0.00000001 );
+
+  TEST_FP_OP2_S( 8,  fmul.s, 0,                2.5,        2.5,        1.0 );
+  TEST_FP_OP2_S( 9,  fmul.s, 1,            1358.61,    -1235.1,       -1.1 );
+  TEST_FP_OP2_S(10,  fmul.s, 1,      3.14159265e-8, 3.14159265, 0.00000001 );
+
+  # Is the canonical NaN generated for Inf - Inf?
+  TEST_FP_OP2_S(11,  fsub.s, 0x10, qNaNf, Inf, Inf);
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64uf/fclass.S b/apps/riscv-tests/isa/rv64uf/fclass.S
new file mode 100644
index 0000000..9bb86b1
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uf/fclass.S
@@ -0,0 +1,40 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fclass.S
+#-----------------------------------------------------------------------------
+#
+# Test fclass.s instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_FCLASS_S( 2, 1 << 0, 0xff800000 )
+  TEST_FCLASS_S( 3, 1 << 1, 0xbf800000 )
+  TEST_FCLASS_S( 4, 1 << 2, 0x807fffff )
+  TEST_FCLASS_S( 5, 1 << 3, 0x80000000 )
+  TEST_FCLASS_S( 6, 1 << 4, 0x00000000 )
+  TEST_FCLASS_S( 7, 1 << 5, 0x007fffff )
+  TEST_FCLASS_S( 8, 1 << 6, 0x3f800000 )
+  TEST_FCLASS_S( 9, 1 << 7, 0x7f800000 )
+  TEST_FCLASS_S(10, 1 << 8, 0x7f800001 )
+  TEST_FCLASS_S(11, 1 << 9, 0x7fc00000 )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64uf/fcmp.S b/apps/riscv-tests/isa/rv64uf/fcmp.S
new file mode 100644
index 0000000..2d7fcc2
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uf/fcmp.S
@@ -0,0 +1,50 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fcmp.S
+#-----------------------------------------------------------------------------
+#
+# Test f{eq|lt|le}.s instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_FP_CMP_OP_S( 2, feq.s, 0x00, 1, -1.36, -1.36)
+  TEST_FP_CMP_OP_S( 3, fle.s, 0x00, 1, -1.36, -1.36)
+  TEST_FP_CMP_OP_S( 4, flt.s, 0x00, 0, -1.36, -1.36)
+
+  TEST_FP_CMP_OP_S( 5, feq.s, 0x00, 0, -1.37, -1.36)
+  TEST_FP_CMP_OP_S( 6, fle.s, 0x00, 1, -1.37, -1.36)
+  TEST_FP_CMP_OP_S( 7, flt.s, 0x00, 1, -1.37, -1.36)
+
+  # Only sNaN should signal invalid for feq.
+  TEST_FP_CMP_OP_S( 8, feq.s, 0x00, 0, NaN, 0)
+  TEST_FP_CMP_OP_S( 9, feq.s, 0x00, 0, NaN, NaN)
+  TEST_FP_CMP_OP_S(10, feq.s, 0x10, 0, sNaNf, 0)
+
+  # qNaN should signal invalid for fle/flt.
+  TEST_FP_CMP_OP_S(11, flt.s, 0x10, 0, NaN, 0)
+  TEST_FP_CMP_OP_S(12, flt.s, 0x10, 0, NaN, NaN)
+  TEST_FP_CMP_OP_S(13, flt.s, 0x10, 0, sNaNf, 0)
+  TEST_FP_CMP_OP_S(14, fle.s, 0x10, 0, NaN, 0)
+  TEST_FP_CMP_OP_S(15, fle.s, 0x10, 0, NaN, NaN)
+  TEST_FP_CMP_OP_S(16, fle.s, 0x10, 0, sNaNf, 0)
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64uf/fcvt.S b/apps/riscv-tests/isa/rv64uf/fcvt.S
new file mode 100644
index 0000000..a41686e
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uf/fcvt.S
@@ -0,0 +1,43 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fcvt.S
+#-----------------------------------------------------------------------------
+#
+# Test fcvt.s.{wu|w|lu|l}, fcvt.s.d, and fcvt.d.s instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_INT_FP_OP_S( 2,  fcvt.s.w,                   2.0,  2);
+  TEST_INT_FP_OP_S( 3,  fcvt.s.w,                  -2.0, -2);
+
+  TEST_INT_FP_OP_S( 4, fcvt.s.wu,                   2.0,  2);
+  TEST_INT_FP_OP_S( 5, fcvt.s.wu,           4.2949673e9, -2);
+
+#if __riscv_xlen >= 64
+  TEST_INT_FP_OP_S( 6,  fcvt.s.l,                   2.0,  2);
+  TEST_INT_FP_OP_S( 7,  fcvt.s.l,                  -2.0, -2);
+
+  TEST_INT_FP_OP_S( 8, fcvt.s.lu,                   2.0,  2);
+  TEST_INT_FP_OP_S( 9, fcvt.s.lu,          1.8446744e19, -2);
+#endif
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64uf/fcvt_w.S b/apps/riscv-tests/isa/rv64uf/fcvt_w.S
new file mode 100644
index 0000000..cad5cba
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uf/fcvt_w.S
@@ -0,0 +1,105 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fcvt_w.S
+#-----------------------------------------------------------------------------
+#
+# Test fcvt{wu|w|lu|l}.s instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_FP_INT_OP_S( 2,  fcvt.w.s, 0x01,         -1, -1.1, rtz);
+  TEST_FP_INT_OP_S( 3,  fcvt.w.s, 0x00,         -1, -1.0, rtz);
+  TEST_FP_INT_OP_S( 4,  fcvt.w.s, 0x01,          0, -0.9, rtz);
+  TEST_FP_INT_OP_S( 5,  fcvt.w.s, 0x01,          0,  0.9, rtz);
+  TEST_FP_INT_OP_S( 6,  fcvt.w.s, 0x00,          1,  1.0, rtz);
+  TEST_FP_INT_OP_S( 7,  fcvt.w.s, 0x01,          1,  1.1, rtz);
+  TEST_FP_INT_OP_S( 8,  fcvt.w.s, 0x10,     -1<<31, -3e9, rtz);
+  TEST_FP_INT_OP_S( 9,  fcvt.w.s, 0x10,  (1<<31)-1,  3e9, rtz);
+
+  TEST_FP_INT_OP_S(12, fcvt.wu.s, 0x10,          0, -3.0, rtz);
+  TEST_FP_INT_OP_S(13, fcvt.wu.s, 0x10,          0, -1.0, rtz);
+  TEST_FP_INT_OP_S(14, fcvt.wu.s, 0x01,          0, -0.9, rtz);
+  TEST_FP_INT_OP_S(15, fcvt.wu.s, 0x01,          0,  0.9, rtz);
+  TEST_FP_INT_OP_S(16, fcvt.wu.s, 0x00,          1,  1.0, rtz);
+  TEST_FP_INT_OP_S(17, fcvt.wu.s, 0x01,          1,  1.1, rtz);
+  TEST_FP_INT_OP_S(18, fcvt.wu.s, 0x10,          0, -3e9, rtz);
+  TEST_FP_INT_OP_S(19, fcvt.wu.s, 0x00, 3000000000,  3e9, rtz);
+
+#if __riscv_xlen >= 64
+  TEST_FP_INT_OP_S(22,  fcvt.l.s, 0x01,         -1, -1.1, rtz);
+  TEST_FP_INT_OP_S(23,  fcvt.l.s, 0x00,         -1, -1.0, rtz);
+  TEST_FP_INT_OP_S(24,  fcvt.l.s, 0x01,          0, -0.9, rtz);
+  TEST_FP_INT_OP_S(25,  fcvt.l.s, 0x01,          0,  0.9, rtz);
+  TEST_FP_INT_OP_S(26,  fcvt.l.s, 0x00,          1,  1.0, rtz);
+  TEST_FP_INT_OP_S(27,  fcvt.l.s, 0x01,          1,  1.1, rtz);
+
+  TEST_FP_INT_OP_S(32, fcvt.lu.s, 0x10,          0, -3.0, rtz);
+  TEST_FP_INT_OP_S(33, fcvt.lu.s, 0x10,          0, -1.0, rtz);
+  TEST_FP_INT_OP_S(34, fcvt.lu.s, 0x01,          0, -0.9, rtz);
+  TEST_FP_INT_OP_S(35, fcvt.lu.s, 0x01,          0,  0.9, rtz);
+  TEST_FP_INT_OP_S(36, fcvt.lu.s, 0x00,          1,  1.0, rtz);
+  TEST_FP_INT_OP_S(37, fcvt.lu.s, 0x01,          1,  1.1, rtz);
+  TEST_FP_INT_OP_S(38, fcvt.lu.s, 0x10,          0, -3e9, rtz);
+#endif
+
+  # test negative NaN, negative infinity conversion
+  TEST_CASE( 42, x1, 0x000000007fffffff, la x1, tdat  ; flw f1,  0(x1); fcvt.w.s x1, f1)
+  TEST_CASE( 44, x1, 0xffffffff80000000, la x1, tdat  ; flw f1,  8(x1); fcvt.w.s x1, f1)
+#if __riscv_xlen >= 64
+  TEST_CASE( 43, x1, 0x7fffffffffffffff, la x1, tdat  ; flw f1,  0(x1); fcvt.l.s x1, f1)
+  TEST_CASE( 45, x1, 0x8000000000000000, la x1, tdat  ; flw f1,  8(x1); fcvt.l.s x1, f1)
+#endif
+
+  # test positive NaN, positive infinity conversion
+  TEST_CASE( 52, x1, 0x000000007fffffff, la x1, tdat  ; flw f1,  4(x1); fcvt.w.s x1, f1)
+  TEST_CASE( 54, x1, 0x000000007fffffff, la x1, tdat  ; flw f1, 12(x1); fcvt.w.s x1, f1)
+#if __riscv_xlen >= 64
+  TEST_CASE( 53, x1, 0x7fffffffffffffff, la x1, tdat  ; flw f1,  4(x1); fcvt.l.s x1, f1)
+  TEST_CASE( 55, x1, 0x7fffffffffffffff, la x1, tdat  ; flw f1, 12(x1); fcvt.l.s x1, f1)
+#endif
+
+  # test NaN, infinity conversions to unsigned integer
+  TEST_CASE( 62, x1, 0xffffffffffffffff, la x1, tdat  ; flw f1,  0(x1); fcvt.wu.s x1, f1)
+  TEST_CASE( 63, x1, 0xffffffffffffffff, la x1, tdat  ; flw f1,  4(x1); fcvt.wu.s x1, f1)
+  TEST_CASE( 64, x1,                  0, la x1, tdat  ; flw f1,  8(x1); fcvt.wu.s x1, f1)
+  TEST_CASE( 65, x1, 0xffffffffffffffff, la x1, tdat  ; flw f1, 12(x1); fcvt.wu.s x1, f1)
+#if __riscv_xlen >= 64
+  TEST_CASE( 66, x1, 0xffffffffffffffff, la x1, tdat  ; flw f1,  0(x1); fcvt.lu.s x1, f1)
+  TEST_CASE( 67, x1, 0xffffffffffffffff, la x1, tdat  ; flw f1,  4(x1); fcvt.lu.s x1, f1)
+  TEST_CASE( 68, x1,                  0, la x1, tdat  ; flw f1,  8(x1); fcvt.lu.s x1, f1)
+  TEST_CASE( 69, x1, 0xffffffffffffffff, la x1, tdat  ; flw f1, 12(x1); fcvt.lu.s x1, f1)
+#endif
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+# -NaN, NaN, -inf, +inf
+tdat:
+.word 0xffffffff
+.word 0x7fffffff
+.word 0xff800000
+.word 0x7f800000
+
+tdat_d:
+.dword 0xffffffffffffffff
+.dword 0x7fffffffffffffff
+.dword 0xfff0000000000000
+.dword 0x7ff0000000000000
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64uf/fdiv.S b/apps/riscv-tests/isa/rv64uf/fdiv.S
new file mode 100644
index 0000000..a75a23d
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uf/fdiv.S
@@ -0,0 +1,40 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fdiv.S
+#-----------------------------------------------------------------------------
+#
+# Test f{div|sqrt}.s instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_FP_OP2_S(2,  fdiv.s, 1, 1.1557273520668288, 3.14159265, 2.71828182 );
+  TEST_FP_OP2_S(3,  fdiv.s, 1,-0.9991093838555584,      -1234,     1235.1 );
+  TEST_FP_OP2_S(4,  fdiv.s, 0,         3.14159265, 3.14159265,        1.0 );
+
+  TEST_FP_OP1_S(5,  fsqrt.s, 1, 1.7724538498928541, 3.14159265 );
+  TEST_FP_OP1_S(6,  fsqrt.s, 0,                100,      10000 );
+
+  TEST_FP_OP1_S_DWORD_RESULT(7,  fsqrt.s, 0x10, 0x7FC00000, -1.0 );
+
+  TEST_FP_OP1_S(8,  fsqrt.s, 1, 13.076696, 171.0);
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64uf/fmadd.S b/apps/riscv-tests/isa/rv64uf/fmadd.S
new file mode 100644
index 0000000..241bead
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uf/fmadd.S
@@ -0,0 +1,45 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fmadd.S
+#-----------------------------------------------------------------------------
+#
+# Test f[n]m{add|sub}.s and f[n]m{add|sub}.d instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_FP_OP3_S( 2,  fmadd.s, 0,                 3.5,  1.0,        2.5,        1.0 );
+  TEST_FP_OP3_S( 3,  fmadd.s, 1,              1236.2, -1.0,    -1235.1,        1.1 );
+  TEST_FP_OP3_S( 4,  fmadd.s, 0,               -12.0,  2.0,       -5.0,       -2.0 );
+
+  TEST_FP_OP3_S( 5, fnmadd.s, 0,                -3.5,  1.0,        2.5,        1.0 );
+  TEST_FP_OP3_S( 6, fnmadd.s, 1,             -1236.2, -1.0,    -1235.1,        1.1 );
+  TEST_FP_OP3_S( 7, fnmadd.s, 0,                12.0,  2.0,       -5.0,       -2.0 );
+
+  TEST_FP_OP3_S( 8,  fmsub.s, 0,                 1.5,  1.0,        2.5,        1.0 );
+  TEST_FP_OP3_S( 9,  fmsub.s, 1,                1234, -1.0,    -1235.1,        1.1 );
+  TEST_FP_OP3_S(10,  fmsub.s, 0,                -8.0,  2.0,       -5.0,       -2.0 );
+
+  TEST_FP_OP3_S(11, fnmsub.s, 0,                -1.5,  1.0,        2.5,        1.0 );
+  TEST_FP_OP3_S(12, fnmsub.s, 1,               -1234, -1.0,    -1235.1,        1.1 );
+  TEST_FP_OP3_S(13, fnmsub.s, 0,                 8.0,  2.0,       -5.0,       -2.0 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64uf/fmin.S b/apps/riscv-tests/isa/rv64uf/fmin.S
new file mode 100644
index 0000000..1f97533
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uf/fmin.S
@@ -0,0 +1,54 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fmin.S
+#-----------------------------------------------------------------------------
+#
+# Test f{min|max}.s instructinos.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_FP_OP2_S( 2,  fmin.s, 0,        1.0,        2.5,        1.0 );
+  TEST_FP_OP2_S( 3,  fmin.s, 0,    -1235.1,    -1235.1,        1.1 );
+  TEST_FP_OP2_S( 4,  fmin.s, 0,    -1235.1,        1.1,    -1235.1 );
+  TEST_FP_OP2_S( 5,  fmin.s, 0,    -1235.1,        NaN,    -1235.1 );
+  TEST_FP_OP2_S( 6,  fmin.s, 0, 0.00000001, 3.14159265, 0.00000001 );
+  TEST_FP_OP2_S( 7,  fmin.s, 0,       -2.0,       -1.0,       -2.0 );
+
+  TEST_FP_OP2_S(12,  fmax.s, 0,        2.5,        2.5,        1.0 );
+  TEST_FP_OP2_S(13,  fmax.s, 0,        1.1,    -1235.1,        1.1 );
+  TEST_FP_OP2_S(14,  fmax.s, 0,        1.1,        1.1,    -1235.1 );
+  TEST_FP_OP2_S(15,  fmax.s, 0,    -1235.1,        NaN,    -1235.1 );
+  TEST_FP_OP2_S(16,  fmax.s, 0, 3.14159265, 3.14159265, 0.00000001 );
+  TEST_FP_OP2_S(17,  fmax.s, 0,       -1.0,       -1.0,       -2.0 );
+
+  # FMAX(sNaN, x) = x
+  TEST_FP_OP2_S(20,  fmax.s, 0x10, 1.0, sNaNf, 1.0);
+  # FMAX(qNaN, qNaN) = canonical NaN
+  TEST_FP_OP2_S(21,  fmax.s, 0x00, qNaNf, NaN, NaN);
+
+  # -0.0 < +0.0
+  TEST_FP_OP2_S(30,  fmin.s, 0,       -0.0,       -0.0,        0.0 );
+  TEST_FP_OP2_S(31,  fmin.s, 0,       -0.0,        0.0,       -0.0 );
+  TEST_FP_OP2_S(32,  fmax.s, 0,        0.0,       -0.0,        0.0 );
+  TEST_FP_OP2_S(33,  fmax.s, 0,        0.0,        0.0,       -0.0 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64uf/ldst.S b/apps/riscv-tests/isa/rv64uf/ldst.S
new file mode 100644
index 0000000..c35dd8d
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uf/ldst.S
@@ -0,0 +1,38 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# ldst.S
+#-----------------------------------------------------------------------------
+#
+# This test verifies that flw, fld, fsw, and fsd work properly.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a0, 0x40000000deadbeef, la a1, tdat; flw f1, 4(a1); fsw f1, 20(a1); ld a0, 16(a1))
+  TEST_CASE(3, a0, 0x1337d00dbf800000, la a1, tdat; flw f1, 0(a1); fsw f1, 24(a1); ld a0, 24(a1))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+tdat:
+.word 0xbf800000
+.word 0x40000000
+.word 0x40400000
+.word 0xc0800000
+.word 0xdeadbeef
+.word 0xcafebabe
+.word 0xabad1dea
+.word 0x1337d00d
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64uf/move.S b/apps/riscv-tests/isa/rv64uf/move.S
new file mode 100644
index 0000000..60f7cf3
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uf/move.S
@@ -0,0 +1,58 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# move.S
+#-----------------------------------------------------------------------------
+#
+# This test verifies that the fmv.s.x, fmv.x.s, and fsgnj[x|n].d instructions
+# and the fcsr work properly.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a1, 1, csrwi fcsr, 1; li a0, 0x1234; fssr a1, a0)
+  TEST_CASE(3, a0, 0x34, frsr a0)
+  TEST_CASE(4, a0, 0x14, frflags a0)
+  TEST_CASE(5, a0, 0x01, csrrwi a0, frm, 2)
+  TEST_CASE(6, a0, 0x54, frsr a0)
+  TEST_CASE(7, a0, 0x14, csrrci a0, fflags, 4)
+  TEST_CASE(8, a0, 0x50, frsr a0)
+
+#define TEST_FSGNJS(n, insn, new_sign, rs1_sign, rs2_sign) \
+  TEST_CASE(n, a0, 0x12345678 | (-(new_sign) << 31), \
+    li a1, ((rs1_sign) << 31) | 0x12345678; \
+    li a2, -(rs2_sign); \
+    fmv.s.x f1, a1; \
+    fmv.s.x f2, a2; \
+    insn f0, f1, f2; \
+    fmv.x.s a0, f0)
+
+  TEST_FSGNJS(10, fsgnj.s, 0, 0, 0)
+  TEST_FSGNJS(11, fsgnj.s, 1, 0, 1)
+  TEST_FSGNJS(12, fsgnj.s, 0, 1, 0)
+  TEST_FSGNJS(13, fsgnj.s, 1, 1, 1)
+
+  TEST_FSGNJS(20, fsgnjn.s, 1, 0, 0)
+  TEST_FSGNJS(21, fsgnjn.s, 0, 0, 1)
+  TEST_FSGNJS(22, fsgnjn.s, 1, 1, 0)
+  TEST_FSGNJS(23, fsgnjn.s, 0, 1, 1)
+
+  TEST_FSGNJS(30, fsgnjx.s, 0, 0, 0)
+  TEST_FSGNJS(31, fsgnjx.s, 1, 0, 1)
+  TEST_FSGNJS(32, fsgnjx.s, 1, 1, 0)
+  TEST_FSGNJS(33, fsgnjx.s, 0, 1, 1)
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64uf/recoding.S b/apps/riscv-tests/isa/rv64uf/recoding.S
new file mode 100644
index 0000000..802be66
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uf/recoding.S
@@ -0,0 +1,46 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# recoding.S
+#-----------------------------------------------------------------------------
+#
+# Test corner cases of John Hauser's microarchitectural recoding scheme.
+# There are twice as many recoded values as IEEE-754 values; some of these
+# extras are redundant (e.g. Inf) and others are illegal (subnormals with
+# too many bits set).
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+  # Make sure infinities with different mantissas compare as equal.
+  flw f0, minf, a0
+  flw f1, three, a0
+  fmul.s f1, f1, f0
+  TEST_CASE( 2, a0, 1, feq.s a0, f0, f1)
+  TEST_CASE( 3, a0, 1, fle.s a0, f0, f1)
+  TEST_CASE( 4, a0, 0, flt.s a0, f0, f1)
+
+  # Likewise, but for zeroes.
+  fcvt.s.w f0, x0
+  li a0, 1
+  fcvt.s.w f1, a0
+  fmul.s f1, f1, f0
+  TEST_CASE(5, a0, 1, feq.s a0, f0, f1)
+  TEST_CASE(6, a0, 1, fle.s a0, f0, f1)
+  TEST_CASE(7, a0, 0, flt.s a0, f0, f1)
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+minf: .float -Inf
+three: .float 3.0
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/Makefrag b/apps/riscv-tests/isa/rv64ui/Makefrag
new file mode 100644
index 0000000..1867ea5
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/Makefrag
@@ -0,0 +1,27 @@
+#=======================================================================
+# Makefrag for rv64ui tests
+#-----------------------------------------------------------------------
+
+rv64ui_sc_tests = \
+	add addi addiw addw \
+	and andi \
+	auipc \
+	beq bge bgeu blt bltu bne \
+	simple \
+	fence_i \
+	jal jalr \
+	lb lbu lh lhu lw lwu ld \
+	lui \
+	or ori \
+	sb sh sw sd \
+	sll slli slliw sllw \
+	slt slti sltiu sltu \
+	sra srai sraiw sraw \
+	srl srli srliw srlw \
+	sub subw \
+	xor xori \
+
+rv64ui_p_tests = $(addprefix rv64ui-p-, $(rv64ui_sc_tests))
+rv64ui_v_tests = $(addprefix rv64ui-v-, $(rv64ui_sc_tests))
+
+spike_tests += $(rv64ui_p_tests) $(rv64ui_v_tests)
diff --git a/apps/riscv-tests/isa/rv64ui/add.S b/apps/riscv-tests/isa/rv64ui/add.S
new file mode 100644
index 0000000..0696428
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/add.S
@@ -0,0 +1,85 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# add.S
+#-----------------------------------------------------------------------------
+#
+# Test add instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  add, 0x00000000, 0x00000000, 0x00000000 );
+  TEST_RR_OP( 3,  add, 0x00000002, 0x00000001, 0x00000001 );
+  TEST_RR_OP( 4,  add, 0x0000000a, 0x00000003, 0x00000007 );
+
+  TEST_RR_OP( 5,  add, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 );
+  TEST_RR_OP( 6,  add, 0xffffffff80000000, 0xffffffff80000000, 0x00000000 );
+  TEST_RR_OP( 7,  add, 0xffffffff7fff8000, 0xffffffff80000000, 0xffffffffffff8000 );
+
+  TEST_RR_OP( 8,  add, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff );
+  TEST_RR_OP( 9,  add, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 );
+  TEST_RR_OP( 10, add, 0x0000000080007ffe, 0x000000007fffffff, 0x0000000000007fff );
+
+  TEST_RR_OP( 11, add, 0xffffffff80007fff, 0xffffffff80000000, 0x0000000000007fff );
+  TEST_RR_OP( 12, add, 0x000000007fff7fff, 0x000000007fffffff, 0xffffffffffff8000 );
+
+  TEST_RR_OP( 13, add, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff );
+  TEST_RR_OP( 14, add, 0x0000000000000000, 0xffffffffffffffff, 0x0000000000000001 );
+  TEST_RR_OP( 15, add, 0xfffffffffffffffe, 0xffffffffffffffff, 0xffffffffffffffff );
+
+  TEST_RR_OP( 16, add, 0x0000000080000000, 0x0000000000000001, 0x000000007fffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 17, add, 24, 13, 11 );
+  TEST_RR_SRC2_EQ_DEST( 18, add, 25, 14, 11 );
+  TEST_RR_SRC12_EQ_DEST( 19, add, 26, 13 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 20, 0, add, 24, 13, 11 );
+  TEST_RR_DEST_BYPASS( 21, 1, add, 25, 14, 11 );
+  TEST_RR_DEST_BYPASS( 22, 2, add, 26, 15, 11 );
+
+  TEST_RR_SRC12_BYPASS( 23, 0, 0, add, 24, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 24, 0, 1, add, 25, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 25, 0, 2, add, 26, 15, 11 );
+  TEST_RR_SRC12_BYPASS( 26, 1, 0, add, 24, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 27, 1, 1, add, 25, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 28, 2, 0, add, 26, 15, 11 );
+
+  TEST_RR_SRC21_BYPASS( 29, 0, 0, add, 24, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 30, 0, 1, add, 25, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 31, 0, 2, add, 26, 15, 11 );
+  TEST_RR_SRC21_BYPASS( 32, 1, 0, add, 24, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 33, 1, 1, add, 25, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 34, 2, 0, add, 26, 15, 11 );
+
+  TEST_RR_ZEROSRC1( 35, add, 15, 15 );
+  TEST_RR_ZEROSRC2( 36, add, 32, 32 );
+  TEST_RR_ZEROSRC12( 37, add, 0 );
+  TEST_RR_ZERODEST( 38, add, 16, 30 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/addi.S b/apps/riscv-tests/isa/rv64ui/addi.S
new file mode 100644
index 0000000..e6b67ca
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/addi.S
@@ -0,0 +1,71 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# addi.S
+#-----------------------------------------------------------------------------
+#
+# Test addi instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_OP( 2,  addi, 0x00000000, 0x00000000, 0x000 );
+  TEST_IMM_OP( 3,  addi, 0x00000002, 0x00000001, 0x001 );
+  TEST_IMM_OP( 4,  addi, 0x0000000a, 0x00000003, 0x007 );
+
+  TEST_IMM_OP( 5,  addi, 0xfffffffffffff800, 0x0000000000000000, 0x800 );
+  TEST_IMM_OP( 6,  addi, 0xffffffff80000000, 0xffffffff80000000, 0x000 );
+  TEST_IMM_OP( 7,  addi, 0xffffffff7ffff800, 0xffffffff80000000, 0x800 );
+
+  TEST_IMM_OP( 8,  addi, 0x00000000000007ff, 0x00000000, 0x7ff );
+  TEST_IMM_OP( 9,  addi, 0x000000007fffffff, 0x7fffffff, 0x000 );
+  TEST_IMM_OP( 10, addi, 0x00000000800007fe, 0x7fffffff, 0x7ff );
+
+  TEST_IMM_OP( 11, addi, 0xffffffff800007ff, 0xffffffff80000000, 0x7ff );
+  TEST_IMM_OP( 12, addi, 0x000000007ffff7ff, 0x000000007fffffff, 0x800 );
+
+  TEST_IMM_OP( 13, addi, 0xffffffffffffffff, 0x0000000000000000, 0xfff );
+  TEST_IMM_OP( 14, addi, 0x0000000000000000, 0xffffffffffffffff, 0x001 );
+  TEST_IMM_OP( 15, addi, 0xfffffffffffffffe, 0xffffffffffffffff, 0xfff );
+
+  TEST_IMM_OP( 16, addi, 0x0000000080000000, 0x7fffffff, 0x001 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_SRC1_EQ_DEST( 17, addi, 24, 13, 11 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_DEST_BYPASS( 18, 0, addi, 24, 13, 11 );
+  TEST_IMM_DEST_BYPASS( 19, 1, addi, 23, 13, 10 );
+  TEST_IMM_DEST_BYPASS( 20, 2, addi, 22, 13,  9 );
+
+  TEST_IMM_SRC1_BYPASS( 21, 0, addi, 24, 13, 11 );
+  TEST_IMM_SRC1_BYPASS( 22, 1, addi, 23, 13, 10 );
+  TEST_IMM_SRC1_BYPASS( 23, 2, addi, 22, 13,  9 );
+
+  TEST_IMM_ZEROSRC1( 24, addi, 32, 32 );
+  TEST_IMM_ZERODEST( 25, addi, 33, 50 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/addiw.S b/apps/riscv-tests/isa/rv64ui/addiw.S
new file mode 100644
index 0000000..c0f9a61
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/addiw.S
@@ -0,0 +1,71 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# addiw.S
+#-----------------------------------------------------------------------------
+#
+# Test addiw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_OP( 2,  addiw, 0x00000000, 0x00000000, 0x000 );
+  TEST_IMM_OP( 3,  addiw, 0x00000002, 0x00000001, 0x001 );
+  TEST_IMM_OP( 4,  addiw, 0x0000000a, 0x00000003, 0x007 );
+
+  TEST_IMM_OP( 5,  addiw, 0xfffffffffffff800, 0x0000000000000000, 0x800 );
+  TEST_IMM_OP( 6,  addiw, 0xffffffff80000000, 0xffffffff80000000, 0x000 );
+  TEST_IMM_OP( 7,  addiw, 0x000000007ffff800, 0xffffffff80000000, 0x800 );
+
+  TEST_IMM_OP( 8,  addiw, 0x00000000000007ff, 0x00000000, 0x7ff );
+  TEST_IMM_OP( 9,  addiw, 0x000000007fffffff, 0x7fffffff, 0x000 );
+  TEST_IMM_OP( 10, addiw, 0xffffffff800007fe, 0x7fffffff, 0x7ff );
+
+  TEST_IMM_OP( 11, addiw, 0xffffffff800007ff, 0xffffffff80000000, 0x7ff );
+  TEST_IMM_OP( 12, addiw, 0x000000007ffff7ff, 0x000000007fffffff, 0x800 );
+
+  TEST_IMM_OP( 13, addiw, 0xffffffffffffffff, 0x0000000000000000, 0xfff );
+  TEST_IMM_OP( 14, addiw, 0x0000000000000000, 0xffffffffffffffff, 0x001 );
+  TEST_IMM_OP( 15, addiw, 0xfffffffffffffffe, 0xffffffffffffffff, 0xfff );
+
+  TEST_IMM_OP( 16, addiw, 0xffffffff80000000, 0x7fffffff, 0x001 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_SRC1_EQ_DEST( 17, addiw, 24, 13, 11 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_DEST_BYPASS( 18, 0, addiw, 24, 13, 11 );
+  TEST_IMM_DEST_BYPASS( 19, 1, addiw, 23, 13, 10 );
+  TEST_IMM_DEST_BYPASS( 20, 2, addiw, 22, 13,  9 );
+
+  TEST_IMM_SRC1_BYPASS( 21, 0, addiw, 24, 13, 11 );
+  TEST_IMM_SRC1_BYPASS( 22, 1, addiw, 23, 13, 10 );
+  TEST_IMM_SRC1_BYPASS( 23, 2, addiw, 22, 13,  9 );
+
+  TEST_IMM_ZEROSRC1( 24, addiw, 32, 32 );
+  TEST_IMM_ZERODEST( 25, addiw, 33, 50 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/addw.S b/apps/riscv-tests/isa/rv64ui/addw.S
new file mode 100644
index 0000000..ad7fe0b
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/addw.S
@@ -0,0 +1,85 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# addw.S
+#-----------------------------------------------------------------------------
+#
+# Test addw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  addw, 0x00000000, 0x00000000, 0x00000000 );
+  TEST_RR_OP( 3,  addw, 0x00000002, 0x00000001, 0x00000001 );
+  TEST_RR_OP( 4,  addw, 0x0000000a, 0x00000003, 0x00000007 );
+
+  TEST_RR_OP( 5,  addw, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 );
+  TEST_RR_OP( 6,  addw, 0xffffffff80000000, 0xffffffff80000000, 0x00000000 );
+  TEST_RR_OP( 7,  addw, 0x000000007fff8000, 0xffffffff80000000, 0xffffffffffff8000 );
+
+  TEST_RR_OP( 8,  addw, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff );
+  TEST_RR_OP( 9,  addw, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 );
+  TEST_RR_OP( 10, addw, 0xffffffff80007ffe, 0x000000007fffffff, 0x0000000000007fff );
+
+  TEST_RR_OP( 11, addw, 0xffffffff80007fff, 0xffffffff80000000, 0x0000000000007fff );
+  TEST_RR_OP( 12, addw, 0x000000007fff7fff, 0x000000007fffffff, 0xffffffffffff8000 );
+
+  TEST_RR_OP( 13, addw, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff );
+  TEST_RR_OP( 14, addw, 0x0000000000000000, 0xffffffffffffffff, 0x0000000000000001 );
+  TEST_RR_OP( 15, addw, 0xfffffffffffffffe, 0xffffffffffffffff, 0xffffffffffffffff );
+
+  TEST_RR_OP( 16, addw, 0xffffffff80000000, 0x0000000000000001, 0x000000007fffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 17, addw, 24, 13, 11 );
+  TEST_RR_SRC2_EQ_DEST( 18, addw, 25, 14, 11 );
+  TEST_RR_SRC12_EQ_DEST( 19, addw, 26, 13 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 20, 0, addw, 24, 13, 11 );
+  TEST_RR_DEST_BYPASS( 21, 1, addw, 25, 14, 11 );
+  TEST_RR_DEST_BYPASS( 22, 2, addw, 26, 15, 11 );
+
+  TEST_RR_SRC12_BYPASS( 23, 0, 0, addw, 24, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 24, 0, 1, addw, 25, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 25, 0, 2, addw, 26, 15, 11 );
+  TEST_RR_SRC12_BYPASS( 26, 1, 0, addw, 24, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 27, 1, 1, addw, 25, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 28, 2, 0, addw, 26, 15, 11 );
+
+  TEST_RR_SRC21_BYPASS( 29, 0, 0, addw, 24, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 30, 0, 1, addw, 25, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 31, 0, 2, addw, 26, 15, 11 );
+  TEST_RR_SRC21_BYPASS( 32, 1, 0, addw, 24, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 33, 1, 1, addw, 25, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 34, 2, 0, addw, 26, 15, 11 );
+
+  TEST_RR_ZEROSRC1( 35, addw, 15, 15 );
+  TEST_RR_ZEROSRC2( 36, addw, 32, 32 );
+  TEST_RR_ZEROSRC12( 37, addw, 0 );
+  TEST_RR_ZERODEST( 38, addw, 16, 30 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/and.S b/apps/riscv-tests/isa/rv64ui/and.S
new file mode 100644
index 0000000..3f63790
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/and.S
@@ -0,0 +1,69 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# and.S
+#-----------------------------------------------------------------------------
+#
+# Test and instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Logical tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_OP( 3, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_OP( 4, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
+  TEST_RR_OP( 5, and, 0xf000f000, 0xf00ff00f, 0xf0f0f0f0 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 6, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC2_EQ_DEST( 7, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_SRC12_EQ_DEST( 8, and, 0xff00ff00, 0xff00ff00 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 9,  0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_DEST_BYPASS( 10, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_DEST_BYPASS( 11, 2, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
+
+  TEST_RR_SRC12_BYPASS( 12, 0, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC12_BYPASS( 13, 0, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_SRC12_BYPASS( 14, 0, 2, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
+  TEST_RR_SRC12_BYPASS( 15, 1, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC12_BYPASS( 16, 1, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_SRC12_BYPASS( 17, 2, 0, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
+
+  TEST_RR_SRC21_BYPASS( 18, 0, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC21_BYPASS( 19, 0, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_SRC21_BYPASS( 20, 0, 2, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
+  TEST_RR_SRC21_BYPASS( 21, 1, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC21_BYPASS( 22, 1, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_SRC21_BYPASS( 23, 2, 0, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
+
+  TEST_RR_ZEROSRC1( 24, and, 0, 0xff00ff00 );
+  TEST_RR_ZEROSRC2( 25, and, 0, 0x00ff00ff );
+  TEST_RR_ZEROSRC12( 26, and, 0 );
+  TEST_RR_ZERODEST( 27, and, 0x11111111, 0x22222222 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/andi.S b/apps/riscv-tests/isa/rv64ui/andi.S
new file mode 100644
index 0000000..913af9d
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/andi.S
@@ -0,0 +1,55 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# andi.S
+#-----------------------------------------------------------------------------
+#
+# Test andi instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Logical tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_OP( 2, andi, 0xff00ff00, 0xff00ff00, 0xf0f );
+  TEST_IMM_OP( 3, andi, 0x000000f0, 0x0ff00ff0, 0x0f0 );
+  TEST_IMM_OP( 4, andi, 0x0000000f, 0x00ff00ff, 0x70f );
+  TEST_IMM_OP( 5, andi, 0x00000000, 0xf00ff00f, 0x0f0 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_SRC1_EQ_DEST( 6, andi, 0x00000000, 0xff00ff00, 0x0f0 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_DEST_BYPASS( 7,  0, andi, 0x00000700, 0x0ff00ff0, 0x70f );
+  TEST_IMM_DEST_BYPASS( 8,  1, andi, 0x000000f0, 0x00ff00ff, 0x0f0 );
+  TEST_IMM_DEST_BYPASS( 9,  2, andi, 0xf00ff00f, 0xf00ff00f, 0xf0f );
+
+  TEST_IMM_SRC1_BYPASS( 10, 0, andi, 0x00000700, 0x0ff00ff0, 0x70f );
+  TEST_IMM_SRC1_BYPASS( 11, 1, andi, 0x000000f0, 0x00ff00ff, 0x0f0 );
+  TEST_IMM_SRC1_BYPASS( 12, 2, andi, 0x0000000f, 0xf00ff00f, 0x70f );
+
+  TEST_IMM_ZEROSRC1( 13, andi, 0, 0x0f0 );
+  TEST_IMM_ZERODEST( 14, andi, 0x00ff00ff, 0x70f );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/auipc.S b/apps/riscv-tests/isa/rv64ui/auipc.S
new file mode 100644
index 0000000..6fe5962
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/auipc.S
@@ -0,0 +1,39 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# auipc.S
+#-----------------------------------------------------------------------------
+#
+# Test auipc instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a0, 10000, \
+    .align 3; \
+    lla a0, 1f + 10000; \
+    jal a1, 1f; \
+    1: sub a0, a0, a1; \
+  )
+
+  TEST_CASE(3, a0, -10000, \
+    .align 3; \
+    lla a0, 1f - 10000; \
+    jal a1, 1f; \
+    1: sub a0, a0, a1; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/beq.S b/apps/riscv-tests/isa/rv64ui/beq.S
new file mode 100644
index 0000000..436db8c
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/beq.S
@@ -0,0 +1,73 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# beq.S
+#-----------------------------------------------------------------------------
+#
+# Test beq instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Branch tests
+  #-------------------------------------------------------------
+
+  # Each test checks both forward and backward branches
+
+  TEST_BR2_OP_TAKEN( 2, beq,  0,  0 );
+  TEST_BR2_OP_TAKEN( 3, beq,  1,  1 );
+  TEST_BR2_OP_TAKEN( 4, beq, -1, -1 );
+
+  TEST_BR2_OP_NOTTAKEN( 5, beq,  0,  1 );
+  TEST_BR2_OP_NOTTAKEN( 6, beq,  1,  0 );
+  TEST_BR2_OP_NOTTAKEN( 7, beq, -1,  1 );
+  TEST_BR2_OP_NOTTAKEN( 8, beq,  1, -1 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_BR2_SRC12_BYPASS( 9,  0, 0, beq, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 10, 0, 1, beq, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 11, 0, 2, beq, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 12, 1, 0, beq, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 13, 1, 1, beq, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 14, 2, 0, beq, 0, -1 );
+
+  TEST_BR2_SRC12_BYPASS( 15, 0, 0, beq, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 16, 0, 1, beq, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 17, 0, 2, beq, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 18, 1, 0, beq, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 19, 1, 1, beq, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 20, 2, 0, beq, 0, -1 );
+
+  #-------------------------------------------------------------
+  # Test delay slot instructions not executed nor bypassed
+  #-------------------------------------------------------------
+
+  TEST_CASE( 21, x1, 3, \
+    li  x1, 1; \
+    beq x0, x0, 1f; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+1:  addi x1, x1, 1; \
+    addi x1, x1, 1; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/bge.S b/apps/riscv-tests/isa/rv64ui/bge.S
new file mode 100644
index 0000000..04aebbc
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/bge.S
@@ -0,0 +1,76 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# bge.S
+#-----------------------------------------------------------------------------
+#
+# Test bge instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Branch tests
+  #-------------------------------------------------------------
+
+  # Each test checks both forward and backward branches
+
+  TEST_BR2_OP_TAKEN( 2, bge,  0,  0 );
+  TEST_BR2_OP_TAKEN( 3, bge,  1,  1 );
+  TEST_BR2_OP_TAKEN( 4, bge, -1, -1 );
+  TEST_BR2_OP_TAKEN( 5, bge,  1,  0 );
+  TEST_BR2_OP_TAKEN( 6, bge,  1, -1 );
+  TEST_BR2_OP_TAKEN( 7, bge, -1, -2 );
+
+  TEST_BR2_OP_NOTTAKEN(  8, bge,  0,  1 );
+  TEST_BR2_OP_NOTTAKEN(  9, bge, -1,  1 );
+  TEST_BR2_OP_NOTTAKEN( 10, bge, -2, -1 );
+  TEST_BR2_OP_NOTTAKEN( 11, bge, -2,  1 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_BR2_SRC12_BYPASS( 12, 0, 0, bge, -1, 0 );
+  TEST_BR2_SRC12_BYPASS( 13, 0, 1, bge, -1, 0 );
+  TEST_BR2_SRC12_BYPASS( 14, 0, 2, bge, -1, 0 );
+  TEST_BR2_SRC12_BYPASS( 15, 1, 0, bge, -1, 0 );
+  TEST_BR2_SRC12_BYPASS( 16, 1, 1, bge, -1, 0 );
+  TEST_BR2_SRC12_BYPASS( 17, 2, 0, bge, -1, 0 );
+
+  TEST_BR2_SRC12_BYPASS( 18, 0, 0, bge, -1, 0 );
+  TEST_BR2_SRC12_BYPASS( 19, 0, 1, bge, -1, 0 );
+  TEST_BR2_SRC12_BYPASS( 20, 0, 2, bge, -1, 0 );
+  TEST_BR2_SRC12_BYPASS( 21, 1, 0, bge, -1, 0 );
+  TEST_BR2_SRC12_BYPASS( 22, 1, 1, bge, -1, 0 );
+  TEST_BR2_SRC12_BYPASS( 23, 2, 0, bge, -1, 0 );
+
+  #-------------------------------------------------------------
+  # Test delay slot instructions not executed nor bypassed
+  #-------------------------------------------------------------
+
+  TEST_CASE( 24, x1, 3, \
+    li  x1, 1; \
+    bge x1, x0, 1f; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+1:  addi x1, x1, 1; \
+    addi x1, x1, 1; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/bgeu.S b/apps/riscv-tests/isa/rv64ui/bgeu.S
new file mode 100644
index 0000000..36b6b3a
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/bgeu.S
@@ -0,0 +1,76 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# bgeu.S
+#-----------------------------------------------------------------------------
+#
+# Test bgeu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Branch tests
+  #-------------------------------------------------------------
+
+  # Each test checks both forward and backward branches
+
+  TEST_BR2_OP_TAKEN( 2, bgeu, 0x00000000, 0x00000000 );
+  TEST_BR2_OP_TAKEN( 3, bgeu, 0x00000001, 0x00000001 );
+  TEST_BR2_OP_TAKEN( 4, bgeu, 0xffffffff, 0xffffffff );
+  TEST_BR2_OP_TAKEN( 5, bgeu, 0x00000001, 0x00000000 );
+  TEST_BR2_OP_TAKEN( 6, bgeu, 0xffffffff, 0xfffffffe );
+  TEST_BR2_OP_TAKEN( 7, bgeu, 0xffffffff, 0x00000000 );
+
+  TEST_BR2_OP_NOTTAKEN(  8, bgeu, 0x00000000, 0x00000001 );
+  TEST_BR2_OP_NOTTAKEN(  9, bgeu, 0xfffffffe, 0xffffffff );
+  TEST_BR2_OP_NOTTAKEN( 10, bgeu, 0x00000000, 0xffffffff );
+  TEST_BR2_OP_NOTTAKEN( 11, bgeu, 0x7fffffff, 0x80000000 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_BR2_SRC12_BYPASS( 12, 0, 0, bgeu, 0xefffffff, 0xf0000000 );
+  TEST_BR2_SRC12_BYPASS( 13, 0, 1, bgeu, 0xefffffff, 0xf0000000 );
+  TEST_BR2_SRC12_BYPASS( 14, 0, 2, bgeu, 0xefffffff, 0xf0000000 );
+  TEST_BR2_SRC12_BYPASS( 15, 1, 0, bgeu, 0xefffffff, 0xf0000000 );
+  TEST_BR2_SRC12_BYPASS( 16, 1, 1, bgeu, 0xefffffff, 0xf0000000 );
+  TEST_BR2_SRC12_BYPASS( 17, 2, 0, bgeu, 0xefffffff, 0xf0000000 );
+
+  TEST_BR2_SRC12_BYPASS( 18, 0, 0, bgeu, 0xefffffff, 0xf0000000 );
+  TEST_BR2_SRC12_BYPASS( 19, 0, 1, bgeu, 0xefffffff, 0xf0000000 );
+  TEST_BR2_SRC12_BYPASS( 20, 0, 2, bgeu, 0xefffffff, 0xf0000000 );
+  TEST_BR2_SRC12_BYPASS( 21, 1, 0, bgeu, 0xefffffff, 0xf0000000 );
+  TEST_BR2_SRC12_BYPASS( 22, 1, 1, bgeu, 0xefffffff, 0xf0000000 );
+  TEST_BR2_SRC12_BYPASS( 23, 2, 0, bgeu, 0xefffffff, 0xf0000000 );
+
+  #-------------------------------------------------------------
+  # Test delay slot instructions not executed nor bypassed
+  #-------------------------------------------------------------
+
+  TEST_CASE( 24, x1, 3, \
+    li  x1, 1; \
+    bgeu x1, x0, 1f; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+1:  addi x1, x1, 1; \
+    addi x1, x1, 1; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/blt.S b/apps/riscv-tests/isa/rv64ui/blt.S
new file mode 100644
index 0000000..1c0ca69
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/blt.S
@@ -0,0 +1,73 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# blt.S
+#-----------------------------------------------------------------------------
+#
+# Test blt instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Branch tests
+  #-------------------------------------------------------------
+
+  # Each test checks both forward and backward branches
+
+  TEST_BR2_OP_TAKEN( 2, blt,  0,  1 );
+  TEST_BR2_OP_TAKEN( 3, blt, -1,  1 );
+  TEST_BR2_OP_TAKEN( 4, blt, -2, -1 );
+
+  TEST_BR2_OP_NOTTAKEN( 5, blt,  1,  0 );
+  TEST_BR2_OP_NOTTAKEN( 6, blt,  1, -1 );
+  TEST_BR2_OP_NOTTAKEN( 7, blt, -1, -2 );
+  TEST_BR2_OP_NOTTAKEN( 8, blt,  1, -2 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_BR2_SRC12_BYPASS( 9,  0, 0, blt, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 10, 0, 1, blt, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 11, 0, 2, blt, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 12, 1, 0, blt, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 13, 1, 1, blt, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 14, 2, 0, blt, 0, -1 );
+
+  TEST_BR2_SRC12_BYPASS( 15, 0, 0, blt, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 16, 0, 1, blt, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 17, 0, 2, blt, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 18, 1, 0, blt, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 19, 1, 1, blt, 0, -1 );
+  TEST_BR2_SRC12_BYPASS( 20, 2, 0, blt, 0, -1 );
+
+  #-------------------------------------------------------------
+  # Test delay slot instructions not executed nor bypassed
+  #-------------------------------------------------------------
+
+  TEST_CASE( 21, x1, 3, \
+    li  x1, 1; \
+    blt x0, x1, 1f; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+1:  addi x1, x1, 1; \
+    addi x1, x1, 1; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/bltu.S b/apps/riscv-tests/isa/rv64ui/bltu.S
new file mode 100644
index 0000000..4e880d6
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/bltu.S
@@ -0,0 +1,73 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# bltu.S
+#-----------------------------------------------------------------------------
+#
+# Test bltu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Branch tests
+  #-------------------------------------------------------------
+
+  # Each test checks both forward and backward branches
+
+  TEST_BR2_OP_TAKEN( 2, bltu, 0x00000000, 0x00000001 );
+  TEST_BR2_OP_TAKEN( 3, bltu, 0xfffffffe, 0xffffffff );
+  TEST_BR2_OP_TAKEN( 4, bltu, 0x00000000, 0xffffffff );
+
+  TEST_BR2_OP_NOTTAKEN( 5, bltu, 0x00000001, 0x00000000 );
+  TEST_BR2_OP_NOTTAKEN( 6, bltu, 0xffffffff, 0xfffffffe );
+  TEST_BR2_OP_NOTTAKEN( 7, bltu, 0xffffffff, 0x00000000 );
+  TEST_BR2_OP_NOTTAKEN( 8, bltu, 0x80000000, 0x7fffffff );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_BR2_SRC12_BYPASS( 9,  0, 0, bltu, 0xf0000000, 0xefffffff );
+  TEST_BR2_SRC12_BYPASS( 10, 0, 1, bltu, 0xf0000000, 0xefffffff );
+  TEST_BR2_SRC12_BYPASS( 11, 0, 2, bltu, 0xf0000000, 0xefffffff );
+  TEST_BR2_SRC12_BYPASS( 12, 1, 0, bltu, 0xf0000000, 0xefffffff );
+  TEST_BR2_SRC12_BYPASS( 13, 1, 1, bltu, 0xf0000000, 0xefffffff );
+  TEST_BR2_SRC12_BYPASS( 14, 2, 0, bltu, 0xf0000000, 0xefffffff );
+
+  TEST_BR2_SRC12_BYPASS( 15, 0, 0, bltu, 0xf0000000, 0xefffffff );
+  TEST_BR2_SRC12_BYPASS( 16, 0, 1, bltu, 0xf0000000, 0xefffffff );
+  TEST_BR2_SRC12_BYPASS( 17, 0, 2, bltu, 0xf0000000, 0xefffffff );
+  TEST_BR2_SRC12_BYPASS( 18, 1, 0, bltu, 0xf0000000, 0xefffffff );
+  TEST_BR2_SRC12_BYPASS( 19, 1, 1, bltu, 0xf0000000, 0xefffffff );
+  TEST_BR2_SRC12_BYPASS( 20, 2, 0, bltu, 0xf0000000, 0xefffffff );
+
+  #-------------------------------------------------------------
+  # Test delay slot instructions not executed nor bypassed
+  #-------------------------------------------------------------
+
+  TEST_CASE( 21, x1, 3, \
+    li  x1, 1; \
+    bltu x0, x1, 1f; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+1:  addi x1, x1, 1; \
+    addi x1, x1, 1; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/bne.S b/apps/riscv-tests/isa/rv64ui/bne.S
new file mode 100644
index 0000000..3ca4e6c
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/bne.S
@@ -0,0 +1,73 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# bne.S
+#-----------------------------------------------------------------------------
+#
+# Test bne instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Branch tests
+  #-------------------------------------------------------------
+
+  # Each test checks both forward and backward branches
+
+  TEST_BR2_OP_TAKEN( 2, bne,  0,  1 );
+  TEST_BR2_OP_TAKEN( 3, bne,  1,  0 );
+  TEST_BR2_OP_TAKEN( 4, bne, -1,  1 );
+  TEST_BR2_OP_TAKEN( 5, bne,  1, -1 );
+
+  TEST_BR2_OP_NOTTAKEN( 6, bne,  0,  0 );
+  TEST_BR2_OP_NOTTAKEN( 7, bne,  1,  1 );
+  TEST_BR2_OP_NOTTAKEN( 8, bne, -1, -1 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_BR2_SRC12_BYPASS( 9,  0, 0, bne, 0, 0 );
+  TEST_BR2_SRC12_BYPASS( 10, 0, 1, bne, 0, 0 );
+  TEST_BR2_SRC12_BYPASS( 11, 0, 2, bne, 0, 0 );
+  TEST_BR2_SRC12_BYPASS( 12, 1, 0, bne, 0, 0 );
+  TEST_BR2_SRC12_BYPASS( 13, 1, 1, bne, 0, 0 );
+  TEST_BR2_SRC12_BYPASS( 14, 2, 0, bne, 0, 0 );
+
+  TEST_BR2_SRC12_BYPASS( 15, 0, 0, bne, 0, 0 );
+  TEST_BR2_SRC12_BYPASS( 16, 0, 1, bne, 0, 0 );
+  TEST_BR2_SRC12_BYPASS( 17, 0, 2, bne, 0, 0 );
+  TEST_BR2_SRC12_BYPASS( 18, 1, 0, bne, 0, 0 );
+  TEST_BR2_SRC12_BYPASS( 19, 1, 1, bne, 0, 0 );
+  TEST_BR2_SRC12_BYPASS( 20, 2, 0, bne, 0, 0 );
+
+  #-------------------------------------------------------------
+  # Test delay slot instructions not executed nor bypassed
+  #-------------------------------------------------------------
+
+  TEST_CASE( 21, x1, 3, \
+    li  x1, 1; \
+    bne x1, x0, 1f; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+    addi x1, x1, 1; \
+1:  addi x1, x1, 1; \
+    addi x1, x1, 1; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/fence_i.S b/apps/riscv-tests/isa/rv64ui/fence_i.S
new file mode 100644
index 0000000..e6a6912
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/fence_i.S
@@ -0,0 +1,62 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fence_i.S
+#-----------------------------------------------------------------------------
+#
+# Test self-modifying code and the fence.i instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+li a3, 111
+lh a0, insn
+lh a1, insn+2
+
+# test I$ hit
+.align 6
+sh a0, 2f, t0
+sh a1, 2f+2, t0
+fence.i
+
+la a5, 2f
+jalr t1, a5, 0
+TEST_CASE( 2, a3, 444, nop )
+
+# test prefetcher hit
+li a4, 100
+1: addi a4, a4, -1
+bnez a4, 1b
+
+sh a0, 3f, t0
+sh a1, 3f+2, t0
+fence.i
+
+.align 6
+la a5, 3f
+jalr t1, a5, 0
+TEST_CASE( 3, a3, 777, nop )
+
+TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+insn:
+  addi a3, a3, 333
+
+2: addi a3, a3, 222
+jalr a5, t1, 0
+
+3: addi a3, a3, 555
+jalr a5, t1, 0
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/jal.S b/apps/riscv-tests/isa/rv64ui/jal.S
new file mode 100644
index 0000000..00c65d8
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/jal.S
@@ -0,0 +1,59 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# jal.S
+#-----------------------------------------------------------------------------
+#
+# Test jal instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Test 2: Basic test
+  #-------------------------------------------------------------
+
+test_2:
+  li  TESTNUM, 2
+  li  ra, 0
+
+  jal x4, target_2
+linkaddr_2:
+  nop
+  nop
+
+  j fail
+
+target_2:
+  la  x2, linkaddr_2
+  bne x2, x4, fail
+
+  #-------------------------------------------------------------
+  # Test delay slot instructions not executed nor bypassed
+  #-------------------------------------------------------------
+
+  TEST_CASE( 3, ra, 3, \
+    li  ra, 1; \
+    jal x0, 1f; \
+    addi ra, ra, 1; \
+    addi ra, ra, 1; \
+    addi ra, ra, 1; \
+    addi ra, ra, 1; \
+1:  addi ra, ra, 1; \
+    addi ra, ra, 1; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/jalr.S b/apps/riscv-tests/isa/rv64ui/jalr.S
new file mode 100644
index 0000000..c922b11
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/jalr.S
@@ -0,0 +1,86 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# jalr.S
+#-----------------------------------------------------------------------------
+#
+# Test jalr instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Test 2: Basic test
+  #-------------------------------------------------------------
+
+test_2:
+  li  TESTNUM, 2
+  li  t0, 0
+  la  t1, target_2
+
+  jalr t0, t1, 0
+linkaddr_2:
+  j fail
+
+target_2:
+  la  t1, linkaddr_2
+  bne t0, t1, fail
+
+  #-------------------------------------------------------------
+  # Test 3: Basic test2, rs = rd
+  #-------------------------------------------------------------
+
+test_3:
+  li  TESTNUM, 3
+  la  t0, target_3
+
+  jalr t0, t0, 0
+linkaddr_3:
+  j fail
+
+target_3:
+  la  t1, linkaddr_3
+  bne t0, t1, fail
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_JALR_SRC1_BYPASS( 4, 0, jalr );
+  TEST_JALR_SRC1_BYPASS( 5, 1, jalr );
+  TEST_JALR_SRC1_BYPASS( 6, 2, jalr );
+
+  #-------------------------------------------------------------
+  # Test delay slot instructions not executed nor bypassed
+  #-------------------------------------------------------------
+
+  .option push
+  .align 2
+  .option norvc
+  TEST_CASE( 7, t0, 4, \
+    li  t0, 1; \
+    la  t1, 1f; \
+    jr  t1, -4; \
+    addi t0, t0, 1; \
+    addi t0, t0, 1; \
+    addi t0, t0, 1; \
+    addi t0, t0, 1; \
+1:  addi t0, t0, 1; \
+    addi t0, t0, 1; \
+  )
+  .option pop
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/lb.S b/apps/riscv-tests/isa/rv64ui/lb.S
new file mode 100644
index 0000000..856dfe9
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/lb.S
@@ -0,0 +1,92 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# lb.S
+#-----------------------------------------------------------------------------
+#
+# Test lb instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  TEST_LD_OP( 2, lb, 0xffffffffffffffff, 0,  tdat );
+  TEST_LD_OP( 3, lb, 0x0000000000000000, 1,  tdat );
+  TEST_LD_OP( 4, lb, 0xfffffffffffffff0, 2,  tdat );
+  TEST_LD_OP( 5, lb, 0x000000000000000f, 3, tdat );
+
+  # Test with negative offset
+
+  TEST_LD_OP( 6, lb, 0xffffffffffffffff, -3, tdat4 );
+  TEST_LD_OP( 7, lb, 0x0000000000000000, -2,  tdat4 );
+  TEST_LD_OP( 8, lb, 0xfffffffffffffff0, -1,  tdat4 );
+  TEST_LD_OP( 9, lb, 0x000000000000000f, 0,   tdat4 );
+
+  # Test with a negative base
+
+  TEST_CASE( 10, x5, 0xffffffffffffffff, \
+    la  x1, tdat; \
+    addi x1, x1, -32; \
+    lb x5, 32(x1); \
+  )
+
+  # Test with unaligned base
+
+  TEST_CASE( 11, x5, 0x0000000000000000, \
+    la  x1, tdat; \
+    addi x1, x1, -6; \
+    lb x5, 7(x1); \
+  )
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_LD_DEST_BYPASS( 12, 0, lb, 0xfffffffffffffff0, 1, tdat2 );
+  TEST_LD_DEST_BYPASS( 13, 1, lb, 0x000000000000000f, 1, tdat3 );
+  TEST_LD_DEST_BYPASS( 14, 2, lb, 0x0000000000000000, 1, tdat1 );
+
+  TEST_LD_SRC1_BYPASS( 15, 0, lb, 0xfffffffffffffff0, 1, tdat2 );
+  TEST_LD_SRC1_BYPASS( 16, 1, lb, 0x000000000000000f, 1, tdat3 );
+  TEST_LD_SRC1_BYPASS( 17, 2, lb, 0x0000000000000000, 1, tdat1 );
+
+  #-------------------------------------------------------------
+  # Test write-after-write hazard
+  #-------------------------------------------------------------
+
+  TEST_CASE( 18, x2, 2, \
+    la  x5, tdat; \
+    lb  x2, 0(x5); \
+    li  x2, 2; \
+  )
+
+  TEST_CASE( 19, x2, 2, \
+    la  x5, tdat; \
+    lb  x2, 0(x5); \
+    nop; \
+    li  x2, 2; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+tdat:
+tdat1:  .byte 0xff
+tdat2:  .byte 0x00
+tdat3:  .byte 0xf0
+tdat4:  .byte 0x0f
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/lbu.S b/apps/riscv-tests/isa/rv64ui/lbu.S
new file mode 100644
index 0000000..adc3a05
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/lbu.S
@@ -0,0 +1,92 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# lbu.S
+#-----------------------------------------------------------------------------
+#
+# Test lbu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  TEST_LD_OP( 2, lbu, 0x00000000000000ff, 0,  tdat );
+  TEST_LD_OP( 3, lbu, 0x0000000000000000, 1,  tdat );
+  TEST_LD_OP( 4, lbu, 0x00000000000000f0, 2,  tdat );
+  TEST_LD_OP( 5, lbu, 0x000000000000000f, 3, tdat );
+
+  # Test with negative offset
+
+  TEST_LD_OP( 6, lbu, 0x00000000000000ff, -3, tdat4 );
+  TEST_LD_OP( 7, lbu, 0x0000000000000000, -2,  tdat4 );
+  TEST_LD_OP( 8, lbu, 0x00000000000000f0, -1,  tdat4 );
+  TEST_LD_OP( 9, lbu, 0x000000000000000f, 0,   tdat4 );
+
+  # Test with a negative base
+
+  TEST_CASE( 10, x5, 0x00000000000000ff, \
+    la  x1, tdat; \
+    addi x1, x1, -32; \
+    lbu x5, 32(x1); \
+  )
+
+  # Test with unaligned base
+
+  TEST_CASE( 11, x5, 0x0000000000000000, \
+    la  x1, tdat; \
+    addi x1, x1, -6; \
+    lbu x5, 7(x1); \
+  )
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_LD_DEST_BYPASS( 12, 0, lbu, 0x00000000000000f0, 1, tdat2 );
+  TEST_LD_DEST_BYPASS( 13, 1, lbu, 0x000000000000000f, 1, tdat3 );
+  TEST_LD_DEST_BYPASS( 14, 2, lbu, 0x0000000000000000, 1, tdat1 );
+
+  TEST_LD_SRC1_BYPASS( 15, 0, lbu, 0x00000000000000f0, 1, tdat2 );
+  TEST_LD_SRC1_BYPASS( 16, 1, lbu, 0x000000000000000f, 1, tdat3 );
+  TEST_LD_SRC1_BYPASS( 17, 2, lbu, 0x0000000000000000, 1, tdat1 );
+
+  #-------------------------------------------------------------
+  # Test write-after-write hazard
+  #-------------------------------------------------------------
+
+  TEST_CASE( 18, x2, 2, \
+    la  x5, tdat; \
+    lbu  x2, 0(x5); \
+    li  x2, 2; \
+  )
+
+  TEST_CASE( 19, x2, 2, \
+    la  x5, tdat; \
+    lbu  x2, 0(x5); \
+    nop; \
+    li  x2, 2; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+tdat:
+tdat1:  .byte 0xff
+tdat2:  .byte 0x00
+tdat3:  .byte 0xf0
+tdat4:  .byte 0x0f
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/ld.S b/apps/riscv-tests/isa/rv64ui/ld.S
new file mode 100644
index 0000000..948c34b
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/ld.S
@@ -0,0 +1,92 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# ld.S
+#-----------------------------------------------------------------------------
+#
+# Test ld instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  TEST_LD_OP( 2, ld, 0x00ff00ff00ff00ff, 0,  tdat );
+  TEST_LD_OP( 3, ld, 0xff00ff00ff00ff00, 8,  tdat );
+  TEST_LD_OP( 4, ld, 0x0ff00ff00ff00ff0, 16, tdat );
+  TEST_LD_OP( 5, ld, 0xf00ff00ff00ff00f, 24, tdat );
+
+  # Test with negative offset
+
+  TEST_LD_OP( 6, ld, 0x00ff00ff00ff00ff, -24, tdat4 );
+  TEST_LD_OP( 7, ld, 0xff00ff00ff00ff00, -16, tdat4 );
+  TEST_LD_OP( 8, ld, 0x0ff00ff00ff00ff0, -8,  tdat4 );
+  TEST_LD_OP( 9, ld, 0xf00ff00ff00ff00f, 0,   tdat4 );
+
+  # Test with a negative base
+
+  TEST_CASE( 10, x5, 0x00ff00ff00ff00ff, \
+    la  x1, tdat; \
+    addi x1, x1, -32; \
+    ld x5, 32(x1); \
+  )
+
+  # Test with unaligned base
+
+  TEST_CASE( 11, x5, 0xff00ff00ff00ff00, \
+    la  x1, tdat; \
+    addi x1, x1, -3; \
+    ld x5, 11(x1); \
+  )
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_LD_DEST_BYPASS( 12, 0, ld, 0x0ff00ff00ff00ff0, 8, tdat2 );
+  TEST_LD_DEST_BYPASS( 13, 1, ld, 0xf00ff00ff00ff00f, 8, tdat3 );
+  TEST_LD_DEST_BYPASS( 14, 2, ld, 0xff00ff00ff00ff00, 8, tdat1 );
+
+  TEST_LD_SRC1_BYPASS( 15, 0, ld, 0x0ff00ff00ff00ff0, 8, tdat2 );
+  TEST_LD_SRC1_BYPASS( 16, 1, ld, 0xf00ff00ff00ff00f, 8, tdat3 );
+  TEST_LD_SRC1_BYPASS( 17, 2, ld, 0xff00ff00ff00ff00, 8, tdat1 );
+
+  #-------------------------------------------------------------
+  # Test write-after-write hazard
+  #-------------------------------------------------------------
+
+  TEST_CASE( 18, x2, 2, \
+    la  x5, tdat; \
+    ld  x2, 0(x5); \
+    li  x2, 2; \
+  )
+
+  TEST_CASE( 19, x2, 2, \
+    la  x5, tdat; \
+    ld  x2, 0(x5); \
+    nop; \
+    li  x2, 2; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+tdat:
+tdat1:  .dword 0x00ff00ff00ff00ff
+tdat2:  .dword 0xff00ff00ff00ff00
+tdat3:  .dword 0x0ff00ff00ff00ff0
+tdat4:  .dword 0xf00ff00ff00ff00f
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/lh.S b/apps/riscv-tests/isa/rv64ui/lh.S
new file mode 100644
index 0000000..338ed69
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/lh.S
@@ -0,0 +1,92 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# lh.S
+#-----------------------------------------------------------------------------
+#
+# Test lh instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  TEST_LD_OP( 2, lh, 0x00000000000000ff, 0,  tdat );
+  TEST_LD_OP( 3, lh, 0xffffffffffffff00, 2,  tdat );
+  TEST_LD_OP( 4, lh, 0x0000000000000ff0, 4,  tdat );
+  TEST_LD_OP( 5, lh, 0xfffffffffffff00f, 6, tdat );
+
+  # Test with negative offset
+
+  TEST_LD_OP( 6, lh, 0x00000000000000ff, -6,  tdat4 );
+  TEST_LD_OP( 7, lh, 0xffffffffffffff00, -4,  tdat4 );
+  TEST_LD_OP( 8, lh, 0x0000000000000ff0, -2,  tdat4 );
+  TEST_LD_OP( 9, lh, 0xfffffffffffff00f,  0, tdat4 );
+
+  # Test with a negative base
+
+  TEST_CASE( 10, x5, 0x00000000000000ff, \
+    la  x1, tdat; \
+    addi x1, x1, -32; \
+    lh x5, 32(x1); \
+  )
+
+  # Test with unaligned base
+
+  TEST_CASE( 11, x5, 0xffffffffffffff00, \
+    la  x1, tdat; \
+    addi x1, x1, -5; \
+    lh x5, 7(x1); \
+  )
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_LD_DEST_BYPASS( 12, 0, lh, 0x0000000000000ff0, 2, tdat2 );
+  TEST_LD_DEST_BYPASS( 13, 1, lh, 0xfffffffffffff00f, 2, tdat3 );
+  TEST_LD_DEST_BYPASS( 14, 2, lh, 0xffffffffffffff00, 2, tdat1 );
+
+  TEST_LD_SRC1_BYPASS( 15, 0, lh, 0x0000000000000ff0, 2, tdat2 );
+  TEST_LD_SRC1_BYPASS( 16, 1, lh, 0xfffffffffffff00f, 2, tdat3 );
+  TEST_LD_SRC1_BYPASS( 17, 2, lh, 0xffffffffffffff00, 2, tdat1 );
+
+  #-------------------------------------------------------------
+  # Test write-after-write hazard
+  #-------------------------------------------------------------
+
+  TEST_CASE( 18, x2, 2, \
+    la  x5, tdat; \
+    lh  x2, 0(x5); \
+    li  x2, 2; \
+  )
+
+  TEST_CASE( 19, x2, 2, \
+    la  x5, tdat; \
+    lh  x2, 0(x5); \
+    nop; \
+    li  x2, 2; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+tdat:
+tdat1:  .half 0x00ff
+tdat2:  .half 0xff00
+tdat3:  .half 0x0ff0
+tdat4:  .half 0xf00f
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/lhu.S b/apps/riscv-tests/isa/rv64ui/lhu.S
new file mode 100644
index 0000000..a4cc49b
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/lhu.S
@@ -0,0 +1,92 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# lhu.S
+#-----------------------------------------------------------------------------
+#
+# Test lhu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  TEST_LD_OP( 2, lhu, 0x00000000000000ff, 0,  tdat );
+  TEST_LD_OP( 3, lhu, 0x000000000000ff00, 2,  tdat );
+  TEST_LD_OP( 4, lhu, 0x0000000000000ff0, 4,  tdat );
+  TEST_LD_OP( 5, lhu, 0x000000000000f00f, 6, tdat );
+
+  # Test with negative offset
+
+  TEST_LD_OP( 6, lhu, 0x00000000000000ff, -6,  tdat4 );
+  TEST_LD_OP( 7, lhu, 0x000000000000ff00, -4,  tdat4 );
+  TEST_LD_OP( 8, lhu, 0x0000000000000ff0, -2,  tdat4 );
+  TEST_LD_OP( 9, lhu, 0x000000000000f00f,  0, tdat4 );
+
+  # Test with a negative base
+
+  TEST_CASE( 10, x5, 0x00000000000000ff, \
+    la  x1, tdat; \
+    addi x1, x1, -32; \
+    lhu x5, 32(x1); \
+  )
+
+  # Test with unaligned base
+
+  TEST_CASE( 11, x5, 0x000000000000ff00, \
+    la  x1, tdat; \
+    addi x1, x1, -5; \
+    lhu x5, 7(x1); \
+  )
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_LD_DEST_BYPASS( 12, 0, lhu, 0x0000000000000ff0, 2, tdat2 );
+  TEST_LD_DEST_BYPASS( 13, 1, lhu, 0x000000000000f00f, 2, tdat3 );
+  TEST_LD_DEST_BYPASS( 14, 2, lhu, 0x000000000000ff00, 2, tdat1 );
+
+  TEST_LD_SRC1_BYPASS( 15, 0, lhu, 0x0000000000000ff0, 2, tdat2 );
+  TEST_LD_SRC1_BYPASS( 16, 1, lhu, 0x000000000000f00f, 2, tdat3 );
+  TEST_LD_SRC1_BYPASS( 17, 2, lhu, 0x000000000000ff00, 2, tdat1 );
+
+  #-------------------------------------------------------------
+  # Test write-after-write hazard
+  #-------------------------------------------------------------
+
+  TEST_CASE( 18, x2, 2, \
+    la  x5, tdat; \
+    lhu  x2, 0(x5); \
+    li  x2, 2; \
+  )
+
+  TEST_CASE( 19, x2, 2, \
+    la  x5, tdat; \
+    lhu  x2, 0(x5); \
+    nop; \
+    li  x2, 2; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+tdat:
+tdat1:  .half 0x00ff
+tdat2:  .half 0xff00
+tdat3:  .half 0x0ff0
+tdat4:  .half 0xf00f
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/lui.S b/apps/riscv-tests/isa/rv64ui/lui.S
new file mode 100644
index 0000000..8a4e70c
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/lui.S
@@ -0,0 +1,36 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# lui.S
+#-----------------------------------------------------------------------------
+#
+# Test lui instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  TEST_CASE( 2, x1, 0x0000000000000000, lui x1, 0x00000 );
+  TEST_CASE( 3, x1, 0xfffffffffffff800, lui x1, 0xfffff;sra x1,x1,1);
+  TEST_CASE( 4, x1, 0x00000000000007ff, lui x1, 0x7ffff;sra x1,x1,20);
+  TEST_CASE( 5, x1, 0xfffffffffffff800, lui x1, 0x80000;sra x1,x1,20);
+
+  TEST_CASE( 6, x0, 0, lui x0, 0x80000 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/lw.S b/apps/riscv-tests/isa/rv64ui/lw.S
new file mode 100644
index 0000000..40a73f1
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/lw.S
@@ -0,0 +1,92 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# lw.S
+#-----------------------------------------------------------------------------
+#
+# Test lw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  TEST_LD_OP( 2, lw, 0x0000000000ff00ff, 0,  tdat );
+  TEST_LD_OP( 3, lw, 0xffffffffff00ff00, 4,  tdat );
+  TEST_LD_OP( 4, lw, 0x000000000ff00ff0, 8,  tdat );
+  TEST_LD_OP( 5, lw, 0xfffffffff00ff00f, 12, tdat );
+
+  # Test with negative offset
+
+  TEST_LD_OP( 6, lw, 0x0000000000ff00ff, -12, tdat4 );
+  TEST_LD_OP( 7, lw, 0xffffffffff00ff00, -8,  tdat4 );
+  TEST_LD_OP( 8, lw, 0x000000000ff00ff0, -4,  tdat4 );
+  TEST_LD_OP( 9, lw, 0xfffffffff00ff00f, 0,   tdat4 );
+
+  # Test with a negative base
+
+  TEST_CASE( 10, x5, 0x0000000000ff00ff, \
+    la  x1, tdat; \
+    addi x1, x1, -32; \
+    lw x5, 32(x1); \
+  )
+
+  # Test with unaligned base
+
+  TEST_CASE( 11, x5, 0xffffffffff00ff00, \
+    la  x1, tdat; \
+    addi x1, x1, -3; \
+    lw x5, 7(x1); \
+  )
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_LD_DEST_BYPASS( 12, 0, lw, 0x000000000ff00ff0, 4, tdat2 );
+  TEST_LD_DEST_BYPASS( 13, 1, lw, 0xfffffffff00ff00f, 4, tdat3 );
+  TEST_LD_DEST_BYPASS( 14, 2, lw, 0xffffffffff00ff00, 4, tdat1 );
+
+  TEST_LD_SRC1_BYPASS( 15, 0, lw, 0x000000000ff00ff0, 4, tdat2 );
+  TEST_LD_SRC1_BYPASS( 16, 1, lw, 0xfffffffff00ff00f, 4, tdat3 );
+  TEST_LD_SRC1_BYPASS( 17, 2, lw, 0xffffffffff00ff00, 4, tdat1 );
+
+  #-------------------------------------------------------------
+  # Test write-after-write hazard
+  #-------------------------------------------------------------
+
+  TEST_CASE( 18, x2, 2, \
+    la  x5, tdat; \
+    lw  x2, 0(x5); \
+    li  x2, 2; \
+  )
+
+  TEST_CASE( 19, x2, 2, \
+    la  x5, tdat; \
+    lw  x2, 0(x5); \
+    nop; \
+    li  x2, 2; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+tdat:
+tdat1:  .word 0x00ff00ff
+tdat2:  .word 0xff00ff00
+tdat3:  .word 0x0ff00ff0
+tdat4:  .word 0xf00ff00f
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/lwu.S b/apps/riscv-tests/isa/rv64ui/lwu.S
new file mode 100644
index 0000000..9f7cf67
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/lwu.S
@@ -0,0 +1,92 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# lwu.S
+#-----------------------------------------------------------------------------
+#
+# Test lwu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  TEST_LD_OP( 2, lwu, 0x0000000000ff00ff, 0,  tdat );
+  TEST_LD_OP( 3, lwu, 0x00000000ff00ff00, 4,  tdat );
+  TEST_LD_OP( 4, lwu, 0x000000000ff00ff0, 8,  tdat );
+  TEST_LD_OP( 5, lwu, 0x00000000f00ff00f, 12, tdat );
+
+  # Test with negative offset
+
+  TEST_LD_OP( 6, lwu, 0x0000000000ff00ff, -12, tdat4 );
+  TEST_LD_OP( 7, lwu, 0x00000000ff00ff00, -8,  tdat4 );
+  TEST_LD_OP( 8, lwu, 0x000000000ff00ff0, -4,  tdat4 );
+  TEST_LD_OP( 9, lwu, 0x00000000f00ff00f, 0,   tdat4 );
+
+  # Test with a negative base
+
+  TEST_CASE( 10, x5, 0x0000000000ff00ff, \
+    la  x1, tdat; \
+    addi x1, x1, -32; \
+    lwu x5, 32(x1); \
+  )
+
+  # Test with unaligned base
+
+  TEST_CASE( 11, x5, 0x00000000ff00ff00, \
+    la  x1, tdat; \
+    addi x1, x1, -3; \
+    lwu x5, 7(x1); \
+  )
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_LD_DEST_BYPASS( 12, 0, lwu, 0x000000000ff00ff0, 4, tdat2 );
+  TEST_LD_DEST_BYPASS( 13, 1, lwu, 0x00000000f00ff00f, 4, tdat3 );
+  TEST_LD_DEST_BYPASS( 14, 2, lwu, 0x00000000ff00ff00, 4, tdat1 );
+
+  TEST_LD_SRC1_BYPASS( 15, 0, lwu, 0x000000000ff00ff0, 4, tdat2 );
+  TEST_LD_SRC1_BYPASS( 16, 1, lwu, 0x00000000f00ff00f, 4, tdat3 );
+  TEST_LD_SRC1_BYPASS( 17, 2, lwu, 0x00000000ff00ff00, 4, tdat1 );
+
+  #-------------------------------------------------------------
+  # Test write-after-write hazard
+  #-------------------------------------------------------------
+
+  TEST_CASE( 18, x2, 2, \
+    la  x5, tdat; \
+    lwu x2, 0(x5); \
+    li  x2, 2; \
+  )
+
+  TEST_CASE( 19, x2, 2, \
+    la  x5, tdat; \
+    lwu x2, 0(x5); \
+    nop; \
+    li  x2, 2; \
+  )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+tdat:
+tdat1:  .word 0x00ff00ff
+tdat2:  .word 0xff00ff00
+tdat3:  .word 0x0ff00ff0
+tdat4:  .word 0xf00ff00f
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/or.S b/apps/riscv-tests/isa/rv64ui/or.S
new file mode 100644
index 0000000..6d84f53
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/or.S
@@ -0,0 +1,69 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# or.S
+#-----------------------------------------------------------------------------
+#
+# Test or instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Logical tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_OP( 3, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_OP( 4, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
+  TEST_RR_OP( 5, or, 0xf0fff0ff, 0xf00ff00f, 0xf0f0f0f0 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 6, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC2_EQ_DEST( 7, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC12_EQ_DEST( 8, or, 0xff00ff00, 0xff00ff00 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 9,  0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_DEST_BYPASS( 10, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_DEST_BYPASS( 11, 2, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
+
+  TEST_RR_SRC12_BYPASS( 12, 0, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC12_BYPASS( 13, 0, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_SRC12_BYPASS( 14, 0, 2, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
+  TEST_RR_SRC12_BYPASS( 15, 1, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC12_BYPASS( 16, 1, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_SRC12_BYPASS( 17, 2, 0, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
+
+  TEST_RR_SRC21_BYPASS( 18, 0, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC21_BYPASS( 19, 0, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_SRC21_BYPASS( 20, 0, 2, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
+  TEST_RR_SRC21_BYPASS( 21, 1, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC21_BYPASS( 22, 1, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_SRC21_BYPASS( 23, 2, 0, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
+
+  TEST_RR_ZEROSRC1( 24, or, 0xff00ff00, 0xff00ff00 );
+  TEST_RR_ZEROSRC2( 25, or, 0x00ff00ff, 0x00ff00ff );
+  TEST_RR_ZEROSRC12( 26, or, 0 );
+  TEST_RR_ZERODEST( 27, or, 0x11111111, 0x22222222 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/ori.S b/apps/riscv-tests/isa/rv64ui/ori.S
new file mode 100644
index 0000000..437c00a
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/ori.S
@@ -0,0 +1,55 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# ori.S
+#-----------------------------------------------------------------------------
+#
+# Test ori instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Logical tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_OP( 2, ori, 0xffffffffffffff0f, 0xffffffffff00ff00, 0xf0f );
+  TEST_IMM_OP( 3, ori, 0x000000000ff00ff0, 0x000000000ff00ff0, 0x0f0 );
+  TEST_IMM_OP( 4, ori, 0x0000000000ff07ff, 0x0000000000ff00ff, 0x70f );
+  TEST_IMM_OP( 5, ori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_SRC1_EQ_DEST( 6, ori, 0xff00fff0, 0xff00ff00, 0x0f0 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_DEST_BYPASS( 7,  0, ori, 0x000000000ff00ff0, 0x000000000ff00ff0, 0x0f0 );
+  TEST_IMM_DEST_BYPASS( 8,  1, ori, 0x0000000000ff07ff, 0x0000000000ff00ff, 0x70f );
+  TEST_IMM_DEST_BYPASS( 9,  2, ori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 );
+
+  TEST_IMM_SRC1_BYPASS( 10, 0, ori, 0x000000000ff00ff0, 0x000000000ff00ff0, 0x0f0 );
+  TEST_IMM_SRC1_BYPASS( 11, 1, ori, 0xffffffffffffffff, 0x0000000000ff00ff, 0xf0f );
+  TEST_IMM_SRC1_BYPASS( 12, 2, ori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 );
+
+  TEST_IMM_ZEROSRC1( 13, ori, 0x0f0, 0x0f0 );
+  TEST_IMM_ZERODEST( 14, ori, 0x00ff00ff, 0x70f );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/sb.S b/apps/riscv-tests/isa/rv64ui/sb.S
new file mode 100644
index 0000000..19e32d6
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/sb.S
@@ -0,0 +1,96 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sb.S
+#-----------------------------------------------------------------------------
+#
+# Test sb instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  TEST_ST_OP( 2, lb, sb, 0xffffffffffffffaa, 0, tdat );
+  TEST_ST_OP( 3, lb, sb, 0x0000000000000000, 1, tdat );
+  TEST_ST_OP( 4, lh, sb, 0xffffffffffffefa0, 2, tdat );
+  TEST_ST_OP( 5, lb, sb, 0x000000000000000a, 3, tdat );
+
+  # Test with negative offset
+
+  TEST_ST_OP( 6, lb, sb, 0xffffffffffffffaa, -3, tdat8 );
+  TEST_ST_OP( 7, lb, sb, 0x0000000000000000, -2, tdat8 );
+  TEST_ST_OP( 8, lb, sb, 0xffffffffffffffa0, -1, tdat8 );
+  TEST_ST_OP( 9, lb, sb, 0x000000000000000a, 0,  tdat8 );
+
+  # Test with a negative base
+
+  TEST_CASE( 10, x5, 0x78, \
+    la  x1, tdat9; \
+    li  x2, 0x12345678; \
+    addi x4, x1, -32; \
+    sb x2, 32(x4); \
+    lb x5, 0(x1); \
+  )
+
+  # Test with unaligned base
+
+  TEST_CASE( 11, x5, 0xffffffffffffff98, \
+    la  x1, tdat9; \
+    li  x2, 0x00003098; \
+    addi x1, x1, -6; \
+    sb x2, 7(x1); \
+    la  x4, tdat10; \
+    lb x5, 0(x4); \
+  )
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_ST_SRC12_BYPASS( 12, 0, 0, lb, sb, 0xffffffffffffffdd, 0, tdat );
+  TEST_ST_SRC12_BYPASS( 13, 0, 1, lb, sb, 0xffffffffffffffcd, 1, tdat );
+  TEST_ST_SRC12_BYPASS( 14, 0, 2, lb, sb, 0xffffffffffffffcc, 2, tdat );
+  TEST_ST_SRC12_BYPASS( 15, 1, 0, lb, sb, 0xffffffffffffffbc, 3, tdat );
+  TEST_ST_SRC12_BYPASS( 16, 1, 1, lb, sb, 0xffffffffffffffbb, 4, tdat );
+  TEST_ST_SRC12_BYPASS( 17, 2, 0, lb, sb, 0xffffffffffffffab, 5, tdat );
+
+  TEST_ST_SRC21_BYPASS( 18, 0, 0, lb, sb, 0x33, 0, tdat );
+  TEST_ST_SRC21_BYPASS( 19, 0, 1, lb, sb, 0x23, 1, tdat );
+  TEST_ST_SRC21_BYPASS( 20, 0, 2, lb, sb, 0x22, 2, tdat );
+  TEST_ST_SRC21_BYPASS( 21, 1, 0, lb, sb, 0x12, 3, tdat );
+  TEST_ST_SRC21_BYPASS( 22, 1, 1, lb, sb, 0x11, 4, tdat );
+  TEST_ST_SRC21_BYPASS( 23, 2, 0, lb, sb, 0x01, 5, tdat );
+
+  li a0, 0xef
+  la a1, tdat
+  sb a0, 3(a1)
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+tdat:
+tdat1:  .byte 0xef
+tdat2:  .byte 0xef
+tdat3:  .byte 0xef
+tdat4:  .byte 0xef
+tdat5:  .byte 0xef
+tdat6:  .byte 0xef
+tdat7:  .byte 0xef
+tdat8:  .byte 0xef
+tdat9:  .byte 0xef
+tdat10: .byte 0xef
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/sd.S b/apps/riscv-tests/isa/rv64ui/sd.S
new file mode 100644
index 0000000..b6fd66d
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/sd.S
@@ -0,0 +1,92 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sd.S
+#-----------------------------------------------------------------------------
+#
+# Test sd instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  TEST_ST_OP( 2, ld, sd, 0x00aa00aa00aa00aa, 0,  tdat );
+  TEST_ST_OP( 3, ld, sd, 0xaa00aa00aa00aa00, 8,  tdat );
+  TEST_ST_OP( 4, ld, sd, 0x0aa00aa00aa00aa0, 16,  tdat );
+  TEST_ST_OP( 5, ld, sd, 0xa00aa00aa00aa00a, 24, tdat );
+
+  # Test with negative offset
+
+  TEST_ST_OP( 6, ld, sd, 0x00aa00aa00aa00aa, -24, tdat8 );
+  TEST_ST_OP( 7, ld, sd, 0xaa00aa00aa00aa00, -16, tdat8 );
+  TEST_ST_OP( 8, ld, sd, 0x0aa00aa00aa00aa0, -8,  tdat8 );
+  TEST_ST_OP( 9, ld, sd, 0xa00aa00aa00aa00a, 0,   tdat8 );
+
+  # Test with a negative base
+
+  TEST_CASE( 10, x5, 0x1234567812345678, \
+    la  x1, tdat9; \
+    li  x2, 0x1234567812345678; \
+    addi x4, x1, -32; \
+    sd x2, 32(x4); \
+    ld x5, 0(x1); \
+  )
+
+  # Test with unaligned base
+
+  TEST_CASE( 11, x5, 0x5821309858213098, \
+    la  x1, tdat9; \
+    li  x2, 0x5821309858213098; \
+    addi x1, x1, -3; \
+    sd x2, 11(x1); \
+    la  x4, tdat10; \
+    ld x5, 0(x4); \
+  )
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_ST_SRC12_BYPASS( 12, 0, 0, ld, sd, 0xabbccdd, 0,  tdat );
+  TEST_ST_SRC12_BYPASS( 13, 0, 1, ld, sd, 0xaabbccd, 8,  tdat );
+  TEST_ST_SRC12_BYPASS( 14, 0, 2, ld, sd, 0xdaabbcc, 16, tdat );
+  TEST_ST_SRC12_BYPASS( 15, 1, 0, ld, sd, 0xddaabbc, 24, tdat );
+  TEST_ST_SRC12_BYPASS( 16, 1, 1, ld, sd, 0xcddaabb, 32, tdat );
+  TEST_ST_SRC12_BYPASS( 17, 2, 0, ld, sd, 0xccddaab, 40, tdat );
+
+  TEST_ST_SRC21_BYPASS( 18, 0, 0, ld, sd, 0x00112233, 0,  tdat );
+  TEST_ST_SRC21_BYPASS( 19, 0, 1, ld, sd, 0x30011223, 8,  tdat );
+  TEST_ST_SRC21_BYPASS( 20, 0, 2, ld, sd, 0x33001122, 16, tdat );
+  TEST_ST_SRC21_BYPASS( 21, 1, 0, ld, sd, 0x23300112, 24, tdat );
+  TEST_ST_SRC21_BYPASS( 22, 1, 1, ld, sd, 0x22330011, 32, tdat );
+  TEST_ST_SRC21_BYPASS( 23, 2, 0, ld, sd, 0x12233001, 40, tdat );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+tdat:
+tdat1:  .dword 0xdeadbeefdeadbeef
+tdat2:  .dword 0xdeadbeefdeadbeef
+tdat3:  .dword 0xdeadbeefdeadbeef
+tdat4:  .dword 0xdeadbeefdeadbeef
+tdat5:  .dword 0xdeadbeefdeadbeef
+tdat6:  .dword 0xdeadbeefdeadbeef
+tdat7:  .dword 0xdeadbeefdeadbeef
+tdat8:  .dword 0xdeadbeefdeadbeef
+tdat9:  .dword 0xdeadbeefdeadbeef
+tdat10: .dword 0xdeadbeefdeadbeef
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/sh.S b/apps/riscv-tests/isa/rv64ui/sh.S
new file mode 100644
index 0000000..ea9eb23
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/sh.S
@@ -0,0 +1,96 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sh.S
+#-----------------------------------------------------------------------------
+#
+# Test sh instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  TEST_ST_OP( 2, lh, sh, 0x00000000000000aa, 0, tdat );
+  TEST_ST_OP( 3, lh, sh, 0xffffffffffffaa00, 2, tdat );
+  TEST_ST_OP( 4, lw, sh, 0xffffffffbeef0aa0, 4, tdat );
+  TEST_ST_OP( 5, lh, sh, 0xffffffffffffa00a, 6, tdat );
+
+  # Test with negative offset
+
+  TEST_ST_OP( 6, lh, sh, 0x00000000000000aa, -6, tdat8 );
+  TEST_ST_OP( 7, lh, sh, 0xffffffffffffaa00, -4, tdat8 );
+  TEST_ST_OP( 8, lh, sh, 0x0000000000000aa0, -2, tdat8 );
+  TEST_ST_OP( 9, lh, sh, 0xffffffffffffa00a, 0,  tdat8 );
+
+  # Test with a negative base
+
+  TEST_CASE( 10, x5, 0x5678, \
+    la  x1, tdat9; \
+    li  x2, 0x12345678; \
+    addi x4, x1, -32; \
+    sh x2, 32(x4); \
+    lh x5, 0(x1); \
+  )
+
+  # Test with unaligned base
+
+  TEST_CASE( 11, x5, 0x3098, \
+    la  x1, tdat9; \
+    li  x2, 0x00003098; \
+    addi x1, x1, -5; \
+    sh x2, 7(x1); \
+    la  x4, tdat10; \
+    lh x5, 0(x4); \
+  )
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_ST_SRC12_BYPASS( 12, 0, 0, lh, sh, 0xffffffffffffccdd, 0,  tdat );
+  TEST_ST_SRC12_BYPASS( 13, 0, 1, lh, sh, 0xffffffffffffbccd, 2,  tdat );
+  TEST_ST_SRC12_BYPASS( 14, 0, 2, lh, sh, 0xffffffffffffbbcc, 4,  tdat );
+  TEST_ST_SRC12_BYPASS( 15, 1, 0, lh, sh, 0xffffffffffffabbc, 6, tdat );
+  TEST_ST_SRC12_BYPASS( 16, 1, 1, lh, sh, 0xffffffffffffaabb, 8, tdat );
+  TEST_ST_SRC12_BYPASS( 17, 2, 0, lh, sh, 0xffffffffffffdaab, 10, tdat );
+
+  TEST_ST_SRC21_BYPASS( 18, 0, 0, lh, sh, 0x2233, 0,  tdat );
+  TEST_ST_SRC21_BYPASS( 19, 0, 1, lh, sh, 0x1223, 2,  tdat );
+  TEST_ST_SRC21_BYPASS( 20, 0, 2, lh, sh, 0x1122, 4,  tdat );
+  TEST_ST_SRC21_BYPASS( 21, 1, 0, lh, sh, 0x0112, 6, tdat );
+  TEST_ST_SRC21_BYPASS( 22, 1, 1, lh, sh, 0x0011, 8, tdat );
+  TEST_ST_SRC21_BYPASS( 23, 2, 0, lh, sh, 0x3001, 10, tdat );
+
+  li a0, 0xbeef
+  la a1, tdat
+  sh a0, 6(a1)
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+tdat:
+tdat1:  .half 0xbeef
+tdat2:  .half 0xbeef
+tdat3:  .half 0xbeef
+tdat4:  .half 0xbeef
+tdat5:  .half 0xbeef
+tdat6:  .half 0xbeef
+tdat7:  .half 0xbeef
+tdat8:  .half 0xbeef
+tdat9:  .half 0xbeef
+tdat10: .half 0xbeef
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/simple.S b/apps/riscv-tests/isa/rv64ui/simple.S
new file mode 100644
index 0000000..6c45fbd
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/simple.S
@@ -0,0 +1,27 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# simple.S
+#-----------------------------------------------------------------------------
+#
+# This is the most basic self checking test. If your simulator does not
+# pass thiss then there is little chance that it will pass any of the
+# more complicated self checking tests.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+RVTEST_PASS
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/sll.S b/apps/riscv-tests/isa/rv64ui/sll.S
new file mode 100644
index 0000000..8682743
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/sll.S
@@ -0,0 +1,96 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sll.S
+#-----------------------------------------------------------------------------
+#
+# Test sll instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  sll, 0x0000000000000001, 0x0000000000000001, 0  );
+  TEST_RR_OP( 3,  sll, 0x0000000000000002, 0x0000000000000001, 1  );
+  TEST_RR_OP( 4,  sll, 0x0000000000000080, 0x0000000000000001, 7  );
+  TEST_RR_OP( 5,  sll, 0x0000000000004000, 0x0000000000000001, 14 );
+  TEST_RR_OP( 6,  sll, 0x0000000080000000, 0x0000000000000001, 31 );
+
+  TEST_RR_OP( 7,  sll, 0xffffffffffffffff, 0xffffffffffffffff, 0  );
+  TEST_RR_OP( 8,  sll, 0xfffffffffffffffe, 0xffffffffffffffff, 1  );
+  TEST_RR_OP( 9,  sll, 0xffffffffffffff80, 0xffffffffffffffff, 7  );
+  TEST_RR_OP( 10, sll, 0xffffffffffffc000, 0xffffffffffffffff, 14 );
+  TEST_RR_OP( 11, sll, 0xffffffff80000000, 0xffffffffffffffff, 31 );
+
+  TEST_RR_OP( 12, sll, 0x0000000021212121, 0x0000000021212121, 0  );
+  TEST_RR_OP( 13, sll, 0x0000000042424242, 0x0000000021212121, 1  );
+  TEST_RR_OP( 14, sll, 0x0000001090909080, 0x0000000021212121, 7  );
+  TEST_RR_OP( 15, sll, 0x0000084848484000, 0x0000000021212121, 14 );
+  TEST_RR_OP( 16, sll, 0x1090909080000000, 0x0000000021212121, 31 );
+
+  # Verify that shifts only use bottom six(rv64) or five(rv32) bits
+
+  TEST_RR_OP( 17, sll, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffc0 );
+  TEST_RR_OP( 18, sll, 0x0000000042424242, 0x0000000021212121, 0xffffffffffffffc1 );
+  TEST_RR_OP( 19, sll, 0x0000001090909080, 0x0000000021212121, 0xffffffffffffffc7 );
+  TEST_RR_OP( 20, sll, 0x0000084848484000, 0x0000000021212121, 0xffffffffffffffce );
+
+#if __riscv_xlen == 64
+  TEST_RR_OP( 21, sll, 0x8000000000000000, 0x0000000021212121, 0xffffffffffffffff );
+  TEST_RR_OP( 50, sll, 0x8000000000000000, 0x0000000000000001, 63 );
+  TEST_RR_OP( 51, sll, 0xffffff8000000000, 0xffffffffffffffff, 39 );
+  TEST_RR_OP( 52, sll, 0x0909080000000000, 0x0000000021212121, 43 );
+#endif
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 22, sll, 0x00000080, 0x00000001, 7  );
+  TEST_RR_SRC2_EQ_DEST( 23, sll, 0x00004000, 0x00000001, 14 );
+  TEST_RR_SRC12_EQ_DEST( 24, sll, 24, 3 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 25, 0, sll, 0x0000000000000080, 0x0000000000000001, 7  );
+  TEST_RR_DEST_BYPASS( 26, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 );
+  TEST_RR_DEST_BYPASS( 27, 2, sll, 0x0000000080000000, 0x0000000000000001, 31 );
+
+  TEST_RR_SRC12_BYPASS( 28, 0, 0, sll, 0x0000000000000080, 0x0000000000000001, 7  );
+  TEST_RR_SRC12_BYPASS( 29, 0, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 );
+  TEST_RR_SRC12_BYPASS( 30, 0, 2, sll, 0x0000000080000000, 0x0000000000000001, 31 );
+  TEST_RR_SRC12_BYPASS( 31, 1, 0, sll, 0x0000000000000080, 0x0000000000000001, 7  );
+  TEST_RR_SRC12_BYPASS( 32, 1, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 );
+  TEST_RR_SRC12_BYPASS( 33, 2, 0, sll, 0x0000000080000000, 0x0000000000000001, 31 );
+
+  TEST_RR_SRC21_BYPASS( 34, 0, 0, sll, 0x0000000000000080, 0x0000000000000001, 7  );
+  TEST_RR_SRC21_BYPASS( 35, 0, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 );
+  TEST_RR_SRC21_BYPASS( 36, 0, 2, sll, 0x0000000080000000, 0x0000000000000001, 31 );
+  TEST_RR_SRC21_BYPASS( 37, 1, 0, sll, 0x0000000000000080, 0x0000000000000001, 7  );
+  TEST_RR_SRC21_BYPASS( 38, 1, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 );
+  TEST_RR_SRC21_BYPASS( 39, 2, 0, sll, 0x0000000080000000, 0x0000000000000001, 31 );
+
+  TEST_RR_ZEROSRC1( 40, sll, 0, 15 );
+  TEST_RR_ZEROSRC2( 41, sll, 32, 32 );
+  TEST_RR_ZEROSRC12( 42, sll, 0 );
+  TEST_RR_ZERODEST( 43, sll, 1024, 2048 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/slli.S b/apps/riscv-tests/isa/rv64ui/slli.S
new file mode 100644
index 0000000..b5341ad
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/slli.S
@@ -0,0 +1,74 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# slli.S
+#-----------------------------------------------------------------------------
+#
+# Test slli instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_OP( 2,  slli, 0x0000000000000001, 0x0000000000000001, 0  );
+  TEST_IMM_OP( 3,  slli, 0x0000000000000002, 0x0000000000000001, 1  );
+  TEST_IMM_OP( 4,  slli, 0x0000000000000080, 0x0000000000000001, 7  );
+  TEST_IMM_OP( 5,  slli, 0x0000000000004000, 0x0000000000000001, 14 );
+  TEST_IMM_OP( 6,  slli, 0x0000000080000000, 0x0000000000000001, 31 );
+
+  TEST_IMM_OP( 7,  slli, 0xffffffffffffffff, 0xffffffffffffffff, 0  );
+  TEST_IMM_OP( 8,  slli, 0xfffffffffffffffe, 0xffffffffffffffff, 1  );
+  TEST_IMM_OP( 9,  slli, 0xffffffffffffff80, 0xffffffffffffffff, 7  );
+  TEST_IMM_OP( 10, slli, 0xffffffffffffc000, 0xffffffffffffffff, 14 );
+  TEST_IMM_OP( 11, slli, 0xffffffff80000000, 0xffffffffffffffff, 31 );
+
+  TEST_IMM_OP( 12, slli, 0x0000000021212121, 0x0000000021212121, 0  );
+  TEST_IMM_OP( 13, slli, 0x0000000042424242, 0x0000000021212121, 1  );
+  TEST_IMM_OP( 14, slli, 0x0000001090909080, 0x0000000021212121, 7  );
+  TEST_IMM_OP( 15, slli, 0x0000084848484000, 0x0000000021212121, 14 );
+  TEST_IMM_OP( 16, slli, 0x1090909080000000, 0x0000000021212121, 31 );
+
+#if __riscv_xlen == 64
+  TEST_IMM_OP( 50, slli, 0x8000000000000000, 0x0000000000000001, 63 );
+  TEST_IMM_OP( 51, slli, 0xffffff8000000000, 0xffffffffffffffff, 39 );
+  TEST_IMM_OP( 52, slli, 0x0909080000000000, 0x0000000021212121, 43 );
+#endif
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_SRC1_EQ_DEST( 17, slli, 0x00000080, 0x00000001, 7 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_DEST_BYPASS( 18, 0, slli, 0x0000000000000080, 0x0000000000000001, 7  );
+  TEST_IMM_DEST_BYPASS( 19, 1, slli, 0x0000000000004000, 0x0000000000000001, 14 );
+  TEST_IMM_DEST_BYPASS( 20, 2, slli, 0x0000000080000000, 0x0000000000000001, 31 );
+
+  TEST_IMM_SRC1_BYPASS( 21, 0, slli, 0x0000000000000080, 0x0000000000000001, 7  );
+  TEST_IMM_SRC1_BYPASS( 22, 1, slli, 0x0000000000004000, 0x0000000000000001, 14 );
+  TEST_IMM_SRC1_BYPASS( 23, 2, slli, 0x0000000080000000, 0x0000000000000001, 31 );
+
+  TEST_IMM_ZEROSRC1( 24, slli, 0, 31 );
+  TEST_IMM_ZERODEST( 25, slli, 33, 20 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/slliw.S b/apps/riscv-tests/isa/rv64ui/slliw.S
new file mode 100644
index 0000000..0ed888b
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/slliw.S
@@ -0,0 +1,75 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# slliw.S
+#-----------------------------------------------------------------------------
+#
+# Test slliw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_OP( 2,  slliw, 0x0000000000000001, 0x0000000000000001, 0  );
+  TEST_IMM_OP( 3,  slliw, 0x0000000000000002, 0x0000000000000001, 1  );
+  TEST_IMM_OP( 4,  slliw, 0x0000000000000080, 0x0000000000000001, 7  );
+  TEST_IMM_OP( 5,  slliw, 0x0000000000004000, 0x0000000000000001, 14 );
+  TEST_IMM_OP( 6,  slliw, 0xffffffff80000000, 0x0000000000000001, 31 );
+
+  TEST_IMM_OP( 7,  slliw, 0xffffffffffffffff, 0xffffffffffffffff, 0  );
+  TEST_IMM_OP( 8,  slliw, 0xfffffffffffffffe, 0xffffffffffffffff, 1  );
+  TEST_IMM_OP( 9,  slliw, 0xffffffffffffff80, 0xffffffffffffffff, 7  );
+  TEST_IMM_OP( 10, slliw, 0xffffffffffffc000, 0xffffffffffffffff, 14 );
+  TEST_IMM_OP( 11, slliw, 0xffffffff80000000, 0xffffffffffffffff, 31 );
+
+  TEST_IMM_OP( 12, slliw, 0x0000000021212121, 0x0000000021212121, 0  );
+  TEST_IMM_OP( 13, slliw, 0x0000000042424242, 0x0000000021212121, 1  );
+  TEST_IMM_OP( 14, slliw, 0xffffffff90909080, 0x0000000021212121, 7  );
+  TEST_IMM_OP( 15, slliw, 0x0000000048484000, 0x0000000021212121, 14 );
+  TEST_IMM_OP( 16, slliw, 0xffffffff80000000, 0x0000000021212121, 31 );
+
+  # Verify that shifts ignore top 32 (using true 64-bit values)
+
+  TEST_IMM_OP( 44, slliw, 0x0000000012345678, 0xffffffff12345678, 0 );
+  TEST_IMM_OP( 45, slliw, 0x0000000023456780, 0xffffffff12345678, 4 );
+  TEST_IMM_OP( 46, slliw, 0xffffffff92345678, 0x0000000092345678, 0 );
+  TEST_IMM_OP( 47, slliw, 0xffffffff93456780, 0x0000000099345678, 4 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_SRC1_EQ_DEST( 17, slliw, 0x00000080, 0x00000001, 7 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_DEST_BYPASS( 18, 0, slliw, 0x0000000000000080, 0x0000000000000001, 7  );
+  TEST_IMM_DEST_BYPASS( 19, 1, slliw, 0x0000000000004000, 0x0000000000000001, 14 );
+  TEST_IMM_DEST_BYPASS( 20, 2, slliw, 0xffffffff80000000, 0x0000000000000001, 31 );
+
+  TEST_IMM_SRC1_BYPASS( 21, 0, slliw, 0x0000000000000080, 0x0000000000000001, 7  );
+  TEST_IMM_SRC1_BYPASS( 22, 1, slliw, 0x0000000000004000, 0x0000000000000001, 14 );
+  TEST_IMM_SRC1_BYPASS( 23, 2, slliw, 0xffffffff80000000, 0x0000000000000001, 31 );
+
+  TEST_IMM_ZEROSRC1( 24, slliw, 0, 31 );
+  TEST_IMM_ZERODEST( 25, slliw, 31, 28 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/sllw.S b/apps/riscv-tests/isa/rv64ui/sllw.S
new file mode 100644
index 0000000..62b4db6
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/sllw.S
@@ -0,0 +1,97 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sllw.S
+#-----------------------------------------------------------------------------
+#
+# Test sllw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  sllw, 0x0000000000000001, 0x0000000000000001, 0  );
+  TEST_RR_OP( 3,  sllw, 0x0000000000000002, 0x0000000000000001, 1  );
+  TEST_RR_OP( 4,  sllw, 0x0000000000000080, 0x0000000000000001, 7  );
+  TEST_RR_OP( 5,  sllw, 0x0000000000004000, 0x0000000000000001, 14 );
+  TEST_RR_OP( 6,  sllw, 0xffffffff80000000, 0x0000000000000001, 31 );
+
+  TEST_RR_OP( 7,  sllw, 0xffffffffffffffff, 0xffffffffffffffff, 0  );
+  TEST_RR_OP( 8,  sllw, 0xfffffffffffffffe, 0xffffffffffffffff, 1  );
+  TEST_RR_OP( 9,  sllw, 0xffffffffffffff80, 0xffffffffffffffff, 7  );
+  TEST_RR_OP( 10, sllw, 0xffffffffffffc000, 0xffffffffffffffff, 14 );
+  TEST_RR_OP( 11, sllw, 0xffffffff80000000, 0xffffffffffffffff, 31 );
+
+  TEST_RR_OP( 12, sllw, 0x0000000021212121, 0x0000000021212121, 0  );
+  TEST_RR_OP( 13, sllw, 0x0000000042424242, 0x0000000021212121, 1  );
+  TEST_RR_OP( 14, sllw, 0xffffffff90909080, 0x0000000021212121, 7  );
+  TEST_RR_OP( 15, sllw, 0x0000000048484000, 0x0000000021212121, 14 );
+  TEST_RR_OP( 16, sllw, 0xffffffff80000000, 0x0000000021212121, 31 );
+
+  # Verify that shifts only use bottom five bits
+
+  TEST_RR_OP( 17, sllw, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffe0 );
+  TEST_RR_OP( 18, sllw, 0x0000000042424242, 0x0000000021212121, 0xffffffffffffffe1 );
+  TEST_RR_OP( 19, sllw, 0xffffffff90909080, 0x0000000021212121, 0xffffffffffffffe7 );
+  TEST_RR_OP( 20, sllw, 0x0000000048484000, 0x0000000021212121, 0xffffffffffffffee );
+  TEST_RR_OP( 21, sllw, 0xffffffff80000000, 0x0000000021212121, 0xffffffffffffffff );
+
+  # Verify that shifts ignore top 32 (using true 64-bit values)
+
+  TEST_RR_OP( 44, sllw, 0x0000000012345678, 0xffffffff12345678, 0 );
+  TEST_RR_OP( 45, sllw, 0x0000000023456780, 0xffffffff12345678, 4 );
+  TEST_RR_OP( 46, sllw, 0xffffffff92345678, 0x0000000092345678, 0 );
+  TEST_RR_OP( 47, sllw, 0xffffffff93456780, 0x0000000099345678, 4 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 22, sllw, 0x00000080, 0x00000001, 7  );
+  TEST_RR_SRC2_EQ_DEST( 23, sllw, 0x00004000, 0x00000001, 14 );
+  TEST_RR_SRC12_EQ_DEST( 24, sllw, 24, 3 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 25, 0, sllw, 0x0000000000000080, 0x0000000000000001, 7  );
+  TEST_RR_DEST_BYPASS( 26, 1, sllw, 0x0000000000004000, 0x0000000000000001, 14 );
+  TEST_RR_DEST_BYPASS( 27, 2, sllw, 0xffffffff80000000, 0x0000000000000001, 31 );
+
+  TEST_RR_SRC12_BYPASS( 28, 0, 0, sllw, 0x0000000000000080, 0x0000000000000001, 7  );
+  TEST_RR_SRC12_BYPASS( 29, 0, 1, sllw, 0x0000000000004000, 0x0000000000000001, 14 );
+  TEST_RR_SRC12_BYPASS( 30, 0, 2, sllw, 0xffffffff80000000, 0x0000000000000001, 31 );
+  TEST_RR_SRC12_BYPASS( 31, 1, 0, sllw, 0x0000000000000080, 0x0000000000000001, 7  );
+  TEST_RR_SRC12_BYPASS( 32, 1, 1, sllw, 0x0000000000004000, 0x0000000000000001, 14 );
+  TEST_RR_SRC12_BYPASS( 33, 2, 0, sllw, 0xffffffff80000000, 0x0000000000000001, 31 );
+
+  TEST_RR_SRC21_BYPASS( 34, 0, 0, sllw, 0x0000000000000080, 0x0000000000000001, 7  );
+  TEST_RR_SRC21_BYPASS( 35, 0, 1, sllw, 0x0000000000004000, 0x0000000000000001, 14 );
+  TEST_RR_SRC21_BYPASS( 36, 0, 2, sllw, 0xffffffff80000000, 0x0000000000000001, 31 );
+  TEST_RR_SRC21_BYPASS( 37, 1, 0, sllw, 0x0000000000000080, 0x0000000000000001, 7  );
+  TEST_RR_SRC21_BYPASS( 38, 1, 1, sllw, 0x0000000000004000, 0x0000000000000001, 14 );
+  TEST_RR_SRC21_BYPASS( 39, 2, 0, sllw, 0xffffffff80000000, 0x0000000000000001, 31 );
+
+  TEST_RR_ZEROSRC1( 40, sllw, 0, 15 );
+  TEST_RR_ZEROSRC2( 41, sllw, 32, 32 );
+  TEST_RR_ZEROSRC12( 42, sllw, 0 );
+  TEST_RR_ZERODEST( 43, sllw, 1024, 2048 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/slt.S b/apps/riscv-tests/isa/rv64ui/slt.S
new file mode 100644
index 0000000..644a51a
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/slt.S
@@ -0,0 +1,84 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# slt.S
+#-----------------------------------------------------------------------------
+#
+# Test slt instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  slt, 0, 0x0000000000000000, 0x0000000000000000 );
+  TEST_RR_OP( 3,  slt, 0, 0x0000000000000001, 0x0000000000000001 );
+  TEST_RR_OP( 4,  slt, 1, 0x0000000000000003, 0x0000000000000007 );
+  TEST_RR_OP( 5,  slt, 0, 0x0000000000000007, 0x0000000000000003 );
+
+  TEST_RR_OP( 6,  slt, 0, 0x0000000000000000, 0xffffffffffff8000 );
+  TEST_RR_OP( 7,  slt, 1, 0xffffffff80000000, 0x0000000000000000 );
+  TEST_RR_OP( 8,  slt, 1, 0xffffffff80000000, 0xffffffffffff8000 );
+
+  TEST_RR_OP( 9,  slt, 1, 0x0000000000000000, 0x0000000000007fff );
+  TEST_RR_OP( 10, slt, 0, 0x000000007fffffff, 0x0000000000000000 );
+  TEST_RR_OP( 11, slt, 0, 0x000000007fffffff, 0x0000000000007fff );
+
+  TEST_RR_OP( 12, slt, 1, 0xffffffff80000000, 0x0000000000007fff );
+  TEST_RR_OP( 13, slt, 0, 0x000000007fffffff, 0xffffffffffff8000 );
+
+  TEST_RR_OP( 14, slt, 0, 0x0000000000000000, 0xffffffffffffffff );
+  TEST_RR_OP( 15, slt, 1, 0xffffffffffffffff, 0x0000000000000001 );
+  TEST_RR_OP( 16, slt, 0, 0xffffffffffffffff, 0xffffffffffffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 17, slt, 0, 14, 13 );
+  TEST_RR_SRC2_EQ_DEST( 18, slt, 1, 11, 13 );
+  TEST_RR_SRC12_EQ_DEST( 19, slt, 0, 13 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 20, 0, slt, 1, 11, 13 );
+  TEST_RR_DEST_BYPASS( 21, 1, slt, 0, 14, 13 );
+  TEST_RR_DEST_BYPASS( 22, 2, slt, 1, 12, 13 );
+
+  TEST_RR_SRC12_BYPASS( 23, 0, 0, slt, 0, 14, 13 );
+  TEST_RR_SRC12_BYPASS( 24, 0, 1, slt, 1, 11, 13 );
+  TEST_RR_SRC12_BYPASS( 25, 0, 2, slt, 0, 15, 13 );
+  TEST_RR_SRC12_BYPASS( 26, 1, 0, slt, 1, 10, 13 );
+  TEST_RR_SRC12_BYPASS( 27, 1, 1, slt, 0, 16, 13 );
+  TEST_RR_SRC12_BYPASS( 28, 2, 0, slt, 1,  9, 13 );
+
+  TEST_RR_SRC21_BYPASS( 29, 0, 0, slt, 0, 17, 13 );
+  TEST_RR_SRC21_BYPASS( 30, 0, 1, slt, 1,  8, 13 );
+  TEST_RR_SRC21_BYPASS( 31, 0, 2, slt, 0, 18, 13 );
+  TEST_RR_SRC21_BYPASS( 32, 1, 0, slt, 1,  7, 13 );
+  TEST_RR_SRC21_BYPASS( 33, 1, 1, slt, 0, 19, 13 );
+  TEST_RR_SRC21_BYPASS( 34, 2, 0, slt, 1,  6, 13 );
+
+  TEST_RR_ZEROSRC1( 35, slt, 0, -1 );
+  TEST_RR_ZEROSRC2( 36, slt, 1, -1 );
+  TEST_RR_ZEROSRC12( 37, slt, 0 );
+  TEST_RR_ZERODEST( 38, slt, 16, 30 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/slti.S b/apps/riscv-tests/isa/rv64ui/slti.S
new file mode 100644
index 0000000..9222fa4
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/slti.S
@@ -0,0 +1,70 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# slti.S
+#-----------------------------------------------------------------------------
+#
+# Test slti instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_OP( 2,  slti, 0, 0x0000000000000000, 0x000 );
+  TEST_IMM_OP( 3,  slti, 0, 0x0000000000000001, 0x001 );
+  TEST_IMM_OP( 4,  slti, 1, 0x0000000000000003, 0x007 );
+  TEST_IMM_OP( 5,  slti, 0, 0x0000000000000007, 0x003 );
+
+  TEST_IMM_OP( 6,  slti, 0, 0x0000000000000000, 0x800 );
+  TEST_IMM_OP( 7,  slti, 1, 0xffffffff80000000, 0x000 );
+  TEST_IMM_OP( 8,  slti, 1, 0xffffffff80000000, 0x800 );
+
+  TEST_IMM_OP( 9,  slti, 1, 0x0000000000000000, 0x7ff );
+  TEST_IMM_OP( 10, slti, 0, 0x000000007fffffff, 0x000 );
+  TEST_IMM_OP( 11, slti, 0, 0x000000007fffffff, 0x7ff );
+
+  TEST_IMM_OP( 12, slti, 1, 0xffffffff80000000, 0x7ff );
+  TEST_IMM_OP( 13, slti, 0, 0x000000007fffffff, 0x800 );
+
+  TEST_IMM_OP( 14, slti, 0, 0x0000000000000000, 0xfff );
+  TEST_IMM_OP( 15, slti, 1, 0xffffffffffffffff, 0x001 );
+  TEST_IMM_OP( 16, slti, 0, 0xffffffffffffffff, 0xfff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_SRC1_EQ_DEST( 17, slti, 1, 11, 13 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_DEST_BYPASS( 18, 0, slti, 0, 15, 10 );
+  TEST_IMM_DEST_BYPASS( 19, 1, slti, 1, 10, 16 );
+  TEST_IMM_DEST_BYPASS( 20, 2, slti, 0, 16,  9 );
+
+  TEST_IMM_SRC1_BYPASS( 21, 0, slti, 1, 11, 15 );
+  TEST_IMM_SRC1_BYPASS( 22, 1, slti, 0, 17,  8 );
+  TEST_IMM_SRC1_BYPASS( 23, 2, slti, 1, 12, 14 );
+
+  TEST_IMM_ZEROSRC1( 24, slti, 0, 0xfff );
+  TEST_IMM_ZERODEST( 25, slti, 0x00ff00ff, 0xfff );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/sltiu.S b/apps/riscv-tests/isa/rv64ui/sltiu.S
new file mode 100644
index 0000000..f6a719b
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/sltiu.S
@@ -0,0 +1,70 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sltiu.S
+#-----------------------------------------------------------------------------
+#
+# Test sltiu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_OP( 2,  sltiu, 0, 0x0000000000000000, 0x000 );
+  TEST_IMM_OP( 3,  sltiu, 0, 0x0000000000000001, 0x001 );
+  TEST_IMM_OP( 4,  sltiu, 1, 0x0000000000000003, 0x007 );
+  TEST_IMM_OP( 5,  sltiu, 0, 0x0000000000000007, 0x003 );
+
+  TEST_IMM_OP( 6,  sltiu, 1, 0x0000000000000000, 0x800 );
+  TEST_IMM_OP( 7,  sltiu, 0, 0xffffffff80000000, 0x000 );
+  TEST_IMM_OP( 8,  sltiu, 1, 0xffffffff80000000, 0x800 );
+
+  TEST_IMM_OP( 9,  sltiu, 1, 0x0000000000000000, 0x7ff );
+  TEST_IMM_OP( 10, sltiu, 0, 0x000000007fffffff, 0x000 );
+  TEST_IMM_OP( 11, sltiu, 0, 0x000000007fffffff, 0x7ff );
+
+  TEST_IMM_OP( 12, sltiu, 0, 0xffffffff80000000, 0x7ff );
+  TEST_IMM_OP( 13, sltiu, 1, 0x000000007fffffff, 0x800 );
+
+  TEST_IMM_OP( 14, sltiu, 1, 0x0000000000000000, 0xfff );
+  TEST_IMM_OP( 15, sltiu, 0, 0xffffffffffffffff, 0x001 );
+  TEST_IMM_OP( 16, sltiu, 0, 0xffffffffffffffff, 0xfff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_SRC1_EQ_DEST( 17, sltiu, 1, 11, 13 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_DEST_BYPASS( 18, 0, sltiu, 0, 15, 10 );
+  TEST_IMM_DEST_BYPASS( 19, 1, sltiu, 1, 10, 16 );
+  TEST_IMM_DEST_BYPASS( 20, 2, sltiu, 0, 16,  9 );
+
+  TEST_IMM_SRC1_BYPASS( 21, 0, sltiu, 1, 11, 15 );
+  TEST_IMM_SRC1_BYPASS( 22, 1, sltiu, 0, 17,  8 );
+  TEST_IMM_SRC1_BYPASS( 23, 2, sltiu, 1, 12, 14 );
+
+  TEST_IMM_ZEROSRC1( 24, sltiu, 1, 0xfff );
+  TEST_IMM_ZERODEST( 25, sltiu, 0x00ff00ff, 0xfff );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/sltu.S b/apps/riscv-tests/isa/rv64ui/sltu.S
new file mode 100644
index 0000000..52ff685
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/sltu.S
@@ -0,0 +1,84 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sltu.S
+#-----------------------------------------------------------------------------
+#
+# Test sltu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  sltu, 0, 0x00000000, 0x00000000 );
+  TEST_RR_OP( 3,  sltu, 0, 0x00000001, 0x00000001 );
+  TEST_RR_OP( 4,  sltu, 1, 0x00000003, 0x00000007 );
+  TEST_RR_OP( 5,  sltu, 0, 0x00000007, 0x00000003 );
+
+  TEST_RR_OP( 6,  sltu, 1, 0x00000000, 0xffff8000 );
+  TEST_RR_OP( 7,  sltu, 0, 0x80000000, 0x00000000 );
+  TEST_RR_OP( 8,  sltu, 1, 0x80000000, 0xffff8000 );
+
+  TEST_RR_OP( 9,  sltu, 1, 0x00000000, 0x00007fff );
+  TEST_RR_OP( 10, sltu, 0, 0x7fffffff, 0x00000000 );
+  TEST_RR_OP( 11, sltu, 0, 0x7fffffff, 0x00007fff );
+
+  TEST_RR_OP( 12, sltu, 0, 0x80000000, 0x00007fff );
+  TEST_RR_OP( 13, sltu, 1, 0x7fffffff, 0xffff8000 );
+
+  TEST_RR_OP( 14, sltu, 1, 0x00000000, 0xffffffff );
+  TEST_RR_OP( 15, sltu, 0, 0xffffffff, 0x00000001 );
+  TEST_RR_OP( 16, sltu, 0, 0xffffffff, 0xffffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 17, sltu, 0, 14, 13 );
+  TEST_RR_SRC2_EQ_DEST( 18, sltu, 1, 11, 13 );
+  TEST_RR_SRC12_EQ_DEST( 19, sltu, 0, 13 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 20, 0, sltu, 1, 11, 13 );
+  TEST_RR_DEST_BYPASS( 21, 1, sltu, 0, 14, 13 );
+  TEST_RR_DEST_BYPASS( 22, 2, sltu, 1, 12, 13 );
+
+  TEST_RR_SRC12_BYPASS( 23, 0, 0, sltu, 0, 14, 13 );
+  TEST_RR_SRC12_BYPASS( 24, 0, 1, sltu, 1, 11, 13 );
+  TEST_RR_SRC12_BYPASS( 25, 0, 2, sltu, 0, 15, 13 );
+  TEST_RR_SRC12_BYPASS( 26, 1, 0, sltu, 1, 10, 13 );
+  TEST_RR_SRC12_BYPASS( 27, 1, 1, sltu, 0, 16, 13 );
+  TEST_RR_SRC12_BYPASS( 28, 2, 0, sltu, 1,  9, 13 );
+
+  TEST_RR_SRC21_BYPASS( 29, 0, 0, sltu, 0, 17, 13 );
+  TEST_RR_SRC21_BYPASS( 30, 0, 1, sltu, 1,  8, 13 );
+  TEST_RR_SRC21_BYPASS( 31, 0, 2, sltu, 0, 18, 13 );
+  TEST_RR_SRC21_BYPASS( 32, 1, 0, sltu, 1,  7, 13 );
+  TEST_RR_SRC21_BYPASS( 33, 1, 1, sltu, 0, 19, 13 );
+  TEST_RR_SRC21_BYPASS( 34, 2, 0, sltu, 1,  6, 13 );
+
+  TEST_RR_ZEROSRC1( 35, sltu, 1, -1 );
+  TEST_RR_ZEROSRC2( 36, sltu, 0, -1 );
+  TEST_RR_ZEROSRC12( 37, sltu, 0 );
+  TEST_RR_ZERODEST( 38, sltu, 16, 30 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/sra.S b/apps/riscv-tests/isa/rv64ui/sra.S
new file mode 100644
index 0000000..580ae89
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/sra.S
@@ -0,0 +1,90 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sra.S
+#-----------------------------------------------------------------------------
+#
+# Test sra instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  sra, 0xffffffff80000000, 0xffffffff80000000, 0  );
+  TEST_RR_OP( 3,  sra, 0xffffffffc0000000, 0xffffffff80000000, 1  );
+  TEST_RR_OP( 4,  sra, 0xffffffffff000000, 0xffffffff80000000, 7  );
+  TEST_RR_OP( 5,  sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+  TEST_RR_OP( 6,  sra, 0xffffffffffffffff, 0xffffffff80000001, 31 );
+
+  TEST_RR_OP( 7,  sra, 0x000000007fffffff, 0x000000007fffffff, 0  );
+  TEST_RR_OP( 8,  sra, 0x000000003fffffff, 0x000000007fffffff, 1  );
+  TEST_RR_OP( 9,  sra, 0x0000000000ffffff, 0x000000007fffffff, 7  );
+  TEST_RR_OP( 10, sra, 0x000000000001ffff, 0x000000007fffffff, 14 );
+  TEST_RR_OP( 11, sra, 0x0000000000000000, 0x000000007fffffff, 31 );
+
+  TEST_RR_OP( 12, sra, 0xffffffff81818181, 0xffffffff81818181, 0  );
+  TEST_RR_OP( 13, sra, 0xffffffffc0c0c0c0, 0xffffffff81818181, 1  );
+  TEST_RR_OP( 14, sra, 0xffffffffff030303, 0xffffffff81818181, 7  );
+  TEST_RR_OP( 15, sra, 0xfffffffffffe0606, 0xffffffff81818181, 14 );
+  TEST_RR_OP( 16, sra, 0xffffffffffffffff, 0xffffffff81818181, 31 );
+
+  # Verify that shifts only use bottom six(rv64) or five(rv32) bits
+
+  TEST_RR_OP( 17, sra, 0xffffffff81818181, 0xffffffff81818181, 0xffffffffffffffc0 );
+  TEST_RR_OP( 18, sra, 0xffffffffc0c0c0c0, 0xffffffff81818181, 0xffffffffffffffc1 );
+  TEST_RR_OP( 19, sra, 0xffffffffff030303, 0xffffffff81818181, 0xffffffffffffffc7 );
+  TEST_RR_OP( 20, sra, 0xfffffffffffe0606, 0xffffffff81818181, 0xffffffffffffffce );
+  TEST_RR_OP( 21, sra, 0xffffffffffffffff, 0xffffffff81818181, 0xffffffffffffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 22, sra, 0xffffffffff000000, 0xffffffff80000000, 7  );
+  TEST_RR_SRC2_EQ_DEST( 23, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+  TEST_RR_SRC12_EQ_DEST( 24, sra, 0, 7 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 25, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7  );
+  TEST_RR_DEST_BYPASS( 26, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+  TEST_RR_DEST_BYPASS( 27, 2, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 );
+
+  TEST_RR_SRC12_BYPASS( 28, 0, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7  );
+  TEST_RR_SRC12_BYPASS( 29, 0, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+  TEST_RR_SRC12_BYPASS( 30, 0, 2, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 );
+  TEST_RR_SRC12_BYPASS( 31, 1, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7  );
+  TEST_RR_SRC12_BYPASS( 32, 1, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+  TEST_RR_SRC12_BYPASS( 33, 2, 0, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 );
+
+  TEST_RR_SRC21_BYPASS( 34, 0, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7  );
+  TEST_RR_SRC21_BYPASS( 35, 0, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+  TEST_RR_SRC21_BYPASS( 36, 0, 2, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 );
+  TEST_RR_SRC21_BYPASS( 37, 1, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7  );
+  TEST_RR_SRC21_BYPASS( 38, 1, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+  TEST_RR_SRC21_BYPASS( 39, 2, 0, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 );
+
+  TEST_RR_ZEROSRC1( 40, sra, 0, 15 );
+  TEST_RR_ZEROSRC2( 41, sra, 32, 32 );
+  TEST_RR_ZEROSRC12( 42, sra, 0 );
+  TEST_RR_ZERODEST( 43, sra, 1024, 2048 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/srai.S b/apps/riscv-tests/isa/rv64ui/srai.S
new file mode 100644
index 0000000..8d05213
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/srai.S
@@ -0,0 +1,68 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# srai.S
+#-----------------------------------------------------------------------------
+#
+# Test srai instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_OP( 2,  srai, 0xffffff8000000000, 0xffffff8000000000, 0  );
+  TEST_IMM_OP( 3,  srai, 0xffffffffc0000000, 0xffffffff80000000, 1  );
+  TEST_IMM_OP( 4,  srai, 0xffffffffff000000, 0xffffffff80000000, 7  );
+  TEST_IMM_OP( 5,  srai, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+  TEST_IMM_OP( 6,  srai, 0xffffffffffffffff, 0xffffffff80000001, 31 );
+
+  TEST_IMM_OP( 7,  srai, 0x000000007fffffff, 0x000000007fffffff, 0  );
+  TEST_IMM_OP( 8,  srai, 0x000000003fffffff, 0x000000007fffffff, 1  );
+  TEST_IMM_OP( 9,  srai, 0x0000000000ffffff, 0x000000007fffffff, 7  );
+  TEST_IMM_OP( 10, srai, 0x000000000001ffff, 0x000000007fffffff, 14 );
+  TEST_IMM_OP( 11, srai, 0x0000000000000000, 0x000000007fffffff, 31 );
+
+  TEST_IMM_OP( 12, srai, 0xffffffff81818181, 0xffffffff81818181, 0  );
+  TEST_IMM_OP( 13, srai, 0xffffffffc0c0c0c0, 0xffffffff81818181, 1  );
+  TEST_IMM_OP( 14, srai, 0xffffffffff030303, 0xffffffff81818181, 7  );
+  TEST_IMM_OP( 15, srai, 0xfffffffffffe0606, 0xffffffff81818181, 14 );
+  TEST_IMM_OP( 16, srai, 0xffffffffffffffff, 0xffffffff81818181, 31 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_SRC1_EQ_DEST( 17, srai, 0xffffffffff000000, 0xffffffff80000000, 7 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_DEST_BYPASS( 18, 0, srai, 0xffffffffff000000, 0xffffffff80000000, 7  );
+  TEST_IMM_DEST_BYPASS( 19, 1, srai, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+  TEST_IMM_DEST_BYPASS( 20, 2, srai, 0xffffffffffffffff, 0xffffffff80000001, 31 );
+
+  TEST_IMM_SRC1_BYPASS( 21, 0, srai, 0xffffffffff000000, 0xffffffff80000000, 7 );
+  TEST_IMM_SRC1_BYPASS( 22, 1, srai, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+  TEST_IMM_SRC1_BYPASS( 23, 2, srai, 0xffffffffffffffff, 0xffffffff80000001, 31 );
+
+  TEST_IMM_ZEROSRC1( 24, srai, 0, 4 );
+  TEST_IMM_ZERODEST( 25, srai, 33, 10 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/sraiw.S b/apps/riscv-tests/isa/rv64ui/sraiw.S
new file mode 100644
index 0000000..a435e59
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/sraiw.S
@@ -0,0 +1,78 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sraiw.S
+#-----------------------------------------------------------------------------
+#
+# Test sraiw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_OP( 2,  sraiw, 0xffffffff80000000, 0xffffffff80000000, 0  );
+  TEST_IMM_OP( 3,  sraiw, 0xffffffffc0000000, 0xffffffff80000000, 1  );
+  TEST_IMM_OP( 4,  sraiw, 0xffffffffff000000, 0xffffffff80000000, 7  );
+  TEST_IMM_OP( 5,  sraiw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+  TEST_IMM_OP( 6,  sraiw, 0xffffffffffffffff, 0xffffffff80000001, 31 );
+
+  TEST_IMM_OP( 7,  sraiw, 0x000000007fffffff, 0x000000007fffffff, 0  );
+  TEST_IMM_OP( 8,  sraiw, 0x000000003fffffff, 0x000000007fffffff, 1  );
+  TEST_IMM_OP( 9,  sraiw, 0x0000000000ffffff, 0x000000007fffffff, 7  );
+  TEST_IMM_OP( 10, sraiw, 0x000000000001ffff, 0x000000007fffffff, 14 );
+  TEST_IMM_OP( 11, sraiw, 0x0000000000000000, 0x000000007fffffff, 31 );
+
+  TEST_IMM_OP( 12, sraiw, 0xffffffff81818181, 0xffffffff81818181, 0  );
+  TEST_IMM_OP( 13, sraiw, 0xffffffffc0c0c0c0, 0xffffffff81818181, 1  );
+  TEST_IMM_OP( 14, sraiw, 0xffffffffff030303, 0xffffffff81818181, 7  );
+  TEST_IMM_OP( 15, sraiw, 0xfffffffffffe0606, 0xffffffff81818181, 14 );
+  TEST_IMM_OP( 16, sraiw, 0xffffffffffffffff, 0xffffffff81818181, 31 );
+
+  # Verify that shifts ignore top 32 (using true 64-bit values)
+
+  TEST_IMM_OP( 44, sraiw, 0x0000000012345678, 0xffffffff12345678, 0 );
+  TEST_IMM_OP( 45, sraiw, 0x0000000001234567, 0xffffffff12345678, 4 );
+  TEST_IMM_OP( 46, sraiw, 0xffffffff92345678, 0x0000000092345678, 0 );
+  TEST_IMM_OP( 47, sraiw, 0xfffffffff9234567, 0x0000000092345678, 4 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_SRC1_EQ_DEST( 17, sraiw, 0xffffffffff000000, 0xffffffff80000000, 7 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_DEST_BYPASS( 18, 0, sraiw, 0xffffffffff000000, 0xffffffff80000000, 7  );
+  TEST_IMM_DEST_BYPASS( 19, 1, sraiw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+  TEST_IMM_DEST_BYPASS( 20, 2, sraiw, 0xffffffffffffffff, 0xffffffff80000001, 31 );
+
+  TEST_IMM_SRC1_BYPASS( 21, 0, sraiw, 0xffffffffff000000, 0xffffffff80000000, 7 );
+  TEST_IMM_SRC1_BYPASS( 22, 1, sraiw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+  TEST_IMM_SRC1_BYPASS( 23, 2, sraiw, 0xffffffffffffffff, 0xffffffff80000001, 31 );
+
+  TEST_IMM_ZEROSRC1( 24, sraiw, 0, 31 );
+  TEST_IMM_ZERODEST( 25, sraiw, 31, 28 );
+
+  TEST_IMM_OP( 26, sraiw, 0x0000000000000000, 0x00e0000000000000, 28)
+  TEST_IMM_OP( 27, sraiw, 0xffffffffff000000, 0x00000000f0000000, 4)
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/sraw.S b/apps/riscv-tests/isa/rv64ui/sraw.S
new file mode 100644
index 0000000..68d913e
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/sraw.S
@@ -0,0 +1,97 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sraw.S
+#-----------------------------------------------------------------------------
+#
+# Test sraw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  sraw, 0xffffffff80000000, 0xffffffff80000000, 0  );
+  TEST_RR_OP( 3,  sraw, 0xffffffffc0000000, 0xffffffff80000000, 1  );
+  TEST_RR_OP( 4,  sraw, 0xffffffffff000000, 0xffffffff80000000, 7  );
+  TEST_RR_OP( 5,  sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+  TEST_RR_OP( 6,  sraw, 0xffffffffffffffff, 0xffffffff80000001, 31 );
+
+  TEST_RR_OP( 7,  sraw, 0x000000007fffffff, 0x000000007fffffff, 0  );
+  TEST_RR_OP( 8,  sraw, 0x000000003fffffff, 0x000000007fffffff, 1  );
+  TEST_RR_OP( 9,  sraw, 0x0000000000ffffff, 0x000000007fffffff, 7  );
+  TEST_RR_OP( 10, sraw, 0x000000000001ffff, 0x000000007fffffff, 14 );
+  TEST_RR_OP( 11, sraw, 0x0000000000000000, 0x000000007fffffff, 31 );
+
+  TEST_RR_OP( 12, sraw, 0xffffffff81818181, 0xffffffff81818181, 0  );
+  TEST_RR_OP( 13, sraw, 0xffffffffc0c0c0c0, 0xffffffff81818181, 1  );
+  TEST_RR_OP( 14, sraw, 0xffffffffff030303, 0xffffffff81818181, 7  );
+  TEST_RR_OP( 15, sraw, 0xfffffffffffe0606, 0xffffffff81818181, 14 );
+  TEST_RR_OP( 16, sraw, 0xffffffffffffffff, 0xffffffff81818181, 31 );
+
+  # Verify that shifts only use bottom five bits
+
+  TEST_RR_OP( 17, sraw, 0xffffffff81818181, 0xffffffff81818181, 0xffffffffffffffe0 );
+  TEST_RR_OP( 18, sraw, 0xffffffffc0c0c0c0, 0xffffffff81818181, 0xffffffffffffffe1 );
+  TEST_RR_OP( 19, sraw, 0xffffffffff030303, 0xffffffff81818181, 0xffffffffffffffe7 );
+  TEST_RR_OP( 20, sraw, 0xfffffffffffe0606, 0xffffffff81818181, 0xffffffffffffffee );
+  TEST_RR_OP( 21, sraw, 0xffffffffffffffff, 0xffffffff81818181, 0xffffffffffffffff );
+
+  # Verify that shifts ignore top 32 (using true 64-bit values)
+
+  TEST_RR_OP( 44, sraw, 0x0000000012345678, 0xffffffff12345678, 0 );
+  TEST_RR_OP( 45, sraw, 0x0000000001234567, 0xffffffff12345678, 4 );
+  TEST_RR_OP( 46, sraw, 0xffffffff92345678, 0x0000000092345678, 0 );
+  TEST_RR_OP( 47, sraw, 0xfffffffff9234567, 0x0000000092345678, 4 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 22, sraw, 0xffffffffff000000, 0xffffffff80000000, 7  );
+  TEST_RR_SRC2_EQ_DEST( 23, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+  TEST_RR_SRC12_EQ_DEST( 24, sraw, 0, 7 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 25, 0, sraw, 0xffffffffff000000, 0xffffffff80000000, 7  );
+  TEST_RR_DEST_BYPASS( 26, 1, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+  TEST_RR_DEST_BYPASS( 27, 2, sraw, 0xffffffffffffffff, 0xffffffff80000000, 31 );
+
+  TEST_RR_SRC12_BYPASS( 28, 0, 0, sraw, 0xffffffffff000000, 0xffffffff80000000, 7  );
+  TEST_RR_SRC12_BYPASS( 29, 0, 1, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+  TEST_RR_SRC12_BYPASS( 30, 0, 2, sraw, 0xffffffffffffffff, 0xffffffff80000000, 31 );
+  TEST_RR_SRC12_BYPASS( 31, 1, 0, sraw, 0xffffffffff000000, 0xffffffff80000000, 7  );
+  TEST_RR_SRC12_BYPASS( 32, 1, 1, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+  TEST_RR_SRC12_BYPASS( 33, 2, 0, sraw, 0xffffffffffffffff, 0xffffffff80000000, 31 );
+
+  TEST_RR_SRC21_BYPASS( 34, 0, 0, sraw, 0xffffffffff000000, 0xffffffff80000000, 7  );
+  TEST_RR_SRC21_BYPASS( 35, 0, 1, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+  TEST_RR_SRC21_BYPASS( 36, 0, 2, sraw, 0xffffffffffffffff, 0xffffffff80000000, 31 );
+  TEST_RR_SRC21_BYPASS( 37, 1, 0, sraw, 0xffffffffff000000, 0xffffffff80000000, 7  );
+  TEST_RR_SRC21_BYPASS( 38, 1, 1, sraw, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
+  TEST_RR_SRC21_BYPASS( 39, 2, 0, sraw, 0xffffffffffffffff, 0xffffffff80000000, 31 );
+
+  TEST_RR_ZEROSRC1( 40, sraw, 0, 15 );
+  TEST_RR_ZEROSRC2( 41, sraw, 32, 32 );
+  TEST_RR_ZEROSRC12( 42, sraw, 0 );
+  TEST_RR_ZERODEST( 43, sraw, 1024, 2048 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/srl.S b/apps/riscv-tests/isa/rv64ui/srl.S
new file mode 100644
index 0000000..5ee223f
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/srl.S
@@ -0,0 +1,93 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# srl.S
+#-----------------------------------------------------------------------------
+#
+# Test srl instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+#define TEST_SRL(n, v, a) \
+  TEST_RR_OP(n, srl, ((v) & ((1 << (__riscv_xlen-1) << 1) - 1)) >> (a), v, a)
+
+  TEST_SRL( 2,  0xffffffff80000000, 0  );
+  TEST_SRL( 3,  0xffffffff80000000, 1  );
+  TEST_SRL( 4,  0xffffffff80000000, 7  );
+  TEST_SRL( 5,  0xffffffff80000000, 14 );
+  TEST_SRL( 6,  0xffffffff80000001, 31 );
+
+  TEST_SRL( 7,  0xffffffffffffffff, 0  );
+  TEST_SRL( 8,  0xffffffffffffffff, 1  );
+  TEST_SRL( 9,  0xffffffffffffffff, 7  );
+  TEST_SRL( 10, 0xffffffffffffffff, 14 );
+  TEST_SRL( 11, 0xffffffffffffffff, 31 );
+
+  TEST_SRL( 12, 0x0000000021212121, 0  );
+  TEST_SRL( 13, 0x0000000021212121, 1  );
+  TEST_SRL( 14, 0x0000000021212121, 7  );
+  TEST_SRL( 15, 0x0000000021212121, 14 );
+  TEST_SRL( 16, 0x0000000021212121, 31 );
+
+  # Verify that shifts only use bottom six(rv64) or five(rv32) bits
+
+  TEST_RR_OP( 17, srl, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffc0 );
+  TEST_RR_OP( 18, srl, 0x0000000010909090, 0x0000000021212121, 0xffffffffffffffc1 );
+  TEST_RR_OP( 19, srl, 0x0000000000424242, 0x0000000021212121, 0xffffffffffffffc7 );
+  TEST_RR_OP( 20, srl, 0x0000000000008484, 0x0000000021212121, 0xffffffffffffffce );
+  TEST_RR_OP( 21, srl, 0x0000000000000000, 0x0000000021212121, 0xffffffffffffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 22, srl, 0x01000000, 0x80000000, 7  );
+  TEST_RR_SRC2_EQ_DEST( 23, srl, 0x00020000, 0x80000000, 14 );
+  TEST_RR_SRC12_EQ_DEST( 24, srl, 0, 7 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 25, 0, srl, 0x01000000, 0x80000000, 7  );
+  TEST_RR_DEST_BYPASS( 26, 1, srl, 0x00020000, 0x80000000, 14 );
+  TEST_RR_DEST_BYPASS( 27, 2, srl, 0x00000001, 0x80000000, 31 );
+
+  TEST_RR_SRC12_BYPASS( 28, 0, 0, srl, 0x01000000, 0x80000000, 7  );
+  TEST_RR_SRC12_BYPASS( 29, 0, 1, srl, 0x00020000, 0x80000000, 14 );
+  TEST_RR_SRC12_BYPASS( 30, 0, 2, srl, 0x00000001, 0x80000000, 31 );
+  TEST_RR_SRC12_BYPASS( 31, 1, 0, srl, 0x01000000, 0x80000000, 7  );
+  TEST_RR_SRC12_BYPASS( 32, 1, 1, srl, 0x00020000, 0x80000000, 14 );
+  TEST_RR_SRC12_BYPASS( 33, 2, 0, srl, 0x00000001, 0x80000000, 31 );
+
+  TEST_RR_SRC21_BYPASS( 34, 0, 0, srl, 0x01000000, 0x80000000, 7  );
+  TEST_RR_SRC21_BYPASS( 35, 0, 1, srl, 0x00020000, 0x80000000, 14 );
+  TEST_RR_SRC21_BYPASS( 36, 0, 2, srl, 0x00000001, 0x80000000, 31 );
+  TEST_RR_SRC21_BYPASS( 37, 1, 0, srl, 0x01000000, 0x80000000, 7  );
+  TEST_RR_SRC21_BYPASS( 38, 1, 1, srl, 0x00020000, 0x80000000, 14 );
+  TEST_RR_SRC21_BYPASS( 39, 2, 0, srl, 0x00000001, 0x80000000, 31 );
+
+  TEST_RR_ZEROSRC1( 40, srl, 0, 15 );
+  TEST_RR_ZEROSRC2( 41, srl, 32, 32 );
+  TEST_RR_ZEROSRC12( 42, srl, 0 );
+  TEST_RR_ZERODEST( 43, srl, 1024, 2048 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/srli.S b/apps/riscv-tests/isa/rv64ui/srli.S
new file mode 100644
index 0000000..3522957
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/srli.S
@@ -0,0 +1,71 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# srli.S
+#-----------------------------------------------------------------------------
+#
+# Test srli instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+#define TEST_SRLI(n, v, a) \
+  TEST_IMM_OP(n, srli, ((v) & ((1 << (__riscv_xlen-1) << 1) - 1)) >> (a), v, a)
+
+  TEST_SRLI( 2,  0xffffffff80000000, 0  );
+  TEST_SRLI( 3,  0xffffffff80000000, 1  );
+  TEST_SRLI( 4,  0xffffffff80000000, 7  );
+  TEST_SRLI( 5,  0xffffffff80000000, 14 );
+  TEST_SRLI( 6,  0xffffffff80000001, 31 );
+
+  TEST_SRLI( 7,  0xffffffffffffffff, 0  );
+  TEST_SRLI( 8,  0xffffffffffffffff, 1  );
+  TEST_SRLI( 9,  0xffffffffffffffff, 7  );
+  TEST_SRLI( 10, 0xffffffffffffffff, 14 );
+  TEST_SRLI( 11, 0xffffffffffffffff, 31 );
+
+  TEST_SRLI( 12, 0x0000000021212121, 0  );
+  TEST_SRLI( 13, 0x0000000021212121, 1  );
+  TEST_SRLI( 14, 0x0000000021212121, 7  );
+  TEST_SRLI( 15, 0x0000000021212121, 14 );
+  TEST_SRLI( 16, 0x0000000021212121, 31 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_SRC1_EQ_DEST( 17, srli, 0x01000000, 0x80000000, 7 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_DEST_BYPASS( 18, 0, srli, 0x01000000, 0x80000000, 7  );
+  TEST_IMM_DEST_BYPASS( 19, 1, srli, 0x00020000, 0x80000000, 14 );
+  TEST_IMM_DEST_BYPASS( 20, 2, srli, 0x00000001, 0x80000001, 31 );
+
+  TEST_IMM_SRC1_BYPASS( 21, 0, srli, 0x01000000, 0x80000000, 7  );
+  TEST_IMM_SRC1_BYPASS( 22, 1, srli, 0x00020000, 0x80000000, 14 );
+  TEST_IMM_SRC1_BYPASS( 23, 2, srli, 0x00000001, 0x80000001, 31 );
+
+  TEST_IMM_ZEROSRC1( 24, srli, 0, 4 );
+  TEST_IMM_ZERODEST( 25, srli, 33, 10 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/srliw.S b/apps/riscv-tests/isa/rv64ui/srliw.S
new file mode 100644
index 0000000..471042f
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/srliw.S
@@ -0,0 +1,75 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# srliw.S
+#-----------------------------------------------------------------------------
+#
+# Test srliw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_OP( 2,  srliw, 0xffffffff80000000, 0xffffffff80000000, 0  );
+  TEST_IMM_OP( 3,  srliw, 0x0000000040000000, 0xffffffff80000000, 1  );
+  TEST_IMM_OP( 4,  srliw, 0x0000000001000000, 0xffffffff80000000, 7  );
+  TEST_IMM_OP( 5,  srliw, 0x0000000000020000, 0xffffffff80000000, 14 );
+  TEST_IMM_OP( 6,  srliw, 0x0000000000000001, 0xffffffff80000001, 31 );
+
+  TEST_IMM_OP( 7,  srliw, 0xffffffffffffffff, 0xffffffffffffffff, 0  );
+  TEST_IMM_OP( 8,  srliw, 0x000000007fffffff, 0xffffffffffffffff, 1  );
+  TEST_IMM_OP( 9,  srliw, 0x0000000001ffffff, 0xffffffffffffffff, 7  );
+  TEST_IMM_OP( 10, srliw, 0x000000000003ffff, 0xffffffffffffffff, 14 );
+  TEST_IMM_OP( 11, srliw, 0x0000000000000001, 0xffffffffffffffff, 31 );
+
+  TEST_IMM_OP( 12, srliw, 0x0000000021212121, 0x0000000021212121, 0  );
+  TEST_IMM_OP( 13, srliw, 0x0000000010909090, 0x0000000021212121, 1  );
+  TEST_IMM_OP( 14, srliw, 0x0000000000424242, 0x0000000021212121, 7  );
+  TEST_IMM_OP( 15, srliw, 0x0000000000008484, 0x0000000021212121, 14 );
+  TEST_IMM_OP( 16, srliw, 0x0000000000000000, 0x0000000021212121, 31 );
+
+  # Verify that shifts ignore top 32 (using true 64-bit values)
+
+  TEST_IMM_OP( 44, srliw, 0x0000000012345678, 0xffffffff12345678, 0 );
+  TEST_IMM_OP( 45, srliw, 0x0000000001234567, 0xffffffff12345678, 4 );
+  TEST_IMM_OP( 46, srliw, 0xffffffff92345678, 0x0000000092345678, 0 );
+  TEST_IMM_OP( 47, srliw, 0x0000000009234567, 0x0000000092345678, 4 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_SRC1_EQ_DEST( 17, srliw, 0x0000000001000000, 0xffffffff80000000, 7 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_DEST_BYPASS( 18, 0, srliw, 0x0000000001000000, 0xffffffff80000000, 7  );
+  TEST_IMM_DEST_BYPASS( 19, 1, srliw, 0x0000000000020000, 0xffffffff80000000, 14 );
+  TEST_IMM_DEST_BYPASS( 20, 2, srliw, 0x0000000000000001, 0xffffffff80000001, 31 );
+
+  TEST_IMM_SRC1_BYPASS( 21, 0, srliw, 0x0000000001000000, 0xffffffff80000000, 7  );
+  TEST_IMM_SRC1_BYPASS( 22, 1, srliw, 0x0000000000020000, 0xffffffff80000000, 14 );
+  TEST_IMM_SRC1_BYPASS( 23, 2, srliw, 0x0000000000000001, 0xffffffff80000001, 31 );
+
+  TEST_IMM_ZEROSRC1( 24, srliw, 0, 31 );
+  TEST_IMM_ZERODEST( 25, srliw, 31, 28 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/srlw.S b/apps/riscv-tests/isa/rv64ui/srlw.S
new file mode 100644
index 0000000..f0d1dae
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/srlw.S
@@ -0,0 +1,97 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# srlw.S
+#-----------------------------------------------------------------------------
+#
+# Test srlw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  srlw, 0xffffffff80000000, 0xffffffff80000000, 0  );
+  TEST_RR_OP( 3,  srlw, 0x0000000040000000, 0xffffffff80000000, 1  );
+  TEST_RR_OP( 4,  srlw, 0x0000000001000000, 0xffffffff80000000, 7  );
+  TEST_RR_OP( 5,  srlw, 0x0000000000020000, 0xffffffff80000000, 14 );
+  TEST_RR_OP( 6,  srlw, 0x0000000000000001, 0xffffffff80000001, 31 );
+
+  TEST_RR_OP( 7,  srlw, 0xffffffffffffffff, 0xffffffffffffffff, 0  );
+  TEST_RR_OP( 8,  srlw, 0x000000007fffffff, 0xffffffffffffffff, 1  );
+  TEST_RR_OP( 9,  srlw, 0x0000000001ffffff, 0xffffffffffffffff, 7  );
+  TEST_RR_OP( 10, srlw, 0x000000000003ffff, 0xffffffffffffffff, 14 );
+  TEST_RR_OP( 11, srlw, 0x0000000000000001, 0xffffffffffffffff, 31 );
+
+  TEST_RR_OP( 12, srlw, 0x0000000021212121, 0x0000000021212121, 0  );
+  TEST_RR_OP( 13, srlw, 0x0000000010909090, 0x0000000021212121, 1  );
+  TEST_RR_OP( 14, srlw, 0x0000000000424242, 0x0000000021212121, 7  );
+  TEST_RR_OP( 15, srlw, 0x0000000000008484, 0x0000000021212121, 14 );
+  TEST_RR_OP( 16, srlw, 0x0000000000000000, 0x0000000021212121, 31 );
+
+  # Verify that shifts only use bottom five bits
+
+  TEST_RR_OP( 17, srlw, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffe0 );
+  TEST_RR_OP( 18, srlw, 0x0000000010909090, 0x0000000021212121, 0xffffffffffffffe1 );
+  TEST_RR_OP( 19, srlw, 0x0000000000424242, 0x0000000021212121, 0xffffffffffffffe7 );
+  TEST_RR_OP( 20, srlw, 0x0000000000008484, 0x0000000021212121, 0xffffffffffffffee );
+  TEST_RR_OP( 21, srlw, 0x0000000000000000, 0x0000000021212121, 0xffffffffffffffff );
+
+  # Verify that shifts ignore top 32 (using true 64-bit values)
+
+  TEST_RR_OP( 44, srlw, 0x0000000012345678, 0xffffffff12345678, 0 );
+  TEST_RR_OP( 45, srlw, 0x0000000001234567, 0xffffffff12345678, 4 );
+  TEST_RR_OP( 46, srlw, 0xffffffff92345678, 0x0000000092345678, 0 );
+  TEST_RR_OP( 47, srlw, 0x0000000009234567, 0x0000000092345678, 4 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 22, srlw, 0x0000000001000000, 0xffffffff80000000, 7  );
+  TEST_RR_SRC2_EQ_DEST( 23, srlw, 0x0000000000020000, 0xffffffff80000000, 14 );
+  TEST_RR_SRC12_EQ_DEST( 24, srlw, 0, 7 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 25, 0, srlw, 0x0000000001000000, 0xffffffff80000000, 7  );
+  TEST_RR_DEST_BYPASS( 26, 1, srlw, 0x0000000000020000, 0xffffffff80000000, 14 );
+  TEST_RR_DEST_BYPASS( 27, 2, srlw, 0x0000000000000001, 0xffffffff80000000, 31 );
+
+  TEST_RR_SRC12_BYPASS( 28, 0, 0, srlw, 0x0000000001000000, 0xffffffff80000000, 7  );
+  TEST_RR_SRC12_BYPASS( 29, 0, 1, srlw, 0x0000000000020000, 0xffffffff80000000, 14 );
+  TEST_RR_SRC12_BYPASS( 30, 0, 2, srlw, 0x0000000000000001, 0xffffffff80000000, 31 );
+  TEST_RR_SRC12_BYPASS( 31, 1, 0, srlw, 0x0000000001000000, 0xffffffff80000000, 7  );
+  TEST_RR_SRC12_BYPASS( 32, 1, 1, srlw, 0x0000000000020000, 0xffffffff80000000, 14 );
+  TEST_RR_SRC12_BYPASS( 33, 2, 0, srlw, 0x0000000000000001, 0xffffffff80000000, 31 );
+
+  TEST_RR_SRC21_BYPASS( 34, 0, 0, srlw, 0x0000000001000000, 0xffffffff80000000, 7  );
+  TEST_RR_SRC21_BYPASS( 35, 0, 1, srlw, 0x0000000000020000, 0xffffffff80000000, 14 );
+  TEST_RR_SRC21_BYPASS( 36, 0, 2, srlw, 0x0000000000000001, 0xffffffff80000000, 31 );
+  TEST_RR_SRC21_BYPASS( 37, 1, 0, srlw, 0x0000000001000000, 0xffffffff80000000, 7  );
+  TEST_RR_SRC21_BYPASS( 38, 1, 1, srlw, 0x0000000000020000, 0xffffffff80000000, 14 );
+  TEST_RR_SRC21_BYPASS( 39, 2, 0, srlw, 0x0000000000000001, 0xffffffff80000000, 31 );
+
+  TEST_RR_ZEROSRC1( 40, srlw, 0, 15 );
+  TEST_RR_ZEROSRC2( 41, srlw, 32, 32 );
+  TEST_RR_ZEROSRC12( 42, srlw, 0 );
+  TEST_RR_ZERODEST( 43, srlw, 1024, 2048 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/sub.S b/apps/riscv-tests/isa/rv64ui/sub.S
new file mode 100644
index 0000000..005bdea
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/sub.S
@@ -0,0 +1,83 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sub.S
+#-----------------------------------------------------------------------------
+#
+# Test sub instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  sub, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000 );
+  TEST_RR_OP( 3,  sub, 0x0000000000000000, 0x0000000000000001, 0x0000000000000001 );
+  TEST_RR_OP( 4,  sub, 0xfffffffffffffffc, 0x0000000000000003, 0x0000000000000007 );
+
+  TEST_RR_OP( 5,  sub, 0x0000000000008000, 0x0000000000000000, 0xffffffffffff8000 );
+  TEST_RR_OP( 6,  sub, 0xffffffff80000000, 0xffffffff80000000, 0x0000000000000000 );
+  TEST_RR_OP( 7,  sub, 0xffffffff80008000, 0xffffffff80000000, 0xffffffffffff8000 );
+
+  TEST_RR_OP( 8,  sub, 0xffffffffffff8001, 0x0000000000000000, 0x0000000000007fff );
+  TEST_RR_OP( 9,  sub, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 );
+  TEST_RR_OP( 10, sub, 0x000000007fff8000, 0x000000007fffffff, 0x0000000000007fff );
+
+  TEST_RR_OP( 11, sub, 0xffffffff7fff8001, 0xffffffff80000000, 0x0000000000007fff );
+  TEST_RR_OP( 12, sub, 0x0000000080007fff, 0x000000007fffffff, 0xffffffffffff8000 );
+
+  TEST_RR_OP( 13, sub, 0x0000000000000001, 0x0000000000000000, 0xffffffffffffffff );
+  TEST_RR_OP( 14, sub, 0xfffffffffffffffe, 0xffffffffffffffff, 0x0000000000000001 );
+  TEST_RR_OP( 15, sub, 0x0000000000000000, 0xffffffffffffffff, 0xffffffffffffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 16, sub, 2, 13, 11 );
+  TEST_RR_SRC2_EQ_DEST( 17, sub, 3, 14, 11 );
+  TEST_RR_SRC12_EQ_DEST( 18, sub, 0, 13 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 19, 0, sub, 2, 13, 11 );
+  TEST_RR_DEST_BYPASS( 20, 1, sub, 3, 14, 11 );
+  TEST_RR_DEST_BYPASS( 21, 2, sub, 4, 15, 11 );
+
+  TEST_RR_SRC12_BYPASS( 22, 0, 0, sub, 2, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 23, 0, 1, sub, 3, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 24, 0, 2, sub, 4, 15, 11 );
+  TEST_RR_SRC12_BYPASS( 25, 1, 0, sub, 2, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 26, 1, 1, sub, 3, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 27, 2, 0, sub, 4, 15, 11 );
+
+  TEST_RR_SRC21_BYPASS( 28, 0, 0, sub, 2, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 29, 0, 1, sub, 3, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 30, 0, 2, sub, 4, 15, 11 );
+  TEST_RR_SRC21_BYPASS( 31, 1, 0, sub, 2, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 32, 1, 1, sub, 3, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 33, 2, 0, sub, 4, 15, 11 );
+
+  TEST_RR_ZEROSRC1( 34, sub, 15, -15 );
+  TEST_RR_ZEROSRC2( 35, sub, 32, 32 );
+  TEST_RR_ZEROSRC12( 36, sub, 0 );
+  TEST_RR_ZERODEST( 37, sub, 16, 30 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/subw.S b/apps/riscv-tests/isa/rv64ui/subw.S
new file mode 100644
index 0000000..9940d8c
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/subw.S
@@ -0,0 +1,83 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# subw.S
+#-----------------------------------------------------------------------------
+#
+# Test subw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  subw, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000 );
+  TEST_RR_OP( 3,  subw, 0x0000000000000000, 0x0000000000000001, 0x0000000000000001 );
+  TEST_RR_OP( 4,  subw, 0xfffffffffffffffc, 0x0000000000000003, 0x0000000000000007 );
+
+  TEST_RR_OP( 5,  subw, 0x0000000000008000, 0x0000000000000000, 0xffffffffffff8000 );
+  TEST_RR_OP( 6,  subw, 0xffffffff80000000, 0xffffffff80000000, 0x0000000000000000 );
+  TEST_RR_OP( 7,  subw, 0xffffffff80008000, 0xffffffff80000000, 0xffffffffffff8000 );
+
+  TEST_RR_OP( 8,  subw, 0xffffffffffff8001, 0x0000000000000000, 0x0000000000007fff );
+  TEST_RR_OP( 9,  subw, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 );
+  TEST_RR_OP( 10, subw, 0x000000007fff8000, 0x000000007fffffff, 0x0000000000007fff );
+
+  TEST_RR_OP( 11, subw, 0x000000007fff8001, 0xffffffff80000000, 0x0000000000007fff );
+  TEST_RR_OP( 12, subw, 0xffffffff80007fff, 0x000000007fffffff, 0xffffffffffff8000 );
+
+  TEST_RR_OP( 13, subw, 0x0000000000000001, 0x0000000000000000, 0xffffffffffffffff );
+  TEST_RR_OP( 14, subw, 0xfffffffffffffffe, 0xffffffffffffffff, 0x0000000000000001 );
+  TEST_RR_OP( 15, subw, 0x0000000000000000, 0xffffffffffffffff, 0xffffffffffffffff );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 16, subw, 2, 13, 11 );
+  TEST_RR_SRC2_EQ_DEST( 17, subw, 3, 14, 11 );
+  TEST_RR_SRC12_EQ_DEST( 18, subw, 0, 13 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 19, 0, subw, 2, 13, 11 );
+  TEST_RR_DEST_BYPASS( 20, 1, subw, 3, 14, 11 );
+  TEST_RR_DEST_BYPASS( 21, 2, subw, 4, 15, 11 );
+
+  TEST_RR_SRC12_BYPASS( 22, 0, 0, subw, 2, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 23, 0, 1, subw, 3, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 24, 0, 2, subw, 4, 15, 11 );
+  TEST_RR_SRC12_BYPASS( 25, 1, 0, subw, 2, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 26, 1, 1, subw, 3, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 27, 2, 0, subw, 4, 15, 11 );
+
+  TEST_RR_SRC21_BYPASS( 28, 0, 0, subw, 2, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 29, 0, 1, subw, 3, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 30, 0, 2, subw, 4, 15, 11 );
+  TEST_RR_SRC21_BYPASS( 31, 1, 0, subw, 2, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 32, 1, 1, subw, 3, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 33, 2, 0, subw, 4, 15, 11 );
+
+  TEST_RR_ZEROSRC1( 34, subw, 15, -15 );
+  TEST_RR_ZEROSRC2( 35, subw, 32, 32 );
+  TEST_RR_ZEROSRC12( 36, subw, 0 );
+  TEST_RR_ZERODEST( 37, subw, 16, 30 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/sw.S b/apps/riscv-tests/isa/rv64ui/sw.S
new file mode 100644
index 0000000..ab094b3
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/sw.S
@@ -0,0 +1,92 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# sw.S
+#-----------------------------------------------------------------------------
+#
+# Test sw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Basic tests
+  #-------------------------------------------------------------
+
+  TEST_ST_OP( 2, lw, sw, 0x0000000000aa00aa, 0,  tdat );
+  TEST_ST_OP( 3, lw, sw, 0xffffffffaa00aa00, 4,  tdat );
+  TEST_ST_OP( 4, lw, sw, 0x000000000aa00aa0, 8,  tdat );
+  TEST_ST_OP( 5, lw, sw, 0xffffffffa00aa00a, 12, tdat );
+
+  # Test with negative offset
+
+  TEST_ST_OP( 6, lw, sw, 0x0000000000aa00aa, -12, tdat8 );
+  TEST_ST_OP( 7, lw, sw, 0xffffffffaa00aa00, -8,  tdat8 );
+  TEST_ST_OP( 8, lw, sw, 0x000000000aa00aa0, -4,  tdat8 );
+  TEST_ST_OP( 9, lw, sw, 0xffffffffa00aa00a, 0,   tdat8 );
+
+  # Test with a negative base
+
+  TEST_CASE( 10, x5, 0x12345678, \
+    la  x1, tdat9; \
+    li  x2, 0x12345678; \
+    addi x4, x1, -32; \
+    sw x2, 32(x4); \
+    lw x5, 0(x1); \
+  )
+
+  # Test with unaligned base
+
+  TEST_CASE( 11, x5, 0x58213098, \
+    la  x1, tdat9; \
+    li  x2, 0x58213098; \
+    addi x1, x1, -3; \
+    sw x2, 7(x1); \
+    la  x4, tdat10; \
+    lw x5, 0(x4); \
+  )
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_ST_SRC12_BYPASS( 12, 0, 0, lw, sw, 0xffffffffaabbccdd, 0,  tdat );
+  TEST_ST_SRC12_BYPASS( 13, 0, 1, lw, sw, 0xffffffffdaabbccd, 4,  tdat );
+  TEST_ST_SRC12_BYPASS( 14, 0, 2, lw, sw, 0xffffffffddaabbcc, 8,  tdat );
+  TEST_ST_SRC12_BYPASS( 15, 1, 0, lw, sw, 0xffffffffcddaabbc, 12, tdat );
+  TEST_ST_SRC12_BYPASS( 16, 1, 1, lw, sw, 0xffffffffccddaabb, 16, tdat );
+  TEST_ST_SRC12_BYPASS( 17, 2, 0, lw, sw, 0xffffffffbccddaab, 20, tdat );
+
+  TEST_ST_SRC21_BYPASS( 18, 0, 0, lw, sw, 0x00112233, 0,  tdat );
+  TEST_ST_SRC21_BYPASS( 19, 0, 1, lw, sw, 0x30011223, 4,  tdat );
+  TEST_ST_SRC21_BYPASS( 20, 0, 2, lw, sw, 0x33001122, 8,  tdat );
+  TEST_ST_SRC21_BYPASS( 21, 1, 0, lw, sw, 0x23300112, 12, tdat );
+  TEST_ST_SRC21_BYPASS( 22, 1, 1, lw, sw, 0x22330011, 16, tdat );
+  TEST_ST_SRC21_BYPASS( 23, 2, 0, lw, sw, 0x12233001, 20, tdat );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+tdat:
+tdat1:  .word 0xdeadbeef
+tdat2:  .word 0xdeadbeef
+tdat3:  .word 0xdeadbeef
+tdat4:  .word 0xdeadbeef
+tdat5:  .word 0xdeadbeef
+tdat6:  .word 0xdeadbeef
+tdat7:  .word 0xdeadbeef
+tdat8:  .word 0xdeadbeef
+tdat9:  .word 0xdeadbeef
+tdat10: .word 0xdeadbeef
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/xor.S b/apps/riscv-tests/isa/rv64ui/xor.S
new file mode 100644
index 0000000..c4e9552
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/xor.S
@@ -0,0 +1,69 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# xor.S
+#-----------------------------------------------------------------------------
+#
+# Test xor instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Logical tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_OP( 3, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_OP( 4, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f );
+  TEST_RR_OP( 5, xor, 0x00ff00ff, 0xf00ff00f, 0xf0f0f0f0 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 6, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC2_EQ_DEST( 7, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC12_EQ_DEST( 8, xor, 0x00000000, 0xff00ff00 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 9,  0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_DEST_BYPASS( 10, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_DEST_BYPASS( 11, 2, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f );
+
+  TEST_RR_SRC12_BYPASS( 12, 0, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC12_BYPASS( 13, 0, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_SRC12_BYPASS( 14, 0, 2, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f );
+  TEST_RR_SRC12_BYPASS( 15, 1, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC12_BYPASS( 16, 1, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_SRC12_BYPASS( 17, 2, 0, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f );
+
+  TEST_RR_SRC21_BYPASS( 18, 0, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC21_BYPASS( 19, 0, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_SRC21_BYPASS( 20, 0, 2, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f );
+  TEST_RR_SRC21_BYPASS( 21, 1, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f );
+  TEST_RR_SRC21_BYPASS( 22, 1, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 );
+  TEST_RR_SRC21_BYPASS( 23, 2, 0, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f );
+
+  TEST_RR_ZEROSRC1( 24, xor, 0xff00ff00, 0xff00ff00 );
+  TEST_RR_ZEROSRC2( 25, xor, 0x00ff00ff, 0x00ff00ff );
+  TEST_RR_ZEROSRC12( 26, xor, 0 );
+  TEST_RR_ZERODEST( 27, xor, 0x11111111, 0x22222222 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64ui/xori.S b/apps/riscv-tests/isa/rv64ui/xori.S
new file mode 100644
index 0000000..eb59d12
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64ui/xori.S
@@ -0,0 +1,55 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# xori.S
+#-----------------------------------------------------------------------------
+#
+# Test xori instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Logical tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_OP( 2, xori, 0xffffffffff00f00f, 0x0000000000ff0f00, 0xf0f );
+  TEST_IMM_OP( 3, xori, 0x000000000ff00f00, 0x000000000ff00ff0, 0x0f0 );
+  TEST_IMM_OP( 4, xori, 0x0000000000ff0ff0, 0x0000000000ff08ff, 0x70f );
+  TEST_IMM_OP( 5, xori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_SRC1_EQ_DEST( 6, xori, 0xffffffffff00f00f, 0xffffffffff00f700, 0x70f );
+
+   #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_IMM_DEST_BYPASS( 7,  0, xori, 0x000000000ff00f00, 0x000000000ff00ff0, 0x0f0 );
+  TEST_IMM_DEST_BYPASS( 8,  1, xori, 0x0000000000ff0ff0, 0x0000000000ff08ff, 0x70f );
+  TEST_IMM_DEST_BYPASS( 9,  2, xori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 );
+
+  TEST_IMM_SRC1_BYPASS( 10, 0, xori, 0x000000000ff00f00, 0x000000000ff00ff0, 0x0f0 );
+  TEST_IMM_SRC1_BYPASS( 11, 1, xori, 0x0000000000ff0ff0, 0x0000000000ff0fff, 0x00f );
+  TEST_IMM_SRC1_BYPASS( 12, 2, xori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 );
+
+  TEST_IMM_ZEROSRC1( 13, xori, 0x0f0, 0x0f0 );
+  TEST_IMM_ZERODEST( 14, xori, 0x00ff00ff, 0x70f );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64um/Makefrag b/apps/riscv-tests/isa/rv64um/Makefrag
new file mode 100644
index 0000000..360bd7a
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64um/Makefrag
@@ -0,0 +1,13 @@
+#=======================================================================
+# Makefrag for rv64um tests
+#-----------------------------------------------------------------------
+
+rv64um_sc_tests = \
+	div divu divuw divw \
+	mul mulh mulhsu mulhu mulw \
+	rem remu remuw remw \
+
+rv64um_p_tests = $(addprefix rv64um-p-, $(rv64um_sc_tests))
+rv64um_v_tests = $(addprefix rv64um-v-, $(rv64um_sc_tests))
+
+spike_tests += $(rv64um_p_tests) $(rv64um_v_tests)
diff --git a/apps/riscv-tests/isa/rv64um/div.S b/apps/riscv-tests/isa/rv64um/div.S
new file mode 100644
index 0000000..ee21f0c
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64um/div.S
@@ -0,0 +1,41 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# div.S
+#-----------------------------------------------------------------------------
+#
+# Test div instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2, div,  3,  20,   6 );
+  TEST_RR_OP( 3, div, -3, -20,   6 );
+  TEST_RR_OP( 4, div, -3,  20,  -6 );
+  TEST_RR_OP( 5, div,  3, -20,  -6 );
+
+  TEST_RR_OP( 6, div, -1<<63, -1<<63,  1 );
+  TEST_RR_OP( 7, div, -1<<63, -1<<63, -1 );
+
+  TEST_RR_OP( 8, div, -1, -1<<63, 0 );
+  TEST_RR_OP( 9, div, -1,      1, 0 );
+  TEST_RR_OP(10, div, -1,      0, 0 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64um/divu.S b/apps/riscv-tests/isa/rv64um/divu.S
new file mode 100644
index 0000000..e63fd65
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64um/divu.S
@@ -0,0 +1,41 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# divu.S
+#-----------------------------------------------------------------------------
+#
+# Test divu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2, divu,                   3,  20,   6 );
+  TEST_RR_OP( 3, divu, 3074457345618258599, -20,   6 );
+  TEST_RR_OP( 4, divu,                   0,  20,  -6 );
+  TEST_RR_OP( 5, divu,                   0, -20,  -6 );
+
+  TEST_RR_OP( 6, divu, -1<<63, -1<<63,  1 );
+  TEST_RR_OP( 7, divu,     0,  -1<<63, -1 );
+
+  TEST_RR_OP( 8, divu, -1, -1<<63, 0 );
+  TEST_RR_OP( 9, divu, -1,      1, 0 );
+  TEST_RR_OP(10, divu, -1,      0, 0 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64um/divuw.S b/apps/riscv-tests/isa/rv64um/divuw.S
new file mode 100644
index 0000000..4c9eee7
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64um/divuw.S
@@ -0,0 +1,41 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# divuw.S
+#-----------------------------------------------------------------------------
+#
+# Test divuw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2, divuw,         3,  20,   6 );
+  TEST_RR_OP( 3, divuw, 715827879, -20 << 32 >> 32,   6 );
+  TEST_RR_OP( 4, divuw,         0,  20,  -6 );
+  TEST_RR_OP( 5, divuw,         0, -20,  -6 );
+
+  TEST_RR_OP( 6, divuw, -1<<31, -1<<31,  1 );
+  TEST_RR_OP( 7, divuw, 0,      -1<<31, -1 );
+
+  TEST_RR_OP( 8, divuw, -1, -1<<31, 0 );
+  TEST_RR_OP( 9, divuw, -1,      1, 0 );
+  TEST_RR_OP(10, divuw, -1,      0, 0 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64um/divw.S b/apps/riscv-tests/isa/rv64um/divw.S
new file mode 100644
index 0000000..4cffa1a
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64um/divw.S
@@ -0,0 +1,41 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# divw.S
+#-----------------------------------------------------------------------------
+#
+# Test divw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2, divw,  3,  20,   6 );
+  TEST_RR_OP( 3, divw, -3, -20,   6 );
+  TEST_RR_OP( 4, divw, -3,  20,  -6 );
+  TEST_RR_OP( 5, divw,  3, -20,  -6 );
+
+  TEST_RR_OP( 6, divw, -1<<31, -1<<31,  1 );
+  TEST_RR_OP( 7, divw, -1<<31, -1<<31, -1 );
+
+  TEST_RR_OP( 8, divw, -1, -1<<31, 0 );
+  TEST_RR_OP( 9, divw, -1,      1, 0 );
+  TEST_RR_OP(10, divw, -1,      0, 0 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64um/mul.S b/apps/riscv-tests/isa/rv64um/mul.S
new file mode 100644
index 0000000..c647e97
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64um/mul.S
@@ -0,0 +1,78 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# mul.S
+#-----------------------------------------------------------------------------
+#
+# Test mul instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP(32,  mul, 0x0000000000001200, 0x0000000000007e00, 0x6db6db6db6db6db7 );
+  TEST_RR_OP(33,  mul, 0x0000000000001240, 0x0000000000007fc0, 0x6db6db6db6db6db7 );
+
+  TEST_RR_OP( 2,  mul, 0x00000000, 0x00000000, 0x00000000 );
+  TEST_RR_OP( 3,  mul, 0x00000001, 0x00000001, 0x00000001 );
+  TEST_RR_OP( 4,  mul, 0x00000015, 0x00000003, 0x00000007 );
+
+  TEST_RR_OP( 5,  mul, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 );
+  TEST_RR_OP( 6,  mul, 0x0000000000000000, 0xffffffff80000000, 0x00000000 );
+  TEST_RR_OP( 7,  mul, 0x0000400000000000, 0xffffffff80000000, 0xffffffffffff8000 );
+
+  TEST_RR_OP(30,  mul, 0x000000000000ff7f, 0xaaaaaaaaaaaaaaab, 0x000000000002fe7d );
+  TEST_RR_OP(31,  mul, 0x000000000000ff7f, 0x000000000002fe7d, 0xaaaaaaaaaaaaaaab );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 8, mul, 143, 13, 11 );
+  TEST_RR_SRC2_EQ_DEST( 9, mul, 154, 14, 11 );
+  TEST_RR_SRC12_EQ_DEST( 10, mul, 169, 13 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 11, 0, mul, 143, 13, 11 );
+  TEST_RR_DEST_BYPASS( 12, 1, mul, 154, 14, 11 );
+  TEST_RR_DEST_BYPASS( 13, 2, mul, 165, 15, 11 );
+
+  TEST_RR_SRC12_BYPASS( 14, 0, 0, mul, 143, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 15, 0, 1, mul, 154, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 16, 0, 2, mul, 165, 15, 11 );
+  TEST_RR_SRC12_BYPASS( 17, 1, 0, mul, 143, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 18, 1, 1, mul, 154, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 19, 2, 0, mul, 165, 15, 11 );
+
+  TEST_RR_SRC21_BYPASS( 20, 0, 0, mul, 143, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 21, 0, 1, mul, 154, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 22, 0, 2, mul, 165, 15, 11 );
+  TEST_RR_SRC21_BYPASS( 23, 1, 0, mul, 143, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 24, 1, 1, mul, 154, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 25, 2, 0, mul, 165, 15, 11 );
+
+  TEST_RR_ZEROSRC1( 26, mul, 0, 31 );
+  TEST_RR_ZEROSRC2( 27, mul, 0, 32 );
+  TEST_RR_ZEROSRC12( 28, mul, 0 );
+  TEST_RR_ZERODEST( 29, mul, 33, 34 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64um/mulh.S b/apps/riscv-tests/isa/rv64um/mulh.S
new file mode 100644
index 0000000..1fd12a1
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64um/mulh.S
@@ -0,0 +1,72 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# mulh.S
+#-----------------------------------------------------------------------------
+#
+# Test mulh instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  mulh, 0x00000000, 0x00000000, 0x00000000 );
+  TEST_RR_OP( 3,  mulh, 0x00000000, 0x00000001, 0x00000001 );
+  TEST_RR_OP( 4,  mulh, 0x00000000, 0x00000003, 0x00000007 );
+
+  TEST_RR_OP( 5,  mulh, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 );
+  TEST_RR_OP( 6,  mulh, 0x0000000000000000, 0xffffffff80000000, 0x00000000 );
+  TEST_RR_OP( 7,  mulh, 0x0000000000000000, 0xffffffff80000000, 0xffffffffffff8000 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 8, mulh, 143, 13<<32, 11<<32 );
+  TEST_RR_SRC2_EQ_DEST( 9, mulh, 154, 14<<32, 11<<32 );
+  TEST_RR_SRC12_EQ_DEST( 10, mulh, 169, 13<<32 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 11, 0, mulh, 143, 13<<32, 11<<32 );
+  TEST_RR_DEST_BYPASS( 12, 1, mulh, 154, 14<<32, 11<<32 );
+  TEST_RR_DEST_BYPASS( 13, 2, mulh, 165, 15<<32, 11<<32 );
+
+  TEST_RR_SRC12_BYPASS( 14, 0, 0, mulh, 143, 13<<32, 11<<32 );
+  TEST_RR_SRC12_BYPASS( 15, 0, 1, mulh, 154, 14<<32, 11<<32 );
+  TEST_RR_SRC12_BYPASS( 16, 0, 2, mulh, 165, 15<<32, 11<<32 );
+  TEST_RR_SRC12_BYPASS( 17, 1, 0, mulh, 143, 13<<32, 11<<32 );
+  TEST_RR_SRC12_BYPASS( 18, 1, 1, mulh, 154, 14<<32, 11<<32 );
+  TEST_RR_SRC12_BYPASS( 19, 2, 0, mulh, 165, 15<<32, 11<<32 );
+
+  TEST_RR_SRC21_BYPASS( 20, 0, 0, mulh, 143, 13<<32, 11<<32 );
+  TEST_RR_SRC21_BYPASS( 21, 0, 1, mulh, 154, 14<<32, 11<<32 );
+  TEST_RR_SRC21_BYPASS( 22, 0, 2, mulh, 165, 15<<32, 11<<32 );
+  TEST_RR_SRC21_BYPASS( 23, 1, 0, mulh, 143, 13<<32, 11<<32 );
+  TEST_RR_SRC21_BYPASS( 24, 1, 1, mulh, 154, 14<<32, 11<<32 );
+  TEST_RR_SRC21_BYPASS( 25, 2, 0, mulh, 165, 15<<32, 11<<32 );
+
+  TEST_RR_ZEROSRC1( 26, mulh, 0, 31<<32 );
+  TEST_RR_ZEROSRC2( 27, mulh, 0, 32<<32 );
+  TEST_RR_ZEROSRC12( 28, mulh, 0 );
+  TEST_RR_ZERODEST( 29, mulh, 33<<32, 34<<32 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64um/mulhsu.S b/apps/riscv-tests/isa/rv64um/mulhsu.S
new file mode 100644
index 0000000..c037db2
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64um/mulhsu.S
@@ -0,0 +1,72 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# mulhsu.S
+#-----------------------------------------------------------------------------
+#
+# Test mulhsu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  mulhsu, 0x00000000, 0x00000000, 0x00000000 );
+  TEST_RR_OP( 3,  mulhsu, 0x00000000, 0x00000001, 0x00000001 );
+  TEST_RR_OP( 4,  mulhsu, 0x00000000, 0x00000003, 0x00000007 );
+
+  TEST_RR_OP( 5,  mulhsu, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 );
+  TEST_RR_OP( 6,  mulhsu, 0x0000000000000000, 0xffffffff80000000, 0x00000000 );
+  TEST_RR_OP( 7,  mulhsu, 0xffffffff80000000, 0xffffffff80000000, 0xffffffffffff8000 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 8, mulhsu, 143, 13<<32, 11<<32 );
+  TEST_RR_SRC2_EQ_DEST( 9, mulhsu, 154, 14<<32, 11<<32 );
+  TEST_RR_SRC12_EQ_DEST( 10, mulhsu, 169, 13<<32 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 11, 0, mulhsu, 143, 13<<32, 11<<32 );
+  TEST_RR_DEST_BYPASS( 12, 1, mulhsu, 154, 14<<32, 11<<32 );
+  TEST_RR_DEST_BYPASS( 13, 2, mulhsu, 165, 15<<32, 11<<32 );
+
+  TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhsu, 143, 13<<32, 11<<32 );
+  TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhsu, 154, 14<<32, 11<<32 );
+  TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhsu, 165, 15<<32, 11<<32 );
+  TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhsu, 143, 13<<32, 11<<32 );
+  TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhsu, 154, 14<<32, 11<<32 );
+  TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhsu, 165, 15<<32, 11<<32 );
+
+  TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhsu, 143, 13<<32, 11<<32 );
+  TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhsu, 154, 14<<32, 11<<32 );
+  TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhsu, 165, 15<<32, 11<<32 );
+  TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhsu, 143, 13<<32, 11<<32 );
+  TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhsu, 154, 14<<32, 11<<32 );
+  TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhsu, 165, 15<<32, 11<<32 );
+
+  TEST_RR_ZEROSRC1( 26, mulhsu, 0, 31<<32 );
+  TEST_RR_ZEROSRC2( 27, mulhsu, 0, 32<<32 );
+  TEST_RR_ZEROSRC12( 28, mulhsu, 0 );
+  TEST_RR_ZERODEST( 29, mulhsu, 33<<32, 34<<32 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64um/mulhu.S b/apps/riscv-tests/isa/rv64um/mulhu.S
new file mode 100644
index 0000000..aa7b762
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64um/mulhu.S
@@ -0,0 +1,75 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# mulhu.S
+#-----------------------------------------------------------------------------
+#
+# Test mulhu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  mulhu, 0x00000000, 0x00000000, 0x00000000 );
+  TEST_RR_OP( 3,  mulhu, 0x00000000, 0x00000001, 0x00000001 );
+  TEST_RR_OP( 4,  mulhu, 0x00000000, 0x00000003, 0x00000007 );
+
+  TEST_RR_OP( 5,  mulhu, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 );
+  TEST_RR_OP( 6,  mulhu, 0x0000000000000000, 0xffffffff80000000, 0x00000000 );
+  TEST_RR_OP( 7,  mulhu, 0xffffffff7fff8000, 0xffffffff80000000, 0xffffffffffff8000 );
+
+  TEST_RR_OP(30,  mulhu, 0x000000000001fefe, 0xaaaaaaaaaaaaaaab, 0x000000000002fe7d );
+  TEST_RR_OP(31,  mulhu, 0x000000000001fefe, 0x000000000002fe7d, 0xaaaaaaaaaaaaaaab );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 8, mulhu, 143, 13<<32, 11<<32 );
+  TEST_RR_SRC2_EQ_DEST( 9, mulhu, 154, 14<<32, 11<<32 );
+  TEST_RR_SRC12_EQ_DEST( 10, mulhu, 169, 13<<32 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 11, 0, mulhu, 143, 13<<32, 11<<32 );
+  TEST_RR_DEST_BYPASS( 12, 1, mulhu, 154, 14<<32, 11<<32 );
+  TEST_RR_DEST_BYPASS( 13, 2, mulhu, 165, 15<<32, 11<<32 );
+
+  TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhu, 143, 13<<32, 11<<32 );
+  TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhu, 154, 14<<32, 11<<32 );
+  TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhu, 165, 15<<32, 11<<32 );
+  TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhu, 143, 13<<32, 11<<32 );
+  TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhu, 154, 14<<32, 11<<32 );
+  TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhu, 165, 15<<32, 11<<32 );
+
+  TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhu, 143, 13<<32, 11<<32 );
+  TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhu, 154, 14<<32, 11<<32 );
+  TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhu, 165, 15<<32, 11<<32 );
+  TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhu, 143, 13<<32, 11<<32 );
+  TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhu, 154, 14<<32, 11<<32 );
+  TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhu, 165, 15<<32, 11<<32 );
+
+  TEST_RR_ZEROSRC1( 26, mulhu, 0, 31<<32 );
+  TEST_RR_ZEROSRC2( 27, mulhu, 0, 32<<32 );
+  TEST_RR_ZEROSRC12( 28, mulhu, 0 );
+  TEST_RR_ZERODEST( 29, mulhu, 33<<32, 34<<32 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64um/mulw.S b/apps/riscv-tests/isa/rv64um/mulw.S
new file mode 100644
index 0000000..379c3f2
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64um/mulw.S
@@ -0,0 +1,72 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# mulw.S
+#-----------------------------------------------------------------------------
+#
+# Test mulw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  mulw, 0x00000000, 0x00000000, 0x00000000 );
+  TEST_RR_OP( 3,  mulw, 0x00000001, 0x00000001, 0x00000001 );
+  TEST_RR_OP( 4,  mulw, 0x00000015, 0x00000003, 0x00000007 );
+
+  TEST_RR_OP( 5,  mulw, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 );
+  TEST_RR_OP( 6,  mulw, 0x0000000000000000, 0xffffffff80000000, 0x00000000 );
+  TEST_RR_OP( 7,  mulw, 0x0000000000000000, 0xffffffff80000000, 0xffffffffffff8000 );
+
+  #-------------------------------------------------------------
+  # Source/Destination tests
+  #-------------------------------------------------------------
+
+  TEST_RR_SRC1_EQ_DEST( 8, mulw, 143, 13, 11 );
+  TEST_RR_SRC2_EQ_DEST( 9, mulw, 154, 14, 11 );
+  TEST_RR_SRC12_EQ_DEST( 10, mulw, 169, 13 );
+
+  #-------------------------------------------------------------
+  # Bypassing tests
+  #-------------------------------------------------------------
+
+  TEST_RR_DEST_BYPASS( 11, 0, mulw, 143, 13, 11 );
+  TEST_RR_DEST_BYPASS( 12, 1, mulw, 154, 14, 11 );
+  TEST_RR_DEST_BYPASS( 13, 2, mulw, 165, 15, 11 );
+
+  TEST_RR_SRC12_BYPASS( 14, 0, 0, mulw, 143, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 15, 0, 1, mulw, 154, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 16, 0, 2, mulw, 165, 15, 11 );
+  TEST_RR_SRC12_BYPASS( 17, 1, 0, mulw, 143, 13, 11 );
+  TEST_RR_SRC12_BYPASS( 18, 1, 1, mulw, 154, 14, 11 );
+  TEST_RR_SRC12_BYPASS( 19, 2, 0, mulw, 165, 15, 11 );
+
+  TEST_RR_SRC21_BYPASS( 20, 0, 0, mulw, 143, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 21, 0, 1, mulw, 154, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 22, 0, 2, mulw, 165, 15, 11 );
+  TEST_RR_SRC21_BYPASS( 23, 1, 0, mulw, 143, 13, 11 );
+  TEST_RR_SRC21_BYPASS( 24, 1, 1, mulw, 154, 14, 11 );
+  TEST_RR_SRC21_BYPASS( 25, 2, 0, mulw, 165, 15, 11 );
+
+  TEST_RR_ZEROSRC1( 26, mulw, 0, 31 );
+  TEST_RR_ZEROSRC2( 27, mulw, 0, 32 );
+  TEST_RR_ZEROSRC12( 28, mulw, 0 );
+  TEST_RR_ZERODEST( 29, mulw, 33, 34 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64um/rem.S b/apps/riscv-tests/isa/rv64um/rem.S
new file mode 100644
index 0000000..e3248ff
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64um/rem.S
@@ -0,0 +1,41 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# rem.S
+#-----------------------------------------------------------------------------
+#
+# Test rem instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2, rem,  2,  20,   6 );
+  TEST_RR_OP( 3, rem, -2, -20,   6 );
+  TEST_RR_OP( 4, rem,  2,  20,  -6 );
+  TEST_RR_OP( 5, rem, -2, -20,  -6 );
+
+  TEST_RR_OP( 6, rem,  0, -1<<63,  1 );
+  TEST_RR_OP( 7, rem,  0, -1<<63, -1 );
+
+  TEST_RR_OP( 8, rem, -1<<63, -1<<63, 0 );
+  TEST_RR_OP( 9, rem,      1,      1, 0 );
+  TEST_RR_OP(10, rem,      0,      0, 0 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64um/remu.S b/apps/riscv-tests/isa/rv64um/remu.S
new file mode 100644
index 0000000..6946d0d
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64um/remu.S
@@ -0,0 +1,41 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# remu.S
+#-----------------------------------------------------------------------------
+#
+# Test remu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2, remu,   2,  20,   6 );
+  TEST_RR_OP( 3, remu,   2, -20,   6 );
+  TEST_RR_OP( 4, remu,  20,  20,  -6 );
+  TEST_RR_OP( 5, remu, -20, -20,  -6 );
+
+  TEST_RR_OP( 6, remu,      0, -1<<63,  1 );
+  TEST_RR_OP( 7, remu, -1<<63, -1<<63, -1 );
+
+  TEST_RR_OP( 8, remu, -1<<63, -1<<63, 0 );
+  TEST_RR_OP( 9, remu,      1,      1, 0 );
+  TEST_RR_OP(10, remu,      0,      0, 0 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64um/remuw.S b/apps/riscv-tests/isa/rv64um/remuw.S
new file mode 100644
index 0000000..334b5c5
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64um/remuw.S
@@ -0,0 +1,41 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# remuw.S
+#-----------------------------------------------------------------------------
+#
+# Test remuw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2, remuw,   2,  20,   6 );
+  TEST_RR_OP( 3, remuw,   2, -20,   6 );
+  TEST_RR_OP( 4, remuw,  20,  20,  -6 );
+  TEST_RR_OP( 5, remuw, -20, -20,  -6 );
+
+  TEST_RR_OP( 6, remuw,      0, -1<<31,  1 );
+  TEST_RR_OP( 7, remuw, -1<<31, -1<<31, -1 );
+
+  TEST_RR_OP( 8, remuw, -1<<31, -1<<31, 0 );
+  TEST_RR_OP( 9, remuw,      1,      1, 0 );
+  TEST_RR_OP(10, remuw,      0,      0, 0 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64um/remw.S b/apps/riscv-tests/isa/rv64um/remw.S
new file mode 100644
index 0000000..3ae8e3d
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64um/remw.S
@@ -0,0 +1,42 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# remw.S
+#-----------------------------------------------------------------------------
+#
+# Test remw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2, remw,  2,  20,   6 );
+  TEST_RR_OP( 3, remw, -2, -20,   6 );
+  TEST_RR_OP( 4, remw,  2,  20,  -6 );
+  TEST_RR_OP( 5, remw, -2, -20,  -6 );
+
+  TEST_RR_OP( 6, remw,  0, -1<<31,  1 );
+  TEST_RR_OP( 7, remw,  0, -1<<31, -1 );
+
+  TEST_RR_OP( 8, remw, -1<<31, -1<<31, 0 );
+  TEST_RR_OP( 9, remw,      1,      1, 0 );
+  TEST_RR_OP(10, remw,      0,      0, 0 );
+  TEST_RR_OP(11, remw, 0xfffffffffffff897,0xfffffffffffff897, 0 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
diff --git a/apps/riscv-tests/isa/rv64uv/Makefrag b/apps/riscv-tests/isa/rv64uv/Makefrag
new file mode 100644
index 0000000..f2c1336
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/Makefrag
@@ -0,0 +1,188 @@
+# Copyright 2021 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+#
+# Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+#         Basile Bougenot <bbougenot@student.ethz.ch>
+
+rv64uv_sc_tests = vaadd \
+                  vaaddu\
+                  vsadd \
+                  vsaddu \
+                  vsmul \
+                  vssra \
+                  vssrl \
+                  vnclip \
+                  vnclipu \
+                  vadd \
+                  vsub \
+                  vrsub \
+                  vwaddu \
+                  vwsubu \
+                  vwadd \
+                  vwsub \
+                  vsext \
+                  vzext \
+                  vadc \
+                  vmadc \
+                  vsbc \
+                  vmsbc \
+                  vand \
+                  vor \
+                  vxor \
+                  vsll \
+                  vsrl \
+                  vsra \
+                  vnsrl \
+                  vnsra \
+                  vmseq \
+                  vmsne \
+                  vmsltu \
+                  vmslt \
+                  vmsleu \
+                  vmsle \
+                  vmsgtu \
+                  vmsgt \
+                  vminu \
+                  vmin \
+                  vmaxu \
+                  vmax \
+                  vmul \
+                  vmulh \
+                  vmulhu \
+                  vmulhsu \
+                  vdivu \
+                  vdiv \
+                  vremu \
+                  vrem \
+                  vwmul \
+                  vwmulu \
+                  vwmulsu \
+                  vmacc \
+                  vnmsac \
+                  vmadd \
+                  vnmsub \
+                  vwmaccu \
+                  vwmacc \
+                  vwmaccsu \
+                  vwmaccus \
+                  vmerge \
+                  vmv \
+                  vmvxs \
+                  vmvsx \
+                  vfmvfs \
+                  vfmvsf \
+                  vmvnrr \
+                  vredsum \
+                  vredmaxu \
+                  vredmax \
+                  vredminu \
+                  vredmin \
+                  vredand \
+                  vredor \
+                  vredxor \
+                  vwredsumu \
+                  vwredsum \
+                  vfadd \
+                  vfsub \
+                  vfrsub \
+                  vfwadd \
+                  vfwsub \
+                  vfmul \
+                  vfdiv \
+                  vfrdiv \
+                  vfwmul \
+                  vfmacc \
+                  vfnmacc \
+                  vfmsac \
+                  vfnmsac \
+                  vfmadd \
+                  vfnmadd \
+                  vfmsub \
+                  vfnmsub \
+                  vfwmacc \
+                  vfwnmacc \
+                  vfwmsac \
+                  vfwnmsac \
+                  vfsqrt \
+                  vfmin \
+                  vfmax \
+                  vfredusum \
+                  vfredosum \
+                  vfredmin \
+                  vfredmax \
+                  vfwredusum \
+                  vfwredosum \
+                  vfclass \
+                  vfsgnj \
+                  vfsgnjn \
+                  vfsgnjx \
+                  vfmerge \
+                  vfmv \
+                  vmfeq \
+                  vmfne \
+                  vmflt \
+                  vmfle \
+                  vmfgt \
+                  vmfge \
+                  vfcvt \
+                  vfwcvt \
+                  vfncvt \
+                  vmand \
+                  vmnand \
+                  vmandnot \
+                  vmor \
+                  vmnor \
+                  vmornot \
+                  vmxor \
+                  vmxnor \
+                  vslideup \
+                  vslidedown \
+                  vslide1up \
+                  vfslide1up \
+                  vslide1down \
+                  vfslide1down \
+                  vl \
+                  vlff \
+                  vlseg \
+                  vlsseg \
+                  vluxseg \
+                  vl1r \
+                  vle1 \
+                  vls \
+                  vluxei \
+                  vs \
+                  vsseg \
+                  vssseg \
+                  vsuxseg \
+                  vs1r \
+                  vse1 \
+                  vss \
+                  vsuxei \
+                  vsetivli\
+                  vsetvli\
+                  vsetvl\
+                  vmsbf \
+                  vmsof \
+                  vmsif \
+                  viota \
+                  vid \
+                  vcpop \
+                  vfirst \
+                  vle8 \
+                  vse8 \
+                  vle16 \
+                  vse16 \
+                  vle32 \
+                  vse32 \
+                  vle64 \
+                  vse64 \
+                  vle_vse_hazards \
+                  vfrec7 \
+                  vfrsqrt7 \
+                  vrgather \
+                  vcompress
+
+rv64uv_p_tests = $(addprefix rv64uv-p-, $(rv64uv_sc_tests))
+
+spike_ctests += $(rv64uv_p_tests)
diff --git a/apps/riscv-tests/isa/rv64uv/vaadd.c b/apps/riscv-tests/isa/rv64uv/vaadd.c
new file mode 100644
index 0000000..40cd9d4
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vaadd.c
@@ -0,0 +1,59 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  set_vxrm(0); // setting vxrm to rnu rounding mode
+  VSET(4, e8, m1);
+  VLOAD_8(v1, 1, -2, -3, 4);
+  VLOAD_8(v2, 1, 2, -3, 3);
+  __asm__ volatile("vaadd.vv v3, v1, v2" ::);
+  VCMP_U8(1, v3, 1, 0, -3, 4);
+}
+
+void TEST_CASE2(void) {
+  set_vxrm(1); // setting vxrm to rne rounding mode
+  VSET(4, e8, m1);
+  VLOAD_8(v1, 1, -2, -3, 4);
+  VLOAD_8(v2, 1, 9, -3, 5);
+  VLOAD_8(v0, 0xA, 0x0, 0x0, 0x0);
+  VCLEAR(v3);
+  __asm__ volatile("vaadd.vv v3, v1, v2, v0.t" ::);
+  VCMP_U8(2, v3, 0, 4, 0, 4);
+}
+
+void TEST_CASE3(void) {
+  set_vxrm(2); // setting vxrm to rdn rounding mode
+  VSET(4, e32, m1);
+  VLOAD_32(v1, 1, -2, 3, -4);
+  const uint32_t scalar = 5;
+  __asm__ volatile("vaadd.vx v3, v1, %[A]" ::[A] "r"(scalar));
+  VCMP_U32(3, v3, 3, 1, 4, 0);
+}
+
+// Dont use VCLEAR here, it results in a glitch where are values are off by 1
+void TEST_CASE4(void) {
+  set_vxrm(3); // setting vxrm to rod rounding mode
+  VSET(4, e32, m1);
+  VLOAD_32(v1, 1, 2, 3, 4);
+  const uint32_t scalar = 5;
+  VLOAD_32(v0, 0xA, 0x0, 0x0, 0x0);
+  VCLEAR(v3);
+  __asm__ volatile("vaadd.vx v3, v1, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U32(4, v3, 0, 3, 0, 5);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vaaddu.c b/apps/riscv-tests/isa/rv64uv/vaaddu.c
new file mode 100644
index 0000000..44bea01
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vaaddu.c
@@ -0,0 +1,59 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  set_vxrm(0); // setting vxrm to rnu rounding mode
+  VSET(4, e8, m1);
+  VLOAD_8(v1, 1, 2, 3, 5);
+  VLOAD_8(v2, 1, 3, 8, 4);
+  __asm__ volatile("vaaddu.vv v3, v1, v2" ::);
+  VCMP_U8(1, v3, 1, 3, 6, 5);
+}
+
+void TEST_CASE2(void) {
+  set_vxrm(1); // setting vxrm to rne rounding mode
+  VSET(4, e8, m1);
+  VLOAD_8(v1, 5, 8, 3, 7);
+  VLOAD_8(v2, 7, 5, 3, 5);
+  VLOAD_8(v0, 0x0A, 0x00, 0x00, 0x00);
+  VCLEAR(v3);
+  __asm__ volatile("vaaddu.vv v3, v1, v2, v0.t" ::);
+  VCMP_U8(2, v3, 0, 6, 0, 6);
+}
+
+void TEST_CASE3(void) {
+  set_vxrm(2); // setting vxrm to rdn rounding mode
+  VSET(4, e32, m1);
+  VLOAD_32(v1, 1, 2, 3, 4);
+  const uint32_t scalar = 5;
+  __asm__ volatile("vaaddu.vx v3, v1, %[A]" ::[A] "r"(scalar));
+  VCMP_U32(3, v3, 3, 3, 4, 4);
+}
+
+// Dont use VCLEAR here, it results in a glitch where are values are off by 1
+void TEST_CASE4(void) {
+  set_vxrm(3); // setting vxrm to rod rounding mode
+  VSET(4, e32, m1);
+  VLOAD_32(v1, 1, 2, 3, 4);
+  const uint32_t scalar = 5;
+  VLOAD_32(v0, 0xA, 0x0, 0x0, 0x0);
+  VCLEAR(v3);
+  __asm__ volatile("vaaddu.vx v3, v1, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U32(4, v3, 0, 3, 0, 5);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vadc.c b/apps/riscv-tests/isa/rv64uv/vadc.c
new file mode 100644
index 0000000..ec16d28
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vadc.c
@@ -0,0 +1,103 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, -7, 7);
+  VLOAD_8(v2, 8, 7, 6, 5, 4, 3, 2, 1, 1, 2, 3, 4, 5, 6, 7, -8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vadc.vvm v3, v1, v2, v0");
+  VCMP_U8(1, v3, 9, 10, 9, 10, 9, 10, 9, 10, 2, 5, 6, 9, 10, 13, 0, 0);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, -7, 7);
+  VLOAD_16(v2, 8, 7, 6, 5, 4, 3, 2, 1, 1, 2, 3, 4, 5, 6, 7, -8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vadc.vvm v3, v1, v2, v0");
+  VCMP_U16(2, v3, 9, 10, 9, 10, 9, 10, 9, 10, 2, 5, 6, 9, 10, 13, 0, 0);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, -7, 7);
+  VLOAD_32(v2, 8, 7, 6, 5, 4, 3, 2, 1, 1, 2, 3, 4, 5, 6, 7, -8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vadc.vvm v3, v1, v2, v0");
+  VCMP_U32(3, v3, 9, 10, 9, 10, 9, 10, 9, 10, 2, 5, 6, 9, 10, 13, 0, 0);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, -7, 7);
+  VLOAD_64(v2, 8, 7, 6, 5, 4, 3, 2, 1, 1, 2, 3, 4, 5, 6, 7, -8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vadc.vvm v3, v1, v2, v0");
+  VCMP_U64(4, v3, 9, 10, 9, 10, 9, 10, 9, 10, 2, 5, 6, 9, 10, 13, 0, 0);
+};
+
+void TEST_CASE2(void) {
+  const uint32_t scalar = 5;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vadc.vxm v3, v1, %[A], v0" ::[A] "r"(scalar));
+  VCMP_U8(5, v3, 6, 8, 8, 10, 10, 12, 12, 14, 6, 8, 8, 10, 10, 12, 12, 14);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vadc.vxm v3, v1, %[A], v0" ::[A] "r"(scalar));
+  VCMP_U16(6, v3, 6, 8, 8, 10, 10, 12, 12, 14, 6, 8, 8, 10, 10, 12, 12, 14);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vadc.vxm v3, v1, %[A], v0" ::[A] "r"(scalar));
+  VCMP_U32(7, v3, 6, 8, 8, 10, 10, 12, 12, 14, 6, 8, 8, 10, 10, 12, 12, 14);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vadc.vxm v3, v1, %[A], v0" ::[A] "r"(scalar));
+  VCMP_U64(8, v3, 6, 8, 8, 10, 10, 12, 12, 14, 6, 8, 8, 10, 10, 12, 12, 14);
+};
+
+void TEST_CASE3(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vadc.vim v3, v1, 5, v0");
+  VCMP_U8(9, v3, 6, 8, 8, 10, 10, 12, 12, 14, 6, 8, 8, 10, 10, 12, 12, 14);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vadc.vim v3, v1, 5, v0");
+  VCMP_U16(10, v3, 6, 8, 8, 10, 10, 12, 12, 14, 6, 8, 8, 10, 10, 12, 12, 14);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vadc.vim v3, v1, 5, v0");
+  VCMP_U32(11, v3, 6, 8, 8, 10, 10, 12, 12, 14, 6, 8, 8, 10, 10, 12, 12, 14);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vadc.vim v3, v1, 5, v0");
+  VCMP_U64(12, v3, 6, 8, 8, 10, 10, 12, 12, 14, 6, 8, 8, 10, 10, 12, 12, 14);
+};
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vadd.c b/apps/riscv-tests/isa/rv64uv/vadd.c
new file mode 100644
index 0000000..b7fc41b
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vadd.c
@@ -0,0 +1,202 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vadd.vv v3, v1, v2");
+  VCMP_U8(1, v3, 2, 4, 6, 8, 10, 12, 14, 16, 2, 4, 6, 8, 10, 12, 14, 16);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vadd.vv v3, v1, v2");
+  VCMP_U16(2, v3, 2, 4, 6, 8, 10, 12, 14, 16, 2, 4, 6, 8, 10, 12, 14, 16);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vadd.vv v3, v1, v2");
+  VCMP_U32(3, v3, 2, 4, 6, 8, 10, 12, 14, 16, 2, 4, 6, 8, 10, 12, 14, 16);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_64(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vadd.vv v3, v1, v2");
+  VCMP_U64(4, v3, 2, 4, 6, 8, 10, 12, 14, 16, 2, 4, 6, 8, 10, 12, 14, 16);
+}
+
+void TEST_CASE2(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v3);
+  asm volatile("vadd.vv v3, v1, v2, v0.t");
+  VCMP_U8(5, v3, 0, 4, 0, 8, 0, 12, 0, 16, 0, 4, 0, 8, 0, 12, 0, 16);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v3);
+  asm volatile("vadd.vv v3, v1, v2, v0.t");
+  VCMP_U16(6, v3, 0, 4, 0, 8, 0, 12, 0, 16, 0, 4, 0, 8, 0, 12, 0, 16);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v3);
+  asm volatile("vadd.vv v3, v1, v2, v0.t");
+  VCMP_U32(7, v3, 0, 4, 0, 8, 0, 12, 0, 16, 0, 4, 0, 8, 0, 12, 0, 16);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_64(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v3);
+  asm volatile("vadd.vv v3, v1, v2, v0.t");
+  VCMP_U64(8, v3, 0, 4, 0, 8, 0, 12, 0, 16, 0, 4, 0, 8, 0, 12, 0, 16);
+}
+
+void TEST_CASE3(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vadd.vi v3, v1, 5");
+  VCMP_U8(9, v3, 6, 7, 8, 9, 10, 11, 12, 13, 6, 7, 8, 9, 10, 11, 12, 13);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vadd.vi v3, v1, 5");
+  VCMP_U16(10, v3, 6, 7, 8, 9, 10, 11, 12, 13, 6, 7, 8, 9, 10, 11, 12, 13);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vadd.vi v3, v1, 5");
+  VCMP_U32(11, v3, 6, 7, 8, 9, 10, 11, 12, 13, 6, 7, 8, 9, 10, 11, 12, 13);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vadd.vi v3, v1, 5");
+  VCMP_U64(12, v3, 6, 7, 8, 9, 10, 11, 12, 13, 6, 7, 8, 9, 10, 11, 12, 13);
+}
+
+void TEST_CASE4(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v3);
+  asm volatile("vadd.vi v3, v1, 5, v0.t");
+  VCMP_U8(13, v3, 0, 7, 0, 9, 0, 11, 0, 13, 0, 7, 0, 9, 0, 11, 0, 13);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v3);
+  asm volatile("vadd.vi v3, v1, 5, v0.t");
+  VCMP_U16(14, v3, 0, 7, 0, 9, 0, 11, 0, 13, 0, 7, 0, 9, 0, 11, 0, 13);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v3);
+  asm volatile("vadd.vi v3, v1, 5, v0.t");
+  VCMP_U32(15, v3, 0, 7, 0, 9, 0, 11, 0, 13, 0, 7, 0, 9, 0, 11, 0, 13);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v3);
+  asm volatile("vadd.vi v3, v1, 5, v0.t");
+  VCMP_U64(16, v3, 0, 7, 0, 9, 0, 11, 0, 13, 0, 7, 0, 9, 0, 11, 0, 13);
+}
+
+void TEST_CASE5(void) {
+  const uint32_t scalar = 5;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 1, -2, 3, -4, 5, -6, 7, -8, 9, -10, 11, -12, 13, -14, 15, -16);
+  asm volatile("vadd.vx v3, v1, %[A]" ::[A] "r"(scalar));
+  VCMP_U8(17, v3, 6, 3, 8, 1, 10, -1, 12, -3, 14, -5, 16, -7, 18, -9, 20, -11);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 1, -2, 3, -4, 5, -6, 7, -8, 9, -10, 11, -12, 13, -14, 15, -16);
+  asm volatile("vadd.vx v3, v1, %[A]" ::[A] "r"(scalar));
+  VCMP_U16(18, v3, 6, 3, 8, 1, 10, -1, 12, -3, 14, -5, 16, -7, 18, -9, 20, -11);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 1, -2, 3, -4, 5, -6, 7, -8, 9, -10, 11, -12, 13, -14, 15, -16);
+  asm volatile("vadd.vx v3, v1, %[A]" ::[A] "r"(scalar));
+  VCMP_U32(19, v3, 6, 3, 8, 1, 10, -1, 12, -3, 14, -5, 16, -7, 18, -9, 20, -11);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 1, -2, 3, -4, 5, -6, 7, -8, 9, -10, 11, -12, 13, -14, 15, -16);
+  asm volatile("vadd.vx v3, v1, %[A]" ::[A] "r"(scalar));
+  VCMP_U64(20, v3, 6, 3, 8, 1, 10, -1, 12, -3, 14, -5, 16, -7, 18, -9, 20, -11);
+}
+
+void TEST_CASE6(void) {
+  const uint32_t scalar = 5;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v3);
+  asm volatile("vadd.vx v3, v1, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U8(21, v3, 0, 7, 0, 9, 0, 11, 0, 13, 0, 7, 0, 9, 0, 11, 0, 13);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v3);
+  asm volatile("vadd.vx v3, v1, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U16(22, v3, 0, 7, 0, 9, 0, 11, 0, 13, 0, 7, 0, 9, 0, 11, 0, 13);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v3);
+  asm volatile("vadd.vx v3, v1, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U32(23, v3, 0, 7, 0, 9, 0, 11, 0, 13, 0, 7, 0, 9, 0, 11, 0, 13);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v3);
+  asm volatile("vadd.vx v3, v1, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U64(24, v3, 0, 7, 0, 9, 0, 11, 0, 13, 0, 7, 0, 9, 0, 11, 0, 13);
+}
+
+// Check that the addition also works when source register EEWs are changed
+void TEST_CASE7(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VSET(8, e16, m1);
+  asm volatile("vadd.vv v3, v1, v2");
+  VSET(16, e8, m1);
+  VCMP_U8(25, v3, 2, 4, 6, 8, 10, 12, 14, 16, 2, 4, 6, 8, 10, 12, 14, 16);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+  TEST_CASE6();
+  TEST_CASE7();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vand.c b/apps/riscv-tests/isa/rv64uv/vand.c
new file mode 100644
index 0000000..521435a
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vand.c
@@ -0,0 +1,309 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1() {
+  VSET(12, e8, m1);
+  VLOAD_8(v2, 0xff, 0x01, 0xf0, 0xff, 0x01, 0xf0, 0xff, 0x01, 0xf0, 0xff, 0x01,
+          0xf0);
+  VLOAD_8(v3, 0xf0, 0x03, 0xf0, 0xf0, 0x03, 0xf0, 0xf0, 0x03, 0xf0, 0xf0, 0x03,
+          0xf0);
+  asm volatile("vand.vv v1, v2, v3");
+  VCMP_U8(1, v1, 0xf0, 0x01, 0xf0, 0xf0, 0x01, 0xf0, 0xf0, 0x01, 0xf0, 0xf0,
+          0x01, 0xf0);
+
+  VSET(12, e16, m1);
+  VLOAD_16(v2, 0xffff, 0x0001, 0xf0f0, 0xffff, 0x0001, 0xf0f0, 0xffff, 0x0001,
+           0xf0f0, 0xffff, 0x0001, 0xf0f0);
+  VLOAD_16(v3, 0xff00, 0x0003, 0xf0f0, 0xff00, 0x0003, 0xf0f0, 0xff00, 0x0003,
+           0xf0f0, 0xff00, 0x0003, 0xf0f0);
+  asm volatile("vand.vv v1, v2, v3");
+  VCMP_U16(2, v1, 0xff00, 0x0001, 0xf0f0, 0xff00, 0x0001, 0xf0f0, 0xff00,
+           0x0001, 0xf0f0, 0xff00, 0x0001, 0xf0f0);
+
+  VSET(12, e32, m1);
+  VLOAD_32(v2, 0xffffffff, 0x00000001, 0xf0f0f0f0, 0xffffffff, 0x00000001,
+           0xf0f0f0f0, 0xffffffff, 0x00000001, 0xf0f0f0f0, 0xffffffff,
+           0x00000001, 0xf0f0f0f0);
+  VLOAD_32(v3, 0xffff0000, 0x00000003, 0xf0f0f0f0, 0xffff0000, 0x00000003,
+           0xf0f0f0f0, 0xffff0000, 0x00000003, 0xf0f0f0f0, 0xffff0000,
+           0x00000003, 0xf0f0f0f0);
+  asm volatile("vand.vv v1, v2, v3");
+  VCMP_U32(3, v1, 0xffff0000, 0x00000001, 0xf0f0f0f0, 0xffff0000, 0x00000001,
+           0xf0f0f0f0, 0xffff0000, 0x00000001, 0xf0f0f0f0, 0xffff0000,
+           0x00000001, 0xf0f0f0f0);
+
+  VSET(12, e64, m1);
+  VLOAD_64(v2, 0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0);
+  VLOAD_64(v3, 0xffffffff00000000, 0x0000000000000003, 0xf0f0f0f0f0f0f0f0,
+           0xffffffff00000000, 0x0000000000000003, 0xf0f0f0f0f0f0f0f0,
+           0xffffffff00000000, 0x0000000000000003, 0xf0f0f0f0f0f0f0f0,
+           0xffffffff00000000, 0x0000000000000003, 0xf0f0f0f0f0f0f0f0);
+  asm volatile("vand.vv v1, v2, v3");
+  VCMP_U64(4, v1, 0xffffffff00000000, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffff00000000, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffff00000000, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffff00000000, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0);
+}
+
+void TEST_CASE2() {
+  VSET(12, e8, m1);
+  VLOAD_8(v2, 0xff, 0x01, 0xf0, 0xff, 0x01, 0xf0, 0xff, 0x01, 0xf0, 0xff, 0x01,
+          0xf0);
+  VLOAD_8(v3, 0xf0, 0x03, 0xf0, 0xf0, 0x03, 0xf0, 0xf0, 0x03, 0xf0, 0xf0, 0x03,
+          0xf0);
+  VLOAD_8(v0, 0x6D, 0x0B);
+  VLOAD_8(v1, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef,
+          0xef);
+  asm volatile("vand.vv v1, v2, v3, v0.t");
+  VCMP_U8(5, v1, 0xf0, 0xef, 0xf0, 0xf0, 0xef, 0xf0, 0xf0, 0xef, 0xf0, 0xf0,
+          0xef, 0xf0);
+
+  VSET(12, e16, m1);
+  VLOAD_16(v2, 0xffff, 0x0001, 0xf0f0, 0xffff, 0x0001, 0xf0f0, 0xffff, 0x0001,
+           0xf0f0, 0xffff, 0x0001, 0xf0f0);
+  VLOAD_16(v3, 0xff00, 0x0003, 0xf0f0, 0xff00, 0x0003, 0xf0f0, 0xff00, 0x0003,
+           0xf0f0, 0xff00, 0x0003, 0xf0f0);
+  VLOAD_8(v0, 0x6D, 0x0B);
+  VLOAD_16(v1, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef,
+           0xbeef, 0xbeef, 0xbeef, 0xbeef);
+  asm volatile("vand.vv v1, v2, v3, v0.t");
+  VCMP_U16(6, v1, 0xff00, 0xbeef, 0xf0f0, 0xff00, 0xbeef, 0xf0f0, 0xff00,
+           0xbeef, 0xf0f0, 0xff00, 0xbeef, 0xf0f0);
+
+  VSET(12, e32, m1);
+  VLOAD_32(v2, 0xffffffff, 0x00000001, 0xf0f0f0f0, 0xffffffff, 0x00000001,
+           0xf0f0f0f0, 0xffffffff, 0x00000001, 0xf0f0f0f0, 0xffffffff,
+           0x00000001, 0xf0f0f0f0);
+  VLOAD_32(v3, 0xffff0000, 0x00000003, 0xf0f0f0f0, 0xffff0000, 0x00000003,
+           0xf0f0f0f0, 0xffff0000, 0x00000003, 0xf0f0f0f0, 0xffff0000,
+           0x00000003, 0xf0f0f0f0);
+  VLOAD_8(v0, 0x6D, 0x0B);
+  VLOAD_32(v1, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
+           0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
+           0xdeadbeef, 0xdeadbeef);
+  asm volatile("vand.vv v1, v2, v3, v0.t");
+  VCMP_U32(7, v1, 0xffff0000, 0xdeadbeef, 0xf0f0f0f0, 0xffff0000, 0xdeadbeef,
+           0xf0f0f0f0, 0xffff0000, 0xdeadbeef, 0xf0f0f0f0, 0xffff0000,
+           0xdeadbeef, 0xf0f0f0f0);
+
+  VSET(12, e64, m1);
+  VLOAD_64(v2, 0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0);
+  VLOAD_64(v3, 0xffffffff00000000, 0x0000000000000003, 0xf0f0f0f0f0f0f0f0,
+           0xffffffff00000000, 0x0000000000000003, 0xf0f0f0f0f0f0f0f0,
+           0xffffffff00000000, 0x0000000000000003, 0xf0f0f0f0f0f0f0f0,
+           0xffffffff00000000, 0x0000000000000003, 0xf0f0f0f0f0f0f0f0);
+  VLOAD_8(v0, 0x6D, 0x0B);
+  VLOAD_64(v1, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef);
+  asm volatile("vand.vv v1, v2, v3, v0.t");
+  VCMP_U64(8, v1, 0xffffffff00000000, 0xdeadbeefdeadbeef, 0xf0f0f0f0f0f0f0f0,
+           0xffffffff00000000, 0xdeadbeefdeadbeef, 0xf0f0f0f0f0f0f0f0,
+           0xffffffff00000000, 0xdeadbeefdeadbeef, 0xf0f0f0f0f0f0f0f0,
+           0xffffffff00000000, 0xdeadbeefdeadbeef, 0xf0f0f0f0f0f0f0f0);
+}
+
+void TEST_CASE3() {
+  const uint64_t scalar = 0x0ff00ff00ff00ff0;
+
+  VSET(12, e8, m1);
+  VLOAD_8(v2, 0xff, 0x01, 0xf0, 0xff, 0x01, 0xf0, 0xff, 0x01, 0xf0, 0xff, 0x01,
+          0xf0);
+  asm volatile("vand.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U8(9, v1, 0xf0, 0x00, 0xf0, 0xf0, 0x00, 0xf0, 0xf0, 0x00, 0xf0, 0xf0,
+          0x00, 0xf0);
+
+  VSET(12, e16, m1);
+  VLOAD_16(v2, 0xffff, 0x0001, 0xf0f0, 0xffff, 0x0001, 0xf0f0, 0xffff, 0x0001,
+           0xf0f0, 0xffff, 0x0001, 0xf0f0);
+  asm volatile("vand.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U16(10, v1, 0x0ff0, 0x0000, 0x00f0, 0x0ff0, 0x0000, 0x00f0, 0x0ff0,
+           0x0000, 0x00f0, 0x0ff0, 0x0000, 0x00f0);
+
+  VSET(12, e32, m1);
+  VLOAD_32(v2, 0xffffffff, 0x00000001, 0xf0f0f0f0, 0xffffffff, 0x00000001,
+           0xf0f0f0f0, 0xffffffff, 0x00000001, 0xf0f0f0f0, 0xffffffff,
+           0x00000001, 0xf0f0f0f0);
+  asm volatile("vand.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U32(11, v1, 0x0ff00ff0, 0x00000000, 0x00f000f0, 0x0ff00ff0, 0x00000000,
+           0x00f000f0, 0x0ff00ff0, 0x00000000, 0x00f000f0, 0x0ff00ff0,
+           0x00000000, 0x00f000f0);
+
+  VSET(12, e64, m1);
+  VLOAD_64(v2, 0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0);
+  asm volatile("vand.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U64(12, v1, 0x0ff00ff00ff00ff0, 0x0000000000000000, 0x00f000f000f000f0,
+           0x0ff00ff00ff00ff0, 0x0000000000000000, 0x00f000f000f000f0,
+           0x0ff00ff00ff00ff0, 0x0000000000000000, 0x00f000f000f000f0,
+           0x0ff00ff00ff00ff0, 0x0000000000000000, 0x00f000f000f000f0);
+}
+
+void TEST_CASE4() {
+  const uint64_t scalar = 0x0ff00ff00ff00ff0;
+
+  VSET(12, e8, m1);
+  VLOAD_8(v2, 0xff, 0x01, 0xf0, 0xff, 0x01, 0xf0, 0xff, 0x01, 0xf0, 0xff, 0x01,
+          0xf0);
+  VLOAD_8(v0, 0x6D, 0x0B);
+  VLOAD_8(v1, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef,
+          0xef);
+  asm volatile("vand.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U8(13, v1, 0xf0, 0xef, 0xf0, 0xf0, 0xef, 0xf0, 0xf0, 0xef, 0xf0, 0xf0,
+          0xef, 0xf0);
+
+  VSET(12, e16, m1);
+  VLOAD_16(v2, 0xffff, 0x0001, 0xf0f0, 0xffff, 0x0001, 0xf0f0, 0xffff, 0x0001,
+           0xf0f0, 0xffff, 0x0001, 0xf0f0);
+  VLOAD_8(v0, 0x6D, 0x0B);
+  VLOAD_16(v1, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef,
+           0xbeef, 0xbeef, 0xbeef, 0xbeef);
+  asm volatile("vand.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U16(14, v1, 0x0ff0, 0xbeef, 0x00f0, 0x0ff0, 0xbeef, 0x00f0, 0x0ff0,
+           0xbeef, 0x00f0, 0x0ff0, 0xbeef, 0x00f0);
+
+  VSET(12, e32, m1);
+  VLOAD_32(v2, 0xffffffff, 0x00000001, 0xf0f0f0f0, 0xffffffff, 0x00000001,
+           0xf0f0f0f0, 0xffffffff, 0x00000001, 0xf0f0f0f0, 0xffffffff,
+           0x00000001, 0xf0f0f0f0);
+  VLOAD_8(v0, 0x6D, 0x0B);
+  VLOAD_32(v1, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
+           0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
+           0xdeadbeef, 0xdeadbeef);
+  asm volatile("vand.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U32(15, v1, 0x0ff00ff0, 0xdeadbeef, 0x00f000f0, 0x0ff00ff0, 0xdeadbeef,
+           0x00f000f0, 0x0ff00ff0, 0xdeadbeef, 0x00f000f0, 0x0ff00ff0,
+           0xdeadbeef, 0x00f000f0);
+
+  VSET(12, e64, m1);
+  VLOAD_64(v2, 0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0);
+  VLOAD_8(v0, 0x6D, 0x0B);
+  VLOAD_64(v1, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef);
+  asm volatile("vand.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U64(16, v1, 0x0ff00ff00ff00ff0, 0xdeadbeefdeadbeef, 0x00f000f000f000f0,
+           0x0ff00ff00ff00ff0, 0xdeadbeefdeadbeef, 0x00f000f000f000f0,
+           0x0ff00ff00ff00ff0, 0xdeadbeefdeadbeef, 0x00f000f000f000f0,
+           0x0ff00ff00ff00ff0, 0xdeadbeefdeadbeef, 0x00f000f000f000f0);
+}
+
+void TEST_CASE5() {
+  VSET(12, e8, m1);
+  VLOAD_8(v2, 0xff, 0x01, 0xf0, 0xff, 0x01, 0xf0, 0xff, 0x01, 0xf0, 0xff, 0x01,
+          0xf0);
+  asm volatile("vand.vi v1, v2, 15");
+  VCMP_U8(17, v1, 0x0f, 0x01, 0x00, 0x0f, 0x01, 0x00, 0x0f, 0x01, 0x00, 0x0f,
+          0x01, 0x00);
+
+  VSET(12, e16, m1);
+  VLOAD_16(v2, 0xffff, 0x0001, 0xf0f0, 0xffff, 0x0001, 0xf0f0, 0xffff, 0x0001,
+           0xf0f0, 0xffff, 0x0001, 0xf0f0);
+  asm volatile("vand.vi v1, v2, 15");
+  VCMP_U16(18, v1, 0x000f, 0x0001, 0x0000, 0x000f, 0x0001, 0x0000, 0x000f,
+           0x0001, 0x0000, 0x000f, 0x0001, 0x0000);
+
+  VSET(12, e32, m1);
+  VLOAD_32(v2, 0xffffffff, 0x00000001, 0xf0f0f0f0, 0xffffffff, 0x00000001,
+           0xf0f0f0f0, 0xffffffff, 0x00000001, 0xf0f0f0f0, 0xffffffff,
+           0x00000001, 0xf0f0f0f0);
+  asm volatile("vand.vi v1, v2, 15");
+  VCMP_U32(19, v1, 0x0000000f, 0x00000001, 0x00000000, 0x0000000f, 0x00000001,
+           0x00000000, 0x0000000f, 0x00000001, 0x00000000, 0x0000000f,
+           0x00000001, 0x00000000);
+
+  VSET(12, e64, m1);
+  VLOAD_64(v2, 0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0);
+  asm volatile("vand.vi v1, v2, 15");
+  VCMP_U64(20, v1, 0x000000000000000f, 0x0000000000000001, 0x0000000000000000,
+           0x000000000000000f, 0x0000000000000001, 0x0000000000000000,
+           0x000000000000000f, 0x0000000000000001, 0x0000000000000000,
+           0x000000000000000f, 0x0000000000000001, 0x0000000000000000);
+}
+
+void TEST_CASE6() {
+  VSET(12, e8, m1);
+  VLOAD_8(v2, 0xff, 0x01, 0xf0, 0xff, 0x01, 0xf0, 0xff, 0x01, 0xf0, 0xff, 0x01,
+          0xf0);
+  VLOAD_8(v0, 0x6D, 0x0B);
+  VLOAD_8(v1, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef,
+          0xef);
+  asm volatile("vand.vi v1, v2, 15, v0.t");
+  VCMP_U8(21, v1, 0x0f, 0xef, 0x00, 0x0f, 0xef, 0x00, 0x0f, 0xef, 0x00, 0x0f,
+          0xef, 0x00);
+
+  VSET(12, e16, m1);
+  VLOAD_16(v2, 0xffff, 0x0001, 0xf0f0, 0xffff, 0x0001, 0xf0f0, 0xffff, 0x0001,
+           0xf0f0, 0xffff, 0x0001, 0xf0f0);
+  VLOAD_8(v0, 0x6D, 0x0B);
+  VLOAD_16(v1, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef,
+           0xbeef, 0xbeef, 0xbeef, 0xbeef);
+  asm volatile("vand.vi v1, v2, 15, v0.t");
+  VCMP_U16(22, v1, 0x000f, 0xbeef, 0x0000, 0x000f, 0xbeef, 0x0000, 0x000f,
+           0xbeef, 0x0000, 0x000f, 0xbeef, 0x0000);
+
+  VSET(12, e32, m1);
+  VLOAD_32(v2, 0xffffffff, 0x00000001, 0xf0f0f0f0, 0xffffffff, 0x00000001,
+           0xf0f0f0f0, 0xffffffff, 0x00000001, 0xf0f0f0f0, 0xffffffff,
+           0x00000001, 0xf0f0f0f0);
+  VLOAD_8(v0, 0x6D, 0x0B);
+  VLOAD_32(v1, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
+           0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
+           0xdeadbeef, 0xdeadbeef);
+  asm volatile("vand.vi v1, v2, 15, v0.t");
+  VCMP_U32(23, v1, 0x0000000f, 0xdeadbeef, 0x00000000, 0x0000000f, 0xdeadbeef,
+           0x00000000, 0x0000000f, 0xdeadbeef, 0x00000000, 0x0000000f,
+           0xdeadbeef, 0x00000000);
+
+  VSET(12, e64, m1);
+  VLOAD_64(v2, 0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0);
+  VLOAD_8(v0, 0x6D, 0x0B);
+  VLOAD_64(v1, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef);
+  asm volatile("vand.vi v1, v2, 15, v0.t");
+  VCMP_U64(24, v1, 0x000000000000000f, 0xdeadbeefdeadbeef, 0x0000000000000000,
+           0x000000000000000f, 0xdeadbeefdeadbeef, 0x0000000000000000,
+           0x000000000000000f, 0xdeadbeefdeadbeef, 0x0000000000000000,
+           0x000000000000000f, 0xdeadbeefdeadbeef, 0x0000000000000000);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+  TEST_CASE6();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vasub.c b/apps/riscv-tests/isa/rv64uv/vasub.c
new file mode 100644
index 0000000..760a333
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vasub.c
@@ -0,0 +1,54 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(4, e32, m1);
+  VLOAD_32(v1, 5, 10, 15, 20);
+  VLOAD_32(v2, -1, 2, -3, 4);
+  __asm__ volatile("vasub.vv v3, v1, v2" ::);
+  VEC_CMP_32(1, v3, 3, 4, 9, 8);
+}
+
+void TEST_CASE2(void) {
+  VSET(4, e32, m1);
+  VLOAD_32(v1, 5, 10, 15, 20);
+  VLOAD_32(v2, 1, 2, 3, -4);
+  VLOAD_32(v0, 10, 0, 0, 0);
+  CLEAR(v3);
+  __asm__ volatile("vasub.vv v3, v1, v2, v0.t" ::);
+  VEC_CMP_32(2, v3, 0, 4, 0, 12);
+}
+
+void TEST_CASE3(void) {
+  VSET(4, e32, m1);
+  VLOAD_U32(v1, 5, 10, 15, 20);
+  const uint64_t scalar = -5;
+  __asm__ volatile("vasub.vx v3, v1, %[A]" ::[A] "r"(scalar));
+  VEC_CMP_U32(3, v3, 5, 8, 10, 13);
+}
+
+void TEST_CASE4(void) {
+  VSET(4, e32, m1);
+  VLOAD_U32(v1, 5, 10, 15, 20);
+  const uint64_t scalar = -5;
+  VLOAD_U32(v0, 10, 0, 0, 0);
+  CLEAR(v3);
+  __asm__ volatile("vasub.vx v3, v1, %[A], v0.t" ::[A] "r"(scalar));
+  VEC_CMP_U32(4, v3, 0, 8, 0, 13);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vasubu.c b/apps/riscv-tests/isa/rv64uv/vasubu.c
new file mode 100644
index 0000000..68ec9cd
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vasubu.c
@@ -0,0 +1,54 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(4, e32, m1);
+  VLOAD_U32(v1, 5, 10, 15, 20);
+  VLOAD_U32(v2, 1, 2, 3, 4);
+  __asm__ volatile("vasubu.vv v3, v1, v2" ::);
+  VEC_CMP_U32(1, v3, 2, 4, 6, 8);
+}
+
+void TEST_CASE2(void) {
+  VSET(4, e32, m1);
+  VLOAD_U32(v1, 5, 10, 15, 20);
+  VLOAD_U32(v2, 1, 2, 3, 4);
+  VLOAD_U32(v0, 10, 0, 0, 0);
+  CLEAR(v3);
+  __asm__ volatile("vasubu.vv v3, v1, v2, v0.t" ::);
+  VEC_CMP_U32(2, v3, 0, 4, 0, 8);
+}
+
+void TEST_CASE3(void) {
+  VSET(4, e32, m1);
+  VLOAD_U32(v1, 5, 10, 15, 20);
+  const uint64_t scalar = 5;
+  __asm__ volatile("vasubu.vx v3, v1, %[A]" ::[A] "r"(scalar));
+  VEC_CMP_U32(3, v3, 0, 3, 5, 8);
+}
+
+void TEST_CASE4(void) {
+  VSET(4, e32, m1);
+  VLOAD_U32(v1, 5, 10, 15, 20);
+  const uint64_t scalar = 5;
+  VLOAD_U32(v0, 10, 0, 0, 0);
+  CLEAR(v3);
+  __asm__ volatile("vasubu.vx v3, v1, %[A], v0.t" ::[A] "r"(scalar));
+  VEC_CMP_U32(4, v3, 0, 3, 0, 8);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vcompress.c b/apps/riscv-tests/isa/rv64uv/vcompress.c
new file mode 100644
index 0000000..d568d95
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vcompress.c
@@ -0,0 +1,183 @@
+// Copyright 2024 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1() {
+  VSET(4, e64, m1);
+  VLOAD_64(v4, 1, 2, 3, 4);
+  VLOAD_64(v0, 12, 0, 0, 0);
+  VCLEAR(v2);
+  asm volatile("vcompress.vm v2, v4, v0");
+  VCMP_U64(1, v2, 3, 4, 0, 0);
+}
+
+void TEST_CASE2() {
+  VSET(16, e8, m1);
+  VLOAD_8(v4, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_8(v0, 0b10111100, 0b10111111, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+  VCLEAR(v2);
+  asm volatile("vcompress.vm v2, v4, v0");
+  VCMP_U8(2, v2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 16, 0, 0, 0, 0);
+
+  VSET(257, e16, m4);
+  VLOAD_16(
+      v28, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
+      20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37,
+      38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55,
+      56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73,
+      74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91,
+      92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
+      108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122,
+      123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137,
+      138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152,
+      153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167,
+      168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182,
+      183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197,
+      198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212,
+      213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227,
+      228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242,
+      243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255, 256);
+  VSET(9, e64, m1);
+  VLOAD_64(v0, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff,
+           0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff,
+           0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff);
+  VSET(1024, e8, m4);
+  VCLEAR_AT_ONE(v24);
+  VSET(257, e16, m4);
+  asm volatile("vcompress.vm v24, v28, v0");
+  VSET(512, e16, m4);
+  VCMP_U16(
+      3, v24, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18,
+      19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,
+      37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54,
+      55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72,
+      73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90,
+      91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106,
+      107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121,
+      122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136,
+      137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151,
+      152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166,
+      167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181,
+      182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196,
+      197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211,
+      212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226,
+      227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241,
+      242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255, 256,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff);
+
+  VSET(257, e16, m4);
+  VLOAD_16(
+      v28, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
+      20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37,
+      38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55,
+      56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73,
+      74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91,
+      92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
+      108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122,
+      123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137,
+      138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152,
+      153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167,
+      168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182,
+      183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197,
+      198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212,
+      213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227,
+      228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242,
+      243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255, 256);
+  VSET(8, e64, m4);
+  VLOAD_64(v0, 0xffffffffffffffbc, 0xffffffffffffffbf, 0xffffffffffffffff,
+           0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff,
+           0xffffffffffffffff, 0xffffffffffffffff);
+  VSET(1024, e8, m4);
+  VCLEAR_AT_ONE(v24);
+  VSET(257, e16, m4);
+  asm volatile("vcompress.vm v24, v28, v0");
+  VSET(512, e16, m4);
+  VCMP_U16(
+      4, v24, 2, 3, 4, 5, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
+      21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38,
+      39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56,
+      57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 71, 72, 73, 74, 75,
+      76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93,
+      94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109,
+      110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124,
+      125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139,
+      140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154,
+      155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169,
+      170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184,
+      185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199,
+      200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214,
+      215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 229,
+      230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244,
+      245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255, 256, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
+      0xffff, 0xffff, 0xffff, 0xffff);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+  enable_fp();
+  TEST_CASE1();
+  TEST_CASE2();
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vcpop.c b/apps/riscv-tests/isa/rv64uv/vcpop.c
new file mode 100644
index 0000000..3c96421
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vcpop.c
@@ -0,0 +1,111 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+// masked
+void TEST_CASE1(void) {
+  VSET(4, e32, m1);
+  VCLEAR(v2);
+  VLOAD_32(v2, 7, 0, 0, 0);
+  VLOAD_32(v0, 5, 0, 0, 0);
+  volatile uint32_t scalar = 1337;
+  volatile uint32_t OUP[] = {0, 0, 0, 0};
+  asm volatile("vpopc.m %[A], v2, v0.t \n"
+               "sw %[A], (%1) \n"
+               :
+               : [A] "r"(scalar), "r"(OUP));
+  XCMP(1, OUP[0], 2);
+
+  VSET(32, e32, m1);
+  VLOAD_32(v8, 0xFFFFFFF7FFFFFFFF, 0x88, 0x1, 0x1F, 0xFFFFFFF7FFFFFFFF, 0x88,
+           0x1, 0x1F, 0xFFFFFFF7FFFFFFFF, 0x88, 0x1, 0x1F, 0xFFFFFFF7FFFFFFFF,
+           0x88, 0x1, 0x1F, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+  VLOAD_32(v0, 0xffffffffffffffff, 0xfffffffffffffff7, 0xffffffffffffffff,
+           0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff,
+           0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff,
+           0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff,
+           0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff,
+           0xefffffffffffffff, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+  VSET(1024, e8, m8);
+  asm volatile("vpopc.m %[A], v8, v0.t \n"
+               "sw %[A], (%1) \n"
+               :
+               : [A] "r"(scalar), "r"(OUP));
+  XCMP(2, OUP[0], 159);
+}
+
+// unmasked
+void TEST_CASE2(void) {
+  VSET(4, e32, m1);
+  VLOAD_32(v2, 0xFFFFFFF7FFFFFFFF, 0x88, 0x1, 0x1F);
+  volatile uint32_t scalar = 1337;
+  volatile uint32_t OUP[] = {0, 0, 0, 0};
+  VSET(128, e32, m2);
+  asm volatile("vpopc.m %[A], v2 \n"
+               "sw %[A], (%1) \n"
+               :
+               : [A] "r"(scalar), "r"(OUP));
+  XCMP(3, OUP[0], 40);
+
+  VSET(8, e32, m1);
+  VLOAD_32(v0, 0xFFFFFFF7FFFFFFFF, 0x88, 0x1, 0x1F, 0xFFFFFFF7FFFFFFFF, 0x88,
+           0x1, 0x1F);
+  VSET(256, e8, m8);
+  asm volatile("vpopc.m %[A], v0 \n"
+               "sw %[A], (%1) \n"
+               :
+               : [A] "r"(scalar), "r"(OUP));
+  XCMP(4, OUP[0], 80);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v0, 0xFFFFFFF7FFFFFFFF, 0x88, 0x1, 0x1F, 0xFFFFFFF7FFFFFFFF, 0x88,
+           0x1, 0x1F, 0xFFFFFFF7FFFFFFFF, 0x88, 0x1, 0x1F, 0xFFFFFFF7FFFFFFFF,
+           0x88, 0x1, 0x1F);
+  VSET(1024, e8, m8);
+  asm volatile("vpopc.m %[A], v0 \n"
+               "sw %[A], (%1) \n"
+               :
+               : [A] "r"(scalar), "r"(OUP));
+  XCMP(5, OUP[0], 160);
+
+  VSET(8, e32, m1);
+  VLOAD_32(v2, 0xFFFFFFF7FFFFFFFF, 0x88, 0x1, 0x1F, 0xFFFFFFF7FFFFFFFF, 0x88,
+           0x1, 0x1F);
+  VSET(256, e8, m1);
+  asm volatile("vpopc.m %[A], v2 \n"
+               "sw %[A], (%1) \n"
+               :
+               : [A] "r"(scalar), "r"(OUP));
+  XCMP(6, OUP[0], 80);
+
+  VSET(2, e32, m1);
+  VLOAD_8(v2, 0xFF, 0x88);
+  VSET(16, e16, m1);
+  asm volatile("vcpop.m %[A], v2 \n"
+               "sw %[A], (%1) \n"
+               :
+               : [A] "r"(scalar), "r"(OUP));
+  XCMP(7, OUP[0], 10);
+
+  VSET(4, e32, m1);
+  VLOAD_32(v2, 0xF, 0, 0, 0);
+  asm volatile("vpopc.m %[A], v2 \n"
+               "sw %[A], (%1) \n"
+               :
+               : [A] "r"(scalar), "r"(OUP));
+  XCMP(8, OUP[0], 4);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+  enable_fp();
+  TEST_CASE1();
+  TEST_CASE2();
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vdiv.c b/apps/riscv-tests/isa/rv64uv/vdiv.c
new file mode 100644
index 0000000..74a8b57
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vdiv.c
@@ -0,0 +1,232 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xcd, 0x42, 0x2c, 0xc4, 0x7a, 0x7b, 0xd1, 0x21, 0x38, 0x1d, 0x2e,
+          0x4f, 0xe7, 0x3d, 0x63, 0xd8);
+  VLOAD_8(v3, 0x11, 0xa1, 0x7c, 0xde, 0x02, 0x38, 0x4e, 0x03, 0x1e, 0xc6, 0x16,
+          0xa0, 0xca, 0x83, 0x54, 0x90);
+  asm volatile("vdiv.vv v1, v2, v3");
+  VCMP_I8(1, v1, 0xfd, 0x00, 0x00, 0x01, 0x3d, 0x02, 0x00, 0x0b, 0x01, 0x00,
+          0x02, 0x00, 0x00, 0x00, 0x01, 0x00);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x9e55, 0xf806, 0xa137, 0xa5fc, 0x38ae, 0x58c3, 0x2a66, 0x6bd7,
+           0x74e7, 0xa845, 0x2052, 0x6f9a, 0x6d88, 0x2861, 0xdaea, 0x2075);
+  VLOAD_16(v3, 0x5e64, 0x0a44, 0xdde5, 0x813f, 0x78b9, 0x29be, 0x28b4, 0x1b2f,
+           0xc4a3, 0x4a05, 0x5501, 0x49bb, 0xe5f8, 0xfa20, 0x4edf, 0xf892);
+  asm volatile("vdiv.vv v1, v2, v3");
+  VCMP_I16(2, v1, 0xffff, 0x0000, 0x0002, 0x0000, 0x0000, 0x0002, 0x0001,
+           0x0003, 0xffff, 0xffff, 0x0000, 0x0001, 0xfffc, 0xfffa, 0x0000,
+           0xfffc);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0xed578a38, 0xba7b1912, 0xb99934ef, 0x21a85df9, 0xb01c09f2,
+           0xd0cb54fc, 0x9b617331, 0xd32cf029, 0xaea08daa, 0xd76f06e2,
+           0x99b8e084, 0x9fdc6bfc, 0x3103b573, 0xaf1e96b4, 0x54fe9ea1,
+           0x0ceff9c0);
+  VLOAD_32(v3, 0x0000002d, 0x0000001e, 0x0000003e, 0xffffffe0, 0x0000004b,
+           0x00000064, 0xffffff88, 0x0000003b, 0x00000011, 0xffffffc3,
+           0xffffffa2, 0x0000004b, 0xffffffcc, 0xffffffb1, 0xffffff9d,
+           0xffffffba);
+  asm volatile("vdiv.vv v1, v2, v3");
+  VCMP_I32(3, v1, 0xff95db40, 0xfdaec51b, 0xfedd4f4f, 0xfef2bd11, 0xfeef4ea4,
+           0xff872740, 0x00d6a792, 0xff3d81e7, 0xfb369eec, 0x00aa3ed6,
+           0x01168b3a, 0xfeb7d87b, 0xff0eb2ab, 0x01061804, 0xff24374a,
+           0xffd0afa2);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x7954dd7fc5e0687c, 0xfcf310f44f869aa0, 0x375fcbcf6aae0cac,
+           0x6038c1825cfb5a72, 0x59046c6b324e7fb3, 0xbac247d729fb18e6,
+           0x0cecf04984784b3f, 0x2cd8e8ea5be0c201, 0xcab2cf17c48b57cb,
+           0xcb53d1b55097656d, 0xbeeb18a6fab9af8d, 0xbf94f3a0fa74670b,
+           0x817c1dfb5ab3bfd7, 0x40951ef6459642d1, 0x4b5f994556f6ba42,
+           0x63a8eaa417e6d29c);
+  VLOAD_64(v3, 0xffffff9bd8e00c88, 0x0000002057c200e4, 0x0000004c4c93640e,
+           0x000000497b7bfcdd, 0x00000001feebe76a, 0xffffffb93a2c242c,
+           0xffffff8523c47d2a, 0x00000019f01c4433, 0xffffffd940862ecc,
+           0x00000016ac4df9c8, 0x0000001e9f15d00c, 0xffffffd0af22d791,
+           0xffffff9feca249bc, 0xffffffac5eae7985, 0x0000003567fe8027,
+           0x000000175355cab3);
+  asm volatile("vdiv.vv v1, v2, v3");
+  VCMP_I64(4, v1, 0xfffffffffec9dd87, 0xffffffffffe7dac0, 0x0000000000b9cad9,
+           0x00000000014f3850, 0x000000002c9a4382, 0x0000000000fa75a9,
+           0xffffffffffe51146, 0x0000000001baa14f, 0x000000000160270e,
+           0xfffffffffdad470e, 0xfffffffffddfe832, 0x00000000015c87ee,
+           0x0000000001511bae, 0xffffffffff3a4e84, 0x0000000001694c75,
+           0x000000000445c6cf);
+};
+
+void TEST_CASE2(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xcd, 0x42, 0x2c, 0xc4, 0x7a, 0x7b, 0xd1, 0x21, 0x38, 0x1d, 0x2e,
+          0x4f, 0xe7, 0x3d, 0x63, 0xd8);
+  VLOAD_8(v3, 0x11, 0xa1, 0x7c, 0xde, 0x02, 0x38, 0x4e, 0x03, 0x1e, 0xc6, 0x16,
+          0xa0, 0xca, 0x83, 0x54, 0x90);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vdiv.vv v1, v2, v3, v0.t");
+  VCMP_I8(5, v1, 0, 0x00, 0, 0x01, 0, 0x02, 0, 0x0b, 0, 0x00, 0, 0x00, 0, 0x00,
+          0, 0x00);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x9e55, 0xf806, 0xa137, 0xa5fc, 0x38ae, 0x58c3, 0x2a66, 0x6bd7,
+           0x74e7, 0xa845, 0x2052, 0x6f9a, 0x6d88, 0x2861, 0xdaea, 0x2075);
+  VLOAD_16(v3, 0x5e64, 0x0a44, 0xdde5, 0x813f, 0x78b9, 0x29be, 0x28b4, 0x1b2f,
+           0xc4a3, 0x4a05, 0x5501, 0x49bb, 0xe5f8, 0xfa20, 0x4edf, 0xf892);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vdiv.vv v1, v2, v3, v0.t");
+  VCMP_I16(6, v1, 0, 0x0000, 0, 0x0000, 0, 0x0002, 0, 0x0003, 0, 0xffff, 0,
+           0x0001, 0, 0xfffa, 0, 0xfffc);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0xed578a38, 0xba7b1912, 0xb99934ef, 0x21a85df9, 0xb01c09f2,
+           0xd0cb54fc, 0x9b617331, 0xd32cf029, 0xaea08daa, 0xd76f06e2,
+           0x99b8e084, 0x9fdc6bfc, 0x3103b573, 0xaf1e96b4, 0x54fe9ea1,
+           0x0ceff9c0);
+  VLOAD_32(v3, 0x0000002d, 0x0000001e, 0x0000003e, 0xffffffe0, 0x0000004b,
+           0x00000064, 0xffffff88, 0x0000003b, 0x00000011, 0xffffffc3,
+           0xffffffa2, 0x0000004b, 0xffffffcc, 0xffffffb1, 0xffffff9d,
+           0xffffffba);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vdiv.vv v1, v2, v3, v0.t");
+  VCMP_I32(7, v1, 0, 0xfdaec51b, 0, 0xfef2bd11, 0, 0xff872740, 0, 0xff3d81e7, 0,
+           0x00aa3ed6, 0, 0xfeb7d87b, 0, 0x01061804, 0, 0xffd0afa2);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x7954dd7fc5e0687c, 0xfcf310f44f869aa0, 0x375fcbcf6aae0cac,
+           0x6038c1825cfb5a72, 0x59046c6b324e7fb3, 0xbac247d729fb18e6,
+           0x0cecf04984784b3f, 0x2cd8e8ea5be0c201, 0xcab2cf17c48b57cb,
+           0xcb53d1b55097656d, 0xbeeb18a6fab9af8d, 0xbf94f3a0fa74670b,
+           0x817c1dfb5ab3bfd7, 0x40951ef6459642d1, 0x4b5f994556f6ba42,
+           0x63a8eaa417e6d29c);
+  VLOAD_64(v3, 0xffffff9bd8e00c88, 0x0000002057c200e4, 0x0000004c4c93640e,
+           0x000000497b7bfcdd, 0x00000001feebe76a, 0xffffffb93a2c242c,
+           0xffffff8523c47d2a, 0x00000019f01c4433, 0xffffffd940862ecc,
+           0x00000016ac4df9c8, 0x0000001e9f15d00c, 0xffffffd0af22d791,
+           0xffffff9feca249bc, 0xffffffac5eae7985, 0x0000003567fe8027,
+           0x000000175355cab3);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vdiv.vv v1, v2, v3, v0.t");
+  VCMP_I64(8, v1, 0, 0xffffffffffe7dac0, 0, 0x00000000014f3850, 0,
+           0x0000000000fa75a9, 0, 0x0000000001baa14f, 0, 0xfffffffffdad470e, 0,
+           0x00000000015c87ee, 0, 0xffffffffff3a4e84, 0, 0x000000000445c6cf);
+};
+
+void TEST_CASE3(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x14, 0xab, 0x4d, 0xcd, 0xc3, 0x7c, 0xb5, 0xf0, 0xc1, 0x90, 0x14,
+          0x59, 0x98, 0xda, 0x76, 0x84);
+  int64_t scalar = 5;
+  asm volatile("vdiv.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_I8(9, v1, 0x04, 0xef, 0x0f, 0xf6, 0xf4, 0x18, 0xf1, 0xfd, 0xf4, 0xea,
+          0x04, 0x11, 0xec, 0xf9, 0x17, 0xe8);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x19c9, 0x865a, 0x3063, 0xd5c2, 0xbe39, 0x98c7, 0x1ca7, 0x5d1e,
+           0x8fdc, 0x3396, 0x9442, 0xee77, 0x7da8, 0xf200, 0xaba3, 0x4cd6);
+  scalar = -538;
+  asm volatile("vdiv.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_I16(10, v1, 0xfff4, 0x0039, 0xffe9, 0x0014, 0x001f, 0x0031, 0xfff3,
+           0xffd4, 0x0035, 0xffe8, 0x0033, 0x0008, 0xffc5, 0x0006, 0x0028,
+           0xffdc);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x49dd393c, 0xfc1d701e, 0x7670b541, 0x5ef6c28f, 0x60da5cab,
+           0x6be56bc4, 0x6f629cde, 0xf1ab595a, 0x3d99363b, 0xb8a7840e,
+           0x84071026, 0x6697d435, 0x3768cf44, 0x82f1a5a1, 0xf5d4f40e,
+           0xcda97e6d);
+  scalar = 649;
+  asm volatile("vdiv.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_I32(11, v1, 0x001d22cc, 0xfffe77b2, 0x002eb818, 0x00257573, 0x00263435,
+           0x002a8f5a, 0x002befac, 0xfffa58e4, 0x00184c36, 0xffe3db85,
+           0xffcf1946, 0x002877d8, 0x0015db3d, 0xffceabd8, 0xfffbfd39,
+           0xffec24e2);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0xeea1bad034de2c3e, 0x5acd284816152166, 0x52a24c3b98af20f9,
+           0x843d3c2e39d3221e, 0xda6c4bef77118459, 0x8c7e991a77cc3ddc,
+           0x58f56c82eceafc72, 0xb4b1bac0a66d4984, 0x126283c905985ab8,
+           0x3a859a64dbdb137e, 0x46674604f440792d, 0x04b1df734a3f312a,
+           0xde91f735ce81d174, 0x3d254eb16d0c87f4, 0xc06ebbe7936e6774,
+           0xb17ccbc475c8724e);
+  scalar = -59223;
+  asm volatile("vdiv.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_I64(12, v1, 0x000013383ad25844, 0xffff9b84f9ef594c, 0xffffa48eb726f738,
+           0x000088f40e45bbd1, 0x0000299522c72a62, 0x00007fd16a16b1db,
+           0xffff9d8efec5cf15, 0x000053554738ae55, 0xffffeba7c8cdd664,
+           0xffffbf3d66c69bdf, 0xffffb2177f70bf18, 0xffffface02d012e3,
+           0x000024fe4bc4a5dc, 0xffffbc56186f1f3d, 0x00004657f2ee1ea3,
+           0x000056e1b88b70d9);
+};
+
+void TEST_CASE4(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x14, 0xab, 0x4d, 0xcd, 0xc3, 0x7c, 0xb5, 0xf0, 0xc1, 0x90, 0x14,
+          0x59, 0x98, 0xda, 0x76, 0x84);
+  int64_t scalar = 5;
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vdiv.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_I8(13, v1, 0, 0xef, 0, 0xf6, 0, 0x18, 0, 0xfd, 0, 0xea, 0, 0x11, 0, 0xf9,
+          0, 0xe8);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x19c9, 0x865a, 0x3063, 0xd5c2, 0xbe39, 0x98c7, 0x1ca7, 0x5d1e,
+           0x8fdc, 0x3396, 0x9442, 0xee77, 0x7da8, 0xf200, 0xaba3, 0x4cd6);
+  scalar = -538;
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vdiv.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_I16(14, v1, 0, 0x0039, 0, 0x0014, 0, 0x0031, 0, 0xffd4, 0, 0xffe8, 0,
+           0x0008, 0, 0x0006, 0, 0xffdc);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x49dd393c, 0xfc1d701e, 0x7670b541, 0x5ef6c28f, 0x60da5cab,
+           0x6be56bc4, 0x6f629cde, 0xf1ab595a, 0x3d99363b, 0xb8a7840e,
+           0x84071026, 0x6697d435, 0x3768cf44, 0x82f1a5a1, 0xf5d4f40e,
+           0xcda97e6d);
+  scalar = 649;
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vdiv.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_I32(15, v1, 0, 0xfffe77b2, 0, 0x00257573, 0, 0x002a8f5a, 0, 0xfffa58e4,
+           0, 0xffe3db85, 0, 0x002877d8, 0, 0xffceabd8, 0, 0xffec24e2);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0xeea1bad034de2c3e, 0x5acd284816152166, 0x52a24c3b98af20f9,
+           0x843d3c2e39d3221e, 0xda6c4bef77118459, 0x8c7e991a77cc3ddc,
+           0x58f56c82eceafc72, 0xb4b1bac0a66d4984, 0x126283c905985ab8,
+           0x3a859a64dbdb137e, 0x46674604f440792d, 0x04b1df734a3f312a,
+           0xde91f735ce81d174, 0x3d254eb16d0c87f4, 0xc06ebbe7936e6774,
+           0xb17ccbc475c8724e);
+  scalar = -59223;
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vdiv.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_I64(16, v1, 0, 0xffff9b84f9ef594c, 0, 0x000088f40e45bbd1, 0,
+           0x00007fd16a16b1db, 0, 0x000053554738ae55, 0, 0xffffbf3d66c69bdf, 0,
+           0xffffface02d012e3, 0, 0xffffbc56186f1f3d, 0, 0x000056e1b88b70d9);
+};
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vdivu.c b/apps/riscv-tests/isa/rv64uv/vdivu.c
new file mode 100644
index 0000000..89f50a3
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vdivu.c
@@ -0,0 +1,232 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x85, 0x1d, 0x9f, 0x31, 0x8c, 0x4c, 0x4c, 0xf2, 0x11, 0xfc, 0xc8,
+          0xab, 0xc2, 0xff, 0xf5, 0xc2);
+  VLOAD_8(v3, 0x3d, 0x06, 0x32, 0x36, 0x02, 0x0f, 0x27, 0x35, 0x1e, 0x0f, 0x36,
+          0x1c, 0x24, 0x1a, 0x22, 0x01);
+  asm volatile("vdivu.vv v1, v2, v3");
+  VCMP_I8(1, v1, 0x02, 0x04, 0x03, 0x00, 0x46, 0x05, 0x01, 0x04, 0x00, 0x10,
+          0x03, 0x06, 0x05, 0x09, 0x07, 0xc2);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0xd200, 0xa047, 0x7af8, 0x453d, 0xd6eb, 0xfabb, 0x604a, 0xea35,
+           0xbc2d, 0x45e7, 0x8407, 0x3845, 0x1495, 0x8ee6, 0x7da4, 0xf34a);
+  VLOAD_16(v3, 0x03ad, 0x00b8, 0x001b, 0x0353, 0x013f, 0x008c, 0x015e, 0x01e6,
+           0x00cd, 0x0093, 0x00ba, 0x03d0, 0x0117, 0x009d, 0x007b, 0x02cf);
+  asm volatile("vdivu.vv v1, v2, v3");
+  VCMP_I16(2, v1, 0x0039, 0x00de, 0x048d, 0x0014, 0x00ac, 0x01ca, 0x0046,
+           0x007b, 0x00ea, 0x0079, 0x00b5, 0x000e, 0x0012, 0x00e9, 0x0105,
+           0x0056);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0xd56bd03a, 0x1036c5ff, 0xaa01847f, 0x988dc35d, 0x4d8615dc,
+           0xb62269e2, 0xe842ba75, 0x02fecbf9, 0xe536c712, 0xe93e2160,
+           0x9ba34297, 0x554d290d, 0x319f668c, 0x0d6c2fbb, 0x6a7eb54a,
+           0x3fa1cc84);
+  VLOAD_32(v3, 0x00000025, 0x00000057, 0x0000002e, 0x0000004c, 0x00000052,
+           0x00000021, 0x0000001d, 0x0000002f, 0x00000029, 0x00000008,
+           0x00000015, 0x00000029, 0x00000048, 0x00000051, 0x0000003f,
+           0x00000007);
+  asm volatile("vdivu.vv v1, v2, v3");
+  VCMP_I32(3, v1, 0x05c4a4c3, 0x002fb5c5, 0x03b21eb4, 0x0201dd84, 0x00f20682,
+           0x0584ebef, 0x08024d0c, 0x00105098, 0x05973090, 0x1d27c42c,
+           0x07694c50, 0x02149d19, 0x00b06fa5, 0x002a6c0b, 0x01b0bdcc,
+           0x09171d37);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0xf251717441f02108, 0x2668b5d7f073b9d1, 0x4708b49fd356a60a,
+           0x195bedcb9ce5956b, 0x41ce2b35b4280568, 0x32e5b89eed21de3b,
+           0x73f17f3d0e1f243f, 0x0d0aa119af3b0e95, 0x024cbba6ba662213,
+           0xf7df98f44da5e55f, 0x3cf2951aa7e4c0a9, 0x0ed8987446e84f30,
+           0xd983a7a0d4c648b4, 0x60eb8249069801a5, 0x529967e8b06df477,
+           0x776410b4b0cc22ad);
+  VLOAD_64(v3, 0x000000000000695b, 0x0000000000007420, 0x000000000001850c,
+           0x000000000000b46f, 0x000000000000e92c, 0x0000000000024e72,
+           0x0000000000032774, 0x000000000001c36f, 0x00000000000063d2,
+           0x0000000000037bb4, 0x000000000003692c, 0x000000000001d60c,
+           0x000000000002cf7b, 0x0000000000037899, 0x0000000000038bcf,
+           0x000000000003d0e4);
+  asm volatile("vdivu.vv v1, v2, v3");
+  VCMP_I64(4, v1, 0x00024ccd25dd5faf, 0x000054ac6a930494, 0x00002ebddee9df57,
+           0x000023fac7321f85, 0x0000483f73b2e3e2, 0x000016114f5d8a9e,
+           0x000024c26869df0e, 0x00000765470f410f, 0x000005e5de9b769d,
+           0x0000472988fa89c3, 0x000011de6d57a394, 0x00000815e7b8df73,
+           0x00004d64ede3b4a6, 0x00001bec0e79307a, 0x0000174af5139f58,
+           0x00001f497ec0ff30);
+};
+
+void TEST_CASE2(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x85, 0x1d, 0x9f, 0x31, 0x8c, 0x4c, 0x4c, 0xf2, 0x11, 0xfc, 0xc8,
+          0xab, 0xc2, 0xff, 0xf5, 0xc2);
+  VLOAD_8(v3, 0x3d, 0x06, 0x32, 0x36, 0x02, 0x0f, 0x27, 0x35, 0x1e, 0x0f, 0x36,
+          0x1c, 0x24, 0x1a, 0x22, 0x01);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vdivu.vv v1, v2, v3, v0.t");
+  VCMP_I8(5, v1, 0, 0x04, 0, 0x00, 0, 0x05, 0, 0x04, 0, 0x10, 0, 0x06, 0, 0x09,
+          0, 0xc2);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0xd200, 0xa047, 0x7af8, 0x453d, 0xd6eb, 0xfabb, 0x604a, 0xea35,
+           0xbc2d, 0x45e7, 0x8407, 0x3845, 0x1495, 0x8ee6, 0x7da4, 0xf34a);
+  VLOAD_16(v3, 0x03ad, 0x00b8, 0x001b, 0x0353, 0x013f, 0x008c, 0x015e, 0x01e6,
+           0x00cd, 0x0093, 0x00ba, 0x03d0, 0x0117, 0x009d, 0x007b, 0x02cf);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vdivu.vv v1, v2, v3, v0.t");
+  VCMP_I16(6, v1, 0, 0x00de, 0, 0x0014, 0, 0x01ca, 0, 0x007b, 0, 0x0079, 0,
+           0x000e, 0, 0x00e9, 0, 0x0056);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0xd56bd03a, 0x1036c5ff, 0xaa01847f, 0x988dc35d, 0x4d8615dc,
+           0xb62269e2, 0xe842ba75, 0x02fecbf9, 0xe536c712, 0xe93e2160,
+           0x9ba34297, 0x554d290d, 0x319f668c, 0x0d6c2fbb, 0x6a7eb54a,
+           0x3fa1cc84);
+  VLOAD_32(v3, 0x00000025, 0x00000057, 0x0000002e, 0x0000004c, 0x00000052,
+           0x00000021, 0x0000001d, 0x0000002f, 0x00000029, 0x00000008,
+           0x00000015, 0x00000029, 0x00000048, 0x00000051, 0x0000003f,
+           0x00000007);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vdivu.vv v1, v2, v3, v0.t");
+  VCMP_I32(7, v1, 0, 0x002fb5c5, 0, 0x0201dd84, 0, 0x0584ebef, 0, 0x00105098, 0,
+           0x1d27c42c, 0, 0x02149d19, 0, 0x002a6c0b, 0, 0x09171d37);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0xf251717441f02108, 0x2668b5d7f073b9d1, 0x4708b49fd356a60a,
+           0x195bedcb9ce5956b, 0x41ce2b35b4280568, 0x32e5b89eed21de3b,
+           0x73f17f3d0e1f243f, 0x0d0aa119af3b0e95, 0x024cbba6ba662213,
+           0xf7df98f44da5e55f, 0x3cf2951aa7e4c0a9, 0x0ed8987446e84f30,
+           0xd983a7a0d4c648b4, 0x60eb8249069801a5, 0x529967e8b06df477,
+           0x776410b4b0cc22ad);
+  VLOAD_64(v3, 0x000000000000695b, 0x0000000000007420, 0x000000000001850c,
+           0x000000000000b46f, 0x000000000000e92c, 0x0000000000024e72,
+           0x0000000000032774, 0x000000000001c36f, 0x00000000000063d2,
+           0x0000000000037bb4, 0x000000000003692c, 0x000000000001d60c,
+           0x000000000002cf7b, 0x0000000000037899, 0x0000000000038bcf,
+           0x000000000003d0e4);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vdivu.vv v1, v2, v3, v0.t");
+  VCMP_I64(8, v1, 0, 0x000054ac6a930494, 0, 0x000023fac7321f85, 0,
+           0x000016114f5d8a9e, 0, 0x00000765470f410f, 0, 0x0000472988fa89c3, 0,
+           0x00000815e7b8df73, 0, 0x00001bec0e79307a, 0, 0x00001f497ec0ff30);
+};
+
+void TEST_CASE3(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x0f, 0xbd, 0x0a, 0x58, 0x8e, 0x09, 0xa7, 0x02, 0x4b, 0xe8, 0xd2,
+          0xfc, 0xa9, 0x8e, 0x67, 0x49);
+  uint64_t scalar = 5;
+  asm volatile("vdivu.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_I8(9, v1, 0x03, 0x25, 0x02, 0x11, 0x1c, 0x01, 0x21, 0x00, 0x0f, 0x2e,
+          0x2a, 0x32, 0x21, 0x1c, 0x14, 0x0e);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0xcf2f, 0x0c02, 0x1417, 0x1747, 0x5e43, 0x9552, 0xe03e, 0x5367,
+           0xb2f9, 0x09d8, 0x3b19, 0x8ed0, 0x4740, 0xa628, 0x5560, 0x713b);
+  scalar = 538;
+  asm volatile("vdivu.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_I16(10, v1, 0x0062, 0x0005, 0x0009, 0x000b, 0x002c, 0x0047, 0x006a,
+           0x0027, 0x0055, 0x0004, 0x001c, 0x0043, 0x0021, 0x004f, 0x0028,
+           0x0035);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x643498d4, 0xe1e4c6d4, 0x2fef6b6f, 0xe68ef651, 0x9943599a,
+           0x68af922e, 0x09a3beb2, 0x117ff561, 0x86a1a3f7, 0x03566f4f,
+           0xc3c0c7de, 0x8cb524f8, 0x532e1652, 0xb0c26bf2, 0x886d0b1c,
+           0xf94d6b63);
+  scalar = 649;
+  asm volatile("vdivu.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_I32(11, v1, 0x002786be, 0x00591abc, 0x0012e87f, 0x005af1c8, 0x003c7480,
+           0x00294b2b, 0x0003cd68, 0x0006e722, 0x00351b13, 0x00015108,
+           0x004d3723, 0x003780a6, 0x0020cf84, 0x0045b92a, 0x0035d049,
+           0x0062568c);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x751ea878eaf9f85f, 0x9843aba4c3e313af, 0xc2f56d78083dc0f2,
+           0x4fcb920a2a4ebc8d, 0x33a71e7364643a7c, 0x76f96f8403af4ad7,
+           0xcdbbb2002ea6ac93, 0xc380d0b6a5182bcc, 0x93b79fcc64af88cf,
+           0x85d32b075e613f6c, 0x4f1f75bfa6d8f319, 0xd2a34a8d9a02d7f1,
+           0x8679a27b237a032e, 0x7e0881a487bbb235, 0x17d97d9849271cec,
+           0x1c85ac87ba3c7d1e);
+  scalar = 9223;
+  asm volatile("vdivu.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_I64(12, v1, 0x000340383152452b, 0x000439f263aaf34a, 0x000569521e089c7c,
+           0x0002370079144c76, 0x00016f07b37c5546, 0x00034d65d36c535c,
+           0x0005b5e194247d88, 0x00056d3090f69ef0, 0x000419a3026cfde7,
+           0x0003b6ebd974c870, 0x000232398140d5dd, 0x0005d8bb7bec2e99,
+           0x0003bb8ab6abb03a, 0x00037f8e5aab0783, 0x0000a977deb32c78,
+           0x0000caab9b4a8885);
+};
+
+void TEST_CASE4(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x0f, 0xbd, 0x0a, 0x58, 0x8e, 0x09, 0xa7, 0x02, 0x4b, 0xe8, 0xd2,
+          0xfc, 0xa9, 0x8e, 0x67, 0x49);
+  uint64_t scalar = 5;
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vdivu.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_I8(13, v1, 0, 0x25, 0, 0x11, 0, 0x01, 0, 0x00, 0, 0x2e, 0, 0x32, 0, 0x1c,
+          0, 0x0e);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0xcf2f, 0x0c02, 0x1417, 0x1747, 0x5e43, 0x9552, 0xe03e, 0x5367,
+           0xb2f9, 0x09d8, 0x3b19, 0x8ed0, 0x4740, 0xa628, 0x5560, 0x713b);
+  scalar = 538;
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vdivu.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_I16(14, v1, 0, 0x0005, 0, 0x000b, 0, 0x0047, 0, 0x0027, 0, 0x0004, 0,
+           0x0043, 0, 0x004f, 0, 0x0035);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x643498d4, 0xe1e4c6d4, 0x2fef6b6f, 0xe68ef651, 0x9943599a,
+           0x68af922e, 0x09a3beb2, 0x117ff561, 0x86a1a3f7, 0x03566f4f,
+           0xc3c0c7de, 0x8cb524f8, 0x532e1652, 0xb0c26bf2, 0x886d0b1c,
+           0xf94d6b63);
+  scalar = 649;
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vdivu.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_I32(15, v1, 0, 0x00591abc, 0, 0x005af1c8, 0, 0x00294b2b, 0, 0x0006e722,
+           0, 0x00015108, 0, 0x003780a6, 0, 0x0045b92a, 0, 0x0062568c);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x751ea878eaf9f85f, 0x9843aba4c3e313af, 0xc2f56d78083dc0f2,
+           0x4fcb920a2a4ebc8d, 0x33a71e7364643a7c, 0x76f96f8403af4ad7,
+           0xcdbbb2002ea6ac93, 0xc380d0b6a5182bcc, 0x93b79fcc64af88cf,
+           0x85d32b075e613f6c, 0x4f1f75bfa6d8f319, 0xd2a34a8d9a02d7f1,
+           0x8679a27b237a032e, 0x7e0881a487bbb235, 0x17d97d9849271cec,
+           0x1c85ac87ba3c7d1e);
+  scalar = 9223;
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vdivu.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_I64(16, v1, 0, 0x000439f263aaf34a, 0, 0x0002370079144c76, 0,
+           0x00034d65d36c535c, 0, 0x00056d3090f69ef0, 0, 0x0003b6ebd974c870, 0,
+           0x0005d8bb7bec2e99, 0, 0x00037f8e5aab0783, 0, 0x0000caab9b4a8885);
+};
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vfadd.c b/apps/riscv-tests/isa/rv64uv/vfadd.c
new file mode 100644
index 0000000..d48ca8e
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vfadd.c
@@ -0,0 +1,463 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+// Notes: hard to check if FS is Dirtied by the first vector FP instruction
+// since it is not accessible in U mode and it is dirtied before the first vfp
+// operation
+
+// Simple random test with similar values + 1 subnormal
+void TEST_CASE1(void) {
+  /*
+    VSET(16, e8, m1);
+    // Enable this test only with 8-bit floating-point support on
+    VLOAD_8(v2, 0b11001100, 0b01011011, 0b11001100, 0b01011011, 0b11001100,
+    0b01011011, 0b11001100, 0b01011011, 0b11001100, 0b01011011, 0b11001100,
+    0b01011011, 0b11001100, 0b01011011, 0b11001100, 0b01011011); VLOAD_8(v3,
+    0b01011011, 0b11001100, 0b01011011, 0b11001100, 0b01011011, 0b11001100,
+    0b01011011, 0b11001100, 0b01011011, 0b11001100, 0b01011011, 0b11001100,
+    0b01011011, 0b11001100, 0b01011011, 0b11001100); asm volatile("vfadd.vv v1,
+    v2, v3"); VCMP_U8(0, v1, 0b01011010, 0b01011010, 0b01011010, 0b01011010,
+    0b01011010, 0b01011010, 0b01011010, 0b01011010, 0b01011010, 0b01011010,
+    0b01011010, 0b01011010, 0b01011010, 0b01011010, 0b01011010, 0b01011010);
+  */
+
+  VSET(16, e16, m1);
+  //             -0.8896, -0.3406,  0.7324, -0.6846, -0.2969, -0.7739,  0.5737,
+  //             0.4331,  0.8940, -0.4900,  0.4219,  0.4639,  0.6694,  0.4382,
+  //             0.1356,  0.5337
+  VLOAD_16(v2, 0xbb1e, 0xb573, 0x39dc, 0xb97a, 0xb4c0, 0xba31, 0x3897, 0x36ee,
+           0x3b27, 0xb7d7, 0x36c0, 0x376c, 0x395b, 0x3703, 0x3057, 0x0001);
+  //             -0.8164,  0.6533, -0.4685,  0.6284,  0.1666,  0.9438,  0.0445,
+  //             -0.1342, -0.8071, -0.3167, -0.8350,  0.2178, -0.0896, -0.3057,
+  //             -0.3064,  0.2073
+  VLOAD_16(v3, 0xba88, 0x393a, 0xb77f, 0x3907, 0x3155, 0x3b8d, 0x29b3, 0xb04b,
+           0xba75, 0xb511, 0xbaae, 0x32f8, 0xadbc, 0xb4e4, 0xb4e7, 0x8010);
+  asm volatile("vfadd.vv v1, v2, v3");
+  //             -1.7061,  0.3127,  0.2639, -0.0562, -0.1302,  0.1699,  0.6182,
+  //             0.2988,  0.0869, -0.8066, -0.4131,  0.6816,  0.5801,  0.1326,
+  //             -0.1708,  0.7412
+  VCMP_U16(1, v1, 0xbed3, 0x3501, 0x3439, 0xab30, 0xb02b, 0x3170, 0x38f2,
+           0x34c8, 0x2d90, 0xba74, 0xb69c, 0x3974, 0x38a4, 0x303e, 0xb177,
+           0x800f);
+
+  VSET(16, e32, m1);
+  //             -0.28968573,  0.40292332,  0.33936000,  0.53889370, 0.39942014,
+  //             -0.27004066,  0.78120714, -0.15632398, -0.49984047,
+  //             -0.69259918, -0.03384063, -0.62385744,  0.00338853, 0.33711585,
+  //             -0.34673852,  0.11450682
+  VLOAD_32(v2, 0xbe9451b0, 0x3ece4bf7, 0x3eadc098, 0x3f09f4f0, 0x3ecc80cc,
+           0xbe8a42c5, 0x3f47fd31, 0xbe201365, 0xbeffeb17, 0xbf314e2e,
+           0xbd0a9c78, 0xbf1fb51f, 0x3b5e1209, 0x3eac9a73, 0xbeb187b6,
+           0x3dea828d);
+  //             -0.62142891,  0.63306540,  0.26511025,  0.85738784,
+  //             -0.78492641, -0.44331804, -0.84668529,  0.13981950, 0.84909225,
+  //             0.23569171,  0.34283128,  0.56619811,  0.22596644,  0.55843508,
+  //             0.53194439,  0.02510819
+  VLOAD_32(v3, 0xbf1f15f7, 0x3f221093, 0x3e87bc88, 0x3f5b7dc5, 0xbf48f0f0,
+           0xbee2fa95, 0xbf58c05e, 0x3e0f2cd8, 0x3f595e1c, 0x3e71592b,
+           0x3eaf8795, 0x3f10f25c, 0x3e6763bf, 0x3f0ef59a, 0x3f082d82,
+           0x3ccdafb0);
+  asm volatile("vfadd.vv v1, v2, v3");
+  //             -0.91111463,  1.03598869,  0.60447025,  1.39628148,
+  //             -0.38550627, -0.71335870, -0.06547815, -0.01650448, 0.34925178,
+  //             -0.45690745,  0.30899066, -0.05765933,  0.22935496, 0.89555097,
+  //             0.18520588,  0.13961500
+  VCMP_U32(2, v1, 0xbf693ecf, 0x3f849b47, 0x3f1abe90, 0x3fb2b95a, 0xbec56114,
+           0xbf369ead, 0xbd861968, 0xbc873468, 0x3eb2d121, 0xbee9efc6,
+           0x3e9e3406, 0xbd6c2c30, 0x3e6adc07, 0x3f6542d4, 0x3e3da69c,
+           0x3e0ef73c);
+
+  VSET(16, e64, m1);
+  //             -0.1192486190170796,  0.7099687505713703, -0.6001652243371716,
+  //             -0.9559723926483070,  0.7987976623002717, -0.3314459653039117,
+  //             0.7678805321182058, -0.3118871679402779, -0.7580588930783800,
+  //             0.5940681950113129,  0.6471754222100761,  0.4175915562917139,
+  //             -0.3690504607938143,  0.0740574148132984, -0.1493616685664843,
+  //             0.3560295367616439
+  VLOAD_64(v2, 0xbfbe8713d6c58260, 0x3fe6b810629c5a40, 0xbfe3348db3573060,
+           0xbfee97536a49b50a, 0x3fe98fc01d766dee, 0xbfd536692357c5dc,
+           0x3fe8927a3195d944, 0xbfd3f5f598961d8c, 0xbfe84204b946d5d6,
+           0x3fe3029b4da55ad8, 0x3fe4b5a93b255a44, 0x3fdab9d1ef56f430,
+           0xbfd79e85d2ebb8f0, 0x3fb2f56d3ea64090, 0xbfc31e487ce26ff0,
+           0x3fd6c9301c334858);
+  //             -0.7765903295164327,  0.4195489676706889, -0.3911414124398265,
+  //             0.6922029856623244,  0.5664741772288600, -0.1412820433489181,
+  //             -0.1847941224896075, -0.4907136082532593, -0.9146160877742129,
+  //             -0.7130864084314152, -0.5516927493459973, -0.4203081001100177,
+  //             0.6487326796833275, -0.5631384800254344, -0.0996872955425372,
+  //             -0.4382844162164241
+  VLOAD_64(v3, 0xbfe8d9d3f67536d2, 0x3fdad9e3e9cdd5bc, 0xbfd90875fda29450,
+           0x3fe62686e0339faa, 0x3fe2208e74273f2c, 0xbfc21587add90b50,
+           0xbfc7a755744afe30, 0xbfdf67da0cc99808, 0xbfed4488f52c57bc,
+           0xbfe6d19a966debbe, 0xbfe1a7778d7c344c, 0xbfdae653f20dd9d4,
+           0x3fe4c26b0962c342, 0xbfe2053afd5a822c, 0xbfb9851b4a2e8ff0,
+           0xbfdc0cda147fbe5c);
+  asm volatile("vfadd.vv v1, v2, v3");
+  //             -0.8958389485335123,  1.1295177182420593, -0.9913066367769980,
+  //             -0.2637694069859826,  1.3652718395291317, -0.4727280086528298,
+  //             0.5830864096285984, -0.8026007761935372, -1.6726749808525929,
+  //             -0.1190182134201023,  0.0954826728640787, -0.0027165438183039,
+  //             0.2796822188895132, -0.4890810652121360, -0.2490489641090214,
+  //             -0.0822548794547802
+  VCMP_U64(3, v1, 0xbfecaab6714de71e, 0x3ff212812bc1a28f, 0xbfefb8c8b2287a88,
+           0xbfd0e199142c2ac0, 0x3ff5d82748ced68d, 0xbfde412cfa444b84,
+           0x3fe2a8a4d48319b8, 0xbfe9aee7d2afdaca, 0xbffac346d73996c9,
+           0xbfbe77fa46448730, 0x3fb8718d6d492fc0, 0xbf6641015b72d200,
+           0x3fd1e6503fd9cd94, 0xbfdf4d1aab0b7434, 0xbfcfe0d621f9b7e8,
+           0xbfb50ea7e131d810);
+};
+
+// Simple random test with similar values + 1 subnormal (masked)
+// The numbers are the same of TEST_CASE1
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0xbb1e, 0xb573, 0x39dc, 0xb97a, 0xb4c0, 0xba31, 0x3897, 0x36ee,
+           0x3b27, 0xb7d7, 0x36c0, 0x376c, 0x395b, 0x3703, 0x3057, 0x0001);
+  VLOAD_16(v3, 0xba88, 0x393a, 0xb77f, 0x3907, 0x3155, 0x3b8d, 0x29b3, 0xb04b,
+           0xba75, 0xb511, 0xbaae, 0x32f8, 0xadbc, 0xb4e4, 0xb4e7, 0x8010);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfadd.vv v1, v2, v3, v0.t");
+  VCMP_U16(4, v1, 0, 0x3501, 0, 0xab30, 0, 0x3170, 0, 0x34c8, 0, 0xba74, 0,
+           0x3974, 0, 0x303e, 0, 0x800f);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0xbe9451b0, 0x3ece4bf7, 0x3eadc098, 0x3f09f4f0, 0x3ecc80cc,
+           0xbe8a42c5, 0x3f47fd31, 0xbe201365, 0xbeffeb17, 0xbf314e2e,
+           0xbd0a9c78, 0xbf1fb51f, 0x3b5e1209, 0x3eac9a73, 0xbeb187b6,
+           0x3dea828d);
+  VLOAD_32(v3, 0xbf1f15f7, 0x3f221093, 0x3e87bc88, 0x3f5b7dc5, 0xbf48f0f0,
+           0xbee2fa95, 0xbf58c05e, 0x3e0f2cd8, 0x3f595e1c, 0x3e71592b,
+           0x3eaf8795, 0x3f10f25c, 0x3e6763bf, 0x3f0ef59a, 0x3f082d82,
+           0x3ccdafb0);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfadd.vv v1, v2, v3, v0.t");
+  VCMP_U32(5, v1, 0, 0x3f849b47, 0, 0x3fb2b95a, 0, 0xbf369ead, 0, 0xbc873468, 0,
+           0xbee9efc6, 0, 0xbd6c2c30, 0, 0x3f6542d4, 0, 0x3e0ef73c);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0xbfbe8713d6c58260, 0x3fe6b810629c5a40, 0xbfe3348db3573060,
+           0xbfee97536a49b50a, 0x3fe98fc01d766dee, 0xbfd536692357c5dc,
+           0x3fe8927a3195d944, 0xbfd3f5f598961d8c, 0xbfe84204b946d5d6,
+           0x3fe3029b4da55ad8, 0x3fe4b5a93b255a44, 0x3fdab9d1ef56f430,
+           0xbfd79e85d2ebb8f0, 0x3fb2f56d3ea64090, 0xbfc31e487ce26ff0,
+           0x3fd6c9301c334858);
+  VLOAD_64(v3, 0xbfe8d9d3f67536d2, 0x3fdad9e3e9cdd5bc, 0xbfd90875fda29450,
+           0x3fe62686e0339faa, 0x3fe2208e74273f2c, 0xbfc21587add90b50,
+           0xbfc7a755744afe30, 0xbfdf67da0cc99808, 0xbfed4488f52c57bc,
+           0xbfe6d19a966debbe, 0xbfe1a7778d7c344c, 0xbfdae653f20dd9d4,
+           0x3fe4c26b0962c342, 0xbfe2053afd5a822c, 0xbfb9851b4a2e8ff0,
+           0xbfdc0cda147fbe5c);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfadd.vv v1, v2, v3, v0.t");
+  VCMP_U64(6, v1, 0, 0x3ff212812bc1a28f, 0, 0xbfd0e199142c2ac0, 0,
+           0xbfde412cfa444b84, 0, 0xbfe9aee7d2afdaca, 0, 0xbfbe77fa46448730, 0,
+           0xbf6641015b72d200, 0, 0xbfdf4d1aab0b7434, 0, 0xbfb50ea7e131d810);
+};
+
+// Edge-case tests
+void TEST_CASE3(void) {
+  VSET(16, e16, m1);
+  VLOAD_16(v2, pInfh, pInfh, mInfh, qNaNh, pMaxh, pMaxh, pZero, mZeroh, pZero,
+           pMaxh, pZero, qNaNh, mInfh, pInfh, qNaNh, qNaNh);
+  VLOAD_16(v3, mInfh, pInfh, mInfh, pZero, pMaxh, mMaxh, pZero, mZeroh, mZeroh,
+           mZeroh, mMaxh, 0x1, 0xba88, pZero, qNaNh, 0xba88);
+  asm volatile("vfadd.vv v1, v2, v3");
+  VCMP_U16(7, v1, qNaNh, pInfh, mInfh, qNaNh, pInfh, pZero, pZero, mZeroh,
+           pZero, pMaxh, mMaxh, qNaNh, mInfh, pInfh, qNaNh, qNaNh);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, pInff, pInff, mInff, qNaNf, pMaxf, pMaxf, pZero, mZerof, pZero,
+           pMaxf, pZero, qNaNf, mInff, pInff, qNaNf, qNaNf);
+  VLOAD_32(v3, mInff, pInff, mInff, pZero, pMaxf, mMaxf, pZero, mZerof, mZerof,
+           mZerof, mMaxf, 0x1, 0xbf48f0f0, pZero, qNaNf, 0xbf48f0f0);
+  asm volatile("vfadd.vv v1, v2, v3");
+  VCMP_U32(8, v1, qNaNf, pInff, mInff, qNaNf, pInff, pZero, pZero, mZerof,
+           pZero, pMaxf, mMaxf, qNaNf, mInff, pInff, qNaNf, qNaNf);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, pInfd, pInfd, mInfd, qNaNd, pMaxd, pMaxd, pZero, mZerod, pZero,
+           pMaxd, pZero, qNaNd, mInfd, pInfd, qNaNd, qNaNd);
+  VLOAD_64(v3, mInfd, pInfd, mInfd, pZero, pMaxd, mMaxd, pZero, mZerod, mZerod,
+           mZerod, mMaxd, 0x1, 0xbfd90875fda29450, pZero, qNaNd,
+           0xbfd90875fda29450);
+  asm volatile("vfadd.vv v1, v2, v3");
+  VCMP_U64(9, v1, qNaNd, pInfd, mInfd, qNaNd, pInfd, pZero, pZero, mZerod,
+           pZero, pMaxd, mMaxd, qNaNd, mInfd, pInfd, qNaNd, qNaNd);
+};
+
+// Imprecise exceptions
+// If the check is done immediately after the vector instruction, it fails as it
+// is completed before the "faulty" operations are executed by Ara's FPU
+void TEST_CASE4(void) {
+  // Overflow + Inexact
+  CLEAR_FFLAGS;
+  VSET(16, e16, m1);
+  CHECK_FFLAGS(0);
+  VLOAD_16(v2, pMaxh, pMaxh, pMaxh, pMaxh, pMaxh, pMaxh, pMaxh, pMaxh, pMaxh,
+           pMaxh, pMaxh, pMaxh, pMaxh, pMaxh, pMaxh, pMaxh);
+  VLOAD_16(v3, pMaxh, pMaxh, pMaxh, pMaxh, pMaxh, pMaxh, pMaxh, pMaxh, pMaxh,
+           pMaxh, pMaxh, pMaxh, pMaxh, pMaxh, pMaxh, pMaxh);
+  asm volatile("vfadd.vv v1, v2, v3");
+  VCMP_U16(10, v1, pInfh, pInfh, pInfh, pInfh, pInfh, pInfh, pInfh, pInfh,
+           pInfh, pInfh, pInfh, pInfh, pInfh, pInfh, pInfh, pInfh);
+  CHECK_FFLAGS(OF | NX);
+
+  // Invalid operation, overflow
+  CLEAR_FFLAGS;
+  VSET(16, e32, m1);
+  CHECK_FFLAGS(0);
+  VLOAD_32(v2, pInff, pInff, pInff, pInff, pInff, pInff, pInff, pInff, pInff,
+           pInff, pInff, pInff, pInff, pInff, pInff, pInff);
+  VLOAD_32(v3, mInff, mInff, mInff, mInff, mInff, mInff, mInff, mInff, mInff,
+           mInff, mInff, mInff, mInff, mInff, mInff, mInff);
+  asm volatile("vfadd.vv v1, v2, v3");
+  VCMP_U32(11, v1, qNaNf, qNaNf, qNaNf, qNaNf, qNaNf, qNaNf, qNaNf, qNaNf,
+           qNaNf, qNaNf, qNaNf, qNaNf, qNaNf, qNaNf, qNaNf, qNaNf);
+  CHECK_FFLAGS(NV);
+
+  // Invalid operation, overflow, inexact
+  CLEAR_FFLAGS;
+  VSET(16, e64, m1);
+  CHECK_FFLAGS(0);
+  VLOAD_64(v2, pMaxd, pInfd, pMaxd, pMaxd, pMaxd, pMaxd, pMaxd, pMaxd, pMaxd,
+           pMaxd, pMaxd, pMaxd, pMaxd, pMaxd, pMaxd, pMaxd);
+  VLOAD_64(v3, pMaxd, mInfd, 8000000000000001, pMaxd, pMaxd, pMaxd, pMaxd,
+           pMaxd, pMaxd, pMaxd, pMaxd, pMaxd, pMaxd, pMaxd, pMaxd, pMaxd);
+  asm volatile("vfadd.vv v1, v2, v3");
+  VCMP_U64(12, v1, pInfd, qNaNd, pMaxd, pInfd, pInfd, pInfd, pInfd, pInfd,
+           pInfd, pInfd, pInfd, pInfd, pInfd, pInfd, pInfd, pInfd);
+  CHECK_FFLAGS(NV | OF | NX);
+};
+
+// Different rounding-mode + Back-to-back rm change and vfp operation
+// Index 12 (starting from 0) rounds differently for RNE and RTZ
+void TEST_CASE5(void) {
+  VSET(16, e16, m1);
+  //             -0.8896, -0.3406,  0.7324, -0.6846, -0.2969, -0.7739,  0.5737,
+  //             0.4331,  0.8940, -0.4900,  0.4219,  0.4639,  0.6694,  0.4382,
+  //             0.1356,  0.5337
+  VLOAD_16(v2, 0xbb1e, 0xb573, 0x39dc, 0xb97a, 0xb4c0, 0xba31, 0x3897, 0x36ee,
+           0x3b27, 0xb7d7, 0x36c0, 0x376c, 0x395b, 0x3703, 0x3057, 0x0001);
+  //             -0.8164,  0.6533, -0.4685,  0.6284,  0.1666,  0.9438,  0.0445,
+  //             -0.1342, -0.8071, -0.3167, -0.8350,  0.2178, -0.0896, -0.3057,
+  //             -0.3064,  0.2073
+  VLOAD_16(v3, 0xba88, 0x393a, 0xb77f, 0x3907, 0x3155, 0x3b8d, 0x29b3, 0xb04b,
+           0xba75, 0xb511, 0xbaae, 0x32f8, 0xadbc, 0xb4e4, 0xb4e7, 0x8010);
+  CHANGE_RM(RM_RTZ);
+  asm volatile("vfadd.vv v1, v2, v3");
+  //              -1.7061,  0.3127,  0.2639, -0.0562, -0.1302,  0.1699,  0.6182,
+  //              0.2988,  0.0869, -0.8066, -0.4131,  0.6816,  0.5801,  0.1326,
+  //              -0.1708,  0.7412
+  VCMP_U16(13, v1, 0xbed3, 0x3501, 0x3439, 0xab30, 0xb02b, 0x3170, 0x38f2,
+           0x34c8, 0x2d90, 0xba74, 0xb69c, 0x3974, 0x38a3, 0x303e, 0xb177,
+           0x800f);
+
+  VSET(16, e16, m1);
+  //             -0.8896, -0.3406,  0.7324, -0.6846, -0.2969, -0.7739,  0.5737,
+  //             0.4331,  0.8940, -0.4900,  0.4219,  0.4639,  0.6694,  0.4382,
+  //             0.1356,  0.5337
+  VLOAD_16(v2, 0xbb1e, 0xb573, 0x39dc, 0xb97a, 0xb4c0, 0xba31, 0x3897, 0x36ee,
+           0x3b27, 0xb7d7, 0x36c0, 0x376c, 0x395b, 0x3703, 0x3057, 0x0001);
+  //             -0.8164,  0.6533, -0.4685,  0.6284,  0.1666,  0.9438,  0.0445,
+  //             -0.1342, -0.8071, -0.3167, -0.8350,  0.2178, -0.0896, -0.3057,
+  //             -0.3064,  0.2073
+  VLOAD_16(v3, 0xba88, 0x393a, 0xb77f, 0x3907, 0x3155, 0x3b8d, 0x29b3, 0xb04b,
+           0xba75, 0xb511, 0xbaae, 0x32f8, 0xadbc, 0xb4e4, 0xb4e7, 0x8010);
+  CHANGE_RM(RM_RNE);
+  asm volatile("vfadd.vv v1, v2, v3");
+  //              -1.7061,  0.3127,  0.2639, -0.0562, -0.1302,  0.1699,  0.6182,
+  //              0.2988,  0.0869, -0.8066, -0.4131,  0.6816,  0.5801,  0.1326,
+  //              -0.1708,  0.7412
+  VCMP_U16(14, v1, 0xbed3, 0x3501, 0x3439, 0xab30, 0xb02b, 0x3170, 0x38f2,
+           0x34c8, 0x2d90, 0xba74, 0xb69c, 0x3974, 0x38a4, 0x303e, 0xb177,
+           0x800f);
+};
+
+// Simple random test with similar values (vector-scalar)
+void TEST_CASE6(void) {
+  VSET(16, e16, m1);
+  //              -0.1481, -0.1797, -0.5454,  0.3228,  0.3237, -0.7212, -0.5195,
+  //              -0.4500,  0.2681,  0.7300,  0.5059,  0.5830,  0.3198, -0.1713,
+  //              -0.6431,  0.4841
+  VLOAD_16(v2, 0xb0bd, 0xb1c0, 0xb85d, 0x352a, 0x352e, 0xb9c5, 0xb828, 0xb733,
+           0x344a, 0x39d7, 0x380c, 0x38aa, 0x351e, 0xb17b, 0xb925, 0x37bf);
+  double dscalar_16;
+  //                         -0.9380
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0xbb81);
+  asm volatile("vfadd.vf v1, v2, %[A]" ::[A] "f"(dscalar_16));
+  //               -1.0859, -1.1172, -1.4834, -0.6152, -0.6143, -1.6592,
+  //               -1.4570, -1.3877, -0.6699, -0.2080, -0.4321, -0.3550,
+  //               -0.6182, -1.1094, -1.5811, -0.4539
+  VCMP_U16(15, v1, 0xbc58, 0xbc78, 0xbdef, 0xb8ec, 0xb8ea, 0xbea3, 0xbdd4,
+           0xbd8d, 0xb95c, 0xb2a8, 0xb6ea, 0xb5ae, 0xb8f2, 0xbc70, 0xbe53,
+           0xb743);
+
+  VSET(16, e32, m1);
+  //               0.86539453, -0.53925377, -0.47128764,  0.99265540,
+  //               0.32128176, -0.47335613, -0.30028856,  0.44394016,
+  //               -0.72540921, -0.26464799,  0.77351445, -0.21725702,
+  //               -0.25191557, -0.53123665,  0.80404943,  0.81841671
+  VLOAD_32(v2, 0x3f5d8a7f, 0xbf0a0c89, 0xbef14c9d, 0x3f7e1eaa, 0x3ea47f0b,
+           0xbef25bbc, 0xbe99bf6c, 0x3ee34c20, 0xbf39b46b, 0xbe877ff1,
+           0x3f46050b, 0xbe5e78a0, 0xbe80fb14, 0xbf07ff20, 0x3f4dd62f,
+           0x3f5183c2);
+  double dscalar_32;
+  //                             -0.96056187
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0xbf75e762);
+  asm volatile("vfadd.vf v1, v2, %[A]" ::[A] "f"(dscalar_32));
+  //              -0.09516734, -1.49981570, -1.43184948,  0.03209352,
+  //              -0.63928008, -1.43391800, -1.26085043, -0.51662171,
+  //              -1.68597102, -1.22520983, -0.18704742, -1.17781889,
+  //              -1.21247745, -1.49179852, -0.15651244, -0.14214516
+  VCMP_U32(16, v1, 0xbdc2e718, 0xbfbff9f6, 0xbfb746d8, 0x3d037480, 0xbf23a7dc,
+           0xbfb78aa0, 0xbfa1638c, 0xbf044152, 0xbfd7cde6, 0xbf9cd3ad,
+           0xbe3f895c, 0xbf96c2c5, 0xbf9b3276, 0xbfbef341, 0xbe2044cc,
+           0xbe118e80);
+
+  VSET(16, e64, m1);
+  //               -0.3488917150781869, -0.4501495513738740, 0.8731197104152684,
+  //               0.3256432550932964,  0.6502591178769535, -0.3169358689246526,
+  //               -0.5396694979141685, -0.5417807430937591,
+  //               -0.7971574213160249, -0.1764794100111047, 0.3564275916066595,
+  //               -0.3754449946313438,  0.6580947137446858,
+  //               -0.3328857144699515,  0.1761214464164236,  0.1429774118511240
+  VLOAD_64(v2, 0xbfd6543dea86cb60, 0xbfdccf40105d6e5c, 0x3febf098bf37400c,
+           0x3fd4d756ceb279f4, 0x3fe4ceec35a6a266, 0xbfd448ad61fd7c88,
+           0xbfe144f8f7861540, 0xbfe1564491a616b8, 0xbfe9825047ca1cd6,
+           0xbfc696e097352100, 0x3fd6cfb5ac55edec, 0xbfd8074a7158dd78,
+           0x3fe50f1ca5268668, 0xbfd54dffe23d0eec, 0x3fc68b25c63dcaf0,
+           0x3fc24d1575fbd080);
+  double dscalar_64;
+  //                               0.9108707261227378
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0x3fed25da5d7296fe);
+  asm volatile("vfadd.vf v1, v2, %[A]" ::[A] "f"(dscalar_64));
+  //                0.5619790110445508, 0.4607211747488638,  1.7839904365380062,
+  //                1.2365139812160342,  1.5611298439996912, 0.5939348571980851,
+  //                0.3712012282085693,  0.3690899830289787, 0.1137133048067129,
+  //                0.7343913161116331,  1.2672983177293973, 0.5354257314913939,
+  //                1.5689654398674235, 0.5779850116527863,  1.0869921725391614,
+  //                1.0538481379738618
+  VCMP_U64(17, v1, 0x3fe1fbbb682f314e, 0x3fdd7c74aa87bfa0, 0x3ffc8b398e54eb85,
+           0x3ff3c8c2e265e9fc, 0x3ff8fa63498c9cb2, 0x3fe30183ac73d8ba,
+           0x3fd7c1c2cbd9037c, 0x3fd79f2b9799008c, 0x3fbd1c50ad43d140,
+           0x3fe7802237a54ebe, 0x3ff446da99cec6fa, 0x3fe1223524c62842,
+           0x3ff91a7b814c8eb3, 0x3fe27eda6c540f88, 0x3ff16451e78104dd,
+           0x3ff0dc8fdd78c58f);
+};
+
+// Simple random test with similar values (vector-scalar) (masked)
+void TEST_CASE7(void) {
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0xb0bd, 0xb1c0, 0xb85d, 0x352a, 0x352e, 0xb9c5, 0xb828, 0xb733,
+           0x344a, 0x39d7, 0x380c, 0x38aa, 0x351e, 0xb17b, 0xb925, 0x37bf);
+  double dscalar_16;
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0xbb81);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfadd.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_16));
+  VCMP_U16(18, v1, 0, 0xbc78, 0, 0xb8ec, 0, 0xbea3, 0, 0xbd8d, 0, 0xb2a8, 0,
+           0xb5ae, 0, 0xbc70, 0, 0xb743);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x3f5d8a7f, 0xbf0a0c89, 0xbef14c9d, 0x3f7e1eaa, 0x3ea47f0b,
+           0xbef25bbc, 0xbe99bf6c, 0x3ee34c20, 0xbf39b46b, 0xbe877ff1,
+           0x3f46050b, 0xbe5e78a0, 0xbe80fb14, 0xbf07ff20, 0x3f4dd62f,
+           0x3f5183c2);
+  double dscalar_32;
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0xbf75e762);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfadd.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_32));
+  VCMP_U32(19, v1, 0, 0xbfbff9f6, 0, 0x3d037480, 0, 0xbfb78aa0, 0, 0xbf044152,
+           0, 0xbf9cd3ad, 0, 0xbf96c2c5, 0, 0xbfbef341, 0, 0xbe118e80);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0xbfd6543dea86cb60, 0xbfdccf40105d6e5c, 0x3febf098bf37400c,
+           0x3fd4d756ceb279f4, 0x3fe4ceec35a6a266, 0xbfd448ad61fd7c88,
+           0xbfe144f8f7861540, 0xbfe1564491a616b8, 0xbfe9825047ca1cd6,
+           0xbfc696e097352100, 0x3fd6cfb5ac55edec, 0xbfd8074a7158dd78,
+           0x3fe50f1ca5268668, 0xbfd54dffe23d0eec, 0x3fc68b25c63dcaf0,
+           0x3fc24d1575fbd080);
+  double dscalar_64;
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0x3fed25da5d7296fe);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfadd.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_64));
+  VCMP_U64(20, v1, 0, 0x3fdd7c74aa87bfa0, 0, 0x3ff3c8c2e265e9fc, 0,
+           0x3fe30183ac73d8ba, 0, 0x3fd79f2b9799008c, 0, 0x3fe7802237a54ebe, 0,
+           0x3fe1223524c62842, 0, 0x3fe27eda6c540f88, 0, 0x3ff0dc8fdd78c58f);
+};
+
+// Raise exceptions only on active elements!
+void TEST_CASE8(void) {
+  // Overflow and Inexact. Invalid operation should not be raised.
+  CLEAR_FFLAGS;
+  VSET(16, e16, m1);
+  CHECK_FFLAGS(0);
+  VLOAD_16(v2, pInfh, pMaxh, pInfh, pMaxh, pInfh, pMaxh, pInfh, pMaxh, pInfh,
+           pMaxh, pInfh, pMaxh, pInfh, pMaxh, pInfh, pMaxh);
+  VLOAD_16(v3, mInfh, pMaxh, mInfh, pMaxh, mInfh, pMaxh, mInfh, pMaxh, mInfh,
+           pMaxh, mInfh, pMaxh, mInfh, pMaxh, mInfh, pMaxh);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfadd.vv v1, v2, v3, v0.t");
+  VCMP_U16(21, v1, 0, pInfh, 0, pInfh, 0, pInfh, 0, pInfh, 0, pInfh, 0, pInfh,
+           0, pInfh, 0, pInfh);
+  CHECK_FFLAGS(OF | NX);
+
+  // Invalid operation. Overflow and Inexact should not be raised.
+  CLEAR_FFLAGS;
+  VSET(16, e32, m1);
+  CHECK_FFLAGS(0);
+  VLOAD_32(v2, pMaxf, pInff, pMaxf, pInff, pMaxf, pInff, pMaxf, pInff, pMaxf,
+           pInff, pMaxf, pInff, pMaxf, pInff, pMaxf, pInff);
+  VLOAD_32(v3, pMaxf, mInff, pMaxf, mInff, pMaxf, mInff, pMaxf, mInff, pMaxf,
+           mInff, pMaxf, mInff, pMaxf, mInff, pMaxf, mInff);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfadd.vv v1, v2, v3, v0.t");
+  VCMP_U32(22, v1, 0, qNaNf, 0, qNaNf, 0, qNaNf, 0, qNaNf, 0, qNaNf, 0, qNaNf,
+           0, qNaNf, 0, qNaNf);
+  CHECK_FFLAGS(NV);
+
+  // No exception should be raised
+  CLEAR_FFLAGS;
+  VSET(16, e64, m1);
+  CHECK_FFLAGS(0);
+  VLOAD_64(v2, pMaxd, 0, pInfd, 0, pMaxd, 0, pMaxd, 0, pMaxd, 0, pMaxd, 0,
+           pMaxd, 0, pMaxd, 0);
+  VLOAD_64(v3, pMaxd, 0, mInfd, 0, pMaxd, 0, pMaxd, 0, pMaxd, 0, pMaxd, 0,
+           pMaxd, 0, pMaxd, 0);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfadd.vv v1, v2, v3, v0.t");
+  VCMP_U64(23, v1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+  CHECK_FFLAGS(0);
+};
+
+int main(void) {
+  enable_vec();
+  enable_fp();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+
+  TEST_CASE6();
+  TEST_CASE7();
+  TEST_CASE8();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vfclass.c b/apps/riscv-tests/isa/rv64uv/vfclass.c
new file mode 100644
index 0000000..40466bb
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vfclass.c
@@ -0,0 +1,90 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+// Test all the different output possibilities
+void TEST_CASE1(void) {
+  CLEAR_FFLAGS;
+  CHECK_FFLAGS(0);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, mInfh, pInfh, qNaNh, sNaNh, 0x3b27, 0xc767, pZero, mZeroh,
+           0x8075, 0x00c5, mInfh, pInfh, qNaNh, sNaNh, 0x3b27, 0xb767);
+  asm volatile("vfclass.v v1, v2");
+  VCMP_U16(1, v1, CLASS_mInf, CLASS_pInf, CLASS_qNAN, CLASS_sNAN, CLASS_pNorm,
+           CLASS_mNorm, CLASS_pZero, CLASS_mZero, CLASS_mSub, CLASS_pSub,
+           CLASS_mInf, CLASS_pInf, CLASS_qNAN, CLASS_sNAN, CLASS_pNorm,
+           CLASS_mNorm);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, mInff, pInff, qNaNf, sNaNf, 0x3f738772, 0xbdef32e4, pZero,
+           mZerof, 0x80000075, 0x000000c5, mInff, pInff, qNaNf, sNaNf,
+           0x3f738772, 0xbdef32e4);
+  asm volatile("vfclass.v v1, v2");
+  VCMP_U32(2, v1, CLASS_mInf, CLASS_pInf, CLASS_qNAN, CLASS_sNAN, CLASS_pNorm,
+           CLASS_mNorm, CLASS_pZero, CLASS_mZero, CLASS_mSub, CLASS_pSub,
+           CLASS_mInf, CLASS_pInf, CLASS_qNAN, CLASS_sNAN, CLASS_pNorm,
+           CLASS_mNorm);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, mInfd, pInfd, qNaNd, sNaNd, 0x3def3136584672de,
+           0xbdef3136584672de, pZero, mZerod, 0x8000000000000075,
+           0x0000000000000c5, mInfd, pInfd, qNaNd, sNaNd, 0x3def313584672de4,
+           0xbdef313654672de4);
+  asm volatile("vfclass.v v1, v2");
+  VCMP_U64(3, v1, CLASS_mInf, CLASS_pInf, CLASS_qNAN, CLASS_sNAN, CLASS_pNorm,
+           CLASS_mNorm, CLASS_pZero, CLASS_mZero, CLASS_mSub, CLASS_pSub,
+           CLASS_mInf, CLASS_pInf, CLASS_qNAN, CLASS_sNAN, CLASS_pNorm,
+           CLASS_mNorm);
+};
+
+// Test all the different output possibilities
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  VLOAD_16(v2, mInfh, pInfh, qNaNh, sNaNh, 0x3b27, 0xc767, pZero, mZeroh,
+           0x8075, 0x00c5, mInfh, pInfh, qNaNh, sNaNh, 0x3b27, 0xb767);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfclass.v v1, v2, v0.t");
+  VCMP_U16(4, v1, 0, CLASS_pInf, 0, CLASS_sNAN, 0, CLASS_mNorm, 0, CLASS_mZero,
+           0, CLASS_pSub, 0, CLASS_pInf, 0, CLASS_sNAN, 0, CLASS_mNorm);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, mInff, pInff, qNaNf, sNaNf, 0x3f738772, 0xbdef32e4, pZero,
+           mZerof, 0x80000075, 0x000000c5, mInff, pInff, qNaNf, sNaNf,
+           0x3f738772, 0xbdef32e4);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfclass.v v1, v2, v0.t");
+  VCMP_U32(5, v1, 0, CLASS_pInf, 0, CLASS_sNAN, 0, CLASS_mNorm, 0, CLASS_mZero,
+           0, CLASS_pSub, 0, CLASS_pInf, 0, CLASS_sNAN, 0, CLASS_mNorm);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, mInfd, pInfd, qNaNd, sNaNd, 0x3def313584672de4,
+           0xbdef313658467de4, pZero, mZerod, 0x8000000000000075,
+           0x0000000000000c5, mInfd, pInfd, qNaNd, sNaNd, 0x3def313658672de4,
+           0xbdef313654672de4);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfclass.v v1, v2, v0.t");
+  VCMP_U64(6, v1, 0, CLASS_pInf, 0, CLASS_sNAN, 0, CLASS_mNorm, 0, CLASS_mZero,
+           0, CLASS_pSub, 0, CLASS_pInf, 0, CLASS_sNAN, 0, CLASS_mNorm);
+  CHECK_FFLAGS(0);
+};
+
+int main(void) {
+  enable_vec();
+  enable_fp();
+
+  // No exception should be raised by vfclass.v
+  TEST_CASE1();
+  TEST_CASE2();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vfcvt.c b/apps/riscv-tests/isa/rv64uv/vfcvt.c
new file mode 100644
index 0000000..26794bf
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vfcvt.c
@@ -0,0 +1,834 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+// We assume RNE rounding when not specified by the encoding
+
+////////////////
+// vfcvt.xu.f //
+////////////////
+
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  //              -2372.000,   2978.000, -5132.000, -3426.000, -3878.000,
+  //              9680.000,   76.000, -8128.000, -2314.000, -4660.000, 8672.000,
+  //              8824.000, -5732.000, -1557.000, -2302.000, -407.250
+  VLOAD_16(v2, 0xe8a2, 0x69d1, 0xed03, 0xeab1, 0xeb93, 0x70ba, 0x54c0, 0xeff0,
+           0xe885, 0xec8d, 0x703c, 0x704f, 0xed99, 0xe615, 0xe87f, 0xde5d);
+  asm volatile("vfcvt.xu.f.v v3, v2");
+  //                       0,       2978,          0,          0,          0,
+  //                       9680,         76,          0,          0,          0,
+  //                       8672,       8824,          0,          0,          0,
+  //                       0
+  VCMP_U16(1, v3, 0x0000, 0x0ba2, 0x0000, 0x0000, 0x0000, 0x25d0, 0x004c,
+           0x0000, 0x0000, 0x0000, 0x21e0, 0x2278, 0x0000, 0x0000, 0x0000,
+           0x0000);
+
+  VSET(16, e32, m1);
+  //              -82436.352, -5427.481, -30119.082,   53784.066,   76500.719,
+  //              65152.020, -94151.375,   71894.320, -20547.545,   95485.906,
+  //              92834.711, -28081.711, -9716.506,   62508.508,   90410.883,
+  //              42708.285
+  VLOAD_32(v2, 0xc7a1022d, 0xc5a99bd9, 0xc6eb4e2a, 0x47521811, 0x47956a5c,
+           0x477e8005, 0xc7b7e3b0, 0x478c6b29, 0xc6a08717, 0x47ba7ef4,
+           0x47b5515b, 0xc6db636c, 0xc617d206, 0x47742c82, 0x47b09571,
+           0x4726d449);
+  asm volatile("vfcvt.xu.f.v v3, v2");
+  //                           0,              0,              0, 53784, 76501,
+  //                           65152,              0,          71894, 0, 95486,
+  //                           92835,              0,              0, 62509,
+  //                           90411,          42708
+  VCMP_U32(2, v3, 0x00000000, 0x00000000, 0x00000000, 0x0000d218, 0x00012ad5,
+           0x0000fe80, 0x00000000, 0x000118d6, 0x00000000, 0x000174fe,
+           0x00016aa3, 0x00000000, 0x00000000, 0x0000f42d, 0x0001612b,
+           0x0000a6d4);
+
+  VSET(16, e64, m1);
+  //                3554390.405,   3670449.443,   3880983.535,   3452087.537,
+  //                -5447847.496,   498812.179,   9535291.051,   113884.868,
+  //                2124622.198, -2164534.614,   1377445.305, -2114478.485,
+  //                -4704971.356, -7866057.432,   7002504.380, -2981734.692
+  VLOAD_64(v2, 0x414b1e2b33d13be4, 0x414c00d8b8b34d48, 0x414d9c0bc4751d78,
+           0x414a565bc4adf2d0, 0xc154c829dfc2d9f6, 0x411e71f0b7161c00,
+           0x41622fe7619e55e2, 0x40fbcdcde34f1a00, 0x414035a7194d9794,
+           0xc140839b4e886550, 0x413504a54df56888, 0xc14021d73e1606dc,
+           0xc151f2b2d6cc57c8, 0xc15e01b25baceaba, 0x415ab6621850fa94,
+           0xc146bfb358869da2);
+  asm volatile("vfcvt.xu.f.v v3, v2");
+  //                             3554390,                3670449, 3880984,
+  //                             3452088,                      0, 498812,
+  //                             9535291,                 113885, 2124622, 0,
+  //                             1377445,                      0, 0, 0, 7002504,
+  //                             0
+  VCMP_U64(3, v3, 0x0000000000363c56, 0x00000000003801b1, 0x00000000003b3818,
+           0x000000000034acb8, 0x0000000000000000, 0x0000000000079c7c,
+           0x0000000000917f3b, 0x000000000001bcdd, 0x0000000000206b4e,
+           0x0000000000000000, 0x00000000001504a5, 0x0000000000000000,
+           0x0000000000000000, 0x0000000000000000, 0x00000000006ad988,
+           0x0000000000000000);
+};
+
+// Simple random test with similar values (masked)
+// The numbers are the same of TEST_CASE1
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  //              -2372.000,   2978.000, -5132.000, -3426.000, -3878.000,
+  //              9680.000,   76.000, -8128.000, -2314.000, -4660.000, 8672.000,
+  //              8824.000, -5732.000, -1557.000, -2302.000, -407.250
+  VLOAD_16(v2, 0xe8a2, 0x69d1, 0xed03, 0xeab1, 0xeb93, 0x70ba, 0x54c0, 0xeff0,
+           0xe885, 0xec8d, 0x703c, 0x704f, 0xed99, 0xe615, 0xe87f, 0xde5d);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v3);
+  asm volatile("vfcvt.xu.f.v v3, v2, v0.t");
+  //                       0,       2978,          0,          0,          0,
+  //                       9680,          0,          0,          0,          0,
+  //                       0,       8824,          0,          0,          0, 0
+  VCMP_U16(4, v3, 0x0000, 0x0ba2, 0x0000, 0x0000, 0x0000, 0x25d0, 0x0000,
+           0x0000, 0x0000, 0x0000, 0x0000, 0x2278, 0x0000, 0x0000, 0x0000,
+           0x0000);
+
+  VSET(16, e32, m1);
+  //              -82436.352, -5427.481, -30119.082,   53784.066,   76500.719,
+  //              65152.020, -94151.375,   71894.320, -20547.545,   95485.906,
+  //              92834.711, -28081.711, -9716.506,   62508.508,   90410.883,
+  //              42708.285
+  VLOAD_32(v2, 0xc7a1022d, 0xc5a99bd9, 0xc6eb4e2a, 0x47521811, 0x47956a5c,
+           0x477e8005, 0xc7b7e3b0, 0x478c6b29, 0xc6a08717, 0x47ba7ef4,
+           0x47b5515b, 0xc6db636c, 0xc617d206, 0x47742c82, 0x47b09571,
+           0x4726d449);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v3);
+  asm volatile("vfcvt.xu.f.v v3, v2, v0.t");
+  //                           0,              0,              0, 53784, 0,
+  //                           65152,              0,          71894, 0, 95486,
+  //                           0,              0,              0, 62509, 0,
+  //                           42708
+  VCMP_U32(5, v3, 0x00000000, 0x00000000, 0x00000000, 0x0000d218, 0x00000000,
+           0x0000fe80, 0x00000000, 0x000118d6, 0x00000000, 0x000174fe,
+           0x00000000, 0x00000000, 0x00000000, 0x0000f42d, 0x00000000,
+           0x0000a6d4);
+
+  VSET(16, e64, m1);
+  //                3554390.405,   3670449.443,   3880983.535,   3452087.537,
+  //                -5447847.496,   498812.179,   9535291.051,   113884.868,
+  //                2124622.198, -2164534.614,   1377445.305, -2114478.485,
+  //                -4704971.356, -7866057.432,   7002504.380, -2981734.692
+  VLOAD_64(v2, 0x414b1e2b33d13be4, 0x414c00d8b8b34d48, 0x414d9c0bc4751d78,
+           0x414a565bc4adf2d0, 0xc154c829dfc2d9f6, 0x411e71f0b7161c00,
+           0x41622fe7619e55e2, 0x40fbcdcde34f1a00, 0x414035a7194d9794,
+           0xc140839b4e886550, 0x413504a54df56888, 0xc14021d73e1606dc,
+           0xc151f2b2d6cc57c8, 0xc15e01b25baceaba, 0x415ab6621850fa94,
+           0xc146bfb358869da2);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v3);
+  asm volatile("vfcvt.xu.f.v v3, v2, v0.t");
+  //                                   0,                3670449, 0, 3452088, 0,
+  //                                   498812,                      0, 113885,
+  //                                   0,                      0, 0, 0, 0, 0, 0,
+  //                                   0
+  VCMP_U64(6, v3, 0x0000000000000000, 0x00000000003801b1, 0x0000000000000000,
+           0x000000000034acb8, 0x0000000000000000, 0x0000000000079c7c,
+           0x0000000000000000, 0x000000000001bcdd, 0x0000000000000000,
+           0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+           0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+           0x0000000000000000);
+};
+
+///////////////
+// vfcvt.x.f //
+///////////////
+
+// Unmasked vfcvt.x.f.c
+void TEST_CASE3(void) {
+  VSET(16, e16, m1);
+  //                4144.000, -861.500, -8680.000,   3792.000,   8800.000,
+  //                -2330.000, -3066.000, -6148.000,   4776.000,   7360.000,
+  //                -7880.000, -1843.000, -7896.000, -6520.000, -7092.000,
+  //                -8344.000
+  VLOAD_16(v2, 0x6c0c, 0xe2bb, 0xf03d, 0x6b68, 0x704c, 0xe88d, 0xe9fd, 0xee01,
+           0x6caa, 0x6f30, 0xefb2, 0xe733, 0xefb6, 0xee5e, 0xeeed, 0xf013);
+  asm volatile("vfcvt.x.f.v v3, v2");
+  //                    4144,       -862,      -8680,       3792,       8800,
+  //                    -2330,      -3066,      -6148,       4776,       7360,
+  //                    -7880,      -1843,      -7896,      -6520,      -7092,
+  //                    -8344
+  VCMP_U16(7, v3, 0x1030, 0xfca2, 0xde18, 0x0ed0, 0x2260, 0xf6e6, 0xf406,
+           0xe7fc, 0x12a8, 0x1cc0, 0xe138, 0xf8cd, 0xe128, 0xe688, 0xe44c,
+           0xdf68);
+
+  VSET(16, e32, m1);
+  //              -28075.818, -5455.616,   6106.086, -11952.592, -50887.914,
+  //              -23028.832, -9221.246, -71657.047, -6655.005, -21208.561,
+  //              -30018.096, -19766.838,   48541.953, -62313.625,   13515.192,
+  //              -83224.820
+  VLOAD_32(v2, 0xc6db57a3, 0xc5aa7ced, 0x45bed0b1, 0xc63ac25e, 0xc746c7ea,
+           0xc6b3e9aa, 0xc61014fc, 0xc78bf486, 0xc5cff80a, 0xc6a5b11f,
+           0xc6ea8431, 0xc69a6dad, 0x473d9df4, 0xc77369a0, 0x46532cc5,
+           0xc7a28c69);
+  asm volatile("vfcvt.x.f.v v3, v2");
+  //                      -28076,          -5456,           6106, -11953,
+  //                      -50888,         -23029,          -9221, -71657, -6655,
+  //                      -21209,         -30018,         -19767, 48542, -62314,
+  //                      13515,         -83225
+  VCMP_U32(8, v3, 0xffff9254, 0xffffeab0, 0x000017da, 0xffffd14f, 0xffff3938,
+           0xffffa60b, 0xffffdbfb, 0xfffee817, 0xffffe601, 0xffffad27,
+           0xffff8abe, 0xffffb2c9, 0x0000bd9e, 0xffff0c96, 0x000034cb,
+           0xfffebae7);
+
+  VSET(16, e64, m1);
+  //                         3087905.033,           -2534011.630, 7824302.813,
+  //                         -9294206.521,   6436555.847,   6645117.193,
+  //                         1358075.867,   5694551.012, -9840938.636,
+  //                         4621816.383,   2584370.751,   5569558.860,
+  //                         495487.041,   4759865.418, -6831172.669,
+  //                         8371055.296
+  VLOAD_64(v2, 0x41478f10842c8b9c, 0xc143553dd0971c82, 0x415dd8ebb40e1fe0,
+           0xc161ba2fd0a8a593, 0x41588db2f632700c, 0x4159595f4c588b60,
+           0x4134b8fbde131210, 0x4155b915c0cb4294, 0xc162c52554566300,
+           0x4151a17e187d1aa8, 0x4143b7996029dc68, 0x41553f05b70b6824,
+           0x411e3dfc2a598ba0, 0x4152284e5ac4da5a, 0xc15a0f112acbf258,
+           0x415feedbd2ed6038);
+  asm volatile("vfcvt.x.f.v v3, v2");
+  //                             3087905,               -2534012, 7824303,
+  //                             -9294207,                6436556, 6645117,
+  //                             1358076,                5694551, -9840939,
+  //                             4621816,                2584371, 5569559,
+  //                             495487,                4759865, -6831173,
+  //                             8371055
+  VCMP_U64(9, v3, 0x00000000002f1e21, 0xffffffffffd95584, 0x00000000007763af,
+           0xffffffffff722e81, 0x00000000006236cc, 0x000000000065657d,
+           0x000000000014b8fc, 0x000000000056e457, 0xffffffffff69d6d5,
+           0x00000000004685f8, 0x0000000000276f33, 0x000000000054fc17,
+           0x0000000000078f7f, 0x000000000048a139, 0xffffffffff97c3bb,
+           0x00000000007fbb6f);
+};
+
+// Masked vfcvt.x.f.c
+void TEST_CASE4(void) {
+  VSET(16, e16, m1);
+  //                4144.000, -861.500, -8680.000,   3792.000,   8800.000,
+  //                -2330.000, -3066.000, -6148.000,   4776.000,   7360.000,
+  //                -7880.000, -1843.000, -7896.000, -6520.000, -7092.000,
+  //                -8344.000
+  VLOAD_16(v2, 0x6c0c, 0xe2bb, 0xf03d, 0x6b68, 0x704c, 0xe88d, 0xe9fd, 0xee01,
+           0x6caa, 0x6f30, 0xefb2, 0xe733, 0xefb6, 0xee5e, 0xeeed, 0xf013);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v3);
+  asm volatile("vfcvt.x.f.v v3, v2, v0.t");
+  //                       0,       -862,          0,       3792,          0,
+  //                       -2330,          0,      -6148,          0, 7360, 0,
+  //                       -1843,          0,      -6520,          0,      -8344
+  VCMP_U16(10, v3, 0x0000, 0xfca2, 0x0000, 0x0ed0, 0x0000, 0xf6e6, 0x0000,
+           0xe7fc, 0x0000, 0x1cc0, 0x0000, 0xf8cd, 0x0000, 0xe688, 0x0000,
+           0xdf68);
+
+  VSET(16, e32, m1);
+  //                  -28075.818,      -5455.616,       6106.086, -11952.592,
+  //                  -50887.914,     -23028.832,      -9221.246, -71657.047,
+  //                  -6655.005, -21208.561, -30018.096, -19766.838, 48541.953,
+  //                  -62313.625,   13515.192, -83224.820
+  VLOAD_32(v2, 0xc6db57a3, 0xc5aa7ced, 0x45bed0b1, 0xc63ac25e, 0xc746c7ea,
+           0xc6b3e9aa, 0xc61014fc, 0xc78bf486, 0xc5cff80a, 0xc6a5b11f,
+           0xc6ea8431, 0xc69a6dad, 0x473d9df4, 0xc77369a0, 0x46532cc5,
+           0xc7a28c69);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v3);
+  asm volatile("vfcvt.x.f.v v3, v2, v0.t");
+  //                           0,          -5456,              0, -11953, 0,
+  //                           -23029,              0,         -71657, 0,
+  //                           -21209,              0,         -19767, 0,
+  //                           -62314,              0,         -83225
+  VCMP_U32(11, v3, 0x00000000, 0xffffeab0, 0x00000000, 0xffffd14f, 0x00000000,
+           0xffffa60b, 0x00000000, 0xfffee817, 0x00000000, 0xffffad27,
+           0x00000000, 0xffffb2c9, 0x00000000, 0xffff0c96, 0x00000000,
+           0xfffebae7);
+
+  VSET(16, e64, m1);
+  //                3087905.033, -2534011.630,   7824302.813, -9294206.521,
+  //                6436555.847,   6645117.193,   1358075.867,   5694551.012,
+  //                -9840938.636,   4621816.383,   2584370.751,   5569558.860,
+  //                495487.041,   4759865.418, -6831172.669,   8371055.296
+  VLOAD_64(v2, 0x41478f10842c8b9c, 0xc143553dd0971c82, 0x415dd8ebb40e1fe0,
+           0xc161ba2fd0a8a593, 0x41588db2f632700c, 0x4159595f4c588b60,
+           0x4134b8fbde131210, 0x4155b915c0cb4294, 0xc162c52554566300,
+           0x4151a17e187d1aa8, 0x4143b7996029dc68, 0x41553f05b70b6824,
+           0x411e3dfc2a598ba0, 0x4152284e5ac4da5a, 0xc15a0f112acbf258,
+           0x415feedbd2ed6038);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v3);
+  asm volatile("vfcvt.x.f.v v3, v2, v0.t");
+  //                                   0,               -2534012, 0, -9294207,
+  //                                   0,                6645117, 0, 5694551, 0,
+  //                                   4621816,                      0, 5569559,
+  //                                   0,                4759865, 0, 8371055
+  VCMP_U64(12, v3, 0x0000000000000000, 0xffffffffffd95584, 0x0000000000000000,
+           0xffffffffff722e81, 0x0000000000000000, 0x000000000065657d,
+           0x0000000000000000, 0x000000000056e457, 0x0000000000000000,
+           0x00000000004685f8, 0x0000000000000000, 0x000000000054fc17,
+           0x0000000000000000, 0x000000000048a139, 0x0000000000000000,
+           0x00000000007fbb6f);
+};
+
+////////////////////
+// vfcvt.rtz.xu.f //
+////////////////////
+
+// Simple random test with similar values
+void TEST_CASE5(void) {
+  VSET(16, e16, m1);
+  //                6996.000, -7512.000, -4792.000,   7240.000,   8336.000,
+  //                6332.000, -277.750, -4074.000,   9352.000,   8832.000,
+  //                -65.000,   5860.000,   6892.000,   2944.000,   9608.000,
+  //                4608.000
+  VLOAD_16(v2, 0x6ed5, 0xef56, 0xecae, 0x6f12, 0x7012, 0x6e2f, 0xdc57, 0xebf5,
+           0x7091, 0x7050, 0xd410, 0x6db9, 0x6ebb, 0x69c0, 0x70b1, 0x6c80);
+  asm volatile("vfcvt.rtz.xu.f.v v3, v2");
+  //                    6996,          0,          0,       7240,       8336,
+  //                    6332,          0,          0,       9352,       8832, 0,
+  //                    5860,       6892,       2944,       9608,       4608
+  VCMP_U16(13, v3, 0x1b54, 0x0000, 0x0000, 0x1c48, 0x2090, 0x18bc, 0x0000,
+           0x0000, 0x2488, 0x2280, 0x0000, 0x16e4, 0x1aec, 0x0b80, 0x2588,
+           0x1200);
+
+  VSET(16, e32, m1);
+  //                85074.883, -2035.769,   67397.633, -57745.480,   82113.172,
+  //                18415.770,   57859.465,   83291.773, -83693.375, 43321.199,
+  //                94626.156, -53520.090,   9604.658, -5764.834,   94299.633,
+  //                57572.980
+  VLOAD_32(v2, 0x47a62971, 0xc4fe789f, 0x4783a2d1, 0xc761917b, 0x47a06096,
+           0x468fdf8a, 0x47620377, 0x47a2ade3, 0xc7a376b0, 0x47293933,
+           0x47b8d114, 0xc7511017, 0x461612a2, 0xc5b426ac, 0x47b82dd1,
+           0x4760e4fb);
+  asm volatile("vfcvt.rtz.xu.f.v v3, v2");
+  //                       85074,              0,          67397, 0, 82113,
+  //                       18415,          57859,          83291, 0, 43321,
+  //                       94626,              0,           9604, 0, 94299,
+  //                       57572
+  VCMP_U32(14, v3, 0x00014c52, 0x00000000, 0x00010745, 0x00000000, 0x000140c1,
+           0x000047ef, 0x0000e203, 0x0001455b, 0x00000000, 0x0000a939,
+           0x000171a2, 0x00000000, 0x00002584, 0x00000000, 0x0001705b,
+           0x0000e0e4);
+
+  VSET(16, e64, m1);
+  //              -5386285.220, -9081004.335, -9603879.062, -4621060.923,
+  //              2017661.058,   1106405.978, -2095853.299,   1911589.313,
+  //              4833261.528,   1291127.404, -9941577.120,   9259799.184,
+  //              -8569693.727,   4926687.920, -7537625.130, -6328586.289
+  VLOAD_64(v2, 0xc1548c0b4e12be63, 0xc16152158ab92a41, 0xc1625164e1fd6af4,
+           0xc151a0c13b0c041c, 0x413ec97d0edd7a68, 0x4130e1e5fa5c8120,
+           0xc13ffaed4c78fc7c, 0x413d2b2550357b50, 0x41526ffb61d23f42,
+           0x4133b377675b6328, 0xc162f64923d5cce3, 0x4161a962e5e3a1e8,
+           0xc160586bb74734b0, 0x4152cb37fae70f80, 0xc15cc0f6484f174c,
+           0xc1582442928257b8);
+  asm volatile("vfcvt.rtz.xu.f.v v3, v2");
+  //                                   0,                      0, 0, 0, 2017661,
+  //                                   1106405,                      0, 1911589,
+  //                                   4833261,                1291127, 0,
+  //                                   9259799,                      0, 4926687,
+  //                                   0,                      0
+  VCMP_U64(15, v3, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+           0x0000000000000000, 0x00000000001ec97d, 0x000000000010e1e5,
+           0x0000000000000000, 0x00000000001d2b25, 0x000000000049bfed,
+           0x000000000013b377, 0x0000000000000000, 0x00000000008d4b17,
+           0x0000000000000000, 0x00000000004b2cdf, 0x0000000000000000,
+           0x0000000000000000);
+};
+
+// Simple random test with similar values (masked)
+// The numbers are the same of TEST_CASE1
+void TEST_CASE6(void) {
+  VSET(16, e16, m1);
+  //                6996.000, -7512.000, -4792.000,   7240.000,   8336.000,
+  //                6332.000, -277.750, -4074.000,   9352.000,   8832.000,
+  //                -65.000,   5860.000,   6892.000,   2944.000,   9608.000,
+  //                4608.000
+  VLOAD_16(v2, 0x6ed5, 0xef56, 0xecae, 0x6f12, 0x7012, 0x6e2f, 0xdc57, 0xebf5,
+           0x7091, 0x7050, 0xd410, 0x6db9, 0x6ebb, 0x69c0, 0x70b1, 0x6c80);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v3);
+  asm volatile("vfcvt.rtz.xu.f.v v3, v2, v0.t");
+  //                       0,          0,          0,       7240,          0,
+  //                       6332,          0,          0,          0,       8832,
+  //                       0,       5860,          0,       2944,          0,
+  //                       4608
+  VCMP_U16(16, v3, 0x0000, 0x0000, 0x0000, 0x1c48, 0x0000, 0x18bc, 0x0000,
+           0x0000, 0x0000, 0x2280, 0x0000, 0x16e4, 0x0000, 0x0b80, 0x0000,
+           0x1200);
+
+  VSET(16, e32, m1);
+  //                85074.883, -2035.769,   67397.633, -57745.480,   82113.172,
+  //                18415.770,   57859.465,   83291.773, -83693.375, 43321.199,
+  //                94626.156, -53520.090,   9604.658, -5764.834,   94299.633,
+  //                57572.980
+  VLOAD_32(v2, 0x47a62971, 0xc4fe789f, 0x4783a2d1, 0xc761917b, 0x47a06096,
+           0x468fdf8a, 0x47620377, 0x47a2ade3, 0xc7a376b0, 0x47293933,
+           0x47b8d114, 0xc7511017, 0x461612a2, 0xc5b426ac, 0x47b82dd1,
+           0x4760e4fb);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v3);
+  asm volatile("vfcvt.rtz.xu.f.v v3, v2, v0.t");
+  //                           0,              0,              0, 0, 0, 18415,
+  //                           0,          83291,              0, 43321, 0, 0,
+  //                           0,              0,              0,          57572
+  VCMP_U32(17, v3, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+           0x000047ef, 0x00000000, 0x0001455b, 0x00000000, 0x0000a939,
+           0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+           0x0000e0e4);
+
+  VSET(16, e64, m1);
+  //              -5386285.220, -9081004.335, -9603879.062, -4621060.923,
+  //              2017661.058,   1106405.978, -2095853.299,   1911589.313,
+  //              4833261.528,   1291127.404, -9941577.120,   9259799.184,
+  //              -8569693.727,   4926687.920, -7537625.130, -6328586.289
+  VLOAD_64(v2, 0xc1548c0b4e12be63, 0xc16152158ab92a41, 0xc1625164e1fd6af4,
+           0xc151a0c13b0c041c, 0x413ec97d0edd7a68, 0x4130e1e5fa5c8120,
+           0xc13ffaed4c78fc7c, 0x413d2b2550357b50, 0x41526ffb61d23f42,
+           0x4133b377675b6328, 0xc162f64923d5cce3, 0x4161a962e5e3a1e8,
+           0xc160586bb74734b0, 0x4152cb37fae70f80, 0xc15cc0f6484f174c,
+           0xc1582442928257b8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v3);
+  asm volatile("vfcvt.rtz.xu.f.v v3, v2, v0.t");
+  //                                   0,                      0, 0, 0, 0,
+  //                                   1106405,                      0, 1911589,
+  //                                   0,                1291127, 0, 9259799, 0,
+  //                                   4926687,                      0, 0
+  VCMP_U64(18, v3, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+           0x0000000000000000, 0x0000000000000000, 0x000000000010e1e5,
+           0x0000000000000000, 0x00000000001d2b25, 0x0000000000000000,
+           0x000000000013b377, 0x0000000000000000, 0x00000000008d4b17,
+           0x0000000000000000, 0x00000000004b2cdf, 0x0000000000000000,
+           0x0000000000000000);
+};
+
+///////////////////
+// vfcvt.rtz.x.f //
+///////////////////
+
+// Simple random test with similar values
+void TEST_CASE7(void) {
+  VSET(16, e16, m1);
+  //                5116.000,   4640.000,   5720.000,   1316.000,   8104.000,
+  //                9952.000,   9400.000, -4120.000, -9368.000,   6076.000,
+  //                1782.000, -5332.000, -4284.000, -2878.000, -2752.000,
+  //                3714.000
+  VLOAD_16(v2, 0x6cff, 0x6c88, 0x6d96, 0x6524, 0x6fea, 0x70dc, 0x7097, 0xec06,
+           0xf093, 0x6def, 0x66f6, 0xed35, 0xec2f, 0xe99f, 0xe960, 0x6b41);
+  asm volatile("vfcvt.rtz.x.f.v v3, v2");
+  //                    5116,       4640,       5720,       1316,       8104,
+  //                    9952,       9400,      -4120,      -9368,       6076,
+  //                    1782,      -5332,      -4284,      -2878,      -2752,
+  //                    3714
+  VCMP_U16(19, v3, 0x13fc, 0x1220, 0x1658, 0x0524, 0x1fa8, 0x26e0, 0x24b8,
+           0xefe8, 0xdb68, 0x17bc, 0x06f6, 0xeb2c, 0xef44, 0xf4c2, 0xf540,
+           0x0e82);
+
+  VSET(16, e32, m1);
+  //              -31395.312,   38407.539,   39625.664, -19419.770, -77414.898,
+  //              -96104.727, -8227.330, -45789.250, -74805.781,   78266.945,
+  //              1635.832, -33150.762,   17428.920, -93694.898,   93592.562,
+  //              -83328.680
+  VLOAD_32(v2, 0xc6f546a0, 0x4716078a, 0x471ac9aa, 0xc697b78a, 0xc7973373,
+           0xc7bbb45d, 0xc6008d52, 0xc732dd40, 0xc7921ae4, 0x4798dd79,
+           0x44cc7aa0, 0xc7017ec3, 0x468829d7, 0xc7b6ff73, 0x47b6cc48,
+           0xc7a2c057);
+  asm volatile("vfcvt.rtz.x.f.v v3, v2");
+  //                      -31395,          38407,          39625, -19419,
+  //                      -77414,         -96104,          -8227, -45789,
+  //                      -74805,          78266,           1635, -33150, 17428,
+  //                      -93694,          93592,         -83328
+  VCMP_U32(20, v3, 0xffff855d, 0x00009607, 0x00009ac9, 0xffffb425, 0xfffed19a,
+           0xfffe8898, 0xffffdfdd, 0xffff4d23, 0xfffedbcb, 0x000131ba,
+           0x00000663, 0xffff7e82, 0x00004414, 0xfffe9202, 0x00016d98,
+           0xfffeba80);
+
+  VSET(16, e64, m1);
+  //                1347922.217,   7326256.926,   2532328.150, -4365139.352,
+  //                -3892733.643, -3401324.772, -2109243.969,   61221.157,
+  //                -307581.498, -6001564.901, -1299579.664, -2048360.900,
+  //                3486773.936, -5491246.977, -2222467.648,   1432204.815
+  VLOAD_64(v2, 0x413491523797bd28, 0x415bf28c3b410560, 0x414351f41339c8f8,
+           0xc150a6d4d6864763, 0xc14db2fed245a01c, 0xc149f33662d1f60e,
+           0xc140179dfc15a4ac, 0x40ede4a503831a00, 0xc112c5f5fdac3c80,
+           0xc156e4e739a40168, 0xc133d47ba9e7da00, 0xc13f4168e650cc0c,
+           0x414a9a1af7c5dda0, 0xc154f28bbe844db6, 0xc140f4c1d2e7a21a,
+           0x4135da8cd09570f8);
+  asm volatile("vfcvt.rtz.x.f.v v3, v2");
+  //                             1347922,                7326256, 2532328,
+  //                             -4365139,               -3892733, -3401324,
+  //                             -2109243,                  61221, -307581,
+  //                             -6001564,               -1299579, -2048360,
+  //                             3486773,               -5491246, -2222467,
+  //                             1432204
+  VCMP_U64(21, v3, 0x0000000000149152, 0x00000000006fca30, 0x000000000026a3e8,
+           0xffffffffffbd64ad, 0xffffffffffc49a03, 0xffffffffffcc1994,
+           0xffffffffffdfd0c5, 0x000000000000ef25, 0xfffffffffffb4e83,
+           0xffffffffffa46c64, 0xffffffffffec2b85, 0xffffffffffe0be98,
+           0x0000000000353435, 0xffffffffffac35d2, 0xffffffffffde167d,
+           0x000000000015da8c);
+};
+
+// Simple random test with similar values (masked)
+// The numbers are the same of TEST_CASE1
+void TEST_CASE8(void) {
+  VSET(16, e16, m1);
+  //                5116.000,   4640.000,   5720.000,   1316.000,   8104.000,
+  //                9952.000,   9400.000, -4120.000, -9368.000,   6076.000,
+  //                1782.000, -5332.000, -4284.000, -2878.000, -2752.000,
+  //                3714.000
+  VLOAD_16(v2, 0x6cff, 0x6c88, 0x6d96, 0x6524, 0x6fea, 0x70dc, 0x7097, 0xec06,
+           0xf093, 0x6def, 0x66f6, 0xed35, 0xec2f, 0xe99f, 0xe960, 0x6b41);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v3);
+  asm volatile("vfcvt.rtz.x.f.v v3, v2, v0.t");
+  //                       0,       4640,          0,       1316,          0,
+  //                       9952,          0,      -4120,          0,       6076,
+  //                       0,      -5332,          0,      -2878,          0,
+  //                       3714
+  VCMP_U16(22, v3, 0x0000, 0x1220, 0x0000, 0x0524, 0x0000, 0x26e0, 0x0000,
+           0xefe8, 0x0000, 0x17bc, 0x0000, 0xeb2c, 0x0000, 0xf4c2, 0x0000,
+           0x0e82);
+
+  VSET(16, e32, m1);
+  //              -31395.312,   38407.539,   39625.664, -19419.770, -77414.898,
+  //              -96104.727, -8227.330, -45789.250, -74805.781,   78266.945,
+  //              1635.832, -33150.762,   17428.920, -93694.898,   93592.562,
+  //              -83328.680
+  VLOAD_32(v2, 0xc6f546a0, 0x4716078a, 0x471ac9aa, 0xc697b78a, 0xc7973373,
+           0xc7bbb45d, 0xc6008d52, 0xc732dd40, 0xc7921ae4, 0x4798dd79,
+           0x44cc7aa0, 0xc7017ec3, 0x468829d7, 0xc7b6ff73, 0x47b6cc48,
+           0xc7a2c057);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v3);
+  asm volatile("vfcvt.rtz.x.f.v v3, v2, v0.t");
+  //                           0,          38407,              0, -19419, 0,
+  //                           -96104,              0,         -45789, 0, 78266,
+  //                           0,         -33150,              0, -93694, 0,
+  //                           -83328
+  VCMP_U32(23, v3, 0x00000000, 0x00009607, 0x00000000, 0xffffb425, 0x00000000,
+           0xfffe8898, 0x00000000, 0xffff4d23, 0x00000000, 0x000131ba,
+           0x00000000, 0xffff7e82, 0x00000000, 0xfffe9202, 0x00000000,
+           0xfffeba80);
+
+  VSET(16, e64, m1);
+  //                1347922.217,   7326256.926,   2532328.150, -4365139.352,
+  //                -3892733.643, -3401324.772, -2109243.969,   61221.157,
+  //                -307581.498, -6001564.901, -1299579.664, -2048360.900,
+  //                3486773.936, -5491246.977, -2222467.648,   1432204.815
+  VLOAD_64(v2, 0x413491523797bd28, 0x415bf28c3b410560, 0x414351f41339c8f8,
+           0xc150a6d4d6864763, 0xc14db2fed245a01c, 0xc149f33662d1f60e,
+           0xc140179dfc15a4ac, 0x40ede4a503831a00, 0xc112c5f5fdac3c80,
+           0xc156e4e739a40168, 0xc133d47ba9e7da00, 0xc13f4168e650cc0c,
+           0x414a9a1af7c5dda0, 0xc154f28bbe844db6, 0xc140f4c1d2e7a21a,
+           0x4135da8cd09570f8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v3);
+  asm volatile("vfcvt.rtz.x.f.v v3, v2, v0.t");
+  //                                   0,                7326256, 0, -4365139,
+  //                                   0,               -3401324, 0, 61221, 0,
+  //                                   -6001564,                      0,
+  //                                   -2048360,                      0,
+  //                                   -5491246,                      0, 1432204
+  VCMP_U64(24, v3, 0x0000000000000000, 0x00000000006fca30, 0x0000000000000000,
+           0xffffffffffbd64ad, 0x0000000000000000, 0xffffffffffcc1994,
+           0x0000000000000000, 0x000000000000ef25, 0x0000000000000000,
+           0xffffffffffa46c64, 0x0000000000000000, 0xffffffffffe0be98,
+           0x0000000000000000, 0xffffffffffac35d2, 0x0000000000000000,
+           0x000000000015da8c);
+};
+
+////////////////
+// vfcvt.f.xu //
+////////////////
+
+void TEST_CASE9(void) {
+  VSET(16, e16, m1);
+  //                   55973,      61786,      64322,      55940,      55857,
+  //                   3425,       1068,       4246,      57901,       7342,
+  //                   8693,      60988,       9047,      63358,      58389,
+  //                   8076
+  VLOAD_16(v2, 0xdaa5, 0xf15a, 0xfb42, 0xda84, 0xda31, 0x0d61, 0x042c, 0x1096,
+           0xe22d, 0x1cae, 0x21f5, 0xee3c, 0x2357, 0xf77e, 0xe415, 0x1f8c);
+  asm volatile("vfcvt.f.xu.v v3, v2");
+  //                55968.000,   61792.000,   64320.000,   55936.000, 55872.000,
+  //                3424.000,   1068.000,   4248.000,   57888.000,   7344.000,
+  //                8696.000,   60992.000,   9048.000,   63360.000,   58400.000,
+  //                8076.000
+  VCMP_U16(25, v3, 0x7ad5, 0x7b8b, 0x7bda, 0x7ad4, 0x7ad2, 0x6ab0, 0x642c,
+           0x6c26, 0x7b11, 0x6f2c, 0x703f, 0x7b72, 0x706b, 0x7bbc, 0x7b21,
+           0x6fe3);
+
+  VSET(16, e32, m1);
+  //                       72473,     4294949057,          50975, 4294915723,
+  //                       4294876584,     4294895088,          24967, 34761,
+  //                       83805,          68361,          49397, 51562, 24877,
+  //                       4294942241,     4294909502,          42562
+  VLOAD_32(v2, 0x00011b19, 0xffffb8c1, 0x0000c71f, 0xffff368b, 0xfffe9da8,
+           0xfffee5f0, 0x00006187, 0x000087c9, 0x0001475d, 0x00010b09,
+           0x0000c0f5, 0x0000c96a, 0x0000612d, 0xffff9e21, 0xffff1e3e,
+           0x0000a642);
+  asm volatile("vfcvt.f.xu.v v3, v2");
+  //                72473.000,   4294949120.000,   50975.000,   4294915840.000,
+  //                4294876672.000,   4294895104.000,   24967.000,   34761.000,
+  //                83805.000,   68361.000,   49397.000,   51562.000, 24877.000,
+  //                4294942208.000,   4294909440.000,   42562.000
+  VCMP_U32(26, v3, 0x478d8c80, 0x4f7fffb9, 0x47471f00, 0x4f7fff37, 0x4f7ffe9e,
+           0x4f7ffee6, 0x46c30e00, 0x4707c900, 0x47a3ae80, 0x47858480,
+           0x4740f500, 0x47496a00, 0x46c25a00, 0x4f7fff9e, 0x4f7fff1e,
+           0x47264200);
+
+  VSET(16, e64, m1);
+  //                 18446744073707704187,    18446744073702261660, 4325496,
+  //                 3834488,    18446744073707063867,    18446744073706356425,
+  //                 5215660,    18446744073707545423,                  69532,
+  //                 18446744073707444829,                4236283, 3402850,
+  //                 18446744073708706866,                 275183, 4230347,
+  //                 18446744073704794800
+  VLOAD_64(v2, 0xffffffffffe3cf7b, 0xffffffffff90c39c, 0x0000000000420078,
+           0x00000000003a8278, 0xffffffffffda0a3b, 0xffffffffffcf3ec9,
+           0x00000000004f95ac, 0xffffffffffe1634f, 0x0000000000010f9c,
+           0xffffffffffdfda5d, 0x000000000040a3fb, 0x000000000033ec62,
+           0xfffffffffff31c32, 0x00000000000432ef, 0x0000000000408ccb,
+           0xffffffffffb76ab0);
+  asm volatile("vfcvt.f.xu.v v3, v2");
+  //                18446744073707704320.000,   18446744073702260736.000,
+  //                4325496.000,   3834488.000,   18446744073707063296.000,
+  //                18446744073706356736.000,   5215660.000,
+  //                18446744073707544576.000,   69532.000,
+  //                18446744073707444224.000,   4236283.000,   3402850.000,
+  //                18446744073708707840.000,   275183.000,   4230347.000,
+  //                18446744073704794112.000
+  VCMP_U64(27, v3, 0x43effffffffffc7a, 0x43effffffffff218, 0x4150801e00000000,
+           0x414d413c00000000, 0x43effffffffffb41, 0x43effffffffff9e8,
+           0x4153e56b00000000, 0x43effffffffffc2c, 0x40f0f9c000000000,
+           0x43effffffffffbfb, 0x415028fec0000000, 0x4149f63100000000,
+           0x43effffffffffe64, 0x4110cbbc00000000, 0x41502332c0000000,
+           0x43effffffffff6ed);
+};
+
+// Simple random test with similar values (masked)
+// The numbers are the same of TEST_CASE1
+void TEST_CASE10(void) {
+  VSET(16, e16, m1);
+  //                   55973,      61786,      64322,      55940,      55857,
+  //                   3425,       1068,       4246,      57901,       7342,
+  //                   8693,      60988,       9047,      63358,      58389,
+  //                   8076
+  VLOAD_16(v2, 0xdaa5, 0xf15a, 0xfb42, 0xda84, 0xda31, 0x0d61, 0x042c, 0x1096,
+           0xe22d, 0x1cae, 0x21f5, 0xee3c, 0x2357, 0xf77e, 0xe415, 0x1f8c);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v3);
+  asm volatile("vfcvt.f.xu.v v3, v2, v0.t");
+  //                0.000,   61792.000,   0.000,   55936.000,   0.000, 3424.000,
+  //                0.000,   4248.000,   0.000,   7344.000,   0.000, 60992.000,
+  //                0.000,   63360.000,   0.000,   8076.000
+  VCMP_U16(28, v3, 0x0, 0x7b8b, 0x0, 0x7ad4, 0x0, 0x6ab0, 0x0, 0x6c26, 0x0,
+           0x6f2c, 0x0, 0x7b72, 0x0, 0x7bbc, 0x0, 0x6fe3);
+
+  VSET(16, e32, m1);
+  //                       72473,     4294949057,          50975, 4294915723,
+  //                       4294876584,     4294895088,          24967, 34761,
+  //                       83805,          68361,          49397, 51562, 24877,
+  //                       4294942241,     4294909502,          42562
+  VLOAD_32(v2, 0x00011b19, 0xffffb8c1, 0x0000c71f, 0xffff368b, 0xfffe9da8,
+           0xfffee5f0, 0x00006187, 0x000087c9, 0x0001475d, 0x00010b09,
+           0x0000c0f5, 0x0000c96a, 0x0000612d, 0xffff9e21, 0xffff1e3e,
+           0x0000a642);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v3);
+  asm volatile("vfcvt.f.xu.v v3, v2, v0.t");
+  //                0.000,   4294949120.000,   0.000,   4294915840.000,   0.000,
+  //                4294895104.000,   0.000,   34761.000,   0.000,   68361.000,
+  //                0.000,   51562.000,   0.000,   4294942208.000,   0.000,
+  //                42562.000
+  VCMP_U32(29, v3, 0x0, 0x4f7fffb9, 0x0, 0x4f7fff37, 0x0, 0x4f7ffee6, 0x0,
+           0x4707c900, 0x0, 0x47858480, 0x0, 0x47496a00, 0x0, 0x4f7fff9e, 0x0,
+           0x47264200);
+
+  VSET(16, e64, m1);
+  //                 18446744073707704187,    18446744073702261660, 4325496,
+  //                 3834488,    18446744073707063867,    18446744073706356425,
+  //                 5215660,    18446744073707545423,                  69532,
+  //                 18446744073707444829,                4236283, 3402850,
+  //                 18446744073708706866,                 275183, 4230347,
+  //                 18446744073704794800
+  VLOAD_64(v2, 0xffffffffffe3cf7b, 0xffffffffff90c39c, 0x0000000000420078,
+           0x00000000003a8278, 0xffffffffffda0a3b, 0xffffffffffcf3ec9,
+           0x00000000004f95ac, 0xffffffffffe1634f, 0x0000000000010f9c,
+           0xffffffffffdfda5d, 0x000000000040a3fb, 0x000000000033ec62,
+           0xfffffffffff31c32, 0x00000000000432ef, 0x0000000000408ccb,
+           0xffffffffffb76ab0);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v3);
+  asm volatile("vfcvt.f.xu.v v3, v2, v0.t");
+  //                0.000,   18446744073702260736.000,   0.000,   3834488.000,
+  //                0.000,   18446744073706356736.000,   0.000,
+  //                18446744073707544576.000,   0.000, 18446744073707444224.000,
+  //                0.000,   3402850.000,   0.000,   275183.000,   0.000,
+  //                18446744073704794112.000
+  VCMP_U64(30, v3, 0x0, 0x43effffffffff218, 0x0, 0x414d413c00000000, 0x0,
+           0x43effffffffff9e8, 0x0, 0x43effffffffffc2c, 0x0, 0x43effffffffffbfb,
+           0x0, 0x4149f63100000000, 0x0, 0x4110cbbc00000000, 0x0,
+           0x43effffffffff6ed);
+};
+
+///////////////
+// vfcvt.f.x //
+///////////////
+
+void TEST_CASE11(void) {
+  VSET(16, e16, m1);
+  //                   -4779,        465,       9893,      -6763,      -4072,
+  //                   1612,      -9552,       2426,        325,       7561,
+  //                   -8581,      -1741,      -8518,      -4699,       3653,
+  //                   9937
+  VLOAD_16(v2, 0xed55, 0x01d1, 0x26a5, 0xe595, 0xf018, 0x064c, 0xdab0, 0x097a,
+           0x0145, 0x1d89, 0xde7b, 0xf933, 0xdeba, 0xeda5, 0x0e45, 0x26d1);
+  asm volatile("vfcvt.f.x.v v3, v2");
+  //              -4780.000,   465.000,   9896.000, -6764.000, -4072.000,
+  //              1612.000, -9552.000,   2426.000,   325.000,   7560.000,
+  //              -8584.000, -1741.000, -8520.000, -4700.000,   3652.000,
+  //              9936.000
+  VCMP_U16(31, v3, 0xecab, 0x5f44, 0x70d5, 0xee9b, 0xebf4, 0x664c, 0xf0aa,
+           0x68bd, 0x5d14, 0x6f62, 0xf031, 0xe6cd, 0xf029, 0xec97, 0x6b22,
+           0x70da);
+
+  VSET(16, e32, m1);
+  //                      -39422,          54262,          12833, -40266,
+  //                      -64918,          28317,          89178, 54320, -99922,
+  //                      -73005,          95070,         -24716, 60663, 59516,
+  //                      14865,          26328
+  VLOAD_32(v2, 0xffff6602, 0x0000d3f6, 0x00003221, 0xffff62b6, 0xffff026a,
+           0x00006e9d, 0x00015c5a, 0x0000d430, 0xfffe79ae, 0xfffee2d3,
+           0x0001735e, 0xffff9f74, 0x0000ecf7, 0x0000e87c, 0x00003a11,
+           0x000066d8);
+  asm volatile("vfcvt.f.x.v v3, v2");
+  //              -39422.000,   54262.000,   12833.000, -40266.000, -64918.000,
+  //              28317.000,   89178.000,   54320.000, -99922.000, -73005.000,
+  //              95070.000, -24716.000,   60663.000,   59516.000,   14865.000,
+  //              26328.000
+  VCMP_U32(32, v3, 0xc719fe00, 0x4753f600, 0x46488400, 0xc71d4a00, 0xc77d9600,
+           0x46dd3a00, 0x47ae2d00, 0x47543000, 0xc7c32900, 0xc78e9680,
+           0x47b9af00, 0xc6c11800, 0x476cf700, 0x47687c00, 0x46684400,
+           0x46cdb000);
+
+  VSET(16, e64, m1);
+  //                            -8860682,                8064547, -5636078,
+  //                            -3712253,                8492493, 9839246,
+  //                            -8271278,               -6234598, -4538479,
+  //                            8807688,                5640899, 3839761,
+  //                            -1394518,               -6118355, 1783927,
+  //                            5819812
+  VLOAD_64(v2, 0xffffffffff78cbf6, 0x00000000007b0e23, 0xffffffffffaa0012,
+           0xffffffffffc75b03, 0x00000000008195cd, 0x000000000096228e,
+           0xffffffffff81ca52, 0xffffffffffa0de1a, 0xffffffffffbabf91,
+           0x0000000000866508, 0x00000000005612c3, 0x00000000003a9711,
+           0xffffffffffeab8aa, 0xffffffffffa2a42d, 0x00000000001b3877,
+           0x000000000058cda4);
+  asm volatile("vfcvt.f.x.v v3, v2");
+  //              -8860682.000,   8064547.000, -5636078.000, -3712253.000,
+  //              8492493.000,   9839246.000, -8271278.000, -6234598.000,
+  //              -4538479.000,   8807688.000,   5640899.000,   3839761.000,
+  //              -1394518.000, -6118355.000,   1783927.000,   5819812.000
+  VCMP_U64(33, v3, 0xc160e68140000000, 0x415ec388c0000000, 0xc1557ffb80000000,
+           0xc14c527e80000000, 0x416032b9a0000000, 0x4162c451c0000000,
+           0xc15f8d6b80000000, 0xc157c87980000000, 0xc151501bc0000000,
+           0x4160cca100000000, 0x415584b0c0000000, 0x414d4b8880000000,
+           0xc135475600000000, 0xc15756f4c0000000, 0x413b387700000000,
+           0x4156336900000000);
+};
+
+// Simple random test with similar values (masked)
+// The numbers are the same of TEST_CASE1
+void TEST_CASE12(void) {
+  VSET(16, e16, m1);
+  //                   -4779,        465,       9893,      -6763,      -4072,
+  //                   1612,      -9552,       2426,        325,       7561,
+  //                   -8581,      -1741,      -8518,      -4699,       3653,
+  //                   9937
+  VLOAD_16(v2, 0xed55, 0x01d1, 0x26a5, 0xe595, 0xf018, 0x064c, 0xdab0, 0x097a,
+           0x0145, 0x1d89, 0xde7b, 0xf933, 0xdeba, 0xeda5, 0x0e45, 0x26d1);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v3);
+  asm volatile("vfcvt.f.x.v v3, v2, v0.t");
+  //                0.000,   465.000,   0.000, -6764.000,   0.000,   1612.000,
+  //                0.000,   2426.000,   0.000,   7560.000,   0.000, -1741.000,
+  //                0.000, -4700.000,   0.000,   9936.000
+  VCMP_U16(34, v3, 0x0, 0x5f44, 0x0, 0xee9b, 0x0, 0x664c, 0x0, 0x68bd, 0x0,
+           0x6f62, 0x0, 0xe6cd, 0x0, 0xec97, 0x0, 0x70da);
+
+  VSET(16, e32, m1);
+  //                      -39422,          54262,          12833, -40266,
+  //                      -64918,          28317,          89178, 54320, -99922,
+  //                      -73005,          95070,         -24716, 60663, 59516,
+  //                      14865,          26328
+  VLOAD_32(v2, 0xffff6602, 0x0000d3f6, 0x00003221, 0xffff62b6, 0xffff026a,
+           0x00006e9d, 0x00015c5a, 0x0000d430, 0xfffe79ae, 0xfffee2d3,
+           0x0001735e, 0xffff9f74, 0x0000ecf7, 0x0000e87c, 0x00003a11,
+           0x000066d8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v3);
+  asm volatile("vfcvt.f.x.v v3, v2, v0.t");
+  //                0.000,   54262.000,   0.000, -40266.000,   0.000, 28317.000,
+  //                0.000,   54320.000,   0.000, -73005.000,   0.000,
+  //                -24716.000,   0.000,   59516.000,   0.000,   26328.000
+  VCMP_U32(35, v3, 0x0, 0x4753f600, 0x0, 0xc71d4a00, 0x0, 0x46dd3a00, 0x0,
+           0x47543000, 0x0, 0xc78e9680, 0x0, 0xc6c11800, 0x0, 0x47687c00, 0x0,
+           0x46cdb000);
+
+  VSET(16, e64, m1);
+  //                            -8860682,                8064547, -5636078,
+  //                            -3712253,                8492493, 9839246,
+  //                            -8271278,               -6234598, -4538479,
+  //                            8807688,                5640899, 3839761,
+  //                            -1394518,               -6118355, 1783927,
+  //                            5819812
+  VLOAD_64(v2, 0xffffffffff78cbf6, 0x00000000007b0e23, 0xffffffffffaa0012,
+           0xffffffffffc75b03, 0x00000000008195cd, 0x000000000096228e,
+           0xffffffffff81ca52, 0xffffffffffa0de1a, 0xffffffffffbabf91,
+           0x0000000000866508, 0x00000000005612c3, 0x00000000003a9711,
+           0xffffffffffeab8aa, 0xffffffffffa2a42d, 0x00000000001b3877,
+           0x000000000058cda4);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v3);
+  asm volatile("vfcvt.f.x.v v3, v2, v0.t");
+  //                0.000,   8064547.000,   0.000, -3712253.000,   0.000,
+  //                9839246.000,   0.000, -6234598.000,   0.000,   8807688.000,
+  //                0.000,   3839761.000,   0.000, -6118355.000,   0.000,
+  //                5819812.000
+  VCMP_U64(36, v3, 0x0, 0x415ec388c0000000, 0x0, 0xc14c527e80000000, 0x0,
+           0x4162c451c0000000, 0x0, 0xc157c87980000000, 0x0, 0x4160cca100000000,
+           0x0, 0x414d4b8880000000, 0x0, 0xc15756f4c0000000, 0x0,
+           0x4156336900000000);
+};
+
+int main(void) {
+  enable_vec();
+  enable_fp();
+
+  TEST_CASE1();
+  TEST_CASE2();
+
+  TEST_CASE3();
+  TEST_CASE4();
+
+  TEST_CASE5();
+  TEST_CASE6();
+
+  TEST_CASE7();
+  TEST_CASE8();
+
+  TEST_CASE9();
+  TEST_CASE10();
+
+  TEST_CASE11();
+  TEST_CASE12();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vfdiv.c b/apps/riscv-tests/isa/rv64uv/vfdiv.c
new file mode 100644
index 0000000..eb90a66
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vfdiv.c
@@ -0,0 +1,355 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+// Simple random test with similar values + 1 subnormal
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  //              -0.8057, -0.8564,  0.3425, -0.3066, -0.7314, -0.6396,  0.7588,
+  //              -0.3743,  0.8706, -0.3064,  0.0390,  0.6123,  0.0237, -0.6201,
+  //              -0.4524,  0.3337
+  VLOAD_16(v2, 0xba72, 0xbada, 0x357b, 0xb4e8, 0xb9da, 0xb91e, 0x3a12, 0xb5fd,
+           0x3af7, 0xb4e7, 0x28fe, 0x38e6, 0x2612, 0xb8f6, 0xb73d, 0x3557);
+  //              -0.4094,  0.0410, -0.7305,  0.9038, -0.3545,  0.2830, -0.7051,
+  //              -0.7124, -0.6348,  0.1256,  0.5576,  0.1334,  0.8779, -0.4836,
+  //              0.3215,  0.4167
+  VLOAD_16(v3, 0xb68d, 0x293e, 0xb9d8, 0x3b3b, 0xb5ac, 0x3487, 0xb9a4, 0xb9b3,
+           0xb914, 0x3005, 0x3876, 0x3045, 0x3b06, 0xb7bd, 0x3525, 0x36ab);
+  asm volatile("vfdiv.vv v1, v2, v3");
+  //               1.9678, -20.9062, -0.4690, -0.3394,  2.0625, -2.2598,
+  //               -1.0762,  0.5254, -1.3711, -2.4395,  0.0699,  4.5898, 0.0270,
+  //               1.2822, -1.4072,  0.8008
+  VCMP_U16(1, v1, 0x3fdf, 0xcd3a, 0xb780, 0xb56d, 0x4020, 0xc085, 0xbc4e,
+           0x3833, 0xbd7c, 0xc0e0, 0x2c79, 0x4496, 0x26ea, 0x3d20, 0xbda0,
+           0x3a68);
+
+  VSET(16, e32, m1);
+  //               0.64838839,  0.00666664, -0.13619921,  0.21094505,
+  //               -0.51040554, -0.77216595,  0.42111391,  0.82974166,
+  //               -0.31227046,  0.68854737, -0.72970057,  0.10843290,
+  //               -0.38442346,  0.18102080,  0.57249051,  0.76465768
+  VLOAD_32(v2, 0x3f25fcc8, 0x3bda73da, 0xbe0b77ce, 0x3e5801fb, 0xbf02a9f0,
+           0xbf45acab, 0x3ed79c3e, 0x3f5469f3, 0xbe9fe1ea, 0x3f3044a4,
+           0xbf3acda8, 0x3dde1212, 0xbec4d327, 0x3e395d84, 0x3f128ebd,
+           0x3f43c09b);
+  //              -0.59629226, -0.46890569,  0.99662799, -0.49397555,
+  //              0.80701596,  0.55786854, -0.26524273, -0.04642257,
+  //              -0.67671824,  0.64403933,  0.06642481,  0.26544699,
+  //              -0.00225505,  0.27478188,  0.76509053,  0.36194146
+  VLOAD_32(v3, 0xbf18a69c, 0xbef01468, 0x3f7f2303, 0xbefcea5d, 0x3f4e9899,
+           0x3f0ed079, 0xbe87cde5, 0xbd3e2597, 0xbf2d3d68, 0x3f24dfc3,
+           0x3d8809bb, 0x3e87e8ab, 0xbb13c97d, 0x3e8cb036, 0x3f43dcf9,
+           0x3eb95064);
+  asm volatile("vfdiv.vv v1, v2, v3");
+  //              -1.08736682, -0.01421745, -0.13666002, -0.42703542,
+  //              -0.63246030, -1.38413608, -1.58765483, -17.87367058,
+  //              0.46144828,  1.06910765, -10.98536205,  0.40849173,
+  //              170.47213745,  0.65877998,  0.74826509,  2.11265564
+  VCMP_U32(2, v1, 0xbf8b2ed5, 0xbc68f04d, 0xbe0bf09b, 0xbedaa462, 0xbf21e8ea,
+           0xbfb12b5e, 0xbfcb3846, 0xc18efd46, 0x3eec42f2, 0x3f88d884,
+           0xc12fc40a, 0x3ed125d4, 0x432a78dd, 0x3f28a5cd, 0x3f3f8e4c,
+           0x400735c0);
+
+  VSET(16, e64, m1);
+  //              -0.6201645522687720,  0.7701971477336478,  0.3292637140913006,
+  //              -0.8434179184761514, -0.7347451981263740,  0.6543864439701519,
+  //              0.1228421097534835, -0.5052233099528094, -0.5128552707464591,
+  //              0.9434287237802566, -0.5723896115412233, -0.5719579148082712,
+  //              -0.6537028651114556,  0.1091378410914579, -0.7602559429758879,
+  //              0.2908894437497427
+  VLOAD_64(v2, 0xbfe3d86354c44060, 0x3fe8a5747d1fa1c6, 0x3fd512a81cf2063c,
+           0xbfeafd479316e516, 0xbfe783085c9b10ee, 0x3fe4f0bbd6f98570,
+           0x3fbf72949bf67da0, 0xbfe02aca132d92f2, 0xbfe0694f74edfe18,
+           0x3fee30916f57c874, 0xbfe2510404c47868, 0xbfe24d7aaf5946b0,
+           0xbfe4eb22455e9102, 0x3fbbf075223e6d60, 0xbfe854044575797c,
+           0x3fd29deec1ea08a0);
+  //               0.6660375425590812, -0.9603615652916235, -0.1168804546788573,
+  //               -0.3258082002843947,  0.0488865860405421,
+  //               -0.1515621417461690, -0.1189568642850463,
+  //               -0.1213016259965920, -0.1369814061459547, 0.5914369694708146,
+  //               0.7538814889966272,  0.2346701936201294,  0.9227364529293489,
+  //               0.9447507336323382, -0.4250995717346850, -0.0882167932097473
+  VLOAD_64(v3, 0x3fe5502df6e661fe, 0xbfeebb482d68699c, 0xbfbdebe0a2632640,
+           0xbfd4da0aa33f5db0, 0x3fa907a9a083b220, 0xbfc36663650e4608,
+           0xbfbe73f501bd2e10, 0xbfbf0d9f949b6370, 0xbfc1889b51c74ac0,
+           0x3fe2ed0d3930b850, 0x3fe81fcc12899c0a, 0x3fce09ac4378e388,
+           0x3fed870e9905133a, 0x3fee3b65e3fa5532, 0xbfdb34d4d5893894,
+           0xbfb6956031cb3a60);
+  asm volatile("vfdiv.vv v1, v2, v3");
+  //              -0.9311255186696326, -0.8019866429158581, -2.8170981623573508,
+  //              2.5886945685834193, -15.0295870019854370, -4.3176114854994303,
+  //              -1.0326609606918302,  4.1650167984310764,  3.7439772679805032,
+  //              1.5951466892987514, -0.7592567530780479, -2.4372840282141826,
+  //              -0.7084394065458121,  0.1155202501636058,  1.7884185106880846,
+  //              -3.2974384260161655
+  VCMP_U64(3, v1, 0xbfedcbc7be65070a, 0xbfe9a9dfe464e0ca, 0xc006896ac2e79279,
+           0x4004b5a57f7b305c, 0xc02e0f26070bd40a, 0xc011453bf1fc3753,
+           0xbff085c77fe07008, 0x4010a8fa29e23558, 0x400df3aa5a978cad,
+           0x3ff985b888edc5e0, 0xbfe84bd4d177987a, 0xc0037f8ec4c1f1c6,
+           0xbfe6ab891e49fb2d, 0x3fbd92bc307a7a1b, 0x3ffc9d5cba6f762a,
+           0xc00a612765c28153);
+};
+
+// Simple random test with similar values + 1 subnormal (masked)
+// The numbers are the same of TEST_CASE1
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  //              -0.8057, -0.8564,  0.3425, -0.3066, -0.7314, -0.6396,  0.7588,
+  //              -0.3743,  0.8706, -0.3064,  0.0390,  0.6123,  0.0237, -0.6201,
+  //              -0.4524,  0.3337
+  VLOAD_16(v2, 0xba72, 0xbada, 0x357b, 0xb4e8, 0xb9da, 0xb91e, 0x3a12, 0xb5fd,
+           0x3af7, 0xb4e7, 0x28fe, 0x38e6, 0x2612, 0xb8f6, 0xb73d, 0x3557);
+  //              -0.4094,  0.0410, -0.7305,  0.9038, -0.3545,  0.2830, -0.7051,
+  //              -0.7124, -0.6348,  0.1256,  0.5576,  0.1334,  0.8779, -0.4836,
+  //              0.3215,  0.4167
+  VLOAD_16(v3, 0xb68d, 0x293e, 0xb9d8, 0x3b3b, 0xb5ac, 0x3487, 0xb9a4, 0xb9b3,
+           0xb914, 0x3005, 0x3876, 0x3045, 0x3b06, 0xb7bd, 0x3525, 0x36ab);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfdiv.vv v1, v2, v3, v0.t");
+  //               0.0000, -20.9062,  0.0000, -0.3394,  0.0000, -2.2598, 0.0000,
+  //               0.5254,  0.0000, -2.4395,  0.0000,  4.5898,  0.0000,  1.2822,
+  //               0.0000,  0.8008
+  VCMP_U16(4, v1, 0x0, 0xcd3a, 0x0, 0xb56d, 0x0, 0xc085, 0x0, 0x3833, 0x0,
+           0xc0e0, 0x0, 0x4496, 0x0, 0x3d20, 0x0, 0x3a68);
+
+  VSET(16, e32, m1);
+  //               0.64838839,  0.00666664, -0.13619921,  0.21094505,
+  //               -0.51040554, -0.77216595,  0.42111391,  0.82974166,
+  //               -0.31227046,  0.68854737, -0.72970057,  0.10843290,
+  //               -0.38442346,  0.18102080,  0.57249051,  0.76465768
+  VLOAD_32(v2, 0x3f25fcc8, 0x3bda73da, 0xbe0b77ce, 0x3e5801fb, 0xbf02a9f0,
+           0xbf45acab, 0x3ed79c3e, 0x3f5469f3, 0xbe9fe1ea, 0x3f3044a4,
+           0xbf3acda8, 0x3dde1212, 0xbec4d327, 0x3e395d84, 0x3f128ebd,
+           0x3f43c09b);
+  //              -0.59629226, -0.46890569,  0.99662799, -0.49397555,
+  //              0.80701596,  0.55786854, -0.26524273, -0.04642257,
+  //              -0.67671824,  0.64403933,  0.06642481,  0.26544699,
+  //              -0.00225505,  0.27478188,  0.76509053,  0.36194146
+  VLOAD_32(v3, 0xbf18a69c, 0xbef01468, 0x3f7f2303, 0xbefcea5d, 0x3f4e9899,
+           0x3f0ed079, 0xbe87cde5, 0xbd3e2597, 0xbf2d3d68, 0x3f24dfc3,
+           0x3d8809bb, 0x3e87e8ab, 0xbb13c97d, 0x3e8cb036, 0x3f43dcf9,
+           0x3eb95064);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfdiv.vv v1, v2, v3, v0.t");
+  //               0.00000000, -0.01421745,  0.00000000, -0.42703542,
+  //               0.00000000, -1.38413608,  0.00000000, -17.87367058,
+  //               0.00000000,  1.06910765,  0.00000000,  0.40849173,
+  //               0.00000000,  0.65877998,  0.00000000,  2.11265564
+  VCMP_U32(5, v1, 0x0, 0xbc68f04d, 0x0, 0xbedaa462, 0x0, 0xbfb12b5e, 0x0,
+           0xc18efd46, 0x0, 0x3f88d884, 0x0, 0x3ed125d4, 0x0, 0x3f28a5cd, 0x0,
+           0x400735c0);
+
+  VSET(16, e64, m1);
+  //              -0.6201645522687720,  0.7701971477336478,  0.3292637140913006,
+  //              -0.8434179184761514, -0.7347451981263740,  0.6543864439701519,
+  //              0.1228421097534835, -0.5052233099528094, -0.5128552707464591,
+  //              0.9434287237802566, -0.5723896115412233, -0.5719579148082712,
+  //              -0.6537028651114556,  0.1091378410914579, -0.7602559429758879,
+  //              0.2908894437497427
+  VLOAD_64(v2, 0xbfe3d86354c44060, 0x3fe8a5747d1fa1c6, 0x3fd512a81cf2063c,
+           0xbfeafd479316e516, 0xbfe783085c9b10ee, 0x3fe4f0bbd6f98570,
+           0x3fbf72949bf67da0, 0xbfe02aca132d92f2, 0xbfe0694f74edfe18,
+           0x3fee30916f57c874, 0xbfe2510404c47868, 0xbfe24d7aaf5946b0,
+           0xbfe4eb22455e9102, 0x3fbbf075223e6d60, 0xbfe854044575797c,
+           0x3fd29deec1ea08a0);
+  //               0.6660375425590812, -0.9603615652916235, -0.1168804546788573,
+  //               -0.3258082002843947,  0.0488865860405421,
+  //               -0.1515621417461690, -0.1189568642850463,
+  //               -0.1213016259965920, -0.1369814061459547, 0.5914369694708146,
+  //               0.7538814889966272,  0.2346701936201294,  0.9227364529293489,
+  //               0.9447507336323382, -0.4250995717346850, -0.0882167932097473
+  VLOAD_64(v3, 0x3fe5502df6e661fe, 0xbfeebb482d68699c, 0xbfbdebe0a2632640,
+           0xbfd4da0aa33f5db0, 0x3fa907a9a083b220, 0xbfc36663650e4608,
+           0xbfbe73f501bd2e10, 0xbfbf0d9f949b6370, 0xbfc1889b51c74ac0,
+           0x3fe2ed0d3930b850, 0x3fe81fcc12899c0a, 0x3fce09ac4378e388,
+           0x3fed870e9905133a, 0x3fee3b65e3fa5532, 0xbfdb34d4d5893894,
+           0xbfb6956031cb3a60);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfdiv.vv v1, v2, v3, v0.t");
+  //               0.0000000000000000, -0.8019866429158581,
+  //               0.0000000000000000,  2.5886945685834193,  0.0000000000000000,
+  //               -4.3176114854994303, 0.0000000000000000,  4.1650167984310764,
+  //               0.0000000000000000,  1.5951466892987514,  0.0000000000000000,
+  //               -2.4372840282141826,  0.0000000000000000, 0.1155202501636058,
+  //               0.0000000000000000, -3.2974384260161655
+  VCMP_U64(6, v1, 0x0, 0xbfe9a9dfe464e0ca, 0x0, 0x4004b5a57f7b305c, 0x0,
+           0xc011453bf1fc3753, 0x0, 0x4010a8fa29e23558, 0x0, 0x3ff985b888edc5e0,
+           0x0, 0xc0037f8ec4c1f1c6, 0x0, 0x3fbd92bc307a7a1b, 0x0,
+           0xc00a612765c28153);
+};
+
+// Simple random test with similar values (vector-scalar)
+void TEST_CASE3(void) {
+  VSET(16, e16, m1);
+  //              -0.0933,  0.4983,  0.5918, -0.0608,  0.0790, -0.2864, -0.7656,
+  //              0.4878,  0.8862,  0.4255,  0.9561, -0.7158, -0.3247,  0.9961,
+  //              -0.4963, -0.4114
+  VLOAD_16(v2, 0xadf9, 0x37f9, 0x38bc, 0xabc7, 0x2d0f, 0xb495, 0xba20, 0x37ce,
+           0x3b17, 0x36cf, 0x3ba6, 0xb9ba, 0xb532, 0x3bf8, 0xb7f1, 0xb695);
+  double dscalar_16;
+  //                             -0.3206
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0xb521);
+  asm volatile("vfdiv.vf v1, v2, %[A]" ::[A] "f"(dscalar_16));
+  //               0.2910, -1.5547, -1.8457,  0.1896, -0.2466,  0.8936,  2.3887,
+  //               -1.5215, -2.7656, -1.3271, -2.9824,  2.2324,  1.0127,
+  //               -3.1074,  1.5488,  1.2832
+  VCMP_U16(7, v1, 0x34a8, 0xbe37, 0xbf62, 0x3210, 0xb3e3, 0x3b25, 0x40c6,
+           0xbe16, 0xc187, 0xbd4f, 0xc1f7, 0x4077, 0x3c0d, 0xc236, 0x3e31,
+           0x3d22);
+
+  VSET(16, e32, m1);
+  //               0.74354362,  0.49774653,  0.25714639,  0.51635689,
+  //               0.74569613,  0.41876560,  0.21346331,  0.08743033,
+  //               -0.15111920, -0.93289024,  0.08753468, -0.33427054,
+  //               0.06167563, -0.54564798,  0.78990245, -0.77273035
+  VLOAD_32(v2, 0x3f3e58e0, 0x3efed8a2, 0x3e83a8b1, 0x3f042ff7, 0x3f3ee5f1,
+           0x3ed66872, 0x3e5a9620, 0x3db30eac, 0xbe1abefe, 0xbf6ed1e5,
+           0x3db34562, 0xbeab2582, 0x3d7c9f95, 0xbf0baf96, 0x3f4a370c,
+           0xbf45d1a8);
+  double dscalar_32;
+  //                              -0.45971388
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0xbeeb5f9e);
+  asm volatile("vfdiv.vf v1, v2, %[A]" ::[A] "f"(dscalar_32));
+  //              -1.61740518, -1.08273113, -0.55936182, -1.12321365,
+  //              -1.62208748, -0.91092664, -0.46433949, -0.19018422,
+  //              0.32872447,  2.02928448, -0.19041122,  0.72712737,
+  //              -0.13416091,  1.18692958, -1.71824801,  1.68089414
+  VCMP_U32(8, v1, 0xbfcf0722, 0xbf8a96ef, 0xbf0f3255, 0xbf8fc576, 0xbfcfa090,
+           0xbf69327c, 0xbeedbde7, 0xbe42bfa7, 0x3ea84e93, 0x4001dfcc,
+           0xbe42fb28, 0x3f3a2504, 0xbe096179, 0x3f97ed4e, 0xbfdbef8c,
+           0x3fd72789);
+
+  VSET(16, e64, m1);
+  //               -0.8580137874650531, -0.4775160339931992, 0.3831482495481682,
+  //               -0.3582952848420831,  0.0009796501269754, 0.5485795361059773,
+  //               -0.8055070333165963, -0.2632019868496005,
+  //               -0.0782680309690278, -0.7119901734202212,
+  //               -0.5084969452651125, -0.7586325258910223, 0.6253847342253853,
+  //               0.5751160060426936,  0.0609762717873976, -0.7366654110036495
+  VLOAD_64(v2, 0xbfeb74d95495be72, 0xbfde8f9f69544024, 0x3fd885803c550ed0,
+           0xbfd6ee4f58ad4bcc, 0x3f500cf35070c000, 0x3fe18df6abda8f8e,
+           0xbfe9c6b6af995e52, 0xbfd0d84d2570b86c, 0xbfb4095fa9559400,
+           0xbfe6c89f9dbd3916, 0xbfe0459b62c0f228, 0xbfe846b7b80c4834,
+           0x3fe40326d89d4d44, 0x3fe26759aeab8116, 0x3faf38482a5158c0,
+           0xbfe792c3570b5cc2);
+  double dscalar_64;
+  //                                0.0072652319849018
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0x3f7dc225dc5e3c00);
+  asm volatile("vfdiv.vf v1, v2, %[A]" ::[A] "f"(dscalar_64));
+  //              -118.0986084474836275,
+  //              -65.7261922242188206,  52.7372354171766275,
+  //              -49.3164272781202087,
+  //              0.1348408597290880,  75.5075044053657223,
+  //              -110.8714814599939871, -36.2276094413188474,
+  //              -10.7729568899768022, -97.9996474854262800,
+  //              -69.9904622896889919,
+  //              -104.4195873535172723,  86.0791142698573424,  79.1600333255520070,
+  //              8.3928870976336363, -101.3959929338175954
+  VCMP_U64(9, v1, 0xc05d864f99ce434b, 0xc0506e79eef36846, 0x404a5e5dbaeb1cfe,
+           0xc048a880b0658b57, 0x3fc142771d59b8f1, 0x4052e07af3c1e7c9,
+           0xc05bb7c65a2c6fa6, 0xc0421d224e615cd6, 0xc0258bc101675622,
+           0xc0587ffa39725bce, 0xc0517f63bbf188ac, 0xc05a1ada84ea4b00,
+           0x40558510354c6bc9, 0x4053ca3dfc6ae106, 0x4020c9287f66b6b2,
+           0xc0595957f2bf0c64);
+};
+
+// Simple random test with similar values (vector-scalar) (masked)
+void TEST_CASE4(void) {
+  VSET(16, e16, m1);
+  //               -0.0933,  0.4983,  0.5918, -0.0608,  0.0790, -0.2864,
+  //               -0.7656,  0.4878,  0.8862,  0.4255,  0.9561, -0.7158,
+  //               -0.3247,  0.9961, -0.4963, -0.4114
+  VLOAD_16(v2, 0xadf9, 0x37f9, 0x38bc, 0xabc7, 0x2d0f, 0xb495, 0xba20, 0x37ce,
+           0x3b17, 0x36cf, 0x3ba6, 0xb9ba, 0xb532, 0x3bf8, 0xb7f1, 0xb695);
+  double dscalar_16;
+  //                             -0.3206
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0xb521);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfdiv.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_16));
+  //                0.0000, -1.5547,  0.0000,  0.1896,  0.0000,  0.8936, 0.0000,
+  //                -1.5215,  0.0000, -1.3271,  0.0000,  2.2324,  0.0000,
+  //                -3.1074,  0.0000,  1.2832
+  VCMP_U16(10, v1, 0x0, 0xbe37, 0x0, 0x3210, 0x0, 0x3b25, 0x0, 0xbe16, 0x0,
+           0xbd4f, 0x0, 0x4077, 0x0, 0xc236, 0x0, 0x3d22);
+
+  VSET(16, e32, m1);
+  //                0.74354362,  0.49774653,  0.25714639,  0.51635689,
+  //                0.74569613,  0.41876560,  0.21346331,  0.08743033,
+  //                -0.15111920, -0.93289024,  0.08753468, -0.33427054,
+  //                0.06167563, -0.54564798,  0.78990245, -0.77273035
+  VLOAD_32(v2, 0x3f3e58e0, 0x3efed8a2, 0x3e83a8b1, 0x3f042ff7, 0x3f3ee5f1,
+           0x3ed66872, 0x3e5a9620, 0x3db30eac, 0xbe1abefe, 0xbf6ed1e5,
+           0x3db34562, 0xbeab2582, 0x3d7c9f95, 0xbf0baf96, 0x3f4a370c,
+           0xbf45d1a8);
+  double dscalar_32;
+  //                              -0.45971388
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0xbeeb5f9e);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfdiv.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_32));
+  //                0.00000000, -1.08273113,  0.00000000, -1.12321365,
+  //                0.00000000, -0.91092664,  0.00000000, -0.19018422,
+  //                0.00000000,  2.02928448,  0.00000000,  0.72712737,
+  //                0.00000000,  1.18692958,  0.00000000,  1.68089414
+  VCMP_U32(11, v1, 0x0, 0xbf8a96ef, 0x0, 0xbf8fc576, 0x0, 0xbf69327c, 0x0,
+           0xbe42bfa7, 0x0, 0x4001dfcc, 0x0, 0x3f3a2504, 0x0, 0x3f97ed4e, 0x0,
+           0x3fd72789);
+
+  VSET(16, e64, m1);
+  //                -0.8580137874650531, -0.4775160339931992,
+  //                0.3831482495481682, -0.3582952848420831, 0.0009796501269754,
+  //                0.5485795361059773, -0.8055070333165963,
+  //                -0.2632019868496005, -0.0782680309690278,
+  //                -0.7119901734202212, -0.5084969452651125,
+  //                -0.7586325258910223,  0.6253847342253853,
+  //                0.5751160060426936,  0.0609762717873976, -0.7366654110036495
+  VLOAD_64(v2, 0xbfeb74d95495be72, 0xbfde8f9f69544024, 0x3fd885803c550ed0,
+           0xbfd6ee4f58ad4bcc, 0x3f500cf35070c000, 0x3fe18df6abda8f8e,
+           0xbfe9c6b6af995e52, 0xbfd0d84d2570b86c, 0xbfb4095fa9559400,
+           0xbfe6c89f9dbd3916, 0xbfe0459b62c0f228, 0xbfe846b7b80c4834,
+           0x3fe40326d89d4d44, 0x3fe26759aeab8116, 0x3faf38482a5158c0,
+           0xbfe792c3570b5cc2);
+  double dscalar_64;
+  //                                0.0072652319849018
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0x3f7dc225dc5e3c00);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfdiv.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_64));
+  //                0.0000000000000000, -65.7261922242188206,
+  //                0.0000000000000000, -49.3164272781202087,
+  //                0.0000000000000000,  75.5075044053657223,
+  //                0.0000000000000000, -36.2276094413188474,
+  //                0.0000000000000000, -97.9996474854262800,
+  //                0.0000000000000000, -104.4195873535172723,
+  //                0.0000000000000000,  79.1600333255520070,
+  //                0.0000000000000000, -101.3959929338175954
+  VCMP_U64(12, v1, 0x0, 0xc0506e79eef36846, 0x0, 0xc048a880b0658b57, 0x0,
+           0x4052e07af3c1e7c9, 0x0, 0xc0421d224e615cd6, 0x0, 0xc0587ffa39725bce,
+           0x0, 0xc05a1ada84ea4b00, 0x0, 0x4053ca3dfc6ae106, 0x0,
+           0xc0595957f2bf0c64);
+};
+
+int main(void) {
+  enable_vec();
+  enable_fp();
+  // Change RM to RTZ since there are issues with FDIV + RNE in fpnew
+  // Update: there are issues also with RTZ...
+  CHANGE_RM(RM_RTZ);
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vfirst.c b/apps/riscv-tests/isa/rv64uv/vfirst.c
new file mode 100644
index 0000000..c7657b4
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vfirst.c
@@ -0,0 +1,43 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1() {
+  VSET(4, e32, m1);
+  VLOAD_32(v2, 3);
+  VLOAD_32(v0, 2, 0, 0, 0);
+  volatile uint32_t scalar = 1337;
+  volatile uint32_t OUP[] = {0};
+  __asm__ volatile("vfirst.m %[A], v2, v0.t \n"
+                   "sw %[A], (%1) \n"
+                   :
+                   : [A] "r"(scalar), "r"(OUP));
+  XCMP(1, OUP[0], 1);
+}
+
+void TEST_CASE2() {
+  VSET(4, e32, m1);
+  VLOAD_32(v2, 1, 2, 3, 4);
+  VLOAD_32(v0, 0, 0, 0, 0);
+  volatile int32_t scalar = 1337;
+  volatile int32_t OUP[] = {0};
+  __asm__ volatile("vfirst.m %[A], v2, v0.t \n"
+                   "sw %[A], (%1) \n"
+                   :
+                   : [A] "r"(scalar), "r"(OUP));
+  XCMP(2, OUP[0], -1);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+  enable_fp();
+  TEST_CASE1();
+  TEST_CASE2();
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vfmacc.c b/apps/riscv-tests/isa/rv64uv/vfmacc.c
new file mode 100644
index 0000000..489359a
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vfmacc.c
@@ -0,0 +1,356 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+// Simple random test with similar values
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  //              -0.6353, -0.2290,  0.6870, -0.1031,  0.5410,  0.4211, -0.4939,
+  //              -0.8779, -0.3213, -0.6846,  0.9229,  0.0103, -0.5068,  0.8706,
+  //              0.6309, -0.3054
+  VLOAD_16(v2, 0xb915, 0xb354, 0x397f, 0xae9a, 0x3854, 0x36bd, 0xb7e7, 0xbb06,
+           0xb524, 0xb97a, 0x3b62, 0x2142, 0xb80e, 0x3af7, 0x390c, 0xb4e3);
+  //              -0.8042, -0.9463,  0.4431,  0.3757, -0.5259, -0.1290,  0.4697,
+  //              0.0952, -0.9995,  0.8823, -0.6128, -0.5010, -0.9976,  0.0081,
+  //              0.9746, -0.7734
+  VLOAD_16(v3, 0xba6f, 0xbb92, 0x3717, 0x3603, 0xb835, 0xb021, 0x3784, 0x2e17,
+           0xbbff, 0x3b0f, 0xb8e7, 0xb802, 0xbbfb, 0x2022, 0x3bcc, 0xba30);
+  //               0.6509,  0.3452,  0.9360,  0.3616, -0.4258, -0.0945, -0.7295,
+  //               -0.7734,  0.3411, -0.1519, -0.3557,  0.6060,  0.2598,
+  //               -0.0171, -0.8042, -0.4419
+  VLOAD_16(v1, 0x3935, 0x3586, 0x3b7d, 0x35c9, 0xb6d0, 0xae0d, 0xb9d6, 0xba30,
+           0x3575, 0xb0dc, 0xb5b1, 0x38d9, 0x3428, 0xa45e, 0xba6f, 0xb712);
+  asm volatile("vfmacc.vv v1, v2, v3");
+  //               1.1621,  0.5620,  1.2402,  0.3228, -0.7100, -0.1489, -0.9614,
+  //               -0.8569,  0.6621, -0.7559, -0.9209,  0.6006,  0.7651,
+  //               -0.0100, -0.1895, -0.2057
+  VCMP_U16(1, v1, 0x3ca6, 0x387f, 0x3cf6, 0x352a, 0xb9af, 0xb0c4, 0xbbb1,
+           0xbadb, 0x394c, 0xba0c, 0xbb5f, 0x38ce, 0x3a1f, 0xa123, 0xb20f,
+           0xb295);
+
+  VSET(16, e32, m1);
+  //               0.72754014,  0.34003398,  0.70107144, -0.41727209,
+  //               -0.52331781, -0.11821542, -0.16069038,  0.30835113,
+  //               -0.59407759, -0.53240144, -0.92390168,  0.33251825,
+  //               -0.45979658,  0.32465541, -0.99342769, -0.16221718
+  VLOAD_32(v2, 0x3f3a4012, 0x3eae18ef, 0x3f33796b, 0xbed5a4b0, 0xbf05f828,
+           0xbdf21aed, 0xbe248c05, 0x3e9de033, 0xbf181578, 0xbf084b76,
+           0xbf6c84d2, 0x3eaa3fd5, 0xbeeb6a75, 0x3ea6393c, 0xbf7e5147,
+           0xbe261c43);
+  //               0.95104939, -0.11575679,  0.13276713,  0.22784369,
+  //               0.93318671, -0.32301557,  0.41414812,  0.81797487,
+  //               -0.21847244, -0.00211347, -0.72070456, -0.58624452,
+  //               0.07381243, -0.16745377,  0.55389816, -0.23427610
+  VLOAD_32(v3, 0x3f7377f9, 0xbded11e6, 0x3e07f41b, 0x3e694fdb, 0x3f6ee553,
+           0xbea5624c, 0x3ed40b39, 0x3f5166cd, 0xbe5fb73d, 0xbb0a8224,
+           0xbf388018, 0xbf16141f, 0x3d972af9, 0xbe2b7900, 0x3f0dcc45,
+           0xbe6fe613);
+  //              -0.07459558, -0.00461283, -0.97654468,  0.94394064,
+  //              0.24971253,  0.97819000,  0.55116856, -0.97427863, 0.61764765,
+  //              0.86367106,  0.48787504, -0.26353455, -0.22228357, 0.40454853,
+  //              0.64000225, -0.51787829
+  VLOAD_32(v1, 0xbd98c591, 0xbb97273a, 0xbf79fed5, 0x3f71a618, 0x3e7fb4a4,
+           0x3f7a6aa9, 0x3f0d1962, 0xbf796a53, 0x3f1e1e28, 0x3f5d198c,
+           0x3ef9cac2, 0xbe86ee00, 0xbe639e4e, 0x3ecf20fc, 0x3f23d730,
+           0xbf0493ac);
+  asm volatile("vfmacc.vv v1, v2, v3");
+  //               0.61733103, -0.04397407, -0.88346541,  0.84886783,
+  //               -0.23864070,  1.01637542,  0.48461893, -0.72205520,
+  //               0.74743724,  0.86479628,  1.15373516, -0.45847154,
+  //               -0.25622228,  0.35018376,  0.08974451, -0.47987467
+  VCMP_U32(2, v1, 0x3f1e0968, 0xbd341e29, 0xbf622aca, 0x3f594f67, 0xbe745e3a,
+           0x3f821897, 0x3ef81ff9, 0xbf38d89b, 0x3f3f580c, 0x3f5d634a,
+           0x3f93ad98, 0xbeeabcc8, 0xbe832f91, 0x3eb34b49, 0x3db7cbf5,
+           0xbef5b222);
+
+  VSET(16, e64, m1);
+  //              -0.8992497708533775,  0.5795977429472710, -0.9421852470430045,
+  //              0.3407052467776674, -0.1137141395145149,  0.3284679540868891,
+  //              0.9781857174570949,  0.6033619236526551, -0.1287683269222892,
+  //              0.6555379481826638,  0.6785468173738887,  0.6923267883951645,
+  //              0.2185923779321672, -0.1310544396012536, -0.7596952716763763,
+  //              -0.4011231994121780,
+  VLOAD_64(v2, 0xbfecc6a774980626, 0x3fe28c1090d967fc, 0xbfee2661acda592c,
+           0x3fd5ce1d611f1590, 0xbfbd1c5eae4ec060, 0x3fd5059e742594fc,
+           0x3fef4d4c223c8f84, 0x3fe34ebdaa37ac76, 0xbfc07b7b047228c0,
+           0x3fe4fa2ab8176850, 0x3fe5b6a7d0ad9fa2, 0x3fe6278a8249a986,
+           0x3fcbfad5c52fcfd8, 0xbfc0c664520a9f78, 0xbfe84f6c7558d3f0,
+           0xbfd9ac00a3c919a8);
+  //               0.3028184794479449,  0.5016121947684244,  0.1900289524299839,
+  //               0.3294240614689632,  0.5945396967575391, -0.8758223026547887,
+  //               0.3719808177193829,  0.9159354723876536,  0.0805670751146079,
+  //               0.1775335284298603, -0.7021940272509897,  0.9279338928738479,
+  //               -0.7358371767028979,  0.2529700403354449,
+  //               -0.8333759771774525, -0.4016540133317048,
+  VLOAD_64(v3, 0x3fd36160c2769da4, 0x3fe00d350479c3ea, 0x3fc852de63fd6e08,
+           0x3fd51548a8a19488, 0x3fe306781d37ea9a, 0xbfec06bc7e604fb8,
+           0x3fd7ce88a1b60584, 0x3fed4f57e864d750, 0x3fb4a00b38c069f0,
+           0x3fc6b96b2d465dc0, 0xbfe6785f9bcfaa42, 0x3fedb1a26b57c7d6,
+           0xbfe78bfa6823d662, 0x3fd030a94086f244, 0xbfeaab0418e7f974,
+           0xbfd9b4b308e446c8);
+  //              -0.0664052564688480, -0.6742544994800144,  0.4321518669568931,
+  //              -0.1627512425330113,  0.0193121553139675, -0.3517684494272582,
+  //              -0.4834881433176264,  0.8328623424117183,  0.0264604353835154,
+  //              0.0322804237161178, -0.8345203693668675,  0.7175251091228996,
+  //              -0.7419013213335950, -0.2977694001417877,  0.4556506623709609,
+  //              -0.7832443836668095,
+  VLOAD_64(v1, 0xbfb0ffef54d0f220, 0xbfe5937e2c0e5202, 0x3fdba8604ddf0d80,
+           0xbfc4d508600804d8, 0x3f93c690cdf47e40, 0xbfd6835fd0838044,
+           0xbfdef17840e363cc, 0x3feaa6ceed574e1a, 0x3f9b1871c270c340,
+           0x3fa0870f4852d0c0, 0xbfeab4640fc8d962, 0x3fe6f5f737b7bbe2,
+           0xbfe7bda7d6ff9552, 0xbfd30ea762d6f1ec, 0x3fdd296165522d4c,
+           0xbfe910568693fcea);
+  asm volatile("vfmacc.vv v1, v2, v3");
+  //              -0.3387147047225807, -0.3835212035574087,  0.2531093914663254,
+  //              -0.0505147363757267, -0.0482954147100367, -0.6394480093239447,
+  //              -0.1196218202565150,  1.3855029309732363,  0.0160859479159849,
+  //              0.1486603886766570, -1.3109918917369803,  1.3599586010192732,
+  //              -0.9027497195599737, -0.3309222470138559,  1.0887624517613512,
+  //              -0.6221316407824544,
+  VCMP_U64(3, v1, 0xbfd5ad8070dd4c48, 0xbfd88b9c84a68118, 0x3fd032f1bbaa2211,
+           0xbfa9dd1149664d37, 0xbfa8ba2d3573e621, 0xbfe4765babf13c96,
+           0xbfbe9f891de3c4d6, 0x3ff62b051f10acd5, 0x3f9078d5b0e5b2ba,
+           0x3fc3074db9c9d78e, 0xbff4f9d2a2454dd5, 0x3ff5c263f334aac4,
+           0xbfece353613f76db, 0xbfd52dd4811c5fc3, 0x3ff16b922d36d831,
+           0xbfe3e8809d5ef572);
+};
+
+// Simple random test with similar values (masked, the numbers are taken from
+// TEST_CASE1)
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0xb915, 0xb354, 0x397f, 0xae9a, 0x3854, 0x36bd, 0xb7e7, 0xbb06,
+           0xb524, 0xb97a, 0x3b62, 0x2142, 0xb80e, 0x3af7, 0x390c, 0xb4e3);
+  VLOAD_16(v3, 0xba6f, 0xbb92, 0x3717, 0x3603, 0xb835, 0xb021, 0x3784, 0x2e17,
+           0xbbff, 0x3b0f, 0xb8e7, 0xb802, 0xbbfb, 0x2022, 0x3bcc, 0xba30);
+  VLOAD_16(v1, 0x3935, 0x3586, 0x3b7d, 0x35c9, 0xb6d0, 0xae0d, 0xb9d6, 0xba30,
+           0x3575, 0xb0dc, 0xb5b1, 0x38d9, 0x3428, 0xa45e, 0xba6f, 0xb712);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vfmacc.vv v1, v2, v3, v0.t");
+  VCMP_U16(4, v1, 0x3935, 0x387f, 0x3b7d, 0x352a, 0xb6d0, 0xb0c4, 0xb9d6,
+           0xbadb, 0x3575, 0xba0c, 0xb5b1, 0x38ce, 0x3428, 0xa123, 0xba6f,
+           0xb295);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x3f3a4012, 0x3eae18ef, 0x3f33796b, 0xbed5a4b0, 0xbf05f828,
+           0xbdf21aed, 0xbe248c05, 0x3e9de033, 0xbf181578, 0xbf084b76,
+           0xbf6c84d2, 0x3eaa3fd5, 0xbeeb6a75, 0x3ea6393c, 0xbf7e5147,
+           0xbe261c43);
+  VLOAD_32(v3, 0x3f7377f9, 0xbded11e6, 0x3e07f41b, 0x3e694fdb, 0x3f6ee553,
+           0xbea5624c, 0x3ed40b39, 0x3f5166cd, 0xbe5fb73d, 0xbb0a8224,
+           0xbf388018, 0xbf16141f, 0x3d972af9, 0xbe2b7900, 0x3f0dcc45,
+           0xbe6fe613);
+  VLOAD_32(v1, 0xbd98c591, 0xbb97273a, 0xbf79fed5, 0x3f71a618, 0x3e7fb4a4,
+           0x3f7a6aa9, 0x3f0d1962, 0xbf796a53, 0x3f1e1e28, 0x3f5d198c,
+           0x3ef9cac2, 0xbe86ee00, 0xbe639e4e, 0x3ecf20fc, 0x3f23d730,
+           0xbf0493ac);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vfmacc.vv v1, v2, v3, v0.t");
+  VCMP_U32(5, v1, 0xbd98c591, 0xbd341e29, 0xbf79fed5, 0x3f594f67, 0x3e7fb4a4,
+           0x3f821897, 0x3f0d1962, 0xbf38d89b, 0x3f1e1e28, 0x3f5d634a,
+           0x3ef9cac2, 0xbeeabcc8, 0xbe639e4e, 0x3eb34b49, 0x3f23d730,
+           0xbef5b222);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0xbfecc6a774980626, 0x3fe28c1090d967fc, 0xbfee2661acda592c,
+           0x3fd5ce1d611f1590, 0xbfbd1c5eae4ec060, 0x3fd5059e742594fc,
+           0x3fef4d4c223c8f84, 0x3fe34ebdaa37ac76, 0xbfc07b7b047228c0,
+           0x3fe4fa2ab8176850, 0x3fe5b6a7d0ad9fa2, 0x3fe6278a8249a986,
+           0x3fcbfad5c52fcfd8, 0xbfc0c664520a9f78, 0xbfe84f6c7558d3f0,
+           0xbfd9ac00a3c919a8);
+  VLOAD_64(v3, 0x3fd36160c2769da4, 0x3fe00d350479c3ea, 0x3fc852de63fd6e08,
+           0x3fd51548a8a19488, 0x3fe306781d37ea9a, 0xbfec06bc7e604fb8,
+           0x3fd7ce88a1b60584, 0x3fed4f57e864d750, 0x3fb4a00b38c069f0,
+           0x3fc6b96b2d465dc0, 0xbfe6785f9bcfaa42, 0x3fedb1a26b57c7d6,
+           0xbfe78bfa6823d662, 0x3fd030a94086f244, 0xbfeaab0418e7f974,
+           0xbfd9b4b308e446c8);
+  VLOAD_64(v1, 0xbfb0ffef54d0f220, 0xbfe5937e2c0e5202, 0x3fdba8604ddf0d80,
+           0xbfc4d508600804d8, 0x3f93c690cdf47e40, 0xbfd6835fd0838044,
+           0xbfdef17840e363cc, 0x3feaa6ceed574e1a, 0x3f9b1871c270c340,
+           0x3fa0870f4852d0c0, 0xbfeab4640fc8d962, 0x3fe6f5f737b7bbe2,
+           0xbfe7bda7d6ff9552, 0xbfd30ea762d6f1ec, 0x3fdd296165522d4c,
+           0xbfe910568693fcea);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vfmacc.vv v1, v2, v3, v0.t");
+  VCMP_U64(6, v1, 0xbfb0ffef54d0f220, 0xbfd88b9c84a68118, 0x3fdba8604ddf0d80,
+           0xbfa9dd1149664d37, 0x3f93c690cdf47e40, 0xbfe4765babf13c96,
+           0xbfdef17840e363cc, 0x3ff62b051f10acd5, 0x3f9b1871c270c340,
+           0x3fc3074db9c9d78e, 0xbfeab4640fc8d962, 0x3ff5c263f334aac4,
+           0xbfe7bda7d6ff9552, 0xbfd52dd4811c5fc3, 0x3fdd296165522d4c,
+           0xbfe3e8809d5ef572);
+};
+
+// Simple random test with similar values (with scalar)
+void TEST_CASE3(void) {
+  VSET(16, e16, m1);
+  //              0.7407, -0.1365,  0.0000, -0.8525, -0.0812,  0.9609, -0.3740,
+  //              0.2800,  0.9692,  0.4045,  0.0205, -0.5503,  0.6499,  0.4470,
+  //              -0.9360, -0.4426
+  VLOAD_16(v3, 0x39ed, 0xb05e, 0x0000, 0xbad2, 0xad33, 0x3bb0, 0xb5fc, 0x347b,
+           0x3bc1, 0x3679, 0x253e, 0xb867, 0x3933, 0x3727, 0xbb7d, 0xb715);
+  double dscalar_16;
+  //                             0.5757
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0x389b);
+  //             -0.1472, -0.8906,  0.2247,  0.6118, -0.0908, -0.6450, -0.5415,
+  //             0.0505, -0.4595,  0.1157, -0.3494,  0.6670, -0.9658, -0.2944,
+  //             -0.8096, -0.3364
+  VLOAD_16(v1, 0xb0b6, 0xbb20, 0x3331, 0x38e5, 0xadcf, 0xb929, 0xb855, 0x2a77,
+           0xb75a, 0x2f68, 0xb597, 0x3956, 0xbbba, 0xb4b6, 0xba7a, 0xb562);
+  asm volatile("vfmacc.vf v1, %[A], v3" ::[A] "f"(dscalar_16));
+  //              0.2793, -0.9692,  0.2247,  0.1210, -0.1375, -0.0918, -0.7568,
+  //              0.2118,  0.0986,  0.3486, -0.3376,  0.3501, -0.5918, -0.0371,
+  //              -1.3486, -0.5913
+  VCMP_U16(7, v1, 0x3478, 0xbbc1, 0x3331, 0x2fbf, 0xb067, 0xade0, 0xba0e,
+           0x32c6, 0x2e4e, 0x3594, 0xb567, 0x359a, 0xb8bc, 0xa8bf, 0xbd65,
+           0xb8bb);
+
+  VSET(16, e32, m1);
+  //              -0.79164708, -0.13258822, -0.94492996, -0.93729085,
+  //              0.80344391,  0.77393818,  0.31253836, -0.42539355,
+  //              -0.20085664, -0.63946086,  0.24876182, -0.45639724,
+  //              0.92842573,  0.39117134, -0.70563781,  0.13946204
+  VLOAD_32(v3, 0xbf4aa962, 0xbe07c535, 0xbf71e6ee, 0xbf6ff24b, 0x3f4dae80,
+           0x3f4620d0, 0x3ea00507, 0xbed9cd2f, 0xbe4dad5d, 0xbf23b3b5,
+           0x3e7ebb6b, 0xbee9ace6, 0x3f6dad4f, 0x3ec8479c, 0xbf34a4ae,
+           0x3e0ecf23);
+  double dscalar_32;
+  //                              0.97630060
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0x3f79eed6);
+  //              -0.43768027, -0.74227923,  0.60234988,  0.43624315,
+  //              0.34759882,  0.65410614,  0.99296939, -0.31534156,
+  //              -0.89647168,  0.47623411, -0.68185741,  0.77072626,
+  //              0.19827089, -0.16254151,  0.81625229, -0.24369264
+  VLOAD_32(v1, 0xbee017a1, 0xbf3e0603, 0x3f1a339a, 0x3edf5b43, 0x3eb1f879,
+           0x3f277380, 0x3f7e333e, 0xbea17473, 0xbf657f2b, 0x3ef3d4f5,
+           0xbf2e8e35, 0x3f454e51, 0x3e4b0786, 0xbe267148, 0x3f50f5e9,
+           0xbe798a90);
+  asm volatile("vfmacc.vf v1, %[A], v3" ::[A] "f"(dscalar_32));
+  //              -1.21056581, -0.87172520, -0.32018578,
+  //              -0.47883448,  1.13200164,  1.40970242,  1.29810071,
+  //              -0.73065352, -1.09256816, -0.14807191, -0.43899110,
+  //              0.32514536,  1.10469353,  0.21935931,  0.12733769, -0.10753576
+  VCMP_U32(8, v1, 0xbf9af3d2, 0xbf5f2962, 0xbea3ef65, 0xbef529cb, 0x3f90e56e,
+           0x3fb47121, 0x3fa6282b, 0xbf3b0c1c, 0xbf8bd946, 0xbe17a02a,
+           0xbee0c371, 0x3ea67974, 0x3f8d6699, 0x3e609fb9, 0x3e0264cf,
+           0xbddc3bb6);
+
+  VSET(16, e64, m1);
+  //              -0.1981785436218435,  0.2324321764718080,  0.3529425082887112,
+  //              -0.4889737836823891,  0.1335009259637479, -0.7964186221277452,
+  //              -0.2707335519445100,  0.8070543770008602, -0.1237072120160827,
+  //              -0.2357903062216291, -0.0812498320849093,  0.8656662449573254,
+  //              0.7178262144151533, -0.3106178959409680, -0.1410836751949509,
+  //              0.6904294937898030
+  VLOAD_64(v3, 0xbfc95dea1dcff710, 0x3fcdc0566a3e04a0, 0x3fd6969c2c9df760,
+           0xbfdf4b58b2611a74, 0x3fc1168eef800078, 0xbfe97c42e7fed97a,
+           0xbfd153b2d1e20588, 0x3fe9d363b369fec4, 0xbfbfab469de36f10,
+           0xbfce2e6072f7c5c0, 0xbfb4ccc9fb9c3490, 0x3febb389b26af886,
+           0x3fe6f86eae63fc74, 0xbfd3e129e2279a3c, 0xbfc20f07a57b1c48,
+           0x3fe617ff9800ac5a);
+  double dscalar_64;
+  //                               0.8738839355493300
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0x3febf6db7175e482);
+  //              -0.9433584234417285, -0.0696473591160720, -0.8171557896146857,
+  //              -0.9495656113293445, -0.6353537919969880,  0.8159507202507001,
+  //              0.0288919190409849, -0.6024741558584952, -0.9583084411212592,
+  //              0.7665070398551490, -0.7817863527411446, -0.2155326059803253,
+  //              -0.7807395886866346,  0.2528540140694266, -0.1740695080779533,
+  //              0.7247829241803623
+  VLOAD_64(v1, 0xbfee2ffe0122d3b6, 0xbfb1d468c9a80310, 0xbfea2623e6043a6c,
+           0xbfee62d76bc21ae2, 0xbfe454d179c08866, 0x3fea1c44af53fb1a,
+           0x3f9d95d7dd994d80, 0xbfe34777e1831e42, 0xbfeeaa7676c316f0,
+           0x3fe88739c58a9cbe, 0xbfe90464d02f6f4c, 0xbfcb96928af41d88,
+           0xbfe8fbd197034034, 0x3fd02ec29a45caf0, 0xbfc647e8de367aa0,
+           0x3fe7316bf581b994);
+  asm volatile("vfmacc.vf v1, %[A], v3" ::[A] "f"(dscalar_64));
+  //              -1.1165434690834197,  0.1334713860074080, -0.5087250014486948,
+  //              -1.3768719457941574, -0.5186894774163083,  0.1199732804009315,
+  //              -0.2076977828175325,  0.1027976993173292, -1.0664141864137089,
+  //              0.5604536790898100, -0.8527892757662274,  0.5409592190351925,
+  //              -0.1534427913930433, -0.0185899752875187, -0.2973602653990804,
+  //              1.3281381674327271
+  VCMP_U64(9, v1, 0xbff1dd5caf44692a, 0x3fc1159722ed4311, 0xbfe04779a77c2679,
+           0xbff607aae09f73e1, 0xbfe0991aacc90937, 0x3fbeb691a3b74133,
+           0xbfca95d7485395ec, 0x3fba50f334ac0644, 0xbff11008526a327e,
+           0x3fe1ef3c8dd3a2b9, 0xbfeb4a0cbc397482, 0x3fe14f89b5473a2f,
+           0xbfc3a4036d6b8775, 0xbf9309401f92c802, 0xbfd307f359c13629,
+           0x3ff5400dce9b1643);
+};
+
+// Simple random test with similar values (masked with scalar, values taken from
+// TEST_CASE3)
+void TEST_CASE4(void) {
+  VSET(16, e16, m1);
+  VLOAD_16(v3, 0x39ed, 0xb05e, 0x0000, 0xbad2, 0xad33, 0x3bb0, 0xb5fc, 0x347b,
+           0x3bc1, 0x3679, 0x253e, 0xb867, 0x3933, 0x3727, 0xbb7d, 0xb715);
+  double dscalar_16;
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0x389b);
+  VLOAD_16(v1, 0xb0b6, 0xbb20, 0x3331, 0x38e5, 0xadcf, 0xb929, 0xb855, 0x2a77,
+           0xb75a, 0x2f68, 0xb597, 0x3956, 0xbbba, 0xb4b6, 0xba7a, 0xb562);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vfmacc.vf v1, %[A], v3, v0.t" ::[A] "f"(dscalar_16));
+  VCMP_U16(10, v1, 0xb0b6, 0xbbc1, 0x3331, 0x2fbf, 0xadcf, 0xade0, 0xb855,
+           0x32c6, 0xb75a, 0x3594, 0xb597, 0x359a, 0xbbba, 0xa8bf, 0xba7a,
+           0xb8bb);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v3, 0xbf4aa962, 0xbe07c535, 0xbf71e6ee, 0xbf6ff24b, 0x3f4dae80,
+           0x3f4620d0, 0x3ea00507, 0xbed9cd2f, 0xbe4dad5d, 0xbf23b3b5,
+           0x3e7ebb6b, 0xbee9ace6, 0x3f6dad4f, 0x3ec8479c, 0xbf34a4ae,
+           0x3e0ecf23);
+  double dscalar_32;
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0x3f79eed6);
+  VLOAD_32(v1, 0xbee017a1, 0xbf3e0603, 0x3f1a339a, 0x3edf5b43, 0x3eb1f879,
+           0x3f277380, 0x3f7e333e, 0xbea17473, 0xbf657f2b, 0x3ef3d4f5,
+           0xbf2e8e35, 0x3f454e51, 0x3e4b0786, 0xbe267148, 0x3f50f5e9,
+           0xbe798a90);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vfmacc.vf v1, %[A], v3, v0.t" ::[A] "f"(dscalar_32));
+  VCMP_U32(11, v1, 0xbee017a1, 0xbf5f2962, 0x3f1a339a, 0xbef529cb, 0x3eb1f879,
+           0x3fb47121, 0x3f7e333e, 0xbf3b0c1c, 0xbf657f2b, 0xbe17a02a,
+           0xbf2e8e35, 0x3ea67974, 0x3e4b0786, 0x3e609fb9, 0x3f50f5e9,
+           0xbddc3bb6);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v3, 0xbfc95dea1dcff710, 0x3fcdc0566a3e04a0, 0x3fd6969c2c9df760,
+           0xbfdf4b58b2611a74, 0x3fc1168eef800078, 0xbfe97c42e7fed97a,
+           0xbfd153b2d1e20588, 0x3fe9d363b369fec4, 0xbfbfab469de36f10,
+           0xbfce2e6072f7c5c0, 0xbfb4ccc9fb9c3490, 0x3febb389b26af886,
+           0x3fe6f86eae63fc74, 0xbfd3e129e2279a3c, 0xbfc20f07a57b1c48,
+           0x3fe617ff9800ac5a);
+  double dscalar_64;
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0x3febf6db7175e482);
+  VLOAD_64(v1, 0xbfee2ffe0122d3b6, 0xbfb1d468c9a80310, 0xbfea2623e6043a6c,
+           0xbfee62d76bc21ae2, 0xbfe454d179c08866, 0x3fea1c44af53fb1a,
+           0x3f9d95d7dd994d80, 0xbfe34777e1831e42, 0xbfeeaa7676c316f0,
+           0x3fe88739c58a9cbe, 0xbfe90464d02f6f4c, 0xbfcb96928af41d88,
+           0xbfe8fbd197034034, 0x3fd02ec29a45caf0, 0xbfc647e8de367aa0,
+           0x3fe7316bf581b994);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vfmacc.vf v1, %[A], v3, v0.t" ::[A] "f"(dscalar_64));
+  VCMP_U64(12, v1, 0xbfee2ffe0122d3b6, 0x3fc1159722ed4311, 0xbfea2623e6043a6c,
+           0xbff607aae09f73e1, 0xbfe454d179c08866, 0x3fbeb691a3b74133,
+           0x3f9d95d7dd994d80, 0x3fba50f334ac0644, 0xbfeeaa7676c316f0,
+           0x3fe1ef3c8dd3a2b9, 0xbfe90464d02f6f4c, 0x3fe14f89b5473a2f,
+           0xbfe8fbd197034034, 0xbf9309401f92c802, 0xbfc647e8de367aa0,
+           0x3ff5400dce9b1643);
+};
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+  enable_fp();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vfmadd.c b/apps/riscv-tests/isa/rv64uv/vfmadd.c
new file mode 100644
index 0000000..cd61bfd
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vfmadd.c
@@ -0,0 +1,433 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+// Simple random test with similar values + 1 subnormal
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  //               0.3501, -0.3289, -0.8853, -0.4082, -0.4346, -0.2659,  0.9316,
+  //               0.5444, -0.0538,  0.7686,  0.8203, -0.8623,  0.3059,  0.0372,
+  //               0.5337, -0.5815
+  VLOAD_16(v2, 0x359a, 0xb543, 0xbb15, 0xb688, 0xb6f4, 0xb441, 0x3b74, 0x385b,
+           0xaae4, 0x3a26, 0x3a90, 0xbae6, 0x34e5, 0x28c4, 0x3845, 0xb8a7);
+  //              -0.8105,  0.5000, -0.8374, -0.8394,  0.3098,  0.1328, -0.2864,
+  //              -0.4041, -0.1729,  0.0196,  0.2739,  0.8071, -0.1553,  0.2815,
+  //              -0.9067, -0.2495
+  VLOAD_16(v3, 0xba7c, 0x3800, 0xbab3, 0xbab7, 0x34f5, 0x3040, 0xb495, 0xb677,
+           0xb188, 0x2502, 0x3462, 0x3a75, 0xb0f8, 0x3481, 0xbb41, 0xb3fc);
+  //              -0.6558, -0.1006,  0.4558, -0.0784,  0.1539,  0.6748,  0.3347,
+  //              -0.3416,  0.0614,  0.2289, -0.0829,  0.3838, -0.6348,  0.0843,
+  //              -0.6890, -0.2598
+  VLOAD_16(v1, 0xb93f, 0xae71, 0x374b, 0xad05, 0x30ed, 0x3966, 0x355b, 0xb577,
+           0x2bdc, 0x3353, 0xad4f, 0x3624, 0xb914, 0x2d65, 0xb983, 0xb428);
+  asm volatile("vfmadd.vv v1, v2, v3");
+  //              -1.0400,  0.5332, -1.2412, -0.8071,  0.2429, -0.0466,  0.0254,
+  //              -0.5898, -0.1761,  0.1954,  0.2058,  0.4761, -0.3496,  0.2847,
+  //              -1.2744, -0.0984
+  VCMP_U16(1, v1, 0xbc29, 0x3844, 0xbcf7, 0xba75, 0x33c6, 0xa9f7, 0x2684,
+           0xb8b8, 0xb1a3, 0x3241, 0x3297, 0x379e, 0xb597, 0x348e, 0xbd19,
+           0xae4d);
+
+  VSET(16, e32, m1);
+  //              -0.20637949, -0.63321692,  0.40850523,  0.58702314,
+  //              -0.25534528, -0.22053087,  0.96057665,  0.85530519,
+  //              0.74252450, -0.87175107, -0.00987994, -0.52556008, 0.26113954,
+  //              -0.71307814,  0.78942811,  0.48685852
+  VLOAD_32(v2, 0xbe535525, 0xbf221a81, 0x3ed12799, 0x3f164726, 0xbe82bc9e,
+           0xbe61d2d8, 0x3f75e85a, 0x3f5af548, 0x3f3e1616, 0xbf5f2b14,
+           0xbc21df78, 0xbf068b1b, 0x3e85b415, 0xbf368c4a, 0x3f4a17f6,
+           0x3ef94585);
+  //              -0.15712014,  0.83088422,  0.57509524,  0.85365236,
+  //              -0.96695948,  0.71368766,  0.23281342, -0.67807233,
+  //              0.79363507,  0.62817359,  0.37205252,  0.27726358,
+  //              -0.85021532, -0.16634122, -0.58148408,  0.06963744
+  VLOAD_32(v3, 0xbe20e41a, 0x3f54b4d4, 0x3f133971, 0x3f5a88f6, 0xbf778aa8,
+           0x3f36b43c, 0x3e6e66a4, 0xbf2d9626, 0x3f4b2bab, 0x3f20cffc,
+           0x3ebe7dab, 0x3e8df57e, 0xbf59a7b6, 0xbe2a555a, 0xbf14dc24,
+           0x3d8e9e13);
+  //              -0.63061494,  0.57643133,  0.08198822, -0.06029604,
+  //              -0.84276563,  0.00681775,  0.30881208,  0.27571887,
+  //              0.12349209,  0.29805747, -0.55497122, -0.52685922, 0.82809180,
+  //              -0.83231467,  0.20959182,  0.15603130
+  VLOAD_32(v1, 0xbf216ffb, 0x3f139101, 0x3da7e970, 0xbd76f8fa, 0xbf57bf7d,
+           0x3bdf676d, 0x3e9e1c9e, 0x3e8d2b06, 0x3dfce96c, 0x3e989afd,
+           0xbf0e1298, 0xbf06e03f, 0x3f53fdd3, 0xbf551293, 0x3e569f3d,
+           0x3e1fc6ab);
+  asm volatile("vfmadd.vv v1, v2, v3");
+  //              -0.02697416,  0.46587816,  0.60858786,  0.81825721,
+  //              -0.75176322,  0.71218413,  0.52945113, -0.44224855,
+  //              0.88533098,  0.36834168,  0.37753561,  0.55415976,
+  //              -0.63396782,  0.42716417, -0.41602641,  0.14560261
+  VCMP_U32(2, v1, 0xbcdcf8e5, 0x3eee8795, 0x3f1bcc6a, 0x3f51794e, 0xbf40738e,
+           0x3f3651b3, 0x3f078a1b, 0xbee26e67, 0x3f62a50d, 0x3ebc9748,
+           0x3ec14c59, 0x3f0ddd6a, 0xbf224bb7, 0x3edab544, 0xbed5016a,
+           0x3e1518d9);
+
+  VSET(16, e64, m1);
+  //               0.0308264568094008,  0.5865382185158325,  0.4543411851187289,
+  //               0.0036656924511687, -0.3103508259554966,  0.9658177901158624,
+  //               -0.3381631341283657, -0.2003719333831677, 0.8989532087589025,
+  //               -0.8054516243685412,  0.8701363884969631,
+  //               -0.3585976675814562,  0.4150155349314333,
+  //               -0.6908185611649824,  0.8412555125501906, -0.3357469205066645
+  VLOAD_64(v2, 0x3f9f90f87f644880, 0x3fe2c4ebcc4c25b4, 0x3fdd13ed0cd3e484,
+           0x3f6e0783a63d2400, 0xbfd3dcc9b5f0fd10, 0x3feee7fab5ce29f4,
+           0xbfd5a476fc72d40c, 0xbfc9a5c99a756020, 0x3fecc43985081eb2,
+           0xbfe9c6427c2588e6, 0x3febd8284474eda0, 0xbfd6f343a1abca7c,
+           0x3fda8f9d51773268, 0xbfe61b2f86f58c4a, 0x3feaeb90ae3f72fc,
+           0xbfd57ce0a6d3c3f8);
+  //               0.5881481456806663, -0.9882550591195853, -0.8483939717953815,
+  //               -0.9684864200393222, -0.6743741213041285, 0.4372709704288931,
+  //               -0.8339944484196176, -0.1519222509233684,
+  //               -0.2540075520951832,  0.6661048539265222, 0.3013290199421905,
+  //               -0.0367795249610035, -0.7178804756969177, 0.1577316726139908,
+  //               -0.1242681642824526, -0.9006297759672148
+  VLOAD_64(v3, 0x3fe2d21c0f5cd922, 0xbfef9fc912e0ce28, 0xbfeb260b1d5f82be,
+           0xbfeefdd73b960c5a, 0xbfe594790988a396, 0x3fdbfc3f615edda8,
+           0xbfeab01520204008, 0xbfc3723035a012c8, 0xbfd041a8e44be49c,
+           0x3fe550bb206a47d8, 0x3fd348f9837f3238, 0xbfa2d4c411bd66e0,
+           0xbfe6f8e079b1c412, 0x3fc4308d2bb5d1f0, 0xbfbfd009d586ef50,
+           0xbfecd1f58932a7e4);
+  //              -0.8344616273245185,  0.7077884806720691, -0.1882041492960900,
+  //              -0.2751607560371576,  0.2338395078923734, -0.9938305657796487,
+  //              -0.5345602642671559,  0.0887204597208056,  0.3045224871958914,
+  //              -0.3946645040604191,  0.6818539464440989,  0.9719861381061521,
+  //              -0.8471643748461517,  0.8077493118513845,  0.2789872574353331,
+  //              0.7073875082318823
+  VLOAD_64(v1, 0xbfeab3e8dee4061e, 0x3fe6a634071f1b28, 0xbfc81712d5195ee0,
+           0xbfd19c3bdc149f5c, 0x3fcdee73f7748a88, 0xbfefcd75c2393d96,
+           0xbfe11b1e209897fa, 0x3fb6b66250fca870, 0x3fd37d4be2d9c9a4,
+           0xbfd9422ee8753844, 0x3fe5d1bf5e1407b4, 0x3fef1a82ac6a99b4,
+           0xbfeb1bf876899dc0, 0x3fe9d91515b8951c, 0x3fd1daed5eabdf0c,
+           0x3fe6a2eb20ae8e42);
+  asm volatile("vfmadd.vv v1, v2, v3");
+  //               0.5624246503668447, -0.5731100645801621, -0.9339028680308291,
+  //               -0.9694950747455855, -0.7469464057195535,
+  //               -0.5225882703620045, -0.6532258740745487,
+  //               -0.1696993409682697,  0.0197439149088051, 0.9839880198025914,
+  //               0.8946349503834604, -0.3853314870073767, -1.0694668518985466,
+  //               -0.4002765447811873,  0.1104314039662806, -1.1381329534609521
+  VCMP_U64(3, v1, 0x3fe1ff61faf9464f, 0xbfe256eaeb0c2af6, 0xbfede288447aa80f,
+           0xbfef061a88f54aac, 0xbfe7e6fc260dc471, 0xbfe0b90b094f4be7,
+           0xbfe4e739f2c1a370, 0xbfc5b8b53fce44b1, 0x3f9437bfb3503463,
+           0x3fef7cd47196a75e, 0x3feca0d979b82d6d, 0xbfd8a94565b434f4,
+           0xbff11c894610f720, 0xbfd99e21834c3aa4, 0x3fbc453b847c8ddf,
+           0xbff235cae659d5ba);
+};
+
+// Simple random test with similar values + 1 subnormal (masked)
+// The numbers are the same of TEST_CASE1
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  //               0.3501, -0.3289, -0.8853, -0.4082, -0.4346, -0.2659,  0.9316,
+  //               0.5444, -0.0538,  0.7686,  0.8203, -0.8623,  0.3059,  0.0372,
+  //               0.5337, -0.5815
+  VLOAD_16(v2, 0x359a, 0xb543, 0xbb15, 0xb688, 0xb6f4, 0xb441, 0x3b74, 0x385b,
+           0xaae4, 0x3a26, 0x3a90, 0xbae6, 0x34e5, 0x28c4, 0x3845, 0xb8a7);
+  //              -0.8105,  0.5000, -0.8374, -0.8394,  0.3098,  0.1328, -0.2864,
+  //              -0.4041, -0.1729,  0.0196,  0.2739,  0.8071, -0.1553,  0.2815,
+  //              -0.9067, -0.2495
+  VLOAD_16(v3, 0xba7c, 0x3800, 0xbab3, 0xbab7, 0x34f5, 0x3040, 0xb495, 0xb677,
+           0xb188, 0x2502, 0x3462, 0x3a75, 0xb0f8, 0x3481, 0xbb41, 0xb3fc);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //              -0.6558, -0.1006,  0.4558, -0.0784,  0.1539,  0.6748,  0.3347,
+  //              -0.3416,  0.0614,  0.2289, -0.0829,  0.3838, -0.6348,  0.0843,
+  //              -0.6890, -0.2598
+  VLOAD_16(v1, 0xb93f, 0xae71, 0x374b, 0xad05, 0x30ed, 0x3966, 0x355b, 0xb577,
+           0x2bdc, 0x3353, 0xad4f, 0x3624, 0xb914, 0x2d65, 0xb983, 0xb428);
+  asm volatile("vfmadd.vv v1, v2, v3, v0.t");
+  VCMP_U16(4, v1, 0xb93f, 0x3844, 0x374b, 0xba75, 0x30ed, 0xa9f7, 0x355b,
+           0xb8b8, 0x2bdc, 0x3241, 0xad4f, 0x379e, 0xb914, 0x348e, 0xb983,
+           0xae4d);
+
+  VSET(16, e32, m1);
+  //              -0.20637949, -0.63321692,  0.40850523,  0.58702314,
+  //              -0.25534528, -0.22053087,  0.96057665,  0.85530519,
+  //              0.74252450, -0.87175107, -0.00987994, -0.52556008, 0.26113954,
+  //              -0.71307814,  0.78942811,  0.48685852
+  VLOAD_32(v2, 0xbe535525, 0xbf221a81, 0x3ed12799, 0x3f164726, 0xbe82bc9e,
+           0xbe61d2d8, 0x3f75e85a, 0x3f5af548, 0x3f3e1616, 0xbf5f2b14,
+           0xbc21df78, 0xbf068b1b, 0x3e85b415, 0xbf368c4a, 0x3f4a17f6,
+           0x3ef94585);
+  //              -0.15712014,  0.83088422,  0.57509524,  0.85365236,
+  //              -0.96695948,  0.71368766,  0.23281342, -0.67807233,
+  //              0.79363507,  0.62817359,  0.37205252,  0.27726358,
+  //              -0.85021532, -0.16634122, -0.58148408,  0.06963744
+  VLOAD_32(v3, 0xbe20e41a, 0x3f54b4d4, 0x3f133971, 0x3f5a88f6, 0xbf778aa8,
+           0x3f36b43c, 0x3e6e66a4, 0xbf2d9626, 0x3f4b2bab, 0x3f20cffc,
+           0x3ebe7dab, 0x3e8df57e, 0xbf59a7b6, 0xbe2a555a, 0xbf14dc24,
+           0x3d8e9e13);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //              -0.63061494,  0.57643133,  0.08198822, -0.06029604,
+  //              -0.84276563,  0.00681775,  0.30881208,  0.27571887,
+  //              0.12349209,  0.29805747, -0.55497122, -0.52685922, 0.82809180,
+  //              -0.83231467,  0.20959182,  0.15603130
+  VLOAD_32(v1, 0xbf216ffb, 0x3f139101, 0x3da7e970, 0xbd76f8fa, 0xbf57bf7d,
+           0x3bdf676d, 0x3e9e1c9e, 0x3e8d2b06, 0x3dfce96c, 0x3e989afd,
+           0xbf0e1298, 0xbf06e03f, 0x3f53fdd3, 0xbf551293, 0x3e569f3d,
+           0x3e1fc6ab);
+  asm volatile("vfmadd.vv v1, v2, v3, v0.t");
+  VCMP_U32(5, v1, 0xbf216ffb, 0x3eee8795, 0x3da7e970, 0x3f51794e, 0xbf57bf7d,
+           0x3f3651b3, 0x3e9e1c9e, 0xbee26e67, 0x3dfce96c, 0x3ebc9748,
+           0xbf0e1298, 0x3f0ddd6a, 0x3f53fdd3, 0x3edab544, 0x3e569f3d,
+           0x3e1518d9);
+
+  VSET(16, e64, m1);
+  //               0.0308264568094008,  0.5865382185158325,  0.4543411851187289,
+  //               0.0036656924511687, -0.3103508259554966,  0.9658177901158624,
+  //               -0.3381631341283657, -0.2003719333831677, 0.8989532087589025,
+  //               -0.8054516243685412,  0.8701363884969631,
+  //               -0.3585976675814562,  0.4150155349314333,
+  //               -0.6908185611649824,  0.8412555125501906, -0.3357469205066645
+  VLOAD_64(v2, 0x3f9f90f87f644880, 0x3fe2c4ebcc4c25b4, 0x3fdd13ed0cd3e484,
+           0x3f6e0783a63d2400, 0xbfd3dcc9b5f0fd10, 0x3feee7fab5ce29f4,
+           0xbfd5a476fc72d40c, 0xbfc9a5c99a756020, 0x3fecc43985081eb2,
+           0xbfe9c6427c2588e6, 0x3febd8284474eda0, 0xbfd6f343a1abca7c,
+           0x3fda8f9d51773268, 0xbfe61b2f86f58c4a, 0x3feaeb90ae3f72fc,
+           0xbfd57ce0a6d3c3f8);
+  //               0.5881481456806663, -0.9882550591195853, -0.8483939717953815,
+  //               -0.9684864200393222, -0.6743741213041285, 0.4372709704288931,
+  //               -0.8339944484196176, -0.1519222509233684,
+  //               -0.2540075520951832,  0.6661048539265222, 0.3013290199421905,
+  //               -0.0367795249610035, -0.7178804756969177, 0.1577316726139908,
+  //               -0.1242681642824526, -0.9006297759672148
+  VLOAD_64(v3, 0x3fe2d21c0f5cd922, 0xbfef9fc912e0ce28, 0xbfeb260b1d5f82be,
+           0xbfeefdd73b960c5a, 0xbfe594790988a396, 0x3fdbfc3f615edda8,
+           0xbfeab01520204008, 0xbfc3723035a012c8, 0xbfd041a8e44be49c,
+           0x3fe550bb206a47d8, 0x3fd348f9837f3238, 0xbfa2d4c411bd66e0,
+           0xbfe6f8e079b1c412, 0x3fc4308d2bb5d1f0, 0xbfbfd009d586ef50,
+           0xbfecd1f58932a7e4);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //              -0.8344616273245185,  0.7077884806720691, -0.1882041492960900,
+  //              -0.2751607560371576,  0.2338395078923734, -0.9938305657796487,
+  //              -0.5345602642671559,  0.0887204597208056,  0.3045224871958914,
+  //              -0.3946645040604191,  0.6818539464440989,  0.9719861381061521,
+  //              -0.8471643748461517,  0.8077493118513845,  0.2789872574353331,
+  //              0.7073875082318823
+  VLOAD_64(v1, 0xbfeab3e8dee4061e, 0x3fe6a634071f1b28, 0xbfc81712d5195ee0,
+           0xbfd19c3bdc149f5c, 0x3fcdee73f7748a88, 0xbfefcd75c2393d96,
+           0xbfe11b1e209897fa, 0x3fb6b66250fca870, 0x3fd37d4be2d9c9a4,
+           0xbfd9422ee8753844, 0x3fe5d1bf5e1407b4, 0x3fef1a82ac6a99b4,
+           0xbfeb1bf876899dc0, 0x3fe9d91515b8951c, 0x3fd1daed5eabdf0c,
+           0x3fe6a2eb20ae8e42);
+  asm volatile("vfmadd.vv v1, v2, v3, v0.t");
+  //               0.0000000000000000, -0.5731100645801621,  0.0000000000000000,
+  //               -0.9694950747455855,  0.0000000000000000,
+  //               -0.5225882703620045,  0.0000000000000000,
+  //               -0.1696993409682697,  0.0000000000000000, 0.9839880198025914,
+  //               0.0000000000000000, -0.3853314870073767,  0.0000000000000000,
+  //               -0.4002765447811873,  0.0000000000000000, -1.1381329534609521
+  VCMP_U64(6, v1, 0xbfeab3e8dee4061e, 0xbfe256eaeb0c2af6, 0xbfc81712d5195ee0,
+           0xbfef061a88f54aac, 0x3fcdee73f7748a88, 0xbfe0b90b094f4be7,
+           0xbfe11b1e209897fa, 0xbfc5b8b53fce44b1, 0x3fd37d4be2d9c9a4,
+           0x3fef7cd47196a75e, 0x3fe5d1bf5e1407b4, 0xbfd8a94565b434f4,
+           0xbfeb1bf876899dc0, 0xbfd99e21834c3aa4, 0x3fd1daed5eabdf0c,
+           0xbff235cae659d5ba);
+};
+
+// Simple random test with similar values (vector-scalar)
+void TEST_CASE3(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //                              0.6299
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0x390a);
+  //              -0.5352,  0.1115,  0.9541, -0.8857, -0.4143,  0.4045,  0.2949,
+  //              -0.5479,  0.6733,  0.8965,  0.8882,  0.6294,  0.7568,  0.8735,
+  //              -0.8569,  0.8271
+  VLOAD_16(v2, 0xb848, 0x2f23, 0x3ba2, 0xbb16, 0xb6a1, 0x3679, 0x34b8, 0xb862,
+           0x3963, 0x3b2c, 0x3b1b, 0x3909, 0x3a0e, 0x3afd, 0xbadb, 0x3a9e);
+  //               0.2844,  0.1008,  0.3777,  0.9790, -0.8613,  0.4951,  0.4126,
+  //               0.5518, -0.6680, -0.8340,  0.2094,  0.5884, -0.6509, -0.9360,
+  //               -0.1609, -0.2527
+  VLOAD_16(v1, 0x348d, 0x2e74, 0x360b, 0x3bd5, 0xbae4, 0x37ec, 0x369a, 0x386a,
+           0xb958, 0xbaac, 0x32b3, 0x38b5, 0xb935, 0xbb7d, 0xb126, 0xb40b);
+  asm volatile("vfmadd.vf v1, %[A], v2" ::[A] "f"(dscalar_16));
+  //              -0.3560,  0.1750,  1.1924, -0.2690, -0.9570,  0.7163,  0.5547,
+  //              -0.2002,  0.2527,  0.3711,  1.0195,  1.0000,  0.3469,  0.2842,
+  //              -0.9580,  0.6680
+  VCMP_U16(7, v1, 0xb5b2, 0x319a, 0x3cc5, 0xb44e, 0xbba8, 0x39bb, 0x3870,
+           0xb269, 0x340b, 0x35f0, 0x3c15, 0x3c00, 0x358d, 0x348b, 0xbbab,
+           0x3958);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                               0.80368215
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0x3f4dbe1d);
+  //               0.13072050, -0.19741143,  0.09370349,  0.41049519,
+  //               -0.69910282, -0.90573430,  0.86481184,  0.33341369,
+  //               0.30657578, -0.90526944, -0.97891974, -0.50830764,
+  //               0.79750061,  0.96885878,  0.48752418,  0.64305341
+  VLOAD_32(v2, 0x3e05db98, 0xbe4a2639, 0x3dbfe79e, 0x3ed22c6d, 0xbf32f867,
+           0xbf67de34, 0x3f5d644f, 0x3eaab533, 0x3e9cf780, 0xbf67bfbd,
+           0xbf7a9a7c, 0xbf022073, 0x3f4c2900, 0x3f780721, 0x3ef99cc5,
+           0x3f249f26);
+  //              -0.61117887,  0.81778014, -0.46267223, -0.30897874,
+  //              -0.84296966,  0.50125730,  0.96147668,  0.65802389,
+  //              0.19629262, -0.73197508, -0.06948850, -0.60436314,
+  //              -0.80817568,  0.72047287, -0.78180677, -0.40237895
+  VLOAD_32(v1, 0xbf1c7638, 0x3f515a0a, 0xbeece360, 0xbe9e3276, 0xbf57ccdc,
+           0x3f005266, 0x3f762356, 0x3f287441, 0x3e4900ef, 0xbf3b62b8,
+           0xbd8e4ffc, 0xbf1ab78b, 0xbf4ee49a, 0x3f3870e9, 0xbf48247d,
+           0xbece049d);
+  asm volatile("vfmadd.vf v1, %[A], v2" ::[A] "f"(dscalar_32));
+  //              -0.36047307,  0.45982391, -0.27813792,  0.16217449,
+  //              -1.37658250, -0.50288272,  1.63753343,  0.86225569,
+  //              0.46433264, -1.49354482, -1.03476644, -0.99402350, 0.14798427,
+  //              1.54788995, -0.14079997,  0.31966865
+  VCMP_U32(8, v1, 0xbeb88fed, 0x3eeb6e09, 0xbe8e6818, 0x3e261112, 0xbfb033db,
+           0xbf00bced, 0x3fd19ab2, 0x3f5cbccb, 0x3eedbd02, 0xbfbf2c79,
+           0xbf84733a, 0xbf7e7853, 0x3e17892e, 0x3fc62142, 0xbe102ddd,
+           0x3ea3ab9c);
+
+  VSET(16, e64, m1);
+  double dscalar_64;
+  //                                0.5717861827636179
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0x3fe24c128968c808);
+  //               -0.0978999279373105, -0.8066508697961206, 0.1001298330116740,
+  //               0.6183499729699258, -0.7091158569428311,  0.4713309006442494,
+  //               -0.9363173157138223,  0.6720957973877764,
+  //               -0.1684678230133414, -0.0206783343753454,
+  //               -0.6941474840922310,  0.4809970389518419,
+  //               -0.4671263490725479,  0.5176516826232249,
+  //               -0.9714116214357187,  0.0212574845134876
+  VLOAD_64(v2, 0xbfb90ff83cc58160, 0xbfe9d0157c220eae, 0x3fb9a21bd6239ad0,
+           0x3fe3c985e1ec6d14, 0xbfe6b113bcd49f88, 0x3fde2a4914f71f28,
+           0xbfedf64fbb356b82, 0x3fe581cf0bb1e7c4, 0xbfc5905a8722a398,
+           0xbf952cb38782ee00, 0xbfe63674c8d8dba6, 0x3fdec8a7cdf1580c,
+           0xbfdde565ea17744c, 0x3fe0909a42f2c184, 0xbfef15cdd320a9f0,
+           0x3f95c485a31f6440);
+  //               -0.8599787754583945, -0.8609648323347547,
+  //               -0.5642848553711928,  0.8958493001041692, 0.3661374487395561,
+  //               0.1017901385891375,  0.2298954297904690, -0.4970717320718749,
+  //               -0.5860844501192310, -0.6581386742527398,
+  //               -0.8379133193505066, -0.6497652150347000,
+  //               -0.4444119628309799, -0.8810041425660891, 0.4421772814931029,
+  //               0.0606105644967410
+  VLOAD_64(v1, 0xbfeb84f2357b2242, 0xbfeb8d061ebc48de, 0xbfe20e9f1cee50cc,
+           0x3fecaacc26c2f0d0, 0x3fd76ecbc40b5864, 0x3fba0eeb244baff0,
+           0x3fcd6d36a4399740, 0xbfdfd005f440f21c, 0xbfe2c1342d3e9986,
+           0xbfe50f78d644befe, 0xbfead02f97efc88a, 0xbfe4cae06b94e0d2,
+           0xbfdc713edf93dac0, 0xbfec312f997ec7ac, 0x3fdc4ca1f0c30314,
+           0x3faf0859109c77c0);
+  asm volatile("vfmadd.vf v1, %[A], v2" ::[A] "f"(dscalar_64));
+  //              -0.5896239092143964, -1.2989386647705283, -0.2225204504323405,
+  //              1.1305842246079476, -0.4997635227612305,  0.5295330954311120,
+  //              -0.8048662854791286,  0.3878770491466992, -0.5035828135241305,
+  //              -0.3969929346554276, -1.1732547424504496,  0.1094702669545694,
+  //              -0.7212349688741608,  0.0139056869464266, -0.7185807615459836,
+  //              0.0559137678222272
+  VCMP_U64(9, v1, 0xbfe2de32f5e07f06, 0xbff4c873e8cb3071, 0xbfcc7b8cd4a627de,
+           0x3ff216df7be108d1, 0xbfdffc20247f9130, 0x3fe0f1ef63e0d73b,
+           0xbfe9c176f0b925be, 0x3fd8d2fa423d0f48, 0xbfe01d59b45d3de9,
+           0xbfd968550dc5a3de, 0xbff2c5a6c3cb39b0, 0x3fbc063e50744ab8,
+           0xbfe7145b5b8179a4, 0x3f8c7a95b54e78da, 0xbfe6fe9d14cbfe26,
+           0x3faca0bab8629cdd);
+};
+
+// Simple random test with similar values (vector-scalar) (masked)
+void TEST_CASE4(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //                              0.6299
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0x390a);
+  //               -0.5352,  0.1115,  0.9541, -0.8857, -0.4143,  0.4045, 0.2949,
+  //               -0.5479,  0.6733,  0.8965,  0.8882,  0.6294,  0.7568, 0.8735,
+  //               -0.8569,  0.8271
+  VLOAD_16(v2, 0xb848, 0x2f23, 0x3ba2, 0xbb16, 0xb6a1, 0x3679, 0x34b8, 0xb862,
+           0x3963, 0x3b2c, 0x3b1b, 0x3909, 0x3a0e, 0x3afd, 0xbadb, 0x3a9e);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //                0.2844,  0.1008,  0.3777,  0.9790, -0.8613,  0.4951, 0.4126,
+  //                0.5518, -0.6680, -0.8340,  0.2094,  0.5884, -0.6509,
+  //                -0.9360, -0.1609, -0.2527
+  VLOAD_16(v1, 0x348d, 0x2e74, 0x360b, 0x3bd5, 0xbae4, 0x37ec, 0x369a, 0x386a,
+           0xb958, 0xbaac, 0x32b3, 0x38b5, 0xb935, 0xbb7d, 0xb126, 0xb40b);
+  asm volatile("vfmadd.vf v1, %[A], v2, v0.t" ::[A] "f"(dscalar_16));
+  VCMP_U16(10, v1, 0x348d, 0x319a, 0x360b, 0xb44e, 0xbae4, 0x39bb, 0x369a,
+           0xb269, 0xb958, 0x35f0, 0x32b3, 0x3c00, 0xb935, 0x348b, 0xb126,
+           0x3958);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                               0.80368215
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0x3f4dbe1d);
+  //                0.13072050, -0.19741143,  0.09370349,  0.41049519,
+  //                -0.69910282, -0.90573430,  0.86481184,  0.33341369,
+  //                0.30657578, -0.90526944, -0.97891974, -0.50830764,
+  //                0.79750061,  0.96885878,  0.48752418,  0.64305341
+  VLOAD_32(v2, 0x3e05db98, 0xbe4a2639, 0x3dbfe79e, 0x3ed22c6d, 0xbf32f867,
+           0xbf67de34, 0x3f5d644f, 0x3eaab533, 0x3e9cf780, 0xbf67bfbd,
+           0xbf7a9a7c, 0xbf022073, 0x3f4c2900, 0x3f780721, 0x3ef99cc5,
+           0x3f249f26);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //               -0.61117887,  0.81778014, -0.46267223, -0.30897874,
+  //               -0.84296966,  0.50125730,  0.96147668,  0.65802389,
+  //               0.19629262, -0.73197508, -0.06948850, -0.60436314,
+  //               -0.80817568,  0.72047287, -0.78180677, -0.40237895
+  VLOAD_32(v1, 0xbf1c7638, 0x3f515a0a, 0xbeece360, 0xbe9e3276, 0xbf57ccdc,
+           0x3f005266, 0x3f762356, 0x3f287441, 0x3e4900ef, 0xbf3b62b8,
+           0xbd8e4ffc, 0xbf1ab78b, 0xbf4ee49a, 0x3f3870e9, 0xbf48247d,
+           0xbece049d);
+  asm volatile("vfmadd.vf v1, %[A], v2, v0.t" ::[A] "f"(dscalar_32));
+  VCMP_U32(11, v1, 0xbf1c7638, 0x3eeb6e09, 0xbeece360, 0x3e261112, 0xbf57ccdc,
+           0xbf00bced, 0x3f762356, 0x3f5cbccb, 0x3e4900ef, 0xbfbf2c79,
+           0xbd8e4ffc, 0xbf7e7853, 0xbf4ee49a, 0x3fc62142, 0xbf48247d,
+           0x3ea3ab9c);
+
+  VSET(16, e64, m1);
+  double dscalar_64;
+  //                                0.5717861827636179
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0x3fe24c128968c808);
+  //                -0.0978999279373105, -0.8066508697961206,
+  //                0.1001298330116740,  0.6183499729699258,
+  //                -0.7091158569428311,  0.4713309006442494,
+  //                -0.9363173157138223,  0.6720957973877764,
+  //                -0.1684678230133414, -0.0206783343753454,
+  //                -0.6941474840922310,  0.4809970389518419,
+  //                -0.4671263490725479,  0.5176516826232249,
+  //                -0.9714116214357187,  0.0212574845134876
+  VLOAD_64(v2, 0xbfb90ff83cc58160, 0xbfe9d0157c220eae, 0x3fb9a21bd6239ad0,
+           0x3fe3c985e1ec6d14, 0xbfe6b113bcd49f88, 0x3fde2a4914f71f28,
+           0xbfedf64fbb356b82, 0x3fe581cf0bb1e7c4, 0xbfc5905a8722a398,
+           0xbf952cb38782ee00, 0xbfe63674c8d8dba6, 0x3fdec8a7cdf1580c,
+           0xbfdde565ea17744c, 0x3fe0909a42f2c184, 0xbfef15cdd320a9f0,
+           0x3f95c485a31f6440);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //                -0.8599787754583945, -0.8609648323347547,
+  //                -0.5642848553711928,  0.8958493001041692,
+  //                0.3661374487395561,  0.1017901385891375, 0.2298954297904690,
+  //                -0.4970717320718749, -0.5860844501192310,
+  //                -0.6581386742527398, -0.8379133193505066,
+  //                -0.6497652150347000, -0.4444119628309799,
+  //                -0.8810041425660891,  0.4421772814931029, 0.0606105644967410
+  VLOAD_64(v1, 0xbfeb84f2357b2242, 0xbfeb8d061ebc48de, 0xbfe20e9f1cee50cc,
+           0x3fecaacc26c2f0d0, 0x3fd76ecbc40b5864, 0x3fba0eeb244baff0,
+           0x3fcd6d36a4399740, 0xbfdfd005f440f21c, 0xbfe2c1342d3e9986,
+           0xbfe50f78d644befe, 0xbfead02f97efc88a, 0xbfe4cae06b94e0d2,
+           0xbfdc713edf93dac0, 0xbfec312f997ec7ac, 0x3fdc4ca1f0c30314,
+           0x3faf0859109c77c0);
+  asm volatile("vfmadd.vf v1, %[A], v2, v0.t" ::[A] "f"(dscalar_64));
+  VCMP_U64(12, v1, 0xbfeb84f2357b2242, 0xbff4c873e8cb3071, 0xbfe20e9f1cee50cc,
+           0x3ff216df7be108d1, 0x3fd76ecbc40b5864, 0x3fe0f1ef63e0d73b,
+           0x3fcd6d36a4399740, 0x3fd8d2fa423d0f48, 0xbfe2c1342d3e9986,
+           0xbfd968550dc5a3de, 0xbfead02f97efc88a, 0x3fbc063e50744ab8,
+           0xbfdc713edf93dac0, 0x3f8c7a95b54e78da, 0x3fdc4ca1f0c30314,
+           0x3faca0bab8629cdd);
+};
+
+int main(void) {
+  enable_vec();
+  enable_fp();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vfmax.c b/apps/riscv-tests/isa/rv64uv/vfmax.c
new file mode 100644
index 0000000..732e9eb
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vfmax.c
@@ -0,0 +1,351 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+// Simple random test with similar values + 1 subnormal
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  //               0.0445, -0.4812,  0.5732,  0.0634,  0.2072, -0.6416,  0.7759,
+  //               -0.0042,  0.6138,  0.7847, -0.5337,  0.3455,  0.0304, 0.7920,
+  //               0.8179, -0.5659
+  VLOAD_16(v2, 0x29b3, 0xb7b3, 0x3896, 0x2c0f, 0x32a1, 0xb922, 0x3a35, 0x9c4d,
+           0x38e9, 0x3a47, 0xb845, 0x3587, 0x27ca, 0x3a56, 0x3a8b, 0xb887);
+  //               0.6426, -0.4099, -0.1183,  0.2915,  0.5972, -0.1932, -0.0265,
+  //               -0.5913, -0.8560,  0.5029, -0.8975, -0.7373,  0.3701, 0.9546,
+  //               -0.2671, -0.6855
+  VLOAD_16(v3, 0x3924, 0xb68f, 0xaf93, 0x34aa, 0x38c7, 0xb22f, 0xa6c7, 0xb8bb,
+           0xbad9, 0x3806, 0xbb2e, 0xb9e6, 0x35ec, 0x3ba3, 0xb446, 0xb97c);
+  asm volatile("vfmax.vv v1, v2, v3");
+  //               0.6426, -0.4099,  0.5732,  0.2915,  0.5972, -0.1932,  0.7759,
+  //               -0.0042,  0.6138,  0.7847, -0.5337,  0.3455,  0.3701, 0.9546,
+  //               0.8179, -0.5659
+  VCMP_U16(1, v1, 0x3924, 0xb68f, 0x3896, 0x34aa, 0x38c7, 0xb22f, 0x3a35,
+           0x9c4d, 0x38e9, 0x3a47, 0xb845, 0x3587, 0x35ec, 0x3ba3, 0x3a8b,
+           0xb887);
+
+  VSET(16, e32, m1);
+  //              -0.19589283,  0.64597517, -0.09556163,  0.96582597,
+  //              0.93413597,  0.78331935, -0.18831402, -0.29520443, 0.09486515,
+  //              0.96548969,  0.74523991,  0.81442171,  0.25644442,
+  //              -0.92091519,  0.25139943, -0.77403748
+  VLOAD_32(v2, 0xbe489821, 0x3f255ea1, 0xbdc3b5d1, 0x3f77405f, 0x3f6f2389,
+           0x3f48879e, 0xbe40d564, 0xbe972509, 0x3dc248a9, 0x3f772a55,
+           0x3f3ec80b, 0x3f507df1, 0x3e834caf, 0xbf6bc119, 0x3e80b76d,
+           0xbf462752);
+  //              -0.58921623,  0.69345474,  0.64817399, -0.00869324,
+  //              0.15872470, -0.17028977, -0.99863762, -0.02739566,
+  //              -0.08060763,  0.73060948,  0.62843031,  0.68798363,
+  //              -0.35207590,  0.01353026,  0.25345275, -0.93635505
+  VLOAD_32(v3, 0xbf16d6e0, 0x3f318640, 0x3f25eebb, 0xbc0e6e1c, 0x3e2288ba,
+           0xbe2e6071, 0xbf7fa6b7, 0xbce06cdd, 0xbda5159d, 0x3f3b0939,
+           0x3f20e0cf, 0x3f301fb2, 0xbeb4434b, 0x3c5dae02, 0x3e81c48f,
+           0xbf6fb4f7);
+  asm volatile("vfmax.vv v1, v2, v3");
+  //              -0.19589283,  0.69345474,  0.64817399,  0.96582597,
+  //              0.93413597,  0.78331935, -0.18831402, -0.02739566, 0.09486515,
+  //              0.96548969,  0.74523991,  0.81442171,  0.25644442, 0.01353026,
+  //              0.25345275, -0.77403748
+  VCMP_U32(2, v1, 0xbe489821, 0x3f318640, 0x3f25eebb, 0x3f77405f, 0x3f6f2389,
+           0x3f48879e, 0xbe40d564, 0xbce06cdd, 0x3dc248a9, 0x3f772a55,
+           0x3f3ec80b, 0x3f507df1, 0x3e834caf, 0x3c5dae02, 0x3e81c48f,
+           0xbf462752);
+
+  VSET(16, e64, m1);
+  //              -0.4061329687298849, -0.2985478109200665,  0.0070087316277823,
+  //              -0.2169778494878496, -0.8530745559533048, -0.1247477743553222,
+  //              0.5680045000966327,  0.9515829310663801, -0.9797693611753244,
+  //              0.0055288881366042,  0.3717566019240965,  0.0982171502328268,
+  //              -0.1563664923399100,  0.9555697921812856,  0.4810293698835877,
+  //              -0.1835757691555060
+  VLOAD_64(v2, 0xbfd9fe1522a16c7c, 0xbfd31b68470c6bc4, 0x3f7cb530120b5400,
+           0xbfcbc5ee1fc0dc58, 0xbfeb4c6302dbd036, 0xbfbfef785b1ada80,
+           0x3fe22d17c5fcaaf0, 0x3fee735e0c0b94e4, 0xbfef5a45467bddd8,
+           0x3f76a5759bade800, 0x3fd7cadc33d5826c, 0x3fb924c2582803f0,
+           0xbfc403d135652390, 0x3fee940719ceda38, 0x3fdec92f69043118,
+           0xbfc77f692a6e3368);
+  //              -0.5461826062085420, -0.4431702866722571, -0.7458438472286320,
+  //              -0.8611805160192025,  0.5288841839862100,  0.4836992661145783,
+  //              -0.5942889927274901,  0.5287333894552471,  0.3093279352228719,
+  //              -0.5415645292681506,  0.0094485111801912, -0.2151605186231076,
+  //              -0.0785069829906857,  0.6345480854408712,  0.4658290296396683,
+  //              -0.5143497066150833
+  VLOAD_64(v3, 0xbfe17a53f1e9e958, 0xbfdc5ce6e7f43e14, 0xbfe7ddf3ea78a228,
+           0xbfeb8eca710827f8, 0x3fe0ec9e8632f518, 0x3fdef4edc443ec94,
+           0xbfe3046a59846530, 0x3fe0eb6249006ebc, 0x3fd3cc0765615f4c,
+           0xbfe1547f22bc2bc2, 0x3f8359bdb41e5580, 0xbfcb8a613f7035f0,
+           0xbfb419089c73df20, 0x3fe44e37c956a792, 0x3fddd0248ff51b48,
+           0xbfe0758d8413ceaa);
+  asm volatile("vfmax.vv v1, v2, v3");
+  //              -0.4061329687298849, -0.2985478109200665,  0.0070087316277823,
+  //              -0.2169778494878496,  0.5288841839862100,  0.4836992661145783,
+  //              0.5680045000966327,  0.9515829310663801,  0.3093279352228719,
+  //              0.0055288881366042,  0.3717566019240965,  0.0982171502328268,
+  //              -0.0785069829906857,  0.9555697921812856,  0.4810293698835877,
+  //              -0.1835757691555060
+  VCMP_U64(3, v1, 0xbfd9fe1522a16c7c, 0xbfd31b68470c6bc4, 0x3f7cb530120b5400,
+           0xbfcbc5ee1fc0dc58, 0x3fe0ec9e8632f518, 0x3fdef4edc443ec94,
+           0x3fe22d17c5fcaaf0, 0x3fee735e0c0b94e4, 0x3fd3cc0765615f4c,
+           0x3f76a5759bade800, 0x3fd7cadc33d5826c, 0x3fb924c2582803f0,
+           0xbfb419089c73df20, 0x3fee940719ceda38, 0x3fdec92f69043118,
+           0xbfc77f692a6e3368);
+};
+
+// Simple random test with similar values + 1 subnormal (masked)
+// The numbers are the same of TEST_CASE1
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  //               0.0445, -0.4812,  0.5732,  0.0634,  0.2072, -0.6416,  0.7759,
+  //               -0.0042,  0.6138,  0.7847, -0.5337,  0.3455,  0.0304, 0.7920,
+  //               0.8179, -0.5659
+  VLOAD_16(v2, 0x29b3, 0xb7b3, 0x3896, 0x2c0f, 0x32a1, 0xb922, 0x3a35, 0x9c4d,
+           0x38e9, 0x3a47, 0xb845, 0x3587, 0x27ca, 0x3a56, 0x3a8b, 0xb887);
+  //               0.6426, -0.4099, -0.1183,  0.2915,  0.5972, -0.1932, -0.0265,
+  //               -0.5913, -0.8560,  0.5029, -0.8975, -0.7373,  0.3701, 0.9546,
+  //               -0.2671, -0.6855
+  VLOAD_16(v3, 0x3924, 0xb68f, 0xaf93, 0x34aa, 0x38c7, 0xb22f, 0xa6c7, 0xb8bb,
+           0xbad9, 0x3806, 0xbb2e, 0xb9e6, 0x35ec, 0x3ba3, 0xb446, 0xb97c);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfmax.vv v1, v2, v3, v0.t");
+  //               0.0000, -0.4099,  0.0000,  0.2915,  0.0000, -0.1932,  0.0000,
+  //               -0.0042,  0.0000,  0.7847,  0.0000,  0.3455,  0.0000, 0.9546,
+  //               0.0000, -0.5659
+  VCMP_U16(4, v1, 0x0, 0xb68f, 0x0, 0x34aa, 0x0, 0xb22f, 0x0, 0x9c4d, 0x0,
+           0x3a47, 0x0, 0x3587, 0x0, 0x3ba3, 0x0, 0xb887);
+
+  VSET(16, e32, m1);
+  //              -0.19589283,  0.64597517, -0.09556163,  0.96582597,
+  //              0.93413597,  0.78331935, -0.18831402, -0.29520443, 0.09486515,
+  //              0.96548969,  0.74523991,  0.81442171,  0.25644442,
+  //              -0.92091519,  0.25139943, -0.77403748
+  VLOAD_32(v2, 0xbe489821, 0x3f255ea1, 0xbdc3b5d1, 0x3f77405f, 0x3f6f2389,
+           0x3f48879e, 0xbe40d564, 0xbe972509, 0x3dc248a9, 0x3f772a55,
+           0x3f3ec80b, 0x3f507df1, 0x3e834caf, 0xbf6bc119, 0x3e80b76d,
+           0xbf462752);
+  //              -0.58921623,  0.69345474,  0.64817399, -0.00869324,
+  //              0.15872470, -0.17028977, -0.99863762, -0.02739566,
+  //              -0.08060763,  0.73060948,  0.62843031,  0.68798363,
+  //              -0.35207590,  0.01353026,  0.25345275, -0.93635505
+  VLOAD_32(v3, 0xbf16d6e0, 0x3f318640, 0x3f25eebb, 0xbc0e6e1c, 0x3e2288ba,
+           0xbe2e6071, 0xbf7fa6b7, 0xbce06cdd, 0xbda5159d, 0x3f3b0939,
+           0x3f20e0cf, 0x3f301fb2, 0xbeb4434b, 0x3c5dae02, 0x3e81c48f,
+           0xbf6fb4f7);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfmax.vv v1, v2, v3, v0.t");
+  //               0.00000000,  0.69345474,  0.00000000,  0.96582597,
+  //               0.00000000,  0.78331935,  0.00000000, -0.02739566,
+  //               0.00000000,  0.96548969,  0.00000000,  0.81442171,
+  //               0.00000000,  0.01353026,  0.00000000, -0.77403748
+  VCMP_U32(5, v1, 0x0, 0x3f318640, 0x0, 0x3f77405f, 0x0, 0x3f48879e, 0x0,
+           0xbce06cdd, 0x0, 0x3f772a55, 0x0, 0x3f507df1, 0x0, 0x3c5dae02, 0x0,
+           0xbf462752);
+
+  VSET(16, e64, m1);
+  //              -0.4061329687298849, -0.2985478109200665,  0.0070087316277823,
+  //              -0.2169778494878496, -0.8530745559533048, -0.1247477743553222,
+  //              0.5680045000966327,  0.9515829310663801, -0.9797693611753244,
+  //              0.0055288881366042,  0.3717566019240965,  0.0982171502328268,
+  //              -0.1563664923399100,  0.9555697921812856,  0.4810293698835877,
+  //              -0.1835757691555060
+  VLOAD_64(v2, 0xbfd9fe1522a16c7c, 0xbfd31b68470c6bc4, 0x3f7cb530120b5400,
+           0xbfcbc5ee1fc0dc58, 0xbfeb4c6302dbd036, 0xbfbfef785b1ada80,
+           0x3fe22d17c5fcaaf0, 0x3fee735e0c0b94e4, 0xbfef5a45467bddd8,
+           0x3f76a5759bade800, 0x3fd7cadc33d5826c, 0x3fb924c2582803f0,
+           0xbfc403d135652390, 0x3fee940719ceda38, 0x3fdec92f69043118,
+           0xbfc77f692a6e3368);
+  //              -0.5461826062085420, -0.4431702866722571, -0.7458438472286320,
+  //              -0.8611805160192025,  0.5288841839862100,  0.4836992661145783,
+  //              -0.5942889927274901,  0.5287333894552471,  0.3093279352228719,
+  //              -0.5415645292681506,  0.0094485111801912, -0.2151605186231076,
+  //              -0.0785069829906857,  0.6345480854408712,  0.4658290296396683,
+  //              -0.5143497066150833
+  VLOAD_64(v3, 0xbfe17a53f1e9e958, 0xbfdc5ce6e7f43e14, 0xbfe7ddf3ea78a228,
+           0xbfeb8eca710827f8, 0x3fe0ec9e8632f518, 0x3fdef4edc443ec94,
+           0xbfe3046a59846530, 0x3fe0eb6249006ebc, 0x3fd3cc0765615f4c,
+           0xbfe1547f22bc2bc2, 0x3f8359bdb41e5580, 0xbfcb8a613f7035f0,
+           0xbfb419089c73df20, 0x3fe44e37c956a792, 0x3fddd0248ff51b48,
+           0xbfe0758d8413ceaa);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfmax.vv v1, v2, v3, v0.t");
+  //               0.0000000000000000, -0.2985478109200665,  0.0000000000000000,
+  //               -0.2169778494878496,  0.0000000000000000, 0.4836992661145783,
+  //               0.0000000000000000,  0.9515829310663801,  0.0000000000000000,
+  //               0.0055288881366042,  0.0000000000000000,  0.0982171502328268,
+  //               0.0000000000000000,  0.9555697921812856,  0.0000000000000000,
+  //               -0.1835757691555060
+  VCMP_U64(6, v1, 0x0, 0xbfd31b68470c6bc4, 0x0, 0xbfcbc5ee1fc0dc58, 0x0,
+           0x3fdef4edc443ec94, 0x0, 0x3fee735e0c0b94e4, 0x0, 0x3f76a5759bade800,
+           0x0, 0x3fb924c2582803f0, 0x0, 0x3fee940719ceda38, 0x0,
+           0xbfc77f692a6e3368);
+};
+
+// Simple random test with similar values (vector-scalar)
+void TEST_CASE3(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //                              0.0368
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0x28b5);
+  //              -0.5518,  0.6772,  0.2756,  0.4421,  0.2081,  0.6250,  0.4136,
+  //              0.8203, -0.3535, -0.1597, -0.5244,  0.8696,  0.1744,  0.0793,
+  //              -0.2445, -0.4031
+  VLOAD_16(v2, 0xb86a, 0x396b, 0x3469, 0x3713, 0x32a9, 0x3900, 0x369e, 0x3a90,
+           0xb5a8, 0xb11c, 0xb832, 0x3af5, 0x3195, 0x2d14, 0xb3d3, 0xb673);
+  asm volatile("vfmax.vf v1, v2, %[A]" ::[A] "f"(dscalar_16));
+  //               0.0368,  0.6772,  0.2756,  0.4421,  0.2081,  0.6250,  0.4136,
+  //               0.8203,  0.0368,  0.0368,  0.0368,  0.8696,  0.1744,  0.0793,
+  //               0.0368,  0.0368
+  VCMP_U16(7, v1, 0x28b5, 0x396b, 0x3469, 0x3713, 0x32a9, 0x3900, 0x369e,
+           0x3a90, 0x28b5, 0x28b5, 0x28b5, 0x3af5, 0x3195, 0x2d14, 0x28b5,
+           0x28b5);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                              -0.94383347
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0xbf719f12);
+  //               0.51733643,  0.31252080,  0.47358772,  0.13738893,
+  //               0.11194360, -0.33637357,  0.83680850,  0.95792335,
+  //               0.41251704,  0.27496886, -0.06774041, -0.19357064,
+  //               -0.48802575, -0.53921199,  0.32722279,  0.28428423
+  VLOAD_32(v2, 0x3f047029, 0x3ea002ba, 0x3ef27a17, 0x3e0cafaf, 0x3de542b0,
+           0xbeac3928, 0x3f563915, 0x3f753a77, 0x3ed3356f, 0x3e8cc8b8,
+           0xbd8abb7c, 0xbe463762, 0xbef9de83, 0xbf0a09cc, 0x3ea789bf,
+           0x3e918db4);
+  asm volatile("vfmax.vf v1, v2, %[A]" ::[A] "f"(dscalar_32));
+  //               0.51733643,  0.31252080,  0.47358772,  0.13738893,
+  //               0.11194360, -0.33637357,  0.83680850,  0.95792335,
+  //               0.41251704,  0.27496886, -0.06774041, -0.19357064,
+  //               -0.48802575, -0.53921199,  0.32722279,  0.28428423
+  VCMP_U32(8, v1, 0x3f047029, 0x3ea002ba, 0x3ef27a17, 0x3e0cafaf, 0x3de542b0,
+           0xbeac3928, 0x3f563915, 0x3f753a77, 0x3ed3356f, 0x3e8cc8b8,
+           0xbd8abb7c, 0xbe463762, 0xbef9de83, 0xbf0a09cc, 0x3ea789bf,
+           0x3e918db4);
+
+  VSET(16, e64, m1);
+  double dscalar_64;
+  //                               -0.8274885128397702
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0xbfea7ac9308eccb6);
+  //                0.9632225672084347,  0.4671677538923853,
+  //                -0.1749283847947720, -0.0938698612480795,
+  //                0.3438198935172891,  0.2938331380713377,
+  //                -0.3607699326176230,  0.6841623039857032,
+  //                -0.6959644979744999,  0.4712155929452235,
+  //                0.1886883982201846,  0.9268486384654282,
+  //                -0.9639662652720637, -0.2101071651393955,
+  //                0.0859470276611187, -0.7001184217853196
+  VLOAD_64(v2, 0x3feed2b8221dbd8e, 0x3fdde613942dab28, 0xbfc6640da5eaf690,
+           0xbfb807daf023fbb0, 0x3fd601252797bdcc, 0x3fd2ce29819fd630,
+           0xbfd716dac57e4298, 0x3fe5e4a85818c992, 0xbfe6455756bf47f8,
+           0x3fde2865724428b0, 0x3fc826f101bec2b8, 0x3feda8be79d1a2f4,
+           0xbfeed8cfc7f94e06, 0xbfcae4caa576e8a8, 0x3fb6009fd8fe2f80,
+           0xbfe6675ebf9ca482);
+  asm volatile("vfmax.vf v1, v2, %[A]" ::[A] "f"(dscalar_64));
+  //               0.9632225672084347,  0.4671677538923853, -0.1749283847947720,
+  //               -0.0938698612480795,  0.3438198935172891, 0.2938331380713377,
+  //               -0.3607699326176230,  0.6841623039857032,
+  //               -0.6959644979744999,  0.4712155929452235, 0.1886883982201846,
+  //               0.9268486384654282, -0.8274885128397702, -0.2101071651393955,
+  //               0.0859470276611187, -0.7001184217853196
+  VCMP_U64(9, v1, 0x3feed2b8221dbd8e, 0x3fdde613942dab28, 0xbfc6640da5eaf690,
+           0xbfb807daf023fbb0, 0x3fd601252797bdcc, 0x3fd2ce29819fd630,
+           0xbfd716dac57e4298, 0x3fe5e4a85818c992, 0xbfe6455756bf47f8,
+           0x3fde2865724428b0, 0x3fc826f101bec2b8, 0x3feda8be79d1a2f4,
+           0xbfea7ac9308eccb6, 0xbfcae4caa576e8a8, 0x3fb6009fd8fe2f80,
+           0xbfe6675ebf9ca482);
+};
+
+// Simple random test with similar values (vector-scalar) (masked)
+void TEST_CASE4(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //                              0.0368
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0x28b5);
+  //               -0.5518,  0.6772,  0.2756,  0.4421,  0.2081,  0.6250, 0.4136,
+  //               0.8203, -0.3535, -0.1597, -0.5244,  0.8696,  0.1744,  0.0793,
+  //               -0.2445, -0.4031
+  VLOAD_16(v2, 0xb86a, 0x396b, 0x3469, 0x3713, 0x32a9, 0x3900, 0x369e, 0x3a90,
+           0xb5a8, 0xb11c, 0xb832, 0x3af5, 0x3195, 0x2d14, 0xb3d3, 0xb673);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfmax.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_16));
+  //                0.0000,  0.6772,  0.0000,  0.4421,  0.0000,  0.6250, 0.0000,
+  //                0.8203,  0.0000,  0.0368,  0.0000,  0.8696,  0.0000, 0.0793,
+  //                0.0000,  0.0368
+  VCMP_U16(10, v1, 0x0, 0x396b, 0x0, 0x3713, 0x0, 0x3900, 0x0, 0x3a90, 0x0,
+           0x28b5, 0x0, 0x3af5, 0x0, 0x2d14, 0x0, 0x28b5);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                              -0.94383347
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0xbf719f12);
+  //                0.51733643,  0.31252080,  0.47358772,  0.13738893,
+  //                0.11194360, -0.33637357,  0.83680850,  0.95792335,
+  //                0.41251704,  0.27496886, -0.06774041, -0.19357064,
+  //                -0.48802575, -0.53921199,  0.32722279,  0.28428423
+  VLOAD_32(v2, 0x3f047029, 0x3ea002ba, 0x3ef27a17, 0x3e0cafaf, 0x3de542b0,
+           0xbeac3928, 0x3f563915, 0x3f753a77, 0x3ed3356f, 0x3e8cc8b8,
+           0xbd8abb7c, 0xbe463762, 0xbef9de83, 0xbf0a09cc, 0x3ea789bf,
+           0x3e918db4);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfmax.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_32));
+  //                0.00000000,  0.31252080,  0.00000000,  0.13738893,
+  //                0.00000000, -0.33637357,  0.00000000,  0.95792335,
+  //                0.00000000,  0.27496886,  0.00000000, -0.19357064,
+  //                0.00000000, -0.53921199,  0.00000000,  0.28428423
+  VCMP_U32(11, v1, 0x0, 0x3ea002ba, 0x0, 0x3e0cafaf, 0x0, 0xbeac3928, 0x0,
+           0x3f753a77, 0x0, 0x3e8cc8b8, 0x0, 0xbe463762, 0x0, 0xbf0a09cc, 0x0,
+           0x3e918db4);
+
+  VSET(16, e64, m1);
+  double dscalar_64;
+  //                               -0.8274885128397702
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0xbfea7ac9308eccb6);
+  //                 0.9632225672084347,  0.4671677538923853,
+  //                 -0.1749283847947720, -0.0938698612480795,
+  //                 0.3438198935172891,  0.2938331380713377,
+  //                 -0.3607699326176230,  0.6841623039857032,
+  //                 -0.6959644979744999,  0.4712155929452235,
+  //                 0.1886883982201846,  0.9268486384654282,
+  //                 -0.9639662652720637, -0.2101071651393955,
+  //                 0.0859470276611187, -0.7001184217853196
+  VLOAD_64(v2, 0x3feed2b8221dbd8e, 0x3fdde613942dab28, 0xbfc6640da5eaf690,
+           0xbfb807daf023fbb0, 0x3fd601252797bdcc, 0x3fd2ce29819fd630,
+           0xbfd716dac57e4298, 0x3fe5e4a85818c992, 0xbfe6455756bf47f8,
+           0x3fde2865724428b0, 0x3fc826f101bec2b8, 0x3feda8be79d1a2f4,
+           0xbfeed8cfc7f94e06, 0xbfcae4caa576e8a8, 0x3fb6009fd8fe2f80,
+           0xbfe6675ebf9ca482);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfmax.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_64));
+  //                0.0000000000000000,  0.4671677538923853, 0.0000000000000000,
+  //                -0.0938698612480795,  0.0000000000000000,
+  //                0.2938331380713377,  0.0000000000000000, 0.6841623039857032,
+  //                0.0000000000000000,  0.4712155929452235, 0.0000000000000000,
+  //                0.9268486384654282,  0.0000000000000000,
+  //                -0.2101071651393955,  0.0000000000000000,
+  //                -0.7001184217853196
+  VCMP_U64(12, v1, 0x0, 0x3fdde613942dab28, 0x0, 0xbfb807daf023fbb0, 0x0,
+           0x3fd2ce29819fd630, 0x0, 0x3fe5e4a85818c992, 0x0, 0x3fde2865724428b0,
+           0x0, 0x3feda8be79d1a2f4, 0x0, 0xbfcae4caa576e8a8, 0x0,
+           0xbfe6675ebf9ca482);
+};
+
+int main(void) {
+  enable_vec();
+  enable_fp();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vfmerge.c b/apps/riscv-tests/isa/rv64uv/vfmerge.c
new file mode 100644
index 0000000..b98192d
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vfmerge.c
@@ -0,0 +1,94 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+//         Matteo Perotti <mperotti@student.ethz.ch>
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  //              -0.1481, -0.1797, -0.5454,  0.3228,  0.3237, -0.7212, -0.5195,
+  //              -0.4500,  0.2681,  0.7300,  0.5059,  0.5830,  0.3198, -0.1713,
+  //              -0.6431,  0.4841
+  VLOAD_16(v2, 0xb0bd, 0xb1c0, 0xb85d, 0x352a, 0x352e, 0xb9c5, 0xb828, 0xb733,
+           0x344a, 0x39d7, 0x380c, 0x38aa, 0x351e, 0xb17b, 0xb925, 0x37bf);
+  double dscalar_16;
+  //                            -0.9380
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0xbb81);
+  VLOAD_8(v0, 0x0F, 0xAA);
+  asm volatile("vfmerge.vfm v1, v2, %[A], v0" ::[A] "f"(dscalar_16));
+  //               -0.9380, -0.9380, -0.9380, -0.9380,  0.3237, -0.7212,
+  //               -0.5195, -0.4500,  0.2681, -0.9380,  0.5059, -0.9380, 0.3198,
+  //               -0.9380, -0.6431, -0.9380
+  VCMP_U16(1, v1, 0xbb81, 0xbb81, 0xbb81, 0xbb81, 0x352e, 0xb9c5, 0xb828,
+           0xb733, 0x344a, 0xbb81, 0x380c, 0xbb81, 0x351e, 0xbb81, 0xb925,
+           0xbb81);
+
+  VSET(16, e32, m1);
+  //               0.86539453, -0.53925377, -0.47128764,  0.99265540,
+  //               0.32128176, -0.47335613, -0.30028856,  0.44394016,
+  //               -0.72540921, -0.26464799,  0.77351445, -0.21725702,
+  //               -0.25191557, -0.53123665,  0.80404943,  0.81841671
+  VLOAD_32(v2, 0x3f5d8a7f, 0xbf0a0c89, 0xbef14c9d, 0x3f7e1eaa, 0x3ea47f0b,
+           0xbef25bbc, 0xbe99bf6c, 0x3ee34c20, 0xbf39b46b, 0xbe877ff1,
+           0x3f46050b, 0xbe5e78a0, 0xbe80fb14, 0xbf07ff20, 0x3f4dd62f,
+           0x3f5183c2);
+  double dscalar_32;
+  //                             -0.96056187
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0xbf75e762);
+  VLOAD_8(v0, 0x0F, 0xAA);
+  asm volatile("vfmerge.vfm v1, v2, %[A], v0" ::[A] "f"(dscalar_32));
+  //               -0.96056187, -0.96056187, -0.96056187, -0.96056187,
+  //               0.32128176, -0.47335613, -0.30028856,  0.44394016,
+  //               -0.72540921, -0.96056187,  0.77351445, -0.96056187,
+  //               -0.25191557, -0.96056187,  0.80404943, -0.96056187
+  VCMP_U32(2, v1, 0xbf75e762, 0xbf75e762, 0xbf75e762, 0xbf75e762, 0x3ea47f0b,
+           0xbef25bbc, 0xbe99bf6c, 0x3ee34c20, 0xbf39b46b, 0xbf75e762,
+           0x3f46050b, 0xbf75e762, 0xbe80fb14, 0xbf75e762, 0x3f4dd62f,
+           0xbf75e762);
+
+  VSET(16, e64, m1);
+  //               -0.3488917150781869, -0.4501495513738740, 0.8731197104152684,
+  //               0.3256432550932964,  0.6502591178769535, -0.3169358689246526,
+  //               -0.5396694979141685, -0.5417807430937591,
+  //               -0.7971574213160249, -0.1764794100111047, 0.3564275916066595,
+  //               -0.3754449946313438,  0.6580947137446858,
+  //               -0.3328857144699515,  0.1761214464164236,  0.1429774118511240
+  VLOAD_64(v2, 0xbfd6543dea86cb60, 0xbfdccf40105d6e5c, 0x3febf098bf37400c,
+           0x3fd4d756ceb279f4, 0x3fe4ceec35a6a266, 0xbfd448ad61fd7c88,
+           0xbfe144f8f7861540, 0xbfe1564491a616b8, 0xbfe9825047ca1cd6,
+           0xbfc696e097352100, 0x3fd6cfb5ac55edec, 0xbfd8074a7158dd78,
+           0x3fe50f1ca5268668, 0xbfd54dffe23d0eec, 0x3fc68b25c63dcaf0,
+           0x3fc24d1575fbd080);
+  double dscalar_64;
+  //                               0.9108707261227378
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0x3fed25da5d7296fe);
+  VLOAD_8(v0, 0x0F, 0xAA);
+  asm volatile("vfmerge.vfm v1, v2, %[A], v0" ::[A] "f"(dscalar_64));
+  //                0.9108707261227378,  0.9108707261227378, 0.9108707261227378,
+  //                0.9108707261227378,  0.6502591178769535,
+  //                -0.3169358689246526, -0.5396694979141685,
+  //                -0.5417807430937591  -0.7971574213160249,
+  //                0.9108707261227378,  0.3564275916066595, 0.9108707261227378,
+  //                0.6580947137446858,  0.9108707261227378, 0.1761214464164236,
+  //                0.9108707261227378
+  VCMP_U64(3, v1, 0x3fed25da5d7296fe, 0x3fed25da5d7296fe, 0x3fed25da5d7296fe,
+           0x3fed25da5d7296fe, 0x3fe4ceec35a6a266, 0xbfd448ad61fd7c88,
+           0xbfe144f8f7861540, 0xbfe1564491a616b8, 0xbfe9825047ca1cd6,
+           0x3fed25da5d7296fe, 0x3fd6cfb5ac55edec, 0x3fed25da5d7296fe,
+           0x3fe50f1ca5268668, 0x3fed25da5d7296fe, 0x3fc68b25c63dcaf0,
+           0x3fed25da5d7296fe);
+};
+
+int main(void) {
+  enable_vec();
+  enable_fp();
+
+  TEST_CASE1();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vfmin.c b/apps/riscv-tests/isa/rv64uv/vfmin.c
new file mode 100644
index 0000000..1ebb2a5
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vfmin.c
@@ -0,0 +1,348 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+// Simple random test with similar values + 1 subnormal
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  //               0.9390,  0.9619,  0.9121,  0.6265,  0.1193, -0.4492, -0.3562,
+  //               0.2365, -0.9897,  0.8638, -0.0379, -0.6201,  0.1809,  0.9824,
+  //               -0.9922, -0.6851
+  VLOAD_16(v2, 0x3b83, 0x3bb2, 0x3b4c, 0x3903, 0x2fa2, 0xb730, 0xb5b3, 0x3391,
+           0xbbeb, 0x3ae9, 0xa8da, 0xb8f6, 0x31ca, 0x3bdc, 0xbbf0, 0xb97b);
+  //               0.9795, -0.1069,  0.7070, -0.7305,  0.0516, -0.1321,  0.3828,
+  //               0.0230, -0.9424, -0.8652, -0.3865, -0.1719, -0.7021,  0.1664,
+  //               0.7026, -0.8535
+  VLOAD_16(v3, 0x3bd6, 0xaed8, 0x39a8, 0xb9d8, 0x2a9a, 0xb03a, 0x3620, 0x25e2,
+           0xbb8a, 0xbaec, 0xb62f, 0xb180, 0xb99e, 0x3153, 0x399f, 0xbad4);
+  asm volatile("vfmin.vv v1, v2, v3");
+  //               0.9390, -0.1069,  0.7070, -0.7305,  0.0516, -0.4492, -0.3562,
+  //               0.0230, -0.9897, -0.8652, -0.3865, -0.6201, -0.7021,  0.1664,
+  //               -0.9922, -0.8535
+  VCMP_U16(1, v1, 0x3b83, 0xaed8, 0x39a8, 0xb9d8, 0x2a9a, 0xb730, 0xb5b3,
+           0x25e2, 0xbbeb, 0xbaec, 0xb62f, 0xb8f6, 0xb99e, 0x3153, 0xbbf0,
+           0xbad4);
+
+  VSET(16, e32, m1);
+  //               0.33477312, -0.14129849, -0.94871885,  0.83600986,
+  //               -0.28163233, -0.47814348,  0.77408481, -0.54823470,
+  //               -0.72419900,  0.27495387, -0.76835793,  0.71516198,
+  //               0.32305571, -0.76598656, -0.36499983, -0.52954155
+  VLOAD_32(v2, 0x3eab6762, 0xbe10b08d, 0xbf72df3d, 0x3f5604be, 0xbe90321d,
+           0xbef4cf39, 0x3f462a6c, 0xbf0c591c, 0xbf39651b, 0x3e8cc6c1,
+           0xbf44b31b, 0x3f3714db, 0x3ea5678f, 0xbf4417b2, 0xbebae142,
+           0xbf079009);
+  //               0.87184614,  0.40005061,  0.40118238,  0.97373396,
+  //               0.74085194, -0.99458516, -0.73125440, -0.46319291,
+  //               -0.76140571, -0.82557100,  0.15205561,  0.39971715,
+  //               -0.32876521, -0.53106725,  0.84727478,  0.21940185
+  VLOAD_32(v3, 0x3f5f314f, 0x3eccd36f, 0x3ecd67c7, 0x3f7946a1, 0x3f3da879,
+           0xbf7e9d22, 0xbf3b337d, 0xbeed279f, 0xbf42eb7c, 0xbf53589f,
+           0x3e1bb477, 0x3ecca7ba, 0xbea853ea, 0xbf07f406, 0x3f58e700,
+           0x3e60aae1);
+  asm volatile("vfmin.vv v1, v2, v3");
+  //               0.33477312, -0.14129849, -0.94871885,  0.83600986,
+  //               -0.28163233, -0.99458516, -0.73125440, -0.54823470,
+  //               -0.76140571, -0.82557100, -0.76835793,  0.39971715,
+  //               -0.32876521, -0.76598656, -0.36499983, -0.52954155
+  VCMP_U32(2, v1, 0x3eab6762, 0xbe10b08d, 0xbf72df3d, 0x3f5604be, 0xbe90321d,
+           0xbf7e9d22, 0xbf3b337d, 0xbf0c591c, 0xbf42eb7c, 0xbf53589f,
+           0xbf44b31b, 0x3ecca7ba, 0xbea853ea, 0xbf4417b2, 0xbebae142,
+           0xbf079009);
+
+  VSET(16, e64, m1);
+  //               0.9387726994461698,  0.8517969615002949, -0.8864275043807637,
+  //               0.3621349692771021,  0.5392486258321831, -0.1288714247798126,
+  //               -0.9149173505741688, -0.9378576380992047,
+  //               -0.2263428385339852,  0.1016628884386184, 0.4783549203499486,
+  //               0.5394596797016060,  0.7861587828590215,  0.0194772848204161,
+  //               -0.9126826319328591,  0.3997583898469530
+  VLOAD_64(v2, 0x3fee0a6d0b4ff74a, 0x3feb41ebb38f3ae2, 0xbfec5d9d36b2e38c,
+           0x3fd72d3826721e9c, 0x3fe14186558b96e0, 0xbfc07edbdd68bb68,
+           0xbfed4700c06849e8, 0xbfee02ee057e1390, 0xbfccf8cd5897f8a0,
+           0x3fba06943d0f8e20, 0x3fde9d5df4b22860, 0x3fe14340f23a8770,
+           0x3fe9283676baf718, 0x3f93f1da754635c0, 0xbfed34b234f8ec38,
+           0x3fd995a436ac6f1c);
+  //               0.4808082103120717,  0.7218925128932789, -0.9454618185734458,
+  //               0.7335258472548418,  0.9800819535502201, -0.6873536121819364,
+  //               -0.7090903925273744,  0.7813319828098306, 0.6810234154055235,
+  //               0.1176441554686278,  0.4929731878752270,  0.0942028280153233,
+  //               0.9496420237972776, -0.4549651855719854, -0.9663401540020158,
+  //               0.4114236885680320
+  VLOAD_64(v3, 0x3fdec58fccbc12a4, 0x3fe719be53c35314, 0xbfee413924cc77e4,
+           0x3fe7790b32975e1a, 0x3fef5cd4d43cbc4e, 0xbfe5fecd00a37bfa,
+           0xbfe6b0de55ba0314, 0x3fe900abee2f95f8, 0x3fe5caf19e1f4324,
+           0x3fbe1ded684da4d0, 0x3fdf8cdf69eea758, 0x3fb81dad31843b10,
+           0x3fee6377ab63bade, 0xbfdd1e264c366a78, 0xbfeeec422fc80224,
+           0x3fda54c405ccc2c0);
+  asm volatile("vfmin.vv v1, v2, v3");
+  //               0.4808082103120717,  0.7218925128932789, -0.9454618185734458,
+  //               0.3621349692771021,  0.5392486258321831, -0.6873536121819364,
+  //               -0.9149173505741688, -0.9378576380992047,
+  //               -0.2263428385339852,  0.1016628884386184, 0.4783549203499486,
+  //               0.0942028280153233,  0.7861587828590215, -0.4549651855719854,
+  //               -0.9663401540020158,  0.3997583898469530
+  VCMP_U64(3, v1, 0x3fdec58fccbc12a4, 0x3fe719be53c35314, 0xbfee413924cc77e4,
+           0x3fd72d3826721e9c, 0x3fe14186558b96e0, 0xbfe5fecd00a37bfa,
+           0xbfed4700c06849e8, 0xbfee02ee057e1390, 0xbfccf8cd5897f8a0,
+           0x3fba06943d0f8e20, 0x3fde9d5df4b22860, 0x3fb81dad31843b10,
+           0x3fe9283676baf718, 0xbfdd1e264c366a78, 0xbfeeec422fc80224,
+           0x3fd995a436ac6f1c);
+};
+
+// Simple random test with similar values + 1 subnormal (masked)
+// The numbers are the same of TEST_CASE1
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  //               0.9390,  0.9619,  0.9121,  0.6265,  0.1193, -0.4492, -0.3562,
+  //               0.2365, -0.9897,  0.8638, -0.0379, -0.6201,  0.1809,  0.9824,
+  //               -0.9922, -0.6851
+  VLOAD_16(v2, 0x3b83, 0x3bb2, 0x3b4c, 0x3903, 0x2fa2, 0xb730, 0xb5b3, 0x3391,
+           0xbbeb, 0x3ae9, 0xa8da, 0xb8f6, 0x31ca, 0x3bdc, 0xbbf0, 0xb97b);
+  //               0.9795, -0.1069,  0.7070, -0.7305,  0.0516, -0.1321,  0.3828,
+  //               0.0230, -0.9424, -0.8652, -0.3865, -0.1719, -0.7021,  0.1664,
+  //               0.7026, -0.8535
+  VLOAD_16(v3, 0x3bd6, 0xaed8, 0x39a8, 0xb9d8, 0x2a9a, 0xb03a, 0x3620, 0x25e2,
+           0xbb8a, 0xbaec, 0xb62f, 0xb180, 0xb99e, 0x3153, 0x399f, 0xbad4);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfmin.vv v1, v2, v3, v0.t");
+  //               0.0000, -0.1069,  0.0000, -0.7305,  0.0000, -0.4492,  0.0000,
+  //               0.0230,  0.0000, -0.8652,  0.0000, -0.6201,  0.0000,  0.1664,
+  //               0.0000, -0.8535
+  VCMP_U16(4, v1, 0x0, 0xaed8, 0x0, 0xb9d8, 0x0, 0xb730, 0x0, 0x25e2, 0x0,
+           0xbaec, 0x0, 0xb8f6, 0x0, 0x3153, 0x0, 0xbad4);
+
+  VSET(16, e32, m1);
+  //               0.33477312, -0.14129849, -0.94871885,  0.83600986,
+  //               -0.28163233, -0.47814348,  0.77408481, -0.54823470,
+  //               -0.72419900,  0.27495387, -0.76835793,  0.71516198,
+  //               0.32305571, -0.76598656, -0.36499983, -0.52954155
+  VLOAD_32(v2, 0x3eab6762, 0xbe10b08d, 0xbf72df3d, 0x3f5604be, 0xbe90321d,
+           0xbef4cf39, 0x3f462a6c, 0xbf0c591c, 0xbf39651b, 0x3e8cc6c1,
+           0xbf44b31b, 0x3f3714db, 0x3ea5678f, 0xbf4417b2, 0xbebae142,
+           0xbf079009);
+  //               0.87184614,  0.40005061,  0.40118238,  0.97373396,
+  //               0.74085194, -0.99458516, -0.73125440, -0.46319291,
+  //               -0.76140571, -0.82557100,  0.15205561,  0.39971715,
+  //               -0.32876521, -0.53106725,  0.84727478,  0.21940185
+  VLOAD_32(v3, 0x3f5f314f, 0x3eccd36f, 0x3ecd67c7, 0x3f7946a1, 0x3f3da879,
+           0xbf7e9d22, 0xbf3b337d, 0xbeed279f, 0xbf42eb7c, 0xbf53589f,
+           0x3e1bb477, 0x3ecca7ba, 0xbea853ea, 0xbf07f406, 0x3f58e700,
+           0x3e60aae1);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfmin.vv v1, v2, v3, v0.t");
+  //               0.00000000, -0.14129849,  0.00000000,  0.83600986,
+  //               0.00000000, -0.99458516,  0.00000000, -0.54823470,
+  //               0.00000000, -0.82557100,  0.00000000,  0.39971715,
+  //               0.00000000, -0.76598656,  0.00000000, -0.52954155
+  VCMP_U32(5, v1, 0x0, 0xbe10b08d, 0x0, 0x3f5604be, 0x0, 0xbf7e9d22, 0x0,
+           0xbf0c591c, 0x0, 0xbf53589f, 0x0, 0x3ecca7ba, 0x0, 0xbf4417b2, 0x0,
+           0xbf079009);
+
+  VSET(16, e64, m1);
+  //               0.9387726994461698,  0.8517969615002949, -0.8864275043807637,
+  //               0.3621349692771021,  0.5392486258321831, -0.1288714247798126,
+  //               -0.9149173505741688, -0.9378576380992047,
+  //               -0.2263428385339852,  0.1016628884386184, 0.4783549203499486,
+  //               0.5394596797016060,  0.7861587828590215,  0.0194772848204161,
+  //               -0.9126826319328591,  0.3997583898469530
+  VLOAD_64(v2, 0x3fee0a6d0b4ff74a, 0x3feb41ebb38f3ae2, 0xbfec5d9d36b2e38c,
+           0x3fd72d3826721e9c, 0x3fe14186558b96e0, 0xbfc07edbdd68bb68,
+           0xbfed4700c06849e8, 0xbfee02ee057e1390, 0xbfccf8cd5897f8a0,
+           0x3fba06943d0f8e20, 0x3fde9d5df4b22860, 0x3fe14340f23a8770,
+           0x3fe9283676baf718, 0x3f93f1da754635c0, 0xbfed34b234f8ec38,
+           0x3fd995a436ac6f1c);
+  //               0.4808082103120717,  0.7218925128932789, -0.9454618185734458,
+  //               0.7335258472548418,  0.9800819535502201, -0.6873536121819364,
+  //               -0.7090903925273744,  0.7813319828098306, 0.6810234154055235,
+  //               0.1176441554686278,  0.4929731878752270,  0.0942028280153233,
+  //               0.9496420237972776, -0.4549651855719854, -0.9663401540020158,
+  //               0.4114236885680320
+  VLOAD_64(v3, 0x3fdec58fccbc12a4, 0x3fe719be53c35314, 0xbfee413924cc77e4,
+           0x3fe7790b32975e1a, 0x3fef5cd4d43cbc4e, 0xbfe5fecd00a37bfa,
+           0xbfe6b0de55ba0314, 0x3fe900abee2f95f8, 0x3fe5caf19e1f4324,
+           0x3fbe1ded684da4d0, 0x3fdf8cdf69eea758, 0x3fb81dad31843b10,
+           0x3fee6377ab63bade, 0xbfdd1e264c366a78, 0xbfeeec422fc80224,
+           0x3fda54c405ccc2c0);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfmin.vv v1, v2, v3, v0.t");
+  //               0.0000000000000000,  0.7218925128932789,  0.0000000000000000,
+  //               0.3621349692771021,  0.0000000000000000, -0.6873536121819364,
+  //               0.0000000000000000, -0.9378576380992047,  0.0000000000000000,
+  //               0.1016628884386184,  0.0000000000000000,  0.0942028280153233,
+  //               0.0000000000000000, -0.4549651855719854,  0.0000000000000000,
+  //               0.3997583898469530
+  VCMP_U64(6, v1, 0x0, 0x3fe719be53c35314, 0x0, 0x3fd72d3826721e9c, 0x0,
+           0xbfe5fecd00a37bfa, 0x0, 0xbfee02ee057e1390, 0x0, 0x3fba06943d0f8e20,
+           0x0, 0x3fb81dad31843b10, 0x0, 0xbfdd1e264c366a78, 0x0,
+           0x3fd995a436ac6f1c);
+};
+
+// Simple random test with similar values (vector-scalar)
+void TEST_CASE3(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //                              0.4434
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0x3718);
+  //              -0.2537,  0.5449,  0.2070, -0.5752, -0.3008,  0.0165, -0.8447,
+  //              0.6279,  0.6802,  0.7300,  0.7720, -0.8525,  0.5264, -0.5249,
+  //              -0.9839,  0.4875
+  VLOAD_16(v2, 0xb40f, 0x385c, 0x32a0, 0xb89a, 0xb4d0, 0x2437, 0xbac2, 0x3906,
+           0x3971, 0x39d7, 0x3a2d, 0xbad2, 0x3836, 0xb833, 0xbbdf, 0x37cd);
+  asm volatile("vfmin.vf v1, v2, %[A]" ::[A] "f"(dscalar_16));
+  //              -0.2537,  0.4434,  0.2070, -0.5752, -0.3008,  0.0165, -0.8447,
+  //              0.4434,  0.4434,  0.4434,  0.4434, -0.8525,  0.4434, -0.5249,
+  //              -0.9839,  0.4434
+  VCMP_U16(7, v1, 0xb40f, 0x3718, 0x32a0, 0xb89a, 0xb4d0, 0x2437, 0xbac2,
+           0x3718, 0x3718, 0x3718, 0x3718, 0xbad2, 0x3718, 0xb833, 0xbbdf,
+           0x3718);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                               0.59499639
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0x3f1851af);
+  //              -0.94244474, -0.52559608, -0.72424960, -0.67824948,
+  //              0.22003150, -0.67564118, -0.90376341,  0.16465612,
+  //              -0.15494362, -0.01763406,  0.97777683, -0.91671157,
+  //              0.81712914, -0.10151604,  0.03442690, -0.14597759
+  VLOAD_32(v2, 0xbf71440f, 0xbf068d77, 0xbf39686c, 0xbf2da1c2, 0x3e614ff0,
+           0xbf2cf6d2, 0xbf675d0a, 0x3e289b9d, 0xbe1ea98a, 0xbc90754e,
+           0x3f7a4f95, 0xbf6aad9c, 0x3f512f60, 0xbdcfe7a4, 0x3d0d0338,
+           0xbe157b26);
+  asm volatile("vfmin.vf v1, v2, %[A]" ::[A] "f"(dscalar_32));
+  //              -0.94244474, -0.52559608, -0.72424960, -0.67824948,
+  //              0.22003150, -0.67564118, -0.90376341,  0.16465612,
+  //              -0.15494362, -0.01763406,  0.59499639, -0.91671157,
+  //              0.59499639, -0.10151604,  0.03442690, -0.14597759
+  VCMP_U32(8, v1, 0xbf71440f, 0xbf068d77, 0xbf39686c, 0xbf2da1c2, 0x3e614ff0,
+           0xbf2cf6d2, 0xbf675d0a, 0x3e289b9d, 0xbe1ea98a, 0xbc90754e,
+           0x3f1851af, 0xbf6aad9c, 0x3f1851af, 0xbdcfe7a4, 0x3d0d0338,
+           0xbe157b26);
+
+  VSET(16, e64, m1);
+  double dscalar_64;
+  //                                0.8631130564395617
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0x3feb9e9f45c51298);
+  //               -0.0203711476424431,  0.4824066080711997, 0.5516514149436702,
+  //               -0.0992829085793798,  0.7425996730256406, 0.3080149644930992,
+  //               -0.6753031265127754, -0.3309631180416657,
+  //               -0.7695072044924456, -0.6726760621514143,
+  //               -0.9995830020822822,  0.2485224245452053, 0.7025040357726613,
+  //               -0.6452676560401207,  0.5090044889036880,  0.0801949752856408
+  VLOAD_64(v2, 0xbf94dc2c93a00800, 0x3fdedfbff74290e0, 0x3fe1a720de3f34c0,
+           0xbfb96a9acd667320, 0x3fe7c36063b54b1e, 0x3fd3b68465cb4b28,
+           0xbfe59c154d684914, 0xbfd52e7fee0af3fc, 0xbfe89fcd92aa9b24,
+           0xbfe5868ff2f7c1a4, 0xbfeffc957df296c0, 0x3fcfcf9532df44b8,
+           0x3fe67ae9be5e7376, 0xbfe4a6085afb7c12, 0x3fe049c3c82b791e,
+           0x3fb487a86c27c560);
+  asm volatile("vfmin.vf v1, v2, %[A]" ::[A] "f"(dscalar_64));
+  //              -0.0203711476424431,  0.4824066080711997,  0.5516514149436702,
+  //              -0.0992829085793798,  0.7425996730256406,  0.3080149644930992,
+  //              -0.6753031265127754, -0.3309631180416657, -0.7695072044924456,
+  //              -0.6726760621514143, -0.9995830020822822,  0.2485224245452053,
+  //              0.7025040357726613, -0.6452676560401207,  0.5090044889036880,
+  //              0.0801949752856408
+  VCMP_U64(9, v1, 0xbf94dc2c93a00800, 0x3fdedfbff74290e0, 0x3fe1a720de3f34c0,
+           0xbfb96a9acd667320, 0x3fe7c36063b54b1e, 0x3fd3b68465cb4b28,
+           0xbfe59c154d684914, 0xbfd52e7fee0af3fc, 0xbfe89fcd92aa9b24,
+           0xbfe5868ff2f7c1a4, 0xbfeffc957df296c0, 0x3fcfcf9532df44b8,
+           0x3fe67ae9be5e7376, 0xbfe4a6085afb7c12, 0x3fe049c3c82b791e,
+           0x3fb487a86c27c560);
+};
+
+// Simple random test with similar values (vector-scalar) (masked)
+void TEST_CASE4(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //                              0.4434
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0x3718);
+  //               -0.2537,  0.5449,  0.2070, -0.5752, -0.3008,  0.0165,
+  //               -0.8447,  0.6279,  0.6802,  0.7300,  0.7720, -0.8525, 0.5264,
+  //               -0.5249, -0.9839,  0.4875
+  VLOAD_16(v2, 0xb40f, 0x385c, 0x32a0, 0xb89a, 0xb4d0, 0x2437, 0xbac2, 0x3906,
+           0x3971, 0x39d7, 0x3a2d, 0xbad2, 0x3836, 0xb833, 0xbbdf, 0x37cd);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfmin.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_16));
+  //                0.0000,  0.4434,  0.0000, -0.5752,  0.0000,  0.0165, 0.0000,
+  //                0.4434,  0.0000,  0.4434,  0.0000, -0.8525,  0.0000,
+  //                -0.5249,  0.0000,  0.4434
+  VCMP_U16(10, v1, 0x0, 0x3718, 0x0, 0xb89a, 0x0, 0x2437, 0x0, 0x3718, 0x0,
+           0x3718, 0x0, 0xbad2, 0x0, 0xb833, 0x0, 0x3718);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                               0.59499639
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0x3f1851af);
+  //               -0.94244474, -0.52559608, -0.72424960, -0.67824948,
+  //               0.22003150, -0.67564118, -0.90376341,  0.16465612,
+  //               -0.15494362, -0.01763406,  0.97777683, -0.91671157,
+  //               0.81712914, -0.10151604,  0.03442690, -0.14597759
+  VLOAD_32(v2, 0xbf71440f, 0xbf068d77, 0xbf39686c, 0xbf2da1c2, 0x3e614ff0,
+           0xbf2cf6d2, 0xbf675d0a, 0x3e289b9d, 0xbe1ea98a, 0xbc90754e,
+           0x3f7a4f95, 0xbf6aad9c, 0x3f512f60, 0xbdcfe7a4, 0x3d0d0338,
+           0xbe157b26);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfmin.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_32));
+  //                0.00000000, -0.52559608,  0.00000000, -0.67824948,
+  //                0.00000000, -0.67564118,  0.00000000,  0.16465612,
+  //                0.00000000, -0.01763406,  0.00000000, -0.91671157,
+  //                0.00000000, -0.10151604,  0.00000000, -0.14597759
+  VCMP_U32(11, v1, 0x0, 0xbf068d77, 0x0, 0xbf2da1c2, 0x0, 0xbf2cf6d2, 0x0,
+           0x3e289b9d, 0x0, 0xbc90754e, 0x0, 0xbf6aad9c, 0x0, 0xbdcfe7a4, 0x0,
+           0xbe157b26);
+
+  VSET(16, e64, m1);
+  double dscalar_64;
+  //                                0.8631130564395617
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0x3feb9e9f45c51298);
+  //                -0.0203711476424431,  0.4824066080711997,
+  //                0.5516514149436702, -0.0992829085793798, 0.7425996730256406,
+  //                0.3080149644930992, -0.6753031265127754,
+  //                -0.3309631180416657, -0.7695072044924456,
+  //                -0.6726760621514143, -0.9995830020822822,
+  //                0.2485224245452053,  0.7025040357726613,
+  //                -0.6452676560401207,  0.5090044889036880, 0.0801949752856408
+  VLOAD_64(v2, 0xbf94dc2c93a00800, 0x3fdedfbff74290e0, 0x3fe1a720de3f34c0,
+           0xbfb96a9acd667320, 0x3fe7c36063b54b1e, 0x3fd3b68465cb4b28,
+           0xbfe59c154d684914, 0xbfd52e7fee0af3fc, 0xbfe89fcd92aa9b24,
+           0xbfe5868ff2f7c1a4, 0xbfeffc957df296c0, 0x3fcfcf9532df44b8,
+           0x3fe67ae9be5e7376, 0xbfe4a6085afb7c12, 0x3fe049c3c82b791e,
+           0x3fb487a86c27c560);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfmin.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_64));
+  //                0.0000000000000000,  0.4824066080711997, 0.0000000000000000,
+  //                -0.0992829085793798,  0.0000000000000000,
+  //                0.3080149644930992,  0.0000000000000000,
+  //                -0.3309631180416657,  0.0000000000000000,
+  //                -0.6726760621514143,  0.0000000000000000,
+  //                0.2485224245452053,  0.0000000000000000,
+  //                -0.6452676560401207,  0.0000000000000000, 0.0801949752856408
+  VCMP_U64(12, v1, 0x0, 0x3fdedfbff74290e0, 0x0, 0xbfb96a9acd667320, 0x0,
+           0x3fd3b68465cb4b28, 0x0, 0xbfd52e7fee0af3fc, 0x0, 0xbfe5868ff2f7c1a4,
+           0x0, 0x3fcfcf9532df44b8, 0x0, 0xbfe4a6085afb7c12, 0x0,
+           0x3fb487a86c27c560);
+};
+
+int main(void) {
+  enable_vec();
+  enable_fp();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vfmsac.c b/apps/riscv-tests/isa/rv64uv/vfmsac.c
new file mode 100644
index 0000000..01e8ceb
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vfmsac.c
@@ -0,0 +1,454 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+// Simple random test with similar values
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  //               0.9175,  0.0740, -0.0362,  0.2961,  0.6226, -0.8032,  0.7749,
+  //               0.8188,  0.2019,  0.4885,  0.5669, -0.1743,  0.4404,  0.0618,
+  //               0.8252, -0.5947
+  VLOAD_16(v2, 0x3b57, 0x2cbc, 0xa8a3, 0x34bd, 0x38fb, 0xba6d, 0x3a33, 0x3a8d,
+           0x3276, 0x37d1, 0x3889, 0xb194, 0x370c, 0x2bea, 0x3a9a, 0xb8c2);
+  //               0.2812, -0.6733,  0.3289,  0.9609, -0.6841,  0.5488, -0.1401,
+  //               0.5591,  0.2759, -0.6973,  0.1418,  0.2389, -0.3308,  0.8867,
+  //               0.8936,  0.3611
+  VLOAD_16(v3, 0x3480, 0xb963, 0x3543, 0x3bb0, 0xb979, 0x3864, 0xb07c, 0x3879,
+           0x346a, 0xb994, 0x308a, 0x33a5, 0xb54b, 0x3b18, 0x3b26, 0x35c7);
+  //               0.4780, -0.1810,  0.2800,  0.7529,  0.6484, -0.9526,
+  //               0.5947,  1.0000, -0.1874,  0.2949, -0.4280,  0.6934,  0.5444,
+  //               0.8823, -0.8911,  0.7603
+  VLOAD_16(v1, 0x37a6, 0xb1cb, 0x347b, 0x3a06, 0x3930, 0xbb9f, 0x38c2, 0x3c00,
+           0xb1ff, 0x34b8, 0xb6d9, 0x398c, 0x385b, 0x3b0f, 0xbb21, 0x3a15);
+  asm volatile("vfmsac.vv v1, v2, v3");
+  //              -0.2200,  0.1312, -0.2920, -0.4683, -1.0742,  0.5117, -0.7031,
+  //              -0.5420,  0.2430, -0.6357,  0.5083, -0.7349, -0.6904, -0.8276,
+  //              1.6289, -0.9751
+  VCMP_U16(1, v1, 0xb30a, 0x3033, 0xb4ac, 0xb77e, 0xbc4c, 0x3818, 0xb9a0,
+           0xb856, 0x33c7, 0xb916, 0x3811, 0xb9e1, 0xb985, 0xba9f, 0x3e84,
+           0xbbcd);
+
+  VSET(16, e32, m1);
+  //              -0.90310860,  0.30282700,  0.54854167, -0.38732994,
+  //              0.92121714,  0.99595129, -0.10263380,  0.83759040,
+  //              -0.23468767,  0.03914077, -0.46234205,  0.38326120,
+  //              0.36417511, -0.50103557,  0.36991179,  0.44718841
+  VLOAD_32(v2, 0xbf673220, 0x3e9b0c24, 0x3f0c6d3a, 0xbec6501c, 0x3f6bd4e3,
+           0x3f7ef6aa, 0xbdd231ab, 0x3f566c53, 0xbe7051f7, 0x3d205212,
+           0xbeecb819, 0x3ec43ad0, 0x3eba7529, 0xbf0043de, 0x3ebd6514,
+           0x3ee4f5e1);
+  //               0.84989786, -0.04543342, -0.74596256, -0.30687407,
+  //               -0.30795863,  0.57084304,  0.51653886, -0.97366458,
+  //               0.49300706,  0.62932760,  0.45846274, -0.73850167,
+  //               -0.42686453, -0.31419462, -0.47245970, -0.87721694
+  VLOAD_32(v3, 0x3f5992e8, 0xbd3a1866, 0xbf3ef767, 0xbe9d1e99, 0xbe9dacc1,
+           0x3f1222c5, 0x3f043be4, 0xbf794215, 0x3efc6b6c, 0x3f211b9d,
+           0x3eeabba1, 0xbf3d0e72, 0xbeda8dfd, 0xbea0de1e, 0xbef1e63d,
+           0xbf60914a);
+  //              -0.76813585,  0.87161541, -0.67958647, -0.98584491,
+  //              0.12284227, -0.04006640, -0.93113720, -0.93526161,
+  //              -0.27461481,  0.64110506,  0.61687475, -0.43741968,
+  //              0.70502371,  0.37014356, -0.98105848,  0.77993429
+  VLOAD_32(v1, 0xbf44a48d, 0x3f5f2230, 0xbf2df961, 0xbf7c6055, 0x3dfb94bb,
+           0xbd241caa, 0xbf6e5f02, 0xbf6f6d4e, 0xbe8c9a50, 0x3f241f76,
+           0x3f1deb81, 0xbedff579, 0x3f347c6f, 0x3ebd8375, 0xbf7b26a6,
+           0x3f47a9c6);
+  asm volatile("vfmsac.vv v1, v2, v3");
+  //               0.00058579, -0.88537389,  0.27039492,  1.10470641,
+  //               -0.40653905,  0.60859829,  0.87812287,  0.11972952,
+  //               0.15891212, -0.61647266, -0.82884133,  0.15438065,
+  //               -0.86047715, -0.21272089,  0.80629003, -1.17221546
+  VCMP_U32(2, v1, 0x3a198f11, 0xbf62a7dd, 0x3e8a7134, 0x3f8d6705, 0xbed025e3,
+           0x3f1bcd19, 0x3f60cca9, 0x3df534be, 0x3e22b9dd, 0xbf1dd127,
+           0xbf542ef3, 0x3e1e15f6, 0xbf5c483b, 0xbe59d381, 0x3f4e6907,
+           0xbf960b29);
+
+  VSET(16, e64, m1);
+  //               0.0971325394189311,  0.6403859199401045,  0.3478142243141771,
+  //               -0.4702414117546168,  0.8862438155310881, 0.6157878617136987,
+  //               -0.9954501284062294, -0.2761157935600853,
+  //               -0.7189549700888722, -0.2302799669824283, 0.0093666993515229,
+  //               0.9188774299961215, -0.4297410504980956,  0.2729294776457381,
+  //               -0.1419575372981836, -0.8472908703054822
+  VLOAD_64(v2, 0x3fb8ddad982e8680, 0x3fe47e0a9cdec59e, 0x3fd6429697a0d4f8,
+           0xbfde186f6f2d8030, 0x3fec5c1bfd7f9ffe, 0x3fe3b488beeab100,
+           0xbfefdaba3a49b85e, 0xbfd1abe193cffa54, 0xbfe701adda7a81f6,
+           0xbfcd79d05f8e86d0, 0x3f832ed91b170d00, 0x3fed6771a3dbb538,
+           0xbfdb80e09b68d514, 0x3fd177ad33269468, 0xbfc22baa220ee628,
+           0xbfeb1d01be452a62);
+  //              -0.2416734667201210, -0.2737616510555549,  0.6084509432766920,
+  //              -0.4000545529138850,  0.5985258122916897, -0.9559409603601607,
+  //              0.5010970610326939,  0.5772808284477746, -0.4551243154247406,
+  //              0.6584804564152213,  0.6542532086910551, -0.2215058802905889,
+  //              0.3203723346938081,  0.0696368102348055,  0.8882580549203218,
+  //              0.7725843936650791
+  VLOAD_64(v3, 0xbfceef27f9efdac8, 0xbfd1854f968baf44, 0x3fe3786e1cd2fff2,
+           0xbfd99a7e695862ec, 0x3fe3271f9ab3593a, 0xbfee97117f34eb4c,
+           0x3fe008fcb4283a76, 0x3fe27915a4d94fb2, 0xbfdd20c1bc974608,
+           0x3fe512459b2b7912, 0x3fe4efa46cd43256, 0xbfcc5a4dffdc2170,
+           0x3fd480faf7036588, 0x3fb1d3b7ce8e6640, 0x3fec6c9c280952c6,
+           0x3fe8b902e80620ce);
+  //              -0.8982912058335177,  0.5582779858188844, -0.3988318240568800,
+  //              0.0267896464795028,  0.8241806039831361,  0.2839220639224551,
+  //              -0.4781090814672235, -0.1240154287362147,  0.4586341020154134,
+  //              -0.6132901056934972,  0.1207753636997857,  0.4420874266235846,
+  //              0.8256868703569773,  0.0642541522901756, -0.3012484644971416,
+  //              0.7323810741358745
+  VLOAD_64(v1, 0xbfecbecd32eadc10, 0x3fe1dd69cb65674e, 0xbfd98675ea3b69b0,
+           0x3f9b6ebebe00e300, 0x3fea5fb000835cf4, 0x3fd22bc772ca399c,
+           0xbfde9956d534a0f8, 0xbfbfbf79a29f1810, 0x3fdd5a42d93f2348,
+           0xbfe3a012925d3f1c, 0x3fbeeb225d40ca30, 0x3fdc4b290fd48cd4,
+           0x3fea6c06df1d6f14, 0x3fb072f5cab7f020, 0xbfd347a7a3bf1174,
+           0x3fe76faa6f33ef10);
+  asm volatile("vfmsac.vv v1, v2, v3");
+  //               0.8748168483008159, -0.7335910925744179,  0.6104597169258920,
+  //               0.1613325712615846, -0.2937408044039052, -0.8725789038271781,
+  //               -0.0207080522817558, -0.0353809253176660,
+  //               -0.1314202134325006,  0.4616552479316257,
+  //               -0.1146471705942074, -0.6456241806340295,
+  //               -0.9633640140188219, -0.0452482140478748, 0.1751535385353780,
+  //               -1.3869847774287927
+  VCMP_U64(3, v1, 0x3febfe7fe72e2334, 0xbfe7799406e7cf1f, 0x3fe388e2d0f71ba3,
+           0x3fc4a68bb2ac8e62, 0xbfd2cca63b1a97a5, 0xbfebec2a97e3c096,
+           0xbf95347ddd418906, 0xbfa21d72da487f01, 0xbfc0d260a75ceb46,
+           0x3fdd8bc273f9289e, 0xbfbd59845847f323, 0xbfe4a8f40aaa8efa,
+           0xbfeed3e0c4cb54ff, 0xbfa72ac61f1378a7, 0x3fc66b6e5fe4e141,
+           0xbff63116f331b43d);
+};
+
+// Simple random test with similar values (masked)
+// The numbers are the same of TEST_CASE1
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  //               0.9175,  0.0740, -0.0362,  0.2961,  0.6226, -0.8032,  0.7749,
+  //               0.8188,  0.2019,  0.4885,  0.5669, -0.1743,  0.4404,  0.0618,
+  //               0.8252, -0.5947
+  VLOAD_16(v2, 0x3b57, 0x2cbc, 0xa8a3, 0x34bd, 0x38fb, 0xba6d, 0x3a33, 0x3a8d,
+           0x3276, 0x37d1, 0x3889, 0xb194, 0x370c, 0x2bea, 0x3a9a, 0xb8c2);
+  //               0.2812, -0.6733,  0.3289,  0.9609, -0.6841,  0.5488, -0.1401,
+  //               0.5591,  0.2759, -0.6973,  0.1418,  0.2389, -0.3308,  0.8867,
+  //               0.8936,  0.3611
+  VLOAD_16(v3, 0x3480, 0xb963, 0x3543, 0x3bb0, 0xb979, 0x3864, 0xb07c, 0x3879,
+           0x346a, 0xb994, 0x308a, 0x33a5, 0xb54b, 0x3b18, 0x3b26, 0x35c7);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //               0.4780, -0.1810,  0.2800,  0.7529,  0.6484, -0.9526,
+  //               0.5947,  1.0000, -0.1874,  0.2949, -0.4280,  0.6934,  0.5444,
+  //               0.8823, -0.8911,  0.7603
+  VLOAD_16(v1, 0x37a6, 0xb1cb, 0x347b, 0x3a06, 0x3930, 0xbb9f, 0x38c2, 0x3c00,
+           0xb1ff, 0x34b8, 0xb6d9, 0x398c, 0x385b, 0x3b0f, 0xbb21, 0x3a15);
+  asm volatile("vfmsac.vv v1, v2, v3, v0.t");
+  //               0.4780,  0.1312,  0.2800, -0.4683,  0.6484,  0.5117,  0.5947,
+  //               -0.5420, -0.1874, -0.6357, -0.4280, -0.7349,  0.5444,
+  //               -0.8276, -0.8911, -0.9751
+  VCMP_U16(4, v1, 0x37a6, 0x3033, 0x347b, 0xb77e, 0x3930, 0x3818, 0x38c2,
+           0xb856, 0xb1ff, 0xb916, 0xb6d9, 0xb9e1, 0x385b, 0xba9f, 0xbb21,
+           0xbbcd);
+
+  VSET(16, e32, m1);
+  //              -0.90310860,  0.30282700,  0.54854167, -0.38732994,
+  //              0.92121714,  0.99595129, -0.10263380,  0.83759040,
+  //              -0.23468767,  0.03914077, -0.46234205,  0.38326120,
+  //              0.36417511, -0.50103557,  0.36991179,  0.44718841
+  VLOAD_32(v2, 0xbf673220, 0x3e9b0c24, 0x3f0c6d3a, 0xbec6501c, 0x3f6bd4e3,
+           0x3f7ef6aa, 0xbdd231ab, 0x3f566c53, 0xbe7051f7, 0x3d205212,
+           0xbeecb819, 0x3ec43ad0, 0x3eba7529, 0xbf0043de, 0x3ebd6514,
+           0x3ee4f5e1);
+  //               0.84989786, -0.04543342, -0.74596256, -0.30687407,
+  //               -0.30795863,  0.57084304,  0.51653886, -0.97366458,
+  //               0.49300706,  0.62932760,  0.45846274, -0.73850167,
+  //               -0.42686453, -0.31419462, -0.47245970, -0.87721694
+  VLOAD_32(v3, 0x3f5992e8, 0xbd3a1866, 0xbf3ef767, 0xbe9d1e99, 0xbe9dacc1,
+           0x3f1222c5, 0x3f043be4, 0xbf794215, 0x3efc6b6c, 0x3f211b9d,
+           0x3eeabba1, 0xbf3d0e72, 0xbeda8dfd, 0xbea0de1e, 0xbef1e63d,
+           0xbf60914a);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //              -0.76813585,  0.87161541, -0.67958647, -0.98584491,
+  //              0.12284227, -0.04006640, -0.93113720, -0.93526161,
+  //              -0.27461481,  0.64110506,  0.61687475, -0.43741968,
+  //              0.70502371,  0.37014356, -0.98105848,  0.77993429
+  VLOAD_32(v1, 0xbf44a48d, 0x3f5f2230, 0xbf2df961, 0xbf7c6055, 0x3dfb94bb,
+           0xbd241caa, 0xbf6e5f02, 0xbf6f6d4e, 0xbe8c9a50, 0x3f241f76,
+           0x3f1deb81, 0xbedff579, 0x3f347c6f, 0x3ebd8375, 0xbf7b26a6,
+           0x3f47a9c6);
+  asm volatile("vfmsac.vv v1, v2, v3, v0.t");
+  //              -0.76813585, -0.88537389, -0.67958647,  1.10470641,
+  //              0.12284227,  0.60859829, -0.93113720,  0.11972952,
+  //              -0.27461481, -0.61647266,  0.61687475,  0.15438065,
+  //              0.70502371, -0.21272089, -0.98105848, -1.17221546
+  VCMP_U32(5, v1, 0xbf44a48d, 0xbf62a7dd, 0xbf2df961, 0x3f8d6705, 0x3dfb94bb,
+           0x3f1bcd19, 0xbf6e5f02, 0x3df534be, 0xbe8c9a50, 0xbf1dd127,
+           0x3f1deb81, 0x3e1e15f6, 0x3f347c6f, 0xbe59d381, 0xbf7b26a6,
+           0xbf960b29);
+
+  VSET(16, e64, m1);
+  //               0.0971325394189311,  0.6403859199401045,  0.3478142243141771,
+  //               -0.4702414117546168,  0.8862438155310881, 0.6157878617136987,
+  //               -0.9954501284062294, -0.2761157935600853,
+  //               -0.7189549700888722, -0.2302799669824283, 0.0093666993515229,
+  //               0.9188774299961215, -0.4297410504980956,  0.2729294776457381,
+  //               -0.1419575372981836, -0.8472908703054822
+  VLOAD_64(v2, 0x3fb8ddad982e8680, 0x3fe47e0a9cdec59e, 0x3fd6429697a0d4f8,
+           0xbfde186f6f2d8030, 0x3fec5c1bfd7f9ffe, 0x3fe3b488beeab100,
+           0xbfefdaba3a49b85e, 0xbfd1abe193cffa54, 0xbfe701adda7a81f6,
+           0xbfcd79d05f8e86d0, 0x3f832ed91b170d00, 0x3fed6771a3dbb538,
+           0xbfdb80e09b68d514, 0x3fd177ad33269468, 0xbfc22baa220ee628,
+           0xbfeb1d01be452a62);
+  //              -0.2416734667201210, -0.2737616510555549,  0.6084509432766920,
+  //              -0.4000545529138850,  0.5985258122916897, -0.9559409603601607,
+  //              0.5010970610326939,  0.5772808284477746, -0.4551243154247406,
+  //              0.6584804564152213,  0.6542532086910551, -0.2215058802905889,
+  //              0.3203723346938081,  0.0696368102348055,  0.8882580549203218,
+  //              0.7725843936650791
+  VLOAD_64(v3, 0xbfceef27f9efdac8, 0xbfd1854f968baf44, 0x3fe3786e1cd2fff2,
+           0xbfd99a7e695862ec, 0x3fe3271f9ab3593a, 0xbfee97117f34eb4c,
+           0x3fe008fcb4283a76, 0x3fe27915a4d94fb2, 0xbfdd20c1bc974608,
+           0x3fe512459b2b7912, 0x3fe4efa46cd43256, 0xbfcc5a4dffdc2170,
+           0x3fd480faf7036588, 0x3fb1d3b7ce8e6640, 0x3fec6c9c280952c6,
+           0x3fe8b902e80620ce);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //              -0.8982912058335177,  0.5582779858188844, -0.3988318240568800,
+  //              0.0267896464795028,  0.8241806039831361,  0.2839220639224551,
+  //              -0.4781090814672235, -0.1240154287362147,  0.4586341020154134,
+  //              -0.6132901056934972,  0.1207753636997857,  0.4420874266235846,
+  //              0.8256868703569773,  0.0642541522901756, -0.3012484644971416,
+  //              0.7323810741358745
+  VLOAD_64(v1, 0xbfecbecd32eadc10, 0x3fe1dd69cb65674e, 0xbfd98675ea3b69b0,
+           0x3f9b6ebebe00e300, 0x3fea5fb000835cf4, 0x3fd22bc772ca399c,
+           0xbfde9956d534a0f8, 0xbfbfbf79a29f1810, 0x3fdd5a42d93f2348,
+           0xbfe3a012925d3f1c, 0x3fbeeb225d40ca30, 0x3fdc4b290fd48cd4,
+           0x3fea6c06df1d6f14, 0x3fb072f5cab7f020, 0xbfd347a7a3bf1174,
+           0x3fe76faa6f33ef10);
+  asm volatile("vfmsac.vv v1, v2, v3, v0.t");
+  //              -0.8982912058335177, -0.7335910925744179, -0.3988318240568800,
+  //              0.1613325712615846,  0.8241806039831361, -0.8725789038271781,
+  //              -0.4781090814672235, -0.0353809253176660,  0.4586341020154134,
+  //              0.4616552479316257,  0.1207753636997857, -0.6456241806340295,
+  //              0.8256868703569773, -0.0452482140478748, -0.3012484644971416,
+  //              -1.3869847774287927
+  VCMP_U64(6, v1, 0xbfecbecd32eadc10, 0xbfe7799406e7cf1f, 0xbfd98675ea3b69b0,
+           0x3fc4a68bb2ac8e62, 0x3fea5fb000835cf4, 0xbfebec2a97e3c096,
+           0xbfde9956d534a0f8, 0xbfa21d72da487f01, 0x3fdd5a42d93f2348,
+           0x3fdd8bc273f9289e, 0x3fbeeb225d40ca30, 0xbfe4a8f40aaa8efa,
+           0x3fea6c06df1d6f14, 0xbfa72ac61f1378a7, 0xbfd347a7a3bf1174,
+           0xbff63116f331b43d);
+};
+
+// Simple random test with similar values (vector-scalar)
+void TEST_CASE3(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //                              0.3911
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0x3642);
+  //               0.3203, -0.8521,  0.0744,  0.9370,  0.2056,  0.2866, -0.8379,
+  //               -0.2668, -0.0878, -0.5703,  0.1272, -0.6606, -0.6919, 0.9189,
+  //               0.6245,  0.9932
+  VLOAD_16(v2, 0x3520, 0xbad1, 0x2cc3, 0x3b7f, 0x3294, 0x3496, 0xbab4, 0xb445,
+           0xad9f, 0xb890, 0x3012, 0xb949, 0xb989, 0x3b5a, 0x38ff, 0x3bf2);
+  //               0.8706,  0.4900, -0.9497,  0.4727, -0.7168,  0.0167, -0.3606,
+  //               -0.1565, -0.5142,  0.8271, -0.4783,  0.6318,  0.0842,
+  //               -0.6646,  0.1454, -0.3020
+  VLOAD_16(v1, 0x3af7, 0x37d7, 0xbb99, 0x3790, 0xb9bc, 0x2445, 0xb5c5, 0xb102,
+           0xb81d, 0x3a9e, 0xb7a7, 0x390e, 0x2d63, 0xb951, 0x30a7, 0xb4d5);
+  asm volatile("vfmsac.vf v1, %[A], v2" ::[A] "f"(dscalar_16));
+  //              -0.7451, -0.8232,  0.9790, -0.1062,  0.7974,  0.0955,  0.0330,
+  //              0.0521,  0.4797, -1.0498,  0.5278, -0.8901, -0.3547,  1.0234,
+  //              0.0989,  0.6904
+  VCMP_U16(7, v1, 0xb9f6, 0xba96, 0x3bd5, 0xaecc, 0x3a61, 0x2e1b, 0x2836,
+           0x2aac, 0x37ad, 0xbc33, 0x3839, 0xbb1f, 0xb5ad, 0x3c19, 0x2e54,
+           0x3986);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                              -0.39704049
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0xbecb48e4);
+  //               0.43844241,  0.13734208,  0.15601240,  0.48965997,
+  //               -0.41457745, -0.69918746,  0.38535324,  0.83301985,
+  //               0.79336989, -0.03326649, -0.85931808,  0.92554229,
+  //               -0.77742523,  0.47821125, -0.53653014, -0.32442030
+  VLOAD_32(v2, 0x3ee07b86, 0x3e0ca367, 0x3e1fc1b7, 0x3efab4b6, 0xbed4437f,
+           0xbf32fdf3, 0x3ec54d05, 0x3f5540ca, 0x3f4b1a4a, 0xbd084272,
+           0xbf5bfc45, 0x3f6cf057, 0xbf470557, 0x3ef4d81b, 0xbf095a0a,
+           0xbea61a6b);
+  //              -0.73119336,  0.87333083, -0.16325396, -0.30275631,
+  //              0.34779423,  0.22721651,  0.47497734, -0.58483958,
+  //              -0.24916913,  0.13750601, -0.99799657,  0.66137350,
+  //              0.58565408,  0.68887448, -0.74538875,  0.99311894
+  VLOAD_32(v1, 0xbf3b2f7d, 0x3f5f929c, 0xbe272c0c, 0xbe9b02e0, 0x3eb21216,
+           0x3e68ab72, 0x3ef3303b, 0xbf15b80c, 0xbe7f2631, 0x3e0cce60,
+           0xbf7f7cb4, 0x3f294fc6, 0x3f15ed6d, 0x3f305a14, 0xbf3ed1cc,
+           0x3f7e3d0b);
+  asm volatile("vfmsac.vf v1, %[A], v2" ::[A] "f"(dscalar_32));
+  //               0.55711401, -0.92786121,  0.10131072,  0.10834149,
+  //               -0.18319020,  0.05038923, -0.62797821,  0.25409698,
+  //               -0.06583084, -0.12429786,  1.33918071, -1.02885127,
+  //               -0.27698478, -0.87874371,  0.95841295, -0.86431098
+  VCMP_U32(8, v1, 0x3f0e9f06, 0xbf6d8850, 0x3dcf7bff, 0x3ddde223, 0xbe3b9636,
+           0x3d4e64ec, 0xbf20c32e, 0x3e821900, 0xbd86d252, 0xbdfe8fe1,
+           0x3fab6a45, 0xbf83b166, 0xbe8dd0f3, 0xbf60f559, 0x3f755a8d,
+           0xbf5d437b);
+
+  VSET(16, e64, m1);
+  double dscalar_64;
+  //                                0.0070730785066928
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0x3f7cf8a90de48000);
+  //               -0.3542445595658672,  0.5861662785402695, 0.5713440701195280,
+  //               0.2841717566030781,  0.4022451154567073, -0.9804628417449213,
+  //               -0.9703836833708208,  0.2288593539727362, 0.1806576644288407,
+  //               0.4892172254017777,  0.9508074316559227, -0.9022151172016701,
+  //               -0.7929839752648156,  0.5513143449560454, 0.4823446191982377,
+  //               -0.7486658065787619
+  VLOAD_64(v2, 0xbfd6abf15f87c3c4, 0x3fe2c1dfc88b26c8, 0x3fe248735bfda932,
+           0x3fd22fdebc43a768, 0x3fd9be624bf72ff4, 0xbfef5ff39c079aea,
+           0xbfef0d621514ca4c, 0x3fcd4b43685929d8, 0x3fc71fca543f2eb8,
+           0x3fdf4f55c3ef6448, 0x3fee6d03b4f830b0, 0xbfecdef23ccad0bc,
+           0xbfe9601fee00766c, 0x3fe1a45dfb2cdc2e, 0x3fdedebbf736e98c,
+           0xbfe7f511fe5c74b0);
+  //               -0.7603855538897846, -0.0491604902215765,
+  //               -0.3714656077097227, -0.6096204185796581,
+  //               -0.2818689596683441,  0.3527700521309320, 0.1176602936422064,
+  //               -0.2049443830034134, -0.6926950556538125, 0.7269529331298494,
+  //               -0.2107692441818434,  0.1746722346734710,
+  //               -0.5298547863982788,  0.2397543330794352,
+  //               -0.8347981409736787, -0.6198539479673024
+  VLOAD_64(v1, 0xbfe8551415c9d6cc, 0xbfa92b9053839560, 0xbfd7c617af2cedf8,
+           0xbfe38202ae18c034, 0xbfd20a241ae21e00, 0x3fd693c8d73a46c0,
+           0x3fbe1efc293b2500, 0xbfca3b9e173fd0c8, 0xbfe62a8ed24449ee,
+           0x3fe74332cc30c46e, 0xbfcafa7c9161bf78, 0x3fc65ba8e7b88cc0,
+           0xbfe0f4920666b5a4, 0x3fceb0451dd34270, 0xbfeab6aa9747cb24,
+           0xbfe3d5d7f25a1d14);
+  asm volatile("vfmsac.vf v1, %[A], v2" ::[A] "f"(dscalar_64));
+  //               0.7578799543094064,  0.0533064903276678,  0.3755067691720115,
+  //               0.6116303877234964,  0.2847140709489031, -0.3597049427834890,
+  //               -0.1245238936163020,  0.2065631231810536, 0.6939728614971534,
+  //               -0.7234926612877562,  0.2174943797906927,
+  //               -0.1810536730273635,  0.5242459484866814,
+  //               -0.2358548434356951,  0.8382098023325486,  0.6145585759420944
+  VCMP_U64(9, v1, 0x3fe8408d7641b126, 0x3fab4afd013e6639, 0x3fd8084d8b414e68,
+           0x3fe39279e4106415, 0x3fd238c15ddbf0a4, 0xbfd70567e15dbc9b,
+           0xbfbfe0cc42a710ce, 0x3fca70a9114fa5b7, 0x3fe63506930e2352,
+           0xbfe726da14e40fb7, 0x3fcbd6db1821e5e6, 0xbfc72cc44a3c91ef,
+           0x3fe0c69f7079f20d, 0xbfce307dd3946ada, 0x3fead29d5d068eb6,
+           0x3fe3aa76bf24b95e);
+};
+
+// Simple random test with similar values (vector-scalar) (masked)
+void TEST_CASE4(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //                              0.3911
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0x3642);
+  //                0.3203, -0.8521,  0.0744,  0.9370,  0.2056,  0.2866,
+  //                -0.8379, -0.2668, -0.0878, -0.5703,  0.1272, -0.6606,
+  //                -0.6919,  0.9189,  0.6245,  0.9932
+  VLOAD_16(v2, 0x3520, 0xbad1, 0x2cc3, 0x3b7f, 0x3294, 0x3496, 0xbab4, 0xb445,
+           0xad9f, 0xb890, 0x3012, 0xb949, 0xb989, 0x3b5a, 0x38ff, 0x3bf2);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //                0.8706,  0.4900, -0.9497,  0.4727, -0.7168,  0.0167,
+  //                -0.3606, -0.1565, -0.5142,  0.8271, -0.4783,  0.6318,
+  //                0.0842, -0.6646,  0.1454, -0.3020
+  VLOAD_16(v1, 0x3af7, 0x37d7, 0xbb99, 0x3790, 0xb9bc, 0x2445, 0xb5c5, 0xb102,
+           0xb81d, 0x3a9e, 0xb7a7, 0x390e, 0x2d63, 0xb951, 0x30a7, 0xb4d5);
+  asm volatile("vfmsac.vf v1, %[A], v2, v0.t" ::[A] "f"(dscalar_16));
+  //                0.8706, -0.8232, -0.9497, -0.1062, -0.7168,  0.0955,
+  //                -0.3606,  0.0521, -0.5142, -1.0498, -0.4783, -0.8901,
+  //                0.0842,  1.0234,  0.1454,  0.6904
+  VCMP_U16(10, v1, 0x3af7, 0xba96, 0xbb99, 0xaecc, 0xb9bc, 0x2e1b, 0xb5c5,
+           0x2aac, 0xb81d, 0xbc33, 0xb7a7, 0xbb1f, 0x2d63, 0x3c19, 0x30a7,
+           0x3986);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                              -0.39704049
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0xbecb48e4);
+  //                0.43844241,  0.13734208,  0.15601240,  0.48965997,
+  //                -0.41457745, -0.69918746,  0.38535324,  0.83301985,
+  //                0.79336989, -0.03326649, -0.85931808,  0.92554229,
+  //                -0.77742523,  0.47821125, -0.53653014, -0.32442030
+  VLOAD_32(v2, 0x3ee07b86, 0x3e0ca367, 0x3e1fc1b7, 0x3efab4b6, 0xbed4437f,
+           0xbf32fdf3, 0x3ec54d05, 0x3f5540ca, 0x3f4b1a4a, 0xbd084272,
+           0xbf5bfc45, 0x3f6cf057, 0xbf470557, 0x3ef4d81b, 0xbf095a0a,
+           0xbea61a6b);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //               -0.73119336,  0.87333083, -0.16325396, -0.30275631,
+  //               0.34779423,  0.22721651,  0.47497734, -0.58483958,
+  //               -0.24916913,  0.13750601, -0.99799657,  0.66137350,
+  //               0.58565408,  0.68887448, -0.74538875,  0.99311894
+  VLOAD_32(v1, 0xbf3b2f7d, 0x3f5f929c, 0xbe272c0c, 0xbe9b02e0, 0x3eb21216,
+           0x3e68ab72, 0x3ef3303b, 0xbf15b80c, 0xbe7f2631, 0x3e0cce60,
+           0xbf7f7cb4, 0x3f294fc6, 0x3f15ed6d, 0x3f305a14, 0xbf3ed1cc,
+           0x3f7e3d0b);
+  asm volatile("vfmsac.vf v1, %[A], v2, v0.t" ::[A] "f"(dscalar_32));
+  //               -0.73119336, -0.92786121, -0.16325396,  0.10834149,
+  //               0.34779423,  0.05038923,  0.47497734,  0.25409698,
+  //               -0.24916913, -0.12429786, -0.99799657, -1.02885127,
+  //               0.58565408, -0.87874371, -0.74538875, -0.86431098
+  VCMP_U32(11, v1, 0xbf3b2f7d, 0xbf6d8850, 0xbe272c0c, 0x3ddde223, 0x3eb21216,
+           0x3d4e64ec, 0x3ef3303b, 0x3e821900, 0xbe7f2631, 0xbdfe8fe1,
+           0xbf7f7cb4, 0xbf83b166, 0x3f15ed6d, 0xbf60f559, 0xbf3ed1cc,
+           0xbf5d437b);
+
+  VSET(16, e64, m1);
+  double dscalar_64;
+  //                                0.0070730785066928
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0x3f7cf8a90de48000);
+  //                -0.3542445595658672,  0.5861662785402695,
+  //                0.5713440701195280,  0.2841717566030781, 0.4022451154567073,
+  //                -0.9804628417449213, -0.9703836833708208,
+  //                0.2288593539727362,  0.1806576644288407, 0.4892172254017777,
+  //                0.9508074316559227, -0.9022151172016701,
+  //                -0.7929839752648156,  0.5513143449560454,
+  //                0.4823446191982377, -0.7486658065787619
+  VLOAD_64(v2, 0xbfd6abf15f87c3c4, 0x3fe2c1dfc88b26c8, 0x3fe248735bfda932,
+           0x3fd22fdebc43a768, 0x3fd9be624bf72ff4, 0xbfef5ff39c079aea,
+           0xbfef0d621514ca4c, 0x3fcd4b43685929d8, 0x3fc71fca543f2eb8,
+           0x3fdf4f55c3ef6448, 0x3fee6d03b4f830b0, 0xbfecdef23ccad0bc,
+           0xbfe9601fee00766c, 0x3fe1a45dfb2cdc2e, 0x3fdedebbf736e98c,
+           0xbfe7f511fe5c74b0);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //                -0.7603855538897846, -0.0491604902215765,
+  //                -0.3714656077097227, -0.6096204185796581,
+  //                -0.2818689596683441,  0.3527700521309320,
+  //                0.1176602936422064, -0.2049443830034134,
+  //                -0.6926950556538125,  0.7269529331298494,
+  //                -0.2107692441818434,  0.1746722346734710,
+  //                -0.5298547863982788,  0.2397543330794352,
+  //                -0.8347981409736787, -0.6198539479673024
+  VLOAD_64(v1, 0xbfe8551415c9d6cc, 0xbfa92b9053839560, 0xbfd7c617af2cedf8,
+           0xbfe38202ae18c034, 0xbfd20a241ae21e00, 0x3fd693c8d73a46c0,
+           0x3fbe1efc293b2500, 0xbfca3b9e173fd0c8, 0xbfe62a8ed24449ee,
+           0x3fe74332cc30c46e, 0xbfcafa7c9161bf78, 0x3fc65ba8e7b88cc0,
+           0xbfe0f4920666b5a4, 0x3fceb0451dd34270, 0xbfeab6aa9747cb24,
+           0xbfe3d5d7f25a1d14);
+  asm volatile("vfmsac.vf v1, %[A], v2, v0.t" ::[A] "f"(dscalar_64));
+  //               -0.7603855538897846,  0.0533064903276678,
+  //               -0.3714656077097227,  0.6116303877234964,
+  //               -0.2818689596683441, -0.3597049427834890, 0.1176602936422064,
+  //               0.2065631231810536, -0.6926950556538125, -0.7234926612877562,
+  //               -0.2107692441818434, -0.1810536730273635,
+  //               -0.5298547863982788, -0.2358548434356951,
+  //               -0.8347981409736787,  0.6145585759420944
+  VCMP_U64(12, v1, 0xbfe8551415c9d6cc, 0x3fab4afd013e6639, 0xbfd7c617af2cedf8,
+           0x3fe39279e4106415, 0xbfd20a241ae21e00, 0xbfd70567e15dbc9b,
+           0x3fbe1efc293b2500, 0x3fca70a9114fa5b7, 0xbfe62a8ed24449ee,
+           0xbfe726da14e40fb7, 0xbfcafa7c9161bf78, 0xbfc72cc44a3c91ef,
+           0xbfe0f4920666b5a4, 0xbfce307dd3946ada, 0xbfeab6aa9747cb24,
+           0x3fe3aa76bf24b95e);
+};
+
+int main(void) {
+  enable_vec();
+  enable_fp();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vfmsub.c b/apps/riscv-tests/isa/rv64uv/vfmsub.c
new file mode 100644
index 0000000..bbe5f92
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vfmsub.c
@@ -0,0 +1,453 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+// Simple random test with similar values
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  //               0.6821,  0.7749,  0.0299,  0.0299, -0.5410, -0.1865,  0.1885,
+  //               0.0228, -0.5410,  0.1902, -0.9160, -0.3511, -0.9287, -0.9961,
+  //               -0.6509, -0.3940
+  VLOAD_16(v2, 0x3975, 0x3a33, 0x27a5, 0x27a5, 0xb854, 0xb1f8, 0x3208, 0x25d8,
+           0xb854, 0x3216, 0xbb54, 0xb59e, 0xbb6e, 0xbbf8, 0xb935, 0xb64e);
+  //              -0.9048,  0.1698,  0.2411,  0.2411, -0.6147,  0.9580,  0.5117,
+  //              0.8330, -0.6147,  0.5591,  0.7031, -0.1556,  0.2397,  0.8154,
+  //              0.1646,  0.2693
+  VLOAD_16(v3, 0xbb3d, 0x316f, 0x33b7, 0x33b7, 0xb8eb, 0x3baa, 0x3818, 0x3aaa,
+           0xb8eb, 0x3879, 0x39a0, 0xb0fb, 0x33ac, 0x3a86, 0x3144, 0x344f);
+  //              -0.2292,  0.7578, -0.7427, -0.7427,  0.1119,  0.2939, -0.2983,
+  //              -0.3608,  0.1119, -0.5562, -0.0629, -0.1968, -0.8638, -0.2700,
+  //              -0.7690,  0.4216
+  VLOAD_16(v1, 0xb356, 0x3a10, 0xb9f1, 0xb9f1, 0x2f29, 0x34b4, 0xb4c6, 0xb5c6,
+           0x2f29, 0xb873, 0xac06, 0xb24c, 0xbae9, 0xb452, 0xba27, 0x36bf);
+  asm volatile("vfmsub.vv v1, v2, v3");
+  //               0.7485,  0.4175, -0.2632, -0.2632,  0.5542, -1.0127, -0.5679,
+  //               -0.8413,  0.5542, -0.6650, -0.6455,  0.2247,  0.5625,
+  //               -0.5464,  0.3359, -0.4355
+  VCMP_U16(1, v1, 0x39fd, 0x36ae, 0xb436, 0xb436, 0x386f, 0xbc0d, 0xb88b,
+           0xbabb, 0x386f, 0xb952, 0xb92a, 0x3331, 0x3880, 0xb85f, 0x3560,
+           0xb6f8);
+
+  VSET(16, e32, m1);
+  //              -0.74553698, -0.16736358, -0.11869104, -0.85860848,
+  //              -0.66138542, -0.68386567, -0.45389724, -0.12761629,
+  //              -0.95652348,  0.71083277,  0.24187960,  0.01609672,
+  //              -0.58867335, -0.55222940, -0.67417240, -0.06725668
+  VLOAD_32(v2, 0xbf3edb83, 0xbe2b615c, 0xbdf3144a, 0xbf5bcdc4, 0xbf29508e,
+           0xbf2f11d2, 0xbee86538, 0xbe02add8, 0xbf74deb9, 0x3f35f923,
+           0x3e77af49, 0x3c83dd45, 0xbf16b34c, 0xbf0d5ee8, 0xbf2c9690,
+           0xbd89bddf);
+  //              -0.17500710, -0.81537211, -0.31956050,  0.22762603,
+  //              0.49659184, -0.09389434,  0.05757815, -0.13087828,
+  //              -0.73042232, -0.79662275, -0.96801740,  0.03017101,
+  //              0.70759267, -0.35606241,  0.18037270, -0.35372722
+  VLOAD_32(v3, 0xbe333510, 0xbf50bc3a, 0xbea39d6f, 0x3e6916cc, 0x3efe4149,
+           0xbdc04bad, 0x3d6bd711, 0xbe0604f5, 0xbf3afcf5, 0xbf4bef78,
+           0xbf77cffd, 0x3cf72932, 0x3f3524cb, 0xbeb64dd0, 0x3e38b39f,
+           0xbeb51bbc);
+  //               0.92876774,  0.18572871, -0.42147154, -0.79289448,
+  //               0.90907055,  0.07037155,  0.07339484,  0.17415307,
+  //               -0.61978233, -0.04939311,  0.56138068, -0.51601994,
+  //               -0.80625385, -0.31227911,  0.91474551,  0.78424871
+  VLOAD_32(v1, 0x3f6dc3b9, 0x3e3e2fab, 0xbed7cb1e, 0xbf4afb22, 0x3f68b8d9,
+           0x3d901ef6, 0x3d965009, 0x3e32552f, 0xbf1eaa0e, 0xbd4a506e,
+           0x3f0fb6a5, 0xbf0419e2, 0xbf4e66a7, 0xbe9fe30c, 0x3f6a2cc3,
+           0x3f48c486);
+  asm volatile("vfmsub.vv v1, v2, v3");
+  //              -0.51742357,  0.78428787,  0.36958539,  0.45315993,
+  //              -1.09783781,  0.04576965, -0.09089187,
+  //              0.10865352,  1.32325864,  0.76151252,  1.10380387,
+  //              -0.03847724, -0.23297250,  0.52851212, -0.79706889, 0.30098125
+  VCMP_U32(2, v1, 0xbf0475df, 0x3f48c717, 0x3ebd3a4c, 0x3ee80493, 0xbf8c85f3,
+           0x3d3b78f5, 0xbdba2584, 0x3dde85bc, 0x3fa9608a, 0x3f42f27c,
+           0x3f8d4973, 0xbd1d9a4f, 0xbe6e9058, 0x3f074c92, 0xbf4c0cb5,
+           0x3e9a1a37);
+
+  VSET(16, e64, m1);
+  //               0.3304351537536074, -0.7528197595818080, -0.7530937950641439,
+  //               -0.7994160811423281,  0.0797802827518117,
+  //               -0.6361377214985149,  0.1748070414096887, 0.8251843575618585,
+  //               0.0699629848559165, -0.8195631240215655, -0.4843919596862658,
+  //               -0.9206444585342115,  0.9791118581337512, 0.5143481050333210,
+  //               0.5856279779979670, -0.5536419150604011
+  VLOAD_64(v2, 0x3fd525d97cb482ac, 0xbfe8171976e5f762, 0xbfe819582893df6e,
+           0xbfe994d1088ce396, 0x3fb46c7b0948dfc0, 0xbfe45b3d7eb2d188,
+           0x3fc66013befb8968, 0x3fea67e9069cc438, 0x3fb1e9181be2ff10,
+           0xbfea39dc71d5c454, 0xbfdf00472253102c, 0xbfed75eb5e14bcf6,
+           0x3fef54e26439ed98, 0x3fe0758a283c1602, 0x3fe2bd76e2a3f6ca,
+           0xbfe1b76f3fdc22ac);
+  //               0.4156163852505284, -0.7806302214299039, -0.8826873649954201,
+  //               0.4810449553239884,  0.9337837820126544, -0.5377837408558668,
+  //               -0.1434453653318362,  0.1199087999382409,
+  //               -0.2601268153647489, -0.1813009025048657,
+  //               -0.2492371358416354,  0.4131695659117063,
+  //               -0.9085600854772706, -0.3952216110937696, 0.0817663443229741,
+  //               0.1439804529607418
+  VLOAD_64(v3, 0x3fda997577954be0, 0xbfe8faec3ae9f10e, 0xbfec3ef992a7ed86,
+           0x3fdec970c7c16d8c, 0x3fede18e86a8f206, 0xbfe135863f697cd2,
+           0xbfc25c6af06e7710, 0x3fbeb257d63cc310, 0xbfd0a5eaf1337874,
+           0xbfc734de337f3100, 0xbfcfe700a1b1bb78, 0x3fda715ec352c558,
+           0xbfed12ec99b26d4c, 0xbfd94b4f95947db0, 0x3fb4eea39ec7d8a0,
+           0x3fc26df3945d6540);
+  //              -0.2185765241217579, -0.9587275435281344,  0.1216903502931035,
+  //              0.7653655177934149, -0.5928258331230032,  0.9123074434439491,
+  //              0.1569052366565831,  0.2566745252901157, -0.9113595614847214,
+  //              0.1628442001087833,  0.2337303194688813,  0.1926350000139823,
+  //              -0.6653994610877216, -0.6745212179353777,  0.8748797125997727,
+  //              -0.7324641634418565
+  VLOAD_64(v1, 0xbfcbfa50c7635df8, 0xbfeeade562a749c2, 0x3fbf27194abf66e0,
+           0x3fe87ddfd38d1514, 0xbfe2f86de1af9792, 0x3fed319f612fa6f6,
+           0x3fc4157886016dd8, 0x3fd06d5afcf59780, 0xbfed29db86ef2934,
+           0x3fc4d81428e7be98, 0x3fcdeae00719eac8, 0x3fc8a84380900070,
+           0xbfe54af3cf84bab0, 0xbfe595ad856fb278, 0x3febff03bd3198ce,
+           0xbfe77058af6f3156);
+  asm volatile("vfmsub.vv v1, v2, v3");
+  //              -0.4878417526056305,  1.5023792602532113,  0.7910431172705017,
+  //              -1.0928904581998689, -0.9810795946017860, -0.0425694375227023,
+  //              0.1708735055334605,  0.0918950033157782,  0.1963653801662987,
+  //              0.0478398011349183,  0.1360200483560070, -0.5905179111943168,
+  //              0.2570595827304748,  0.0482829008439404,  0.4305876927582732,
+  //              0.2615424092003222
+  VCMP_U64(3, v1, 0xbfdf38cc9d4420dd, 0x3ff809bed5cf9e94, 0x3fe95039a7cce2e7,
+           0xbff17c7ab4814324, 0xbfef650108b2cdb1, 0xbfa5cba94bf030ac,
+           0x3fc5df2edb027178, 0x3fb7866e51e83656, 0x3fc9228032f0c004,
+           0x3fa87e755aa4ab1c, 0x3fc1691adda50ab1, 0xbfe2e585d18904b2,
+           0x3fd073aa093cd9d6, 0x3fa8b88950295616, 0x3fdb8ebfae9d3d83,
+           0x3fd0bd1c5f821364);
+};
+
+// Simple random test with similar values (masked)
+// The numbers are the same of TEST_CASE1
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  //               0.6821,  0.7749,  0.0299,  0.0299, -0.5410, -0.1865,  0.1885,
+  //               0.0228,  0.7217,  0.1902, -0.9160, -0.3511, -0.9287, -0.9961,
+  //               -0.6509, -0.3940
+  VLOAD_16(v2, 0x3975, 0x3a33, 0x27a5, 0x27a5, 0xb854, 0xb1f8, 0x3208, 0x25d8,
+           0x39c6, 0x3216, 0xbb54, 0xb59e, 0xbb6e, 0xbbf8, 0xb935, 0xb64e);
+  //              -0.9048,  0.1698,  0.2411,  0.2411, -0.6147,  0.9580,  0.5117,
+  //              0.8330, -0.8584,  0.5591,  0.7031, -0.1556,  0.2397,  0.8154,
+  //              0.1646,  0.2693
+  VLOAD_16(v3, 0xbb3d, 0x316f, 0x33b7, 0x33b7, 0xb8eb, 0x3baa, 0x3818, 0x3aaa,
+           0xbade, 0x3879, 0x39a0, 0xb0fb, 0x33ac, 0x3a86, 0x3144, 0x344f);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //              -0.2292,  0.7578, -0.7427, -0.7427,  0.1119,  0.2939, -0.2983,
+  //              -0.3608,  0.3169, -0.5562, -0.0629, -0.1968, -0.8638, -0.2700,
+  //              -0.7690,  0.4216
+  VLOAD_16(v1, 0xb356, 0x3a10, 0xb9f1, 0xb9f1, 0x2f29, 0x34b4, 0xb4c6, 0xb5c6,
+           0x3512, 0xb873, 0xac06, 0xb24c, 0xbae9, 0xb452, 0xba27, 0x36bf);
+  asm volatile("vfmsub.vv v1, v2, v3, v0.t");
+  //              -0.2292,  0.4175, -0.7427, -0.2632,  0.1119, -1.0127, -0.2983,
+  //              -0.8413,  0.3169, -0.6650, -0.0629,  0.2247, -0.8638, -0.5464,
+  //              -0.7690, -0.4355
+  VCMP_U16(4, v1, 0xb356, 0x36ae, 0xb9f1, 0xb436, 0x2f29, 0xbc0d, 0xb4c6,
+           0xbabb, 0x3512, 0xb952, 0xac06, 0x3331, 0xbae9, 0xb85f, 0xba27,
+           0xb6f8);
+
+  VSET(16, e32, m1);
+  //              -0.74553698, -0.16736358, -0.11869104, -0.85860848,
+  //              -0.66138542, -0.68386567, -0.45389724, -0.12761629,
+  //              -0.95652348,  0.71083277,  0.24187960,  0.01609672,
+  //              -0.58867335, -0.55222940, -0.67417240, -0.06725668
+  VLOAD_32(v2, 0xbf3edb83, 0xbe2b615c, 0xbdf3144a, 0xbf5bcdc4, 0xbf29508e,
+           0xbf2f11d2, 0xbee86538, 0xbe02add8, 0xbf74deb9, 0x3f35f923,
+           0x3e77af49, 0x3c83dd45, 0xbf16b34c, 0xbf0d5ee8, 0xbf2c9690,
+           0xbd89bddf);
+  //              -0.17500710, -0.81537211, -0.31956050,  0.22762603,
+  //              0.49659184, -0.09389434,  0.05757815, -0.13087828,
+  //              -0.73042232, -0.79662275, -0.96801740,  0.03017101,
+  //              0.70759267, -0.35606241,  0.18037270, -0.35372722
+  VLOAD_32(v3, 0xbe333510, 0xbf50bc3a, 0xbea39d6f, 0x3e6916cc, 0x3efe4149,
+           0xbdc04bad, 0x3d6bd711, 0xbe0604f5, 0xbf3afcf5, 0xbf4bef78,
+           0xbf77cffd, 0x3cf72932, 0x3f3524cb, 0xbeb64dd0, 0x3e38b39f,
+           0xbeb51bbc);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //               0.92876774,  0.18572871, -0.42147154, -0.79289448,
+  //               0.90907055,  0.07037155,  0.07339484,  0.17415307,
+  //               -0.61978233, -0.04939311,  0.56138068, -0.51601994,
+  //               -0.80625385, -0.31227911,  0.91474551,  0.78424871
+  VLOAD_32(v1, 0x3f6dc3b9, 0x3e3e2fab, 0xbed7cb1e, 0xbf4afb22, 0x3f68b8d9,
+           0x3d901ef6, 0x3d965009, 0x3e32552f, 0xbf1eaa0e, 0xbd4a506e,
+           0x3f0fb6a5, 0xbf0419e2, 0xbf4e66a7, 0xbe9fe30c, 0x3f6a2cc3,
+           0x3f48c486);
+  asm volatile("vfmsub.vv v1, v2, v3, v0.t");
+  //               0.92876774,  0.78428787, -0.42147154,  0.45315993,
+  //               0.90907055,  0.04576965,  0.07339484,  0.10865352,
+  //               -0.61978233,  0.76151252,  0.56138068, -0.03847724,
+  //               -0.80625385,  0.52851212,  0.91474551,  0.30098125
+  VCMP_U32(5, v1, 0x3f6dc3b9, 0x3f48c717, 0xbed7cb1e, 0x3ee80493, 0x3f68b8d9,
+           0x3d3b78f5, 0x3d965009, 0x3dde85bc, 0xbf1eaa0e, 0x3f42f27c,
+           0x3f0fb6a5, 0xbd1d9a4f, 0xbf4e66a7, 0x3f074c92, 0x3f6a2cc3,
+           0x3e9a1a37);
+
+  VSET(16, e64, m1);
+  //               0.3304351537536074, -0.7528197595818080, -0.7530937950641439,
+  //               -0.7994160811423281,  0.0797802827518117,
+  //               -0.6361377214985149,  0.1748070414096887, 0.8251843575618585,
+  //               0.0699629848559165, -0.8195631240215655, -0.4843919596862658,
+  //               -0.9206444585342115,  0.9791118581337512, 0.5143481050333210,
+  //               0.5856279779979670, -0.5536419150604011
+  VLOAD_64(v2, 0x3fd525d97cb482ac, 0xbfe8171976e5f762, 0xbfe819582893df6e,
+           0xbfe994d1088ce396, 0x3fb46c7b0948dfc0, 0xbfe45b3d7eb2d188,
+           0x3fc66013befb8968, 0x3fea67e9069cc438, 0x3fb1e9181be2ff10,
+           0xbfea39dc71d5c454, 0xbfdf00472253102c, 0xbfed75eb5e14bcf6,
+           0x3fef54e26439ed98, 0x3fe0758a283c1602, 0x3fe2bd76e2a3f6ca,
+           0xbfe1b76f3fdc22ac);
+  //               0.4156163852505284, -0.7806302214299039, -0.8826873649954201,
+  //               0.4810449553239884,  0.9337837820126544, -0.5377837408558668,
+  //               -0.1434453653318362,  0.1199087999382409,
+  //               -0.2601268153647489, -0.1813009025048657,
+  //               -0.2492371358416354,  0.4131695659117063,
+  //               -0.9085600854772706, -0.3952216110937696, 0.0817663443229741,
+  //               0.1439804529607418
+  VLOAD_64(v3, 0x3fda997577954be0, 0xbfe8faec3ae9f10e, 0xbfec3ef992a7ed86,
+           0x3fdec970c7c16d8c, 0x3fede18e86a8f206, 0xbfe135863f697cd2,
+           0xbfc25c6af06e7710, 0x3fbeb257d63cc310, 0xbfd0a5eaf1337874,
+           0xbfc734de337f3100, 0xbfcfe700a1b1bb78, 0x3fda715ec352c558,
+           0xbfed12ec99b26d4c, 0xbfd94b4f95947db0, 0x3fb4eea39ec7d8a0,
+           0x3fc26df3945d6540);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //              -0.2185765241217579, -0.9587275435281344,  0.1216903502931035,
+  //              0.7653655177934149, -0.5928258331230032,  0.9123074434439491,
+  //              0.1569052366565831,  0.2566745252901157, -0.9113595614847214,
+  //              0.1628442001087833,  0.2337303194688813,  0.1926350000139823,
+  //              -0.6653994610877216, -0.6745212179353777,  0.8748797125997727,
+  //              -0.7324641634418565
+  VLOAD_64(v1, 0xbfcbfa50c7635df8, 0xbfeeade562a749c2, 0x3fbf27194abf66e0,
+           0x3fe87ddfd38d1514, 0xbfe2f86de1af9792, 0x3fed319f612fa6f6,
+           0x3fc4157886016dd8, 0x3fd06d5afcf59780, 0xbfed29db86ef2934,
+           0x3fc4d81428e7be98, 0x3fcdeae00719eac8, 0x3fc8a84380900070,
+           0xbfe54af3cf84bab0, 0xbfe595ad856fb278, 0x3febff03bd3198ce,
+           0xbfe77058af6f3156);
+  asm volatile("vfmsub.vv v1, v2, v3, v0.t");
+  //              -0.2185765241217579,  1.5023792602532113,  0.1216903502931035,
+  //              -1.0928904581998689, -0.5928258331230032, -0.0425694375227023,
+  //              0.1569052366565831,  0.0918950033157782, -0.9113595614847214,
+  //              0.0478398011349183,  0.2337303194688813, -0.5905179111943168,
+  //              -0.6653994610877216,  0.0482829008439404,  0.8748797125997727,
+  //              0.2615424092003222
+  VCMP_U64(6, v1, 0xbfcbfa50c7635df8, 0x3ff809bed5cf9e94, 0x3fbf27194abf66e0,
+           0xbff17c7ab4814324, 0xbfe2f86de1af9792, 0xbfa5cba94bf030ac,
+           0x3fc4157886016dd8, 0x3fb7866e51e83656, 0xbfed29db86ef2934,
+           0x3fa87e755aa4ab1c, 0x3fcdeae00719eac8, 0xbfe2e585d18904b2,
+           0xbfe54af3cf84bab0, 0x3fa8b88950295616, 0x3febff03bd3198ce,
+           0x3fd0bd1c5f821364);
+};
+
+// Simple random test with similar values (vector-scalar)
+void TEST_CASE3(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //                              0.1489
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0x30c4);
+  //               0.8530, -0.3298, -0.1814, -0.2385,  0.9946,  0.6553,  0.8711,
+  //               -0.6377,  0.4224, -0.1814,  0.7026,  0.2852,  0.0553, 0.7349,
+  //               -0.8105,  0.0033
+  VLOAD_16(v2, 0x3ad3, 0xb547, 0xb1ce, 0xb3a2, 0x3bf5, 0x393e, 0x3af8, 0xb91a,
+           0x36c2, 0xb1ce, 0x399f, 0x3490, 0x2b15, 0x39e1, 0xba7c, 0x1abd);
+  //              -0.2338, -0.2512,  0.0069,  0.0613, -0.1733,  0.8560, -0.2766,
+  //              -0.0028, -0.1803,  0.0069,  0.7856, -0.0243, -0.1974,  0.6416,
+  //              0.7109,  0.0817
+  VLOAD_16(v1, 0xb37b, 0xb405, 0x1f06, 0x2bd8, 0xb18c, 0x3ad9, 0xb46d, 0x99d2,
+           0xb1c5, 0x1f06, 0x3a49, 0xa639, 0xb251, 0x3922, 0x39b0, 0x2d3a);
+  asm volatile("vfmsub.vf v1, %[A], v2" ::[A] "f"(dscalar_16));
+  //              -0.8877,  0.2925,  0.1824,  0.2477, -1.0205, -0.5278, -0.9121,
+  //              0.6372, -0.4492,  0.1824, -0.5854, -0.2888, -0.0847, -0.6392,
+  //              0.9165,  0.0089
+  VCMP_U16(7, v1, 0xbb1a, 0x34ae, 0x31d6, 0x33ed, 0xbc15, 0xb839, 0xbb4c,
+           0x3919, 0xb730, 0x31d6, 0xb8af, 0xb49f, 0xad6c, 0xb91d, 0x3b55,
+           0x208b);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                              -0.12857932
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0xbe03aa4c);
+  //               0.31050768, -0.13843875,  0.23405042, -0.30545133,
+  //               -0.28880060,  0.46233574, -0.51105869, -0.11776974,
+  //               -0.39969075,  0.51141965,  0.88750082, -0.22310242,
+  //               0.60111052,  0.58466393, -0.14306845, -0.01826003
+  VLOAD_32(v2, 0x3e9efadd, 0xbe0dc2e3, 0x3e6faaea, 0xbe9c641e, 0xbe93ddac,
+           0x3eecb745, 0xbf02d4be, 0xbdf13143, 0xbecca444, 0x3f02ec66,
+           0x3f633341, 0xbe6474f6, 0x3f19e261, 0x3f15ac89, 0xbe128089,
+           0xbc95960e);
+  //              -0.51789892,  0.77328473, -0.88433731,  0.40865302,
+  //              -0.50454420,  0.30827177, -0.25503114,  0.07736996,
+  //              0.20596179, -0.42633566,  0.89622146,  0.03779412, 0.50878429,
+  //              0.67896879, -0.17667305,  0.06984760
+  VLOAD_32(v1, 0xbf049506, 0x3f45f5fd, 0xbf6263ee, 0x3ed13af8, 0xbf0129cf,
+           0x3e9dd5cc, 0xbe829371, 0x3d9e7424, 0x3e52e7a6, 0xbeda48ab,
+           0x3f656ec5, 0x3d1ace01, 0x3f023fb0, 0x3f2dd0e6, 0xbe34e9c8,
+           0x3d8f0c42);
+  asm volatile("vfmsub.vf v1, %[A], v2" ::[A] "f"(dscalar_32));
+  //              -0.24391660,  0.03901032, -0.12034293,  0.25290701,
+  //              0.35367453, -0.50197309,  0.54385042,  0.10782156, 0.37320831,
+  //              -0.45660171, -1.00273633,  0.21824288, -0.66652966,
+  //              -0.67196524,  0.16578496,  0.00927907
+  VCMP_U32(8, v1, 0xbe79c546, 0x3d1fc94a, 0xbdf6765b, 0x3e817d07, 0x3eb514d5,
+           0xbf00814f, 0x3f0b39c8, 0x3ddcd18d, 0x3ebf1529, 0xbee9c7b3,
+           0xbf8059aa, 0x3e5f7b10, 0xbf2aa1b0, 0xbf2c05eb, 0x3e29c388,
+           0x3c18073f);
+
+  VSET(16, e64, m1);
+  double dscalar_64;
+  //                               -0.6953502965951812
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0xbfe6404f43e47c8c);
+  //               -0.8873182146436771,  0.3913246153259273, 0.8941416868753180,
+  //               0.2630283463166789, -0.8096670634564123,  0.6449486037845993,
+  //               0.8384405697279889, -0.9956067461953679, -0.8936777193492917,
+  //               -0.4464070291333477,  0.5599998966835931,
+  //               -0.3406088963725078,  0.4908382567748615,
+  //               -0.5194254665571632,  0.0909287222245825,  0.5893410930389467
+  VLOAD_64(v2, 0xbfec64e92b21453c, 0x3fd90b76663c74f4, 0x3fec9ccf06e3d51a,
+           0x3fd0d574d8567864, 0xbfe9e8cae6c6325c, 0x3fe4a36b411b6206,
+           0x3fead4815153e1da, 0xbfefdc02add2c126, 0xbfec990204389c42,
+           0xbfdc91eec9b5438c, 0x3fe1eb84e7409f04, 0xbfd5cc8941a96178,
+           0x3fdf69e4dd1e50c8, 0xbfe09f2227f25264, 0x3fb7471ad038be10,
+           0x3fe2dbe1da195142);
+  //               -0.4387964890891065, -0.2425720412460179,
+  //               -0.8909058709916624, -0.7961584351708695, 0.0353694444236163,
+  //               0.2992862865812480, -0.4186756300648600, -0.5421957392048740,
+  //               0.3780444269462682, -0.6731508364205383,  0.1263808806166760,
+  //               0.8571806635726140,  0.5149747658358419,  0.3530123248386567,
+  //               -0.3756405874818076, -0.4529815298587780
+  VLOAD_64(v1, 0xbfdc153dde8f3078, 0xbfcf0c99c409ad98, 0xbfec824d0777279c,
+           0xbfe97a21412fca1a, 0x3fa21bf19e277c80, 0x3fd32781ab407ee0,
+           0xbfdacb94deb0b06c, 0xbfe159aae0fd4b9a, 0x3fd831e1408ad588,
+           0xbfe58a739f7670b4, 0x3fc02d3faa8b4d88, 0x3feb6e062499dac6,
+           0x3fe07aac5c30f764, 0x3fd697c1019115dc, 0xbfd80a7ed19236bc,
+           0xbfdcfda63e1bdf38);
+  asm volatile("vfmsub.vf v1, %[A], v2" ::[A] "f"(dscalar_64));
+  //               1.1924354834767115, -0.2226520744998102, -0.2746500252428773,
+  //               0.2905806577161405,  0.7850729097860438, -0.8530574119257405,
+  //               -0.5473143461852141,  1.3726227142641205, 0.6308044149460488,
+  //               0.9144826628916634, -0.6478788795043589, -0.2554319322783636,
+  //               -0.8489261129378481,  0.2739582417788488, 0.1702730716940806,
+  //               -0.2743602518995064
+  VCMP_U64(9, v1, 0x3ff314373ac1f573, 0xbfcc7fdcf92e7eaa, 0xbfd193ddb310e0ff,
+           0x3fd298df9d6f6c70, 0x3fe91f5139103634, 0xbfeb4c3f0eba9b49,
+           0xbfe18399602fe862, 0x3ff5f6433c382dac, 0x3fe42f8cbd8bb3c3,
+           0x3fed4371253c1e34, 0xbfe4bb6c7ce7b0ea, 0xbfd058ff2cdf5691,
+           0xbfeb2a6718793b11, 0x3fd18888263a3a6e, 0x3fc5cb820d286398,
+           0xbfd18f1e4d4ec3d2);
+};
+
+// Simple random test with similar values (vector-scalar) (masked)
+void TEST_CASE4(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //                              0.1489
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0x30c4);
+  //                0.8530, -0.3298, -0.1814, -0.2385,  0.9946,  0.6553, 0.8711,
+  //                -0.6377,  0.4224, -0.1814,  0.7026,  0.2852,  0.0553,
+  //                0.7349, -0.8105,  0.0033
+  VLOAD_16(v2, 0x3ad3, 0xb547, 0xb1ce, 0xb3a2, 0x3bf5, 0x393e, 0x3af8, 0xb91a,
+           0x36c2, 0xb1ce, 0x399f, 0x3490, 0x2b15, 0x39e1, 0xba7c, 0x1abd);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //               -0.2338, -0.2512,  0.0069,  0.0613, -0.1733,  0.8560,
+  //               -0.2766, -0.0028, -0.1803,  0.0069,  0.7856, -0.0243,
+  //               -0.1974,  0.6416,  0.7109,  0.0817
+  VLOAD_16(v1, 0xb37b, 0xb405, 0x1f06, 0x2bd8, 0xb18c, 0x3ad9, 0xb46d, 0x99d2,
+           0xb1c5, 0x1f06, 0x3a49, 0xa639, 0xb251, 0x3922, 0x39b0, 0x2d3a);
+  asm volatile("vfmsub.vf v1, %[A], v2, v0.t" ::[A] "f"(dscalar_16));
+  //               -0.2338,  0.2925,  0.0069,  0.2477, -0.1733, -0.5278,
+  //               -0.2766,  0.6372, -0.1803,  0.1824,  0.7856, -0.2888,
+  //               -0.1974, -0.6392,  0.7109,  0.0089
+  VCMP_U16(10, v1, 0xb37b, 0x34ae, 0x1f06, 0x33ed, 0xb18c, 0xb839, 0xb46d,
+           0x3919, 0xb1c5, 0x31d6, 0x3a49, 0xb49f, 0xb251, 0xb91d, 0x39b0,
+           0x208b);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                              -0.12857932
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0xbe03aa4c);
+  //                0.31050768, -0.13843875,  0.23405042, -0.30545133,
+  //                -0.28880060,  0.46233574, -0.51105869, -0.11776974,
+  //                -0.39969075,  0.51141965,  0.88750082, -0.22310242,
+  //                0.60111052,  0.58466393, -0.14306845, -0.01826003
+  VLOAD_32(v2, 0x3e9efadd, 0xbe0dc2e3, 0x3e6faaea, 0xbe9c641e, 0xbe93ddac,
+           0x3eecb745, 0xbf02d4be, 0xbdf13143, 0xbecca444, 0x3f02ec66,
+           0x3f633341, 0xbe6474f6, 0x3f19e261, 0x3f15ac89, 0xbe128089,
+           0xbc95960e);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //               -0.51789892,  0.77328473, -0.88433731,  0.40865302,
+  //               -0.50454420,  0.30827177, -0.25503114,  0.07736996,
+  //               0.20596179, -0.42633566,  0.89622146,  0.03779412,
+  //               0.50878429,  0.67896879, -0.17667305,  0.06984760
+  VLOAD_32(v1, 0xbf049506, 0x3f45f5fd, 0xbf6263ee, 0x3ed13af8, 0xbf0129cf,
+           0x3e9dd5cc, 0xbe829371, 0x3d9e7424, 0x3e52e7a6, 0xbeda48ab,
+           0x3f656ec5, 0x3d1ace01, 0x3f023fb0, 0x3f2dd0e6, 0xbe34e9c8,
+           0x3d8f0c42);
+  asm volatile("vfmsub.vf v1, %[A], v2, v0.t" ::[A] "f"(dscalar_32));
+  //               -0.51789892,  0.03901032, -0.88433731,  0.25290701,
+  //               -0.50454420, -0.50197309, -0.25503114,  0.10782156,
+  //               0.20596179, -0.45660171,  0.89622146,  0.21824288,
+  //               0.50878429, -0.67196524, -0.17667305,  0.00927907
+  VCMP_U32(11, v1, 0xbf049506, 0x3d1fc94a, 0xbf6263ee, 0x3e817d07, 0xbf0129cf,
+           0xbf00814f, 0xbe829371, 0x3ddcd18d, 0x3e52e7a6, 0xbee9c7b3,
+           0x3f656ec5, 0x3e5f7b10, 0x3f023fb0, 0xbf2c05eb, 0xbe34e9c8,
+           0x3c18073f);
+
+  VSET(16, e64, m1);
+  double dscalar_64;
+  //                               -0.6953502965951812
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0xbfe6404f43e47c8c);
+  //                -0.8873182146436771,  0.3913246153259273,
+  //                0.8941416868753180,  0.2630283463166789,
+  //                -0.8096670634564123,  0.6449486037845993,
+  //                0.8384405697279889, -0.9956067461953679,
+  //                -0.8936777193492917, -0.4464070291333477,
+  //                0.5599998966835931, -0.3406088963725078, 0.4908382567748615,
+  //                -0.5194254665571632,  0.0909287222245825, 0.5893410930389467
+  VLOAD_64(v2, 0xbfec64e92b21453c, 0x3fd90b76663c74f4, 0x3fec9ccf06e3d51a,
+           0x3fd0d574d8567864, 0xbfe9e8cae6c6325c, 0x3fe4a36b411b6206,
+           0x3fead4815153e1da, 0xbfefdc02add2c126, 0xbfec990204389c42,
+           0xbfdc91eec9b5438c, 0x3fe1eb84e7409f04, 0xbfd5cc8941a96178,
+           0x3fdf69e4dd1e50c8, 0xbfe09f2227f25264, 0x3fb7471ad038be10,
+           0x3fe2dbe1da195142);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //                -0.4387964890891065, -0.2425720412460179,
+  //                -0.8909058709916624, -0.7961584351708695,
+  //                0.0353694444236163,  0.2992862865812480,
+  //                -0.4186756300648600, -0.5421957392048740,
+  //                0.3780444269462682, -0.6731508364205383, 0.1263808806166760,
+  //                0.8571806635726140,  0.5149747658358419, 0.3530123248386567,
+  //                -0.3756405874818076, -0.4529815298587780
+  VLOAD_64(v1, 0xbfdc153dde8f3078, 0xbfcf0c99c409ad98, 0xbfec824d0777279c,
+           0xbfe97a21412fca1a, 0x3fa21bf19e277c80, 0x3fd32781ab407ee0,
+           0xbfdacb94deb0b06c, 0xbfe159aae0fd4b9a, 0x3fd831e1408ad588,
+           0xbfe58a739f7670b4, 0x3fc02d3faa8b4d88, 0x3feb6e062499dac6,
+           0x3fe07aac5c30f764, 0x3fd697c1019115dc, 0xbfd80a7ed19236bc,
+           0xbfdcfda63e1bdf38);
+  asm volatile("vfmsub.vf v1, %[A], v2, v0.t" ::[A] "f"(dscalar_64));
+  //               -0.4387964890891065, -0.2226520744998102,
+  //               -0.8909058709916624,  0.2905806577161405, 0.0353694444236163,
+  //               -0.8530574119257405,
+  //               -0.4186756300648600,  1.3726227142641205, 0.3780444269462682,
+  //               0.9144826628916634,  0.1263808806166760, -0.2554319322783636,
+  //               0.5149747658358419,  0.2739582417788488, -0.3756405874818076,
+  //               -0.2743602518995064
+  VCMP_U64(12, v1, 0xbfdc153dde8f3078, 0xbfcc7fdcf92e7eaa, 0xbfec824d0777279c,
+           0x3fd298df9d6f6c70, 0x3fa21bf19e277c80, 0xbfeb4c3f0eba9b49,
+           0xbfdacb94deb0b06c, 0x3ff5f6433c382dac, 0x3fd831e1408ad588,
+           0x3fed4371253c1e34, 0x3fc02d3faa8b4d88, 0xbfd058ff2cdf5691,
+           0x3fe07aac5c30f764, 0x3fd18888263a3a6e, 0xbfd80a7ed19236bc,
+           0xbfd18f1e4d4ec3d2);
+};
+
+int main(void) {
+  enable_vec();
+  enable_fp();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vfmul.c b/apps/riscv-tests/isa/rv64uv/vfmul.c
new file mode 100644
index 0000000..fe2faec
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vfmul.c
@@ -0,0 +1,350 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+// Simple random test with similar values + 1 subnormal
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  //              -0.5522,  0.0462, -0.4255,  0.4131,  0.4658,  0.3931, -0.4868,
+  //              0.5503,  0.3516, -0.3025, -0.2155,  0.9307,  0.9775,  0.8394,
+  //              0.7446,  0.3909
+  VLOAD_16(v2, 0xb86b, 0x29e9, 0xb6cf, 0x369c, 0x3774, 0x364a, 0xb7ca, 0x3867,
+           0x35a0, 0xb4d7, 0xb2e5, 0x3b72, 0x3bd2, 0x3ab7, 0x39f5, 0x3641);
+  //               0.8247,  0.4902,  0.5796, -0.9561, -0.7676,  0.1672, -0.1094,
+  //               -0.9395,  0.4885, -0.2739,  0.8691, -0.3394, -0.8032,
+  //               -0.4922,  0.4456,  0.2050
+  VLOAD_16(v3, 0x3a99, 0x37d8, 0x38a3, 0xbba6, 0xba24, 0x315a, 0xaf01, 0xbb84,
+           0x37d1, 0xb462, 0x3af4, 0xb56e, 0xba6d, 0xb7e0, 0x3721, 0x328f);
+  asm volatile("vfmul.vv v1, v2, v3");
+  //              -0.4553,  0.0226, -0.2466, -0.3950, -0.3577,  0.0657,  0.0533,
+  //              -0.5171,  0.1718,  0.0829, -0.1873, -0.3159, -0.7852, -0.4131,
+  //              0.3318,  0.0801
+  VCMP_U16(1, v1, 0xb749, 0x25cb, 0xb3e4, 0xb652, 0xb5b9, 0x2c35, 0x2ad2,
+           0xb823, 0x317f, 0x2d4e, 0xb1fe, 0xb50e, 0xba48, 0xb69c, 0x354f,
+           0x2d21);
+
+  VSET(16, e32, m1);
+  //               0.48805356,  0.30350628, -0.10483003,  0.61108905,
+  //               -0.09161828,  0.83353645, -0.55006021, -0.78635991,
+  //               0.49253011, -0.03583150, -0.77662903,  0.57397723,
+  //               -0.54674339,  0.86299890,  0.65402901, -0.16832402
+  VLOAD_32(v2, 0x3ef9e228, 0x3e9b652d, 0xbdd6b121, 0x3f1c7055, 0xbdbba25d,
+           0x3f5562a5, 0xbf0cd0bf, 0xbf494ee2, 0x3efc2ce8, 0xbd12c40e,
+           0xbf46d129, 0x3f12f02c, 0xbf0bf760, 0x3f5ced7f, 0x3f276e72,
+           0xbe2c5d22);
+  //               0.87142652, -0.32756421,  0.76706660, -0.54420376,
+  //               -0.99424285,  0.31885657,  0.18092929, -0.68290263,
+  //               0.45391774, -0.45151946, -0.08929581,  0.80524033,
+  //               0.81978256, -0.28325567, -0.53026456, -0.21847765
+  VLOAD_32(v3, 0x3f5f15cf, 0xbea7b67f, 0x3f445e7a, 0xbf0b50f0, 0xbf7e86b3,
+           0x3ea3412b, 0x3e394587, 0xbf2ed2b5, 0x3ee867e8, 0xbee72d8f,
+           0xbdb6e0b9, 0x3f4e243b, 0x3f51dd45, 0xbe9106e3, 0xbf07bf6b,
+           0xbe5fb89b);
+  asm volatile("vfmul.vv v1, v2, v3");
+  //               0.42530280, -0.09941780, -0.08041162, -0.33255696,
+  //               0.09109081,  0.26577857, -0.09952200,  0.53700727,
+  //               0.22356816,  0.01617862,  0.06934972,  0.46218961,
+  //               -0.44821069, -0.24444933, -0.34680840,  0.03677504
+  VCMP_U32(2, v1, 0x3ed9c14a, 0xbdcb9b8f, 0xbda4aed9, 0xbeaa44e8, 0x3dba8dd2,
+           0x3e881421, 0xbdcbd231, 0x3f09794f, 0x3e64ef0d, 0x3c848907,
+           0x3d8e073a, 0x3eeca41e, 0xbee57bdf, 0xbe7a50ed, 0xbeb190df,
+           0x3d16a16c);
+
+  VSET(16, e64, m1);
+  //              -0.7493892241714462,  0.7026559207451004,  0.6475697152132245,
+  //              0.0771197585157644, -0.2238692303359540,  0.8998213782649329,
+  //              -0.9446193329247832,  0.8596730101791072, -0.0254417293392082,
+  //              0.1965035124326171, -0.4709662077579637, -0.2875069600640039,
+  //              -0.4671574223295827,  0.3105385724706418,  0.1703390668980564,
+  //              0.1487690137320270
+  VLOAD_64(v2, 0xbfe7faff1c39514c, 0x3fe67c2844fe1c76, 0x3fe4b8e41f971110,
+           0x3fb3be1ed8b35c30, 0xbfcca7bf376fd290, 0x3feccb5633fc770c,
+           0xbfee3a5252c299d8, 0x3feb8270f8ff23f8, 0xbf9a0d658ddcc1c0,
+           0x3fc92706efb93e80, 0xbfde244f72f5dcb4, 0xbfd2668397b639c0,
+           0xbfdde5e83ebf4f58, 0x3fd3dfdd2d3a1b90, 0x3fc5cdaba8c776a8,
+           0x3fc30adcf05190c8);
+  //               0.6932733143704406, -0.2687556191190688,  0.2528829246597466,
+  //               0.7287253758892476, -0.5682564905667424,  0.0092122398882537,
+  //               -0.5132517188156311, -0.0178020357545405, 0.0816988280997786,
+  //               0.6297663200296084,  0.3637508978200528,  0.6003193921430929,
+  //               -0.9089688764960682,  0.1595578103621622, 0.2113473996516566,
+  //               -0.4586515678904381
+  VLOAD_64(v3, 0x3fe62f4b848d2362, 0xbfd1334ac4aee374, 0x3fd02f3bdcc85930,
+           0x3fe751b7e126b540, 0xbfe22f283c572a1e, 0x3f82dddde857f980,
+           0xbfe06c8ede5db9be, 0xbf923ab26578ce40, 0x3fb4ea36e2cf6110,
+           0x3fe4270bb294c832, 0x3fd747b1d881c6e4, 0x3fe335d1038d1808,
+           0xbfed1645e5b43d3e, 0x3fc46c63eca9d670, 0x3fcb0d6e7ccc9be0,
+           0xbfdd5a8c1b164ebc);
+  asm volatile("vfmul.vv v1, v2, v3");
+  //              -0.5195315511948315, -0.1888427270075288,  0.1637593235041994,
+  //              0.0561991250128884,  0.1272151431765869,  0.0082893703931556,
+  //              0.4848274962501199, -0.0153039296644220, -0.0020785594718451,
+  //              0.1237512938975817, -0.1713143809148648, -0.1725960035025313,
+  //              0.4246315573217200,  0.0495488546564072,  0.0360007188479938,
+  //              -0.0682331414017083
+  VCMP_U64(3, v1, 0xbfe0a000a1b3e706, 0xbfc82bff9c4ada77, 0x3fc4f610c56ecca8,
+           0x3facc621b7fd0401, 0x3fc04895f7bfec49, 0x3f80fa0475f1bbe1,
+           0x3fdf0769e826220a, 0xbf8f57aaab459580, 0xbf61070e1e8a29ae,
+           0x3fbfae2a3020b759, 0xbfc5eda12fae9203, 0xbfc617a0373b59a7,
+           0x3fdb2d29d6e2f72e, 0x3fa95e77ac9b67ce, 0x3fa26eafac2b53dd,
+           0xbfb177ba26d2dcbe);
+};
+
+// Simple random test with similar values + 1 subnormal (masked)
+// The numbers are the same of TEST_CASE1
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  //              -0.5522,  0.0462, -0.4255,  0.4131,  0.4658,  0.3931, -0.4868,
+  //              0.5503,  0.3516, -0.3025, -0.2155,  0.9307,  0.9775,  0.8394,
+  //              0.7446,  0.3909
+  VLOAD_16(v2, 0xb86b, 0x29e9, 0xb6cf, 0x369c, 0x3774, 0x364a, 0xb7ca, 0x3867,
+           0x35a0, 0xb4d7, 0xb2e5, 0x3b72, 0x3bd2, 0x3ab7, 0x39f5, 0x3641);
+  //               0.8247,  0.4902,  0.5796, -0.9561, -0.7676,  0.1672, -0.1094,
+  //               -0.9395,  0.4885, -0.2739,  0.8691, -0.3394, -0.8032,
+  //               -0.4922,  0.4456,  0.2050
+  VLOAD_16(v3, 0x3a99, 0x37d8, 0x38a3, 0xbba6, 0xba24, 0x315a, 0xaf01, 0xbb84,
+           0x37d1, 0xb462, 0x3af4, 0xb56e, 0xba6d, 0xb7e0, 0x3721, 0x328f);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfmul.vv v1, v2, v3, v0.t");
+  //               0.0000,  0.0226,  0.0000, -0.3950,  0.0000,  0.0657,  0.0000,
+  //               -0.5171,  0.0000,  0.0829,  0.0000, -0.3159,  0.0000,
+  //               -0.4131,  0.0000,  0.0801
+  VCMP_U16(4, v1, 0x0, 0x25cb, 0x0, 0xb652, 0x0, 0x2c35, 0x0, 0xb823, 0x0,
+           0x2d4e, 0x0, 0xb50e, 0x0, 0xb69c, 0x0, 0x2d21);
+
+  VSET(16, e32, m1);
+  //               0.48805356,  0.30350628, -0.10483003,  0.61108905,
+  //               -0.09161828,  0.83353645, -0.55006021, -0.78635991,
+  //               0.49253011, -0.03583150, -0.77662903,  0.57397723,
+  //               -0.54674339,  0.86299890,  0.65402901, -0.16832402
+  VLOAD_32(v2, 0x3ef9e228, 0x3e9b652d, 0xbdd6b121, 0x3f1c7055, 0xbdbba25d,
+           0x3f5562a5, 0xbf0cd0bf, 0xbf494ee2, 0x3efc2ce8, 0xbd12c40e,
+           0xbf46d129, 0x3f12f02c, 0xbf0bf760, 0x3f5ced7f, 0x3f276e72,
+           0xbe2c5d22);
+  //               0.87142652, -0.32756421,  0.76706660, -0.54420376,
+  //               -0.99424285,  0.31885657,  0.18092929, -0.68290263,
+  //               0.45391774, -0.45151946, -0.08929581,  0.80524033,
+  //               0.81978256, -0.28325567, -0.53026456, -0.21847765
+  VLOAD_32(v3, 0x3f5f15cf, 0xbea7b67f, 0x3f445e7a, 0xbf0b50f0, 0xbf7e86b3,
+           0x3ea3412b, 0x3e394587, 0xbf2ed2b5, 0x3ee867e8, 0xbee72d8f,
+           0xbdb6e0b9, 0x3f4e243b, 0x3f51dd45, 0xbe9106e3, 0xbf07bf6b,
+           0xbe5fb89b);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfmul.vv v1, v2, v3, v0.t");
+  //               0.00000000, -0.09941780,  0.00000000, -0.33255696,
+  //               0.00000000,  0.26577857,  0.00000000,  0.53700727,
+  //               0.00000000,  0.01617862,  0.00000000,  0.46218961,
+  //               0.00000000, -0.24444933,  0.00000000,  0.03677504
+  VCMP_U32(5, v1, 0x0, 0xbdcb9b8f, 0x0, 0xbeaa44e8, 0x0, 0x3e881421, 0x0,
+           0x3f09794f, 0x0, 0x3c848907, 0x0, 0x3eeca41e, 0x0, 0xbe7a50ed, 0x0,
+           0x3d16a16c);
+
+  VSET(16, e64, m1);
+  //              -0.7493892241714462,  0.7026559207451004,  0.6475697152132245,
+  //              0.0771197585157644, -0.2238692303359540,  0.8998213782649329,
+  //              -0.9446193329247832,  0.8596730101791072, -0.0254417293392082,
+  //              0.1965035124326171, -0.4709662077579637, -0.2875069600640039,
+  //              -0.4671574223295827,  0.3105385724706418,  0.1703390668980564,
+  //              0.1487690137320270
+  VLOAD_64(v2, 0xbfe7faff1c39514c, 0x3fe67c2844fe1c76, 0x3fe4b8e41f971110,
+           0x3fb3be1ed8b35c30, 0xbfcca7bf376fd290, 0x3feccb5633fc770c,
+           0xbfee3a5252c299d8, 0x3feb8270f8ff23f8, 0xbf9a0d658ddcc1c0,
+           0x3fc92706efb93e80, 0xbfde244f72f5dcb4, 0xbfd2668397b639c0,
+           0xbfdde5e83ebf4f58, 0x3fd3dfdd2d3a1b90, 0x3fc5cdaba8c776a8,
+           0x3fc30adcf05190c8);
+  //               0.6932733143704406, -0.2687556191190688,  0.2528829246597466,
+  //               0.7287253758892476, -0.5682564905667424,  0.0092122398882537,
+  //               -0.5132517188156311, -0.0178020357545405, 0.0816988280997786,
+  //               0.6297663200296084,  0.3637508978200528,  0.6003193921430929,
+  //               -0.9089688764960682,  0.1595578103621622, 0.2113473996516566,
+  //               -0.4586515678904381
+  VLOAD_64(v3, 0x3fe62f4b848d2362, 0xbfd1334ac4aee374, 0x3fd02f3bdcc85930,
+           0x3fe751b7e126b540, 0xbfe22f283c572a1e, 0x3f82dddde857f980,
+           0xbfe06c8ede5db9be, 0xbf923ab26578ce40, 0x3fb4ea36e2cf6110,
+           0x3fe4270bb294c832, 0x3fd747b1d881c6e4, 0x3fe335d1038d1808,
+           0xbfed1645e5b43d3e, 0x3fc46c63eca9d670, 0x3fcb0d6e7ccc9be0,
+           0xbfdd5a8c1b164ebc);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfmul.vv v1, v2, v3, v0.t");
+  //               0.0000000000000000, -0.1888427270075288,  0.0000000000000000,
+  //               0.0561991250128884,  0.0000000000000000,  0.0082893703931556,
+  //               0.0000000000000000, -0.0153039296644220,  0.0000000000000000,
+  //               0.1237512938975817,  0.0000000000000000, -0.1725960035025313,
+  //               0.0000000000000000,  0.0495488546564072,  0.0000000000000000,
+  //               -0.0682331414017083
+  VCMP_U64(6, v1, 0x0, 0xbfc82bff9c4ada77, 0x0, 0x3facc621b7fd0401, 0x0,
+           0x3f80fa0475f1bbe1, 0x0, 0xbf8f57aaab459580, 0x0, 0x3fbfae2a3020b759,
+           0x0, 0xbfc617a0373b59a7, 0x0, 0x3fa95e77ac9b67ce, 0x0,
+           0xbfb177ba26d2dcbe);
+};
+
+// Simple random test with similar values (vector-scalar)
+void TEST_CASE3(void) {
+  VSET(16, e16, m1);
+  //              -0.8423,  0.9531,  0.3889, -0.3704, -0.9731, -0.4636, -0.4797,
+  //              -0.5903,  0.2959,  0.4685, -0.3660,  0.3167, -0.9766,  0.0052,
+  //              -0.6489, -0.0474
+  VLOAD_16(v2, 0xbabd, 0x3ba0, 0x3639, 0xb5ed, 0xbbc9, 0xb76b, 0xb7ad, 0xb8b9,
+           0x34bc, 0x377f, 0xb5db, 0x3511, 0xbbd0, 0x1d48, 0xb931, 0xaa11);
+  double dscalar_16;
+  //                              0.2971
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0x34c1);
+  asm volatile("vfmul.vf v1, v2, %[A]" ::[A] "f"(dscalar_16));
+  //              -0.2502,  0.2832,  0.1155, -0.1100, -0.2891, -0.1377, -0.1426,
+  //              -0.1754,  0.0879,  0.1392, -0.1088,  0.0941, -0.2900,  0.0015,
+  //              -0.1927, -0.0141
+  VCMP_U16(7, v1, 0xb401, 0x3488, 0x2f65, 0xaf0b, 0xb4a0, 0xb068, 0xb090,
+           0xb19d, 0x2da0, 0x3074, 0xaef6, 0x2e05, 0xb4a4, 0x1647, 0xb22b,
+           0xa336);
+
+  VSET(16, e32, m1);
+  //              -0.11454447, -0.46133029,  0.06972761,  0.20429718,
+  //              -0.97134608, -0.95719630, -0.11250938,  0.48455358,
+  //              0.59656250,  0.46462929,  0.13447689, -0.32035729, 0.75118428,
+  //              0.90634471,  0.73552424, -0.53555632
+  VLOAD_32(v2, 0xbdea964b, 0xbeec337c, 0x3d8ecd5a, 0x3e513348, 0xbf78aa23,
+           0xbf750ad1, 0xbde66b52, 0x3ef81768, 0x3f18b852, 0x3eede3e4,
+           0x3e09b44f, 0xbea405df, 0x3f404d9d, 0x3f680635, 0x3f3c4b51,
+           0xbf091a38);
+  double dscalar_32;
+  //                               0.94017404
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0x3f70af3f);
+  asm volatile("vfmul.vf v1, v2, %[A]" ::[A] "f"(dscalar_32));
+  //              -0.10769174, -0.43373078,  0.06555609,  0.19207491,
+  //              -0.91323435, -0.89993113, -0.10577840,  0.45556471,
+  //              0.56087255,  0.43683240,  0.12643167, -0.30119160, 0.70624399,
+  //              0.85212177,  0.69152081, -0.50351614
+  VCMP_U32(8, v1, 0xbddc8d7d, 0xbede11f6, 0x3d864246, 0x3e44af49, 0xbf69c9ba,
+           0xbf6661e3, 0xbdd8a259, 0x3ee93fc7, 0x3f0f9558, 0x3edfa87f,
+           0x3e01774e, 0xbe9a35c9, 0x3f34cc68, 0x3f5a24a7, 0x3f310782,
+           0xbf00e66f);
+
+  VSET(16, e64, m1);
+  //               -0.3344965024132001, -0.2497404698970234, 0.3402338726452623,
+  //               -0.5885400342262450, -0.7135559920290824, 0.1114442794173345,
+  //               -0.9541638058007114,  0.1021679621951177,
+  //               -0.1364702451627324, -0.9351295729000717,
+  //               -0.2701320849999789,  0.3582375365191053,
+  //               -0.6137661452178358,  0.6195430637830983, 0.2731869234335833,
+  //               -0.4075196944877124
+  VLOAD_64(v2, 0xbfd56864049f6dd8, 0xbfcff77ee7590278, 0x3fd5c6644b002e60,
+           0xbfe2d551e8ec6e20, 0xbfe6d573603426e0, 0x3fbc879cbf6c7a10,
+           0xbfee8882889e1c44, 0x3fba27adf853b5f0, 0xbfc177db63eceed0,
+           0xbfedec94daa41aac, 0xbfd149d815ab3680, 0x3fd6ed5d21e3257c,
+           0xbfe3a3f8e623486e, 0x3fe3d34bf9ad2f82, 0x3fd17be50175e4e8,
+           0xbfda14cd7c133da0);
+  double dscalar_64;
+  //                               -0.7970907277742201
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0xbfe981c469f7860e);
+  asm volatile("vfmul.vf v1, v2, %[A]" ::[A] "f"(dscalar_64));
+  //               0.2666240605464688,  0.1990658129048941, -0.2711972651602534,
+  //               0.4691198042056620,  0.5687688649941168, -0.0888312017870367,
+  //               0.7605551223815086, -0.0814371353413154,  0.1087791670362886,
+  //               0.7453831118261137,  0.2153197802278006, -0.2855478187000574,
+  //               0.4892273033748624, -0.4938320315983399, -0.2177547636180751,
+  //               0.3248301698615385
+  VCMP_U64(9, v1, 0x3fd1105e5d17ec76, 0x3fc97afd1216ce6e, 0xbfd15b4bc6282ffc,
+           0x3fde060f123e080e, 0x3fe2335ac3443fa9, 0xbfb6bda4428a29bb,
+           0x3fe85677b22de228, 0xbfb4d91068f88b49, 0x3fbbd8f394e82fe7,
+           0x3fe7da2daf091575, 0x3fcb8f993b2151e0, 0xbfd2466a5bb0b251,
+           0x3fdf4f8009138a1b, 0xbfdf9af1aa5ba7aa, 0xbfcbdf635a24d80a,
+           0x3fd4ca047b13cdbf);
+};
+
+// Simple random test with similar values (vector-scalar) (masked)
+void TEST_CASE4(void) {
+  VSET(16, e16, m1);
+  //               -0.8423,  0.9531,  0.3889, -0.3704, -0.9731, -0.4636,
+  //               -0.4797, -0.5903,  0.2959,  0.4685, -0.3660,  0.3167,
+  //               -0.9766,  0.0052, -0.6489, -0.0474
+  VLOAD_16(v2, 0xbabd, 0x3ba0, 0x3639, 0xb5ed, 0xbbc9, 0xb76b, 0xb7ad, 0xb8b9,
+           0x34bc, 0x377f, 0xb5db, 0x3511, 0xbbd0, 0x1d48, 0xb931, 0xaa11);
+  double dscalar_16;
+  //                              0.2971
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0x34c1);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfmul.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_16));
+  //                0.0000,  0.2832,  0.0000, -0.1100,  0.0000, -0.1377, 0.0000,
+  //                -0.1754,  0.0000,  0.1392,  0.0000,  0.0941,  0.0000,
+  //                0.0015,  0.0000, -0.0141
+  VCMP_U16(10, v1, 0x0, 0x3488, 0x0, 0xaf0b, 0x0, 0xb068, 0x0, 0xb19d, 0x0,
+           0x3074, 0x0, 0x2e05, 0x0, 0x1647, 0x0, 0xa336);
+
+  VSET(16, e32, m1);
+  //               -0.11454447, -0.46133029,  0.06972761,  0.20429718,
+  //               -0.97134608, -0.95719630, -0.11250938,  0.48455358,
+  //               0.59656250,  0.46462929,  0.13447689, -0.32035729,
+  //               0.75118428,  0.90634471,  0.73552424, -0.53555632
+  VLOAD_32(v2, 0xbdea964b, 0xbeec337c, 0x3d8ecd5a, 0x3e513348, 0xbf78aa23,
+           0xbf750ad1, 0xbde66b52, 0x3ef81768, 0x3f18b852, 0x3eede3e4,
+           0x3e09b44f, 0xbea405df, 0x3f404d9d, 0x3f680635, 0x3f3c4b51,
+           0xbf091a38);
+  double dscalar_32;
+  //                               0.94017404
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0x3f70af3f);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfmul.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_32));
+  //                0.00000000, -0.43373078,  0.00000000,  0.19207491,
+  //                0.00000000, -0.89993113,  0.00000000,  0.45556471,
+  //                0.00000000,  0.43683240,  0.00000000, -0.30119160,
+  //                0.00000000,  0.85212177,  0.00000000, -0.50351614
+  VCMP_U32(11, v1, 0x0, 0xbede11f6, 0x0, 0x3e44af49, 0x0, 0xbf6661e3, 0x0,
+           0x3ee93fc7, 0x0, 0x3edfa87f, 0x0, 0xbe9a35c9, 0x0, 0x3f5a24a7, 0x0,
+           0xbf00e66f);
+
+  VSET(16, e64, m1);
+  //                -0.3344965024132001, -0.2497404698970234,
+  //                0.3402338726452623, -0.5885400342262450,
+  //                -0.7135559920290824,  0.1114442794173345,
+  //                -0.9541638058007114,  0.1021679621951177,
+  //                -0.1364702451627324, -0.9351295729000717,
+  //                -0.2701320849999789,  0.3582375365191053,
+  //                -0.6137661452178358,  0.6195430637830983,
+  //                0.2731869234335833, -0.4075196944877124
+  VLOAD_64(v2, 0xbfd56864049f6dd8, 0xbfcff77ee7590278, 0x3fd5c6644b002e60,
+           0xbfe2d551e8ec6e20, 0xbfe6d573603426e0, 0x3fbc879cbf6c7a10,
+           0xbfee8882889e1c44, 0x3fba27adf853b5f0, 0xbfc177db63eceed0,
+           0xbfedec94daa41aac, 0xbfd149d815ab3680, 0x3fd6ed5d21e3257c,
+           0xbfe3a3f8e623486e, 0x3fe3d34bf9ad2f82, 0x3fd17be50175e4e8,
+           0xbfda14cd7c133da0);
+  double dscalar_64;
+  //                               -0.7970907277742201
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0xbfe981c469f7860e);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfmul.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_64));
+  //                0.0000000000000000,  0.1990658129048941, 0.0000000000000000,
+  //                0.4691198042056620,  0.0000000000000000,
+  //                -0.0888312017870367,  0.0000000000000000,
+  //                -0.0814371353413154,  0.0000000000000000,
+  //                0.7453831118261137,  0.0000000000000000,
+  //                -0.2855478187000574,  0.0000000000000000,
+  //                -0.4938320315983399,  0.0000000000000000, 0.3248301698615385
+  VCMP_U64(12, v1, 0x0, 0x3fc97afd1216ce6e, 0x0, 0x3fde060f123e080e, 0x0,
+           0xbfb6bda4428a29bb, 0x0, 0xbfb4d91068f88b49, 0x0, 0x3fe7da2daf091575,
+           0x0, 0xbfd2466a5bb0b251, 0x0, 0xbfdf9af1aa5ba7aa, 0x0,
+           0x3fd4ca047b13cdbf);
+};
+
+int main(void) {
+  enable_vec();
+  enable_fp();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vfmv.c b/apps/riscv-tests/isa/rv64uv/vfmv.c
new file mode 100644
index 0000000..4f5cb63
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vfmv.c
@@ -0,0 +1,68 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+//         Matteo Perotti <mperotti@student.ethz.ch>
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //                            -0.9380
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0xbb81);
+  VCLEAR(v1);
+  asm volatile("vfmv.v.f v1, %[A]" ::[A] "f"(dscalar_16));
+  //              -0.9380, -0.9380, -0.9380, -0.9380, -0.9380, -0.9380, -0.9380,
+  //              -0.9380, -0.9380, -0.9380, -0.9380, -0.9380, -0.9380, -0.9380,
+  //              -0.9380, -0.9380
+  VCMP_U16(1, v1, 0xbb81, 0xbb81, 0xbb81, 0xbb81, 0xbb81, 0xbb81, 0xbb81,
+           0xbb81, 0xbb81, 0xbb81, 0xbb81, 0xbb81, 0xbb81, 0xbb81, 0xbb81,
+           0xbb81);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                             -0.96056187
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0xbf75e762);
+  VCLEAR(v1);
+  asm volatile("vfmv.v.f v1, %[A]" ::[A] "f"(dscalar_32));
+  //               -0.96056187, -0.96056187, -0.96056187, -0.96056187,
+  //               -0.96056187, -0.96056187, -0.96056187, -0.96056187,
+  //               -0.96056187, -0.96056187, -0.96056187, -0.96056187,
+  //               -0.96056187, -0.96056187, -0.96056187, -0.96056187
+  VCMP_U32(2, v1, 0xbf75e762, 0xbf75e762, 0xbf75e762, 0xbf75e762, 0xbf75e762,
+           0xbf75e762, 0xbf75e762, 0xbf75e762, 0xbf75e762, 0xbf75e762,
+           0xbf75e762, 0xbf75e762, 0xbf75e762, 0xbf75e762, 0xbf75e762,
+           0xbf75e762);
+
+  VSET(16, e64, m1);
+  double dscalar_64;
+  //                               0.9108707261227378
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0x3fed25da5d7296fe);
+  VCLEAR(v1);
+  asm volatile("vfmv.v.f v1, %[A]" ::[A] "f"(dscalar_64));
+  //                0.9108707261227378,  0.9108707261227378, 0.9108707261227378,
+  //                0.9108707261227378,  0.9108707261227378, 0.9108707261227378,
+  //                0.9108707261227378,  0.9108707261227378, 0.9108707261227378,
+  //                0.9108707261227378,  0.9108707261227378, 0.9108707261227378,
+  //                0.9108707261227378,  0.9108707261227378, 0.9108707261227378,
+  //                0.9108707261227378
+  VCMP_U64(3, v1, 0x3fed25da5d7296fe, 0x3fed25da5d7296fe, 0x3fed25da5d7296fe,
+           0x3fed25da5d7296fe, 0x3fed25da5d7296fe, 0x3fed25da5d7296fe,
+           0x3fed25da5d7296fe, 0x3fed25da5d7296fe, 0x3fed25da5d7296fe,
+           0x3fed25da5d7296fe, 0x3fed25da5d7296fe, 0x3fed25da5d7296fe,
+           0x3fed25da5d7296fe, 0x3fed25da5d7296fe, 0x3fed25da5d7296fe,
+           0x3fed25da5d7296fe);
+};
+
+int main(void) {
+  enable_vec();
+  enable_fp();
+
+  TEST_CASE1();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vfmvfs.c b/apps/riscv-tests/isa/rv64uv/vfmvfs.c
new file mode 100644
index 0000000..25b339d
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vfmvfs.c
@@ -0,0 +1,90 @@
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+double scalar_16b;
+float scalar_32b;
+double scalar_64b;
+
+void TEST_CASE1() {
+  BOX_HALF_IN_DOUBLE(scalar_16b, 0);
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 0xbb1e, 0xb573, 0x39dc, 0xb97a, 0xb4c0, 0xba31, 0x3897, 0x36ee,
+           0x3b27, 0xb7d7, 0x36c0, 0x376c, 0x395b, 0x3703, 0x3057, 0x0001);
+  asm volatile("vfmv.f.s %0, v1" : "=f"(scalar_16b));
+  XCMP(1, *((uint16_t *)&scalar_16b), 0xbb1e);
+
+  scalar_32b = 0;
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 0xbe9451b0, 0x3ece4bf7, 0x3eadc098, 0x3f09f4f0, 0x3ecc80cc,
+           0xbe8a42c5, 0x3f47fd31, 0xbe201365, 0xbeffeb17, 0xbf314e2e,
+           0xbd0a9c78, 0xbf1fb51f, 0x3b5e1209, 0x3eac9a73, 0xbeb187b6,
+           0x3dea828d);
+  asm volatile("vfmv.f.s %0, v1" : "=f"(scalar_32b));
+  XCMP(2, *((uint32_t *)&scalar_32b), 0xbe9451b0);
+
+  scalar_64b = 0;
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 0xbfe8d9d3f67536d2, 0x3fdad9e3e9cdd5bc, 0xbfd90875fda29450,
+           0x3fe62686e0339faa, 0x3fe2208e74273f2c, 0xbfc21587add90b50,
+           0xbfc7a755744afe30, 0xbfdf67da0cc99808, 0xbfed4488f52c57bc,
+           0xbfe6d19a966debbe, 0xbfe1a7778d7c344c, 0xbfdae653f20dd9d4,
+           0x3fe4c26b0962c342, 0xbfe2053afd5a822c, 0xbfb9851b4a2e8ff0,
+           0xbfdc0cda147fbe5c);
+  asm volatile("vfmv.f.s %0, v1" : "=f"(scalar_64b));
+  XCMP(3, *((uint64_t *)&scalar_64b), 0xbfe8d9d3f67536d2);
+}
+
+// Check special cases
+void TEST_CASE2() {
+  scalar_64b = 0;
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 0xbfe8d9d3f67536d2, 0x3fdad9e3e9cdd5bc, 0xbfd90875fda29450,
+           0x3fe62686e0339faa, 0x3fe2208e74273f2c, 0xbfc21587add90b50,
+           0xbfc7a755744afe30, 0xbfdf67da0cc99808, 0xbfed4488f52c57bc,
+           0xbfe6d19a966debbe, 0xbfe1a7778d7c344c, 0xbfdae653f20dd9d4,
+           0x3fe4c26b0962c342, 0xbfe2053afd5a822c, 0xbfb9851b4a2e8ff0,
+           0xbfdc0cda147fbe5c);
+  VSET(16, e64, m8);
+  asm volatile("vfmv.f.s %0, v1" : "=f"(scalar_64b));
+  XCMP(4, *((uint64_t *)&scalar_64b), 0xbfe8d9d3f67536d2);
+
+  scalar_64b = 0;
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 0xbfe8d9d3f67536d2, 0x3fdad9e3e9cdd5bc, 0xbfd90875fda29450,
+           0x3fe62686e0339faa, 0x3fe2208e74273f2c, 0xbfc21587add90b50,
+           0xbfc7a755744afe30, 0xbfdf67da0cc99808, 0xbfed4488f52c57bc,
+           0xbfe6d19a966debbe, 0xbfe1a7778d7c344c, 0xbfdae653f20dd9d4,
+           0x3fe4c26b0962c342, 0xbfe2053afd5a822c, 0xbfb9851b4a2e8ff0,
+           0xbfdc0cda147fbe5c);
+  VSET_ZERO(e64, m1);
+  asm volatile("vfmv.f.s %0, v1" : "=f"(scalar_64b));
+  XCMP(5, *((uint64_t *)&scalar_64b), 0xbfe8d9d3f67536d2);
+
+  scalar_64b = 0;
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 0xbfe8d9d3f67536d2, 0x3fdad9e3e9cdd5bc, 0xbfd90875fda29450,
+           0x3fe62686e0339faa, 0x3fe2208e74273f2c, 0xbfc21587add90b50,
+           0xbfc7a755744afe30, 0xbfdf67da0cc99808, 0xbfed4488f52c57bc,
+           0xbfe6d19a966debbe, 0xbfe1a7778d7c344c, 0xbfdae653f20dd9d4,
+           0x3fe4c26b0962c342, 0xbfe2053afd5a822c, 0xbfb9851b4a2e8ff0,
+           0xbfdc0cda147fbe5c);
+  VSET_ZERO(e64, m8);
+  asm volatile("vfmv.f.s %0, v1" : "=f"(scalar_64b));
+  XCMP(6, *((uint64_t *)&scalar_64b), 0xbfe8d9d3f67536d2);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vfmvsf.c b/apps/riscv-tests/isa/rv64uv/vfmvsf.c
new file mode 100644
index 0000000..5a751ed
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vfmvsf.c
@@ -0,0 +1,69 @@
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+double scalar_16b;
+float scalar_32b;
+double scalar_64b;
+
+void TEST_CASE1() {
+  BOX_HALF_IN_DOUBLE(scalar_16b, 0xbb1e);
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vfmv.s.f v1, %0" ::"f"(scalar_16b));
+  VCMP_U16(1, v1, *((uint16_t *)&scalar_16b));
+
+  scalar_32b = 0xbe9451b0;
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vfmv.s.f v1, %0" ::"f"(scalar_32b));
+  VCMP_U32(2, v1, *((uint32_t *)&scalar_32b));
+
+  scalar_64b = 0xbfe8d9d3f67536d2;
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vfmv.s.f v1, %0" ::"f"(scalar_64b));
+  VCMP_U64(3, v1, *((uint64_t *)&scalar_64b));
+}
+
+// Check special cases
+void TEST_CASE2() {
+  scalar_64b = 0xbfe8d9d3f67536d2;
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VSET(16, e64, m8);
+  asm volatile("vfmv.s.f v1, %0" ::"f"(scalar_64b));
+  VSET(1, e64, m1);
+  VCMP_U64(4, v1, *((uint64_t *)&scalar_64b));
+
+  scalar_64b = 0xbfe8d9d3f67536d2;
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VSET_ZERO(e64, m1);
+  asm volatile("vfmv.s.f v1, %0" ::"f"(scalar_64b));
+  VSET(1, e64, m1);
+  VCMP_U64(5, v1, 1);
+
+  scalar_64b = 0xbfe8d9d3f67536d2;
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VSET_ZERO(e64, m8);
+  asm volatile("vfmv.s.f v1, %0" ::"f"(scalar_64b));
+  VSET(1, e64, m1);
+  VCMP_U64(6, v1, 1);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vfncvt.c b/apps/riscv-tests/isa/rv64uv/vfncvt.c
new file mode 100644
index 0000000..19563ba
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vfncvt.c
@@ -0,0 +1,773 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+/////////////////
+// vfncvt.xu.f //
+/////////////////
+
+// Simple random test with similar values
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  //                9165.669,   5488.131,  -1648.302,  80154.047,   7163.093,
+  //                -6826.076,  -6976.746,   2675.899,   9587.624, -3671.810,
+  //                3611.960, -9086.531, -5333.617, -3284.205,   5676.141,
+  //                -8293.472
+  VLOAD_32(v2, 0x460f36ad, 0x45ab810c, 0x479c8d06, 0xc59cf316, 0x45dfd8be,
+           0xc5d5509c, 0xc5da05f8, 0x45273e62, 0x4615ce7f, 0xc5657cf5,
+           0x4561bf5b, 0xc60dfa20, 0xc5a6acf0, 0xc54d4347, 0x45b16120,
+           0xc60195e3);
+  asm volatile("vfncvt.xu.f.w v4, v2");
+  //                    9166,       5488,      65535,          0,       7163, 0,
+  //                    0,       2676,       9588,          0,       3612, 0, 0,
+  //                    0,       5676,          0
+  VCMP_U16(1, v4, 0x23ce, 0x1570, 0xffff, 0x0000, 0x1bfb, 0x0000, 0x0000,
+           0x0a74, 0x2574, 0x0000, 0x0e1c, 0x0000, 0x0000, 0x0000, 0x162c,
+           0x0000);
+
+  VSET(16, e32, m1);
+  //              -3508862.563,   1678202.418, -799491.756,   1707676.429,
+  //              -5056868.769,   4282070.604,   458667.918,   8393053.957,
+  //              -4485003.775, -5016427.098, -9086965.507, -6796529.257,
+  //              -7756776.890, -1173384.460,   4850684.145,   8658279.578
+  VLOAD_64(v2, 0xc14ac53f4813ac38, 0x41399b7a6ae9e42f, 0xc128660783332e44,
+           0x413a0e9c6ddfa609, 0xc1534a59313a407b, 0x415055b5a6a655de,
+           0x411bfeafabb28b3f, 0x4160022bbe9fc5e9, 0xc1511be2f1a1ac8b,
+           0xc15322dac64b7c31, 0xc16154feb0372db3, 0xc159ed3c506ab6eb,
+           0xc15d96fa38fb0400, 0xc131e78875bc4ace, 0x415280ff09493a97,
+           0x416083acf280b61e);
+  asm volatile("vfncvt.xu.f.w v4, v2");
+  //                           0,        1678202,              0, 1707676, 0,
+  //                           4282071,         458668,        8393054, 0, 0, 0,
+  //                           0,              0,              0, 4850684,
+  //                           8658280
+  VCMP_U32(2, v4, 0x00000000, 0x00199b7a, 0x00000000, 0x001a0e9c, 0x00000000,
+           0x004156d7, 0x0006ffac, 0x0080115e, 0x00000000, 0x00000000,
+           0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x004a03fc,
+           0x00841d68);
+};
+
+// Simple random test with similar values (masked)
+// The numbers are the same of TEST_CASE1
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  //                    9165.669,       5488.131,      -1648.302, -5022.386,
+  //                    7163.093, -6826.076, -6976.746,   2675.899,   9587.624,
+  //                    -3671.810,   3611.960, -9086.531, -5333.617, -3284.205,
+  //                    5676.141, -8293.472
+  VLOAD_32(v2, 0x460f36ad, 0x45ab810c, 0xc4ce09ad, 0xc59cf316, 0x45dfd8be,
+           0xc5d5509c, 0xc5da05f8, 0x45273e62, 0x4615ce7f, 0xc5657cf5,
+           0x4561bf5b, 0xc60dfa20, 0xc5a6acf0, 0xc54d4347, 0x45b16120,
+           0xc60195e3);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfncvt.xu.f.w v4, v2, v0.t");
+  //                       0,       5488,          0,          0,          0, 0,
+  //                       0,       2676,          0,          0,          0, 0,
+  //                       0,          0,          0,          0
+  VCMP_U16(3, v4, 0x0000, 0x1570, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+           0x0a74, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+           0x0000);
+
+  VSET(16, e32, m1);
+  //                        -3508862.563,            1678202.418, -799491.756,
+  //                        1707676.429, -5056868.769,   4282070.604,
+  //                        458667.918,   8393053.957, -4485003.775,
+  //                        -5016427.098, -9086965.507, -6796529.257,
+  //                        -7756776.890, -1173384.460,   4850684.145,
+  //                        8658279.578
+  VLOAD_64(v2, 0xc14ac53f4813ac38, 0x41399b7a6ae9e42f, 0xc128660783332e44,
+           0x413a0e9c6ddfa609, 0xc1534a59313a407b, 0x415055b5a6a655de,
+           0x411bfeafabb28b3f, 0x4160022bbe9fc5e9, 0xc1511be2f1a1ac8b,
+           0xc15322dac64b7c31, 0xc16154feb0372db3, 0xc159ed3c506ab6eb,
+           0xc15d96fa38fb0400, 0xc131e78875bc4ace, 0x415280ff09493a97,
+           0x416083acf280b61e);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfncvt.xu.f.w v4, v2, v0.t");
+  //                           0,        1678202,              0, 1707676, 0,
+  //                           4282071,              0,        8393054, 0, 0, 0,
+  //                           0,              0,              0, 0, 8658280
+  VCMP_U32(4, v4, 0x00000000, 0x00199b7a, 0x00000000, 0x001a0e9c, 0x00000000,
+           0x004156d7, 0x00000000, 0x0080115e, 0x00000000, 0x00000000,
+           0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+           0x00841d68);
+};
+
+////////////////
+// vfncvt.x.f //
+////////////////
+
+// Simple random test with similar values
+void TEST_CASE3(void) {
+  VSET(16, e16, m1);
+  //              -7808.056,   9317.408,   1685.891,   3975.596, -5978.108,
+  //              9676.333,   6963.966,   3589.870, -4334.772, -3261.309,
+  //              -2340.480,   6085.075,   4043.322,   2827.902,   4389.497,
+  //              -5196.684
+  VLOAD_32(v2, 0xc5f40072, 0x461195a2, 0x44d2bc86, 0x4578798a, 0xc5bad0dd,
+           0x46173155, 0x45d99fbb, 0x45605ded, 0xc587762e, 0xc54bd4f0,
+           0xc51247af, 0x45be2899, 0x457cb528, 0x4530be6f, 0x45892bfa,
+           0xc5a26578);
+  asm volatile("vfncvt.x.f.w v4, v2");
+  //                   -7808,       9317,       1686,       3976,      -5978,
+  //                   9676,       6964,       3590,      -4335,      -3261,
+  //                   -2340,       6085,       4043,       2828,       4389,
+  //                   -5197
+  VCMP_U16(5, v4, 0xe180, 0x2465, 0x0696, 0x0f88, 0xe8a6, 0x25cc, 0x1b34,
+           0x0e06, 0xef11, 0xf343, 0xf6dc, 0x17c5, 0x0fcb, 0x0b0c, 0x1125,
+           0xebb3);
+
+  VSET(16, e32, m1);
+  //                5365665.770, -7563846.858,   8056193.411, -2468299.255,
+  //                -9624608.750, -6974543.165,   5868078.422, -5387798.170,
+  //                3847378.080,   1368753.124,   4380497.931, -8044304.268,
+  //                1687738.849,   3753399.509, -3684410.483, -7416477.444
+  VLOAD_64(v2, 0x415477e8714aea69, 0xc15cda91b6eefd56, 0x415ebb605a479cd5,
+           0xc142d4e5a0a1f367, 0xc1625b841802ee1d, 0xc15a9b13ca8c7bb6,
+           0x4156628b9afacdc9, 0xc1548d858ae6df86, 0x414d5a690a2dbb5e,
+           0x4134e2b11fa8e994, 0x4150b5d47b9c3df2, 0xc15eafc4112995f5,
+           0x4139c0bad971859a, 0x414ca2dbc1288a12, 0xc14c1c1d3dcd1b39,
+           0xc15c4aa75c6c5635);
+  asm volatile("vfncvt.x.f.w v4, v2");
+  //                     5365666,       -7563847,        8056193, -2468299,
+  //                     -9624609,       -6974543,        5868078, -5387798,
+  //                     3847378,        1368753,        4380498, -8044304,
+  //                     1687739,        3753400,       -3684410,       -7416477
+  VCMP_U32(6, v4, 0x0051dfa2, 0xff8c95b9, 0x007aed81, 0xffda5635, 0xff6d23df,
+           0xff9593b1, 0x00598a2e, 0xffadc9ea, 0x003ab4d2, 0x0014e2b1,
+           0x0042d752, 0xff8540f0, 0x0019c0bb, 0x003945b8, 0xffc7c7c6,
+           0xff8ed563);
+};
+
+// Simple random test with similar values (masked)
+// The numbers are the same of TEST_CASE1
+void TEST_CASE4(void) {
+  VSET(16, e16, m1);
+  //              -7808.056,   9317.408,   1685.891,   3975.596, -5978.108,
+  //              9676.333,   6963.966,   3589.870, -4334.772, -3261.309,
+  //              -2340.480,   6085.075,   4043.322,   2827.902,   4389.497,
+  //              -5196.684
+  VLOAD_32(v2, 0xc5f40072, 0x461195a2, 0x44d2bc86, 0x4578798a, 0xc5bad0dd,
+           0x46173155, 0x45d99fbb, 0x45605ded, 0xc587762e, 0xc54bd4f0,
+           0xc51247af, 0x45be2899, 0x457cb528, 0x4530be6f, 0x45892bfa,
+           0xc5a26578);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfncvt.x.f.w v4, v2, v0.t");
+  //                       0,       9317,          0,       3976,          0,
+  //                       9676,          0,       3590,          0,      -3261,
+  //                       0,       6085,          0,       2828,          0,
+  //                       -5197
+  VCMP_U16(7, v4, 0x0000, 0x2465, 0x0000, 0x0f88, 0x0000, 0x25cc, 0x0000,
+           0x0e06, 0x0000, 0xf343, 0x0000, 0x17c5, 0x0000, 0x0b0c, 0x0000,
+           0xebb3);
+
+  VSET(16, e32, m1);
+  //                5365665.770, -7563846.858,   8056193.411, -2468299.255,
+  //                -9624608.750, -6974543.165,   5868078.422, -5387798.170,
+  //                3847378.080,   1368753.124,   4380497.931, -8044304.268,
+  //                1687738.849,   3753399.509, -3684410.483, -7416477.444
+  VLOAD_64(v2, 0x415477e8714aea69, 0xc15cda91b6eefd56, 0x415ebb605a479cd5,
+           0xc142d4e5a0a1f367, 0xc1625b841802ee1d, 0xc15a9b13ca8c7bb6,
+           0x4156628b9afacdc9, 0xc1548d858ae6df86, 0x414d5a690a2dbb5e,
+           0x4134e2b11fa8e994, 0x4150b5d47b9c3df2, 0xc15eafc4112995f5,
+           0x4139c0bad971859a, 0x414ca2dbc1288a12, 0xc14c1c1d3dcd1b39,
+           0xc15c4aa75c6c5635);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfncvt.x.f.w v4, v2, v0.t");
+  //                           0,       -7563847,              0, -2468299, 0,
+  //                           -6974543,              0,       -5387798, 0,
+  //                           1368753,              0,       -8044304, 0,
+  //                           3753400,              0,       -7416477
+  VCMP_U32(8, v4, 0x00000000, 0xff8c95b9, 0x00000000, 0xffda5635, 0x00000000,
+           0xff9593b1, 0x00000000, 0xffadc9ea, 0x00000000, 0x0014e2b1,
+           0x00000000, 0xff8540f0, 0x00000000, 0x003945b8, 0x00000000,
+           0xff8ed563);
+};
+
+/////////////////////
+// vfncvt.rtz.xu.f //
+/////////////////////
+
+// Simple random test with similar values
+void TEST_CASE5(void) {
+  VSET(16, e16, m1);
+  //              -9750.252, -4363.736, -2345.615,   6996.062, -7115.004,
+  //              6670.171, -4079.234, -1773.082,   254.350,   53.058,
+  //              -9041.926, -8137.022,   1522.146,   198.516, -920.430,
+  //              2857.583
+  VLOAD_32(v2, 0xc6185902, 0xc5885de3, 0xc51299d6, 0x45daa07e, 0xc5de5808,
+           0x45d0715e, 0xc57ef3bf, 0xc4dda29c, 0x437e5998, 0x42543afb,
+           0xc60d47b4, 0xc5fe482e, 0x44be44af, 0x43468433, 0xc4661b8b,
+           0x45329953);
+  asm volatile("vfncvt.rtz.xu.f.w v4, v2");
+  //                       0,          0,          0,       6996,          0,
+  //                       6670,          0,          0,        254,         53,
+  //                       0,          0,       1522,        198,          0,
+  //                       2857
+  VCMP_U16(9, v4, 0x0000, 0x0000, 0x0000, 0x1b54, 0x0000, 0x1a0e, 0x0000,
+           0x0000, 0x00fe, 0x0035, 0x0000, 0x0000, 0x05f2, 0x00c6, 0x0000,
+           0x0b29);
+
+  VSET(16, e32, m1);
+  //              -8404683.758,   3627605.540, -4368861.865, -2883871.623,
+  //              5750957.328, -7243911.338, -8202847.045,   5348152.868,
+  //              9957770.965,   8018962.598, -8478197.842, -9780786.953,
+  //              184470.081,   250336.923, -6517203.475, -7691903.192
+  VLOAD_64(v2, 0xc16007d978438b7f, 0x414bad2ac51eade4, 0xc150aa777763eeda,
+           0xc146008fcfc2093b, 0x4155f02b54fbd105, 0xc15ba221d5a4f5c3,
+           0xc15f4a97c2e2daa6, 0x415466ce378e9269, 0x4162fe315edeecec,
+           0x415e9704a64d845e, 0xc1602bbebaf40bb8, 0xc162a7c65e8002a9,
+           0x410684b0a4ee482d, 0x410e8f07623ffd06, 0xc158dc74de617fbc,
+           0xc15d579fcc41ba16);
+  asm volatile("vfncvt.rtz.xu.f.w v4, v2");
+  //                           0,        3627605,              0, 0, 5750957, 0,
+  //                           0,        5348152,        9957770, 8018962, 0, 0,
+  //                           184470,         250336,              0, 0
+  VCMP_U32(10, v4, 0x00000000, 0x00375a55, 0x00000000, 0x00000000, 0x0057c0ad,
+           0x00000000, 0x00000000, 0x00519b38, 0x0097f18a, 0x007a5c12,
+           0x00000000, 0x00000000, 0x0002d096, 0x0003d1e0, 0x00000000,
+           0x00000000);
+};
+
+// Simple random test with similar values (masked)
+// The numbers are the same of TEST_CASE1
+void TEST_CASE6(void) {
+  VSET(16, e16, m1);
+  //              -9750.252, -4363.736, -2345.615,   6996.062, -7115.004,
+  //              6670.171, -4079.234, -1773.082,   254.350,   53.058,
+  //              -9041.926, -8137.022,   1522.146,   198.516, -920.430,
+  //              2857.583
+  VLOAD_32(v2, 0xc6185902, 0xc5885de3, 0xc51299d6, 0x45daa07e, 0xc5de5808,
+           0x45d0715e, 0xc57ef3bf, 0xc4dda29c, 0x437e5998, 0x42543afb,
+           0xc60d47b4, 0xc5fe482e, 0x44be44af, 0x43468433, 0xc4661b8b,
+           0x45329953);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfncvt.rtz.xu.f.w v4, v2, v0.t");
+  //                       0,          0,          0,       6996,          0,
+  //                       6670,          0,          0,          0,         53,
+  //                       0,          0,          0,        198,          0,
+  //                       2857
+  VCMP_U16(11, v4, 0x0000, 0x0000, 0x0000, 0x1b54, 0x0000, 0x1a0e, 0x0000,
+           0x0000, 0x0000, 0x0035, 0x0000, 0x0000, 0x0000, 0x00c6, 0x0000,
+           0x0b29);
+
+  VSET(16, e32, m1);
+  //              -8404683.758,   3627605.540, -4368861.865, -2883871.623,
+  //              5750957.328, -7243911.338, -8202847.045,   5348152.868,
+  //              9957770.965,   8018962.598, -8478197.842, -9780786.953,
+  //              184470.081,   250336.923, -6517203.475, -7691903.192
+  VLOAD_64(v2, 0xc16007d978438b7f, 0x414bad2ac51eade4, 0xc150aa777763eeda,
+           0xc146008fcfc2093b, 0x4155f02b54fbd105, 0xc15ba221d5a4f5c3,
+           0xc15f4a97c2e2daa6, 0x415466ce378e9269, 0x4162fe315edeecec,
+           0x415e9704a64d845e, 0xc1602bbebaf40bb8, 0xc162a7c65e8002a9,
+           0x410684b0a4ee482d, 0x410e8f07623ffd06, 0xc158dc74de617fbc,
+           0xc15d579fcc41ba16);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfncvt.rtz.xu.f.w v4, v2, v0.t");
+  //                           0,        3627605,              0, 0, 0, 0, 0,
+  //                           5348152,              0,        8018962, 0, 0, 0,
+  //                           250336,              0,              0
+  VCMP_U32(12, v4, 0x00000000, 0x00375a55, 0x00000000, 0x00000000, 0x00000000,
+           0x00000000, 0x00000000, 0x00519b38, 0x00000000, 0x007a5c12,
+           0x00000000, 0x00000000, 0x00000000, 0x0003d1e0, 0x00000000,
+           0x00000000);
+};
+
+////////////////////
+// vfncvt.rtz.x.f //
+////////////////////
+
+// Simple random test with similar values
+void TEST_CASE7(void) {
+  VSET(16, e16, m1);
+  //                9352.418, -5719.459,   4617.815, -3012.009, -3597.063,
+  //                -5717.140, -3327.545,   1286.004,   1797.767,   3842.966,
+  //                -2148.369, -7283.256,   8783.331, -7958.880, -6728.271,
+  //                4727.792
+  VLOAD_32(v2, 0x461221ac, 0xc5b2bbac, 0x45904e86, 0xc53c4026, 0xc560d104,
+           0xc5b2a91e, 0xc54ff8b9, 0x44a0c01e, 0x44e0b88c, 0x45702f76,
+           0xc50645e9, 0xc5e39a0c, 0x46093d53, 0xc5f8b70a, 0xc5d2422c,
+           0x4593be56);
+  asm volatile("vfncvt.rtz.x.f.w v4, v2");
+  //                    9352,      -5719,       4617,      -3012,      -3597,
+  //                    -5717,      -3327,       1286,       1797,       3842,
+  //                    -2148,      -7283,       8783,      -7958,      -6728,
+  //                    4727
+  VCMP_U16(13, v4, 0x2488, 0xe9a9, 0x1209, 0xf43c, 0xf1f3, 0xe9ab, 0xf301,
+           0x0506, 0x0705, 0x0f02, 0xf79c, 0xe38d, 0x224f, 0xe0ea, 0xe5b8,
+           0x1277);
+
+  VSET(16, e32, m1);
+  //                1563546.261, -1988965.594,   6496092.888,   5054778.769,
+  //                9551708.952, -336377.787, -2352111.643,   4412162.570,
+  //                7087155.475,   338850.875,   2765611.498,   2723631.912,
+  //                -3252079.308,   1096915.326,   5492109.280, -7265880.245
+  VLOAD_64(v2, 0x4137db9a42b839bd, 0xc13e596598118127, 0x4158c7d738d1eec8,
+           0x4153484eb13573ed, 0x416237eb9e79d2a8, 0xc11487e725f1ce50,
+           0xc141f1f7d2451c3d, 0x4150d4c0a47be906, 0x415b090cde6b0575,
+           0x4114ae8b8081532d, 0x41451995bfc3bc74, 0x4144c797f4b307dd,
+           0xc148cfb7a76dea0f, 0x4130bcd353667e5d, 0x4154f36351f3a3c5,
+           0xc15bb7960fb007a5);
+  asm volatile("vfncvt.rtz.x.f.w v4, v2");
+  //                     1563546,       -1988965,        6496092, 5054778,
+  //                     9551708,        -336377,       -2352111, 4412162,
+  //                     7087155,         338850,        2765611, 2723631,
+  //                     -3252079,        1096915,        5492109, -7265880
+  VCMP_U32(14, v4, 0x0017db9a, 0xffe1a69b, 0x00631f5c, 0x004d213a, 0x0091bf5c,
+           0xfffade07, 0xffdc1c11, 0x00435302, 0x006c2433, 0x00052ba2,
+           0x002a332b, 0x00298f2f, 0xffce6091, 0x0010bcd3, 0x0053cd8d,
+           0xff9121a8);
+};
+
+// Simple random test with similar values (masked)
+// The numbers are the same of TEST_CASE1
+void TEST_CASE8(void) {
+  VSET(16, e16, m1);
+  //                9352.418, -5719.459,   4617.815, -3012.009, -3597.063,
+  //                -5717.140, -3327.545,   1286.004,   1797.767,   3842.966,
+  //                -2148.369, -7283.256,   8783.331, -7958.880, -6728.271,
+  //                4727.792
+  VLOAD_32(v2, 0x461221ac, 0xc5b2bbac, 0x45904e86, 0xc53c4026, 0xc560d104,
+           0xc5b2a91e, 0xc54ff8b9, 0x44a0c01e, 0x44e0b88c, 0x45702f76,
+           0xc50645e9, 0xc5e39a0c, 0x46093d53, 0xc5f8b70a, 0xc5d2422c,
+           0x4593be56);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfncvt.rtz.x.f.w v4, v2, v0.t");
+  //                       0,      -5719,          0,      -3012,          0,
+  //                       -5717,          0,       1286,          0, 3842, 0,
+  //                       -7283,          0,      -7958,          0,       4727
+  VCMP_U16(15, v4, 0x0000, 0xe9a9, 0x0000, 0xf43c, 0x0000, 0xe9ab, 0x0000,
+           0x0506, 0x0000, 0x0f02, 0x0000, 0xe38d, 0x0000, 0xe0ea, 0x0000,
+           0x1277);
+
+  VSET(16, e32, m1);
+  //                1563546.261, -1988965.594,   6496092.888,   5054778.769,
+  //                9551708.952, -336377.787, -2352111.643,   4412162.570,
+  //                7087155.475,   338850.875,   2765611.498,   2723631.912,
+  //                -3252079.308,   1096915.326,   5492109.280, -7265880.245
+  VLOAD_64(v2, 0x4137db9a42b839bd, 0xc13e596598118127, 0x4158c7d738d1eec8,
+           0x4153484eb13573ed, 0x416237eb9e79d2a8, 0xc11487e725f1ce50,
+           0xc141f1f7d2451c3d, 0x4150d4c0a47be906, 0x415b090cde6b0575,
+           0x4114ae8b8081532d, 0x41451995bfc3bc74, 0x4144c797f4b307dd,
+           0xc148cfb7a76dea0f, 0x4130bcd353667e5d, 0x4154f36351f3a3c5,
+           0xc15bb7960fb007a5);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfncvt.rtz.x.f.w v4, v2, v0.t");
+  //                           0,       -1988965,              0, 5054778, 0,
+  //                           -336377,              0,        4412162, 0,
+  //                           338850,              0,        2723631, 0,
+  //                           1096915,              0,       -7265880
+  VCMP_U32(16, v4, 0x00000000, 0xffe1a69b, 0x00000000, 0x004d213a, 0x00000000,
+           0xfffade07, 0x00000000, 0x00435302, 0x00000000, 0x00052ba2,
+           0x00000000, 0x00298f2f, 0x00000000, 0x0010bcd3, 0x00000000,
+           0xff9121a8);
+};
+
+/////////////////
+// vfncvt.f.xu //
+/////////////////
+
+// Simple random test with similar values
+void TEST_CASE9(void) {
+  VSET(16, e16, m1);
+  //                 4294964178,       5853,    4294962638,    4294962082, 4585,
+  //                 1637,       3984,    4294964217,       9553,    4294962615,
+  //                 4294962166,       9867,    4294958580,    4294966752, 5172,
+  //                 7478
+  VLOAD_32(v2, 0xfffff3d2, 0x000016dd, 0xffffedce, 0xffffeba2, 0x000011e9,
+           0x00000665, 0x00000f90, 0xfffff3f9, 0x00002551, 0xffffedb7,
+           0xffffebf6, 0x0000268b, 0xffffddf4, 0xfffffde0, 0x00001434,
+           0x00001d36);
+  asm volatile("vfncvt.f.xu.w v4, v2");
+  //                     inf,   5852.000,   inf,   inf,   4584.000,   1637.000,
+  //                     3984.000,   inf,   9552.000,   inf,   inf,   9864.000,
+  //                     inf,   inf,   5172.000,   7480.000
+  VCMP_U16(17, v4, 0x7c00, 0x6db7, 0x7c00, 0x7c00, 0x6c7a, 0x6665, 0x6bc8,
+           0x7c00, 0x70aa, 0x7c00, 0x7c00, 0x70d1, 0x7c00, 0x7c00, 0x6d0d,
+           0x6f4e);
+
+  VSET(16, e32, m1);
+  //                 18446744073704835106,    18446744073709117625,
+  //                 18446744073705901616,        2086515, 18446744073699655996,
+  //                 932771,         255753,        3148047,
+  //                 18446744073705977615,    18446744073704792883,
+  //                 18446744073704699584,        8685460, 18446744073709143843,
+  //                 18446744073703142874,        3905530, 18446744073704152149
+  VLOAD_64(v2, 0xffffffffffb80822, 0xfffffffffff960b9, 0xffffffffffc84e30,
+           0x00000000001fd673, 0xffffffffff69013c, 0x00000000000e3ba3,
+           0x000000000003e709, 0x000000000030090f, 0xffffffffffc9770f,
+           0xffffffffffb76333, 0xffffffffffb5f6c0, 0x0000000000848794,
+           0xfffffffffff9c723, 0xffffffffff9e35da, 0x00000000003b97fa,
+           0xffffffffffad9c55);
+  asm volatile("vfncvt.f.xu.w v4, v2");
+  //                18446744073709551616.000,   18446744073709551616.000,
+  //                18446744073709551616.000,   2086515.000,
+  //                18446744073709551616.000,   932771.000,   255753.000,
+  //                3148047.000,   18446744073709551616.000,
+  //                18446744073709551616.000,   18446744073709551616.000,
+  //                8685460.000,   18446744073709551616.000,
+  //                18446744073709551616.000,   3905530.000,
+  //                18446744073709551616.000
+  VCMP_U32(18, v4, 0x5f800000, 0x5f800000, 0x5f800000, 0x49feb398, 0x5f800000,
+           0x4963ba30, 0x4879c240, 0x4a40243c, 0x5f800000, 0x5f800000,
+           0x5f800000, 0x4b048794, 0x5f800000, 0x5f800000, 0x4a6e5fe8,
+           0x5f800000);
+};
+
+// Simple random test with similar values (masked)
+// The numbers are the same of TEST_CASE1
+void TEST_CASE10(void) {
+  VSET(16, e16, m1);
+  //                 4294964178,       5853,    4294962638,    4294962082, 4585,
+  //                 1637,       3984,    4294964217,       9553,    4294962615,
+  //                 4294962166,       9867,    4294958580,    4294966752, 5172,
+  //                 7478
+  VLOAD_32(v2, 0xfffff3d2, 0x000016dd, 0xffffedce, 0xffffeba2, 0x000011e9,
+           0x00000665, 0x00000f90, 0xfffff3f9, 0x00002551, 0xffffedb7,
+           0xffffebf6, 0x0000268b, 0xffffddf4, 0xfffffde0, 0x00001434,
+           0x00001d36);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfncvt.f.xu.w v4, v2, v0.t");
+  //                0.000,   5852.000,   0.000,   inf,   0.000,   1637.000,
+  //                0.000,   inf,   0.000,   inf,   0.000,   9864.000,   0.000,
+  //                inf,   0.000,   7480.000
+  VCMP_U16(19, v4, 0x0, 0x6db7, 0x0, 0x7c00, 0x0, 0x6665, 0x0, 0x7c00, 0x0,
+           0x7c00, 0x0, 0x70d1, 0x0, 0x7c00, 0x0, 0x6f4e);
+
+  VSET(16, e32, m1);
+  //                 18446744073704835106,    18446744073709117625,
+  //                 18446744073705901616,        2086515, 18446744073699655996,
+  //                 932771,         255753,        3148047,
+  //                 18446744073705977615,    18446744073704792883,
+  //                 18446744073704699584,        8685460, 18446744073709143843,
+  //                 18446744073703142874,        3905530, 18446744073704152149
+  VLOAD_64(v2, 0xffffffffffb80822, 0xfffffffffff960b9, 0xffffffffffc84e30,
+           0x00000000001fd673, 0xffffffffff69013c, 0x00000000000e3ba3,
+           0x000000000003e709, 0x000000000030090f, 0xffffffffffc9770f,
+           0xffffffffffb76333, 0xffffffffffb5f6c0, 0x0000000000848794,
+           0xfffffffffff9c723, 0xffffffffff9e35da, 0x00000000003b97fa,
+           0xffffffffffad9c55);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfncvt.f.xu.w v4, v2, v0.t");
+  //                0.000,   18446744073709551616.000,   0.000,   2086515.000,
+  //                0.000,   932771.000,   0.000,   3148047.000,   0.000,
+  //                18446744073709551616.000,   0.000,   8685460.000,   0.000,
+  //                18446744073709551616.000,   0.000, 18446744073709551616.000
+  VCMP_U32(20, v4, 0x0, 0x5f800000, 0x0, 0x49feb398, 0x0, 0x4963ba30, 0x0,
+           0x4a40243c, 0x0, 0x5f800000, 0x0, 0x4b048794, 0x0, 0x5f800000, 0x0,
+           0x5f800000);
+};
+
+////////////////
+// vfncvt.f.x //
+////////////////
+
+// Simple random test with similar values
+void TEST_CASE11(void) {
+  VSET(16, e16, m1);
+  //                       -6279,           3717,           9022, -8925, -5530,
+  //                       3851,       5592,      -3692,      -2747,       -748,
+  //                       -2621,      -9352,       4018,       3174, -6975,
+  //                       -4466
+  VLOAD_32(v2, 0xffffe779, 0x00000e85, 0x0000233e, 0xffffdd23, 0xffffea66,
+           0x00000f0b, 0x000015d8, 0xfffff194, 0xfffff545, 0xfffffd14,
+           0xfffff5c3, 0xffffdb78, 0x00000fb2, 0x00000c66, 0xffffe4c1,
+           0xffffee8e);
+  asm volatile("vfncvt.f.x.w v4, v2");
+  //                -6280.000,   3716.000,   9024.000,  -8928.000,  -5528.000,
+  //                3852.000,   5592.000, -3692.000, -2748.000, -748.000,
+  //                -2620.000, -9352.000,   4018.000,   3174.000, -6976.000,
+  //                -4464.000
+  VCMP_U16(21, v4, 0xee22, 0x6b42, 0x7068, 0xf05c, 0xed66, 0x6b86, 0x6d76,
+           0xeb36, 0xe95e, 0xe1d8, 0xe91e, 0xf091, 0x6bd9, 0x6a33, 0xeed0,
+           0xec5c);
+
+  VSET(16, e32, m1);
+  //                              757099,       -9365555,        3016973,
+  //                              -9277105,       -8350486,        -650348,
+  //                              -1775160,        4659116,         148573,
+  //                              4475248,       -2937762,        3310433,
+  //                              9151745,       -2201488,       -1506850,
+  //                              1593161
+  VLOAD_64(v2, 0x00000000000b8d6b, 0xffffffffff7117cd, 0x00000000002e090d,
+           0xffffffffff72714f, 0xffffffffff8094ea, 0xfffffffffff61394,
+           0xffffffffffe4e9c8, 0x00000000004717ac, 0x000000000002445d,
+           0x0000000000444970, 0xffffffffffd32c5e, 0x0000000000328361,
+           0x00000000008ba501, 0xffffffffffde6870, 0xffffffffffe901de,
+           0x0000000000184f49);
+  asm volatile("vfncvt.f.x.w v4, v2");
+  //                   757099.000, -9365555.000,   3016973.000, -9277105.000,
+  //                   -8350486.000, -650348.000, -1775160.000,   4659116.000,
+  //                   148573.000,   4475248.000, -2937762.000,   3310433.000,
+  //                   9151745.000, -2201488.000, -1506850.000,   1593161.000
+  VCMP_U32(22, v4, 0x4938d6b0, 0xcb0ee833, 0x4a382434, 0xcb0d8eb1, 0xcafed62c,
+           0xc91ec6c0, 0xc9d8b1c0, 0x4a8e2f58, 0x48111740, 0x4a8892e0,
+           0xca334e88, 0x4a4a0d84, 0x4b0ba501, 0xca065e40, 0xc9b7f110,
+           0x49c27a48);
+};
+
+// Simple random test with similar values (masked)
+// The numbers are the same of TEST_CASE1
+void TEST_CASE12(void) {
+  VSET(16, e16, m1);
+  //                   -6279,       3717,       9022,      -8925,      -5530,
+  //                   3851,       5592,      -3692,      -2747,       -748,
+  //                   -2621,      -9352,       4018,       3174,      -6975,
+  //                   -4466
+  VLOAD_32(v2, 0xffffe779, 0x00000e85, 0x0000233e, 0xffffdd23, 0xffffea66,
+           0x00000f0b, 0x000015d8, 0xfffff194, 0xfffff545, 0xfffffd14,
+           0xfffff5c3, 0xffffdb78, 0x00000fb2, 0x00000c66, 0xffffe4c1,
+           0xffffee8e);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfncvt.f.x.w v4, v2, v0.t");
+  //                0.000,   3716.000,   0.000, -8928.000,   0.000,   3852.000,
+  //                0.000, -3692.000,   0.000, -748.000,   0.000, -9352.000,
+  //                0.000,   3174.000,   0.000, -4464.000
+  VCMP_U16(23, v4, 0x0, 0x6b42, 0x0, 0xf05c, 0x0, 0x6b86, 0x0, 0xeb36, 0x0,
+           0xe1d8, 0x0, 0xf091, 0x0, 0x6a33, 0x0, 0xec5c);
+
+  VSET(16, e32, m1);
+  //                      757099,       -9365555,        3016973, -9277105,
+  //                      -8350486,        -650348,       -1775160, 4659116,
+  //                      148573,        4475248,       -2937762, 3310433,
+  //                      9151745,       -2201488,       -1506850, 1593161
+  VLOAD_64(v2, 0x00000000000b8d6b, 0xffffffffff7117cd, 0x00000000002e090d,
+           0xffffffffff72714f, 0xffffffffff8094ea, 0xfffffffffff61394,
+           0xffffffffffe4e9c8, 0x00000000004717ac, 0x000000000002445d,
+           0x0000000000444970, 0xffffffffffd32c5e, 0x0000000000328361,
+           0x00000000008ba501, 0xffffffffffde6870, 0xffffffffffe901de,
+           0x0000000000184f49);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfncvt.f.x.w v4, v2, v0.t");
+  //                0.000, -9365555.000,   0.000, -9277105.000,   0.000,
+  //                -650348.000,   0.000,   4659116.000,   0.000,   4475248.000,
+  //                0.000,   3310433.000,   0.000, -2201488.000,   0.000,
+  //                1593161.000
+  VCMP_U32(24, v4, 0x0, 0xcb0ee833, 0x0, 0xcb0d8eb1, 0x0, 0xc91ec6c0, 0x0,
+           0x4a8e2f58, 0x0, 0x4a8892e0, 0x0, 0x4a4a0d84, 0x0, 0xca065e40, 0x0,
+           0x49c27a48);
+};
+
+////////////////
+// vfncvt.f.f //
+////////////////
+
+// Simple random test with similar values
+void TEST_CASE13(void) {
+  VSET(16, e16, m1);
+  //              908.994, -6788.630, -5789.335, 8054.104, 3947.551, 9596.856,
+  //              2474.506, 3094.286, 7684.992, -6850.149, -54.922, 7737.443,
+  //              4171.873, 5266.611, 9163.839, 5679.187
+  VLOAD_32(v2, 0x44633fa3, 0xc5d4250b, 0xc5b4eaaf, 0x45fbb0d4, 0x4576b8d0,
+           0x4615f36d, 0x451aa818, 0x45416494, 0x45f027ef, 0xc5d61131,
+           0xc25bb026, 0x45f1cb8c, 0x45825efb, 0x45a494e4, 0x460f2f5b,
+           0x45b1797f);
+  asm volatile("vfncvt.f.f.w v4, v2");
+  //              909.000, -6788.000, -5788.000, 8056.000, 3948.000, 9600.000,
+  //              2474.000, 3094.000, 7684.000, -6852.000, -54.938, 7736.000,
+  //              4172.000, 5268.000, 9160.000, 5680.000
+  VCMP_U16(25, v4, 0x631a, 0xeea1, 0xeda7, 0x6fde, 0x6bb6, 0x70b0, 0x68d5,
+           0x6a0b, 0x6f81, 0xeeb1, 0xd2de, 0x6f8e, 0x6c13, 0x6d25, 0x7079,
+           0x6d8c);
+
+  VSET(16, e32, m1);
+  //              153431.766, -7796010.957, -6652812.196, 1049714.758,
+  //              7538298.328, -8731739.480, 537176.622, -3884944.157,
+  //              7612336.042, -2270131.404, -4976406.726, -5260237.163,
+  //              -4947737.810, 3583352.355, 7648790.331, -9360989.228
+  VLOAD_64(v2, 0x4102babe20435c2f, 0xc15dbd4abd4015a9, 0xc15960e30c871450,
+           0x41300472c1efbd9f, 0x415cc19e94ffb79b, 0xc160a78b6f5bcd25,
+           0x412064b13e931aa9, 0xc14da3c81425b914, 0x415d09ec02a8cc93,
+           0xc14151d9b3c1ecaf, 0xc152fbc5ae718384, 0xc15410f34a6ddb48,
+           0xc152dfc673d9ba53, 0x414b56bc2d765fad, 0x415d2d85952e8398,
+           0xc161dacba74d791e);
+  asm volatile("vfncvt.f.f.w v4, v2");
+  //              153431.766, -7796011.000, -6652812.000, 1049714.750,
+  //              7538298.500, -8731739.000, 537176.625, -3884944.250,
+  //              7612336.000, -2270131.500, -4976406.500, -5260237.000,
+  //              -4947738.000, 3583352.250, 7648790.500, -9360989.000
+  VCMP_U32(26, v4, 0x4815d5f1, 0xcaedea56, 0xcacb0718, 0x49802396, 0x4ae60cf5,
+           0xcb053c5b, 0x4903258a, 0xca6d1e41, 0x4ae84f60, 0xca0a8ece,
+           0xca97de2d, 0xcaa0879a, 0xca96fe34, 0x4a5ab5e1, 0x4ae96c2d,
+           0xcb0ed65d);
+};
+
+// Simple random test with similar values (masked)
+// The numbers are the same of TEST_CASE1
+void TEST_CASE14(void) {
+  VSET(16, e16, m1);
+  //              908.994, -6788.630, -5789.335, 8054.104, 3947.551, 9596.856,
+  //              2474.506, 3094.286, 7684.992, -6850.149, -54.922, 7737.443,
+  //              4171.873, 5266.611, 9163.839, 5679.187
+  VLOAD_32(v2, 0x44633fa3, 0xc5d4250b, 0xc5b4eaaf, 0x45fbb0d4, 0x4576b8d0,
+           0x4615f36d, 0x451aa818, 0x45416494, 0x45f027ef, 0xc5d61131,
+           0xc25bb026, 0x45f1cb8c, 0x45825efb, 0x45a494e4, 0x460f2f5b,
+           0x45b1797f);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfncvt.f.f.w v4, v2, v0.t");
+  //              0.000, -6788.000, 0.000, 8056.000, 0.000, 9600.000, 0.000,
+  //              3094.000, 0.000, -6852.000, 0.000, 7736.000, 0.000, 5268.000,
+  //              0.000, 5680.000
+  VCMP_U16(27, v4, 0x0, 0xeea1, 0x0, 0x6fde, 0x0, 0x70b0, 0x0, 0x6a0b, 0x0,
+           0xeeb1, 0x0, 0x6f8e, 0x0, 0x6d25, 0x0, 0x6d8c);
+
+  VSET(16, e32, m1);
+  //              153431.766, -7796010.957, -6652812.196, 1049714.758,
+  //              7538298.328, -8731739.480, 537176.622, -3884944.157,
+  //              7612336.042, -2270131.404, -4976406.726, -5260237.163,
+  //              -4947737.810, 3583352.355, 7648790.331, -9360989.228
+  VLOAD_64(v2, 0x4102babe20435c2f, 0xc15dbd4abd4015a9, 0xc15960e30c871450,
+           0x41300472c1efbd9f, 0x415cc19e94ffb79b, 0xc160a78b6f5bcd25,
+           0x412064b13e931aa9, 0xc14da3c81425b914, 0x415d09ec02a8cc93,
+           0xc14151d9b3c1ecaf, 0xc152fbc5ae718384, 0xc15410f34a6ddb48,
+           0xc152dfc673d9ba53, 0x414b56bc2d765fad, 0x415d2d85952e8398,
+           0xc161dacba74d791e);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfncvt.f.f.w v4, v2, v0.t");
+  //              0.000, -7796011.000, 0.000, 1049714.750, 0.000, -8731739.000,
+  //              0.000, -3884944.250, 0.000, -2270131.500, 0.000, -5260237.000,
+  //              0.000, 3583352.250, 0.000, -9360989.000
+  VCMP_U32(28, v4, 0x0, 0xcaedea56, 0x0, 0x49802396, 0x0, 0xcb053c5b, 0x0,
+           0xca6d1e41, 0x0, 0xca0a8ece, 0x0, 0xcaa0879a, 0x0, 0x4a5ab5e1, 0x0,
+           0xcb0ed65d);
+};
+
+////////////////////
+// vfncvt.rod.f.f //
+////////////////////
+
+// Simple random test with similar values
+void TEST_CASE15(void) {
+  VSET(16, e16, m1);
+  //                     908.994, -6788.630, -5789.335, 8054.104, 3947.551,
+  //                     9596.856, 2474.506, 3094.286, 7684.992, -6850.149,
+  //                     -54.922, 7737.443, 4171.873, 5266.611, 9163.839,
+  //                     5679.187
+  VLOAD_32(v2, 0x44633fa3, 0xc5d4250b, 0xc5b4eaaf, 0x45fbb0d4, 0x4576b8d0,
+           0x4615f36d, 0x451aa818, 0x45416494, 0x45f027ef, 0xc5d61131,
+           0xc25bb026, 0x45f1cb8c, 0x45825efb, 0x45a494e4, 0x460f2f5b,
+           0x45b1797f);
+  asm volatile("vfncvt.rod.f.f.w v4, v2");
+  //                  909.000, -6788.000, -5788.000, 8056.000, 3948.000,
+  //                  9600.000, 2474.000, 3094.000, 7684.000, -6852.000,
+  //                  -54.938, 7736.000, 4172.000, 5268.000, 9160.000, 5680.000
+  VCMP_U16(29, v4, 0x6319, 0xeea1, 0xeda7, 0x6fdd, 0x6bb5, 0x70af, 0x68d5,
+           0x6a0b, 0x6f81, 0xeeb1, 0xd2dd, 0x6f8f, 0x6c13, 0x6d25, 0x7079,
+           0x6d8b);
+
+  VSET(16, e32, m1);
+  //                       153431.9687, 153431.984375, -6652812.196,
+  //                       1049714.758, 7538298.328, -8731739.480, 537176.622,
+  //                       -3884944.157, 7612336.042, -2270131.404,
+  //                       -4976406.726, -5260237.163, -4947737.810,
+  //                       3583352.355, 7648790.331, -9360989.228
+  VLOAD_64(v2, 0x4102babfc0000000, 0x4102babfe0000000, 0xc15960e30c871450,
+           0x41300472c1efbd9f, 0x415cc19e94ffb79b, 0xc160a78b6f5bcd25,
+           0x412064b13e931aa9, 0xc14da3c81425b914, 0x415d09ec02a8cc93,
+           0xc14151d9b3c1ecaf, 0xc152fbc5ae718384, 0xc15410f34a6ddb48,
+           0xc152dfc673d9ba53, 0x414b56bc2d765fad, 0x415d2d85952e8398,
+           0xc161dacba74d791e);
+  asm volatile("vfncvt.rod.f.f.w v4, v2");
+  //                       153431.9687, 153431.984375,    -6652812.500,
+  //                       1049714.875,    7538298.500,   -8731739.000,
+  //                       537176.5625,   -3884944.250,    7612336.500,
+  //                       -2270131.250, -4976406.500,     -5260237.500,
+  //                       -4947737.500,    3583352.250,    7648790.500,
+  //                       -9360989.000
+  VCMP_U32(30, v4, 0x4815d5fe, 0x4815d5ff, 0xcacb0719, 0x49802397, 0x4ae60cf5,
+           0xcb053c5b, 0x49032589, 0xca6d1e41, 0x4ae84f61, 0xca0a8ecd,
+           0xca97de2d, 0xcaa0879b, 0xca96fe33, 0x4a5ab5e1, 0x4ae96c2d,
+           0xcb0ed65d);
+};
+
+// Simple random test with similar values (masked)
+// The numbers are the same of TEST_CASE1
+void TEST_CASE16(void) {
+  VSET(16, e16, m1);
+  //              908.994, -6788.630, -5789.335, 8054.104, 3947.551, 9596.856,
+  //              2474.506, 3094.286, 7684.992, -6850.149, -54.922, 7737.443,
+  //              4171.873, 5266.611, 9163.839, 5679.187
+  VLOAD_32(v2, 0x44633fa3, 0xc5d4250b, 0xc5b4eaaf, 0x45fbb0d4, 0x4576b8d0,
+           0x4615f36d, 0x451aa818, 0x45416494, 0x45f027ef, 0xc5d61131,
+           0xc25bb026, 0x45f1cb8c, 0x45825efb, 0x45a494e4, 0x460f2f5b,
+           0x45b1797f);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfncvt.rod.f.f.w v4, v2, v0.t");
+  //              0.000, -6788.000, 0.000, 8056.000, 0.000, 9600.000, 0.000,
+  //              3094.000, 0.000, -6852.000, 0.000, 7736.000, 0.000, 5268.000,
+  //              0.000, 5680.000
+  VCMP_U16(31, v4, 0x0, 0xeea1, 0x0, 0x6fdd, 0x0, 0x70af, 0x0, 0x6a0b, 0x0,
+           0xeeb1, 0x0, 0x6f8f, 0x0, 0x6d25, 0x0, 0x6d8b);
+
+  VSET(16, e32, m1);
+  //              153431.766, -7796010.957, -6652812.196, 1049714.758,
+  //              7538298.328, -8731739.480, 537176.622, -3884944.157,
+  //              7612336.042, -2270131.404, -4976406.726, -5260237.163,
+  //              -4947737.810, 3583352.355, 7648790.331, -9360989.228
+  VLOAD_64(v2, 0x4102babe20435c2f, 0xc15dbd4abd4015a9, 0xc15960e30c871450,
+           0x41300472c1efbd9f, 0x415cc19e94ffb79b, 0xc160a78b6f5bcd25,
+           0x412064b13e931aa9, 0xc14da3c81425b914, 0x415d09ec02a8cc93,
+           0xc14151d9b3c1ecaf, 0xc152fbc5ae718384, 0xc15410f34a6ddb48,
+           0xc152dfc673d9ba53, 0x414b56bc2d765fad, 0x415d2d85952e8398,
+           0xc161dacba74d791e);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfncvt.rod.f.f.w v4, v2, v0.t");
+  //              0.000, -7796011.000, 0.000, 1049714.750, 0.000, -8731739.000,
+  //              0.000, -3884944.250, 0.000, -2270131.500, 0.000, -5260237.000,
+  //              0.000, 3583352.250, 0.000, -9360989.000
+  VCMP_U32(32, v4, 0x0, 0xcaedea55, 0x0, 0x49802397, 0x0, 0xcb053c5b, 0x0,
+           0xca6d1e41, 0x0, 0xca0a8ecd, 0x0, 0xcaa0879b, 0x0, 0x4a5ab5e1, 0x0,
+           0xcb0ed65d);
+};
+
+int main(void) {
+  enable_vec();
+  enable_fp();
+
+  TEST_CASE1();
+  TEST_CASE2();
+
+  TEST_CASE3();
+  TEST_CASE4();
+
+  TEST_CASE5();
+  TEST_CASE6();
+
+  TEST_CASE7();
+  TEST_CASE8();
+
+  TEST_CASE9();
+  TEST_CASE10();
+
+  TEST_CASE11();
+  TEST_CASE12();
+
+  TEST_CASE13();
+  TEST_CASE14();
+
+  TEST_CASE15();
+  TEST_CASE16();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vfnmacc.c b/apps/riscv-tests/isa/rv64uv/vfnmacc.c
new file mode 100644
index 0000000..76cbdbe
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vfnmacc.c
@@ -0,0 +1,456 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+// Simple random test with similar values + 1 subnormal
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  //              -0.6377, -0.2332,  0.9458, -0.2612, -0.6772,  0.4543,  0.1002,
+  //              0.7764,  0.7979, -0.8599,  0.7837, -0.2461,  0.4221,  0.2251,
+  //              0.7739,  0.1461
+  VLOAD_16(v2, 0xb91a, 0xb376, 0x3b91, 0xb42e, 0xb96b, 0x3745, 0x2e69, 0x3a36,
+           0x3a62, 0xbae1, 0x3a45, 0xb3e0, 0x36c1, 0x3334, 0x3a31, 0x30ad);
+  //               0.9551, -0.6787,  0.5605, -0.7305, -0.7197, -0.1581,  0.7271,
+  //               0.6113,  0.2971, -0.8062,  0.9668, -0.5278,  0.3972, -0.1084,
+  //               -0.3015,  0.9556
+  VLOAD_16(v3, 0x3ba4, 0xb96e, 0x387c, 0xb9d8, 0xb9c2, 0xb10f, 0x39d1, 0x38e4,
+           0x34c1, 0xba73, 0x3bbc, 0xb839, 0x365b, 0xaef0, 0xb4d3, 0x3ba5);
+  //               0.7402,  0.0935,  0.1455, -0.2771,  0.3347,  0.7964,  0.6543,
+  //               -0.7534,  0.2476,  0.0338,  0.9980,  0.3284,  0.2239,
+  //               -0.4551,  0.6694, -0.8550
+  VLOAD_16(v1, 0x39ec, 0x2dfc, 0x30a8, 0xb46f, 0x355b, 0x3a5f, 0x393c, 0xba07,
+           0x33ec, 0x2853, 0x3bfc, 0x3541, 0x332a, 0xb748, 0x395b, 0xbad7);
+  asm volatile("vfnmacc.vv v1, v2, v3");
+  //              -0.1313, -0.2517, -0.6758,  0.0863, -0.8223, -0.7246, -0.7271,
+  //              0.2788, -0.4846, -0.7271, -1.7559, -0.4583, -0.3916,  0.4795,
+  //              -0.4360,  0.7153
+  VCMP_U16(1, v1, 0xb033, 0xb407, 0xb968, 0x2d86, 0xba94, 0xb9cc, 0xb9d1,
+           0x3476, 0xb7c1, 0xb9d1, 0xbf06, 0xb755, 0xb644, 0x37ac, 0xb6fa,
+           0x39b9);
+
+  VSET(16, e32, m1);
+  //              -0.17374928, -0.36242354, -0.18093164,  0.94970566,
+  //              -0.45790458, -0.17780401, -0.51985794, -0.04832974,
+  //              0.13252106,  0.77533042,  0.42536697, -0.72199643,
+  //              -0.25088808,  0.28798762,  0.66300607, -0.63549894
+  VLOAD_32(v2, 0xbe31eb55, 0xbeb98f94, 0xbe394625, 0x3f731fe9, 0xbeea7278,
+           0xbe361241, 0xbf051569, 0xbd45f569, 0x3e07b39a, 0x3f467c0e,
+           0x3ed9c9b3, 0xbf38d4c2, 0xbe807467, 0x3e93731d, 0x3f29bac4,
+           0xbf22b00f);
+  //              -0.61242568,  0.71439523, -0.15632962,  0.10917858,
+  //              0.19637996, -0.88467985,  0.73412597, -0.98048240, 0.25438991,
+  //              -0.02058743, -0.00876777,  0.21936898, -0.71130067,
+  //              -0.29675287, -0.96093589,  0.24695934
+  VLOAD_32(v3, 0xbf1cc7ee, 0x3f36e29b, 0xbe2014df, 0x3ddf9905, 0x3e4917d4,
+           0xbf627a61, 0x3f3befae, 0xbf7b00e5, 0x3e823f65, 0xbca8a6f9,
+           0xbc0fa6af, 0x3e60a243, 0xbf3617cd, 0xbe97effe, 0xbf75ffe5,
+           0x3e7ce2e9);
+  //               0.77600455,  0.02542816, -0.63618338,  0.11704731,
+  //               0.45613721, -0.90825689,  0.21235447,  0.35766414,
+  //               0.08650716, -0.98431164,  0.21029140, -0.92919809,
+  //               0.46440944,  0.70648551, -0.80876821, -0.19595607
+  VLOAD_32(v1, 0x3f46a83c, 0x3cd04eb8, 0xbf22dcea, 0x3defb680, 0x3ee98ad1,
+           0xbf688386, 0x3e597373, 0x3eb71fc1, 0x3db12aaa, 0xbf7bfbd9,
+           0x3e5756a1, 0xbf6ddfed, 0x3eedc713, 0x3f34dc3c, 0xbf4f0b6f,
+           0xbe48a8b5);
+  asm volatile("vfnmacc.vv v1, v2, v3");
+  //              -0.88241309,  0.23348548,  0.60789841, -0.22073483,
+  //              -0.36621392,  0.75095725,  0.16928674, -0.40505061,
+  //              -0.12021918,  1.00027370, -0.20656188,  1.08758175,
+  //              -0.64286631, -0.62102437,  1.44587445,  0.35289848
+  VCMP_U32(2, v1, 0xbf61e5d3, 0x3e6f16d2, 0x3f1b9f3b, 0xbe62084f, 0xbebb8064,
+           0x3f403ebc, 0x3e2d5982, 0xbecf62cb, 0xbdf63579, 0x3f8008f8,
+           0xbe5384f5, 0x3f8b35e1, 0xbf2492e3, 0xbf1efb74, 0x3fb9126b,
+           0x3eb4af1c);
+
+  VSET(16, e64, m1);
+  //              -0.3252450595073633,  0.4758165631309326, -0.1595578232245429,
+  //              -0.5062008461482019, -0.8497827573746595, -0.1941654045426651,
+  //              0.5653121187716577, -0.9852357785633095, -0.4238236947700038,
+  //              0.5852522737985073,  0.4009389814391957, -0.8725649196362917,
+  //              -0.5946782335830663,  0.4175703122760628, -0.6355596052793091,
+  //              -0.3469340725892474
+  VLOAD_64(v2, 0xbfd4d0d0a77142c0, 0x3fde73c75062b7e8, 0xbfc46c6408490198,
+           0xbfe032cc1ded3ff0, 0xbfeb316b9bf41faa, 0xbfc8da6977433ee0,
+           0x3fe2170970c503fe, 0xbfef870d2ef8e992, 0xbfdb1fed6b13a6c0,
+           0x3fe2ba62f9fbf9aa, 0x3fd9a8fbf93e43f0, 0xbfebec0d442f3114,
+           0xbfe3079aa59c3bf4, 0x3fdab978d4c06588, 0xbfe4568118eaaa68,
+           0xbfd6342af7e8e3dc);
+  //               0.9024789401717532,  0.1750129013440402,  0.5031110880652467,
+  //               -0.2303324647743561, -0.3880673069078899,
+  //               -0.9441232974464955, -0.9718449040015202, 0.6713775626400460,
+  //               -0.0912048565692380, -0.5347347522064834,
+  //               -0.5209348837668262,  0.1676058792979986,
+  //               -0.3611782231841894,  0.5839305722445856,
+  //               -0.5690013462620132, -0.7273345685963009
+  VLOAD_64(v3, 0x3fece11b83abb9b8, 0x3fc666d29fd34b08, 0x3fe0197c6cafd8c4,
+           0xbfcd7b88c1b4daf0, 0xbfd8d61841f43c54, 0xbfee36420fbd9482,
+           0xbfef195a7bef10b4, 0x3fe57beccc59d47e, 0xbfb7593394338500,
+           0xbfe11c8c0e185e4a, 0xbfe0ab7fa223f876, 0x3fc5741c0519e298,
+           0xbfd71d8b44269f74, 0x3fe2af8f2add9a18, 0xbfe235424fb26902,
+           0xbfe74653252be25a);
+  //              -0.0769255470598902, -0.8447241112550155, -0.1913688167412757,
+  //              0.7663381230505260,  0.2058488268749510, -0.0251549939511286,
+  //              0.5275264461714482, -0.7602756587514194,  0.6498044022974587,
+  //              -0.7128277097157256, -0.8385947434294139,  0.8834902787005550,
+  //              0.5936682304042178,  0.1532178226844403, -0.5096194622607613,
+  //              -0.8578075287458693
+  VLOAD_64(v1, 0xbfb3b16484d96110, 0xbfeb07fadbff7462, 0xbfc87ec5fcb06230,
+           0x3fe885d78705c2d4, 0x3fca59411dac8758, 0xbf99c23b11679a80,
+           0x3fe0e17f24429b70, 0xbfe8542d9e4907ce, 0x3fe4cb329a1542de,
+           0xbfe6cf7c0e9d2c04, 0xbfead5c4a4b40f1a, 0x3fec458d67ab4a36,
+           0x3fe2ff5484485472, 0x3fc39ca440cc0820, 0xbfe04ecd797a151a,
+           0xbfeb7328c6473c1e);
+  asm volatile("vfnmacc.vv v1, v2, v3");
+  //               0.3704523636601942,  0.7614500740339213,  0.2716441267930978,
+  //               -0.8829326116147059, -0.5356217329860959,
+  //               -0.1581610880357251, 0.0218692556270895,  1.4217408543890222,
+  //               -0.6884591815896014,  1.0257824393236514,  1.0474578451230310,
+  //               -0.7372432681003268, -0.8084530581760619,
+  //               -0.3970498940841519,  0.1479851912270807,  0.6054703847278113
+  VCMP_U64(3, v1, 0x3fd7b57dd4a95f28, 0x3fe85dcc8bb06629, 0x3fd1629e0c2e846c,
+           0xbfec40fbe46ea001, 0xbfe123d0304677d2, 0xbfc43e9f5e4e7ddd,
+           0x3f9664e4e6d32991, 0x3ff6bf73568fcea3, 0xbfe607db8cb1dd4b,
+           0x3ff0699ad8db4c8b, 0x3ff0c263284bdf71, 0xbfe7977f31b5fc6d,
+           0xbfe9ded8f2a6f4b5, 0xbfd96943f57e3046, 0x3fc2f12dc24e6a42,
+           0x3fe360036da34794);
+};
+
+// Simple random test with similar values + 1 subnormal (masked)
+// The numbers are the same of TEST_CASE1
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  //              -0.6377, -0.2332,  0.9458, -0.2612, -0.6772,  0.4543,  0.1002,
+  //              0.7764,  0.7979, -0.8599,  0.7837, -0.2461,  0.4221,  0.2251,
+  //              0.7739,  0.1461
+  VLOAD_16(v2, 0xb91a, 0xb376, 0x3b91, 0xb42e, 0xb96b, 0x3745, 0x2e69, 0x3a36,
+           0x3a62, 0xbae1, 0x3a45, 0xb3e0, 0x36c1, 0x3334, 0x3a31, 0x30ad);
+  //               0.9551, -0.6787,  0.5605, -0.7305, -0.7197, -0.1581,  0.7271,
+  //               0.6113,  0.2971, -0.8062,  0.9668, -0.5278,  0.3972, -0.1084,
+  //               -0.3015,  0.9556
+  VLOAD_16(v3, 0x3ba4, 0xb96e, 0x387c, 0xb9d8, 0xb9c2, 0xb10f, 0x39d1, 0x38e4,
+           0x34c1, 0xba73, 0x3bbc, 0xb839, 0x365b, 0xaef0, 0xb4d3, 0x3ba5);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //               0.7402,  0.0935,  0.1455, -0.2771,  0.3347,  0.7964,  0.6543,
+  //               -0.7534,  0.2476,  0.0338,  0.9980,  0.3284,  0.2239,
+  //               -0.4551,  0.6694, -0.8550
+  VLOAD_16(v1, 0x39ec, 0x2dfc, 0x30a8, 0xb46f, 0x355b, 0x3a5f, 0x393c, 0xba07,
+           0x33ec, 0x2853, 0x3bfc, 0x3541, 0x332a, 0xb748, 0x395b, 0xbad7);
+  asm volatile("vfnmacc.vv v1, v2, v3, v0.t");
+  //               0.0000, -0.2517,  0.0000,  0.0863,  0.0000, -0.7246,  0.0000,
+  //               0.2788,  0.0000, -0.7271,  0.0000, -0.4583,  0.0000,  0.4795,
+  //               0.0000,  0.7153
+  VCMP_U16(4, v1, 0x39ec, 0xb407, 0x30a8, 0x2d86, 0x355b, 0xb9cc, 0x393c,
+           0x3476, 0x33ec, 0xb9d1, 0x3bfc, 0xb755, 0x332a, 0x37ac, 0x395b,
+           0x39b9);
+
+  VSET(16, e32, m1);
+  //              -0.17374928, -0.36242354, -0.18093164,  0.94970566,
+  //              -0.45790458, -0.17780401, -0.51985794, -0.04832974,
+  //              0.13252106,  0.77533042,  0.42536697, -0.72199643,
+  //              -0.25088808,  0.28798762,  0.66300607, -0.63549894
+  VLOAD_32(v2, 0xbe31eb55, 0xbeb98f94, 0xbe394625, 0x3f731fe9, 0xbeea7278,
+           0xbe361241, 0xbf051569, 0xbd45f569, 0x3e07b39a, 0x3f467c0e,
+           0x3ed9c9b3, 0xbf38d4c2, 0xbe807467, 0x3e93731d, 0x3f29bac4,
+           0xbf22b00f);
+  //              -0.61242568,  0.71439523, -0.15632962,  0.10917858,
+  //              0.19637996, -0.88467985,  0.73412597, -0.98048240, 0.25438991,
+  //              -0.02058743, -0.00876777,  0.21936898, -0.71130067,
+  //              -0.29675287, -0.96093589,  0.24695934
+  VLOAD_32(v3, 0xbf1cc7ee, 0x3f36e29b, 0xbe2014df, 0x3ddf9905, 0x3e4917d4,
+           0xbf627a61, 0x3f3befae, 0xbf7b00e5, 0x3e823f65, 0xbca8a6f9,
+           0xbc0fa6af, 0x3e60a243, 0xbf3617cd, 0xbe97effe, 0xbf75ffe5,
+           0x3e7ce2e9);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //               0.77600455,  0.02542816, -0.63618338,  0.11704731,
+  //               0.45613721, -0.90825689,  0.21235447,  0.35766414,
+  //               0.08650716, -0.98431164,  0.21029140, -0.92919809,
+  //               0.46440944,  0.70648551, -0.80876821, -0.19595607
+  VLOAD_32(v1, 0x3f46a83c, 0x3cd04eb8, 0xbf22dcea, 0x3defb680, 0x3ee98ad1,
+           0xbf688386, 0x3e597373, 0x3eb71fc1, 0x3db12aaa, 0xbf7bfbd9,
+           0x3e5756a1, 0xbf6ddfed, 0x3eedc713, 0x3f34dc3c, 0xbf4f0b6f,
+           0xbe48a8b5);
+  asm volatile("vfnmacc.vv v1, v2, v3, v0.t");
+  //               0.00000000,  0.23348548,  0.00000000, -0.22073483,
+  //               0.00000000,  0.75095725,  0.00000000, -0.40505061,
+  //               0.00000000,  1.00027370,  0.00000000,  1.08758175,
+  //               0.00000000, -0.62102437,  0.00000000,  0.35289848
+  VCMP_U32(5, v1, 0x3f46a83c, 0x3e6f16d2, 0xbf22dcea, 0xbe62084f, 0x3ee98ad1,
+           0x3f403ebc, 0x3e597373, 0xbecf62cb, 0x3db12aaa, 0x3f8008f8,
+           0x3e5756a1, 0x3f8b35e1, 0x3eedc713, 0xbf1efb74, 0xbf4f0b6f,
+           0x3eb4af1c);
+
+  VSET(16, e64, m1);
+  //              -0.3252450595073633,  0.4758165631309326, -0.1595578232245429,
+  //              -0.5062008461482019, -0.8497827573746595, -0.1941654045426651,
+  //              0.5653121187716577, -0.9852357785633095, -0.4238236947700038,
+  //              0.5852522737985073,  0.4009389814391957, -0.8725649196362917,
+  //              -0.5946782335830663,  0.4175703122760628, -0.6355596052793091,
+  //              -0.3469340725892474
+  VLOAD_64(v2, 0xbfd4d0d0a77142c0, 0x3fde73c75062b7e8, 0xbfc46c6408490198,
+           0xbfe032cc1ded3ff0, 0xbfeb316b9bf41faa, 0xbfc8da6977433ee0,
+           0x3fe2170970c503fe, 0xbfef870d2ef8e992, 0xbfdb1fed6b13a6c0,
+           0x3fe2ba62f9fbf9aa, 0x3fd9a8fbf93e43f0, 0xbfebec0d442f3114,
+           0xbfe3079aa59c3bf4, 0x3fdab978d4c06588, 0xbfe4568118eaaa68,
+           0xbfd6342af7e8e3dc);
+  //               0.9024789401717532,  0.1750129013440402,  0.5031110880652467,
+  //               -0.2303324647743561, -0.3880673069078899,
+  //               -0.9441232974464955, -0.9718449040015202, 0.6713775626400460,
+  //               -0.0912048565692380, -0.5347347522064834,
+  //               -0.5209348837668262,  0.1676058792979986,
+  //               -0.3611782231841894,  0.5839305722445856,
+  //               -0.5690013462620132, -0.7273345685963009
+  VLOAD_64(v3, 0x3fece11b83abb9b8, 0x3fc666d29fd34b08, 0x3fe0197c6cafd8c4,
+           0xbfcd7b88c1b4daf0, 0xbfd8d61841f43c54, 0xbfee36420fbd9482,
+           0xbfef195a7bef10b4, 0x3fe57beccc59d47e, 0xbfb7593394338500,
+           0xbfe11c8c0e185e4a, 0xbfe0ab7fa223f876, 0x3fc5741c0519e298,
+           0xbfd71d8b44269f74, 0x3fe2af8f2add9a18, 0xbfe235424fb26902,
+           0xbfe74653252be25a);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //              -0.0769255470598902, -0.8447241112550155, -0.1913688167412757,
+  //              0.7663381230505260,  0.2058488268749510, -0.0251549939511286,
+  //              0.5275264461714482, -0.7602756587514194,  0.6498044022974587,
+  //              -0.7128277097157256, -0.8385947434294139,  0.8834902787005550,
+  //              0.5936682304042178,  0.1532178226844403, -0.5096194622607613,
+  //              -0.8578075287458693
+  VLOAD_64(v1, 0xbfb3b16484d96110, 0xbfeb07fadbff7462, 0xbfc87ec5fcb06230,
+           0x3fe885d78705c2d4, 0x3fca59411dac8758, 0xbf99c23b11679a80,
+           0x3fe0e17f24429b70, 0xbfe8542d9e4907ce, 0x3fe4cb329a1542de,
+           0xbfe6cf7c0e9d2c04, 0xbfead5c4a4b40f1a, 0x3fec458d67ab4a36,
+           0x3fe2ff5484485472, 0x3fc39ca440cc0820, 0xbfe04ecd797a151a,
+           0xbfeb7328c6473c1e);
+  asm volatile("vfnmacc.vv v1, v2, v3, v0.t");
+  //               0.0000000000000000,  0.7614500740339213,  0.0000000000000000,
+  //               -0.8829326116147059,  0.0000000000000000,
+  //               -0.1581610880357251, 0.0000000000000000,  1.4217408543890222,
+  //               0.0000000000000000,  1.0257824393236514,  0.0000000000000000,
+  //               -0.7372432681003268,  0.0000000000000000,
+  //               -0.3970498940841519,  0.0000000000000000,  0.6054703847278113
+  VCMP_U64(6, v1, 0xbfb3b16484d96110, 0x3fe85dcc8bb06629, 0xbfc87ec5fcb06230,
+           0xbfec40fbe46ea001, 0x3fca59411dac8758, 0xbfc43e9f5e4e7ddd,
+           0x3fe0e17f24429b70, 0x3ff6bf73568fcea3, 0x3fe4cb329a1542de,
+           0x3ff0699ad8db4c8b, 0xbfead5c4a4b40f1a, 0xbfe7977f31b5fc6d,
+           0x3fe2ff5484485472, 0xbfd96943f57e3046, 0xbfe04ecd797a151a,
+           0x3fe360036da34794);
+};
+
+// Simple random test with similar values (vector-scalar)
+void TEST_CASE3(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //                              0.1300
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0x3029);
+  //              -0.2844,  0.4070, -0.1837, -0.2321, -0.5283, -0.6104, -0.7183,
+  //              -0.1191,  0.7998,  0.1169,  0.1169, -0.9214, -0.4360, -0.6250,
+  //              -0.5386,  0.6543
+  VLOAD_16(v2, 0xb48d, 0x3683, 0xb1e1, 0xb36d, 0xb83a, 0xb8e2, 0xb9bf, 0xaf9f,
+           0x3a66, 0x2f7c, 0x2f7c, 0xbb5f, 0xb6fa, 0xb900, 0xb84f, 0x393c);
+  //               0.9268, -0.3337, -0.3225, -0.8306, -0.1857, -0.6831,  0.0557,
+  //               0.5586,  0.2352,  0.6294,  0.6294, -0.8877, -0.2426,  0.5488,
+  //               0.4001,  0.1772
+  VLOAD_16(v1, 0x3b6a, 0xb557, 0xb529, 0xbaa5, 0xb1f1, 0xb977, 0x2b21, 0x3878,
+           0x3387, 0x3909, 0x3909, 0xbb1a, 0xb3c3, 0x3864, 0x3667, 0x31ac);
+  asm volatile("vfnmacc.vf v1, %[A], v2" ::[A] "f"(dscalar_16));
+  //              -0.8896,  0.2808,  0.3464,  0.8608,  0.2544,  0.7627,  0.0377,
+  //              -0.5430, -0.3394, -0.6445, -0.6445,  1.0078,  0.2993, -0.4675,
+  //              -0.3301, -0.2622
+  VCMP_U16(7, v1, 0xbb1e, 0x347e, 0x358b, 0x3ae3, 0x3412, 0x3a1a, 0x28d3,
+           0xb858, 0xb56d, 0xb928, 0xb928, 0x3c08, 0x34ca, 0xb77b, 0xb548,
+           0xb432);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                              -0.26917368
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0xbe89d122);
+  //              -0.27745819, -0.86308837, -0.16746511, -0.68674469,
+  //              -0.49064314, -0.74352056, -0.17169137,  0.26071417,
+  //              0.71857828,  0.07920383, -0.43244356, -0.58339220, 0.80679923,
+  //              0.23900302,  0.73513943, -0.80685192
+  VLOAD_32(v2, 0xbe8e0f00, 0xbf5cf35c, 0xbe2b7bf9, 0xbf2fce80, 0xbefb3594,
+           0xbf3e575d, 0xbe2fcfdd, 0x3e857c54, 0x3f37f4bf, 0x3da2359e,
+           0xbedd693e, 0xbf155931, 0x3f4e8a65, 0x3e74bd35, 0x3f3c3219,
+           0xbf4e8dd9);
+  //               0.13509545, -0.29169917,  0.80494332, -0.63637137,
+  //               0.63772237, -0.87242430, -0.44194883, -0.41286576,
+  //               -0.57735479,  0.61664599,  0.94073379, -0.89744234,
+  //               -0.70681161,  0.23247144,  0.06774496, -0.38581881
+  VLOAD_32(v1, 0x3e0a5676, 0xbe955998, 0x3f4e10c4, 0xbf22e93c, 0x3f2341c6,
+           0xbf5f5733, 0xbee2471e, 0xbed36324, 0xbf13cd86, 0x3f1ddc83,
+           0x3f70d3ee, 0xbf65bec8, 0xbf34f19b, 0x3e6e0cfe, 0x3d8abdde,
+           0xbec58a0b);
+  asm volatile("vfnmacc.vf v1, %[A], v2" ::[A] "f"(dscalar_32));
+  //              -0.20977989,  0.05937849, -0.85002053,  0.45151776,
+  //              -0.76979059,  0.67228812,  0.39573404,  0.48304313,
+  //              0.77077717, -0.59532642, -1.05713618,  0.74040854, 0.92398071,
+  //              -0.16813812,  0.13013524,  0.16863550
+  VCMP_U32(8, v1, 0xbe56d08a, 0x3d7336de, 0xbf599af2, 0x3ee72d57, 0xbf4510ff,
+           0x3f2c1b13, 0x3eca9da7, 0x3ef7516f, 0x3f4551a7, 0xbf186750,
+           0xbf87503d, 0x3f3d8b6a, 0x3f6c8a00, 0xbe2c2c66, 0x3e05422c,
+           0x3e2caec9);
+
+  VSET(16, e64, m1);
+  double dscalar_64;
+  //                                0.1021836258281641
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0x3fba28b4c31e60e0);
+  //                0.3274079371230154,  0.9254873656544997, 0.9683609308176633,
+  //                -0.6778040243955326,  0.9669615854915627,
+  //                0.8026267269428324, -0.7388821308618641, 0.7432413708598076,
+  //                0.9355143976513562, -0.4219868517017851, 0.8950700270161456,
+  //                0.6727820676214205, -0.8833440526985297, 0.0357808590148252,
+  //                -0.3802125831332157,  0.9831607630398518
+  VLOAD_64(v2, 0x3fd4f4406b993a2c, 0x3fed9d97ae0b1cd6, 0x3feefcd01012c05e,
+           0xbfe5b09210bc082e, 0x3feef1596c459614, 0x3fe9af1e3ee3adfa,
+           0xbfe7a4ec2374d0e2, 0x3fe7c8a2209c110c, 0x3fedefbbe3db30dc,
+           0xbfdb01d523d9acc0, 0x3feca469e5b540fa, 0x3fe5876e42389dca,
+           0xbfec445abf2e99e4, 0x3fa251de66953a60, 0xbfd8556728856e10,
+           0x3fef760d8f7eee22);
+  //                0.1671854121593166,  0.6264287337062140, 0.1587305627009998,
+  //                -0.3348358495277817,  0.4721131630506652,
+  //                0.2878076790245236,  0.5083797506594245, 0.9444607965181537,
+  //                -0.2805814092841707, -0.7218856627753110,
+  //                -0.3443302881655670,  0.3680926220616383,
+  //                -0.2344410843781140,  0.3553553454507421,
+  //                0.0951222110617760, -0.8329780449088213
+  VLOAD_64(v1, 0x3fc56654e2cbd888, 0x3fe40bb445915f4a, 0x3fc4514877d696a0,
+           0xbfd56df357d00344, 0x3fde371a20d41408, 0x3fd26b70e63cabf0,
+           0x3fe044a59c60fcd4, 0x3fee3905d92cc95e, 0xbfd1f50bba2f6e40,
+           0xbfe719aff62247a4, 0xbfd60981e7ac601c, 0x3fd78ed45b69d4fc,
+           0xbfce022a5b1f1348, 0x3fd6be2458cadcb0, 0x3fb859ede1a22f80,
+           0xbfeaa7c192a56bc8);
+  asm volatile("vfnmacc.vf v1, %[A], v2" ::[A] "f"(dscalar_64));
+  //              -0.2006411422994659, -0.7209983883869466, -0.2576811937222847,
+  //              0.4040963223414386, -0.5709208038927434, -0.3698229881701340,
+  //              -0.4328780954683192, -1.0204078946581041,  0.1849871561177042,
+  //              0.7650058093340112,  0.2528687874349445, -0.4368399331233641,
+  //              0.3247043825365946, -0.3590115633601233, -0.0562707107317317,
+  //              0.7325151133694248
+  VCMP_U64(9, v1, 0xbfc9ae9be43442c9, 0xbfe7126b3652e68a, 0xbfd07dd942f53687,
+           0x3fd9dcb6d238fb8a, 0xbfe244fbb4aa695e, 0xbfd7ab2e09dffb6d,
+           0xbfdbb44653cc3c92, 0xbff053973a823036, 0x3fc7ada8bcda50a5,
+           0x3fe87aed768addeb, 0x3fd02f00910d95b4, 0xbfdbf52f7a9681dc,
+           0x3fd4c7f4e3f733f9, 0xbfd6fa0ba2e11fba, 0xbfaccf83bca18481,
+           0x3fe770c388f7eacc);
+};
+
+// Simple random test with similar values (vector-scalar) (masked)
+void TEST_CASE4(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //                              0.1300
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0x3029);
+  //               -0.2844,  0.4070, -0.1837, -0.2321, -0.5283, -0.6104,
+  //               -0.7183, -0.1191,  0.7998,  0.1169,  0.2551, -0.9214,
+  //               -0.4360, -0.6250, -0.5386,  0.6543
+  VLOAD_16(v2, 0xb48d, 0x3683, 0xb1e1, 0xb36d, 0xb83a, 0xb8e2, 0xb9bf, 0xaf9f,
+           0x3a66, 0x2f7c, 0x3415, 0xbb5f, 0xb6fa, 0xb900, 0xb84f, 0x393c);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //                0.9268, -0.3337, -0.3225, -0.8306, -0.1857, -0.6831, 0.0557,
+  //                0.5586,  0.2352,  0.6294, -0.0325, -0.8877, -0.2426, 0.5488,
+  //                0.4001,  0.1772
+  VLOAD_16(v1, 0x3b6a, 0xb557, 0xb529, 0xbaa5, 0xb1f1, 0xb977, 0x2b21, 0x3878,
+           0x3387, 0x3909, 0xa828, 0xbb1a, 0xb3c3, 0x3864, 0x3667, 0x31ac);
+  asm volatile("vfnmacc.vf v1, %[A], v2, v0.t" ::[A] "f"(dscalar_16));
+  //                0.0000,  0.2808,  0.0000,  0.8608,  0.0000,  0.7627, 0.0000,
+  //                -0.5430,  0.0000, -0.6445,  0.0000,  1.0078,  0.0000,
+  //                -0.4675,  0.0000, -0.2622
+  VCMP_U16(10, v1, 0x3b6a, 0x347e, 0xb529, 0x3ae3, 0xb1f1, 0x3a1a, 0x2b21,
+           0xb858, 0x3387, 0xb928, 0xa828, 0x3c08, 0xb3c3, 0xb77b, 0x3667,
+           0xb432);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                              -0.26917368
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0xbe89d122);
+  //               -0.27745819, -0.86308837, -0.16746511, -0.68674469,
+  //               -0.49064314, -0.74352056, -0.17169137,  0.26071417,
+  //               0.71857828,  0.07920383, -0.43244356, -0.58339220,
+  //               0.80679923,  0.23900302,  0.73513943, -0.80685192
+  VLOAD_32(v2, 0xbe8e0f00, 0xbf5cf35c, 0xbe2b7bf9, 0xbf2fce80, 0xbefb3594,
+           0xbf3e575d, 0xbe2fcfdd, 0x3e857c54, 0x3f37f4bf, 0x3da2359e,
+           0xbedd693e, 0xbf155931, 0x3f4e8a65, 0x3e74bd35, 0x3f3c3219,
+           0xbf4e8dd9);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //                0.13509545, -0.29169917,  0.80494332, -0.63637137,
+  //                0.63772237, -0.87242430, -0.44194883, -0.41286576,
+  //                -0.57735479,  0.61664599,  0.94073379, -0.89744234,
+  //                -0.70681161,  0.23247144,  0.06774496, -0.38581881
+  VLOAD_32(v1, 0x3e0a5676, 0xbe955998, 0x3f4e10c4, 0xbf22e93c, 0x3f2341c6,
+           0xbf5f5733, 0xbee2471e, 0xbed36324, 0xbf13cd86, 0x3f1ddc83,
+           0x3f70d3ee, 0xbf65bec8, 0xbf34f19b, 0x3e6e0cfe, 0x3d8abdde,
+           0xbec58a0b);
+  asm volatile("vfnmacc.vf v1, %[A], v2, v0.t" ::[A] "f"(dscalar_32));
+  //                0.00000000,  0.05937849,  0.00000000,  0.45151776,
+  //                0.00000000,  0.67228812,  0.00000000,  0.48304313,
+  //                0.00000000, -0.59532642,  0.00000000,  0.74040854,
+  //                0.00000000, -0.16813812,  0.00000000,  0.16863550
+  VCMP_U32(11, v1, 0x3e0a5676, 0x3d7336de, 0x3f4e10c4, 0x3ee72d57, 0x3f2341c6,
+           0x3f2c1b13, 0xbee2471e, 0x3ef7516f, 0xbf13cd86, 0xbf186750,
+           0x3f70d3ee, 0x3f3d8b6a, 0xbf34f19b, 0xbe2c2c66, 0x3d8abdde,
+           0x3e2caec9);
+
+  VSET(16, e64, m1);
+  double dscalar_64;
+  //                                0.1021836258281641
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0x3fba28b4c31e60e0);
+  //                 0.3274079371230154,  0.9254873656544997,
+  //                 0.9683609308176633, -0.6778040243955326,
+  //                 0.9669615854915627,  0.8026267269428324,
+  //                 -0.7388821308618641,  0.7432413708598076,
+  //                 0.9355143976513562, -0.4219868517017851,
+  //                 0.8950700270161456,  0.6727820676214205,
+  //                 -0.8833440526985297,  0.0357808590148252,
+  //                 -0.3802125831332157,  0.9831607630398518
+  VLOAD_64(v2, 0x3fd4f4406b993a2c, 0x3fed9d97ae0b1cd6, 0x3feefcd01012c05e,
+           0xbfe5b09210bc082e, 0x3feef1596c459614, 0x3fe9af1e3ee3adfa,
+           0xbfe7a4ec2374d0e2, 0x3fe7c8a2209c110c, 0x3fedefbbe3db30dc,
+           0xbfdb01d523d9acc0, 0x3feca469e5b540fa, 0x3fe5876e42389dca,
+           0xbfec445abf2e99e4, 0x3fa251de66953a60, 0xbfd8556728856e10,
+           0x3fef760d8f7eee22);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //                 0.1671854121593166,  0.6264287337062140,
+  //                 0.1587305627009998, -0.3348358495277817,
+  //                 0.4721131630506652,  0.2878076790245236,
+  //                 0.5083797506594245,  0.9444607965181537,
+  //                 -0.2805814092841707, -0.7218856627753110,
+  //                 -0.3443302881655670,  0.3680926220616383,
+  //                 -0.2344410843781140,  0.3553553454507421,
+  //                 0.0951222110617760, -0.8329780449088213
+  VLOAD_64(v1, 0x3fc56654e2cbd888, 0x3fe40bb445915f4a, 0x3fc4514877d696a0,
+           0xbfd56df357d00344, 0x3fde371a20d41408, 0x3fd26b70e63cabf0,
+           0x3fe044a59c60fcd4, 0x3fee3905d92cc95e, 0xbfd1f50bba2f6e40,
+           0xbfe719aff62247a4, 0xbfd60981e7ac601c, 0x3fd78ed45b69d4fc,
+           0xbfce022a5b1f1348, 0x3fd6be2458cadcb0, 0x3fb859ede1a22f80,
+           0xbfeaa7c192a56bc8);
+  asm volatile("vfnmacc.vf v1, %[A], v2, v0.t" ::[A] "f"(dscalar_64));
+  //                -0.2006411422994659, -0.7209983883869466,
+  //                -0.2576811937222847,  0.4040963223414386,
+  //                -0.5709208038927434, -0.3698229881701340,
+  //                -0.4328780954683192, -1.0204078946581041,
+  //                0.1849871561177042,  0.7650058093340112, 0.2528687874349445,
+  //                -0.4368399331233641,  0.3247043825365946,
+  //                -0.3590115633601233, -0.0562707107317317, 0.7325151133694248
+  VCMP_U64(12, v1, 0x3fc56654e2cbd888, 0xbfe7126b3652e68a, 0x3fc4514877d696a0,
+           0x3fd9dcb6d238fb8a, 0x3fde371a20d41408, 0xbfd7ab2e09dffb6d,
+           0x3fe044a59c60fcd4, 0xbff053973a823036, 0xbfd1f50bba2f6e40,
+           0x3fe87aed768addeb, 0xbfd60981e7ac601c, 0xbfdbf52f7a9681dc,
+           0xbfce022a5b1f1348, 0xbfd6fa0ba2e11fba, 0x3fb859ede1a22f80,
+           0x3fe770c388f7eacc);
+};
+
+int main(void) {
+  enable_vec();
+  enable_fp();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vfnmadd.c b/apps/riscv-tests/isa/rv64uv/vfnmadd.c
new file mode 100644
index 0000000..307666f
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vfnmadd.c
@@ -0,0 +1,458 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+// Simple random test with similar values
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  //              -0.7461,  0.0514, -0.3071, -0.4934, -0.5220, -0.7983,  0.4907,
+  //              -0.9028,  0.1752,  0.0676,  0.1040,  0.4526,  0.3525, -0.2686,
+  //              0.3540, -0.0847
+  VLOAD_16(v2, 0xb9f8, 0x2a94, 0xb4ea, 0xb7e5, 0xb82d, 0xba63, 0x37da, 0xbb39,
+           0x319b, 0x2c54, 0x2ea8, 0x373e, 0x35a4, 0xb44c, 0x35aa, 0xad6c);
+  //               0.1573, -0.7700,  0.0804, -0.9438,  0.0790,  0.7998, -0.2854,
+  //               0.1963, -0.0687, -0.2123,  0.3625, -0.0002,  0.7168, -0.4033,
+  //               0.2812, -0.3159
+  VLOAD_16(v3, 0x3109, 0xba29, 0x2d25, 0xbb8d, 0x2d0e, 0x3a66, 0xb491, 0x3248,
+           0xac65, 0xb2cb, 0x35cd, 0x897c, 0x39bc, 0xb674, 0x3480, 0xb50e);
+  //               0.0337,  0.2034, -0.1886,  0.8242,  0.3225,  0.0331,  0.0698,
+  //               0.6777, -0.2539, -0.5825, -0.4319, -0.6323,  0.0674, -0.2903,
+  //               -0.8145,  0.1893
+  VLOAD_16(v1, 0x284f, 0x3282, 0xb209, 0x3a98, 0x3529, 0x283b, 0x2c77, 0x396c,
+           0xb410, 0xb8a9, 0xb6e9, 0xb90f, 0x2c50, 0xb4a5, 0xba84, 0x320f);
+  asm volatile("vfnmadd.vv v1, v2, v3");
+  //              -0.1322,  0.7598, -0.1383,  1.3506,  0.0894, -0.7734,  0.2512,
+  //              0.4155,  0.1132,  0.2517, -0.3176,  0.2864, -0.7407,  0.3254,
+  //              0.0071,  0.3320
+  VCMP_U16(1, v1, 0xb03b, 0x3a14, 0xb06d, 0x3d67, 0x2db8, 0xba30, 0x3405,
+           0x36a6, 0x2f3e, 0x3407, 0xb515, 0x3495, 0xb9ed, 0x3535, 0x1f3d,
+           0x3550);
+
+  VSET(16, e32, m1);
+  //              -0.36820358,  0.10496315, -0.32905263, -0.92334682,
+  //              0.43153936,  0.92736709, -0.59600371,  0.75117606, 0.84123290,
+  //              0.33028743, -0.43412161,  0.95273590,  0.06816643,
+  //              -0.88978988,  0.18573478,  0.61926919
+  VLOAD_32(v2, 0xbebc852e, 0x3dd6f6ec, 0xbea87996, 0xbf6c6075, 0x3edcf2ba,
+           0x3f6d67ee, 0xbf1893b3, 0x3f404d13, 0x3f575b0a, 0x3ea91b6f,
+           0xbede4530, 0x3f73e680, 0x3d8b9ad8, 0xbf63c945, 0x3e3e3142,
+           0x3f1e886d);
+  //               0.69083834, -0.31329882, -0.54809541,  0.25019145,
+  //               -0.67489260,  0.23259214, -0.14038530,  0.09741956,
+  //               -0.23567833,  0.75417399, -0.90357685, -0.87489468,
+  //               0.54726779, -0.06705534, -0.15476358, -0.96940458
+  VLOAD_32(v3, 0x3f30dac8, 0xbea068b4, 0xbf0c4ffb, 0x3e801918, 0xbf2cc5c3,
+           0x3e6e2ca2, 0xbe0fc12a, 0x3dc783e8, 0xbe7155a9, 0x3f41118c,
+           0xbf6750d0, 0xbf5ff919, 0x3f0c19be, 0xbd895450, 0xbe1e7a58,
+           0xbf782ae6);
+  //               0.03722767,  0.80796093,  0.53925264, -0.50804031,
+  //               0.63562357, -0.45508829, -0.22051410,  0.42499006,
+  //               -0.59229839, -0.50074077, -0.80474108, -0.20762257,
+  //               0.15367362,  0.98349953, -0.15871963, -0.07445616
+  VLOAD_32(v1, 0x3d187c0a, 0x3f4ed687, 0x3f0a0c76, 0xbf020eee, 0x3f22b83a,
+           0xbee90155, 0xbe61ce73, 0x3ed9984c, 0xbf17a0de, 0xbf00308c,
+           0xbf4e0383, 0xbe549b03, 0x3e1d5c9e, 0x3f7bc6a0, 0xbe228766,
+           0xbd987c79);
+  asm volatile("vfnmadd.vv v1, v2, v3");
+  //              -0.67713100,  0.22849269,  0.72553790, -0.71928883,
+  //              0.40059602,  0.18944177,  0.00895807, -0.41666192, 0.73393923,
+  //              -0.58878565,  0.55422139,  1.07270420, -0.55774319,
+  //              0.94216329,  0.18424334,  1.01551294
+  VCMP_U32(2, v1, 0xbf2d5875, 0x3e69f9fd, 0x3f39bcda, 0xbf382350, 0x3ecd1aec,
+           0x3e41fd06, 0x3c12c4e5, 0xbed554b6, 0x3f3be371, 0xbf16baa7,
+           0x3f0de173, 0x3f894e5f, 0xbf0ec842, 0x3f71319d, 0x3e3caa49,
+           0x3f81fc54);
+
+  VSET(16, e64, m1);
+  //              -0.1517393950396491, -0.0976116299317518,  0.4195080955516000,
+  //              -0.8346165642452430,  0.0078216057137750, -0.5126918345148062,
+  //              -0.9302856586058497, -0.8971839537614414,  0.1317157676127678,
+  //              -0.3423297874984121,  0.7678405723111816, -0.6465198020108864,
+  //              0.4795090517472360, -0.9006147069685106,  0.9841759200408695,
+  //              0.8437352562659637
+  VLOAD_64(v2, 0xbfc36c324d9ae520, 0xbfb8fd1366442100, 0x3fdad9387bb34990,
+           0xbfeab52dcc044330, 0x3f8004c625f16600, 0xbfe067f8b4c55ad2,
+           0xbfedc4e66df4cc5a, 0xbfecb5bb1f7cd800, 0x3fc0dc0ff121d700,
+           0xbfd5e8bb327025d8, 0x3fe892266453ca54, 0xbfe4b04a4bbb4d06,
+           0x3fdeb046bbd8fb80, 0xbfecd1d5ef173e7a, 0x3fef7e5e7fc2c286,
+           0x3feaffe114849fb0);
+  //               0.3915682245289982,  0.0468282563045201,  0.4640582663413180,
+  //               0.9199907734666593, -0.6702920875531786,  0.6250479001245852,
+  //               -0.3716310293668668,  0.2191474803863191,
+  //               -0.3398132406457823, -0.1436002174993440,
+  //               -0.7049093483038609,  0.0726450331160087, 0.3054536350672581,
+  //               -0.9906780567812383,  0.2659677084286980, -0.6111168392293305
+  VLOAD_64(v3, 0x3fd90f742ba04f2c, 0x3fa7f9df8ab696e0, 0x3fddb3217157f678,
+           0x3fed70907d95274a, 0xbfe573086459defe, 0x3fe40064742efe82,
+           0xbfd7c8cd8353cefc, 0x3fcc0d064ea14910, 0xbfd5bf8008d49208,
+           0xbfc2617deeedd880, 0xbfe68e9e0cb3831e, 0x3fb298dd69733960,
+           0x3fd38c8d6743b96c, 0xbfefb3a277d7b020, 0x3fd1059d6c5f9294,
+           0xbfe38e44e6d0cbb0);
+  //               0.8932002267748917,  0.5237198185024288, -0.3716642114238491,
+  //               0.8806741908360942,  0.4285584084885536, -0.9185899240339090,
+  //               -0.3906189235600976, -0.8681987020972610,
+  //               -0.8703598457154336, -0.2254866845234647, 0.7002825787534324,
+  //               0.0892712008047818,  0.9241326299982451,  0.6615225744181676,
+  //               0.7351775340550828, -0.4044996673659886
+  VLOAD_64(v1, 0x3fec9518a458e4ea, 0x3fe0c25010978504, 0xbfd7c958b04a2e10,
+           0x3fec2e7ba402502e, 0x3fdb6d803f3895dc, 0xbfed6516b24524fa,
+           0xbfd8ffe68378eb00, 0xbfebc848a4fdff0a, 0xbfebd9fce4232e3a,
+           0xbfccdcbf67db1aa0, 0x3fe668b702b68b90, 0x3fb6da7a37ee6240,
+           0x3fed927e97e0492a, 0x3fe52b3163d622de, 0x3fe786930930a7fe,
+           0xbfd9e35292a51b70);
+  asm volatile("vfnmadd.vv v1, v2, v3");
+  //              -0.2560345624688988,  0.0042928888070631, -0.3081421208222118,
+  //              -0.1849655060915788,  0.6669400726566582, -1.0960014534443465,
+  //              0.0082438467988533, -0.9980814245844917,  0.4544533558235209,
+  //              0.0664094087027049,  0.1672039722542752, -0.0149294340464271,
+  //              -0.7485835961663959,  1.5864550162939111, -0.9895117344007368,
+  //              0.9524074697338700
+  VCMP_U64(3, v1, 0xbfd062deca1cc612, 0x3f71956b9081d880, 0xbfd3b899badce50e,
+           0xbfc7acf31fc694ed, 0x3fe55792b50e7883, 0xbff18938d1ee9749,
+           0x3f80e22663278b8b, 0xbfeff04874aabc45, 0x3fdd15c38734723f,
+           0x3fb10034fe865a4b, 0x3fc566f0944bf4a6, 0xbf8e9352b7d14aa9,
+           0xbfe7f46595fb6a6d, 0x3ff9621ea7b8eb80, 0xbfefaa1483484d07,
+           0x3fee7a1f3adf237b);
+};
+
+// Simple random test with similar values (masked)
+// The numbers are the same of TEST_CASE1
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  //              -0.7461,  0.0514, -0.3071, -0.4934, -0.5220, -0.7983,  0.4907,
+  //              -0.9028,  0.1752,  0.0676,  0.1040,  0.4526,  0.3525, -0.2686,
+  //              0.3540, -0.0847
+  VLOAD_16(v2, 0xb9f8, 0x2a94, 0xb4ea, 0xb7e5, 0xb82d, 0xba63, 0x37da, 0xbb39,
+           0x319b, 0x2c54, 0x2ea8, 0x373e, 0x35a4, 0xb44c, 0x35aa, 0xad6c);
+  //               0.1573, -0.7700,  0.0804, -0.9438,  0.0790,  0.7998, -0.2854,
+  //               0.1963, -0.0687, -0.2123,  0.3625, -0.0002,  0.7168, -0.4033,
+  //               0.2812, -0.3159
+  VLOAD_16(v3, 0x3109, 0xba29, 0x2d25, 0xbb8d, 0x2d0e, 0x3a66, 0xb491, 0x3248,
+           0xac65, 0xb2cb, 0x35cd, 0x897c, 0x39bc, 0xb674, 0x3480, 0xb50e);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //               0.0337,  0.2034, -0.1886,  0.8242,  0.3225,  0.0331,  0.0698,
+  //               0.6777, -0.2539, -0.5825, -0.4319, -0.6323,  0.0674, -0.2903,
+  //               -0.8145,  0.1893
+  VLOAD_16(v1, 0x284f, 0x3282, 0xb209, 0x3a98, 0x3529, 0x283b, 0x2c77, 0x396c,
+           0xb410, 0xb8a9, 0xb6e9, 0xb90f, 0x2c50, 0xb4a5, 0xba84, 0x320f);
+  asm volatile("vfnmadd.vv v1, v2, v3, v0.t");
+  //               0.0337,  0.7598, -0.1886,  1.3506,  0.3225, -0.7734,  0.0698,
+  //               0.4155, -0.2539,  0.2517, -0.4319,  0.2864,  0.0674,  0.3254,
+  //               -0.8145,  0.3320
+  VCMP_U16(4, v1, 0x284f, 0x3a14, 0xb209, 0x3d67, 0x3529, 0xba30, 0x2c77,
+           0x36a6, 0xb410, 0x3407, 0xb6e9, 0x3495, 0x2c50, 0x3535, 0xba84,
+           0x3550);
+
+  VSET(16, e32, m1);
+  //              -0.36820358,  0.10496315, -0.32905263, -0.92334682,
+  //              0.43153936,  0.92736709, -0.59600371,  0.75117606, 0.84123290,
+  //              0.33028743, -0.43412161,  0.95273590,  0.06816643,
+  //              -0.88978988,  0.18573478,  0.61926919
+  VLOAD_32(v2, 0xbebc852e, 0x3dd6f6ec, 0xbea87996, 0xbf6c6075, 0x3edcf2ba,
+           0x3f6d67ee, 0xbf1893b3, 0x3f404d13, 0x3f575b0a, 0x3ea91b6f,
+           0xbede4530, 0x3f73e680, 0x3d8b9ad8, 0xbf63c945, 0x3e3e3142,
+           0x3f1e886d);
+  //               0.69083834, -0.31329882, -0.54809541,  0.25019145,
+  //               -0.67489260,  0.23259214, -0.14038530,  0.09741956,
+  //               -0.23567833,  0.75417399, -0.90357685, -0.87489468,
+  //               0.54726779, -0.06705534, -0.15476358, -0.96940458
+  VLOAD_32(v3, 0x3f30dac8, 0xbea068b4, 0xbf0c4ffb, 0x3e801918, 0xbf2cc5c3,
+           0x3e6e2ca2, 0xbe0fc12a, 0x3dc783e8, 0xbe7155a9, 0x3f41118c,
+           0xbf6750d0, 0xbf5ff919, 0x3f0c19be, 0xbd895450, 0xbe1e7a58,
+           0xbf782ae6);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //               0.03722767,  0.80796093,  0.53925264, -0.50804031,
+  //               0.63562357, -0.45508829, -0.22051410,  0.42499006,
+  //               -0.59229839, -0.50074077, -0.80474108, -0.20762257,
+  //               0.15367362,  0.98349953, -0.15871963, -0.07445616
+  VLOAD_32(v1, 0x3d187c0a, 0x3f4ed687, 0x3f0a0c76, 0xbf020eee, 0x3f22b83a,
+           0xbee90155, 0xbe61ce73, 0x3ed9984c, 0xbf17a0de, 0xbf00308c,
+           0xbf4e0383, 0xbe549b03, 0x3e1d5c9e, 0x3f7bc6a0, 0xbe228766,
+           0xbd987c79);
+  asm volatile("vfnmadd.vv v1, v2, v3, v0.t");
+  //               0.03722767,  0.22849269,  0.53925264, -0.71928883,
+  //               0.63562357,  0.18944177, -0.22051410, -0.41666192,
+  //               -0.59229839, -0.58878565, -0.80474108,  1.07270420,
+  //               0.15367362,  0.94216329, -0.15871963,  1.01551294
+  VCMP_U32(5, v1, 0x3d187c0a, 0x3e69f9fd, 0x3f0a0c76, 0xbf382350, 0x3f22b83a,
+           0x3e41fd06, 0xbe61ce73, 0xbed554b6, 0xbf17a0de, 0xbf16baa7,
+           0xbf4e0383, 0x3f894e5f, 0x3e1d5c9e, 0x3f71319d, 0xbe228766,
+           0x3f81fc54);
+
+  VSET(16, e64, m1);
+  //              -0.1517393950396491, -0.0976116299317518,  0.4195080955516000,
+  //              -0.8346165642452430,  0.0078216057137750, -0.5126918345148062,
+  //              -0.9302856586058497, -0.8971839537614414,  0.1317157676127678,
+  //              -0.3423297874984121,  0.7678405723111816, -0.6465198020108864,
+  //              0.4795090517472360, -0.9006147069685106,  0.9841759200408695,
+  //              0.8437352562659637
+  VLOAD_64(v2, 0xbfc36c324d9ae520, 0xbfb8fd1366442100, 0x3fdad9387bb34990,
+           0xbfeab52dcc044330, 0x3f8004c625f16600, 0xbfe067f8b4c55ad2,
+           0xbfedc4e66df4cc5a, 0xbfecb5bb1f7cd800, 0x3fc0dc0ff121d700,
+           0xbfd5e8bb327025d8, 0x3fe892266453ca54, 0xbfe4b04a4bbb4d06,
+           0x3fdeb046bbd8fb80, 0xbfecd1d5ef173e7a, 0x3fef7e5e7fc2c286,
+           0x3feaffe114849fb0);
+  //               0.3915682245289982,  0.0468282563045201,  0.4640582663413180,
+  //               0.9199907734666593, -0.6702920875531786,  0.6250479001245852,
+  //               -0.3716310293668668,  0.2191474803863191,
+  //               -0.3398132406457823, -0.1436002174993440,
+  //               -0.7049093483038609,  0.0726450331160087, 0.3054536350672581,
+  //               -0.9906780567812383,  0.2659677084286980, -0.6111168392293305
+  VLOAD_64(v3, 0x3fd90f742ba04f2c, 0x3fa7f9df8ab696e0, 0x3fddb3217157f678,
+           0x3fed70907d95274a, 0xbfe573086459defe, 0x3fe40064742efe82,
+           0xbfd7c8cd8353cefc, 0x3fcc0d064ea14910, 0xbfd5bf8008d49208,
+           0xbfc2617deeedd880, 0xbfe68e9e0cb3831e, 0x3fb298dd69733960,
+           0x3fd38c8d6743b96c, 0xbfefb3a277d7b020, 0x3fd1059d6c5f9294,
+           0xbfe38e44e6d0cbb0);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //               0.8932002267748917,  0.5237198185024288, -0.3716642114238491,
+  //               0.8806741908360942,  0.4285584084885536, -0.9185899240339090,
+  //               -0.3906189235600976, -0.8681987020972610,
+  //               -0.8703598457154336, -0.2254866845234647, 0.7002825787534324,
+  //               0.0892712008047818,  0.9241326299982451,  0.6615225744181676,
+  //               0.7351775340550828, -0.4044996673659886
+  VLOAD_64(v1, 0x3fec9518a458e4ea, 0x3fe0c25010978504, 0xbfd7c958b04a2e10,
+           0x3fec2e7ba402502e, 0x3fdb6d803f3895dc, 0xbfed6516b24524fa,
+           0xbfd8ffe68378eb00, 0xbfebc848a4fdff0a, 0xbfebd9fce4232e3a,
+           0xbfccdcbf67db1aa0, 0x3fe668b702b68b90, 0x3fb6da7a37ee6240,
+           0x3fed927e97e0492a, 0x3fe52b3163d622de, 0x3fe786930930a7fe,
+           0xbfd9e35292a51b70);
+  asm volatile("vfnmadd.vv v1, v2, v3, v0.t");
+  //               0.8932002267748917,  0.0042928888070631, -0.3716642114238491,
+  //               -0.1849655060915788,  0.4285584084885536,
+  //               -1.0960014534443465, -0.3906189235600976,
+  //               -0.9980814245844917, -0.8703598457154336, 0.0664094087027049,
+  //               0.7002825787534324, -0.0149294340464271,
+  //               0.9241326299982451,  1.5864550162939111,  0.7351775340550828,
+  //               0.9524074697338700
+  VCMP_U64(6, v1, 0x3fec9518a458e4ea, 0x3f71956b9081d880, 0xbfd7c958b04a2e10,
+           0xbfc7acf31fc694ed, 0x3fdb6d803f3895dc, 0xbff18938d1ee9749,
+           0xbfd8ffe68378eb00, 0xbfeff04874aabc45, 0xbfebd9fce4232e3a,
+           0x3fb10034fe865a4b, 0x3fe668b702b68b90, 0xbf8e9352b7d14aa9,
+           0x3fed927e97e0492a, 0x3ff9621ea7b8eb80, 0x3fe786930930a7fe,
+           0x3fee7a1f3adf237b);
+};
+
+// Simple random test with similar values (vector-scalar)
+void TEST_CASE3(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //                              0.2646
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0x343c);
+  //               0.4216, -0.2148,  0.0047,  0.6802, -0.8965, -0.2986, -0.1786,
+  //               -0.1904,  0.2805,  0.5322, -0.5298,  0.3208,  0.0567,
+  //               -0.9897, -0.5400, -0.4187
+  VLOAD_16(v2, 0x36bf, 0xb2e0, 0x1cc3, 0x3971, 0xbb2c, 0xb4c7, 0xb1b7, 0xb218,
+           0x347d, 0x3842, 0xb83d, 0x3522, 0x2b41, 0xbbeb, 0xb852, 0xb6b3);
+  //              -0.7886, -0.5435, -0.8345,  0.7793,  0.5796, -0.8374, -0.8623,
+  //              -0.3313, -0.2690, -0.9214,  0.2126, -0.6772, -0.6514, -0.5703,
+  //              -0.2585, -0.3320
+  VLOAD_16(v1, 0xba4f, 0xb859, 0xbaad, 0x3a3c, 0x38a3, 0xbab3, 0xbae6, 0xb54d,
+           0xb44e, 0xbb5f, 0x32ce, 0xb96b, 0xb936, 0xb890, 0xb423, 0xb550);
+  asm volatile("vfnmadd.vf v1, %[A], v2" ::[A] "f"(dscalar_16));
+  //              -0.2129,  0.3586,  0.2162, -0.8867,  0.7432,  0.5200,  0.4067,
+  //              0.2781, -0.2092, -0.2883,  0.4736, -0.1416,  0.1157,  1.1406,
+  //              0.6084,  0.5068
+  VCMP_U16(7, v1, 0xb2d0, 0x35bd, 0x32eb, 0xbb17, 0x39f2, 0x3829, 0x3682,
+           0x3473, 0xb2b3, 0xb49d, 0x3793, 0xb088, 0x2f68, 0x3c90, 0x38de,
+           0x380d);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                              -0.13809182
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0xbe0d67f1);
+  //              -0.16977388, -0.30800357, -0.37010264, -0.92290556,
+  //              0.55768263,  0.47349435,  0.77556002,  0.16363664, 0.80314618,
+  //              -0.48171839, -0.60694915,  0.16937894,  0.86316317,
+  //              0.00897404, -0.96310323, -0.27890080
+  VLOAD_32(v2, 0xbe2dd934, 0xbe9db2a5, 0xbebd7e18, 0xbf6c438a, 0x3f0ec44a,
+           0x3ef26dda, 0x3f468b1a, 0x3e27905d, 0x3f4d9afd, 0xbef6a3cb,
+           0xbf1b6105, 0x3e2d71ac, 0x3f5cf843, 0x3c1307df, 0xbf768def,
+           0xbe8ecc16);
+  //              -0.33133313, -0.48972869,  0.95656961, -0.89211702,
+  //              0.72045243, -0.36672497,  0.69402671,  0.44954479,
+  //              -0.77024877, -0.83221292,  0.37576449, -0.77536738,
+  //              -0.55040795, -0.71568310, -0.75874990,  0.91956782
+  VLOAD_32(v1, 0xbea9a47f, 0xbefabdb8, 0x3f74e1bf, 0xbf6461c8, 0x3f386f92,
+           0xbebbc360, 0x3f31abbc, 0x3ee62abc, 0xbf452f06, 0xbf550be8,
+           0x3ec06434, 0xbf467e7a, 0xbf0ce789, 0xbf373702, 0xbf423d6f,
+           0x3f6b68cc);
+  asm volatile("vfnmadd.vf v1, %[A], v2" ::[A] "f"(dscalar_32));
+  //               0.12401948,  0.24037606,  0.50219709,  0.79971153,
+  //               -0.45819405, -0.52413607, -0.67972064, -0.10155818,
+  //               -0.90951121,  0.36679661,  0.65883917, -0.27645081,
+  //               -0.93917000, -0.10780402,  0.85832608,  0.40588558
+  VCMP_U32(8, v1, 0x3dfdfded, 0x3e762524, 0x3f008ffd, 0x3f4cb9e5, 0xbeea9869,
+           0xbf062dc8, 0xbf2e022c, 0xbdcffdbd, 0xbf68d5ba, 0x3ebbccc3,
+           0x3f28a9af, 0xbe8d8af6, 0xbf706d72, 0xbddcc85b, 0x3f5bbb42,
+           0x3ecfd03d);
+
+  VSET(16, e64, m1);
+  double dscalar_64;
+  //                                0.8978909040536565
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0x3fecbb85b489299a);
+  //                0.4119623576675431, -0.1190899643735133, 0.9903323592718865,
+  //                0.5311038519754858,  0.1686986553141236,
+  //                -0.8788301781199843,  0.1880579223718752,
+  //                0.7610824660598337, -0.0872931389118274,
+  //                -0.6855627317033812, -0.0181686933036735,
+  //                -0.9796673648941667,  0.2148282430178909,
+  //                -0.1529278220414154, -0.7708574130314993,
+  //                -0.4104905538508556
+  VLOAD_64(v2, 0x3fda5d975d575ea8, 0xbfbe7cae0e441b80, 0x3fefb0cd7ce7c8e8,
+           0x3fe0fecd81607572, 0x3fc597eae3ba06f8, 0xbfec1f6077386c08,
+           0x3fc81248312ba2f8, 0x3fe85ac99da9270a, 0xbfb658d7d8ca9eb0,
+           0xbfe5f0214100b7de, 0xbf929ad05e338a40, 0xbfef596f5fa5b9ea,
+           0x3fcb7f7deb026e00, 0xbfc393238d287f60, 0xbfe8aadd2a5b2eba,
+           0xbfda457a2c06ce78);
+  //                0.5050016609492949,  0.8257750946258060,
+  //                -0.2631016891694440,  0.8041841986447893,
+  //                -0.0322547653971421, -0.3994438840519345,
+  //                -0.6154540433263920, -0.9209485498858390,
+  //                0.3334000822950238, -0.6004917796663505, 0.4588428764280068,
+  //                0.8937156106780619,  0.8421999503441004, 0.3083609158934253,
+  //                -0.2219824502919918,  0.5118870280625194
+  VLOAD_64(v1, 0x3fe028f93e467e2c, 0x3fea6cbfe4289cd0, 0xbfd0d6a877a053e0,
+           0x3fe9bbe080247574, 0xbfa083b2550ab080, 0xbfd9907d14a5c710,
+           0xbfe3b1ccad88e3e8, 0xbfed786917e1dd9e, 0x3fd5566d4c7c36a8,
+           0xbfe3373a8965e1cc, 0x3fdd5dae8310b1e8, 0x3fec99517af92ea6,
+           0x3feaf34d4f6d76aa, 0x3fd3bc2f6c481e9c, 0xbfcc69ebc2252060,
+           0x3fe06160e798ce12);
+  asm volatile("vfnmadd.vf v1, %[A], v2" ::[A] "f"(dscalar_64));
+  //              -0.8653987555659035, -0.6223659818850454, -0.7540957457254903,
+  //              -1.2531735291223209, -0.1397373948516451,  1.2374872082900796,
+  //              0.3645526649939371,  0.0658288599840662,
+  //              -0.2120637623916150,  1.2247388386247897, -0.3938221518308497,
+  //              0.1772082472555760, -0.9710319178262998, -0.1239466395049457,
+  //              0.9701734360082217, -0.0491281525495393
+  VCMP_U64(9, v1, 0xbfebb158bb24f2ec, 0xbfe3ea6c104adab7, 0xbfe8218d66be32e5,
+           0xbff40cffafbcb13e, 0xbfc1e2ea3a754147, 0x3ff3ccbf630d300f,
+           0x3fd754d4b3746402, 0x3fb0da2900c3b814, 0xbfcb24e7c611c0f4,
+           0x3ff39887c0a08d49, 0xbfd93461d3a37236, 0x3fc6aec28545a7b7,
+           0xbfef12b1874df4ac, 0xbfbfbaf78b1f72ad, 0x3fef0ba929634dea,
+           0xbfa927534106be44);
+};
+
+// Simple random test with similar values (vector-scalar) (masked)
+void TEST_CASE4(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //                              0.2646
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0x343c);
+  //                0.4216, -0.2148,  0.0047,  0.6802, -0.8965, -0.2986,
+  //                -0.1786, -0.1904,  0.2805,  0.5322, -0.5298,  0.3208,
+  //                0.0567, -0.9897, -0.5400, -0.4187
+  VLOAD_16(v2, 0x36bf, 0xb2e0, 0x1cc3, 0x3971, 0xbb2c, 0xb4c7, 0xb1b7, 0xb218,
+           0x347d, 0x3842, 0xb83d, 0x3522, 0x2b41, 0xbbeb, 0xb852, 0xb6b3);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //               -0.7886, -0.5435, -0.8345,  0.7793,  0.5796, -0.8374,
+  //               -0.8623, -0.3313, -0.2690, -0.9214,  0.2126, -0.6772,
+  //               -0.6514, -0.5703, -0.2585, -0.3320
+  VLOAD_16(v1, 0xba4f, 0xb859, 0xbaad, 0x3a3c, 0x38a3, 0xbab3, 0xbae6, 0xb54d,
+           0xb44e, 0xbb5f, 0x32ce, 0xb96b, 0xb936, 0xb890, 0xb423, 0xb550);
+  asm volatile("vfnmadd.vf v1, %[A], v2, v0.t" ::[A] "f"(dscalar_16));
+  //               -0.7886,  0.3586, -0.8345, -0.8867,  0.5796,  0.5200,
+  //               -0.8623,  0.2781, -0.2690, -0.2883,  0.2126, -0.1416,
+  //               -0.6514,  1.1406, -0.2585,  0.5068
+  VCMP_U16(10, v1, 0xba4f, 0x35bd, 0xbaad, 0xbb17, 0x38a3, 0x3829, 0xbae6,
+           0x3473, 0xb44e, 0xb49d, 0x32ce, 0xb088, 0xb936, 0x3c90, 0xb423,
+           0x380d);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                              -0.13809182
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0xbe0d67f1);
+  //               -0.16977388, -0.30800357, -0.37010264, -0.92290556,
+  //               0.55768263,  0.47349435,  0.77556002,  0.16363664,
+  //               0.80314618, -0.48171839, -0.60694915,  0.16937894,
+  //               0.86316317,  0.00897404, -0.96310323, -0.27890080
+  VLOAD_32(v2, 0xbe2dd934, 0xbe9db2a5, 0xbebd7e18, 0xbf6c438a, 0x3f0ec44a,
+           0x3ef26dda, 0x3f468b1a, 0x3e27905d, 0x3f4d9afd, 0xbef6a3cb,
+           0xbf1b6105, 0x3e2d71ac, 0x3f5cf843, 0x3c1307df, 0xbf768def,
+           0xbe8ecc16);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //               -0.33133313, -0.48972869,  0.95656961, -0.89211702,
+  //               0.72045243, -0.36672497,  0.69402671,  0.44954479,
+  //               -0.77024877, -0.83221292,  0.37576449, -0.77536738,
+  //               -0.55040795, -0.71568310, -0.75874990,  0.91956782
+  VLOAD_32(v1, 0xbea9a47f, 0xbefabdb8, 0x3f74e1bf, 0xbf6461c8, 0x3f386f92,
+           0xbebbc360, 0x3f31abbc, 0x3ee62abc, 0xbf452f06, 0xbf550be8,
+           0x3ec06434, 0xbf467e7a, 0xbf0ce789, 0xbf373702, 0xbf423d6f,
+           0x3f6b68cc);
+  asm volatile("vfnmadd.vf v1, %[A], v2, v0.t" ::[A] "f"(dscalar_32));
+  //               -0.33133313,  0.24037606,  0.95656961,  0.79971153,
+  //               0.72045243, -0.52413607,  0.69402671, -0.10155818,
+  //               -0.77024877,  0.36679661,  0.37576449, -0.27645081,
+  //               -0.55040795, -0.10780402, -0.75874990,  0.40588558
+  VCMP_U32(11, v1, 0xbea9a47f, 0x3e762524, 0x3f74e1bf, 0x3f4cb9e5, 0x3f386f92,
+           0xbf062dc8, 0x3f31abbc, 0xbdcffdbd, 0xbf452f06, 0x3ebbccc3,
+           0x3ec06434, 0xbe8d8af6, 0xbf0ce789, 0xbddcc85b, 0xbf423d6f,
+           0x3ecfd03d);
+
+  VSET(16, e64, m1);
+  double dscalar_64;
+  //                                0.8978909040536565
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0x3fecbb85b489299a);
+  //                 0.4119623576675431, -0.1190899643735133,
+  //                 0.9903323592718865,  0.5311038519754858,
+  //                 0.1686986553141236, -0.8788301781199843,
+  //                 0.1880579223718752,  0.7610824660598337,
+  //                 -0.0872931389118274, -0.6855627317033812,
+  //                 -0.0181686933036735, -0.9796673648941667,
+  //                 0.2148282430178909, -0.1529278220414154,
+  //                 -0.7708574130314993, -0.4104905538508556
+  VLOAD_64(v2, 0x3fda5d975d575ea8, 0xbfbe7cae0e441b80, 0x3fefb0cd7ce7c8e8,
+           0x3fe0fecd81607572, 0x3fc597eae3ba06f8, 0xbfec1f6077386c08,
+           0x3fc81248312ba2f8, 0x3fe85ac99da9270a, 0xbfb658d7d8ca9eb0,
+           0xbfe5f0214100b7de, 0xbf929ad05e338a40, 0xbfef596f5fa5b9ea,
+           0x3fcb7f7deb026e00, 0xbfc393238d287f60, 0xbfe8aadd2a5b2eba,
+           0xbfda457a2c06ce78);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //                 0.5050016609492949,  0.8257750946258060,
+  //                 -0.2631016891694440,  0.8041841986447893,
+  //                 -0.0322547653971421, -0.3994438840519345,
+  //                 -0.6154540433263920, -0.9209485498858390,
+  //                 0.3334000822950238, -0.6004917796663505,
+  //                 0.4588428764280068,  0.8937156106780619,
+  //                 0.8421999503441004,  0.3083609158934253,
+  //                 -0.2219824502919918,  0.5118870280625194
+  VLOAD_64(v1, 0x3fe028f93e467e2c, 0x3fea6cbfe4289cd0, 0xbfd0d6a877a053e0,
+           0x3fe9bbe080247574, 0xbfa083b2550ab080, 0xbfd9907d14a5c710,
+           0xbfe3b1ccad88e3e8, 0xbfed786917e1dd9e, 0x3fd5566d4c7c36a8,
+           0xbfe3373a8965e1cc, 0x3fdd5dae8310b1e8, 0x3fec99517af92ea6,
+           0x3feaf34d4f6d76aa, 0x3fd3bc2f6c481e9c, 0xbfcc69ebc2252060,
+           0x3fe06160e798ce12);
+  asm volatile("vfnmadd.vf v1, %[A], v2, v0.t" ::[A] "f"(dscalar_64));
+  //                0.5050016609492949, -0.6223659818850454,
+  //                -0.2631016891694440, -1.2531735291223209,
+  //                -0.0322547653971421,  1.2374872082900796,
+  //                -0.6154540433263920,  0.0658288599840662,
+  //                0.3334000822950238,  1.2247388386247897, 0.4588428764280068,
+  //                0.1772082472555760,  0.8421999503441004,
+  //                -0.1239466395049457, -0.2219824502919918,
+  //                -0.0491281525495393
+  VCMP_U64(12, v1, 0x3fe028f93e467e2c, 0xbfe3ea6c104adab7, 0xbfd0d6a877a053e0,
+           0xbff40cffafbcb13e, 0xbfa083b2550ab080, 0x3ff3ccbf630d300f,
+           0xbfe3b1ccad88e3e8, 0x3fb0da2900c3b814, 0x3fd5566d4c7c36a8,
+           0x3ff39887c0a08d49, 0x3fdd5dae8310b1e8, 0x3fc6aec28545a7b7,
+           0x3feaf34d4f6d76aa, 0xbfbfbaf78b1f72ad, 0xbfcc69ebc2252060,
+           0xbfa927534106be44);
+};
+
+int main(void) {
+  enable_vec();
+  enable_fp();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vfnmsac.c b/apps/riscv-tests/isa/rv64uv/vfnmsac.c
new file mode 100644
index 0000000..7db965a
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vfnmsac.c
@@ -0,0 +1,455 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+// Simple random test with similar values
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  //               0.3474, -0.9888,  0.2810,  0.4199,  0.1704, -0.3772,  0.2998,
+  //               0.7871, -0.2527, -0.8618,  0.2646,  0.5488, -0.3184, -0.3508,
+  //               -0.3589, -0.3914
+  VLOAD_16(v2, 0x358f, 0xbbe9, 0x347f, 0x36b8, 0x3174, 0xb609, 0x34cc, 0x3a4c,
+           0xb40b, 0xbae5, 0x343c, 0x3864, 0xb518, 0xb59d, 0xb5be, 0xb643);
+  //               0.0417,  0.3862, -0.9619, -0.5659,  0.1731,  0.4827,  0.7334,
+  //               -0.7271, -0.9814,  0.8003, -0.4836,  0.5234, -0.8540,
+  //               -0.2036, -0.8823,  0.2603
+  VLOAD_16(v3, 0x2958, 0x362e, 0xbbb2, 0xb887, 0x318a, 0x37b9, 0x39de, 0xb9d1,
+           0xbbda, 0x3a67, 0xb7bd, 0x3830, 0xbad5, 0xb284, 0xbb0f, 0x342a);
+  //              -0.2739,  0.2146,  0.5264, -0.8853,  0.8877, -0.6748, -0.7563,
+  //              -0.9634,  0.7451, -0.5166,  0.0698,  0.4790, -0.0681, -0.9746,
+  //              0.2129,  0.9072
+  VLOAD_16(v1, 0xb462, 0x32de, 0x3836, 0xbb15, 0x3b1a, 0xb966, 0xba0d, 0xbbb5,
+           0x39f6, 0xb822, 0x2c77, 0x37aa, 0xac5b, 0xbbcc, 0x32d0, 0x3b42);
+  asm volatile("vfnmsac.vv v1, v2, v3");
+  //              -0.2883,  0.5967,  0.7969, -0.6475,  0.8584, -0.4927, -0.9761,
+  //              -0.3911,  0.4971,  0.1733,  0.1978,  0.1917, -0.3401, -1.0459,
+  //              -0.1038,  1.0088
+  VCMP_U16(1, v1, 0xb49d, 0x38c6, 0x3a60, 0xb92e, 0x3ade, 0xb7e2, 0xbbcf,
+           0xb642, 0x37f4, 0x318a, 0x3254, 0x3223, 0xb570, 0xbc2f, 0xaea4,
+           0x3c09);
+
+  VSET(16, e32, m1);
+  //               0.11577118, -0.10074481,  0.13861528,  0.44782066,
+  //               0.42196107, -0.67597556,  0.34948668, -0.87903690,
+  //               -0.34136006, -0.19722189,  0.76997000, -0.68663412,
+  //               0.45603558,  0.60629857, -0.86984915, -0.08019307
+  VLOAD_32(v2, 0x3ded1971, 0xbdce534c, 0x3e0df12a, 0x3ee548c0, 0x3ed80b48,
+           0xbf2d0cbc, 0x3eb2efeb, 0xbf610890, 0xbeaec6bf, 0xbe49f489,
+           0x3f451cc1, 0xbf2fc741, 0x3ee97d7f, 0x3f1b3662, 0xbf5eae6f,
+           0xbda43c43);
+  //              -0.38970658,  0.40460527,  0.69067985, -0.98108912,
+  //              0.47494572, -0.34277225, -0.54462087, -0.90492284, 0.60100728,
+  //              -0.02819708, -0.46859986,  0.87238866,  0.46812481,
+  //              0.49922746,  0.97036403,  0.04279163
+  VLOAD_32(v3, 0xbec7879f, 0x3ecf286c, 0x3f30d065, 0xbf7b28a8, 0x3ef32c16,
+           0xbeaf7fd8, 0xbf0b6c46, 0xbf67a906, 0x3f19db9d, 0xbce6fd92,
+           0xbeefec52, 0x3f5f54dd, 0x3eefae0e, 0x3eff9abe, 0x3f7869c7,
+           0x3d2f4647);
+  //               0.79804420, -0.70010293, -0.51047552,  0.38566175,
+  //               0.15318950,  0.15531392, -0.20705318, -0.82493448,
+  //               0.12047531,  0.57526720,  0.23939800, -0.19725421,
+  //               0.15403098,  0.03931713, -0.45930895, -0.15395784
+  VLOAD_32(v1, 0x3f4c4ca0, 0xbf3339f2, 0xbf02ae86, 0x3ec57575, 0x3e1cddb5,
+           0x3e1f0a9d, 0xbe5405c0, 0xbf532ee8, 0x3df6bbc3, 0x3f1344b6,
+           0x3e7524c0, 0xbe49fd02, 0x3e1dba4c, 0x3d210b00, 0xbeeb2a8b,
+           0xbe1da720);
+  asm volatile("vfnmsac.vv v1, v2, v3");
+  //               0.84316099, -0.65934104, -0.60621428,  0.82501376,
+  //               -0.04721911, -0.07639174, -0.01671545, -1.62039506,
+  //               0.32563519,  0.56970614,  0.60020584,  0.40175763,
+  //               -0.05945060, -0.26336378,  0.38476136, -0.15052626
+  VCMP_U32(2, v1, 0x3f57d966, 0xbf28ca93, 0xbf1b30dc, 0x3f53341a, 0xbd4168d3,
+           0xbd9c7345, 0xbc88eed4, 0xbfcf691b, 0x3ea6b9a8, 0x3f11d843,
+           0x3f19a717, 0x3ecdb32c, 0xbd738277, 0xbe86d79e, 0x3ec4ff71,
+           0xbe1a238e);
+
+  VSET(16, e64, m1);
+  //              -0.1779684802061718,  0.1122733699429854, -0.0166033088608786,
+  //              -0.0418350503858864,  0.0809510021720363, -0.9993917101510512,
+  //              -0.2139048161619248,  0.7196716914796224,  0.6489783595942558,
+  //              0.5950689618839839, -0.7376256302221853, -0.5442228345597713,
+  //              -0.8234113806545975, -0.6424001059348645, -0.3817524674245201,
+  //              -0.8801262923106541
+  VLOAD_64(v2, 0xbfc6c7abd11a2788, 0x3fbcbdf2941de8b0, 0xbf91007532405e80,
+           0xbfa56b675a77c100, 0x3fb4b93472e84630, 0xbfeffb0452dfc0ba,
+           0xbfcb613ba6efa978, 0x3fe7078ced586224, 0x3fe4c46e43c89c1c,
+           0x3fe30ace10450114, 0xbfe79aa110cfdc92, 0xbfe16a46018575da,
+           0xbfea5962d2e21a3e, 0xbfe48e8aaabdfd5e, 0xbfd86ea1e6b05c10,
+           0xbfec29fe9d3a5e2c);
+  //               0.6809772463364707, -0.3512739833826983, -0.3746023351803702,
+  //               -0.7912172181005324,  0.8292434726428350, 0.4103374079106952,
+  //               -0.0850673796598582, -0.5834949864830523,
+  //               -0.9215678788036654,  0.4412210589054084, 0.3537359089001260,
+  //               -0.4889461402031243,  0.2341577339668230, 0.0593866008892341,
+  //               -0.4825773777931026,  0.8989772522533539
+  VLOAD_64(v3, 0x3fe5ca90cb4aba98, 0xbfd67b45dfa41e18, 0xbfd7f97c12a6b704,
+           0xbfe951a6c578c3ac, 0x3fea89299b6d84b0, 0x3fda42f7d4d35178,
+           0xbfb5c6f9cd987320, 0xbfe2abfdad8a63b6, 0xbfed7d7beb902fcc,
+           0x3fdc3cf7409388b4, 0x3fd6a39bf009666c, 0xbfdf4ae4c06b61e4,
+           0x3fcdf8e170bf19c0, 0x3fae67eba9479c60, 0xbfdee28c39da4ac0,
+           0x3fecc46bf148d5ca);
+  //               0.2213384305747967, -0.6962211546566610, -0.0896076892809434,
+  //               -0.1334142611967066,  0.1988436916560323,
+  //               -0.3391391007320459, -0.6137202819751713, 0.6759552396290200,
+  //               -0.7798663937316326, -0.1025181838739857, 0.5296250728149803,
+  //               0.8832422045338422,  0.8373555508937671, -0.8622529212135799,
+  //               0.4241832213372883,  0.7769982087360683
+  VLOAD_64(v1, 0x3fcc54d154555708, 0xbfe6477196411436, 0xbfb6f0878eee8940,
+           0xbfc113b7f0547630, 0x3fc973b5c856db48, 0xbfd5b4747c9c185c,
+           0xbfe3a398b77f3552, 0x3fe5a16ce1f8870a, 0xbfe8f4aa5e0a7552,
+           0xbfba3ea1b6fbece0, 0x3fe0f2b047dc3902, 0x3fec438527dd6ef6,
+           0x3feacb9dde46cf34, 0xbfeb9793702fc4f0, 0x3fdb25d161c9f510,
+           0x3fe8dd2b58f24dc8);
+  asm volatile("vfnmsac.vv v1, v2, v3");
+  //               0.3425309161602823, -0.6567824407689892, -0.0958273275519495,
+  //               -0.1665148733821233,  0.1317156015009752, 0.0709487030987733,
+  //               -0.6319166041826899,  1.0958800635211576,
+  //               -0.1817887834908719, -0.3650751413581792, 0.7905497455496533,
+  //               0.6171465501654385,  1.0301636939103409, -0.8241029625112244,
+  //               0.2399581166415165,  1.5682117246334322
+  VCMP_U64(3, v1, 0x3fd5ec06cab1bfc9, 0xbfe5045c9bf61361, 0xbfb88823c5e61162,
+           0xbfc5505bffbca57e, 0x3fc0dc0e8c68ea87, 0x3fb229b1b780ba72,
+           0xbfe438a92b9872ef, 0x3ff188b9889296a1, 0xbfc744dad7efbbd3,
+           0xbfd75d64202dd23c, 0x3fe94c2efadfe675, 0x3fe3bfaa1f3997d0,
+           0x3ff07b8cecedf189, 0xbfea5f0d2d10b7b0, 0x3fceb6f293b149df,
+           0x3ff917652d6811d0);
+};
+
+// Simple random test with similar values (masked)
+// The numbers are the same of TEST_CASE1
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  //               0.3474, -0.9888,  0.2810,  0.4199,  0.1704, -0.3772,  0.2998,
+  //               0.7871, -0.2527, -0.8618,  0.2646,  0.5488, -0.3184, -0.3508,
+  //               -0.3589, -0.3914
+  VLOAD_16(v2, 0x358f, 0xbbe9, 0x347f, 0x36b8, 0x3174, 0xb609, 0x34cc, 0x3a4c,
+           0xb40b, 0xbae5, 0x343c, 0x3864, 0xb518, 0xb59d, 0xb5be, 0xb643);
+  //               0.0417,  0.3862, -0.9619, -0.5659,  0.1731,  0.4827,  0.7334,
+  //               -0.7271, -0.9814,  0.8003, -0.4836,  0.5234, -0.8540,
+  //               -0.2036, -0.8823,  0.2603
+  VLOAD_16(v3, 0x2958, 0x362e, 0xbbb2, 0xb887, 0x318a, 0x37b9, 0x39de, 0xb9d1,
+           0xbbda, 0x3a67, 0xb7bd, 0x3830, 0xbad5, 0xb284, 0xbb0f, 0x342a);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //              -0.2739,  0.2146,  0.5264, -0.8853,  0.8877, -0.6748, -0.7563,
+  //              -0.9634,  0.7451, -0.5166,  0.0698,  0.4790, -0.0681, -0.9746,
+  //              0.2129,  0.9072
+  VLOAD_16(v1, 0xb462, 0x32de, 0x3836, 0xbb15, 0x3b1a, 0xb966, 0xba0d, 0xbbb5,
+           0x39f6, 0xb822, 0x2c77, 0x37aa, 0xac5b, 0xbbcc, 0x32d0, 0x3b42);
+  asm volatile("vfnmsac.vv v1, v2, v3, v0.t");
+  //              -0.2739,  0.5967,  0.5264, -0.6475,  0.8877, -0.4927, -0.7563,
+  //              -0.3911,  0.7451,  0.1733,  0.0698,  0.1917, -0.0681, -1.0459,
+  //              0.2129,  1.0088
+  VCMP_U16(4, v1, 0xb462, 0x38c6, 0x3836, 0xb92e, 0x3b1a, 0xb7e2, 0xba0d,
+           0xb642, 0x39f6, 0x318a, 0x2c77, 0x3223, 0xac5b, 0xbc2f, 0x32d0,
+           0x3c09);
+
+  VSET(16, e32, m1);
+  //               0.11577118, -0.10074481,  0.13861528,  0.44782066,
+  //               0.42196107, -0.67597556,  0.34948668, -0.87903690,
+  //               -0.34136006, -0.19722189,  0.76997000, -0.68663412,
+  //               0.45603558,  0.60629857, -0.86984915, -0.08019307
+  VLOAD_32(v2, 0x3ded1971, 0xbdce534c, 0x3e0df12a, 0x3ee548c0, 0x3ed80b48,
+           0xbf2d0cbc, 0x3eb2efeb, 0xbf610890, 0xbeaec6bf, 0xbe49f489,
+           0x3f451cc1, 0xbf2fc741, 0x3ee97d7f, 0x3f1b3662, 0xbf5eae6f,
+           0xbda43c43);
+  //              -0.38970658,  0.40460527,  0.69067985, -0.98108912,
+  //              0.47494572, -0.34277225, -0.54462087, -0.90492284, 0.60100728,
+  //              -0.02819708, -0.46859986,  0.87238866,  0.46812481,
+  //              0.49922746,  0.97036403,  0.04279163
+  VLOAD_32(v3, 0xbec7879f, 0x3ecf286c, 0x3f30d065, 0xbf7b28a8, 0x3ef32c16,
+           0xbeaf7fd8, 0xbf0b6c46, 0xbf67a906, 0x3f19db9d, 0xbce6fd92,
+           0xbeefec52, 0x3f5f54dd, 0x3eefae0e, 0x3eff9abe, 0x3f7869c7,
+           0x3d2f4647);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //               0.79804420, -0.70010293, -0.51047552,  0.38566175,
+  //               0.15318950,  0.15531392, -0.20705318, -0.82493448,
+  //               0.12047531,  0.57526720,  0.23939800, -0.19725421,
+  //               0.15403098,  0.03931713, -0.45930895, -0.15395784
+  VLOAD_32(v1, 0x3f4c4ca0, 0xbf3339f2, 0xbf02ae86, 0x3ec57575, 0x3e1cddb5,
+           0x3e1f0a9d, 0xbe5405c0, 0xbf532ee8, 0x3df6bbc3, 0x3f1344b6,
+           0x3e7524c0, 0xbe49fd02, 0x3e1dba4c, 0x3d210b00, 0xbeeb2a8b,
+           0xbe1da720);
+  asm volatile("vfnmsac.vv v1, v2, v3, v0.t");
+  //               0.79804420, -0.65934104, -0.51047552,  0.82501376,
+  //               0.15318950, -0.07639174, -0.20705318, -1.62039506,
+  //               0.12047531,  0.56970614,  0.23939800,  0.40175763,
+  //               0.15403098, -0.26336378, -0.45930895, -0.15052626
+  VCMP_U32(5, v1, 0x3f4c4ca0, 0xbf28ca93, 0xbf02ae86, 0x3f53341a, 0x3e1cddb5,
+           0xbd9c7345, 0xbe5405c0, 0xbfcf691b, 0x3df6bbc3, 0x3f11d843,
+           0x3e7524c0, 0x3ecdb32c, 0x3e1dba4c, 0xbe86d79e, 0xbeeb2a8b,
+           0xbe1a238e);
+
+  VSET(16, e64, m1);
+  //              -0.1779684802061718,  0.1122733699429854, -0.0166033088608786,
+  //              -0.0418350503858864,  0.0809510021720363, -0.9993917101510512,
+  //              -0.2139048161619248,  0.7196716914796224,  0.6489783595942558,
+  //              0.5950689618839839, -0.7376256302221853, -0.5442228345597713,
+  //              -0.8234113806545975, -0.6424001059348645, -0.3817524674245201,
+  //              -0.8801262923106541
+  VLOAD_64(v2, 0xbfc6c7abd11a2788, 0x3fbcbdf2941de8b0, 0xbf91007532405e80,
+           0xbfa56b675a77c100, 0x3fb4b93472e84630, 0xbfeffb0452dfc0ba,
+           0xbfcb613ba6efa978, 0x3fe7078ced586224, 0x3fe4c46e43c89c1c,
+           0x3fe30ace10450114, 0xbfe79aa110cfdc92, 0xbfe16a46018575da,
+           0xbfea5962d2e21a3e, 0xbfe48e8aaabdfd5e, 0xbfd86ea1e6b05c10,
+           0xbfec29fe9d3a5e2c);
+  //               0.6809772463364707, -0.3512739833826983, -0.3746023351803702,
+  //               -0.7912172181005324,  0.8292434726428350, 0.4103374079106952,
+  //               -0.0850673796598582, -0.5834949864830523,
+  //               -0.9215678788036654,  0.4412210589054084, 0.3537359089001260,
+  //               -0.4889461402031243,  0.2341577339668230, 0.0593866008892341,
+  //               -0.4825773777931026,  0.8989772522533539
+  VLOAD_64(v3, 0x3fe5ca90cb4aba98, 0xbfd67b45dfa41e18, 0xbfd7f97c12a6b704,
+           0xbfe951a6c578c3ac, 0x3fea89299b6d84b0, 0x3fda42f7d4d35178,
+           0xbfb5c6f9cd987320, 0xbfe2abfdad8a63b6, 0xbfed7d7beb902fcc,
+           0x3fdc3cf7409388b4, 0x3fd6a39bf009666c, 0xbfdf4ae4c06b61e4,
+           0x3fcdf8e170bf19c0, 0x3fae67eba9479c60, 0xbfdee28c39da4ac0,
+           0x3fecc46bf148d5ca);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //               0.2213384305747967, -0.6962211546566610, -0.0896076892809434,
+  //               -0.1334142611967066,  0.1988436916560323,
+  //               -0.3391391007320459, -0.6137202819751713, 0.6759552396290200,
+  //               -0.7798663937316326, -0.1025181838739857, 0.5296250728149803,
+  //               0.8832422045338422,  0.8373555508937671, -0.8622529212135799,
+  //               0.4241832213372883,  0.7769982087360683
+  VLOAD_64(v1, 0x3fcc54d154555708, 0xbfe6477196411436, 0xbfb6f0878eee8940,
+           0xbfc113b7f0547630, 0x3fc973b5c856db48, 0xbfd5b4747c9c185c,
+           0xbfe3a398b77f3552, 0x3fe5a16ce1f8870a, 0xbfe8f4aa5e0a7552,
+           0xbfba3ea1b6fbece0, 0x3fe0f2b047dc3902, 0x3fec438527dd6ef6,
+           0x3feacb9dde46cf34, 0xbfeb9793702fc4f0, 0x3fdb25d161c9f510,
+           0x3fe8dd2b58f24dc8);
+  asm volatile("vfnmsac.vv v1, v2, v3, v0.t");
+  //               0.2213384305747967, -0.6567824407689892, -0.0896076892809434,
+  //               -0.1665148733821233,  0.1988436916560323, 0.0709487030987733,
+  //               -0.6137202819751713,  1.0958800635211576,
+  //               -0.7798663937316326, -0.3650751413581792, 0.5296250728149803,
+  //               0.6171465501654385,  0.8373555508937671, -0.8241029625112244,
+  //               0.4241832213372883,  1.5682117246334322
+  VCMP_U64(6, v1, 0x3fcc54d154555708, 0xbfe5045c9bf61361, 0xbfb6f0878eee8940,
+           0xbfc5505bffbca57e, 0x3fc973b5c856db48, 0x3fb229b1b780ba72,
+           0xbfe3a398b77f3552, 0x3ff188b9889296a1, 0xbfe8f4aa5e0a7552,
+           0xbfd75d64202dd23c, 0x3fe0f2b047dc3902, 0x3fe3bfaa1f3997d0,
+           0x3feacb9dde46cf34, 0xbfea5f0d2d10b7b0, 0x3fdb25d161c9f510,
+           0x3ff917652d6811d0);
+};
+
+// Simple random test with similar values (vector-scalar)
+void TEST_CASE3(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //                             -0.4771
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0xb7a2);
+  //              -0.6172,  0.8584, -0.1088, -0.6719,  0.3579,  0.5889,  0.1724,
+  //              -0.5239, -0.5732, -0.6167,  0.8271, -0.7334,  0.3489, -0.7607,
+  //              -0.7788, -0.5264
+  VLOAD_16(v2, 0xb8f0, 0x3ade, 0xaef7, 0xb960, 0x35ba, 0x38b6, 0x3184, 0xb831,
+           0xb896, 0xb8ef, 0x3a9e, 0xb9de, 0x3595, 0xba16, 0xba3b, 0xb836);
+  //               0.0186,  0.9351,  0.6201,  0.9463,  0.2512,  0.5786,  0.9424,
+  //               -0.5132, -0.7646,  0.0194, -0.2507, -0.2905,  0.3452,
+  //               -0.7803, -0.7666, -0.1387
+  VLOAD_16(v1, 0x24c1, 0x3b7b, 0x38f6, 0x3b92, 0x3405, 0x38a1, 0x3b8a, 0xb81b,
+           0xba1e, 0x24f6, 0xb403, 0xb4a6, 0x3586, 0xba3e, 0xba22, 0xb070);
+  asm volatile("vfnmsac.vf v1, %[A], v2" ::[A] "f"(dscalar_16));
+  //              -0.2759,  1.3447,  0.5684,  0.6260,  0.4219,  0.8594,  1.0244,
+  //              -0.7632, -1.0381, -0.2749,  0.1438, -0.6406,  0.5117, -1.1426,
+  //              -1.1387, -0.3899
+  VCMP_U16(7, v1, 0xb46a, 0x3d61, 0x388c, 0x3902, 0x36c0, 0x3ae0, 0x3c19,
+           0xba1b, 0xbc27, 0xb466, 0x309a, 0xb920, 0x3818, 0xbc93, 0xbc8d,
+           0xb63d);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                              -0.73549986
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0xbf3c49b8);
+  //               0.74252719,  0.73023552,  0.75118375,  0.04020444,
+  //               -0.77184784, -0.41120139, -0.57577437, -0.15976480,
+  //               -0.05041125,  0.42673740,  0.88473374, -0.49891368,
+  //               -0.84324479, -0.26009968, -0.01877740, -0.13754985
+  VLOAD_32(v2, 0x3f3e1643, 0x3f3af0b7, 0x3f404d94, 0x3d24ad6a, 0xbf4597d2,
+           0xbed288fd, 0xbf1365f3, 0xbe239962, 0xbd4e7c07, 0x3eda7d53,
+           0x3f627de9, 0xbeff719d, 0xbf57dee4, 0xbe852bc9, 0xbc99d30f,
+           0xbe0cd9de);
+  //               0.89538908,  0.68592542,  0.67501348,  0.08327232,
+  //               0.28473541, -0.93230879, -0.77235961, -0.92498165,
+  //               -0.55227244,  0.97729182,  0.28253901,  0.45306230,
+  //               -0.50359881,  0.40307203, -0.65891176, -0.59297264
+  VLOAD_32(v1, 0x3f653838, 0x3f2f98cf, 0x3f2ccdaf, 0x3daa8aad, 0x3e91c8d7,
+           0xbf6eabca, 0xbf45b95c, 0xbf6ccb99, 0xbf0d61ba, 0x3f7a2fcc,
+           0x3e90a8f4, 0x3ee7f7c8, 0xbf00ebda, 0x3ece5f75, 0xbf28ae71,
+           0xbf17cd0e);
+  asm volatile("vfnmsac.vf v1, %[A], v2" ::[A] "f"(dscalar_32));
+  //               1.44151771,  1.22301352,  1.22750902,  0.11284268,
+  //               -0.28295860, -1.23474741, -1.19584155, -1.04248869,
+  //               -0.58934993,  1.29115713,  0.93326056,  0.08611137,
+  //               -1.12380528,  0.21176875, -0.67272252, -0.69414055
+  VCMP_U32(8, v1, 0x3fb883a7, 0x3f9c8bb5, 0x3f9d1f04, 0x3de71a10, 0xbe90dff2,
+           0xbf9e0c34, 0xbf991156, 0xbf857045, 0xbf16dfa3, 0x3fa544a3,
+           0x3f6eea2a, 0x3db05b27, 0xbf8fd8da, 0x3e58d9e8, 0xbf2c378b,
+           0xbf31b332);
+
+  VSET(16, e64, m1);
+  double dscalar_64;
+  //                                0.5178244899339752
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0x3fe09204aa2ab2a0);
+  //                0.8646249694399413,  0.0049558737185129, 0.9278624830778543,
+  //                -0.8820434014846885,  0.9252937592855630,
+  //                -0.0640564429957495, -0.9483662154664578,
+  //                0.6036726974274773,  0.6321354499926264, 0.8250130840364809,
+  //                0.1494192541908572,  0.0196333207724690,
+  //                -0.2272946521816408,  0.9289723385226867,
+  //                -0.5162193242581365, -0.3917544955022987
+  VLOAD_64(v2, 0x3febab01fbe195e4, 0x3f744c9c38b4b600, 0x3fedb10ca98026d0,
+           0xbfec39b31560f050, 0x3fed9c01a86a6166, 0xbfb06600c7c3cc10,
+           0xbfee59041b01e946, 0x3fe35149679e0d42, 0x3fe43a741f8b89d2,
+           0x3fea6681d6d6ae5e, 0x3fc3202b8d123b90, 0x3f941ac1da84be40,
+           0xbfcd17fdbcd68200, 0x3fedba24329afe9c, 0xbfe084de63680fb2,
+           0xbfd91281728f9314);
+  //                0.3888129269587612, -0.8225750100551035, 0.8430062678626642,
+  //                -0.6316792665412014, -0.6696614660277347,
+  //                0.6130084754374303, -0.2295750183537659, 0.1572393304616742,
+  //                -0.7542147373874082,  0.6149250820738357,
+  //                0.1236692515687874,  0.9290168852760794,
+  //                -0.0433411597165929, -0.8422695068160440,
+  //                0.6519328829008422, -0.3347506024828231
+  VLOAD_64(v1, 0x3fd8e24f9d6331d4, 0xbfea5288d3d6317c, 0x3feaf9e847d9618e,
+           0xbfe436b76feb621e, 0xbfe56ddde1ff608c, 0x3fe39dc3f345962e,
+           0xbfcd62b6d5e76d58, 0x3fc4206b1afd2970, 0xbfe82286f1e7af48,
+           0x3fe3ad775d9fe964, 0x3fbfa8c9bf023cb0, 0x3fedba819e762954,
+           0xbfa630cfff1b61a0, 0xbfeaf3df2e462cb6, 0x3fe4dca25967e02c,
+           0xbfd56c8dca7eb8ac);
+  asm volatile("vfnmsac.vf v1, %[A], v2" ::[A] "f"(dscalar_64));
+  //               -0.0589110568256553, -0.8251412828355696, 0.3625363508340025,
+  //               -0.1749355920677641, -1.1488012349688719, 0.6461784703586890,
+  //               0.2615122334407671, -0.1553571761707763, -1.0815499543490239,
+  //               0.1877131026437891,  0.0462963024810918,  0.9188502709613655,
+  //               0.0743575776140855, -1.3233141341743264,  0.9192438911788732,
+  //               -0.1318905306700034
+  VCMP_U64(9, v1, 0xbfae29970ce0c2e6, 0xbfea678eb10b76d9, 0x3fd733cbaa9c5dc5,
+           0xbfc6644a1b6b315b, 0xbff2617d675cbb41, 0x3fe4ad7e78b23c6a,
+           0x3fd0bc9dce8872e3, 0xbfc3e2be736d1b43, 0xbff14e07532eb5a9,
+           0x3fc806fba27160c3, 0x3fa7b4262229fd93, 0x3fed6738aef664ca,
+           0x3fb30919240ff186, 0xbff52c4b7109d007, 0x3fed6a722a352743,
+           0xbfc0e1c9f5f09ba4);
+};
+
+// Simple random test with similar values (vector-scalar) (masked)
+void TEST_CASE4(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //                             -0.4771
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0xb7a2);
+  //               -0.6172,  0.8584, -0.1088, -0.6719,  0.3579,  0.5889, 0.1724,
+  //               -0.5239, -0.5732, -0.6167,  0.8271, -0.7334,  0.3489,
+  //               -0.7607, -0.7788, -0.5264
+  VLOAD_16(v2, 0xb8f0, 0x3ade, 0xaef7, 0xb960, 0x35ba, 0x38b6, 0x3184, 0xb831,
+           0xb896, 0xb8ef, 0x3a9e, 0xb9de, 0x3595, 0xba16, 0xba3b, 0xb836);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //                0.0186,  0.9351,  0.6201,  0.9463,  0.2512,  0.5786, 0.9424,
+  //                -0.5132, -0.7646,  0.0194, -0.2507, -0.2905,  0.3452,
+  //                -0.7803, -0.7666, -0.1387
+  VLOAD_16(v1, 0x24c1, 0x3b7b, 0x38f6, 0x3b92, 0x3405, 0x38a1, 0x3b8a, 0xb81b,
+           0xba1e, 0x24f6, 0xb403, 0xb4a6, 0x3586, 0xba3e, 0xba22, 0xb070);
+  asm volatile("vfnmsac.vf v1, %[A], v2, v0.t" ::[A] "f"(dscalar_16));
+  //                0.0186,  1.3447,  0.6201,  0.6260,  0.2512,  0.8594, 0.9424,
+  //                -0.7632, -0.7646, -0.2749, -0.2507, -0.6406,  0.3452,
+  //                -1.1426, -0.7666, -0.3899
+  VCMP_U16(10, v1, 0x24c1, 0x3d61, 0x38f6, 0x3902, 0x3405, 0x3ae0, 0x3b8a,
+           0xba1b, 0xba1e, 0xb466, 0xb403, 0xb920, 0x3586, 0xbc93, 0xba22,
+           0xb63d);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                              -0.73549986
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0xbf3c49b8);
+  //                0.74252719,  0.73023552,  0.75118375,  0.04020444,
+  //                -0.77184784, -0.41120139, -0.57577437, -0.15976480,
+  //                -0.05041125,  0.42673740,  0.88473374, -0.49891368,
+  //                -0.84324479, -0.26009968, -0.01877740, -0.13754985
+  VLOAD_32(v2, 0x3f3e1643, 0x3f3af0b7, 0x3f404d94, 0x3d24ad6a, 0xbf4597d2,
+           0xbed288fd, 0xbf1365f3, 0xbe239962, 0xbd4e7c07, 0x3eda7d53,
+           0x3f627de9, 0xbeff719d, 0xbf57dee4, 0xbe852bc9, 0xbc99d30f,
+           0xbe0cd9de);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //                0.89538908,  0.68592542,  0.67501348,  0.08327232,
+  //                0.28473541, -0.93230879, -0.77235961, -0.92498165,
+  //                -0.55227244,  0.97729182,  0.28253901,  0.45306230,
+  //                -0.50359881,  0.40307203, -0.65891176, -0.59297264
+  VLOAD_32(v1, 0x3f653838, 0x3f2f98cf, 0x3f2ccdaf, 0x3daa8aad, 0x3e91c8d7,
+           0xbf6eabca, 0xbf45b95c, 0xbf6ccb99, 0xbf0d61ba, 0x3f7a2fcc,
+           0x3e90a8f4, 0x3ee7f7c8, 0xbf00ebda, 0x3ece5f75, 0xbf28ae71,
+           0xbf17cd0e);
+  asm volatile("vfnmsac.vf v1, %[A], v2, v0.t" ::[A] "f"(dscalar_32));
+  //                0.89538908,  1.22301352,  0.67501348,  0.11284268,
+  //                0.28473541, -1.23474741, -0.77235961, -1.04248869,
+  //                -0.55227244,  1.29115713,  0.28253901,  0.08611137,
+  //                -0.50359881,  0.21176875, -0.65891176, -0.69414055
+  VCMP_U32(11, v1, 0x3f653838, 0x3f9c8bb5, 0x3f2ccdaf, 0x3de71a10, 0x3e91c8d7,
+           0xbf9e0c34, 0xbf45b95c, 0xbf857045, 0xbf0d61ba, 0x3fa544a3,
+           0x3e90a8f4, 0x3db05b27, 0xbf00ebda, 0x3e58d9e8, 0xbf28ae71,
+           0xbf31b332);
+
+  VSET(16, e64, m1);
+  double dscalar_64;
+  //                                0.5178244899339752
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0x3fe09204aa2ab2a0);
+  //                 0.8646249694399413,  0.0049558737185129,
+  //                 0.9278624830778543, -0.8820434014846885,
+  //                 0.9252937592855630, -0.0640564429957495,
+  //                 -0.9483662154664578,  0.6036726974274773,
+  //                 0.6321354499926264,  0.8250130840364809,
+  //                 0.1494192541908572,  0.0196333207724690,
+  //                 -0.2272946521816408,  0.9289723385226867,
+  //                 -0.5162193242581365, -0.3917544955022987
+  VLOAD_64(v2, 0x3febab01fbe195e4, 0x3f744c9c38b4b600, 0x3fedb10ca98026d0,
+           0xbfec39b31560f050, 0x3fed9c01a86a6166, 0xbfb06600c7c3cc10,
+           0xbfee59041b01e946, 0x3fe35149679e0d42, 0x3fe43a741f8b89d2,
+           0x3fea6681d6d6ae5e, 0x3fc3202b8d123b90, 0x3f941ac1da84be40,
+           0xbfcd17fdbcd68200, 0x3fedba24329afe9c, 0xbfe084de63680fb2,
+           0xbfd91281728f9314);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //                 0.3888129269587612, -0.8225750100551035,
+  //                 0.8430062678626642, -0.6316792665412014,
+  //                 -0.6696614660277347,  0.6130084754374303,
+  //                 -0.2295750183537659,  0.1572393304616742,
+  //                 -0.7542147373874082,  0.6149250820738357,
+  //                 0.1236692515687874,  0.9290168852760794,
+  //                 -0.0433411597165929, -0.8422695068160440,
+  //                 0.6519328829008422, -0.3347506024828231
+  VLOAD_64(v1, 0x3fd8e24f9d6331d4, 0xbfea5288d3d6317c, 0x3feaf9e847d9618e,
+           0xbfe436b76feb621e, 0xbfe56ddde1ff608c, 0x3fe39dc3f345962e,
+           0xbfcd62b6d5e76d58, 0x3fc4206b1afd2970, 0xbfe82286f1e7af48,
+           0x3fe3ad775d9fe964, 0x3fbfa8c9bf023cb0, 0x3fedba819e762954,
+           0xbfa630cfff1b61a0, 0xbfeaf3df2e462cb6, 0x3fe4dca25967e02c,
+           0xbfd56c8dca7eb8ac);
+  asm volatile("vfnmsac.vf v1, %[A], v2, v0.t" ::[A] "f"(dscalar_64));
+  //                0.3888129269587612, -0.8251412828355696, 0.8430062678626642,
+  //                -0.1749355920677641, -0.6696614660277347,
+  //                0.6461784703586890, -0.2295750183537659,
+  //                -0.1553571761707763, -0.7542147373874082,
+  //                0.1877131026437891,  0.1236692515687874, 0.9188502709613655,
+  //                -0.0433411597165929, -1.3233141341743264,
+  //                0.6519328829008422, -0.1318905306700034
+  VCMP_U64(12, v1, 0x3fd8e24f9d6331d4, 0xbfea678eb10b76d9, 0x3feaf9e847d9618e,
+           0xbfc6644a1b6b315b, 0xbfe56ddde1ff608c, 0x3fe4ad7e78b23c6a,
+           0xbfcd62b6d5e76d58, 0xbfc3e2be736d1b43, 0xbfe82286f1e7af48,
+           0x3fc806fba27160c3, 0x3fbfa8c9bf023cb0, 0x3fed6738aef664ca,
+           0xbfa630cfff1b61a0, 0xbff52c4b7109d007, 0x3fe4dca25967e02c,
+           0xbfc0e1c9f5f09ba4);
+};
+
+int main(void) {
+  enable_vec();
+  enable_fp();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vfnmsub.c b/apps/riscv-tests/isa/rv64uv/vfnmsub.c
new file mode 100644
index 0000000..efb561c
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vfnmsub.c
@@ -0,0 +1,454 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+// Simple random test with similar values
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  //              -0.0091, -0.3794, -0.0005, -0.0464,  0.4834,  0.2932, -0.3042,
+  //              -0.3096, -0.9844, -0.1815, -0.8760,  0.0853, -0.3723, -0.8877,
+  //              0.1584,  0.1943
+  VLOAD_16(v2, 0xa0ac, 0xb612, 0x8f83, 0xa9f0, 0x37bc, 0x34b1, 0xb4de, 0xb4f4,
+           0xbbe0, 0xb1cf, 0xbb02, 0x2d75, 0xb5f5, 0xbb1a, 0x3112, 0x3238);
+  //              -0.3301,  0.7769,  0.6572, -0.8193,  0.4529,  0.2349,  0.5264,
+  //              -0.2456,  0.0873,  0.5381,  0.4670,  0.8564, -0.1790,  0.6641,
+  //              0.0182,  0.0447
+  VLOAD_16(v3, 0xb548, 0x3a37, 0x3942, 0xba8e, 0x373f, 0x3384, 0x3836, 0xb3dc,
+           0x2d97, 0x384e, 0x3779, 0x3ada, 0xb1ba, 0x3950, 0x24a7, 0x29b9);
+  //               0.5835,  0.4404, -0.3459,  0.0516, -0.4866, -0.2191,  0.0685,
+  //               -0.5430, -0.1429, -0.7539, -0.6416, -0.6758, -0.1147, 0.3438,
+  //               0.3440,  0.1991
+  VLOAD_16(v1, 0x38ab, 0x370c, 0xb589, 0x2a9b, 0xb7c9, 0xb303, 0x2c62, 0xb858,
+           0xb093, 0xba08, 0xb922, 0xb968, 0xaf57, 0x3580, 0x3581, 0x325f);
+  asm volatile("vfnmsub.vv v1, v2, v3");
+  //              -0.3247,  0.9438,  0.6572, -0.8169,  0.6880,  0.2991,  0.5474,
+  //              -0.4136, -0.0534,  0.4014, -0.0950,  0.9141, -0.2217,  0.9692,
+  //              -0.0363,  0.0060
+  VCMP_U16(1, v1, 0xb532, 0x3b8d, 0x3942, 0xba89, 0x3981, 0x34c9, 0x3861,
+           0xb69e, 0xaad5, 0x366b, 0xae14, 0x3b50, 0xb318, 0x3bc1, 0xa8a7,
+           0x1e29);
+
+  VSET(16, e32, m1);
+  //               0.76259303, -0.43966120, -0.19390504, -0.57240725,
+  //               -0.57148474, -0.93710214,  0.24273214,  0.44242114,
+  //               -0.93160200, -0.56412256, -0.75430351, -0.02741535,
+  //               -0.60542876, -0.93627954,  0.02798123,  0.23119579
+  VLOAD_32(v2, 0x3f43394c, 0xbee11b46, 0xbe468f0b, 0xbf128948, 0xbf124cd3,
+           0xbf6fe5ed, 0x3e788ec6, 0x3ee28506, 0xbf6e7d78, 0xbf106a56,
+           0xbf411a09, 0xbce09629, 0xbf1afd61, 0xbf6fb004, 0x3ce538e6,
+           0x3e6cbe97);
+  //               0.48736989,  0.19715627, -0.47227743,  0.13752034,
+  //               -0.16710435,  0.84761631,  0.37147006,  0.25389814,
+  //               -0.44707820,  0.38169226, -0.82191414, -0.81056035,
+  //               0.29047397, -0.46743703, -0.91869444, -0.08079135
+  VLOAD_32(v3, 0x3ef9888c, 0x3e49e355, 0xbef1ce59, 0x3e0cd222, 0xbe2b1d67,
+           0x3f58fd62, 0x3ebe3153, 0x3e81fef0, 0xbee4e76f, 0x3ec36d2b,
+           0xbf5268f7, 0xbf4f80e2, 0x3e94b901, 0xbeef53e8, 0xbf6b2f8f,
+           0xbda575f0);
+  //              -0.48655373, -0.87417608,  0.17854533,  0.67417324,
+  //              0.46947387,  0.29113689, -0.11920074,  0.63394654,
+  //              -0.82611400, -0.84088647, -0.13328743,  0.29885510,
+  //              0.91797447, -0.15480036,  0.76857966,  0.16230854
+  VLOAD_32(v1, 0xbef91d92, 0xbf5fca01, 0x3e36d496, 0x3f2c969e, 0x3ef05ee1,
+           0x3e950fe5, 0xbdf41f84, 0x3f224a52, 0xbf537c35, 0xbf574456,
+           0xbe087c80, 0x3e990389, 0x3f6b0060, 0xbe1e83fc, 0x3f44c1a3,
+           0x3e263436);
+  asm volatile("vfnmsub.vv v1, v2, v3");
+  //               0.85841238, -0.18718503, -0.43765658,  0.52342200,
+  //               0.10119282,  1.12044132,  0.40040392, -0.02657321,
+  //               -1.21668768, -0.09267077, -0.92245328, -0.80236715,
+  //               0.84624207, -0.61237341, -0.94020027, -0.11831641
+  VCMP_U32(2, v1, 0x3f5bc0ea, 0xbe3fad70, 0xbee01486, 0x3f05fefc, 0x3dcf3e2c,
+           0x3f8f6a9f, 0x3ecd01be, 0xbcd9b00d, 0xbf9bbc6c, 0xbdbdca2c,
+           0xbf6c25e6, 0xbf4d67ef, 0x3f58a353, 0xbf1cc481, 0xbf70b0f7,
+           0xbdf24fdf);
+
+  VSET(16, e64, m1);
+  //              -0.1307639483617093,  0.9224167823566942,  0.8635785104096312,
+  //              -0.1786758246437388,  0.0810514505300033,  0.4196384170211611,
+  //              0.9100790646565715, -0.5457616411379209, -0.5513001815564993,
+  //              -0.4320693373833464,  0.2818536966914695,  0.5493933224246561,
+  //              0.0505621823765807,  0.7247332126666939, -0.8702311369694951,
+  //              -0.0660417836134264
+  VLOAD_64(v2, 0xbfc0bcdf80daccc8, 0x3fed847033301d18, 0x3feba26f66779bbe,
+           0xbfc6ded973b720d0, 0x3fb4bfc9b151d990, 0x3fdadb5b175011f8,
+           0x3fed1f5e216f2d02, 0xbfe176e11e032836, 0xbfe1a44047420c82,
+           0xbfdba706266a9d80, 0x3fd209e41662faec, 0x3fe194a14e0e8cc0,
+           0x3fa9e3494f719000, 0x3fe73103b4d74f92, 0xbfebd8eef827d60a,
+           0xbfb0e81d44ca0760);
+  //               0.6650460871127466, -0.8389896062690501,  0.3260860096573337,
+  //               0.4421797679090849, -0.1921872051427089, -0.1798768047606598,
+  //               -0.5065656464186716,  0.8248933299429206,
+  //               -0.3169052211432897, -0.0970247500649024, 0.8584276150948376,
+  //               -0.2642287948226270,  0.2403355182026823,
+  //               -0.0814065713760876, -0.7437013715700231, -0.6226210619792329
+  VLOAD_64(v3, 0x3fe5480ebb4f6ca8, 0xbfead900bb1380ea, 0x3fd4de97daca5430,
+           0x3fdc4cac5e87d53c, 0xbfc8999720661708, 0xbfc7063400e0c4f8,
+           0xbfe035c92894a640, 0x3fea6586b2596362, 0xbfd4482cd62f7e30,
+           0xbfb8d69d306e6ba0, 0x3feb783d309a196c, 0xbfd0e91fe41b2de8,
+           0x3fcec350735fb5b8, 0xbfb4d70fa1bd62a0, 0xbfe7cc66d19c4666,
+           0xbfe3ec8301600d10);
+  //              -0.2122847293404504,  0.9074328134093839, -0.4150374170703475,
+  //              -0.4511563805942409, -0.9126942371441604, -0.8237861842027401,
+  //              -0.0636244117792013,  0.7124530373845765, -0.4126670585839094,
+  //              -0.2810978842877421, -0.3240264495739638,  0.5540367578795606,
+  //              0.7398533272929233,  0.4690189457399407, -0.2427822500985419,
+  //              0.2399358773396087
+  VLOAD_64(v1, 0xbfcb2c2560fa8d98, 0x3fed09b08a1d236c, 0xbfda8ff9193bbdb8,
+           0xbfdcdfbf03022cf4, 0xbfed34ca8b7904d0, 0xbfea5c74d801844e,
+           0xbfb049b07fd1a3e0, 0x3fe6cc6a4ff0157a, 0xbfda692318304834,
+           0xbfd1fd81faff66b8, 0xbfd4bcd96efd6300, 0x3fe1baab4b7bfc96,
+           0x3fe7ace0e291ea9e, 0x3fde04680a4a1390, 0xbfcf137d201c7be0,
+           0x3fceb6380527c498);
+  asm volatile("vfnmsub.vv v1, v2, v3");
+  //               0.6372868977272925, -1.6760208622190165,  0.6845034040552052,
+  //               0.3615690295631244, -0.1182120133317999,  0.1658155255420807,
+  //               -0.4486624012573315,  1.2137228688596235,
+  //               -0.5444086454629855, -0.2184785266689677, 0.9497556677330713,
+  //               -0.5686128899794636,  0.2029269193361774,
+  //               -0.4213201787237407, -0.9549780451092895, -0.6067752686868729
+  VCMP_U64(3, v1, 0x3fe464a77dfd0e7c, 0xbffad0fb406a4f74, 0x3fe5e773aecd5e74,
+           0x3fd723f26d4e15bc, 0xbfbe43247b412024, 0x3fc5397171afa72c,
+           0xbfdcb6e281161599, 0x3ff36b68abc28cd2, 0xbfe16bcbadfd8ab4,
+           0xbfcbf71ab775f310, 0x3fee6465ff835579, 0xbfe23213a8d1778a,
+           0x3fc9f982610371db, 0xbfdaf6e8e930da95, 0xbfee8f2e1e048ea3,
+           0xbfe36ab3f7e103f3);
+};
+
+// Simple random test with similar values (masked)
+// The numbers are the same of TEST_CASE1
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  //              -0.0091, -0.3794, -0.0005, -0.0464,  0.4834,  0.2932, -0.3042,
+  //              -0.3096, -0.9844, -0.1815, -0.8760,  0.0853, -0.3723, -0.8877,
+  //              0.1584,  0.1943
+  VLOAD_16(v2, 0xa0ac, 0xb612, 0x8f83, 0xa9f0, 0x37bc, 0x34b1, 0xb4de, 0xb4f4,
+           0xbbe0, 0xb1cf, 0xbb02, 0x2d75, 0xb5f5, 0xbb1a, 0x3112, 0x3238);
+  //              -0.3301,  0.7769,  0.6572, -0.8193,  0.4529,  0.2349,  0.5264,
+  //              -0.2456,  0.0873,  0.5381,  0.4670,  0.8564, -0.1790,  0.6641,
+  //              0.0182,  0.0447
+  VLOAD_16(v3, 0xb548, 0x3a37, 0x3942, 0xba8e, 0x373f, 0x3384, 0x3836, 0xb3dc,
+           0x2d97, 0x384e, 0x3779, 0x3ada, 0xb1ba, 0x3950, 0x24a7, 0x29b9);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //               0.5835,  0.4404, -0.3459,  0.0516, -0.4866, -0.2191,  0.0685,
+  //               -0.5430, -0.1429, -0.7539, -0.6416, -0.6758, -0.1147, 0.3438,
+  //               0.3440,  0.1991
+  VLOAD_16(v1, 0x38ab, 0x370c, 0xb589, 0x2a9b, 0xb7c9, 0xb303, 0x2c62, 0xb858,
+           0xb093, 0xba08, 0xb922, 0xb968, 0xaf57, 0x3580, 0x3581, 0x325f);
+  asm volatile("vfnmsub.vv v1, v2, v3, v0.t");
+  //               0.5835,  0.9438, -0.3459, -0.8169, -0.4866,  0.2991,  0.0685,
+  //               -0.4136, -0.1429,  0.4014, -0.6416,  0.9141, -0.1147, 0.9692,
+  //               0.3440,  0.0060
+  VCMP_U16(4, v1, 0x38ab, 0x3b8d, 0xb589, 0xba89, 0xb7c9, 0x34c9, 0x2c62,
+           0xb69e, 0xb093, 0x366b, 0xb922, 0x3b50, 0xaf57, 0x3bc1, 0x3581,
+           0x1e29);
+
+  VSET(16, e32, m1);
+  //               0.76259303, -0.43966120, -0.19390504, -0.57240725,
+  //               -0.57148474, -0.93710214,  0.24273214,  0.44242114,
+  //               -0.93160200, -0.56412256, -0.75430351, -0.02741535,
+  //               -0.60542876, -0.93627954,  0.02798123,  0.23119579
+  VLOAD_32(v2, 0x3f43394c, 0xbee11b46, 0xbe468f0b, 0xbf128948, 0xbf124cd3,
+           0xbf6fe5ed, 0x3e788ec6, 0x3ee28506, 0xbf6e7d78, 0xbf106a56,
+           0xbf411a09, 0xbce09629, 0xbf1afd61, 0xbf6fb004, 0x3ce538e6,
+           0x3e6cbe97);
+  //               0.48736989,  0.19715627, -0.47227743,  0.13752034,
+  //               -0.16710435,  0.84761631,  0.37147006,  0.25389814,
+  //               -0.44707820,  0.38169226, -0.82191414, -0.81056035,
+  //               0.29047397, -0.46743703, -0.91869444, -0.08079135
+  VLOAD_32(v3, 0x3ef9888c, 0x3e49e355, 0xbef1ce59, 0x3e0cd222, 0xbe2b1d67,
+           0x3f58fd62, 0x3ebe3153, 0x3e81fef0, 0xbee4e76f, 0x3ec36d2b,
+           0xbf5268f7, 0xbf4f80e2, 0x3e94b901, 0xbeef53e8, 0xbf6b2f8f,
+           0xbda575f0);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //              -0.48655373, -0.87417608,  0.17854533,  0.67417324,
+  //              0.46947387,  0.29113689, -0.11920074,  0.63394654,
+  //              -0.82611400, -0.84088647, -0.13328743,  0.29885510,
+  //              0.91797447, -0.15480036,  0.76857966,  0.16230854
+  VLOAD_32(v1, 0xbef91d92, 0xbf5fca01, 0x3e36d496, 0x3f2c969e, 0x3ef05ee1,
+           0x3e950fe5, 0xbdf41f84, 0x3f224a52, 0xbf537c35, 0xbf574456,
+           0xbe087c80, 0x3e990389, 0x3f6b0060, 0xbe1e83fc, 0x3f44c1a3,
+           0x3e263436);
+  asm volatile("vfnmsub.vv v1, v2, v3, v0.t");
+  //              -0.48655373, -0.18718503,  0.17854533,  0.52342200,
+  //              0.46947387,  1.12044132, -0.11920074, -0.02657321,
+  //              -0.82611400, -0.09267077, -0.13328743, -0.80236715,
+  //              0.91797447, -0.61237341,  0.76857966, -0.11831641
+  VCMP_U32(5, v1, 0xbef91d92, 0xbe3fad70, 0x3e36d496, 0x3f05fefc, 0x3ef05ee1,
+           0x3f8f6a9f, 0xbdf41f84, 0xbcd9b00d, 0xbf537c35, 0xbdbdca2c,
+           0xbe087c80, 0xbf4d67ef, 0x3f6b0060, 0xbf1cc481, 0x3f44c1a3,
+           0xbdf24fdf);
+
+  VSET(16, e64, m1);
+  //              -0.1307639483617093,  0.9224167823566942,  0.8635785104096312,
+  //              -0.1786758246437388,  0.0810514505300033,  0.4196384170211611,
+  //              0.9100790646565715, -0.5457616411379209, -0.5513001815564993,
+  //              -0.4320693373833464,  0.2818536966914695,  0.5493933224246561,
+  //              0.0505621823765807,  0.7247332126666939, -0.8702311369694951,
+  //              -0.0660417836134264
+  VLOAD_64(v2, 0xbfc0bcdf80daccc8, 0x3fed847033301d18, 0x3feba26f66779bbe,
+           0xbfc6ded973b720d0, 0x3fb4bfc9b151d990, 0x3fdadb5b175011f8,
+           0x3fed1f5e216f2d02, 0xbfe176e11e032836, 0xbfe1a44047420c82,
+           0xbfdba706266a9d80, 0x3fd209e41662faec, 0x3fe194a14e0e8cc0,
+           0x3fa9e3494f719000, 0x3fe73103b4d74f92, 0xbfebd8eef827d60a,
+           0xbfb0e81d44ca0760);
+  //               0.6650460871127466, -0.8389896062690501,  0.3260860096573337,
+  //               0.4421797679090849, -0.1921872051427089, -0.1798768047606598,
+  //               -0.5065656464186716,  0.8248933299429206,
+  //               -0.3169052211432897, -0.0970247500649024, 0.8584276150948376,
+  //               -0.2642287948226270,  0.2403355182026823,
+  //               -0.0814065713760876, -0.7437013715700231, -0.6226210619792329
+  VLOAD_64(v3, 0x3fe5480ebb4f6ca8, 0xbfead900bb1380ea, 0x3fd4de97daca5430,
+           0x3fdc4cac5e87d53c, 0xbfc8999720661708, 0xbfc7063400e0c4f8,
+           0xbfe035c92894a640, 0x3fea6586b2596362, 0xbfd4482cd62f7e30,
+           0xbfb8d69d306e6ba0, 0x3feb783d309a196c, 0xbfd0e91fe41b2de8,
+           0x3fcec350735fb5b8, 0xbfb4d70fa1bd62a0, 0xbfe7cc66d19c4666,
+           0xbfe3ec8301600d10);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //              -0.2122847293404504,  0.9074328134093839, -0.4150374170703475,
+  //              -0.4511563805942409, -0.9126942371441604, -0.8237861842027401,
+  //              -0.0636244117792013,  0.7124530373845765, -0.4126670585839094,
+  //              -0.2810978842877421, -0.3240264495739638,  0.5540367578795606,
+  //              0.7398533272929233,  0.4690189457399407, -0.2427822500985419,
+  //              0.2399358773396087
+  VLOAD_64(v1, 0xbfcb2c2560fa8d98, 0x3fed09b08a1d236c, 0xbfda8ff9193bbdb8,
+           0xbfdcdfbf03022cf4, 0xbfed34ca8b7904d0, 0xbfea5c74d801844e,
+           0xbfb049b07fd1a3e0, 0x3fe6cc6a4ff0157a, 0xbfda692318304834,
+           0xbfd1fd81faff66b8, 0xbfd4bcd96efd6300, 0x3fe1baab4b7bfc96,
+           0x3fe7ace0e291ea9e, 0x3fde04680a4a1390, 0xbfcf137d201c7be0,
+           0x3fceb6380527c498);
+  asm volatile("vfnmsub.vv v1, v2, v3, v0.t");
+  //              -0.2122847293404504, -1.6760208622190165, -0.4150374170703475,
+  //              0.3615690295631244, -0.9126942371441604,  0.1658155255420807,
+  //              -0.0636244117792013,  1.2137228688596235, -0.4126670585839094,
+  //              -0.2184785266689677, -0.3240264495739638, -0.5686128899794636,
+  //              0.7398533272929233, -0.4213201787237407, -0.2427822500985419,
+  //              -0.6067752686868729
+  VCMP_U64(6, v1, 0xbfcb2c2560fa8d98, 0xbffad0fb406a4f74, 0xbfda8ff9193bbdb8,
+           0x3fd723f26d4e15bc, 0xbfed34ca8b7904d0, 0x3fc5397171afa72c,
+           0xbfb049b07fd1a3e0, 0x3ff36b68abc28cd2, 0xbfda692318304834,
+           0xbfcbf71ab775f310, 0xbfd4bcd96efd6300, 0xbfe23213a8d1778a,
+           0x3fe7ace0e291ea9e, 0xbfdaf6e8e930da95, 0xbfcf137d201c7be0,
+           0xbfe36ab3f7e103f3);
+};
+
+// Simple random test with similar values (vector-scalar)
+void TEST_CASE3(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //                             -0.1346
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0xb04f);
+  //              -0.1886,  0.9912, -0.0325,  0.5850,  0.2578, -0.2350, -0.8701,
+  //              0.9209,  0.5859, -0.4795,  0.8682,  0.9233, -0.8896, -0.5981,
+  //              -0.3223,  0.6924
+  VLOAD_16(v2, 0xb209, 0x3bee, 0xa82a, 0x38ae, 0x3420, 0xb385, 0xbaf6, 0x3b5e,
+           0x38b0, 0xb7ac, 0x3af2, 0x3b63, 0xbb1e, 0xb8c9, 0xb528, 0x398a);
+  //              -0.0126,  0.9678,  0.8945, -0.9600, -0.9272,  0.4412,  0.5527,
+  //              0.1136,  0.7207, -0.5181, -0.2810, -0.4048,  0.1648,  0.7612,
+  //              -0.8853,  0.1761
+  VLOAD_16(v1, 0xa27a, 0x3bbe, 0x3b28, 0xbbae, 0xbb6b, 0x370f, 0x386c, 0x2f45,
+           0x39c4, 0xb825, 0xb47f, 0xb67a, 0x3146, 0x3a17, 0xbb15, 0x31a3);
+  asm volatile("vfnmsub.vf v1, %[A], v2" ::[A] "f"(dscalar_16));
+  //              -0.1903,  1.1211,  0.0879,  0.4556,  0.1329, -0.1755, -0.7959,
+  //              0.9360,  0.6831, -0.5493,  0.8301,  0.8687, -0.8677, -0.4956,
+  //              -0.4414,  0.7163
+  VCMP_U16(7, v1, 0xb217, 0x3c7c, 0x2da0, 0x374b, 0x3041, 0xb19e, 0xba5e,
+           0x3b7d, 0x3977, 0xb865, 0x3aa5, 0x3af3, 0xbaf1, 0xb7ee, 0xb710,
+           0x39bb);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                              -0.16110219
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0xbe24f7f9);
+  //              -0.31537205, -0.17563045, -0.79069936,  0.22939304,
+  //              -0.89379781,  0.26157290,  0.56702632, -0.11594663,
+  //              0.09605245,  0.45930776, -0.76518077, -0.26341528, 0.74385208,
+  //              0.89362013, -0.21185355,  0.23924881
+  VLOAD_32(v2, 0xbea17872, 0xbe33d878, 0xbf4a6b46, 0x3e6ae602, 0xbf64cfef,
+           0x3e85ece2, 0x3f1128a3, 0xbded756d, 0x3dc4b726, 0x3eeb2a63,
+           0xbf43e2e3, 0xbe86de5e, 0x3f3e6d17, 0x3f64c44a, 0xbe58f023,
+           0x3e74fda4);
+  //               0.31856158,  0.48641542,  0.57264513,  0.30210373,
+  //               -0.19719712,  0.85649359,  0.36901370, -0.78377151,
+  //               0.22567192, -0.75179213, -0.65690833,  0.11298654,
+  //               -0.64884853, -0.48376039, -0.11539485, -0.42667609
+  VLOAD_32(v1, 0x3ea31a81, 0x3ef90b71, 0x3f1298df, 0x3e9aad57, 0xbe49ee0b,
+           0x3f5b432a, 0x3ebcef5d, 0xbf48a540, 0x3e67168a, 0xbf407573,
+           0xbf282b25, 0x3de7657d, 0xbf261af0, 0xbef7af71, 0xbdec5422,
+           0xbeda754a);
+  asm volatile("vfnmsub.vf v1, %[A], v2" ::[A] "f"(dscalar_32));
+  //              -0.26405108, -0.09726786, -0.69844496,  0.27806261,
+  //              -0.92556667,  0.39955589,  0.62647521, -0.24221393,
+  //              0.13240869,  0.33819240, -0.87101012, -0.24521290, 0.63932115,
+  //              0.81568527, -0.23044391,  0.17051035
+  VCMP_U32(8, v1, 0xbe8731b4, 0xbdc7345f, 0xbf32cd4a, 0x3e8e5e39, 0xbf6cf1f1,
+           0x3ecc9297, 0x3f2060ae, 0xbe7806ee, 0x3e079625, 0x3ead278e,
+           0xbf5efa85, 0xbe7b1917, 0x3f23aa8d, 0x3f50d0c0, 0xbe6bf97d,
+           0x3e2e9a44);
+
+  VSET(16, e64, m1);
+  double dscalar_64;
+  //                                0.5849101968457469
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0x3fe2b79596d194ba);
+  //               -0.7607808895269514, -0.0192591699518767, 0.6815284686654297,
+  //               -0.5163928614577513, -0.9560613023939111,
+  //               -0.8652684824342871,  0.4588682754059621,
+  //               -0.5708244737077264, -0.7636024500128011, 0.2236424444447431,
+  //               0.8245435877598175,  0.8527344486412596, -0.3097355632002228,
+  //               0.0764086736442742,  0.2567358761671383,  0.1904958118727702
+  VLOAD_64(v2, 0xbfe8585129fe14da, 0xbf93b8ad045d9c40, 0x3fe5cf14ca86c05c,
+           0xbfe0864a527b2a32, 0xbfee980ddf5818b2, 0xbfebb047874a12f4,
+           0x3fdd5e190b029804, 0xbfe24431afca9858, 0xbfe86f6e67be6a22,
+           0x3fcca050cc719f20, 0x3fea62a93bf1c1ec, 0x3feb4999c122c714,
+           0xbfd3d2b51c969928, 0x3fb38f84d26ed230, 0x3fd06e5c4ff641c8,
+           0x3fc8622ab1025ec0);
+  //                0.1182575129292827, -0.8756460666506833,
+  //                -0.3686593299789440,  0.2802900907620893,
+  //                -0.5167592439660142,  0.3872686605057347,
+  //                -0.0640775227939985, -0.4352087179743556,
+  //                -0.1509314378482451, -0.9803534868251271,
+  //                0.9211862470421908,  0.7804942879773937, 0.5029472314120484,
+  //                0.1158347026033590,  0.7422982722940397,  0.0792254120441500
+  VLOAD_64(v1, 0x3fbe461fd6899df0, 0xbfec054ae66457d4, 0xbfd7981d4d67fd54,
+           0x3fd1f045d94dd3b0, 0xbfe0894aae97abc2, 0x3fd8c9027de8d2a8,
+           0xbfb0676270cf1540, 0xbfdbda75aaa8928c, 0xbfc351b8aabf8c50,
+           0xbfef5f0e468ddf22, 0x3fed7a5b94924728, 0x3fe8f9cf28327c9e,
+           0x3fe01824cad0e968, 0x3fbda757d36c5e40, 0x3fe7c0e84e6c2aa0,
+           0x3fb4481dd9bde340);
+  asm volatile("vfnmsub.vf v1, %[A], v2" ::[A] "f"(dscalar_64));
+  //              -0.8299509146929066,  0.4929151432599784,  0.8971610699324351,
+  //              -0.6803373936193172, -0.6538035512838903, -1.0917858708828851,
+  //              0.4963478718767876, -0.3162664568083610, -0.6753211129907725,
+  //              0.7970611954020426,  0.2857323586707750,  0.3962153810234212,
+  //              -0.6039145273284674,  0.0086557749429749, -0.1774419523986262,
+  //              0.1441560605188410
+  VCMP_U64(9, v1, 0xbfea8ef5387c85b1, 0x3fdf8bebf5004e06, 0x3fecb58b21d3556c,
+           0xbfe5c552ecfae837, 0xbfe4ebf56cd8bc27, 0xbff177f4761ad476,
+           0x3fdfc429dd49999d, 0xbfd43db5aa3413c6, 0xbfe59c3b05d2ff7f,
+           0x3fe981867ae532b2, 0x3fd249705ff9984b, 0x3fd95b97c1eabccb,
+           0xbfe353448f0e8fe6, 0x3f81ba1e7269b44b, 0xbfc6b66afb3ec852,
+           0x3fc273b4aeb96c59);
+};
+
+// Simple random test with similar values (vector-scalar) (masked)
+void TEST_CASE4(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //                             -0.1346
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0xb04f);
+  //               -0.1886,  0.9912, -0.0325,  0.5850,  0.2578, -0.2350,
+  //               -0.8701,  0.9209,  0.5859, -0.4795,  0.8682,  0.9233,
+  //               -0.8896, -0.5981, -0.3223,  0.6924
+  VLOAD_16(v2, 0xb209, 0x3bee, 0xa82a, 0x38ae, 0x3420, 0xb385, 0xbaf6, 0x3b5e,
+           0x38b0, 0xb7ac, 0x3af2, 0x3b63, 0xbb1e, 0xb8c9, 0xb528, 0x398a);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //               -0.0126,  0.9678,  0.8945, -0.9600, -0.9272,  0.4412, 0.5527,
+  //               0.1136,  0.7207, -0.5181, -0.2810, -0.4048,  0.1648,  0.7612,
+  //               -0.8853,  0.1761
+  VLOAD_16(v1, 0xa27a, 0x3bbe, 0x3b28, 0xbbae, 0xbb6b, 0x370f, 0x386c, 0x2f45,
+           0x39c4, 0xb825, 0xb47f, 0xb67a, 0x3146, 0x3a17, 0xbb15, 0x31a3);
+  asm volatile("vfnmsub.vf v1, %[A], v2, v0.t" ::[A] "f"(dscalar_16));
+  //               -0.0126,  1.1211,  0.8945,  0.4556, -0.9272, -0.1755, 0.5527,
+  //               0.9360,  0.7207, -0.5493, -0.2810,  0.8687,  0.1648, -0.4956,
+  //               -0.8853,  0.7163
+  VCMP_U16(10, v1, 0xa27a, 0x3c7c, 0x3b28, 0x374b, 0xbb6b, 0xb19e, 0x386c,
+           0x3b7d, 0x39c4, 0xb865, 0xb47f, 0x3af3, 0x3146, 0xb7ee, 0xbb15,
+           0x39bb);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                              -0.16110219
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0xbe24f7f9);
+  //               -0.31537205, -0.17563045, -0.79069936,  0.22939304,
+  //               -0.89379781,  0.26157290,  0.56702632, -0.11594663,
+  //               0.09605245,  0.45930776, -0.76518077, -0.26341528,
+  //               0.74385208,  0.89362013, -0.21185355,  0.23924881
+  VLOAD_32(v2, 0xbea17872, 0xbe33d878, 0xbf4a6b46, 0x3e6ae602, 0xbf64cfef,
+           0x3e85ece2, 0x3f1128a3, 0xbded756d, 0x3dc4b726, 0x3eeb2a63,
+           0xbf43e2e3, 0xbe86de5e, 0x3f3e6d17, 0x3f64c44a, 0xbe58f023,
+           0x3e74fda4);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //                0.31856158,  0.48641542,  0.57264513,  0.30210373,
+  //                -0.19719712,  0.85649359,  0.36901370, -0.78377151,
+  //                0.22567192, -0.75179213, -0.65690833,  0.11298654,
+  //                -0.64884853, -0.48376039, -0.11539485, -0.42667609
+  VLOAD_32(v1, 0x3ea31a81, 0x3ef90b71, 0x3f1298df, 0x3e9aad57, 0xbe49ee0b,
+           0x3f5b432a, 0x3ebcef5d, 0xbf48a540, 0x3e67168a, 0xbf407573,
+           0xbf282b25, 0x3de7657d, 0xbf261af0, 0xbef7af71, 0xbdec5422,
+           0xbeda754a);
+  asm volatile("vfnmsub.vf v1, %[A], v2, v0.t" ::[A] "f"(dscalar_32));
+  //                0.31856158, -0.09726786,  0.57264513,  0.27806261,
+  //                -0.19719712,  0.39955589,  0.36901370, -0.24221393,
+  //                0.22567192,  0.33819240, -0.65690833, -0.24521290,
+  //                -0.64884853,  0.81568527, -0.11539485,  0.17051035
+  VCMP_U32(11, v1, 0x3ea31a81, 0xbdc7345f, 0x3f1298df, 0x3e8e5e39, 0xbe49ee0b,
+           0x3ecc9297, 0x3ebcef5d, 0xbe7806ee, 0x3e67168a, 0x3ead278e,
+           0xbf282b25, 0xbe7b1917, 0xbf261af0, 0x3f50d0c0, 0xbdec5422,
+           0x3e2e9a44);
+
+  VSET(16, e64, m1);
+  double dscalar_64;
+  //                                0.5849101968457469
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0x3fe2b79596d194ba);
+  //                -0.7607808895269514, -0.0192591699518767,
+  //                0.6815284686654297, -0.5163928614577513,
+  //                -0.9560613023939111, -0.8652684824342871,
+  //                0.4588682754059621, -0.5708244737077264,
+  //                -0.7636024500128011,  0.2236424444447431,
+  //                0.8245435877598175,  0.8527344486412596,
+  //                -0.3097355632002228,  0.0764086736442742,
+  //                0.2567358761671383,  0.1904958118727702
+  VLOAD_64(v2, 0xbfe8585129fe14da, 0xbf93b8ad045d9c40, 0x3fe5cf14ca86c05c,
+           0xbfe0864a527b2a32, 0xbfee980ddf5818b2, 0xbfebb047874a12f4,
+           0x3fdd5e190b029804, 0xbfe24431afca9858, 0xbfe86f6e67be6a22,
+           0x3fcca050cc719f20, 0x3fea62a93bf1c1ec, 0x3feb4999c122c714,
+           0xbfd3d2b51c969928, 0x3fb38f84d26ed230, 0x3fd06e5c4ff641c8,
+           0x3fc8622ab1025ec0);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //                 0.1182575129292827, -0.8756460666506833,
+  //                 -0.3686593299789440,  0.2802900907620893,
+  //                 -0.5167592439660142,  0.3872686605057347,
+  //                 -0.0640775227939985, -0.4352087179743556,
+  //                 -0.1509314378482451, -0.9803534868251271,
+  //                 0.9211862470421908,  0.7804942879773937,
+  //                 0.5029472314120484,  0.1158347026033590,
+  //                 0.7422982722940397,  0.0792254120441500
+  VLOAD_64(v1, 0x3fbe461fd6899df0, 0xbfec054ae66457d4, 0xbfd7981d4d67fd54,
+           0x3fd1f045d94dd3b0, 0xbfe0894aae97abc2, 0x3fd8c9027de8d2a8,
+           0xbfb0676270cf1540, 0xbfdbda75aaa8928c, 0xbfc351b8aabf8c50,
+           0xbfef5f0e468ddf22, 0x3fed7a5b94924728, 0x3fe8f9cf28327c9e,
+           0x3fe01824cad0e968, 0x3fbda757d36c5e40, 0x3fe7c0e84e6c2aa0,
+           0x3fb4481dd9bde340);
+  asm volatile("vfnmsub.vf v1, %[A], v2, v0.t" ::[A] "f"(dscalar_64));
+  //                0.1182575129292827,  0.4929151432599784,
+  //                -0.3686593299789440, -0.6803373936193172,
+  //                -0.5167592439660142, -1.0917858708828851,
+  //                -0.0640775227939985, -0.3162664568083610,
+  //                -0.1509314378482451,  0.7970611954020426,
+  //                0.9211862470421908,  0.3962153810234212, 0.5029472314120484,
+  //                0.0086557749429749,  0.7422982722940397,  0.1441560605188410
+  VCMP_U64(12, v1, 0x3fbe461fd6899df0, 0x3fdf8bebf5004e06, 0xbfd7981d4d67fd54,
+           0xbfe5c552ecfae837, 0xbfe0894aae97abc2, 0xbff177f4761ad476,
+           0xbfb0676270cf1540, 0xbfd43db5aa3413c6, 0xbfc351b8aabf8c50,
+           0x3fe981867ae532b2, 0x3fed7a5b94924728, 0x3fd95b97c1eabccb,
+           0x3fe01824cad0e968, 0x3f81ba1e7269b44b, 0x3fe7c0e84e6c2aa0,
+           0x3fc273b4aeb96c59);
+};
+
+int main(void) {
+  enable_vec();
+  enable_fp();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vfrdiv.c b/apps/riscv-tests/isa/rv64uv/vfrdiv.c
new file mode 100644
index 0000000..f676427
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vfrdiv.c
@@ -0,0 +1,179 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+//         Matteo Perotti <mperotti@iis.ee.ethz.ch>
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+// Simple random test with similar values (vector-scalar)
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //              -35.5312, -61.8125, -37.3125,  23.5938,  44.4688,  38.1250,
+  //              -93.5000, -23.2031, -62.8125,  27.9844, -26.2344, -10.3594,
+  //              -10.7109, -42.0938,  11.0625,  17.8281
+  VLOAD_16(v2, 0xd071, 0xd3ba, 0xd0aa, 0x4de6, 0x518f, 0x50c4, 0xd5d8, 0xcdcd,
+           0xd3da, 0x4eff, 0xce8f, 0xc92e, 0xc95b, 0xd143, 0x4988, 0x4c75);
+  //                             -17.4844
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0xcc5f);
+  asm volatile("vfrdiv.vf v4, v2, %[A]" ::[A] "f"(dscalar_16));
+  //               0.4922,  0.2830,  0.4685, -0.7412, -0.3931, -0.4585,  0.1870,
+  //               0.7534,  0.2783, -0.6250,  0.6665,  1.6875,  1.6328,  0.4153,
+  //               -1.5801, -0.9810
+  VCMP_U16(1, v4, 0x37df, 0x3486, 0x377f, 0xb9ed, 0xb64a, 0xb756, 0x31fb,
+           0x3a07, 0x3474, 0xb8ff, 0x3954, 0x3ec0, 0x3e87, 0x36a5, 0xbe52,
+           0xbbd8);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //               981163.06250000, -831670.37500000, -85439.06250000,
+  //               64225.75781250, -215361.43750000, -292944.75000000,
+  //               396490.21875000,  954345.93750000,  241910.40625000,
+  //               -62372.83593750,  391838.50000000,  263890.03125000,
+  //               755217.06250000, -6653.31689453,  526939.25000000,
+  //               -759232.75000000
+  VLOAD_32(v2, 0x496f8ab1, 0xc94b0b66, 0xc7a6df88, 0x477ae1c2, 0xc852505c,
+           0xc88f0a18, 0x48c19947, 0x4968fe9f, 0x486c3d9a, 0xc773a4d6,
+           0x48bf53d0, 0x4880da41, 0x49386111, 0xc5cfea89, 0x4900a5b4,
+           0xc9395c0c);
+  //                              -816463.43750000
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0xc94754f7);
+  asm volatile("vfrdiv.vf v4, v2, %[A]" ::[A] "f"(dscalar_32));
+  //              -0.83213836,  0.98171520,  9.55609035,
+  //              -12.71239853,  3.79113102,  2.78709030, -2.05922723,
+  //              -0.85552144, -3.37506533,  13.09004879, -2.08367324,
+  //              -3.09395337, -1.08109772,  122.71524811,
+  //              -1.54944515,  1.07537961
+  VCMP_U32(2, v4, 0xbf550705, 0x3f7b51af, 0x4118e5bf, 0xc14b65fc, 0x4072a1e4,
+           0x40325faf, 0xc003ca60, 0xbf5b0374, 0xc0580112, 0x415170d6,
+           0xc0055ae7, 0xc0460354, 0xbf8a6168, 0x42f56e35, 0xbfc65437,
+           0x3f89a60a);
+
+  VSET(16, e64, m1);
+  double dscalar_64;
+  //               -1436518.0384849868714809,  7616315.8933699131011963,
+  //               -3920170.8619796745479107, -8788296.3276759665459394,
+  //               -4048340.2138868225738406,  7863298.6869412772357464,
+  //               6686376.3073008488863707,  7004262.4451152756810188,
+  //               5533006.3396991230547428,  2002846.6050684414803982,
+  //               -1239975.7277694121003151,  4133787.1656649876385927,
+  //               2465999.3703419454395771, -4337686.8389181373640895,
+  //               -5741249.6292232554405928,  1762825.0474482532590628
+  VLOAD_64(v2, 0xc135eb6609da26f0, 0x415d0dcef92cf900, 0xc14de8956e555998,
+           0xc160c3290a7c524f, 0xc14ee2ea1b60a4b6, 0x415dff00abf6d88c,
+           0x415981aa13aad12e, 0x415ab8199c7cc4c8, 0x41551b5395bda164,
+           0x413e8f9e9ae5c3f0, 0xc132eba7ba4f18a0, 0x414f89cd953482a4,
+           0x4142d067af675d68, 0xc1508c05b5b0d5b3, 0xc155e6b06845319e,
+           0x413ae6090c259198);
+  //                               -181636.6228598635643721
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0xc1062c24fb9df3c0);
+  asm volatile("vfrdiv.vf v4, v2, %[A]" ::[A] "f"(dscalar_64));
+  //               0.1264422847425051, -0.0238483573164265,  0.0463338536137523,
+  //               0.0206680130126992,  0.0448669363895861, -0.0230992907800273,
+  //               -0.0271651810355835, -0.0259322982659703,
+  //               -0.0328278356662322, -0.0906892332144711, 0.1464840148013292,
+  //               -0.0439395197625382, -0.0736563946626949, 0.0418740747326899,
+  //               0.0316371233773435, -0.1030372373723578
+  VCMP_U64(3, v4, 0x3fc02f42c2e6795f, 0xbf986bb42af3122b, 0x3fa7b91223effbc4,
+           0x3f9529fedfd9f42e, 0x3fa6f8cc90ee127a, 0xbf97a75729d81370,
+           0xbf9bd130708d0e6e, 0xbf9a8dff13d98f11, 0xbfa0cecf612b7be2,
+           0xbfb73768dac16680, 0x3fc2bffcfa7aafc4, 0xbfa67f3da0c39bb5,
+           0xbfb2db253e37b0f2, 0x3fa57084cb0de853, 0x3fa032bdb47d8bce,
+           0xbfba60a5fcc8d2be);
+};
+
+// Simple random test with similar values (vector-scalar) (masked)
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //               -35.5312, -61.8125, -37.3125,  23.5938,  44.4688,  38.1250,
+  //               -93.5000, -23.2031, -62.8125,  27.9844, -26.2344, -10.3594,
+  //               -10.7109, -42.0938,  11.0625,  17.8281
+  VLOAD_16(v2, 0xd071, 0xd3ba, 0xd0aa, 0x4de6, 0x518f, 0x50c4, 0xd5d8, 0xcdcd,
+           0xd3da, 0x4eff, 0xce8f, 0xc92e, 0xc95b, 0xd143, 0x4988, 0x4c75);
+  //                             -17.4844
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0xcc5f);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfrdiv.vf v4, v2, %[A], v0.t" ::[A] "f"(dscalar_16));
+  //                0.0000,  0.2830,  0.0000, -0.7412,  0.0000, -0.4585, 0.0000,
+  //                0.7534,  0.0000, -0.6250,  0.0000,  1.6875,  0.0000, 0.4153,
+  //                0.0000, -0.9810
+  VCMP_U16(4, v4, 0x0, 0x3486, 0x0, 0xb9ed, 0x0, 0xb756, 0x0, 0x3a07, 0x0,
+           0xb8ff, 0x0, 0x3ec0, 0x0, 0x36a5, 0x0, 0xbbd8);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                981163.06250000, -831670.37500000, -85439.06250000,
+  //                64225.75781250, -215361.43750000, -292944.75000000,
+  //                396490.21875000,  954345.93750000,  241910.40625000,
+  //                -62372.83593750,  391838.50000000,  263890.03125000,
+  //                755217.06250000, -6653.31689453,  526939.25000000,
+  //                -759232.75000000
+  VLOAD_32(v2, 0x496f8ab1, 0xc94b0b66, 0xc7a6df88, 0x477ae1c2, 0xc852505c,
+           0xc88f0a18, 0x48c19947, 0x4968fe9f, 0x486c3d9a, 0xc773a4d6,
+           0x48bf53d0, 0x4880da41, 0x49386111, 0xc5cfea89, 0x4900a5b4,
+           0xc9395c0c);
+  //                              -816463.43750000
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0xc94754f7);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfrdiv.vf v4, v2, %[A], v0.t" ::[A] "f"(dscalar_32));
+  //                0.00000000,  0.98171520,  0.00000000, -12.71239853,
+  //                0.00000000,  2.78709030,  0.00000000, -0.85552144,
+  //                0.00000000,  13.09004879,  0.00000000, -3.09395337,
+  //                0.00000000,  122.71524811,  0.00000000,  1.07537961
+  VCMP_U32(5, v4, 0x0, 0x3f7b51af, 0x0, 0xc14b65fc, 0x0, 0x40325faf, 0x0,
+           0xbf5b0374, 0x0, 0x415170d6, 0x0, 0xc0460354, 0x0, 0x42f56e35, 0x0,
+           0x3f89a60a);
+
+  VSET(16, e64, m1);
+  double dscalar_64;
+  //                -1436518.0384849868714809,  7616315.8933699131011963,
+  //                -3920170.8619796745479107, -8788296.3276759665459394,
+  //                -4048340.2138868225738406,  7863298.6869412772357464,
+  //                6686376.3073008488863707,  7004262.4451152756810188,
+  //                5533006.3396991230547428,  2002846.6050684414803982,
+  //                -1239975.7277694121003151,  4133787.1656649876385927,
+  //                2465999.3703419454395771, -4337686.8389181373640895,
+  //                -5741249.6292232554405928,  1762825.0474482532590628
+  VLOAD_64(v2, 0xc135eb6609da26f0, 0x415d0dcef92cf900, 0xc14de8956e555998,
+           0xc160c3290a7c524f, 0xc14ee2ea1b60a4b6, 0x415dff00abf6d88c,
+           0x415981aa13aad12e, 0x415ab8199c7cc4c8, 0x41551b5395bda164,
+           0x413e8f9e9ae5c3f0, 0xc132eba7ba4f18a0, 0x414f89cd953482a4,
+           0x4142d067af675d68, 0xc1508c05b5b0d5b3, 0xc155e6b06845319e,
+           0x413ae6090c259198);
+  //                               -181636.6228598635643721
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0xc1062c24fb9df3c0);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfrdiv.vf v4, v2, %[A], v0.t" ::[A] "f"(dscalar_64));
+  //                0.0000000000000000, -0.0238483573164265, 0.0000000000000000,
+  //                0.0206680130126992,  0.0000000000000000,
+  //                -0.0230992907800273,  0.0000000000000000,
+  //                -0.0259322982659703,  0.0000000000000000,
+  //                -0.0906892332144711,  0.0000000000000000,
+  //                -0.0439395197625382,  0.0000000000000000,
+  //                0.0418740747326899,  0.0000000000000000, -0.1030372373723578
+  VCMP_U64(6, v4, 0x0, 0xbf986bb42af3122b, 0x0, 0x3f9529fedfd9f42e, 0x0,
+           0xbf97a75729d81370, 0x0, 0xbf9a8dff13d98f11, 0x0, 0xbfb73768dac16680,
+           0x0, 0xbfa67f3da0c39bb5, 0x0, 0x3fa57084cb0de853, 0x0,
+           0xbfba60a5fcc8d2be);
+};
+
+int main(void) {
+  enable_vec();
+  enable_fp();
+  // Change RM to RTZ since there are issues with FDIV + RNE in fpnew
+  // Update: there are issues also with RTZ...
+  CHANGE_RM(RM_RTZ);
+
+  TEST_CASE1();
+  TEST_CASE2();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vfrec7.c b/apps/riscv-tests/isa/rv64uv/vfrec7.c
new file mode 100644
index 0000000..fe3bd7d
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vfrec7.c
@@ -0,0 +1,121 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+//         Shafiullah Khan <shafi.ullah@10xengineers.ai>
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  VLOAD_16(v2, mInfh, pInfh, qNaNh, sNaNh, pZero, mZeroh, 0xba72, 0x3a12,
+           0x3af7, 0x00fe, 0x01e6, 0x75e6, 0x80fe, 0xb5fd, 0xb4e7, 0x7bc0);
+  asm volatile("vfrec7.v v1, v2");
+  VCMP_U16(1, v1, mZeroh, pZero, qNaNh, qNaNh, pInfh, mInfh, 0xbcf8, 0x3d40,
+           0x3c98, pInfh, 0x7838, 0x02b8, mInfh, 0xc158, 0xc288, 0x0108);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, mInff, pInff, qNaNf, sNaNf, pZero, mZerof, 0xfe7fca13,
+           0x00800000, 0x807ee93e, 0x803ee93e, 0x00200000, 0x00400000,
+           0x00800000, 0xff787a12, 0xff000005, 0x800dd27e);
+  asm volatile("vfrec7.v v1, v2");
+  VCMP_U32(2, v1, mZerof, pZero, qNaNf, qNaNf, pInff, mInff, 0x80800000,
+           0x7e7f0000, 0xfe810000, 0xff020000, 0x7f7f0000, 0x7eff0000,
+           0x7e7f0000, 0x80210000, 0x803fc000, mInff);
+  VSET(16, e64, m1);
+  VLOAD_64(v2, mInfd, pInfd, qNaNd, sNaNd, pZero, mZerod, 0xffee384e0c3fbf7c,
+           0xffdfa4dc68d2ae1a, 0xffcf49b8d1aa1fda, 0x800f47ea9ea8e436,
+           0x800747ea961ff344, 0x00060000005e7fcf, 0x000bffffd07b5869,
+           0x7fbfffff9bfec946, 0x7fdc709c2bde6967, 0x000347ea91db7acb);
+  asm volatile("vfrec7.v v1, v2");
+  VCMP_U64(3, v1, mZerod, pZero, qNaNd, qNaNd, pInfd, mInfd, 0x8004400000000000,
+           0x8008100000000000, 0x8010600000000000, 0xffd0c00000000000,
+           0xffe1a00000000000, 0x7fe5400000000000, 0x7fd5600000000000,
+           0x0020000000000000, 0x0009000000000000, pInfd);
+};
+// Test to check DZ flag
+void TEST_CASE2(void) {
+  CLEAR_FFLAGS;
+  VSET(16, e16, m1);
+  CHECK_FFLAGS(0);
+  VLOAD_16(v2, pZero, mZeroh, pZero, mZeroh, pZero, mZeroh, pZero, mZeroh,
+           pZero, mZeroh, pZero, mZeroh, pZero, mZeroh, pZero, mZeroh);
+  asm volatile("vfrec7.v v1, v2");
+  VCMP_U16(4, v1, pInfh, mInfh, pInfh, mInfh, pInfh, mInfh, pInfh, mInfh, pInfh,
+           mInfh, pInfh, mInfh, pInfh, mInfh, pInfh, mInfh);
+  CHECK_FFLAGS(DZ);
+
+  CLEAR_FFLAGS;
+  VSET(16, e32, m1);
+  CHECK_FFLAGS(0);
+  VLOAD_32(v2, pZero, mZerof, pZero, mZerof, pZero, mZerof, pZero, mZerof,
+           pZero, mZerof, pZero, mZerof, pZero, mZerof, pZero, mZerof);
+  asm volatile("vfrec7.v v1, v2");
+  VCMP_U32(5, v1, pInff, mInff, pInff, mInff, pInff, mInff, pInff, mInff, pInff,
+           mInff, pInff, mInff, pInff, mInff, pInff, mInff);
+  CHECK_FFLAGS(DZ);
+
+  CLEAR_FFLAGS;
+  VSET(16, e64, m1);
+  CHECK_FFLAGS(0);
+  VLOAD_64(v2, pZero, mZerod, pZero, mZerod, pZero, mZerod, pZero, mZerod,
+           pZero, mZerod, pZero, mZerod, pZero, mZerod, pZero, mZerod);
+  asm volatile("vfrec7.v v1, v2");
+  VCMP_U64(6, v1, pInfd, mInfd, pInfd, mInfd, pInfd, mInfd, pInfd, mInfd, pInfd,
+           mInfd, pInfd, mInfd, pInfd, mInfd, pInfd, mInfd);
+  CHECK_FFLAGS(DZ);
+};
+// Test to check NX,OF flags as well as for subnormal numbers with sig=00..
+void TEST_CASE3(void) {
+  CLEAR_FFLAGS;
+  VSET(16, e16, m1);
+  CHECK_FFLAGS(0);
+  CHANGE_RM(RM_RUP);
+  VLOAD_16(v2, 0x80fe, 0x807e, 0x803e, 0x801e, 0x800e, 0x8006, 0x8002, 0x8030,
+           0x00fe, 0x007e, 0x003e, 0x001e, 0x000e, 0x0006, 0x0002, 0x0030);
+  asm volatile("vfrec7.v v1, v2");
+  VCMP_U16(7, v1, mMaxh, mMaxh, mMaxh, mMaxh, mMaxh, mMaxh, mMaxh, mMaxh, pInfh,
+           pInfh, pInfh, pInfh, pInfh, pInfh, pInfh, pInfh);
+  CHECK_FFLAGS(NX | OF);
+
+  CLEAR_FFLAGS;
+  VSET(16, e32, m1);
+  CHECK_FFLAGS(0);
+  CHANGE_RM(RM_RDN);
+  VLOAD_32(v2, 0x800dd27e, 0x8005d27e, 0x8005d27c, 0x8001d27c, 0x8000d27c,
+           0x8000527c, 0x8000127c, 0x8000107c, 0x000dd27e, 0x0005d27e,
+           0x0005d27c, 0x0001d27c, 0x0000d27c, 0x0000527c, 0x0000127c,
+           0x0000107c);
+  asm volatile("vfrec7.v v1, v2");
+  VCMP_U32(8, v1, mInff, mInff, mInff, mInff, mInff, mInff, mInff, mInff, pMaxf,
+           pMaxf, pMaxf, pMaxf, pMaxf, pMaxf, pMaxf, pMaxf);
+  CHECK_FFLAGS(NX | OF);
+
+  CLEAR_FFLAGS;
+  VSET(16, e64, m1);
+  CHECK_FFLAGS(0);
+  CHANGE_RM(RM_RTZ);
+  VLOAD_64(v2, 0x000147ea91db7acb, 0x000347ea91db7acb, 0x000047ea91db7acb,
+           0x000347ea91db70cb, 0x000347ea91db7a0b, 0x000347ea91db7ac0,
+           0x000347ea91db0acb, 0x000348e91db7acb, 0x800147ea91db7acb,
+           0x800347ea91db7acb, 0x800047ea91db7acb, 0x800347ea91db70cb,
+           0x800347ea91db7a0b, 0x800347ea91db7ac0, 0x800347ea91db0acb,
+           0x800147ea91db7a0b);
+  asm volatile("vfrec7.v v1, v2");
+  VCMP_U64(9, v1, pMaxd, pMaxd, pMaxd, pMaxd, pMaxd, pMaxd, pMaxd, pMaxd, mMaxd,
+           mMaxd, mMaxd, mMaxd, mMaxd, mMaxd, mMaxd, mMaxd);
+  CHECK_FFLAGS(NX | OF);
+};
+int main(void) {
+  enable_vec();
+  enable_fp();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vfredmax.c b/apps/riscv-tests/isa/rv64uv/vfredmax.c
new file mode 100644
index 0000000..ddfb104
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vfredmax.c
@@ -0,0 +1,348 @@
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Xiaorui Yin <yinx@student.ethz.ch>
+// Date: 2022/05/03
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+// Naive test
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  // 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
+  VLOAD_16(v2, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800,
+           0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800);
+  VLOAD_16(v3, 0x3c00);
+  asm volatile("vfredmax.vs v1, v2, v3");
+  VCMP_U16(1, v1, 0x4800);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  VLOAD_32(v3, 0x3F800000);
+  asm volatile("vfredmax.vs v1, v2, v3");
+  VCMP_U32(2, v1, 0x41000000);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v3, 0x3FF0000000000000);
+  asm volatile("vfredmax.vs v1, v2, v3");
+  VCMP_U64(3, v1, 0x4020000000000000);
+
+  // Super lang vector length
+  VSET(64, e32, m1);
+  VLOAD_32(
+      v2, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+      0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000, 0x40400000,
+      0x40800000, 0x40A00000, 0x40C00000, 0x40E00000, 0x41000000,
+
+      0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 0x40C00000,
+      0x40E00000, 0x41000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000,
+      0x40A00000, 0x40C00000, 0x40E00000, 0x41000000,
+
+      0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 0x40C00000,
+      0x40E00000, 0x41000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000,
+      0x40A00000, 0x40C00000, 0x40E00000, 0x41000000,
+
+      0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 0x40C00000,
+      0x40E00000, 0x41000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000,
+      0x40A00000, 0x40C00000, 0x40E00000, 0x41000000);
+  VLOAD_32(v3, 0x3F800000);
+  asm volatile("vfredmax.vs v1, v2, v3");
+  VCMP_U32(4, v1, 0x41000000);
+}
+
+// Masked naive test
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  VLOAD_8(v0, 0xaa, 0x55);
+  // 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
+  VLOAD_16(v2, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800,
+           0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800);
+  VLOAD_16(v3, 0x3c00);
+  asm volatile("vfredmax.vs v1, v2, v3, v0.t");
+  VCMP_U16(5, v1, 0x4800);
+
+  VSET(16, e32, m1);
+  VLOAD_8(v0, 0xaa, 0x55);
+  VLOAD_32(v2, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  VLOAD_32(v3, 0x3F800000);
+  asm volatile("vfredmax.vs v1, v2, v3, v0.t");
+  VCMP_U32(6, v1, 0x41000000);
+
+  VSET(16, e64, m1);
+  VLOAD_8(v0, 0xaa, 0x55);
+  VLOAD_64(v2, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v3, 0x3FF0000000000000);
+  asm volatile("vfredmax.vs v1, v2, v3, v0.t");
+  VCMP_U64(7, v1, 0x4020000000000000);
+}
+
+// Are we respecting the undisturbed tail policy?
+void TEST_CASE3(void) {
+  VSET(16, e16, m1);
+  // 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
+  VLOAD_16(v2, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800,
+           0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800);
+  VLOAD_16(v3, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800,
+           0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800);
+  VLOAD_16(v1, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800,
+           0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800);
+  asm volatile("vfredmax.vs v1, v2, v3");
+  VCMP_U16(8, v1, 0x4800, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700,
+           0x4800, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700,
+           0x4800);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  VLOAD_32(v3, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  VLOAD_32(v1, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  asm volatile("vfredmax.vs v1, v2, v3");
+  VCMP_U32(9, v1, 0x41000000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v3, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v1, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  asm volatile("vfredmax.vs v1, v2, v3");
+  VCMP_U64(10, v1, 0x4020000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+}
+
+// Odd number of elements, undisturbed policy
+void TEST_CASE4(void) {
+  VSET(1, e64, m1);
+  VLOAD_64(v2, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v3, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v1, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  asm volatile("vfredmax.vs v1, v2, v3");
+  VCMP_U64(11, v1, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+
+  VSET(3, e64, m1);
+  VLOAD_64(v2, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v3, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v1, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  asm volatile("vfredmax.vs v1, v2, v3");
+  VCMP_U64(12, v1, 0x4008000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3ff0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+
+  VSET(7, e64, m1);
+  VLOAD_64(v2, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v3, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v1, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  asm volatile("vfredmax.vs v1, v2, v3");
+  VCMP_U64(13, v1, 0x401C000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3ff0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+
+  VSET(15, e64, m1);
+  VLOAD_64(v2, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v3, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v1, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  asm volatile("vfredmax.vs v1, v2, v3");
+  VCMP_U64(14, v1, 0x4020000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+}
+
+// Odd number of elements, undisturbed policy, and mask
+void TEST_CASE5(void) {
+  VSET(7, e16, m1);
+  VLOAD_8(v0, 0x00, 0xff);
+  // 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
+  VLOAD_16(v2, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800,
+           0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800);
+  VLOAD_16(v3, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800,
+           0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800);
+  VLOAD_16(v1, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800,
+           0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800);
+  asm volatile("vfredmax.vs v1, v2, v3, v0.t");
+  VCMP_U16(15, v1, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700,
+           0x4800, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700,
+           0x4800);
+
+  VSET(1, e32, m1);
+  VLOAD_8(v0, 0xff, 0x00);
+  VLOAD_32(v2, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  VLOAD_32(v3, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  VLOAD_32(v1, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  asm volatile("vfredmax.vs v1, v2, v3, v0.t");
+  VCMP_U32(16, v1, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+
+  VSET(3, e64, m1);
+  VLOAD_8(v0, 0xaa, 0x55);
+  VLOAD_64(v2, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v3, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v1, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  asm volatile("vfredmax.vs v1, v2, v3, v0.t");
+  VCMP_U64(17, v1, 0x4000000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+  enable_fp();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vfredmin.c b/apps/riscv-tests/isa/rv64uv/vfredmin.c
new file mode 100644
index 0000000..5823797
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vfredmin.c
@@ -0,0 +1,348 @@
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Xiaorui Yin <yinx@student.ethz.ch>
+// Date: 2022/05/03
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+// Naive test
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  // 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
+  VLOAD_16(v2, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800,
+           0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800);
+  VLOAD_16(v3, 0x3c00);
+  asm volatile("vfredmin.vs v1, v2, v3");
+  VCMP_U16(1, v1, 0x3c00);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  VLOAD_32(v3, 0x3F800000);
+  asm volatile("vfredmin.vs v1, v2, v3");
+  VCMP_U32(2, v1, 0x3F800000);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v3, 0x3FF0000000000000);
+  asm volatile("vfredmin.vs v1, v2, v3");
+  VCMP_U64(3, v1, 0x3FF0000000000000);
+
+  // Super lang vector length
+  VSET(64, e32, m1);
+  VLOAD_32(
+      v2, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+      0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000, 0x40400000,
+      0x40800000, 0x40A00000, 0x40C00000, 0x40E00000, 0x41000000,
+
+      0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 0x40C00000,
+      0x40E00000, 0x41000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000,
+      0x40A00000, 0x40C00000, 0x40E00000, 0x41000000,
+
+      0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 0x40C00000,
+      0x40E00000, 0x41000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000,
+      0x40A00000, 0x40C00000, 0x40E00000, 0x41000000,
+
+      0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 0x40C00000,
+      0x40E00000, 0x41000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000,
+      0x40A00000, 0x40C00000, 0x40E00000, 0x41000000);
+  VLOAD_32(v3, 0x3F800000);
+  asm volatile("vfredmin.vs v1, v2, v3");
+  VCMP_U32(4, v1, 0x3F800000);
+}
+
+// Masked naive test
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  VLOAD_8(v0, 0xaa, 0x55);
+  // 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
+  VLOAD_16(v2, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800,
+           0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800);
+  VLOAD_16(v3, 0x3c00);
+  asm volatile("vfredmin.vs v1, v2, v3, v0.t");
+  VCMP_U16(5, v1, 0x3c00);
+
+  VSET(16, e32, m1);
+  VLOAD_8(v0, 0xaa, 0x55);
+  VLOAD_32(v2, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  VLOAD_32(v3, 0x3F800000);
+  asm volatile("vfredmin.vs v1, v2, v3, v0.t");
+  VCMP_U32(6, v1, 0x3F800000);
+
+  VSET(16, e64, m1);
+  VLOAD_8(v0, 0xaa, 0x55);
+  VLOAD_64(v2, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v3, 0x3FF0000000000000);
+  asm volatile("vfredmin.vs v1, v2, v3, v0.t");
+  VCMP_U64(7, v1, 0x3FF0000000000000);
+}
+
+// Are we respecting the undisturbed tail policy?
+void TEST_CASE3(void) {
+  VSET(16, e16, m1);
+  // 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
+  VLOAD_16(v2, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800,
+           0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800);
+  VLOAD_16(v3, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800,
+           0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800);
+  VLOAD_16(v1, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800,
+           0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800);
+  asm volatile("vfredmin.vs v1, v2, v3");
+  VCMP_U16(8, v1, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700,
+           0x4800, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700,
+           0x4800);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  VLOAD_32(v3, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  VLOAD_32(v1, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  asm volatile("vfredmin.vs v1, v2, v3");
+  VCMP_U32(9, v1, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v3, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v1, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  asm volatile("vfredmin.vs v1, v2, v3");
+  VCMP_U64(10, v1, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+}
+
+// Odd number of elements, undisturbed policy
+void TEST_CASE4(void) {
+  VSET(1, e64, m1);
+  VLOAD_64(v2, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v3, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v1, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  asm volatile("vfredmin.vs v1, v2, v3");
+  VCMP_U64(11, v1, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+
+  VSET(3, e64, m1);
+  VLOAD_64(v2, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v3, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v1, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  asm volatile("vfredmin.vs v1, v2, v3");
+  VCMP_U64(12, v1, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3ff0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+
+  VSET(7, e64, m1);
+  VLOAD_64(v2, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v3, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v1, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  asm volatile("vfredmin.vs v1, v2, v3");
+  VCMP_U64(13, v1, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3ff0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+
+  VSET(15, e64, m1);
+  VLOAD_64(v2, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v3, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v1, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  asm volatile("vfredmin.vs v1, v2, v3");
+  VCMP_U64(14, v1, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+}
+
+// Odd number of elements, undisturbed policy, and mask
+void TEST_CASE5(void) {
+  VSET(7, e16, m1);
+  VLOAD_8(v0, 0x00, 0xff);
+  // 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
+  VLOAD_16(v2, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800,
+           0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800);
+  VLOAD_16(v3, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800,
+           0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800);
+  VLOAD_16(v1, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800,
+           0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800);
+  asm volatile("vfredmin.vs v1, v2, v3, v0.t");
+  VCMP_U16(15, v1, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700,
+           0x4800, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700,
+           0x4800);
+
+  VSET(1, e32, m1);
+  VLOAD_8(v0, 0xff, 0x00);
+  VLOAD_32(v2, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  VLOAD_32(v3, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  VLOAD_32(v1, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  asm volatile("vfredmin.vs v1, v2, v3, v0.t");
+  VCMP_U32(16, v1, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+
+  VSET(3, e64, m1);
+  VLOAD_8(v0, 0xaa, 0x55);
+  VLOAD_64(v2, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v3, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v1, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  asm volatile("vfredmin.vs v1, v2, v3, v0.t");
+  VCMP_U64(17, v1, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+  enable_fp();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vfredosum.c b/apps/riscv-tests/isa/rv64uv/vfredosum.c
new file mode 100644
index 0000000..c193b6e
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vfredosum.c
@@ -0,0 +1,348 @@
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Xiaorui Yin <yinx@student.ethz.ch>
+// Date: 2022/05/03
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+// Naive test
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  // 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
+  VLOAD_16(v2, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800,
+           0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800);
+  VLOAD_16(v3, 0x3c00);
+  asm volatile("vfredosum.vs v1, v2, v3");
+  VCMP_U16(1, v1, 0x5490);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  VLOAD_32(v3, 0x3F800000);
+  asm volatile("vfredosum.vs v1, v2, v3");
+  VCMP_U32(2, v1, 0x42920000);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v3, 0x3FF0000000000000);
+  asm volatile("vfredosum.vs v1, v2, v3");
+  VCMP_U64(3, v1, 0x4052400000000000);
+
+  // Super lang vector length
+  VSET(64, e32, m1);
+  VLOAD_32(
+      v2, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+      0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000, 0x40400000,
+      0x40800000, 0x40A00000, 0x40C00000, 0x40E00000, 0x41000000,
+
+      0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 0x40C00000,
+      0x40E00000, 0x41000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000,
+      0x40A00000, 0x40C00000, 0x40E00000, 0x41000000,
+
+      0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 0x40C00000,
+      0x40E00000, 0x41000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000,
+      0x40A00000, 0x40C00000, 0x40E00000, 0x41000000,
+
+      0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 0x40C00000,
+      0x40E00000, 0x41000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000,
+      0x40A00000, 0x40C00000, 0x40E00000, 0x41000000);
+  VLOAD_32(v3, 0x3F800000);
+  asm volatile("vfredosum.vs v1, v2, v3");
+  VCMP_U32(4, v1, 0x43908000);
+}
+
+// Masked naive test
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  VLOAD_8(v0, 0xaa, 0x55);
+  // 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
+  VLOAD_16(v2, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800,
+           0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800);
+  VLOAD_16(v3, 0x3c00);
+  asm volatile("vfredosum.vs v1, v2, v3, v0.t");
+  VCMP_U16(5, v1, 0x50A0);
+
+  VSET(16, e32, m1);
+  VLOAD_8(v0, 0xaa, 0x55);
+  VLOAD_32(v2, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  VLOAD_32(v3, 0x3F800000);
+  asm volatile("vfredosum.vs v1, v2, v3, v0.t");
+  VCMP_U32(6, v1, 0x42140000);
+
+  VSET(16, e64, m1);
+  VLOAD_8(v0, 0xaa, 0x55);
+  VLOAD_64(v2, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v3, 0x3FF0000000000000);
+  asm volatile("vfredosum.vs v1, v2, v3, v0.t");
+  VCMP_U64(7, v1, 0x4042800000000000);
+}
+
+// Are we respecting the undisturbed tail policy?
+void TEST_CASE3(void) {
+  VSET(16, e16, m1);
+  // 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
+  VLOAD_16(v2, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800,
+           0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800);
+  VLOAD_16(v3, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800,
+           0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800);
+  VLOAD_16(v1, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800,
+           0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800);
+  asm volatile("vfredosum.vs v1, v2, v3");
+  VCMP_U16(8, v1, 0x5490, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700,
+           0x4800, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700,
+           0x4800);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  VLOAD_32(v3, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  VLOAD_32(v1, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  asm volatile("vfredosum.vs v1, v2, v3");
+  VCMP_U32(9, v1, 0x42920000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v3, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v1, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  asm volatile("vfredosum.vs v1, v2, v3");
+  VCMP_U64(10, v1, 0x4052400000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+}
+
+// Odd number of elements, undisturbed policy
+void TEST_CASE4(void) {
+  VSET(1, e64, m1);
+  VLOAD_64(v2, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v3, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v1, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  asm volatile("vfredosum.vs v1, v2, v3");
+  VCMP_U64(11, v1, 0x4000000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+
+  VSET(3, e64, m1);
+  VLOAD_64(v2, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v3, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v1, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  asm volatile("vfredosum.vs v1, v2, v3");
+  VCMP_U64(12, v1, 0x401C000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3ff0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+
+  VSET(7, e64, m1);
+  VLOAD_64(v2, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v3, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v1, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  asm volatile("vfredosum.vs v1, v2, v3");
+  VCMP_U64(13, v1, 0x403d000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3ff0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+
+  VSET(15, e64, m1);
+  VLOAD_64(v2, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v3, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v1, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  asm volatile("vfredosum.vs v1, v2, v3");
+  VCMP_U64(14, v1, 0x4050400000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+}
+
+// Odd number of elements, undisturbed policy, and mask
+void TEST_CASE5(void) {
+  VSET(7, e16, m1);
+  VLOAD_8(v0, 0x00, 0xff);
+  // 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
+  VLOAD_16(v2, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800,
+           0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800);
+  VLOAD_16(v3, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800,
+           0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800);
+  VLOAD_16(v1, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800,
+           0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800);
+  asm volatile("vfredosum.vs v1, v2, v3, v0.t");
+  VCMP_U16(15, v1, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700,
+           0x4800, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700,
+           0x4800);
+
+  VSET(1, e32, m1);
+  VLOAD_8(v0, 0xff, 0x00);
+  VLOAD_32(v2, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  VLOAD_32(v3, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  VLOAD_32(v1, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  asm volatile("vfredosum.vs v1, v2, v3, v0.t");
+  VCMP_U32(16, v1, 0x40000000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+
+  VSET(3, e64, m1);
+  VLOAD_8(v0, 0xaa, 0x55);
+  VLOAD_64(v2, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v3, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v1, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  asm volatile("vfredosum.vs v1, v2, v3, v0.t");
+  VCMP_U64(17, v1, 0x4008000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+  enable_fp();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vfredusum.c b/apps/riscv-tests/isa/rv64uv/vfredusum.c
new file mode 100644
index 0000000..9bf6b68
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vfredusum.c
@@ -0,0 +1,348 @@
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Xiaorui Yin <yinx@student.ethz.ch>
+// Date: 2022/05/03
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+// Naive test
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  // 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
+  VLOAD_16(v2, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800,
+           0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800);
+  VLOAD_16(v3, 0x3c00);
+  asm volatile("vfredsum.vs v1, v2, v3");
+  VCMP_U16(1, v1, 0x5490);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  VLOAD_32(v3, 0x3F800000);
+  asm volatile("vfredsum.vs v1, v2, v3");
+  VCMP_F32(2, v1, 0x42920000);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v3, 0x3FF0000000000000);
+  asm volatile("vfredsum.vs v1, v2, v3");
+  VCMP_F64(3, v1, 0x4052400000000000);
+
+  // Super lang vector length
+  VSET(64, e32, m1);
+  VLOAD_32(
+      v2, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+      0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000, 0x40400000,
+      0x40800000, 0x40A00000, 0x40C00000, 0x40E00000, 0x41000000,
+
+      0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 0x40C00000,
+      0x40E00000, 0x41000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000,
+      0x40A00000, 0x40C00000, 0x40E00000, 0x41000000,
+
+      0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 0x40C00000,
+      0x40E00000, 0x41000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000,
+      0x40A00000, 0x40C00000, 0x40E00000, 0x41000000,
+
+      0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 0x40C00000,
+      0x40E00000, 0x41000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000,
+      0x40A00000, 0x40C00000, 0x40E00000, 0x41000000);
+  VLOAD_32(v3, 0x3F800000);
+  asm volatile("vfredsum.vs v1, v2, v3");
+  VCMP_F32(4, v1, 0x43908000);
+}
+
+// Masked naive test
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  VLOAD_8(v0, 0xaa, 0x55);
+  // 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
+  VLOAD_16(v2, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800,
+           0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800);
+  VLOAD_16(v3, 0x3c00);
+  asm volatile("vfredsum.vs v1, v2, v3, v0.t");
+  VCMP_U16(5, v1, 0x50A0);
+
+  VSET(16, e32, m1);
+  VLOAD_8(v0, 0xaa, 0x55);
+  VLOAD_32(v2, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  VLOAD_32(v3, 0x3F800000);
+  asm volatile("vfredsum.vs v1, v2, v3, v0.t");
+  VCMP_F32(6, v1, 0x42140000);
+
+  VSET(16, e64, m1);
+  VLOAD_8(v0, 0xaa, 0x55);
+  VLOAD_64(v2, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v3, 0x3FF0000000000000);
+  asm volatile("vfredsum.vs v1, v2, v3, v0.t");
+  VCMP_F64(7, v1, 0x4042800000000000);
+}
+
+// Are we respecting the undisturbed tail policy?
+void TEST_CASE3(void) {
+  VSET(16, e16, m1);
+  // 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
+  VLOAD_16(v2, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800,
+           0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800);
+  VLOAD_16(v3, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800,
+           0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800);
+  VLOAD_16(v1, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800,
+           0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800);
+  asm volatile("vfredsum.vs v1, v2, v3");
+  VCMP_U16(8, v1, 0x5490, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700,
+           0x4800, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700,
+           0x4800);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  VLOAD_32(v3, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  VLOAD_32(v1, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  asm volatile("vfredsum.vs v1, v2, v3");
+  VCMP_F32(9, v1, 0x42920000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v3, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v1, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  asm volatile("vfredsum.vs v1, v2, v3");
+  VCMP_F64(10, v1, 0x4052400000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+}
+
+// Odd number of elements, undisturbed policy
+void TEST_CASE4(void) {
+  VSET(1, e64, m1);
+  VLOAD_64(v2, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v3, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v1, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  asm volatile("vfredsum.vs v1, v2, v3");
+  VCMP_F64(11, v1, 0x4000000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+
+  VSET(3, e64, m1);
+  VLOAD_64(v2, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v3, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v1, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  asm volatile("vfredsum.vs v1, v2, v3");
+  VCMP_F64(12, v1, 0x401C000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3ff0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+
+  VSET(7, e64, m1);
+  VLOAD_64(v2, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v3, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v1, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  asm volatile("vfredsum.vs v1, v2, v3");
+  VCMP_F64(13, v1, 0x403d000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3ff0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+
+  VSET(15, e64, m1);
+  VLOAD_64(v2, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v3, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v1, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  asm volatile("vfredsum.vs v1, v2, v3");
+  VCMP_F64(14, v1, 0x4050400000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+}
+
+// Odd number of elements, undisturbed policy, and mask
+void TEST_CASE5(void) {
+  VSET(7, e16, m1);
+  VLOAD_8(v0, 0x00, 0xff);
+  // 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
+  VLOAD_16(v2, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800,
+           0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800);
+  VLOAD_16(v3, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800,
+           0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800);
+  VLOAD_16(v1, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800,
+           0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800);
+  asm volatile("vfredsum.vs v1, v2, v3, v0.t");
+  VCMP_U16(15, v1, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700,
+           0x4800, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700,
+           0x4800);
+
+  VSET(1, e32, m1);
+  VLOAD_8(v0, 0xff, 0x00);
+  VLOAD_32(v2, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  VLOAD_32(v3, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  VLOAD_32(v1, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  asm volatile("vfredsum.vs v1, v2, v3, v0.t");
+  VCMP_F32(16, v1, 0x40000000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+
+  VSET(3, e64, m1);
+  VLOAD_8(v0, 0xaa, 0x55);
+  VLOAD_64(v2, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v3, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v1, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  asm volatile("vfredsum.vs v1, v2, v3, v0.t");
+  VCMP_F64(17, v1, 0x4008000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+  enable_fp();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vfrsqrt7.c b/apps/riscv-tests/isa/rv64uv/vfrsqrt7.c
new file mode 100644
index 0000000..268f9cd
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vfrsqrt7.c
@@ -0,0 +1,71 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+//         Shafiullah Khan <shafi.ullah@10xengineers.ai>
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  VLOAD_16(v2, mInfh, pInfh, qNaNh, sNaNh, pZero, mZeroh, 0x3a12, 0x0001,
+           0x3af7, 0x00fe, 0x01e6, 0x75e6, 0x80fe, 0x35fd, 0x20a7, 0x7bc0);
+  asm volatile("vfrsqrt7.v v1, v2");
+  VCMP_U16(1, v1, qNaNh, pZero, qNaNh, qNaNh, pInfh, mInfh, 0x3c98, 0x6bf8,
+           0x3c48, 0x5c00, 0x59d0, 0x1e98, qNaNh, 0x3e90, 0x4940, 0x1c10);
+  VSET(16, e32, m1);
+  VLOAD_32(v2, mInff, pInff, qNaNf, 0xfe7fca13, 0x00800000, 0x00200000,
+           0x003f3cde, 0x00400000, 0x7f787a12, 0x7f000005, 0x7ef0f42d,
+           0x7f765432, 0x00718abc, 0x00e50000, 0x001ee941, 0x00000001);
+  asm volatile("vfrsqrt7.v v1, v2");
+  VCMP_U32(2, v1, qNaNf, pZero, qNaNf, qNaNf, 0x5eff0000, 0x5f7f0000,
+           0x5f360000, 0x5f340000, 0x1f820000, 0x1fb40000, 0x1fbb0000,
+           0x1f820000, 0x5f080000, 0x5ebf0000, 0x5f820000, 0x64b40000);
+  VSET(16, e64, m1);
+  VLOAD_64(v2, mInfd, pInfd, qNaNd, sNaNd, pZero, mZerod, 0xffee384e0c3fbf7c,
+           0x00060000005e7fcf, 0x000bffffd07b5869, 0x7fbfffff9bfec946,
+           0x7fdc709c2bde6967, 0x000347ea91db7acb, 0x7fd5600000000000,
+           0x000000000000001, 0x000000000000ded, 0x7fdc000000006967);
+  asm volatile("vfrsqrt7.v v1, v2");
+  VCMP_U64(3, v1, qNaNd, pZero, qNaNd, qNaNd, pInfd, mInfd, qNaNd,
+           0x5fea000000000000, 0x5fe2800000000000, 0x2006a00000000000,
+           0x1ff8000000000000, 0x5ff1c00000000000, 0x1ffba00000000000,
+           0x617fe00000000000, 0x6121200000000000, 0x1ff8200000000000);
+};
+// Exceptions check
+void TEST_CASE2(void) {
+  // Invalid operation
+  CLEAR_FFLAGS;
+  VSET(16, e16, m1);
+  CHECK_FFLAGS(0);
+  VLOAD_16(v2, mInfh, sNaNh, 0xba12, 0x8001, 0xbaf7, 0x80fe, 0x81e6, 0xf5e6,
+           0x80ff, 0xb5fd, 0xa0a7, 0xfbc0, mInfh, sNaNh, mInfh, sNaNh);
+  asm volatile("vfrsqrt7.v v1, v2");
+  VCMP_U16(4, v1, qNaNh, qNaNh, qNaNh, qNaNh, qNaNh, qNaNh, qNaNh, qNaNh, qNaNh,
+           qNaNh, qNaNh, qNaNh, qNaNh, qNaNh, qNaNh, qNaNh);
+  CHECK_FFLAGS(NV);
+
+  // Divide by zero
+  CLEAR_FFLAGS;
+  VSET(16, e32, m1);
+  CHECK_FFLAGS(0);
+  VLOAD_32(v2, pZero, mZerof, pZero, mZerof, pZero, mZerof, pZero, mZerof,
+           pZero, mZerof, pZero, mZerof, pZero, mZerof, pZero, mZerof);
+  asm volatile("vfrsqrt7.v v1, v2");
+  VCMP_U32(5, v1, pInff, mInff, pInff, mInff, pInff, mInff, pInff, mInff, pInff,
+           mInff, pInff, mInff, pInff, mInff, pInff, mInff);
+  CHECK_FFLAGS(DZ);
+};
+
+int main(void) {
+  enable_vec();
+  enable_fp();
+
+  TEST_CASE1();
+  TEST_CASE2();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vfrsub.c b/apps/riscv-tests/isa/rv64uv/vfrsub.c
new file mode 100644
index 0000000..4dcf3d7
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vfrsub.c
@@ -0,0 +1,167 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+// Simple random test with similar values (vector-scalar)
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  //              -0.0273, -0.8511,  0.7173,  0.9551, -0.7842, -0.6509, -0.5771,
+  //              0.6060, -0.5361,  0.6099,  0.2859,  0.6318, -0.9521,  0.3818,
+  //              0.2783, -0.7905
+  VLOAD_16(v2, 0xa700, 0xbacf, 0x39bd, 0x3ba4, 0xba46, 0xb935, 0xb89e, 0x38d9,
+           0xb84a, 0x38e1, 0x3493, 0x390e, 0xbb9e, 0x361c, 0x3474, 0xba53);
+  double dscalar_16;
+  //                              0.3062
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0x34e6);
+  asm volatile("vfrsub.vf v1, v2, %[A]" ::[A] "f"(dscalar_16));
+  //               0.3335,  1.1572, -0.4111, -0.6489,  1.0898,  0.9570,  0.8833,
+  //               -0.2998,  0.8423, -0.3037,  0.0203, -0.3257,  1.2578,
+  //               -0.0757,  0.0278,  1.0967
+  VCMP_U16(1, v1, 0x3556, 0x3ca1, 0xb694, 0xb931, 0x3c5c, 0x3ba8, 0x3b11,
+           0xb4cc, 0x3abd, 0xb4dc, 0x2530, 0xb536, 0x3d08, 0xacd8, 0x2720,
+           0x3c63);
+
+  VSET(16, e32, m1);
+  //               0.61218858,  0.50298065,  0.82400811, -0.50508654,
+  //               -0.08447543, -0.66344708, -0.94741052,  0.85856712,
+  //               -0.16725175, -0.36700448, -0.86911696,  0.82600677,
+  //               -0.95377433,  0.06016647,  0.67027277,  0.08167093
+  VLOAD_32(v2, 0x3f1cb864, 0x3f00c357, 0x3f52f232, 0xbf014d5a, 0xbdad0174,
+           0xbf29d7ab, 0xbf72897f, 0x3f5bcb0e, 0xbe2b440b, 0xbebbe803,
+           0xbf5e7e73, 0x3f53752e, 0xbf742a8e, 0x3d76711d, 0x3f2b96ff,
+           0x3da74316);
+  double dscalar_32;
+  //                              -0.78482366
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0xbf48ea34);
+  asm volatile("vfrsub.vf v1, v2, %[A]" ::[A] "f"(dscalar_32));
+  //              -1.39701223, -1.28780437, -1.60883176, -0.27973711,
+  //              -0.70034826, -0.12137657,  0.16258687, -1.64339077,
+  //              -0.61757189, -0.41781917,  0.08429331, -1.61083043,
+  //              0.16895068, -0.84499013, -1.45509648, -0.86649460
+  VCMP_U32(2, v1, 0xbfb2d14c, 0xbfa4d6c6, 0xbfcdee33, 0xbe8f39b4, 0xbf334a06,
+           0xbdf89448, 0x3e267d2c, 0xbfd25aa1, 0xbf1e1931, 0xbed5ec65,
+           0x3daca1f8, 0xbfce2fb1, 0x3e2d0168, 0xbf585146, 0xbfba409a,
+           0xbf5dd297);
+
+  VSET(16, e64, m1);
+  //               -0.0920900511004143,  0.2386858516984947, 0.7068975504949517,
+  //               0.5997172971219242,  0.7714780386644180, -0.1053493184316212,
+  //               0.8711121216121871, -0.7388672665065719,  0.0889924652556937,
+  //               0.3266446452514173, -0.5909707717470494, -0.2733520923877579,
+  //               0.2365505631181986,  0.9616545156279142, -0.9315790291358075,
+  //               -0.8056559777055108
+  VLOAD_64(v2, 0xbfb79336adc36440, 0x3fce8d420b880e70, 0x3fe69ee79c9ff24a,
+           0x3fe330e2543f7e66, 0x3fe8aff2b634ab34, 0xbfbaf82c4551d810,
+           0x3febe026872f2710, 0xbfe7a4ccf737616c, 0x3fb6c835cfdd1640,
+           0x3fd4e7bef1312ccc, 0xbfe2e93b89317464, 0xbfd17e99c6464f50,
+           0x3fce4749f238b5c0, 0x3feec5dfb0d5860a, 0xbfedcf7ed2f8e31e,
+           0xbfe9c7ef0b824e6e);
+  double dscalar_64;
+  //                               -0.4500891854782252
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0xbfdcce42defa6264);
+  asm volatile("vfrsub.vf v1, v2, %[A]" ::[A] "f"(dscalar_64));
+  //              -0.3579991343778108, -0.6887750371767198, -1.1569867359731769,
+  //              -1.0498064826001494, -1.2215672241426432, -0.3447398670466040,
+  //              -1.3212013070904123,  0.2887780810283467, -0.5390816507339189,
+  //              -0.7767338307296425,  0.1408815862688242, -0.1767370930904673,
+  //              -0.6866397485964237, -1.4117437011061393,  0.4814898436575823,
+  //              0.3555667922272856
+  VCMP_U64(3, v1, 0xbfd6e97533898954, 0xbfe60a71f25f34ce, 0xbff28304860e91be,
+           0xbff0cc01e1de57cc, 0xbff38b8a12d8ee33, 0xbfd61037cda5ec60,
+           0xbff523a3fb562c21, 0x3fd27b570f746074, 0xbfe140282978d3fa,
+           0xbfe8db00e815c798, 0x3fc2086866d10cc8, 0xbfc69f5231682628,
+           0xbfe5f8f3ec0b5ea2, 0xbff6968090295b9e, 0x3fded0bac6f763d8,
+           0x3fd6c19b380a3a78);
+};
+
+// Simple random test with similar values (vector-scalar) (masked)
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  //               -0.0273, -0.8511,  0.7173,  0.9551, -0.7842, -0.6509,
+  //               -0.5771,  0.6060, -0.5361,  0.6099,  0.2859,  0.6318,
+  //               -0.9521,  0.3818,  0.2783, -0.7905
+  VLOAD_16(v2, 0xa700, 0xbacf, 0x39bd, 0x3ba4, 0xba46, 0xb935, 0xb89e, 0x38d9,
+           0xb84a, 0x38e1, 0x3493, 0x390e, 0xbb9e, 0x361c, 0x3474, 0xba53);
+  double dscalar_16;
+  //                              0.3062
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0x34e6);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfrsub.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_16));
+  //                0.0000,  1.1572,  0.0000, -0.6489,  0.0000,  0.9570, 0.0000,
+  //                -0.2998,  0.0000, -0.3037,  0.0000, -0.3257,  0.0000,
+  //                -0.0757,  0.0000,  1.0967
+  VCMP_U16(4, v1, 0x0, 0x3ca1, 0x0, 0xb931, 0x0, 0x3ba8, 0x0, 0xb4cc, 0x0,
+           0xb4dc, 0x0, 0xb536, 0x0, 0xacd8, 0x0, 0x3c63);
+
+  VSET(16, e32, m1);
+  //                0.61218858,  0.50298065,  0.82400811, -0.50508654,
+  //                -0.08447543, -0.66344708, -0.94741052,  0.85856712,
+  //                -0.16725175, -0.36700448, -0.86911696,  0.82600677,
+  //                -0.95377433,  0.06016647,  0.67027277,  0.08167093
+  VLOAD_32(v2, 0x3f1cb864, 0x3f00c357, 0x3f52f232, 0xbf014d5a, 0xbdad0174,
+           0xbf29d7ab, 0xbf72897f, 0x3f5bcb0e, 0xbe2b440b, 0xbebbe803,
+           0xbf5e7e73, 0x3f53752e, 0xbf742a8e, 0x3d76711d, 0x3f2b96ff,
+           0x3da74316);
+  double dscalar_32;
+  //                              -0.78482366
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0xbf48ea34);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfrsub.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_32));
+  //                0.00000000, -1.28780437,  0.00000000, -0.27973711,
+  //                0.00000000, -0.12137657,  0.00000000, -1.64339077,
+  //                0.00000000, -0.41781917,  0.00000000, -1.61083043,
+  //                0.00000000, -0.84499013,  0.00000000, -0.86649460
+  VCMP_U32(5, v1, 0x0, 0xbfa4d6c6, 0x0, 0xbe8f39b4, 0x0, 0xbdf89448, 0x0,
+           0xbfd25aa1, 0x0, 0xbed5ec65, 0x0, 0xbfce2fb1, 0x0, 0xbf585146, 0x0,
+           0xbf5dd297);
+
+  VSET(16, e64, m1);
+  //                -0.0920900511004143,  0.2386858516984947,
+  //                0.7068975504949517,  0.5997172971219242, 0.7714780386644180,
+  //                -0.1053493184316212,  0.8711121216121871,
+  //                -0.7388672665065719,  0.0889924652556937,
+  //                0.3266446452514173, -0.5909707717470494,
+  //                -0.2733520923877579,  0.2365505631181986,
+  //                0.9616545156279142, -0.9315790291358075, -0.8056559777055108
+  VLOAD_64(v2, 0xbfb79336adc36440, 0x3fce8d420b880e70, 0x3fe69ee79c9ff24a,
+           0x3fe330e2543f7e66, 0x3fe8aff2b634ab34, 0xbfbaf82c4551d810,
+           0x3febe026872f2710, 0xbfe7a4ccf737616c, 0x3fb6c835cfdd1640,
+           0x3fd4e7bef1312ccc, 0xbfe2e93b89317464, 0xbfd17e99c6464f50,
+           0x3fce4749f238b5c0, 0x3feec5dfb0d5860a, 0xbfedcf7ed2f8e31e,
+           0xbfe9c7ef0b824e6e);
+  double dscalar_64;
+  //                               -0.4500891854782252
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0xbfdcce42defa6264);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfrsub.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_64));
+  //                0.0000000000000000, -0.6887750371767198, 0.0000000000000000,
+  //                -1.0498064826001494,  0.0000000000000000,
+  //                -0.3447398670466040,  0.0000000000000000,
+  //                0.2887780810283467,  0.0000000000000000,
+  //                -0.7767338307296425,  0.0000000000000000,
+  //                -0.1767370930904673,  0.0000000000000000,
+  //                -1.4117437011061393,  0.0000000000000000, 0.3555667922272856
+  VCMP_U64(6, v1, 0x0, 0xbfe60a71f25f34ce, 0x0, 0xbff0cc01e1de57cc, 0x0,
+           0xbfd61037cda5ec60, 0x0, 0x3fd27b570f746074, 0x0, 0xbfe8db00e815c798,
+           0x0, 0xbfc69f5231682628, 0x0, 0xbff6968090295b9e, 0x0,
+           0x3fd6c19b380a3a78);
+};
+
+int main(void) {
+  enable_vec();
+  enable_fp();
+
+  TEST_CASE1();
+  TEST_CASE2();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vfsgnj.c b/apps/riscv-tests/isa/rv64uv/vfsgnj.c
new file mode 100644
index 0000000..b7cbe50
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vfsgnj.c
@@ -0,0 +1,408 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+// Simple random test with similar values
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  //               0.3784,  0.9043, -0.4600, -0.6748,  0.4448,  0.8804,  0.1497,
+  //               0.7285,  0.9927,  0.9922,  0.8965,  0.8672, -0.1860,  0.9336,
+  //               -0.2959,  0.9668
+  VLOAD_16(v2, 0x360e, 0x3b3c, 0xb75c, 0xb966, 0x371e, 0x3b0b, 0x30ca, 0x39d4,
+           0x3bf1, 0x3bf0, 0x3b2c, 0x3af0, 0xb1f4, 0x3b78, 0xb4bc, 0x3bbc);
+  //              -0.7988, -0.5054, -0.9380, -0.7383, -0.7168,  0.2181, -0.1597,
+  //              0.1833,  0.0045, -0.2152,  0.1919, -0.6914,  0.1748, -0.8604,
+  //              0.6084,  0.1591
+  VLOAD_16(v3, 0xba64, 0xb80b, 0xbb81, 0xb9e8, 0xb9bc, 0x32fb, 0xb11c, 0x31de,
+           0x1c8f, 0xb2e3, 0x3224, 0xb988, 0x3198, 0xbae2, 0x38de, 0x3117);
+  asm volatile("vfsgnj.vv v1, v2, v3");
+  //              -0.3784, -0.9043, -0.4600, -0.6748, -0.4448,  0.8804, -0.1497,
+  //              0.7285,  0.9927, -0.9922,  0.8965, -0.8672,  0.1860, -0.9336,
+  //              0.2959,  0.9668
+  VCMP_U16(1, v1, 0xb60e, 0xbb3c, 0xb75c, 0xb966, 0xb71e, 0x3b0b, 0xb0ca,
+           0x39d4, 0x3bf1, 0xbbf0, 0x3b2c, 0xbaf0, 0x31f4, 0xbb78, 0x34bc,
+           0x3bbc);
+
+  VSET(16, e32, m1);
+  //               0.30226409,  0.06318295, -0.82590002, -0.17829193,
+  //               0.45379546,  0.85831785, -0.43186289, -0.32250872,
+  //               0.35404092, -0.55081791,  0.09124859, -0.13254598,
+  //               0.95786512,  0.95395225,  0.19890578,  0.76956910
+  VLOAD_32(v2, 0x3e9ac25c, 0x3d816610, 0xbf536e2f, 0xbe369229, 0x3ee857e1,
+           0x3f5bbab8, 0xbedd1d22, 0xbea51fdd, 0x3eb544da, 0xbf0d0267,
+           0x3dbae08b, 0xbe07ba22, 0x3f7536a6, 0x3f743637, 0x3e4badf5,
+           0x3f45027b);
+  //               0.06560040,  0.31805936,  0.14663234, -0.85004497,
+  //               -0.49171701,  0.32139263, -0.09995110, -0.34368968,
+  //               0.33917251,  0.07372360,  0.70147520,  0.82915747,
+  //               -0.14581841, -0.19974701, -0.58837658,  0.95794803
+  VLOAD_32(v3, 0x3d865981, 0x3ea2d8ad, 0x3e1626ca, 0xbf599c8c, 0xbefbc255,
+           0x3ea48d93, 0xbdccb329, 0xbeaff818, 0x3eada805, 0x3d96fc66,
+           0x3f3393e1, 0x3f5443aa, 0xbe15516c, 0xbe4c8a7b, 0xbf169fd9,
+           0x3f753c15);
+  asm volatile("vfsgnj.vv v1, v2, v3");
+  //               0.30226409,  0.06318295,  0.82590002, -0.17829193,
+  //               -0.45379546,  0.85831785, -0.43186289, -0.32250872,
+  //               0.35404092,  0.55081791,  0.09124859,  0.13254598,
+  //               -0.95786512, -0.95395225, -0.19890578,  0.76956910
+  VCMP_U32(2, v1, 0x3e9ac25c, 0x3d816610, 0x3f536e2f, 0xbe369229, 0xbee857e1,
+           0x3f5bbab8, 0xbedd1d22, 0xbea51fdd, 0x3eb544da, 0x3f0d0267,
+           0x3dbae08b, 0x3e07ba22, 0xbf7536a6, 0xbf743637, 0xbe4badf5,
+           0x3f45027b);
+
+  VSET(16, e64, m1);
+  //              -0.1900636538602862, -0.9484843154859770,  0.5869658512198073,
+  //              0.4707187701595239,  0.1954104859873083,  0.0486819373954939,
+  //              -0.1899986048192088, -0.1837438621239862,  0.2694105234528963,
+  //              -0.7960262036276018,  0.6381040017115214,  0.2199215324293253,
+  //              0.4219965521278597, -0.6541697303087526,  0.7254411745966671,
+  //              0.2439726910863504
+  VLOAD_64(v2, 0xbfc854017cbe7d20, 0xbfee59fbc778ffbc, 0x3fe2c86c9bdb73b4,
+           0x3fde20419edcb428, 0x3fc90335f74e33c8, 0x3fa8ecd6c20a0480,
+           0xbfc851dfd0fdf7f8, 0xbfc784eb3b54e580, 0x3fd13e05a2db6b68,
+           0xbfe9790bf1eadde4, 0x3fe46b59155986dc, 0x3fcc266386bc2e10,
+           0x3fdb01fdd39a7d9c, 0xbfe4eef55bb6b208, 0x3fe736d06902107a,
+           0x3fcf3a7f44aa9f48);
+  //               0.0713540199640168,  0.3499800646587572, -0.5478360240866667,
+  //               -0.7324007835973676,  0.5646664961108800,
+  //               -0.7430380608733607, -0.5676032662558192,
+  //               -0.7382565525776155, -0.7933198466305424,
+  //               -0.0650991402083496, -0.1766522935757786,
+  //               -0.4663829943595241, -0.1565231028144627,
+  //               -0.0629224333525875, -0.9086692399439535, -0.1206057821437510
+  VLOAD_64(v3, 0x3fb24441ce2eff50, 0x3fd66612c8fd8664, 0xbfe187df69e0bb9c,
+           0xbfe76fd3c4a3b1e8, 0x3fe211bf78be2e36, 0xbfe7c6f7c1644c86,
+           0xbfe229ce53357d20, 0xbfe79fcc34ac1d30, 0xbfe962e04d917824,
+           0xbfb0aa5656314cf0, 0xbfc69c8ad7d5ef20, 0xbfddd9380f0bd244,
+           0xbfc408f2f3d40a40, 0xbfb01baf416f2160, 0xbfed13d1838e183a,
+           0xbfbee005420412c0);
+  asm volatile("vfsgnj.vv v1, v2, v3");
+  //               0.1900636538602862,  0.9484843154859770, -0.5869658512198073,
+  //               -0.4707187701595239,  0.1954104859873083,
+  //               -0.0486819373954939, -0.1899986048192088,
+  //               -0.1837438621239862, -0.2694105234528963,
+  //               -0.7960262036276018, -0.6381040017115214,
+  //               -0.2199215324293253, -0.4219965521278597,
+  //               -0.6541697303087526, -0.7254411745966671, -0.2439726910863504
+  VCMP_U64(3, v1, 0x3fc854017cbe7d20, 0x3fee59fbc778ffbc, 0xbfe2c86c9bdb73b4,
+           0xbfde20419edcb428, 0x3fc90335f74e33c8, 0xbfa8ecd6c20a0480,
+           0xbfc851dfd0fdf7f8, 0xbfc784eb3b54e580, 0xbfd13e05a2db6b68,
+           0xbfe9790bf1eadde4, 0xbfe46b59155986dc, 0xbfcc266386bc2e10,
+           0xbfdb01fdd39a7d9c, 0xbfe4eef55bb6b208, 0xbfe736d06902107a,
+           0xbfcf3a7f44aa9f48);
+};
+
+// Simple random test with similar values (masked)
+// The numbers are the same of TEST_CASE1
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  //               0.3784,  0.9043, -0.4600, -0.6748,  0.4448,  0.8804,  0.1497,
+  //               0.7285,  0.9927,  0.9922,  0.8965,  0.8672, -0.1860,  0.9336,
+  //               -0.2959,  0.9668
+  VLOAD_16(v2, 0x360e, 0x3b3c, 0xb75c, 0xb966, 0x371e, 0x3b0b, 0x30ca, 0x39d4,
+           0x3bf1, 0x3bf0, 0x3b2c, 0x3af0, 0xb1f4, 0x3b78, 0xb4bc, 0x3bbc);
+  //              -0.7988, -0.5054, -0.9380, -0.7383, -0.7168,  0.2181, -0.1597,
+  //              0.1833,  0.0045, -0.2152,  0.1919, -0.6914,  0.1748, -0.8604,
+  //              0.6084,  0.1591
+  VLOAD_16(v3, 0xba64, 0xb80b, 0xbb81, 0xb9e8, 0xb9bc, 0x32fb, 0xb11c, 0x31de,
+           0x1c8f, 0xb2e3, 0x3224, 0xb988, 0x3198, 0xbae2, 0x38de, 0x3117);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfsgnj.vv v1, v2, v3, v0.t");
+  //               0.0000, -0.9043,  0.0000, -0.6748,  0.0000,  0.8804,  0.0000,
+  //               0.7285,  0.0000, -0.9922,  0.0000, -0.8672,  0.0000, -0.9336,
+  //               0.0000,  0.9668
+  VCMP_U16(4, v1, 0x0, 0xbb3c, 0x0, 0xb966, 0x0, 0x3b0b, 0x0, 0x39d4, 0x0,
+           0xbbf0, 0x0, 0xbaf0, 0x0, 0xbb78, 0x0, 0x3bbc);
+
+  VSET(16, e32, m1);
+  //               0.30226409,  0.06318295, -0.82590002, -0.17829193,
+  //               0.45379546,  0.85831785, -0.43186289, -0.32250872,
+  //               0.35404092, -0.55081791,  0.09124859, -0.13254598,
+  //               0.95786512,  0.95395225,  0.19890578,  0.76956910
+  VLOAD_32(v2, 0x3e9ac25c, 0x3d816610, 0xbf536e2f, 0xbe369229, 0x3ee857e1,
+           0x3f5bbab8, 0xbedd1d22, 0xbea51fdd, 0x3eb544da, 0xbf0d0267,
+           0x3dbae08b, 0xbe07ba22, 0x3f7536a6, 0x3f743637, 0x3e4badf5,
+           0x3f45027b);
+  //               0.06560040,  0.31805936,  0.14663234, -0.85004497,
+  //               -0.49171701,  0.32139263, -0.09995110, -0.34368968,
+  //               0.33917251,  0.07372360,  0.70147520,  0.82915747,
+  //               -0.14581841, -0.19974701, -0.58837658,  0.95794803
+  VLOAD_32(v3, 0x3d865981, 0x3ea2d8ad, 0x3e1626ca, 0xbf599c8c, 0xbefbc255,
+           0x3ea48d93, 0xbdccb329, 0xbeaff818, 0x3eada805, 0x3d96fc66,
+           0x3f3393e1, 0x3f5443aa, 0xbe15516c, 0xbe4c8a7b, 0xbf169fd9,
+           0x3f753c15);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfsgnj.vv v1, v2, v3, v0.t");
+  //               0.00000000,  0.06318295,  0.00000000, -0.17829193,
+  //               0.00000000,  0.85831785,  0.00000000, -0.32250872,
+  //               0.00000000,  0.55081791,  0.00000000,  0.13254598,
+  //               0.00000000, -0.95395225,  0.00000000,  0.76956910
+  VCMP_U32(5, v1, 0x0, 0x3d816610, 0x0, 0xbe369229, 0x0, 0x3f5bbab8, 0x0,
+           0xbea51fdd, 0x0, 0x3f0d0267, 0x0, 0x3e07ba22, 0x0, 0xbf743637, 0x0,
+           0x3f45027b);
+
+  VSET(16, e64, m1);
+  //              -0.1900636538602862, -0.9484843154859770,  0.5869658512198073,
+  //              0.4707187701595239,  0.1954104859873083,  0.0486819373954939,
+  //              -0.1899986048192088, -0.1837438621239862,  0.2694105234528963,
+  //              -0.7960262036276018,  0.6381040017115214,  0.2199215324293253,
+  //              0.4219965521278597, -0.6541697303087526,  0.7254411745966671,
+  //              0.2439726910863504
+  VLOAD_64(v2, 0xbfc854017cbe7d20, 0xbfee59fbc778ffbc, 0x3fe2c86c9bdb73b4,
+           0x3fde20419edcb428, 0x3fc90335f74e33c8, 0x3fa8ecd6c20a0480,
+           0xbfc851dfd0fdf7f8, 0xbfc784eb3b54e580, 0x3fd13e05a2db6b68,
+           0xbfe9790bf1eadde4, 0x3fe46b59155986dc, 0x3fcc266386bc2e10,
+           0x3fdb01fdd39a7d9c, 0xbfe4eef55bb6b208, 0x3fe736d06902107a,
+           0x3fcf3a7f44aa9f48);
+  //               0.0713540199640168,  0.3499800646587572, -0.5478360240866667,
+  //               -0.7324007835973676,  0.5646664961108800,
+  //               -0.7430380608733607, -0.5676032662558192,
+  //               -0.7382565525776155, -0.7933198466305424,
+  //               -0.0650991402083496, -0.1766522935757786,
+  //               -0.4663829943595241, -0.1565231028144627,
+  //               -0.0629224333525875, -0.9086692399439535, -0.1206057821437510
+  VLOAD_64(v3, 0x3fb24441ce2eff50, 0x3fd66612c8fd8664, 0xbfe187df69e0bb9c,
+           0xbfe76fd3c4a3b1e8, 0x3fe211bf78be2e36, 0xbfe7c6f7c1644c86,
+           0xbfe229ce53357d20, 0xbfe79fcc34ac1d30, 0xbfe962e04d917824,
+           0xbfb0aa5656314cf0, 0xbfc69c8ad7d5ef20, 0xbfddd9380f0bd244,
+           0xbfc408f2f3d40a40, 0xbfb01baf416f2160, 0xbfed13d1838e183a,
+           0xbfbee005420412c0);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfsgnj.vv v1, v2, v3, v0.t");
+  //               0.0000000000000000,  0.9484843154859770,  0.0000000000000000,
+  //               -0.4707187701595239,  0.0000000000000000,
+  //               -0.0486819373954939,  0.0000000000000000,
+  //               -0.1837438621239862,  0.0000000000000000,
+  //               -0.7960262036276018,  0.0000000000000000,
+  //               -0.2199215324293253,  0.0000000000000000,
+  //               -0.6541697303087526,  0.0000000000000000, -0.2439726910863504
+  VCMP_U64(6, v1, 0x0, 0x3fee59fbc778ffbc, 0x0, 0xbfde20419edcb428, 0x0,
+           0xbfa8ecd6c20a0480, 0x0, 0xbfc784eb3b54e580, 0x0, 0xbfe9790bf1eadde4,
+           0x0, 0xbfcc266386bc2e10, 0x0, 0xbfe4eef55bb6b208, 0x0,
+           0xbfcf3a7f44aa9f48);
+};
+
+// Simple random test with similar values (vector-scalar)
+void TEST_CASE3(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //                              0.9023
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0x3b38);
+  //               0.5586,  0.0221,  0.7397,  0.9844, -0.1426,  0.6958,  0.0319,
+  //               0.3943, -0.5425,  0.9814,  0.7852, -0.7271, -0.1810, -0.7485,
+  //               -0.3499, -0.2178
+  VLOAD_16(v2, 0x3878, 0x25a7, 0x39eb, 0x3be0, 0xb090, 0x3991, 0x2816, 0x364f,
+           0xb857, 0x3bda, 0x3a48, 0xb9d1, 0xb1cb, 0xb9fd, 0xb599, 0xb2f8);
+  asm volatile("vfsgnj.vf v1, v2, %[A]" ::[A] "f"(dscalar_16));
+  //               0.5586,  0.0221,  0.7397,  0.9844,  0.1426,  0.6958,  0.0319,
+  //               0.3943,  0.5425,  0.9814,  0.7852,  0.7271,  0.1810,  0.7485,
+  //               0.3499,  0.2178
+  VCMP_U16(7, v1, 0x3878, 0x25a7, 0x39eb, 0x3be0, 0x3090, 0x3991, 0x2816,
+           0x364f, 0x3857, 0x3bda, 0x3a48, 0x39d1, 0x31cb, 0x39fd, 0x3599,
+           0x32f8);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                               0.64529878
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0x3f25324d);
+  //               0.27794743,  0.64720273,  0.88201439, -0.27750894,
+  //               -0.02381280, -0.27677080, -0.58998328,  0.15329099,
+  //               0.52908343, -0.63265759,  0.48432603,  0.70191479,
+  //               -0.55785930,  0.34719029, -0.06872076, -0.69960916
+  VLOAD_32(v2, 0x3e8e4f20, 0x3f25af14, 0x3f61cbb2, 0xbe8e15a7, 0xbcc31310,
+           0xbe8db4e7, 0xbf170925, 0x3e1cf850, 0x3f077203, 0xbf21f5d9,
+           0x3ef7f995, 0x3f33b0b0, 0xbf0ecfde, 0x3eb1c2ed, 0xbd8cbd78,
+           0xbf331996);
+  asm volatile("vfsgnj.vf v1, v2, %[A]" ::[A] "f"(dscalar_32));
+  //               0.27794743,  0.64720273,  0.88201439,  0.27750894,
+  //               0.02381280,  0.27677080,  0.58998328,  0.15329099,
+  //               0.52908343,  0.63265759,  0.48432603,  0.70191479,
+  //               0.55785930,  0.34719029,  0.06872076,  0.69960916
+  VCMP_U32(8, v1, 0x3e8e4f20, 0x3f25af14, 0x3f61cbb2, 0x3e8e15a7, 0x3cc31310,
+           0x3e8db4e7, 0x3f170925, 0x3e1cf850, 0x3f077203, 0x3f21f5d9,
+           0x3ef7f995, 0x3f33b0b0, 0x3f0ecfde, 0x3eb1c2ed, 0x3d8cbd78,
+           0x3f331996);
+
+  VSET(16, e64, m1);
+  double dscalar_64;
+  //                                0.4863995754678485
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0x3fdf212baf5b0d68);
+  //                0.4577518787562838, -0.0989909265811582,
+  //                -0.5406373582107198, -0.6896639688670565,
+  //                0.9053190721589099, -0.7617679756965072, 0.4649312111760273,
+  //                0.6917063611214438,  0.2205644023843889, 0.1217272698758698,
+  //                -0.3345487709580650,  0.1693366988903542,
+  //                0.4095982059989967,  0.7157757577569959,
+  //                -0.5339346851091937,  0.4946553559543683
+  VLOAD_64(v2, 0x3fdd4bce893c3600, 0xbfb9577828444dc0, 0xbfe14ce6b790591e,
+           0xbfe611ba2bf06f2a, 0x3fecf85fb3ebc33c, 0xbfe860673bd8363e,
+           0x3fddc16ed6b90158, 0x3fe6227560ee74e0, 0x3fcc3b744f738cd0,
+           0x3fbf2984b325f230, 0xbfd5693f3f8ba3fc, 0x3fc5acd32fdf92e8,
+           0x3fda36db64d10584, 0x3fe6e7a28fdabfd2, 0xbfe115fe3157cf38,
+           0x3fdfa86ef0276044);
+  asm volatile("vfsgnj.vf v1, v2, %[A]" ::[A] "f"(dscalar_64));
+  //               0.4577518787562838,  0.0989909265811582,  0.5406373582107198,
+  //               0.6896639688670565,  0.9053190721589099,  0.7617679756965072,
+  //               0.4649312111760273,  0.6917063611214438,  0.2205644023843889,
+  //               0.1217272698758698,  0.3345487709580650,  0.1693366988903542,
+  //               0.4095982059989967,  0.7157757577569959,  0.5339346851091937,
+  //               0.4946553559543683
+  VCMP_U64(9, v1, 0x3fdd4bce893c3600, 0x3fb9577828444dc0, 0x3fe14ce6b790591e,
+           0x3fe611ba2bf06f2a, 0x3fecf85fb3ebc33c, 0x3fe860673bd8363e,
+           0x3fddc16ed6b90158, 0x3fe6227560ee74e0, 0x3fcc3b744f738cd0,
+           0x3fbf2984b325f230, 0x3fd5693f3f8ba3fc, 0x3fc5acd32fdf92e8,
+           0x3fda36db64d10584, 0x3fe6e7a28fdabfd2, 0x3fe115fe3157cf38,
+           0x3fdfa86ef0276044);
+};
+
+// Simple random test with similar values (vector-scalar) (masked)
+void TEST_CASE4(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //                              0.9023
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0x3b38);
+  //                0.5586,  0.0221,  0.7397,  0.9844, -0.1426,  0.6958, 0.0319,
+  //                0.3943, -0.5425,  0.9814,  0.7852, -0.7271, -0.1810,
+  //                -0.7485, -0.3499, -0.2178
+  VLOAD_16(v2, 0x3878, 0x25a7, 0x39eb, 0x3be0, 0xb090, 0x3991, 0x2816, 0x364f,
+           0xb857, 0x3bda, 0x3a48, 0xb9d1, 0xb1cb, 0xb9fd, 0xb599, 0xb2f8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfsgnj.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_16));
+  //                0.0000,  0.0221,  0.0000,  0.9844,  0.0000,  0.6958, 0.0000,
+  //                0.3943,  0.0000,  0.9814,  0.0000,  0.7271,  0.0000, 0.7485,
+  //                0.0000,  0.2178
+  VCMP_U16(10, v1, 0x0, 0x25a7, 0x0, 0x3be0, 0x0, 0x3991, 0x0, 0x364f, 0x0,
+           0x3bda, 0x0, 0x39d1, 0x0, 0x39fd, 0x0, 0x32f8);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                               0.64529878
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0x3f25324d);
+  //                0.27794743,  0.64720273,  0.88201439, -0.27750894,
+  //                -0.02381280, -0.27677080, -0.58998328,  0.15329099,
+  //                0.52908343, -0.63265759,  0.48432603,  0.70191479,
+  //                -0.55785930,  0.34719029, -0.06872076, -0.69960916
+  VLOAD_32(v2, 0x3e8e4f20, 0x3f25af14, 0x3f61cbb2, 0xbe8e15a7, 0xbcc31310,
+           0xbe8db4e7, 0xbf170925, 0x3e1cf850, 0x3f077203, 0xbf21f5d9,
+           0x3ef7f995, 0x3f33b0b0, 0xbf0ecfde, 0x3eb1c2ed, 0xbd8cbd78,
+           0xbf331996);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfsgnj.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_32));
+  //                0.00000000,  0.64720273,  0.00000000,  0.27750894,
+  //                0.00000000,  0.27677080,  0.00000000,  0.15329099,
+  //                0.00000000,  0.63265759,  0.00000000,  0.70191479,
+  //                0.00000000,  0.34719029,  0.00000000,  0.69960916
+  VCMP_U32(11, v1, 0x0, 0x3f25af14, 0x0, 0x3e8e15a7, 0x0, 0x3e8db4e7, 0x0,
+           0x3e1cf850, 0x0, 0x3f21f5d9, 0x0, 0x3f33b0b0, 0x0, 0x3eb1c2ed, 0x0,
+           0x3f331996);
+
+  VSET(16, e64, m1);
+  double dscalar_64;
+  //                                0.4863995754678485
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0x3fdf212baf5b0d68);
+  //                 0.4577518787562838, -0.0989909265811582,
+  //                 -0.5406373582107198, -0.6896639688670565,
+  //                 0.9053190721589099, -0.7617679756965072,
+  //                 0.4649312111760273,  0.6917063611214438,
+  //                 0.2205644023843889,  0.1217272698758698,
+  //                 -0.3345487709580650,  0.1693366988903542,
+  //                 0.4095982059989967,  0.7157757577569959,
+  //                 -0.5339346851091937,  0.4946553559543683
+  VLOAD_64(v2, 0x3fdd4bce893c3600, 0xbfb9577828444dc0, 0xbfe14ce6b790591e,
+           0xbfe611ba2bf06f2a, 0x3fecf85fb3ebc33c, 0xbfe860673bd8363e,
+           0x3fddc16ed6b90158, 0x3fe6227560ee74e0, 0x3fcc3b744f738cd0,
+           0x3fbf2984b325f230, 0xbfd5693f3f8ba3fc, 0x3fc5acd32fdf92e8,
+           0x3fda36db64d10584, 0x3fe6e7a28fdabfd2, 0xbfe115fe3157cf38,
+           0x3fdfa86ef0276044);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfsgnj.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_64));
+  //                0.0000000000000000,  0.0989909265811582, 0.0000000000000000,
+  //                0.6896639688670565,  0.0000000000000000, 0.7617679756965072,
+  //                0.0000000000000000,  0.6917063611214438, 0.0000000000000000,
+  //                0.1217272698758698,  0.0000000000000000, 0.1693366988903542,
+  //                0.0000000000000000,  0.7157757577569959, 0.0000000000000000,
+  //                0.4946553559543683
+  VCMP_U64(12, v1, 0x0, 0x3fb9577828444dc0, 0x0, 0x3fe611ba2bf06f2a, 0x0,
+           0x3fe860673bd8363e, 0x0, 0x3fe6227560ee74e0, 0x0, 0x3fbf2984b325f230,
+           0x0, 0x3fc5acd32fdf92e8, 0x0, 0x3fe6e7a28fdabfd2, 0x0,
+           0x3fdfa86ef0276044);
+};
+
+// The sign injection should work with NaNs and special values, and should not
+// raise any exceptions
+void TEST_CASE5(void) {
+  CLEAR_FFLAGS;
+  VSET(16, e16, m1);
+  CHECK_FFLAGS(0);
+  VLOAD_16(v2, 0x0000, 0x3b3c, 0xb75c, 0x7fff, 0x371e, 0x3b0b, 0x30ca, 0x39d4,
+           0x3bf1, 0x3bf0, 0x0000, 0x3af0, 0xb1f4, 0x3b78, 0xb4bc, 0x3bbc);
+  VLOAD_16(v3, 0x8000, 0xffff, 0xffff, 0xb9e8, 0xb9bc, 0x7fff, 0xb11c, 0x31de,
+           0x1c8f, 0xb2e3, 0x7fff, 0xb988, 0x3198, 0xbae2, 0x38de, 0x3117);
+  asm volatile("vfsgnj.vv v1, v2, v3");
+  VCMP_U16(13, v1, 0x8000, 0xbb3c, 0xb75c, 0xffff, 0xb71e, 0x3b0b, 0xb0ca,
+           0x39d4, 0x3bf1, 0xbbf0, 0x0000, 0xbaf0, 0x31f4, 0xbb78, 0x34bc,
+           0x3bbc);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x00000000, 0x3d816610, 0xbf536e2f, 0xbe369229, 0x3ee857e1,
+           0x7fffffff, 0x80000000, 0xbea51fdd, 0x3eb544da, 0xbf0d0267,
+           0x3dbae08b, 0xbe07ba22, 0x3f7536a6, 0x3f743637, 0x3e4badf5,
+           0x3f45027b);
+  VLOAD_32(v3, 0x80000000, 0x7fffffff, 0x3e1626ca, 0xffffffff, 0xbefbc255,
+           0x7fffffff, 0xffffffff, 0xbeaff818, 0x3eada805, 0x3d96fc66,
+           0x3f3393e1, 0x3f5443aa, 0xbe15516c, 0xbe4c8a7b, 0xbf169fd9,
+           0x3f753c15);
+  asm volatile("vfsgnj.vv v1, v2, v3");
+  VCMP_U32(14, v1, 0x80000000, 0x3d816610, 0x3f536e2f, 0xbe369229, 0xbee857e1,
+           0x7fffffff, 0x80000000, 0xbea51fdd, 0x3eb544da, 0x3f0d0267,
+           0x3dbae08b, 0x3e07ba22, 0xbf7536a6, 0xbf743637, 0xbe4badf5,
+           0x3f45027b);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x0000000000000000, 0xbfee59fbc778ffbc, 0x7fffffffffffffff,
+           0x3fde20419edcb428, 0x8000000000000000, 0x3fa8ecd6c20a0480,
+           0xbfc851dfd0fdf7f8, 0xbfc784eb3b54e580, 0x3fd13e05a2db6b68,
+           0xbfe9790bf1eadde4, 0x3fe46b59155986dc, 0x3fcc266386bc2e10,
+           0x3fdb01fdd39a7d9c, 0xbfe4eef55bb6b208, 0x3fe736d06902107a,
+           0x3fcf3a7f44aa9f48);
+  VLOAD_64(v3, 0x8000000000000000, 0x7fffffffffffffff, 0xbfe187df69e0bb9c,
+           0xbfe76fd3c4a3b1e8, 0x0000000000000001, 0xbfe7c6f7c1644c86,
+           0xbfe229ce53357d20, 0xbfe79fcc34ac1d30, 0xbfe962e04d917824,
+           0xbfb0aa5656314cf0, 0xbfc69c8ad7d5ef20, 0xbfddd9380f0bd244,
+           0xbfc408f2f3d40a40, 0xbfb01baf416f2160, 0xbfed13d1838e183a,
+           0xbfbee005420412c0);
+  asm volatile("vfsgnj.vv v1, v2, v3");
+  VCMP_U64(15, v1, 0x8000000000000000, 0x3fee59fbc778ffbc, 0xffffffffffffffff,
+           0xbfde20419edcb428, 0x0000000000000000, 0xbfa8ecd6c20a0480,
+           0xbfc851dfd0fdf7f8, 0xbfc784eb3b54e580, 0xbfd13e05a2db6b68,
+           0xbfe9790bf1eadde4, 0xbfe46b59155986dc, 0xbfcc266386bc2e10,
+           0xbfdb01fdd39a7d9c, 0xbfe4eef55bb6b208, 0xbfe736d06902107a,
+           0xbfcf3a7f44aa9f48);
+  CHECK_FFLAGS(0);
+};
+
+int main(void) {
+  enable_vec();
+  enable_fp();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  TEST_CASE5();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vfsgnjn.c b/apps/riscv-tests/isa/rv64uv/vfsgnjn.c
new file mode 100644
index 0000000..6312e72
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vfsgnjn.c
@@ -0,0 +1,350 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+// Simple random test with similar values
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  //               0.5278, -0.6548,  0.2776,  0.8730,  0.2180,  0.6172, -0.8408,
+  //               0.9922,  0.4250,  0.7393,  0.2549,  0.4998,  0.4609, -0.6348,
+  //               0.1127, -0.1804
+  VLOAD_16(v2, 0x3839, 0xb93d, 0x3471, 0x3afc, 0x32fa, 0x38f0, 0xbaba, 0x3bf0,
+           0x36cd, 0x39ea, 0x3414, 0x37ff, 0x3760, 0xb914, 0x2f36, 0xb1c6);
+  //              -0.6348, -0.4368, -0.1896,  0.9419, -0.6108, -0.3594, -0.5166,
+  //              -0.1266, -0.9233,  0.2368,  0.1243,  0.3745,  0.0945, -0.3088,
+  //              0.0190, -0.6289
+  VLOAD_16(v3, 0xb914, 0xb6fd, 0xb211, 0x3b89, 0xb8e3, 0xb5c0, 0xb822, 0xb00d,
+           0xbb63, 0x3394, 0x2ff5, 0x35fe, 0x2e0c, 0xb4f1, 0x24da, 0xb908);
+  asm volatile("vfsgnjn.vv v1, v2, v3");
+  //               0.5278,  0.6548,  0.2776, -0.8730,  0.2180,  0.6172,  0.8408,
+  //               0.9922,  0.4250, -0.7393, -0.2549, -0.4998, -0.4609,  0.6348,
+  //               -0.1127,  0.1804
+  VCMP_U16(1, v1, 0x3839, 0x393d, 0x3471, 0xbafc, 0x32fa, 0x38f0, 0x3aba,
+           0x3bf0, 0x36cd, 0xb9ea, 0xb414, 0xb7ff, 0xb760, 0x3914, 0xaf36,
+           0x31c6);
+
+  VSET(16, e32, m1);
+  //              -0.64186704,  0.87601262, -0.93132722,  0.53574133,
+  //              0.17954259, -0.80486834, -0.95272040, -0.45182621, 0.20335940,
+  //              0.96179944,  0.80393785,  0.06180594,  0.86447370,
+  //              -0.24008171, -0.42264909, -0.01868468
+  VLOAD_32(v2, 0xbf245166, 0x3f60425d, 0xbf6e6b76, 0x3f092658, 0x3e37da03,
+           0xbf4e0bda, 0xbf73e57c, 0xbee755c4, 0x3e503d72, 0x3f76387d,
+           0x3f4dcedf, 0x3d7d283b, 0x3f5d4e26, 0xbe75d7fb, 0xbed86576,
+           0xbc99109c);
+  //               0.32984266, -0.78281105,  0.73037797,  0.99060333,
+  //               0.44768164,  0.66998041,  0.39474848, -0.39895460,
+  //               -0.06065369,  0.53388232, -0.60164928, -0.09839682,
+  //               -0.38704434,  0.47123700,  0.40912241, -0.54495376
+  VLOAD_32(v3, 0x3ea8e123, 0xbf48664e, 0x3f3afa0d, 0x3f7d982e, 0x3ee53687,
+           0x3f2b83d6, 0x3eca1c79, 0xbecc43c7, 0xbd787002, 0x3f08ac83,
+           0xbf1a05b0, 0xbdc98446, 0xbec62aad, 0x3ef145fa, 0x3ed1787e,
+           0xbf0b8217);
+  asm volatile("vfsgnjn.vv v1, v2, v3");
+  //              -0.64186704,  0.87601262, -0.93132722, -0.53574133,
+  //              -0.17954259, -0.80486834, -0.95272040,  0.45182621,
+  //              0.20335940, -0.96179944,  0.80393785,  0.06180594, 0.86447370,
+  //              -0.24008171, -0.42264909,  0.01868468
+  VCMP_U32(2, v1, 0xbf245166, 0x3f60425d, 0xbf6e6b76, 0xbf092658, 0xbe37da03,
+           0xbf4e0bda, 0xbf73e57c, 0x3ee755c4, 0x3e503d72, 0xbf76387d,
+           0x3f4dcedf, 0x3d7d283b, 0x3f5d4e26, 0xbe75d7fb, 0xbed86576,
+           0x3c99109c);
+
+  VSET(16, e64, m1);
+  //               0.3054868811191440, -0.2848737407493320,  0.8796894022735833,
+  //               -0.2053728688878902, -0.3336030943630310, 0.2807217618714037,
+  //               0.4723331455917303, -0.8582398814993568,  0.8015611350975347,
+  //               0.0545934239457773,  0.8461592442963186,  0.5731810427237676,
+  //               0.9004228762726765, -0.5815114412549589, -0.4481603571708770,
+  //               -0.3109452697316515
+  VLOAD_64(v2, 0x3fd38d18d8f0e180, 0xbfd23b5f12007bec, 0x3fec266a63ace3f8,
+           0xbfca49a87dadf9c0, 0xbfd559c0cb088d3c, 0x3fd1f75868a0d7ec,
+           0x3fde3ab4cd4887cc, 0xbfeb76b37be53474, 0x3fe9a663899fa232,
+           0x3fabf3ab54d8f940, 0x3feb13bc8d2ebe92, 0x3fe2577fc525f1c0,
+           0x3fecd043a2c52a30, 0xbfe29bbde1ce1372, 0xbfdcaea8c75a67f8,
+           0xbfd3e686fd15f950);
+  //              -0.8601583185162320, -0.2023208019417544,  0.7046992650654684,
+  //              0.0669209072111863, -0.9495814052980500,  0.4501419112888980,
+  //              0.1528430256162707, -0.2750771515266404, -0.5539880061109905,
+  //              -0.7302340801247744,  0.1579280396497211, -0.6128023516491234,
+  //              0.2706272563647967, -0.7982929669593624, -0.2521632643799878,
+  //              0.9025785865542095
+  VLOAD_64(v3, 0xbfeb866abced1b2e, 0xbfc9e5a5e5d1f648, 0x3fe68ce5791f15e4,
+           0x3fb121ba83e404a0, 0xbfee62f88b14a294, 0x3fdccf2004e2dd30,
+           0x3fc3905c3a38c700, 0xbfd19add326bc2ac, 0xbfe1ba450e13ef3a,
+           0xbfe75e13dc91f006, 0x3fc436fc6ab55e68, 0xbfe39c13ad67d608,
+           0x3fd151f4fbdf8d78, 0xbfe98b9db136f3e0, 0xbfd023716370f004,
+           0x3fece1ec7cea3f5e);
+  asm volatile("vfsgnjn.vv v1, v2, v3");
+  //               0.3054868811191440,  0.2848737407493320, -0.8796894022735833,
+  //               -0.2053728688878902,  0.3336030943630310,
+  //               -0.2807217618714037, -0.4723331455917303, 0.8582398814993568,
+  //               0.8015611350975347,  0.0545934239457773, -0.8461592442963186,
+  //               0.5731810427237676, -0.9004228762726765,  0.5815114412549589,
+  //               0.4481603571708770, -0.3109452697316515
+  VCMP_U64(3, v1, 0x3fd38d18d8f0e180, 0x3fd23b5f12007bec, 0xbfec266a63ace3f8,
+           0xbfca49a87dadf9c0, 0x3fd559c0cb088d3c, 0xbfd1f75868a0d7ec,
+           0xbfde3ab4cd4887cc, 0x3feb76b37be53474, 0x3fe9a663899fa232,
+           0x3fabf3ab54d8f940, 0xbfeb13bc8d2ebe92, 0x3fe2577fc525f1c0,
+           0xbfecd043a2c52a30, 0x3fe29bbde1ce1372, 0x3fdcaea8c75a67f8,
+           0xbfd3e686fd15f950);
+};
+
+// Simple random test with similar values (masked)
+// The numbers are the same of TEST_CASE1
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  //               0.5278, -0.6548,  0.2776,  0.8730,  0.2180,  0.6172, -0.8408,
+  //               0.9922,  0.4250,  0.7393,  0.2549,  0.4998,  0.4609, -0.6348,
+  //               0.1127, -0.1804
+  VLOAD_16(v2, 0x3839, 0xb93d, 0x3471, 0x3afc, 0x32fa, 0x38f0, 0xbaba, 0x3bf0,
+           0x36cd, 0x39ea, 0x3414, 0x37ff, 0x3760, 0xb914, 0x2f36, 0xb1c6);
+  //              -0.6348, -0.4368, -0.1896,  0.9419, -0.6108, -0.3594, -0.5166,
+  //              -0.1266, -0.9233,  0.2368,  0.1243,  0.3745,  0.0945, -0.3088,
+  //              0.0190, -0.6289
+  VLOAD_16(v3, 0xb914, 0xb6fd, 0xb211, 0x3b89, 0xb8e3, 0xb5c0, 0xb822, 0xb00d,
+           0xbb63, 0x3394, 0x2ff5, 0x35fe, 0x2e0c, 0xb4f1, 0x24da, 0xb908);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfsgnjn.vv v1, v2, v3, v0.t");
+  //               0.0000,  0.6548,  0.0000, -0.8730,  0.0000,  0.6172,  0.0000,
+  //               0.9922,  0.0000, -0.7393,  0.0000, -0.4998,  0.0000,  0.6348,
+  //               0.0000,  0.1804
+  VCMP_U16(4, v1, 0x0, 0x393d, 0x0, 0xbafc, 0x0, 0x38f0, 0x0, 0x3bf0, 0x0,
+           0xb9ea, 0x0, 0xb7ff, 0x0, 0x3914, 0x0, 0x31c6);
+
+  VSET(16, e32, m1);
+  //              -0.64186704,  0.87601262, -0.93132722,  0.53574133,
+  //              0.17954259, -0.80486834, -0.95272040, -0.45182621, 0.20335940,
+  //              0.96179944,  0.80393785,  0.06180594,  0.86447370,
+  //              -0.24008171, -0.42264909, -0.01868468
+  VLOAD_32(v2, 0xbf245166, 0x3f60425d, 0xbf6e6b76, 0x3f092658, 0x3e37da03,
+           0xbf4e0bda, 0xbf73e57c, 0xbee755c4, 0x3e503d72, 0x3f76387d,
+           0x3f4dcedf, 0x3d7d283b, 0x3f5d4e26, 0xbe75d7fb, 0xbed86576,
+           0xbc99109c);
+  //               0.32984266, -0.78281105,  0.73037797,  0.99060333,
+  //               0.44768164,  0.66998041,  0.39474848, -0.39895460,
+  //               -0.06065369,  0.53388232, -0.60164928, -0.09839682,
+  //               -0.38704434,  0.47123700,  0.40912241, -0.54495376
+  VLOAD_32(v3, 0x3ea8e123, 0xbf48664e, 0x3f3afa0d, 0x3f7d982e, 0x3ee53687,
+           0x3f2b83d6, 0x3eca1c79, 0xbecc43c7, 0xbd787002, 0x3f08ac83,
+           0xbf1a05b0, 0xbdc98446, 0xbec62aad, 0x3ef145fa, 0x3ed1787e,
+           0xbf0b8217);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfsgnjn.vv v1, v2, v3, v0.t");
+  //               0.00000000,  0.87601262,  0.00000000, -0.53574133,
+  //               0.00000000, -0.80486834,  0.00000000,  0.45182621,
+  //               0.00000000, -0.96179944,  0.00000000,  0.06180594,
+  //               0.00000000, -0.24008171,  0.00000000,  0.01868468
+  VCMP_U32(5, v1, 0x0, 0x3f60425d, 0x0, 0xbf092658, 0x0, 0xbf4e0bda, 0x0,
+           0x3ee755c4, 0x0, 0xbf76387d, 0x0, 0x3d7d283b, 0x0, 0xbe75d7fb, 0x0,
+           0x3c99109c);
+
+  VSET(16, e64, m1);
+  //               0.3054868811191440, -0.2848737407493320,  0.8796894022735833,
+  //               -0.2053728688878902, -0.3336030943630310, 0.2807217618714037,
+  //               0.4723331455917303, -0.8582398814993568,  0.8015611350975347,
+  //               0.0545934239457773,  0.8461592442963186,  0.5731810427237676,
+  //               0.9004228762726765, -0.5815114412549589, -0.4481603571708770,
+  //               -0.3109452697316515
+  VLOAD_64(v2, 0x3fd38d18d8f0e180, 0xbfd23b5f12007bec, 0x3fec266a63ace3f8,
+           0xbfca49a87dadf9c0, 0xbfd559c0cb088d3c, 0x3fd1f75868a0d7ec,
+           0x3fde3ab4cd4887cc, 0xbfeb76b37be53474, 0x3fe9a663899fa232,
+           0x3fabf3ab54d8f940, 0x3feb13bc8d2ebe92, 0x3fe2577fc525f1c0,
+           0x3fecd043a2c52a30, 0xbfe29bbde1ce1372, 0xbfdcaea8c75a67f8,
+           0xbfd3e686fd15f950);
+  //              -0.8601583185162320, -0.2023208019417544,  0.7046992650654684,
+  //              0.0669209072111863, -0.9495814052980500,  0.4501419112888980,
+  //              0.1528430256162707, -0.2750771515266404, -0.5539880061109905,
+  //              -0.7302340801247744,  0.1579280396497211, -0.6128023516491234,
+  //              0.2706272563647967, -0.7982929669593624, -0.2521632643799878,
+  //              0.9025785865542095
+  VLOAD_64(v3, 0xbfeb866abced1b2e, 0xbfc9e5a5e5d1f648, 0x3fe68ce5791f15e4,
+           0x3fb121ba83e404a0, 0xbfee62f88b14a294, 0x3fdccf2004e2dd30,
+           0x3fc3905c3a38c700, 0xbfd19add326bc2ac, 0xbfe1ba450e13ef3a,
+           0xbfe75e13dc91f006, 0x3fc436fc6ab55e68, 0xbfe39c13ad67d608,
+           0x3fd151f4fbdf8d78, 0xbfe98b9db136f3e0, 0xbfd023716370f004,
+           0x3fece1ec7cea3f5e);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfsgnjn.vv v1, v2, v3, v0.t");
+  //               0.0000000000000000,  0.2848737407493320,  0.0000000000000000,
+  //               -0.2053728688878902,  0.0000000000000000,
+  //               -0.2807217618714037,  0.0000000000000000, 0.8582398814993568,
+  //               0.0000000000000000,  0.0545934239457773,  0.0000000000000000,
+  //               0.5731810427237676,  0.0000000000000000,  0.5815114412549589,
+  //               0.0000000000000000, -0.3109452697316515
+  VCMP_U64(6, v1, 0x0, 0x3fd23b5f12007bec, 0x0, 0xbfca49a87dadf9c0, 0x0,
+           0xbfd1f75868a0d7ec, 0x0, 0x3feb76b37be53474, 0x0, 0x3fabf3ab54d8f940,
+           0x0, 0x3fe2577fc525f1c0, 0x0, 0x3fe29bbde1ce1372, 0x0,
+           0xbfd3e686fd15f950);
+};
+
+// Simple random test with similar values (vector-scalar)
+void TEST_CASE3(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //                             -0.6143
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0xb8ea);
+  //              -0.9351,  0.6538, -0.6743, -0.4695, -0.1439,  0.6250, -0.1511,
+  //              -0.7476,  0.8496,  0.6279,  0.5234,  0.2610,  0.6299, -0.0123,
+  //              -0.9995, -0.3872
+  VLOAD_16(v2, 0xbb7b, 0x393b, 0xb965, 0xb783, 0xb09b, 0x3900, 0xb0d6, 0xb9fb,
+           0x3acc, 0x3906, 0x3830, 0x342d, 0x390a, 0xa24d, 0xbbff, 0xb632);
+  asm volatile("vfsgnjn.vf v1, v2, %[A]" ::[A] "f"(dscalar_16));
+  //               0.9351,  0.6538,  0.6743,  0.4695,  0.1439,  0.6250,  0.1511,
+  //               0.7476,  0.8496,  0.6279,  0.5234,  0.2610,  0.6299,  0.0123,
+  //               0.9995,  0.3872
+  VCMP_U16(7, v1, 0x3b7b, 0x393b, 0x3965, 0x3783, 0x309b, 0x3900, 0x30d6,
+           0x39fb, 0x3acc, 0x3906, 0x3830, 0x342d, 0x390a, 0x224d, 0x3bff,
+           0x3632);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                               0.56259364
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0x3f100623);
+  //              -0.00813205, -0.38676089,  0.94379848,  0.39548567,
+  //              0.90217608,  0.57424510,  0.05995686, -0.00974263,
+  //              -0.45620662, -0.36967716, -0.56535333, -0.93745488,
+  //              -0.55570704,  0.04399948, -0.57520008, -0.05702910
+  VLOAD_32(v2, 0xbc053c4a, 0xbec60586, 0x3f719cc7, 0x3eca7d19, 0x3f66f503,
+           0x3f1301ba, 0x3d759554, 0xbc1f9f8d, 0xbee993ea, 0xbebd4653,
+           0xbf10baff, 0xbf6ffd0b, 0xbf0e42d1, 0x3d3438cd, 0xbf134050,
+           0xbd699758);
+  asm volatile("vfsgnjn.vf v1, v2, %[A]" ::[A] "f"(dscalar_32));
+  //              -0.00813205, -0.38676089, -0.94379848, -0.39548567,
+  //              -0.90217608, -0.57424510, -0.05995686, -0.00974263,
+  //              -0.45620662, -0.36967716, -0.56535333, -0.93745488,
+  //              -0.55570704, -0.04399948, -0.57520008, -0.05702910
+  VCMP_U32(8, v1, 0xbc053c4a, 0xbec60586, 0xbf719cc7, 0xbeca7d19, 0xbf66f503,
+           0xbf1301ba, 0xbd759554, 0xbc1f9f8d, 0xbee993ea, 0xbebd4653,
+           0xbf10baff, 0xbf6ffd0b, 0xbf0e42d1, 0xbd3438cd, 0xbf134050,
+           0xbd699758);
+
+  VSET(16, e64, m1);
+  double dscalar_64;
+  //                                0.1909501680714165
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0x3fc8710e1b8426e8);
+  //               -0.2692390874696449, -0.3268380231167121, 0.8386824891028197,
+  //               -0.5650452268361481, -0.6389787807266418, 0.5318945600667211,
+  //               -0.7817543128402196, -0.5679136293897145,
+  //               -0.0001555883762874,  0.5283267089670276, 0.5439688283816015,
+  //               -0.2866314604291811, -0.0576946087921848, 0.7960283598249005,
+  //               -0.8999056473475127,  0.2142070697411482
+  VLOAD_64(v2, 0xbfd13b3694df2b24, 0xbfd4eaea07180958, 0x3fead67ca8cd9566,
+           0xbfe214d9ba40b584, 0xbfe47283a0c1e25c, 0x3fe10547bd8d051e,
+           0xbfe904219ee4fb76, 0xbfe22c593425cec0, 0xbf2464adf9bfe000,
+           0x3fe0e80d6a13bbf4, 0x3fe1683150fe2844, 0xbfd2582b7b231344,
+           0xbfad8a25d3d5fd40, 0x3fe9791077845df2, 0xbfeccc06ed9afc1e,
+           0x3fcb6b23238e1bc8);
+  asm volatile("vfsgnjn.vf v1, v2, %[A]" ::[A] "f"(dscalar_64));
+  //              -0.2692390874696449, -0.3268380231167121, -0.8386824891028197,
+  //              -0.5650452268361481, -0.6389787807266418, -0.5318945600667211,
+  //              -0.7817543128402196, -0.5679136293897145, -0.0001555883762874,
+  //              -0.5283267089670276, -0.5439688283816015, -0.2866314604291811,
+  //              -0.0576946087921848, -0.7960283598249005, -0.8999056473475127,
+  //              -0.2142070697411482
+  VCMP_U64(9, v1, 0xbfd13b3694df2b24, 0xbfd4eaea07180958, 0xbfead67ca8cd9566,
+           0xbfe214d9ba40b584, 0xbfe47283a0c1e25c, 0xbfe10547bd8d051e,
+           0xbfe904219ee4fb76, 0xbfe22c593425cec0, 0xbf2464adf9bfe000,
+           0xbfe0e80d6a13bbf4, 0xbfe1683150fe2844, 0xbfd2582b7b231344,
+           0xbfad8a25d3d5fd40, 0xbfe9791077845df2, 0xbfeccc06ed9afc1e,
+           0xbfcb6b23238e1bc8);
+};
+
+// Simple random test with similar values (vector-scalar) (masked)
+void TEST_CASE4(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //                             -0.6143
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0xb8ea);
+  //               -0.9351,  0.6538, -0.6743, -0.4695, -0.1439,  0.6250,
+  //               -0.1511, -0.7476,  0.8496,  0.6279,  0.5234,  0.2610, 0.6299,
+  //               -0.0123, -0.9995, -0.3872
+  VLOAD_16(v2, 0xbb7b, 0x393b, 0xb965, 0xb783, 0xb09b, 0x3900, 0xb0d6, 0xb9fb,
+           0x3acc, 0x3906, 0x3830, 0x342d, 0x390a, 0xa24d, 0xbbff, 0xb632);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfsgnjn.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_16));
+  //                0.0000,  0.6538,  0.0000,  0.4695,  0.0000,  0.6250, 0.0000,
+  //                0.7476,  0.0000,  0.6279,  0.0000,  0.2610,  0.0000, 0.0123,
+  //                0.0000,  0.3872
+  VCMP_U16(10, v1, 0x0, 0x393b, 0x0, 0x3783, 0x0, 0x3900, 0x0, 0x39fb, 0x0,
+           0x3906, 0x0, 0x342d, 0x0, 0x224d, 0x0, 0x3632);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                               0.56259364
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0x3f100623);
+  //               -0.00813205, -0.38676089,  0.94379848,  0.39548567,
+  //               0.90217608,  0.57424510,  0.05995686, -0.00974263,
+  //               -0.45620662, -0.36967716, -0.56535333, -0.93745488,
+  //               -0.55570704,  0.04399948, -0.57520008, -0.05702910
+  VLOAD_32(v2, 0xbc053c4a, 0xbec60586, 0x3f719cc7, 0x3eca7d19, 0x3f66f503,
+           0x3f1301ba, 0x3d759554, 0xbc1f9f8d, 0xbee993ea, 0xbebd4653,
+           0xbf10baff, 0xbf6ffd0b, 0xbf0e42d1, 0x3d3438cd, 0xbf134050,
+           0xbd699758);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfsgnjn.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_32));
+  //                0.00000000, -0.38676089,  0.00000000, -0.39548567,
+  //                0.00000000, -0.57424510,  0.00000000, -0.00974263,
+  //                0.00000000, -0.36967716,  0.00000000, -0.93745488,
+  //                0.00000000, -0.04399948,  0.00000000, -0.05702910
+  VCMP_U32(11, v1, 0x0, 0xbec60586, 0x0, 0xbeca7d19, 0x0, 0xbf1301ba, 0x0,
+           0xbc1f9f8d, 0x0, 0xbebd4653, 0x0, 0xbf6ffd0b, 0x0, 0xbd3438cd, 0x0,
+           0xbd699758);
+
+  VSET(16, e64, m1);
+  double dscalar_64;
+  //                                0.1909501680714165
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0x3fc8710e1b8426e8);
+  //                -0.2692390874696449, -0.3268380231167121,
+  //                0.8386824891028197, -0.5650452268361481,
+  //                -0.6389787807266418,  0.5318945600667211,
+  //                -0.7817543128402196, -0.5679136293897145,
+  //                -0.0001555883762874,  0.5283267089670276,
+  //                0.5439688283816015, -0.2866314604291811,
+  //                -0.0576946087921848,  0.7960283598249005,
+  //                -0.8999056473475127,  0.2142070697411482
+  VLOAD_64(v2, 0xbfd13b3694df2b24, 0xbfd4eaea07180958, 0x3fead67ca8cd9566,
+           0xbfe214d9ba40b584, 0xbfe47283a0c1e25c, 0x3fe10547bd8d051e,
+           0xbfe904219ee4fb76, 0xbfe22c593425cec0, 0xbf2464adf9bfe000,
+           0x3fe0e80d6a13bbf4, 0x3fe1683150fe2844, 0xbfd2582b7b231344,
+           0xbfad8a25d3d5fd40, 0x3fe9791077845df2, 0xbfeccc06ed9afc1e,
+           0x3fcb6b23238e1bc8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfsgnjn.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_64));
+  //                0.0000000000000000, -0.3268380231167121, 0.0000000000000000,
+  //                -0.5650452268361481,  0.0000000000000000,
+  //                -0.5318945600667211,  0.0000000000000000,
+  //                -0.5679136293897145,  0.0000000000000000,
+  //                -0.5283267089670276,  0.0000000000000000,
+  //                -0.2866314604291811,  0.0000000000000000,
+  //                -0.7960283598249005,  0.0000000000000000,
+  //                -0.2142070697411482
+  VCMP_U64(12, v1, 0x0, 0xbfd4eaea07180958, 0x0, 0xbfe214d9ba40b584, 0x0,
+           0xbfe10547bd8d051e, 0x0, 0xbfe22c593425cec0, 0x0, 0xbfe0e80d6a13bbf4,
+           0x0, 0xbfd2582b7b231344, 0x0, 0xbfe9791077845df2, 0x0,
+           0xbfcb6b23238e1bc8);
+};
+
+int main(void) {
+  enable_vec();
+  enable_fp();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vfsgnjx.c b/apps/riscv-tests/isa/rv64uv/vfsgnjx.c
new file mode 100644
index 0000000..8e9c4d8
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vfsgnjx.c
@@ -0,0 +1,348 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+// Simple random test with similar values
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  //              -0.0371,  0.8374,  0.7183,  0.8086, -0.8940,  0.4626,  0.5449,
+  //              0.6831,  0.4661,  0.2981,  0.5615, -0.6167, -0.7075, -0.7603,
+  //              0.8438, -0.2742
+  VLOAD_16(v2, 0xa8c1, 0x3ab3, 0x39bf, 0x3a78, 0xbb27, 0x3767, 0x385c, 0x3977,
+           0x3775, 0x34c5, 0x387e, 0xb8ef, 0xb9a9, 0xba15, 0x3ac0, 0xb463);
+  //               0.3516,  0.7925, -0.5034, -0.1672,  0.0703, -0.9731,  0.0361,
+  //               -0.4077,  0.8965,  0.8242, -0.7822,  0.0265, -0.5361, 0.1226,
+  //               -0.9917,  0.5415
+  VLOAD_16(v3, 0x35a0, 0x3a57, 0xb807, 0xb15a, 0x2c7f, 0xbbc9, 0x289f, 0xb686,
+           0x3b2c, 0x3a98, 0xba42, 0x26cb, 0xb84a, 0x2fd8, 0xbbef, 0x3855);
+  asm volatile("vfsgnjx.vv v1, v2, v3");
+  //              -0.0371,  0.8374, -0.7183, -0.8086, -0.8940, -0.4626,  0.5449,
+  //              -0.6831,  0.4661,  0.2981, -0.5615, -0.6167,  0.7075, -0.7603,
+  //              -0.8438, -0.2742
+  VCMP_U16(1, v1, 0xa8c1, 0x3ab3, 0xb9bf, 0xba78, 0xbb27, 0xb767, 0x385c,
+           0xb977, 0x3775, 0x34c5, 0xb87e, 0xb8ef, 0x39a9, 0xba15, 0xbac0,
+           0xb463);
+
+  VSET(16, e32, m1);
+  //              -0.00918692, -0.23372029,  0.42919466,  0.95128548,
+  //              0.05014091,  0.08194520,  0.65458435,  0.38167605,
+  //              -0.52784044,  0.46330592,  0.66792834,  0.94584799,
+  //              -0.11679628,  0.12139154,  0.61421394, -0.71422517
+  VLOAD_32(v2, 0xbc1684ba, 0xbe6f545f, 0x3edbbf67, 0x3f738772, 0x3d4d608d,
+           0x3da7d2e2, 0x3f2792d7, 0x3ec36b0b, 0xbf07208d, 0x3eed366f,
+           0x3f2afd5a, 0x3f722318, 0xbdef32e4, 0x3df89c21, 0x3f1d3d20,
+           0xbf36d776);
+  //              -0.96525091, -0.82903022, -0.98528612,  0.36915505,
+  //              0.23285799,  0.19133335,  0.78484982, -0.40654737,
+  //              -0.40144378, -0.94419461,  0.60990387, -0.37662670,
+  //              0.75369638, -0.82297397,  0.24545205, -0.75572032
+  VLOAD_32(v3, 0xbf771aaf, 0xbf543b53, 0xbf7c3bb6, 0x3ebd01e4, 0x3e6e7253,
+           0x3e43ece4, 0x3f48ebeb, 0xbed026fa, 0xbecd8a0a, 0xbf71b6bd,
+           0x3f1c22a9, 0xbec0d537, 0x3f40f23f, 0xbf52ae6c, 0x3e7b57c8,
+           0xbf4176e3);
+  asm volatile("vfsgnjx.vv v1, v2, v3");
+  //               0.00918692,  0.23372029, -0.42919466,  0.95128548,
+  //               0.05014091,  0.08194520,  0.65458435, -0.38167605,
+  //               0.52784044, -0.46330592,  0.66792834, -0.94584799,
+  //               -0.11679628, -0.12139154,  0.61421394,  0.71422517
+  VCMP_U32(2, v1, 0x3c1684ba, 0x3e6f545f, 0xbedbbf67, 0x3f738772, 0x3d4d608d,
+           0x3da7d2e2, 0x3f2792d7, 0xbec36b0b, 0x3f07208d, 0xbeed366f,
+           0x3f2afd5a, 0xbf722318, 0xbdef32e4, 0xbdf89c21, 0x3f1d3d20,
+           0x3f36d776);
+
+  VSET(16, e64, m1);
+  //              -0.4085246287477386,  0.8681744372264055, -0.9782992825101422,
+  //              0.9959576051606904, -0.7910104167136705,  0.0799315061445605,
+  //              0.2562329212571202, -0.0401280831920132, -0.6164331117742006,
+  //              0.0314794700215042, -0.2391312835511448,  0.2944948324466776,
+  //              -0.3469257666022745,  0.3129356083924371,  0.1418123916338592,
+  //              -0.2697778839142546
+  VLOAD_64(v2, 0xbfda25447c0540c8, 0x3febc815c1e38a2c, 0xbfef4e3a4c029a38,
+           0x3fefdee27bcbc3c2, 0xbfe94ff513d293d6, 0x3fb4766424cf97d0,
+           0x3fd0661ec43d4dd0, 0xbfa48bab09ebf660, 0xbfe3b9d1eee7bc0a,
+           0x3fa01e13bc79bd60, 0xbfce9bda9926bde0, 0x3fd2d900da8cc448,
+           0xbfd63408216c936c, 0x3fd4072312f3290c, 0x3fc226e8901e1378,
+           0xbfd1440a752621b8);
+  //              -0.9042358342806300,  0.2953863994960662, -0.4373909703642964,
+  //              0.1464626280814265, -0.5161207396769107, -0.3525096032632213,
+  //              -0.0692332757289065, -0.9900711773455610,  0.6225050177521096,
+  //              -0.1361158534833962,  0.1558021548512183,  0.9766583762298613,
+  //              0.2768845956890595,  0.6672273199701737, -0.4444943981200347,
+  //              0.5095574851608440
+  VLOAD_64(v3, 0xbfecef7ffd03691e, 0x3fd2e79c5b6133f0, 0xbfdbfe36b251f164,
+           0x3fc2bf4992d91480, 0xbfe0840fa43663a0, 0xbfd68f847062a774,
+           0xbfb1b9459f0cf460, 0xbfefaea9bfed2a32, 0x3fe3eb8fa49aeb32,
+           0xbfc16c3e8996d300, 0x3fc3f15333ddbc58, 0x3fef40c91128b1ea,
+           0x3fd1b87a2ad00b5c, 0x3fe559ed1bc8a0c2, 0xbfdc7298a1cb9174,
+           0x3fe04e4b7fc654a0);
+  asm volatile("vfsgnjx.vv v1, v2, v3");
+  //               0.4085246287477386,  0.8681744372264055,  0.9782992825101422,
+  //               0.9959576051606904,  0.7910104167136705, -0.0799315061445605,
+  //               -0.2562329212571202,  0.0401280831920132,
+  //               -0.6164331117742006, -0.0314794700215042,
+  //               -0.2391312835511448,  0.2944948324466776,
+  //               -0.3469257666022745,  0.3129356083924371,
+  //               -0.1418123916338592, -0.2697778839142546
+  VCMP_U64(3, v1, 0x3fda25447c0540c8, 0x3febc815c1e38a2c, 0x3fef4e3a4c029a38,
+           0x3fefdee27bcbc3c2, 0x3fe94ff513d293d6, 0xbfb4766424cf97d0,
+           0xbfd0661ec43d4dd0, 0x3fa48bab09ebf660, 0xbfe3b9d1eee7bc0a,
+           0xbfa01e13bc79bd60, 0xbfce9bda9926bde0, 0x3fd2d900da8cc448,
+           0xbfd63408216c936c, 0x3fd4072312f3290c, 0xbfc226e8901e1378,
+           0xbfd1440a752621b8);
+};
+
+// Simple random test with similar values (masked)
+// The numbers are the same of TEST_CASE1
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  //              -0.0371,  0.8374,  0.7183,  0.8086, -0.8940,  0.4626,  0.5449,
+  //              0.6831,  0.4661,  0.2981,  0.5615, -0.6167, -0.7075, -0.7603,
+  //              0.8438, -0.2742
+  VLOAD_16(v2, 0xa8c1, 0x3ab3, 0x39bf, 0x3a78, 0xbb27, 0x3767, 0x385c, 0x3977,
+           0x3775, 0x34c5, 0x387e, 0xb8ef, 0xb9a9, 0xba15, 0x3ac0, 0xb463);
+  //               0.3516,  0.7925, -0.5034, -0.1672,  0.0703, -0.9731,  0.0361,
+  //               -0.4077,  0.8965,  0.8242, -0.7822,  0.0265, -0.5361, 0.1226,
+  //               -0.9917,  0.5415
+  VLOAD_16(v3, 0x35a0, 0x3a57, 0xb807, 0xb15a, 0x2c7f, 0xbbc9, 0x289f, 0xb686,
+           0x3b2c, 0x3a98, 0xba42, 0x26cb, 0xb84a, 0x2fd8, 0xbbef, 0x3855);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfsgnjx.vv v1, v2, v3, v0.t");
+  //               0.0000,  0.8374,  0.0000, -0.8086,  0.0000, -0.4626,  0.0000,
+  //               -0.6831,  0.0000,  0.2981,  0.0000, -0.6167,  0.0000,
+  //               -0.7603,  0.0000, -0.2742
+  VCMP_U16(4, v1, 0x0, 0x3ab3, 0x0, 0xba78, 0x0, 0xb767, 0x0, 0xb977, 0x0,
+           0x34c5, 0x0, 0xb8ef, 0x0, 0xba15, 0x0, 0xb463);
+
+  VSET(16, e32, m1);
+  //              -0.00918692, -0.23372029,  0.42919466,  0.95128548,
+  //              0.05014091,  0.08194520,  0.65458435,  0.38167605,
+  //              -0.52784044,  0.46330592,  0.66792834,  0.94584799,
+  //              -0.11679628,  0.12139154,  0.61421394, -0.71422517
+  VLOAD_32(v2, 0xbc1684ba, 0xbe6f545f, 0x3edbbf67, 0x3f738772, 0x3d4d608d,
+           0x3da7d2e2, 0x3f2792d7, 0x3ec36b0b, 0xbf07208d, 0x3eed366f,
+           0x3f2afd5a, 0x3f722318, 0xbdef32e4, 0x3df89c21, 0x3f1d3d20,
+           0xbf36d776);
+  //              -0.96525091, -0.82903022, -0.98528612,  0.36915505,
+  //              0.23285799,  0.19133335,  0.78484982, -0.40654737,
+  //              -0.40144378, -0.94419461,  0.60990387, -0.37662670,
+  //              0.75369638, -0.82297397,  0.24545205, -0.75572032
+  VLOAD_32(v3, 0xbf771aaf, 0xbf543b53, 0xbf7c3bb6, 0x3ebd01e4, 0x3e6e7253,
+           0x3e43ece4, 0x3f48ebeb, 0xbed026fa, 0xbecd8a0a, 0xbf71b6bd,
+           0x3f1c22a9, 0xbec0d537, 0x3f40f23f, 0xbf52ae6c, 0x3e7b57c8,
+           0xbf4176e3);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfsgnjx.vv v1, v2, v3, v0.t");
+  //               0.00000000,  0.23372029,  0.00000000,  0.95128548,
+  //               0.00000000,  0.08194520,  0.00000000, -0.38167605,
+  //               0.00000000, -0.46330592,  0.00000000, -0.94584799,
+  //               0.00000000, -0.12139154,  0.00000000,  0.71422517
+  VCMP_U32(5, v1, 0x0, 0x3e6f545f, 0x0, 0x3f738772, 0x0, 0x3da7d2e2, 0x0,
+           0xbec36b0b, 0x0, 0xbeed366f, 0x0, 0xbf722318, 0x0, 0xbdf89c21, 0x0,
+           0x3f36d776);
+
+  VSET(16, e64, m1);
+  //              -0.4085246287477386,  0.8681744372264055, -0.9782992825101422,
+  //              0.9959576051606904, -0.7910104167136705,  0.0799315061445605,
+  //              0.2562329212571202, -0.0401280831920132, -0.6164331117742006,
+  //              0.0314794700215042, -0.2391312835511448,  0.2944948324466776,
+  //              -0.3469257666022745,  0.3129356083924371,  0.1418123916338592,
+  //              -0.2697778839142546
+  VLOAD_64(v2, 0xbfda25447c0540c8, 0x3febc815c1e38a2c, 0xbfef4e3a4c029a38,
+           0x3fefdee27bcbc3c2, 0xbfe94ff513d293d6, 0x3fb4766424cf97d0,
+           0x3fd0661ec43d4dd0, 0xbfa48bab09ebf660, 0xbfe3b9d1eee7bc0a,
+           0x3fa01e13bc79bd60, 0xbfce9bda9926bde0, 0x3fd2d900da8cc448,
+           0xbfd63408216c936c, 0x3fd4072312f3290c, 0x3fc226e8901e1378,
+           0xbfd1440a752621b8);
+  //              -0.9042358342806300,  0.2953863994960662, -0.4373909703642964,
+  //              0.1464626280814265, -0.5161207396769107, -0.3525096032632213,
+  //              -0.0692332757289065, -0.9900711773455610,  0.6225050177521096,
+  //              -0.1361158534833962,  0.1558021548512183,  0.9766583762298613,
+  //              0.2768845956890595,  0.6672273199701737, -0.4444943981200347,
+  //              0.5095574851608440
+  VLOAD_64(v3, 0xbfecef7ffd03691e, 0x3fd2e79c5b6133f0, 0xbfdbfe36b251f164,
+           0x3fc2bf4992d91480, 0xbfe0840fa43663a0, 0xbfd68f847062a774,
+           0xbfb1b9459f0cf460, 0xbfefaea9bfed2a32, 0x3fe3eb8fa49aeb32,
+           0xbfc16c3e8996d300, 0x3fc3f15333ddbc58, 0x3fef40c91128b1ea,
+           0x3fd1b87a2ad00b5c, 0x3fe559ed1bc8a0c2, 0xbfdc7298a1cb9174,
+           0x3fe04e4b7fc654a0);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfsgnjx.vv v1, v2, v3, v0.t");
+  //               0.0000000000000000,  0.8681744372264055,  0.0000000000000000,
+  //               0.9959576051606904,  0.0000000000000000, -0.0799315061445605,
+  //               0.0000000000000000,  0.0401280831920132,  0.0000000000000000,
+  //               -0.0314794700215042,  0.0000000000000000, 0.2944948324466776,
+  //               0.0000000000000000,  0.3129356083924371,  0.0000000000000000,
+  //               -0.2697778839142546
+  VCMP_U64(6, v1, 0x0, 0x3febc815c1e38a2c, 0x0, 0x3fefdee27bcbc3c2, 0x0,
+           0xbfb4766424cf97d0, 0x0, 0x3fa48bab09ebf660, 0x0, 0xbfa01e13bc79bd60,
+           0x0, 0x3fd2d900da8cc448, 0x0, 0x3fd4072312f3290c, 0x0,
+           0xbfd1440a752621b8);
+};
+
+// Simple random test with similar values (vector-scalar)
+void TEST_CASE3(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //                             -0.9766
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0xbbd0);
+  //               0.8535, -0.3750, -0.8066, -0.9097, -0.2216, -0.5645, -0.3149,
+  //               -0.4512,  0.5981,  0.6587,  0.9546, -0.3040, -0.6157, 0.5723,
+  //               0.8438, -0.1544
+  VLOAD_16(v2, 0x3ad4, 0xb600, 0xba74, 0xbb47, 0xb317, 0xb884, 0xb50a, 0xb738,
+           0x38c9, 0x3945, 0x3ba3, 0xb4dd, 0xb8ed, 0x3894, 0x3ac0, 0xb0f1);
+  asm volatile("vfsgnjx.vf v1, v2, %[A]" ::[A] "f"(dscalar_16));
+  //              -0.8535,  0.3750,  0.8066,  0.9097,  0.2216,  0.5645,  0.3149,
+  //              0.4512, -0.5981, -0.6587, -0.9546,  0.3040,  0.6157, -0.5723,
+  //              -0.8438,  0.1544
+  VCMP_U16(7, v1, 0xbad4, 0x3600, 0x3a74, 0x3b47, 0x3317, 0x3884, 0x350a,
+           0x3738, 0xb8c9, 0xb945, 0xbba3, 0x34dd, 0x38ed, 0xb894, 0xbac0,
+           0x30f1);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                              -0.71056527
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0xbf35e79b);
+  //              -0.13350210, -0.18642496,  0.30152589, -0.62076813,
+  //              0.00040700, -0.59566921, -0.88075870,  0.08096603, 0.94059193,
+  //              -0.29601631, -0.54263371, -0.86016685, -0.57158113,
+  //              0.85538357, -0.76839548,  0.28374606
+  VLOAD_32(v2, 0xbe08b4c6, 0xbe3ee62f, 0x3e9a619a, 0xbf1eeaa9, 0x39d561f4,
+           0xbf187dc7, 0xbf617967, 0x3da5d185, 0x3f70caa2, 0xbe978f73,
+           0xbf0aea0b, 0xbf5c33e5, 0xbf125324, 0x3f5afa6b, 0xbf44b591,
+           0x3e91472a);
+  asm volatile("vfsgnjx.vf v1, v2, %[A]" ::[A] "f"(dscalar_32));
+  //               0.13350210,  0.18642496, -0.30152589,  0.62076813,
+  //               -0.00040700,  0.59566921,  0.88075870, -0.08096603,
+  //               -0.94059193,  0.29601631,  0.54263371,  0.86016685,
+  //               0.57158113, -0.85538357,  0.76839548, -0.28374606
+  VCMP_U32(8, v1, 0x3e08b4c6, 0x3e3ee62f, 0xbe9a619a, 0x3f1eeaa9, 0xb9d561f4,
+           0x3f187dc7, 0x3f617967, 0xbda5d185, 0xbf70caa2, 0x3e978f73,
+           0x3f0aea0b, 0x3f5c33e5, 0x3f125324, 0xbf5afa6b, 0x3f44b591,
+           0xbe91472a);
+
+  VSET(16, e64, m1);
+  double dscalar_64;
+  //                               -0.1599292306617626
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0xbfc4788f9faef060);
+  //               -0.3770377828689853,  0.5963307040587882,
+  //               -0.4228346580189990, -0.8395360297727528, 0.2884308755790033,
+  //               -0.9332093226534830, -0.3077793113682024,
+  //               -0.3241690978469995,  0.9848431705043186, 0.5835571766262024,
+  //               0.6934128987139432, -0.8499240402166686,  0.9392758702585176,
+  //               0.8754505566292561, -0.4187493105472220, -0.7967172481248119
+  VLOAD_64(v2, 0xbfd8216314b1d540, 0x3fe3152420f10f90, 0xbfdb0fb918f3a4fc,
+           0xbfeadd7aa9f60146, 0x3fd275a6c6712e84, 0xbfeddcd9cc23cf06,
+           0xbfd3b2a7ff2d8ea0, 0xbfd4bf2fbe681ba4, 0x3fef83d5d32028f6,
+           0x3fe2ac80199e9490, 0x3fe630703f533af4, 0xbfeb3293e69a12ae,
+           0x3fee0e8c4515d52c, 0x3fec03b0e2bf9ad6, 0xbfdaccc9e88176a4,
+           0xbfe97eb52b9b5dac);
+  asm volatile("vfsgnjx.vf v1, v2, %[A]" ::[A] "f"(dscalar_64));
+  //               0.3770377828689853, -0.5963307040587882,  0.4228346580189990,
+  //               0.8395360297727528, -0.2884308755790033,  0.9332093226534830,
+  //               0.3077793113682024,  0.3241690978469995, -0.9848431705043186,
+  //               -0.5835571766262024, -0.6934128987139432, 0.8499240402166686,
+  //               -0.9392758702585176, -0.8754505566292561, 0.4187493105472220,
+  //               0.7967172481248119
+  VCMP_U64(9, v1, 0x3fd8216314b1d540, 0xbfe3152420f10f90, 0x3fdb0fb918f3a4fc,
+           0x3feadd7aa9f60146, 0xbfd275a6c6712e84, 0x3feddcd9cc23cf06,
+           0x3fd3b2a7ff2d8ea0, 0x3fd4bf2fbe681ba4, 0xbfef83d5d32028f6,
+           0xbfe2ac80199e9490, 0xbfe630703f533af4, 0x3feb3293e69a12ae,
+           0xbfee0e8c4515d52c, 0xbfec03b0e2bf9ad6, 0x3fdaccc9e88176a4,
+           0x3fe97eb52b9b5dac);
+};
+
+// Simple random test with similar values (vector-scalar) (masked)
+void TEST_CASE4(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //                             -0.9766
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0xbbd0);
+  //                0.8535, -0.3750, -0.8066, -0.9097, -0.2216, -0.5645,
+  //                -0.3149, -0.4512,  0.5981,  0.6587,  0.9546, -0.3040,
+  //                -0.6157,  0.5723,  0.8438, -0.1544
+  VLOAD_16(v2, 0x3ad4, 0xb600, 0xba74, 0xbb47, 0xb317, 0xb884, 0xb50a, 0xb738,
+           0x38c9, 0x3945, 0x3ba3, 0xb4dd, 0xb8ed, 0x3894, 0x3ac0, 0xb0f1);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfsgnjx.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_16));
+  //                0.0000,  0.3750,  0.0000,  0.9097,  0.0000,  0.5645, 0.0000,
+  //                0.4512,  0.0000, -0.6587,  0.0000,  0.3040,  0.0000,
+  //                -0.5723,  0.0000,  0.1544
+  VCMP_U16(10, v1, 0x0, 0x3600, 0x0, 0x3b47, 0x0, 0x3884, 0x0, 0x3738, 0x0,
+           0xb945, 0x0, 0x34dd, 0x0, 0xb894, 0x0, 0x30f1);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                              -0.71056527
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0xbf35e79b);
+  //               -0.13350210, -0.18642496,  0.30152589, -0.62076813,
+  //               0.00040700, -0.59566921, -0.88075870,  0.08096603,
+  //               0.94059193, -0.29601631, -0.54263371, -0.86016685,
+  //               -0.57158113,  0.85538357, -0.76839548,  0.28374606
+  VLOAD_32(v2, 0xbe08b4c6, 0xbe3ee62f, 0x3e9a619a, 0xbf1eeaa9, 0x39d561f4,
+           0xbf187dc7, 0xbf617967, 0x3da5d185, 0x3f70caa2, 0xbe978f73,
+           0xbf0aea0b, 0xbf5c33e5, 0xbf125324, 0x3f5afa6b, 0xbf44b591,
+           0x3e91472a);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfsgnjx.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_32));
+  //                0.00000000,  0.18642496,  0.00000000,  0.62076813,
+  //                0.00000000,  0.59566921,  0.00000000, -0.08096603,
+  //                0.00000000,  0.29601631,  0.00000000,  0.86016685,
+  //                0.00000000, -0.85538357,  0.00000000, -0.28374606
+  VCMP_U32(11, v1, 0x0, 0x3e3ee62f, 0x0, 0x3f1eeaa9, 0x0, 0x3f187dc7, 0x0,
+           0xbda5d185, 0x0, 0x3e978f73, 0x0, 0x3f5c33e5, 0x0, 0xbf5afa6b, 0x0,
+           0xbe91472a);
+
+  VSET(16, e64, m1);
+  double dscalar_64;
+  //                               -0.1599292306617626
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0xbfc4788f9faef060);
+  //                -0.3770377828689853,  0.5963307040587882,
+  //                -0.4228346580189990, -0.8395360297727528,
+  //                0.2884308755790033, -0.9332093226534830,
+  //                -0.3077793113682024, -0.3241690978469995,
+  //                0.9848431705043186,  0.5835571766262024, 0.6934128987139432,
+  //                -0.8499240402166686,  0.9392758702585176,
+  //                0.8754505566292561, -0.4187493105472220, -0.7967172481248119
+  VLOAD_64(v2, 0xbfd8216314b1d540, 0x3fe3152420f10f90, 0xbfdb0fb918f3a4fc,
+           0xbfeadd7aa9f60146, 0x3fd275a6c6712e84, 0xbfeddcd9cc23cf06,
+           0xbfd3b2a7ff2d8ea0, 0xbfd4bf2fbe681ba4, 0x3fef83d5d32028f6,
+           0x3fe2ac80199e9490, 0x3fe630703f533af4, 0xbfeb3293e69a12ae,
+           0x3fee0e8c4515d52c, 0x3fec03b0e2bf9ad6, 0xbfdaccc9e88176a4,
+           0xbfe97eb52b9b5dac);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfsgnjx.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_64));
+  //                0.0000000000000000, -0.5963307040587882, 0.0000000000000000,
+  //                0.8395360297727528,  0.0000000000000000, 0.9332093226534830,
+  //                0.0000000000000000,  0.3241690978469995, 0.0000000000000000,
+  //                -0.5835571766262024,  0.0000000000000000,
+  //                0.8499240402166686,  0.0000000000000000,
+  //                -0.8754505566292561,  0.0000000000000000, 0.7967172481248119
+  VCMP_U64(12, v1, 0x0, 0xbfe3152420f10f90, 0x0, 0x3feadd7aa9f60146, 0x0,
+           0x3feddcd9cc23cf06, 0x0, 0x3fd4bf2fbe681ba4, 0x0, 0xbfe2ac80199e9490,
+           0x0, 0x3feb3293e69a12ae, 0x0, 0xbfec03b0e2bf9ad6, 0x0,
+           0x3fe97eb52b9b5dac);
+};
+
+int main(void) {
+  enable_vec();
+  enable_fp();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vfslide1down.c b/apps/riscv-tests/isa/rv64uv/vfslide1down.c
new file mode 100644
index 0000000..db6c325
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vfslide1down.c
@@ -0,0 +1,107 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+void TEST_CASE1() {
+  double dscalar_16;
+  //                            -0.9380
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0xbb81);
+
+  VSET(32, e16, m1);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18,
+           19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_16(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  asm volatile("vfslide1down.vf v1, v2, %[A]" ::[A] "f"(dscalar_16));
+  VCMP_U16(1, v1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 0xbb81);
+
+  double dscalar_32;
+  //                             -0.96056187
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0xbf75e762);
+
+  VSET(32, e32, m1);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18,
+           19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_32(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  asm volatile("vfslide1down.vf v1, v2, %[A]" ::[A] "f"(dscalar_32));
+  VCMP_U32(2, v1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+           0xbf75e762);
+
+  double dscalar_64;
+  //                               0.9108707261227378
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0x3fed25da5d7296fe);
+
+  VSET(32, e64, m1);
+  VLOAD_64(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18,
+           19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_64(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  asm volatile("vfslide1down.vf v1, v2, %[A]" ::[A] "f"(dscalar_64));
+  VCMP_U64(3, v1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
+           0x3fed25da5d7296fe);
+}
+
+void TEST_CASE2() {
+  double dscalar_16;
+  //                            -0.9380
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0xbb81);
+
+  VSET(32, e16, m1);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18,
+           19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_16(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  VLOAD_8(v0, 0x55, 0x55);
+  asm volatile("vfslide1down.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_16));
+  VCMP_U16(6, v1, 2, -1, 4, -1, 6, -1, 8, -1, 10, -1, 12, -1, 14, -1, 16, -1);
+
+  double dscalar_32;
+  //                             -0.96056187
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0xbf75e762);
+
+  VSET(32, e32, m1);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18,
+           19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_32(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vfslide1down.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_32));
+  VCMP_U32(7, v1, -1, 3, -1, 5, -1, 7, -1, 9, -1, 11, -1, 13, -1, 15, -1,
+           0xbf75e762);
+
+  double dscalar_64;
+  //                               0.9108707261227378
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0x3fed25da5d7296fe);
+
+  VSET(32, e64, m1);
+  VLOAD_64(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18,
+           19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_64(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  VLOAD_8(v0, 0x55, 0x55);
+  asm volatile("vfslide1down.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_64));
+  VCMP_U64(8, v1, 2, -1, 4, -1, 6, -1, 8, -1, 10, -1, 12, -1, 14, -1, 16, -1);
+}
+
+int main(void) {
+  enable_vec();
+  enable_fp();
+
+  TEST_CASE1();
+  TEST_CASE2();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vfslide1up.c b/apps/riscv-tests/isa/rv64uv/vfslide1up.c
new file mode 100644
index 0000000..90fc5a8
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vfslide1up.c
@@ -0,0 +1,90 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+void TEST_CASE1() {
+  double dscalar_16;
+  //                            -0.9380
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0xbb81);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_16(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  asm volatile("vfslide1up.vf v1, v2, %[A]" ::[A] "f"(dscalar_16));
+  VCMP_U16(1, v1, 0xbb81, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+
+  double dscalar_32;
+  //                             -0.96056187
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0xbf75e762);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_32(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  asm volatile("vfslide1up.vf v1, v2, %[A]" ::[A] "f"(dscalar_32));
+  VCMP_U32(2, v1, 0xbf75e762, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
+           15);
+
+  double dscalar_64;
+  //                               0.9108707261227378
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0x3fed25da5d7296fe);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_64(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  asm volatile("vfslide1up.vf v1, v2, %[A]" ::[A] "f"(dscalar_64));
+  VCMP_U64(3, v1, 0x3fed25da5d7296fe, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
+           14, 15);
+}
+
+void TEST_CASE2() {
+  double dscalar_16;
+  //                            -0.9380
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0xbb81);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_16(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  VLOAD_8(v0, 0x55, 0x55);
+  asm volatile("vfslide1up.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_16));
+  VCMP_U16(4, v1, 0xbb81, -1, 2, -1, 4, -1, 6, -1, 8, -1, 10, -1, 12, -1, 14,
+           -1);
+
+  double dscalar_32;
+  //                             -0.96056187
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0xbf75e762);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_32(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vfslide1up.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_32));
+  VCMP_U32(5, v1, -1, 1, -1, 3, -1, 5, -1, 7, -1, 9, -1, 11, -1, 13, -1, 15);
+
+  double dscalar_64;
+  //                               0.9108707261227378
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0x3fed25da5d7296fe);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_64(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  VLOAD_8(v0, 0x55, 0x55);
+  asm volatile("vfslide1up.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_64));
+  VCMP_U64(6, v1, 0x3fed25da5d7296fe, -1, 2, -1, 4, -1, 6, -1, 8, -1, 10, -1,
+           12, -1, 14, -1);
+}
+
+int main(void) {
+  enable_vec();
+  enable_fp();
+
+  TEST_CASE1();
+  TEST_CASE2();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vfsqrt.c b/apps/riscv-tests/isa/rv64uv/vfsqrt.c
new file mode 100644
index 0000000..12421bd
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vfsqrt.c
@@ -0,0 +1,142 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+//         Matteo Perotti <mperotti@iis.ee.ethz.ch>
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+// Simple random test with similar values
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  //              -4628.000,   5116.000, -9928.000,   9392.000, -140.875,
+  //              6112.000,   2598.000,   3210.000,   528.000, -3298.000,
+  //              -3674.000,   368.250,   1712.000, -8584.000, -2080.000,
+  //              4336.000
+  VLOAD_16(v2, 0xec85, 0x6cff, 0xf0d9, 0x7096, 0xd867, 0x6df8, 0x6913, 0x6a45,
+           0x6020, 0xea71, 0xeb2d, 0x5dc1, 0x66b0, 0xf031, 0xe810, 0x6c3c);
+  asm volatile("vfsqrt.v v3, v2");
+  //                nan,   71.500,   nan,   96.938,
+  //                nan,   78.188,   50.969,   56.656,   22.984,   nan,
+  //                nan,   19.188,   41.375,   nan,   nan,   65.875
+  VCMP_U16(1, v3, 0x7e00, 0x5478, 0x7e00, 0x560e, 0x7e00, 0x54e2, 0x525f,
+           0x5315, 0x4dbe, 0x7e00, 0x7e00, 0x4ccc, 0x512c, 0x7e00, 0x7e00,
+           0x541d);
+
+  VSET(16, e32, m1);
+  //                53688.590, -5719.180, -59560.355, -34640.023, -22323.398,
+  //                -52381.586,   19136.160,   13055.238, -68576.781,
+  //                -35066.488,   62475.219, -25604.578,   54705.039,
+  //                -19827.459,   17792.961, -28415.572
+  VLOAD_32(v2, 0x4751b897, 0xc5b2b971, 0xc768a85b, 0xc7075006, 0xc6ae66cc,
+           0xc74c9d96, 0x46958052, 0x464bfcf4, 0xc785f064, 0xc708fa7d,
+           0x47740b38, 0xc6c80928, 0x4755b10a, 0xc69ae6eb, 0x468b01ec,
+           0xc6ddff25);
+  asm volatile("vfsqrt.v v3, v2");
+  //                231.708,   nan,   nan,   nan,   nan,   nan,   138.334,
+  //                114.260,   nan,   nan,   249.950,   nan,   233.891,   nan,
+  //                133.390,   nan
+  VCMP_U32(2, v3, 0x4367b53e, 0x7fc00000, 0x7fc00000, 0x7fc00000, 0x7fc00000,
+           0x7fc00000, 0x430a5560, 0x42e484e0, 0x7fc00000, 0x7fc00000,
+           0x4379f34f, 0x7fc00000, 0x4369e41e, 0x7fc00000, 0x430563e7,
+           0x7fc00000);
+
+  VSET(16, e64, m1);
+  //              -2532126.867, -601715.939, -7176821.248,   9617114.284,
+  //              -4651296.040, -9962642.835,   4027953.647,   7849763.850,
+  //              -9544132.585, -8682313.823,   7018932.012,   639358.130,
+  //              -7598169.215, -9585529.793, -4604984.668,   314584.590
+  VLOAD_64(v2, 0xc143518f6efce4ae, 0xc1225ce7e096cbf0, 0xc15b609d4fd8b968,
+           0x416257db4912ef24, 0xc151be4802974a67, 0xc16300925abc1630,
+           0x414ebb18d2c34030, 0x415df1c8f662a87c, 0xc162343892b8d28c,
+           0xc1608f693a52837e, 0x415ac66d00c810d8, 0x412382fc427c96a0,
+           0xc15cfc164dc9e320, 0xc162486f39607ee9, 0xc151910e2ac0e818,
+           0x411333625c861bc0);
+  asm volatile("vfsqrt.v v3, v2");
+  //                nan,   nan,   nan,   3101.147,   nan,   nan,   2006.976,
+  //                2801.743,   nan,   nan,   2649.327,   799.599,   nan,   nan,
+  //                nan,   560.878
+  VCMP_U64(3, v3, 0x7ff8000000000000, 0x7ff8000000000000, 0x7ff8000000000000,
+           0x40a83a4b64b82189, 0x7ff8000000000000, 0x7ff8000000000000,
+           0x409f5be7acad5998, 0x40a5e37c6ac52c2f, 0x7ff8000000000000,
+           0x7ff8000000000000, 0x40a4b2a7466e763d, 0x4088fcca333ab72d,
+           0x7ff8000000000000, 0x7ff8000000000000, 0x7ff8000000000000,
+           0x40818706fb9cc11b);
+};
+
+// Simple random test with similar values (masked)
+// The numbers are the same of TEST_CASE1
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  //              -4628.000,   5116.000, -9928.000,   9392.000, -140.875,
+  //              6112.000,   2598.000,   3210.000,   528.000, -3298.000,
+  //              -3674.000,   368.250,   1712.000, -8584.000, -2080.000,
+  //              4336.000
+  VLOAD_16(v2, 0xec85, 0x6cff, 0xf0d9, 0x7096, 0xd867, 0x6df8, 0x6913, 0x6a45,
+           0x6020, 0xea71, 0xeb2d, 0x5dc1, 0x66b0, 0xf031, 0xe810, 0x6c3c);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v3);
+  asm volatile("vfsqrt.v v3, v2, v0.t");
+  //                0.000,   71.500,   0.000,   96.938,   0.000,   78.188,
+  //                0.000,   56.656,   0.000,   nan,   0.000,   19.188,   0.000,
+  //                nan,   0.000,   65.875
+  VCMP_U16(4, v3, 0x0, 0x5478, 0x0, 0x560e, 0x0, 0x54e2, 0x0, 0x5315, 0x0,
+           0x7e00, 0x0, 0x4ccc, 0x0, 0x7e00, 0x0, 0x541d);
+
+  VSET(16, e32, m1);
+  //                53688.590, -5719.180, -59560.355, -34640.023, -22323.398,
+  //                -52381.586,   19136.160,   13055.238, -68576.781,
+  //                -35066.488,   62475.219, -25604.578,   54705.039,
+  //                -19827.459,   17792.961, -28415.572
+  VLOAD_32(v2, 0x4751b897, 0xc5b2b971, 0xc768a85b, 0xc7075006, 0xc6ae66cc,
+           0xc74c9d96, 0x46958052, 0x464bfcf4, 0xc785f064, 0xc708fa7d,
+           0x47740b38, 0xc6c80928, 0x4755b10a, 0xc69ae6eb, 0x468b01ec,
+           0xc6ddff25);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v3);
+  asm volatile("vfsqrt.v v3, v2, v0.t");
+  //                0.000,   nan,   0.000,   nan,   0.000,   nan,   0.000,
+  //                114.260,   0.000,   nan,   0.000,   nan,   0.000,   nan,
+  //                0.000,   nan
+  VCMP_U32(5, v3, 0x0, 0x7fc00000, 0x0, 0x7fc00000, 0x0, 0x7fc00000, 0x0,
+           0x42e484e0, 0x0, 0x7fc00000, 0x0, 0x7fc00000, 0x0, 0x7fc00000, 0x0,
+           0x7fc00000);
+
+  VSET(16, e64, m1);
+  //              -2532126.867, -601715.939, -7176821.248,   9617114.284,
+  //              -4651296.040, -9962642.835,   4027953.647,   7849763.850,
+  //              -9544132.585, -8682313.823,   7018932.012,   639358.130,
+  //              -7598169.215, -9585529.793, -4604984.668,   314584.590
+  VLOAD_64(v2, 0xc143518f6efce4ae, 0xc1225ce7e096cbf0, 0xc15b609d4fd8b968,
+           0x416257db4912ef24, 0xc151be4802974a67, 0xc16300925abc1630,
+           0x414ebb18d2c34030, 0x415df1c8f662a87c, 0xc162343892b8d28c,
+           0xc1608f693a52837e, 0x415ac66d00c810d8, 0x412382fc427c96a0,
+           0xc15cfc164dc9e320, 0xc162486f39607ee9, 0xc151910e2ac0e818,
+           0x411333625c861bc0);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v3);
+  asm volatile("vfsqrt.v v3, v2, v0.t");
+  //                0.000,   nan,   0.000,   3101.147,   0.000,   nan,   0.000,
+  //                2801.743,   0.000,   nan,   0.000,   799.599,   0.000, nan,
+  //                0.000,   560.878
+  VCMP_U64(6, v3, 0x0, 0x7ff8000000000000, 0x0, 0x40a83a4b64b82189, 0x0,
+           0x7ff8000000000000, 0x0, 0x40a5e37c6ac52c2f, 0x0, 0x7ff8000000000000,
+           0x0, 0x4088fcca333ab72d, 0x0, 0x7ff8000000000000, 0x0,
+           0x40818706fb9cc11b);
+};
+
+int main(void) {
+  enable_vec();
+  enable_fp();
+  // Change RM to RTZ since there are issues with FDIV + RNE in fpnew
+  // Update: there are issues also with RTZ...
+  CHANGE_RM(RM_RTZ);
+
+  TEST_CASE1();
+  TEST_CASE2();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vfsub.c b/apps/riscv-tests/isa/rv64uv/vfsub.c
new file mode 100644
index 0000000..195e6bb
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vfsub.c
@@ -0,0 +1,349 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+// Simple random test with similar values + 1 subnormal
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  //              -0.2161,  0.7432,  0.7871,  0.7583, -0.4546, -0.0478,  0.1260,
+  //              -0.4824,  0.9282, -0.6221,  0.6543,  0.3025, -0.1420, -0.7236,
+  //              0.2333, -0.0269
+  VLOAD_16(v2, 0xb2ea, 0x39f2, 0x3a4c, 0x3a11, 0xb746, 0xaa1f, 0x3008, 0xb7b8,
+           0x3b6d, 0xb8fa, 0x393c, 0x34d7, 0xb08b, 0xb9ca, 0x3377, 0xa6e5);
+  //              -0.3289, -0.8408, -0.1754, -0.8472,  0.7739, -0.9111, -0.3152,
+  //              0.4519, -0.2537,  0.9287, -0.7163, -0.2318,  0.0615, -0.2563,
+  //              0.1448,  0.6606
+  VLOAD_16(v3, 0xb543, 0xbaba, 0xb19d, 0xbac7, 0x3a31, 0xbb4a, 0xb50b, 0x373b,
+           0xb40f, 0x3b6e, 0xb9bb, 0xb36b, 0x2bde, 0xb41a, 0x30a2, 0x3949);
+  asm volatile("vfsub.vv v1, v2, v3");
+  //               0.1128,  1.5840,  0.9624,  1.6055, -1.2285,  0.8633,  0.4412,
+  //               -0.9346,  1.1816, -1.5508,  1.3711,  0.5342, -0.2034,
+  //               -0.4673,  0.0885, -0.6875
+  VCMP_U16(1, v1, 0x2f38, 0x3e56, 0x3bb3, 0x3e6c, 0xbcea, 0x3ae8, 0x370f,
+           0xbb7a, 0x3cba, 0xbe34, 0x3d7c, 0x3846, 0xb282, 0xb77a, 0x2daa,
+           0xb980);
+
+  VSET(16, e32, m1);
+  //              -0.12869358,  0.96847999, -0.85811919, -0.21122381,
+  //              -0.05195865,  0.43910158,  0.86828148, -0.90407801,
+  //              0.62089461, -0.65907389,  0.91886526, -0.57595438,
+  //              -0.35377914, -0.26657876,  0.49153560,  0.42637765
+  VLOAD_32(v2, 0xbe03c840, 0x3f77ee4e, 0xbf5badb3, 0xbe584b0e, 0xbd54d298,
+           0x3ee0d1ec, 0x3f5e47b2, 0xbf6771a8, 0x3f1ef2f3, 0xbf28b911,
+           0x3f6b3ac1, 0xbf1371bf, 0xbeb5228a, 0xbe887d03, 0x3efbaa8e,
+           0x3eda4e2c);
+  //              -0.50821143, -0.56901741, -0.88642830,  0.91128469,
+  //              -0.00441748,  0.72763014,  0.81834352, -0.49977919,
+  //              -0.94507313, -0.60766727,  0.21069343,  0.35644454,
+  //              -0.51639801, -0.74812186, -0.97028691,  0.42650157
+  VLOAD_32(v3, 0xbf021a25, 0xbf11ab20, 0xbf62ecf7, 0x3f6949f4, 0xbb90c083,
+           0x3f3a45f8, 0x3f517ef6, 0xbeffe30f, 0xbf71f050, 0xbf1b9015,
+           0x3e57c005, 0x3eb67fe6, 0xbf0432a9, 0xbf3f84ea, 0xbf7864b9,
+           0x3eda5e6a);
+  asm volatile("vfsub.vv v1, v2, v3");
+  //               0.37951785,  1.53749740,  0.02830911, -1.12250853,
+  //               -0.04754117, -0.28852856,  0.04993796,
+  //               -0.40429881,  1.56596780, -0.05140662,  0.70817184,
+  //               -0.93239892,  0.16261888,  0.48154309,  1.46182251,
+  //               -0.00012392
+  VCMP_U32(2, v1, 0x3ec2502a, 0x3fc4ccb7, 0x3ce7e880, 0xbf8fae5c, 0xbd42ba88,
+           0xbe93ba04, 0x3d4c8bc0, 0xbecf0041, 0x3fc871a2, 0xbd528fc0,
+           0x3f354ac0, 0xbf6eb1b2, 0x3e268590, 0x3ef68cd1, 0x3fbb1d00,
+           0xb901f000);
+
+  VSET(16, e64, m1);
+  //              -0.5053356652713634, -0.6291854947278097,  0.6181258713941662,
+  //              -0.6097328085365348,  0.8960683065358290,  0.1233825892982841,
+  //              -0.7071646124826323, -0.6783334309218909,  0.3533001486660008,
+  //              0.4732651306122215, -0.7335080825789513, -0.9296500813876505,
+  //              0.5349827137885166, -0.0621174552558810, -0.8122743533756343,
+  //              -0.8908485518923974
+  VLOAD_64(v2, 0xbfe02bb5b37af91c, 0xbfe422499e5f271a, 0x3fe3c7afe84e61dc,
+           0xbfe382ee60fece00, 0x3fecac9770f1b62e, 0x3fbf960059ee92f0,
+           0xbfe6a117ae700ba0, 0xbfe5b4e84fb2f9d4, 0x3fd69c783a0c5078,
+           0x3fde49f9d4944428, 0xbfe778e5f140e788, 0xbfedbfb18709140c,
+           0x3fe11e941174b448, 0xbfafcddbedab64a0, 0xbfe9fe26c8e417ba,
+           0xbfec81d4d2822346);
+  //              -0.6041772411195545,  0.1691588460867453, -0.3855578735230800,
+  //              -0.9206749118255901,  0.7025181961160538, -0.9905598942344518,
+  //              0.9510997049380876,  0.2754176494545910,  0.5271936205102918,
+  //              0.8778238674058336,  0.9294006140978470, -0.8775508592745904,
+  //              0.7472392658861982, -0.3880038279796372, -0.6483706997783654,
+  //              -0.1530785884604509
+  VLOAD_64(v3, 0xbfe3556b82731260, 0x3fc5a6ff3fe2c608, 0xbfd8acfaee5fcdc0,
+           0xbfed762b3b913c28, 0x3fe67b0770a53a4a, 0xbfefb2aaa9ceeb06,
+           0x3fee6f68a5fe3800, 0x3fd1a071594983a8, 0x3fe0dec527d80c9a,
+           0x3fec172214450060, 0x3fedbda65b4dd79c, 0xbfec14e58a252770,
+           0x3fe7e962522895aa, 0xbfd8d50e01f94d70, 0xbfe4bf73e8e77264,
+           0xbfc398144593e6c0);
+  asm volatile("vfsub.vv v1, v2, v3");
+  //               0.0988415758481911, -0.7983443408145550,  1.0036837449172462,
+  //               0.3109421032890554,  0.1935501104197752,  1.1139424835327358,
+  //               -1.6582643174207199, -0.9537510803764819,
+  //               -0.1738934718442910, -0.4045587367936121,
+  //               -1.6629086966767983, -0.0520992221130601,
+  //               -0.2122565520976816,  0.3258863727237562,
+  //               -0.1639036535972689, -0.7377699634319466
+  VCMP_U64(3, v1, 0x3fb94dae77c0ca20, 0xbfe98c096e57d89c, 0x3ff00f16afbf245e,
+           0x3fd3e679b524dc50, 0x3fc8c6400131ef90, 0x3ff1d2b55a865eb2,
+           0xbffa88402a3721d0, 0xbfee8520fc57bba8, 0xbfc642242b479178,
+           0xbfd9e44a53f5bc98, 0xbffa9b4626475f92, 0xbfaaacbfce3ec9c0,
+           0xbfcb2b3902cf8588, 0x3fd4db528443e0dc, 0xbfc4facb7ff29558,
+           0xbfe79bcfc11d2996);
+};
+
+// Simple random test with similar values + 1 subnormal (masked)
+// The numbers are the same of TEST_CASE1
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  //              -0.2161,  0.7432,  0.7871,  0.7583, -0.4546, -0.0478,  0.1260,
+  //              -0.4824,  0.9282, -0.6221,  0.6543,  0.3025, -0.1420, -0.7236,
+  //              0.2333, -0.0269
+  VLOAD_16(v2, 0xb2ea, 0x39f2, 0x3a4c, 0x3a11, 0xb746, 0xaa1f, 0x3008, 0xb7b8,
+           0x3b6d, 0xb8fa, 0x393c, 0x34d7, 0xb08b, 0xb9ca, 0x3377, 0xa6e5);
+  //              -0.3289, -0.8408, -0.1754, -0.8472,  0.7739, -0.9111, -0.3152,
+  //              0.4519, -0.2537,  0.9287, -0.7163, -0.2318,  0.0615, -0.2563,
+  //              0.1448,  0.6606
+  VLOAD_16(v3, 0xb543, 0xbaba, 0xb19d, 0xbac7, 0x3a31, 0xbb4a, 0xb50b, 0x373b,
+           0xb40f, 0x3b6e, 0xb9bb, 0xb36b, 0x2bde, 0xb41a, 0x30a2, 0x3949);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfsub.vv v1, v2, v3, v0.t");
+  //               0.0000,  1.5840,  0.0000,  1.6055,  0.0000,  0.8633,  0.0000,
+  //               -0.9346,  0.0000, -1.5508,  0.0000,  0.5342,  0.0000,
+  //               -0.4673,  0.0000, -0.6875
+  VCMP_U16(4, v1, 0x0, 0x3e56, 0x0, 0x3e6c, 0x0, 0x3ae8, 0x0, 0xbb7a, 0x0,
+           0xbe34, 0x0, 0x3846, 0x0, 0xb77a, 0x0, 0xb980);
+
+  VSET(16, e32, m1);
+  //              -0.12869358,  0.96847999, -0.85811919, -0.21122381,
+  //              -0.05195865,  0.43910158,  0.86828148, -0.90407801,
+  //              0.62089461, -0.65907389,  0.91886526, -0.57595438,
+  //              -0.35377914, -0.26657876,  0.49153560,  0.42637765
+  VLOAD_32(v2, 0xbe03c840, 0x3f77ee4e, 0xbf5badb3, 0xbe584b0e, 0xbd54d298,
+           0x3ee0d1ec, 0x3f5e47b2, 0xbf6771a8, 0x3f1ef2f3, 0xbf28b911,
+           0x3f6b3ac1, 0xbf1371bf, 0xbeb5228a, 0xbe887d03, 0x3efbaa8e,
+           0x3eda4e2c);
+  //              -0.50821143, -0.56901741, -0.88642830,  0.91128469,
+  //              -0.00441748,  0.72763014,  0.81834352, -0.49977919,
+  //              -0.94507313, -0.60766727,  0.21069343,  0.35644454,
+  //              -0.51639801, -0.74812186, -0.97028691,  0.42650157
+  VLOAD_32(v3, 0xbf021a25, 0xbf11ab20, 0xbf62ecf7, 0x3f6949f4, 0xbb90c083,
+           0x3f3a45f8, 0x3f517ef6, 0xbeffe30f, 0xbf71f050, 0xbf1b9015,
+           0x3e57c005, 0x3eb67fe6, 0xbf0432a9, 0xbf3f84ea, 0xbf7864b9,
+           0x3eda5e6a);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfsub.vv v1, v2, v3, v0.t");
+  //               0.00000000,  1.53749740,  0.00000000, -1.12250853,
+  //               0.00000000, -0.28852856,  0.00000000, -0.40429881,
+  //               0.00000000, -0.05140662,  0.00000000, -0.93239892,
+  //               0.00000000,  0.48154309,  0.00000000, -0.00012392
+  VCMP_U32(5, v1, 0x0, 0x3fc4ccb7, 0x0, 0xbf8fae5c, 0x0, 0xbe93ba04, 0x0,
+           0xbecf0041, 0x0, 0xbd528fc0, 0x0, 0xbf6eb1b2, 0x0, 0x3ef68cd1, 0x0,
+           0xb901f000);
+
+  VSET(16, e64, m1);
+  //              -0.5053356652713634, -0.6291854947278097,  0.6181258713941662,
+  //              -0.6097328085365348,  0.8960683065358290,  0.1233825892982841,
+  //              -0.7071646124826323, -0.6783334309218909,  0.3533001486660008,
+  //              0.4732651306122215, -0.7335080825789513, -0.9296500813876505,
+  //              0.5349827137885166, -0.0621174552558810, -0.8122743533756343,
+  //              -0.8908485518923974
+  VLOAD_64(v2, 0xbfe02bb5b37af91c, 0xbfe422499e5f271a, 0x3fe3c7afe84e61dc,
+           0xbfe382ee60fece00, 0x3fecac9770f1b62e, 0x3fbf960059ee92f0,
+           0xbfe6a117ae700ba0, 0xbfe5b4e84fb2f9d4, 0x3fd69c783a0c5078,
+           0x3fde49f9d4944428, 0xbfe778e5f140e788, 0xbfedbfb18709140c,
+           0x3fe11e941174b448, 0xbfafcddbedab64a0, 0xbfe9fe26c8e417ba,
+           0xbfec81d4d2822346);
+  //              -0.6041772411195545,  0.1691588460867453, -0.3855578735230800,
+  //              -0.9206749118255901,  0.7025181961160538, -0.9905598942344518,
+  //              0.9510997049380876,  0.2754176494545910,  0.5271936205102918,
+  //              0.8778238674058336,  0.9294006140978470, -0.8775508592745904,
+  //              0.7472392658861982, -0.3880038279796372, -0.6483706997783654,
+  //              -0.1530785884604509
+  VLOAD_64(v3, 0xbfe3556b82731260, 0x3fc5a6ff3fe2c608, 0xbfd8acfaee5fcdc0,
+           0xbfed762b3b913c28, 0x3fe67b0770a53a4a, 0xbfefb2aaa9ceeb06,
+           0x3fee6f68a5fe3800, 0x3fd1a071594983a8, 0x3fe0dec527d80c9a,
+           0x3fec172214450060, 0x3fedbda65b4dd79c, 0xbfec14e58a252770,
+           0x3fe7e962522895aa, 0xbfd8d50e01f94d70, 0xbfe4bf73e8e77264,
+           0xbfc398144593e6c0);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfsub.vv v1, v2, v3, v0.t");
+  //               0.0000000000000000, -0.7983443408145550,  0.0000000000000000,
+  //               0.3109421032890554,  0.0000000000000000,  1.1139424835327358,
+  //               0.0000000000000000, -0.9537510803764819,  0.0000000000000000,
+  //               -0.4045587367936121,  0.0000000000000000,
+  //               -0.0520992221130601,  0.0000000000000000, 0.3258863727237562,
+  //               0.0000000000000000, -0.7377699634319466
+  VCMP_U64(6, v1, 0x0, 0xbfe98c096e57d89c, 0x0, 0x3fd3e679b524dc50, 0x0,
+           0x3ff1d2b55a865eb2, 0x0, 0xbfee8520fc57bba8, 0x0, 0xbfd9e44a53f5bc98,
+           0x0, 0xbfaaacbfce3ec9c0, 0x0, 0x3fd4db528443e0dc, 0x0,
+           0xbfe79bcfc11d2996);
+};
+
+// Simple random test with similar values (vector-scalar)
+void TEST_CASE3(void) {
+  VSET(16, e16, m1);
+  //               0.9727,  0.7676,  0.0876, -0.4526, -0.1158,  0.6221,  0.7612,
+  //               -0.7539,  0.3875, -0.2002,  0.2168, -0.1055, -0.4348, 0.9795,
+  //               0.3650,  0.5171
+  VLOAD_16(v2, 0x3bc8, 0x3a24, 0x2d9c, 0xb73e, 0xaf6a, 0x38fa, 0x3a17, 0xba08,
+           0x3633, 0xb268, 0x32f0, 0xaec0, 0xb6f5, 0x3bd6, 0x35d7, 0x3823);
+  double dscalar_16;
+  //                             -0.8667
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0xbaef);
+  asm volatile("vfsub.vf v1, v2, %[A]" ::[A] "f"(dscalar_16));
+  //               1.8398,  1.6348,  0.9541,  0.4141,  0.7510,  1.4883,  1.6279,
+  //               0.1128,  1.2539,  0.6665,  1.0840,  0.7612,
+  //               0.4319,  1.8457,  1.2314,  1.3838
+  VCMP_U16(7, v1, 0x3f5c, 0x3e8a, 0x3ba2, 0x36a0, 0x3a02, 0x3df4, 0x3e83,
+           0x2f38, 0x3d04, 0x3955, 0x3c56, 0x3a17, 0x36e9, 0x3f62, 0x3ced,
+           0x3d89);
+
+  VSET(16, e32, m1);
+  //               0.85933530, -0.31821987,  0.18340160, -0.58902484,
+  //               -0.83326858, -0.98716992, -0.74268776, -0.50486410,
+  //               0.91496444, -0.46108878, -0.75265163, -0.17853038,
+  //               0.09909800, -0.22828153,  0.31248060,  0.70940411
+  VLOAD_32(v2, 0x3f5bfd66, 0xbea2edb7, 0x3e3bcda1, 0xbf16ca55, 0xbf555117,
+           0xbf7cb72b, 0xbf3e20c9, 0xbf013ec6, 0x3f6a3b1c, 0xbeec13d4,
+           0xbf40adc7, 0xbe36d0ab, 0x3dcaf3e5, 0xbe69c2a2, 0x3e9ffd75,
+           0x3f359b82);
+  double dscalar_32;
+  //                              -0.16449618
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0xbe2871b0);
+  asm volatile("vfsub.vf v1, v2, %[A]" ::[A] "f"(dscalar_32));
+  //               1.02383149, -0.15372369,  0.34789777, -0.42452866,
+  //               -0.66877240, -0.82267374, -0.57819158,
+  //               -0.34036791,  1.07946062, -0.29659259, -0.58815545,
+  //               -0.01403420,  0.26359418, -0.06378534,  0.47697678,
+  //               0.87390029
+  VCMP_U32(8, v1, 0x3f830ce9, 0xbe1d69be, 0x3eb21fa8, 0xbed95bd2, 0xbf2b34ab,
+           0xbf529abf, 0xbf14045d, 0xbeae44b4, 0x3f8a2bc4, 0xbe97dafc,
+           0xbf16915b, 0xbc65efb0, 0x3e86f5d1, 0xbd82a1e4, 0x3ef4364d,
+           0x3f5fb7ee);
+
+  VSET(16, e64, m1);
+  //               -0.5270370833343294, -0.3892108170289901, 0.3278104985181656,
+  //               0.8978904717616114,  0.2838388271052681,  0.1890152734369528,
+  //               -0.5587120809764872,  0.0329118609761476, 0.2661042157694802,
+  //               0.4284631655495406,  0.3525175873513684, -0.7218762878034530,
+  //               -0.1902187411555145,  0.0621279131630217,
+  //               -0.3175600204168794,  0.2653267716685161
+  VLOAD_64(v2, 0xbfe0dd7cdf9667ce, 0xbfd8e8d47c98e498, 0x3fd4fad8e29af14c,
+           0x3fecbb84cc736570, 0x3fd22a6a53f022d0, 0x3fc831a708ed9848,
+           0xbfe1e0f82875925c, 0x3fa0d9d2cd160b00, 0x3fd107d9fa03b074,
+           0x3fdb6bf0c4e4dbb8, 0x3fd68fa5ed3c17c4, 0xbfe7199c4cfbf578,
+           0xbfc85916742cb360, 0x3fafcf3ad6686660, 0xbfd452e7438d4924,
+           0x3fd0fb1d23c47348);
+  double dscalar_64;
+  //                               -0.3447987329466446
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0xbfd6112eb46d5120);
+  asm volatile("vfsub.vf v1, v2, %[A]" ::[A] "f"(dscalar_64));
+  //              -0.1822383503876848, -0.0444120840823454,
+  //              0.6726092314648102,  1.2426892047082561,  0.6286375600519127,
+  //              0.5338140063835974, -0.2139133480298425,  0.3777105939227923,
+  //              0.6109029487161248,  0.7732618984961852,  0.6973163202980130,
+  //              -0.3770775548568084,  0.1545799917911301,  0.4069266461096663,
+  //              0.0272387125297653,  0.6101255046151608
+  VCMP_U64(9, v1, 0xbfc75396157efcf8, 0xbfa6bd2e415c9bc0, 0x3fe58603cb842136,
+           0x3ff3e20e13550700, 0x3fe41dcc842eb9f8, 0x3fe115011c720ea2,
+           0xbfcb618338fba730, 0x3fd82c690e101280, 0x3fe38c84573880ca,
+           0x3fe8be8fbca9166c, 0x3fe6506a50d4b472, 0xbfd82209e58a99d0,
+           0x3fc3c946f4adeee0, 0x3fda0b160f3a5dec, 0x3f9be4770e007fc0,
+           0x3fe38625ec18e234);
+};
+
+// Simple random test with similar values (vector-scalar) (masked)
+void TEST_CASE4(void) {
+  VSET(16, e16, m1);
+  //                0.9727,  0.7676,  0.0876, -0.4526, -0.1158,  0.6221, 0.7612,
+  //                -0.7539,  0.3875, -0.2002,  0.2168, -0.1055, -0.4348,
+  //                0.9795,  0.3650,  0.5171
+  VLOAD_16(v2, 0x3bc8, 0x3a24, 0x2d9c, 0xb73e, 0xaf6a, 0x38fa, 0x3a17, 0xba08,
+           0x3633, 0xb268, 0x32f0, 0xaec0, 0xb6f5, 0x3bd6, 0x35d7, 0x3823);
+  double dscalar_16;
+  //                             -0.8667
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0xbaef);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfsub.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_16));
+  //                0.0000,  1.6348,  0.0000,  0.4141,  0.0000,  1.4883, 0.0000,
+  //                0.1128,  0.0000,  0.6665,  0.0000,  0.7612, 0.0000,  1.8457,
+  //                0.0000,  1.3838
+  VCMP_U16(10, v1, 0x0, 0x3e8a, 0x0, 0x36a0, 0x0, 0x3df4, 0x0, 0x2f38, 0x0,
+           0x3955, 0x0, 0x3a17, 0x0, 0x3f62, 0x0, 0x3d89);
+
+  VSET(16, e32, m1);
+  //                0.85933530, -0.31821987,  0.18340160, -0.58902484,
+  //                -0.83326858, -0.98716992, -0.74268776, -0.50486410,
+  //                0.91496444, -0.46108878, -0.75265163, -0.17853038,
+  //                0.09909800, -0.22828153,  0.31248060,  0.70940411
+  VLOAD_32(v2, 0x3f5bfd66, 0xbea2edb7, 0x3e3bcda1, 0xbf16ca55, 0xbf555117,
+           0xbf7cb72b, 0xbf3e20c9, 0xbf013ec6, 0x3f6a3b1c, 0xbeec13d4,
+           0xbf40adc7, 0xbe36d0ab, 0x3dcaf3e5, 0xbe69c2a2, 0x3e9ffd75,
+           0x3f359b82);
+  double dscalar_32;
+  //                              -0.16449618
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0xbe2871b0);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfsub.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_32));
+  //                0.00000000, -0.15372369,  0.00000000, -0.42452866,
+  //                0.00000000, -0.82267374,  0.00000000, -0.34036791,
+  //                0.00000000, -0.29659259,  0.00000000, -0.01403420,
+  //                0.00000000, -0.06378534,  0.00000000,  0.87390029
+  VCMP_U32(11, v1, 0x0, 0xbe1d69be, 0x0, 0xbed95bd2, 0x0, 0xbf529abf, 0x0,
+           0xbeae44b4, 0x0, 0xbe97dafc, 0x0, 0xbc65efb0, 0x0, 0xbd82a1e4, 0x0,
+           0x3f5fb7ee);
+
+  VSET(16, e64, m1);
+  //                -0.5270370833343294, -0.3892108170289901,
+  //                0.3278104985181656,  0.8978904717616114, 0.2838388271052681,
+  //                0.1890152734369528, -0.5587120809764872, 0.0329118609761476,
+  //                0.2661042157694802,  0.4284631655495406, 0.3525175873513684,
+  //                -0.7218762878034530, -0.1902187411555145,
+  //                0.0621279131630217, -0.3175600204168794,  0.2653267716685161
+  VLOAD_64(v2, 0xbfe0dd7cdf9667ce, 0xbfd8e8d47c98e498, 0x3fd4fad8e29af14c,
+           0x3fecbb84cc736570, 0x3fd22a6a53f022d0, 0x3fc831a708ed9848,
+           0xbfe1e0f82875925c, 0x3fa0d9d2cd160b00, 0x3fd107d9fa03b074,
+           0x3fdb6bf0c4e4dbb8, 0x3fd68fa5ed3c17c4, 0xbfe7199c4cfbf578,
+           0xbfc85916742cb360, 0x3fafcf3ad6686660, 0xbfd452e7438d4924,
+           0x3fd0fb1d23c47348);
+  double dscalar_64;
+  //                               -0.3447987329466446
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0xbfd6112eb46d5120);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vfsub.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_64));
+  //                0.0000000000000000, -0.0444120840823454, 0.0000000000000000,
+  //                1.2426892047082561,  0.0000000000000000, 0.5338140063835974,
+  //                0.0000000000000000,  0.3777105939227923, 0.0000000000000000,
+  //                0.7732618984961852,  0.0000000000000000,
+  //                -0.3770775548568084,  0.0000000000000000,
+  //                0.4069266461096663,  0.0000000000000000,  0.6101255046151608
+  VCMP_U64(12, v1, 0x0, 0xbfa6bd2e415c9bc0, 0x0, 0x3ff3e20e13550700, 0x0,
+           0x3fe115011c720ea2, 0x0, 0x3fd82c690e101280, 0x0, 0x3fe8be8fbca9166c,
+           0x0, 0xbfd82209e58a99d0, 0x0, 0x3fda0b160f3a5dec, 0x0,
+           0x3fe38625ec18e234);
+};
+
+int main(void) {
+  enable_vec();
+  enable_fp();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vfwadd.c b/apps/riscv-tests/isa/rv64uv/vfwadd.c
new file mode 100644
index 0000000..0879277
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vfwadd.c
@@ -0,0 +1,523 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+//         Matteo Perotti <mperotti@iis.ee.ethz.ch>
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+// Simple random test with similar values
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  //               10.5312,  79.6250,  12.2891,  89.5000,  62.5938,  53.5625,
+  //               -37.3438, -48.3750,  49.3438,  1.1475, -79.6250,  52.0000,
+  //               -61.0312,  5.1641,  48.7500, -25.6250
+  VLOAD_16(v2, 0x4944, 0x54fa, 0x4a25, 0x5598, 0x53d3, 0x52b2, 0xd0ab, 0xd20c,
+           0x522b, 0x3c97, 0xd4fa, 0x5280, 0xd3a1, 0x452a, 0x5218, 0xce68);
+  //               68.1875,
+  //               -7.0742,  20.2656,  72.3125,  88.5625,  36.0000,  96.6250,  70.4375,
+  //               -87.6875,  87.6875,  8.7891, -18.8906, -40.1562,  88.8750,
+  //               -55.5312,  2.1875
+  VLOAD_16(v3, 0x5443, 0xc713, 0x4d11, 0x5485, 0x5589, 0x5080, 0x560a, 0x5467,
+           0xd57b, 0x557b, 0x4865, 0xccb9, 0xd105, 0x558e, 0xd2f1, 0x4060);
+  asm volatile("vfwadd.vv v4, v2, v3");
+  //               78.71875000,  72.55078125,  32.55468750,  161.81250000,
+  //               151.15625000,  89.56250000,  59.28125000,  22.06250000,
+  //               -38.34375000,  88.83496094, -70.83593750,  33.10937500,
+  //               -101.18750000,  94.03906250, -6.78125000, -23.43750000
+  VCMP_U32(1, v4, 0x429d7000, 0x42911a00, 0x42023800, 0x4321d000, 0x43172800,
+           0x42b32000, 0x426d2000, 0x41b08000, 0xc2196000, 0x42b1ab80,
+           0xc28dac00, 0x42047000, 0xc2ca6000, 0x42bc1400, 0xc0d90000,
+           0xc1bb8000);
+
+  VSET(16, e32, m1);
+  //              -35386.17187500, -52670.69531250,  69391.31250000,
+  //              3219.84130859,  74596.35156250, -45488.69921875,
+  //              6598.72949219,  20221.24609375,  75105.62500000,
+  //              67354.82031250,  32844.19140625, -73470.18750000,
+  //              -28377.67382812,  61998.10937500,  24691.54296875,
+  //              -29873.45507812
+  VLOAD_32(v2, 0xc70a3a2c, 0xc74dbeb2, 0x478787a8, 0x45493d76, 0x4791b22d,
+           0xc731b0b3, 0x45ce35d6, 0x469dfa7e, 0x4792b0d0, 0x47838d69,
+           0x47004c31, 0xc78f7f18, 0xc6ddb359, 0x47722e1c, 0x46c0e716,
+           0xc6e962e9);
+  //              -90937.21875000, -72297.07031250,  18867.19531250,
+  //              -516.01525879, -13301.11425781,  85173.41406250,
+  //              -32079.35546875, -23770.60937500,  39295.43359375,
+  //              38042.19140625, -61343.24218750,  76844.01562500,
+  //              26642.50390625,  91893.05468750,  88349.72656250,
+  //              29134.96093750
+  VLOAD_32(v3, 0xc7b19c9c, 0xc78d3489, 0x46936664, 0xc40100fa, 0xc64fd475,
+           0x47a65ab5, 0xc6fa9eb6, 0xc6b9b538, 0x47197f6f, 0x47149a31,
+           0xc76f9f3e, 0x47961602, 0x46d02502, 0x47b37a87, 0x47ac8edd,
+           0x46e39dec);
+  asm volatile("vfwadd.vv v4, v2, v3");
+  //              -126323.3906250000000000, -124967.7656250000000000,
+  //              88258.5078125000000000,  2703.8260498046875000,
+  //              61295.2373046875000000,  39684.7148437500000000,
+  //              -25480.6259765625000000, -3549.3632812500000000,
+  //              114401.0585937500000000,  105397.0117187500000000,
+  //              -28499.0507812500000000,  3373.8281250000000000,
+  //              -1735.1699218750000000,  153891.1640625000000000,
+  //              113041.2695312500000000, -738.4941406250000000
+  VCMP_U64(2, v4, 0xc0fed73640000000, 0xc0fe827c40000000, 0x40f58c2820000000,
+           0x40a51fa6f0000000, 0x40edede798000000, 0x40e36096e0000000,
+           0xc0d8e22810000000, 0xc0abbaba00000000, 0x40fbee10f0000000,
+           0x40f9bb5030000000, 0xc0dbd4c340000000, 0x40aa5ba800000000,
+           0xc09b1cae00000000, 0x4102c91950000000, 0x40fb991450000000,
+           0xc08713f400000000);
+};
+
+// Simple random test with similar values (masked)
+// The numbers are the same of TEST_CASE1
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  //               10.5312,  79.6250,  12.2891,  89.5000,  62.5938,  53.5625,
+  //               -37.3438, -48.3750,  49.3438,  1.1475, -79.6250,  52.0000,
+  //               -61.0312,  5.1641,  48.7500, -25.6250
+  VLOAD_16(v2, 0x4944, 0x54fa, 0x4a25, 0x5598, 0x53d3, 0x52b2, 0xd0ab, 0xd20c,
+           0x522b, 0x3c97, 0xd4fa, 0x5280, 0xd3a1, 0x452a, 0x5218, 0xce68);
+  //               68.1875,
+  //               -7.0742,  20.2656,  72.3125,  88.5625,  36.0000,  96.6250,  70.4375,
+  //               -87.6875,  87.6875,  8.7891, -18.8906, -40.1562,  88.8750,
+  //               -55.5312,  2.1875
+  VLOAD_16(v3, 0x5443, 0xc713, 0x4d11, 0x5485, 0x5589, 0x5080, 0x560a, 0x5467,
+           0xd57b, 0x557b, 0x4865, 0xccb9, 0xd105, 0x558e, 0xd2f1, 0x4060);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfwadd.vv v4, v2, v3, v0.t");
+  //               0.00000000,  72.55078125,  0.00000000,  161.81250000,
+  //               0.00000000,  89.56250000,  0.00000000,  22.06250000,
+  //               0.00000000,  88.83496094,  0.00000000,  33.10937500,
+  //               0.00000000,  94.03906250,  0.00000000, -23.43750000
+  VCMP_U32(3, v4, 0x0, 0x42911a00, 0x0, 0x4321d000, 0x0, 0x42b32000, 0x0,
+           0x41b08000, 0x0, 0x42b1ab80, 0x0, 0x42047000, 0x0, 0x42bc1400, 0x0,
+           0xc1bb8000);
+
+  VSET(16, e32, m1);
+  //              -35386.17187500, -52670.69531250,  69391.31250000,
+  //              3219.84130859,  74596.35156250, -45488.69921875,
+  //              6598.72949219,  20221.24609375,  75105.62500000,
+  //              67354.82031250,  32844.19140625, -73470.18750000,
+  //              -28377.67382812,  61998.10937500,  24691.54296875,
+  //              -29873.45507812
+  VLOAD_32(v2, 0xc70a3a2c, 0xc74dbeb2, 0x478787a8, 0x45493d76, 0x4791b22d,
+           0xc731b0b3, 0x45ce35d6, 0x469dfa7e, 0x4792b0d0, 0x47838d69,
+           0x47004c31, 0xc78f7f18, 0xc6ddb359, 0x47722e1c, 0x46c0e716,
+           0xc6e962e9);
+  //              -90937.21875000, -72297.07031250,  18867.19531250,
+  //              -516.01525879, -13301.11425781,  85173.41406250,
+  //              -32079.35546875, -23770.60937500,  39295.43359375,
+  //              38042.19140625, -61343.24218750,  76844.01562500,
+  //              26642.50390625,  91893.05468750,  88349.72656250,
+  //              29134.96093750
+  VLOAD_32(v3, 0xc7b19c9c, 0xc78d3489, 0x46936664, 0xc40100fa, 0xc64fd475,
+           0x47a65ab5, 0xc6fa9eb6, 0xc6b9b538, 0x47197f6f, 0x47149a31,
+           0xc76f9f3e, 0x47961602, 0x46d02502, 0x47b37a87, 0x47ac8edd,
+           0x46e39dec);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfwadd.vv v4, v2, v3, v0.t");
+  //               0.0000000000000000, -124967.7656250000000000,
+  //               0.0000000000000000,  2703.8260498046875000,
+  //               0.0000000000000000,  39684.7148437500000000,
+  //               0.0000000000000000, -3549.3632812500000000,
+  //               0.0000000000000000,  105397.0117187500000000,
+  //               0.0000000000000000,  3373.8281250000000000,
+  //               0.0000000000000000,  153891.1640625000000000,
+  //               0.0000000000000000, -738.4941406250000000
+  VCMP_U64(4, v4, 0x0, 0xc0fe827c40000000, 0x0, 0x40a51fa6f0000000, 0x0,
+           0x40e36096e0000000, 0x0, 0xc0abbaba00000000, 0x0, 0x40f9bb5030000000,
+           0x0, 0x40aa5ba800000000, 0x0, 0x4102c91950000000, 0x0,
+           0xc08713f400000000);
+};
+
+// Simple random test with similar values (vector-scalar)
+void TEST_CASE3(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //                              12.5859
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0x4a4b);
+  //               2.1094,  59.2188,  89.4375,  75.2500, -4.0742,  64.7500,
+  //               -82.9375, -84.9375, -48.0625,
+  //               -6.1016,  29.9688,  10.6172,  52.5938, -8.5000,  70.5000,
+  //               -83.6875
+  VLOAD_16(v2, 0x4038, 0x5367, 0x5597, 0x54b4, 0xc413, 0x540c, 0xd52f, 0xd54f,
+           0xd202, 0xc61a, 0x4f7e, 0x494f, 0x5293, 0xc840, 0x5468, 0xd53b);
+  asm volatile("vfwadd.vf v4, v2, %[A]" ::[A] "f"(dscalar_16));
+  //               14.69531250,  71.80468750,
+  //               102.02343750,  87.83593750,  8.51171875,  77.33593750,
+  //               -70.35156250, -72.35156250,
+  //               -35.47656250,  6.48437500,  42.55468750,  23.20312500,  65.17968750,
+  //               4.08593750,  83.08593750, -71.10156250
+  VCMP_U32(5, v4, 0x416b2000, 0x428f9c00, 0x42cc0c00, 0x42afac00, 0x41083000,
+           0x429aac00, 0xc28cb400, 0xc290b400, 0xc20de800, 0x40cf8000,
+           0x422a3800, 0x41b9a000, 0x42825c00, 0x4082c000, 0x42a62c00,
+           0xc28e3400);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                              -497871.25000000
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0xc8f319e8);
+  //              -568507.00000000,  457995.96875000,  409553.18750000,
+  //              -797866.87500000,  263520.50000000,  290072.90625000,
+  //              530785.75000000,  226941.43750000,  285558.65625000,
+  //              -987117.31250000, -423428.21875000, -140664.31250000,
+  //              -844580.25000000,  549948.50000000,  304879.87500000,
+  //              -655518.43750000
+  VLOAD_32(v2, 0xc90acbb0, 0x48dfa17f, 0x48c7fa26, 0xc942caae, 0x4880ac10,
+           0x488da31d, 0x4901961c, 0x485d9f5c, 0x488b6ed5, 0xc970fed5,
+           0xc8cec087, 0xc8095e14, 0xc94e3244, 0x490643c8, 0x4894ddfc,
+           0xc92009e7);
+  asm volatile("vfwadd.vf v4, v2, %[A]" ::[A] "f"(dscalar_32));
+  //              -1066378.2500000000000000, -39875.2812500000000000,
+  //              -88318.0625000000000000, -1295738.1250000000000000,
+  //              -234350.7500000000000000, -207798.3437500000000000,
+  //              32914.5000000000000000, -270929.8125000000000000,
+  //              -212312.5937500000000000, -1484988.5625000000000000,
+  //              -921299.4687500000000000, -638535.5625000000000000,
+  //              -1342451.5000000000000000,  52077.2500000000000000,
+  //              -192991.3750000000000000, -1153389.6875000000000000
+  VCMP_U64(6, v4, 0xc130458a40000000, 0xc0e3786900000000, 0xc0f58fe100000000,
+           0xc133c57a20000000, 0xc10c9b7600000000, 0xc1095db2c0000000,
+           0x40e0125000000000, 0xc110894740000000, 0xc109eac4c0000000,
+           0xc136a8bc90000000, 0xc12c1da6f0000000, 0xc1237c8f20000000,
+           0xc1347bf380000000, 0x40e96da800000000, 0xc1078efb00000000,
+           0xc131996db0000000);
+};
+
+// Simple random test with similar values (vector-scalar) (masked)
+void TEST_CASE4(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //                              12.5859
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0x4a4b);
+  //                2.1094,  59.2188,  89.4375,  75.2500, -4.0742,  64.7500,
+  //                -82.9375, -84.9375, -48.0625,
+  //                -6.1016,  29.9688,  10.6172,  52.5938, -8.5000,  70.5000,
+  //                -83.6875
+  VLOAD_16(v2, 0x4038, 0x5367, 0x5597, 0x54b4, 0xc413, 0x540c, 0xd52f, 0xd54f,
+           0xd202, 0xc61a, 0x4f7e, 0x494f, 0x5293, 0xc840, 0x5468, 0xd53b);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfwadd.vf v4, v2, %[A], v0.t" ::[A] "f"(dscalar_16));
+  //                0.00000000,  71.80468750,  0.00000000,  87.83593750,
+  //                0.00000000,  77.33593750,  0.00000000, -72.35156250,
+  //                0.00000000,  6.48437500,  0.00000000,  23.20312500,
+  //                0.00000000,  4.08593750,  0.00000000, -71.10156250
+  VCMP_U32(7, v4, 0x0, 0x428f9c00, 0x0, 0x42afac00, 0x0, 0x429aac00, 0x0,
+           0xc290b400, 0x0, 0x40cf8000, 0x0, 0x41b9a000, 0x0, 0x4082c000, 0x0,
+           0xc28e3400);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                              -497871.25000000
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0xc8f319e8);
+  //               -568507.00000000,  457995.96875000,  409553.18750000,
+  //               -797866.87500000,  263520.50000000,  290072.90625000,
+  //               530785.75000000,  226941.43750000,  285558.65625000,
+  //               -987117.31250000, -423428.21875000, -140664.31250000,
+  //               -844580.25000000,  549948.50000000,  304879.87500000,
+  //               -655518.43750000
+  VLOAD_32(v2, 0xc90acbb0, 0x48dfa17f, 0x48c7fa26, 0xc942caae, 0x4880ac10,
+           0x488da31d, 0x4901961c, 0x485d9f5c, 0x488b6ed5, 0xc970fed5,
+           0xc8cec087, 0xc8095e14, 0xc94e3244, 0x490643c8, 0x4894ddfc,
+           0xc92009e7);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfwadd.vf v4, v2, %[A], v0.t" ::[A] "f"(dscalar_32));
+  //                0.0000000000000000, -39875.2812500000000000,
+  //                0.0000000000000000, -1295738.1250000000000000,
+  //                0.0000000000000000, -207798.3437500000000000,
+  //                0.0000000000000000, -270929.8125000000000000,
+  //                0.0000000000000000, -1484988.5625000000000000,
+  //                0.0000000000000000, -638535.5625000000000000,
+  //                0.0000000000000000,  52077.2500000000000000,
+  //                0.0000000000000000, -1153389.6875000000000000
+  VCMP_U64(8, v4, 0x0, 0xc0e3786900000000, 0x0, 0xc133c57a20000000, 0x0,
+           0xc1095db2c0000000, 0x0, 0xc110894740000000, 0x0, 0xc136a8bc90000000,
+           0x0, 0xc1237c8f20000000, 0x0, 0x40e96da800000000, 0x0,
+           0xc131996db0000000);
+};
+
+// Simple random test with similar values
+void TEST_CASE5(void) {
+  VSET(16, e16, m1);
+  //              -4.22890615,  94.35176849, -2.66183305,  81.53971863,
+  //              -30.80995941, -61.45680237,  53.70308304,  26.43629074,
+  //              -50.49792862,  12.57134342, -18.77090454, -0.50017655,
+  //              -33.71574402,  14.64656544,  89.57390594,  94.32437897
+  VLOAD_32(v2, 0xc0875333, 0x42bcb41b, 0xc02a5b79, 0x42a31456, 0xc1f67acc,
+           0xc275d3c4, 0x4256cff5, 0x41d37d86, 0xc249fde1, 0x41492439,
+           0xc1962ad0, 0xbf000b92, 0xc206dcec, 0x416a5855, 0x42b325d7,
+           0x42bca615);
+  //              -38.1875,
+  //              -22.7500,  51.3438,  8.8594,  23.0938,  32.6875,  71.7500,  7.6758,
+  //              -12.8047,  98.0625, -8.7734, -73.5625,
+  //              -59.0312,  44.9688,  63.8438,  30.1406
+  VLOAD_16(v3, 0xd0c6, 0xcdb0, 0x526b, 0x486e, 0x4dc6, 0x5016, 0x547c, 0x47ad,
+           0xca67, 0x5621, 0xc863, 0xd499, 0xd361, 0x519f, 0x53fb, 0x4f89);
+  asm volatile("vfwadd.wv v4, v2, v3");
+  //              -42.41640472,  71.60176849,  48.68191528,  90.39909363,
+  //              -7.71620941, -28.76930237,  125.45307922,  34.11207199,
+  //              -63.30261612,  110.63384247, -27.54434204, -74.06267548,
+  //              -92.74699402,  59.61531448,  153.41766357,  124.46500397
+  VCMP_U32(9, v4, 0xc229aa66, 0x428f341b, 0x4242ba48, 0x42b4cc56, 0xc0f6eb30,
+           0xc1e62788, 0x42fae7fa, 0x420872c3, 0xc27d35e1, 0x42dd4487,
+           0xc1dc5ad0, 0xc2942017, 0xc2b97e76, 0x426e7615, 0x43196aec,
+           0x42f8ee15);
+
+  VSET(16, e32, m1);
+  //              -55997.9824854041071376,  64501.1750668793683872,
+  //              -29542.1742966430028901, -97235.1376669598394074,
+  //              -76290.1568635256844573, -53719.7602741207738291,
+  //              -71738.9507989753619768,  76087.4621994893532246,
+  //              88201.1680542646208778, -10676.6526112916035345,
+  //              -87188.1793410585087258,  19855.3190320774738211,
+  //              17509.5892884960630909,  30185.4023848686192650,
+  //              54203.3669640090665780, -57884.3948619379953016
+  VLOAD_64(v2, 0xc0eb57bf70853aee, 0x40ef7ea59a25db30, 0xc0dcd98b27ad1b60,
+           0xc0f7bd3233e24524, 0xc0f2a0228283540c, 0xc0ea3af8542a6497,
+           0xc0f183af3678fc84, 0x40f29377652b4ab0, 0x40f58892b059ab28,
+           0xc0c4da5388c44d38, 0xc0f54942de94bad2, 0x40d363d46b0584c8,
+           0x40d11965b6e718a0, 0x40dd7a59c0ac76c8, 0x40ea776bbe2b4e38,
+           0xc0ec438ca2b580c4);
+  //              -73536.78125000,  57454.64062500, -32693.95507812,
+  //              -56205.09375000,  12513.70898438,  20858.82226562,
+  //              12284.94335938,  61625.35156250, -11893.36132812,
+  //              -46430.30078125,  30247.85937500, -94111.64843750,
+  //              89016.30468750, -52090.74609375,  72764.65625000,
+  //              -47109.86328125
+  VLOAD_32(v3, 0xc78fa064, 0x47606ea4, 0xc6ff6be9, 0xc75b8d18, 0x464386d6,
+           0x46a2f5a5, 0x463ff3c6, 0x4770b95a, 0xc639d572, 0xc7355e4d,
+           0x46ec4fb8, 0xc7b7cfd3, 0x47addc27, 0xc74b7abf, 0x478e1e54,
+           0xc73805dd);
+  asm volatile("vfwadd.wv v4, v2, v3");
+  //              -129534.7637354041071376,  121955.8156918793683872,
+  //              -62236.1293747680028901, -153440.2314169598394074,
+  //              -63776.4478791506844573, -32860.9380084957738291,
+  //              -59454.0074396003619768,  137712.8137619893532246,
+  //              76307.8067261396208778, -57106.9533925416035345,
+  //              -56940.3199660585087258, -74256.3294054225261789,
+  //              106525.8939759960630909, -21905.3437088813807350,
+  //              126968.0232140090665780, -104994.2581431879953016
+  VCMP_U64(10, v4, 0xc0ff9fec38429d77, 0x40fdc63d0d12ed98, 0xc0ee638423d68db0,
+           0xc102bb01d9f12292, 0xc0ef240e5506a818, 0xc0e00b9e042a6497,
+           0xc0ed07c03cf1f908, 0x4100cf868295a558, 0x40f2a13ce859ab28,
+           0xc0ebe25e8231134e, 0xc0ebcd8a3d2975a4, 0xc0f22105453e9ece,
+           0x40fa01de4db9c628, 0xc0d56455ff538938, 0x40feff805f15a71c,
+           0xc0f9a224215ac062);
+};
+
+// Simple random test with similar values (masked)
+// The numbers are the same of TEST_CASE1
+void TEST_CASE6(void) {
+  VSET(16, e16, m1);
+  //              -4.22890615,  94.35176849, -2.66183305,  81.53971863,
+  //              -30.80995941, -61.45680237,  53.70308304,  26.43629074,
+  //              -50.49792862,  12.57134342, -18.77090454, -0.50017655,
+  //              -33.71574402,  14.64656544,  89.57390594,  94.32437897
+  VLOAD_32(v2, 0xc0875333, 0x42bcb41b, 0xc02a5b79, 0x42a31456, 0xc1f67acc,
+           0xc275d3c4, 0x4256cff5, 0x41d37d86, 0xc249fde1, 0x41492439,
+           0xc1962ad0, 0xbf000b92, 0xc206dcec, 0x416a5855, 0x42b325d7,
+           0x42bca615);
+  //              -38.1875,
+  //              -22.7500,  51.3438,  8.8594,  23.0938,  32.6875,  71.7500,  7.6758,
+  //              -12.8047,  98.0625, -8.7734, -73.5625,
+  //              -59.0312,  44.9688,  63.8438,  30.1406
+  VLOAD_16(v3, 0xd0c6, 0xcdb0, 0x526b, 0x486e, 0x4dc6, 0x5016, 0x547c, 0x47ad,
+           0xca67, 0x5621, 0xc863, 0xd499, 0xd361, 0x519f, 0x53fb, 0x4f89);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfwadd.wv v4, v2, v3, v0.t");
+  //               0.00000000,  71.60176849,  0.00000000,  90.39909363,
+  //               0.00000000, -28.76930237,  0.00000000,  34.11207199,
+  //               0.00000000,  110.63384247,  0.00000000, -74.06267548,
+  //               0.00000000,  59.61531448,  0.00000000,  124.46500397
+  VCMP_U32(11, v4, 0x0, 0x428f341b, 0x0, 0x42b4cc56, 0x0, 0xc1e62788, 0x0,
+           0x420872c3, 0x0, 0x42dd4487, 0x0, 0xc2942017, 0x0, 0x426e7615, 0x0,
+           0x42f8ee15);
+
+  VSET(16, e32, m1);
+  //              -55997.9824854041071376,  64501.1750668793683872,
+  //              -29542.1742966430028901, -97235.1376669598394074,
+  //              -76290.1568635256844573, -53719.7602741207738291,
+  //              -71738.9507989753619768,  76087.4621994893532246,
+  //              88201.1680542646208778, -10676.6526112916035345,
+  //              -87188.1793410585087258,  19855.3190320774738211,
+  //              17509.5892884960630909,  30185.4023848686192650,
+  //              54203.3669640090665780, -57884.3948619379953016
+  VLOAD_64(v2, 0xc0eb57bf70853aee, 0x40ef7ea59a25db30, 0xc0dcd98b27ad1b60,
+           0xc0f7bd3233e24524, 0xc0f2a0228283540c, 0xc0ea3af8542a6497,
+           0xc0f183af3678fc84, 0x40f29377652b4ab0, 0x40f58892b059ab28,
+           0xc0c4da5388c44d38, 0xc0f54942de94bad2, 0x40d363d46b0584c8,
+           0x40d11965b6e718a0, 0x40dd7a59c0ac76c8, 0x40ea776bbe2b4e38,
+           0xc0ec438ca2b580c4);
+  //              -73536.78125000,  57454.64062500, -32693.95507812,
+  //              -56205.09375000,  12513.70898438,  20858.82226562,
+  //              12284.94335938,  61625.35156250, -11893.36132812,
+  //              -46430.30078125,  30247.85937500, -94111.64843750,
+  //              89016.30468750, -52090.74609375,  72764.65625000,
+  //              -47109.86328125
+  VLOAD_32(v3, 0xc78fa064, 0x47606ea4, 0xc6ff6be9, 0xc75b8d18, 0x464386d6,
+           0x46a2f5a5, 0x463ff3c6, 0x4770b95a, 0xc639d572, 0xc7355e4d,
+           0x46ec4fb8, 0xc7b7cfd3, 0x47addc27, 0xc74b7abf, 0x478e1e54,
+           0xc73805dd);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfwadd.wv v4, v2, v3, v0.t");
+  //               0.0000000000000000,  121955.8156918793683872,
+  //               0.0000000000000000, -153440.2314169598394074,
+  //               0.0000000000000000, -32860.9380084957738291,
+  //               0.0000000000000000,  137712.8137619893532246,
+  //               0.0000000000000000, -57106.9533925416035345,
+  //               0.0000000000000000, -74256.3294054225261789,
+  //               0.0000000000000000, -21905.3437088813807350,
+  //               0.0000000000000000, -104994.2581431879953016
+  VCMP_U64(12, v4, 0x0, 0x40fdc63d0d12ed98, 0x0, 0xc102bb01d9f12292, 0x0,
+           0xc0e00b9e042a6497, 0x0, 0x4100cf868295a558, 0x0, 0xc0ebe25e8231134e,
+           0x0, 0xc0f22105453e9ece, 0x0, 0xc0d56455ff538938, 0x0,
+           0xc0f9a224215ac062);
+};
+
+// Simple random test with similar values (vector-scalar)
+void TEST_CASE7(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //              -16.64103889,  69.17821503,  38.24327850,
+  //              -60.26666641,  97.95110321, -47.38455200,  94.12043762,
+  //              -90.39623260, -17.02018356,  28.09982681,
+  //              -85.91639709,  73.60102081, -98.61261749,
+  //              -81.75864410,  40.07990265,  55.56723022
+  VLOAD_32(v2, 0xc18520d9, 0x428a5b3f, 0x4218f91e, 0xc2711111, 0x42c3e6f7,
+           0xc23d89c8, 0x42bc3daa, 0xc2b4cadf, 0xc1882956, 0x41e0cc72,
+           0xc2abd532, 0x429333b9, 0xc2c539a9, 0xc2a3846d, 0x422051d2,
+           0x425e44d8);
+  //                              53.8750
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0x52bc);
+  asm volatile("vfwadd.wf v4, v2, %[A]" ::[A] "f"(dscalar_16));
+  //               37.23396301,  123.05321503,  92.11827850, -6.39166641,
+  //               151.82611084,  6.49044800,  147.99543762,
+  //               -36.52123260,  36.85481644,  81.97482300, -32.04139709,
+  //               127.47602081, -44.73761749, -27.88364410,  93.95490265,
+  //               109.44223022
+  VCMP_U32(13, v4, 0x4214ef94, 0x42f61b3f, 0x42b83c8f, 0xc0cc8888, 0x4317d37c,
+           0x40cfb1c0, 0x4313fed5, 0xc21215be, 0x42136b55, 0x42a3f31c,
+           0xc2002a64, 0x42fef3b9, 0xc232f352, 0xc1df11b4, 0x42bbe8e9,
+           0x42dae26c);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //               366783.2934919928666204, -648147.5638866436202079,
+  //               24949.3815817765425891, -211759.8585660880198702,
+  //               337740.3714956413023174, -528559.3617047512670979,
+  //               -863948.2704646114725620, -463848.5980863422155380,
+  //               958859.3069495267700404, -853775.5625991101842374,
+  //               -7020.6864214694360271,  839278.6509590207133442,
+  //               -443325.1460256360005587,  97289.3425237806513906,
+  //               220009.0786798361223191,  491284.4355713783297688
+  VLOAD_64(v2, 0x411662fd2c892a3c, 0xc123c7a720b5c00a, 0x40d85d586bd5f8c0,
+           0xc109d97ede57e5ac, 0x41149d317c695a78, 0xc120215eb9315d7b,
+           0xc12a5d988a7a566a, 0xc11c4fa26470bf00, 0x412d43169d287d06,
+           0xc12a0e1f200cfd96, 0xc0bb6cafb9514280, 0x41299cdd4d4a8032,
+           0xc11b0ef49587be8c, 0x40f7c0957afa3740, 0x410adb48a122e4d8,
+           0x411dfc51be066c64);
+  //                               572932.37500000
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0x490be046);
+  asm volatile("vfwadd.wf v4, v2, %[A]" ::[A] "f"(dscalar_32));
+  //               939715.6684919928666204, -75215.1888866436202079,
+  //               597881.7565817765425891,  361172.5164339119801298,
+  //               910672.7464956413023174,  44373.0132952487329021,
+  //               -291015.8954646114725620,  109083.7769136577844620,
+  //               1531791.6819495267700404, -280843.1875991101842374,
+  //               565911.6885785305639729,  1412211.0259590207133442,
+  //               129607.2289743639994413,  670221.7175237806513906,
+  //               792941.4536798361223191,  1064216.8105713783297688
+  VCMP_U64(14, v4, 0x412cad875644951e, 0xc0f25cf305ae0050, 0x41223ef3835eafc6,
+           0x41160b5210d40d2a, 0x412bcaa17e34ad3c, 0x40e5aaa06cea2850,
+           0xc111c31f94f4acd4, 0x40faa1bc6e3d0400, 0x41375f8fae943e83,
+           0xc111242cc019fb2c, 0x4121452f608d5d7b, 0x41358c7306a54019,
+           0x40ffa473a9e105d0, 0x4124741b6f5f46e8, 0x412832dae848b936,
+           0x41303d18cf819b19);
+};
+
+// Simple random test with similar values (vector-scalar) (masked)
+void TEST_CASE8(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //               -16.64103889,  69.17821503,  38.24327850,
+  //               -60.26666641,  97.95110321, -47.38455200,  94.12043762,
+  //               -90.39623260, -17.02018356,  28.09982681,
+  //               -85.91639709,  73.60102081, -98.61261749,
+  //               -81.75864410,  40.07990265,  55.56723022
+  VLOAD_32(v2, 0xc18520d9, 0x428a5b3f, 0x4218f91e, 0xc2711111, 0x42c3e6f7,
+           0xc23d89c8, 0x42bc3daa, 0xc2b4cadf, 0xc1882956, 0x41e0cc72,
+           0xc2abd532, 0x429333b9, 0xc2c539a9, 0xc2a3846d, 0x422051d2,
+           0x425e44d8);
+  //                              53.8750
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0x52bc);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfwadd.wf v4, v2, %[A], v0.t" ::[A] "f"(dscalar_16));
+  //                0.00000000,  123.05321503,  0.00000000, -6.39166641,
+  //                0.00000000,  6.49044800,  0.00000000, -36.52123260,
+  //                0.00000000,  81.97482300,  0.00000000,  127.47602081,
+  //                0.00000000, -27.88364410,  0.00000000,  109.44223022
+  VCMP_U32(15, v4, 0x0, 0x42f61b3f, 0x0, 0xc0cc8888, 0x0, 0x40cfb1c0, 0x0,
+           0xc21215be, 0x0, 0x42a3f31c, 0x0, 0x42fef3b9, 0x0, 0xc1df11b4, 0x0,
+           0x42dae26c);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                366783.2934919928666204, -648147.5638866436202079,
+  //                24949.3815817765425891, -211759.8585660880198702,
+  //                337740.3714956413023174, -528559.3617047512670979,
+  //                -863948.2704646114725620, -463848.5980863422155380,
+  //                958859.3069495267700404, -853775.5625991101842374,
+  //                -7020.6864214694360271,  839278.6509590207133442,
+  //                -443325.1460256360005587,  97289.3425237806513906,
+  //                220009.0786798361223191,  491284.4355713783297688
+  VLOAD_64(v2, 0x411662fd2c892a3c, 0xc123c7a720b5c00a, 0x40d85d586bd5f8c0,
+           0xc109d97ede57e5ac, 0x41149d317c695a78, 0xc120215eb9315d7b,
+           0xc12a5d988a7a566a, 0xc11c4fa26470bf00, 0x412d43169d287d06,
+           0xc12a0e1f200cfd96, 0xc0bb6cafb9514280, 0x41299cdd4d4a8032,
+           0xc11b0ef49587be8c, 0x40f7c0957afa3740, 0x410adb48a122e4d8,
+           0x411dfc51be066c64);
+  //                               572932.37500000
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0x490be046);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfwadd.wf v4, v2, %[A], v0.t" ::[A] "f"(dscalar_32));
+  //                0.0000000000000000, -75215.1888866436202079,
+  //                0.0000000000000000,  361172.5164339119801298,
+  //                0.0000000000000000,  44373.0132952487329021,
+  //                0.0000000000000000,  109083.7769136577844620,
+  //                0.0000000000000000, -280843.1875991101842374,
+  //                0.0000000000000000,  1412211.0259590207133442,
+  //                0.0000000000000000,  670221.7175237806513906,
+  //                0.0000000000000000,  1064216.8105713783297688
+  VCMP_U64(16, v4, 0x0, 0xc0f25cf305ae0050, 0x0, 0x41160b5210d40d2a, 0x0,
+           0x40e5aaa06cea2850, 0x0, 0x40faa1bc6e3d0400, 0x0, 0xc111242cc019fb2c,
+           0x0, 0x41358c7306a54019, 0x0, 0x4124741b6f5f46e8, 0x0,
+           0x41303d18cf819b19);
+};
+
+int main(void) {
+  enable_vec();
+  enable_fp();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  TEST_CASE5();
+  TEST_CASE6();
+  TEST_CASE7();
+  TEST_CASE8();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vfwcvt.c b/apps/riscv-tests/isa/rv64uv/vfwcvt.c
new file mode 100644
index 0000000..84db96d
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vfwcvt.c
@@ -0,0 +1,656 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+// We assume RNE rounding when not specified by the encoding
+
+/////////////////
+// vfwcvt.xu.f //
+/////////////////
+
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  //                 56.438,    -30.938,    -68.438,    -32.969,     56.438,
+  //                 -5.816,   53.094, -29.875, -93.562, -90.750, -65.875,
+  //                 -91.062,   16.281, -77.938, -67.000, -51.844
+  VLOAD_16(v2, 0x530e, 0xcfbc, 0xd447, 0xd01f, 0x530e, 0xc5d1, 0x52a3, 0xcf78,
+           0xd5d9, 0xd5ac, 0xd41e, 0xd5b1, 0x4c12, 0xd4df, 0xd430, 0xd27b);
+  asm volatile("vfwcvt.xu.f.v v4, v2");
+  //                           56,              0,              0, 0, 56, 0, 53,
+  //                           0,              0,              0, 0, 0, 16, 0,
+  //                           0,              0
+  VCMP_U32(1, v4, 0x00000038, 0x00000000, 0x00000000, 0x00000000, 0x00000038,
+           0x00000000, 0x00000035, 0x00000000, 0x00000000, 0x00000000,
+           0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000,
+           0x00000000);
+
+  VSET(16, e32, m1);
+  //                  -54444.973,      43481.863,   88447.461,   32690.551,
+  //                  -37979.809,   68218.094, -43036.512, -38011.395,
+  //                  -36599.363,   48418.234,   81414.820,   16330.853,
+  //                  75606.320, -85030.219,   13033.059,   7375.421
+  VLOAD_32(v2, 0xc754acf9, 0x4729d9dd, 0x47acbfbb, 0x46ff651a, 0xc7145bcf,
+           0x47853d0c, 0xc7281c83, 0xc7147b65, 0xc70ef75d, 0x473d223c,
+           0x479f0369, 0x467f2b69, 0x4793ab29, 0xc7a6131c, 0x464ba43c,
+           0x45e67b5f);
+  asm volatile("vfwcvt.xu.f.v v4, v2");
+  //                                   0,                  43482, 88447, 32691,
+  //                                   0,                  68218, 0, 0, 0,
+  //                                   48418,                  81415, 16331,
+  //                                   75606,                      0, 13033,
+  //                                   7375
+  VCMP_U64(2, v4, 0x0000000000000000, 0x000000000000a9da, 0x000000000001597f,
+           0x0000000000007fb3, 0x0000000000000000, 0x0000000000010a7a,
+           0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+           0x000000000000bd22, 0x0000000000013e07, 0x0000000000003fcb,
+           0x0000000000012756, 0x0000000000000000, 0x00000000000032e9,
+           0x0000000000001ccf);
+};
+
+// Simple random test with similar values (masked)
+// The numbers are the same of TEST_CASE1
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  //                 -36.375,    56.438, -68.438, -32.969,   56.438,
+  //                 -5.816,   53.094, -29.875, -93.562, -90.750, -65.875,
+  //                 -91.062,   16.281, -77.938, -67.000, -51.844
+  VLOAD_16(v2, 0xd08c, 0x530e, 0xd447, 0xd01f, 0x530e, 0xc5d1, 0x52a3, 0xcf78,
+           0xd5d9, 0xd5ac, 0xd41e, 0xd5b1, 0x4c12, 0xd4df, 0xd430, 0xd27b);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfwcvt.xu.f.v v4, v2, v0.t");
+  //                           0,             56,              0, 0, 0, 0, 0, 0,
+  //                           0,              0,              0, 0, 0, 0, 0, 0
+  VCMP_U32(3, v4, 0x00000000, 0x00000038, 0x00000000, 0x00000000, 0x00000000,
+           0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+           0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+           0x00000000);
+
+  VSET(16, e32, m1);
+  //              -54444.973,   43481.863,   88447.461,   32690.551, -37979.809,
+  //              68218.094, -43036.512, -38011.395, -36599.363,   48418.234,
+  //              81414.820,   16330.853,   75606.320, -85030.219,   13033.059,
+  //              7375.421
+  VLOAD_32(v2, 0xc754acf9, 0x4729d9dd, 0x47acbfbb, 0x46ff651a, 0xc7145bcf,
+           0x47853d0c, 0xc7281c83, 0xc7147b65, 0xc70ef75d, 0x473d223c,
+           0x479f0369, 0x467f2b69, 0x4793ab29, 0xc7a6131c, 0x464ba43c,
+           0x45e67b5f);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfwcvt.xu.f.v v4, v2, v0.t");
+  //                                   0,                  43482, 0, 32691, 0,
+  //                                   68218,                      0, 0, 0,
+  //                                   48418,                      0, 16331, 0,
+  //                                   0,                      0, 7375
+  VCMP_U64(4, v4, 0x0000000000000000, 0x000000000000a9da, 0x0000000000000000,
+           0x0000000000007fb3, 0x0000000000000000, 0x0000000000010a7a,
+           0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+           0x000000000000bd22, 0x0000000000000000, 0x0000000000003fcb,
+           0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+           0x0000000000001ccf);
+};
+
+////////////////
+// vfwcvt.x.f //
+////////////////
+
+// Simple random test with similar values
+void TEST_CASE3(void) {
+  VSET(16, e16, m1);
+  //                 -55.656,    -23.391,     53.094, -0.356,   26.859, -81.938,
+  //                 63.625, -54.594, -36.375,   77.312,   73.188, -79.500,
+  //                 -22.047, -30.500,   33.375, -26.281
+  VLOAD_16(v2, 0xd2f5, 0xcdd9, 0x52a3, 0xb5b2, 0x4eb7, 0xd51f, 0x53f4, 0xd2d3,
+           0xd08c, 0x54d5, 0x5493, 0xd4f8, 0xcd83, 0xcfa0, 0x502c, 0xce92);
+  asm volatile("vfwcvt.x.f.v v4, v2");
+  //                         -56,            -23,             53, 0, 27, -82,
+  //                         64,            -55,            -36,             77,
+  //                         73,            -80,            -22,            -30,
+  //                         33,            -26
+  VCMP_U32(5, v4, 0xffffffc8, 0xffffffe9, 0x00000035, 0x00000000, 0x0000001b,
+           0xffffffae, 0x00000040, 0xffffffc9, 0xffffffdc, 0x0000004d,
+           0x00000049, 0xffffffb0, 0xffffffea, 0xffffffe2, 0x00000021,
+           0xffffffe6);
+
+  VSET(16, e32, m1);
+  //                  -22345.104,     -55208.160,   60155.754, -4924.268,
+  //                  -42337.285, -60609.004,   51795.328,   33876.547,
+  //                  -99812.922,   59419.867, -78706.844,   72266.555,
+  //                  -70664.008, -83501.727, -15981.749, -2004.535
+  VLOAD_32(v2, 0xc6ae9235, 0xc757a829, 0x476afbc1, 0xc599e225, 0xc7256149,
+           0xc76cc101, 0x474a5354, 0x4704548c, 0xc7c2f276, 0x47681bde,
+           0xc799b96c, 0x478d2547, 0xc78a0401, 0xc7a316dd, 0xc679b6ff,
+           0xc4fa9120);
+  asm volatile("vfwcvt.x.f.v v4, v2");
+  //                              -22345,                 -55208, 60156, -4924,
+  //                              -42337,                 -60609, 51795, 33877,
+  //                              -99813,                  59420, -78707, 72267,
+  //                              -70664,                 -83502, -15982, -2005
+  VCMP_U64(6, v4, 0xffffffffffffa8b7, 0xffffffffffff2858, 0x000000000000eafc,
+           0xffffffffffffecc4, 0xffffffffffff5a9f, 0xffffffffffff133f,
+           0x000000000000ca53, 0x0000000000008455, 0xfffffffffffe7a1b,
+           0x000000000000e81c, 0xfffffffffffecc8d, 0x0000000000011a4b,
+           0xfffffffffffeebf8, 0xfffffffffffeb9d2, 0xffffffffffffc192,
+           0xfffffffffffff82b);
+};
+
+// Simple random test with similar values (masked)
+// The numbers are the same of TEST_CASE1
+void TEST_CASE4(void) {
+  VSET(16, e16, m1);
+  //                 -55.656,    -23.391,   53.094, -0.356,   26.859,
+  //                 -81.938,   63.625, -54.594, -36.375,   77.312,   73.188,
+  //                 -79.500, -22.047, -30.500,   33.375, -26.281
+  VLOAD_16(v2, 0xd2f5, 0xcdd9, 0x52a3, 0xb5b2, 0x4eb7, 0xd51f, 0x53f4, 0xd2d3,
+           0xd08c, 0x54d5, 0x5493, 0xd4f8, 0xcd83, 0xcfa0, 0x502c, 0xce92);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfwcvt.x.f.v v4, v2, v0.t");
+  //                           0,            -23,              0, 0, 0, -82, 0,
+  //                           -55,              0,             77, 0, -80, 0,
+  //                           -30,              0,            -26
+  VCMP_U32(7, v4, 0x00000000, 0xffffffe9, 0x00000000, 0x00000000, 0x00000000,
+           0xffffffae, 0x00000000, 0xffffffc9, 0x00000000, 0x0000004d,
+           0x00000000, 0xffffffb0, 0x00000000, 0xffffffe2, 0x00000000,
+           0xffffffe6);
+
+  VSET(16, e32, m1);
+  //                  -22345.104,     -55208.160,   60155.754, -4924.268,
+  //                  -42337.285, -60609.004,   51795.328,   33876.547,
+  //                  -99812.922,   59419.867, -78706.844,   72266.555,
+  //                  -70664.008, -83501.727, -15981.749, -2004.535
+  VLOAD_32(v2, 0xc6ae9235, 0xc757a829, 0x476afbc1, 0xc599e225, 0xc7256149,
+           0xc76cc101, 0x474a5354, 0x4704548c, 0xc7c2f276, 0x47681bde,
+           0xc799b96c, 0x478d2547, 0xc78a0401, 0xc7a316dd, 0xc679b6ff,
+           0xc4fa9120);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfwcvt.x.f.v v4, v2, v0.t");
+  //                                   0,                 -55208, 0, -4924, 0,
+  //                                   -60609,                      0, 33877, 0,
+  //                                   59420,                      0, 72267, 0,
+  //                                   -83502,                      0, -2005
+  VCMP_U64(8, v4, 0x0000000000000000, 0xffffffffffff2858, 0x0000000000000000,
+           0xffffffffffffecc4, 0x0000000000000000, 0xffffffffffff133f,
+           0x0000000000000000, 0x0000000000008455, 0x0000000000000000,
+           0x000000000000e81c, 0x0000000000000000, 0x0000000000011a4b,
+           0x0000000000000000, 0xfffffffffffeb9d2, 0x0000000000000000,
+           0xfffffffffffff82b);
+};
+
+/////////////////////
+// vfwcvt.rtz.xu.f //
+/////////////////////
+
+// Simple random test with similar values
+void TEST_CASE5(void) {
+  VSET(16, e16, m1);
+  //                26304.000, -31056.000,   6932.000,   63168.000, -10920.000,
+  //                -38528.000,   inf, -inf, -1313.000,   52736.000,   inf,
+  //                -inf, -61024.000, -inf, -5672.000,   53824.000
+  VLOAD_16(v2, 0x766c, 0xf795, 0x6ec5, 0x7bb6, 0xf155, 0xf8b4, 0x7c00, 0xfc00,
+           0xe521, 0x7a70, 0x7c00, 0xfc00, 0xfb73, 0xfc00, 0xed8a, 0x7a92);
+  asm volatile("vfwcvt.rtz.xu.f.v v4, v2");
+  //                       26304,              0,           6932, 63168, 0, 0,
+  //                       0,              0,              0,          52736, 0,
+  //                       0,              0,              0,              0,
+  //                       53824
+  VCMP_U32(9, v4, 0x000066c0, 0x00000000, 0x00001b14, 0x0000f6c0, 0x00000000,
+           0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x0000ce00,
+           0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+           0x0000d240);
+
+  VSET(16, e32, m1);
+  //           -139027333120.000,   783549530112.000,   166903955456.000,
+  //           -848099999744.000, -671032279040.000, -402660294656.000,
+  //           -259808854016.000,   248555126784.000,   712853684224.000,
+  //           -492155797504.000, -448682098688.000, -916605566976.000,
+  //           67602378752.000,   519669350400.000,   569111478272.000,
+  //           -920229773312.000
+  VLOAD_32(v2, 0xd2017ab3, 0x53366f31, 0x521b7101, 0xd34576b3, 0xd31c3ca4,
+           0xd2bb80d9, 0xd271f742, 0x52677c29, 0x5325f964, 0xd2e52d8b,
+           0xd2d0ef13, 0xd35569f3, 0x517bd6a7, 0x52f1fd6a, 0x530481b0,
+           0xd35641f8);
+  asm volatile("vfwcvt.rtz.xu.f.v v4, v2");
+  //                                   0,           783549530112, 166903955456,
+  //                                   0,                      0, 0, 0,
+  //                                   248555126784,           712853684224, 0,
+  //                                   0,                      0, 67602378752,
+  //                                   519669350400,           569111478272, 0
+  VCMP_U64(10, v4, 0x0000000000000000, 0x000000b66f310000, 0x00000026dc404000,
+           0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+           0x0000000000000000, 0x00000039df0a4000, 0x000000a5f9640000,
+           0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+           0x0000000fbd6a7000, 0x00000078feb50000, 0x0000008481b00000,
+           0x0000000000000000);
+};
+
+// Simple random test with similar values (masked)
+// The numbers are the same of TEST_CASE1
+void TEST_CASE6(void) {
+  VSET(16, e16, m1);
+  //                26304.000, -31056.000,   6932.000,   63168.000, -10920.000,
+  //                -38528.000,   inf, -inf, -1313.000,   52736.000,   inf,
+  //                -inf, -61024.000, -inf, -5672.000,   53824.000
+  VLOAD_16(v2, 0x766c, 0xf795, 0x6ec5, 0x7bb6, 0xf155, 0xf8b4, 0x7c00, 0xfc00,
+           0xe521, 0x7a70, 0x7c00, 0xfc00, 0xfb73, 0xfc00, 0xed8a, 0x7a92);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfwcvt.rtz.xu.f.v v4, v2, v0.t");
+  //                           0,              0,              0, 63168, 0, 0,
+  //                           0,              0,              0, 52736, 0, 0,
+  //                           0,              0,              0,          53824
+  VCMP_U32(11, v4, 0x00000000, 0x00000000, 0x00000000, 0x0000f6c0, 0x00000000,
+           0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000ce00,
+           0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+           0x0000d240);
+
+  VSET(16, e32, m1);
+  //              -139027333120.000,   783549530112.000,   166903955456.000,
+  //              -848099999744.000, -671032279040.000, -402660294656.000,
+  //              -259808854016.000,   248555126784.000,   712853684224.000,
+  //              -492155797504.000, -448682098688.000, -916605566976.000,
+  //              67602378752.000,   519669350400.000,   569111478272.000,
+  //              -920229773312.000
+  VLOAD_32(v2, 0xd2017ab3, 0x53366f31, 0x521b7101, 0xd34576b3, 0xd31c3ca4,
+           0xd2bb80d9, 0xd271f742, 0x52677c29, 0x5325f964, 0xd2e52d8b,
+           0xd2d0ef13, 0xd35569f3, 0x517bd6a7, 0x52f1fd6a, 0x530481b0,
+           0xd35641f8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfwcvt.rtz.xu.f.v v4, v2, v0.t");
+  //                                   0,           783549530112, 0, 0, 0, 0, 0,
+  //                                   248555126784,                      0, 0,
+  //                                   0,                      0, 0,
+  //                                   519669350400,                      0, 0
+  VCMP_U64(12, v4, 0x0000000000000000, 0x000000b66f310000, 0x0000000000000000,
+           0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+           0x0000000000000000, 0x00000039df0a4000, 0x0000000000000000,
+           0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+           0x0000000000000000, 0x00000078feb50000, 0x0000000000000000,
+           0x0000000000000000);
+};
+
+////////////////////
+// vfwcvt.rtz.x.f //
+////////////////////
+
+// Simple random test with similar values
+void TEST_CASE7(void) {
+  VSET(16, e16, m1);
+  //                5.844,   36.219, -86.250,   20.406, -45.688,   13.961,
+  //                -96.562,   81.000, -32.594,   51.281,   80.750,
+  //                -17.750,   14.516,   58.000,   69.938, -94.688
+  VLOAD_16(v2, 0x45d8, 0x5087, 0xd564, 0x4d1a, 0xd1b6, 0x4afb, 0xd609, 0x5510,
+           0xd013, 0x5269, 0x550c, 0xcc70, 0x4b42, 0x5340, 0x545f, 0xd5eb);
+  asm volatile("vfwcvt.rtz.x.f.v v4, v2");
+  //                           5,             36,            -86, 20, -45, 13,
+  //                           -96,             81,            -32, 51, 80, -17,
+  //                           14,             58,             69, -94
+  VCMP_U32(13, v4, 0x00000005, 0x00000024, 0xffffffaa, 0x00000014, 0xffffffd3,
+           0x0000000d, 0xffffffa0, 0x00000051, 0xffffffe0, 0x00000033,
+           0x00000050, 0xffffffef, 0x0000000e, 0x0000003a, 0x00000045,
+           0xffffffa2);
+
+  VSET(16, e32, m1);
+  //                2116.345,  -810274979840.000, -5833.340, -6088.383,
+  //                -9260.508, -2389.850,   9361.639,   5574.592, -6825.026,
+  //                2473.934, -6756.971, -7155.075,   2251.162, -2899.548,
+  //                -3184.759, -1954.714
+  VLOAD_32(v2, 0x45044584, 0xd33ca827, 0xc5b64ab9, 0xc5be4311, 0xc610b208,
+           0xc5155d98, 0x4612468e, 0x45ae34bd, 0xc5d54835, 0x451a9ef1,
+           0xc5d327c5, 0xc5df9899, 0x450cb297, 0xc53538c6, 0xc5470c23,
+           0xc4f456dc);
+  asm volatile("vfwcvt.rtz.x.f.v v4, v2");
+  //                                2116,         -810274979840, -5833, -6088,
+  //                                -9260,                  -2389, 9361, 5574,
+  //                                -6825,                   2473, -6756, -7155,
+  //                                2251,                  -2899, -3184, -1954
+  VCMP_U64(14, v4, 0x0000000000000844, 0xffffff4357d90000, 0xffffffffffffe937,
+           0xffffffffffffe838, 0xffffffffffffdbd4, 0xfffffffffffff6ab,
+           0x0000000000002491, 0x00000000000015c6, 0xffffffffffffe557,
+           0x00000000000009a9, 0xffffffffffffe59c, 0xffffffffffffe40d,
+           0x00000000000008cb, 0xfffffffffffff4ad, 0xfffffffffffff390,
+           0xfffffffffffff85e);
+};
+
+// Simple random test with similar values (masked)
+// The numbers are the same of TEST_CASE1
+void TEST_CASE8(void) {
+  VSET(16, e16, m1);
+  //                5.844,   36.219, -86.250,   20.406, -45.688,   13.961,
+  //                -96.562,   81.000, -32.594,   51.281,   80.750,
+  //                -17.750,   14.516,   58.000,   69.938, -94.688
+  VLOAD_16(v2, 0x45d8, 0x5087, 0xd564, 0x4d1a, 0xd1b6, 0x4afb, 0xd609, 0x5510,
+           0xd013, 0x5269, 0x550c, 0xcc70, 0x4b42, 0x5340, 0x545f, 0xd5eb);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfwcvt.rtz.x.f.v v4, v2, v0.t");
+  //                           0,             36,              0, 20, 0, 13, 0,
+  //                           81,              0,             51, 0, -17, 0,
+  //                           58,              0,            -94
+  VCMP_U32(15, v4, 0x00000000, 0x00000024, 0x00000000, 0x00000014, 0x00000000,
+           0x0000000d, 0x00000000, 0x00000051, 0x00000000, 0x00000033,
+           0x00000000, 0xffffffef, 0x00000000, 0x0000003a, 0x00000000,
+           0xffffffa2);
+
+  VSET(16, e32, m1);
+  //                2116.345, -6652.860, -5833.340, -6088.383, -9260.508,
+  //                -2389.850,   9361.639,   5574.592, -6825.026,   2473.934,
+  //                -6756.971, -7155.075,   2251.162, -2899.548, -3184.759,
+  //                -1954.714
+  VLOAD_32(v2, 0x45044584, 0xc5cfe6e1, 0xc5b64ab9, 0xc5be4311, 0xc610b208,
+           0xc5155d98, 0x4612468e, 0x45ae34bd, 0xc5d54835, 0x451a9ef1,
+           0xc5d327c5, 0xc5df9899, 0x450cb297, 0xc53538c6, 0xc5470c23,
+           0xc4f456dc);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfwcvt.rtz.x.f.v v4, v2, v0.t");
+  //                                   0,                  -6652, 0, -6088, 0,
+  //                                   -2389,                      0, 5574, 0,
+  //                                   2473,                      0, -7155, 0,
+  //                                   -2899,                      0, -1954
+  VCMP_U64(16, v4, 0x0000000000000000, 0xffffffffffffe604, 0x0000000000000000,
+           0xffffffffffffe838, 0x0000000000000000, 0xfffffffffffff6ab,
+           0x0000000000000000, 0x00000000000015c6, 0x0000000000000000,
+           0x00000000000009a9, 0x0000000000000000, 0xffffffffffffe40d,
+           0x0000000000000000, 0xfffffffffffff4ad, 0x0000000000000000,
+           0xfffffffffffff85e);
+};
+
+/////////////////
+// vfwcvt.f.xu //
+/////////////////
+
+// Simple random test with similar values
+void TEST_CASE9(void) {
+  VSET(16, e16, m1);
+  //                    64656,       64687,       64823,         970, 543,
+  //                    65038,       65122,         966,         180, 389, 337,
+  //                    341,       65240,          51,       64922,       64676
+  VLOAD_16(v2, 0xfc90, 0xfcaf, 0xfd37, 0x03ca, 0x021f, 0xfe0e, 0xfe62, 0x03c6,
+           0x00b4, 0x0185, 0x0151, 0x0155, 0xfed8, 0x0033, 0xfd9a, 0xfca4);
+  asm volatile("vfwcvt.f.xu.v v4, v2");
+  //                   64656.000,      64687.000,      64823.000,      970.000,
+  //                   543.000,      65038.000,      65122.000,      966.000,
+  //                   180.000,      389.000,      337.000,      341.000,
+  //                   65240.000,      51.000,      64922.000,      64676.000
+  VCMP_U32(17, v4, 0x477c9000, 0x477caf00, 0x477d3700, 0x44728000, 0x4407c000,
+           0x477e0e00, 0x477e6200, 0x44718000, 0x43340000, 0x43c28000,
+           0x43a88000, 0x43aa8000, 0x477ed800, 0x424c0000, 0x477d9a00,
+           0x477ca400);
+
+  VSET(16, e32, m1);
+  //                            97144,          4294936082,               42555,
+  //                            4294893205,               55337, 4294948570,
+  //                            4294931792,          4294924170, 4294912208,
+  //                            4294947132,          4294903099, 4294944521,
+  //                            4294923920,          4294889958, 31133, 30359
+  VLOAD_32(v2, 0x00017b78, 0xffff8612, 0x0000a63b, 0xfffede95, 0x0000d829,
+           0xffffb6da, 0xffff7550, 0xffff578a, 0xffff28d0, 0xffffb13c,
+           0xffff053b, 0xffffa709, 0xffff5690, 0xfffed1e6, 0x0000799d,
+           0x00007697);
+  asm volatile("vfwcvt.f.xu.v v4, v2");
+  //                   97144.000,      4294936082.000,      42555.000,
+  //                   4294893205.000,      55337.000,      4294948570.000,
+  //                   4294931792.000,      4294924170.000,      4294912208.000,
+  //                   4294947132.000,      4294903099.000,      4294944521.000,
+  //                   4294923920.000,      4294889958.000,      31133.000,
+  //                   30359.000
+  VCMP_U64(18, v4, 0x40f7b78000000000, 0x41effff0c2400000, 0x40e4c76000000000,
+           0x41efffdbd2a00000, 0x40eb052000000000, 0x41effff6db400000,
+           0x41efffeeaa000000, 0x41efffeaf1400000, 0x41efffe51a000000,
+           0x41effff627800000, 0x41efffe0a7600000, 0x41effff4e1200000,
+           0x41efffead2000000, 0x41efffda3cc00000, 0x40de674000000000,
+           0x40dda5c000000000);
+};
+
+// Simple random test with similar values (masked)
+// The numbers are the same of TEST_CASE1
+void TEST_CASE10(void) {
+  VSET(16, e16, m1);
+  //                    64656,       64687,       64823,         970, 543,
+  //                    65038,       65122,         966,         180, 389, 337,
+  //                    341,       65240,          51,       64922,       64676
+  VLOAD_16(v2, 0xfc90, 0xfcaf, 0xfd37, 0x03ca, 0x021f, 0xfe0e, 0xfe62, 0x03c6,
+           0x00b4, 0x0185, 0x0151, 0x0155, 0xfed8, 0x0033, 0xfd9a, 0xfca4);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfwcvt.f.xu.v v4, v2, v0.t");
+  //                   0.000,      64687.000,      0.000,      970.000, 0.000,
+  //                   65038.000,      0.000,      966.000,      0.000, 389.000,
+  //                   0.000,      341.000,      0.000,      51.000,      0.000,
+  //                   64676.000
+  VCMP_U32(19, v4, 0x0, 0x477caf00, 0x0, 0x44728000, 0x0, 0x477e0e00, 0x0,
+           0x44718000, 0x0, 0x43c28000, 0x0, 0x43aa8000, 0x0, 0x424c0000, 0x0,
+           0x477ca400);
+
+  VSET(16, e32, m1);
+  //                            97144,          4294936082,               42555,
+  //                            4294893205,               55337, 4294948570,
+  //                            4294931792,          4294924170, 4294912208,
+  //                            4294947132,          4294903099, 4294944521,
+  //                            4294923920,          4294889958, 31133, 30359
+  VLOAD_32(v2, 0x00017b78, 0xffff8612, 0x0000a63b, 0xfffede95, 0x0000d829,
+           0xffffb6da, 0xffff7550, 0xffff578a, 0xffff28d0, 0xffffb13c,
+           0xffff053b, 0xffffa709, 0xffff5690, 0xfffed1e6, 0x0000799d,
+           0x00007697);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfwcvt.f.xu.v v4, v2, v0.t");
+  //                   0.000,      4294936082.000,      0.000, 4294893205.000,
+  //                   0.000,      4294948570.000,      0.000, 4294924170.000,
+  //                   0.000,      4294947132.000,      0.000, 4294944521.000,
+  //                   0.000,      4294889958.000,      0.000,      30359.000
+  VCMP_U64(20, v4, 0x0, 0x41effff0c2400000, 0x0, 0x41efffdbd2a00000, 0x0,
+           0x41effff6db400000, 0x0, 0x41efffeaf1400000, 0x0, 0x41effff627800000,
+           0x0, 0x41effff4e1200000, 0x0, 0x41efffda3cc00000, 0x0,
+           0x40dda5c000000000);
+};
+
+////////////////
+// vfwcvt.f.x //
+////////////////
+
+// Simple random test with similar values
+void TEST_CASE11(void) {
+  VSET(16, e16, m1);
+  //                     -263,        -943,         111,        -140, -792,
+  //                     -320,        -384,         250,        -308, 578, -830,
+  //                     -865,         908,         264,          93, 833
+  VLOAD_16(v2, 0xfef9, 0xfc51, 0x006f, 0xff74, 0xfce8, 0xfec0, 0xfe80, 0x00fa,
+           0xfecc, 0x0242, 0xfcc2, 0xfc9f, 0x038c, 0x0108, 0x005d, 0x0341);
+  asm volatile("vfwcvt.f.x.v v4, v2");
+  //                  -263.000,     -943.000,      111.000,     -140.000,
+  //                  -792.000,     -320.000,     -384.000,      250.000,
+  //                  -308.000,      578.000,     -830.000,     -865.000,
+  //                  908.000,      264.000,      93.000,      833.000
+  VCMP_U32(21, v4, 0xc3838000, 0xc46bc000, 0x42de0000, 0xc30c0000, 0xc4460000,
+           0xc3a00000, 0xc3c00000, 0x437a0000, 0xc39a0000, 0x44108000,
+           0xc44f8000, 0xc4584000, 0x44630000, 0x43840000, 0x42ba0000,
+           0x44504000);
+
+  VSET(16, e32, m1);
+  //                           -85277,               33391,               84804,
+  //                           -45155,              -68903,               19141,
+  //                           -10026,               87992,               13128,
+  //                           95737,              -70832,               43360,
+  //                           32471,                  51,               50027,
+  //                           -57346
+  VLOAD_32(v2, 0xfffeb2e3, 0x0000826f, 0x00014b44, 0xffff4f9d, 0xfffef2d9,
+           0x00004ac5, 0xffffd8d6, 0x000157b8, 0x00003348, 0x000175f9,
+           0xfffeeb50, 0x0000a960, 0x00007ed7, 0x00000033, 0x0000c36b,
+           0xffff1ffe);
+  asm volatile("vfwcvt.f.x.v v4, v2");
+  //                  -85277.000,      33391.000,      84804.000, -45155.000,
+  //                  -68903.000,      19141.000,     -10026.000, 87992.000,
+  //                  13128.000,      95737.000,     -70832.000,      43360.000,
+  //                  32471.000,      51.000,      50027.000,     -57346.000
+  VCMP_U64(22, v4, 0xc0f4d1d000000000, 0x40e04de000000000, 0x40f4b44000000000,
+           0xc0e60c6000000000, 0xc0f0d27000000000, 0x40d2b14000000000,
+           0xc0c3950000000000, 0x40f57b8000000000, 0x40c9a40000000000,
+           0x40f75f9000000000, 0xc0f14b0000000000, 0x40e52c0000000000,
+           0x40dfb5c000000000, 0x4049800000000000, 0x40e86d6000000000,
+           0xc0ec004000000000);
+};
+
+// Simple random test with similar values (masked)
+// The numbers are the same of TEST_CASE1
+void TEST_CASE12(void) {
+  VSET(16, e16, m1);
+  //                     -263,        -943,         111,        -140, -792,
+  //                     -320,        -384,         250,        -308, 578, -830,
+  //                     -865,         908,         264,          93, 833
+  VLOAD_16(v2, 0xfef9, 0xfc51, 0x006f, 0xff74, 0xfce8, 0xfec0, 0xfe80, 0x00fa,
+           0xfecc, 0x0242, 0xfcc2, 0xfc9f, 0x038c, 0x0108, 0x005d, 0x0341);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfwcvt.f.x.v v4, v2, v0.t");
+  //                   0.000,     -943.000,      0.000,     -140.000, 0.000,
+  //                   -320.000,      0.000,      250.000,      0.000, 578.000,
+  //                   0.000,     -865.000,      0.000,      264.000, 0.000,
+  //                   833.000
+  VCMP_U32(23, v4, 0x0, 0xc46bc000, 0x0, 0xc30c0000, 0x0, 0xc3a00000, 0x0,
+           0x437a0000, 0x0, 0x44108000, 0x0, 0xc4584000, 0x0, 0x43840000, 0x0,
+           0x44504000);
+
+  VSET(16, e32, m1);
+  //                           -85277,               33391,               84804,
+  //                           -45155,              -68903,               19141,
+  //                           -10026,               87992,               13128,
+  //                           95737,              -70832,               43360,
+  //                           32471,                  51,               50027,
+  //                           -57346
+  VLOAD_32(v2, 0xfffeb2e3, 0x0000826f, 0x00014b44, 0xffff4f9d, 0xfffef2d9,
+           0x00004ac5, 0xffffd8d6, 0x000157b8, 0x00003348, 0x000175f9,
+           0xfffeeb50, 0x0000a960, 0x00007ed7, 0x00000033, 0x0000c36b,
+           0xffff1ffe);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfwcvt.f.x.v v4, v2, v0.t");
+  //                   0.000,      33391.000,      0.000,     -45155.000, 0.000,
+  //                   19141.000,      0.000,      87992.000,      0.000,
+  //                   95737.000,      0.000,      43360.000,
+  //                   0.000,      51.000,      0.000,     -57346.000
+  VCMP_U64(24, v4, 0x0, 0x40e04de000000000, 0x0, 0xc0e60c6000000000, 0x0,
+           0x40d2b14000000000, 0x0, 0x40f57b8000000000, 0x0, 0x40f75f9000000000,
+           0x0, 0x40e52c0000000000, 0x0, 0x4049800000000000, 0x0,
+           0xc0ec004000000000);
+};
+
+////////////////
+// vfwcvt.f.f //
+////////////////
+
+// Simple random test with similar values
+void TEST_CASE13(void) {
+  VSET(16, e16, m1);
+  //                83.312, -83.188,   62.469,   94.812,   10.797, -13.070,
+  //                -9.039,   54.250, -92.188,   63.688, -32.875, -81.688,
+  //                -62.219, -78.250, -29.703, -1.137
+  VLOAD_16(v2, 0x5535, 0xd533, 0x53cf, 0x55ed, 0x4966, 0xca89, 0xc885, 0x52c8,
+           0xd5c3, 0x53f6, 0xd01c, 0xd51b, 0xd3c7, 0xd4e4, 0xcf6d, 0xbc8c);
+  asm volatile("vfwcvt.f.f.v v4, v2");
+  //                83.312, -83.188,   62.469,   94.812,   10.797, -13.070,
+  //                -9.039,   54.250, -92.188,   63.688, -32.875, -81.688,
+  //                -62.219, -78.250, -29.703, -1.137
+  VCMP_U32(25, v4, 0x42a6a000, 0xc2a66000, 0x4279e000, 0x42bda000, 0x412cc000,
+           0xc1512000, 0xc110a000, 0x42590000, 0xc2b86000, 0x427ec000,
+           0xc2038000, 0xc2a36000, 0xc278e000, 0xc29c8000, 0xc1eda000,
+           0xbf918000);
+
+  VSET(16, e32, m1);
+  //              -69280.273, -24625.789,   58970.254,   57986.516,   34031.016,
+  //              61977.340, -84548.211,   89658.250,   4958.967, -73911.508,
+  //              -83526.188, -59814.750,   71544.742,   93401.383,   79319.078,
+  //              4639.214
+  VLOAD_32(v2, 0xc7875023, 0xc6c06394, 0x47665a41, 0x47628284, 0x4704ef04,
+           0x47721957, 0xc7a5221b, 0x47af1d20, 0x459af7bc, 0xc7905bc1,
+           0xc7a32318, 0xc769a6c0, 0x478bbc5f, 0x47b66cb1, 0x479aeb8a,
+           0x4590f9b7);
+  asm volatile("vfwcvt.f.f.v v4, v2");
+  //              -69280.273, -24625.789,   58970.254,   57986.516,   34031.016,
+  //              61977.340, -84548.211,   89658.250,   4958.967, -73911.508,
+  //              -83526.188, -59814.750,   71544.742,   93401.383,   79319.078,
+  //              4639.214
+  VCMP_U64(26, v4, 0xc0f0ea0460000000, 0xc0d80c7280000000, 0x40eccb4820000000,
+           0x40ec505080000000, 0x40e09de080000000, 0x40ee432ae0000000,
+           0xc0f4a44360000000, 0x40f5e3a400000000, 0x40b35ef780000000,
+           0xc0f20b7820000000, 0xc0f4646300000000, 0xc0ed34d800000000,
+           0x40f1778be0000000, 0x40f6cd9620000000, 0x40f35d7140000000,
+           0x40b21f36e0000000);
+};
+
+// Simple random test with similar values (masked)
+// The numbers are the same of TEST_CASE1
+void TEST_CASE14(void) {
+  VSET(16, e16, m1);
+  //                83.312, -83.188,   62.469,   94.812,   10.797, -13.070,
+  //                -9.039,   54.250, -92.188,   63.688, -32.875, -81.688,
+  //                -62.219, -78.250, -29.703, -1.137
+  VLOAD_16(v2, 0x5535, 0xd533, 0x53cf, 0x55ed, 0x4966, 0xca89, 0xc885, 0x52c8,
+           0xd5c3, 0x53f6, 0xd01c, 0xd51b, 0xd3c7, 0xd4e4, 0xcf6d, 0xbc8c);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfwcvt.f.f.v v4, v2, v0.t");
+  //                0.000, -83.188,   0.000,   94.812,   0.000, -13.070, 0.000,
+  //                54.250,   0.000,   63.688,   0.000, -81.688,   0.000,
+  //                -78.250,   0.000, -1.137
+  VCMP_U32(27, v4, 0x0, 0xc2a66000, 0x0, 0x42bda000, 0x0, 0xc1512000, 0x0,
+           0x42590000, 0x0, 0x427ec000, 0x0, 0xc2a36000, 0x0, 0xc29c8000, 0x0,
+           0xbf918000);
+
+  VSET(16, e32, m1);
+  //              -69280.273, -24625.789,   58970.254,   57986.516,   34031.016,
+  //              61977.340, -84548.211,   89658.250,   4958.967, -73911.508,
+  //              -83526.188, -59814.750,   71544.742,   93401.383,   79319.078,
+  //              4639.214
+  VLOAD_32(v2, 0xc7875023, 0xc6c06394, 0x47665a41, 0x47628284, 0x4704ef04,
+           0x47721957, 0xc7a5221b, 0x47af1d20, 0x459af7bc, 0xc7905bc1,
+           0xc7a32318, 0xc769a6c0, 0x478bbc5f, 0x47b66cb1, 0x479aeb8a,
+           0x4590f9b7);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfwcvt.f.f.v v4, v2, v0.t");
+  //                0.000, -24625.789,   0.000,   57986.516,   0.000, 61977.340,
+  //                0.000,   89658.250,   0.000, -73911.508,   0.000,
+  //                -59814.750,   0.000,   93401.383,   0.000,   4639.214
+  VCMP_U64(28, v4, 0x0, 0xc0d80c7280000000, 0x0, 0x40ec505080000000, 0x0,
+           0x40ee432ae0000000, 0x0, 0x40f5e3a400000000, 0x0, 0xc0f20b7820000000,
+           0x0, 0xc0ed34d800000000, 0x0, 0x40f6cd9620000000, 0x0,
+           0x40b21f36e0000000);
+};
+
+int main(void) {
+  enable_vec();
+  enable_fp();
+
+  TEST_CASE1();
+  TEST_CASE2();
+
+  TEST_CASE3();
+  TEST_CASE4();
+
+  TEST_CASE5();
+  TEST_CASE6();
+
+  TEST_CASE7();
+  TEST_CASE8();
+
+  TEST_CASE9();
+  TEST_CASE10();
+
+  TEST_CASE11();
+  TEST_CASE12();
+
+  TEST_CASE13();
+  TEST_CASE14();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vfwmacc.c b/apps/riscv-tests/isa/rv64uv/vfwmacc.c
new file mode 100644
index 0000000..0ed2899
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vfwmacc.c
@@ -0,0 +1,351 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+//         Matteo Perotti <mperotti@iis.ee.ethz.ch>
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+// Simple random test with similar values
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  //               52.7812,  74.1875,  0.3564,  97.5000,  7.8477,  53.2188,
+  //               -26.4688, -48.1250, -32.9688,  7.8750,
+  //               -38.4375,  51.5625,  46.2188, -75.1875,  23.5625, -77.8125
+  VLOAD_16(v2, 0x5299, 0x54a3, 0x35b4, 0x5618, 0x47d9, 0x52a7, 0xce9e, 0xd204,
+           0xd01f, 0x47e0, 0xd0ce, 0x5272, 0x51c7, 0xd4b3, 0x4de4, 0xd4dd);
+  //               49.6875,  28.5312,  13.4766, -90.5625,  58.0000,
+  //               -63.8125,  49.0625,  0.3325,  30.8906,  11.2266, -93.9375,
+  //               -54.6875,  61.7500,  38.3438,  95.8125,  10.0938
+  VLOAD_16(v6, 0x5236, 0x4f22, 0x4abd, 0xd5a9, 0x5340, 0xd3fa, 0x5222, 0x3552,
+           0x4fb9, 0x499d, 0xd5df, 0xd2d6, 0x53b8, 0x50cb, 0x55fd, 0x490c);
+  //              -83.87223053, -48.34465408,  70.48658752, -1.26614821,
+  //              -24.13150024, -65.13838196,
+  //              0.84671319,  34.34510040,  72.80049896,
+  //              -86.23424530,  25.52654839, -68.44364929,  9.81109142,
+  //              -85.20966339, -81.00300598,  16.25512505
+  VLOAD_32(v4, 0xc2a7be95, 0xc24160ed, 0x428cf922, 0xbfa21125, 0xc1c10d50,
+           0xc28246da, 0x3f58c232, 0x42096162, 0x429199db, 0xc2ac77ef,
+           0x41cc365f, 0xc288e326, 0x411cfa3b, 0xc2aa6b59, 0xc2a2018a,
+           0x41820a7f);
+  asm volatile("vfwmacc.vv v4, v2, v6");
+  //               2538.69604492,  2068.31738281,  75.29024506, -8831.11035156,
+  //               431.03256226, -3461.15991211, -1297.77636719,  18.34259796,
+  //               -945.62481689,  2.17493439,  3636.24926758, -2888.26782227,
+  //               2863.81884766, -2968.18041992,  2176.57910156, -769.16479492
+  VCMP_U32(1, v4, 0x451eab23, 0x45014514, 0x4296949b, 0xc609fc71, 0x43d7842b,
+           0xc558528f, 0xc4a238d8, 0x4192bda4, 0xc46c67fd, 0x400b3220,
+           0x456343fd, 0xc5348449, 0x4532fd1a, 0xc53982e3, 0x45080944,
+           0xc4404a8c);
+
+  VSET(16, e32, m1);
+  //              -3306.98510742, -33314.88281250,  64578.31250000,
+  //              11648.08203125, -92704.16406250,  33998.11328125,
+  //              23406.90429688,  44169.36718750, -1206.53601074,
+  //              4568.00048828, -89687.13281250,  47865.25781250,
+  //              -72205.21875000,  40772.06640625,  95904.72656250,
+  //              96043.19531250
+  VLOAD_32(v2, 0xc54eafc3, 0xc70222e2, 0x477c4250, 0x46360054, 0xc7b51015,
+           0x4704ce1d, 0x46b6ddcf, 0x472c895e, 0xc496d127, 0x458ec001,
+           0xc7af2b91, 0x473af942, 0xc78d069c, 0x471f4411, 0x47bb505d,
+           0x47bb9599);
+  //              -52385.05468750, -31301.09960938,  1862.59667969,
+  //              86344.56250000,  9560.06835938, -93766.92187500,
+  //              -68756.87500000,  42627.23046875, -89604.89062500,
+  //              -47420.98437500, -40235.07421875,  44342.39453125,
+  //              90261.61718750,  76035.55468750, -92912.59375000,
+  //              40474.20703125
+  VLOAD_32(v6, 0xc74ca10e, 0xc6f48a33, 0x44e8d318, 0x47a8a448, 0x46156046,
+           0xc7b72376, 0xc7864a70, 0x4726833b, 0xc7af0272, 0xc7393cfc,
+           0xc71d2b13, 0x472d3665, 0x47b04acf, 0x479481c7, 0xc7b5784c,
+           0x471e1a35);
+  //              -10044.0368110413110116,  13040.9349537673260784,
+  //              88916.1136409099854063,  79168.4367756713472772,
+  //              21611.0950133731239475, -26455.6752808090968756,
+  //              5979.6755084589240141, -99733.4556307629245566,
+  //              85141.1192070578690618, -87838.0155233480472816,
+  //              53604.5772563865466509, -30101.3490022116457112,
+  //              80638.7360704737366177, -75019.8948306038219016,
+  //              63887.5576457676361315,  1225.3713199536578031
+  VLOAD_64(v4, 0xc0c39e04b6396548, 0x40c97877ac90a6f8, 0x40f5b541d179217e,
+           0x40f35406fd087c82, 0x40d51ac614b2f890, 0xc0d9d5eb37ccffac,
+           0x40b75bacee1f5340, 0xc0f859574a437b9d, 0x40f4c951e845a8f0,
+           0xc0f571e03f956903, 0x40ea2c9278e262b4, 0xc0dd6556560d5f50,
+           0x40f3afebc6f1d544, 0xc0f250be5139e52e, 0x40ef31f1d83befd8,
+           0x4093257c3b4c4540);
+  asm volatile("vfwmacc.vv v4, v2, v6");
+  //               173226551.6662319302558899,  1042805506.3236714601516724,
+  //               120372266.5559626817703247,  1005827715.3891682624816895,
+  //               -886236534.5412018299102783, -3187924887.6156492233276367,
+  //               -1609379613.2016887664794922,  1882718061.3047757148742676,
+  //               108196668.3968845903873444, -216706917.7953008711338043,
+  //               3608622049.7550821304321289,  2122430044.9128692150115967,
+  //               -6517279175.0161266326904297,  3100051665.0599727630615234,
+  //               -8910693010.2487506866455078,  3887273396.3922243118286133
+  VCMP_U64(2, v4, 0x41a4a6746f551c5a, 0x41cf13f981296e11, 0x419cb2f0aa394e48,
+           0x41cdf9db41b1d044, 0xc1ca6972bb45461a, 0xc1e7c07bf2f3b366,
+           0xc1d7fb4bc74ce878, 0x41dc0dffdb538172, 0x4199cbccf19668ea,
+           0xc1a9d55ecb9731ad, 0x41eae2e67c3829a2, 0x41dfa06d973a6c73,
+           0xc1f8475c9c70420e, 0x41e718e11a21eb4c, 0xc20098f31491fd71,
+           0x41ecf662b68c8d1a);
+};
+
+// Simple random test with similar values (masked)
+// The numbers are the same of TEST_CASE1
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  //               52.7812,  74.1875,  0.3564,  97.5000,  7.8477,  53.2188,
+  //               -26.4688, -48.1250, -32.9688,  7.8750,
+  //               -38.4375,  51.5625,  46.2188, -75.1875,  23.5625, -77.8125
+  VLOAD_16(v2, 0x5299, 0x54a3, 0x35b4, 0x5618, 0x47d9, 0x52a7, 0xce9e, 0xd204,
+           0xd01f, 0x47e0, 0xd0ce, 0x5272, 0x51c7, 0xd4b3, 0x4de4, 0xd4dd);
+  //               49.6875,  28.5312,  13.4766, -90.5625,  58.0000,
+  //               -63.8125,  49.0625,  0.3325,  30.8906,  11.2266, -93.9375,
+  //               -54.6875,  61.7500,  38.3438,  95.8125,  10.0938
+  VLOAD_16(v6, 0x5236, 0x4f22, 0x4abd, 0xd5a9, 0x5340, 0xd3fa, 0x5222, 0x3552,
+           0x4fb9, 0x499d, 0xd5df, 0xd2d6, 0x53b8, 0x50cb, 0x55fd, 0x490c);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //              -83.87223053, -48.34465408,  70.48658752, -1.26614821,
+  //              -24.13150024, -65.13838196,
+  //              0.84671319,  34.34510040,  72.80049896,
+  //              -86.23424530,  25.52654839, -68.44364929,  9.81109142,
+  //              -85.20966339, -81.00300598,  16.25512505
+  VLOAD_32(v4, 0xc2a7be95, 0xc24160ed, 0x428cf922, 0xbfa21125, 0xc1c10d50,
+           0xc28246da, 0x3f58c232, 0x42096162, 0x429199db, 0xc2ac77ef,
+           0x41cc365f, 0xc288e326, 0x411cfa3b, 0xc2aa6b59, 0xc2a2018a,
+           0x41820a7f);
+  asm volatile("vfwmacc.vv v4, v2, v6, v0.t");
+  //              -83.87223053,  2068.31738281,  70.48658752, -8831.11035156,
+  //              -24.13150024, -3461.15991211,
+  //              0.84671319,  18.34259796,  72.80049896,  2.17493439,  25.52654839,
+  //              -2888.26782227,  9.81109142, -2968.18041992, -81.00300598,
+  //              -769.16479492
+  VCMP_U32(3, v4, 0xc2a7be95, 0x45014514, 0x428cf922, 0xc609fc71, 0xc1c10d50,
+           0xc558528f, 0x3f58c232, 0x4192bda4, 0x429199db, 0x400b3220,
+           0x41cc365f, 0xc5348449, 0x411cfa3b, 0xc53982e3, 0xc2a2018a,
+           0xc4404a8c);
+
+  VSET(16, e32, m1);
+  //              -3306.98510742, -33314.88281250,  64578.31250000,
+  //              11648.08203125, -92704.16406250,  33998.11328125,
+  //              23406.90429688,  44169.36718750, -1206.53601074,
+  //              4568.00048828, -89687.13281250,  47865.25781250,
+  //              -72205.21875000,  40772.06640625,  95904.72656250,
+  //              96043.19531250
+  VLOAD_32(v2, 0xc54eafc3, 0xc70222e2, 0x477c4250, 0x46360054, 0xc7b51015,
+           0x4704ce1d, 0x46b6ddcf, 0x472c895e, 0xc496d127, 0x458ec001,
+           0xc7af2b91, 0x473af942, 0xc78d069c, 0x471f4411, 0x47bb505d,
+           0x47bb9599);
+  //              -52385.05468750, -31301.09960938,  1862.59667969,
+  //              86344.56250000,  9560.06835938, -93766.92187500,
+  //              -68756.87500000,  42627.23046875, -89604.89062500,
+  //              -47420.98437500, -40235.07421875,  44342.39453125,
+  //              90261.61718750,  76035.55468750, -92912.59375000,
+  //              40474.20703125
+  VLOAD_32(v6, 0xc74ca10e, 0xc6f48a33, 0x44e8d318, 0x47a8a448, 0x46156046,
+           0xc7b72376, 0xc7864a70, 0x4726833b, 0xc7af0272, 0xc7393cfc,
+           0xc71d2b13, 0x472d3665, 0x47b04acf, 0x479481c7, 0xc7b5784c,
+           0x471e1a35);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //              -10044.0368110413110116,  13040.9349537673260784,
+  //              88916.1136409099854063,  79168.4367756713472772,
+  //              21611.0950133731239475, -26455.6752808090968756,
+  //              5979.6755084589240141, -99733.4556307629245566,
+  //              85141.1192070578690618, -87838.0155233480472816,
+  //              53604.5772563865466509, -30101.3490022116457112,
+  //              80638.7360704737366177, -75019.8948306038219016,
+  //              63887.5576457676361315,  1225.3713199536578031
+  VLOAD_64(v4, 0xc0c39e04b6396548, 0x40c97877ac90a6f8, 0x40f5b541d179217e,
+           0x40f35406fd087c82, 0x40d51ac614b2f890, 0xc0d9d5eb37ccffac,
+           0x40b75bacee1f5340, 0xc0f859574a437b9d, 0x40f4c951e845a8f0,
+           0xc0f571e03f956903, 0x40ea2c9278e262b4, 0xc0dd6556560d5f50,
+           0x40f3afebc6f1d544, 0xc0f250be5139e52e, 0x40ef31f1d83befd8,
+           0x4093257c3b4c4540);
+  asm volatile("vfwmacc.vv v4, v2, v6, v0.t");
+  //              -10044.0368110413110116,  1042805506.3236714601516724,
+  //              88916.1136409099854063,  1005827715.3891682624816895,
+  //              21611.0950133731239475, -3187924887.6156492233276367,
+  //              5979.6755084589240141,  1882718061.3047757148742676,
+  //              85141.1192070578690618, -216706917.7953008711338043,
+  //              53604.5772563865466509,  2122430044.9128692150115967,
+  //              80638.7360704737366177,  3100051665.0599727630615234,
+  //              63887.5576457676361315,  3887273396.3922243118286133
+  VCMP_U64(4, v4, 0xc0c39e04b6396548, 0x41cf13f981296e11, 0x40f5b541d179217e,
+           0x41cdf9db41b1d044, 0x40d51ac614b2f890, 0xc1e7c07bf2f3b366,
+           0x40b75bacee1f5340, 0x41dc0dffdb538172, 0x40f4c951e845a8f0,
+           0xc1a9d55ecb9731ad, 0x40ea2c9278e262b4, 0x41dfa06d973a6c73,
+           0x40f3afebc6f1d544, 0x41e718e11a21eb4c, 0x40ef31f1d83befd8,
+           0x41ecf662b68c8d1a);
+};
+
+// Simple random test with similar values (vector-scalar)
+void TEST_CASE3(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //              -15.3750,  11.9375,
+  //              -31.7656,  27.0625,  3.0684,  71.2500,  63.2500, -95.6875,
+  //              -62.0625, -27.7344,  55.5312, -62.1875, -42.1875,
+  //              -95.3125,  27.1406, -16.9219
+  VLOAD_16(v2, 0xcbb0, 0x49f8, 0xcff1, 0x4ec4, 0x4223, 0x5474, 0x53e8, 0xd5fb,
+           0xd3c2, 0xceef, 0x52f1, 0xd3c6, 0xd146, 0xd5f5, 0x4ec9, 0xcc3b);
+  //                              32.2812
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0x5009);
+  //              -70.22966003,  68.36327362, -69.75650787, -92.51078796,
+  //              -53.56798553,
+  //              -92.09814453,  92.33961487,  42.48206329,  99.15431976,
+  //              -5.94871950, -55.92549133,  59.99367523, -45.05080032,
+  //              -68.93397522,  55.13935089, -80.23659515
+  VLOAD_32(v4, 0xc28c7596, 0x4288b9ff, 0xc28b8355, 0xc2b90586, 0xc256459e,
+           0xc2b83240, 0x42b8ade2, 0x4229eda2, 0x42c64f03, 0xc0be5be9,
+           0xc25fb3b4, 0x426ff986, 0xc2343405, 0xc289de32, 0x425c8eb2,
+           0xc2a07923);
+  asm volatile("vfwmacc.vf v4, %[A], v2" ::[A] "f"(dscalar_16));
+  //              -566.55389404,  453.72070312, -1095.19055176,
+  //              781.10052490,  45.48249054,  2207.94091797,  2134.12866211,
+  //              -3046.42993164, -1904.30078125, -901.24902344,  1736.69262695,
+  //              -1947.49658203, -1406.91601562, -3145.74072266,  931.27264404,
+  //              -626.49584961
+  VCMP_U32(5, v4, 0xc40da373, 0x43e2dc40, 0xc488e619, 0x4443466f, 0x4235ee12,
+           0x4509ff0e, 0x4505620f, 0xc53e66e1, 0xc4ee09a0, 0xc4614ff0,
+           0x44d9162a, 0xc4f36fe4, 0xc4afdd50, 0xc5449bda, 0x4468d173,
+           0xc41c9fbc);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //              -260866.17187500, -221967.43750000, -907157.25000000,
+  //              754760.87500000, -585546.12500000,  260611.84375000,
+  //              -768453.25000000, -117569.82812500, -469705.78125000,
+  //              775094.50000000,  533114.81250000, -798136.87500000,
+  //              66693.82812500,  246179.67187500,  728220.87500000,
+  //              -749270.75000000
+  VLOAD_32(v2, 0xc87ec08b, 0xc858c3dc, 0xc95d7954, 0x4938448e, 0xc90ef4a2,
+           0x487e80f6, 0xc93b9c54, 0xc7e5a0ea, 0xc8e55939, 0x493d3b68,
+           0x490227ad, 0xc942db8e, 0x478242ea, 0x487068eb, 0x4931c9ce,
+           0xc936ed6c);
+  //                              -164832.20312500
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0xc820f80d);
+  //              -730249.9193813583115116, -885955.2111547881504521,
+  //              -739704.0702666083816439,  991252.9466537751723081,
+  //              -543412.1947198503185064,  859135.3883249030914158,
+  //              862259.4763332824222744,  331294.3916525302920491,
+  //              936699.0835190876387060, -813722.4244660194963217,
+  //              -602138.5575914122164249,  253718.7884360067546368,
+  //              7255.4825419568223879,  957493.0229552322998643,
+  //              -446793.8022573012858629, -757660.7323241395642981
+  VLOAD_64(v4, 0xc1264913d6b92745, 0xc12b09866c1c7afb, 0xc12692f023f9fc22,
+           0x412e4029e4afcdba, 0xc120956863b251fa, 0x412a37fec6d2858e,
+           0x412a5066f3e1f4bc, 0x41143879910d5c64, 0x412c95f62ac3038c,
+           0xc128d534d9539c30, 0xc12260351d7c9f20, 0x410ef8b64eb78980,
+           0x40bc577b87dea380, 0x412d386a0bc0c9c8, 0xc11b45273582f020,
+           0xc1271f3976f3308b);
+  asm volatile("vfwmacc.vf v4, %[A], v2" ::[A] "f"(dscalar_32));
+  //               42998415581.0217819213867188,  36586495789.9245910644531250,
+  //               149527988394.2461547851562500,
+  //               -124407906605.8560791015625000, 96516314402.8619232177734375,
+  //               -42956365230.3924331665039062, 126666704455.5427398681640625,
+  //               19379625085.2629890441894531,  77423575443.0703430175781250,
+  //               -127761347787.4947814941406250,
+  //               -87875091201.5038757324218750, 131558913220.3411712646484375,
+  //               -10993283369.2012958526611328, -40577380186.7228927612304688,
+  //               -120034697981.6674957275390625, 123503190798.8887634277343750
+  VCMP_U64(6, v4, 0x422405cf81ba0b27, 0x422109733e5bd964, 0x4241684804551f82,
+           0xc23cf74a012ddb28, 0x423678d21522dca7, 0xc22400cc3b5cc8ed,
+           0x423d7dec86478af1, 0x42120c7671f50d4d, 0x423206ce01931202,
+           0xc23dbf2b74cb7eaa, 0xc23475c37b0180fe, 0x423ea185b4c45757,
+           0xc2047a0189499c41, 0xc222e5335eb5721f, 0xc23bf2a022fdaae1,
+           0x423cc15d230ee386);
+};
+
+// Simple random test with similar values (vector-scalar) (masked)
+void TEST_CASE4(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //               -15.3750,  11.9375,
+  //               -31.7656,  27.0625,  3.0684,  71.2500,  63.2500, -95.6875,
+  //               -62.0625, -27.7344,  55.5312, -62.1875, -42.1875,
+  //               -95.3125,  27.1406, -16.9219
+  VLOAD_16(v2, 0xcbb0, 0x49f8, 0xcff1, 0x4ec4, 0x4223, 0x5474, 0x53e8, 0xd5fb,
+           0xd3c2, 0xceef, 0x52f1, 0xd3c6, 0xd146, 0xd5f5, 0x4ec9, 0xcc3b);
+  //                              32.2812
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0x5009);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //               -70.22966003,  68.36327362, -69.75650787, -92.51078796,
+  //               -53.56798553,
+  //               -92.09814453,  92.33961487,  42.48206329,  99.15431976,
+  //               -5.94871950, -55.92549133,  59.99367523, -45.05080032,
+  //               -68.93397522,  55.13935089, -80.23659515
+  VLOAD_32(v4, 0xc28c7596, 0x4288b9ff, 0xc28b8355, 0xc2b90586, 0xc256459e,
+           0xc2b83240, 0x42b8ade2, 0x4229eda2, 0x42c64f03, 0xc0be5be9,
+           0xc25fb3b4, 0x426ff986, 0xc2343405, 0xc289de32, 0x425c8eb2,
+           0xc2a07923);
+  asm volatile("vfwmacc.vf v4, %[A], v2, v0.t" ::[A] "f"(dscalar_16));
+  //               -70.22966003,  453.72070312, -69.75650787,  781.10052490,
+  //               -53.56798553,  2207.94091797,  92.33961487,
+  //               -3046.42993164,  99.15431976, -901.24902344, -55.92549133,
+  //               -1947.49658203, -45.05080032, -3145.74072266,  55.13935089,
+  //               -626.49584961
+  VCMP_U32(7, v4, 0xc28c7596, 0x43e2dc40, 0xc28b8355, 0x4443466f, 0xc256459e,
+           0x4509ff0e, 0x42b8ade2, 0xc53e66e1, 0x42c64f03, 0xc4614ff0,
+           0xc25fb3b4, 0xc4f36fe4, 0xc2343405, 0xc5449bda, 0x425c8eb2,
+           0xc41c9fbc);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //               -260866.17187500, -221967.43750000, -907157.25000000,
+  //               754760.87500000, -585546.12500000,  260611.84375000,
+  //               -768453.25000000, -117569.82812500, -469705.78125000,
+  //               775094.50000000,  533114.81250000, -798136.87500000,
+  //               66693.82812500,  246179.67187500,  728220.87500000,
+  //               -749270.75000000
+  VLOAD_32(v2, 0xc87ec08b, 0xc858c3dc, 0xc95d7954, 0x4938448e, 0xc90ef4a2,
+           0x487e80f6, 0xc93b9c54, 0xc7e5a0ea, 0xc8e55939, 0x493d3b68,
+           0x490227ad, 0xc942db8e, 0x478242ea, 0x487068eb, 0x4931c9ce,
+           0xc936ed6c);
+  //                              -164832.20312500
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0xc820f80d);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //               -730249.9193813583115116, -885955.2111547881504521,
+  //               -739704.0702666083816439,  991252.9466537751723081,
+  //               -543412.1947198503185064,  859135.3883249030914158,
+  //               862259.4763332824222744,  331294.3916525302920491,
+  //               936699.0835190876387060, -813722.4244660194963217,
+  //               -602138.5575914122164249,  253718.7884360067546368,
+  //               7255.4825419568223879,  957493.0229552322998643,
+  //               -446793.8022573012858629, -757660.7323241395642981
+  VLOAD_64(v4, 0xc1264913d6b92745, 0xc12b09866c1c7afb, 0xc12692f023f9fc22,
+           0x412e4029e4afcdba, 0xc120956863b251fa, 0x412a37fec6d2858e,
+           0x412a5066f3e1f4bc, 0x41143879910d5c64, 0x412c95f62ac3038c,
+           0xc128d534d9539c30, 0xc12260351d7c9f20, 0x410ef8b64eb78980,
+           0x40bc577b87dea380, 0x412d386a0bc0c9c8, 0xc11b45273582f020,
+           0xc1271f3976f3308b);
+  asm volatile("vfwmacc.vf v4, %[A], v2, v0.t" ::[A] "f"(dscalar_32));
+  //               -730249.9193813583115116,  36586495789.9245910644531250,
+  //               -739704.0702666083816439, -124407906605.8560791015625000,
+  //               -543412.1947198503185064, -42956365230.3924331665039062,
+  //               862259.4763332824222744,  19379625085.2629890441894531,
+  //               936699.0835190876387060, -127761347787.4947814941406250,
+  //               -602138.5575914122164249,  131558913220.3411712646484375,
+  //               7255.4825419568223879, -40577380186.7228927612304688,
+  //               -446793.8022573012858629,  123503190798.8887634277343750
+  VCMP_U64(8, v4, 0xc1264913d6b92745, 0x422109733e5bd964, 0xc12692f023f9fc22,
+           0xc23cf74a012ddb28, 0xc120956863b251fa, 0xc22400cc3b5cc8ed,
+           0x412a5066f3e1f4bc, 0x42120c7671f50d4d, 0x412c95f62ac3038c,
+           0xc23dbf2b74cb7eaa, 0xc12260351d7c9f20, 0x423ea185b4c45757,
+           0x40bc577b87dea380, 0xc222e5335eb5721f, 0xc11b45273582f020,
+           0x423cc15d230ee386);
+};
+
+int main(void) {
+  enable_vec();
+  enable_fp();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vfwmsac.c b/apps/riscv-tests/isa/rv64uv/vfwmsac.c
new file mode 100644
index 0000000..d38bb1c
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vfwmsac.c
@@ -0,0 +1,353 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+//         Matteo Perotti <mperotti@iis.ee.ethz.ch>
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+// Simple random test with similar values
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  //              -93.0000, -55.1250, -68.5625,  76.3125, -61.2188,  48.9375,
+  //              -56.3125,  71.0000, -74.5625, -38.7188,
+  //              -50.3438,  93.3750,  80.2500, -7.4141,  93.8125,  83.1875
+  VLOAD_16(v2, 0xd5d0, 0xd2e4, 0xd449, 0x54c5, 0xd3a7, 0x521e, 0xd30a, 0x5470,
+           0xd4a9, 0xd0d7, 0xd24b, 0x55d6, 0x5504, 0xc76a, 0x55dd, 0x5533);
+  //              -60.0312, -31.7188, -74.2500, -0.9077,  30.4844, -56.2500,
+  //              -4.8320,  34.2812,  66.6875,  37.9375,  78.1875,  5.6094,
+  //              -81.8125,  67.6250,  29.4531, -64.9375
+  VLOAD_16(v6, 0xd381, 0xcfee, 0xd4a4, 0xbb43, 0x4f9f, 0xd308, 0xc4d5, 0x5049,
+           0x542b, 0x50be, 0x54e3, 0x459c, 0xd51d, 0x543a, 0x4f5d, 0xd40f);
+  //               31.29529381, -66.12346649,
+  //               -48.59321213,  21.66906929,  92.08473206,  1.95985305,
+  //               -96.55027771,  77.65225220, -82.48660278,
+  //               -35.32508850,  42.91923141,
+  //               -76.65069580,  25.13817024,  72.89311981,  21.44047737,  69.71634674
+  VLOAD_32(v4, 0x41fa5cc3, 0xc2843f37, 0xc2425f73, 0x41ad5a41, 0x42b82b62,
+           0x3ffadc77, 0xc2c119be, 0x429b4df4, 0xc2a4f924, 0xc20d4ce4,
+           0x422bad4b, 0xc2994d28, 0x41c91af9, 0x4291c947, 0x41ab8619,
+           0x428b6ec5);
+  asm volatile("vfwmsac.vv v4, v2, v6");
+  //               5551.61083984,  1814.61950684,  5139.35888672, -90.93905640,
+  //               -1958.30004883, -2754.69433594,  368.65405273, 2356.31640625,
+  //               -4889.89990234, -1433.56750488, -3979.17114258, 600.42608643,
+  //               -6590.59130859, -574.26910400,  2741.63085938, -5471.70458984
+  VCMP_U32(1, v4, 0x45ad7ce3, 0x44e2d3d3, 0x45a09adf, 0xc2b5e0cc, 0xc4f4c99a,
+           0xc52c2b1c, 0x43b853b8, 0x45134510, 0xc598cf33, 0xc4b33229,
+           0xc578b2bd, 0x44161b45, 0xc5cdf4bb, 0xc40f9139, 0x452b5a18,
+           0xc5aafda3);
+
+  VSET(16, e32, m1);
+  //              -71423.96093750, -46625.21875000, -59851.39453125,
+  //              -43461.99218750, -10255.72753906,  37671.59765625,
+  //              96842.05468750,  33293.05859375,  27126.79296875,
+  //              -27343.42187500,  26815.15429688,  28654.72070312,
+  //              -5699.91699219,  70582.03906250, -5936.72802734,
+  //              43479.90234375
+  VLOAD_32(v2, 0xc78b7ffb, 0xc7362138, 0xc769cb65, 0xc729c5fe, 0xc6203ee9,
+           0x47132799, 0x47bd2507, 0x47020d0f, 0x46d3ed96, 0xc6d59ed8,
+           0x46d17e4f, 0x46dfdd71, 0xc5b21f56, 0x4789db05, 0xc5b985d3,
+           0x4729d7e7);
+  //               93657.15625000, -28369.10156250, -42169.91406250,
+  //               -21377.95507812,  16308.38183594,  64517.84375000,
+  //               -12469.71679688, -76994.53125000, -33687.83593750,
+  //               -84006.54687500,  31506.48437500,  2731.77905273,
+  //               -20272.41992188,  53550.01953125, -85441.62500000,
+  //               -33418.07031250
+  VLOAD_32(v6, 0x47b6ec94, 0xc6dda234, 0xc724b9ea, 0xc6a703e9, 0x467ed187,
+           0x477c05d8, 0xc642d6de, 0xc7966144, 0xc70397d6, 0xc7a41346,
+           0x46f624f8, 0x452abc77, 0xc69e60d7, 0x47512e05, 0xc7a6e0d0,
+           0xc7028a12);
+  //               15054.1952512034331448, -39042.3922682931588497,
+  //               -83554.3539477824524511,  35787.9235785690543707,
+  //               -34715.2784411938628182,  35880.5352577352605294,
+  //               -52433.9701052222590079, -40831.3148960549369804,
+  //               -3569.6808186589187244,  77018.1414445060363505,
+  //               58906.1301468654128257, -84146.7844421620393405,
+  //               -23969.5482366856886074,  92255.7186088700836990,
+  //               -35519.3091108352309675, -65623.9480113173485734
+  VLOAD_64(v4, 0x40cd6718fdfdcea0, 0xc0e3104c8d763c4c, 0xc0f46625a9c52662,
+           0x40e1797d8df4a4ac, 0xc0e0f368e8fd81b0, 0x40e1851120d4d47c,
+           0xc0e99a3f0b1a1b69, 0xc0e3efea13a0e433, 0xc0abe35c94436520,
+           0x40f2cda2435b507a, 0x40ecc3442a29c254, 0xc0f48b2c8d133979,
+           0xc0d76863164f52e0, 0x40f685fb7f6c03ba, 0xc0e157e9e43c6805,
+           0xc0f0057f2b0dea44);
+  asm volatile("vfwmsac.vv v4, v2, v6");
+  //              -6689380123.7125854492187500,  1322754608.4847974777221680,
+  //              2524011718.2575426101684570,  929092728.6666160821914673,
+  //              -167219605.4339296817779541,  2430454370.8635458946228027,
+  //              -1207540562.0105009078979492, -2563342608.9896693229675293,
+  //              -913839381.3609598875045776,  2296949433.3236432075500488,
+  //              844792333.7375594377517700,  78362512.5631930530071259,
+  //              115575080.3336923867464066,  3779577314.6337165832519531,
+  //              507279209.1484052538871765, -1452948809.7560596466064453
+  VCMP_U64(2, v4, 0xc1f8eb7d71bb66c0, 0x41d3b5e88c1f06ec, 0x41e2ce2b98c83dca,
+           0x41cbb06a3c5553ad, 0xc1a3ef232ade2c08, 0x41e21bb94c5ba22b,
+           0xc1d1fe66d480ac0c, 0xc1e31930221fab5f, 0xc1cb3c0a8aae33ef,
+           0x41e11d15572a5b49, 0x41c92d4106de6859, 0x4192aede4240b5ae,
+           0x419b8e24a155b375, 0x41ec28f8bc544768, 0x41be3c776925fde3,
+           0xc1d5a68f52706348);
+};
+
+// Simple random test with similar values (masked)
+// The numbers are the same of TEST_CASE1
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  //              -93.0000, -55.1250, -68.5625,  76.3125, -61.2188,  48.9375,
+  //              -56.3125,  71.0000, -74.5625, -38.7188,
+  //              -50.3438,  93.3750,  80.2500, -7.4141,  93.8125,  83.1875
+  VLOAD_16(v2, 0xd5d0, 0xd2e4, 0xd449, 0x54c5, 0xd3a7, 0x521e, 0xd30a, 0x5470,
+           0xd4a9, 0xd0d7, 0xd24b, 0x55d6, 0x5504, 0xc76a, 0x55dd, 0x5533);
+  //              -60.0312, -31.7188, -74.2500, -0.9077,  30.4844, -56.2500,
+  //              -4.8320,  34.2812,  66.6875,  37.9375,  78.1875,  5.6094,
+  //              -81.8125,  67.6250,  29.4531, -64.9375
+  VLOAD_16(v6, 0xd381, 0xcfee, 0xd4a4, 0xbb43, 0x4f9f, 0xd308, 0xc4d5, 0x5049,
+           0x542b, 0x50be, 0x54e3, 0x459c, 0xd51d, 0x543a, 0x4f5d, 0xd40f);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //               31.29529381, -66.12346649,
+  //               -48.59321213,  21.66906929,  92.08473206,  1.95985305,
+  //               -96.55027771,  77.65225220, -82.48660278,
+  //               -35.32508850,  42.91923141,
+  //               -76.65069580,  25.13817024,  72.89311981,  21.44047737,  69.71634674
+  VLOAD_32(v4, 0x41fa5cc3, 0xc2843f37, 0xc2425f73, 0x41ad5a41, 0x42b82b62,
+           0x3ffadc77, 0xc2c119be, 0x429b4df4, 0xc2a4f924, 0xc20d4ce4,
+           0x422bad4b, 0xc2994d28, 0x41c91af9, 0x4291c947, 0x41ab8619,
+           0x428b6ec5);
+  asm volatile("vfwmsac.vv v4, v2, v6, v0.t");
+  //               31.29529381,  1814.61950684, -48.59321213,
+  //               -90.93905640,  92.08473206, -2754.69433594, -96.55027771,
+  //               2356.31640625, -82.48660278, -1433.56750488,  42.91923141,
+  //               600.42608643,  25.13817024, -574.26910400,  21.44047737,
+  //               -5471.70458984
+  VCMP_U32(3, v4, 0x41fa5cc3, 0x44e2d3d3, 0xc2425f73, 0xc2b5e0cc, 0x42b82b62,
+           0xc52c2b1c, 0xc2c119be, 0x45134510, 0xc2a4f924, 0xc4b33229,
+           0x422bad4b, 0x44161b45, 0x41c91af9, 0xc40f9139, 0x41ab8619,
+           0xc5aafda3);
+
+  VSET(16, e32, m1);
+  //              -71423.96093750, -46625.21875000, -59851.39453125,
+  //              -43461.99218750, -10255.72753906,  37671.59765625,
+  //              96842.05468750,  33293.05859375,  27126.79296875,
+  //              -27343.42187500,  26815.15429688,  28654.72070312,
+  //              -5699.91699219,  70582.03906250, -5936.72802734,
+  //              43479.90234375
+  VLOAD_32(v2, 0xc78b7ffb, 0xc7362138, 0xc769cb65, 0xc729c5fe, 0xc6203ee9,
+           0x47132799, 0x47bd2507, 0x47020d0f, 0x46d3ed96, 0xc6d59ed8,
+           0x46d17e4f, 0x46dfdd71, 0xc5b21f56, 0x4789db05, 0xc5b985d3,
+           0x4729d7e7);
+  //               93657.15625000, -28369.10156250, -42169.91406250,
+  //               -21377.95507812,  16308.38183594,  64517.84375000,
+  //               -12469.71679688, -76994.53125000, -33687.83593750,
+  //               -84006.54687500,  31506.48437500,  2731.77905273,
+  //               -20272.41992188,  53550.01953125, -85441.62500000,
+  //               -33418.07031250
+  VLOAD_32(v6, 0x47b6ec94, 0xc6dda234, 0xc724b9ea, 0xc6a703e9, 0x467ed187,
+           0x477c05d8, 0xc642d6de, 0xc7966144, 0xc70397d6, 0xc7a41346,
+           0x46f624f8, 0x452abc77, 0xc69e60d7, 0x47512e05, 0xc7a6e0d0,
+           0xc7028a12);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //               15054.1952512034331448, -39042.3922682931588497,
+  //               -83554.3539477824524511,  35787.9235785690543707,
+  //               -34715.2784411938628182,  35880.5352577352605294,
+  //               -52433.9701052222590079, -40831.3148960549369804,
+  //               -3569.6808186589187244,  77018.1414445060363505,
+  //               58906.1301468654128257, -84146.7844421620393405,
+  //               -23969.5482366856886074,  92255.7186088700836990,
+  //               -35519.3091108352309675, -65623.9480113173485734
+  VLOAD_64(v4, 0x40cd6718fdfdcea0, 0xc0e3104c8d763c4c, 0xc0f46625a9c52662,
+           0x40e1797d8df4a4ac, 0xc0e0f368e8fd81b0, 0x40e1851120d4d47c,
+           0xc0e99a3f0b1a1b69, 0xc0e3efea13a0e433, 0xc0abe35c94436520,
+           0x40f2cda2435b507a, 0x40ecc3442a29c254, 0xc0f48b2c8d133979,
+           0xc0d76863164f52e0, 0x40f685fb7f6c03ba, 0xc0e157e9e43c6805,
+           0xc0f0057f2b0dea44);
+  asm volatile("vfwmsac.vv v4, v2, v6, v0.t");
+  //               15054.1952512034331448,  1322754608.4847974777221680,
+  //               -83554.3539477824524511,  929092728.6666160821914673,
+  //               -34715.2784411938628182,  2430454370.8635458946228027,
+  //               -52433.9701052222590079, -2563342608.9896693229675293,
+  //               -3569.6808186589187244,  2296949433.3236432075500488,
+  //               58906.1301468654128257,  78362512.5631930530071259,
+  //               -23969.5482366856886074,  3779577314.6337165832519531,
+  //               -35519.3091108352309675, -1452948809.7560596466064453
+  VCMP_U64(4, v4, 0x40cd6718fdfdcea0, 0x41d3b5e88c1f06ec, 0xc0f46625a9c52662,
+           0x41cbb06a3c5553ad, 0xc0e0f368e8fd81b0, 0x41e21bb94c5ba22b,
+           0xc0e99a3f0b1a1b69, 0xc1e31930221fab5f, 0xc0abe35c94436520,
+           0x41e11d15572a5b49, 0x40ecc3442a29c254, 0x4192aede4240b5ae,
+           0xc0d76863164f52e0, 0x41ec28f8bc544768, 0xc0e157e9e43c6805,
+           0xc1d5a68f52706348);
+};
+
+// Simple random test with similar values (vector-scalar)
+void TEST_CASE3(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //               8.1562,  2.6836,  56.7188,  38.4688,  33.8125,
+  //               -83.0625,  37.7812, -28.0938, -33.0625,  61.1562,  13.0859,
+  //               -80.5000,  78.3125, -38.0625,  30.0625, -78.6250
+  VLOAD_16(v2, 0x4814, 0x415e, 0x5317, 0x50cf, 0x503a, 0xd531, 0x50b9, 0xcf06,
+           0xd022, 0x53a5, 0x4a8b, 0xd508, 0x54e5, 0xd0c2, 0x4f84, 0xd4ea);
+  //                              39.8125
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0x50fa);
+  //               56.66989136,  59.83663559, -8.21133614, -19.17305374,
+  //               -93.35797119, -34.25491333,  46.99548721,
+  //               -6.17113161,  55.22229004,  7.96844339, -92.84493256,
+  //               -90.90106201,  78.59468842, -58.67407608,  39.90958405,
+  //               -93.58789825
+  VLOAD_32(v4, 0x4262adf8, 0x426f58b7, 0xc10361a2, 0xc199626a, 0xc2bab748,
+           0xc2090508, 0x423bfb61, 0xc0c579e9, 0x425ce3a0, 0x40fefd7d,
+           0xc2b9b09b, 0xc2b5cd58, 0x429d307b, 0xc26ab241, 0x421fa36a,
+           0xc2bb2d01);
+  asm volatile("vfwmsac.vf v4, %[A], v2" ::[A] "f"(dscalar_16));
+  //               268.05081177,  47.00394058,  2266.32666016,  1550.71020508,
+  //               1439.51806641, -3272.67089844,  1457.17053223,
+  //               -1112.31127930, -1371.52307129,  2426.81469727, 613.82879639,
+  //               -3114.00512695,  3039.22167969, -1456.68920898,
+  //               1156.95373535, -3036.66992188
+  VCMP_U32(5, v4, 0x43860681, 0x423c0409, 0x450da53a, 0x44c1d6ba, 0x44b3f094,
+           0xc54c8abc, 0x44b62575, 0xc48b09f6, 0xc4ab70bd, 0x4517ad09,
+           0x4419750b, 0xc542a015, 0x453df38c, 0xc4b6160e, 0x44909e85,
+           0xc53dcab8);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //               580253.06250000, -300331.93750000,  485801.21875000,
+  //               -751037.87500000, -360868.65625000,  893035.68750000,
+  //               541162.00000000,  417622.93750000, -933287.18750000,
+  //               -790074.12500000,  496987.96875000,  455066.96875000,
+  //               -928285.18750000,  300725.40625000, -645096.93750000,
+  //               102530.55468750
+  VLOAD_32(v2, 0x490da9d1, 0xc892a57e, 0x48ed3527, 0xc9375bde, 0xc8b03495,
+           0x495a06bb, 0x49041ea0, 0x48cbeade, 0xc963da73, 0xc940e3a2,
+           0x48f2ab7f, 0x48de335f, 0xc962a1d3, 0x4892d6ad, 0xc91d7e8f,
+           0x47c84147);
+  //                               670995.56250000
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0x4923d139);
+  //               579132.0708449089433998,  521241.3016625398304313,
+  //               409779.0302067114971578,  454935.4394149139989167,
+  //               -640831.0776052488945425,  262502.9360184965189546,
+  //               -132061.7241549796890467, -523289.4277524493518285,
+  //               796635.9535234714858234,  170970.3947326899506152,
+  //               -520724.0386287728324533, -616193.5881990450434387,
+  //               79952.4583538805600256, -869849.3916852036491036,
+  //               535808.2751473840326071, -306070.6657954099355265
+  VLOAD_64(v4, 0x4121ac782445c8ae, 0x411fd06534e7065c, 0x411902cc1eee8218,
+           0x411bc45dc1f5fbb4, 0xc1238e7e27bbe00c, 0x4110059bbe7ba1fc,
+           0xc1001eedcb11c418, 0xc11ff065b604bcf3, 0x41284fb7e8343a7c,
+           0x4104ded328699cd0, 0xc11fc850278e4d10, 0xc122ce032d286cdc,
+           0x40f38507556ae0f0, 0xc12a8bb2c88af688, 0x41205a008ce01e30,
+           0xc112ae5aa9c6459e);
+  asm volatile("vfwmsac.vf v4, %[A], v2" ::[A] "f"(dscalar_32));
+  //               389346650932.4642944335937500,
+  //               -201521918580.8290100097656250,
+  //               325970052259.3115844726562500,
+  //               -503943536329.8690795898437500,
+  //               -242140626158.0102844238281250,
+  //               599222720963.7006835937500000, 363117432655.3491821289062500,
+  //               280223661150.1425781250000000,
+  //               -626232357986.5589599609375000,
+  //               -530136402891.4650268554687500,
+  //               333477242371.1773071289062500, 305348532865.1643676757812500,
+  //               -622875321499.4388427734375000,
+  //               201786282974.1514587402343750,
+  //               -432857718253.1149902343750000,  68797853286.6418762207031250
+  VCMP_U64(6, v4, 0x4256a9b79acd1db7, 0xc24775d2393a6a1d, 0x4252f9551128d3f1,
+           0xc25d555807b2779f, 0xc24c305a5e770151, 0x4261708ea338766c,
+           0x425522df13d3d659, 0x42504fa86f178920, 0xc26239cb6e8c51e3,
+           0xc25edba5e2f2ddc3, 0x42536932b980cb59, 0x4251c60c36a04a85,
+           0xc26220c864936e0b, 0x42477db329ef1363, 0xc2593215277b475c,
+           0x423004abee66a452);
+};
+
+// Simple random test with similar values (vector-scalar) (masked)
+void TEST_CASE4(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //                8.1562,  2.6836,  56.7188,  38.4688,  33.8125,
+  //                -83.0625,  37.7812, -28.0938, -33.0625,  61.1562,  13.0859,
+  //                -80.5000,  78.3125, -38.0625,  30.0625, -78.6250
+  VLOAD_16(v2, 0x4814, 0x415e, 0x5317, 0x50cf, 0x503a, 0xd531, 0x50b9, 0xcf06,
+           0xd022, 0x53a5, 0x4a8b, 0xd508, 0x54e5, 0xd0c2, 0x4f84, 0xd4ea);
+  //                              39.8125
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0x50fa);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //                56.66989136,  59.83663559, -8.21133614, -19.17305374,
+  //                -93.35797119, -34.25491333,  46.99548721,
+  //                -6.17113161,  55.22229004,  7.96844339, -92.84493256,
+  //                -90.90106201,  78.59468842, -58.67407608,  39.90958405,
+  //                -93.58789825
+  VLOAD_32(v4, 0x4262adf8, 0x426f58b7, 0xc10361a2, 0xc199626a, 0xc2bab748,
+           0xc2090508, 0x423bfb61, 0xc0c579e9, 0x425ce3a0, 0x40fefd7d,
+           0xc2b9b09b, 0xc2b5cd58, 0x429d307b, 0xc26ab241, 0x421fa36a,
+           0xc2bb2d01);
+  asm volatile("vfwmsac.vf v4, %[A], v2, v0.t" ::[A] "f"(dscalar_16));
+  //                56.66989136,  47.00394058, -8.21133614,  1550.71020508,
+  //                -93.35797119, -3272.67089844,  46.99548721,
+  //                -1112.31127930,  55.22229004,  2426.81469727, -92.84493256,
+  //                -3114.00512695,  78.59468842, -1456.68920898,  39.90958405,
+  //                -3036.66992188
+  VCMP_U32(7, v4, 0x4262adf8, 0x423c0409, 0xc10361a2, 0x44c1d6ba, 0xc2bab748,
+           0xc54c8abc, 0x423bfb61, 0xc48b09f6, 0x425ce3a0, 0x4517ad09,
+           0xc2b9b09b, 0xc542a015, 0x429d307b, 0xc4b6160e, 0x421fa36a,
+           0xc53dcab8);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                580253.06250000, -300331.93750000,  485801.21875000,
+  //                -751037.87500000, -360868.65625000,  893035.68750000,
+  //                541162.00000000,  417622.93750000, -933287.18750000,
+  //                -790074.12500000,  496987.96875000,  455066.96875000,
+  //                -928285.18750000,  300725.40625000, -645096.93750000,
+  //                102530.55468750
+  VLOAD_32(v2, 0x490da9d1, 0xc892a57e, 0x48ed3527, 0xc9375bde, 0xc8b03495,
+           0x495a06bb, 0x49041ea0, 0x48cbeade, 0xc963da73, 0xc940e3a2,
+           0x48f2ab7f, 0x48de335f, 0xc962a1d3, 0x4892d6ad, 0xc91d7e8f,
+           0x47c84147);
+  //                               670995.56250000
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0x4923d139);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //                579132.0708449089433998,  521241.3016625398304313,
+  //                409779.0302067114971578,  454935.4394149139989167,
+  //                -640831.0776052488945425,  262502.9360184965189546,
+  //                -132061.7241549796890467, -523289.4277524493518285,
+  //                796635.9535234714858234,  170970.3947326899506152,
+  //                -520724.0386287728324533, -616193.5881990450434387,
+  //                79952.4583538805600256, -869849.3916852036491036,
+  //                535808.2751473840326071, -306070.6657954099355265
+  VLOAD_64(v4, 0x4121ac782445c8ae, 0x411fd06534e7065c, 0x411902cc1eee8218,
+           0x411bc45dc1f5fbb4, 0xc1238e7e27bbe00c, 0x4110059bbe7ba1fc,
+           0xc1001eedcb11c418, 0xc11ff065b604bcf3, 0x41284fb7e8343a7c,
+           0x4104ded328699cd0, 0xc11fc850278e4d10, 0xc122ce032d286cdc,
+           0x40f38507556ae0f0, 0xc12a8bb2c88af688, 0x41205a008ce01e30,
+           0xc112ae5aa9c6459e);
+  asm volatile("vfwmsac.vf v4, %[A], v2, v0.t" ::[A] "f"(dscalar_32));
+  //                579132.0708449089433998, -201521918580.8290100097656250,
+  //                409779.0302067114971578, -503943536329.8690795898437500,
+  //                -640831.0776052488945425,  599222720963.7006835937500000,
+  //                -132061.7241549796890467,  280223661150.1425781250000000,
+  //                796635.9535234714858234, -530136402891.4650268554687500,
+  //                -520724.0386287728324533,  305348532865.1643676757812500,
+  //                79952.4583538805600256,  201786282974.1514587402343750,
+  //                535808.2751473840326071,  68797853286.6418762207031250
+  VCMP_U64(8, v4, 0x4121ac782445c8ae, 0xc24775d2393a6a1d, 0x411902cc1eee8218,
+           0xc25d555807b2779f, 0xc1238e7e27bbe00c, 0x4261708ea338766c,
+           0xc1001eedcb11c418, 0x42504fa86f178920, 0x41284fb7e8343a7c,
+           0xc25edba5e2f2ddc3, 0xc11fc850278e4d10, 0x4251c60c36a04a85,
+           0x40f38507556ae0f0, 0x42477db329ef1363, 0x41205a008ce01e30,
+           0x423004abee66a452);
+};
+
+int main(void) {
+  enable_vec();
+  enable_fp();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vfwmul.c b/apps/riscv-tests/isa/rv64uv/vfwmul.c
new file mode 100644
index 0000000..c9f5f1c
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vfwmul.c
@@ -0,0 +1,254 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+//         Matteo Perotti <mperotti@iis.ee.ethz.ch>
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+// Simple random test with similar values
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  //              -56.5312,  95.3750,  86.3750, -33.4375,  4.7656,  58.8438,
+  //              -80.4375, -96.4375,  74.3750, -92.7500, -57.2812, -90.0625,
+  //              -93.2500,  40.6875, -32.2812, -36.8125
+  VLOAD_16(v2, 0xd311, 0x55f6, 0x5566, 0xd02e, 0x44c4, 0x535b, 0xd507, 0xd607,
+           0x54a6, 0xd5cc, 0xd329, 0xd5a1, 0xd5d4, 0x5116, 0xd009, 0xd09a);
+  //               96.4375, -98.8125, -49.1250, -78.8750,
+  //               -5.9180,  32.8750,  32.8750, -74.8125,
+  //               -10.3750,  39.5938,  43.2812,  15.0547, -31.9062,
+  //               -11.2500,  16.3594,  28.6094
+  VLOAD_16(v6, 0x5607, 0xd62d, 0xd224, 0xd4ee, 0xc5eb, 0x501c, 0x501c, 0xd4ad,
+           0xc930, 0x50f3, 0x5169, 0x4b87, 0xcffa, 0xc9a0, 0x4c17, 0x4f27);
+  asm volatile("vfwmul.vv v4, v2, v6");
+  //              -5451.73242188, -9424.24218750, -4243.17187500, 2637.38281250,
+  //              -28.20281982,  1934.48828125, -2644.38281250,  7214.73046875,
+  //              -771.64062500, -3672.32031250, -2479.20410156, -1355.86279297,
+  //              2975.25781250, -457.73437500, -528.10107422, -1053.18261719
+  VCMP_U32(1, v4, 0xc5aa5ddc, 0xc61340f8, 0xc5849960, 0x4524d620, 0xc1e19f60,
+           0x44f1cfa0, 0xc5254620, 0x45e175d8, 0xc440e900, 0xc5658520,
+           0xc51af344, 0xc4a97b9c, 0x4539f420, 0xc3e4de00, 0xc4040678,
+           0xc483a5d8);
+
+  VSET(16, e32, m1);
+  //              -89875.40625000,  87678.49218750, -37342.58593750,
+  //              -47507.81640625, -80717.72656250,  2230.02978516,
+  //              -68805.99218750,  79032.60156250, -43338.95703125,
+  //              42250.94531250, -6447.03955078,  25544.21679688,
+  //              5945.30566406, -47409.30468750, -43415.17187500,
+  //              92669.35156250
+  VLOAD_32(v2, 0xc7af89b4, 0x47ab3f3f, 0xc711de96, 0xc73993d1, 0xc79da6dd,
+           0x450b607a, 0xc78662ff, 0x479a5c4d, 0xc7294af5, 0x47250af2,
+           0xc5c97851, 0x46c7906f, 0x45b9ca72, 0xc739314e, 0xc729972c,
+           0x47b4fead);
+  //               99630.39843750,  37076.73437500, -66118.01562500,
+  //               -99829.85156250, -78879.75000000,  75633.85937500,
+  //               -90564.15625000, -84653.48437500,  34630.80859375,
+  //               85817.48437500, -23627.74023438, -79522.11718750,
+  //               51590.63671875,  7574.55957031, -93117.57812500,
+  //               28056.31054688
+  VLOAD_32(v6, 0x47c29733, 0x4710d4bc, 0xc7812302, 0xc7c2faed, 0xc79a0fe0,
+           0x4793b8ee, 0xc7b0e214, 0xc7a556be, 0x470746cf, 0x47a79cbe,
+           0xc6b8977b, 0xc79b510f, 0x474986a3, 0x45ecb47a, 0xc7b5deca,
+           0x46db309f);
+  asm volatile("vfwmul.vv v4, v2, v6");
+  //              -8954322534.4196777343750000,  3250832165.2364501953125000,
+  //              2469017680.4935302734375000,  4742698259.8944396972656250,
+  //              6366994091.8183593750000000,  168665759.1725692749023438,
+  //              6231356627.4050292968750000, -6690385101.4866943359375000,
+  //              -1500863125.6019744873046875,  3625869839.1844482421875000,
+  //              152328975.7866010665893555, -2031330201.5839996337890625,
+  //              306722104.6965751647949219, -359104602.5425643920898438,
+  //              4042715658.8806152343750000,  2599960105.6150360107421875
+  VCMP_U64(2, v4, 0xc200adc0f3335b80, 0x41e8387864a79100, 0x41e265470a0fcb00,
+           0x41f1aafd513e4fa0, 0x41f7b809eabd1800, 0x41a41b453e585b00,
+           0x41f736af4d367b00, 0xc1f8ec72ccd7c980, 0xc1d65d56a56686c0,
+           0x41eb03cc41e5e700, 0x41a228b61f92bd60, 0xc1de44e8e6656040,
+           0x41b2483538b252c0, 0xc1b567805a8ae580, 0x41ee1ede415c2e00,
+           0x41e35f07c533ae60);
+};
+
+// Simple random test with similar values (masked)
+// The numbers are the same of TEST_CASE1
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  //              -56.5312,  95.3750,  86.3750, -33.4375,  4.7656,  58.8438,
+  //              -80.4375, -96.4375,  74.3750, -92.7500, -57.2812, -90.0625,
+  //              -93.2500,  40.6875, -32.2812, -36.8125
+  VLOAD_16(v2, 0xd311, 0x55f6, 0x5566, 0xd02e, 0x44c4, 0x535b, 0xd507, 0xd607,
+           0x54a6, 0xd5cc, 0xd329, 0xd5a1, 0xd5d4, 0x5116, 0xd009, 0xd09a);
+  //               96.4375, -98.8125, -49.1250, -78.8750,
+  //               -5.9180,  32.8750,  32.8750, -74.8125,
+  //               -10.3750,  39.5938,  43.2812,  15.0547, -31.9062,
+  //               -11.2500,  16.3594,  28.6094
+  VLOAD_16(v6, 0x5607, 0xd62d, 0xd224, 0xd4ee, 0xc5eb, 0x501c, 0x501c, 0xd4ad,
+           0xc930, 0x50f3, 0x5169, 0x4b87, 0xcffa, 0xc9a0, 0x4c17, 0x4f27);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfwmul.vv v4, v2, v6, v0.t");
+  //               0.00000000, -9424.24218750,  0.00000000,  2637.38281250,
+  //               0.00000000,  1934.48828125,  0.00000000,  7214.73046875,
+  //               0.00000000, -3672.32031250,  0.00000000, -1355.86279297,
+  //               0.00000000, -457.73437500,  0.00000000, -1053.18261719
+  VCMP_U32(3, v4, 0x0, 0xc61340f8, 0x0, 0x4524d620, 0x0, 0x44f1cfa0, 0x0,
+           0x45e175d8, 0x0, 0xc5658520, 0x0, 0xc4a97b9c, 0x0, 0xc3e4de00, 0x0,
+           0xc483a5d8);
+
+  VSET(16, e32, m1);
+  //              -89875.40625000,  87678.49218750, -37342.58593750,
+  //              -47507.81640625, -80717.72656250,  2230.02978516,
+  //              -68805.99218750,  79032.60156250, -43338.95703125,
+  //              42250.94531250, -6447.03955078,  25544.21679688,
+  //              5945.30566406, -47409.30468750, -43415.17187500,
+  //              92669.35156250
+  VLOAD_32(v2, 0xc7af89b4, 0x47ab3f3f, 0xc711de96, 0xc73993d1, 0xc79da6dd,
+           0x450b607a, 0xc78662ff, 0x479a5c4d, 0xc7294af5, 0x47250af2,
+           0xc5c97851, 0x46c7906f, 0x45b9ca72, 0xc739314e, 0xc729972c,
+           0x47b4fead);
+  //               99630.39843750,  37076.73437500, -66118.01562500,
+  //               -99829.85156250, -78879.75000000,  75633.85937500,
+  //               -90564.15625000, -84653.48437500,  34630.80859375,
+  //               85817.48437500, -23627.74023438, -79522.11718750,
+  //               51590.63671875,  7574.55957031, -93117.57812500,
+  //               28056.31054688
+  VLOAD_32(v6, 0x47c29733, 0x4710d4bc, 0xc7812302, 0xc7c2faed, 0xc79a0fe0,
+           0x4793b8ee, 0xc7b0e214, 0xc7a556be, 0x470746cf, 0x47a79cbe,
+           0xc6b8977b, 0xc79b510f, 0x474986a3, 0x45ecb47a, 0xc7b5deca,
+           0x46db309f);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfwmul.vv v4, v2, v6, v0.t");
+  //               0.0000000000000000,  3250832165.2364501953125000,
+  //               0.0000000000000000,  4742698259.8944396972656250,
+  //               0.0000000000000000,  168665759.1725692749023438,
+  //               0.0000000000000000, -6690385101.4866943359375000,
+  //               0.0000000000000000,  3625869839.1844482421875000,
+  //               0.0000000000000000, -2031330201.5839996337890625,
+  //               0.0000000000000000, -359104602.5425643920898438,
+  //               0.0000000000000000,  2599960105.6150360107421875
+  VCMP_U64(4, v4, 0x0, 0x41e8387864a79100, 0x0, 0x41f1aafd513e4fa0, 0x0,
+           0x41a41b453e585b00, 0x0, 0xc1f8ec72ccd7c980, 0x0, 0x41eb03cc41e5e700,
+           0x0, 0xc1de44e8e6656040, 0x0, 0xc1b567805a8ae580, 0x0,
+           0x41e35f07c533ae60);
+};
+
+// Simple random test with similar values (vector-scalar)
+void TEST_CASE3(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //              -44.4062, -27.0781, -21.6562,  75.5625, -84.5000,
+  //              -1.0713,  72.5625, -84.6250,  83.9375, -52.3438,
+  //              -40.5625,  1.6523,  79.6875, -36.2812,  33.5938, -72.4375
+  VLOAD_16(v2, 0xd18d, 0xcec5, 0xcd6a, 0x54b9, 0xd548, 0xbc49, 0x5489, 0xd54a,
+           0x553f, 0xd28b, 0xd112, 0x3e9c, 0x54fb, 0xd089, 0x5033, 0xd487);
+  //                             -58.9688
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0xd35f);
+  asm volatile("vfwmul.vf v4, v2, %[A]" ::[A] "f"(dscalar_16));
+  //               2618.58105469,  1596.76318359,  1277.04199219,
+  //               -4455.82617188,  4982.85937500,  63.17257690, -4278.91992188,
+  //               4990.23046875, -4949.68945312,  3086.64550781, 2391.91992188,
+  //               -97.43664551, -4699.07226562,  2139.45996094, -1980.98144531,
+  //               4271.54882812
+  VCMP_U32(5, v4, 0x4523a94c, 0x44c7986c, 0x449fa158, 0xc58b3e9c, 0x459bb6e0,
+           0x427cb0b8, 0xc585b75c, 0x459bf1d8, 0xc59aad84, 0x4540ea54,
+           0x45157eb8, 0xc2c2df90, 0xc592d894, 0x4505b75c, 0xc4f79f68,
+           0x45857c64);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //              -187018.20312500, -714032.18750000, -891429.25000000,
+  //              -378265.00000000,  211566.90625000,  231934.78125000,
+  //              947047.75000000, -241945.03125000, -489658.75000000,
+  //              -788001.68750000, -817411.37500000, -522168.21875000,
+  //              -668021.56250000,  744069.12500000, -620354.68750000,
+  //              913454.68750000
+  VLOAD_32(v2, 0xc836a28d, 0xc92e5303, 0xc959a254, 0xc8b8b320, 0x484e9bba,
+           0x48627fb2, 0x4967367c, 0xc86c4642, 0xc8ef1758, 0xc940621b,
+           0xc9479036, 0xc8fef707, 0xc9231759, 0x4935a852, 0xc917742b,
+           0x495f02eb);
+  //                              -50557.21484375
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0xc7457d37);
+  asm volatile("vfwmul.vf v4, v2, %[A]" ::[A] "f"(dscalar_32));
+  //               9455119475.0827026367187500,  36099478708.7902832031250000,
+  //               45068180110.2529296875000000,  19124024872.8710937500000000,
+  //               -10696233533.1087646484375000, -11725976565.3944091796875000,
+  //               -47880096564.0400390625000000,  12232066925.2840576171875000,
+  //               24755782623.8720703125000000,  39839170612.1750488281250000,
+  //               41326042501.6000976562500000,  26399370819.9219970703125000,
+  //               33773309655.5700683593750000, -37618062611.2260742187500000,
+  //               31363405215.2648925781250000, -46181724885.9680175781250000
+  VCMP_U64(6, v4, 0x42019c8d6398a960, 0x4220cf64a96994a0, 0x4224fc8bb51c8180,
+           0x4211cf85d8a37c00, 0xc203ec5c91e8dec0, 0xc205d7619fab27c0,
+           0xc2264bc096681480, 0x4206c8b43b6a45c0, 0x42170e3d0f7f7d00,
+           0x42228d33006859a0, 0x42233e72bb0b3340, 0x42189619b90fb020,
+           0x421f742f3b5e47c0, 0xc221846c2a2673c0, 0x421d359e567d0f40,
+           0xc225814a65abefa0);
+};
+
+// Simple random test with similar values (vector-scalar) (masked)
+void TEST_CASE4(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //               -44.4062, -27.0781, -21.6562,  75.5625, -84.5000,
+  //               -1.0713,  72.5625, -84.6250,  83.9375, -52.3438,
+  //               -40.5625,  1.6523,  79.6875, -36.2812,  33.5938, -72.4375
+  VLOAD_16(v2, 0xd18d, 0xcec5, 0xcd6a, 0x54b9, 0xd548, 0xbc49, 0x5489, 0xd54a,
+           0x553f, 0xd28b, 0xd112, 0x3e9c, 0x54fb, 0xd089, 0x5033, 0xd487);
+  //                             -58.9688
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0xd35f);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfwmul.vf v4, v2, %[A], v0.t" ::[A] "f"(dscalar_16));
+  //                0.00000000,  1596.76318359,  0.00000000, -4455.82617188,
+  //                0.00000000,  63.17257690,  0.00000000,  4990.23046875,
+  //                0.00000000,  3086.64550781,  0.00000000, -97.43664551,
+  //                0.00000000,  2139.45996094,  0.00000000,  4271.54882812
+  VCMP_U32(7, v4, 0x0, 0x44c7986c, 0x0, 0xc58b3e9c, 0x0, 0x427cb0b8, 0x0,
+           0x459bf1d8, 0x0, 0x4540ea54, 0x0, 0xc2c2df90, 0x0, 0x4505b75c, 0x0,
+           0x45857c64);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //               -187018.20312500, -714032.18750000, -891429.25000000,
+  //               -378265.00000000,  211566.90625000,  231934.78125000,
+  //               947047.75000000, -241945.03125000, -489658.75000000,
+  //               -788001.68750000, -817411.37500000, -522168.21875000,
+  //               -668021.56250000,  744069.12500000, -620354.68750000,
+  //               913454.68750000
+  VLOAD_32(v2, 0xc836a28d, 0xc92e5303, 0xc959a254, 0xc8b8b320, 0x484e9bba,
+           0x48627fb2, 0x4967367c, 0xc86c4642, 0xc8ef1758, 0xc940621b,
+           0xc9479036, 0xc8fef707, 0xc9231759, 0x4935a852, 0xc917742b,
+           0x495f02eb);
+  //                              -50557.21484375
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0xc7457d37);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfwmul.vf v4, v2, %[A], v0.t" ::[A] "f"(dscalar_32));
+  //                0.0000000000000000,  36099478708.7902832031250000,
+  //                0.0000000000000000,  19124024872.8710937500000000,
+  //                0.0000000000000000, -11725976565.3944091796875000,
+  //                0.0000000000000000,  12232066925.2840576171875000,
+  //                0.0000000000000000,  39839170612.1750488281250000,
+  //                0.0000000000000000,  26399370819.9219970703125000,
+  //                0.0000000000000000, -37618062611.2260742187500000,
+  //                0.0000000000000000, -46181724885.9680175781250000
+  VCMP_U64(8, v4, 0x0, 0x4220cf64a96994a0, 0x0, 0x4211cf85d8a37c00, 0x0,
+           0xc205d7619fab27c0, 0x0, 0x4206c8b43b6a45c0, 0x0, 0x42228d33006859a0,
+           0x0, 0x42189619b90fb020, 0x0, 0xc221846c2a2673c0, 0x0,
+           0xc225814a65abefa0);
+};
+
+int main(void) {
+  enable_vec();
+  enable_fp();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vfwnmacc.c b/apps/riscv-tests/isa/rv64uv/vfwnmacc.c
new file mode 100644
index 0000000..500af15
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vfwnmacc.c
@@ -0,0 +1,352 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+//         Matteo Perotti <mperotti@iis.ee.ethz.ch>
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+// Simple random test with similar values
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  //               33.9375,  31.7344, -56.0000, -62.0625,  77.6875, -7.7383,
+  //               -75.3750,  4.1953,  79.5625, -87.3750,
+  //               -37.2188,  90.5000,  68.0625,  69.0625,  54.0312, -64.6875
+  VLOAD_16(v2, 0x503e, 0x4fef, 0xd300, 0xd3c2, 0x54db, 0xc7bd, 0xd4b6, 0x4432,
+           0x54f9, 0xd576, 0xd0a7, 0x55a8, 0x5441, 0x5451, 0x52c1, 0xd40b);
+  //              -92.3125, -75.9375,  26.1094,
+  //              -79.6875,  3.9375,  37.2812,  50.7812, -3.9375, -55.9688,
+  //              -31.5312,  76.0000,  69.1875, -8.2578, -52.5000,
+  //              -98.4375,  40.3438
+  VLOAD_16(v6, 0xd5c5, 0xd4bf, 0x4e87, 0xd4fb, 0x43e0, 0x50a9, 0x5259, 0xc3e0,
+           0xd2ff, 0xcfe2, 0x54c0, 0x5453, 0xc821, 0xd290, 0xd627, 0x510b);
+  //               75.62483215,  29.19676971,  69.45310211, -70.36167145,
+  //               -0.92180759, -77.84928131,  86.66299438, -43.34124756,
+  //               -3.36894345,  7.33576536, -64.43717194, -80.48993683,
+  //               -5.57641745,  89.34833527, -39.19780731, -55.64332581
+  VLOAD_32(v4, 0x42973fea, 0x41e992fc, 0x428ae7fd, 0xc28cb92d, 0xbf6bfb95,
+           0xc29bb2d5, 0x42ad5374, 0xc22d5d70, 0xc0579cc5, 0x40eabe97,
+           0xc280dfd5, 0xc2a0fad9, 0xc0b27203, 0x42b2b259, 0xc21cca8e,
+           0xc25e92c4);
+  asm volatile("vfwnmacc.vv v4, v2, v6");
+  //               3057.23071289,  2380.63232422,  1392.67187500,
+  //               -4875.24365234, -304.97271729,  366.34207153,
+  //               3740.97363281,  59.86029053,  4456.38281250, -2762.37866211,
+  //               2893.06225586, -6180.97900391,  567.62377930,  3536.43286133,
+  //               5357.89892578,  2665.37963867
+  VCMP_U32(1, v4, 0x453f13b1, 0x4514ca1e, 0x44ae1580, 0xc59859f3, 0xc3987c82,
+           0x43b72bc9, 0x4569cf94, 0x426f70f0, 0x458b4310, 0xc52ca60f,
+           0x4534d0ff, 0xc5c127d5, 0x440de7ec, 0x455d06ed, 0x45a76f31,
+           0x45269613);
+
+  VSET(16, e32, m1);
+  //               24686.12304688,  45012.43359375,  5708.16113281,
+  //               -32777.98828125,  74121.31250000, -74877.15625000,
+  //               -60082.02734375,  46400.20312500, -45509.65234375,
+  //               -63994.57031250, -8693.70019531,  57683.04296875,
+  //               70424.14843750,  90967.72656250,  16158.18359375,
+  //               -90782.41406250
+  VLOAD_32(v2, 0x46c0dc3f, 0x472fd46f, 0x45b2614a, 0xc70009fd, 0x4790c4a8,
+           0xc7923e94, 0xc76ab207, 0x47354034, 0xc731c5a7, 0xc779fa92,
+           0xc607d6cd, 0x4761530b, 0x47898c13, 0x47b1abdd, 0x467c78bc,
+           0xc7b14f35);
+  //              -87108.13281250, -7857.04492188, -40309.92968750,
+  //              -77418.73437500,  28954.62109375, -28385.13085938,
+  //              42368.34375000, -32644.74804688,  89327.02343750,
+  //              -91567.60156250, -25929.78515625, -88250.83593750,
+  //              -49992.60156250,  34217.12500000,  49765.98046875,
+  //              8088.22802734
+  VLOAD_32(v6, 0xc7aa2211, 0xc5f5885c, 0xc71d75ee, 0xc797355e, 0x46e2353e,
+           0xc6ddc243, 0x47258058, 0xc6ff097f, 0x47ae7783, 0xc7b2d7cd,
+           0xc6ca9392, 0xc7ac5d6b, 0xc743489a, 0x4705a920, 0x474265fb,
+           0x45fcc1d3);
+  //              -95159.7034957902651513, -25746.0480722606444033,
+  //              -89272.3172746254567755, -57390.5516721799431252,
+  //              98139.9797031646012329, -66607.6782029465102823,
+  //              67788.7602550606534351, -90593.7788542728667380,
+  //              -68056.0128839309472824, -37127.9738570771587547,
+  //              21060.8546093095501419, -76483.1707763712329324,
+  //              83261.7813338561973069, -99608.0446094776270911,
+  //              32602.1877863906847779,  52037.0826651407405734
+  VLOAD_64(v4, 0xc0f73b7b4184cd41, 0xc0d92483139dacd4, 0xc0f5cb85138e8ec3,
+           0xc0ec05d1a74c6a5f, 0x40f7f5bfacdd39bc, 0xc0f042fad9eb5535,
+           0x40f08ccc2a0135e2, 0xc0f61e1c762fe5e5, 0xc0f09d8034c5c7e1,
+           0xc0e220ff29d6512c, 0x40d49136b1eb3ed8, 0xc0f2ac32bb800116,
+           0x40f453dc8057edfa, 0xc0f85180b6b86d78, 0x40dfd68c04b135a8,
+           0x40e968a2a5315d80);
+  asm volatile("vfwnmacc.vv v4, v2, v6");
+  //               2150457244.6964006423950195,  353690458.8370813727378845,
+  //               230184846.2258668541908264, -2537572977.5412845611572266,
+  //               -2146252658.3886387348175049, -2125331270.8559157848358154,
+  //               2545508198.9366445541381836,  1514813534.1183013916015625,
+  //               4065309837.5555171966552734, -5859792188.5645341873168945,
+  //               -225446839.1319110989570618,  5090653244.5816955566406250,
+  //               3520603131.4329605102539062, -3112554462.7102732658386230,
+  //               -804160451.3248255252838135,  734216828.7275727987289429
+  VCMP_U64(2, v4, 0x41e005abf39648ea, 0x41b514e35ad64af7, 0x41ab70af1c73a4d2,
+           0xc1e2e8094e315234, 0xc1dffb4ddc98df75, 0xc1dfab7ed1b6c753,
+           0x41e2f72becddf8fe, 0x41d6928e17879240, 0x41ee49f691b1c6cc,
+           0xc1f5d45553c90855, 0xc1aae0176e4389da, 0x41f2f6d343c94ea0,
+           0x41ea3b047f6ddad0, 0xc1e730b9fbd6ba8f, 0xc1c7f741e1a993e2,
+           0x41c5e1a13e5d211b);
+};
+
+// Simple random test with similar values (masked)
+// The numbers are the same of TEST_CASE1
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  //               33.9375,  31.7344, -56.0000, -62.0625,  77.6875, -7.7383,
+  //               -75.3750,  4.1953,  79.5625, -87.3750,
+  //               -37.2188,  90.5000,  68.0625,  69.0625,  54.0312, -64.6875
+  VLOAD_16(v2, 0x503e, 0x4fef, 0xd300, 0xd3c2, 0x54db, 0xc7bd, 0xd4b6, 0x4432,
+           0x54f9, 0xd576, 0xd0a7, 0x55a8, 0x5441, 0x5451, 0x52c1, 0xd40b);
+  //              -92.3125, -75.9375,  26.1094,
+  //              -79.6875,  3.9375,  37.2812,  50.7812, -3.9375, -55.9688,
+  //              -31.5312,  76.0000,  69.1875, -8.2578, -52.5000,
+  //              -98.4375,  40.3438
+  VLOAD_16(v6, 0xd5c5, 0xd4bf, 0x4e87, 0xd4fb, 0x43e0, 0x50a9, 0x5259, 0xc3e0,
+           0xd2ff, 0xcfe2, 0x54c0, 0x5453, 0xc821, 0xd290, 0xd627, 0x510b);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //               75.62483215,  29.19676971,  69.45310211, -70.36167145,
+  //               -0.92180759, -77.84928131,  86.66299438, -43.34124756,
+  //               -3.36894345,  7.33576536, -64.43717194, -80.48993683,
+  //               -5.57641745,  89.34833527, -39.19780731, -55.64332581
+  VLOAD_32(v4, 0x42973fea, 0x41e992fc, 0x428ae7fd, 0xc28cb92d, 0xbf6bfb95,
+           0xc29bb2d5, 0x42ad5374, 0xc22d5d70, 0xc0579cc5, 0x40eabe97,
+           0xc280dfd5, 0xc2a0fad9, 0xc0b27203, 0x42b2b259, 0xc21cca8e,
+           0xc25e92c4);
+  asm volatile("vfwnmacc.vv v4, v2, v6, v0.t");
+  //               75.62483215,  2380.63232422,  69.45310211, -4875.24365234,
+  //               -0.92180759,  366.34207153,  86.66299438,  59.86029053,
+  //               -3.36894345, -2762.37866211, -64.43717194, -6180.97900391,
+  //               -5.57641745,  3536.43286133, -39.19780731,  2665.37963867
+  VCMP_U32(3, v4, 0x42973fea, 0x4514ca1e, 0x428ae7fd, 0xc59859f3, 0xbf6bfb95,
+           0x43b72bc9, 0x42ad5374, 0x426f70f0, 0xc0579cc5, 0xc52ca60f,
+           0xc280dfd5, 0xc5c127d5, 0xc0b27203, 0x455d06ed, 0xc21cca8e,
+           0x45269613);
+
+  VSET(16, e32, m1);
+  //               24686.12304688,  45012.43359375,  5708.16113281,
+  //               -32777.98828125,  74121.31250000, -74877.15625000,
+  //               -60082.02734375,  46400.20312500, -45509.65234375,
+  //               -63994.57031250, -8693.70019531,  57683.04296875,
+  //               70424.14843750,  90967.72656250,  16158.18359375,
+  //               -90782.41406250
+  VLOAD_32(v2, 0x46c0dc3f, 0x472fd46f, 0x45b2614a, 0xc70009fd, 0x4790c4a8,
+           0xc7923e94, 0xc76ab207, 0x47354034, 0xc731c5a7, 0xc779fa92,
+           0xc607d6cd, 0x4761530b, 0x47898c13, 0x47b1abdd, 0x467c78bc,
+           0xc7b14f35);
+  //              -87108.13281250, -7857.04492188, -40309.92968750,
+  //              -77418.73437500,  28954.62109375, -28385.13085938,
+  //              42368.34375000, -32644.74804688,  89327.02343750,
+  //              -91567.60156250, -25929.78515625, -88250.83593750,
+  //              -49992.60156250,  34217.12500000,  49765.98046875,
+  //              8088.22802734
+  VLOAD_32(v6, 0xc7aa2211, 0xc5f5885c, 0xc71d75ee, 0xc797355e, 0x46e2353e,
+           0xc6ddc243, 0x47258058, 0xc6ff097f, 0x47ae7783, 0xc7b2d7cd,
+           0xc6ca9392, 0xc7ac5d6b, 0xc743489a, 0x4705a920, 0x474265fb,
+           0x45fcc1d3);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //              -95159.7034957902651513, -25746.0480722606444033,
+  //              -89272.3172746254567755, -57390.5516721799431252,
+  //              98139.9797031646012329, -66607.6782029465102823,
+  //              67788.7602550606534351, -90593.7788542728667380,
+  //              -68056.0128839309472824, -37127.9738570771587547,
+  //              21060.8546093095501419, -76483.1707763712329324,
+  //              83261.7813338561973069, -99608.0446094776270911,
+  //              32602.1877863906847779,  52037.0826651407405734
+  VLOAD_64(v4, 0xc0f73b7b4184cd41, 0xc0d92483139dacd4, 0xc0f5cb85138e8ec3,
+           0xc0ec05d1a74c6a5f, 0x40f7f5bfacdd39bc, 0xc0f042fad9eb5535,
+           0x40f08ccc2a0135e2, 0xc0f61e1c762fe5e5, 0xc0f09d8034c5c7e1,
+           0xc0e220ff29d6512c, 0x40d49136b1eb3ed8, 0xc0f2ac32bb800116,
+           0x40f453dc8057edfa, 0xc0f85180b6b86d78, 0x40dfd68c04b135a8,
+           0x40e968a2a5315d80);
+  asm volatile("vfwnmacc.vv v4, v2, v6, v0.t");
+  //              -95159.7034957902651513,  353690458.8370813727378845,
+  //              -89272.3172746254567755, -2537572977.5412845611572266,
+  //              98139.9797031646012329, -2125331270.8559157848358154,
+  //              67788.7602550606534351,  1514813534.1183013916015625,
+  //              -68056.0128839309472824, -5859792188.5645341873168945,
+  //              21060.8546093095501419,  5090653244.5816955566406250,
+  //              83261.7813338561973069, -3112554462.7102732658386230,
+  //              32602.1877863906847779,  734216828.7275727987289429
+  VCMP_U64(4, v4, 0xc0f73b7b4184cd41, 0x41b514e35ad64af7, 0xc0f5cb85138e8ec3,
+           0xc1e2e8094e315234, 0x40f7f5bfacdd39bc, 0xc1dfab7ed1b6c753,
+           0x40f08ccc2a0135e2, 0x41d6928e17879240, 0xc0f09d8034c5c7e1,
+           0xc1f5d45553c90855, 0x40d49136b1eb3ed8, 0x41f2f6d343c94ea0,
+           0x40f453dc8057edfa, 0xc1e730b9fbd6ba8f, 0x40dfd68c04b135a8,
+           0x41c5e1a13e5d211b);
+};
+
+// Simple random test with similar values (vector-scalar)
+void TEST_CASE3(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //               85.2500, -7.6602, -81.8125, -37.2500,
+  //               -48.0000,  14.9531,  25.9844,  96.1875,  46.5000,
+  //               -77.4375,  45.5312, -68.7500,  58.8438, -70.5625, -45.9375,
+  //               -90.5000
+  VLOAD_16(v2, 0x5554, 0xc7a9, 0xd51d, 0xd0a8, 0xd200, 0x4b7a, 0x4e7f, 0x5603,
+           0x51d0, 0xd4d7, 0x51b1, 0xd44c, 0x535b, 0xd469, 0xd1be, 0xd5a8);
+  //                             -47.9375
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0xd1fe);
+  //               6.19335365, -81.26284790,
+  //               -77.74858093,  15.38204670,  27.37081337,  48.81098938,
+  //               -82.18785095,  3.87765026, -34.03960037,
+  //               -92.34690857,  46.98464203,  28.09385681,  58.44809723,  57.04935455,
+  //               -44.62148285,  83.52678680
+  VLOAD_32(v4, 0x40c62ff4, 0xc2a28694, 0xc29b7f46, 0x41761cdd, 0x41daf76d,
+           0x42433e74, 0xc2a4602e, 0x40782b6c, 0xc208288d, 0xc2b8b19e,
+           0x423bf046, 0x41e0c038, 0x4269cada, 0x4264328a, 0xc2327c66,
+           0x42a70db7);
+  asm volatile("vfwnmacc.vf v4, %[A], v2" ::[A] "f"(dscalar_16));
+  //               4080.47851562, -285.94589233, -3844.13818359, -1801.05395508,
+  //               -2328.37084961,  668.00445557,  1327.81384277, 4607.11083984,
+  //               2263.13330078, -3619.81323242,  2135.66967773,
+  //               -3323.79687500,  2762.37426758, -3439.63916016,
+  //               -2157.50732422, -4421.87060547
+  VCMP_U32(5, v4, 0x457f07a8, 0xc38ef913, 0xc5704236, 0xc4e121ba, 0xc51185ef,
+           0x44270049, 0x44a5fa0b, 0x458ff8e3, 0x450d7222, 0xc5623d03,
+           0x45057ab7, 0xc54fbcc0, 0x452ca5fd, 0xc556fa3a, 0xc506d81e,
+           0xc58a2ef7);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //               415907.75000000,  16644.92773438, -320087.15625000,
+  //               -560497.81250000,  51200.66406250,  175961.67187500,
+  //               -62272.61328125, -40134.65234375,  67972.27343750,
+  //               832511.06250000, -279323.15625000, -48243.37500000,
+  //               685093.43750000,  272952.25000000,  518086.00000000,
+  //               -349626.18750000
+  VLOAD_32(v2, 0x48cb1478, 0x468209db, 0xc89c4ae5, 0xc908d71d, 0x474800aa,
+           0x482bd66b, 0xc773409d, 0xc71cc6a7, 0x4784c223, 0x494b3ff1,
+           0xc8886365, 0xc73c7360, 0x49274257, 0x48854708, 0x48fcf8c0,
+           0xc8aab746);
+  //                              -648299.93750000
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0xc91e46bf);
+  //              -3761.4446916116867214,  251037.4171459318604320,
+  //              -832277.7590174797223881, -817938.7112226528115571,
+  //              -640813.8540152770001441, -87111.6097838475834578,
+  //              -748981.3983645441476256,  259451.7965630525723100,
+  //              -469164.5467169298790395, -204901.8221613015048206,
+  //              97767.4262132318690419, -208046.9794710964197293,
+  //              -303699.6372622016351670, -710697.5104083393234760,
+  //              -907884.7086961114546284, -326406.2730544115183875
+  VLOAD_64(v4, 0xc0ad62e3ae9e7200, 0x410ea4eb56509b38, 0xc129662b849df069,
+           0xc128f6256c256024, 0xc1238e5bb5417d8a, 0xc0f54479c1acb530,
+           0xc126db6acbf67002, 0x410fabde5f5c7320, 0xc11ca2b22fd69018,
+           0xc109032e93c94df0, 0x40f7de76d1c4f740, 0xc1096577d5f4f134,
+           0xc112894e8c8e766c, 0xc125b05305543dea, 0xc12bb4d96ada377b,
+           0xc113ec19179b935e);
+  asm volatile("vfwnmacc.vf v4, %[A], v2" ::[A] "f"(dscalar_32));
+  //               269632972092.2103271484375000,  10790654572.4701824188232422,
+  //               -207511651113.6687316894531250,
+  //               -363369878873.9254760742187500, 33194028125.5312614440917969,
+  //               114076027990.5677947998046875, -40370582316.7976837158203125,
+  //               -26019552057.8339157104492188,  44066889785.8108749389648438,
+  //               539717074688.6307373046875000,
+  //               -181085282506.6039428710937500,
+  //               -31275968950.3095932006835938, 444146336412.5474243164062500,
+  //               176955637312.9947814941406250, 335876029304.3336791992187500,
+  //               -226662309098.3402404785156250
+  VCMP_U64(6, v4, 0x424f63b0529e1aec, 0x420419629363c2ef, 0xc24828544194d599,
+           0xc25526a215567b3b, 0x421eea12b1762003, 0x423a8f760c56915b,
+           0xc222cc8c6659986a, 0xc2183b8b6ce755ee, 0x4224852ec0739f2b,
+           0x425f6a693fc0285e, 0xc24514c310654d4e, 0xc21d20c5a6d93d06,
+           0x4259da4bd0a72309, 0x424499b05f207f55, 0x42538cf15ede155b,
+           0xc24a63102e752b8d);
+};
+
+// Simple random test with similar values (vector-scalar) (masked)
+void TEST_CASE4(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //                85.2500, -7.6602, -81.8125, -37.2500,
+  //                -48.0000,  14.9531,  25.9844,  96.1875,  46.5000,
+  //                -77.4375,  45.5312, -68.7500,  58.8438, -70.5625, -45.9375,
+  //                -90.5000
+  VLOAD_16(v2, 0x5554, 0xc7a9, 0xd51d, 0xd0a8, 0xd200, 0x4b7a, 0x4e7f, 0x5603,
+           0x51d0, 0xd4d7, 0x51b1, 0xd44c, 0x535b, 0xd469, 0xd1be, 0xd5a8);
+  //                             -47.9375
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0xd1fe);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //                6.19335365, -81.26284790,
+  //                -77.74858093,  15.38204670,  27.37081337,  48.81098938,
+  //                -82.18785095,  3.87765026, -34.03960037,
+  //                -92.34690857,  46.98464203,  28.09385681,  58.44809723,  57.04935455,
+  //                -44.62148285,  83.52678680
+  VLOAD_32(v4, 0x40c62ff4, 0xc2a28694, 0xc29b7f46, 0x41761cdd, 0x41daf76d,
+           0x42433e74, 0xc2a4602e, 0x40782b6c, 0xc208288d, 0xc2b8b19e,
+           0x423bf046, 0x41e0c038, 0x4269cada, 0x4264328a, 0xc2327c66,
+           0x42a70db7);
+  asm volatile("vfwnmacc.vf v4, %[A], v2, v0.t" ::[A] "f"(dscalar_16));
+  //                6.19335365, -285.94589233, -77.74858093,
+  //                -1801.05395508,  27.37081337,  668.00445557, -82.18785095,
+  //                4607.11083984, -34.03960037, -3619.81323242,  46.98464203,
+  //                -3323.79687500,  58.44809723, -3439.63916016, -44.62148285,
+  //                -4421.87060547
+  VCMP_U32(7, v4, 0x40c62ff4, 0xc38ef913, 0xc29b7f46, 0xc4e121ba, 0x41daf76d,
+           0x44270049, 0xc2a4602e, 0x458ff8e3, 0xc208288d, 0xc5623d03,
+           0x423bf046, 0xc54fbcc0, 0x4269cada, 0xc556fa3a, 0xc2327c66,
+           0xc58a2ef7);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                415907.75000000,  16644.92773438, -320087.15625000,
+  //                -560497.81250000,  51200.66406250,  175961.67187500,
+  //                -62272.61328125, -40134.65234375,  67972.27343750,
+  //                832511.06250000, -279323.15625000, -48243.37500000,
+  //                685093.43750000,  272952.25000000,  518086.00000000,
+  //                -349626.18750000
+  VLOAD_32(v2, 0x48cb1478, 0x468209db, 0xc89c4ae5, 0xc908d71d, 0x474800aa,
+           0x482bd66b, 0xc773409d, 0xc71cc6a7, 0x4784c223, 0x494b3ff1,
+           0xc8886365, 0xc73c7360, 0x49274257, 0x48854708, 0x48fcf8c0,
+           0xc8aab746);
+  //                              -648299.93750000
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0xc91e46bf);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //               -3761.4446916116867214,  251037.4171459318604320,
+  //               -832277.7590174797223881, -817938.7112226528115571,
+  //               -640813.8540152770001441, -87111.6097838475834578,
+  //               -748981.3983645441476256,  259451.7965630525723100,
+  //               -469164.5467169298790395, -204901.8221613015048206,
+  //               97767.4262132318690419, -208046.9794710964197293,
+  //               -303699.6372622016351670, -710697.5104083393234760,
+  //               -907884.7086961114546284, -326406.2730544115183875
+  VLOAD_64(v4, 0xc0ad62e3ae9e7200, 0x410ea4eb56509b38, 0xc129662b849df069,
+           0xc128f6256c256024, 0xc1238e5bb5417d8a, 0xc0f54479c1acb530,
+           0xc126db6acbf67002, 0x410fabde5f5c7320, 0xc11ca2b22fd69018,
+           0xc109032e93c94df0, 0x40f7de76d1c4f740, 0xc1096577d5f4f134,
+           0xc112894e8c8e766c, 0xc125b05305543dea, 0xc12bb4d96ada377b,
+           0xc113ec19179b935e);
+  asm volatile("vfwnmacc.vf v4, %[A], v2, v0.t" ::[A] "f"(dscalar_32));
+  //               -3761.4446916116867214,  10790654572.4701824188232422,
+  //               -832277.7590174797223881, -363369878873.9254760742187500,
+  //               -640813.8540152770001441,  114076027990.5677947998046875,
+  //               -748981.3983645441476256, -26019552057.8339157104492188,
+  //               -469164.5467169298790395,  539717074688.6307373046875000,
+  //               97767.4262132318690419, -31275968950.3095932006835938,
+  //               -303699.6372622016351670,  176955637312.9947814941406250,
+  //               -907884.7086961114546284, -226662309098.3402404785156250
+  VCMP_U64(8, v4, 0xc0ad62e3ae9e7200, 0x420419629363c2ef, 0xc129662b849df069,
+           0xc25526a215567b3b, 0xc1238e5bb5417d8a, 0x423a8f760c56915b,
+           0xc126db6acbf67002, 0xc2183b8b6ce755ee, 0xc11ca2b22fd69018,
+           0x425f6a693fc0285e, 0x40f7de76d1c4f740, 0xc21d20c5a6d93d06,
+           0xc112894e8c8e766c, 0x424499b05f207f55, 0xc12bb4d96ada377b,
+           0xc24a63102e752b8d);
+};
+
+int main(void) {
+  enable_vec();
+  enable_fp();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vfwnmsac.c b/apps/riscv-tests/isa/rv64uv/vfwnmsac.c
new file mode 100644
index 0000000..8bc4176
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vfwnmsac.c
@@ -0,0 +1,347 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+//         Matteo Perotti <mperotti@iis.ee.ethz.ch>
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+// Simple random test with similar values
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  //              -27.1719,  16.3438, -76.1250,  73.7500,  39.2500,  32.8438,
+  //              -48.0312, -62.9062, -52.3125,  50.8750, -32.1562, -86.3750,
+  //              -42.7812,  97.2500, -83.6250,  46.6250
+  VLOAD_16(v2, 0xcecb, 0x4c16, 0xd4c2, 0x549c, 0x50e8, 0x501b, 0xd201, 0xd3dd,
+           0xd28a, 0x525c, 0xd005, 0xd566, 0xd159, 0x5614, 0xd53a, 0x51d4);
+  //              -18.1719, -46.5312, -72.7500,
+  //              -78.0625,  13.7344,  6.3164,  19.1250,  23.3125,  72.4375,
+  //              -53.2812, -16.3438, -95.0625, -96.2500,  10.4141,
+  //              -44.4688,  42.5938
+  VLOAD_16(v6, 0xcc8b, 0xd1d1, 0xd48c, 0xd4e1, 0x4ade, 0x4651, 0x4cc8, 0x4dd4,
+           0x5487, 0xd2a9, 0xcc16, 0xd5f1, 0xd604, 0x4935, 0xd18f, 0x5153);
+  //               69.72727966,  14.41778183,
+  //               -64.82620239,  5.66590357,  73.33881378,
+  //               -23.97786140,  94.91672516,  17.38204765, -39.07393646,
+  //               -50.71182251, -11.98221493, -36.07648849,
+  //               -86.86090088,  55.96418381,  61.43484116, -88.02533722
+  VLOAD_32(v4, 0x428b745e, 0x4166af3c, 0xc281a704, 0x40b54f15, 0x4292ad79,
+           0xc1bfd2a9, 0x42bdd55d, 0x418b0e6f, 0xc21c4bb6, 0xc24ad8e8,
+           0xc13fb727, 0xc2104e53, 0xc2adb8c8, 0x425fdb53, 0x4275bd47,
+           0xc2b00cf9);
+  asm volatile("vfwnmsac.vv v4, v2, v6");
+  //              -424.03662109,  774.91290283, -5602.91992188,  5762.77539062,
+  //              -465.73541260, -231.43232727,  1013.51440430,  1483.88403320,
+  //              3750.31274414,  2659.97167969, -537.53594971, -8247.09960938,
+  //              -4204.55615234, -956.80340576, -3657.26440430, -2073.95898438
+  VCMP_U32(1, v4, 0xc3d404b0, 0x4441ba6d, 0xc5af175c, 0x45b41634, 0xc3e8de22,
+           0xc3676ead, 0x447d60ec, 0x44b97c4a, 0x456a6501, 0x45263f8c,
+           0xc406624d, 0xc600dc66, 0xc5836473, 0xc46f336b, 0xc564943b,
+           0xc5019f58);
+
+  VSET(16, e32, m1);
+  //               76109.13281250,  56176.41406250, -69127.14843750,
+  //               -80327.49218750,  42920.59375000, -22857.18164062,
+  //               -74227.70312500, -2650.23828125,  34254.71093750,
+  //               -45853.78125000,  16339.80859375,
+  //               -48032.71875000,  49.54582977, -47754.19921875,
+  //               -95663.35156250,  82512.11718750
+  VLOAD_32(v2, 0x4794a691, 0x475b706a, 0xc7870393, 0xc79ce3bf, 0x4727a898,
+           0xc6b2925d, 0xc790f9da, 0xc525a3d0, 0x4705ceb6, 0xc7331dc8,
+           0x467f4f3c, 0xc73ba0b8, 0x42462eee, 0xc73a8a33, 0xc7bad7ad,
+           0x47a1280f);
+  //              -36622.54296875, -60900.32421875, -36611.69921875,
+  //              -74411.05468750, -25865.60937500, -67159.76562500,
+  //              6145.43457031, -31624.23242188, -69962.68750000, 468.94165039,
+  //              10443.93554688, -6054.45410156, -26090.46093750,
+  //              83534.57031250,  49878.42968750, -62082.53125000
+  VLOAD_32(v6, 0xc70f0e8b, 0xc76de453, 0xc70f03b3, 0xc7915587, 0xc6ca1338,
+           0xc7832be2, 0x45c00b7a, 0xc6f71077, 0xc788a558, 0x43ea7888,
+           0x46232fbe, 0xc5bd33a2, 0xc6cbd4ec, 0x47a32749, 0x4742d66e,
+           0xc7728288);
+  //               69521.3925020728202071,  98263.6759213360201102,
+  //               -97991.2678309752518544, -63510.9471883209771477,
+  //               65329.9928102507547010, -34993.7523106171429390,
+  //               -15831.2510480509663466, -3510.3868967669695849,
+  //               47068.9415519913600292, -19802.3942476644588169,
+  //               25915.8242703938303748,  82619.8738822988234460,
+  //               36865.7501246419560630,  41236.4660055586136878,
+  //               -5735.0030344506667461,  97965.1847665070963558
+  VLOAD_64(v4, 0x40f0f91647b040e6, 0x40f7fd7ad092e40e, 0xc0f7ec74490921f9,
+           0xc0ef02de4f5de1b8, 0x40efe63fc51a00c4, 0xc0e1163812edb722,
+           0xc0ceeba02257b050, 0xc0ab6cc617554220, 0x40e6fb9e2131a44c,
+           0xc0d356993b5a8e58, 0x40d94ef4c0d89c24, 0x40f42bbdfb6c0160,
+           0x40e20038010564a4, 0x40e4228ee9847d40, 0xc0b66700c6dda260,
+           0x40f7ead2f4cdb996);
+  asm volatile("vfwnmsac.vv v4, v2, v6");
+  //               2787379508.1325840950012207,  3421260093.5289182662963867,
+  //               -2530960357.7114648818969727, -5977316925.0209798812866211,
+  //               1110232642.0733766555786133, -1535117955.5847384929656982,
+  //               456145661.6082201600074768, -83815261.7664972990751266,
+  //               2396598705.6646966934204102,  21482945.4617780297994614,
+  //               -170625991.9771288335323334, -290729271.1712532043457031,
+  //               1329539.2864317980129272,  3989167748.8218097686767578,
+  //               4771532019.5777149200439453,  5122659058.9813976287841797
+  VCMP_U64(2, v4, 0x41e4c48126843e21, 0x41e97d8927b0ece6, 0xc1e2db6c7cb6c452,
+           0xc1f64469e3d055ef, 0x41d08b339084b234, 0xc1d6e002a0e56c5b,
+           0x41bb303afd9bb451, 0xc193fbad7710e4ab, 0x41e1db2636354532,
+           0x41747cdc1763715c, 0xc1a457178ff44a3b, 0xc1b1542d372bd740,
+           0x4134498349539825, 0x41edb8bbd09a4c44, 0x41f1c67ccf393e52,
+           0x41f315592f2fb3ce);
+};
+
+// Simple random test with similar values (masked)
+// The numbers are the same of TEST_CASE1
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  //              -27.1719,  16.3438, -76.1250,  73.7500,  39.2500,  32.8438,
+  //              -48.0312, -62.9062, -52.3125,  50.8750, -32.1562, -86.3750,
+  //              -42.7812,  97.2500, -83.6250,  46.6250
+  VLOAD_16(v2, 0xcecb, 0x4c16, 0xd4c2, 0x549c, 0x50e8, 0x501b, 0xd201, 0xd3dd,
+           0xd28a, 0x525c, 0xd005, 0xd566, 0xd159, 0x5614, 0xd53a, 0x51d4);
+  //              -18.1719, -46.5312, -72.7500,
+  //              -78.0625,  13.7344,  6.3164,  19.1250,  23.3125,  72.4375,
+  //              -53.2812, -16.3438, -95.0625, -96.2500,  10.4141,
+  //              -44.4688,  42.5938
+  VLOAD_16(v6, 0xcc8b, 0xd1d1, 0xd48c, 0xd4e1, 0x4ade, 0x4651, 0x4cc8, 0x4dd4,
+           0x5487, 0xd2a9, 0xcc16, 0xd5f1, 0xd604, 0x4935, 0xd18f, 0x5153);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //               69.72727966,  14.41778183,
+  //               -64.82620239,  5.66590357,  73.33881378,
+  //               -23.97786140,  94.91672516,  17.38204765, -39.07393646,
+  //               -50.71182251, -11.98221493, -36.07648849,
+  //               -86.86090088,  55.96418381,  61.43484116, -88.02533722
+  VLOAD_32(v4, 0x428b745e, 0x4166af3c, 0xc281a704, 0x40b54f15, 0x4292ad79,
+           0xc1bfd2a9, 0x42bdd55d, 0x418b0e6f, 0xc21c4bb6, 0xc24ad8e8,
+           0xc13fb727, 0xc2104e53, 0xc2adb8c8, 0x425fdb53, 0x4275bd47,
+           0xc2b00cf9);
+  asm volatile("vfwnmsac.vv v4, v2, v6, v0.t");
+  //               69.72727966,  774.91290283, -64.82620239,
+  //               5762.77539062,  73.33881378, -231.43232727,  94.91672516,
+  //               1483.88403320, -39.07393646,  2659.97167969, -11.98221493,
+  //               -8247.09960938, -86.86090088, -956.80340576,  61.43484116,
+  //               -2073.95898438
+  VCMP_U32(3, v4, 0x428b745e, 0x4441ba6d, 0xc281a704, 0x45b41634, 0x4292ad79,
+           0xc3676ead, 0x42bdd55d, 0x44b97c4a, 0xc21c4bb6, 0x45263f8c,
+           0xc13fb727, 0xc600dc66, 0xc2adb8c8, 0xc46f336b, 0x4275bd47,
+           0xc5019f58);
+
+  VSET(16, e32, m1);
+  //               76109.13281250,  56176.41406250, -69127.14843750,
+  //               -80327.49218750,  42920.59375000, -22857.18164062,
+  //               -74227.70312500, -2650.23828125,  34254.71093750,
+  //               -45853.78125000,  16339.80859375,
+  //               -48032.71875000,  49.54582977, -47754.19921875,
+  //               -95663.35156250,  82512.11718750
+  VLOAD_32(v2, 0x4794a691, 0x475b706a, 0xc7870393, 0xc79ce3bf, 0x4727a898,
+           0xc6b2925d, 0xc790f9da, 0xc525a3d0, 0x4705ceb6, 0xc7331dc8,
+           0x467f4f3c, 0xc73ba0b8, 0x42462eee, 0xc73a8a33, 0xc7bad7ad,
+           0x47a1280f);
+  //              -36622.54296875, -60900.32421875, -36611.69921875,
+  //              -74411.05468750, -25865.60937500, -67159.76562500,
+  //              6145.43457031, -31624.23242188, -69962.68750000, 468.94165039,
+  //              10443.93554688, -6054.45410156, -26090.46093750,
+  //              83534.57031250,  49878.42968750, -62082.53125000
+  VLOAD_32(v6, 0xc70f0e8b, 0xc76de453, 0xc70f03b3, 0xc7915587, 0xc6ca1338,
+           0xc7832be2, 0x45c00b7a, 0xc6f71077, 0xc788a558, 0x43ea7888,
+           0x46232fbe, 0xc5bd33a2, 0xc6cbd4ec, 0x47a32749, 0x4742d66e,
+           0xc7728288);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //               69521.3925020728202071,  98263.6759213360201102,
+  //               -97991.2678309752518544, -63510.9471883209771477,
+  //               65329.9928102507547010, -34993.7523106171429390,
+  //               -15831.2510480509663466, -3510.3868967669695849,
+  //               47068.9415519913600292, -19802.3942476644588169,
+  //               25915.8242703938303748,  82619.8738822988234460,
+  //               36865.7501246419560630,  41236.4660055586136878,
+  //               -5735.0030344506667461,  97965.1847665070963558
+  VLOAD_64(v4, 0x40f0f91647b040e6, 0x40f7fd7ad092e40e, 0xc0f7ec74490921f9,
+           0xc0ef02de4f5de1b8, 0x40efe63fc51a00c4, 0xc0e1163812edb722,
+           0xc0ceeba02257b050, 0xc0ab6cc617554220, 0x40e6fb9e2131a44c,
+           0xc0d356993b5a8e58, 0x40d94ef4c0d89c24, 0x40f42bbdfb6c0160,
+           0x40e20038010564a4, 0x40e4228ee9847d40, 0xc0b66700c6dda260,
+           0x40f7ead2f4cdb996);
+  asm volatile("vfwnmsac.vv v4, v2, v6, v0.t");
+  //               69521.3925020728202071,  3421260093.5289182662963867,
+  //               -97991.2678309752518544, -5977316925.0209798812866211,
+  //               65329.9928102507547010, -1535117955.5847384929656982,
+  //               -15831.2510480509663466, -83815261.7664972990751266,
+  //               47068.9415519913600292,  21482945.4617780297994614,
+  //               25915.8242703938303748, -290729271.1712532043457031,
+  //               36865.7501246419560630,  3989167748.8218097686767578,
+  //               -5735.0030344506667461,  5122659058.9813976287841797
+  VCMP_U64(4, v4, 0x40f0f91647b040e6, 0x41e97d8927b0ece6, 0xc0f7ec74490921f9,
+           0xc1f64469e3d055ef, 0x40efe63fc51a00c4, 0xc1d6e002a0e56c5b,
+           0xc0ceeba02257b050, 0xc193fbad7710e4ab, 0x40e6fb9e2131a44c,
+           0x41747cdc1763715c, 0x40d94ef4c0d89c24, 0xc1b1542d372bd740,
+           0x40e20038010564a4, 0x41edb8bbd09a4c44, 0xc0b66700c6dda260,
+           0x41f315592f2fb3ce);
+};
+
+// Simple random test with similar values (vector-scalar)
+void TEST_CASE3(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //               15.1797, -57.5312, -39.9688,  95.8125,  22.3906,
+  //               -30.2344,  61.3438,  67.1250, -80.6250, -20.6875, -34.1250,
+  //               -7.6758, -25.1562,  64.8125,  28.0156, -51.9688
+  VLOAD_16(v2, 0x4b97, 0xd331, 0xd0ff, 0x55fd, 0x4d99, 0xcf8f, 0x53ab, 0x5432,
+           0xd50a, 0xcd2c, 0xd044, 0xc7ad, 0xce4a, 0x540d, 0x4f01, 0xd27f);
+  //                             -27.7344
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0xceef);
+  //              -90.47762299, -89.97399139, -34.20752716,
+  //              -93.73470306,  81.75606537,  80.60296631,  73.45400238,
+  //              -61.63031769, -55.39078903,  21.99703789,  29.49930191,
+  //              -64.56553650, -17.54965782,  84.51310730, -88.96613312,
+  //              -6.75917578
+  VLOAD_32(v4, 0xc2b4f48b, 0xc2b3f2af, 0xc208d482, 0xc2bb782b, 0x42a3831b,
+           0x42a134b8, 0x4292e873, 0xc2768572, 0xc25d902b, 0x41aff9ef,
+           0x41ebfe92, 0xc281218e, 0xc18c65b3, 0x42a906b6, 0xc2b1eea9,
+           0xc0d84b2b);
+  asm volatile("vfwnmsac.vf v4, %[A], v2" ::[A] "f"(dscalar_16));
+  //               330.52151489, -1685.56726074, -1142.71582031,  2563.56518555,
+  //               702.74603271, -757.92852783,  1774.78454590,  1800.03955078,
+  //               -2291.47485352, -551.75787354, -916.93621826, -277.44854736,
+  //               -715.24255371,  1882.04724121,  688.02972412, -1448.07995605
+  VCMP_U32(5, v4, 0x43a542c1, 0xc4d2b227, 0xc48ed6e8, 0x4520390b, 0x442fafbf,
+           0xc43d7b6d, 0x44ddd91b, 0x44e10144, 0xc50f3799, 0xc409f081,
+           0xc4653beb, 0xc38ab96a, 0xc432cf86, 0x44eb4183, 0x442c01e7,
+           0xc4b5028f);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //               467373.87500000, -160965.29687500,  883060.25000000,
+  //               -737665.37500000, -482502.81250000, -983579.31250000,
+  //               -407525.09375000,  564889.31250000, -121145.03125000,
+  //               744798.75000000,  160985.04687500, -9122.68847656,
+  //               -708214.37500000,  763142.93750000, -340832.59375000,
+  //               -663023.75000000
+  VLOAD_32(v2, 0x48e435bc, 0xc81d3153, 0x49579744, 0xc9341816, 0xc8eb98da,
+           0xc97021b5, 0xc8c6fca3, 0x4909e995, 0xc7ec9c84, 0x4935d5ec,
+           0x481d3643, 0xc60e8ac1, 0xc92ce766, 0x493a506f, 0xc8a66c13,
+           0xc921defc);
+  //                               235169.78125000
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0x4865a872);
+  //              -460724.6105727200629190, -944938.6498861069558188,
+  //              -303510.4811713555827737, -748025.6652074699522927,
+  //              387702.0000469267833978, -894167.6638924945145845,
+  //              98379.0701996718998998, -950753.1128427713410929,
+  //              -749333.7338243273552507,  898522.0366696736309677,
+  //              -388606.5700500296661630,  47697.1169114386430010,
+  //              -665347.3327810273040086,  976438.6193965608254075,
+  //              -498588.0437998892739415,  793291.0511387982405722
+  VLOAD_64(v4, 0xc11c1ed27139f9a2, 0xc12cd6554cbddf2f, 0xc1128659ecb82f10,
+           0xc126d3f3549612d1, 0x4117a9d8000c4d34, 0xc12b49af53e9b790,
+           0x40f804b11f89b0f0, 0xc12d03c239c68719, 0xc126de2b77b7d27e,
+           0x412b6bb412c65e12, 0xc117b7fa47bb31ea, 0x40e74a23bdbd0eb0,
+           0xc1244e06aa62465a, 0x412dcc6d3d218bc8, 0xc11e6e702cd9e0d0,
+           0x412835961a2edd54);
+  asm volatile("vfwnmsac.vf v4, %[A], v2" ::[A] "f"(dscalar_32));
+  //              -109912672670.3254089355468750,  37853228716.2851715087890625,
+  //              -207669389333.5514831542968750, 173475856848.7839965820312500,
+  //              113470468570.1348114013671875,  231307237594.9865112304687500,
+  //              95837685530.1434478759765625, -132845846804.2007293701171875,
+  //              28488901164.8530883789062500, -175153260590.7367553710937500,
+  //              -37859206864.6847991943359375,  2145428350.5620102882385254,
+  //              166549954299.5226745605468750, -179467181235.7380371093750000,
+  //              80153027927.0138244628906250,  155923943542.1058349609375000
+  VCMP_U64(6, v4, 0xc239974e499e534e, 0x4221a074dd589202, 0xc2482d07b40ac697,
+           0x424431fbc0e8645a, 0x423a6b5df1da2283, 0x424aed7e2c6d7e46,
+           0x4236505f071a24b9, 0xc23eee3ac1143363, 0x421a884888b36990,
+           0xc24463f954175e4e, 0xc221a12b4da15e9e, 0x41dff828dfa3f7fa,
+           0x424363934f7dc2e7, 0xc244e489ee59de78, 0x4232a97e2557038a,
+           0x424226e5483b0d8c);
+};
+
+// Simple random test with similar values (vector-scalar) (masked)
+void TEST_CASE4(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //                15.1797, -57.5312, -39.9688,  95.8125,  22.3906,
+  //                -30.2344,  61.3438,  67.1250, -80.6250, -20.6875, -34.1250,
+  //                -7.6758, -25.1562,  64.8125,  28.0156, -51.9688
+  VLOAD_16(v2, 0x4b97, 0xd331, 0xd0ff, 0x55fd, 0x4d99, 0xcf8f, 0x53ab, 0x5432,
+           0xd50a, 0xcd2c, 0xd044, 0xc7ad, 0xce4a, 0x540d, 0x4f01, 0xd27f);
+  //                             -27.7344
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0xceef);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //               -90.47762299, -89.97399139, -34.20752716,
+  //               -93.73470306,  81.75606537,  80.60296631,  73.45400238,
+  //               -61.63031769, -55.39078903,  21.99703789,  29.49930191,
+  //               -64.56553650, -17.54965782,  84.51310730, -88.96613312,
+  //               -6.75917578
+  VLOAD_32(v4, 0xc2b4f48b, 0xc2b3f2af, 0xc208d482, 0xc2bb782b, 0x42a3831b,
+           0x42a134b8, 0x4292e873, 0xc2768572, 0xc25d902b, 0x41aff9ef,
+           0x41ebfe92, 0xc281218e, 0xc18c65b3, 0x42a906b6, 0xc2b1eea9,
+           0xc0d84b2b);
+  asm volatile("vfwnmsac.vf v4, %[A], v2, v0.t" ::[A] "f"(dscalar_16));
+  //               -90.47762299, -1685.56726074, -34.20752716,
+  //               2563.56518555,  81.75606537, -757.92852783,  73.45400238,
+  //               1800.03955078, -55.39078903, -551.75787354,  29.49930191,
+  //               -277.44854736, -17.54965782,  1882.04724121, -88.96613312,
+  //               -1448.07995605
+  VCMP_U32(7, v4, 0xc2b4f48b, 0xc4d2b227, 0xc208d482, 0x4520390b, 0x42a3831b,
+           0xc43d7b6d, 0x4292e873, 0x44e10144, 0xc25d902b, 0xc409f081,
+           0x41ebfe92, 0xc38ab96a, 0xc18c65b3, 0x44eb4183, 0xc2b1eea9,
+           0xc4b5028f);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                467373.87500000, -160965.29687500,  883060.25000000,
+  //                -737665.37500000, -482502.81250000, -983579.31250000,
+  //                -407525.09375000,  564889.31250000, -121145.03125000,
+  //                744798.75000000,  160985.04687500, -9122.68847656,
+  //                -708214.37500000,  763142.93750000, -340832.59375000,
+  //                -663023.75000000
+  VLOAD_32(v2, 0x48e435bc, 0xc81d3153, 0x49579744, 0xc9341816, 0xc8eb98da,
+           0xc97021b5, 0xc8c6fca3, 0x4909e995, 0xc7ec9c84, 0x4935d5ec,
+           0x481d3643, 0xc60e8ac1, 0xc92ce766, 0x493a506f, 0xc8a66c13,
+           0xc921defc);
+  //                               235169.78125000
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0x4865a872);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  //               -460724.6105727200629190, -944938.6498861069558188,
+  //               -303510.4811713555827737, -748025.6652074699522927,
+  //               387702.0000469267833978, -894167.6638924945145845,
+  //               98379.0701996718998998, -950753.1128427713410929,
+  //               -749333.7338243273552507,  898522.0366696736309677,
+  //               -388606.5700500296661630,  47697.1169114386430010,
+  //               -665347.3327810273040086,  976438.6193965608254075,
+  //               -498588.0437998892739415,  793291.0511387982405722
+  VLOAD_64(v4, 0xc11c1ed27139f9a2, 0xc12cd6554cbddf2f, 0xc1128659ecb82f10,
+           0xc126d3f3549612d1, 0x4117a9d8000c4d34, 0xc12b49af53e9b790,
+           0x40f804b11f89b0f0, 0xc12d03c239c68719, 0xc126de2b77b7d27e,
+           0x412b6bb412c65e12, 0xc117b7fa47bb31ea, 0x40e74a23bdbd0eb0,
+           0xc1244e06aa62465a, 0x412dcc6d3d218bc8, 0xc11e6e702cd9e0d0,
+           0x412835961a2edd54);
+  asm volatile("vfwnmsac.vf v4, %[A], v2, v0.t" ::[A] "f"(dscalar_32));
+  //               -460724.6105727200629190,  37853228716.2851715087890625,
+  //               -303510.4811713555827737,  173475856848.7839965820312500,
+  //               387702.0000469267833978,  231307237594.9865112304687500,
+  //               98379.0701996718998998, -132845846804.2007293701171875,
+  //               -749333.7338243273552507, -175153260590.7367553710937500,
+  //               -388606.5700500296661630,  2145428350.5620102882385254,
+  //               -665347.3327810273040086, -179467181235.7380371093750000,
+  //               -498588.0437998892739415,  155923943542.1058349609375000
+  VCMP_U64(8, v4, 0xc11c1ed27139f9a2, 0x4221a074dd589202, 0xc1128659ecb82f10,
+           0x424431fbc0e8645a, 0x4117a9d8000c4d34, 0x424aed7e2c6d7e46,
+           0x40f804b11f89b0f0, 0xc23eee3ac1143363, 0xc126de2b77b7d27e,
+           0xc24463f954175e4e, 0xc117b7fa47bb31ea, 0x41dff828dfa3f7fa,
+           0xc1244e06aa62465a, 0xc244e489ee59de78, 0xc11e6e702cd9e0d0,
+           0x424226e5483b0d8c);
+};
+
+int main(void) {
+  enable_vec();
+  enable_fp();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vfwredosum.c b/apps/riscv-tests/isa/rv64uv/vfwredosum.c
new file mode 100644
index 0000000..b07ee99
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vfwredosum.c
@@ -0,0 +1,268 @@
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Xiaorui Yin <yinx@student.ethz.ch>
+// Date: 2022/05/03
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+// Naive test
+void TEST_CASE1(void) {
+  VSET(1, e32, m1);
+  VLOAD_32(v2, 0x3F800000);
+  VSET(16, e16, m1);
+  // 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
+  VLOAD_16(v6, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800,
+           0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800);
+  asm volatile("vfwredosum.vs v4, v6, v2");
+  VCMP_U32(1, v4, 0x42920000);
+}
+
+// Masked naive test
+void TEST_CASE2(void) {
+  VSET(1, e64, m1);
+  VLOAD_64(v2, 0x3FF0000000000000);
+  VSET(16, e32, m1);
+  VLOAD_32(v6, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  asm volatile("vfwredosum.vs v4, v6, v2");
+  VCMP_U64(2, v4, 0x4052400000000000);
+
+  VSET(1, e32, m1);
+  VLOAD_32(v2, 0x3F800000);
+  VSET(2, e8, m1);
+  VLOAD_8(v0, 0xaa, 0x55);
+  VSET(16, e16, m1);
+  // 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
+  VLOAD_16(v6, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800,
+           0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800);
+  asm volatile("vfwredosum.vs v4, v6, v2, v0.t");
+  VCMP_U32(3, v4, 0x42140000);
+
+  VSET(1, e64, m1);
+  VLOAD_64(v2, 0x3FF0000000000000);
+  VSET(2, e8, m1);
+  VLOAD_8(v0, 0xaa, 0x55);
+  VSET(16, e32, m1);
+  VLOAD_32(v6, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  asm volatile("vfwredosum.vs v4, v6, v2, v0.t");
+  VCMP_U64(4, v4, 0x4042800000000000);
+}
+
+// Are we respecting the undisturbed tail policy?
+void TEST_CASE3(void) {
+  VSET(16, e16, m1);
+  // 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
+  VLOAD_16(v6, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800,
+           0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800);
+  VLOAD_32(v2, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  VLOAD_32(v4, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  asm volatile("vfwredosum.vs v4, v6, v2");
+  VCMP_U32(5, v4, 0x42920000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v6, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  VLOAD_64(v2, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v4, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  asm volatile("vfwredosum.vs v4, v6, v2");
+  VCMP_U64(6, v4, 0x4052400000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+}
+
+// Odd number of elements, undisturbed policy
+void TEST_CASE4(void) {
+  VSET(1, e32, m1);
+  VLOAD_32(v6, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  VLOAD_64(v2, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v4, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  asm volatile("vfwredosum.vs v4, v6, v2");
+  VCMP_U64(7, v4, 0x4000000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+
+  VSET(3, e32, m1);
+  VLOAD_32(v6, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  VLOAD_64(v2, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v4, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  asm volatile("vfwredosum.vs v4, v6, v2");
+  VCMP_U64(8, v4, 0x401C000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+
+  VSET(7, e32, m1);
+  VLOAD_32(v6, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  VLOAD_64(v2, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v4, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  asm volatile("vfwredosum.vs v4, v6, v2");
+  VCMP_U64(9, v4, 0x403d000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+
+  VSET(15, e32, m1);
+  VLOAD_32(v6, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  VLOAD_64(v2, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v4, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  asm volatile("vfwredosum.vs v4, v6, v2");
+  VCMP_U64(10, v4, 0x4050400000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+}
+
+// Odd number of elements, undisturbed policy, and mask
+void TEST_CASE5(void) {
+  VSET(7, e16, m1);
+  VLOAD_8(v0, 0x00, 0xff);
+  // 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
+  VLOAD_16(v6, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800,
+           0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800);
+  VLOAD_32(v2, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  VLOAD_32(v4, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  asm volatile("vfwredosum.vs v4, v6, v2, v0.t");
+  VCMP_U32(11, v4, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+
+  VSET(1, e32, m1);
+  VLOAD_8(v0, 0xff, 0x00);
+  VLOAD_32(v6, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  VLOAD_64(v2, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v4, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  asm volatile("vfwredosum.vs v4, v6, v2, v0.t");
+  VCMP_U64(12, v4, 0x4000000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+  enable_fp();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vfwredusum.c b/apps/riscv-tests/isa/rv64uv/vfwredusum.c
new file mode 100644
index 0000000..b07246d
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vfwredusum.c
@@ -0,0 +1,272 @@
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Xiaorui Yin <yinx@student.ethz.ch>
+// Date: 2022/05/03
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+// Naive test
+void TEST_CASE1(void) {
+  // WARNING: setting vl == 1 is mandatory here since
+  // these variables are initialized on the stack, which is
+  // immediately before the UART.
+  // Loading more values would load from the UART
+  // addr space!!!!
+  VSET(1, e32, m1);
+  VLOAD_32(v2, 0x3F800000);
+  VSET(16, e16, m1);
+  // 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
+  VLOAD_16(v6, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800,
+           0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800);
+  asm volatile("vfwredsum.vs v4, v6, v2");
+  VCMP_U32(1, v4, 0x42920000);
+}
+
+// Masked naive test
+void TEST_CASE2(void) {
+  VSET(1, e64, m1);
+  VLOAD_64(v2, 0x3FF0000000000000);
+  VSET(16, e32, m1);
+  VLOAD_32(v6, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  asm volatile("vfwredsum.vs v4, v6, v2");
+  VCMP_U64(2, v4, 0x4052400000000000);
+
+  VSET(1, e32, m1);
+  VLOAD_32(v2, 0x3F800000);
+  VSET(16, e16, m1);
+  VLOAD_8(v0, 0xaa, 0x55);
+  // 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
+  VLOAD_16(v6, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800,
+           0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800);
+  asm volatile("vfwredsum.vs v4, v6, v2, v0.t");
+  VCMP_U32(3, v4, 0x42140000);
+
+  VSET(1, e64, m1);
+  VLOAD_64(v2, 0x3FF0000000000000);
+  VSET(16, e32, m1);
+  VLOAD_8(v0, 0xaa, 0x55);
+  VLOAD_32(v6, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  VLOAD_64(v2, 0x3FF0000000000000);
+  asm volatile("vfwredsum.vs v4, v6, v2, v0.t");
+  VCMP_U64(4, v4, 0x4042800000000000);
+}
+
+// Are we respecting the undisturbed tail policy?
+void TEST_CASE3(void) {
+  VSET(16, e16, m1);
+  // 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
+  VLOAD_16(v6, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800,
+           0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800);
+  VLOAD_32(v2, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  VLOAD_32(v4, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  asm volatile("vfwredsum.vs v4, v6, v2");
+  VCMP_U32(5, v4, 0x42920000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v6, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  VLOAD_64(v2, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v4, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  asm volatile("vfwredsum.vs v4, v6, v2");
+  VCMP_U64(6, v4, 0x4052400000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+}
+
+// Odd number of elements, undisturbed policy
+void TEST_CASE4(void) {
+  VSET(1, e32, m1);
+  VLOAD_32(v6, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  VLOAD_64(v2, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v4, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  asm volatile("vfwredsum.vs v4, v6, v2");
+  VCMP_U64(7, v4, 0x4000000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+
+  VSET(3, e32, m1);
+  VLOAD_32(v6, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  VLOAD_64(v2, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v4, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  asm volatile("vfwredsum.vs v4, v6, v2");
+  VCMP_U64(8, v4, 0x401C000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+
+  VSET(7, e32, m1);
+  VLOAD_32(v6, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  VLOAD_64(v2, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v4, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  asm volatile("vfwredsum.vs v4, v6, v2");
+  VCMP_U64(9, v4, 0x403d000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+
+  VSET(15, e32, m1);
+  VLOAD_32(v6, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  VLOAD_64(v2, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v4, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  asm volatile("vfwredsum.vs v4, v6, v2");
+  VCMP_U64(10, v4, 0x4050400000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+}
+
+// Odd number of elements, undisturbed policy, and mask
+void TEST_CASE5(void) {
+  VSET(7, e16, m1);
+  VLOAD_8(v0, 0x00, 0xff);
+  // 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
+  VLOAD_16(v6, 0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800,
+           0x3c00, 0x4000, 0x4200, 0x4400, 0x4500, 0x4600, 0x4700, 0x4800);
+  VLOAD_32(v2, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  VLOAD_32(v4, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  asm volatile("vfwredsum.vs v4, v6, v2, v0.t");
+  VCMP_U32(11, v4, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+
+  VSET(1, e32, m1);
+  VLOAD_8(v0, 0xff, 0x00);
+  VLOAD_32(v6, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
+           0x40C00000, 0x40E00000, 0x41000000, 0x3F800000, 0x40000000,
+           0x40400000, 0x40800000, 0x40A00000, 0x40C00000, 0x40E00000,
+           0x41000000);
+  VLOAD_64(v2, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  VLOAD_64(v4, 0x3FF0000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+  asm volatile("vfwredsum.vs v4, v6, v2, v0.t");
+  VCMP_U64(12, v4, 0x4000000000000000, 0x4000000000000000, 0x4008000000000000,
+           0x4010000000000000, 0x4014000000000000, 0x4018000000000000,
+           0x401C000000000000, 0x4020000000000000, 0x3FF0000000000000,
+           0x4000000000000000, 0x4008000000000000, 0x4010000000000000,
+           0x4014000000000000, 0x4018000000000000, 0x401C000000000000,
+           0x4020000000000000);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+  enable_fp();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vfwsub.c b/apps/riscv-tests/isa/rv64uv/vfwsub.c
new file mode 100644
index 0000000..452085a
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vfwsub.c
@@ -0,0 +1,519 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+//         Matteo Perotti <mperotti@iis.ee.ethz.ch>
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+// Simple random test with similar values
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  //              -15.5625,  95.7500, -42.4375,  30.7188, -50.7500, -90.2500,
+  //              -95.5000,  29.5938, -41.4062, -94.0000,  34.3438,
+  //              -69.5625,  31.5625, -75.0625,  46.2500, -63.6875
+  VLOAD_16(v2, 0xcbc8, 0x55fc, 0xd14e, 0x4fae, 0xd258, 0xd5a4, 0xd5f8, 0x4f66,
+           0xd12d, 0xd5e0, 0x504b, 0xd459, 0x4fe4, 0xd4b1, 0x51c8, 0xd3f6);
+  //               57.2500,  43.2812, -49.4062, -53.5625, -54.7812,
+  //               -12.1406,  92.1875,  67.1875, -19.7656, -41.2812,  98.0625,
+  //               -41.9062,  10.1719, -84.6250, -7.1016,  62.8750
+  VLOAD_16(v6, 0x5328, 0x5169, 0xd22d, 0xd2b2, 0xd2d9, 0xca12, 0x55c3, 0x5433,
+           0xccf1, 0xd129, 0x5621, 0xd13d, 0x4916, 0xd54a, 0xc71a, 0x53dc);
+  asm volatile("vfwsub.vv v4, v2, v6");
+  //              -72.81250000,  52.46875000,  6.96875000,  84.28125000,  4.03125000,
+  //              -78.10937500, -187.68750000, -37.59375000, -21.64062500,
+  //              -52.71875000, -63.71875000,
+  //              -27.65625000,  21.39062500,  9.56250000,  53.35156250,
+  //              -126.56250000
+  VCMP_U32(1, v4, 0xc291a000, 0x4251e000, 0x40df0000, 0x42a89000, 0x40810000,
+           0xc29c3800, 0xc33bb000, 0xc2166000, 0xc1ad2000, 0xc252e000,
+           0xc27ee000, 0xc1dd4000, 0x41ab2000, 0x41190000, 0x42556800,
+           0xc2fd2000);
+
+  VSET(16, e32, m1);
+  //               74632.77343750, -65636.60937500,  16165.84765625,
+  //               -17815.85937500, -85604.03125000, -76754.03125000,
+  //               21778.01171875, -70512.52343750,  85301.90625000,
+  //               -8385.11035156,  98258.05468750, -50421.53125000,
+  //               69842.53906250, -65219.96093750, -65266.08984375,
+  //               -90740.60156250
+  VLOAD_32(v2, 0x4791c463, 0xc780324e, 0x467c9764, 0xc68b2fb8, 0xc7a73204,
+           0xc795e904, 0x46aa2406, 0xc789b843, 0x47a69af4, 0xc6030471,
+           0x47bfe907, 0xc744f588, 0x47886945, 0xc77ec3f6, 0xc77ef217,
+           0xc7b13a4d);
+  //               5391.72216797, -90760.36718750, -22961.19531250,
+  //               12708.62500000,  87107.59375000,  54867.48437500,
+  //               55424.39453125, -71436.00781250, -61505.46484375,
+  //               57701.78906250, -81581.38281250,  53319.19531250,
+  //               -86229.57031250,  44376.69531250,  46809.38671875,
+  //               -92887.27343750
+  VLOAD_32(v6, 0x45a87dc7, 0xc7b1442f, 0xc6b36264, 0x46469280, 0x47aa21cc,
+           0x4756537c, 0x47588065, 0xc78b8601, 0xc7704177, 0x476165ca,
+           0xc79f56b1, 0x47504732, 0xc7a86ac9, 0x472d58b2, 0x4736d963,
+           0xc7b56ba3);
+  asm volatile("vfwsub.vv v4, v2, v6");
+  //               69241.0512695312500000,  25123.7578125000000000,
+  //               39127.0429687500000000, -30524.4843750000000000,
+  //               -172711.6250000000000000, -131621.5156250000000000,
+  //               -33646.3828125000000000,  923.4843750000000000,
+  //               146807.3710937500000000, -66086.8994140625000000,
+  //               179839.4375000000000000, -103740.7265625000000000,
+  //               156072.1093750000000000, -109596.6562500000000000,
+  //               -112075.4765625000000000,  2146.6718750000000000
+  VCMP_U64(2, v4, 0x40f0e790d2000000, 0x40d888f080000000, 0x40e31ae160000000,
+           0xc0ddcf1f00000000, 0xc105153d00000000, 0xc100112c20000000,
+           0xc0e06dcc40000000, 0x408cdbe000000000, 0x4101ebbaf8000000,
+           0xc0f0226e64000000, 0x4105f3fb80000000, 0xc0f953cba0000000,
+           0x41030d40e0000000, 0xc0fac1ca80000000, 0xc0fb5cb7a0000000,
+           0x40a0c55800000000);
+};
+
+// Simple random test with similar values (masked)
+// The numbers are the same of TEST_CASE1
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  //              -15.5625,  95.7500, -42.4375,  30.7188, -50.7500, -90.2500,
+  //              -95.5000,  29.5938, -41.4062, -94.0000,  34.3438,
+  //              -69.5625,  31.5625, -75.0625,  46.2500, -63.6875
+  VLOAD_16(v2, 0xcbc8, 0x55fc, 0xd14e, 0x4fae, 0xd258, 0xd5a4, 0xd5f8, 0x4f66,
+           0xd12d, 0xd5e0, 0x504b, 0xd459, 0x4fe4, 0xd4b1, 0x51c8, 0xd3f6);
+  //               57.2500,  43.2812, -49.4062, -53.5625, -54.7812,
+  //               -12.1406,  92.1875,  67.1875, -19.7656, -41.2812,  98.0625,
+  //               -41.9062,  10.1719, -84.6250, -7.1016,  62.8750
+  VLOAD_16(v6, 0x5328, 0x5169, 0xd22d, 0xd2b2, 0xd2d9, 0xca12, 0x55c3, 0x5433,
+           0xccf1, 0xd129, 0x5621, 0xd13d, 0x4916, 0xd54a, 0xc71a, 0x53dc);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfwsub.vv v4, v2, v6, v0.t");
+  //               0.00000000,  52.46875000,  0.00000000,  84.28125000,
+  //               0.00000000, -78.10937500,  0.00000000, -37.59375000,
+  //               0.00000000, -52.71875000,  0.00000000, -27.65625000,
+  //               0.00000000,  9.56250000,  0.00000000, -126.56250000
+  VCMP_U32(3, v4, 0x0, 0x4251e000, 0x0, 0x42a89000, 0x0, 0xc29c3800, 0x0,
+           0xc2166000, 0x0, 0xc252e000, 0x0, 0xc1dd4000, 0x0, 0x41190000, 0x0,
+           0xc2fd2000);
+
+  VSET(16, e32, m1);
+  //               74632.77343750, -65636.60937500,  16165.84765625,
+  //               -17815.85937500, -85604.03125000, -76754.03125000,
+  //               21778.01171875, -70512.52343750,  85301.90625000,
+  //               -8385.11035156,  98258.05468750, -50421.53125000,
+  //               69842.53906250, -65219.96093750, -65266.08984375,
+  //               -90740.60156250
+  VLOAD_32(v2, 0x4791c463, 0xc780324e, 0x467c9764, 0xc68b2fb8, 0xc7a73204,
+           0xc795e904, 0x46aa2406, 0xc789b843, 0x47a69af4, 0xc6030471,
+           0x47bfe907, 0xc744f588, 0x47886945, 0xc77ec3f6, 0xc77ef217,
+           0xc7b13a4d);
+  //               5391.72216797, -90760.36718750, -22961.19531250,
+  //               12708.62500000,  87107.59375000,  54867.48437500,
+  //               55424.39453125, -71436.00781250, -61505.46484375,
+  //               57701.78906250, -81581.38281250,  53319.19531250,
+  //               -86229.57031250,  44376.69531250,  46809.38671875,
+  //               -92887.27343750
+  VLOAD_32(v6, 0x45a87dc7, 0xc7b1442f, 0xc6b36264, 0x46469280, 0x47aa21cc,
+           0x4756537c, 0x47588065, 0xc78b8601, 0xc7704177, 0x476165ca,
+           0xc79f56b1, 0x47504732, 0xc7a86ac9, 0x472d58b2, 0x4736d963,
+           0xc7b56ba3);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfwsub.vv v4, v2, v6, v0.t");
+  //               0.0000000000000000,  25123.7578125000000000,
+  //               0.0000000000000000, -30524.4843750000000000,
+  //               0.0000000000000000, -131621.5156250000000000,
+  //               0.0000000000000000,  923.4843750000000000,
+  //               0.0000000000000000, -66086.8994140625000000,
+  //               0.0000000000000000, -103740.7265625000000000,
+  //               0.0000000000000000, -109596.6562500000000000,
+  //               0.0000000000000000,  2146.6718750000000000
+  VCMP_U64(4, v4, 0x0, 0x40d888f080000000, 0x0, 0xc0ddcf1f00000000, 0x0,
+           0xc100112c20000000, 0x0, 0x408cdbe000000000, 0x0, 0xc0f0226e64000000,
+           0x0, 0xc0f953cba0000000, 0x0, 0xc0fac1ca80000000, 0x0,
+           0x40a0c55800000000);
+};
+
+// Simple random test with similar values (vector-scalar)
+void TEST_CASE3(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //                              36.4375
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0x508e);
+  //               69.8125, -37.3125, -77.2500,  32.7188,
+  //               -83.0000,  76.3125,  14.9375,  72.5000,  39.6250,
+  //               -61.2188,  36.3438,  93.5000, -87.1875, -6.9258,  25.1094,
+  //               -96.8750
+  VLOAD_16(v2, 0x545d, 0xd0aa, 0xd4d4, 0x5017, 0xd530, 0x54c5, 0x4b78, 0x5488,
+           0x50f4, 0xd3a7, 0x508b, 0x55d8, 0xd573, 0xc6ed, 0x4e47, 0xd60e);
+  asm volatile("vfwsub.vf v4, v2, %[A]" ::[A] "f"(dscalar_16));
+  //               33.37500000, -73.75000000, -113.68750000, -3.71875000,
+  //               -119.43750000,  39.87500000,
+  //               -21.50000000,  36.06250000,  3.18750000, -97.65625000,
+  //               -0.09375000,  57.06250000, -123.62500000, -43.36328125,
+  //               -11.32812500, -133.31250000
+  VCMP_U32(5, v4, 0x42058000, 0xc2938000, 0xc2e36000, 0xc06e0000, 0xc2eee000,
+           0x421f8000, 0xc1ac0000, 0x42104000, 0x404c0000, 0xc2c35000,
+           0xbdc00000, 0x42644000, 0xc2f74000, 0xc22d7400, 0xc1354000,
+           0xc3055000);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                              -138614.20312500
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0xc8075d8d);
+  //               473107.93750000,  161975.07812500, -173044.89062500,
+  //               -322046.09375000, -485607.56250000, -613808.37500000,
+  //               -182790.53125000,  121114.44531250, -958537.81250000,
+  //               295217.40625000,  281159.84375000, -735195.87500000,
+  //               -783982.56250000,  420983.65625000,  954426.12500000,
+  //               -297052.53125000
+  VLOAD_32(v2, 0x48e7027e, 0x481e2dc5, 0xc828fd39, 0xc89d3fc3, 0xc8ed1cf2,
+           0xc915db06, 0xc83281a2, 0x47ec8d39, 0xc96a049d, 0x4890262d,
+           0x488948fb, 0xc9337dbe, 0xc93f66e9, 0x48cd8ef5, 0x496903a2,
+           0xc8910b91);
+  asm volatile("vfwsub.vf v4, v2, %[A]" ::[A] "f"(dscalar_32));
+  //               611722.1406250000000000,  300589.2812500000000000,
+  //               -34430.6875000000000000, -183431.8906250000000000,
+  //               -346993.3593750000000000, -475194.1718750000000000,
+  //               -44176.3281250000000000,  259728.6484375000000000,
+  //               -819923.6093750000000000,  433831.6093750000000000,
+  //               419774.0468750000000000, -596581.6718750000000000,
+  //               -645368.3593750000000000,  559597.8593750000000000,
+  //               1093040.3281250000000000, -158438.3281250000000000
+  VCMP_U64(6, v4, 0x4122ab1448000000, 0x411258b520000000, 0xc0e0cfd600000000,
+           0xc106643f20000000, 0xc1152dc570000000, 0xc11d00e8b0000000,
+           0xc0e5920a80000000, 0x410fb48530000000, 0xc12905a738000000,
+           0x411a7a9e70000000, 0x41199ef830000000, 0xc12234cb58000000,
+           0xc123b1f0b8000000, 0x412113dbb8000000, 0x4130adb054000000,
+           0xc1035732a0000000);
+};
+
+// Simple random test with similar values (vector-scalar) (masked)
+void TEST_CASE4(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //                              36.4375
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0x508e);
+  //                69.8125, -37.3125, -77.2500,  32.7188,
+  //                -83.0000,  76.3125,  14.9375,  72.5000,  39.6250,
+  //                -61.2188,  36.3438,  93.5000, -87.1875, -6.9258,  25.1094,
+  //                -96.8750
+  VLOAD_16(v2, 0x545d, 0xd0aa, 0xd4d4, 0x5017, 0xd530, 0x54c5, 0x4b78, 0x5488,
+           0x50f4, 0xd3a7, 0x508b, 0x55d8, 0xd573, 0xc6ed, 0x4e47, 0xd60e);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfwsub.vf v4, v2, %[A], v0.t" ::[A] "f"(dscalar_16));
+  //                0.00000000, -73.75000000,  0.00000000, -3.71875000,
+  //                0.00000000,  39.87500000,  0.00000000,  36.06250000,
+  //                0.00000000, -97.65625000,  0.00000000,  57.06250000,
+  //                0.00000000, -43.36328125,  0.00000000, -133.31250000
+  VCMP_U32(7, v4, 0x0, 0xc2938000, 0x0, 0xc06e0000, 0x0, 0x421f8000, 0x0,
+           0x42104000, 0x0, 0xc2c35000, 0x0, 0x42644000, 0x0, 0xc22d7400, 0x0,
+           0xc3055000);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                              -138614.20312500
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0xc8075d8d);
+  //                473107.93750000,  161975.07812500, -173044.89062500,
+  //                -322046.09375000, -485607.56250000, -613808.37500000,
+  //                -182790.53125000,  121114.44531250, -958537.81250000,
+  //                295217.40625000,  281159.84375000, -735195.87500000,
+  //                -783982.56250000,  420983.65625000,  954426.12500000,
+  //                -297052.53125000
+  VLOAD_32(v2, 0x48e7027e, 0x481e2dc5, 0xc828fd39, 0xc89d3fc3, 0xc8ed1cf2,
+           0xc915db06, 0xc83281a2, 0x47ec8d39, 0xc96a049d, 0x4890262d,
+           0x488948fb, 0xc9337dbe, 0xc93f66e9, 0x48cd8ef5, 0x496903a2,
+           0xc8910b91);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfwsub.vf v4, v2, %[A], v0.t" ::[A] "f"(dscalar_32));
+  //                0.0000000000000000,  300589.2812500000000000,
+  //                0.0000000000000000, -183431.8906250000000000,
+  //                0.0000000000000000, -475194.1718750000000000,
+  //                0.0000000000000000,  259728.6484375000000000,
+  //                0.0000000000000000,  433831.6093750000000000,
+  //                0.0000000000000000, -596581.6718750000000000,
+  //                0.0000000000000000,  559597.8593750000000000,
+  //                0.0000000000000000, -158438.3281250000000000
+  VCMP_U64(8, v4, 0x0, 0x411258b520000000, 0x0, 0xc106643f20000000, 0x0,
+           0xc11d00e8b0000000, 0x0, 0x410fb48530000000, 0x0, 0x411a7a9e70000000,
+           0x0, 0xc12234cb58000000, 0x0, 0x412113dbb8000000, 0x0,
+           0xc1035732a0000000);
+};
+// Simple random test with similar values
+void TEST_CASE5(void) {
+  VSET(16, e16, m1);
+  //              -92.15529633,  27.66998672,
+  //              -5.68499708,  78.95133209,  57.52299500,  15.45270920,  50.26883316,
+  //              46.63587189,  71.16806793, -80.68485260,
+  //              -22.34193420,  40.17027283,  93.54611969,  25.86016083,  41.82838821,
+  //              82.50254822
+  VLOAD_32(v2, 0xc2b84f83, 0x41dd5c22, 0xc0b5eb7f, 0x429de715, 0x4266178c,
+           0x41773e4c, 0x42491349, 0x423a8b22, 0x428e560d, 0xc2a15ea5,
+           0xc1b2bc48, 0x4220ae5c, 0x42bb179d, 0x41cee19c, 0x42275045,
+           0x42a5014e);
+  //              -72.5625, -83.4375,  28.8281,  33.5938,
+  //              -85.7500,  67.5000,  91.0625, -91.8750, -9.2578, -64.2500,
+  //              -58.6250,  50.3438, -70.5000,  36.6250,  5.7930,  86.6875
+  VLOAD_16(v6, 0xd489, 0xd537, 0x4f35, 0x5033, 0xd55c, 0x5438, 0x55b1, 0xd5be,
+           0xc8a1, 0xd404, 0xd354, 0x524b, 0xd468, 0x5094, 0x45cb, 0x556b);
+  asm volatile("vfwsub.wv v4, v2, v6");
+  //              -19.59279633,  111.10748291, -34.51312256,  45.35758209,
+  //              143.27299500, -52.04729080, -40.79366684,
+  //              138.51086426,  80.42588043, -16.43485260,  36.28306580,
+  //              -10.17347717,  164.04611206, -10.76483917,  36.03541946,
+  //              -4.18495178
+  VCMP_U32(9, v4, 0xc19cbe0c, 0x42de3708, 0xc20a0d70, 0x42356e2a, 0x430f45e3,
+           0xc250306d, 0xc2232cb7, 0x430a82c8, 0x42a0da0d, 0xc1837a94,
+           0x421121dc, 0xc122c690, 0x43240bce, 0xc12c3cc8, 0x42102445,
+           0xc085eb20);
+
+  VSET(16, e32, m1);
+  //              -79494.9435096215456724,  81629.4152202270051930,
+  //              60506.1876363231276628, -81020.4028176319407066,
+  //              -6814.2587861350475578,  11974.4045779409498209,
+  //              97975.7066144426062237, -93357.8779376419261098,
+  //              95959.4397212496260181, -58528.4286213813902577,
+  //              28958.3763895476586185, -36387.3665319164574612,
+  //              -90399.7993234442838002, -78772.1006454367889091,
+  //              -62854.6154750282003079,  37858.6386504948022775
+  VLOAD_64(v2, 0xc0f3686f189d8b80, 0x40f3edd6a4bdf6fa, 0x40ed8b46011de3ec,
+           0xc0f3c7c671f0e6b7, 0xc0ba9e423fcee2b0, 0x40c76333c935c088,
+           0x40f7eb7b4e4af21e, 0xc0f6cade0c085740, 0x40f76d7709192628,
+           0xc0ec940db7442fee, 0x40dc479816c42f70, 0xc0e1c46bbaa12444,
+           0xc0f611fcca076142, 0xc0f33b419c3e63b8, 0xc0eeb0d3b1f8afb4,
+           0x40e27c546fd32998);
+  //               95822.63281250,  21789.49804688, -42409.42968750,
+  //               60172.89062500, -46359.57812500, -71236.33593750,
+  //               4124.35888672, -80527.00000000,  27430.70507812,
+  //               39975.67578125, -71197.53125000, -66640.12500000,
+  //               47459.75390625, -34899.84375000, -21371.85937500,
+  //               17582.65820312
+  VLOAD_32(v6, 0x47bb2751, 0x46aa3aff, 0xc725a96e, 0x476b0ce4, 0xc7351794,
+           0xc78b222b, 0x4580e2df, 0xc79d4780, 0x46d64d69, 0x471c27ad,
+           0xc78b0ec4, 0xc7822810, 0x473963c1, 0xc70853d8, 0xc6a6f7b8,
+           0x46895d51);
+  asm volatile("vfwsub.wv v4, v2, v6");
+  //              -175317.5763221215456724,  59839.9171733520051930,
+  //              102915.6173238231276628, -141193.2934426319552585,
+  //              39545.3193388649524422,  83210.7405154409498209,
+  //              93851.3477277238562237, -12830.8779376419261098,
+  //              68528.7346431246260181, -98504.1044026313902577,
+  //              100155.9076395476586185,  30252.7584680835425388,
+  //              -137859.5532296942838002, -43872.2568954367889091,
+  //              -41482.7561000282003079,  20275.9804473698022775
+  VCMP_U64(10, v4, 0xc10566ac9c4ec5c0, 0x40ed37fd597bedf4, 0x40f92039e08ef1f6,
+           0xc1013c4a58f8735c, 0x40e34f2a380623aa, 0x40f450abd926b811,
+           0x40f6e9b5904af21e, 0xc0c90f706042ba00, 0x40f0bb0bc1192628,
+           0xc0f80c81aba217f7, 0x40f873be85b10bdc, 0x40dd8b308abdb778,
+           0xc100d41c6d03b0a1, 0xc0e56c08387cc770, 0xc0e4415831f8afb4,
+           0x40d3ccfebfa65330);
+};
+
+// Simple random test with similar values (masked)
+// The numbers are the same of TEST_CASE1
+void TEST_CASE6(void) {
+  VSET(16, e16, m1);
+  //              -92.15529633,  27.66998672,
+  //              -5.68499708,  78.95133209,  57.52299500,  15.45270920,  50.26883316,
+  //              46.63587189,  71.16806793, -80.68485260,
+  //              -22.34193420,  40.17027283,  93.54611969,  25.86016083,  41.82838821,
+  //              82.50254822
+  VLOAD_32(v2, 0xc2b84f83, 0x41dd5c22, 0xc0b5eb7f, 0x429de715, 0x4266178c,
+           0x41773e4c, 0x42491349, 0x423a8b22, 0x428e560d, 0xc2a15ea5,
+           0xc1b2bc48, 0x4220ae5c, 0x42bb179d, 0x41cee19c, 0x42275045,
+           0x42a5014e);
+  //              -72.5625, -83.4375,  28.8281,  33.5938,
+  //              -85.7500,  67.5000,  91.0625, -91.8750, -9.2578, -64.2500,
+  //              -58.6250,  50.3438, -70.5000,  36.6250,  5.7930,  86.6875
+  VLOAD_16(v6, 0xd489, 0xd537, 0x4f35, 0x5033, 0xd55c, 0x5438, 0x55b1, 0xd5be,
+           0xc8a1, 0xd404, 0xd354, 0x524b, 0xd468, 0x5094, 0x45cb, 0x556b);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfwsub.wv v4, v2, v6, v0.t");
+  //               0.00000000,  111.10748291,  0.00000000,  45.35758209,
+  //               0.00000000, -52.04729080,  0.00000000,  138.51086426,
+  //               0.00000000, -16.43485260,  0.00000000, -10.17347717,
+  //               0.00000000, -10.76483917,  0.00000000, -4.18495178
+  VCMP_U32(11, v4, 0x0, 0x42de3708, 0x0, 0x42356e2a, 0x0, 0xc250306d, 0x0,
+           0x430a82c8, 0x0, 0xc1837a94, 0x0, 0xc122c690, 0x0, 0xc12c3cc8, 0x0,
+           0xc085eb20);
+
+  VSET(16, e32, m1);
+  //              -79494.9435096215456724,  81629.4152202270051930,
+  //              60506.1876363231276628, -81020.4028176319407066,
+  //              -6814.2587861350475578,  11974.4045779409498209,
+  //              97975.7066144426062237, -93357.8779376419261098,
+  //              95959.4397212496260181, -58528.4286213813902577,
+  //              28958.3763895476586185, -36387.3665319164574612,
+  //              -90399.7993234442838002, -78772.1006454367889091,
+  //              -62854.6154750282003079,  37858.6386504948022775
+  VLOAD_64(v2, 0xc0f3686f189d8b80, 0x40f3edd6a4bdf6fa, 0x40ed8b46011de3ec,
+           0xc0f3c7c671f0e6b7, 0xc0ba9e423fcee2b0, 0x40c76333c935c088,
+           0x40f7eb7b4e4af21e, 0xc0f6cade0c085740, 0x40f76d7709192628,
+           0xc0ec940db7442fee, 0x40dc479816c42f70, 0xc0e1c46bbaa12444,
+           0xc0f611fcca076142, 0xc0f33b419c3e63b8, 0xc0eeb0d3b1f8afb4,
+           0x40e27c546fd32998);
+  //               95822.63281250,  21789.49804688, -42409.42968750,
+  //               60172.89062500, -46359.57812500, -71236.33593750,
+  //               4124.35888672, -80527.00000000,  27430.70507812,
+  //               39975.67578125, -71197.53125000, -66640.12500000,
+  //               47459.75390625, -34899.84375000, -21371.85937500,
+  //               17582.65820312
+  VLOAD_32(v6, 0x47bb2751, 0x46aa3aff, 0xc725a96e, 0x476b0ce4, 0xc7351794,
+           0xc78b222b, 0x4580e2df, 0xc79d4780, 0x46d64d69, 0x471c27ad,
+           0xc78b0ec4, 0xc7822810, 0x473963c1, 0xc70853d8, 0xc6a6f7b8,
+           0x46895d51);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfwsub.wv v4, v2, v6, v0.t");
+  //               0.0000000000000000,  59839.9171733520051930,
+  //               0.0000000000000000, -141193.2934426319552585,
+  //               0.0000000000000000,  83210.7405154409498209,
+  //               0.0000000000000000, -12830.8779376419261098,
+  //               0.0000000000000000, -98504.1044026313902577,
+  //               0.0000000000000000,  30252.7584680835425388,
+  //               0.0000000000000000, -43872.2568954367889091,
+  //               0.0000000000000000,  20275.9804473698022775
+  VCMP_U64(12, v4, 0x0, 0x40ed37fd597bedf4, 0x0, 0xc1013c4a58f8735c, 0x0,
+           0x40f450abd926b811, 0x0, 0xc0c90f706042ba00, 0x0, 0xc0f80c81aba217f7,
+           0x0, 0x40dd8b308abdb778, 0x0, 0xc0e56c08387cc770, 0x0,
+           0x40d3ccfebfa65330);
+};
+
+// Simple random test with similar values (vector-scalar)
+void TEST_CASE7(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //              -8.76965809,  55.45920181,  71.29286957, -84.65414429,
+  //              -81.93881226,  75.13192749, -75.44019318, -48.81898499,
+  //              0.10306206, -25.18898392,  49.68006516,  72.66278076,
+  //              -24.90880966, -32.59431458,  14.58876038, -55.07221603
+  VLOAD_32(v2, 0xc10c5085, 0x425dd639, 0x428e95f3, 0xc2a94eec, 0xc2a3e0ac,
+           0x4296438c, 0xc296e161, 0xc24346a4, 0x3dd31233, 0xc1c9830a,
+           0x4246b863, 0x42915358, 0xc1c7453e, 0xc2026094, 0x41696b90,
+           0xc25c49f3);
+  //                              34.7812
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0x5059);
+  asm volatile("vfwsub.wf v4, v2, %[A]" ::[A] "f"(dscalar_16));
+  //              -43.55090714,  20.67795181,  36.51161957, -119.43539429,
+  //              -116.72006226,  40.35067749, -110.22144318, -83.60023499,
+  //              -34.67818832, -59.97023392,  14.89881516,  37.88153076,
+  //              -59.69005966, -67.37556458, -20.19248962, -89.85346985
+  VCMP_U32(13, v4, 0xc22e3421, 0x41a56c72, 0x42120be6, 0xc2eedeec, 0xc2e970ac,
+           0x42216718, 0xc2dc7161, 0xc2a73352, 0xc20ab677, 0xc26fe185,
+           0x416e618c, 0x421786b0, 0xc26ec29f, 0xc286c04a, 0xc1a18a38,
+           0xc2b3b4fa);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //               322189.5706008458510041,  914899.9451866354793310,
+  //               -620811.0881863175891340, -456926.2657179111847654,
+  //               -549945.8717311944346875, -386814.9759888321859762,
+  //               748677.5319772073999047,  821298.7777016961481422,
+  //               968861.0598710167687386, -343694.5546012039994821,
+  //               -782815.4022130169905722, -561429.7869165195152164,
+  //               755371.9691831718664616, -954868.1761190977413207,
+  //               -606267.0986005428712815,  818185.4808380266185850
+  VLOAD_64(v2, 0x4113aa36484b9690, 0x412beba7e3ef80b0, 0xc122f2162d26c1cc,
+           0xc11be37910185b2a, 0xc120c873be538d16, 0xc1179bfbe7699dce,
+           0x4126d90b105f5108, 0x412910658e2eeaae, 0x412d913a1ea769f6,
+           0xc114fa3a37e960c6, 0xc127e3becdeedd54, 0xc121222b92e6b8d8,
+           0x41270d57f038c6d6, 0xc12d23e85a2c484a, 0xc1228076327bc536,
+           0x4128f812f63066de);
+  //                              -83388.08593750
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0xc7a2de0b);
+  asm volatile("vfwsub.wf v4, v2, %[A]" ::[A] "f"(dscalar_32));
+  //               405577.6565383458510041,  998288.0311241354793310,
+  //               -537423.0022488175891340, -373538.1797804111847654,
+  //               -466557.7857936944346875, -303426.8900513321859762,
+  //               832065.6179147073999047,  904686.8636391961481422,
+  //               1052249.1458085167687386, -260306.4686637039994821,
+  //               -699427.3162755169905722, -478041.7009790195152164,
+  //               838760.0551206718664616, -871480.0901815977413207,
+  //               -522879.0126630428712815,  901573.5667755266185850
+  VCMP_U64(14, v4, 0x4118c126a04b9690, 0x412e77200fef80b0, 0xc120669e0126c1cc,
+           0xc116cc88b8185b2a, 0xc11c79f724a71a2c, 0xc112850b8f699dce,
+           0x412964833c5f5108, 0x412b9bddba2eeaae, 0x41300e592553b4fb,
+           0xc10fc693bfd2c18c, 0xc1255846a1eedd54, 0xc11d2d66cdcd71b0,
+           0x412998d01c38c6d6, 0xc12a98702e2c484a, 0xc11fe9fc0cf78a6c,
+           0x412b838b223066de);
+};
+
+// Simple random test with similar values (vector-scalar) (masked)
+void TEST_CASE8(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //               -8.76965809,  55.45920181,  71.29286957, -84.65414429,
+  //               -81.93881226,  75.13192749, -75.44019318, -48.81898499,
+  //               0.10306206, -25.18898392,  49.68006516,  72.66278076,
+  //               -24.90880966, -32.59431458,  14.58876038, -55.07221603
+  VLOAD_32(v2, 0xc10c5085, 0x425dd639, 0x428e95f3, 0xc2a94eec, 0xc2a3e0ac,
+           0x4296438c, 0xc296e161, 0xc24346a4, 0x3dd31233, 0xc1c9830a,
+           0x4246b863, 0x42915358, 0xc1c7453e, 0xc2026094, 0x41696b90,
+           0xc25c49f3);
+  //                              34.7812
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0x5059);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfwsub.wf v4, v2, %[A], v0.t" ::[A] "f"(dscalar_16));
+  //                0.00000000,  20.67795181,  0.00000000, -119.43539429,
+  //                0.00000000,  40.35067749,  0.00000000, -83.60023499,
+  //                0.00000000, -59.97023392,  0.00000000,  37.88153076,
+  //                0.00000000, -67.37556458,  0.00000000, -89.85346985
+  VCMP_U32(15, v4, 0x0, 0x41a56c72, 0x0, 0xc2eedeec, 0x0, 0x42216718, 0x0,
+           0xc2a73352, 0x0, 0xc26fe185, 0x0, 0x421786b0, 0x0, 0xc286c04a, 0x0,
+           0xc2b3b4fa);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                322189.5706008458510041,  914899.9451866354793310,
+  //                -620811.0881863175891340, -456926.2657179111847654,
+  //                -549945.8717311944346875, -386814.9759888321859762,
+  //                748677.5319772073999047,  821298.7777016961481422,
+  //                968861.0598710167687386, -343694.5546012039994821,
+  //                -782815.4022130169905722, -561429.7869165195152164,
+  //                755371.9691831718664616, -954868.1761190977413207,
+  //                -606267.0986005428712815,  818185.4808380266185850
+  VLOAD_64(v2, 0x4113aa36484b9690, 0x412beba7e3ef80b0, 0xc122f2162d26c1cc,
+           0xc11be37910185b2a, 0xc120c873be538d16, 0xc1179bfbe7699dce,
+           0x4126d90b105f5108, 0x412910658e2eeaae, 0x412d913a1ea769f6,
+           0xc114fa3a37e960c6, 0xc127e3becdeedd54, 0xc121222b92e6b8d8,
+           0x41270d57f038c6d6, 0xc12d23e85a2c484a, 0xc1228076327bc536,
+           0x4128f812f63066de);
+  //                              -83388.08593750
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0xc7a2de0b);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vfwsub.wf v4, v2, %[A], v0.t" ::[A] "f"(dscalar_32));
+  //                0.0000000000000000,  998288.0311241354793310,
+  //                0.0000000000000000, -373538.1797804111847654,
+  //                0.0000000000000000, -303426.8900513321859762,
+  //                0.0000000000000000,  904686.8636391961481422,
+  //                0.0000000000000000, -260306.4686637039994821,
+  //                0.0000000000000000, -478041.7009790195152164,
+  //                0.0000000000000000, -871480.0901815977413207,
+  //                0.0000000000000000,  901573.5667755266185850
+  VCMP_U64(16, v4, 0x0, 0x412e77200fef80b0, 0x0, 0xc116cc88b8185b2a, 0x0,
+           0xc112850b8f699dce, 0x0, 0x412b9bddba2eeaae, 0x0, 0xc10fc693bfd2c18c,
+           0x0, 0xc11d2d66cdcd71b0, 0x0, 0xc12a98702e2c484a, 0x0,
+           0x412b838b223066de);
+};
+
+int main(void) {
+  enable_vec();
+  enable_fp();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  TEST_CASE5();
+  TEST_CASE6();
+  TEST_CASE7();
+  TEST_CASE8();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vid.c b/apps/riscv-tests/isa/rv64uv/vid.c
new file mode 100644
index 0000000..796e3e1
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vid.c
@@ -0,0 +1,42 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1() {
+  VSET(16, e8, m1);
+  __asm__ volatile("vid.v v1");
+  VCMP_U8(1, v1, 0, 1, 2, 3, 4, 5, 6, 7);
+  VSET(10, e8, m1);
+
+  VLOAD_8(v1, 0b00001110, 0b00000111, 0b00010000, 0b01001011, 0b00110100,
+          0b01111101, 0b11001100, 0b00011000, 0b01000111, 0b00010100);
+  VSET(77, e8, m1);
+  asm volatile("vid.v v2");
+  VCMP_U8(2, v2, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
+          18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34,
+          35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,
+          52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68,
+          69, 70, 71, 72, 73, 74, 75, 76);
+}
+
+void TEST_CASE2() {
+  VSET(16, e8, m1);
+  VLOAD_8(v0, 85, 0, 0, 0, 0, 0, 0, 0);
+  VCLEAR(v1);
+  __asm__ volatile("vid.v v1, v0.t");
+  VCMP_U8(3, v1, 0, 0, 2, 0, 4, 0, 6, 0);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+  enable_fp();
+  TEST_CASE1();
+  TEST_CASE2();
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/viota.c b/apps/riscv-tests/isa/rv64uv/viota.c
new file mode 100644
index 0000000..bd8dbec
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/viota.c
@@ -0,0 +1,280 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1() {
+  VSET(1, e8, m1);
+  VLOAD_8(v1, 0b10001001);
+  VSET(8, e8, m1);
+  asm volatile("viota.m v2, v1");
+  VCMP_U8(1, v2, 0, 1, 1, 1, 2, 2, 2, 2);
+
+  VSET(2, e8, m1);
+  VLOAD_8(v1, 0b01100010, 0b01001100);
+  VSET(16, e8, m1);
+  asm volatile("viota.m v2, v1");
+  VCMP_U8(2, v2, 0, 0, 1, 1, 1, 1, 2, 3, 3, 3, 3, 4, 5, 5, 5, 6);
+
+  VSET(1, e8, m8);
+  VLOAD_8(v0, 0b00000001);
+  VSET(4, e16, m8);
+  asm volatile("viota.m v8, v0");
+  VCMP_U16(3, v8, 0, 1, 1, 1);
+
+  VSET(64, e8, m4);
+  VLOAD_8(
+      v0, 0b10101101, 0b10000000, 0b00000110, 0b10011100, 0b10010101,
+      0b01001100, 0b01101010, 0b11000100, 0b00011110, 0b10111010, 0b00100110,
+      0b11001010, 0b01101101, 0b11001010, 0b01000101, 0b00010110, 0b00001000,
+      0b10111000, 0b11011100, 0b11100000, 0b00110101, 0b10011110, 0b01001111,
+      0b01011101, 0b00001010, 0b01111000, 0b11010100, 0b01011101, 0b11000101,
+      0b10010010, 0b01011100, 0b11010101, 0b00100010, 0b10000100, 0b11001011,
+      0b01001101, 0b01010000, 0b10110011, 0b00011000, 0b10000101, 0b01110101,
+      0b00001111, 0b10111100, 0b00010101, 0b10011101, 0b11011001, 0b11010101,
+      0b00100001, 0b01101110, 0b10000001, 0b01100100, 0b00010001, 0b00010100,
+      0b00101011, 0b11111000, 0b10010000, 0b01010000, 0b01001111, 0b00000011,
+      0b10100100, 0b10001010, 0b01110011, 0b10100010, 0b01111110);
+  VSET(512, e8, m4);
+  asm volatile("viota.m v8, v0");
+  VCMP_U8(
+      4, v8, 0, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 5, 5, 5, 5, 5, 6, 6, 7, 8, 8, 8,
+      8, 8, 8, 8, 8, 9, 10, 11, 11, 11, 12, 13, 13, 14, 14, 15, 15, 15, 16, 16,
+      16, 17, 18, 18, 18, 19, 19, 19, 20, 20, 21, 21, 22, 23, 23, 23, 23, 24,
+      24, 24, 24, 25, 26, 26, 27, 28, 29, 30, 30, 30, 30, 30, 31, 31, 32, 33,
+      34, 34, 35, 35, 36, 37, 37, 37, 38, 38, 38, 38, 39, 39, 40, 40, 40, 41,
+      42, 43, 43, 44, 45, 45, 46, 47, 47, 47, 48, 48, 49, 49, 49, 50, 51, 52,
+      52, 53, 53, 53, 53, 54, 54, 54, 55, 56, 56, 57, 57, 57, 57, 57, 57, 57,
+      58, 58, 58, 58, 58, 58, 58, 58, 59, 60, 61, 61, 62, 62, 62, 63, 64, 65,
+      65, 66, 67, 67, 67, 67, 67, 67, 68, 69, 70, 71, 71, 72, 72, 73, 74, 74,
+      74, 74, 75, 76, 77, 78, 78, 78, 79, 80, 81, 82, 83, 83, 83, 84, 84, 85,
+      85, 86, 87, 88, 88, 89, 89, 89, 90, 90, 91, 91, 91, 91, 91, 91, 91, 91,
+      92, 93, 94, 95, 95, 95, 95, 96, 96, 97, 97, 98, 99, 100, 100, 101, 102,
+      103, 103, 104, 104, 105, 105, 106, 106, 106, 106, 107, 108, 108, 109, 109,
+      109, 110, 110, 110, 111, 111, 111, 112, 113, 114, 114, 115, 115, 116, 116,
+      117, 117, 118, 118, 119, 120, 120, 121, 121, 121, 121, 122, 122, 122, 122,
+      122, 123, 123, 123, 123, 123, 124, 125, 126, 126, 127, 127, 127, 128, 129,
+      130, 130, 131, 132, 132, 132, 133, 133, 133, 133, 133, 133, 134, 134, 135,
+      135, 136, 137, 137, 137, 138, 139, 139, 140, 140, 140, 140, 141, 142, 142,
+      142, 142, 143, 143, 144, 144, 144, 144, 144, 145, 146, 146, 147, 147, 148,
+      149, 150, 150, 151, 152, 153, 154, 154, 154, 154, 154, 154, 154, 155, 156,
+      157, 158, 158, 159, 160, 160, 161, 161, 162, 162, 162, 162, 163, 163, 164,
+      165, 166, 166, 166, 167, 168, 168, 168, 169, 170, 170, 171, 172, 173, 173,
+      174, 174, 175, 175, 176, 177, 178, 178, 178, 178, 178, 179, 179, 179, 179,
+      180, 181, 182, 182, 183, 184, 184, 185, 185, 185, 185, 185, 185, 185, 186,
+      186, 186, 187, 187, 187, 188, 189, 189, 190, 190, 190, 190, 191, 191, 191,
+      191, 191, 191, 192, 192, 193, 193, 193, 193, 194, 195, 195, 196, 196, 197,
+      197, 197, 197, 197, 197, 198, 199, 200, 201, 202, 202, 202, 202, 202, 203,
+      203, 203, 204, 204, 204, 204, 204, 205, 205, 206, 206, 207, 208, 209, 210,
+      210, 210, 211, 211, 212, 213, 213, 213, 213, 213, 213, 213, 213, 213, 214,
+      214, 214, 215, 215, 216, 216, 217, 217, 218, 218, 218, 218, 219, 220, 221,
+      221, 221, 222, 223, 224, 224, 224, 225, 225, 225, 225, 226, 226, 227, 227,
+      228, 229, 230, 231, 232, 233);
+
+  VSET(128, e8, m8);
+  VLOAD_8(
+      v0, 0b00000001, 0b00000011, 0b00111110, 0b00000100, 0b01101000,
+      0b10111011, 0b11010110, 0b10111111, 0b00110011, 0b00011100, 0b11010100,
+      0b00011010, 0b10100001, 0b10110100, 0b10010111, 0b01010100, 0b00011010,
+      0b01101011, 0b00101010, 0b11111111, 0b10000100, 0b11100110, 0b00100001,
+      0b01101000, 0b10110100, 0b01100010, 0b11100001, 0b10011100, 0b00110111,
+      0b01010011, 0b01010111, 0b10010001, 0b11001000, 0b01001011, 0b01000000,
+      0b10001111, 0b00001111, 0b01110100, 0b10101100, 0b00010101, 0b00110100,
+      0b10010010, 0b00001101, 0b11110011, 0b10101101, 0b10000100, 0b01111000,
+      0b11010101, 0b10110110, 0b00110110, 0b01010001, 0b01001000, 0b11100011,
+      0b01001110, 0b11101101, 0b01111000, 0b10111101, 0b00111011, 0b10111001,
+      0b11000110, 0b00000011, 0b00001110, 0b00001111, 0b00000010, 0b01010110,
+      0b00000010, 0b11011011, 0b01010100, 0b10110110, 0b10100011, 0b10100101,
+      0b11110101, 0b00000110, 0b10011111, 0b01000110, 0b00100000, 0b00100011,
+      0b11110100, 0b10111101, 0b10000010, 0b11110011, 0b00111111, 0b11000010,
+      0b00011001, 0b10000010, 0b00110011, 0b11000110, 0b11001100, 0b10011100,
+      0b11001011, 0b10101101, 0b11011110, 0b11010110, 0b11010110, 0b00100100,
+      0b01111010, 0b00111001, 0b10111000, 0b01101000, 0b00001001, 0b10010100,
+      0b11111101, 0b00001101, 0b10100111, 0b11000110, 0b01100111, 0b01010111,
+      0b10011001, 0b01100111, 0b00001011, 0b01001011, 0b10001101, 0b11110110,
+      0b10001001, 0b10010101, 0b10010010, 0b10100100, 0b01010110, 0b10110110,
+      0b10111001, 0b01010000, 0b01010001, 0b01001100, 0b11001101, 0b10111100,
+      0b11110010, 0b00001000, 0b10111000);
+  VSET(1024, e16, m8);
+  asm volatile("viota.m v8, v0");
+  VCMP_U16(
+      5, v8, 0, 1, 1, 1, 1, 1, 1, 1, 1, 2, 3, 3, 3, 3, 3, 3, 3, 3, 4, 5, 6, 7,
+      8, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9, 9, 10, 10, 11, 12, 12, 13, 14, 14,
+      15, 16, 17, 17, 18, 18, 19, 20, 20, 21, 21, 22, 23, 24, 25, 26, 27, 28,
+      29, 29, 30, 31, 32, 32, 32, 33, 34, 34, 34, 34, 34, 35, 36, 37, 37, 37,
+      37, 37, 37, 38, 38, 39, 39, 40, 41, 41, 42, 42, 43, 44, 44, 44, 44, 45,
+      45, 45, 45, 45, 46, 46, 47, 47, 47, 48, 48, 49, 50, 50, 51, 52, 53, 54,
+      54, 55, 55, 55, 56, 56, 56, 57, 57, 58, 58, 59, 59, 59, 60, 60, 61, 62,
+      62, 62, 62, 63, 64, 64, 65, 65, 66, 67, 67, 67, 68, 68, 69, 69, 70, 70,
+      70, 71, 72, 73, 74, 75, 76, 77, 78, 78, 78, 79, 79, 79, 79, 79, 80, 80,
+      81, 82, 82, 82, 83, 84, 85, 86, 86, 86, 86, 86, 87, 87, 87, 87, 87, 87,
+      88, 88, 89, 90, 90, 90, 90, 91, 91, 92, 93, 93, 94, 94, 95, 95, 95, 95,
+      96, 97, 97, 98, 98, 98, 98, 98, 99, 100, 101, 101, 101, 102, 103, 104,
+      104, 104, 105, 106, 107, 108, 108, 109, 110, 110, 110, 111, 112, 112, 112,
+      113, 113, 114, 114, 115, 116, 117, 117, 118, 118, 119, 119, 120, 120, 120,
+      120, 121, 121, 121, 122, 122, 122, 122, 123, 123, 123, 124, 125, 126, 127,
+      127, 128, 128, 128, 129, 129, 129, 129, 129, 129, 129, 129, 130, 130, 131,
+      132, 133, 134, 134, 134, 134, 135, 136, 137, 138, 139, 139, 139, 139, 139,
+      139, 139, 140, 140, 141, 142, 143, 143, 143, 143, 144, 145, 145, 146, 146,
+      147, 148, 148, 149, 149, 150, 150, 150, 150, 150, 150, 151, 151, 152, 153,
+      153, 153, 153, 154, 154, 154, 155, 155, 155, 156, 157, 157, 158, 159, 159,
+      159, 159, 159, 160, 161, 161, 161, 162, 163, 164, 165, 166, 166, 167, 168,
+      168, 169, 169, 170, 170, 170, 171, 171, 171, 171, 171, 172, 172, 172, 172,
+      173, 174, 175, 176, 176, 177, 177, 178, 178, 179, 179, 180, 181, 181, 182,
+      183, 183, 184, 185, 185, 186, 186, 187, 188, 188, 189, 190, 190, 190, 191,
+      191, 191, 191, 192, 192, 193, 193, 193, 193, 193, 194, 194, 194, 195, 195,
+      196, 197, 197, 197, 197, 198, 199, 200, 200, 201, 202, 203, 203, 203, 204,
+      204, 205, 205, 206, 207, 207, 208, 209, 210, 210, 210, 210, 211, 212, 213,
+      214, 214, 215, 215, 216, 217, 218, 219, 219, 220, 221, 222, 222, 223, 224,
+      225, 225, 225, 226, 226, 226, 227, 228, 229, 229, 230, 230, 231, 232, 232,
+      232, 232, 233, 234, 235, 236, 236, 236, 236, 236, 236, 236, 236, 237, 238,
+      239, 239, 239, 239, 239, 240, 241, 242, 243, 243, 243, 243, 243, 243, 244,
+      244, 244, 244, 244, 244, 244, 244, 245, 246, 246, 247, 247, 248, 248, 248,
+      249, 249, 249, 249, 249, 249, 249, 250, 251, 251, 252, 253, 253, 254, 255,
+      255, 255, 256, 256, 257, 257, 258, 258, 258, 259, 260, 260, 261, 262, 262,
+      263, 264, 265, 265, 265, 265, 266, 266, 267, 268, 268, 269, 269, 269, 270,
+      270, 271, 272, 272, 273, 273, 274, 275, 276, 277, 277, 278, 279, 279, 279,
+      279, 279, 279, 280, 281, 282, 283, 284, 284, 284, 285, 285, 286, 287, 287,
+      287, 287, 288, 288, 288, 288, 288, 288, 288, 289, 289, 289, 290, 291, 291,
+      291, 291, 292, 292, 292, 292, 292, 293, 293, 294, 295, 296, 297, 298, 298,
+      299, 300, 301, 302, 302, 303, 303, 304, 304, 304, 304, 304, 304, 305, 306,
+      307, 307, 307, 308, 309, 310, 311, 312, 313, 314, 315, 316, 317, 317, 317,
+      317, 318, 318, 318, 318, 318, 319, 320, 321, 321, 321, 322, 323, 323, 323,
+      323, 323, 324, 324, 324, 324, 324, 324, 325, 326, 327, 327, 327, 328, 329,
+      329, 329, 329, 330, 331, 331, 331, 331, 332, 333, 333, 333, 334, 335, 335,
+      335, 336, 337, 337, 337, 338, 339, 340, 340, 340, 341, 342, 343, 343, 344,
+      344, 344, 345, 346, 347, 347, 348, 349, 349, 350, 350, 351, 351, 352, 353,
+      354, 355, 355, 356, 357, 357, 358, 359, 359, 360, 360, 361, 362, 362, 363,
+      364, 364, 365, 365, 366, 367, 367, 367, 368, 368, 368, 369, 369, 369, 369,
+      370, 370, 371, 372, 373, 374, 374, 375, 375, 375, 376, 377, 378, 378, 378,
+      378, 378, 378, 379, 380, 381, 381, 382, 382, 382, 382, 383, 383, 384, 385,
+      385, 386, 386, 386, 387, 387, 387, 387, 387, 387, 387, 388, 388, 389, 389,
+      389, 390, 391, 391, 392, 393, 394, 395, 396, 397, 398, 398, 399, 400, 400,
+      400, 400, 400, 401, 402, 403, 403, 403, 404, 404, 405, 405, 406, 407, 407,
+      407, 407, 408, 409, 410, 411, 412, 412, 412, 413, 414, 414, 415, 416, 417,
+      417, 418, 418, 419, 419, 420, 420, 420, 421, 422, 422, 422, 423, 424, 425,
+      426, 426, 426, 427, 428, 428, 429, 430, 430, 431, 431, 431, 431, 431, 432,
+      433, 433, 434, 434, 434, 435, 435, 436, 436, 437, 438, 438, 438, 438, 439,
+      439, 440, 441, 441, 442, 443, 444, 445, 446, 446, 446, 447, 447, 447, 447,
+      448, 449, 449, 450, 450, 451, 451, 451, 452, 452, 453, 453, 453, 454, 454,
+      454, 455, 455, 455, 456, 456, 456, 457, 457, 458, 458, 459, 460, 460, 461,
+      461, 462, 462, 462, 463, 464, 464, 465, 466, 466, 467, 468, 468, 468, 469,
+      470, 471, 471, 472, 472, 472, 472, 472, 473, 473, 474, 474, 475, 475, 475,
+      475, 476, 476, 477, 477, 477, 477, 478, 479, 479, 479, 480, 480, 481, 481,
+      482, 483, 483, 483, 484, 485, 485, 485, 486, 487, 488, 489, 489, 490, 490,
+      491, 491, 491, 492, 493, 494, 495, 495, 495, 495, 496, 496, 496, 496, 496,
+      496, 496, 496, 497, 498, 499, 499);
+
+  VSET(10, e8, m1);
+  VLOAD_8(v1, 0b00001110, 0b00000111, 0b00010000, 0b01001011, 0b00110100,
+          0b01111101, 0b11001100, 0b00011000, 0b01000111, 0b00010100);
+  VSET(77, e8, m1);
+  asm volatile("viota.m v2, v1");
+  VCMP_U8(6, v2, 0, 0, 1, 2, 3, 3, 3, 3, 3, 4, 5, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
+          7, 7, 7, 7, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11, 12, 12, 13, 14, 14,
+          14, 15, 15, 16, 17, 18, 19, 20, 20, 20, 20, 21, 22, 22, 22, 23, 24,
+          24, 24, 24, 25, 26, 26, 26, 26, 27, 28, 29, 29, 29, 29, 30, 30, 30,
+          30, 31, 31);
+
+  VSET(10, e8, m1);
+  VLOAD_8(v0, 0b00001110, 0b00000111, 0b00010000, 0b01001011, 0b00110100,
+          0b01111101, 0b11001100, 0b00011000, 0b01000111, 0b00010100);
+  VSET(77, e32, m2);
+  asm volatile("viota.m v2, v0");
+  VCMP_U32(7, v2, 0, 0, 1, 2, 3, 3, 3, 3, 3, 4, 5, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
+           7, 7, 7, 7, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11, 12, 12, 13, 14, 14,
+           14, 15, 15, 16, 17, 18, 19, 20, 20, 20, 20, 21, 22, 22, 22, 23, 24,
+           24, 24, 24, 25, 26, 26, 26, 26, 27, 28, 29, 29, 29, 29, 30, 30, 30,
+           30, 31, 31);
+
+  VSET(10, e8, m1);
+  VLOAD_8(v0, 0b00001110, 0b00000111, 0b00010000, 0b01001011, 0b00110100,
+          0b01111101, 0b11001100, 0b00011000, 0b01000111, 0b00010100);
+  VSET(77, e64, m4);
+  asm volatile("viota.m v4, v0");
+  VCMP_U64(8, v4, 0, 0, 1, 2, 3, 3, 3, 3, 3, 4, 5, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
+           7, 7, 7, 7, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11, 12, 12, 13, 14, 14,
+           14, 15, 15, 16, 17, 18, 19, 20, 20, 20, 20, 21, 22, 22, 22, 23, 24,
+           24, 24, 24, 25, 26, 26, 26, 26, 27, 28, 29, 29, 29, 29, 30, 30, 30,
+           30, 31, 31);
+
+  VSET(5, e16, m1);
+  VLOAD_16(v0, 0b0000011100001110, 0b0100101100010000, 0b0111110100110100,
+           0b0001100011001100, 0b0001010001000111);
+  VSET(77, e8, m4);
+  asm volatile("viota.m v4, v0");
+  VCMP_U8(9, v4, 0, 0, 1, 2, 3, 3, 3, 3, 3, 4, 5, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
+          7, 7, 7, 7, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11, 12, 12, 13, 14, 14,
+          14, 15, 15, 16, 17, 18, 19, 20, 20, 20, 20, 21, 22, 22, 22, 23, 24,
+          24, 24, 24, 25, 26, 26, 26, 26, 27, 28, 29, 29, 29, 29, 30, 30, 30,
+          30, 31, 31);
+}
+
+void TEST_CASE2() {
+  VSET(16, e8, m1);
+  VCLEAR(v2);
+  VLOAD_8(v2, 0, 1, 2, 3, 4, 5, 6, 7);
+  VSET(1, e8, m1);
+  VLOAD_8(v1, 0b10001001);
+  VLOAD_8(v0, 0b11000111);
+  VSET(16, e8, m1);
+  asm volatile("viota.m v2, v1, v0.t");
+  VCMP_U8(10, v2, 0, 1, 1, 3, 4, 5, 1, 1);
+
+  VSET(5, e16, m1);
+  VLOAD_16(v8, 0b0000011100001110, 0b0100101100010000, 0b0111110100110100,
+           0b0001100011001100, 0b0001010001000111);
+  VSET(10, e16, m1);
+  VLOAD_8(v0, 0b11111111, 0b11111111, 0b11111111, 0b11111111, 0b11111111,
+          0b11111111, 0b11111111, 0b11111111, 0b11111111, 0b00001111);
+  VSET(77, e8, m4);
+  VCLEAR(v4);
+  asm volatile("viota.m v4, v8, v0.t");
+  VCMP_U8(11, v4, 0, 0, 1, 2, 3, 3, 3, 3, 3, 4, 5, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
+          7, 7, 7, 7, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11, 12, 12, 13, 14, 14,
+          14, 15, 15, 16, 17, 18, 19, 20, 20, 20, 20, 21, 22, 22, 22, 23, 24,
+          24, 24, 24, 25, 26, 26, 26, 26, 27, 28, 29, 29, 29, 29, 30, 30, 30,
+          30, 31, 0);
+
+  VSET(5, e16, m1);
+  VLOAD_16(v8, 0b0000011100001110, 0b0100101100010000, 0b0111110100110100,
+           0b0001100011001100, 0b0001010001000111);
+  VSET(10, e16, m1);
+  VLOAD_8(v0, 0b11111111, 0b11111111, 0b11111111, 0b11111111, 0b11111111,
+          0b11111111, 0b11111111, 0b11111111, 0b11111111, 0b00001011);
+  VSET(77, e8, m4);
+  VCLEAR(v4);
+  asm volatile("viota.m v4, v8, v0.t");
+  VCMP_U8(12, v4, 0, 0, 1, 2, 3, 3, 3, 3, 3, 4, 5, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
+          7, 7, 7, 7, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11, 12, 12, 13, 14, 14,
+          14, 15, 15, 16, 17, 18, 19, 20, 20, 20, 20, 21, 22, 22, 22, 23, 24,
+          24, 24, 24, 25, 26, 26, 26, 26, 27, 28, 29, 29, 29, 29, 30, 30, 30, 0,
+          30, 0);
+
+  VSET(5, e16, m1);
+  VLOAD_16(v8, 0b0000011100001110, 0b0100101100010000, 0b0111110100110100,
+           0b0001100011001100, 0b0001010001000111);
+  VSET(10, e16, m1);
+  VLOAD_8(v0, 0b11111111, 0b11111111, 0b11111111, 0b11111111, 0b11111111,
+          0b11111111, 0b11111111, 0b11111111, 0b11111111, 0b11111111);
+  VSET(77, e8, m4);
+  asm volatile("viota.m v4, v8, v0.t");
+  VCMP_U8(13, v4, 0, 0, 1, 2, 3, 3, 3, 3, 3, 4, 5, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
+          7, 7, 7, 7, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11, 12, 12, 13, 14, 14,
+          14, 15, 15, 16, 17, 18, 19, 20, 20, 20, 20, 21, 22, 22, 22, 23, 24,
+          24, 24, 24, 25, 26, 26, 26, 26, 27, 28, 29, 29, 29, 29, 30, 30, 30,
+          30, 31, 31);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+  enable_fp();
+  TEST_CASE1();
+  TEST_CASE2();
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vl.c b/apps/riscv-tests/isa/rv64uv/vl.c
new file mode 100644
index 0000000..f40e88d
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vl.c
@@ -0,0 +1,79 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+#define AXI_DWIDTH 128
+
+static volatile uint8_t ALIGNED_I8[16] __attribute__((aligned(AXI_DWIDTH))) = {
+    0xe0, 0xd3, 0x40, 0xd1, 0x84, 0x48, 0x89, 0x88,
+    0x88, 0xae, 0x08, 0x91, 0x02, 0x59, 0x11, 0x89};
+
+static volatile uint16_t ALIGNED_I16[16]
+    __attribute__((aligned(AXI_DWIDTH))) = {
+        0x05e0, 0xbbd3, 0x3840, 0x8cd1, 0x9384, 0x7548, 0x3489, 0x9388,
+        0x8188, 0x11ae, 0x5808, 0x4891, 0x4902, 0x8759, 0x1111, 0x1989};
+
+static volatile uint32_t ALIGNED_I32[16]
+    __attribute__((aligned(AXI_DWIDTH))) = {
+        0x9fe41920, 0xf9aa71f0, 0xa11a9384, 0x99991348, 0x9fa831c7, 0x38197598,
+        0x18931795, 0x81937598, 0x18747547, 0x3eeeeeee, 0x90139301, 0xab8b9148,
+        0x90318509, 0x31897598, 0x83195999, 0x89139848};
+
+static volatile uint64_t ALIGNED_I64[16]
+    __attribute__((aligned(AXI_DWIDTH))) = {
+        0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3, 0xa11a9384a7163840,
+        0x99991348a9f38cd1, 0x9fa831c7a11a9384, 0x3819759853987548,
+        0x1893179501093489, 0x81937598aa819388, 0x1874754791888188,
+        0x3eeeeeeee33111ae, 0x9013930148815808, 0xab8b914891484891,
+        0x9031850931584902, 0x3189759837598759, 0x8319599991911111,
+        0x8913984898951989};
+
+// Misaligned access wrt 128-bit
+void TEST_CASE1(void) {
+  VSET(15, e8, m1);
+  asm volatile("vle8.v v1, (%0)" ::"r"(&ALIGNED_I8[1]));
+  VCMP_U8(1, v1, 0xd3, 0x40, 0xd1, 0x84, 0x48, 0x89, 0x88, 0x88, 0xae, 0x08,
+          0x91, 0x02, 0x59, 0x11, 0x89);
+}
+
+void TEST_CASE2(void) {
+  VSET(15, e16, m1);
+  asm volatile("vle16.v v1, (%0)" ::"r"(&ALIGNED_I16[1]));
+  VCMP_U16(2, v1, 0xbbd3, 0x3840, 0x8cd1, 0x9384, 0x7548, 0x3489, 0x9388,
+           0x8188, 0x11ae, 0x5808, 0x4891, 0x4902, 0x8759, 0x1111, 0x1989);
+}
+
+void TEST_CASE3(void) {
+  VSET(15, e32, m1);
+  asm volatile("vle32.v v1, (%0)" ::"r"(&ALIGNED_I32[1]));
+  VCMP_U32(3, v1, 0xf9aa71f0, 0xa11a9384, 0x99991348, 0x9fa831c7, 0x38197598,
+           0x18931795, 0x81937598, 0x18747547, 0x3eeeeeee, 0x90139301,
+           0xab8b9148, 0x90318509, 0x31897598, 0x83195999, 0x89139848);
+}
+
+void TEST_CASE4(void) {
+  VSET(15, e64, m1);
+  asm volatile("vle64.v v1, (%0)" ::"r"(&ALIGNED_I64[1]));
+  VCMP_U64(4, v1, 0xf9aa71f0c394bbd3, 0xa11a9384a7163840, 0x99991348a9f38cd1,
+           0x9fa831c7a11a9384, 0x3819759853987548, 0x1893179501093489,
+           0x81937598aa819388, 0x1874754791888188, 0x3eeeeeeee33111ae,
+           0x9013930148815808, 0xab8b914891484891, 0x9031850931584902,
+           0x3189759837598759, 0x8319599991911111, 0x8913984898951989);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vl1r.c b/apps/riscv-tests/isa/rv64uv/vl1r.c
new file mode 100644
index 0000000..c5e4209
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vl1r.c
@@ -0,0 +1,439 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti
+
+#include "vector_macros.h"
+
+uint64_t counter;
+
+// Vectors are statically allocated not to exceed the stack and go in the UART
+// address space
+
+// Maximum size: (VLEN/8 Bytes * (MAX_LMUL == 8)) = VLEN
+// Define VLEN before compiling me
+// #define VLEN 4096
+uint8_t gold_vec_8b[VLEN];
+uint16_t gold_vec_16b[VLEN / 2];
+uint32_t gold_vec_32b[VLEN / 4];
+uint64_t gold_vec_64b[VLEN / 8];
+
+uint8_t zero_vec_8b[VLEN];
+uint16_t zero_vec_16b[VLEN / 2];
+uint32_t zero_vec_32b[VLEN / 4];
+uint64_t zero_vec_64b[VLEN / 8];
+
+uint8_t buf_vec_8b[VLEN];
+uint16_t buf_vec_16b[VLEN / 2];
+uint32_t buf_vec_32b[VLEN / 4];
+uint64_t buf_vec_64b[VLEN / 8];
+
+////////////
+// vl1reX //
+////////////
+
+// 1 whole register load
+void TEST_CASE1(void) {
+  // Initialize a golden vector
+  INIT_MEM_CNT(gold_vec_8b, VLEN / 8);
+  // Initialize a zero golden vector
+  INIT_MEM_ZEROES(zero_vec_8b, VLEN / 8);
+  // Reserve space for a buffer in memory
+  INIT_MEM_ZEROES(buf_vec_8b, VLEN / 8);
+  // Set vl and vtype to super short values
+  VSET(1, e64, m2);
+  // Initialize register + neighbours to pattern value
+  VCLEAR(v16);
+  // Load a buffer from memory - whole register load
+  asm volatile("vl1re8.v v16, (%0)" ::"r"(gold_vec_8b));
+  // Change vtype and vl to match the whole register
+  VSET(VLEN / 8, e8, m1);
+  // Check that the whole register was loaded
+  VSTORE(uint8_t, e8, v16, buf_vec_8b);
+  VMCMP(uint8_t, % hhu, 0, buf_vec_8b, gold_vec_8b, VLEN / 8);
+  // Check that the neighbour registers are okay
+  VSTORE(uint8_t, e8, v17, buf_vec_8b);
+  VMCMP(uint8_t, % hhu, 0, buf_vec_8b, zero_vec_8b, VLEN / 8);
+
+  // Initialize a golden vector
+  INIT_MEM_CNT(gold_vec_16b, VLEN / 16);
+  // Initialize a zero golden vector
+  INIT_MEM_ZEROES(zero_vec_16b, VLEN / 16);
+  // Reserve space for a buffer in memory
+  INIT_MEM_ZEROES(buf_vec_16b, VLEN / 16);
+  // Set vl and vtype to super short values
+  VSET(1, e64, m2);
+  // Initialize register + neighbours to pattern value
+  VCLEAR(v16);
+  // Load a buffer from memory - whole register load
+  asm volatile("vl1re16.v v16, (%0)" ::"r"(gold_vec_16b));
+  // Change vtype and vl to match the whole register
+  VSET(VLEN / 16, e16, m1);
+  // Check that the whole register was loaded
+  VSTORE(uint16_t, e16, v16, buf_vec_16b);
+  VMCMP(uint16_t, % hu, 1, buf_vec_16b, gold_vec_16b, VLEN / 16);
+  // Check that the neighbour registers are okay
+  VSTORE(uint16_t, e16, v17, buf_vec_16b);
+  VMCMP(uint16_t, % hu, 1, buf_vec_16b, zero_vec_16b, VLEN / 16);
+
+  // Initialize a golden vector
+  INIT_MEM_CNT(gold_vec_32b, VLEN / 32);
+  // Initialize a zero golden vector
+  INIT_MEM_ZEROES(zero_vec_32b, VLEN / 32);
+  // Reserve space for a buffer in memory
+  INIT_MEM_ZEROES(buf_vec_32b, VLEN / 32);
+  // Set vl and vtype to super short values
+  VSET(1, e64, m2);
+  // Initialize register + neighbours to pattern value
+  VCLEAR(v16);
+  // Load a buffer from memory - whole register load
+  asm volatile("vl1re32.v v16, (%0)" ::"r"(gold_vec_32b));
+  // Change vtype and vl to match the whole register
+  VSET(VLEN / 32, e32, m1);
+  // Check that the whole register was loaded
+  VSTORE(uint32_t, e32, v16, buf_vec_32b);
+  VMCMP(uint32_t, % u, 2, buf_vec_32b, gold_vec_32b, VLEN / 32);
+  // Check that the neighbour registers are okay
+  VSTORE(uint32_t, e32, v17, buf_vec_32b);
+  VMCMP(uint32_t, % u, 2, buf_vec_32b, zero_vec_32b, VLEN / 32);
+
+  // Initialize a golden vector
+  INIT_MEM_CNT(gold_vec_64b, VLEN / 64);
+  // Initialize a zero golden vector
+  INIT_MEM_ZEROES(zero_vec_64b, VLEN / 64);
+  // Reserve space for a buffer in memory
+  INIT_MEM_ZEROES(buf_vec_64b, VLEN / 64);
+  // Set vl and vtype to super short values
+  VSET(1, e64, m2);
+  // Initialize register + neighbours to pattern value
+  VCLEAR(v16);
+  // Load a buffer from memory - whole register load
+  asm volatile("vl1re64.v v16, (%0)" ::"r"(gold_vec_64b));
+  // Change vtype and vl to match the whole register
+  VSET(VLEN / 64, e64, m1);
+  // Check that the whole register was loaded3
+  VSTORE(uint64_t, e64, v16, buf_vec_64b);
+  VMCMP(uint64_t, % lu, 3, buf_vec_64b, gold_vec_64b, VLEN / 64);
+  // Check that the neighbour registers are okay
+  VSTORE(uint64_t, e64, v17, buf_vec_64b);
+  VMCMP(uint64_t, % lu, 3, buf_vec_64b, zero_vec_64b, VLEN / 64);
+}
+
+////////////
+// vl2reX //
+////////////
+
+// 2 whole registers load
+void TEST_CASE2(void) {
+  // Initialize a golden vector
+  INIT_MEM_CNT(gold_vec_8b, VLEN / 4);
+  // Initialize a zero golden vector
+  INIT_MEM_ZEROES(zero_vec_8b, VLEN / 4);
+  // Reserve space for a buffer in memory
+  INIT_MEM_ZEROES(buf_vec_8b, VLEN / 4);
+  // Set vl and vtype to super short values
+  VSET(1, e64, m4);
+  // Initialize register + neighbours to pattern value
+  VCLEAR(v16);
+  // Load a buffer from memory - whole register load
+  asm volatile("vl2re8.v v16, (%0)" ::"r"(gold_vec_8b));
+  // Change vtype and vl to match the whole register
+  VSET(VLEN / 4, e8, m2);
+  // Check that the whole register was loaded
+  VSTORE(uint8_t, e8, v16, buf_vec_8b);
+  VMCMP(uint8_t, % hhu, 4, buf_vec_8b, gold_vec_8b, VLEN / 4);
+  // Check that the neighbour registers are okay
+  VSTORE(uint8_t, e8, v18, buf_vec_8b);
+  VMCMP(uint8_t, % hhu, 4, buf_vec_8b, zero_vec_8b, VLEN / 4);
+
+  // Initialize a golden vector
+  INIT_MEM_CNT(gold_vec_16b, VLEN / 8);
+  // Initialize a zero golden vector
+  INIT_MEM_ZEROES(zero_vec_16b, VLEN / 8);
+  // Reserve space for a buffer in memory
+  INIT_MEM_ZEROES(buf_vec_16b, VLEN / 8);
+  // Set vl and vtype to super short values
+  VSET(1, e64, m4);
+  // Initialize register + neighbours to pattern value
+  VCLEAR(v16);
+  // Load a buffer from memory - whole register load
+  asm volatile("vl2re16.v v16, (%0)" ::"r"(gold_vec_16b));
+  // Change vtype and vl to match the whole register
+  VSET(VLEN / 8, e16, m2);
+  // Check that the whole register was loaded
+  VSTORE(uint16_t, e16, v16, buf_vec_16b);
+  VMCMP(uint16_t, % hu, 5, buf_vec_16b, gold_vec_16b, VLEN / 8);
+  // Check that the neighbour registers are okay
+  VSTORE(uint16_t, e16, v18, buf_vec_16b);
+  VMCMP(uint16_t, % hu, 5, buf_vec_16b, zero_vec_16b, VLEN / 8);
+
+  // Initialize a golden vector
+  INIT_MEM_CNT(gold_vec_32b, VLEN / 16);
+  // Initialize a zero golden vector
+  INIT_MEM_ZEROES(zero_vec_32b, VLEN / 16);
+  // Reserve space for a buffer in memory
+  INIT_MEM_ZEROES(buf_vec_32b, VLEN / 16);
+  // Set vl and vtype to super short values
+  VSET(1, e64, m4);
+  // Initialize register + neighbours to pattern value
+  VCLEAR(v16);
+  // Load a buffer from memory - whole register load
+  asm volatile("vl2re32.v v16, (%0)" ::"r"(gold_vec_32b));
+  // Change vtype and vl to match the whole register
+  VSET(VLEN / 16, e32, m2);
+  // Check that the whole register was loaded
+  VSTORE(uint32_t, e32, v16, buf_vec_32b);
+  VMCMP(uint32_t, % u, 6, buf_vec_32b, gold_vec_32b, VLEN / 16);
+  // Check that the neighbour registers are okay
+  VSTORE(uint32_t, e32, v18, buf_vec_32b);
+  VMCMP(uint32_t, % u, 6, buf_vec_32b, zero_vec_32b, VLEN / 16);
+
+  // Initialize a golden vector
+  INIT_MEM_CNT(gold_vec_64b, VLEN / 32);
+  // Initialize a zero golden vector
+  INIT_MEM_ZEROES(zero_vec_64b, VLEN / 32);
+  // Reserve space for a buffer in memory
+  INIT_MEM_ZEROES(buf_vec_64b, VLEN / 32);
+  // Set vl and vtype to super short values
+  VSET(1, e64, m4);
+  // Initialize register + neighbours to pattern value
+  VCLEAR(v16);
+  // Load a buffer from memory - whole register load
+  asm volatile("vl2re64.v v16, (%0)" ::"r"(gold_vec_64b));
+  // Change vtype and vl to match the whole register
+  VSET(VLEN / 32, e64, m2);
+  // Check that the whole register was loaded3
+  VSTORE(uint64_t, e64, v16, buf_vec_64b);
+  VMCMP(uint64_t, % lu, 7, buf_vec_64b, gold_vec_64b, VLEN / 32);
+  // Check that the neighbour registers are okay
+  VSTORE(uint64_t, e64, v18, buf_vec_64b);
+  VMCMP(uint64_t, % lu, 7, buf_vec_64b, zero_vec_64b, VLEN / 32);
+}
+
+////////////
+// vl4reX //
+////////////
+
+// 4 whole registers load
+void TEST_CASE3(void) {
+  // Initialize a golden vector
+  INIT_MEM_CNT(gold_vec_8b, VLEN / 2);
+  // Initialize a zero golden vector
+  INIT_MEM_ZEROES(zero_vec_8b, VLEN / 2);
+  // Reserve space for a buffer in memory
+  INIT_MEM_ZEROES(buf_vec_8b, VLEN / 2);
+  // Set vl and vtype to super short values
+  VSET(1, e64, m8);
+  // Initialize register + neighbours to pattern value
+  VCLEAR(v16);
+  // Load a buffer from memory - whole register load
+  asm volatile("vl4re8.v v16, (%0)" ::"r"(gold_vec_8b));
+  // Change vtype and vl to match the whole register
+  VSET(VLEN / 2, e8, m4);
+  // Check that the whole register was loaded
+  VSTORE(uint8_t, e8, v16, buf_vec_8b);
+  VMCMP(uint8_t, % hhu, 8, buf_vec_8b, gold_vec_8b, VLEN / 2);
+  // Check that the neighbour registers are okay
+  VSTORE(uint8_t, e8, v20, buf_vec_8b);
+  VMCMP(uint8_t, % hhu, 8, buf_vec_8b, zero_vec_8b, VLEN / 2);
+
+  // Initialize a golden vector
+  INIT_MEM_CNT(gold_vec_16b, VLEN / 4);
+  // Initialize a zero golden vector
+  INIT_MEM_ZEROES(zero_vec_16b, VLEN / 4);
+  // Reserve space for a buffer in memory
+  INIT_MEM_ZEROES(buf_vec_16b, VLEN / 4);
+  // Set vl and vtype to super short values
+  VSET(1, e64, m8);
+  // Initialize register + neighbours to pattern value
+  VCLEAR(v16);
+  // Load a buffer from memory - whole register load
+  asm volatile("vl4re16.v v16, (%0)" ::"r"(gold_vec_16b));
+  // Change vtype and vl to match the whole register
+  VSET(VLEN / 4, e16, m4);
+  // Check that the whole register was loaded
+  VSTORE(uint16_t, e16, v16, buf_vec_16b);
+  VMCMP(uint16_t, % hu, 9, buf_vec_16b, gold_vec_16b, VLEN / 4);
+  // Check that the neighbour registers are okay
+  VSTORE(uint16_t, e16, v20, buf_vec_16b);
+  VMCMP(uint16_t, % hu, 9, buf_vec_16b, zero_vec_16b, VLEN / 4);
+
+  // Initialize a golden vector
+  INIT_MEM_CNT(gold_vec_32b, VLEN / 8);
+  // Initialize a zero golden vector
+  INIT_MEM_ZEROES(zero_vec_32b, VLEN / 8);
+  // Reserve space for a buffer in memory
+  INIT_MEM_ZEROES(buf_vec_32b, VLEN / 8);
+  // Set vl and vtype to super short values
+  VSET(1, e64, m8);
+  // Initialize register + neighbours to pattern value
+  VCLEAR(v16);
+  // Load a buffer from memory - whole register load
+  asm volatile("vl4re32.v v16, (%0)" ::"r"(gold_vec_32b));
+  // Change vtype and vl to match the whole register
+  VSET(VLEN / 8, e32, m4);
+  // Check that the whole register was loaded
+  VSTORE(uint32_t, e32, v16, buf_vec_32b);
+  VMCMP(uint32_t, % u, 10, buf_vec_32b, gold_vec_32b, VLEN / 8);
+  // Check that the neighbour registers are okay
+  VSTORE(uint32_t, e32, v20, buf_vec_32b);
+  VMCMP(uint32_t, % u, 10, buf_vec_32b, zero_vec_32b, VLEN / 8);
+
+  // Initialize a golden vector
+  INIT_MEM_CNT(gold_vec_64b, VLEN / 16);
+  // Initialize a zero golden vector
+  INIT_MEM_ZEROES(zero_vec_64b, VLEN / 16);
+  // Reserve space for a buffer in memory
+  INIT_MEM_ZEROES(buf_vec_64b, VLEN / 16);
+  // Set vl and vtype to super short values
+  VSET(1, e64, m8);
+  // Initialize register + neighbours to pattern value
+  VCLEAR(v16);
+  // Load a buffer from memory - whole register load
+  asm volatile("vl4re64.v v16, (%0)" ::"r"(gold_vec_64b));
+  // Change vtype and vl to match the whole register
+  VSET(VLEN / 16, e64, m4);
+  // Check that the whole register was loaded
+  VSTORE(uint64_t, e64, v16, buf_vec_64b);
+  VMCMP(uint64_t, % lu, 11, buf_vec_64b, gold_vec_64b, VLEN / 16);
+  // Check that the neighbour registers are okay
+  VSTORE(uint64_t, e64, v20, buf_vec_64b);
+  VMCMP(uint64_t, % lu, 11, buf_vec_64b, zero_vec_64b, VLEN / 16);
+}
+
+////////////
+// vl8reX //
+////////////
+
+// 8 whole registers load
+void TEST_CASE4(void) {
+  // Initialize a golden vector
+  INIT_MEM_CNT(gold_vec_8b, VLEN);
+  // Initialize a zero golden vector
+  INIT_MEM_ZEROES(zero_vec_8b, VLEN);
+  // Reserve space for a buffer in memory
+  INIT_MEM_ZEROES(buf_vec_8b, VLEN);
+  // Set vl and vtype to super short values
+  VSET(1, e64, m8);
+  // Initialize register + neighbours to pattern value
+  VCLEAR(v16);
+  VCLEAR(v24);
+  // Load a buffer from memory - whole register load
+  asm volatile("vl8re8.v v16, (%0)" ::"r"(gold_vec_8b));
+  // Change vtype and vl to match the whole register
+  VSET(VLEN, e8, m8);
+  // Check that the whole register was loaded
+  VSTORE(uint8_t, e8, v16, buf_vec_8b);
+  VMCMP(uint8_t, % hhu, 12, buf_vec_8b, gold_vec_8b, VLEN);
+  // Check that the neighbour registers are okay
+  VSTORE(uint8_t, e8, v24, buf_vec_8b);
+  VMCMP(uint8_t, % hhu, 12, buf_vec_8b, zero_vec_8b, VLEN);
+
+  // Initialize a golden vector
+  INIT_MEM_CNT(gold_vec_16b, VLEN / 2);
+  // Initialize a zero golden vector
+  INIT_MEM_ZEROES(zero_vec_16b, VLEN / 2);
+  // Reserve space for a buffer in memory
+  INIT_MEM_ZEROES(buf_vec_16b, VLEN / 2);
+  // Set vl and vtype to super short values
+  VSET(1, e64, m8);
+  // Initialize register + neighbours to pattern value
+  VCLEAR(v16);
+  VCLEAR(v24);
+  // Load a buffer from memory - whole register load
+  asm volatile("vl8re16.v v16, (%0)" ::"r"(gold_vec_16b));
+  // Change vtype and vl to match the whole register
+  VSET(VLEN / 2, e16, m8);
+  // Check that the whole register was loaded
+  VSTORE(uint16_t, e16, v16, buf_vec_16b);
+  VMCMP(uint16_t, % hu, 13, buf_vec_16b, gold_vec_16b, VLEN / 2);
+  // Check that the neighbour registers are okay
+  VSTORE(uint16_t, e16, v24, buf_vec_16b);
+  VMCMP(uint16_t, % hu, 13, buf_vec_16b, zero_vec_16b, VLEN / 2);
+
+  // Initialize a golden vector
+  INIT_MEM_CNT(gold_vec_32b, VLEN / 4);
+  // Initialize a zero golden vector
+  INIT_MEM_ZEROES(zero_vec_32b, VLEN / 4);
+  // Reserve space for a buffer in memory
+  INIT_MEM_ZEROES(buf_vec_32b, VLEN / 4);
+  // Set vl and vtype to super short values
+  VSET(1, e64, m8);
+  // Initialize register + neighbours to pattern value
+  VCLEAR(v16);
+  VCLEAR(v24);
+  // Load a buffer from memory - whole register load
+  asm volatile("vl8re32.v v16, (%0)" ::"r"(gold_vec_32b));
+  // Change vtype and vl to match the whole register
+  VSET(VLEN / 4, e32, m8);
+  // Check that the whole register was loaded
+  VSTORE(uint32_t, e32, v16, buf_vec_32b);
+  VMCMP(uint32_t, % u, 14, buf_vec_32b, gold_vec_32b, VLEN / 4);
+  // Check that the neighbour registers are okay
+  VSTORE(uint32_t, e32, v24, buf_vec_32b);
+  VMCMP(uint32_t, % u, 14, buf_vec_32b, zero_vec_32b, VLEN / 4);
+
+  // Initialize a golden vector
+  INIT_MEM_CNT(gold_vec_64b, VLEN / 8);
+  // Initialize a zero golden vector
+  INIT_MEM_ZEROES(zero_vec_64b, VLEN / 8);
+  // Reserve space for a buffer in memory
+  INIT_MEM_ZEROES(buf_vec_64b, VLEN / 8);
+  // Set vl and vtype to super short values
+  VSET(1, e64, m8);
+  // Initialize register + neighbours to pattern value
+  VCLEAR(v16);
+  VCLEAR(v24);
+  // Load a buffer from memory - whole register load
+  asm volatile("vl8re64.v v16, (%0)" ::"r"(gold_vec_64b));
+  // Change vtype and vl to match the whole register
+  VSET(VLEN / 8, e64, m8);
+  // Check that the whole register was loaded3
+  VSTORE(uint64_t, e64, v16, buf_vec_64b);
+  VMCMP(uint64_t, % lu, 15, buf_vec_64b, gold_vec_64b, VLEN / 8);
+  // Check that the neighbour registers are okay
+  VSTORE(uint64_t, e64, v24, buf_vec_64b);
+  VMCMP(uint64_t, % lu, 15, buf_vec_64b, zero_vec_64b, VLEN / 8);
+}
+
+////////////
+// Others //
+////////////
+
+// Check with initial vl == 0
+void TEST_CASE5(void) {
+  // Initialize a golden vector
+  INIT_MEM_CNT(gold_vec_8b, VLEN / 8);
+  // Initialize a zero golden vector
+  INIT_MEM_ZEROES(zero_vec_8b, VLEN / 8);
+  // Reserve space for a buffer in memory
+  INIT_MEM_ZEROES(buf_vec_8b, VLEN / 8);
+  // Set vl and vtype to super short values
+  VSET(0, e64, m2);
+  // Initialize register + neighbours to pattern value
+  VCLEAR(v16);
+  // Load a buffer from memory - whole register load
+  asm volatile("vl1re8.v v16, (%0)" ::"r"(gold_vec_8b));
+  // Change vtype and vl to match the whole register
+  VSET(VLEN / 8, e8, m1);
+  // Check that the whole register was loaded
+  VSTORE(uint8_t, e8, v16, buf_vec_8b);
+  VMCMP(uint8_t, % hhu, 16, buf_vec_8b, gold_vec_8b, VLEN / 8);
+  // Check that the neighbour registers are okay
+  VSTORE(uint8_t, e8, v17, buf_vec_8b);
+  VMCMP(uint8_t, % hhu, 16, buf_vec_8b, zero_vec_8b, VLEN / 8);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vl_nocheck.c b/apps/riscv-tests/isa/rv64uv/vl_nocheck.c
new file mode 100644
index 0000000..aadc372
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vl_nocheck.c
@@ -0,0 +1,68 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+// or add inp here
+void TEST_CASE1(void) {
+  VSET(4, e8, m1);
+  volatile int8_t INP1[] = {0xff, 0x00, 0x0f, 0xf0}; // flush
+  __asm__ volatile("fence");
+  __asm__ volatile("vle8.v v1, (%0)" ::"r"(INP1));
+  //  VEC_CMP_8(1,v1,0xff, 0x00, 0x0f,0xf0);
+  //  __asm__ volatile ("fence");
+}
+
+void TEST_CASE2(void) {
+  VSET(4, e16, m1);
+  volatile int16_t INP1[] = {0xffff, 0x0000, 0x0f0f, 0xf0f0}; // flush
+  __asm__ volatile("fence");
+  __asm__ volatile("vle16.v v1, (%0)" ::"r"(INP1));
+  //  VEC_CMP_16(2,v1,0xffff, 0x0000, 0x0f0f,0xf0f0);
+  //  __asm__ volatile ("fence");
+}
+
+void TEST_CASE3(void) {
+  VSET(4, e32, m1);
+  volatile int32_t INP3[] = {0xffffffff, 0x00000000, 0x0f0f0f0f,
+                             0xf0f0f0f0}; // flush
+  __asm__ volatile("fence");
+  __asm__ volatile("vle32.v v1, (%0)" ::"r"(INP3));
+  //  VEC_CMP_32(3,v1,0xffffffff, 0x00000000, 0x0f0f0f0f,0xf0f0f0f0);
+  //  __asm__ volatile ("fence");
+}
+
+void TEST_CASE4(void) {
+  VSET(4, e64, m1);
+  volatile int64_t INP1[] = {0xffffffffffffffff, 0x0000000000000000,
+                             0x0f0f0f0f0f0f0f0f, 0xf0f0f0f0f0f0f0f0}; // flush
+  __asm__ volatile("fence");
+  __asm__ volatile("vle64.v v1, (%0)" ::"r"(INP1));
+  //  VEC_CMP_64(4,v1,0xffffffffffffffff, 0x00000000000000000,
+  //  0x0f0f0f0f0f0f0f0f,0xf0f0f0f0f0f0f0f0);
+  //  __asm__ volatile ("fence");
+}
+
+/*  void TEST_CASE2(void) { */
+/*    VSET(4,e8,m1); */
+/*    volatile int8_t INP2[] = {0xff, 0x00, 0x0f, 0xf0}; */
+/*    __asm__ volatile ("fence"); */
+/*    VLOAD_8(v0,0x1,0x0,0x1,0x0); */
+/*    VCLEAR_U8(v1); */
+/*    __asm__ volatile ("vle8.v v1, (%0), v0.t"::"r" (INP2)); */
+/*    VEC_CMP_8(2,v1,0xff, 0x00, 0x0f,0x00); */
+/* } */
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vle1.c b/apps/riscv-tests/isa/rv64uv/vle1.c
new file mode 100644
index 0000000..d8659e2
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vle1.c
@@ -0,0 +1,45 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+
+#include "vector_macros.h"
+
+#define AXI_DWIDTH 128
+
+static volatile uint8_t ALIGNED_I8[16] __attribute__((aligned(AXI_DWIDTH))) = {
+    0xe0, 0xd3, 0x40, 0xd1, 0x84, 0x48, 0x89, 0x88,
+    0x88, 0xae, 0x08, 0x91, 0x02, 0x59, 0x11, 0x89};
+
+// All the accesses are misaligned wrt AXI DATA WIDTH
+
+void TEST_CASE1(void) {
+  VSET(9, e8, m1);
+  asm volatile("vle1.v v1, (%0)" ::"r"(&ALIGNED_I8[1]));
+  VCMP_U8(1, v1, 0xd3, 0x40);
+
+  VSET(9, e64, m2);
+  asm volatile("vle1.v v1, (%0)" ::"r"(&ALIGNED_I8[1]));
+  VCMP_U8(2, v1, 0xd3, 0x40);
+
+  VSET(16, e64, m8);
+  asm volatile("vle1.v v1, (%0)" ::"r"(&ALIGNED_I8[1]));
+  VCMP_U8(3, v1, 0xd3, 0x40);
+
+  VSET(17, e64, m8);
+  asm volatile("vle1.v v1, (%0)" ::"r"(&ALIGNED_I8[1]));
+  // The vector used by VCMP_U8 is actually 16 elements long
+  // Don't store more if you don't want to overflow
+  VSET(16, e64, m8);
+  VCMP_U8(4, v1, 0xd3, 0x40, 0xd1);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vle16.c b/apps/riscv-tests/isa/rv64uv/vle16.c
new file mode 100644
index 0000000..b7727a5
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vle16.c
@@ -0,0 +1,294 @@
+// TODO uncomment TEST_CASE13 and TEST_CASE 15 after issue of vl=0 and
+// non-zero vstart is resolved
+// TODO uncomment TEST_CASE2 after issue of exception is resolved
+
+#include "long_array.h"
+#include "vector_macros.h"
+
+#define AXI_DWIDTH 128
+// Exception Handler for rtl
+
+void mtvec_handler(void) {
+  asm volatile("csrr t0, mcause"); // Read mcause
+
+  // Read mepc
+  asm volatile("csrr t1, mepc");
+
+  // Increment return address by 4
+  asm volatile("addi t1, t1, 4");
+  asm volatile("csrw mepc, t1");
+
+  // Filter with mcause and handle here
+
+  asm volatile("mret");
+}
+// Exception Handler for spike
+void handle_trap(void) {
+  // Read mepc
+  asm volatile("csrr t1, mepc");
+
+  // Increment return address by 4
+  asm volatile("addi t1, t1, 4");
+  asm volatile("csrw mepc, t1");
+
+  asm volatile("ld ra, 8(sp)");
+  asm volatile("ld sp, 16(sp)");
+  asm volatile("ld gp, 24(sp)");
+  asm volatile("ld tp, 32(sp)");
+  asm volatile("ld t0, 40(sp)");
+  asm volatile("ld t0, 40(sp)");
+  asm volatile("ld t1, 48(sp)");
+  asm volatile("ld t2, 56(sp)");
+  asm volatile("ld s0, 64(sp)");
+  asm volatile("ld s1, 72(sp)");
+  asm volatile("ld a0, 80(sp)");
+  asm volatile("ld a1, 88(sp)");
+  asm volatile("ld a2, 96(sp)");
+  asm volatile("ld a3, 104(sp)");
+  asm volatile("ld a4, 112(sp)");
+  asm volatile("ld a5, 120(sp)");
+  asm volatile("ld a6, 128(sp)");
+  asm volatile("ld a7, 136(sp)");
+  asm volatile("ld s2, 144(sp)");
+  asm volatile("ld s3, 152(sp)");
+  asm volatile("ld s4, 160(sp)");
+  asm volatile("ld s5, 168(sp)");
+  asm volatile("ld s6, 176(sp)");
+  asm volatile("ld s7, 184(sp)");
+  asm volatile("ld s8, 192(sp)");
+  asm volatile("ld s9, 200(sp)");
+  asm volatile("ld s10, 208(sp)");
+  asm volatile("ld s11, 216(sp)");
+  asm volatile("ld t3, 224(sp)");
+  asm volatile("ld t4, 232(sp)");
+  asm volatile("ld t5, 240(sp)");
+  asm volatile("ld t6, 248(sp)");
+
+  // Read mcause
+  asm volatile("csrr t3, mcause");
+
+  asm volatile("addi sp, sp, 272");
+
+  // Filter with mcause and handle here
+
+  asm volatile("mret");
+}
+
+static volatile uint16_t ALIGNED_I16[16]
+    __attribute__((aligned(AXI_DWIDTH))) = {
+        0x05e0, 0xbbd3, 0x3840, 0x8cd1, 0x9384, 0x7548, 0x3489, 0x9388,
+        0x8188, 0x11ae, 0x5808, 0x4891, 0x4902, 0x8759, 0x1111, 0x1989};
+
+//**********Checking functionality of vle16******//
+void TEST_CASE1(void) {
+  VSET(15, e16, m1);
+  asm volatile("vle16.v v0, (%0)" ::"r"(&ALIGNED_I16[1]));
+  VCMP_U16(1, v0, 0xbbd3, 0x3840, 0x8cd1, 0x9384, 0x7548, 0x3489, 0x9388,
+           0x8188, 0x11ae, 0x5808, 0x4891, 0x4902, 0x8759, 0x1111, 0x1989);
+}
+
+//******Checking functionality of  with illegal destination register
+// specifier for EMUL********//
+// In this test case EMUL=2 and register is v1 which will cause illegal
+// instruction exception and set mcause = 2
+void TEST_CASE2(void) {
+  uint8_t mcause;
+  VSET(15, e32, m4);
+  asm volatile("vle16.v v1, (%0)" ::"r"(&ALIGNED_I16[1]));
+  asm volatile("addi %[A], t3, 0" : [A] "=r"(mcause));
+  XCMP(2, mcause, 2);
+}
+
+//*******Checking functionality of vle16 with different values of masking
+// register******//
+void TEST_CASE3(void) {
+  VSET(16, e16, m1);
+  VCLEAR(v3);
+  VLOAD_8(v0, 0xFF, 0xFF);
+  asm volatile("vle16.v v3, (%0), v0.t" ::"r"(&ALIGNED_I16[0]));
+  VCMP_U16(3, v3, 0x05e0, 0xbbd3, 0x3840, 0x8cd1, 0x9384, 0x7548, 0x3489,
+           0x9388, 0x8188, 0x11ae, 0x5808, 0x4891, 0x4902, 0x8759, 0x1111,
+           0x1989);
+}
+
+void TEST_CASE4(void) {
+  VSET(16, e16, m1);
+  VLOAD_16(v3, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_8(v0, 0x00, 0x00);
+  asm volatile("vle16.v v3, (%0), v0.t" ::"r"(&ALIGNED_I16[0]));
+  VCMP_U16(4, v3, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+}
+
+void TEST_CASE5(void) {
+  VSET(16, e16, m1);
+  VCLEAR(v3);
+  VLOAD_16(v3, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vle16.v v3, (%0), v0.t" ::"r"(&ALIGNED_I16[0]));
+  VCMP_U16(5, v3, 1, 0xbbd3, 3, 0x8cd1, 5, 0x7548, 7, 0x9388, 9, 0x11ae, 11,
+           0x4891, 13, 0x8759, 15, 0x1989);
+}
+
+//******Checking functionality with different combinations of vta and vma*****//
+// **** It uses undisturbed policy for tail agnostic and mask agnostic****//
+void TEST_CASE6(void) {
+  uint64_t avl;
+  VSET(16, e16, m1);
+  VLOAD_16(v4, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  __asm__ volatile("vsetivli %[A], 12, e16, m1, ta, ma" : [A] "=r"(avl));
+  asm volatile("vle16.v v4, (%0), v0.t" ::"r"(&ALIGNED_I16[0]));
+  VSET(16, e16, m1);
+  VCMP_U16(6, v4, 1, 0xbbd3, 3, 0x8cd1, 5, 0x7548, 7, 0x9388, 9, 0x11ae, 11,
+           0x4891, 13, 14, 15, 16);
+}
+
+void TEST_CASE7(void) {
+  uint64_t avl;
+  VSET(16, e16, m1);
+  VLOAD_16(v4, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  __asm__ volatile("vsetivli %[A], 12, e16, m1, ta, mu" : [A] "=r"(avl));
+  asm volatile("vle16.v v4, (%0), v0.t" ::"r"(&ALIGNED_I16[0]));
+  VSET(16, e16, m1);
+  VCMP_U16(7, v4, 1, 0xbbd3, 3, 0x8cd1, 5, 0x7548, 7, 0x9388, 9, 0x11ae, 11,
+           0x4891, 13, 14, 15, 16);
+}
+
+void TEST_CASE8(void) {
+  uint64_t avl;
+  VSET(16, e16, m1);
+  VLOAD_16(v4, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  __asm__ volatile("vsetivli %[A], 12, e16, m1, tu, ma" : [A] "=r"(avl));
+  asm volatile("vle16.v v4, (%0), v0.t" ::"r"(&ALIGNED_I16[0]));
+  VSET(16, e16, m1);
+  VCMP_U16(8, v4, 1, 0xbbd3, 3, 0x8cd1, 5, 0x7548, 7, 0x9388, 9, 0x11ae, 11,
+           0x4891, 13, 14, 15, 16);
+}
+
+void TEST_CASE9(void) {
+  uint64_t avl;
+  VSET(16, e16, m1);
+  VLOAD_16(v4, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  __asm__ volatile("vsetivli %[A], 12, e16, m1, tu, mu" : [A] "=r"(avl));
+  asm volatile("vle16.v v4, (%0), v0.t" ::"r"(&ALIGNED_I16[0]));
+  VSET(16, e16, m1);
+  VCMP_U16(9, v4, 1, 0xbbd3, 3, 0x8cd1, 5, 0x7548, 7, 0x9388, 9, 0x11ae, 11,
+           0x4891, 13, 14, 15, 16);
+}
+
+//*******Checking functionality if encoded EEW is not supported for given SEW
+// and LMUL values because EMUL become out of range*****//
+// This test case cover corner case for EEW = 16.If LMUL is changed to
+// mf8 it will give error because emul become less than 1/8 (EMUL = 1/16)
+// But it does not support this configuration because SEW/LMUL > ELEN
+void TEST_CASE10(void) {
+  VSET(15, e32, mf2);
+  asm volatile("vle16.v v5, (%0)" ::"r"(&ALIGNED_I16[1]));
+  VCMP_U16(10, v5, 0xbbd3, 0x3840, 0x8cd1, 0x9384, 0x7548, 0x3489, 0x9388,
+           0x8188, 0x11ae, 0x5808, 0x4891, 0x4902, 0x8759, 0x1111, 0x1989);
+}
+
+// This test case execute upper bound case of EMUL (8)
+// If LMUL is changed to m8 it will give error because emul become greater than
+// 8 (EMUL = 16)
+
+void TEST_CASE11(void) {
+  VSET(16, e8, m4);
+  asm volatile("vle16.v v8, (%0)" ::"r"(&ALIGNED_I16[0]));
+  VCMP_U16(11, v8, 0x05e0, 0xbbd3, 0x3840, 0x8cd1, 0x9384, 0x7548, 0x3489,
+           0x9388, 0x8188, 0x11ae, 0x5808, 0x4891, 0x4902, 0x8759, 0x1111,
+           0x1989);
+}
+
+//******Checking functionality with different values of vl******//
+void TEST_CASE12(void) {
+  VSET(16, e16, m1);
+  VLOAD_16(v6, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VSET(16, e16, m1);
+  asm volatile("vle16.v v6, (%0)" ::"r"(&ALIGNED_I16[0]));
+  VSET(16, e8, m1);
+  VCMP_U16(12, v6, 0x05e0, 0xbbd3, 0x3840, 0x8cd1, 0x9384, 0x7548, 0x3489,
+           0x9388, 0x8188, 0x11ae, 0x5808, 0x4891, 0x4902, 0x8759, 0x1111,
+           0x1989);
+}
+
+void TEST_CASE13(void) {
+  uint64_t avl;
+  VSET(16, e16, m1);
+  VLOAD_16(v6, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  __asm__ volatile("vsetivli %[A], 0, e16, m1, ta, ma" : [A] "=r"(avl));
+  asm volatile("vle16.v v6, (%0)" ::"r"(&ALIGNED_I16[0]));
+  VSET(16, e16, m1);
+  VCMP_U16(13, v6, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+}
+
+void TEST_CASE14(void) {
+  VSET(16, e16, m1);
+  VLOAD_16(v6, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VSET(13, e16, m1);
+  asm volatile("vle16.v v6, (%0)" ::"r"(&ALIGNED_I16[0]));
+  VSET(16, e16, m1);
+  VCMP_U16(14, v6, 0x05e0, 0xbbd3, 0x3840, 0x8cd1, 0x9384, 0x7548, 0x3489,
+           0x9388, 0x8188, 0x11ae, 0x5808, 0x4891, 0x4902, 14, 15, 16);
+}
+
+//******Checking functionality with different vstart value*****//
+void TEST_CASE15(void) {
+  VSET(16, e16, m1);
+  VLOAD_16(v7, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  write_csr(vstart, 2);
+  asm volatile("vle16.v v7, (%0)" ::"r"(&ALIGNED_I16[0]));
+  VSET(16, e16, m1);
+  VCMP_U16(15, v7, 1, 2, 0x3840, 0x8cd1, 0x9384, 0x7548, 0x3489, 0x9388, 0x8188,
+           0x11ae, 0x5808, 0x4891, 0x4902, 0x8759, 0x1111, 0x1989);
+}
+
+//****Checking functionality with different values of EMUL and
+// large number of elements *******//
+void TEST_CASE16(void) {
+  VSET(1024, e16, m4);
+  asm volatile("vle16.v v8, (%0)" ::"r"(&LONG_I16[0]));
+  LVCMP_U16(16, v8, LONG_I16);
+}
+
+void TEST_CASE17(void) {
+  VSET(512, e16, m2);
+  asm volatile("vle16.v v10, (%0)" ::"r"(&LONG_I16[0]));
+  LVCMP_U16(17, v10, LONG_I16);
+}
+
+void TEST_CASE18(void) {
+  VSET(300, e16, m2);
+  asm volatile("vle16.v v12, (%0)" ::"r"(&LONG_I16[0]));
+  LVCMP_U16(18, v12, LONG_I16);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  printf("*****Running tests for vle16.v*****\n");
+  TEST_CASE1();
+  // TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+  TEST_CASE6();
+  TEST_CASE7();
+  TEST_CASE8();
+  TEST_CASE9();
+  TEST_CASE10();
+  TEST_CASE11();
+  TEST_CASE12();
+  // TEST_CASE13();
+  TEST_CASE14();
+  // TEST_CASE15();
+  TEST_CASE16();
+  TEST_CASE17();
+  TEST_CASE18();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vle32.c b/apps/riscv-tests/isa/rv64uv/vle32.c
new file mode 100644
index 0000000..168725b
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vle32.c
@@ -0,0 +1,311 @@
+// TODO uncomment TEST_CASE13 and TEST_CASE 15 after issue of vl=0 and
+// non-zero vstart is resolved
+// TODO uncomment TEST_CASE2 after issue of exception is resolved
+
+#include "long_array.h"
+#include "vector_macros.h"
+#define AXI_DWIDTH 128
+// Exception Handler for rtl
+
+void mtvec_handler(void) {
+  asm volatile("csrr t0, mcause"); // Read mcause
+
+  // Read mepc
+  asm volatile("csrr t1, mepc");
+
+  // Increment return address by 4
+  asm volatile("addi t1, t1, 4");
+  asm volatile("csrw mepc, t1");
+
+  // Filter with mcause and handle here
+
+  asm volatile("mret");
+}
+// Exception Handler for spike
+void handle_trap(void) {
+  // Read mepc
+  asm volatile("csrr t1, mepc");
+
+  // Increment return address by 4
+  asm volatile("addi t1, t1, 4");
+  asm volatile("csrw mepc, t1");
+
+  asm volatile("ld ra, 8(sp)");
+  asm volatile("ld sp, 16(sp)");
+  asm volatile("ld gp, 24(sp)");
+  asm volatile("ld tp, 32(sp)");
+  asm volatile("ld t0, 40(sp)");
+  asm volatile("ld t0, 40(sp)");
+  asm volatile("ld t1, 48(sp)");
+  asm volatile("ld t2, 56(sp)");
+  asm volatile("ld s0, 64(sp)");
+  asm volatile("ld s1, 72(sp)");
+  asm volatile("ld a0, 80(sp)");
+  asm volatile("ld a1, 88(sp)");
+  asm volatile("ld a2, 96(sp)");
+  asm volatile("ld a3, 104(sp)");
+  asm volatile("ld a4, 112(sp)");
+  asm volatile("ld a5, 120(sp)");
+  asm volatile("ld a6, 128(sp)");
+  asm volatile("ld a7, 136(sp)");
+  asm volatile("ld s2, 144(sp)");
+  asm volatile("ld s3, 152(sp)");
+  asm volatile("ld s4, 160(sp)");
+  asm volatile("ld s5, 168(sp)");
+  asm volatile("ld s6, 176(sp)");
+  asm volatile("ld s7, 184(sp)");
+  asm volatile("ld s8, 192(sp)");
+  asm volatile("ld s9, 200(sp)");
+  asm volatile("ld s10, 208(sp)");
+  asm volatile("ld s11, 216(sp)");
+  asm volatile("ld t3, 224(sp)");
+  asm volatile("ld t4, 232(sp)");
+  asm volatile("ld t5, 240(sp)");
+  asm volatile("ld t6, 248(sp)");
+
+  // Read mcause
+  asm volatile("csrr t3, mcause");
+
+  asm volatile("addi sp, sp, 272");
+
+  // Filter with mcause and handle here
+
+  asm volatile("mret");
+}
+
+static volatile uint32_t ALIGNED_I32[16]
+    __attribute__((aligned(AXI_DWIDTH))) = {
+        0x9fe41920, 0xf9aa71f0, 0xa11a9384, 0x99991348, 0x9fa831c7, 0x38197598,
+        0x18931795, 0x81937598, 0x18747547, 0x3eeeeeee, 0x90139301, 0xab8b9148,
+        0x90318509, 0x31897598, 0x83195999, 0x89139848};
+
+//**********Checking functionality of vle32********//
+void TEST_CASE1(void) {
+  VSET(15, e32, m1);
+  asm volatile("vle32.v v0, (%0)" ::"r"(&ALIGNED_I32[1]));
+  VCMP_U32(1, v0, 0xf9aa71f0, 0xa11a9384, 0x99991348, 0x9fa831c7, 0x38197598,
+           0x18931795, 0x81937598, 0x18747547, 0x3eeeeeee, 0x90139301,
+           0xab8b9148, 0x90318509, 0x31897598, 0x83195999, 0x89139848);
+}
+
+//******Checking functionality of  with illegal destination register
+// specifier for EMUL********//
+// In this test case EMUL=2 and register is v1 which will cause illegal
+// instruction exception and set mcause = 2
+void TEST_CASE2(void) {
+  uint8_t mcause;
+  VSET(15, e64, m4);
+  asm volatile("vle32.v v1, (%0)" ::"r"(&ALIGNED_I32[1]));
+  asm volatile("addi %[A], t3, 0" : [A] "=r"(mcause));
+  XCMP(2, mcause, 2);
+}
+
+//*******Checking functionality of vle32 with different values of masking
+// register******//
+void TEST_CASE3(void) {
+  VSET(16, e32, m1);
+  VCLEAR(v3);
+  VLOAD_8(v0, 0xFF, 0xFF);
+  asm volatile("vle32.v v3, (%0), v0.t" ::"r"(&ALIGNED_I32[0]));
+  VCMP_U32(3, v3, 0x9fe41920, 0xf9aa71f0, 0xa11a9384, 0x99991348, 0x9fa831c7,
+           0x38197598, 0x18931795, 0x81937598, 0x18747547, 0x3eeeeeee,
+           0x90139301, 0xab8b9148, 0x90318509, 0x31897598, 0x83195999,
+           0x89139848);
+}
+
+void TEST_CASE4(void) {
+  VSET(16, e32, m1);
+  VLOAD_32(v3, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_8(v0, 0x00, 0x00);
+  asm volatile("vle32.v v3, (%0), v0.t" ::"r"(&ALIGNED_I32[0]));
+  VCMP_U32(4, v3, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+}
+
+void TEST_CASE5(void) {
+  VSET(16, e32, m1);
+  VCLEAR(v3);
+  VLOAD_32(v3, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vle32.v v3, (%0), v0.t" ::"r"(&ALIGNED_I32[0]));
+  VCMP_U32(5, v3, 1, 0xf9aa71f0, 3, 0x99991348, 5, 0x38197598, 7, 0x81937598, 9,
+           0x3eeeeeee, 11, 0xab8b9148, 13, 0x31897598, 15, 0x89139848);
+}
+
+//******Checking functionality with different combinations of vta and vma*****//
+// **** It uses undisturbed policy for tail agnostic and mask agnostic****//
+void TEST_CASE6(void) {
+  uint64_t avl;
+  VSET(16, e32, m1);
+  VLOAD_32(v4, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  __asm__ volatile("vsetivli %[A], 12, e32, m1, ta, ma" : [A] "=r"(avl));
+  asm volatile("vle32.v v4, (%0), v0.t" ::"r"(&ALIGNED_I32[0]));
+  VSET(16, e32, m1);
+  VCMP_U32(6, v4, 1, 0xf9aa71f0, 3, 0x99991348, 5, 0x38197598, 7, 0x81937598, 9,
+           0x3eeeeeee, 11, 0xab8b9148, 13, 14, 15, 16);
+}
+
+void TEST_CASE7(void) {
+  uint64_t avl;
+  VSET(16, e32, m1);
+  VLOAD_32(v4, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  __asm__ volatile("vsetivli %[A], 12, e32, m1, ta, mu" : [A] "=r"(avl));
+  asm volatile("vle32.v v4, (%0), v0.t" ::"r"(&ALIGNED_I32[0]));
+  VSET(16, e32, m1);
+  VCMP_U32(7, v4, 1, 0xf9aa71f0, 3, 0x99991348, 5, 0x38197598, 7, 0x81937598, 9,
+           0x3eeeeeee, 11, 0xab8b9148, 13, 14, 15, 16);
+}
+
+void TEST_CASE8(void) {
+  uint64_t avl;
+  VSET(16, e32, m1);
+  VLOAD_32(v4, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  __asm__ volatile("vsetivli %[A], 12, e32, m1, tu, ma" : [A] "=r"(avl));
+  asm volatile("vle32.v v4, (%0), v0.t" ::"r"(&ALIGNED_I32[0]));
+  VSET(16, e32, m1);
+  VCMP_U32(8, v4, 1, 0xf9aa71f0, 3, 0x99991348, 5, 0x38197598, 7, 0x81937598, 9,
+           0x3eeeeeee, 11, 0xab8b9148, 13, 14, 15, 16);
+}
+
+void TEST_CASE9(void) {
+  uint64_t avl;
+  VSET(16, e32, m1);
+  VLOAD_32(v4, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  __asm__ volatile("vsetivli %[A], 12, e32, m1, tu, mu" : [A] "=r"(avl));
+  asm volatile("vle32.v v4, (%0), v0.t" ::"r"(&ALIGNED_I32[0]));
+  VSET(16, e32, m1);
+  VCMP_U32(9, v4, 1, 0xf9aa71f0, 3, 0x99991348, 5, 0x38197598, 7, 0x81937598, 9,
+           0x3eeeeeee, 11, 0xab8b9148, 13, 14, 15, 16);
+}
+
+//*******Checking functionality if encoded EEW is not supported for given SEW
+// and LMUL values because EMUL become out of range*****//
+// This test case cover corner case for EEW = 32.If LMUL is changed to
+// mf8 and SEW is changed to e64 it will give error because emul become less
+// than 1/8 (EMUL = 1/16) But it does not support this configuration because
+// SEW/LMUL > ELEN
+void TEST_CASE10(void) {
+  VSET(15, e32, mf2);
+  asm volatile("vle32.v v5, (%0)" ::"r"(&ALIGNED_I32[1]));
+  VCMP_U32(10, v5, 0xf9aa71f0, 0xa11a9384, 0x99991348, 0x9fa831c7, 0x38197598,
+           0x18931795, 0x81937598, 0x18747547, 0x3eeeeeee, 0x90139301,
+           0xab8b9148, 0x90318509, 0x31897598, 0x83195999, 0x89139848);
+}
+
+// This test case execute upper bound case of EMUL (8)
+// If LMUL is changed to m8 or m4 it will give error because emul become greater
+// than
+// 8
+// (EMUL = 16)
+
+void TEST_CASE11(void) {
+  VSET(16, e8, m2);
+  asm volatile("vle32.v v8, (%0)" ::"r"(&ALIGNED_I32[0]));
+  VCMP_U32(11, v8, 0x9fe41920, 0xf9aa71f0, 0xa11a9384, 0x99991348, 0x9fa831c7,
+           0x38197598, 0x18931795, 0x81937598, 0x18747547, 0x3eeeeeee,
+           0x90139301, 0xab8b9148, 0x90318509, 0x31897598, 0x83195999,
+           0x89139848);
+}
+
+//******Checking functionality with different values of vl******//
+void TEST_CASE12(void) {
+  VSET(16, e32, m1);
+  VLOAD_32(v6, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VSET(16, e32, m1);
+  asm volatile("vle32.v v6, (%0)" ::"r"(&ALIGNED_I32[0]));
+  VSET(16, e32, m1);
+  VCMP_U32(12, v6, 0x9fe41920, 0xf9aa71f0, 0xa11a9384, 0x99991348, 0x9fa831c7,
+           0x38197598, 0x18931795, 0x81937598, 0x18747547, 0x3eeeeeee,
+           0x90139301, 0xab8b9148, 0x90318509, 0x31897598, 0x83195999,
+           0x89139848);
+}
+
+void TEST_CASE13(void) {
+  uint64_t avl;
+  VSET(16, e32, m1);
+  VLOAD_32(v6, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  __asm__ volatile("vsetivli %[A], 0, e16, m1, ta, ma" : [A] "=r"(avl));
+  asm volatile("vle32.v v6, (%0)" ::"r"(&ALIGNED_I32[0]));
+  VSET(16, e32, m1);
+  VCMP_U32(13, v6, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+}
+
+void TEST_CASE14(void) {
+  VSET(16, e16, m1);
+  VLOAD_32(v6, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VSET(13, e16, m1);
+  asm volatile("vle32.v v6, (%0)" ::"r"(&ALIGNED_I32[0]));
+  VSET(16, e16, m1);
+  VCMP_U32(14, v6, 0x9fe41920, 0xf9aa71f0, 0xa11a9384, 0x99991348, 0x9fa831c7,
+           0x38197598, 0x18931795, 0x81937598, 0x18747547, 0x3eeeeeee,
+           0x90139301, 0xab8b9148, 0x90318509, 14, 15, 16);
+}
+
+//******Checking functionality with different vstart value*****//
+void TEST_CASE15(void) {
+  VSET(16, e32, m1);
+  VLOAD_32(v7, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  write_csr(vstart, 2);
+  asm volatile("vle32.v v7, (%0)" ::"r"(&ALIGNED_I32[0]));
+  VSET(15, e32, m1);
+  VCMP_U32(16, v7, 1, 2, 0xa11a9384, 0x99991348, 0x9fa831c7, 0x38197598,
+           0x18931795, 0x81937598, 0x18747547, 0x3eeeeeee, 0x90139301,
+           0xab8b9148, 0x90318509, 0x31897598, 0x83195999, 0x89139848);
+}
+
+//****Checking functionality with different values of EMUL and
+// large number of elements *******//
+
+void TEST_CASE16(void) {
+  VSET(1024, e32, m8);
+  asm volatile("vle32.v v8, (%0)" ::"r"(&LONG_I32[0]));
+  LVCMP_U32(16, v8, LONG_I32);
+}
+
+void TEST_CASE17(void) {
+  VSET(512, e32, m4);
+  asm volatile("vle32.v v12, (%0)" ::"r"(&LONG_I32[0]));
+  LVCMP_U32(17, v12, LONG_I32);
+}
+
+void TEST_CASE18(void) {
+  VSET(256, e32, m2);
+  asm volatile("vle32.v v14, (%0)" ::"r"(&LONG_I32[0]));
+  LVCMP_U32(18, v14, LONG_I32);
+}
+
+void TEST_CASE19(void) {
+  VSET(200, e32, m2);
+  asm volatile("vle32.v v16, (%0)" ::"r"(&LONG_I32[0]));
+  LVCMP_U32(19, v16, LONG_I32);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  printf("*****Running tests for vle32.v*****\n");
+  TEST_CASE1();
+  // TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+  TEST_CASE6();
+  TEST_CASE7();
+  TEST_CASE8();
+  TEST_CASE9();
+  TEST_CASE10();
+  TEST_CASE11();
+  TEST_CASE12();
+  // TEST_CASE13();
+  TEST_CASE14();
+  // TEST_CASE15();
+  TEST_CASE16();
+  TEST_CASE17();
+  TEST_CASE18();
+  TEST_CASE19();
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vle64.c b/apps/riscv-tests/isa/rv64uv/vle64.c
new file mode 100644
index 0000000..13c69cd
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vle64.c
@@ -0,0 +1,315 @@
+// TODO uncomment TEST_CASE12 and TEST_CASE 14 after issue of vl=0 and
+// non-zero vstart is resolved
+// TODO uncomment TEST_CASE2 after issue of exception is resolved
+
+#include "long_array.h"
+#include "vector_macros.h"
+
+#define AXI_DWIDTH 128
+// Exception Handler for rtl
+
+void mtvec_handler(void) {
+  asm volatile("csrr t0, mcause"); // Read mcause
+
+  // Read mepc
+  asm volatile("csrr t1, mepc");
+
+  // Increment return address by 4
+  asm volatile("addi t1, t1, 4");
+  asm volatile("csrw mepc, t1");
+
+  // Filter with mcause and handle here
+
+  asm volatile("mret");
+}
+
+// Exception Handler for spike
+void handle_trap(void) {
+  // Read mepc
+  asm volatile("csrr t1, mepc");
+
+  // Increment return address by 4
+  asm volatile("addi t1, t1, 4");
+  asm volatile("csrw mepc, t1");
+
+  asm volatile("ld ra, 8(sp)");
+  asm volatile("ld sp, 16(sp)");
+  asm volatile("ld gp, 24(sp)");
+  asm volatile("ld tp, 32(sp)");
+  asm volatile("ld t0, 40(sp)");
+  asm volatile("ld t0, 40(sp)");
+  asm volatile("ld t1, 48(sp)");
+  asm volatile("ld t2, 56(sp)");
+  asm volatile("ld s0, 64(sp)");
+  asm volatile("ld s1, 72(sp)");
+  asm volatile("ld a0, 80(sp)");
+  asm volatile("ld a1, 88(sp)");
+  asm volatile("ld a2, 96(sp)");
+  asm volatile("ld a3, 104(sp)");
+  asm volatile("ld a4, 112(sp)");
+  asm volatile("ld a5, 120(sp)");
+  asm volatile("ld a6, 128(sp)");
+  asm volatile("ld a7, 136(sp)");
+  asm volatile("ld s2, 144(sp)");
+  asm volatile("ld s3, 152(sp)");
+  asm volatile("ld s4, 160(sp)");
+  asm volatile("ld s5, 168(sp)");
+  asm volatile("ld s6, 176(sp)");
+  asm volatile("ld s7, 184(sp)");
+  asm volatile("ld s8, 192(sp)");
+  asm volatile("ld s9, 200(sp)");
+  asm volatile("ld s10, 208(sp)");
+  asm volatile("ld s11, 216(sp)");
+  asm volatile("ld t3, 224(sp)");
+  asm volatile("ld t4, 232(sp)");
+  asm volatile("ld t5, 240(sp)");
+  asm volatile("ld t6, 248(sp)");
+
+  // Read mcause
+  asm volatile("csrr t3, mcause");
+
+  asm volatile("addi sp, sp, 272");
+
+  // Filter with mcause and handle here
+
+  asm volatile("mret");
+}
+
+static volatile uint64_t ALIGNED_I64[16]
+    __attribute__((aligned(AXI_DWIDTH))) = {
+        0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3, 0xa11a9384a7163840,
+        0x99991348a9f38cd1, 0x9fa831c7a11a9384, 0x3819759853987548,
+        0x1893179501093489, 0x81937598aa819388, 0x1874754791888188,
+        0x3eeeeeeee33111ae, 0x9013930148815808, 0xab8b914891484891,
+        0x9031850931584902, 0x3189759837598759, 0x8319599991911111,
+        0x8913984898951989};
+
+//**********Checking functionality of vle64********//
+void TEST_CASE1(void) {
+  VSET(15, e64, m1);
+  asm volatile("vle64.v v0, (%0)" ::"r"(&ALIGNED_I64[1]));
+  VCMP_U64(1, v0, 0xf9aa71f0c394bbd3, 0xa11a9384a7163840, 0x99991348a9f38cd1,
+           0x9fa831c7a11a9384, 0x3819759853987548, 0x1893179501093489,
+           0x81937598aa819388, 0x1874754791888188, 0x3eeeeeeee33111ae,
+           0x9013930148815808, 0xab8b914891484891, 0x9031850931584902,
+           0x3189759837598759, 0x8319599991911111, 0x8913984898951989);
+}
+
+//******Checking functionality of  with illegal destination register
+// specifier for EMUL********//
+// In this test case EMUL=2 and register is v1 which will cause illegal
+// instruction exception and set mcause = 2
+void TEST_CASE2(void) {
+  uint8_t mcause;
+  VSET(15, e64, m2);
+  asm volatile("vle64.v v1, (%0)" ::"r"(&ALIGNED_I64[1]));
+  asm volatile("addi %[A], t3, 0" : [A] "=r"(mcause));
+  XCMP(2, mcause, 2);
+}
+
+//*******Checking functionality of vle64 with different values of masking
+// register******//
+void TEST_CASE3(void) {
+  VSET(16, e64, m1);
+  VCLEAR(v3);
+  VLOAD_8(v0, 0xFF, 0xFF);
+  asm volatile("vle64.v v3, (%0), v0.t" ::"r"(&ALIGNED_I64[0]));
+  VCMP_U64(3, v3, 0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3, 0xa11a9384a7163840,
+           0x99991348a9f38cd1, 0x9fa831c7a11a9384, 0x3819759853987548,
+           0x1893179501093489, 0x81937598aa819388, 0x1874754791888188,
+           0x3eeeeeeee33111ae, 0x9013930148815808, 0xab8b914891484891,
+           0x9031850931584902, 0x3189759837598759, 0x8319599991911111,
+           0x8913984898951989);
+}
+
+void TEST_CASE4(void) {
+  VSET(16, e64, m1);
+  VCLEAR(v3);
+  VLOAD_8(v0, 0x00, 0x00);
+  asm volatile("vle64.v v3, (%0), v0.t" ::"r"(&ALIGNED_I64[0]));
+  VCMP_U64(4, v3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+}
+
+void TEST_CASE5(void) {
+  VSET(16, e64, m1);
+  VCLEAR(v3);
+  VLOAD_64(v3, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vle64.v v3, (%0), v0.t" ::"r"(&ALIGNED_I64[0]));
+  VCMP_U64(5, v3, 1, 0xf9aa71f0c394bbd3, 3, 0x99991348a9f38cd1, 5,
+           0x3819759853987548, 7, 0x81937598aa819388, 9, 0x3eeeeeeee33111ae, 11,
+           0xab8b914891484891, 13, 0x3189759837598759, 15, 0x8913984898951989);
+}
+
+//******Checking functionality with different combinations of vta and vma*****//
+// **** It uses undisturbed policy for tail agnostic and mask agnostic****//
+void TEST_CASE6(void) {
+  uint64_t avl;
+  VSET(16, e64, m1);
+  VLOAD_64(v4, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  __asm__ volatile("vsetivli %[A], 12, e64, m1, ta, ma" : [A] "=r"(avl));
+  asm volatile("vle64.v v4, (%0), v0.t" ::"r"(&ALIGNED_I64[0]));
+  VSET(16, e64, m1);
+  VCMP_U64(6, v4, 1, 0xf9aa71f0c394bbd3, 3, 0x99991348a9f38cd1, 5,
+           0x3819759853987548, 7, 0x81937598aa819388, 9, 0x3eeeeeeee33111ae, 11,
+           0xab8b914891484891, 13, 14, 15, 16);
+}
+
+void TEST_CASE7(void) {
+  uint64_t avl;
+  VSET(16, e64, m1);
+  VLOAD_64(v4, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  __asm__ volatile("vsetivli %[A], 12, e64, m1, ta, mu" : [A] "=r"(avl));
+  asm volatile("vle64.v v4, (%0), v0.t" ::"r"(&ALIGNED_I64[0]));
+  VSET(16, e64, m1);
+  VCMP_U64(7, v4, 1, 0xf9aa71f0c394bbd3, 3, 0x99991348a9f38cd1, 5,
+           0x3819759853987548, 7, 0x81937598aa819388, 9, 0x3eeeeeeee33111ae, 11,
+           0xab8b914891484891, 13, 14, 15, 16);
+}
+
+void TEST_CASE8(void) {
+  uint64_t avl;
+  VSET(16, e64, m1);
+  VLOAD_64(v4, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  __asm__ volatile("vsetivli %[A], 12, e64, m1, tu, ma" : [A] "=r"(avl));
+  asm volatile("vle64.v v4, (%0), v0.t" ::"r"(&ALIGNED_I64[0]));
+  VSET(16, e64, m1);
+  VCMP_U64(8, v4, 1, 0xf9aa71f0c394bbd3, 3, 0x99991348a9f38cd1, 5,
+           0x3819759853987548, 7, 0x81937598aa819388, 9, 0x3eeeeeeee33111ae, 11,
+           0xab8b914891484891, 13, 14, 15, 16);
+}
+
+void TEST_CASE9(void) {
+  uint64_t avl;
+  VSET(16, e64, m1);
+  VLOAD_64(v4, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  __asm__ volatile("vsetivli %[A], 12, e64, m1, tu, mu" : [A] "=r"(avl));
+  asm volatile("vle64.v v4, (%0), v0.t" ::"r"(&ALIGNED_I64[0]));
+  VSET(16, e64, m1);
+  VCMP_U64(9, v4, 1, 0xf9aa71f0c394bbd3, 3, 0x99991348a9f38cd1, 5,
+           0x3819759853987548, 7, 0x81937598aa819388, 9, 0x3eeeeeeee33111ae, 11,
+           0xab8b914891484891, 13, 14, 15, 16);
+}
+
+//*******Checking functionality if encoded EEW is not supported for given SEW
+// and LMUL values because EMUL become out of range*****//
+// This test case cover upper bound of EMUL(8). If LMUL is changed to
+// m2 it will give error because emul become greater than 8 (EMUL = 16)
+void TEST_CASE10(void) {
+  VSET(15, e8, m1);
+  asm volatile("vle64.v v8, (%0)" ::"r"(&ALIGNED_I64[1]));
+  VCMP_U64(10, v8, 0xf9aa71f0c394bbd3, 0xa11a9384a7163840, 0x99991348a9f38cd1,
+           0x9fa831c7a11a9384, 0x3819759853987548, 0x1893179501093489,
+           0x81937598aa819388, 0x1874754791888188, 0x3eeeeeeee33111ae,
+           0x9013930148815808, 0xab8b914891484891, 0x9031850931584902,
+           0x3189759837598759, 0x8319599991911111, 0x8913984898951989);
+}
+
+//******Checking functionality with different values of vl******//
+void TEST_CASE11(void) {
+  VSET(16, e64, m1);
+  VLOAD_64(v6, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VSET(16, e64, m1);
+  asm volatile("vle64.v v6, (%0)" ::"r"(&ALIGNED_I64[0]));
+  VSET(16, e64, m1);
+  VCMP_U64(11, v6, 0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3, 0xa11a9384a7163840,
+           0x99991348a9f38cd1, 0x9fa831c7a11a9384, 0x3819759853987548,
+           0x1893179501093489, 0x81937598aa819388, 0x1874754791888188,
+           0x3eeeeeeee33111ae, 0x9013930148815808, 0xab8b914891484891,
+           0x9031850931584902, 0x3189759837598759, 0x8319599991911111,
+           0x8913984898951989);
+}
+
+void TEST_CASE12(void) {
+  uint64_t avl;
+  VSET(16, e64, m1);
+  VLOAD_64(v6, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  __asm__ volatile("vsetivli %[A], 0, e64, m1, ta, ma" : [A] "=r"(avl));
+  asm volatile("vle64.v v6, (%0)" ::"r"(&ALIGNED_I64[0]));
+  VSET(16, e64, m1);
+  VCMP_U64(12, v6, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+}
+
+void TEST_CASE13(void) {
+  VSET(16, e64, m1);
+  VLOAD_64(v6, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VSET(13, e64, m1);
+  asm volatile("vle64.v v6, (%0)" ::"r"(&ALIGNED_I64[0]));
+  VSET(16, e64, m1);
+  VCMP_U64(13, v6, 0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3, 0xa11a9384a7163840,
+           0x99991348a9f38cd1, 0x9fa831c7a11a9384, 0x3819759853987548,
+           0x1893179501093489, 0x81937598aa819388, 0x1874754791888188,
+           0x3eeeeeeee33111ae, 0x9013930148815808, 0xab8b914891484891,
+           0x9031850931584902, 14, 15, 16);
+}
+
+//******Checking functionality with different vstart value*****//
+void TEST_CASE14(void) {
+  VSET(16, e64, m1);
+  VLOAD_64(v7, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  write_csr(vstart, 2);
+  asm volatile("vle64.v v7, (%0)" ::"r"(&ALIGNED_I64[0]));
+  VSET(16, e64, m1);
+  VCMP_U64(14, v7, 1, 2, 0xa11a9384a7163840, 0x99991348a9f38cd1,
+           0x9fa831c7a11a9384, 0x3819759853987548, 0x1893179501093489,
+           0x81937598aa819388, 0x1874754791888188, 0x3eeeeeeee33111ae,
+           0x9013930148815808, 0xab8b914891484891, 0x9031850931584902,
+           0x3189759837598759, 0x8319599991911111, 0x8913984898951989);
+}
+
+//****Checking functionality with different values of EMUL and
+// large number of elements *******//
+void TEST_CASE15(void) {
+  VSET(512, e64, m8);
+  asm volatile("vle64.v v8, (%0)" ::"r"(&LONG_I64[0]));
+  LVCMP_U64(15, v8, LONG_I64);
+}
+
+void TEST_CASE16(void) {
+  VSET(256, e64, m4);
+  asm volatile("vle64.v v12, (%0)" ::"r"(&LONG_I64[0]));
+  LVCMP_U64(16, v12, LONG_I64);
+}
+
+void TEST_CASE17(void) {
+  VSET(128, e64, m2);
+  asm volatile("vle64.v v10, (%0)" ::"r"(&LONG_I64[0]));
+  LVCMP_U64(17, v10, LONG_I64);
+}
+
+void TEST_CASE18(void) {
+  VSET(100, e64, m2);
+  asm volatile("vle64.v v14, (%0)" ::"r"(&LONG_I64[0]));
+  LVCMP_U64(18, v14, LONG_I64);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  printf("*****Running tests for vle64.v*****\n");
+  TEST_CASE1();
+  // TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+  TEST_CASE6();
+  TEST_CASE7();
+  TEST_CASE8();
+  TEST_CASE9();
+  TEST_CASE10();
+  TEST_CASE11();
+  // TEST_CASE12();
+  TEST_CASE13();
+  // TEST_CASE14();
+  TEST_CASE15();
+  TEST_CASE16();
+  TEST_CASE17();
+  TEST_CASE18();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vle8.c b/apps/riscv-tests/isa/rv64uv/vle8.c
new file mode 100644
index 0000000..afb62fb
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vle8.c
@@ -0,0 +1,274 @@
+// TODO uncomment TEST_CASE12 and TEST_CASE 14 after issue of vl=0 and
+// non-zero vstart is resolved
+// TODO uncomment TEST_CASE2 after issue of exception is resolved
+
+#include "long_array.h"
+#include "vector_macros.h"
+
+#define AXI_DWIDTH 128
+
+// Exception Handler for rtl
+
+void mtvec_handler(void) {
+  asm volatile("csrr t0, mcause"); // Read mcause
+
+  // Read mepc
+  asm volatile("csrr t1, mepc");
+
+  // Increment return address by 4
+  asm volatile("addi t1, t1, 4");
+  asm volatile("csrw mepc, t1");
+
+  // Filter with mcause and handle here
+
+  asm volatile("mret");
+}
+
+// Exception Handler for spike
+void handle_trap(void) {
+  // Read mepc
+  asm volatile("csrr t1, mepc");
+
+  // Increment return address by 4
+  asm volatile("addi t1, t1, 4");
+  asm volatile("csrw mepc, t1");
+
+  asm volatile("ld ra, 8(sp)");
+  asm volatile("ld sp, 16(sp)");
+  asm volatile("ld gp, 24(sp)");
+  asm volatile("ld tp, 32(sp)");
+  asm volatile("ld t0, 40(sp)");
+  asm volatile("ld t0, 40(sp)");
+  asm volatile("ld t1, 48(sp)");
+  asm volatile("ld t2, 56(sp)");
+  asm volatile("ld s0, 64(sp)");
+  asm volatile("ld s1, 72(sp)");
+  asm volatile("ld a0, 80(sp)");
+  asm volatile("ld a1, 88(sp)");
+  asm volatile("ld a2, 96(sp)");
+  asm volatile("ld a3, 104(sp)");
+  asm volatile("ld a4, 112(sp)");
+  asm volatile("ld a5, 120(sp)");
+  asm volatile("ld a6, 128(sp)");
+  asm volatile("ld a7, 136(sp)");
+  asm volatile("ld s2, 144(sp)");
+  asm volatile("ld s3, 152(sp)");
+  asm volatile("ld s4, 160(sp)");
+  asm volatile("ld s5, 168(sp)");
+  asm volatile("ld s6, 176(sp)");
+  asm volatile("ld s7, 184(sp)");
+  asm volatile("ld s8, 192(sp)");
+  asm volatile("ld s9, 200(sp)");
+  asm volatile("ld s10, 208(sp)");
+  asm volatile("ld s11, 216(sp)");
+  asm volatile("ld t3, 224(sp)");
+  asm volatile("ld t4, 232(sp)");
+  asm volatile("ld t5, 240(sp)");
+  asm volatile("ld t6, 248(sp)");
+
+  // Read mcause
+  asm volatile("csrr t3, mcause");
+
+  asm volatile("addi sp, sp, 272");
+
+  // Filter with mcause and handle here
+
+  asm volatile("mret");
+}
+
+static volatile uint8_t ALIGNED_I8[16] __attribute__((aligned(AXI_DWIDTH))) = {
+    0xe0, 0xd3, 0x40, 0xd1, 0x84, 0x48, 0x89, 0x88,
+    0x88, 0xae, 0x08, 0x91, 0x02, 0x59, 0x11, 0x89};
+
+//**********Checking functionality of vle8 ********//
+void TEST_CASE1(void) {
+  VSET(15, e8, m1);
+  asm volatile("vle8.v v0, (%0)" ::"r"(&ALIGNED_I8[1]));
+  VCMP_U8(1, v0, 0xd3, 0x40, 0xd1, 0x84, 0x48, 0x89, 0x88, 0x88, 0xae, 0x08,
+          0x91, 0x02, 0x59, 0x11, 0x89);
+}
+
+//******Checking functionality of  with illegal destination register
+// specifier for EMUL********//
+// In this test case EMUL=2 and register is v1 which will cause illegal
+// instruction exception and set mcause = 2
+void TEST_CASE2(void) {
+  uint8_t mcause;
+  VSET(15, e16, m4);
+  asm volatile("vle8.v v1, (%0)" ::"r"(&ALIGNED_I8[1]));
+  asm volatile("addi %[A], t3, 0" : [A] "=r"(mcause));
+  XCMP(2, mcause, 2);
+}
+
+//*******Checking functionality of vle8 with different values of masking
+// register******//
+void TEST_CASE3(void) {
+  VSET(16, e8, m1);
+  VCLEAR(v3);
+  VLOAD_8(v0, 0xFF, 0xFF);
+  asm volatile("vle8.v v3, (%0), v0.t" ::"r"(&ALIGNED_I8[0]));
+  VCMP_U8(3, v3, 0xe0, 0xd3, 0x40, 0xd1, 0x84, 0x48, 0x89, 0x88, 0x88, 0xae,
+          0x08, 0x91, 0x02, 0x59, 0x11, 0x89);
+}
+
+void TEST_CASE4(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v3, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_8(v0, 0x00, 0x00);
+  asm volatile("vle8.v v3, (%0), v0.t" ::"r"(&ALIGNED_I8[0]));
+  VCMP_U8(4, v3, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+}
+
+void TEST_CASE5(void) {
+  VSET(16, e8, m1);
+  VCLEAR(v3);
+  VLOAD_8(v3, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vle8.v v3, (%0), v0.t" ::"r"(&ALIGNED_I8[0]));
+  VCMP_U8(5, v3, 1, 0xd3, 3, 0xd1, 5, 0x48, 7, 0x88, 9, 0xae, 11, 0x91, 13,
+          0x59, 15, 0x89);
+}
+
+//******Checking functionality with different combinations of vta and vma*****//
+// **** It uses undisturbed policy for tail agnostic and mask agnostic****//
+void TEST_CASE6(void) {
+  uint64_t avl;
+  VSET(16, e8, m1);
+  VLOAD_8(v4, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  __asm__ volatile("vsetivli %[A], 12, e8, m1, ta, ma" : [A] "=r"(avl));
+  asm volatile("vle8.v v4, (%0), v0.t" ::"r"(&ALIGNED_I8[0]));
+  VSET(16, e8, m1);
+  VCMP_U8(6, v4, 1, 0xd3, 3, 0xd1, 5, 0x48, 7, 0x88, 9, 0xae, 11, 0x91, 13, 14,
+          15, 16);
+}
+
+void TEST_CASE7(void) {
+  uint64_t avl;
+  VSET(16, e8, m1);
+  VLOAD_8(v4, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  __asm__ volatile("vsetivli %[A], 12, e8, m1, ta, mu" : [A] "=r"(avl));
+  asm volatile("vle8.v v4, (%0), v0.t" ::"r"(&ALIGNED_I8[0]));
+  VSET(16, e8, m1);
+  VCMP_U8(7, v4, 1, 0xd3, 3, 0xd1, 5, 0x48, 7, 0x88, 9, 0xae, 11, 0x91, 13, 14,
+          15, 16);
+}
+
+void TEST_CASE8(void) {
+  uint64_t avl;
+  VSET(16, e8, m1);
+  VLOAD_8(v4, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  __asm__ volatile("vsetivli %[A], 12, e8, m1, tu, ma" : [A] "=r"(avl));
+  asm volatile("vle8.v v4, (%0), v0.t" ::"r"(&ALIGNED_I8[0]));
+  VSET(16, e8, m1);
+  VCMP_U8(8, v4, 1, 0xd3, 3, 0xd1, 5, 0x48, 7, 0x88, 9, 0xae, 11, 0x91, 13, 14,
+          15, 16);
+}
+
+void TEST_CASE9(void) {
+  uint64_t avl;
+  VSET(16, e8, m1);
+  VLOAD_8(v4, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  __asm__ volatile("vsetivli %[A], 12, e8, m1, tu, mu" : [A] "=r"(avl));
+  asm volatile("vle8.v v4, (%0), v0.t" ::"r"(&ALIGNED_I8[0]));
+  VSET(16, e8, m1);
+  VCMP_U8(9, v4, 1, 0xd3, 3, 0xd1, 5, 0x48, 7, 0x88, 9, 0xae, 11, 0x91, 13, 14,
+          15, 16);
+}
+
+//*******Checking functionality if encoded EEW is not supported for given SEW
+// and LMUL values because EMUL become out of range*****//
+// This test case execute lower bound case of EMUL (1/8). If LMUL is changed to
+// mf4 or mf8 it will give error because emul become out of range
+void TEST_CASE10(void) {
+  VSET(15, e32, mf2);
+  asm volatile("vle8.v v5, (%0)" ::"r"(&ALIGNED_I8[1]));
+  VCMP_U8(10, v5, 0xd3, 0x40, 0xd1, 0x84, 0x48, 0x89, 0x88, 0x88, 0xae, 0x08,
+          0x91, 0x02, 0x59, 0x11, 0x89);
+}
+
+//******Checking functionality with different values of vl******//
+void TEST_CASE11(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v6, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VSET(16, e8, m1); // Setting vl=16
+  asm volatile("vle8.v v6, (%0)" ::"r"(&ALIGNED_I8[0]));
+  VSET(16, e8, m1);
+  VCMP_U8(11, v6, 0xe0, 0xd3, 0x40, 0xd1, 0x84, 0x48, 0x89, 0x88, 0x88, 0xae,
+          0x08, 0x91, 0x02, 0x59, 0x11, 0x89);
+}
+
+void TEST_CASE12(void) {
+  uint64_t avl;
+  VSET(16, e8, m1);
+  VLOAD_8(v6, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  __asm__ volatile("vsetivli %[A], 0, e8, m1, ta, ma"
+                   : [A] "=r"(avl)); // Setting vl=0
+  asm volatile("vle8.v v6, (%0)" ::"r"(&ALIGNED_I8[0]));
+  VSET(16, e8, m1);
+  VCMP_U8(12, v6, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+}
+
+void TEST_CASE13(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v6, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VSET(13, e8, m1); // Setting vl =13
+  asm volatile("vle8.v v6, (%0)" ::"r"(&ALIGNED_I8[0]));
+  VSET(16, e8, m1);
+  VCMP_U8(13, v6, 0xe0, 0xd3, 0x40, 0xd1, 0x84, 0x48, 0x89, 0x88, 0x88, 0xae,
+          0x08, 0x91, 0x02, 14, 15, 16);
+}
+
+//******Checking functionality with different vstart value*****//
+void TEST_CASE14(void) {
+  uint64_t vstart;
+  VSET(16, e8, m1);
+  VLOAD_8(v7, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  write_csr(vstart, 2);
+  asm volatile("vle8.v v7, (%0)" ::"r"(&ALIGNED_I8[0]));
+  write_csr(vstart, 0);
+  VSET(16, e8, m1);
+  VCMP_U8(14, v7, 1, 2, 0x40, 0xd1, 0x84, 0x48, 0x89, 0x88, 0x88, 0xae, 0x08,
+          0x91, 0x02, 0x59, 0x11, 0x89);
+}
+
+//****Checking functionality with different values of EMUL and
+// large number of elements *******//
+void TEST_CASE15(void) {
+  VSET(1024, e8, m2);
+  asm volatile("vle8.v v8, (%0)" ::"r"(&LONG_I8[0]));
+  LVCMP_U8(15, v8, LONG_I8);
+}
+
+void TEST_CASE16(void) {
+  VSET(800, e8, m2);
+  asm volatile("vle8.v v8, (%0)" ::"r"(&LONG_I8[0]));
+  LVCMP_U8(16, v8, LONG_I8);
+}
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  printf("*****Running tests for vle8.v*****\n");
+  TEST_CASE1();
+  // TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+  TEST_CASE6();
+  TEST_CASE7();
+  TEST_CASE8();
+  TEST_CASE9();
+  TEST_CASE10();
+  TEST_CASE11();
+  // TEST_CASE12();
+  TEST_CASE13();
+  // TEST_CASE14();
+  TEST_CASE15();
+  TEST_CASE16();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vle_vse_hazards.c b/apps/riscv-tests/isa/rv64uv/vle_vse_hazards.c
new file mode 100644
index 0000000..3b1b6ce
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vle_vse_hazards.c
@@ -0,0 +1,222 @@
+#include "vector_macros.h"
+
+#define AXI_DWIDTH 128
+
+#define INIT 98
+
+void reset_vec8(volatile uint8_t *vec, int rst_val, uint64_t len) {
+  for (uint64_t i = 0; i < len; ++i)
+    vec[i] = rst_val;
+}
+void reset_vec16(volatile uint16_t *vec, int rst_val, uint64_t len) {
+  for (uint64_t i = 0; i < len; ++i)
+    vec[i] = rst_val;
+}
+void reset_vec32(volatile uint32_t *vec, int rst_val, uint64_t len) {
+  for (uint64_t i = 0; i < len; ++i)
+    vec[i] = rst_val;
+}
+void reset_vec64(volatile uint64_t *vec, int rst_val, uint64_t len) {
+  for (uint64_t i = 0; i < len; ++i)
+    vec[i] = rst_val;
+}
+
+static volatile uint8_t TEST_I8[16] __attribute__((aligned(AXI_DWIDTH))) = {
+    1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
+static volatile uint16_t TEST_I16[16] __attribute__((aligned(AXI_DWIDTH))) = {
+    2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32};
+static volatile uint32_t TEST_I32[16] __attribute__((aligned(AXI_DWIDTH))) = {
+    4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64};
+static volatile uint64_t TEST_I64[16] __attribute__((aligned(AXI_DWIDTH))) = {
+    8, 16, 24, 32, 40, 48, 56, 64, 72, 80, 88, 96, 104, 112, 120, 128};
+
+static volatile uint8_t ALIGNED_I8[16] __attribute__((aligned(AXI_DWIDTH))) = {
+    0xe0, 0xd3, 0x40, 0xd1, 0x84, 0x48, 0x89, 0x88,
+    0x88, 0xae, 0x08, 0x91, 0x02, 0x59, 0x11, 0x89};
+static volatile uint16_t ALIGNED_I16[16]
+    __attribute__((aligned(AXI_DWIDTH))) = {
+        0x05e0, 0xbbd3, 0x3840, 0x8cd1, 0x9384, 0x7548, 0x3489, 0x9388,
+        0x8188, 0x11ae, 0x5808, 0x4891, 0x4902, 0x8759, 0x1111, 0x1989};
+static volatile uint32_t ALIGNED_I32[16]
+    __attribute__((aligned(AXI_DWIDTH))) = {
+        0x9fe41920, 0xf9aa71f0, 0xa11a9384, 0x99991348, 0x9fa831c7, 0x38197598,
+        0x18931795, 0x81937598, 0x18747547, 0x3eeeeeee, 0x90139301, 0xab8b9148,
+        0x90318509, 0x31897598, 0x83195999, 0x89139848};
+static volatile uint64_t ALIGNED_I64[16]
+    __attribute__((aligned(AXI_DWIDTH))) = {
+        0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3, 0xa11a9384a7163840,
+        0x99991348a9f38cd1, 0x9fa831c7a11a9384, 0x3819759853987548,
+        0x1893179501093489, 0x81937598aa819388, 0x1874754791888188,
+        0x3eeeeeeee33111ae, 0x9013930148815808, 0xab8b914891484891,
+        0x9031850931584902, 0x3189759837598759, 0x8319599991911111,
+        0x8913984898951989};
+
+static volatile uint8_t BUFFER_O8[16] __attribute__((aligned(AXI_DWIDTH))) = {
+    INIT, INIT, INIT, INIT, INIT, INIT, INIT, INIT,
+    INIT, INIT, INIT, INIT, INIT, INIT, INIT, INIT};
+static volatile uint16_t BUFFER_O16[16] __attribute__((aligned(AXI_DWIDTH))) = {
+    INIT, INIT, INIT, INIT, INIT, INIT, INIT, INIT,
+    INIT, INIT, INIT, INIT, INIT, INIT, INIT, INIT};
+static volatile uint32_t BUFFER_O32[16] __attribute__((aligned(AXI_DWIDTH))) = {
+    INIT, INIT, INIT, INIT, INIT, INIT, INIT, INIT,
+    INIT, INIT, INIT, INIT, INIT, INIT, INIT, INIT};
+static volatile uint64_t BUFFER_O64[16] __attribute__((aligned(AXI_DWIDTH))) = {
+    INIT, INIT, INIT, INIT, INIT, INIT, INIT, INIT,
+    INIT, INIT, INIT, INIT, INIT, INIT, INIT, INIT};
+
+//****** RAW Hazard****//
+void TEST_CASE1(void) {
+  VSET(16, e8, m1);
+  asm volatile("vle8.v v1, (%0)" ::"r"(&ALIGNED_I8[0]));
+  asm volatile("vse8.v v1, (%0)" ::"r"(&BUFFER_O8[0]));
+  VVCMP_U8(1, BUFFER_O8, 0xe0, 0xd3, 0x40, 0xd1, 0x84, 0x48, 0x89, 0x88, 0x88,
+           0xae, 0x08, 0x91, 0x02, 0x59, 0x11, 0x89);
+}
+
+//******WAR Hazard****//
+void TEST_CASE2(void) {
+  reset_vec8(&BUFFER_O8[0], INIT, 16);
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xe0, 0xd3, 0x40, 0xd1, 0x84, 0x48, 0x89, 0x88, 0x88, 0xae, 0x08,
+          0x91, 0x02, 0x59, 0x11, 0x89);
+  asm volatile("vse8.v v2, (%0)" ::"r"(&BUFFER_O8[0]));
+  asm volatile("vle8.v v2, (%0)" ::"r"(&BUFFER_O8[0]));
+  VCMP_U8(2, v2, 0xe0, 0xd3, 0x40, 0xd1, 0x84, 0x48, 0x89, 0x88, 0x88, 0xae,
+          0x08, 0x91, 0x02, 0x59, 0x11, 0x89);
+}
+
+//******WAW Hazard****//
+void TEST_CASE3(void) {
+  VSET(16, e8, m1);
+  asm volatile("vle8.v v3, (%0)" ::"r"(&ALIGNED_I8[0]));
+  asm volatile("vle8.v v3, (%0)" ::"r"(&TEST_I8[0]));
+  VCMP_U8(3, v3, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+}
+
+//****** RAW Hazard****//
+void TEST_CASE4(void) {
+  VSET(16, e16, m1);
+  asm volatile("vle16.v v4, (%0)" ::"r"(&ALIGNED_I16[0]));
+  asm volatile("vse16.v v4, (%0)" ::"r"(&BUFFER_O16[0]));
+  VVCMP_U16(4, BUFFER_O16, 0x05e0, 0xbbd3, 0x3840, 0x8cd1, 0x9384, 0x7548,
+            0x3489, 0x9388, 0x8188, 0x11ae, 0x5808, 0x4891, 0x4902, 0x8759,
+            0x1111, 0x1989);
+}
+
+//******WAR Hazard****//
+void TEST_CASE5(void) {
+  reset_vec16(&BUFFER_O16[0], INIT, 16);
+  VSET(16, e16, m1);
+  VLOAD_16(v5, 0x05e0, 0xbbd3, 0x3840, 0x8cd1, 0x9384, 0x7548, 0x3489, 0x9388,
+           0x8188, 0x11ae, 0x5808, 0x4891, 0x4902, 0x8759, 0x1111, 0x1989);
+  asm volatile("vse16.v v5, (%0)" ::"r"(&BUFFER_O16[0]));
+  asm volatile("vle16.v v5, (%0)" ::"r"(&BUFFER_O16[0]));
+  VCMP_U16(5, v5, 0x05e0, 0xbbd3, 0x3840, 0x8cd1, 0x9384, 0x7548, 0x3489,
+           0x9388, 0x8188, 0x11ae, 0x5808, 0x4891, 0x4902, 0x8759, 0x1111,
+           0x1989);
+}
+
+//******WAW Hazard****//
+void TEST_CASE6(void) {
+  VSET(16, e16, m1);
+  asm volatile("vle16.v v6, (%0)" ::"r"(&ALIGNED_I16[0]));
+  asm volatile("vle16.v v6, (%0)" ::"r"(&TEST_I16[0]));
+  VCMP_U16(6, v6, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32);
+}
+
+//****** RAW Hazard****//
+void TEST_CASE7(void) {
+  VSET(16, e32, m1);
+  asm volatile("vle32.v v7, (%0)" ::"r"(&ALIGNED_I32[0]));
+  asm volatile("vse32.v v7, (%0)" ::"r"(&BUFFER_O32[0]));
+  VVCMP_U32(7, BUFFER_O32, 0x9fe41920, 0xf9aa71f0, 0xa11a9384, 0x99991348,
+            0x9fa831c7, 0x38197598, 0x18931795, 0x81937598, 0x18747547,
+            0x3eeeeeee, 0x90139301, 0xab8b9148, 0x90318509, 0x31897598,
+            0x83195999, 0x89139848);
+}
+
+//******WAR Hazard****//
+void TEST_CASE8(void) {
+  reset_vec32(&BUFFER_O32[0], INIT, 16);
+  VSET(16, e32, m1);
+  VLOAD_32(v8, 0x9fe41920, 0xf9aa71f0, 0xa11a9384, 0x99991348, 0x9fa831c7,
+           0x38197598, 0x18931795, 0x81937598, 0x18747547, 0x3eeeeeee,
+           0x90139301, 0xab8b9148, 0x90318509, 0x31897598, 0x83195999,
+           0x89139848);
+  asm volatile("vse32.v v8, (%0)" ::"r"(&BUFFER_O32[0]));
+  asm volatile("vle32.v v8, (%0)" ::"r"(&BUFFER_O32[0]));
+  VCMP_U32(8, v8, 0x9fe41920, 0xf9aa71f0, 0xa11a9384, 0x99991348, 0x9fa831c7,
+           0x38197598, 0x18931795, 0x81937598, 0x18747547, 0x3eeeeeee,
+           0x90139301, 0xab8b9148, 0x90318509, 0x31897598, 0x83195999,
+           0x89139848);
+}
+
+//******WAW Hazard****//
+void TEST_CASE9(void) {
+  VSET(16, e32, m1);
+  asm volatile("vle32.v v9, (%0)" ::"r"(&ALIGNED_I32[0]));
+  asm volatile("vle32.v v9, (%0)" ::"r"(&TEST_I32[0]));
+  VCMP_U32(9, v9, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64);
+}
+
+//****** RAW Hazard****//
+void TEST_CASE10(void) {
+  VSET(16, e64, m1);
+  asm volatile("vle64.v v10, (%0)" ::"r"(&ALIGNED_I64[0]));
+  asm volatile("vse64.v v10, (%0)" ::"r"(&BUFFER_O64[0]));
+  VVCMP_U64(10, BUFFER_O64, 0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3,
+            0xa11a9384a7163840, 0x99991348a9f38cd1, 0x9fa831c7a11a9384,
+            0x3819759853987548, 0x1893179501093489, 0x81937598aa819388,
+            0x1874754791888188, 0x3eeeeeeee33111ae, 0x9013930148815808,
+            0xab8b914891484891, 0x9031850931584902, 0x3189759837598759,
+            0x8319599991911111, 0x8913984898951989);
+}
+
+//******WAR Hazard****//
+void TEST_CASE11(void) {
+  reset_vec64(&BUFFER_O64[0], INIT, 16);
+  VSET(16, e64, m1);
+  VLOAD_64(v11, 0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3, 0xa11a9384a7163840,
+           0x99991348a9f38cd1, 0x9fa831c7a11a9384, 0x3819759853987548,
+           0x1893179501093489, 0x81937598aa819388, 0x1874754791888188,
+           0x3eeeeeeee33111ae, 0x9013930148815808, 0xab8b914891484891,
+           0x9031850931584902, 0x3189759837598759, 0x8319599991911111,
+           0x8913984898951989);
+  asm volatile("vse64.v v11, (%0)" ::"r"(&BUFFER_O64[0]));
+  asm volatile("vle64.v v5, (%0)" ::"r"(&BUFFER_O64[0]));
+  VCMP_U64(11, v11, 0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3, 0xa11a9384a7163840,
+           0x99991348a9f38cd1, 0x9fa831c7a11a9384, 0x3819759853987548,
+           0x1893179501093489, 0x81937598aa819388, 0x1874754791888188,
+           0x3eeeeeeee33111ae, 0x9013930148815808, 0xab8b914891484891,
+           0x9031850931584902, 0x3189759837598759, 0x8319599991911111,
+           0x8913984898951989);
+}
+
+//******WAW Hazard****//
+void TEST_CASE12(void) {
+  VSET(16, e64, m1);
+  asm volatile("vle64.v v12, (%0)" ::"r"(&ALIGNED_I64[0]));
+  asm volatile("vle64.v v12, (%0)" ::"r"(&TEST_I64[0]));
+  VCMP_U64(12, v12, 8, 16, 24, 32, 40, 48, 56, 64, 72, 80, 88, 96, 104, 112,
+           120, 128);
+}
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  printf("*****Running tests of vle-vse for data hazards*****\n");
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+  TEST_CASE6();
+  TEST_CASE7();
+  TEST_CASE8();
+  TEST_CASE9();
+  TEST_CASE10();
+  TEST_CASE11();
+  TEST_CASE12();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vlff.c b/apps/riscv-tests/isa/rv64uv/vlff.c
new file mode 100644
index 0000000..886e36b
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vlff.c
@@ -0,0 +1,91 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(4, e8, m1);
+  volatile int8_t INP[] = {0xff, 0x00, 0x0f, 0xf0};
+  asm volatile("vle8ff.v v1, (%0)" ::"r"(INP));
+  VCMP_U8(1, v1, 0xff, 0x00, 0x0f, 0xf0);
+}
+
+void TEST_CASE2(void) {
+  VSET(4, e8, m1);
+  volatile int8_t INP[] = {0xff, 0x00, 0x0f, 0xf0};
+  VLOAD_8(v0, 0x5, 0x0, 0x0, 0x0);
+  VCLEAR(v1);
+  asm volatile("vle8ff.v v1, (%0), v0.t" ::"r"(INP));
+  VCMP_U8(2, v1, 0xff, 0x00, 0x0f, 0x00);
+}
+
+void TEST_CASE3(void) {
+  VSET(3, e16, m1);
+  volatile int16_t INP[] = {0xffff, 0x0000, 0x0f0f, 0xf0f0};
+  asm volatile("vle16ff.v v1, (%0)" ::"r"(INP));
+  VCMP_U16(3, v1, 0xffff, 0x0000, 0x0f0f);
+}
+
+void TEST_CASE4(void) {
+  VSET(3, e16, m1);
+  volatile int16_t INP[] = {0xffff, 0x0001, 0x0f0f, 0xf0f0};
+  VLOAD_16(v0, 0x5, 0x0, 0x0, 0x0);
+  VCLEAR(v1);
+  asm volatile("vle16ff.v v1, (%0), v0.t" ::"r"(INP));
+  VCMP_U16(4, v1, 0xffff, 0x0000, 0x0f0f);
+}
+
+void TEST_CASE5(void) {
+  VSET(4, e32, m1);
+  volatile int32_t INP[] = {0xffffffff, 0x00000000, 0x0f0f0f0f, 0xf0f0f0f0};
+  asm volatile("vle32ff.v v1, (%0)" ::"r"(INP));
+  VCMP_U32(5, v1, 0xffffffff, 0x00000000, 0x0f0f0f0f, 0xf0f0f0f0);
+}
+
+void TEST_CASE6(void) {
+  VSET(4, e32, m1);
+  volatile int32_t INP[] = {0xffffffff, 0x80000000, 0x0f0f0f0f, 0xf0f0f0f0};
+  VLOAD_32(v0, 0x5, 0x0, 0x0, 0x0);
+  VCLEAR(v1);
+  asm volatile(" vle32ff.v v1, (%0), v0.t \n" ::"r"(INP));
+  VCMP_U32(6, v1, 0xffffffff, 0x0, 0x0f0f0f0f, 0x0);
+}
+
+void TEST_CASE7(void) {
+  VSET(4, e64, m1);
+  volatile int64_t INP[] = {0xdeadbeefffffffff, 0xdeadbeef00000000,
+                            0xdeadbeef0f0f0f0f, 0xdeadbeeff0f0f0f0};
+  asm volatile("vle64ff.v v1,(%0)" ::"r"(INP));
+  VCMP_U64(7, v1, 0xdeadbeefffffffff, 0xdeadbeef00000000, 0xdeadbeef0f0f0f0f,
+           0xdeadbeeff0f0f0f0);
+}
+
+void TEST_CASE8(void) {
+  VSET(4, e64, m1);
+  volatile int64_t INP[] = {0xdeadbeefffffffff, 0xdeadbeef00000000,
+                            0xdeadbeef0f0f0f0f, 0xdeadbeeff0f0f0f0};
+  VLOAD_64(v0, 0x5, 0x0, 0x0, 0x0);
+  VCLEAR(v1);
+  asm volatile("vle64ff.v v1,(%0), v0.t" ::"r"(INP));
+  VCMP_U64(8, v1, 0xdeadbeefffffffff, 0x0000000000000000, 0xdeadbeef0f0f0f0f,
+           0x0000000000000000);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+  enable_fp();
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+  TEST_CASE6();
+  TEST_CASE7();
+  TEST_CASE8();
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vls.c b/apps/riscv-tests/isa/rv64uv/vls.c
new file mode 100644
index 0000000..0248384
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vls.c
@@ -0,0 +1,190 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+
+#include "vector_macros.h"
+
+// Positive-stride tests
+void TEST_CASE1(void) {
+  VSET(4, e8, m1);
+  volatile uint8_t INP1[] = {0x9f, 0xe4, 0x19, 0x20, 0x8f, 0x2e, 0x05, 0xe0,
+                             0xf9, 0xaa, 0x71, 0xf0, 0xc3, 0x94, 0xbb, 0xd3};
+  uint64_t stride = 3;
+  asm volatile("vlse8.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U8(1, v1, 0x9f, 0x20, 0x05, 0xaa);
+}
+
+void TEST_CASE2(void) {
+  VSET(4, e16, m1);
+  volatile uint16_t INP1[] = {0x9fe4, 0x1920, 0x8f2e, 0x05e0,
+                              0xf9aa, 0x71f0, 0xc394, 0xbbd3};
+  uint64_t stride = 4;
+  asm volatile("vlse16.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U16(2, v1, 0x9fe4, 0x8f2e, 0xf9aa, 0xc394);
+}
+
+void TEST_CASE3(void) {
+  VSET(4, e32, m1);
+  volatile uint32_t INP1[] = {0x9fe41920, 0x8f2e05e0, 0xf9aa71f0, 0xc394bbd3,
+                              0xa11a9384, 0xa7163840, 0x99991348, 0xa9f38cd1};
+  uint64_t stride = 8;
+  asm volatile("vlse32.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U32(3, v1, 0x9fe41920, 0xf9aa71f0, 0xa11a9384, 0x99991348);
+}
+
+void TEST_CASE4(void) {
+  VSET(4, e64, m1);
+  volatile uint64_t INP1[] = {0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3,
+                              0xa11a9384a7163840, 0x99991348a9f38cd1};
+  uint64_t stride = 8;
+  asm volatile("vlse64.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U64(4, v1, 0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3, 0xa11a9384a7163840,
+           0x99991348a9f38cd1);
+}
+
+// Zero-stride tests
+// The implementation must perform all the memory accesses
+void TEST_CASE5(void) {
+  VSET(16, e8, m1);
+  volatile uint8_t INP1[] = {0x9f};
+  uint64_t stride = 0;
+  asm volatile("vlse8.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U8(5, v1, 0x9f, 0x9f, 0x9f, 0x9f, 0x9f, 0x9f, 0x9f, 0x9f, 0x9f, 0x9f,
+          0x9f, 0x9f, 0x9f, 0x9f, 0x9f, 0x9f);
+}
+
+// The implementation can also perform fewer accesses
+void TEST_CASE6(void) {
+  VSET(16, e8, m1);
+  volatile uint8_t INP1[] = {0x9f};
+  asm volatile("vlse8.v v1, (%0), x0" ::"r"(INP1));
+  VCMP_U8(6, v1, 0x9f, 0x9f, 0x9f, 0x9f, 0x9f, 0x9f, 0x9f, 0x9f, 0x9f, 0x9f,
+          0x9f, 0x9f, 0x9f, 0x9f, 0x9f, 0x9f);
+}
+
+// Different LMUL
+void TEST_CASE7(void) {
+  VSET(8, e64, m2);
+  volatile uint64_t INP1[] = {0x9fa831c7a11a9384};
+  asm volatile("vlse64.v v2, (%0), x0" ::"r"(INP1));
+  VCMP_U64(7, v2, 0x9fa831c7a11a9384, 0x9fa831c7a11a9384, 0x9fa831c7a11a9384,
+           0x9fa831c7a11a9384, 0x9fa831c7a11a9384, 0x9fa831c7a11a9384,
+           0x9fa831c7a11a9384, 0x9fa831c7a11a9384);
+}
+
+// Others
+// Negative-stride test
+void TEST_CASE8(void) {
+  VSET(4, e16, m1);
+  volatile uint16_t INP1[] = {0x9fe4, 0x1920, 0x8f2e, 0x05e0,
+                              0xf9aa, 0x71f0, 0xc394, 0xbbd3};
+  uint64_t stride = -4;
+  asm volatile("vlse16.v v1, (%0), %1" ::"r"(&INP1[7]), "r"(stride));
+  VCMP_U16(8, v1, 0xbbd3, 0x71f0, 0x05e0, 0x1920);
+}
+
+// Stride greater than default Ara AXI width == 128-bit (4 lanes)
+void TEST_CASE9(void) {
+  VSET(2, e64, m1);
+  volatile uint64_t INP1[] = {0x99991348a9f38cd1, 0x9fa831c7a11a9384,
+                              0x9fa831c7a11a9384, 0x9fa831c7a11a9384,
+                              0x9fa831c7a11a9384, 0x01015ac1309bb678};
+  uint64_t stride = 40;
+  asm volatile("vlse64.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U64(9, v1, 0x99991348a9f38cd1, 0x01015ac1309bb678);
+}
+
+// Fill Ara internal Load Buffer
+void TEST_CASE10(void) {
+  VSET(8, e64, m1);
+  volatile uint64_t INP1[] = {
+      0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3, 0xa11a9384a7163840,
+      0x99991348a9f38cd1, 0x9fa831c7a11a9384, 0x3819759853987548,
+      0x1893179501093489, 0x81937598aa819388, 0x1874754791888188,
+      0x3eeeeeeee33111ae, 0x9013930148815808, 0xab8b914891484891,
+      0x9031850931584902, 0x3189759837598759, 0x8319599991911111,
+      0x8913984898951989};
+  uint64_t stride = 16;
+  asm volatile("vlse64.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U64(10, v1, 0x9fe419208f2e05e0, 0xa11a9384a7163840, 0x9fa831c7a11a9384,
+           0x1893179501093489, 0x1874754791888188, 0x9013930148815808,
+           0x9031850931584902, 0x8319599991911111);
+}
+
+// Masked stride loads
+void TEST_CASE11(void) {
+  VSET(4, e8, m1);
+  volatile uint8_t INP1[] = {0x9f, 0xe4, 0x19, 0x20, 0x8f, 0x2e, 0x05, 0xe0,
+                             0xf9, 0xaa, 0x71, 0xf0, 0xc3, 0x94, 0xbb, 0xd3};
+  uint64_t stride = 3;
+  VLOAD_8(v0, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vlse8.v v1, (%0), %1, v0.t" ::"r"(INP1), "r"(stride));
+  VCMP_U8(11, v1, 0x00, 0x20, 0x00, 0xaa);
+}
+
+void TEST_CASE12(void) {
+  VSET(4, e16, m1);
+  volatile uint16_t INP1[] = {0x9fe4, 0x1920, 0x8f2e, 0x05e0,
+                              0xf9aa, 0x71f0, 0xc394, 0xbbd3};
+  uint64_t stride = 4;
+  VLOAD_8(v0, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vlse16.v v1, (%0), %1, v0.t" ::"r"(INP1), "r"(stride));
+  VCMP_U16(12, v1, 0, 0x8f2e, 0, 0xc394);
+}
+
+void TEST_CASE13(void) {
+  VSET(4, e32, m1);
+  volatile uint32_t INP1[] = {0x9fe41920, 0x8f2e05e0, 0xf9aa71f0, 0xc394bbd3,
+                              0xa11a9384, 0xa7163840, 0x99991348, 0xa9f38cd1};
+  uint64_t stride = 8;
+  VLOAD_8(v0, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vlse32.v v1, (%0), %1, v0.t" ::"r"(INP1), "r"(stride));
+  VCMP_U32(13, v1, 0, 0xf9aa71f0, 0, 0x99991348);
+}
+
+void TEST_CASE14(void) {
+  VSET(8, e64, m1);
+  volatile uint64_t INP1[] = {
+      0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3, 0xa11a9384a7163840,
+      0x99991348a9f38cd1, 0x9fa831c7a11a9384, 0x3819759853987548,
+      0x1893179501093489, 0x81937598aa819388, 0x1874754791888188,
+      0x3eeeeeeee33111ae, 0x9013930148815808, 0xab8b914891484891,
+      0x9031850931584902, 0x3189759837598759, 0x8319599991911111,
+      0x8913984898951989};
+  uint64_t stride = 16;
+  VLOAD_8(v0, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vlse64.v v1, (%0), %1, v0.t" ::"r"(INP1), "r"(stride));
+  VCMP_U64(14, v1, 0, 0xa11a9384a7163840, 0, 0x1893179501093489, 0,
+           0x9013930148815808, 0, 0x8319599991911111);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  TEST_CASE5();
+  TEST_CASE6();
+  TEST_CASE7();
+
+  TEST_CASE8();
+  TEST_CASE9();
+  TEST_CASE10();
+
+  TEST_CASE11();
+  TEST_CASE12();
+  TEST_CASE13();
+  TEST_CASE14();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vlseg.c b/apps/riscv-tests/isa/rv64uv/vlseg.c
new file mode 100644
index 0000000..6bd4678
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vlseg.c
@@ -0,0 +1,391 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+
+#include "vector_macros.h"
+
+// Segment-2
+void TEST_CASE1_8(void) {
+  VSET(4, e8, m1);
+  volatile uint8_t INP1[] = {0x9f, 0xe4, 0x19, 0x20, 0x8f, 0x2e, 0x05, 0xe0,
+                             0xf9, 0xaa, 0x71, 0xf0, 0xc3, 0x94, 0xbb, 0xd3};
+  VCLEAR(v1);
+  VCLEAR(v2);
+  asm volatile("vlseg2e8.v v1, (%0)" ::"r"(INP1));
+  VCMP_U8(1, v1, 0x9f, 0x19, 0x8f, 0x05);
+  VCMP_U8(2, v2, 0xe4, 0x20, 0x2e, 0xe0);
+}
+
+// Segment-3
+void TEST_CASE2_8(void) {
+  VSET(4, e8, m1);
+  volatile uint8_t INP1[] = {0x9f, 0xe4, 0x19, 0x20, 0x8f, 0x2e, 0x05, 0xe0,
+                             0xf9, 0xaa, 0x71, 0xf0, 0xc3, 0x94, 0xbb, 0xd3};
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  asm volatile("vlseg3e8.v v1, (%0)" ::"r"(INP1));
+  VCMP_U8(3, v1, 0x9f, 0x20, 0x05, 0xaa);
+  VCMP_U8(4, v2, 0xe4, 0x8f, 0xe0, 0x71);
+  VCMP_U8(5, v3, 0x19, 0x2e, 0xf9, 0xf0);
+}
+
+// Segment-4
+void TEST_CASE3_8(void) {
+  VSET(4, e8, m1);
+  volatile uint8_t INP1[] = {0x9f, 0xe4, 0x19, 0x20, 0x8f, 0x2e, 0x05, 0xe0,
+                             0xf9, 0xaa, 0x71, 0xf0, 0xc3, 0x94, 0xbb, 0xd3};
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  asm volatile("vlseg4e8.v v1, (%0)" ::"r"(INP1));
+  VCMP_U8(6, v1, 0x9f, 0x8f, 0xf9, 0xc3);
+  VCMP_U8(7, v2, 0xe4, 0x2e, 0xaa, 0x94);
+  VCMP_U8(8, v3, 0x19, 0x05, 0x71, 0xbb);
+  VCMP_U8(9, v4, 0x20, 0xe0, 0xf0, 0xd3);
+}
+
+// Segment-8
+void TEST_CASE4_8(void) {
+  VSET(2, e8, m1);
+  volatile uint8_t INP1[] = {0x9f, 0xe4, 0x19, 0x20, 0x8f, 0x2e, 0x05, 0xe0,
+                             0xf9, 0xaa, 0x71, 0xf0, 0xc3, 0x94, 0xbb, 0xd3};
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  VCLEAR(v5);
+  VCLEAR(v6);
+  VCLEAR(v7);
+  VCLEAR(v8);
+  asm volatile("vlseg8e8.v v1, (%0)" ::"r"(INP1));
+  VCMP_U8(10, v1, 0x9f, 0xf9);
+  VCMP_U8(11, v2, 0xe4, 0xaa);
+  VCMP_U8(12, v3, 0x19, 0x71);
+  VCMP_U8(13, v4, 0x20, 0xf0);
+  VCMP_U8(14, v5, 0x8f, 0xc3);
+  VCMP_U8(15, v6, 0x2e, 0x94);
+  VCMP_U8(16, v7, 0x05, 0xbb);
+  VCMP_U8(17, v8, 0xe0, 0xd3);
+}
+
+// Segment-2 for 16-bit
+void TEST_CASE1_16(void) {
+  VSET(4, e16, m1);
+  volatile uint16_t INP1[] = {0x9fe4, 0x1920, 0x8f2e, 0x05e0, 0xf9aa, 0x71f0,
+                              0xc394, 0xbbd3, 0x1234, 0x5678, 0x9abc, 0xdef0,
+                              0x1357, 0x2468, 0x369b, 0x48ac};
+  VCLEAR(v1);
+  VCLEAR(v2);
+  asm volatile("vlseg2e16.v v1, (%0)" ::"r"(INP1));
+  VCMP_U16(18, v1, 0x9fe4, 0x8f2e, 0xf9aa, 0xc394);
+  VCMP_U16(19, v2, 0x1920, 0x05e0, 0x71f0, 0xbbd3);
+}
+
+// Segment-3 for 16-bit
+void TEST_CASE2_16(void) {
+  VSET(4, e16, m1);
+  volatile uint16_t INP1[] = {0x9fe4, 0x1920, 0x8f2e, 0x05e0, 0xf9aa, 0x71f0,
+                              0xc394, 0xbbd3, 0x1234, 0x5678, 0x9abc, 0xdef0,
+                              0x1357, 0x2468, 0x369b, 0x48ac};
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  asm volatile("vlseg3e16.v v1, (%0)" ::"r"(INP1));
+  VCMP_U16(20, v1, 0x9fe4, 0x05e0, 0xc394, 0x5678);
+  VCMP_U16(21, v2, 0x1920, 0xf9aa, 0xbbd3, 0x9abc);
+  VCMP_U16(22, v3, 0x8f2e, 0x71f0, 0x1234, 0xdef0);
+}
+
+// Segment-4 for 16-bit
+void TEST_CASE3_16(void) {
+  VSET(4, e16, m1);
+  volatile uint16_t INP1[] = {0x9fe4, 0x1920, 0x8f2e, 0x05e0, 0xf9aa, 0x71f0,
+                              0xc394, 0xbbd3, 0x1234, 0x5678, 0x9abc, 0xdef0,
+                              0x1357, 0x2468, 0x369b, 0x48ac};
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  asm volatile("vlseg4e16.v v1, (%0)" ::"r"(INP1));
+  VCMP_U16(23, v1, 0x9fe4, 0xf9aa, 0x1234, 0x1357);
+  VCMP_U16(24, v2, 0x1920, 0x71f0, 0x5678, 0x2468);
+  VCMP_U16(25, v3, 0x8f2e, 0xc394, 0x9abc, 0x369b);
+  VCMP_U16(26, v4, 0x05e0, 0xbbd3, 0xdef0, 0x48ac);
+}
+
+// Segment-8 for 16-bit
+void TEST_CASE4_16(void) {
+  VSET(2, e16, m1);
+  volatile uint16_t INP1[] = {0x9fe4, 0x1920, 0x8f2e, 0x05e0, 0xf9aa, 0x71f0,
+                              0xc394, 0xbbd3, 0x1234, 0x5678, 0x9abc, 0xdef0,
+                              0x1357, 0x2468, 0x369b, 0x48ac};
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  VCLEAR(v5);
+  VCLEAR(v6);
+  VCLEAR(v7);
+  VCLEAR(v8);
+  asm volatile("vlseg8e16.v v1, (%0)" ::"r"(INP1));
+  VCMP_U16(27, v1, 0x9fe4, 0x1234);
+  VCMP_U16(28, v2, 0x1920, 0x5678);
+  VCMP_U16(29, v3, 0x8f2e, 0x9abc);
+  VCMP_U16(30, v4, 0x05e0, 0xdef0);
+  VCMP_U16(31, v5, 0xf9aa, 0x1357);
+  VCMP_U16(32, v6, 0x71f0, 0x2468);
+  VCMP_U16(33, v7, 0xc394, 0x369b);
+  VCMP_U16(34, v8, 0xbbd3, 0x48ac);
+}
+
+// Segment-2 for 32-bit
+void TEST_CASE1_32(void) {
+  VSET(4, e32, m1);
+  volatile uint32_t INP1[] = {0x9fe41920, 0x8f2e05e0, 0xf9aa71f0, 0xc394bbd3,
+                              0x12345678, 0x9abcdef0, 0x13572468, 0x369b48ac,
+                              0xdeadbeef, 0xcafebabe, 0x01234567, 0x89abcdef,
+                              0x55aa55aa, 0x77889900, 0xabcdef12, 0x34567890};
+  VCLEAR(v1);
+  VCLEAR(v2);
+  asm volatile("vlseg2e32.v v1, (%0)" ::"r"(INP1));
+  VCMP_U32(35, v1, 0x9fe41920, 0xf9aa71f0, 0x12345678, 0x13572468);
+  VCMP_U32(36, v2, 0x8f2e05e0, 0xc394bbd3, 0x9abcdef0, 0x369b48ac);
+}
+
+// Segment-3 for 32-bit
+void TEST_CASE2_32(void) {
+  VSET(4, e32, m1);
+  volatile uint32_t INP1[] = {0x9fe41920, 0x8f2e05e0, 0xf9aa71f0, 0xc394bbd3,
+                              0x12345678, 0x9abcdef0, 0x13572468, 0x369b48ac,
+                              0xdeadbeef, 0xcafebabe, 0x01234567, 0x89abcdef,
+                              0x55aa55aa, 0x77889900, 0xabcdef12, 0x34567890};
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  asm volatile("vlseg3e32.v v1, (%0)" ::"r"(INP1));
+  VCMP_U32(37, v1, 0x9fe41920, 0xc394bbd3, 0x13572468, 0xcafebabe);
+  VCMP_U32(38, v2, 0x8f2e05e0, 0x12345678, 0x369b48ac, 0x01234567);
+  VCMP_U32(39, v3, 0xf9aa71f0, 0x9abcdef0, 0xdeadbeef, 0x89abcdef);
+}
+
+// Segment-4 for 32-bit
+void TEST_CASE3_32(void) {
+  VSET(4, e32, m1);
+  volatile uint32_t INP1[] = {0x9fe41920, 0x8f2e05e0, 0xf9aa71f0, 0xc394bbd3,
+                              0x12345678, 0x9abcdef0, 0x13572468, 0x369b48ac,
+                              0xdeadbeef, 0xcafebabe, 0x01234567, 0x89abcdef,
+                              0x55aa55aa, 0x77889900, 0xabcdef12, 0x34567890};
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  asm volatile("vlseg4e32.v v1, (%0)" ::"r"(INP1));
+  VCMP_U32(40, v1, 0x9fe41920, 0x12345678, 0xdeadbeef, 0x55aa55aa);
+  VCMP_U32(41, v2, 0x8f2e05e0, 0x9abcdef0, 0xcafebabe, 0x77889900);
+  VCMP_U32(42, v3, 0xf9aa71f0, 0x13572468, 0x01234567, 0xabcdef12);
+  VCMP_U32(43, v4, 0xc394bbd3, 0x369b48ac, 0x89abcdef, 0x34567890);
+}
+
+// Segment-8 for 32-bit
+void TEST_CASE4_32(void) {
+  VSET(2, e32, m1);
+  volatile uint32_t INP1[] = {0x9fe41920, 0x8f2e05e0, 0xf9aa71f0, 0xc394bbd3,
+                              0x12345678, 0x9abcdef0, 0x13572468, 0x369b48ac,
+                              0xdeadbeef, 0xcafebabe, 0x01234567, 0x89abcdef,
+                              0x55aa55aa, 0x77889900, 0xabcdef12, 0x34567890};
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  VCLEAR(v5);
+  VCLEAR(v6);
+  VCLEAR(v7);
+  VCLEAR(v8);
+  asm volatile("vlseg8e32.v v1, (%0)" ::"r"(INP1));
+  VCMP_U32(44, v1, 0x9fe41920, 0xdeadbeef);
+  VCMP_U32(45, v2, 0x8f2e05e0, 0xcafebabe);
+  VCMP_U32(46, v3, 0xf9aa71f0, 0x01234567);
+  VCMP_U32(47, v4, 0xc394bbd3, 0x89abcdef);
+  VCMP_U32(48, v5, 0x12345678, 0x55aa55aa);
+  VCMP_U32(49, v6, 0x9abcdef0, 0x77889900);
+  VCMP_U32(50, v7, 0x13572468, 0xabcdef12);
+  VCMP_U32(51, v8, 0x369b48ac, 0x34567890);
+}
+
+// Segment-2 for 64-bit
+void TEST_CASE1_64(void) {
+  VSET(4, e64, m1);
+  volatile uint64_t INP1[] = {
+      0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3, 0x123456789abcdef0,
+      0x13572468369b48ac, 0xdeadbeefcafebabe, 0x0123456789abcdef,
+      0x55aa55aa77889900, 0xabcdef1234567890, 0xfeedfacecafebabe,
+      0x123456789abcdef0, 0x1357246855aa55aa, 0x369b48acdeadbeef,
+      0xcafebabe12345678, 0xabcdef0987654321, 0x012345670abcdef1,
+      0x987654321fedcba0};
+  VCLEAR(v1);
+  VCLEAR(v2);
+  asm volatile("vlseg2e64.v v1, (%0)" ::"r"(INP1));
+  VCMP_U64(52, v1, 0x9fe419208f2e05e0, 0x123456789abcdef0, 0xdeadbeefcafebabe,
+           0x55aa55aa77889900);
+  VCMP_U64(53, v2, 0xf9aa71f0c394bbd3, 0x13572468369b48ac, 0x0123456789abcdef,
+           0xabcdef1234567890);
+}
+
+// Segment-3 for 64-bit
+void TEST_CASE2_64(void) {
+  VSET(4, e64, m1);
+  volatile uint64_t INP1[] = {
+      0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3, 0x123456789abcdef0,
+      0x13572468369b48ac, 0xdeadbeefcafebabe, 0x0123456789abcdef,
+      0x55aa55aa77889900, 0xabcdef1234567890, 0xfeedfacecafebabe,
+      0x123456789abcdef0, 0x1357246855aa55aa, 0x369b48acdeadbeef,
+      0xcafebabe12345678, 0xabcdef0987654321, 0x012345670abcdef1,
+      0x987654321fedcba0};
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  asm volatile("vlseg3e64.v v1, (%0)" ::"r"(INP1));
+  VCMP_U64(54, v1, 0x9fe419208f2e05e0, 0x13572468369b48ac, 0x55aa55aa77889900,
+           0x123456789abcdef0);
+  VCMP_U64(55, v2, 0xf9aa71f0c394bbd3, 0xdeadbeefcafebabe, 0xabcdef1234567890,
+           0x1357246855aa55aa);
+  VCMP_U64(56, v3, 0x123456789abcdef0, 0x0123456789abcdef, 0xfeedfacecafebabe,
+           0x369b48acdeadbeef);
+}
+
+// Segment-4 for 64-bit
+void TEST_CASE3_64(void) {
+  VSET(4, e64, m1);
+  volatile uint64_t INP1[] = {
+      0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3, 0x123456789abcdef0,
+      0x13572468369b48ac, 0xdeadbeefcafebabe, 0x0123456789abcdef,
+      0x55aa55aa77889900, 0xabcdef1234567890, 0xfeedfacecafebabe,
+      0x123456789abcdef0, 0x1357246855aa55aa, 0x369b48acdeadbeef,
+      0xcafebabe12345678, 0xabcdef0987654321, 0x012345670abcdef1,
+      0x987654321fedcba0};
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  asm volatile("vlseg4e64.v v1, (%0)" ::"r"(INP1));
+  VCMP_U64(57, v1, 0x9fe419208f2e05e0, 0xdeadbeefcafebabe, 0xfeedfacecafebabe,
+           0xcafebabe12345678);
+  VCMP_U64(58, v2, 0xf9aa71f0c394bbd3, 0x0123456789abcdef, 0x123456789abcdef0,
+           0xabcdef0987654321);
+  VCMP_U64(59, v3, 0x123456789abcdef0, 0x55aa55aa77889900, 0x1357246855aa55aa,
+           0x012345670abcdef1);
+  VCMP_U64(60, v4, 0x13572468369b48ac, 0xabcdef1234567890, 0x369b48acdeadbeef,
+           0x987654321fedcba0);
+}
+
+// Segment-8 for 64-bit
+void TEST_CASE4_64(void) {
+  VSET(2, e64, m1);
+  volatile uint64_t INP1[] = {
+      0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3, 0x123456789abcdef0,
+      0x13572468369b48ac, 0xdeadbeefcafebabe, 0x0123456789abcdef,
+      0x55aa55aa77889900, 0xabcdef1234567890, 0xfeedfacecafebabe,
+      0x123456789abcdef0, 0x1357246855aa55aa, 0x369b48acdeadbeef,
+      0xcafebabe12345678, 0xabcdef0987654321, 0x012345670abcdef1,
+      0x987654321fedcba0};
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  VCLEAR(v5);
+  VCLEAR(v6);
+  VCLEAR(v7);
+  VCLEAR(v8);
+  asm volatile("vlseg8e64.v v1, (%0)" ::"r"(INP1));
+  VCMP_U64(61, v1, 0x9fe419208f2e05e0, 0xfeedfacecafebabe);
+  VCMP_U64(62, v2, 0xf9aa71f0c394bbd3, 0x123456789abcdef0);
+  VCMP_U64(63, v3, 0x123456789abcdef0, 0x1357246855aa55aa);
+  VCMP_U64(64, v4, 0x13572468369b48ac, 0x369b48acdeadbeef);
+  VCMP_U64(65, v5, 0xdeadbeefcafebabe, 0xcafebabe12345678);
+  VCMP_U64(66, v6, 0x0123456789abcdef, 0xabcdef0987654321);
+  VCMP_U64(67, v7, 0x55aa55aa77889900, 0x012345670abcdef1);
+  VCMP_U64(68, v8, 0xabcdef1234567890, 0x987654321fedcba0);
+}
+
+// Segment-8 for 64-bit
+void TEST_CASE4_64_m(void) {
+  VSET(2, e64, m1);
+  volatile uint64_t INP1[] = {
+      0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3, 0x123456789abcdef0,
+      0x13572468369b48ac, 0xdeadbeefcafebabe, 0x0123456789abcdef,
+      0x55aa55aa77889900, 0xabcdef1234567890, 0xfeedfacecafebabe,
+      0x123456789abcdef0, 0x1357246855aa55aa, 0x369b48acdeadbeef,
+      0xcafebabe12345678, 0xabcdef0987654321, 0x012345670abcdef1,
+      0x987654321fedcba0};
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  VCLEAR(v5);
+  VCLEAR(v6);
+  VCLEAR(v7);
+  VCLEAR(v8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vlseg8e64.v v1, (%0), v0.t" ::"r"(INP1));
+  VCMP_U64(69, v1, 0, 0xfeedfacecafebabe);
+  VCMP_U64(70, v2, 0, 0x123456789abcdef0);
+  VCMP_U64(71, v3, 0, 0x1357246855aa55aa);
+  VCMP_U64(72, v4, 0, 0x369b48acdeadbeef);
+  VCMP_U64(73, v5, 0, 0xcafebabe12345678);
+  VCMP_U64(74, v6, 0, 0xabcdef0987654321);
+  VCMP_U64(75, v7, 0, 0x012345670abcdef1);
+  VCMP_U64(76, v8, 0, 0x987654321fedcba0);
+
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  VCLEAR(v5);
+  VCLEAR(v6);
+  VCLEAR(v7);
+  VCLEAR(v8);
+  VLOAD_8(v0, 0xA8, 0xAA);
+  asm volatile("vlseg8e64.v v1, (%0), v0.t" ::"r"(INP1));
+  VCMP_U64(77, v1, 0, 0);
+  VCMP_U64(78, v2, 0, 0);
+  VCMP_U64(79, v3, 0, 0);
+  VCMP_U64(80, v4, 0, 0);
+  VCMP_U64(81, v5, 0, 0);
+  VCMP_U64(82, v6, 0, 0);
+  VCMP_U64(83, v7, 0, 0);
+  VCMP_U64(84, v8, 0, 0);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1_8();
+  TEST_CASE2_8();
+  TEST_CASE3_8();
+  TEST_CASE4_8();
+
+  TEST_CASE1_16();
+  TEST_CASE2_16();
+  TEST_CASE3_16();
+  TEST_CASE4_16();
+
+  TEST_CASE1_32();
+  TEST_CASE2_32();
+  TEST_CASE3_32();
+  TEST_CASE4_32();
+
+  TEST_CASE1_64();
+  TEST_CASE2_64();
+  TEST_CASE3_64();
+  TEST_CASE4_64();
+
+  // Masked
+  TEST_CASE4_64_m();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vlsseg.c b/apps/riscv-tests/isa/rv64uv/vlsseg.c
new file mode 100644
index 0000000..c6d7a70
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vlsseg.c
@@ -0,0 +1,1678 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+
+#include "vector_macros.h"
+
+int stride;
+
+// Segment-2
+void TEST_CASE1_8(void) {
+
+  VSET(-1, e8, m1);
+  volatile uint8_t INP1[] = {
+      0x9f, 0xe4, 0x19, 0x20, 0x8f, 0x2e, 0x05, 0xe0, 0xf9, 0xaa, 0x71,
+      0xf0, 0xc3, 0x94, 0xbb, 0xd3, 0x31, 0x4a, 0x57, 0x6b, 0x83, 0x7d,
+      0x1a, 0x45, 0xb2, 0xda, 0x22, 0x56, 0x63, 0x8c, 0xf7, 0x3e, 0x6c,
+      0x27, 0x74, 0x9d, 0xab, 0xcd, 0x13, 0x38, 0x5e, 0x42, 0xdf, 0x80,
+      0x60, 0xa4, 0x7b, 0x0b, 0xc6, 0xad, 0x91, 0xec, 0x3c, 0x69, 0xf5,
+      0x18, 0xe8, 0x6d, 0xb9, 0x82, 0x97, 0x2a, 0x51, 0x70};
+  VCLEAR(v1);
+  VCLEAR(v2);
+  stride = 0;
+  VSET(5, e8, m1);
+  asm volatile("vlsseg2e8.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U8(1, v1, 0x9f, 0x9f, 0x9f, 0x9f, 0x9f);
+  VCMP_U8(2, v2, 0xe4, 0xe4, 0xe4, 0xe4, 0xe4);
+
+  VCLEAR(v1);
+  VCLEAR(v2);
+  stride = 2;
+  VSET(32, e8, m1);
+  asm volatile("vlsseg2e8.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U8(1, v1, 0x9f, 0x19, 0x8f, 0x05, 0xf9, 0x71, 0xc3, 0xbb, 0x31, 0x57,
+          0x83, 0x1a, 0xb2, 0x22, 0x63, 0xf7, 0x6c, 0x74, 0xab, 0x13, 0x5e,
+          0xdf, 0x60, 0x7b, 0xc6, 0x91, 0x3c, 0xf5, 0xe8, 0xb9, 0x97, 0x51);
+  VCMP_U8(2, v2, 0xe4, 0x20, 0x2e, 0xe0, 0xaa, 0xf0, 0x94, 0xd3, 0x4a, 0x6b,
+          0x7d, 0x45, 0xda, 0x56, 0x8c, 0x3e, 0x27, 0x9d, 0xcd, 0x38, 0x42,
+          0x80, 0xa4, 0x0b, 0xad, 0xec, 0x69, 0x18, 0x6d, 0x82, 0x2a, 0x70);
+
+  VCLEAR(v1);
+  VCLEAR(v2);
+  stride = 3;
+  VSET(21, e8, m1);
+  asm volatile("vlsseg2e8.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U8(3, v1, 0x9f, 0x20, 0x05, 0xaa, 0xc3, 0xd3, 0x57, 0x7d, 0xb2, 0x56,
+          0xf7, 0x27, 0xab, 0x38, 0xdf, 0xa4, 0xc6, 0xec, 0xf5, 0x6d, 0x97);
+  VCMP_U8(4, v2, 0xe4, 0x8f, 0xe0, 0x71, 0x94, 0x31, 0x6b, 0x1a, 0xda, 0x63,
+          0x3e, 0x74, 0xcd, 0x5e, 0x80, 0x7b, 0xad, 0x3c, 0x18, 0xb9, 0x2a);
+  VCLEAR(v1);
+  VCLEAR(v2);
+  stride = 4;
+  VSET(16, e8, m1);
+  asm volatile("vlsseg2e8.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U8(5, v1, 0x9f, 0x8f, 0xf9, 0xc3, 0x31, 0x83, 0xb2, 0x63, 0x6c, 0xab,
+          0x5e, 0x60, 0xc6, 0x3c, 0xe8, 0x97);
+  VCMP_U8(6, v2, 0xe4, 0x2e, 0xaa, 0x94, 0x4a, 0x7d, 0xda, 0x8c, 0x27, 0xcd,
+          0x42, 0xa4, 0xad, 0x69, 0x6d, 0x2a);
+}
+
+// Segment-3
+void TEST_CASE2_8(void) {
+  VSET(-1, e8, m1);
+  volatile uint8_t INP1[] = {
+      0x9f, 0xe4, 0x19, 0x20, 0x8f, 0x2e, 0x05, 0xe0, 0xf9, 0xaa, 0x71,
+      0xf0, 0xc3, 0x94, 0xbb, 0xd3, 0x31, 0x4a, 0x57, 0x6b, 0x83, 0x7d,
+      0x1a, 0x45, 0xb2, 0xda, 0x22, 0x56, 0x63, 0x8c, 0xf7, 0x3e, 0x6c,
+      0x27, 0x74, 0x9d, 0xab, 0xcd, 0x13, 0x38, 0x5e, 0x42, 0xdf, 0x80,
+      0x60, 0xa4, 0x7b, 0x0b, 0xc6, 0xad, 0x91, 0xec, 0x3c, 0x69, 0xf5,
+      0x18, 0xe8, 0x6d, 0xb9, 0x82, 0x97, 0x2a, 0x51, 0x70};
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  stride = 2;
+  VSET(31, e8, m1);
+  asm volatile("vlsseg3e8.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U8(7, v1, 0x9f, 0x19, 0x8f, 0x05, 0xf9, 0x71, 0xc3, 0xbb, 0x31, 0x57,
+          0x83, 0x1a, 0xb2, 0x22, 0x63, 0xf7, 0x6c, 0x74, 0xab, 0x13, 0x5e,
+          0xdf, 0x60, 0x7b, 0xc6, 0x91, 0x3c, 0xf5, 0xe8, 0xb9, 0x97);
+  VCMP_U8(8, v2, 0xe4, 0x20, 0x2e, 0xe0, 0xaa, 0xf0, 0x94, 0xd3, 0x4a, 0x6b,
+          0x7d, 0x45, 0xda, 0x56, 0x8c, 0x3e, 0x27, 0x9d, 0xcd, 0x38, 0x42,
+          0x80, 0xa4, 0x0b, 0xad, 0xec, 0x69, 0x18, 0x6d, 0x82, 0x2a);
+  VCMP_U8(9, v3, 0x19, 0x8f, 0x05, 0xf9, 0x71, 0xc3, 0xbb, 0x31, 0x57, 0x83,
+          0x1a, 0xb2, 0x22, 0x63, 0xf7, 0x6c, 0x74, 0xab, 0x13, 0x5e, 0xdf,
+          0x60, 0x7b, 0xc6, 0x91, 0x3c, 0xf5, 0xe8, 0xb9, 0x97, 0x51);
+
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  stride = 3;
+  VSET(21, e8, m1);
+  asm volatile("vlsseg3e8.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U8(10, v1, 0x9f, 0x20, 0x05, 0xaa, 0xc3, 0xd3, 0x57, 0x7d, 0xb2, 0x56,
+          0xf7, 0x27, 0xab, 0x38, 0xdf, 0xa4, 0xc6, 0xec, 0xf5, 0x6d, 0x97);
+  VCMP_U8(11, v2, 0xe4, 0x8f, 0xe0, 0x71, 0x94, 0x31, 0x6b, 0x1a, 0xda, 0x63,
+          0x3e, 0x74, 0xcd, 0x5e, 0x80, 0x7b, 0xad, 0x3c, 0x18, 0xb9, 0x2a);
+  VCMP_U8(12, v3, 0x19, 0x2e, 0xf9, 0xf0, 0xbb, 0x4a, 0x83, 0x45, 0x22, 0x8c,
+          0x6c, 0x9d, 0x13, 0x42, 0x60, 0x0b, 0x91, 0x69, 0xe8, 0x82, 0x51);
+
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  stride = 4;
+  VSET(16, e8, m1);
+  asm volatile("vlsseg3e8.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U8(13, v1, 0x9f, 0x8f, 0xf9, 0xc3, 0x31, 0x83, 0xb2, 0x63, 0x6c, 0xab,
+          0x5e, 0x60, 0xc6, 0x3c, 0xe8, 0x97);
+  VCMP_U8(14, v2, 0xe4, 0x2e, 0xaa, 0x94, 0x4a, 0x7d, 0xda, 0x8c, 0x27, 0xcd,
+          0x42, 0xa4, 0xad, 0x69, 0x6d, 0x2a);
+  VCMP_U8(15, v3, 0x19, 0x05, 0x71, 0xbb, 0x57, 0x1a, 0x22, 0xf7, 0x74, 0x13,
+          0xdf, 0x7b, 0x91, 0xf5, 0xb9, 0x51);
+}
+
+// Segment-4
+void TEST_CASE3_8(void) {
+  VSET(-1, e8, m1);
+  volatile uint8_t INP1[] = {
+      0x9f, 0xe4, 0x19, 0x20, 0x8f, 0x2e, 0x05, 0xe0, 0xf9, 0xaa, 0x71,
+      0xf0, 0xc3, 0x94, 0xbb, 0xd3, 0x31, 0x4a, 0x57, 0x6b, 0x83, 0x7d,
+      0x1a, 0x45, 0xb2, 0xda, 0x22, 0x56, 0x63, 0x8c, 0xf7, 0x3e, 0x6c,
+      0x27, 0x74, 0x9d, 0xab, 0xcd, 0x13, 0x38, 0x5e, 0x42, 0xdf, 0x80,
+      0x60, 0xa4, 0x7b, 0x0b, 0xc6, 0xad, 0x91, 0xec, 0x3c, 0x69, 0xf5,
+      0x18, 0xe8, 0x6d, 0xb9, 0x82, 0x97, 0x2a, 0x51, 0x70};
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  stride = 2;
+  VSET(31, e8, m1);
+  asm volatile("vlsseg4e8.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U8(16, v1, 0x9f, 0x19, 0x8f, 0x05, 0xf9, 0x71, 0xc3, 0xbb, 0x31, 0x57,
+          0x83, 0x1a, 0xb2, 0x22, 0x63, 0xf7, 0x6c, 0x74, 0xab, 0x13, 0x5e,
+          0xdf, 0x60, 0x7b, 0xc6, 0x91, 0x3c, 0xf5, 0xe8, 0xb9, 0x97);
+  VCMP_U8(17, v2, 0xe4, 0x20, 0x2e, 0xe0, 0xaa, 0xf0, 0x94, 0xd3, 0x4a, 0x6b,
+          0x7d, 0x45, 0xda, 0x56, 0x8c, 0x3e, 0x27, 0x9d, 0xcd, 0x38, 0x42,
+          0x80, 0xa4, 0x0b, 0xad, 0xec, 0x69, 0x18, 0x6d, 0x82, 0x2a);
+  VCMP_U8(18, v3, 0x19, 0x8f, 0x05, 0xf9, 0x71, 0xc3, 0xbb, 0x31, 0x57, 0x83,
+          0x1a, 0xb2, 0x22, 0x63, 0xf7, 0x6c, 0x74, 0xab, 0x13, 0x5e, 0xdf,
+          0x60, 0x7b, 0xc6, 0x91, 0x3c, 0xf5, 0xe8, 0xb9, 0x97, 0x51);
+  VCMP_U8(19, v4, 0x20, 0x2e, 0xe0, 0xaa, 0xf0, 0x94, 0xd3, 0x4a, 0x6b, 0x7d,
+          0x45, 0xda, 0x56, 0x8c, 0x3e, 0x27, 0x9d, 0xcd, 0x38, 0x42, 0x80,
+          0xa4, 0x0b, 0xad, 0xec, 0x69, 0x18, 0x6d, 0x82, 0x2a, 0x70);
+
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  stride = 3;
+  VSET(21, e8, m1);
+  asm volatile("vlsseg4e8.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U8(20, v1, 0x9f, 0x20, 0x05, 0xaa, 0xc3, 0xd3, 0x57, 0x7d, 0xb2, 0x56,
+          0xf7, 0x27, 0xab, 0x38, 0xdf, 0xa4, 0xc6, 0xec, 0xf5, 0x6d, 0x97);
+  VCMP_U8(21, v2, 0xe4, 0x8f, 0xe0, 0x71, 0x94, 0x31, 0x6b, 0x1a, 0xda, 0x63,
+          0x3e, 0x74, 0xcd, 0x5e, 0x80, 0x7b, 0xad, 0x3c, 0x18, 0xb9, 0x2a);
+  VCMP_U8(22, v3, 0x19, 0x2e, 0xf9, 0xf0, 0xbb, 0x4a, 0x83, 0x45, 0x22, 0x8c,
+          0x6c, 0x9d, 0x13, 0x42, 0x60, 0x0b, 0x91, 0x69, 0xe8, 0x82, 0x51);
+  VCMP_U8(23, v4, 0x20, 0x05, 0xaa, 0xc3, 0xd3, 0x57, 0x7d, 0xb2, 0x56, 0xf7,
+          0x27, 0xab, 0x38, 0xdf, 0xa4, 0xc6, 0xec, 0xf5, 0x6d, 0x97, 0x70);
+
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  stride = 4;
+  VSET(15, e8, m1);
+  asm volatile("vlsseg4e8.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U8(24, v1, 0x9f, 0x8f, 0xf9, 0xc3, 0x31, 0x83, 0xb2, 0x63, 0x6c, 0xab,
+          0x5e, 0x60, 0xc6, 0x3c, 0xe8);
+  VCMP_U8(25, v2, 0xe4, 0x2e, 0xaa, 0x94, 0x4a, 0x7d, 0xda, 0x8c, 0x27, 0xcd,
+          0x42, 0xa4, 0xad, 0x69, 0x6d);
+  VCMP_U8(26, v3, 0x19, 0x05, 0x71, 0xbb, 0x57, 0x1a, 0x22, 0xf7, 0x74, 0x13,
+          0xdf, 0x7b, 0x91, 0xf5, 0xb9);
+  VCMP_U8(27, v4, 0x20, 0xe0, 0xf0, 0xd3, 0x6b, 0x45, 0x56, 0x3e, 0x9d, 0x38,
+          0x80, 0x0b, 0xec, 0x18, 0x82);
+}
+
+// Segment-8
+void TEST_CASE4_8(void) {
+  VSET(-1, e8, m1);
+  volatile uint8_t INP1[] = {
+      0x9f, 0xe4, 0x19, 0x20, 0x8f, 0x2e, 0x05, 0xe0, 0xf9, 0xaa, 0x71,
+      0xf0, 0xc3, 0x94, 0xbb, 0xd3, 0x31, 0x4a, 0x57, 0x6b, 0x83, 0x7d,
+      0x1a, 0x45, 0xb2, 0xda, 0x22, 0x56, 0x63, 0x8c, 0xf7, 0x3e, 0x6c,
+      0x27, 0x74, 0x9d, 0xab, 0xcd, 0x13, 0x38, 0x5e, 0x42, 0xdf, 0x80,
+      0x60, 0xa4, 0x7b, 0x0b, 0xc6, 0xad, 0x91, 0xec, 0x3c, 0x69, 0xf5,
+      0x18, 0xe8, 0x6d, 0xb9, 0x82, 0x97, 0x2a, 0x51, 0x70};
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  VCLEAR(v5);
+  VCLEAR(v6);
+  VCLEAR(v7);
+  VCLEAR(v8);
+  stride = 2;
+  VSET(29, e8, m1);
+  asm volatile("vlsseg8e8.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U8(28, v1, 0x9f, 0x19, 0x8f, 0x05, 0xf9, 0x71, 0xc3, 0xbb, 0x31, 0x57,
+          0x83, 0x1a, 0xb2, 0x22, 0x63, 0xf7, 0x6c, 0x74, 0xab, 0x13, 0x5e,
+          0xdf, 0x60, 0x7b, 0xc6, 0x91, 0x3c, 0xf5, 0xe8);
+  VCMP_U8(29, v2, 0xe4, 0x20, 0x2e, 0xe0, 0xaa, 0xf0, 0x94, 0xd3, 0x4a, 0x6b,
+          0x7d, 0x45, 0xda, 0x56, 0x8c, 0x3e, 0x27, 0x9d, 0xcd, 0x38, 0x42,
+          0x80, 0xa4, 0x0b, 0xad, 0xec, 0x69, 0x18, 0x6d);
+  VCMP_U8(30, v3, 0x19, 0x8f, 0x05, 0xf9, 0x71, 0xc3, 0xbb, 0x31, 0x57, 0x83,
+          0x1a, 0xb2, 0x22, 0x63, 0xf7, 0x6c, 0x74, 0xab, 0x13, 0x5e, 0xdf,
+          0x60, 0x7b, 0xc6, 0x91, 0x3c, 0xf5, 0xe8, 0xb9);
+  VCMP_U8(31, v4, 0x20, 0x2e, 0xe0, 0xaa, 0xf0, 0x94, 0xd3, 0x4a, 0x6b, 0x7d,
+          0x45, 0xda, 0x56, 0x8c, 0x3e, 0x27, 0x9d, 0xcd, 0x38, 0x42, 0x80,
+          0xa4, 0x0b, 0xad, 0xec, 0x69, 0x18, 0x6d, 0x82);
+  VCMP_U8(32, v5, 0x8f, 0x05, 0xf9, 0x71, 0xc3, 0xbb, 0x31, 0x57, 0x83, 0x1a,
+          0xb2, 0x22, 0x63, 0xf7, 0x6c, 0x74, 0xab, 0x13, 0x5e, 0xdf, 0x60,
+          0x7b, 0xc6, 0x91, 0x3c, 0xf5, 0xe8, 0xb9, 0x97);
+  VCMP_U8(33, v6, 0x2e, 0xe0, 0xaa, 0xf0, 0x94, 0xd3, 0x4a, 0x6b, 0x7d, 0x45,
+          0xda, 0x56, 0x8c, 0x3e, 0x27, 0x9d, 0xcd, 0x38, 0x42, 0x80, 0xa4,
+          0x0b, 0xad, 0xec, 0x69, 0x18, 0x6d, 0x82, 0x2a);
+  VCMP_U8(34, v7, 0x05, 0xf9, 0x71, 0xc3, 0xbb, 0x31, 0x57, 0x83, 0x1a, 0xb2,
+          0x22, 0x63, 0xf7, 0x6c, 0x74, 0xab, 0x13, 0x5e, 0xdf, 0x60, 0x7b,
+          0xc6, 0x91, 0x3c, 0xf5, 0xe8, 0xb9, 0x97, 0x51);
+  VCMP_U8(35, v8, 0xe0, 0xaa, 0xf0, 0x94, 0xd3, 0x4a, 0x6b, 0x7d, 0x45, 0xda,
+          0x56, 0x8c, 0x3e, 0x27, 0x9d, 0xcd, 0x38, 0x42, 0x80, 0xa4, 0x0b,
+          0xad, 0xec, 0x69, 0x18, 0x6d, 0x82, 0x2a, 0x70);
+}
+
+// Segment-2
+void TEST_CASE1_16(void) {
+
+  VSET(-1, e16, m1);
+  volatile uint16_t INP1[] = {
+      0x1234, 0x5678, 0x9abc, 0xdef0, 0x1111, 0x2222, 0x3333, 0x4444,
+      0x5555, 0x6666, 0x7777, 0x8888, 0x9999, 0xaaaa, 0xbbbb, 0xcccc,
+      0xdddd, 0xeeee, 0xffff, 0x0101, 0x0202, 0x0303, 0x0404, 0x0505,
+      0x0606, 0x0707, 0x0808, 0x0909, 0x0a0a, 0x0b0b, 0x0c0c, 0x0d0d,
+      0x0e0e, 0x0f0f, 0x1010, 0x1111, 0x1212, 0x1313, 0x1414, 0x1515,
+      0x1616, 0x1717, 0x1818, 0x1919, 0x1a1a, 0x1b1b, 0x1c1c, 0x1d1d,
+      0x1e1e, 0x1f1f, 0x2020, 0x2121, 0x2222, 0x2323, 0x2424, 0x2525,
+      0x2626, 0x2727, 0x2828, 0x2929, 0x2a2a, 0x2b2b, 0x2c2c, 0x2d2d};
+
+  VCLEAR(v1);
+  VCLEAR(v2);
+  stride = 0;
+  VSET(5, e16, m1);
+  asm volatile("vlsseg2e16.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U16(36, v1, 0x1234, 0x1234, 0x1234, 0x1234, 0x1234);
+  VCMP_U16(37, v2, 0x5678, 0x5678, 0x5678, 0x5678, 0x5678);
+
+  VSET(-1, e16, m1);
+  VCLEAR(v1);
+  VCLEAR(v2);
+  stride = 4;
+  VSET(32, e16, m1);
+  asm volatile("vlsseg2e16.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U16(38, v1, 0x1234, 0x9abc, 0x1111, 0x3333, 0x5555, 0x7777, 0x9999,
+           0xbbbb, 0xdddd, 0xffff, 0x0202, 0x0404, 0x0606, 0x0808, 0x0a0a,
+           0x0c0c, 0x0e0e, 0x1010, 0x1212, 0x1414, 0x1616, 0x1818, 0x1a1a,
+           0x1c1c, 0x1e1e, 0x2020, 0x2222, 0x2424, 0x2626, 0x2828, 0x2a2a,
+           0x2c2c);
+  VCMP_U16(39, v2, 0x5678, 0xdef0, 0x2222, 0x4444, 0x6666, 0x8888, 0xaaaa,
+           0xcccc, 0xeeee, 0x0101, 0x0303, 0x0505, 0x0707, 0x0909, 0x0b0b,
+           0x0d0d, 0x0f0f, 0x1111, 0x1313, 0x1515, 0x1717, 0x1919, 0x1b1b,
+           0x1d1d, 0x1f1f, 0x2121, 0x2323, 0x2525, 0x2727, 0x2929, 0x2b2b,
+           0x2d2d);
+
+  VSET(-1, e16, m1);
+  VCLEAR(v1);
+  VCLEAR(v2);
+  stride = 6;
+  VSET(22, e16, m1);
+  asm volatile("vlsseg2e16.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U16(40, v1, 0x1234, 0xdef0, 0x3333, 0x6666, 0x9999, 0xcccc, 0xffff,
+           0x303, 0x606, 0x909, 0xc0c, 0xf0f, 0x1212, 0x1515, 0x1818, 0x1b1b,
+           0x1e1e, 0x2121, 0x2424, 0x2727, 0x2a2a, 0x2d2d);
+  VCMP_U16(41, v2, 0x5678, 0x1111, 0x4444, 0x7777, 0xaaaa, 0xdddd, 0x101, 0x404,
+           0x707, 0xa0a, 0xd0d, 0x1010, 0x1313, 0x1616, 0x1919, 0x1c1c, 0x1f1f,
+           0x2222, 0x2525, 0x2828, 0x2b2b);
+
+  VSET(-1, e16, m1);
+  VCLEAR(v1);
+  VCLEAR(v2);
+  stride = 8;
+  VSET(16, e16, m1);
+  asm volatile("vlsseg2e16.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U16(42, v1, 0x1234, 0x1111, 0x5555, 0x9999, 0xdddd, 0x0202, 0x0606,
+           0x0a0a, 0x0e0e, 0x1212, 0x1616, 0x1a1a, 0x1e1e, 0x2222, 0x2626,
+           0x2a2a);
+  VCMP_U16(43, v2, 0x5678, 0x2222, 0x6666, 0xaaaa, 0xeeee, 0x0303, 0x0707,
+           0x0b0b, 0x0f0f, 0x1313, 0x1717, 0x1b1b, 0x1f1f, 0x2323, 0x2727,
+           0x2b2b);
+}
+
+// Segment-3
+void TEST_CASE2_16(void) {
+  VSET(-1, e16, m1);
+  volatile uint16_t INP1[] = {
+      0x1234, 0x5678, 0x9abc, 0xdef0, 0x1111, 0x2222, 0x3333, 0x4444,
+      0x5555, 0x6666, 0x7777, 0x8888, 0x9999, 0xaaaa, 0xbbbb, 0xcccc,
+      0xdddd, 0xeeee, 0xffff, 0x0101, 0x0202, 0x0303, 0x0404, 0x0505,
+      0x0606, 0x0707, 0x0808, 0x0909, 0x0a0a, 0x0b0b, 0x0c0c, 0x0d0d,
+      0x0e0e, 0x0f0f, 0x1010, 0x1111, 0x1212, 0x1313, 0x1414, 0x1515,
+      0x1616, 0x1717, 0x1818, 0x1919, 0x1a1a, 0x1b1b, 0x1c1c, 0x1d1d,
+      0x1e1e, 0x1f1f, 0x2020, 0x2121, 0x2222, 0x2323, 0x2424, 0x2525,
+      0x2626, 0x2727, 0x2828, 0x2929, 0x2a2a, 0x2b2b, 0x2c2c, 0x2d2d};
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  stride = 4;
+  VSET(31, e16, m1);
+  asm volatile("vlsseg3e16.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U16(44, v1, 0x1234, 0x9abc, 0x1111, 0x3333, 0x5555, 0x7777, 0x9999,
+           0xbbbb, 0xdddd, 0xffff, 0x0202, 0x0404, 0x0606, 0x0808, 0x0a0a,
+           0x0c0c, 0x0e0e, 0x1010, 0x1212, 0x1414, 0x1616, 0x1818, 0x1a1a,
+           0x1c1c, 0x1e1e, 0x2020, 0x2222, 0x2424, 0x2626, 0x2828, 0x2a2a);
+  VCMP_U16(45, v2, 0x5678, 0xdef0, 0x2222, 0x4444, 0x6666, 0x8888, 0xaaaa,
+           0xcccc, 0xeeee, 0x0101, 0x0303, 0x0505, 0x0707, 0x0909, 0x0b0b,
+           0x0d0d, 0x0f0f, 0x1111, 0x1313, 0x1515, 0x1717, 0x1919, 0x1b1b,
+           0x1d1d, 0x1f1f, 0x2121, 0x2323, 0x2525, 0x2727, 0x2929, 0x2b2b,
+           0x2d2d);
+  VCMP_U16(46, v3, 0x9abc, 0x1111, 0x3333, 0x5555, 0x7777, 0x9999, 0xbbbb,
+           0xdddd, 0xffff, 0x0202, 0x0404, 0x0606, 0x0808, 0x0a0a, 0x0c0c,
+           0x0e0e, 0x1010, 0x1212, 0x1414, 0x1616, 0x1818, 0x1a1a, 0x1c1c,
+           0x1e1e, 0x2020, 0x2222, 0x2424, 0x2626, 0x2828, 0x2a2a, 0x2c2c);
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  stride = 6;
+  VSET(21, e16, m1);
+  asm volatile("vlsseg3e16.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U16(47, v1, 0x1234, 0xdef0, 0x3333, 0x6666, 0x9999, 0xcccc, 0xffff,
+           0x303, 0x606, 0x909, 0xc0c, 0xf0f, 0x1212, 0x1515, 0x1818, 0x1b1b,
+           0x1e1e, 0x2121, 0x2424, 0x2727, 0x2a2a);
+  VCMP_U16(48, v2, 0x5678, 0x1111, 0x4444, 0x7777, 0xaaaa, 0xdddd, 0x101, 0x404,
+           0x707, 0xa0a, 0xd0d, 0x1010, 0x1313, 0x1616, 0x1919, 0x1c1c, 0x1f1f,
+           0x2222, 0x2525, 0x2828, 0x2b2b);
+  VCMP_U16(49, v3, 0x9abc, 0x2222, 0x5555, 0x8888, 0xbbbb, 0xeeee, 0x202, 0x505,
+           0x808, 0xb0b, 0xe0e, 0x1111, 0x1414, 0x1717, 0x1a1a, 0x1d1d, 0x2020,
+           0x2323, 0x2626, 0x2929, 0x2c2c);
+
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  stride = 8;
+  VSET(16, e16, m1);
+  asm volatile("vlsseg3e16.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U16(50, v1, 0x1234, 0x1111, 0x5555, 0x9999, 0xdddd, 0x202, 0x606, 0xa0a,
+           0xe0e, 0x1212, 0x1616, 0x1a1a, 0x1e1e, 0x2222, 0x2626, 0x2a2a);
+  VCMP_U16(51, v2, 0x5678, 0x2222, 0x6666, 0xaaaa, 0xeeee, 0x303, 0x707, 0xb0b,
+           0xf0f, 0x1313, 0x1717, 0x1b1b, 0x1f1f, 0x2323, 0x2727, 0x2b2b);
+  VCMP_U16(52, v3, 0x9abc, 0x3333, 0x7777, 0xbbbb, 0xffff, 0x404, 0x808, 0xc0c,
+           0x1010, 0x1414, 0x1818, 0x1c1c, 0x2020, 0x2424, 0x2828, 0x2c2c);
+}
+
+// Segment-4
+void TEST_CASE3_16(void) {
+  VSET(-1, e16, m1);
+  volatile uint16_t INP1[] = {
+      0x1234, 0x5678, 0x9abc, 0xdef0, 0x1111, 0x2222, 0x3333, 0x4444,
+      0x5555, 0x6666, 0x7777, 0x8888, 0x9999, 0xaaaa, 0xbbbb, 0xcccc,
+      0xdddd, 0xeeee, 0xffff, 0x0101, 0x0202, 0x0303, 0x0404, 0x0505,
+      0x0606, 0x0707, 0x0808, 0x0909, 0x0a0a, 0x0b0b, 0x0c0c, 0x0d0d,
+      0x0e0e, 0x0f0f, 0x1010, 0x1111, 0x1212, 0x1313, 0x1414, 0x1515,
+      0x1616, 0x1717, 0x1818, 0x1919, 0x1a1a, 0x1b1b, 0x1c1c, 0x1d1d,
+      0x1e1e, 0x1f1f, 0x2020, 0x2121, 0x2222, 0x2323, 0x2424, 0x2525,
+      0x2626, 0x2727, 0x2828, 0x2929, 0x2a2a, 0x2b2b, 0x2c2c, 0x2d2d};
+
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  stride = 4;
+  VSET(32, e16, m1);
+  asm volatile("vlsseg4e16.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U16(53, v1, 0x1234, 0x9abc, 0x1111, 0x3333, 0x5555, 0x7777, 0x9999,
+           0xbbbb, 0xdddd, 0xffff, 0x202, 0x404, 0x606, 0x808, 0xa0a, 0xc0c,
+           0xe0e, 0x1010, 0x1212, 0x1414, 0x1616, 0x1818, 0x1a1a, 0x1c1c,
+           0x1e1e, 0x2020, 0x2222, 0x2424, 0x2626, 0x2828, 0x2a2a, 0x2c2c);
+  VCMP_U16(54, v2, 0x5678, 0xdef0, 0x2222, 0x4444, 0x6666, 0x8888, 0xaaaa,
+           0xcccc, 0xeeee, 0x101, 0x303, 0x505, 0x707, 0x909, 0xb0b, 0xd0d,
+           0xf0f, 0x1111, 0x1313, 0x1515, 0x1717, 0x1919, 0x1b1b, 0x1d1d,
+           0x1f1f, 0x2121, 0x2323, 0x2525, 0x2727, 0x2929, 0x2b2b, 0x2d2d);
+  VCMP_U16(55, v3, 0x9abc, 0x1111, 0x3333, 0x5555, 0x7777, 0x9999, 0xbbbb,
+           0xdddd, 0xffff, 0x202, 0x404, 0x606, 0x808, 0xa0a, 0xc0c, 0xe0e,
+           0x1010, 0x1212, 0x1414, 0x1616, 0x1818, 0x1a1a, 0x1c1c, 0x1e1e,
+           0x2020, 0x2222, 0x2424, 0x2626, 0x2828, 0x2a2a, 0x2c2c);
+  VCMP_U16(56, v4, 0xdef0, 0x2222, 0x4444, 0x6666, 0x8888, 0xaaaa, 0xcccc,
+           0xeeee, 0x101, 0x303, 0x505, 0x707, 0x909, 0xb0b, 0xd0d, 0xf0f,
+           0x1111, 0x1313, 0x1515, 0x1717, 0x1919, 0x1b1b, 0x1d1d, 0x1f1f,
+           0x2121, 0x2323, 0x2525, 0x2727, 0x2929, 0x2b2b, 0x2d2d);
+
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  stride = 6;
+  VSET(22, e16, m1);
+  asm volatile("vlsseg4e16.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U16(57, v1, 0x1234, 0xdef0, 0x3333, 0x6666, 0x9999, 0xcccc, 0xffff,
+           0x303, 0x606, 0x909, 0xc0c, 0xf0f, 0x1212, 0x1515, 0x1818, 0x1b1b,
+           0x1e1e, 0x2121, 0x2424, 0x2727, 0x2a2a, 0x2d2d);
+  VCMP_U16(58, v2, 0x5678, 0x1111, 0x4444, 0x7777, 0xaaaa, 0xdddd, 0x101, 0x404,
+           0x707, 0xa0a, 0xd0d, 0x1010, 0x1313, 0x1616, 0x1919, 0x1c1c, 0x1f1f,
+           0x2222, 0x2525, 0x2828, 0x2b2b);
+  VCMP_U16(59, v3, 0x9abc, 0x2222, 0x5555, 0x8888, 0xbbbb, 0xeeee, 0x202, 0x505,
+           0x808, 0xb0b, 0xe0e, 0x1111, 0x1414, 0x1717, 0x1a1a, 0x1d1d, 0x2020,
+           0x2323, 0x2626, 0x2929, 0x2c2c);
+  VCMP_U16(60, v4, 0xdef0, 0x3333, 0x6666, 0x9999, 0xcccc, 0xffff, 0x303, 0x606,
+           0x909, 0xc0c, 0xf0f, 0x1212, 0x1515, 0x1818, 0x1b1b, 0x1e1e, 0x2121,
+           0x2424, 0x2727, 0x2a2a, 0x2d2d);
+
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  stride = 8;
+  VSET(16, e16, m1);
+  asm volatile("vlsseg4e16.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U16(61, v1, 0x1234, 0x1111, 0x5555, 0x9999, 0xdddd, 0x202, 0x606, 0xa0a,
+           0xe0e, 0x1212, 0x1616, 0x1a1a, 0x1e1e, 0x2222, 0x2626, 0x2a2a);
+  VCMP_U16(62, v2, 0x5678, 0x2222, 0x6666, 0xaaaa, 0xeeee, 0x303, 0x707, 0xb0b,
+           0xf0f, 0x1313, 0x1717, 0x1b1b, 0x1f1f, 0x2323, 0x2727, 0x2b2b);
+  VCMP_U16(63, v3, 0x9abc, 0x3333, 0x7777, 0xbbbb, 0xffff, 0x404, 0x808, 0xc0c,
+           0x1010, 0x1414, 0x1818, 0x1c1c, 0x2020, 0x2424, 0x2828, 0x2c2c);
+  VCMP_U16(64, v4, 0xdef0, 0x4444, 0x8888, 0xcccc, 0x101, 0x505, 0x909, 0xd0d,
+           0x1111, 0x1515, 0x1919, 0x1d1d, 0x2121, 0x2525, 0x2929, 0x2d2d);
+}
+
+// Segment-8
+void TEST_CASE4_16(void) {
+  VSET(-1, e16, m1);
+  volatile uint16_t INP1[] = {
+      0x1234, 0x5678, 0x9abc, 0xdef0, 0x1111, 0x2222, 0x3333, 0x4444,
+      0x5555, 0x6666, 0x7777, 0x8888, 0x9999, 0xaaaa, 0xbbbb, 0xcccc,
+      0xdddd, 0xeeee, 0xffff, 0x0101, 0x0202, 0x0303, 0x0404, 0x0505,
+      0x0606, 0x0707, 0x0808, 0x0909, 0x0a0a, 0x0b0b, 0x0c0c, 0x0d0d,
+      0x0e0e, 0x0f0f, 0x1010, 0x1111, 0x1212, 0x1313, 0x1414, 0x1515,
+      0x1616, 0x1717, 0x1818, 0x1919, 0x1a1a, 0x1b1b, 0x1c1c, 0x1d1d,
+      0x1e1e, 0x1f1f, 0x2020, 0x2121, 0x2222, 0x2323, 0x2424, 0x2525,
+      0x2626, 0x2727, 0x2828, 0x2929, 0x2a2a, 0x2b2b, 0x2c2c, 0x2d2d};
+
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  VCLEAR(v5);
+  VCLEAR(v6);
+  VCLEAR(v7);
+  VCLEAR(v8);
+  stride = 4;
+  VSET(32, e16, m1);
+  asm volatile("vlsseg8e16.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U16(65, v1, 0x1234, 0x9abc, 0x1111, 0x3333, 0x5555, 0x7777, 0x9999,
+           0xbbbb, 0xdddd, 0xffff, 0x202, 0x404, 0x606, 0x808, 0xa0a, 0xc0c,
+           0xe0e, 0x1010, 0x1212, 0x1414, 0x1616, 0x1818, 0x1a1a, 0x1c1c,
+           0x1e1e, 0x2020, 0x2222, 0x2424, 0x2626, 0x2828, 0x2a2a, 0x2c2c);
+  VCMP_U16(66, v2, 0x5678, 0xdef0, 0x2222, 0x4444, 0x6666, 0x8888, 0xaaaa,
+           0xcccc, 0xeeee, 0x101, 0x303, 0x505, 0x707, 0x909, 0xb0b, 0xd0d,
+           0xf0f, 0x1111, 0x1313, 0x1515, 0x1717, 0x1919, 0x1b1b, 0x1d1d,
+           0x1f1f, 0x2121, 0x2323, 0x2525, 0x2727, 0x2929, 0x2b2b, 0x2d2d);
+  VCMP_U16(67, v3, 0x9abc, 0x1111, 0x3333, 0x5555, 0x7777, 0x9999, 0xbbbb,
+           0xdddd, 0xffff, 0x202, 0x404, 0x606, 0x808, 0xa0a, 0xc0c, 0xe0e,
+           0x1010, 0x1212, 0x1414, 0x1616, 0x1818, 0x1a1a, 0x1c1c, 0x1e1e,
+           0x2020, 0x2222, 0x2424, 0x2626, 0x2828, 0x2a2a, 0x2c2c);
+  VCMP_U16(68, v4, 0xdef0, 0x2222, 0x4444, 0x6666, 0x8888, 0xaaaa, 0xcccc,
+           0xeeee, 0x101, 0x303, 0x505, 0x707, 0x909, 0xb0b, 0xd0d, 0xf0f,
+           0x1111, 0x1313, 0x1515, 0x1717, 0x1919, 0x1b1b, 0x1d1d, 0x1f1f,
+           0x2121, 0x2323, 0x2525, 0x2727, 0x2929, 0x2b2b, 0x2d2d);
+  VCMP_U16(69, v5, 0x1111, 0x3333, 0x5555, 0x7777, 0x9999, 0xbbbb, 0xdddd,
+           0xffff, 0x202, 0x404, 0x606, 0x808, 0xa0a, 0xc0c, 0xe0e, 0x1010,
+           0x1212, 0x1414, 0x1616, 0x1818, 0x1a1a, 0x1c1c, 0x1e1e, 0x2020,
+           0x2222, 0x2424, 0x2626, 0x2828, 0x2a2a, 0x2c2c);
+  VCMP_U16(70, v6, 0x2222, 0x4444, 0x6666, 0x8888, 0xaaaa, 0xcccc, 0xeeee,
+           0x101, 0x303, 0x505, 0x707, 0x909, 0xb0b, 0xd0d, 0xf0f, 0x1111,
+           0x1313, 0x1515, 0x1717, 0x1919, 0x1b1b, 0x1d1d, 0x1f1f, 0x2121,
+           0x2323, 0x2525, 0x2727, 0x2929, 0x2b2b, 0x2d2d);
+  VCMP_U16(71, v7, 0x3333, 0x5555, 0x7777, 0x9999, 0xbbbb, 0xdddd, 0xffff,
+           0x202, 0x404, 0x606, 0x808, 0xa0a, 0xc0c, 0xe0e, 0x1010, 0x1212,
+           0x1414, 0x1616, 0x1818, 0x1a1a, 0x1c1c, 0x1e1e, 0x2020, 0x2222,
+           0x2424, 0x2626, 0x2828, 0x2a2a, 0x2c2c);
+  VCMP_U16(72, v8, 0x4444, 0x6666, 0x8888, 0xaaaa, 0xcccc, 0xeeee, 0x101, 0x303,
+           0x505, 0x707, 0x909, 0xb0b, 0xd0d, 0xf0f, 0x1111, 0x1313, 0x1515,
+           0x1717, 0x1919, 0x1b1b, 0x1d1d, 0x1f1f, 0x2121, 0x2323, 0x2525,
+           0x2727, 0x2929, 0x2b2b, 0x2d2d);
+
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  VCLEAR(v5);
+  VCLEAR(v6);
+  VCLEAR(v7);
+  VCLEAR(v8);
+  stride = 6;
+  VSET(22, e16, m1);
+  asm volatile("vlsseg8e16.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U16(73, v1, 0x1234, 0xdef0, 0x3333, 0x6666, 0x9999, 0xcccc, 0xffff,
+           0x303, 0x606, 0x909, 0xc0c, 0xf0f, 0x1212, 0x1515, 0x1818, 0x1b1b,
+           0x1e1e, 0x2121, 0x2424, 0x2727, 0x2a2a, 0x2d2d);
+  VCMP_U16(74, v2, 0x5678, 0x1111, 0x4444, 0x7777, 0xaaaa, 0xdddd, 0x101, 0x404,
+           0x707, 0xa0a, 0xd0d, 0x1010, 0x1313, 0x1616, 0x1919, 0x1c1c, 0x1f1f,
+           0x2222, 0x2525, 0x2828, 0x2b2b);
+  VCMP_U16(75, v3, 0x9abc, 0x2222, 0x5555, 0x8888, 0xbbbb, 0xeeee, 0x202, 0x505,
+           0x808, 0xb0b, 0xe0e, 0x1111, 0x1414, 0x1717, 0x1a1a, 0x1d1d, 0x2020,
+           0x2323, 0x2626, 0x2929, 0x2c2c);
+  VCMP_U16(76, v4, 0xdef0, 0x3333, 0x6666, 0x9999, 0xcccc, 0xffff, 0x303, 0x606,
+           0x909, 0xc0c, 0xf0f, 0x1212, 0x1515, 0x1818, 0x1b1b, 0x1e1e, 0x2121,
+           0x2424, 0x2727, 0x2a2a, 0x2d2d);
+  VCMP_U16(77, v5, 0x1111, 0x4444, 0x7777, 0xaaaa, 0xdddd, 0x101, 0x404, 0x707,
+           0xa0a, 0xd0d, 0x1010, 0x1313, 0x1616, 0x1919, 0x1c1c, 0x1f1f, 0x2222,
+           0x2525, 0x2828, 0x2b2b);
+  VCMP_U16(78, v6, 0x2222, 0x5555, 0x8888, 0xbbbb, 0xeeee, 0x202, 0x505, 0x808,
+           0xb0b, 0xe0e, 0x1111, 0x1414, 0x1717, 0x1a1a, 0x1d1d, 0x2020, 0x2323,
+           0x2626, 0x2929, 0x2c2c);
+  VCMP_U16(79, v7, 0x3333, 0x6666, 0x9999, 0xcccc, 0xffff, 0x303, 0x606, 0x909,
+           0xc0c, 0xf0f, 0x1212, 0x1515, 0x1818, 0x1b1b, 0x1e1e, 0x2121, 0x2424,
+           0x2727, 0x2a2a, 0x2d2d);
+  VCMP_U16(80, v8, 0x4444, 0x7777, 0xaaaa, 0xdddd, 0x101, 0x404, 0x707, 0xa0a,
+           0xd0d, 0x1010, 0x1313, 0x1616, 0x1919, 0x1c1c, 0x1f1f, 0x2222,
+           0x2525, 0x2828, 0x2b2b);
+
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  VCLEAR(v5);
+  VCLEAR(v6);
+  VCLEAR(v7);
+  VCLEAR(v8);
+  stride = 8;
+  VSET(16, e16, m1);
+  asm volatile("vlsseg8e16.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U16(81, v1, 0x1234, 0x1111, 0x5555, 0x9999, 0xdddd, 0x202, 0x606, 0xa0a,
+           0xe0e, 0x1212, 0x1616, 0x1a1a, 0x1e1e, 0x2222, 0x2626, 0x2a2a);
+  VCMP_U16(82, v2, 0x5678, 0x2222, 0x6666, 0xaaaa, 0xeeee, 0x303, 0x707, 0xb0b,
+           0xf0f, 0x1313, 0x1717, 0x1b1b, 0x1f1f, 0x2323, 0x2727, 0x2b2b);
+  VCMP_U16(83, v3, 0x9abc, 0x3333, 0x7777, 0xbbbb, 0xffff, 0x404, 0x808, 0xc0c,
+           0x1010, 0x1414, 0x1818, 0x1c1c, 0x2020, 0x2424, 0x2828, 0x2c2c);
+  VCMP_U16(84, v4, 0xdef0, 0x4444, 0x8888, 0xcccc, 0x101, 0x505, 0x909, 0xd0d,
+           0x1111, 0x1515, 0x1919, 0x1d1d, 0x2121, 0x2525, 0x2929, 0x2d2d);
+  VCMP_U16(85, v5, 0x1111, 0x5555, 0x9999, 0xdddd, 0x202, 0x606, 0xa0a, 0xe0e,
+           0x1212, 0x1616, 0x1a1a, 0x1e1e, 0x2222, 0x2626, 0x2a2a);
+  VCMP_U16(86, v6, 0x2222, 0x6666, 0xaaaa, 0xeeee, 0x303, 0x707, 0xb0b, 0xf0f,
+           0x1313, 0x1717, 0x1b1b, 0x1f1f, 0x2323, 0x2727, 0x2b2b);
+  VCMP_U16(87, v7, 0x3333, 0x7777, 0xbbbb, 0xffff, 0x404, 0x808, 0xc0c, 0x1010,
+           0x1414, 0x1818, 0x1c1c, 0x2020, 0x2424, 0x2828, 0x2c2c);
+  VCMP_U16(88, v8, 0x4444, 0x8888, 0xcccc, 0x101, 0x505, 0x909, 0xd0d, 0x1111,
+           0x1515, 0x1919, 0x1d1d, 0x2121, 0x2525, 0x2929, 0x2d2d);
+}
+
+// Segment-2
+void TEST_CASE1_32(void) {
+
+  VSET(-1, e32, m1);
+  volatile uint32_t INP1[] = {
+      0xe19afa6b, 0x8c10145c, 0xbca44cc5, 0x11ffa54e, 0x82f92af6, 0x9af29daa,
+      0x956eb527, 0x575c2e05, 0x68fb4cc5, 0xcf7a1d98, 0x53a0be4e, 0x26439a12,
+      0x785cc853, 0x35659121, 0xf7a96b8c, 0xa87678a2, 0xb11d757e, 0x67dd4037,
+      0xd29ad01e, 0xb7600abf, 0x2e572002, 0xaadc6195, 0xcefce71b, 0x64d90d0c,
+      0x6c3b54b0, 0xcc6da682, 0xd8b7ae76, 0x8533b185, 0xa2cd798c, 0x2a4339cc,
+      0xcf9238fb, 0x7e70281b, 0xdf162ee9, 0x4f2ea60f, 0x4b32bcdd, 0xbf3b8546,
+      0x52b26ff5, 0x18cbcecd, 0xc364c8f8, 0x5bf0c67b, 0x60914005, 0x93265d9d,
+      0xcff3c77d, 0x788529c3, 0xdda63ceb, 0x4edd7f48, 0xddcd4d07, 0x3266d631,
+      0x3b2f25a6, 0x7bfd8a81, 0x9db64ef5, 0xa06a42d4, 0x687f8a39, 0xb9272633,
+      0xb009319e, 0xf542d689, 0x45ef05c9, 0xf547c96e, 0x2a143e76, 0x17a38eec,
+      0x9a73626c, 0xca064493, 0x582140dd, 0x97df3c7a};
+
+  VCLEAR(v1);
+  VCLEAR(v2);
+  stride = 0;
+  VSET(5, e32, m1);
+  asm volatile("vlsseg2e32.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U32(89, v1, 0xe19afa6b, 0xe19afa6b, 0xe19afa6b, 0xe19afa6b, 0xe19afa6b);
+  VCMP_U32(90, v2, 0x8c10145c, 0x8c10145c, 0x8c10145c, 0x8c10145c, 0x8c10145c);
+
+  VSET(-1, e32, m1);
+  VCLEAR(v1);
+  VCLEAR(v2);
+  stride = 8;
+  VSET(32, e32, m1);
+  asm volatile("vlsseg2e32.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U32(91, v1, 0xe19afa6b, 0xbca44cc5, 0x82f92af6, 0x956eb527, 0x68fb4cc5,
+           0x53a0be4e, 0x785cc853, 0xf7a96b8c, 0xb11d757e, 0xd29ad01e,
+           0x2e572002, 0xcefce71b, 0x6c3b54b0, 0xd8b7ae76, 0xa2cd798c,
+           0xcf9238fb, 0xdf162ee9, 0x4b32bcdd, 0x52b26ff5, 0xc364c8f8,
+           0x60914005, 0xcff3c77d, 0xdda63ceb, 0xddcd4d07, 0x3b2f25a6,
+           0x9db64ef5, 0x687f8a39, 0xb009319e, 0x45ef05c9, 0x2a143e76,
+           0x9a73626c, 0x582140dd);
+  VCMP_U32(92, v2, 0x8c10145c, 0x11ffa54e, 0x9af29daa, 0x575c2e05, 0xcf7a1d98,
+           0x26439a12, 0x35659121, 0xa87678a2, 0x67dd4037, 0xb7600abf,
+           0xaadc6195, 0x64d90d0c, 0xcc6da682, 0x8533b185, 0x2a4339cc,
+           0x7e70281b, 0x4f2ea60f, 0xbf3b8546, 0x18cbcecd, 0x5bf0c67b,
+           0x93265d9d, 0x788529c3, 0x4edd7f48, 0x3266d631, 0x7bfd8a81,
+           0xa06a42d4, 0xb9272633, 0xf542d689, 0xf547c96e, 0x17a38eec,
+           0xca064493, 0x97df3c7a);
+
+  VSET(-1, e32, m1);
+  VCLEAR(v1);
+  VCLEAR(v2);
+  stride = 12;
+  VSET(22, e32, m1);
+  asm volatile("vlsseg2e32.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U32(93, v1, 0xe19afa6b, 0x11ffa54e, 0x956eb527, 0xcf7a1d98, 0x785cc853,
+           0xa87678a2, 0xd29ad01e, 0xaadc6195, 0x6c3b54b0, 0x8533b185,
+           0xcf9238fb, 0x4f2ea60f, 0x52b26ff5, 0x5bf0c67b, 0xcff3c77d,
+           0x4edd7f48, 0x3b2f25a6, 0xa06a42d4, 0xb009319e, 0xf547c96e,
+           0x9a73626c, 0x97df3c7a);
+  VCMP_U32(94, v2, 0x8c10145c, 0x82f92af6, 0x575c2e05, 0x53a0be4e, 0x35659121,
+           0xb11d757e, 0xb7600abf, 0xcefce71b, 0xcc6da682, 0xa2cd798c,
+           0x7e70281b, 0x4b32bcdd, 0x18cbcecd, 0x60914005, 0x788529c3,
+           0xddcd4d07, 0x7bfd8a81, 0x687f8a39, 0xf542d689, 0x2a143e76,
+           0xca064493);
+
+  VSET(-1, e32, m1);
+  VCLEAR(v1);
+  VCLEAR(v2);
+  stride = 16;
+  VSET(16, e32, m1);
+  asm volatile("vlsseg2e32.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U32(95, v1, 0xe19afa6b, 0x82f92af6, 0x68fb4cc5, 0x785cc853, 0xb11d757e,
+           0x2e572002, 0x6c3b54b0, 0xa2cd798c, 0xdf162ee9, 0x52b26ff5,
+           0x60914005, 0xdda63ceb, 0x3b2f25a6, 0x687f8a39, 0x45ef05c9,
+           0x9a73626c);
+  VCMP_U32(96, v2, 0x8c10145c, 0x9af29daa, 0xcf7a1d98, 0x35659121, 0x67dd4037,
+           0xaadc6195, 0xcc6da682, 0x2a4339cc, 0x4f2ea60f, 0x18cbcecd,
+           0x93265d9d, 0x4edd7f48, 0x7bfd8a81, 0xb9272633, 0xf547c96e,
+           0xca064493);
+}
+
+// Segment-3
+void TEST_CASE2_32(void) {
+  VSET(-1, e32, m1);
+  volatile uint32_t INP1[] = {
+      0xe19afa6b, 0x8c10145c, 0xbca44cc5, 0x11ffa54e, 0x82f92af6, 0x9af29daa,
+      0x956eb527, 0x575c2e05, 0x68fb4cc5, 0xcf7a1d98, 0x53a0be4e, 0x26439a12,
+      0x785cc853, 0x35659121, 0xf7a96b8c, 0xa87678a2, 0xb11d757e, 0x67dd4037,
+      0xd29ad01e, 0xb7600abf, 0x2e572002, 0xaadc6195, 0xcefce71b, 0x64d90d0c,
+      0x6c3b54b0, 0xcc6da682, 0xd8b7ae76, 0x8533b185, 0xa2cd798c, 0x2a4339cc,
+      0xcf9238fb, 0x7e70281b, 0xdf162ee9, 0x4f2ea60f, 0x4b32bcdd, 0xbf3b8546,
+      0x52b26ff5, 0x18cbcecd, 0xc364c8f8, 0x5bf0c67b, 0x60914005, 0x93265d9d,
+      0xcff3c77d, 0x788529c3, 0xdda63ceb, 0x4edd7f48, 0xddcd4d07, 0x3266d631,
+      0x3b2f25a6, 0x7bfd8a81, 0x9db64ef5, 0xa06a42d4, 0x687f8a39, 0xb9272633,
+      0xb009319e, 0xf542d689, 0x45ef05c9, 0xf547c96e, 0x2a143e76, 0x17a38eec,
+      0x9a73626c, 0xca064493, 0x582140dd, 0x97df3c7a};
+
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  stride = 8;
+  VSET(32, e32, m1);
+  asm volatile("vlsseg3e32.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U32(97, v1, 0xe19afa6b, 0xbca44cc5, 0x82f92af6, 0x956eb527, 0x68fb4cc5,
+           0x53a0be4e, 0x785cc853, 0xf7a96b8c, 0xb11d757e, 0xd29ad01e,
+           0x2e572002, 0xcefce71b, 0x6c3b54b0, 0xd8b7ae76, 0xa2cd798c,
+           0xcf9238fb, 0xdf162ee9, 0x4b32bcdd, 0x52b26ff5, 0xc364c8f8,
+           0x60914005, 0xcff3c77d, 0xdda63ceb, 0xddcd4d07, 0x3b2f25a6,
+           0x9db64ef5, 0x687f8a39, 0xb009319e, 0x45ef05c9, 0x2a143e76,
+           0x9a73626c, 0x582140dd);
+  VCMP_U32(98, v2, 0x8c10145c, 0x11ffa54e, 0x9af29daa, 0x575c2e05, 0xcf7a1d98,
+           0x26439a12, 0x35659121, 0xa87678a2, 0x67dd4037, 0xb7600abf,
+           0xaadc6195, 0x64d90d0c, 0xcc6da682, 0x8533b185, 0x2a4339cc,
+           0x7e70281b, 0x4f2ea60f, 0xbf3b8546, 0x18cbcecd, 0x5bf0c67b,
+           0x93265d9d, 0x788529c3, 0x4edd7f48, 0x3266d631, 0x7bfd8a81,
+           0xa06a42d4, 0xb9272633, 0xf542d689, 0xf547c96e, 0x17a38eec,
+           0xca064493, 0x97df3c7a);
+  VCMP_U32(99, v3, 0xbca44cc5, 0x82f92af6, 0x956eb527, 0x68fb4cc5, 0x53a0be4e,
+           0x785cc853, 0xf7a96b8c, 0xb11d757e, 0xd29ad01e, 0x2e572002,
+           0xcefce71b, 0x6c3b54b0, 0xd8b7ae76, 0xa2cd798c, 0xcf9238fb,
+           0xdf162ee9, 0x4b32bcdd, 0x52b26ff5, 0xc364c8f8, 0x60914005,
+           0xcff3c77d, 0xdda63ceb, 0xddcd4d07, 0x3b2f25a6, 0x9db64ef5,
+           0x687f8a39, 0xb009319e, 0x45ef05c9, 0x2a143e76, 0x9a73626c,
+           0x582140dd);
+
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  stride = 12;
+  VSET(22, e32, m1);
+  asm volatile("vlsseg3e32.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U32(100, v1, 0xe19afa6b, 0x11ffa54e, 0x956eb527, 0xcf7a1d98, 0x785cc853,
+           0xa87678a2, 0xd29ad01e, 0xaadc6195, 0x6c3b54b0, 0x8533b185,
+           0xcf9238fb, 0x4f2ea60f, 0x52b26ff5, 0x5bf0c67b, 0xcff3c77d,
+           0x4edd7f48, 0x3b2f25a6, 0xa06a42d4, 0xb009319e, 0xf547c96e,
+           0x9a73626c, 0x97df3c7a);
+  VCMP_U32(101, v2, 0x8c10145c, 0x82f92af6, 0x575c2e05, 0x53a0be4e, 0x35659121,
+           0xb11d757e, 0xb7600abf, 0xcefce71b, 0xcc6da682, 0xa2cd798c,
+           0x7e70281b, 0x4b32bcdd, 0x18cbcecd, 0x60914005, 0x788529c3,
+           0xddcd4d07, 0x7bfd8a81, 0x687f8a39, 0xf542d689, 0x2a143e76,
+           0xca064493);
+  VCMP_U32(102, v3, 0xbca44cc5, 0x9af29daa, 0x68fb4cc5, 0x26439a12, 0xf7a96b8c,
+           0x67dd4037, 0x2e572002, 0x64d90d0c, 0xd8b7ae76, 0x2a4339cc,
+           0xdf162ee9, 0xbf3b8546, 0xc364c8f8, 0x93265d9d, 0xdda63ceb,
+           0x3266d631, 0x9db64ef5, 0xb9272633, 0x45ef05c9, 0x17a38eec,
+           0x582140dd);
+
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  stride = 16;
+  VSET(16, e32, m1);
+  asm volatile("vlsseg3e32.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U32(103, v1, 0xe19afa6b, 0x82f92af6, 0x68fb4cc5, 0x785cc853, 0xb11d757e,
+           0x2e572002, 0x6c3b54b0, 0xa2cd798c, 0xdf162ee9, 0x52b26ff5,
+           0x60914005, 0xdda63ceb, 0x3b2f25a6, 0x687f8a39, 0x45ef05c9,
+           0x9a73626c);
+  VCMP_U32(104, v2, 0x8c10145c, 0x9af29daa, 0xcf7a1d98, 0x35659121, 0x67dd4037,
+           0xaadc6195, 0xcc6da682, 0x2a4339cc, 0x4f2ea60f, 0x18cbcecd,
+           0x93265d9d, 0x4edd7f48, 0x7bfd8a81, 0xb9272633, 0xf547c96e,
+           0xca064493);
+  VCMP_U32(105, v3, 0xbca44cc5, 0x956eb527, 0x53a0be4e, 0xf7a96b8c, 0xd29ad01e,
+           0xcefce71b, 0xd8b7ae76, 0xcf9238fb, 0x4b32bcdd, 0xc364c8f8,
+           0xcff3c77d, 0xddcd4d07, 0x9db64ef5, 0xb009319e, 0x2a143e76,
+           0x582140dd);
+}
+
+// Segment-4
+void TEST_CASE3_32(void) {
+  VSET(-1, e32, m1);
+  volatile uint32_t INP1[] = {
+      0xe19afa6b, 0x8c10145c, 0xbca44cc5, 0x11ffa54e, 0x82f92af6, 0x9af29daa,
+      0x956eb527, 0x575c2e05, 0x68fb4cc5, 0xcf7a1d98, 0x53a0be4e, 0x26439a12,
+      0x785cc853, 0x35659121, 0xf7a96b8c, 0xa87678a2, 0xb11d757e, 0x67dd4037,
+      0xd29ad01e, 0xb7600abf, 0x2e572002, 0xaadc6195, 0xcefce71b, 0x64d90d0c,
+      0x6c3b54b0, 0xcc6da682, 0xd8b7ae76, 0x8533b185, 0xa2cd798c, 0x2a4339cc,
+      0xcf9238fb, 0x7e70281b, 0xdf162ee9, 0x4f2ea60f, 0x4b32bcdd, 0xbf3b8546,
+      0x52b26ff5, 0x18cbcecd, 0xc364c8f8, 0x5bf0c67b, 0x60914005, 0x93265d9d,
+      0xcff3c77d, 0x788529c3, 0xdda63ceb, 0x4edd7f48, 0xddcd4d07, 0x3266d631,
+      0x3b2f25a6, 0x7bfd8a81, 0x9db64ef5, 0xa06a42d4, 0x687f8a39, 0xb9272633,
+      0xb009319e, 0xf542d689, 0x45ef05c9, 0xf547c96e, 0x2a143e76, 0x17a38eec,
+      0x9a73626c, 0xca064493, 0x582140dd, 0x97df3c7a};
+
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  stride = 8;
+  VSET(32, e32, m1);
+  asm volatile("vlsseg4e32.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U32(106, v1, 0xe19afa6b, 0xbca44cc5, 0x82f92af6, 0x956eb527, 0x68fb4cc5,
+           0x53a0be4e, 0x785cc853, 0xf7a96b8c, 0xb11d757e, 0xd29ad01e,
+           0x2e572002, 0xcefce71b, 0x6c3b54b0, 0xd8b7ae76, 0xa2cd798c,
+           0xcf9238fb, 0xdf162ee9, 0x4b32bcdd, 0x52b26ff5, 0xc364c8f8,
+           0x60914005, 0xcff3c77d, 0xdda63ceb, 0xddcd4d07, 0x3b2f25a6,
+           0x9db64ef5, 0x687f8a39, 0xb009319e, 0x45ef05c9, 0x2a143e76,
+           0x9a73626c, 0x582140dd);
+  VCMP_U32(107, v2, 0x8c10145c, 0x11ffa54e, 0x9af29daa, 0x575c2e05, 0xcf7a1d98,
+           0x26439a12, 0x35659121, 0xa87678a2, 0x67dd4037, 0xb7600abf,
+           0xaadc6195, 0x64d90d0c, 0xcc6da682, 0x8533b185, 0x2a4339cc,
+           0x7e70281b, 0x4f2ea60f, 0xbf3b8546, 0x18cbcecd, 0x5bf0c67b,
+           0x93265d9d, 0x788529c3, 0x4edd7f48, 0x3266d631, 0x7bfd8a81,
+           0xa06a42d4, 0xb9272633, 0xf542d689, 0xf547c96e, 0x17a38eec,
+           0xca064493, 0x97df3c7a);
+  VCMP_U32(108, v3, 0xbca44cc5, 0x82f92af6, 0x956eb527, 0x68fb4cc5, 0x53a0be4e,
+           0x785cc853, 0xf7a96b8c, 0xb11d757e, 0xd29ad01e, 0x2e572002,
+           0xcefce71b, 0x6c3b54b0, 0xd8b7ae76, 0xa2cd798c, 0xcf9238fb,
+           0xdf162ee9, 0x4b32bcdd, 0x52b26ff5, 0xc364c8f8, 0x60914005,
+           0xcff3c77d, 0xdda63ceb, 0xddcd4d07, 0x3b2f25a6, 0x9db64ef5,
+           0x687f8a39, 0xb009319e, 0x45ef05c9, 0x2a143e76, 0x9a73626c,
+           0x582140dd);
+  VCMP_U32(109, v4, 0x11ffa54e, 0x9af29daa, 0x575c2e05, 0xcf7a1d98, 0x26439a12,
+           0x35659121, 0xa87678a2, 0x67dd4037, 0xb7600abf, 0xaadc6195,
+           0x64d90d0c, 0xcc6da682, 0x8533b185, 0x2a4339cc, 0x7e70281b,
+           0x4f2ea60f, 0xbf3b8546, 0x18cbcecd, 0x5bf0c67b, 0x93265d9d,
+           0x788529c3, 0x4edd7f48, 0x3266d631, 0x7bfd8a81, 0xa06a42d4,
+           0xb9272633, 0xf542d689, 0xf547c96e, 0x17a38eec, 0xca064493,
+           0x97df3c7a);
+
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  stride = 12;
+  VSET(22, e32, m1);
+  asm volatile("vlsseg4e32.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U32(110, v1, 0xe19afa6b, 0x11ffa54e, 0x956eb527, 0xcf7a1d98, 0x785cc853,
+           0xa87678a2, 0xd29ad01e, 0xaadc6195, 0x6c3b54b0, 0x8533b185,
+           0xcf9238fb, 0x4f2ea60f, 0x52b26ff5, 0x5bf0c67b, 0xcff3c77d,
+           0x4edd7f48, 0x3b2f25a6, 0xa06a42d4, 0xb009319e, 0xf547c96e,
+           0x9a73626c, 0x97df3c7a);
+  VCMP_U32(111, v2, 0x8c10145c, 0x82f92af6, 0x575c2e05, 0x53a0be4e, 0x35659121,
+           0xb11d757e, 0xb7600abf, 0xcefce71b, 0xcc6da682, 0xa2cd798c,
+           0x7e70281b, 0x4b32bcdd, 0x18cbcecd, 0x60914005, 0x788529c3,
+           0xddcd4d07, 0x7bfd8a81, 0x687f8a39, 0xf542d689, 0x2a143e76,
+           0xca064493);
+  VCMP_U32(112, v3, 0xbca44cc5, 0x9af29daa, 0x68fb4cc5, 0x26439a12, 0xf7a96b8c,
+           0x67dd4037, 0x2e572002, 0x64d90d0c, 0xd8b7ae76, 0x2a4339cc,
+           0xdf162ee9, 0xbf3b8546, 0xc364c8f8, 0x93265d9d, 0xdda63ceb,
+           0x3266d631, 0x9db64ef5, 0xb9272633, 0x45ef05c9, 0x17a38eec,
+           0x582140dd);
+  VCMP_U32(113, v4, 0x11ffa54e, 0x956eb527, 0xcf7a1d98, 0x785cc853, 0xa87678a2,
+           0xd29ad01e, 0xaadc6195, 0x6c3b54b0, 0x8533b185, 0xcf9238fb,
+           0x4f2ea60f, 0x52b26ff5, 0x5bf0c67b, 0xcff3c77d, 0x4edd7f48,
+           0x3b2f25a6, 0xa06a42d4, 0xb009319e, 0xf547c96e, 0x9a73626c,
+           0x97df3c7a);
+
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  stride = 16;
+  VSET(16, e32, m1);
+  asm volatile("vlsseg4e32.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U32(114, v1, 0xe19afa6b, 0x82f92af6, 0x68fb4cc5, 0x785cc853, 0xb11d757e,
+           0x2e572002, 0x6c3b54b0, 0xa2cd798c, 0xdf162ee9, 0x52b26ff5,
+           0x60914005, 0xdda63ceb, 0x3b2f25a6, 0x687f8a39, 0x45ef05c9,
+           0x9a73626c);
+  VCMP_U32(115, v2, 0x8c10145c, 0x9af29daa, 0xcf7a1d98, 0x35659121, 0x67dd4037,
+           0xaadc6195, 0xcc6da682, 0x2a4339cc, 0x4f2ea60f, 0x18cbcecd,
+           0x93265d9d, 0x4edd7f48, 0x7bfd8a81, 0xb9272633, 0xf547c96e,
+           0xca064493);
+  VCMP_U32(116, v3, 0xbca44cc5, 0x956eb527, 0x53a0be4e, 0xf7a96b8c, 0xd29ad01e,
+           0xcefce71b, 0xd8b7ae76, 0xcf9238fb, 0x4b32bcdd, 0xc364c8f8,
+           0xcff3c77d, 0xddcd4d07, 0x9db64ef5, 0xb009319e, 0x2a143e76,
+           0x582140dd);
+  VCMP_U32(117, v4, 0x11ffa54e, 0x575c2e05, 0x26439a12, 0xa87678a2, 0xb7600abf,
+           0x64d90d0c, 0x8533b185, 0x7e70281b, 0xbf3b8546, 0x5bf0c67b,
+           0x788529c3, 0x3266d631, 0xa06a42d4, 0xf542d689, 0x17a38eec,
+           0x97df3c7a);
+}
+
+// Segment-8
+void TEST_CASE4_32(void) {
+  VSET(-1, e32, m1);
+  volatile uint32_t INP1[] = {
+      0xe19afa6b, 0x8c10145c, 0xbca44cc5, 0x11ffa54e, 0x82f92af6, 0x9af29daa,
+      0x956eb527, 0x575c2e05, 0x68fb4cc5, 0xcf7a1d98, 0x53a0be4e, 0x26439a12,
+      0x785cc853, 0x35659121, 0xf7a96b8c, 0xa87678a2, 0xb11d757e, 0x67dd4037,
+      0xd29ad01e, 0xb7600abf, 0x2e572002, 0xaadc6195, 0xcefce71b, 0x64d90d0c,
+      0x6c3b54b0, 0xcc6da682, 0xd8b7ae76, 0x8533b185, 0xa2cd798c, 0x2a4339cc,
+      0xcf9238fb, 0x7e70281b, 0xdf162ee9, 0x4f2ea60f, 0x4b32bcdd, 0xbf3b8546,
+      0x52b26ff5, 0x18cbcecd, 0xc364c8f8, 0x5bf0c67b, 0x60914005, 0x93265d9d,
+      0xcff3c77d, 0x788529c3, 0xdda63ceb, 0x4edd7f48, 0xddcd4d07, 0x3266d631,
+      0x3b2f25a6, 0x7bfd8a81, 0x9db64ef5, 0xa06a42d4, 0x687f8a39, 0xb9272633,
+      0xb009319e, 0xf542d689, 0x45ef05c9, 0xf547c96e, 0x2a143e76, 0x17a38eec,
+      0x9a73626c, 0xca064493, 0x582140dd, 0x97df3c7a};
+
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  VCLEAR(v5);
+  VCLEAR(v6);
+  VCLEAR(v7);
+  VCLEAR(v8);
+  stride = 8;
+  VSET(32, e32, m1);
+  asm volatile("vlsseg8e32.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U32(118, v1, 0xe19afa6b, 0xbca44cc5, 0x82f92af6, 0x956eb527, 0x68fb4cc5,
+           0x53a0be4e, 0x785cc853, 0xf7a96b8c, 0xb11d757e, 0xd29ad01e,
+           0x2e572002, 0xcefce71b, 0x6c3b54b0, 0xd8b7ae76, 0xa2cd798c,
+           0xcf9238fb, 0xdf162ee9, 0x4b32bcdd, 0x52b26ff5, 0xc364c8f8,
+           0x60914005, 0xcff3c77d, 0xdda63ceb, 0xddcd4d07, 0x3b2f25a6,
+           0x9db64ef5, 0x687f8a39, 0xb009319e, 0x45ef05c9, 0x2a143e76,
+           0x9a73626c, 0x582140dd);
+  VCMP_U32(119, v2, 0x8c10145c, 0x11ffa54e, 0x9af29daa, 0x575c2e05, 0xcf7a1d98,
+           0x26439a12, 0x35659121, 0xa87678a2, 0x67dd4037, 0xb7600abf,
+           0xaadc6195, 0x64d90d0c, 0xcc6da682, 0x8533b185, 0x2a4339cc,
+           0x7e70281b, 0x4f2ea60f, 0xbf3b8546, 0x18cbcecd, 0x5bf0c67b,
+           0x93265d9d, 0x788529c3, 0x4edd7f48, 0x3266d631, 0x7bfd8a81,
+           0xa06a42d4, 0xb9272633, 0xf542d689, 0xf547c96e, 0x17a38eec,
+           0xca064493, 0x97df3c7a);
+  VCMP_U32(120, v3, 0xbca44cc5, 0x82f92af6, 0x956eb527, 0x68fb4cc5, 0x53a0be4e,
+           0x785cc853, 0xf7a96b8c, 0xb11d757e, 0xd29ad01e, 0x2e572002,
+           0xcefce71b, 0x6c3b54b0, 0xd8b7ae76, 0xa2cd798c, 0xcf9238fb,
+           0xdf162ee9, 0x4b32bcdd, 0x52b26ff5, 0xc364c8f8, 0x60914005,
+           0xcff3c77d, 0xdda63ceb, 0xddcd4d07, 0x3b2f25a6, 0x9db64ef5,
+           0x687f8a39, 0xb009319e, 0x45ef05c9, 0x2a143e76, 0x9a73626c,
+           0x582140dd);
+  VCMP_U32(121, v4, 0x11ffa54e, 0x9af29daa, 0x575c2e05, 0xcf7a1d98, 0x26439a12,
+           0x35659121, 0xa87678a2, 0x67dd4037, 0xb7600abf, 0xaadc6195,
+           0x64d90d0c, 0xcc6da682, 0x8533b185, 0x2a4339cc, 0x7e70281b,
+           0x4f2ea60f, 0xbf3b8546, 0x18cbcecd, 0x5bf0c67b, 0x93265d9d,
+           0x788529c3, 0x4edd7f48, 0x3266d631, 0x7bfd8a81, 0xa06a42d4,
+           0xb9272633, 0xf542d689, 0xf547c96e, 0x17a38eec, 0xca064493,
+           0x97df3c7a);
+  VCMP_U32(122, v5, 0x82f92af6, 0x956eb527, 0x68fb4cc5, 0x53a0be4e, 0x785cc853,
+           0xf7a96b8c, 0xb11d757e, 0xd29ad01e, 0x2e572002, 0xcefce71b,
+           0x6c3b54b0, 0xd8b7ae76, 0xa2cd798c, 0xcf9238fb, 0xdf162ee9,
+           0x4b32bcdd, 0x52b26ff5, 0xc364c8f8, 0x60914005, 0xcff3c77d,
+           0xdda63ceb, 0xddcd4d07, 0x3b2f25a6, 0x9db64ef5, 0x687f8a39,
+           0xb009319e, 0x45ef05c9, 0x2a143e76, 0x9a73626c, 0x582140dd);
+  VCMP_U32(123, v6, 0x9af29daa, 0x575c2e05, 0xcf7a1d98, 0x26439a12, 0x35659121,
+           0xa87678a2, 0x67dd4037, 0xb7600abf, 0xaadc6195, 0x64d90d0c,
+           0xcc6da682, 0x8533b185, 0x2a4339cc, 0x7e70281b, 0x4f2ea60f,
+           0xbf3b8546, 0x18cbcecd, 0x5bf0c67b, 0x93265d9d, 0x788529c3,
+           0x4edd7f48, 0x3266d631, 0x7bfd8a81, 0xa06a42d4, 0xb9272633,
+           0xf542d689, 0xf547c96e, 0x17a38eec, 0xca064493, 0x97df3c7a);
+  VCMP_U32(124, v7, 0x956eb527, 0x68fb4cc5, 0x53a0be4e, 0x785cc853, 0xf7a96b8c,
+           0xb11d757e, 0xd29ad01e, 0x2e572002, 0xcefce71b, 0x6c3b54b0,
+           0xd8b7ae76, 0xa2cd798c, 0xcf9238fb, 0xdf162ee9, 0x4b32bcdd,
+           0x52b26ff5, 0xc364c8f8, 0x60914005, 0xcff3c77d, 0xdda63ceb,
+           0xddcd4d07, 0x3b2f25a6, 0x9db64ef5, 0x687f8a39, 0xb009319e,
+           0x45ef05c9, 0x2a143e76, 0x9a73626c, 0x582140dd);
+  VCMP_U32(125, v8, 0x575c2e05, 0xcf7a1d98, 0x26439a12, 0x35659121, 0xa87678a2,
+           0x67dd4037, 0xb7600abf, 0xaadc6195, 0x64d90d0c, 0xcc6da682,
+           0x8533b185, 0x2a4339cc, 0x7e70281b, 0x4f2ea60f, 0xbf3b8546,
+           0x18cbcecd, 0x5bf0c67b, 0x93265d9d, 0x788529c3, 0x4edd7f48,
+           0x3266d631, 0x7bfd8a81, 0xa06a42d4, 0xb9272633, 0xf542d689,
+           0xf547c96e, 0x17a38eec, 0xca064493, 0x97df3c7a);
+
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  VCLEAR(v5);
+  VCLEAR(v6);
+  VCLEAR(v7);
+  VCLEAR(v8);
+  stride = 12;
+  VSET(22, e32, m1);
+  asm volatile("vlsseg8e32.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U32(126, v1, 0xe19afa6b, 0x11ffa54e, 0x956eb527, 0xcf7a1d98, 0x785cc853,
+           0xa87678a2, 0xd29ad01e, 0xaadc6195, 0x6c3b54b0, 0x8533b185,
+           0xcf9238fb, 0x4f2ea60f, 0x52b26ff5, 0x5bf0c67b, 0xcff3c77d,
+           0x4edd7f48, 0x3b2f25a6, 0xa06a42d4, 0xb009319e, 0xf547c96e,
+           0x9a73626c, 0x97df3c7a);
+  VCMP_U32(127, v2, 0x8c10145c, 0x82f92af6, 0x575c2e05, 0x53a0be4e, 0x35659121,
+           0xb11d757e, 0xb7600abf, 0xcefce71b, 0xcc6da682, 0xa2cd798c,
+           0x7e70281b, 0x4b32bcdd, 0x18cbcecd, 0x60914005, 0x788529c3,
+           0xddcd4d07, 0x7bfd8a81, 0x687f8a39, 0xf542d689, 0x2a143e76,
+           0xca064493);
+  VCMP_U32(128, v3, 0xbca44cc5, 0x9af29daa, 0x68fb4cc5, 0x26439a12, 0xf7a96b8c,
+           0x67dd4037, 0x2e572002, 0x64d90d0c, 0xd8b7ae76, 0x2a4339cc,
+           0xdf162ee9, 0xbf3b8546, 0xc364c8f8, 0x93265d9d, 0xdda63ceb,
+           0x3266d631, 0x9db64ef5, 0xb9272633, 0x45ef05c9, 0x17a38eec,
+           0x582140dd);
+  VCMP_U32(129, v4, 0x11ffa54e, 0x956eb527, 0xcf7a1d98, 0x785cc853, 0xa87678a2,
+           0xd29ad01e, 0xaadc6195, 0x6c3b54b0, 0x8533b185, 0xcf9238fb,
+           0x4f2ea60f, 0x52b26ff5, 0x5bf0c67b, 0xcff3c77d, 0x4edd7f48,
+           0x3b2f25a6, 0xa06a42d4, 0xb009319e, 0xf547c96e, 0x9a73626c,
+           0x97df3c7a);
+  VCMP_U32(130, v5, 0x82f92af6, 0x575c2e05, 0x53a0be4e, 0x35659121, 0xb11d757e,
+           0xb7600abf, 0xcefce71b, 0xcc6da682, 0xa2cd798c, 0x7e70281b,
+           0x4b32bcdd, 0x18cbcecd, 0x60914005, 0x788529c3, 0xddcd4d07,
+           0x7bfd8a81, 0x687f8a39, 0xf542d689, 0x2a143e76, 0xca064493);
+  VCMP_U32(131, v6, 0x9af29daa, 0x68fb4cc5, 0x26439a12, 0xf7a96b8c, 0x67dd4037,
+           0x2e572002, 0x64d90d0c, 0xd8b7ae76, 0x2a4339cc, 0xdf162ee9,
+           0xbf3b8546, 0xc364c8f8, 0x93265d9d, 0xdda63ceb, 0x3266d631,
+           0x9db64ef5, 0xb9272633, 0x45ef05c9, 0x17a38eec, 0x582140dd);
+  VCMP_U32(132, v7, 0x956eb527, 0xcf7a1d98, 0x785cc853, 0xa87678a2, 0xd29ad01e,
+           0xaadc6195, 0x6c3b54b0, 0x8533b185, 0xcf9238fb, 0x4f2ea60f,
+           0x52b26ff5, 0x5bf0c67b, 0xcff3c77d, 0x4edd7f48, 0x3b2f25a6,
+           0xa06a42d4, 0xb009319e, 0xf547c96e, 0x9a73626c, 0x97df3c7a);
+  VCMP_U32(133, v8, 0x575c2e05, 0x53a0be4e, 0x35659121, 0xb11d757e, 0xb7600abf,
+           0xcefce71b, 0xcc6da682, 0xa2cd798c, 0x7e70281b, 0x4b32bcdd,
+           0x18cbcecd, 0x60914005, 0x788529c3, 0xddcd4d07, 0x7bfd8a81,
+           0x687f8a39, 0xf542d689, 0x2a143e76, 0xca064493);
+
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  VCLEAR(v5);
+  VCLEAR(v6);
+  VCLEAR(v7);
+  VCLEAR(v8);
+  stride = 16;
+  VSET(16, e32, m1);
+  asm volatile("vlsseg8e32.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U32(134, v1, 0xe19afa6b, 0x82f92af6, 0x68fb4cc5, 0x785cc853, 0xb11d757e,
+           0x2e572002, 0x6c3b54b0, 0xa2cd798c, 0xdf162ee9, 0x52b26ff5,
+           0x60914005, 0xdda63ceb, 0x3b2f25a6, 0x687f8a39, 0x45ef05c9,
+           0x9a73626c);
+  VCMP_U32(135, v2, 0x8c10145c, 0x9af29daa, 0xcf7a1d98, 0x35659121, 0x67dd4037,
+           0xaadc6195, 0xcc6da682, 0x2a4339cc, 0x4f2ea60f, 0x18cbcecd,
+           0x93265d9d, 0x4edd7f48, 0x7bfd8a81, 0xb9272633, 0xf547c96e,
+           0xca064493);
+  VCMP_U32(136, v3, 0xbca44cc5, 0x956eb527, 0x53a0be4e, 0xf7a96b8c, 0xd29ad01e,
+           0xcefce71b, 0xd8b7ae76, 0xcf9238fb, 0x4b32bcdd, 0xc364c8f8,
+           0xcff3c77d, 0xddcd4d07, 0x9db64ef5, 0xb009319e, 0x2a143e76,
+           0x582140dd);
+  VCMP_U32(137, v4, 0x11ffa54e, 0x575c2e05, 0x26439a12, 0xa87678a2, 0xb7600abf,
+           0x64d90d0c, 0x8533b185, 0x7e70281b, 0xbf3b8546, 0x5bf0c67b,
+           0x788529c3, 0x3266d631, 0xa06a42d4, 0xf542d689, 0x17a38eec,
+           0x97df3c7a);
+  VCMP_U32(138, v5, 0x82f92af6, 0x68fb4cc5, 0x785cc853, 0xb11d757e, 0x2e572002,
+           0x6c3b54b0, 0xa2cd798c, 0xdf162ee9, 0x52b26ff5, 0x60914005,
+           0xdda63ceb, 0x3b2f25a6, 0x687f8a39, 0x45ef05c9, 0x9a73626c);
+  VCMP_U32(139, v6, 0x9af29daa, 0xcf7a1d98, 0x35659121, 0x67dd4037, 0xaadc6195,
+           0xcc6da682, 0x2a4339cc, 0x4f2ea60f, 0x18cbcecd, 0x93265d9d,
+           0x4edd7f48, 0x7bfd8a81, 0xb9272633, 0xf547c96e, 0xca064493);
+  VCMP_U32(140, v7, 0x956eb527, 0x53a0be4e, 0xf7a96b8c, 0xd29ad01e, 0xcefce71b,
+           0xd8b7ae76, 0xcf9238fb, 0x4b32bcdd, 0xc364c8f8, 0xcff3c77d,
+           0xddcd4d07, 0x9db64ef5, 0xb009319e, 0x2a143e76, 0x582140dd);
+  VCMP_U32(141, v8, 0x575c2e05, 0x26439a12, 0xa87678a2, 0xb7600abf, 0x64d90d0c,
+           0x8533b185, 0x7e70281b, 0xbf3b8546, 0x5bf0c67b, 0x788529c3,
+           0x3266d631, 0xa06a42d4, 0xf542d689, 0x17a38eec, 0x97df3c7a);
+}
+
+// Segment-2
+void TEST_CASE1_64(void) {
+
+  VSET(-1, e64, m1);
+  volatile uint64_t INP1[] = {
+      0xfa3a99086b4b64aa, 0x57bb4a671118fdc0, 0xbb8df43b65bac0d2,
+      0xa41351c301c72b5b, 0x511e175802d24608, 0x64d7a5514d544e52,
+      0xbf1d53ca3e3c6bf7, 0xd31ac04eea8ecc07, 0x52edd3cfec205090,
+      0x891a1820b423c29c, 0xfc8e3370b171c315, 0xa30da5c56e052f67,
+      0x9f79ec1cdf33c0bc, 0x5d2c78d9927dfa33, 0x52b80462b7e072f9,
+      0x3e0efee7a99a28e7, 0x3216edfad69d8286, 0x7409095aa2433e2e,
+      0x45efda30062c904b, 0x2b707d3fbaef7019, 0xde9483fe82609c40,
+      0x9d5e63fed3019ea6, 0xc4bae94e8d757c0f, 0x7c917722900ef4d8,
+      0x693f603446fb64e6, 0x42cb1e2132c3d7d5, 0xd77ba2e13e47d589,
+      0x45887508688c93b2, 0xac730ac471f57a8e, 0x708ca6623c11c1ff,
+      0x90c7d0d2a8aa883c, 0xdb0427f14bb4d5ba, 0x3adf5823d1051252,
+      0xc31b51ef18e6dc16, 0xa96c56ed56947466, 0x5e0f5c76fdd72450,
+      0xada6b728b9b84f27, 0x9ef5b07ca6742028, 0x2d52c2213e1497ab,
+      0x201b60e0fbbc4acd, 0x5428920ecca684b1, 0xc826aff176ba9a29,
+      0x6f8c8820840f716e, 0x4a2bb5a96b1f24f5, 0x8aac4c04213d26aa,
+      0xecd584f402152e19, 0x89f5805801f25a66, 0xbad7cab9c4062ffc,
+      0xb6715b7275106bc1, 0x53112b0cc2123035, 0x8ec585926ed7af58,
+      0xce4722d4b56cd330, 0x14041ab000c9c396, 0x928220385ce8c56d,
+      0xdb402f4b0fd38776, 0x180002d7d73b1ae2, 0x76c882042e57f707,
+      0xd13e73308658ad1f, 0x5142eb4c19644e7d, 0x23def41d77db2d38,
+      0x34affa8555d23fd9, 0xa311951efe71188d, 0xf96089370f7fa0a7,
+      0xb0899dfea0b44c26};
+
+  VCLEAR(v1);
+  VCLEAR(v2);
+  stride = 0;
+  VSET(5, e64, m1);
+  asm volatile("vlsseg2e64.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U64(143, v1, 0xfa3a99086b4b64aa, 0xfa3a99086b4b64aa, 0xfa3a99086b4b64aa,
+           0xfa3a99086b4b64aa, 0xfa3a99086b4b64aa);
+  VCMP_U64(144, v2, 0x57bb4a671118fdc0, 0x57bb4a671118fdc0, 0x57bb4a671118fdc0,
+           0x57bb4a671118fdc0, 0x57bb4a671118fdc0);
+
+  VSET(-1, e64, m1);
+  VCLEAR(v1);
+  VCLEAR(v2);
+  stride = 16;
+  VSET(32, e64, m1);
+  asm volatile("vlsseg2e64.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U64(145, v1, 0xfa3a99086b4b64aa, 0xbb8df43b65bac0d2, 0x511e175802d24608,
+           0xbf1d53ca3e3c6bf7, 0x52edd3cfec205090, 0xfc8e3370b171c315,
+           0x9f79ec1cdf33c0bc, 0x52b80462b7e072f9, 0x3216edfad69d8286,
+           0x45efda30062c904b, 0xde9483fe82609c40, 0xc4bae94e8d757c0f,
+           0x693f603446fb64e6, 0xd77ba2e13e47d589, 0xac730ac471f57a8e,
+           0x90c7d0d2a8aa883c, 0x3adf5823d1051252, 0xa96c56ed56947466,
+           0xada6b728b9b84f27, 0x2d52c2213e1497ab, 0x5428920ecca684b1,
+           0x6f8c8820840f716e, 0x8aac4c04213d26aa, 0x89f5805801f25a66,
+           0xb6715b7275106bc1, 0x8ec585926ed7af58, 0x14041ab000c9c396,
+           0xdb402f4b0fd38776, 0x76c882042e57f707, 0x5142eb4c19644e7d,
+           0x34affa8555d23fd9, 0xf96089370f7fa0a7);
+  VCMP_U64(146, v2, 0x57bb4a671118fdc0, 0xa41351c301c72b5b, 0x64d7a5514d544e52,
+           0xd31ac04eea8ecc07, 0x891a1820b423c29c, 0xa30da5c56e052f67,
+           0x5d2c78d9927dfa33, 0x3e0efee7a99a28e7, 0x7409095aa2433e2e,
+           0x2b707d3fbaef7019, 0x9d5e63fed3019ea6, 0x7c917722900ef4d8,
+           0x42cb1e2132c3d7d5, 0x45887508688c93b2, 0x708ca6623c11c1ff,
+           0xdb0427f14bb4d5ba, 0xc31b51ef18e6dc16, 0x5e0f5c76fdd72450,
+           0x9ef5b07ca6742028, 0x201b60e0fbbc4acd, 0xc826aff176ba9a29,
+           0x4a2bb5a96b1f24f5, 0xecd584f402152e19, 0xbad7cab9c4062ffc,
+           0x53112b0cc2123035, 0xce4722d4b56cd330, 0x928220385ce8c56d,
+           0x180002d7d73b1ae2, 0xd13e73308658ad1f, 0x23def41d77db2d38,
+           0xa311951efe71188d, 0xb0899dfea0b44c26);
+
+  VSET(-1, e64, m1);
+  VCLEAR(v1);
+  VCLEAR(v2);
+  stride = 24;
+  VSET(22, e64, m1);
+  asm volatile("vlsseg2e64.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U64(149, v1, 0xfa3a99086b4b64aa, 0xa41351c301c72b5b, 0xbf1d53ca3e3c6bf7,
+           0x891a1820b423c29c, 0x9f79ec1cdf33c0bc, 0x3e0efee7a99a28e7,
+           0x45efda30062c904b, 0x9d5e63fed3019ea6, 0x693f603446fb64e6,
+           0x45887508688c93b2, 0x90c7d0d2a8aa883c, 0xc31b51ef18e6dc16,
+           0xada6b728b9b84f27, 0x201b60e0fbbc4acd, 0x6f8c8820840f716e,
+           0xecd584f402152e19, 0xb6715b7275106bc1, 0xce4722d4b56cd330,
+           0xdb402f4b0fd38776, 0xd13e73308658ad1f, 0x34affa8555d23fd9,
+           0xb0899dfea0b44c26);
+  VCMP_U64(150, v2, 0x57bb4a671118fdc0, 0x511e175802d24608, 0xd31ac04eea8ecc07,
+           0xfc8e3370b171c315, 0x5d2c78d9927dfa33, 0x3216edfad69d8286,
+           0x2b707d3fbaef7019, 0xc4bae94e8d757c0f, 0x42cb1e2132c3d7d5,
+           0xac730ac471f57a8e, 0xdb0427f14bb4d5ba, 0xa96c56ed56947466,
+           0x9ef5b07ca6742028, 0x5428920ecca684b1, 0x4a2bb5a96b1f24f5,
+           0x89f5805801f25a66, 0x53112b0cc2123035, 0x14041ab000c9c396,
+           0x180002d7d73b1ae2, 0x5142eb4c19644e7d, 0xa311951efe71188d);
+
+  VSET(-1, e64, m1);
+  VCLEAR(v1);
+  VCLEAR(v2);
+  stride = 32;
+  VSET(16, e64, m1);
+  asm volatile("vlsseg2e64.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U64(151, v1, 0xfa3a99086b4b64aa, 0x511e175802d24608, 0x52edd3cfec205090,
+           0x9f79ec1cdf33c0bc, 0x3216edfad69d8286, 0xde9483fe82609c40,
+           0x693f603446fb64e6, 0xac730ac471f57a8e, 0x3adf5823d1051252,
+           0xada6b728b9b84f27, 0x5428920ecca684b1, 0x8aac4c04213d26aa,
+           0xb6715b7275106bc1, 0x14041ab000c9c396, 0x76c882042e57f707,
+           0x34affa8555d23fd9);
+  VCMP_U64(152, v2, 0x57bb4a671118fdc0, 0x64d7a5514d544e52, 0x891a1820b423c29c,
+           0x5d2c78d9927dfa33, 0x7409095aa2433e2e, 0x9d5e63fed3019ea6,
+           0x42cb1e2132c3d7d5, 0x708ca6623c11c1ff, 0xc31b51ef18e6dc16,
+           0x9ef5b07ca6742028, 0xc826aff176ba9a29, 0xecd584f402152e19,
+           0x53112b0cc2123035, 0x928220385ce8c56d, 0xd13e73308658ad1f,
+           0xa311951efe71188d);
+}
+
+// Segment-3
+void TEST_CASE2_64(void) {
+  VSET(-1, e64, m1);
+  volatile uint64_t INP1[] = {
+      0xfa3a99086b4b64aa, 0x57bb4a671118fdc0, 0xbb8df43b65bac0d2,
+      0xa41351c301c72b5b, 0x511e175802d24608, 0x64d7a5514d544e52,
+      0xbf1d53ca3e3c6bf7, 0xd31ac04eea8ecc07, 0x52edd3cfec205090,
+      0x891a1820b423c29c, 0xfc8e3370b171c315, 0xa30da5c56e052f67,
+      0x9f79ec1cdf33c0bc, 0x5d2c78d9927dfa33, 0x52b80462b7e072f9,
+      0x3e0efee7a99a28e7, 0x3216edfad69d8286, 0x7409095aa2433e2e,
+      0x45efda30062c904b, 0x2b707d3fbaef7019, 0xde9483fe82609c40,
+      0x9d5e63fed3019ea6, 0xc4bae94e8d757c0f, 0x7c917722900ef4d8,
+      0x693f603446fb64e6, 0x42cb1e2132c3d7d5, 0xd77ba2e13e47d589,
+      0x45887508688c93b2, 0xac730ac471f57a8e, 0x708ca6623c11c1ff,
+      0x90c7d0d2a8aa883c, 0xdb0427f14bb4d5ba, 0x3adf5823d1051252,
+      0xc31b51ef18e6dc16, 0xa96c56ed56947466, 0x5e0f5c76fdd72450,
+      0xada6b728b9b84f27, 0x9ef5b07ca6742028, 0x2d52c2213e1497ab,
+      0x201b60e0fbbc4acd, 0x5428920ecca684b1, 0xc826aff176ba9a29,
+      0x6f8c8820840f716e, 0x4a2bb5a96b1f24f5, 0x8aac4c04213d26aa,
+      0xecd584f402152e19, 0x89f5805801f25a66, 0xbad7cab9c4062ffc,
+      0xb6715b7275106bc1, 0x53112b0cc2123035, 0x8ec585926ed7af58,
+      0xce4722d4b56cd330, 0x14041ab000c9c396, 0x928220385ce8c56d,
+      0xdb402f4b0fd38776, 0x180002d7d73b1ae2, 0x76c882042e57f707,
+      0xd13e73308658ad1f, 0x5142eb4c19644e7d, 0x23def41d77db2d38,
+      0x34affa8555d23fd9, 0xa311951efe71188d, 0xf96089370f7fa0a7,
+      0xb0899dfea0b44c26};
+
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  stride = 16;
+  VSET(32, e64, m1);
+  asm volatile("vlsseg3e64.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U64(153, v1, 0xfa3a99086b4b64aa, 0xbb8df43b65bac0d2, 0x511e175802d24608,
+           0xbf1d53ca3e3c6bf7, 0x52edd3cfec205090, 0xfc8e3370b171c315,
+           0x9f79ec1cdf33c0bc, 0x52b80462b7e072f9, 0x3216edfad69d8286,
+           0x45efda30062c904b, 0xde9483fe82609c40, 0xc4bae94e8d757c0f,
+           0x693f603446fb64e6, 0xd77ba2e13e47d589, 0xac730ac471f57a8e,
+           0x90c7d0d2a8aa883c, 0x3adf5823d1051252, 0xa96c56ed56947466,
+           0xada6b728b9b84f27, 0x2d52c2213e1497ab, 0x5428920ecca684b1,
+           0x6f8c8820840f716e, 0x8aac4c04213d26aa, 0x89f5805801f25a66,
+           0xb6715b7275106bc1, 0x8ec585926ed7af58, 0x14041ab000c9c396,
+           0xdb402f4b0fd38776, 0x76c882042e57f707, 0x5142eb4c19644e7d,
+           0x34affa8555d23fd9, 0xf96089370f7fa0a7);
+  VCMP_U64(154, v2, 0x57bb4a671118fdc0, 0xa41351c301c72b5b, 0x64d7a5514d544e52,
+           0xd31ac04eea8ecc07, 0x891a1820b423c29c, 0xa30da5c56e052f67,
+           0x5d2c78d9927dfa33, 0x3e0efee7a99a28e7, 0x7409095aa2433e2e,
+           0x2b707d3fbaef7019, 0x9d5e63fed3019ea6, 0x7c917722900ef4d8,
+           0x42cb1e2132c3d7d5, 0x45887508688c93b2, 0x708ca6623c11c1ff,
+           0xdb0427f14bb4d5ba, 0xc31b51ef18e6dc16, 0x5e0f5c76fdd72450,
+           0x9ef5b07ca6742028, 0x201b60e0fbbc4acd, 0xc826aff176ba9a29,
+           0x4a2bb5a96b1f24f5, 0xecd584f402152e19, 0xbad7cab9c4062ffc,
+           0x53112b0cc2123035, 0xce4722d4b56cd330, 0x928220385ce8c56d,
+           0x180002d7d73b1ae2, 0xd13e73308658ad1f, 0x23def41d77db2d38,
+           0xa311951efe71188d, 0xb0899dfea0b44c26);
+  VCMP_U64(155, v3, 0xbb8df43b65bac0d2, 0x511e175802d24608, 0xbf1d53ca3e3c6bf7,
+           0x52edd3cfec205090, 0xfc8e3370b171c315, 0x9f79ec1cdf33c0bc,
+           0x52b80462b7e072f9, 0x3216edfad69d8286, 0x45efda30062c904b,
+           0xde9483fe82609c40, 0xc4bae94e8d757c0f, 0x693f603446fb64e6,
+           0xd77ba2e13e47d589, 0xac730ac471f57a8e, 0x90c7d0d2a8aa883c,
+           0x3adf5823d1051252, 0xa96c56ed56947466, 0xada6b728b9b84f27,
+           0x2d52c2213e1497ab, 0x5428920ecca684b1, 0x6f8c8820840f716e,
+           0x8aac4c04213d26aa, 0x89f5805801f25a66, 0xb6715b7275106bc1,
+           0x8ec585926ed7af58, 0x14041ab000c9c396, 0xdb402f4b0fd38776,
+           0x76c882042e57f707, 0x5142eb4c19644e7d, 0x34affa8555d23fd9,
+           0xf96089370f7fa0a7);
+
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  stride = 24;
+  VSET(22, e64, m1);
+  asm volatile("vlsseg3e64.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U64(156, v1, 0xfa3a99086b4b64aa, 0xa41351c301c72b5b, 0xbf1d53ca3e3c6bf7,
+           0x891a1820b423c29c, 0x9f79ec1cdf33c0bc, 0x3e0efee7a99a28e7,
+           0x45efda30062c904b, 0x9d5e63fed3019ea6, 0x693f603446fb64e6,
+           0x45887508688c93b2, 0x90c7d0d2a8aa883c, 0xc31b51ef18e6dc16,
+           0xada6b728b9b84f27, 0x201b60e0fbbc4acd, 0x6f8c8820840f716e,
+           0xecd584f402152e19, 0xb6715b7275106bc1, 0xce4722d4b56cd330,
+           0xdb402f4b0fd38776, 0xd13e73308658ad1f, 0x34affa8555d23fd9,
+           0xb0899dfea0b44c26);
+  VCMP_U64(157, v2, 0x57bb4a671118fdc0, 0x511e175802d24608, 0xd31ac04eea8ecc07,
+           0xfc8e3370b171c315, 0x5d2c78d9927dfa33, 0x3216edfad69d8286,
+           0x2b707d3fbaef7019, 0xc4bae94e8d757c0f, 0x42cb1e2132c3d7d5,
+           0xac730ac471f57a8e, 0xdb0427f14bb4d5ba, 0xa96c56ed56947466,
+           0x9ef5b07ca6742028, 0x5428920ecca684b1, 0x4a2bb5a96b1f24f5,
+           0x89f5805801f25a66, 0x53112b0cc2123035, 0x14041ab000c9c396,
+           0x180002d7d73b1ae2, 0x5142eb4c19644e7d, 0xa311951efe71188d);
+  VCMP_U64(158, v3, 0xbb8df43b65bac0d2, 0x64d7a5514d544e52, 0x52edd3cfec205090,
+           0xa30da5c56e052f67, 0x52b80462b7e072f9, 0x7409095aa2433e2e,
+           0xde9483fe82609c40, 0x7c917722900ef4d8, 0xd77ba2e13e47d589,
+           0x708ca6623c11c1ff, 0x3adf5823d1051252, 0x5e0f5c76fdd72450,
+           0x2d52c2213e1497ab, 0xc826aff176ba9a29, 0x8aac4c04213d26aa,
+           0xbad7cab9c4062ffc, 0x8ec585926ed7af58, 0x928220385ce8c56d,
+           0x76c882042e57f707, 0x23def41d77db2d38, 0xf96089370f7fa0a7);
+
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  stride = 32;
+  VSET(16, e64, m1);
+  asm volatile("vlsseg3e64.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U64(159, v1, 0xfa3a99086b4b64aa, 0x511e175802d24608, 0x52edd3cfec205090,
+           0x9f79ec1cdf33c0bc, 0x3216edfad69d8286, 0xde9483fe82609c40,
+           0x693f603446fb64e6, 0xac730ac471f57a8e, 0x3adf5823d1051252,
+           0xada6b728b9b84f27, 0x5428920ecca684b1, 0x8aac4c04213d26aa,
+           0xb6715b7275106bc1, 0x14041ab000c9c396, 0x76c882042e57f707,
+           0x34affa8555d23fd9);
+  VCMP_U64(160, v2, 0x57bb4a671118fdc0, 0x64d7a5514d544e52, 0x891a1820b423c29c,
+           0x5d2c78d9927dfa33, 0x7409095aa2433e2e, 0x9d5e63fed3019ea6,
+           0x42cb1e2132c3d7d5, 0x708ca6623c11c1ff, 0xc31b51ef18e6dc16,
+           0x9ef5b07ca6742028, 0xc826aff176ba9a29, 0xecd584f402152e19,
+           0x53112b0cc2123035, 0x928220385ce8c56d, 0xd13e73308658ad1f,
+           0xa311951efe71188d);
+  VCMP_U64(161, v3, 0xbb8df43b65bac0d2, 0xbf1d53ca3e3c6bf7, 0xfc8e3370b171c315,
+           0x52b80462b7e072f9, 0x45efda30062c904b, 0xc4bae94e8d757c0f,
+           0xd77ba2e13e47d589, 0x90c7d0d2a8aa883c, 0xa96c56ed56947466,
+           0x2d52c2213e1497ab, 0x6f8c8820840f716e, 0x89f5805801f25a66,
+           0x8ec585926ed7af58, 0xdb402f4b0fd38776, 0x5142eb4c19644e7d,
+           0xf96089370f7fa0a7);
+}
+
+// Segment-4
+void TEST_CASE3_64(void) {
+  VSET(-1, e64, m1);
+  volatile uint64_t INP1[] = {
+      0xfa3a99086b4b64aa, 0x57bb4a671118fdc0, 0xbb8df43b65bac0d2,
+      0xa41351c301c72b5b, 0x511e175802d24608, 0x64d7a5514d544e52,
+      0xbf1d53ca3e3c6bf7, 0xd31ac04eea8ecc07, 0x52edd3cfec205090,
+      0x891a1820b423c29c, 0xfc8e3370b171c315, 0xa30da5c56e052f67,
+      0x9f79ec1cdf33c0bc, 0x5d2c78d9927dfa33, 0x52b80462b7e072f9,
+      0x3e0efee7a99a28e7, 0x3216edfad69d8286, 0x7409095aa2433e2e,
+      0x45efda30062c904b, 0x2b707d3fbaef7019, 0xde9483fe82609c40,
+      0x9d5e63fed3019ea6, 0xc4bae94e8d757c0f, 0x7c917722900ef4d8,
+      0x693f603446fb64e6, 0x42cb1e2132c3d7d5, 0xd77ba2e13e47d589,
+      0x45887508688c93b2, 0xac730ac471f57a8e, 0x708ca6623c11c1ff,
+      0x90c7d0d2a8aa883c, 0xdb0427f14bb4d5ba, 0x3adf5823d1051252,
+      0xc31b51ef18e6dc16, 0xa96c56ed56947466, 0x5e0f5c76fdd72450,
+      0xada6b728b9b84f27, 0x9ef5b07ca6742028, 0x2d52c2213e1497ab,
+      0x201b60e0fbbc4acd, 0x5428920ecca684b1, 0xc826aff176ba9a29,
+      0x6f8c8820840f716e, 0x4a2bb5a96b1f24f5, 0x8aac4c04213d26aa,
+      0xecd584f402152e19, 0x89f5805801f25a66, 0xbad7cab9c4062ffc,
+      0xb6715b7275106bc1, 0x53112b0cc2123035, 0x8ec585926ed7af58,
+      0xce4722d4b56cd330, 0x14041ab000c9c396, 0x928220385ce8c56d,
+      0xdb402f4b0fd38776, 0x180002d7d73b1ae2, 0x76c882042e57f707,
+      0xd13e73308658ad1f, 0x5142eb4c19644e7d, 0x23def41d77db2d38,
+      0x34affa8555d23fd9, 0xa311951efe71188d, 0xf96089370f7fa0a7,
+      0xb0899dfea0b44c26};
+
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  stride = 16;
+  VSET(32, e64, m1);
+  asm volatile("vlsseg4e64.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U64(162, v1, 0xfa3a99086b4b64aa, 0xbb8df43b65bac0d2, 0x511e175802d24608,
+           0xbf1d53ca3e3c6bf7, 0x52edd3cfec205090, 0xfc8e3370b171c315,
+           0x9f79ec1cdf33c0bc, 0x52b80462b7e072f9, 0x3216edfad69d8286,
+           0x45efda30062c904b, 0xde9483fe82609c40, 0xc4bae94e8d757c0f,
+           0x693f603446fb64e6, 0xd77ba2e13e47d589, 0xac730ac471f57a8e,
+           0x90c7d0d2a8aa883c, 0x3adf5823d1051252, 0xa96c56ed56947466,
+           0xada6b728b9b84f27, 0x2d52c2213e1497ab, 0x5428920ecca684b1,
+           0x6f8c8820840f716e, 0x8aac4c04213d26aa, 0x89f5805801f25a66,
+           0xb6715b7275106bc1, 0x8ec585926ed7af58, 0x14041ab000c9c396,
+           0xdb402f4b0fd38776, 0x76c882042e57f707, 0x5142eb4c19644e7d,
+           0x34affa8555d23fd9, 0xf96089370f7fa0a7);
+  VCMP_U64(163, v2, 0x57bb4a671118fdc0, 0xa41351c301c72b5b, 0x64d7a5514d544e52,
+           0xd31ac04eea8ecc07, 0x891a1820b423c29c, 0xa30da5c56e052f67,
+           0x5d2c78d9927dfa33, 0x3e0efee7a99a28e7, 0x7409095aa2433e2e,
+           0x2b707d3fbaef7019, 0x9d5e63fed3019ea6, 0x7c917722900ef4d8,
+           0x42cb1e2132c3d7d5, 0x45887508688c93b2, 0x708ca6623c11c1ff,
+           0xdb0427f14bb4d5ba, 0xc31b51ef18e6dc16, 0x5e0f5c76fdd72450,
+           0x9ef5b07ca6742028, 0x201b60e0fbbc4acd, 0xc826aff176ba9a29,
+           0x4a2bb5a96b1f24f5, 0xecd584f402152e19, 0xbad7cab9c4062ffc,
+           0x53112b0cc2123035, 0xce4722d4b56cd330, 0x928220385ce8c56d,
+           0x180002d7d73b1ae2, 0xd13e73308658ad1f, 0x23def41d77db2d38,
+           0xa311951efe71188d, 0xb0899dfea0b44c26);
+  VCMP_U64(164, v3, 0xbb8df43b65bac0d2, 0x511e175802d24608, 0xbf1d53ca3e3c6bf7,
+           0x52edd3cfec205090, 0xfc8e3370b171c315, 0x9f79ec1cdf33c0bc,
+           0x52b80462b7e072f9, 0x3216edfad69d8286, 0x45efda30062c904b,
+           0xde9483fe82609c40, 0xc4bae94e8d757c0f, 0x693f603446fb64e6,
+           0xd77ba2e13e47d589, 0xac730ac471f57a8e, 0x90c7d0d2a8aa883c,
+           0x3adf5823d1051252, 0xa96c56ed56947466, 0xada6b728b9b84f27,
+           0x2d52c2213e1497ab, 0x5428920ecca684b1, 0x6f8c8820840f716e,
+           0x8aac4c04213d26aa, 0x89f5805801f25a66, 0xb6715b7275106bc1,
+           0x8ec585926ed7af58, 0x14041ab000c9c396, 0xdb402f4b0fd38776,
+           0x76c882042e57f707, 0x5142eb4c19644e7d, 0x34affa8555d23fd9,
+           0xf96089370f7fa0a7);
+  VCMP_U64(165, v4, 0xa41351c301c72b5b, 0x64d7a5514d544e52, 0xd31ac04eea8ecc07,
+           0x891a1820b423c29c, 0xa30da5c56e052f67, 0x5d2c78d9927dfa33,
+           0x3e0efee7a99a28e7, 0x7409095aa2433e2e, 0x2b707d3fbaef7019,
+           0x9d5e63fed3019ea6, 0x7c917722900ef4d8, 0x42cb1e2132c3d7d5,
+           0x45887508688c93b2, 0x708ca6623c11c1ff, 0xdb0427f14bb4d5ba,
+           0xc31b51ef18e6dc16, 0x5e0f5c76fdd72450, 0x9ef5b07ca6742028,
+           0x201b60e0fbbc4acd, 0xc826aff176ba9a29, 0x4a2bb5a96b1f24f5,
+           0xecd584f402152e19, 0xbad7cab9c4062ffc, 0x53112b0cc2123035,
+           0xce4722d4b56cd330, 0x928220385ce8c56d, 0x180002d7d73b1ae2,
+           0xd13e73308658ad1f, 0x23def41d77db2d38, 0xa311951efe71188d,
+           0xb0899dfea0b44c26);
+
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  stride = 24;
+  VSET(22, e64, m1);
+  asm volatile("vlsseg4e64.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U64(166, v1, 0xfa3a99086b4b64aa, 0xa41351c301c72b5b, 0xbf1d53ca3e3c6bf7,
+           0x891a1820b423c29c, 0x9f79ec1cdf33c0bc, 0x3e0efee7a99a28e7,
+           0x45efda30062c904b, 0x9d5e63fed3019ea6, 0x693f603446fb64e6,
+           0x45887508688c93b2, 0x90c7d0d2a8aa883c, 0xc31b51ef18e6dc16,
+           0xada6b728b9b84f27, 0x201b60e0fbbc4acd, 0x6f8c8820840f716e,
+           0xecd584f402152e19, 0xb6715b7275106bc1, 0xce4722d4b56cd330,
+           0xdb402f4b0fd38776, 0xd13e73308658ad1f, 0x34affa8555d23fd9,
+           0xb0899dfea0b44c26);
+  VCMP_U64(167, v2, 0x57bb4a671118fdc0, 0x511e175802d24608, 0xd31ac04eea8ecc07,
+           0xfc8e3370b171c315, 0x5d2c78d9927dfa33, 0x3216edfad69d8286,
+           0x2b707d3fbaef7019, 0xc4bae94e8d757c0f, 0x42cb1e2132c3d7d5,
+           0xac730ac471f57a8e, 0xdb0427f14bb4d5ba, 0xa96c56ed56947466,
+           0x9ef5b07ca6742028, 0x5428920ecca684b1, 0x4a2bb5a96b1f24f5,
+           0x89f5805801f25a66, 0x53112b0cc2123035, 0x14041ab000c9c396,
+           0x180002d7d73b1ae2, 0x5142eb4c19644e7d, 0xa311951efe71188d);
+  VCMP_U64(168, v3, 0xbb8df43b65bac0d2, 0x64d7a5514d544e52, 0x52edd3cfec205090,
+           0xa30da5c56e052f67, 0x52b80462b7e072f9, 0x7409095aa2433e2e,
+           0xde9483fe82609c40, 0x7c917722900ef4d8, 0xd77ba2e13e47d589,
+           0x708ca6623c11c1ff, 0x3adf5823d1051252, 0x5e0f5c76fdd72450,
+           0x2d52c2213e1497ab, 0xc826aff176ba9a29, 0x8aac4c04213d26aa,
+           0xbad7cab9c4062ffc, 0x8ec585926ed7af58, 0x928220385ce8c56d,
+           0x76c882042e57f707, 0x23def41d77db2d38, 0xf96089370f7fa0a7);
+  VCMP_U64(169, v4, 0xa41351c301c72b5b, 0xbf1d53ca3e3c6bf7, 0x891a1820b423c29c,
+           0x9f79ec1cdf33c0bc, 0x3e0efee7a99a28e7, 0x45efda30062c904b,
+           0x9d5e63fed3019ea6, 0x693f603446fb64e6, 0x45887508688c93b2,
+           0x90c7d0d2a8aa883c, 0xc31b51ef18e6dc16, 0xada6b728b9b84f27,
+           0x201b60e0fbbc4acd, 0x6f8c8820840f716e, 0xecd584f402152e19,
+           0xb6715b7275106bc1, 0xce4722d4b56cd330, 0xdb402f4b0fd38776,
+           0xd13e73308658ad1f, 0x34affa8555d23fd9, 0xb0899dfea0b44c26);
+
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  stride = 32;
+  VSET(16, e64, m1);
+  asm volatile("vlsseg4e64.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U64(170, v1, 0xfa3a99086b4b64aa, 0x511e175802d24608, 0x52edd3cfec205090,
+           0x9f79ec1cdf33c0bc, 0x3216edfad69d8286, 0xde9483fe82609c40,
+           0x693f603446fb64e6, 0xac730ac471f57a8e, 0x3adf5823d1051252,
+           0xada6b728b9b84f27, 0x5428920ecca684b1, 0x8aac4c04213d26aa,
+           0xb6715b7275106bc1, 0x14041ab000c9c396, 0x76c882042e57f707,
+           0x34affa8555d23fd9);
+  VCMP_U64(171, v2, 0x57bb4a671118fdc0, 0x64d7a5514d544e52, 0x891a1820b423c29c,
+           0x5d2c78d9927dfa33, 0x7409095aa2433e2e, 0x9d5e63fed3019ea6,
+           0x42cb1e2132c3d7d5, 0x708ca6623c11c1ff, 0xc31b51ef18e6dc16,
+           0x9ef5b07ca6742028, 0xc826aff176ba9a29, 0xecd584f402152e19,
+           0x53112b0cc2123035, 0x928220385ce8c56d, 0xd13e73308658ad1f,
+           0xa311951efe71188d);
+  VCMP_U64(172, v3, 0xbb8df43b65bac0d2, 0xbf1d53ca3e3c6bf7, 0xfc8e3370b171c315,
+           0x52b80462b7e072f9, 0x45efda30062c904b, 0xc4bae94e8d757c0f,
+           0xd77ba2e13e47d589, 0x90c7d0d2a8aa883c, 0xa96c56ed56947466,
+           0x2d52c2213e1497ab, 0x6f8c8820840f716e, 0x89f5805801f25a66,
+           0x8ec585926ed7af58, 0xdb402f4b0fd38776, 0x5142eb4c19644e7d,
+           0xf96089370f7fa0a7);
+  VCMP_U64(173, v4, 0xa41351c301c72b5b, 0xd31ac04eea8ecc07, 0xa30da5c56e052f67,
+           0x3e0efee7a99a28e7, 0x2b707d3fbaef7019, 0x7c917722900ef4d8,
+           0x45887508688c93b2, 0xdb0427f14bb4d5ba, 0x5e0f5c76fdd72450,
+           0x201b60e0fbbc4acd, 0x4a2bb5a96b1f24f5, 0xbad7cab9c4062ffc,
+           0xce4722d4b56cd330, 0x180002d7d73b1ae2, 0x23def41d77db2d38,
+           0xb0899dfea0b44c26);
+}
+
+// Segment-8
+void TEST_CASE4_64(void) {
+  VSET(-1, e64, m1);
+  volatile uint64_t INP1[] = {
+      0xfa3a99086b4b64aa, 0x57bb4a671118fdc0, 0xbb8df43b65bac0d2,
+      0xa41351c301c72b5b, 0x511e175802d24608, 0x64d7a5514d544e52,
+      0xbf1d53ca3e3c6bf7, 0xd31ac04eea8ecc07, 0x52edd3cfec205090,
+      0x891a1820b423c29c, 0xfc8e3370b171c315, 0xa30da5c56e052f67,
+      0x9f79ec1cdf33c0bc, 0x5d2c78d9927dfa33, 0x52b80462b7e072f9,
+      0x3e0efee7a99a28e7, 0x3216edfad69d8286, 0x7409095aa2433e2e,
+      0x45efda30062c904b, 0x2b707d3fbaef7019, 0xde9483fe82609c40,
+      0x9d5e63fed3019ea6, 0xc4bae94e8d757c0f, 0x7c917722900ef4d8,
+      0x693f603446fb64e6, 0x42cb1e2132c3d7d5, 0xd77ba2e13e47d589,
+      0x45887508688c93b2, 0xac730ac471f57a8e, 0x708ca6623c11c1ff,
+      0x90c7d0d2a8aa883c, 0xdb0427f14bb4d5ba, 0x3adf5823d1051252,
+      0xc31b51ef18e6dc16, 0xa96c56ed56947466, 0x5e0f5c76fdd72450,
+      0xada6b728b9b84f27, 0x9ef5b07ca6742028, 0x2d52c2213e1497ab,
+      0x201b60e0fbbc4acd, 0x5428920ecca684b1, 0xc826aff176ba9a29,
+      0x6f8c8820840f716e, 0x4a2bb5a96b1f24f5, 0x8aac4c04213d26aa,
+      0xecd584f402152e19, 0x89f5805801f25a66, 0xbad7cab9c4062ffc,
+      0xb6715b7275106bc1, 0x53112b0cc2123035, 0x8ec585926ed7af58,
+      0xce4722d4b56cd330, 0x14041ab000c9c396, 0x928220385ce8c56d,
+      0xdb402f4b0fd38776, 0x180002d7d73b1ae2, 0x76c882042e57f707,
+      0xd13e73308658ad1f, 0x5142eb4c19644e7d, 0x23def41d77db2d38,
+      0x34affa8555d23fd9, 0xa311951efe71188d, 0xf96089370f7fa0a7,
+      0xb0899dfea0b44c26};
+
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  VCLEAR(v5);
+  VCLEAR(v6);
+  VCLEAR(v7);
+  VCLEAR(v8);
+  stride = 16;
+  VSET(32, e64, m1);
+  asm volatile("vlsseg8e64.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U64(174, v1, 0xfa3a99086b4b64aa, 0xbb8df43b65bac0d2, 0x511e175802d24608,
+           0xbf1d53ca3e3c6bf7, 0x52edd3cfec205090, 0xfc8e3370b171c315,
+           0x9f79ec1cdf33c0bc, 0x52b80462b7e072f9, 0x3216edfad69d8286,
+           0x45efda30062c904b, 0xde9483fe82609c40, 0xc4bae94e8d757c0f,
+           0x693f603446fb64e6, 0xd77ba2e13e47d589, 0xac730ac471f57a8e,
+           0x90c7d0d2a8aa883c, 0x3adf5823d1051252, 0xa96c56ed56947466,
+           0xada6b728b9b84f27, 0x2d52c2213e1497ab, 0x5428920ecca684b1,
+           0x6f8c8820840f716e, 0x8aac4c04213d26aa, 0x89f5805801f25a66,
+           0xb6715b7275106bc1, 0x8ec585926ed7af58, 0x14041ab000c9c396,
+           0xdb402f4b0fd38776, 0x76c882042e57f707, 0x5142eb4c19644e7d,
+           0x34affa8555d23fd9, 0xf96089370f7fa0a7);
+  VCMP_U64(175, v2, 0x57bb4a671118fdc0, 0xa41351c301c72b5b, 0x64d7a5514d544e52,
+           0xd31ac04eea8ecc07, 0x891a1820b423c29c, 0xa30da5c56e052f67,
+           0x5d2c78d9927dfa33, 0x3e0efee7a99a28e7, 0x7409095aa2433e2e,
+           0x2b707d3fbaef7019, 0x9d5e63fed3019ea6, 0x7c917722900ef4d8,
+           0x42cb1e2132c3d7d5, 0x45887508688c93b2, 0x708ca6623c11c1ff,
+           0xdb0427f14bb4d5ba, 0xc31b51ef18e6dc16, 0x5e0f5c76fdd72450,
+           0x9ef5b07ca6742028, 0x201b60e0fbbc4acd, 0xc826aff176ba9a29,
+           0x4a2bb5a96b1f24f5, 0xecd584f402152e19, 0xbad7cab9c4062ffc,
+           0x53112b0cc2123035, 0xce4722d4b56cd330, 0x928220385ce8c56d,
+           0x180002d7d73b1ae2, 0xd13e73308658ad1f, 0x23def41d77db2d38,
+           0xa311951efe71188d, 0xb0899dfea0b44c26);
+  VCMP_U64(176, v3, 0xbb8df43b65bac0d2, 0x511e175802d24608, 0xbf1d53ca3e3c6bf7,
+           0x52edd3cfec205090, 0xfc8e3370b171c315, 0x9f79ec1cdf33c0bc,
+           0x52b80462b7e072f9, 0x3216edfad69d8286, 0x45efda30062c904b,
+           0xde9483fe82609c40, 0xc4bae94e8d757c0f, 0x693f603446fb64e6,
+           0xd77ba2e13e47d589, 0xac730ac471f57a8e, 0x90c7d0d2a8aa883c,
+           0x3adf5823d1051252, 0xa96c56ed56947466, 0xada6b728b9b84f27,
+           0x2d52c2213e1497ab, 0x5428920ecca684b1, 0x6f8c8820840f716e,
+           0x8aac4c04213d26aa, 0x89f5805801f25a66, 0xb6715b7275106bc1,
+           0x8ec585926ed7af58, 0x14041ab000c9c396, 0xdb402f4b0fd38776,
+           0x76c882042e57f707, 0x5142eb4c19644e7d, 0x34affa8555d23fd9,
+           0xf96089370f7fa0a7);
+  VCMP_U64(177, v4, 0xa41351c301c72b5b, 0x64d7a5514d544e52, 0xd31ac04eea8ecc07,
+           0x891a1820b423c29c, 0xa30da5c56e052f67, 0x5d2c78d9927dfa33,
+           0x3e0efee7a99a28e7, 0x7409095aa2433e2e, 0x2b707d3fbaef7019,
+           0x9d5e63fed3019ea6, 0x7c917722900ef4d8, 0x42cb1e2132c3d7d5,
+           0x45887508688c93b2, 0x708ca6623c11c1ff, 0xdb0427f14bb4d5ba,
+           0xc31b51ef18e6dc16, 0x5e0f5c76fdd72450, 0x9ef5b07ca6742028,
+           0x201b60e0fbbc4acd, 0xc826aff176ba9a29, 0x4a2bb5a96b1f24f5,
+           0xecd584f402152e19, 0xbad7cab9c4062ffc, 0x53112b0cc2123035,
+           0xce4722d4b56cd330, 0x928220385ce8c56d, 0x180002d7d73b1ae2,
+           0xd13e73308658ad1f, 0x23def41d77db2d38, 0xa311951efe71188d,
+           0xb0899dfea0b44c26);
+  VCMP_U64(178, v5, 0x511e175802d24608, 0xbf1d53ca3e3c6bf7, 0x52edd3cfec205090,
+           0xfc8e3370b171c315, 0x9f79ec1cdf33c0bc, 0x52b80462b7e072f9,
+           0x3216edfad69d8286, 0x45efda30062c904b, 0xde9483fe82609c40,
+           0xc4bae94e8d757c0f, 0x693f603446fb64e6, 0xd77ba2e13e47d589,
+           0xac730ac471f57a8e, 0x90c7d0d2a8aa883c, 0x3adf5823d1051252,
+           0xa96c56ed56947466, 0xada6b728b9b84f27, 0x2d52c2213e1497ab,
+           0x5428920ecca684b1, 0x6f8c8820840f716e, 0x8aac4c04213d26aa,
+           0x89f5805801f25a66, 0xb6715b7275106bc1, 0x8ec585926ed7af58,
+           0x14041ab000c9c396, 0xdb402f4b0fd38776, 0x76c882042e57f707,
+           0x5142eb4c19644e7d, 0x34affa8555d23fd9, 0xf96089370f7fa0a7);
+  VCMP_U64(179, v6, 0x64d7a5514d544e52, 0xd31ac04eea8ecc07, 0x891a1820b423c29c,
+           0xa30da5c56e052f67, 0x5d2c78d9927dfa33, 0x3e0efee7a99a28e7,
+           0x7409095aa2433e2e, 0x2b707d3fbaef7019, 0x9d5e63fed3019ea6,
+           0x7c917722900ef4d8, 0x42cb1e2132c3d7d5, 0x45887508688c93b2,
+           0x708ca6623c11c1ff, 0xdb0427f14bb4d5ba, 0xc31b51ef18e6dc16,
+           0x5e0f5c76fdd72450, 0x9ef5b07ca6742028, 0x201b60e0fbbc4acd,
+           0xc826aff176ba9a29, 0x4a2bb5a96b1f24f5, 0xecd584f402152e19,
+           0xbad7cab9c4062ffc, 0x53112b0cc2123035, 0xce4722d4b56cd330,
+           0x928220385ce8c56d, 0x180002d7d73b1ae2, 0xd13e73308658ad1f,
+           0x23def41d77db2d38, 0xa311951efe71188d, 0xb0899dfea0b44c26);
+  VCMP_U64(180, v7, 0xbf1d53ca3e3c6bf7, 0x52edd3cfec205090, 0xfc8e3370b171c315,
+           0x9f79ec1cdf33c0bc, 0x52b80462b7e072f9, 0x3216edfad69d8286,
+           0x45efda30062c904b, 0xde9483fe82609c40, 0xc4bae94e8d757c0f,
+           0x693f603446fb64e6, 0xd77ba2e13e47d589, 0xac730ac471f57a8e,
+           0x90c7d0d2a8aa883c, 0x3adf5823d1051252, 0xa96c56ed56947466,
+           0xada6b728b9b84f27, 0x2d52c2213e1497ab, 0x5428920ecca684b1,
+           0x6f8c8820840f716e, 0x8aac4c04213d26aa, 0x89f5805801f25a66,
+           0xb6715b7275106bc1, 0x8ec585926ed7af58, 0x14041ab000c9c396,
+           0xdb402f4b0fd38776, 0x76c882042e57f707, 0x5142eb4c19644e7d,
+           0x34affa8555d23fd9, 0xf96089370f7fa0a7);
+  VCMP_U64(181, v8, 0xd31ac04eea8ecc07, 0x891a1820b423c29c, 0xa30da5c56e052f67,
+           0x5d2c78d9927dfa33, 0x3e0efee7a99a28e7, 0x7409095aa2433e2e,
+           0x2b707d3fbaef7019, 0x9d5e63fed3019ea6, 0x7c917722900ef4d8,
+           0x42cb1e2132c3d7d5, 0x45887508688c93b2, 0x708ca6623c11c1ff,
+           0xdb0427f14bb4d5ba, 0xc31b51ef18e6dc16, 0x5e0f5c76fdd72450,
+           0x9ef5b07ca6742028, 0x201b60e0fbbc4acd, 0xc826aff176ba9a29,
+           0x4a2bb5a96b1f24f5, 0xecd584f402152e19, 0xbad7cab9c4062ffc,
+           0x53112b0cc2123035, 0xce4722d4b56cd330, 0x928220385ce8c56d,
+           0x180002d7d73b1ae2, 0xd13e73308658ad1f, 0x23def41d77db2d38,
+           0xa311951efe71188d, 0xb0899dfea0b44c26);
+
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  VCLEAR(v5);
+  VCLEAR(v6);
+  VCLEAR(v7);
+  VCLEAR(v8);
+  stride = 24;
+  VSET(22, e64, m1);
+  asm volatile("vlsseg8e64.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U64(182, v1, 0xfa3a99086b4b64aa, 0xa41351c301c72b5b, 0xbf1d53ca3e3c6bf7,
+           0x891a1820b423c29c, 0x9f79ec1cdf33c0bc, 0x3e0efee7a99a28e7,
+           0x45efda30062c904b, 0x9d5e63fed3019ea6, 0x693f603446fb64e6,
+           0x45887508688c93b2, 0x90c7d0d2a8aa883c, 0xc31b51ef18e6dc16,
+           0xada6b728b9b84f27, 0x201b60e0fbbc4acd, 0x6f8c8820840f716e,
+           0xecd584f402152e19, 0xb6715b7275106bc1, 0xce4722d4b56cd330,
+           0xdb402f4b0fd38776, 0xd13e73308658ad1f, 0x34affa8555d23fd9,
+           0xb0899dfea0b44c26);
+  VCMP_U64(183, v2, 0x57bb4a671118fdc0, 0x511e175802d24608, 0xd31ac04eea8ecc07,
+           0xfc8e3370b171c315, 0x5d2c78d9927dfa33, 0x3216edfad69d8286,
+           0x2b707d3fbaef7019, 0xc4bae94e8d757c0f, 0x42cb1e2132c3d7d5,
+           0xac730ac471f57a8e, 0xdb0427f14bb4d5ba, 0xa96c56ed56947466,
+           0x9ef5b07ca6742028, 0x5428920ecca684b1, 0x4a2bb5a96b1f24f5,
+           0x89f5805801f25a66, 0x53112b0cc2123035, 0x14041ab000c9c396,
+           0x180002d7d73b1ae2, 0x5142eb4c19644e7d, 0xa311951efe71188d);
+  VCMP_U64(184, v3, 0xbb8df43b65bac0d2, 0x64d7a5514d544e52, 0x52edd3cfec205090,
+           0xa30da5c56e052f67, 0x52b80462b7e072f9, 0x7409095aa2433e2e,
+           0xde9483fe82609c40, 0x7c917722900ef4d8, 0xd77ba2e13e47d589,
+           0x708ca6623c11c1ff, 0x3adf5823d1051252, 0x5e0f5c76fdd72450,
+           0x2d52c2213e1497ab, 0xc826aff176ba9a29, 0x8aac4c04213d26aa,
+           0xbad7cab9c4062ffc, 0x8ec585926ed7af58, 0x928220385ce8c56d,
+           0x76c882042e57f707, 0x23def41d77db2d38, 0xf96089370f7fa0a7);
+  VCMP_U64(185, v4, 0xa41351c301c72b5b, 0xbf1d53ca3e3c6bf7, 0x891a1820b423c29c,
+           0x9f79ec1cdf33c0bc, 0x3e0efee7a99a28e7, 0x45efda30062c904b,
+           0x9d5e63fed3019ea6, 0x693f603446fb64e6, 0x45887508688c93b2,
+           0x90c7d0d2a8aa883c, 0xc31b51ef18e6dc16, 0xada6b728b9b84f27,
+           0x201b60e0fbbc4acd, 0x6f8c8820840f716e, 0xecd584f402152e19,
+           0xb6715b7275106bc1, 0xce4722d4b56cd330, 0xdb402f4b0fd38776,
+           0xd13e73308658ad1f, 0x34affa8555d23fd9, 0xb0899dfea0b44c26);
+  VCMP_U64(186, v5, 0x511e175802d24608, 0xd31ac04eea8ecc07, 0xfc8e3370b171c315,
+           0x5d2c78d9927dfa33, 0x3216edfad69d8286, 0x2b707d3fbaef7019,
+           0xc4bae94e8d757c0f, 0x42cb1e2132c3d7d5, 0xac730ac471f57a8e,
+           0xdb0427f14bb4d5ba, 0xa96c56ed56947466, 0x9ef5b07ca6742028,
+           0x5428920ecca684b1, 0x4a2bb5a96b1f24f5, 0x89f5805801f25a66,
+           0x53112b0cc2123035, 0x14041ab000c9c396, 0x180002d7d73b1ae2,
+           0x5142eb4c19644e7d, 0xa311951efe71188d);
+  VCMP_U64(187, v6, 0x64d7a5514d544e52, 0x52edd3cfec205090, 0xa30da5c56e052f67,
+           0x52b80462b7e072f9, 0x7409095aa2433e2e, 0xde9483fe82609c40,
+           0x7c917722900ef4d8, 0xd77ba2e13e47d589, 0x708ca6623c11c1ff,
+           0x3adf5823d1051252, 0x5e0f5c76fdd72450, 0x2d52c2213e1497ab,
+           0xc826aff176ba9a29, 0x8aac4c04213d26aa, 0xbad7cab9c4062ffc,
+           0x8ec585926ed7af58, 0x928220385ce8c56d, 0x76c882042e57f707,
+           0x23def41d77db2d38, 0xf96089370f7fa0a7);
+  VCMP_U64(188, v7, 0xbf1d53ca3e3c6bf7, 0x891a1820b423c29c, 0x9f79ec1cdf33c0bc,
+           0x3e0efee7a99a28e7, 0x45efda30062c904b, 0x9d5e63fed3019ea6,
+           0x693f603446fb64e6, 0x45887508688c93b2, 0x90c7d0d2a8aa883c,
+           0xc31b51ef18e6dc16, 0xada6b728b9b84f27, 0x201b60e0fbbc4acd,
+           0x6f8c8820840f716e, 0xecd584f402152e19, 0xb6715b7275106bc1,
+           0xce4722d4b56cd330, 0xdb402f4b0fd38776, 0xd13e73308658ad1f,
+           0x34affa8555d23fd9, 0xb0899dfea0b44c26);
+  VCMP_U64(189, v8, 0xd31ac04eea8ecc07, 0xfc8e3370b171c315, 0x5d2c78d9927dfa33,
+           0x3216edfad69d8286, 0x2b707d3fbaef7019, 0xc4bae94e8d757c0f,
+           0x42cb1e2132c3d7d5, 0xac730ac471f57a8e, 0xdb0427f14bb4d5ba,
+           0xa96c56ed56947466, 0x9ef5b07ca6742028, 0x5428920ecca684b1,
+           0x4a2bb5a96b1f24f5, 0x89f5805801f25a66, 0x53112b0cc2123035,
+           0x14041ab000c9c396, 0x180002d7d73b1ae2, 0x5142eb4c19644e7d,
+           0xa311951efe71188d);
+
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  VCLEAR(v5);
+  VCLEAR(v6);
+  VCLEAR(v7);
+  VCLEAR(v8);
+  stride = 32;
+  VSET(16, e64, m1);
+  asm volatile("vlsseg8e64.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  VCMP_U64(190, v1, 0xfa3a99086b4b64aa, 0x511e175802d24608, 0x52edd3cfec205090,
+           0x9f79ec1cdf33c0bc, 0x3216edfad69d8286, 0xde9483fe82609c40,
+           0x693f603446fb64e6, 0xac730ac471f57a8e, 0x3adf5823d1051252,
+           0xada6b728b9b84f27, 0x5428920ecca684b1, 0x8aac4c04213d26aa,
+           0xb6715b7275106bc1, 0x14041ab000c9c396, 0x76c882042e57f707,
+           0x34affa8555d23fd9);
+  VCMP_U64(191, v2, 0x57bb4a671118fdc0, 0x64d7a5514d544e52, 0x891a1820b423c29c,
+           0x5d2c78d9927dfa33, 0x7409095aa2433e2e, 0x9d5e63fed3019ea6,
+           0x42cb1e2132c3d7d5, 0x708ca6623c11c1ff, 0xc31b51ef18e6dc16,
+           0x9ef5b07ca6742028, 0xc826aff176ba9a29, 0xecd584f402152e19,
+           0x53112b0cc2123035, 0x928220385ce8c56d, 0xd13e73308658ad1f,
+           0xa311951efe71188d);
+  VCMP_U64(192, v3, 0xbb8df43b65bac0d2, 0xbf1d53ca3e3c6bf7, 0xfc8e3370b171c315,
+           0x52b80462b7e072f9, 0x45efda30062c904b, 0xc4bae94e8d757c0f,
+           0xd77ba2e13e47d589, 0x90c7d0d2a8aa883c, 0xa96c56ed56947466,
+           0x2d52c2213e1497ab, 0x6f8c8820840f716e, 0x89f5805801f25a66,
+           0x8ec585926ed7af58, 0xdb402f4b0fd38776, 0x5142eb4c19644e7d,
+           0xf96089370f7fa0a7);
+  VCMP_U64(193, v4, 0xa41351c301c72b5b, 0xd31ac04eea8ecc07, 0xa30da5c56e052f67,
+           0x3e0efee7a99a28e7, 0x2b707d3fbaef7019, 0x7c917722900ef4d8,
+           0x45887508688c93b2, 0xdb0427f14bb4d5ba, 0x5e0f5c76fdd72450,
+           0x201b60e0fbbc4acd, 0x4a2bb5a96b1f24f5, 0xbad7cab9c4062ffc,
+           0xce4722d4b56cd330, 0x180002d7d73b1ae2, 0x23def41d77db2d38,
+           0xb0899dfea0b44c26);
+  VCMP_U64(194, v5, 0x511e175802d24608, 0x52edd3cfec205090, 0x9f79ec1cdf33c0bc,
+           0x3216edfad69d8286, 0xde9483fe82609c40, 0x693f603446fb64e6,
+           0xac730ac471f57a8e, 0x3adf5823d1051252, 0xada6b728b9b84f27,
+           0x5428920ecca684b1, 0x8aac4c04213d26aa, 0xb6715b7275106bc1,
+           0x14041ab000c9c396, 0x76c882042e57f707, 0x34affa8555d23fd9);
+  VCMP_U64(195, v6, 0x64d7a5514d544e52, 0x891a1820b423c29c, 0x5d2c78d9927dfa33,
+           0x7409095aa2433e2e, 0x9d5e63fed3019ea6, 0x42cb1e2132c3d7d5,
+           0x708ca6623c11c1ff, 0xc31b51ef18e6dc16, 0x9ef5b07ca6742028,
+           0xc826aff176ba9a29, 0xecd584f402152e19, 0x53112b0cc2123035,
+           0x928220385ce8c56d, 0xd13e73308658ad1f, 0xa311951efe71188d);
+  VCMP_U64(196, v7, 0xbf1d53ca3e3c6bf7, 0xfc8e3370b171c315, 0x52b80462b7e072f9,
+           0x45efda30062c904b, 0xc4bae94e8d757c0f, 0xd77ba2e13e47d589,
+           0x90c7d0d2a8aa883c, 0xa96c56ed56947466, 0x2d52c2213e1497ab,
+           0x6f8c8820840f716e, 0x89f5805801f25a66, 0x8ec585926ed7af58,
+           0xdb402f4b0fd38776, 0x5142eb4c19644e7d, 0xf96089370f7fa0a7);
+  VCMP_U64(197, v8, 0xd31ac04eea8ecc07, 0xa30da5c56e052f67, 0x3e0efee7a99a28e7,
+           0x2b707d3fbaef7019, 0x7c917722900ef4d8, 0x45887508688c93b2,
+           0xdb0427f14bb4d5ba, 0x5e0f5c76fdd72450, 0x201b60e0fbbc4acd,
+           0x4a2bb5a96b1f24f5, 0xbad7cab9c4062ffc, 0xce4722d4b56cd330,
+           0x180002d7d73b1ae2, 0x23def41d77db2d38, 0xb0899dfea0b44c26);
+}
+
+// Segment-4
+void TEST_CASE3_32_m(void) {
+  VSET(-1, e32, m1);
+  volatile uint32_t INP1[] = {
+      0xe19afa6b, 0x8c10145c, 0xbca44cc5, 0x11ffa54e, 0x82f92af6, 0x9af29daa,
+      0x956eb527, 0x575c2e05, 0x68fb4cc5, 0xcf7a1d98, 0x53a0be4e, 0x26439a12,
+      0x785cc853, 0x35659121, 0xf7a96b8c, 0xa87678a2, 0xb11d757e, 0x67dd4037,
+      0xd29ad01e, 0xb7600abf, 0x2e572002, 0xaadc6195, 0xcefce71b, 0x64d90d0c,
+      0x6c3b54b0, 0xcc6da682, 0xd8b7ae76, 0x8533b185, 0xa2cd798c, 0x2a4339cc,
+      0xcf9238fb, 0x7e70281b, 0xdf162ee9, 0x4f2ea60f, 0x4b32bcdd, 0xbf3b8546,
+      0x52b26ff5, 0x18cbcecd, 0xc364c8f8, 0x5bf0c67b, 0x60914005, 0x93265d9d,
+      0xcff3c77d, 0x788529c3, 0xdda63ceb, 0x4edd7f48, 0xddcd4d07, 0x3266d631,
+      0x3b2f25a6, 0x7bfd8a81, 0x9db64ef5, 0xa06a42d4, 0x687f8a39, 0xb9272633,
+      0xb009319e, 0xf542d689, 0x45ef05c9, 0xf547c96e, 0x2a143e76, 0x17a38eec,
+      0x9a73626c, 0xca064493, 0x582140dd, 0x97df3c7a};
+
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  stride = 16;
+  VSET(2, e32, m1);
+  VLOAD_8(v0, 0x0F, 0xAA);
+  VSET(16, e32, m1);
+  asm volatile("vlsseg4e32.v v1, (%0), %1, v0.t" ::"r"(INP1), "r"(stride));
+  VCMP_U32(198, v1, 0xe19afa6b, 0x82f92af6, 0x68fb4cc5, 0x785cc853, 0, 0, 0, 0,
+           0, 0x52b26ff5, 0, 0xdda63ceb, 0, 0x687f8a39, 0, 0x9a73626c);
+  VCMP_U32(199, v2, 0x8c10145c, 0x9af29daa, 0xcf7a1d98, 0x35659121, 0, 0, 0, 0,
+           0, 0x18cbcecd, 0, 0x4edd7f48, 0, 0xb9272633, 0, 0xca064493);
+  VCMP_U32(200, v3, 0xbca44cc5, 0x956eb527, 0x53a0be4e, 0xf7a96b8c, 0, 0, 0, 0,
+           0, 0xc364c8f8, 0, 0xddcd4d07, 0, 0xb009319e, 0, 0x582140dd);
+  VCMP_U32(201, v4, 0x11ffa54e, 0x575c2e05, 0x26439a12, 0xa87678a2, 0, 0, 0, 0,
+           0, 0x5bf0c67b, 0, 0x3266d631, 0, 0xf542d689, 0, 0x97df3c7a);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1_8();
+  TEST_CASE2_8();
+  TEST_CASE3_8();
+  TEST_CASE4_8();
+
+  TEST_CASE1_16();
+  TEST_CASE2_16();
+  TEST_CASE3_16();
+  TEST_CASE4_16();
+
+  TEST_CASE1_32();
+  TEST_CASE2_32();
+  TEST_CASE3_32();
+  TEST_CASE4_32();
+
+  TEST_CASE1_64();
+  TEST_CASE2_64();
+  TEST_CASE3_64();
+  TEST_CASE4_64();
+
+  //  TEST_CASE3_32_m(); // Todo: fix masked mem ops
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vluxei.c b/apps/riscv-tests/isa/rv64uv/vluxei.c
new file mode 100644
index 0000000..dea1f33
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vluxei.c
@@ -0,0 +1,206 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+
+#include "vector_macros.h"
+
+#define AXI_DWIDTH 128
+
+static volatile uint8_t ALIGNED_I8[16] __attribute__((aligned(AXI_DWIDTH))) = {
+    0xe0, 0xd3, 0x40, 0xd1, 0x84, 0x48, 0x89, 0x88,
+    0x88, 0xae, 0x08, 0x91, 0x02, 0x59, 0x11, 0x89};
+
+static volatile uint16_t ALIGNED_I16[16]
+    __attribute__((aligned(AXI_DWIDTH))) = {
+        0x05e0, 0xbbd3, 0x3840, 0x8cd1, 0x9384, 0x7548, 0x3489, 0x9388,
+        0x8188, 0x11ae, 0x5808, 0x4891, 0x4902, 0x8759, 0x1111, 0x1989};
+
+static volatile uint32_t ALIGNED_I32[16]
+    __attribute__((aligned(AXI_DWIDTH))) = {
+        0x9fe41920, 0xf9aa71f0, 0xa11a9384, 0x99991348, 0x9fa831c7, 0x38197598,
+        0x18931795, 0x81937598, 0x18747547, 0x3eeeeeee, 0x90139301, 0xab8b9148,
+        0x90318509, 0x31897598, 0x83195999, 0x89139848};
+
+static volatile uint64_t ALIGNED_I64[16]
+    __attribute__((aligned(AXI_DWIDTH))) = {
+        0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3, 0xa11a9384a7163840,
+        0x99991348a9f38cd1, 0x9fa831c7a11a9384, 0x3819759853987548,
+        0x1893179501093489, 0x81937598aa819388, 0x1874754791888188,
+        0x3eeeeeeee33111ae, 0x9013930148815808, 0xab8b914891484891,
+        0x9031850931584902, 0x3189759837598759, 0x8319599991911111,
+        0x8913984898951989};
+
+// EEW destination == EEW indexes
+void TEST_CASE1(void) {
+  VSET(2, e8, m1);
+  VLOAD_8(v2, 1, 15);
+  asm volatile("vluxei8.v v1, (%0), v2" ::"r"(&ALIGNED_I8[0]));
+  VCMP_U8(1, v1, 0xd3, 0x89);
+
+  VSET(2, e16, m1);
+  VLOAD_16(v2, 2, 30);
+  asm volatile("vluxei16.v v1, (%0), v2" ::"r"(&ALIGNED_I16[0]));
+  VCMP_U16(2, v1, 0xbbd3, 0x1989);
+
+  VSET(2, e32, m1);
+  VLOAD_32(v2, 4, 60);
+  asm volatile("vluxei32.v v1, (%0), v2" ::"r"(&ALIGNED_I32[0]));
+  VCMP_U32(3, v1, 0xf9aa71f0, 0x89139848);
+
+  VSET(2, e64, m1);
+  VLOAD_64(v2, 8, 120);
+  asm volatile("vluxei64.v v1, (%0), v2" ::"r"(&ALIGNED_I64[0]));
+  VCMP_U64(4, v1, 0xf9aa71f0c394bbd3, 0x8913984898951989);
+}
+
+// EEW Destination > EEW indexes
+void TEST_CASE2(void) {
+  VSET(2, e16, m1);
+  VLOAD_8(v2, 2, 30);
+  asm volatile("vluxei8.v v1, (%0), v2" ::"r"(&ALIGNED_I16[0]));
+  VCMP_U16(5, v1, 0xbbd3, 0x1989);
+
+  VSET(2, e32, m1);
+  VLOAD_16(v2, 4, 60);
+  asm volatile("vluxei16.v v1, (%0), v2" ::"r"(&ALIGNED_I32[0]));
+  VCMP_U32(6, v1, 0xf9aa71f0, 0x89139848);
+
+  VSET(2, e64, m1);
+  VLOAD_32(v2, 8, 120);
+  asm volatile("vluxei32.v v1, (%0), v2" ::"r"(&ALIGNED_I64[0]));
+  VCMP_U64(7, v1, 0xf9aa71f0c394bbd3, 0x8913984898951989);
+}
+
+// EEW Destination < EEW indexes
+void TEST_CASE3(void) {
+  VSET(2, e8, m1);
+  VLOAD_16(v2, 1, 15);
+  asm volatile("vluxei16.v v1, (%0), v2" ::"r"(&ALIGNED_I8[0]));
+  VCMP_U8(8, v1, 0xd3, 0x89);
+
+  VSET(2, e16, m1);
+  VLOAD_32(v2, 2, 30);
+  asm volatile("vluxei32.v v1, (%0), v2" ::"r"(&ALIGNED_I16[0]));
+  VCMP_U16(9, v1, 0xbbd3, 0x1989);
+
+  VSET(2, e32, m1);
+  VLOAD_64(v2, 4, 60);
+  asm volatile("vluxei64.v v1, (%0), v2" ::"r"(&ALIGNED_I32[0]));
+  VCMP_U32(10, v1, 0xf9aa71f0, 0x89139848);
+}
+
+// Naive, masked
+void TEST_CASE4(void) {
+  VSET(2, e8, m1);
+  VLOAD_8(v1, 99, 99);
+  VLOAD_8(v2, 1, 15);
+  VLOAD_8(v0, 0xAA);
+  asm volatile("vluxei8.v v1, (%0), v2, v0.t" ::"r"(&ALIGNED_I8[0]));
+  VCMP_U8(11, v1, 99, 0x89);
+
+  VSET(2, e16, m1);
+  VLOAD_16(v1, 999, 999);
+  VLOAD_16(v2, 2, 30);
+  VLOAD_8(v0, 0xAA);
+  asm volatile("vluxei16.v v1, (%0), v2, v0.t" ::"r"(&ALIGNED_I16[0]));
+  VCMP_U16(12, v1, 999, 0x1989);
+
+  VSET(2, e32, m1);
+  VLOAD_32(v1, 999, 999);
+  VLOAD_32(v2, 4, 60);
+  VLOAD_8(v0, 0xAA);
+  asm volatile("vluxei32.v v1, (%0), v2, v0.t" ::"r"(&ALIGNED_I32[0]));
+  VCMP_U32(13, v1, 999, 0x89139848);
+
+  VSET(2, e64, m1);
+  VLOAD_64(v1, 999, 999);
+  VLOAD_64(v2, 8, 120);
+  VLOAD_8(v0, 0xAA);
+  asm volatile("vluxei64.v v1, (%0), v2, v0.t" ::"r"(&ALIGNED_I64[0]));
+  VCMP_U64(14, v1, 999, 0x8913984898951989);
+}
+
+// EEW destination == EEW indexes, many elements
+void TEST_CASE5(void) {
+  VSET(12, e8, m1);
+  VLOAD_8(v2, 1, 2, 3, 4, 5, 7, 8, 9, 11, 12, 13, 15);
+  asm volatile("vluxei8.v v1, (%0), v2" ::"r"(&ALIGNED_I8[0]));
+  VCMP_U8(15, v1, 0xd3, 0x40, 0xd1, 0x84, 0x48, 0x88, 0x88, 0xae, 0x91, 0x02,
+          0x59, 0x89);
+
+  VSET(12, e16, m1);
+  VLOAD_16(v2, 2, 4, 6, 8, 10, 14, 16, 18, 22, 24, 26, 30);
+  asm volatile("vluxei16.v v1, (%0), v2" ::"r"(&ALIGNED_I16[0]));
+  VCMP_U16(16, v1, 0xbbd3, 0x3840, 0x8cd1, 0x9384, 0x7548, 0x9388, 0x8188,
+           0x11ae, 0x4891, 0x4902, 0x8759, 0x1989);
+
+  VSET(12, e32, m1);
+  VLOAD_32(v2, 4, 8, 12, 16, 20, 28, 32, 36, 44, 48, 52, 60);
+  asm volatile("vluxei32.v v1, (%0), v2" ::"r"(&ALIGNED_I32[0]));
+  VCMP_U32(17, v1, 0xf9aa71f0, 0xa11a9384, 0x99991348, 0x9fa831c7, 0x38197598,
+           0x81937598, 0x18747547, 0x3eeeeeee, 0xab8b9148, 0x90318509,
+           0x31897598, 0x89139848);
+
+  VSET(12, e64, m1);
+  VLOAD_64(v2, 8, 16, 24, 32, 40, 56, 64, 72, 88, 96, 104, 120);
+  asm volatile("vluxei64.v v1, (%0), v2" ::"r"(&ALIGNED_I64[0]));
+  VCMP_U64(18, v1, 0xf9aa71f0c394bbd3, 0xa11a9384a7163840, 0x99991348a9f38cd1,
+           0x9fa831c7a11a9384, 0x3819759853987548, 0x81937598aa819388,
+           0x1874754791888188, 0x3eeeeeeee33111ae, 0xab8b914891484891,
+           0x9031850931584902, 0x3189759837598759, 0x8913984898951989);
+}
+
+// Test vstart
+void TEST_CASE6(void) {
+  VSET(-1, e8, m1);
+  VCLEAR(v1);
+  VSET(5, e8, m1);
+  VLOAD_8(v2, 1, 15, 1, 3, 10);
+  // Modify vstart val
+  asm volatile("csrs vstart, %0" ::"r"(1));
+  asm volatile("vluxei8.v v1, (%0), v2" ::"r"(&ALIGNED_I8[0]));
+  VCMP_U8(19, v1, 0, 0x89, 0xd3, 0xd1, 0x08);
+
+  VSET(-1, e16, m1);
+  VCLEAR(v1);
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30);
+  asm volatile("csrs vstart, %0" ::"r"(5));
+  asm volatile("vluxei16.v v1, (%0), v2" ::"r"(&ALIGNED_I16[0]));
+  VCMP_U16(20, v1, 0, 0, 0, 0, 0, 0x7548, 0x3489, 0x9388, 0x8188, 0x11ae,
+           0x5808, 0x4891, 0x4902, 0x8759, 0x1111, 0x1989);
+
+  VSET(-1, e32, m1);
+  VCLEAR(v1);
+  VSET(3, e32, m1);
+  VLOAD_32(v2, 4, 60, 4);
+  asm volatile("csrs vstart, %0" ::"r"(2));
+  asm volatile("vluxei32.v v1, (%0), v2" ::"r"(&ALIGNED_I32[0]));
+  VCMP_U32(21, v1, 0, 0, 0xf9aa71f0);
+
+  VSET(-1, e64, m1);
+  VCLEAR(v1);
+  VSET(8, e64, m1);
+  VLOAD_64(v2, 8, 120, 8, 8, 8, 8, 120, 0);
+  asm volatile("csrs vstart, %0" ::"r"(3));
+  asm volatile("vluxei64.v v1, (%0), v2" ::"r"(&ALIGNED_I64[0]));
+  VCMP_U64(22, v1, 0, 0, 0, 0xf9aa71f0c394bbd3, 0xf9aa71f0c394bbd3,
+           0xf9aa71f0c394bbd3, 0x8913984898951989, 0x9fe419208f2e05e0);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+
+  TEST_CASE6();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vluxseg.c b/apps/riscv-tests/isa/rv64uv/vluxseg.c
new file mode 100644
index 0000000..2537b5d
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vluxseg.c
@@ -0,0 +1,145 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+
+#include "vector_macros.h"
+
+// Segment-2
+void TEST_CASE1_8(void) {
+  VSET(4, e8, m1);
+  volatile uint8_t INP1[] = {0x9f, 0xe4, 0x19, 0x20, 0x8f, 0x2e, 0x05, 0xe0,
+                             0xf9, 0xaa, 0x71, 0xf0, 0xc3, 0x94, 0xbb, 0xd3};
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VLOAD_8(v24, 1, 1, 0, 2);
+  asm volatile("vluxseg2ei8.v v1, (%0), v24" ::"r"(INP1));
+  VCMP_U8(1, v1, 0xe4, 0xe4, 0x9f, 0x19);
+  VCMP_U8(2, v2, 0x19, 0x19, 0xe4, 0x20);
+}
+
+// Segment-3
+void TEST_CASE2_8(void) {
+  VSET(4, e8, m1);
+  volatile uint8_t INP1[] = {0x9f, 0xe4, 0x19, 0x20, 0x8f, 0x2e, 0x05, 0xe0,
+                             0xf9, 0xaa, 0x71, 0xf0, 0xc3, 0x94, 0xbb, 0xd3};
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VLOAD_16(v24, 0, 1, 0, 3);
+  asm volatile("vluxseg3ei16.v v1, (%0), v24" ::"r"(INP1));
+  VCMP_U8(3, v1, 0x9f, 0xe4, 0x9f, 0x20);
+  VCMP_U8(4, v2, 0xe4, 0x19, 0xe4, 0x8f);
+  VCMP_U8(5, v3, 0x19, 0x20, 0x19, 0x2e);
+}
+
+// Segment-4
+void TEST_CASE3_8(void) {
+  VSET(4, e8, m1);
+  volatile uint8_t INP1[] = {0x9f, 0xe4, 0x19, 0x20, 0x8f, 0x2e, 0x05, 0xe0,
+                             0xf9, 0xaa, 0x71, 0xf0, 0xc3, 0x94, 0xbb, 0xd3};
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  VLOAD_64(v24, 1, 1, 0, 5);
+  asm volatile("vluxseg4ei64.v v1, (%0), v24" ::"r"(INP1));
+  VCMP_U8(6, v1, 0xe4, 0xe4, 0x9f, 0x2e);
+  VCMP_U8(7, v2, 0x19, 0x19, 0xe4, 0x05);
+  VCMP_U8(8, v3, 0x20, 0x20, 0x19, 0xe0);
+  VCMP_U8(9, v4, 0x8f, 0x8f, 0x20, 0xf9);
+}
+
+// Segment-4 for 64-bit
+void TEST_CASE3_64(void) {
+  VSET(4, e64, m1);
+  volatile uint64_t INP1[] = {
+      0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3, 0x123456789abcdef0,
+      0x13572468369b48ac, 0xdeadbeefcafebabe, 0x0123456789abcdef,
+      0x55aa55aa77889900, 0xabcdef1234567890, 0xfeedfacecafebabe,
+      0x123456789abcdef0, 0x1357246855aa55aa, 0x369b48acdeadbeef,
+      0xcafebabe12345678, 0xabcdef0987654321, 0x012345670abcdef1,
+      0x987654321fedcba0};
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  VLOAD_8(v24, 8, 8, 0, 40);
+  asm volatile("vluxseg4ei8.v v1, (%0), v24" ::"r"(INP1));
+  VCMP_U64(10, v1, 0xf9aa71f0c394bbd3, 0xf9aa71f0c394bbd3, 0x9fe419208f2e05e0,
+           0x0123456789abcdef);
+  VCMP_U64(11, v2, 0x123456789abcdef0, 0x123456789abcdef0, 0xf9aa71f0c394bbd3,
+           0x55aa55aa77889900);
+  VCMP_U64(12, v3, 0x13572468369b48ac, 0x13572468369b48ac, 0x123456789abcdef0,
+           0xabcdef1234567890);
+  VCMP_U64(13, v4, 0xdeadbeefcafebabe, 0xdeadbeefcafebabe, 0x13572468369b48ac,
+           0xfeedfacecafebabe);
+}
+
+// Segment-8 for 64-bit
+void TEST_CASE4_64_m(void) {
+  VSET(2, e64, m1);
+  volatile uint64_t INP1[] = {
+      0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3, 0x123456789abcdef0,
+      0x13572468369b48ac, 0xdeadbeefcafebabe, 0x0123456789abcdef,
+      0x55aa55aa77889900, 0xabcdef1234567890, 0xfeedfacecafebabe,
+      0x123456789abcdef0, 0x1357246855aa55aa, 0x369b48acdeadbeef,
+      0xcafebabe12345678, 0xabcdef0987654321, 0x012345670abcdef1,
+      0x987654321fedcba0};
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  VCLEAR(v5);
+  VCLEAR(v6);
+  VCLEAR(v7);
+  VCLEAR(v8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VLOAD_8(v24, 8, 32);
+  asm volatile("vluxseg8ei8.v v1, (%0), v24, v0.t" ::"r"(INP1));
+  VCMP_U64(14, v1, 0, 0xdeadbeefcafebabe);
+  VCMP_U64(15, v2, 0, 0x0123456789abcdef);
+  VCMP_U64(16, v3, 0, 0x55aa55aa77889900);
+  VCMP_U64(17, v4, 0, 0xabcdef1234567890);
+  VCMP_U64(18, v5, 0, 0xfeedfacecafebabe);
+  VCMP_U64(19, v6, 0, 0x123456789abcdef0);
+  VCMP_U64(20, v7, 0, 0x1357246855aa55aa);
+  VCMP_U64(21, v8, 0, 0x369b48acdeadbeef);
+
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  VCLEAR(v5);
+  VCLEAR(v6);
+  VCLEAR(v7);
+  VCLEAR(v8);
+  VLOAD_8(v0, 0xA1, 0xAA);
+  VLOAD_32(v24, 8, 32);
+  asm volatile("vluxseg8ei32.v v1, (%0), v24, v0.t" ::"r"(INP1));
+  VCMP_U64(22, v1, 0xf9aa71f0c394bbd3, 0);
+  VCMP_U64(23, v2, 0x123456789abcdef0, 0);
+  VCMP_U64(24, v3, 0x13572468369b48ac, 0);
+  VCMP_U64(25, v4, 0xdeadbeefcafebabe, 0);
+  VCMP_U64(26, v5, 0x0123456789abcdef, 0);
+  VCMP_U64(27, v6, 0x55aa55aa77889900, 0);
+  VCMP_U64(28, v7, 0xabcdef1234567890, 0);
+  VCMP_U64(29, v8, 0xfeedfacecafebabe, 0);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1_8();
+  TEST_CASE2_8();
+  TEST_CASE3_8();
+
+  TEST_CASE3_64();
+
+  // Masked
+  TEST_CASE4_64_m();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vlx.c b/apps/riscv-tests/isa/rv64uv/vlx.c
new file mode 100644
index 0000000..a56f5b1
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vlx.c
@@ -0,0 +1,101 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(4, e8, m1);
+  VLOAD_U8(v2, 0, 1, 2, 3);
+  volatile uint8_t INP[] = {0xff, 0x00, 0x0f, 0xf0};
+  MEMBARRIER;
+  __asm__ volatile("vlxei8.v v1, (%0), v2" ::"r"(INP));
+  VEC_CMP_U8(1, v1, 0xff, 0x00, 0x0f, 0xf0);
+}
+
+// void TEST_CASE2(void) {
+//   VSET(4,e8,m1);
+//   VLOAD_8(v2,0,1,2,3);
+//   volatile int8_t INP[] = {0xff, 0x00, 0x0f, 0xf0};
+//   VLOAD_8(v0,0x5,0x0,0x0,0x0);
+//   CLEAR(v1);
+//   __asm__ volatile ("vlxei8.v v1, (%0), v2, v0.t"::"r" (INP));
+//   VEC_CMP_8(2,v1,0xff, 0x00, 0x0f,0x00);
+// }
+
+void TEST_CASE3(void) {
+  VSET(3, e16, m1);
+  VLOAD_U16(v2, 0, 2, 4);
+  volatile uint16_t INP[] = {0xffff, 0x0000, 0x0f0f, 0xf0f0};
+  MEMBARRIER;
+  __asm__ volatile("vlxei16.v v1, (%0), v2" ::"r"(INP));
+  VEC_CMP_U16(3, v1, 0xffff, 0x0000, 0x0f0f);
+}
+
+// void TEST_CASE4(void) {
+//   VSET(3,e16,m1);
+//   VLOAD_16(v2,0,2,4);
+//   volatile int16_t INP[] = {0xffff, 0x0000, 0x0f0f, 0xf0f0};
+//   VLOAD_16(v0,0x5,0x0,0x0,0x0);
+//   CLEAR(v1);
+//   __asm__ volatile ("vlxei16.v v1, (%0), v2, v0.t"::"r" (INP));
+//   VEC_CMP_16(4,v1,0xffff, 0x0000, 0x0f0f);
+// }
+
+void TEST_CASE5(void) {
+  VSET(4, e32, m1);
+  VLOAD_U32(v2, 0, 4, 8, 12);
+  volatile uint32_t INP[] = {0xffffffff, 0x00000000, 0x0f0f0f0f, 0xf0f0f0f0};
+  MEMBARRIER;
+  __asm__ volatile("vlxei32.v v1, (%0), v2" ::"r"(INP));
+  VEC_CMP_U32(5, v1, 0xffffffff, 0x00000000, 0x0f0f0f0f, 0xf0f0f0f0);
+}
+
+// void TEST_CASE6(void) {
+//   VSET(4,e32,m1);
+//   VLOAD_32(v2,0,4,8,12);
+//   volatile int32_t INP[] = {0xffffffff, 0x80000000, 0x0f0f0f0f, 0xf0f0f0f0};
+//   VLOAD_32(v0,0x5,0x0,0x0,0x0);
+//   CLEAR(v1);
+//   __asm__ volatile (" vlxei32.v v1, (%0), v2, v0.t \n"   :: "r" (INP));
+//   VEC_CMP_32(6,v1,0xffffffff, 0x0, 0x0f0f0f0f, 0x0);
+// }
+
+void TEST_CASE7(void) {
+  VSET(4, e64, m1);
+  VLOAD_U64(v2, 0, 8, 16, 24);
+  volatile uint64_t INP[] = {0xdeadbeefffffffff, 0xdeadbeef00000000,
+                             0xdeadbeef0f0f0f0f, 0xdeadbeeff0f0f0f0};
+  MEMBARRIER;
+  __asm__ volatile("vlxei64.v v1,(%0), v2" ::"r"(INP));
+  VEC_CMP_U64(7, v1, 0xdeadbeefffffffff, 0xdeadbeef00000000, 0xdeadbeef0f0f0f0f,
+              0xdeadbeeff0f0f0f0);
+}
+
+// void TEST_CASE8(void) {
+//   VSET(4,e64,m1);
+//   VLOAD_64(v2,0,8,16,24);
+//   volatile int64_t INP[] =
+//   {0xdeadbeefffffffff,0xdeadbeef00000000,0xdeadbeef0f0f0f0f,0xdeadbeeff0f0f0f0};
+//   VLOAD_64(v0,0x5,0x0,0x0,0x0);
+//   CLEAR(v1);
+//   __asm__ volatile ("vlxei64.v v1,(%0), v2, v0.t"::"r" (INP));
+//   VEC_CMP_64(8,v1,0xdeadbeefffffffff,0x0000000000000000,0xdeadbeef0f0f0f0f,0x0000000000000000);
+// }
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+  TEST_CASE1();
+  TEST_CASE3();
+  TEST_CASE5();
+  TEST_CASE7();
+  // TEST_CASE2();
+  // TEST_CASE4();
+  // TEST_CASE6();
+  // TEST_CASE8();
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vmacc.c b/apps/riscv-tests/isa/rv64uv/vmacc.c
new file mode 100644
index 0000000..8804dd5
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vmacc.c
@@ -0,0 +1,292 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1() {
+  VSET(16, e8, m1);
+  VLOAD_8(v3, 0x21, 0x75, 0x7f, 0x3a, 0x50, 0x6d, 0x3f, 0x3e, 0x74, 0x11, 0x29,
+          0xea, 0x14, 0xce, 0xb0, 0x37);
+  VLOAD_8(v2, 0xfe, 0xa7, 0x06, 0xaa, 0x35, 0x3c, 0x2c, 0x58, 0xa1, 0xc4, 0x40,
+          0x42, 0x52, 0x40, 0xa8, 0x53);
+  VLOAD_8(v1, 0x30, 0xef, 0xb4, 0x12, 0x6d, 0x3b, 0x2c, 0x5e, 0xf0, 0x25, 0xd7,
+          0x70, 0xc2, 0x62, 0xe0, 0x99);
+  asm volatile("vmacc.vv v1, v2, v3");
+  VCMP_U8(1, v1, 0xee, 0x42, 0xae, 0x96, 0xfd, 0xc7, 0x00, 0xae, 0xe4, 0x29,
+          0x17, 0xc4, 0x2a, 0xe2, 0x60, 0x6e);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v3, 0x1c20, 0x11e4, 0xde38, 0x642f, 0x3eb5, 0xa0af, 0x48e1, 0x5fc4,
+           0x3d2a, 0x67d5, 0x3f07, 0x2889, 0x8812, 0x0bd9, 0x56f4, 0xe068);
+  VLOAD_16(v2, 0x02cc, 0xd99c, 0xdba2, 0xf282, 0x0f99, 0xa219, 0x2dcc, 0x17cc,
+           0xe8fb, 0x1e83, 0xed20, 0xbfee, 0xee87, 0x6b0f, 0xf6cf, 0x4cd1);
+  VLOAD_16(v1, 0xe3f0, 0x42db, 0x2fde, 0x1983, 0x910c, 0x853b, 0x82aa, 0x9ac2,
+           0x4631, 0x1f8b, 0x68c3, 0x6fbc, 0x3b5c, 0xf98b, 0x2db1, 0x8e75);
+  asm volatile("vmacc.vv v1, v2, v3");
+  VCMP_U16(2, v1, 0x8d70, 0x6dcb, 0xb74e, 0x6761, 0xa639, 0xf452, 0x22f6,
+           0x86f2, 0x4e5f, 0x378a, 0xc4a3, 0x561a, 0xb8da, 0x5e42, 0xf4fd,
+           0xa35d);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v3, 0x0401c584, 0x69049955, 0x4a71aa0c, 0xc651666f, 0x273fcd5d,
+           0x23ca1d7d, 0x599c994e, 0xb2d8adc5, 0x4710afae, 0x69c61cad,
+           0x96ee5026, 0x2c197996, 0xd95da451, 0x3a654fb9, 0xbe990e4b,
+           0xc41fd55a);
+  VLOAD_32(v2, 0x39d5b56a, 0xc578a540, 0x51283b5c, 0x07b4ba9d, 0xe5aba5e4,
+           0x28720dc8, 0x600fb42b, 0xf2937fa7, 0x4032d36f, 0xc676e3b3,
+           0xf1cd5f96, 0x1c14bcbf, 0x7dea81ed, 0x40270562, 0x9577b3be,
+           0xea615f0a);
+  VLOAD_32(v1, 0xa055bbb6, 0x71f9a668, 0x0be640c9, 0x2336ca55, 0xca121638,
+           0xbf234fb5, 0xe7c83142, 0xb7048f12, 0x8eb340e3, 0xef253e93,
+           0xffef4a03, 0xdf346833, 0xd0922181, 0xf159ee1d, 0xf86a7c06,
+           0xfcb24a2d);
+  asm volatile("vmacc.vv v1, v2, v3");
+  VCMP_U32(3, v1, 0x448bd85e, 0xf2cbc4a8, 0x5cd02119, 0xf69b4268, 0x3c60ee0c,
+           0xa233b25d, 0x4c72c95c, 0xe2b1a595, 0xefb7d755, 0x95d6b28a,
+           0xd3be5a47, 0x6338471d, 0xfb1a117e, 0xabe00fef, 0xbede88b0,
+           0x913705b1);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v3, 0x9cffef345b95f00b, 0x85d366e07e4bbc6b, 0xadfda1d2464c6433,
+           0x610bf2c1435b3cf6, 0x8a0c6e4bc950e81f, 0x4296e7147ef94d7a,
+           0x27d7ec90ba159756, 0x2a6c87932c3aef86, 0xbfd90c33e58a8fe3,
+           0x1114f7672cf625c1, 0x1a7b72dd8ac39fab, 0xdb80f952e5fd2e5b,
+           0x6b01c18a3daf288b, 0x69b4b0e4335f26d5, 0x0c059f365ec6d3d5,
+           0xc22568276f1dcdd0);
+  VLOAD_64(v2, 0x6dc8e88769e54465, 0xce8cda83d16c3859, 0x1465ee5b6eb0d2b8,
+           0x4827a9b40add2507, 0xd24c4005695a64d6, 0xb97c8e41e912f84a,
+           0xc8c22e3b3b2e2fa1, 0x26712aa325bd00b6, 0xdf7ad19151df27b5,
+           0x68ba6d050ffcba1e, 0x94448979a2b854e6, 0x84bf5d544f97f739,
+           0x6d4bfa429e9d6ef0, 0xdb6c54b9a91ab935, 0x1a0051ca72162c5e,
+           0xe04b73fdf1b61f9c);
+  VLOAD_64(v1, 0x32a4c1edbbfe5591, 0xf6baf4e747f4a120, 0x3a29727ae38b9b92,
+           0xf173f78d09c997e4, 0xaab9d34e4aeaa57a, 0xa8fe3bf12b7c95e8,
+           0xc4bd99b066821092, 0x9c2f1daf5fe2db9d, 0xa8b041a876aabcae,
+           0xb9a2e6f9ded9a60a, 0x8bdf55954f50101d, 0x704f0e648c11d63f,
+           0x0c8ca4d0a6d1a982, 0xa74d01c12ae6aea5, 0x3f2cd5d2e2f5b538,
+           0x79803b24efa2caa3);
+  asm volatile("vmacc.vv v1, v2, v3");
+  VCMP_U64(4, v1, 0xf7c2044aeebff5e8, 0xad447a1b99a48a53, 0x78676efbe1b5763a,
+           0x813582af4d75d09e, 0x483adf8d811ecb64, 0x36d90fe4df2f2b2c,
+           0xf833b173685307a8, 0x955c2ac405b724e1, 0xdcf9681f074b0d2d,
+           0x10277404741c4ca8, 0x25d9bca0245d9fbf, 0x58439c4175d7f582,
+           0x27ae9e3365b265d2, 0xabfe86591f4ba5be, 0xd964de90eaae196e,
+           0xfb655e2263986563);
+}
+
+void TEST_CASE2() {
+  VSET(16, e8, m1);
+  VLOAD_8(v3, 0x21, 0x75, 0x7f, 0x3a, 0x50, 0x6d, 0x3f, 0x3e, 0x74, 0x11, 0x29,
+          0xea, 0x14, 0xce, 0xb0, 0x37);
+  VLOAD_8(v2, 0xfe, 0xa7, 0x06, 0xaa, 0x35, 0x3c, 0x2c, 0x58, 0xa1, 0xc4, 0x40,
+          0x42, 0x52, 0x40, 0xa8, 0x53);
+  VLOAD_8(v1, 0x30, 0xef, 0xb4, 0x12, 0x6d, 0x3b, 0x2c, 0x5e, 0xf0, 0x25, 0xd7,
+          0x70, 0xc2, 0x62, 0xe0, 0x99);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vmacc.vv v1, v2, v3, v0.t");
+  VCMP_U8(5, v1, 0x30, 0x42, 0xb4, 0x96, 0x6d, 0xc7, 0x2c, 0xae, 0xf0, 0x29,
+          0xd7, 0xc4, 0xc2, 0xe2, 0xe0, 0x6e);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v3, 0x1c20, 0x11e4, 0xde38, 0x642f, 0x3eb5, 0xa0af, 0x48e1, 0x5fc4,
+           0x3d2a, 0x67d5, 0x3f07, 0x2889, 0x8812, 0x0bd9, 0x56f4, 0xe068);
+  VLOAD_16(v2, 0x02cc, 0xd99c, 0xdba2, 0xf282, 0x0f99, 0xa219, 0x2dcc, 0x17cc,
+           0xe8fb, 0x1e83, 0xed20, 0xbfee, 0xee87, 0x6b0f, 0xf6cf, 0x4cd1);
+  VLOAD_16(v1, 0xe3f0, 0x42db, 0x2fde, 0x1983, 0x910c, 0x853b, 0x82aa, 0x9ac2,
+           0x4631, 0x1f8b, 0x68c3, 0x6fbc, 0x3b5c, 0xf98b, 0x2db1, 0x8e75);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vmacc.vv v1, v2, v3, v0.t");
+  VCMP_U16(6, v1, 0xe3f0, 0x6dcb, 0x2fde, 0x6761, 0x910c, 0xf452, 0x82aa,
+           0x86f2, 0x4631, 0x378a, 0x68c3, 0x561a, 0x3b5c, 0x5e42, 0x2db1,
+           0xa35d);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v3, 0x0401c584, 0x69049955, 0x4a71aa0c, 0xc651666f, 0x273fcd5d,
+           0x23ca1d7d, 0x599c994e, 0xb2d8adc5, 0x4710afae, 0x69c61cad,
+           0x96ee5026, 0x2c197996, 0xd95da451, 0x3a654fb9, 0xbe990e4b,
+           0xc41fd55a);
+  VLOAD_32(v2, 0x39d5b56a, 0xc578a540, 0x51283b5c, 0x07b4ba9d, 0xe5aba5e4,
+           0x28720dc8, 0x600fb42b, 0xf2937fa7, 0x4032d36f, 0xc676e3b3,
+           0xf1cd5f96, 0x1c14bcbf, 0x7dea81ed, 0x40270562, 0x9577b3be,
+           0xea615f0a);
+  VLOAD_32(v1, 0xa055bbb6, 0x71f9a668, 0x0be640c9, 0x2336ca55, 0xca121638,
+           0xbf234fb5, 0xe7c83142, 0xb7048f12, 0x8eb340e3, 0xef253e93,
+           0xffef4a03, 0xdf346833, 0xd0922181, 0xf159ee1d, 0xf86a7c06,
+           0xfcb24a2d);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vmacc.vv v1, v2, v3, v0.t");
+  VCMP_U32(7, v1, 0xa055bbb6, 0xf2cbc4a8, 0x0be640c9, 0xf69b4268, 0xca121638,
+           0xa233b25d, 0xe7c83142, 0xe2b1a595, 0x8eb340e3, 0x95d6b28a,
+           0xffef4a03, 0x6338471d, 0xd0922181, 0xabe00fef, 0xf86a7c06,
+           0x913705b1);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v3, 0x9cffef345b95f00b, 0x85d366e07e4bbc6b, 0xadfda1d2464c6433,
+           0x610bf2c1435b3cf6, 0x8a0c6e4bc950e81f, 0x4296e7147ef94d7a,
+           0x27d7ec90ba159756, 0x2a6c87932c3aef86, 0xbfd90c33e58a8fe3,
+           0x1114f7672cf625c1, 0x1a7b72dd8ac39fab, 0xdb80f952e5fd2e5b,
+           0x6b01c18a3daf288b, 0x69b4b0e4335f26d5, 0x0c059f365ec6d3d5,
+           0xc22568276f1dcdd0);
+  VLOAD_64(v2, 0x6dc8e88769e54465, 0xce8cda83d16c3859, 0x1465ee5b6eb0d2b8,
+           0x4827a9b40add2507, 0xd24c4005695a64d6, 0xb97c8e41e912f84a,
+           0xc8c22e3b3b2e2fa1, 0x26712aa325bd00b6, 0xdf7ad19151df27b5,
+           0x68ba6d050ffcba1e, 0x94448979a2b854e6, 0x84bf5d544f97f739,
+           0x6d4bfa429e9d6ef0, 0xdb6c54b9a91ab935, 0x1a0051ca72162c5e,
+           0xe04b73fdf1b61f9c);
+  VLOAD_64(v1, 0x32a4c1edbbfe5591, 0xf6baf4e747f4a120, 0x3a29727ae38b9b92,
+           0xf173f78d09c997e4, 0xaab9d34e4aeaa57a, 0xa8fe3bf12b7c95e8,
+           0xc4bd99b066821092, 0x9c2f1daf5fe2db9d, 0xa8b041a876aabcae,
+           0xb9a2e6f9ded9a60a, 0x8bdf55954f50101d, 0x704f0e648c11d63f,
+           0x0c8ca4d0a6d1a982, 0xa74d01c12ae6aea5, 0x3f2cd5d2e2f5b538,
+           0x79803b24efa2caa3);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vmacc.vv v1, v2, v3, v0.t");
+  VCMP_U64(8, v1, 0x32a4c1edbbfe5591, 0xad447a1b99a48a53, 0x3a29727ae38b9b92,
+           0x813582af4d75d09e, 0xaab9d34e4aeaa57a, 0x36d90fe4df2f2b2c,
+           0xc4bd99b066821092, 0x955c2ac405b724e1, 0xa8b041a876aabcae,
+           0x10277404741c4ca8, 0x8bdf55954f50101d, 0x58439c4175d7f582,
+           0x0c8ca4d0a6d1a982, 0xabfe86591f4ba5be, 0x3f2cd5d2e2f5b538,
+           0xfb655e2263986563);
+}
+
+void TEST_CASE3() {
+  VSET(16, e8, m1);
+  int64_t scalar = 5;
+  VLOAD_8(v2, 0x60, 0xe3, 0xa0, 0xb7, 0x35, 0x23, 0xa3, 0xf4, 0x5f, 0x6e, 0x07,
+          0x01, 0xe7, 0x51, 0x53, 0x29);
+  VLOAD_8(v1, 0xfb, 0x1b, 0xc0, 0x36, 0xa7, 0xe0, 0xc8, 0x47, 0x57, 0xe0, 0x51,
+          0xaa, 0xd2, 0x93, 0x83, 0xa8);
+  asm volatile("vmacc.vx v1, %[A], v2" ::[A] "r"(scalar));
+  VCMP_U8(9, v1, 0xdb, 0x8a, 0xe0, 0xc9, 0xb0, 0x8f, 0xf7, 0x0b, 0x32, 0x06,
+          0x74, 0xaf, 0x55, 0x28, 0x22, 0x75);
+
+  VSET(16, e16, m1);
+  scalar = -5383;
+  VLOAD_16(v2, 0x992e, 0x9a07, 0x90c3, 0xf1ce, 0xd53c, 0x8f07, 0x2d2f, 0x5ab1,
+           0x0a79, 0x0523, 0x6f34, 0xe5fd, 0xc95a, 0xca1c, 0x36bf, 0x16a1);
+  VLOAD_16(v1, 0x0a9f, 0x7ee0, 0x494e, 0xb6d0, 0x394c, 0xc8e7, 0xc117, 0x8108,
+           0xb1af, 0x9f16, 0x22ab, 0xa244, 0xf1c9, 0xe363, 0x9bed, 0xa06f);
+  asm volatile("vmacc.vx v1, %[A], v2" ::[A] "r"(scalar));
+  VCMP_U16(10, v1, 0x145d, 0xb5af, 0x54f9, 0x342e, 0x78a8, 0x4cb6, 0xa9ce,
+           0x8131, 0x7b60, 0x9c21, 0xd43f, 0x9759, 0x0e53, 0x109f, 0x71b4,
+           0xcd08);
+
+  VSET(16, e32, m1);
+  scalar = 6474219;
+  VLOAD_32(v2, 0x709e784e, 0x8e13e48a, 0xad5df7fd, 0x738c8997, 0x0a0030d0,
+           0x7569b952, 0x507fd5c7, 0x5d09af12, 0x0bf1c209, 0x7be6ed49,
+           0x842ba667, 0x53360ec0, 0xd85d7415, 0xf20de61f, 0x153e7e16,
+           0xec5512e4);
+  VLOAD_32(v1, 0xb2436fad, 0x6b162382, 0xd94eebe7, 0x9c43d906, 0xb80f178d,
+           0x5cf91d42, 0x7764b8a3, 0x6269f72c, 0xb0dff3a6, 0x838d6893,
+           0xa98a861e, 0x758b63de, 0xde488617, 0x371696ab, 0xc3ba8192,
+           0x7ca33236);
+  asm volatile("vmacc.vx v1, %[A], v2" ::[A] "r"(scalar));
+  VCMP_U32(11, v1, 0x8e0d1d47, 0xf29d4830, 0xb5213626, 0xb21bb5a3, 0xbc2f367d,
+           0x18eb9d88, 0x91c53550, 0x69a6ceb2, 0xc09822e9, 0x66c98b96,
+           0xf6b125ab, 0xef3fae1e, 0x4c40925e, 0x6b652c20, 0x998385c4,
+           0x75d88d82);
+
+  VSET(16, e64, m1);
+  scalar = -598189234597999223;
+  VLOAD_64(v2, 0x2a47beb4fd7729c5, 0x401c187818b15d1e, 0xbbaf5fe50c41f22a,
+           0x31eaddea171055a9, 0x609cbc4a78316c29, 0xd7bb8f31d8b59d88,
+           0x97860fd5fba018c0, 0x724cecf178bd2125, 0x866d16f96d3d8b67,
+           0x56153b0315164a5a, 0x6962bde49e3edf3f, 0x9b3f792bfbf5f343,
+           0x64cf433b239e7764, 0x583c3a4ae481fef0, 0x217e2df75fcf0d8d,
+           0x935ac02069fe54ce);
+  VLOAD_64(v1, 0x0dc8fa1b817237e5, 0xc817934370de904d, 0xb015bdbf0f39ec01,
+           0x3c7e70a75643cce5, 0x80c45834a5026c02, 0xcdf1fcd83b8133a0,
+           0x9d31b9b802ae2db1, 0xba7e57975c5febf5, 0x8732f75adf268ddb,
+           0x5ff488a4187bd3f3, 0x6a259fe666091333, 0x5afc4de057de51c4,
+           0x8a479b7e3558e399, 0xbc21e79022996c26, 0xe2c7432cd7e3e81d,
+           0xdab377ddbdfb2df7);
+  asm volatile("vmacc.vx v1, %[A], v2" ::[A] "r"(scalar));
+  VCMP_U64(12, v1, 0x093861b79ac45352, 0xfd3c909decf66b5b, 0x04eb13132ce4267b,
+           0xb258e6b065bbf956, 0x62775181e33422f3, 0xdc0ae0e371686968,
+           0xf8db06270cad2c71, 0x6c3cc52cd1fb49c2, 0x41c19c0ac1b5a2fa,
+           0x8867d35049c7b01d, 0x6d71fe0f35a1feea, 0xace16ac43ec0279f,
+           0x82faf4a574c9dc1d, 0xa875c9d17e310a96, 0x1f75616001b61192,
+           0x16ce205f44fb8635);
+}
+
+void TEST_CASE4() {
+  VSET(16, e8, m1);
+  int64_t scalar = 5;
+  VLOAD_8(v2, 0x60, 0xe3, 0xa0, 0xb7, 0x35, 0x23, 0xa3, 0xf4, 0x5f, 0x6e, 0x07,
+          0x01, 0xe7, 0x51, 0x53, 0x29);
+  VLOAD_8(v1, 0xfb, 0x1b, 0xc0, 0x36, 0xa7, 0xe0, 0xc8, 0x47, 0x57, 0xe0, 0x51,
+          0xaa, 0xd2, 0x93, 0x83, 0xa8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vmacc.vx v1, %[A], v2, v0.t" ::[A] "r"(scalar));
+  VCMP_U8(13, v1, 0xfb, 0x8a, 0xc0, 0xc9, 0xa7, 0x8f, 0xc8, 0x0b, 0x57, 0x06,
+          0x51, 0xaf, 0xd2, 0x28, 0x83, 0x75);
+
+  VSET(16, e16, m1);
+  scalar = -5383;
+  VLOAD_16(v2, 0x992e, 0x9a07, 0x90c3, 0xf1ce, 0xd53c, 0x8f07, 0x2d2f, 0x5ab1,
+           0x0a79, 0x0523, 0x6f34, 0xe5fd, 0xc95a, 0xca1c, 0x36bf, 0x16a1);
+  VLOAD_16(v1, 0x0a9f, 0x7ee0, 0x494e, 0xb6d0, 0x394c, 0xc8e7, 0xc117, 0x8108,
+           0xb1af, 0x9f16, 0x22ab, 0xa244, 0xf1c9, 0xe363, 0x9bed, 0xa06f);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vmacc.vx v1, %[A], v2, v0.t" ::[A] "r"(scalar));
+  VCMP_U16(14, v1, 0x0a9f, 0xb5af, 0x494e, 0x342e, 0x394c, 0x4cb6, 0xc117,
+           0x8131, 0xb1af, 0x9c21, 0x22ab, 0x9759, 0xf1c9, 0x109f, 0x9bed,
+           0xcd08);
+
+  VSET(16, e32, m1);
+  scalar = 6474219;
+  VLOAD_32(v2, 0x709e784e, 0x8e13e48a, 0xad5df7fd, 0x738c8997, 0x0a0030d0,
+           0x7569b952, 0x507fd5c7, 0x5d09af12, 0x0bf1c209, 0x7be6ed49,
+           0x842ba667, 0x53360ec0, 0xd85d7415, 0xf20de61f, 0x153e7e16,
+           0xec5512e4);
+  VLOAD_32(v1, 0xb2436fad, 0x6b162382, 0xd94eebe7, 0x9c43d906, 0xb80f178d,
+           0x5cf91d42, 0x7764b8a3, 0x6269f72c, 0xb0dff3a6, 0x838d6893,
+           0xa98a861e, 0x758b63de, 0xde488617, 0x371696ab, 0xc3ba8192,
+           0x7ca33236);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vmacc.vx v1, %[A], v2, v0.t" ::[A] "r"(scalar));
+  VCMP_U32(15, v1, 0xb2436fad, 0xf29d4830, 0xd94eebe7, 0xb21bb5a3, 0xb80f178d,
+           0x18eb9d88, 0x7764b8a3, 0x69a6ceb2, 0xb0dff3a6, 0x66c98b96,
+           0xa98a861e, 0xef3fae1e, 0xde488617, 0x6b652c20, 0xc3ba8192,
+           0x75d88d82);
+
+  VSET(16, e64, m1);
+  scalar = -598189234597999223;
+  VLOAD_64(v2, 0x2a47beb4fd7729c5, 0x401c187818b15d1e, 0xbbaf5fe50c41f22a,
+           0x31eaddea171055a9, 0x609cbc4a78316c29, 0xd7bb8f31d8b59d88,
+           0x97860fd5fba018c0, 0x724cecf178bd2125, 0x866d16f96d3d8b67,
+           0x56153b0315164a5a, 0x6962bde49e3edf3f, 0x9b3f792bfbf5f343,
+           0x64cf433b239e7764, 0x583c3a4ae481fef0, 0x217e2df75fcf0d8d,
+           0x935ac02069fe54ce);
+  VLOAD_64(v1, 0x0dc8fa1b817237e5, 0xc817934370de904d, 0xb015bdbf0f39ec01,
+           0x3c7e70a75643cce5, 0x80c45834a5026c02, 0xcdf1fcd83b8133a0,
+           0x9d31b9b802ae2db1, 0xba7e57975c5febf5, 0x8732f75adf268ddb,
+           0x5ff488a4187bd3f3, 0x6a259fe666091333, 0x5afc4de057de51c4,
+           0x8a479b7e3558e399, 0xbc21e79022996c26, 0xe2c7432cd7e3e81d,
+           0xdab377ddbdfb2df7);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vmacc.vx v1, %[A], v2, v0.t" ::[A] "r"(scalar));
+  VCMP_U64(16, v1, 0x0dc8fa1b817237e5, 0xfd3c909decf66b5b, 0xb015bdbf0f39ec01,
+           0xb258e6b065bbf956, 0x80c45834a5026c02, 0xdc0ae0e371686968,
+           0x9d31b9b802ae2db1, 0x6c3cc52cd1fb49c2, 0x8732f75adf268ddb,
+           0x8867d35049c7b01d, 0x6a259fe666091333, 0xace16ac43ec0279f,
+           0x8a479b7e3558e399, 0xa875c9d17e310a96, 0xe2c7432cd7e3e81d,
+           0x16ce205f44fb8635);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vmadc.c b/apps/riscv-tests/isa/rv64uv/vmadc.c
new file mode 100644
index 0000000..524ae9e
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vmadc.c
@@ -0,0 +1,238 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 16, 0xff, 8, 0x81, 16, 0xff, 8, 0x81, 16, 0xff, 8, 0x81, 16, 0xff,
+          8, 0x81);
+  VLOAD_8(v2, 4, 8, 12, 0x80, 4, 8, 12, 0x80, 4, 8, 12, 0x80, 4, 8, 12, 0x80);
+  VLOAD_8(v0, 0xDD, 0xDD);
+  asm volatile("vmadc.vvm v3, v1, v2, v0");
+  VSET(2, e8, m1);
+  VCMP_U8(1, v3, 0xAA, 0xAA);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 16, 0xffff, 8, 0x8001, 16, 0xffff, 8, 0x8001, 16, 0xffff, 8,
+           0x8001, 16, 0xffff, 8, 0x8001);
+  VLOAD_16(v2, 4, 8, 12, 0x8000, 4, 8, 12, 0x8000, 4, 8, 12, 0x8000, 4, 8, 12,
+           0x8000);
+  VLOAD_8(v0, 0xDD, 0xDD);
+  asm volatile("vmadc.vvm v3, v1, v2, v0");
+  VSET(2, e8, m1);
+  VCMP_U8(2, v3, 0xAA, 0xAA);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 16, 0xffffffff, 8, 0x80000001, 16, 0xffffffff, 8, 0x80000001, 16,
+           0xffffffff, 8, 0x80000001, 16, 0xffffffff, 8, 0x80000001);
+  VLOAD_32(v2, 4, 8, 12, 0x80000000, 4, 8, 12, 0x80000000, 4, 8, 12, 0x80000000,
+           4, 8, 12, 0x80000000);
+  VLOAD_8(v0, 0xDD, 0xDD);
+  asm volatile("vmadc.vvm v3, v1, v2, v0");
+  VSET(2, e8, m1);
+  VCMP_U8(3, v3, 0xAA, 0xAA);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 16, 0xffffffffffffffff, 8, 0x8000000000000001, 16,
+           0xffffffffffffffff, 8, 0x8000000000000001, 16, 0xffffffffffffffff, 8,
+           0x8000000000000001, 16, 0xffffffffffffffff, 8, 0x8000000000000001);
+  VLOAD_64(v2, 4, 8, 12, 0x8000000000000000, 4, 8, 12, 0x8000000000000000, 4, 8,
+           12, 0x8000000000000000, 4, 8, 12, 0x8000000000000000);
+  VLOAD_8(v0, 0xDD, 0xDD);
+  asm volatile("vmadc.vvm v3, v1, v2, v0");
+  VSET(2, e8, m1);
+  VCMP_U8(4, v3, 0xAA, 0xAA);
+};
+
+void TEST_CASE2(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 16, 0xff, 8, 0x81, 16, 0xff, 8, 0x81, 16, 0xff, 8, 0x81, 16, 0xff,
+          8, 0x81);
+  VLOAD_8(v2, 4, 8, 12, 0x80, 4, 8, 12, 0x80, 4, 8, 12, 0x80, 4, 8, 12, 0x80);
+  asm volatile("vmadc.vv v3, v1, v2");
+  VSET(2, e8, m1);
+  VCMP_U8(5, v3, 0xAA, 0xAA);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 16, 0xffff, 8, 0x8001, 16, 0xffff, 8, 0x8001, 16, 0xffff, 8,
+           0x8001, 16, 0xffff, 8, 0x8001);
+  VLOAD_16(v2, 4, 8, 12, 0x8000, 4, 8, 12, 0x8000, 4, 8, 12, 0x8000, 4, 8, 12,
+           0x8000);
+  asm volatile("vmadc.vv v3, v1, v2");
+  VSET(2, e8, m1);
+  VCMP_U8(6, v3, 0xAA, 0xAA);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 16, 0xffffffff, 8, 0x80000001, 16, 0xffffffff, 8, 0x80000001, 16,
+           0xffffffff, 8, 0x80000001, 16, 0xffffffff, 8, 0x80000001);
+  VLOAD_32(v2, 4, 8, 12, 0x80000000, 4, 8, 12, 0x80000000, 4, 8, 12, 0x80000000,
+           4, 8, 12, 0x80000000);
+  asm volatile("vmadc.vv v3, v1, v2");
+  VSET(2, e8, m1);
+  VCMP_U8(7, v3, 0xAA, 0xAA);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 16, 0xffffffffffffffff, 8, 0x8000000000000001, 16,
+           0xffffffffffffffff, 8, 0x8000000000000001, 16, 0xffffffffffffffff, 8,
+           0x8000000000000001, 16, 0xffffffffffffffff, 8, 0x8000000000000001);
+  VLOAD_64(v2, 4, 8, 12, 0x8000000000000000, 4, 8, 12, 0x8000000000000000, 4, 8,
+           12, 0x8000000000000000, 4, 8, 12, 0x8000000000000000);
+  asm volatile("vmadc.vv v3, v1, v2");
+  VSET(2, e8, m1);
+  VCMP_U8(8, v3, 0xAA, 0xAA);
+};
+
+void TEST_CASE3(void) {
+  const uint64_t scalar = 0x8000000080008080;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 16, 0xff, 8, 0x81, 16, 0xff, 8, 0x81, 16, 0xff, 8, 0x81, 16, 0xff,
+          8, 0x81);
+  VLOAD_8(v0, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1);
+  asm volatile("vmadc.vxm v3, v1, %[A], v0" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(9, v3, 0xAA, 0xAA);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 16, 0xffff, 8, 0x8001, 16, 0xffff, 8, 0x8001, 16, 0xffff, 8,
+           0x8001, 16, 0xffff, 8, 0x8001);
+  VLOAD_16(v0, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1);
+  asm volatile("vmadc.vxm v3, v1, %[A], v0" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(10, v3, 0xAA, 0xAA);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 16, 0xffffffff, 8, 0x80000001, 16, 0xffffffff, 8, 0x80000001, 16,
+           0xffffffff, 8, 0x80000001, 16, 0xffffffff, 8, 0x80000001);
+  VLOAD_32(v0, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1);
+  asm volatile("vmadc.vxm v3, v1, %[A], v0" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(11, v3, 0xAA, 0xAA);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 16, 0xffffffffffffffff, 8, 0x8000000000000001, 16,
+           0xffffffffffffffff, 8, 0x8000000000000001, 16, 0xffffffffffffffff, 8,
+           0x8000000000000001, 16, 0xffffffffffffffff, 8, 0x8000000000000001);
+  VLOAD_64(v0, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1);
+  asm volatile("vmadc.vxm v3, v1, %[A], v0" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(12, v3, 0xAA, 0xAA);
+};
+
+void TEST_CASE4(void) {
+  const uint64_t scalar = 0x8000000080008080;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 16, 0xff, 8, 0x81, 16, 0xff, 8, 0x81, 16, 0xff, 8, 0x81, 16, 0xff,
+          8, 0x81);
+  asm volatile("vmadc.vx v3, v1, %[A]" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(13, v3, 0xAA, 0xAA);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 16, 0xffff, 8, 0x8001, 16, 0xffff, 8, 0x8001, 16, 0xffff, 8,
+           0x8001, 16, 0xffff, 8, 0x8001);
+  asm volatile("vmadc.vx v3, v1, %[A]" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(14, v3, 0xAA, 0xAA);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 16, 0xffffffff, 8, 0x80000001, 16, 0xffffffff, 8, 0x80000001, 16,
+           0xffffffff, 8, 0x80000001, 16, 0xffffffff, 8, 0x80000001);
+  asm volatile("vmadc.vx v3, v1, %[A]" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(15, v3, 0xAA, 0xAA);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 16, 0xffffffffffffffff, 8, 0x8000000000000001, 16,
+           0xffffffffffffffff, 8, 0x8000000000000001, 16, 0xffffffffffffffff, 8,
+           0x8000000000000001, 16, 0xffffffffffffffff, 8, 0x8000000000000001);
+  asm volatile("vmadc.vx v3, v1, %[A]" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(16, v3, 0xAA, 0xAA);
+};
+
+void TEST_CASE5(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 16, 0xff, 8, 0x81, 16, 0xff, 8, 0x81, 16, 0xff, 8, 0x81, 16, 0xff,
+          8, 0x81);
+  VLOAD_8(v0, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1);
+  asm volatile("vmadc.vim v3, v1, 10, v0");
+  VSET(2, e8, m1);
+  VCMP_U8(17, v3, 0x22, 0x22);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 16, 0xffff, 8, 0x8001, 16, 0xffff, 8, 0x8001, 16, 0xffff, 8,
+           0x8001, 16, 0xffff, 8, 0x8001);
+  VLOAD_16(v0, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1);
+  asm volatile("vmadc.vim v3, v1, 10, v0");
+  VSET(2, e8, m1);
+  VCMP_U8(18, v3, 0x22, 0x22);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 16, 0xffffffff, 8, 0x80000001, 16, 0xffffffff, 8, 0x80000001, 16,
+           0xffffffff, 8, 0x80000001, 16, 0xffffffff, 8, 0x80000001);
+  VLOAD_32(v0, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1);
+  asm volatile("vmadc.vim v3, v1, 10, v0");
+  VSET(2, e8, m1);
+  VCMP_U8(19, v3, 0x22, 0x22);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 16, 0xffffffffffffffff, 8, 0x8000000000000001, 16,
+           0xffffffffffffffff, 8, 0x8000000000000001, 16, 0xffffffffffffffff, 8,
+           0x8000000000000001, 16, 0xffffffffffffffff, 8, 0x8000000000000001);
+  VLOAD_64(v0, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1);
+  asm volatile("vmadc.vim v3, v1, 10, v0");
+  VSET(2, e8, m1);
+  VCMP_U8(20, v3, 0x22, 0x22);
+};
+
+void TEST_CASE6(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 16, 0xff, 8, 0x81, 16, 0xff, 8, 0x81, 16, 0xff, 8, 0x81, 16, 0xff,
+          8, 0x81);
+  asm volatile("vmadc.vi v3, v1, 10");
+  VSET(2, e8, m1);
+  VCMP_U8(21, v3, 0x22, 0x22);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 16, 0xffff, 8, 0x8001, 16, 0xffff, 8, 0x8001, 16, 0xffff, 8,
+           0x8001, 16, 0xffff, 8, 0x8001);
+  asm volatile("vmadc.vi v3, v1, 10");
+  VSET(2, e8, m1);
+  VCMP_U8(22, v3, 0x22, 0x22);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 16, 0xffffffff, 8, 0x80000001, 16, 0xffffffff, 8, 0x80000001, 16,
+           0xffffffff, 8, 0x80000001, 16, 0xffffffff, 8, 0x80000001);
+  asm volatile("vmadc.vi v3, v1, 10");
+  VSET(2, e8, m1);
+  VCMP_U8(23, v3, 0x22, 0x22);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 16, 0xffffffffffffffff, 8, 0x8000000000000001, 16,
+           0xffffffffffffffff, 8, 0x8000000000000001, 16, 0xffffffffffffffff, 8,
+           0x8000000000000001, 16, 0xffffffffffffffff, 8, 0x8000000000000001);
+  asm volatile("vmadc.vi v3, v1, 10");
+  VSET(2, e8, m1);
+  VCMP_U8(24, v3, 0x22, 0x22);
+};
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+  TEST_CASE6();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vmadd.c b/apps/riscv-tests/isa/rv64uv/vmadd.c
new file mode 100644
index 0000000..797fc77
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vmadd.c
@@ -0,0 +1,292 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1() {
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 0x21, 0x75, 0x7f, 0x3a, 0x50, 0x6d, 0x3f, 0x3e, 0x74, 0x11, 0x29,
+          0xea, 0x14, 0xce, 0xb0, 0x37);
+  VLOAD_8(v2, 0xfe, 0xa7, 0x06, 0xaa, 0x35, 0x3c, 0x2c, 0x58, 0xa1, 0xc4, 0x40,
+          0x42, 0x52, 0x40, 0xa8, 0x53);
+  VLOAD_8(v3, 0x30, 0xef, 0xb4, 0x12, 0x6d, 0x3b, 0x2c, 0x5e, 0xf0, 0x25, 0xd7,
+          0x70, 0xc2, 0x62, 0xe0, 0x99);
+  asm volatile("vmadd.vv v1, v2, v3");
+  VCMP_U8(1, v1, 0xee, 0x42, 0xae, 0x96, 0xfd, 0xc7, 0x00, 0xae, 0xe4, 0x29,
+          0x17, 0xc4, 0x2a, 0xe2, 0x60, 0x6e);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 0x1c20, 0x11e4, 0xde38, 0x642f, 0x3eb5, 0xa0af, 0x48e1, 0x5fc4,
+           0x3d2a, 0x67d5, 0x3f07, 0x2889, 0x8812, 0x0bd9, 0x56f4, 0xe068);
+  VLOAD_16(v2, 0x02cc, 0xd99c, 0xdba2, 0xf282, 0x0f99, 0xa219, 0x2dcc, 0x17cc,
+           0xe8fb, 0x1e83, 0xed20, 0xbfee, 0xee87, 0x6b0f, 0xf6cf, 0x4cd1);
+  VLOAD_16(v3, 0xe3f0, 0x42db, 0x2fde, 0x1983, 0x910c, 0x853b, 0x82aa, 0x9ac2,
+           0x4631, 0x1f8b, 0x68c3, 0x6fbc, 0x3b5c, 0xf98b, 0x2db1, 0x8e75);
+  asm volatile("vmadd.vv v1, v2, v3");
+  VCMP_U16(2, v1, 0x8d70, 0x6dcb, 0xb74e, 0x6761, 0xa639, 0xf452, 0x22f6,
+           0x86f2, 0x4e5f, 0x378a, 0xc4a3, 0x561a, 0xb8da, 0x5e42, 0xf4fd,
+           0xa35d);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 0x0401c584, 0x69049955, 0x4a71aa0c, 0xc651666f, 0x273fcd5d,
+           0x23ca1d7d, 0x599c994e, 0xb2d8adc5, 0x4710afae, 0x69c61cad,
+           0x96ee5026, 0x2c197996, 0xd95da451, 0x3a654fb9, 0xbe990e4b,
+           0xc41fd55a);
+  VLOAD_32(v2, 0x39d5b56a, 0xc578a540, 0x51283b5c, 0x07b4ba9d, 0xe5aba5e4,
+           0x28720dc8, 0x600fb42b, 0xf2937fa7, 0x4032d36f, 0xc676e3b3,
+           0xf1cd5f96, 0x1c14bcbf, 0x7dea81ed, 0x40270562, 0x9577b3be,
+           0xea615f0a);
+  VLOAD_32(v3, 0xa055bbb6, 0x71f9a668, 0x0be640c9, 0x2336ca55, 0xca121638,
+           0xbf234fb5, 0xe7c83142, 0xb7048f12, 0x8eb340e3, 0xef253e93,
+           0xffef4a03, 0xdf346833, 0xd0922181, 0xf159ee1d, 0xf86a7c06,
+           0xfcb24a2d);
+  asm volatile("vmadd.vv v1, v2, v3");
+  VCMP_U32(3, v1, 0x448bd85e, 0xf2cbc4a8, 0x5cd02119, 0xf69b4268, 0x3c60ee0c,
+           0xa233b25d, 0x4c72c95c, 0xe2b1a595, 0xefb7d755, 0x95d6b28a,
+           0xd3be5a47, 0x6338471d, 0xfb1a117e, 0xabe00fef, 0xbede88b0,
+           0x913705b1);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 0x9cffef345b95f00b, 0x85d366e07e4bbc6b, 0xadfda1d2464c6433,
+           0x610bf2c1435b3cf6, 0x8a0c6e4bc950e81f, 0x4296e7147ef94d7a,
+           0x27d7ec90ba159756, 0x2a6c87932c3aef86, 0xbfd90c33e58a8fe3,
+           0x1114f7672cf625c1, 0x1a7b72dd8ac39fab, 0xdb80f952e5fd2e5b,
+           0x6b01c18a3daf288b, 0x69b4b0e4335f26d5, 0x0c059f365ec6d3d5,
+           0xc22568276f1dcdd0);
+  VLOAD_64(v2, 0x6dc8e88769e54465, 0xce8cda83d16c3859, 0x1465ee5b6eb0d2b8,
+           0x4827a9b40add2507, 0xd24c4005695a64d6, 0xb97c8e41e912f84a,
+           0xc8c22e3b3b2e2fa1, 0x26712aa325bd00b6, 0xdf7ad19151df27b5,
+           0x68ba6d050ffcba1e, 0x94448979a2b854e6, 0x84bf5d544f97f739,
+           0x6d4bfa429e9d6ef0, 0xdb6c54b9a91ab935, 0x1a0051ca72162c5e,
+           0xe04b73fdf1b61f9c);
+  VLOAD_64(v3, 0x32a4c1edbbfe5591, 0xf6baf4e747f4a120, 0x3a29727ae38b9b92,
+           0xf173f78d09c997e4, 0xaab9d34e4aeaa57a, 0xa8fe3bf12b7c95e8,
+           0xc4bd99b066821092, 0x9c2f1daf5fe2db9d, 0xa8b041a876aabcae,
+           0xb9a2e6f9ded9a60a, 0x8bdf55954f50101d, 0x704f0e648c11d63f,
+           0x0c8ca4d0a6d1a982, 0xa74d01c12ae6aea5, 0x3f2cd5d2e2f5b538,
+           0x79803b24efa2caa3);
+  asm volatile("vmadd.vv v1, v2, v3");
+  VCMP_U64(4, v1, 0xf7c2044aeebff5e8, 0xad447a1b99a48a53, 0x78676efbe1b5763a,
+           0x813582af4d75d09e, 0x483adf8d811ecb64, 0x36d90fe4df2f2b2c,
+           0xf833b173685307a8, 0x955c2ac405b724e1, 0xdcf9681f074b0d2d,
+           0x10277404741c4ca8, 0x25d9bca0245d9fbf, 0x58439c4175d7f582,
+           0x27ae9e3365b265d2, 0xabfe86591f4ba5be, 0xd964de90eaae196e,
+           0xfb655e2263986563);
+}
+
+void TEST_CASE2() {
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 0x21, 0x75, 0x7f, 0x3a, 0x50, 0x6d, 0x3f, 0x3e, 0x74, 0x11, 0x29,
+          0xea, 0x14, 0xce, 0xb0, 0x37);
+  VLOAD_8(v2, 0xfe, 0xa7, 0x06, 0xaa, 0x35, 0x3c, 0x2c, 0x58, 0xa1, 0xc4, 0x40,
+          0x42, 0x52, 0x40, 0xa8, 0x53);
+  VLOAD_8(v3, 0x30, 0xef, 0xb4, 0x12, 0x6d, 0x3b, 0x2c, 0x5e, 0xf0, 0x25, 0xd7,
+          0x70, 0xc2, 0x62, 0xe0, 0x99);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vmadd.vv v1, v2, v3, v0.t");
+  VCMP_U8(5, v1, 0x21, 0x42, 0x7f, 0x96, 0x50, 0xc7, 0x3f, 0xae, 0x74, 0x29,
+          0x29, 0xc4, 0x14, 0xe2, 0xb0, 0x6e);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 0x1c20, 0x11e4, 0xde38, 0x642f, 0x3eb5, 0xa0af, 0x48e1, 0x5fc4,
+           0x3d2a, 0x67d5, 0x3f07, 0x2889, 0x8812, 0x0bd9, 0x56f4, 0xe068);
+  VLOAD_16(v2, 0x02cc, 0xd99c, 0xdba2, 0xf282, 0x0f99, 0xa219, 0x2dcc, 0x17cc,
+           0xe8fb, 0x1e83, 0xed20, 0xbfee, 0xee87, 0x6b0f, 0xf6cf, 0x4cd1);
+  VLOAD_16(v3, 0xe3f0, 0x42db, 0x2fde, 0x1983, 0x910c, 0x853b, 0x82aa, 0x9ac2,
+           0x4631, 0x1f8b, 0x68c3, 0x6fbc, 0x3b5c, 0xf98b, 0x2db1, 0x8e75);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vmadd.vv v1, v2, v3, v0.t");
+  VCMP_U16(6, v1, 0x1c20, 0x6dcb, 0xde38, 0x6761, 0x3eb5, 0xf452, 0x48e1,
+           0x86f2, 0x3d2a, 0x378a, 0x3f07, 0x561a, 0x8812, 0x5e42, 0x56f4,
+           0xa35d);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 0x0401c584, 0x69049955, 0x4a71aa0c, 0xc651666f, 0x273fcd5d,
+           0x23ca1d7d, 0x599c994e, 0xb2d8adc5, 0x4710afae, 0x69c61cad,
+           0x96ee5026, 0x2c197996, 0xd95da451, 0x3a654fb9, 0xbe990e4b,
+           0xc41fd55a);
+  VLOAD_32(v2, 0x39d5b56a, 0xc578a540, 0x51283b5c, 0x07b4ba9d, 0xe5aba5e4,
+           0x28720dc8, 0x600fb42b, 0xf2937fa7, 0x4032d36f, 0xc676e3b3,
+           0xf1cd5f96, 0x1c14bcbf, 0x7dea81ed, 0x40270562, 0x9577b3be,
+           0xea615f0a);
+  VLOAD_32(v3, 0xa055bbb6, 0x71f9a668, 0x0be640c9, 0x2336ca55, 0xca121638,
+           0xbf234fb5, 0xe7c83142, 0xb7048f12, 0x8eb340e3, 0xef253e93,
+           0xffef4a03, 0xdf346833, 0xd0922181, 0xf159ee1d, 0xf86a7c06,
+           0xfcb24a2d);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vmadd.vv v1, v2, v3, v0.t");
+  VCMP_U32(7, v1, 0x0401c584, 0xf2cbc4a8, 0x4a71aa0c, 0xf69b4268, 0x273fcd5d,
+           0xa233b25d, 0x599c994e, 0xe2b1a595, 0x4710afae, 0x95d6b28a,
+           0x96ee5026, 0x6338471d, 0xd95da451, 0xabe00fef, 0xbe990e4b,
+           0x913705b1);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 0x9cffef345b95f00b, 0x85d366e07e4bbc6b, 0xadfda1d2464c6433,
+           0x610bf2c1435b3cf6, 0x8a0c6e4bc950e81f, 0x4296e7147ef94d7a,
+           0x27d7ec90ba159756, 0x2a6c87932c3aef86, 0xbfd90c33e58a8fe3,
+           0x1114f7672cf625c1, 0x1a7b72dd8ac39fab, 0xdb80f952e5fd2e5b,
+           0x6b01c18a3daf288b, 0x69b4b0e4335f26d5, 0x0c059f365ec6d3d5,
+           0xc22568276f1dcdd0);
+  VLOAD_64(v2, 0x6dc8e88769e54465, 0xce8cda83d16c3859, 0x1465ee5b6eb0d2b8,
+           0x4827a9b40add2507, 0xd24c4005695a64d6, 0xb97c8e41e912f84a,
+           0xc8c22e3b3b2e2fa1, 0x26712aa325bd00b6, 0xdf7ad19151df27b5,
+           0x68ba6d050ffcba1e, 0x94448979a2b854e6, 0x84bf5d544f97f739,
+           0x6d4bfa429e9d6ef0, 0xdb6c54b9a91ab935, 0x1a0051ca72162c5e,
+           0xe04b73fdf1b61f9c);
+  VLOAD_64(v3, 0x32a4c1edbbfe5591, 0xf6baf4e747f4a120, 0x3a29727ae38b9b92,
+           0xf173f78d09c997e4, 0xaab9d34e4aeaa57a, 0xa8fe3bf12b7c95e8,
+           0xc4bd99b066821092, 0x9c2f1daf5fe2db9d, 0xa8b041a876aabcae,
+           0xb9a2e6f9ded9a60a, 0x8bdf55954f50101d, 0x704f0e648c11d63f,
+           0x0c8ca4d0a6d1a982, 0xa74d01c12ae6aea5, 0x3f2cd5d2e2f5b538,
+           0x79803b24efa2caa3);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vmadd.vv v1, v2, v3, v0.t");
+  VCMP_U64(8, v1, 0x9cffef345b95f00b, 0xad447a1b99a48a53, 0xadfda1d2464c6433,
+           0x813582af4d75d09e, 0x8a0c6e4bc950e81f, 0x36d90fe4df2f2b2c,
+           0x27d7ec90ba159756, 0x955c2ac405b724e1, 0xbfd90c33e58a8fe3,
+           0x10277404741c4ca8, 0x1a7b72dd8ac39fab, 0x58439c4175d7f582,
+           0x6b01c18a3daf288b, 0xabfe86591f4ba5be, 0x0c059f365ec6d3d5,
+           0xfb655e2263986563);
+}
+
+void TEST_CASE3() {
+  VSET(16, e8, m1);
+  int64_t scalar = 5;
+  VLOAD_8(v1, 0x60, 0xe3, 0xa0, 0xb7, 0x35, 0x23, 0xa3, 0xf4, 0x5f, 0x6e, 0x07,
+          0x01, 0xe7, 0x51, 0x53, 0x29);
+  VLOAD_8(v2, 0xfb, 0x1b, 0xc0, 0x36, 0xa7, 0xe0, 0xc8, 0x47, 0x57, 0xe0, 0x51,
+          0xaa, 0xd2, 0x93, 0x83, 0xa8);
+  asm volatile("vmadd.vx v1, %[A], v2" ::[A] "r"(scalar));
+  VCMP_U8(9, v1, 0xdb, 0x8a, 0xe0, 0xc9, 0xb0, 0x8f, 0xf7, 0x0b, 0x32, 0x06,
+          0x74, 0xaf, 0x55, 0x28, 0x22, 0x75);
+
+  VSET(16, e16, m1);
+  scalar = -5383;
+  VLOAD_16(v1, 0x992e, 0x9a07, 0x90c3, 0xf1ce, 0xd53c, 0x8f07, 0x2d2f, 0x5ab1,
+           0x0a79, 0x0523, 0x6f34, 0xe5fd, 0xc95a, 0xca1c, 0x36bf, 0x16a1);
+  VLOAD_16(v2, 0x0a9f, 0x7ee0, 0x494e, 0xb6d0, 0x394c, 0xc8e7, 0xc117, 0x8108,
+           0xb1af, 0x9f16, 0x22ab, 0xa244, 0xf1c9, 0xe363, 0x9bed, 0xa06f);
+  asm volatile("vmadd.vx v1, %[A], v2" ::[A] "r"(scalar));
+  VCMP_U16(10, v1, 0x145d, 0xb5af, 0x54f9, 0x342e, 0x78a8, 0x4cb6, 0xa9ce,
+           0x8131, 0x7b60, 0x9c21, 0xd43f, 0x9759, 0x0e53, 0x109f, 0x71b4,
+           0xcd08);
+
+  VSET(16, e32, m1);
+  scalar = 6474219;
+  VLOAD_32(v1, 0x709e784e, 0x8e13e48a, 0xad5df7fd, 0x738c8997, 0x0a0030d0,
+           0x7569b952, 0x507fd5c7, 0x5d09af12, 0x0bf1c209, 0x7be6ed49,
+           0x842ba667, 0x53360ec0, 0xd85d7415, 0xf20de61f, 0x153e7e16,
+           0xec5512e4);
+  VLOAD_32(v2, 0xb2436fad, 0x6b162382, 0xd94eebe7, 0x9c43d906, 0xb80f178d,
+           0x5cf91d42, 0x7764b8a3, 0x6269f72c, 0xb0dff3a6, 0x838d6893,
+           0xa98a861e, 0x758b63de, 0xde488617, 0x371696ab, 0xc3ba8192,
+           0x7ca33236);
+  asm volatile("vmadd.vx v1, %[A], v2" ::[A] "r"(scalar));
+  VCMP_U32(11, v1, 0x8e0d1d47, 0xf29d4830, 0xb5213626, 0xb21bb5a3, 0xbc2f367d,
+           0x18eb9d88, 0x91c53550, 0x69a6ceb2, 0xc09822e9, 0x66c98b96,
+           0xf6b125ab, 0xef3fae1e, 0x4c40925e, 0x6b652c20, 0x998385c4,
+           0x75d88d82);
+
+  VSET(16, e64, m1);
+  scalar = -598189234597999223;
+  VLOAD_64(v1, 0x2a47beb4fd7729c5, 0x401c187818b15d1e, 0xbbaf5fe50c41f22a,
+           0x31eaddea171055a9, 0x609cbc4a78316c29, 0xd7bb8f31d8b59d88,
+           0x97860fd5fba018c0, 0x724cecf178bd2125, 0x866d16f96d3d8b67,
+           0x56153b0315164a5a, 0x6962bde49e3edf3f, 0x9b3f792bfbf5f343,
+           0x64cf433b239e7764, 0x583c3a4ae481fef0, 0x217e2df75fcf0d8d,
+           0x935ac02069fe54ce);
+  VLOAD_64(v2, 0x0dc8fa1b817237e5, 0xc817934370de904d, 0xb015bdbf0f39ec01,
+           0x3c7e70a75643cce5, 0x80c45834a5026c02, 0xcdf1fcd83b8133a0,
+           0x9d31b9b802ae2db1, 0xba7e57975c5febf5, 0x8732f75adf268ddb,
+           0x5ff488a4187bd3f3, 0x6a259fe666091333, 0x5afc4de057de51c4,
+           0x8a479b7e3558e399, 0xbc21e79022996c26, 0xe2c7432cd7e3e81d,
+           0xdab377ddbdfb2df7);
+  asm volatile("vmadd.vx v1, %[A], v2" ::[A] "r"(scalar));
+  VCMP_U64(12, v1, 0x093861b79ac45352, 0xfd3c909decf66b5b, 0x04eb13132ce4267b,
+           0xb258e6b065bbf956, 0x62775181e33422f3, 0xdc0ae0e371686968,
+           0xf8db06270cad2c71, 0x6c3cc52cd1fb49c2, 0x41c19c0ac1b5a2fa,
+           0x8867d35049c7b01d, 0x6d71fe0f35a1feea, 0xace16ac43ec0279f,
+           0x82faf4a574c9dc1d, 0xa875c9d17e310a96, 0x1f75616001b61192,
+           0x16ce205f44fb8635);
+}
+
+void TEST_CASE4() {
+  VSET(16, e8, m1);
+  int64_t scalar = 5;
+  VLOAD_8(v1, 0x60, 0xe3, 0xa0, 0xb7, 0x35, 0x23, 0xa3, 0xf4, 0x5f, 0x6e, 0x07,
+          0x01, 0xe7, 0x51, 0x53, 0x29);
+  VLOAD_8(v2, 0xfb, 0x1b, 0xc0, 0x36, 0xa7, 0xe0, 0xc8, 0x47, 0x57, 0xe0, 0x51,
+          0xaa, 0xd2, 0x93, 0x83, 0xa8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vmadd.vx v1, %[A], v2, v0.t" ::[A] "r"(scalar));
+  VCMP_U8(13, v1, 0x60, 0x8a, 0xa0, 0xc9, 0x35, 0x8f, 0xa3, 0x0b, 0x5f, 0x06,
+          0x07, 0xaf, 0xe7, 0x28, 0x53, 0x75);
+
+  VSET(16, e16, m1);
+  scalar = -5383;
+  VLOAD_16(v1, 0x992e, 0x9a07, 0x90c3, 0xf1ce, 0xd53c, 0x8f07, 0x2d2f, 0x5ab1,
+           0x0a79, 0x0523, 0x6f34, 0xe5fd, 0xc95a, 0xca1c, 0x36bf, 0x16a1);
+  VLOAD_16(v2, 0x0a9f, 0x7ee0, 0x494e, 0xb6d0, 0x394c, 0xc8e7, 0xc117, 0x8108,
+           0xb1af, 0x9f16, 0x22ab, 0xa244, 0xf1c9, 0xe363, 0x9bed, 0xa06f);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vmadd.vx v1, %[A], v2, v0.t" ::[A] "r"(scalar));
+  VCMP_U16(14, v1, 0x992e, 0xb5af, 0x90c3, 0x342e, 0xd53c, 0x4cb6, 0x2d2f,
+           0x8131, 0x0a79, 0x9c21, 0x6f34, 0x9759, 0xc95a, 0x109f, 0x36bf,
+           0xcd08);
+
+  VSET(16, e32, m1);
+  scalar = 6474219;
+  VLOAD_32(v1, 0x709e784e, 0x8e13e48a, 0xad5df7fd, 0x738c8997, 0x0a0030d0,
+           0x7569b952, 0x507fd5c7, 0x5d09af12, 0x0bf1c209, 0x7be6ed49,
+           0x842ba667, 0x53360ec0, 0xd85d7415, 0xf20de61f, 0x153e7e16,
+           0xec5512e4);
+  VLOAD_32(v2, 0xb2436fad, 0x6b162382, 0xd94eebe7, 0x9c43d906, 0xb80f178d,
+           0x5cf91d42, 0x7764b8a3, 0x6269f72c, 0xb0dff3a6, 0x838d6893,
+           0xa98a861e, 0x758b63de, 0xde488617, 0x371696ab, 0xc3ba8192,
+           0x7ca33236);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vmadd.vx v1, %[A], v2, v0.t" ::[A] "r"(scalar));
+  VCMP_U32(15, v1, 0x709e784e, 0xf29d4830, 0xad5df7fd, 0xb21bb5a3, 0x0a0030d0,
+           0x18eb9d88, 0x507fd5c7, 0x69a6ceb2, 0x0bf1c209, 0x66c98b96,
+           0x842ba667, 0xef3fae1e, 0xd85d7415, 0x6b652c20, 0x153e7e16,
+           0x75d88d82);
+
+  VSET(16, e64, m1);
+  scalar = -598189234597999223;
+  VLOAD_64(v1, 0x2a47beb4fd7729c5, 0x401c187818b15d1e, 0xbbaf5fe50c41f22a,
+           0x31eaddea171055a9, 0x609cbc4a78316c29, 0xd7bb8f31d8b59d88,
+           0x97860fd5fba018c0, 0x724cecf178bd2125, 0x866d16f96d3d8b67,
+           0x56153b0315164a5a, 0x6962bde49e3edf3f, 0x9b3f792bfbf5f343,
+           0x64cf433b239e7764, 0x583c3a4ae481fef0, 0x217e2df75fcf0d8d,
+           0x935ac02069fe54ce);
+  VLOAD_64(v2, 0x0dc8fa1b817237e5, 0xc817934370de904d, 0xb015bdbf0f39ec01,
+           0x3c7e70a75643cce5, 0x80c45834a5026c02, 0xcdf1fcd83b8133a0,
+           0x9d31b9b802ae2db1, 0xba7e57975c5febf5, 0x8732f75adf268ddb,
+           0x5ff488a4187bd3f3, 0x6a259fe666091333, 0x5afc4de057de51c4,
+           0x8a479b7e3558e399, 0xbc21e79022996c26, 0xe2c7432cd7e3e81d,
+           0xdab377ddbdfb2df7);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vmadd.vx v1, %[A], v2, v0.t" ::[A] "r"(scalar));
+  VCMP_U64(16, v1, 0x2a47beb4fd7729c5, 0xfd3c909decf66b5b, 0xbbaf5fe50c41f22a,
+           0xb258e6b065bbf956, 0x609cbc4a78316c29, 0xdc0ae0e371686968,
+           0x97860fd5fba018c0, 0x6c3cc52cd1fb49c2, 0x866d16f96d3d8b67,
+           0x8867d35049c7b01d, 0x6962bde49e3edf3f, 0xace16ac43ec0279f,
+           0x64cf433b239e7764, 0xa875c9d17e310a96, 0x217e2df75fcf0d8d,
+           0x16ce205f44fb8635);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vmand.c b/apps/riscv-tests/isa/rv64uv/vmand.c
new file mode 100644
index 0000000..82332f4
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vmand.c
@@ -0,0 +1,79 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1() {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xCD, 0xEF);
+  VLOAD_8(v3, 0x84, 0x21);
+  asm volatile("vmand.mm v1, v2, v3");
+  VSET(16, e8, m1);
+  VCMP_U8(1, v1, 0x84, 0x21);
+}
+
+void TEST_CASE2() {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xCD, 0xEF);
+  VLOAD_8(v3, 0xFF, 0xFF);
+  asm volatile("vmand.mm v1, v2, v3");
+  VSET(16, e8, m1);
+  VCMP_U8(2, v1, 0xCD, 0xEF);
+}
+
+void TEST_CASE3() {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xCD, 0xEF);
+  VLOAD_8(v3, 0x00, 0x00);
+  asm volatile("vmand.mm v1, v2, v3");
+  VSET(16, e8, m1);
+  VCMP_U8(3, v1, 0x00, 0x00);
+}
+
+void TEST_CASE4() {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xCD, 0xEF);
+  VLOAD_8(v3, 0x0F, 0xF0);
+  asm volatile("vmand.mm v1, v2, v3");
+  VSET(16, e8, m1);
+  VCMP_U8(4, v1, 0x0D, 0xE0);
+}
+
+void TEST_CASE5() {
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 0xFF, 0xFF);
+  VLOAD_8(v2, 0xCD, 0xEF);
+  VLOAD_8(v3, 0x84, 0x21);
+  VSET(16, e8, m1);
+  asm volatile("vmand.mm v1, v2, v3");
+  VSET(16, e8, m1);
+  VCMP_U8(5, v1, 0x84, 0x21);
+}
+
+void TEST_CASE6() {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xCD, 0xEF, 0xCD, 0xEF, 0xCD, 0xEF, 0xCD, 0xEF);
+  VLOAD_8(v3, 0x84, 0x21, 0x84, 0x21, 0x84, 0x21, 0x84, 0x21);
+  asm volatile("vmand.mm v1, v2, v3");
+  VSET(13, e8, m1);
+  VCLEAR(v2);
+  VCMP_U8(6, v2, 0, 0, 0, 0, 0, 0, 0, 0);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+  TEST_CASE6();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vmandnot.c b/apps/riscv-tests/isa/rv64uv/vmandnot.c
new file mode 100644
index 0000000..5902eed
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vmandnot.c
@@ -0,0 +1,68 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1() {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xCD, 0xEF);
+  VLOAD_8(v3, 0x84, 0x21);
+  asm volatile("vmandnot.mm v1, v2, v3");
+  VSET(16, e8, m1);
+  VCMP_U8(1, v1, 0x49, 0xCE);
+}
+
+void TEST_CASE2() {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xCD, 0xEF);
+  VLOAD_8(v3, 0xFF, 0xFF);
+  asm volatile("vmandnot.mm v1, v2, v3");
+  VSET(16, e8, m1);
+  VCMP_U8(2, v1, 0x00, 0x00);
+}
+
+void TEST_CASE3() {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xCD, 0xEF);
+  VLOAD_8(v3, 0x00, 0x00);
+  asm volatile("vmandnot.mm v1, v2, v3");
+  VSET(16, e8, m1);
+  VCMP_U8(3, v1, 0xCD, 0xEF);
+}
+
+void TEST_CASE4() {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xCD, 0xEF);
+  VLOAD_8(v3, 0x0F, 0xF0);
+  asm volatile("vmandnot.mm v1, v2, v3");
+  VSET(16, e8, m1);
+  VCMP_U8(4, v1, 0xC0, 0x0F);
+}
+
+void TEST_CASE5() {
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 0xFF, 0xFF);
+  VLOAD_8(v2, 0xCD, 0xEF);
+  VLOAD_8(v3, 0x84, 0x21);
+  VSET(16, e8, m1);
+  asm volatile("vmandnot.mm v1, v2, v3");
+  VSET(16, e8, m1);
+  VCMP_U8(5, v1, 0x49, 0xCE);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vmax.c b/apps/riscv-tests/isa/rv64uv/vmax.c
new file mode 100644
index 0000000..eae2406
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vmax.c
@@ -0,0 +1,181 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 12345, -80, 2560, -19900, 12345, -80, 2560, -19900, 12345, -80,
+           2560, -19900, 12345, -80, 2560, -19900);
+  VLOAD_16(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  asm volatile("vmax.vv v1, v2, v3");
+  VCMP_I16(1, v1, 12345, 7000, 2560, 19901, 12345, 7000, 2560, 19901, 12345,
+           7000, 2560, 19901, 12345, 7000, 2560, 19901);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 12345, -80, 2560, -19900, 12345, -80, 2560, -19900, 12345, -80,
+           2560, -19900, 12345, -80, 2560, -19900);
+  VLOAD_32(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  asm volatile("vmax.vv v1, v2, v3");
+  VCMP_I32(2, v1, 12345, 7000, 2560, 19901, 12345, 7000, 2560, 19901, 12345,
+           7000, 2560, 19901, 12345, 7000, 2560, 19901);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 12345, -80, 2560, -19900, 12345, -80, 2560, -19900, 12345, -80,
+           2560, -19900, 12345, -80, 2560, -19900);
+  VLOAD_64(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  asm volatile("vmax.vv v1, v2, v3");
+  VCMP_I64(3, v1, 12345, 7000, 2560, 19901, 12345, 7000, 2560, 19901, 12345,
+           7000, 2560, 19901, 12345, 7000, 2560, 19901);
+};
+
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 12345, -80, 2560, -19900, 12345, -80, 2560, -19900, 12345, -80,
+           2560, -19900, 12345, -80, 2560, -19900);
+  VLOAD_16(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VLOAD_16(v1, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef,
+           0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef);
+  asm volatile("vmax.vv v1, v2, v3, v0.t");
+  VCMP_I16(4, v1, 0xbeef, 0xbeef, 2560, 19901, 0xbeef, 0xbeef, 2560, 19901,
+           0xbeef, 0xbeef, 2560, 19901, 0xbeef, 0xbeef, 2560, 19901);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 12345, -80, 2560, -19900, 12345, -80, 2560, -19900, 12345, -80,
+           2560, -19900, 12345, -80, 2560, -19900);
+  VLOAD_32(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VLOAD_32(v1, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
+           0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
+           0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
+           0xdeadbeef);
+  asm volatile("vmax.vv v1, v2, v3, v0.t");
+  VCMP_I32(5, v1, 0xdeadbeef, 0xdeadbeef, 2560, 19901, 0xdeadbeef, 0xdeadbeef,
+           2560, 19901, 0xdeadbeef, 0xdeadbeef, 2560, 19901, 0xdeadbeef,
+           0xdeadbeef, 2560, 19901);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 12345, -80, 2560, -19900, 12345, -80, 2560, -19900, 12345, -80,
+           2560, -19900, 12345, -80, 2560, -19900);
+  VLOAD_64(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VLOAD_64(v1, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef);
+  asm volatile("vmax.vv v1, v2, v3, v0.t");
+  VCMP_I64(6, v1, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 2560, 19901,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 2560, 19901,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 2560, 19901,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 2560, 19901);
+};
+
+void TEST_CASE3(void) {
+  const uint64_t scalar = 40;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 123, -8, -25, 99, 123, -8, -25, 99, 123, -8, -25, 99, 123, -8,
+          -25, 99);
+  asm volatile("vmax.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_I8(7, v1, 123, 40, 40, 99, 123, 40, 40, 99, 123, 40, 40, 99, 123, 40, 40,
+          99);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 12345, -8, -25, 199, 12345, -8, -25, 199, 12345, -8, -25, 199,
+           12345, -8, -25, 199);
+  asm volatile("vmax.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_I16(8, v1, 12345, 40, 40, 199, 12345, 40, 40, 199, 12345, 40, 40, 199,
+           12345, 40, 40, 199);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 12345, -8, -25, 199, 12345, -8, -25, 199, 12345, -8, -25, 199,
+           12345, -8, -25, 199);
+  asm volatile("vmax.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_I32(9, v1, 12345, 40, 40, 199, 12345, 40, 40, 199, 12345, 40, 40, 199,
+           12345, 40, 40, 199);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 12345, -8, -25, 199, 12345, -8, -25, 199, 12345, -8, -25, 199,
+           12345, -8, -25, 199);
+  asm volatile("vmax.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_I64(10, v1, 12345, 40, 40, 199, 12345, 40, 40, 199, 12345, 40, 40, 199,
+           12345, 40, 40, 199);
+};
+
+void TEST_CASE4(void) {
+  const uint64_t scalar = 40;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 123, -8, -25, 99, 123, -8, -25, 99, 123, -8, -25, 99, 123, -8,
+          -25, 99);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VLOAD_8(v1, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef,
+          0xef, 0xef, 0xef, 0xef, 0xef);
+  asm volatile("vmax.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_I8(11, v1, 0xef, 0xef, 40, 99, 0xef, 0xef, 40, 99, 0xef, 0xef, 40, 99,
+          0xef, 0xef, 40, 99);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 12345, -8, -25, 199, 12345, -8, -25, 199, 12345, -8, -25, 199,
+           12345, -8, -25, 199);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VLOAD_16(v1, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef,
+           0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef);
+  asm volatile("vmax.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_I16(12, v1, 0xbeef, 0xbeef, 40, 199, 0xbeef, 0xbeef, 40, 199, 0xbeef,
+           0xbeef, 40, 199, 0xbeef, 0xbeef, 40, 199);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 12345, -8, -25, 199, 12345, -8, -25, 199, 12345, -8, -25, 199,
+           12345, -8, -25, 199);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VLOAD_32(v1, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
+           0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
+           0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
+           0xdeadbeef);
+  asm volatile("vmax.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_I32(13, v1, 0xdeadbeef, 0xdeadbeef, 40, 199, 0xdeadbeef, 0xdeadbeef, 40,
+           199, 0xdeadbeef, 0xdeadbeef, 40, 199, 0xdeadbeef, 0xdeadbeef, 40,
+           199);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 12345, -8, -25, 199, 12345, -8, -25, 199, 12345, -8, -25, 199,
+           12345, -8, -25, 199);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VLOAD_64(v1, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef);
+  asm volatile("vmax.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_I64(14, v1, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 40, 199,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 40, 199, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 40, 199, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           40, 199);
+};
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vmaxu.c b/apps/riscv-tests/isa/rv64uv/vmaxu.c
new file mode 100644
index 0000000..b166eb6
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vmaxu.c
@@ -0,0 +1,181 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 12345, 80, 2560, 19900, 12345, 80, 2560, 19900, 12345, 80, 2560,
+           19900, 12345, 80, 2560, 19900);
+  VLOAD_16(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  asm volatile("vmaxu.vv v1, v2, v3");
+  VCMP_U16(1, v1, 12345, 7000, 2560, 19901, 12345, 7000, 2560, 19901, 12345,
+           7000, 2560, 19901, 12345, 7000, 2560, 19901);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 12345, 80, 2560, 19900, 12345, 80, 2560, 19900, 12345, 80, 2560,
+           19900, 12345, 80, 2560, 19900);
+  VLOAD_32(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  asm volatile("vmaxu.vv v1, v2, v3");
+  VCMP_U32(2, v1, 12345, 7000, 2560, 19901, 12345, 7000, 2560, 19901, 12345,
+           7000, 2560, 19901, 12345, 7000, 2560, 19901);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 12345, 80, 2560, 19900, 12345, 80, 2560, 19900, 12345, 80, 2560,
+           19900, 12345, 80, 2560, 19900);
+  VLOAD_64(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  asm volatile("vmaxu.vv v1, v2, v3");
+  VCMP_U64(3, v1, 12345, 7000, 2560, 19901, 12345, 7000, 2560, 19901, 12345,
+           7000, 2560, 19901, 12345, 7000, 2560, 19901);
+};
+
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 12345, 80, 2560, 19900, 12345, 80, 2560, 19900, 12345, 80, 2560,
+           19900, 12345, 80, 2560, 19900);
+  VLOAD_16(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VLOAD_16(v1, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef,
+           0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef);
+  asm volatile("vmaxu.vv v1, v2, v3, v0.t");
+  VCMP_U16(4, v1, 0xbeef, 0xbeef, 2560, 19901, 0xbeef, 0xbeef, 2560, 19901,
+           0xbeef, 0xbeef, 2560, 19901, 0xbeef, 0xbeef, 2560, 19901);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 12345, 80, 2560, 19900, 12345, 80, 2560, 19900, 12345, 80, 2560,
+           19900, 12345, 80, 2560, 19900);
+  VLOAD_32(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VLOAD_32(v1, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
+           0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
+           0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
+           0xdeadbeef);
+  asm volatile("vmaxu.vv v1, v2, v3, v0.t");
+  VCMP_U32(5, v1, 0xdeadbeef, 0xdeadbeef, 2560, 19901, 0xdeadbeef, 0xdeadbeef,
+           2560, 19901, 0xdeadbeef, 0xdeadbeef, 2560, 19901, 0xdeadbeef,
+           0xdeadbeef, 2560, 19901);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 12345, 80, 2560, 19900, 12345, 80, 2560, 19900, 12345, 80, 2560,
+           19900, 12345, 80, 2560, 19900);
+  VLOAD_64(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VLOAD_64(v1, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef);
+  asm volatile("vmaxu.vv v1, v2, v3, v0.t");
+  VCMP_U64(6, v1, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 2560, 19901,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 2560, 19901,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 2560, 19901,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 2560, 19901);
+};
+
+void TEST_CASE3(void) {
+  const uint64_t scalar = 40;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 123, 8, 25, 199, 123, 8, 25, 199, 123, 8, 25, 199, 123, 8, 25,
+          199);
+  asm volatile("vmaxu.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U8(7, v1, 123, 40, 40, 199, 123, 40, 40, 199, 123, 40, 40, 199, 123, 40,
+          40, 199);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345,
+           8, 25, 199);
+  asm volatile("vmaxu.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U16(8, v1, 12345, 40, 40, 199, 12345, 40, 40, 199, 12345, 40, 40, 199,
+           12345, 40, 40, 199);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345,
+           8, 25, 199);
+  asm volatile("vmaxu.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U32(9, v1, 12345, 40, 40, 199, 12345, 40, 40, 199, 12345, 40, 40, 199,
+           12345, 40, 40, 199);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345,
+           8, 25, 199);
+  asm volatile("vmaxu.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U64(10, v1, 12345, 40, 40, 199, 12345, 40, 40, 199, 12345, 40, 40, 199,
+           12345, 40, 40, 199);
+};
+
+void TEST_CASE4(void) {
+  const uint64_t scalar = 40;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 123, 8, 25, 199, 123, 8, 25, 199, 123, 8, 25, 199, 123, 8, 25,
+          199);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VLOAD_8(v1, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef,
+          0xef, 0xef, 0xef, 0xef, 0xef);
+  asm volatile("vmaxu.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U8(11, v1, 0xef, 0xef, 40, 199, 0xef, 0xef, 40, 199, 0xef, 0xef, 40, 199,
+          0xef, 0xef, 40, 199);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345,
+           8, 25, 199);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VLOAD_16(v1, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef,
+           0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef);
+  asm volatile("vmaxu.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U16(12, v1, 0xbeef, 0xbeef, 40, 199, 0xbeef, 0xbeef, 40, 199, 0xbeef,
+           0xbeef, 40, 199, 0xbeef, 0xbeef, 40, 199);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345,
+           8, 25, 199);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VLOAD_32(v1, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
+           0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
+           0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
+           0xdeadbeef);
+  asm volatile("vmaxu.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U32(13, v1, 0xdeadbeef, 0xdeadbeef, 40, 199, 0xdeadbeef, 0xdeadbeef, 40,
+           199, 0xdeadbeef, 0xdeadbeef, 40, 199, 0xdeadbeef, 0xdeadbeef, 40,
+           199);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345,
+           8, 25, 199);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VLOAD_64(v1, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef);
+  asm volatile("vmaxu.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U64(14, v1, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 40, 199,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 40, 199, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 40, 199, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           40, 199);
+};
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vmerge.c b/apps/riscv-tests/isa/rv64uv/vmerge.c
new file mode 100644
index 0000000..2be295e
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vmerge.c
@@ -0,0 +1,113 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1() {
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v2, 8, 7, 6, 5, 4, 3, 2, 1, 8, 7, 6, 5, 4, 3, 2, 1);
+  VLOAD_8(v0, 0xAA, 0x55);
+  asm volatile("vmerge.vvm v3, v1, v2, v0");
+  VCMP_U8(1, v3, 1, 7, 3, 5, 5, 3, 7, 1, 8, 2, 6, 4, 4, 6, 2, 8);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v2, 8, 7, 6, 5, 4, 3, 2, 1, 8, 7, 6, 5, 4, 3, 2, 1);
+  VLOAD_8(v0, 0xAA, 0x55);
+  asm volatile("vmerge.vvm v3, v1, v2, v0");
+  VCMP_U16(2, v3, 1, 7, 3, 5, 5, 3, 7, 1, 8, 2, 6, 4, 4, 6, 2, 8);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v2, 8, 7, 6, 5, 4, 3, 2, 1, 8, 7, 6, 5, 4, 3, 2, 1);
+  VLOAD_8(v0, 0xAA, 0x55);
+  asm volatile("vmerge.vvm v3, v1, v2, v0");
+  VCMP_U32(3, v3, 1, 7, 3, 5, 5, 3, 7, 1, 8, 2, 6, 4, 4, 6, 2, 8);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_64(v2, 8, 7, 6, 5, 4, 3, 2, 1, 8, 7, 6, 5, 4, 3, 2, 1);
+  VLOAD_8(v0, 0xAA, 0x55);
+  asm volatile("vmerge.vvm v3, v1, v2, v0");
+  VCMP_U64(4, v3, 1, 7, 3, 5, 5, 3, 7, 1, 8, 2, 6, 4, 4, 6, 2, 8);
+}
+
+void TEST_CASE2() {
+  const uint64_t scalar = 0x00000000deadbeef;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0x55);
+  asm volatile("vmerge.vxm v3, v1, %[A], v0" ::[A] "r"(scalar));
+  VCMP_U8(5, v3, 1, 0xef, 3, 0xef, 5, 0xef, 7, 0xef, 0xef, 2, 0xef, 4, 0xef, 6,
+          0xef, 8);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0x55);
+  asm volatile("vmerge.vxm v3, v1, %[A], v0" ::[A] "r"(scalar));
+  VCMP_U16(6, v3, 1, 0xbeef, 3, 0xbeef, 5, 0xbeef, 7, 0xbeef, 0xbeef, 2, 0xbeef,
+           4, 0xbeef, 6, 0xbeef, 8);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0x55);
+  asm volatile("vmerge.vxm v3, v1, %[A], v0" ::[A] "r"(scalar));
+  VCMP_U32(7, v3, 1, 0xdeadbeef, 3, 0xdeadbeef, 5, 0xdeadbeef, 7, 0xdeadbeef,
+           0xdeadbeef, 2, 0xdeadbeef, 4, 0xdeadbeef, 6, 0xdeadbeef, 8);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0x55);
+  asm volatile("vmerge.vxm v3, v1, %[A], v0" ::[A] "r"(scalar));
+  VCMP_U64(8, v3, 1, 0x00000000deadbeef, 3, 0x00000000deadbeef, 5,
+           0x00000000deadbeef, 7, 0x00000000deadbeef, 0x00000000deadbeef, 2,
+           0x00000000deadbeef, 4, 0x00000000deadbeef, 6, 0x00000000deadbeef, 8);
+}
+
+void TEST_CASE3() {
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0x55);
+  asm volatile("vmerge.vim v3, v1, -1, v0");
+  VCMP_U8(9, v3, 1, 0xff, 3, 0xff, 5, 0xff, 7, 0xff, 0xff, 2, 0xff, 4, 0xff, 6,
+          0xff, 8);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0x55);
+  asm volatile("vmerge.vim v3, v1, -1, v0");
+  VCMP_U16(10, v3, 1, 0xffff, 3, 0xffff, 5, 0xffff, 7, 0xffff, 0xffff, 2,
+           0xffff, 4, 0xffff, 6, 0xffff, 8);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0x55);
+  asm volatile("vmerge.vim v3, v1, -1, v0");
+  VCMP_U32(11, v3, 1, 0xffffffff, 3, 0xffffffff, 5, 0xffffffff, 7, 0xffffffff,
+           0xffffffff, 2, 0xffffffff, 4, 0xffffffff, 6, 0xffffffff, 8);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0x55);
+  asm volatile("vmerge.vim v3, v1, -1, v0");
+  VCMP_U64(12, v3, 1, 0xffffffffffffffff, 3, 0xffffffffffffffff, 5,
+           0xffffffffffffffff, 7, 0xffffffffffffffff, 0xffffffffffffffff, 2,
+           0xffffffffffffffff, 4, 0xffffffffffffffff, 6, 0xffffffffffffffff, 8);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vmfeq.c b/apps/riscv-tests/isa/rv64uv/vmfeq.c
new file mode 100644
index 0000000..e169790
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vmfeq.c
@@ -0,0 +1,503 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+//         Matteo Perotti <mperotti@iis.ee.ethz.ch>
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+// This instruction writes a mask to a register, with a layout of elements as
+// described in section "Mask Register Layout"
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  //               0.2434,  0.7285,  0.7241, -0.2678,  0.0027, -0.7114,  0.2622,
+  //               0.8701, -0.5786, -0.4229,  0.5981,  0.6968,  0.7217, -0.2842,
+  //               0.1328,  0.1659
+  VLOAD_16(v2, 0x33ca, 0x39d4, 0x39cb, 0xb449, 0x1975, 0xb9b1, 0x3432, 0x3af6,
+           0xb8a1, 0xb6c4, 0x38c9, 0x3993, 0x39c6, 0xb48c, 0x3040, 0x314f);
+  //               0.7319,  0.0590,  0.7593, -0.6606, -0.4758,  0.8530,  0.0453,
+  //               0.0987,  0.1777,  0.3047,  0.2330, -0.3467, -0.4153,  0.7080,
+  //               0.3142, -0.9492
+  VLOAD_16(v3, 0x39db, 0x2b8c, 0x3a13, 0xb949, 0xb79d, 0x3ad3, 0x29cc, 0x2e51,
+           0x31b0, 0x34e0, 0x3375, 0xb58c, 0xb6a5, 0x39aa, 0x3041, 0xbb98);
+  asm volatile("vmfeq.vv v1, v2, v3");
+  VSET(1, e16, m1);
+  VCMP_U16(1, v1, 0x0);
+
+  VSET(16, e32, m1);
+  //                       +0,        sNaN, -0.34645590, -0.06222415,
+  //                       0.96037650, -0.81018746, -0.69337404,  0.70466602,
+  //                       -0.30920035, -0.31596854, -0.92116749,  0.51336122,
+  //                       0.22002794,  0.48599416,  0.69166088,  0.85755372
+  VLOAD_32(v2, 0x00000000, 0xffffffff, 0xbeb162ab, 0xbd7edebf, 0x3f75db3c,
+           0xbf4f6872, 0xbf3180f6, 0x3f3464fe, 0xbe9e4f82, 0xbea1c6a1,
+           0xbf6bd1a2, 0x3f036ba4, 0x3e614f01, 0x3ef8d43a, 0x3f3110b0,
+           0x3f5b88a4);
+  //                       -0,        sNaN,  0.39402914, -0.81853813,
+  //                       0.24656086, -0.71423489, -0.44735566, -0.25510681,
+  //                       -0.94378990, -0.30138883,  0.19188073, -0.29310879,
+  //                       -0.22981364, -0.58626360, -0.80913633, -0.00670803
+  VLOAD_32(v3, 0x80000000, 0xffffffff, 0x3ec9be30, 0xbf518bb7, 0x3e7c7a73,
+           0xbf36d819, 0xbee50bcd, 0xbe829d5c, 0xbf719c37, 0xbe9a4fa3,
+           0x3e447c62, 0xbe96125b, 0xbe6b5444, 0xbf16155f, 0xbf4f238f,
+           0xbbdbcefe);
+  asm volatile("vmfeq.vv v1, v2, v3");
+  VSET(1, e16, m1);
+  VCMP_U16(2, v1, 0x1);
+
+  VSET(16, e64, m1);
+  //               0.8643613633211786,  0.4842301798024149,  0.9229840140784857,
+  //               -0.9479687162489723, -0.1308855743137316,
+  //               -0.3798019472030296,  0.1570811980936915,
+  //               -0.7665403705017886, -0.3736408604742532, 0.4947226024634424,
+  //               -0.3032110323317654,  0.8998114670494881, 0.6283940115157876,
+  //               0.1053912590957002, -0.2936564640984622,  0.4329957213663693
+  VLOAD_64(v2, 0x3feba8d9296c7e74, 0x3fdefda0947f3460, 0x3fed8915c5665532,
+           0xbfee55c27d3d743e, 0xbfc0c0dbc6990b38, 0xbfd84eacd38c6ca4,
+           0x3fc41b3c98507fe0, 0xbfe8877fabcbce12, 0xbfd7e9bb5b0beaf8,
+           0x3fdfa988fd8b0a24, 0xbfd367cf3ee9af68, 0x3feccb416af162fc,
+           0x3fe41bcdc20ecd40, 0x3fbafaebeb19acf0, 0xbfd2cb447b63f610,
+           0x3fdbb633afa4e520);
+  //              -0.3562510538138417, -0.0135629748736219,  0.6176167733891369,
+  //              0.9703747829163081, -0.0909539316920625, -0.1057326828885887,
+  //              -0.8792039527057112, -0.1745056251010144,  0.3110320594479206,
+  //              0.3238986651420683, -0.9079294226891812, -0.9490909352855985,
+  //              0.6962970677624296,  0.7585780695949504, -0.5927175227484118,
+  //              -0.7793965434104730
+  VLOAD_64(v3, 0xbfd6ccd13852f170, 0xbf8bc6e7ac263f80, 0x3fed8915c5665532,
+           0x3fef0d4f6aafa2f6, 0xbfb748c1c20f5de0, 0xbfbb114c0f1ff4b0,
+           0xbfec227053ec5198, 0xbfc6563348637140, 0x3fd3e7f302d586b4,
+           0x3fd4bac177803510, 0xbfed0dc20130d694, 0xbfee5ef3f3ff6a12,
+           0x3fe64810c9cae3fe, 0x3fe84645840bf0a2, 0xbfe2f78abcff0ede,
+           0xbfe8f0d105120796);
+  asm volatile("vmfeq.vv v1, v2, v3");
+  VSET(1, e16, m1);
+  VCMP_U16(3, v1, 0x4);
+};
+
+// Simple random test with similar values + 1 subnormal (masked)
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  //               0.2434,  0.7285,  0.7241, -0.2678,  0.0027, -0.7114,  0.2622,
+  //               0.8701, -0.5786, -0.4229,  0.5981,  0.6968,  0.7217, -0.2842,
+  //               0.1328,  0.1659
+  VLOAD_16(v2, 0x33ca, 0x39d4, 0x39cb, 0xb449, 0x1975, 0xb9b1, 0x3432, 0x3af6,
+           0xb8a1, 0xb6c4, 0x38c9, 0x3993, 0x39c6, 0xb48c, 0x3040, 0x314f);
+  //               0.7319,  0.7285,  0.7593, -0.6606, -0.4758,  0.8530,  0.0453,
+  //               0.0987,  0.1777,  0.3047,  0.2330, -0.3467, -0.4153,  0.7080,
+  //               0.3142, -0.9492
+  VLOAD_16(v3, 0x39db, 0x39d4, 0x3a13, 0xb949, 0xb79d, 0x3ad3, 0x29cc, 0x2e51,
+           0x31b0, 0x34e0, 0x3375, 0xb58c, 0xb6a5, 0x39aa, 0x3507, 0xbb98);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmfeq.vv v1, v2, v3, v0.t");
+  VSET(1, e16, m1);
+  VCMP_U16(4, v1, 0x0002);
+
+  VSET(16, e32, m1);
+  //               0x00000000,  0.09933749, -0.34645590, -0.06222415,
+  //               0.96037650, -0.81018746, -0.69337404,  0.70466602,
+  //               -0.30920035, -0.31596854, -0.92116749,  0.51336122,
+  //               0.22002794,  0.48599416,  0.69166088,  0.85755372
+  VLOAD_32(v2, 0x00000000, 0x3dcb7174, 0xbeb162ab, 0xbd7edebf, 0x3f75db3c,
+           0xbf4f6872, 0xbf3180f6, 0x3f3464fe, 0xbe9e4f82, 0xbea1c6a1,
+           0xbf6bd1a2, 0x3f036ba4, 0x3e614f01, 0x3ef8d43a, 0x3f3110b0,
+           0x3f5d88a4);
+  //               0x00000000, -0.64782482,  0.39402914, -0.81853813,
+  //               0.24656086, -0.71423489, -0.44735566, -0.25510681,
+  //               -0.94378990, -0.30138883,  0.19188073, -0.29310879,
+  //               -0.22981364, -0.58626360, -0.80913633,  0.85755372
+  VLOAD_32(v3, 0x00000000, 0xbf25d7d9, 0x3ec9be30, 0xbf518bb7, 0x3e7c7a73,
+           0xbf36d819, 0xbee50bcd, 0xbe829d5c, 0xbf719c37, 0xbe9a4fa3,
+           0x3e447c62, 0xbe96125b, 0xbe6b5444, 0xbf16155f, 0xbf4f238f,
+           0x3f5d88a4);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmfeq.vv v1, v2, v3, v0.t");
+  VSET(1, e16, m1);
+  VCMP_U16(5, v1, 0x8000);
+
+  VSET(16, e64, m1);
+  //               0.8643613633211786,  0.4842301798024149,  0.9229840140784857,
+  //               -0.9479687162489723, -0.1308855743137316,
+  //               -0.3798019472030296,  0.1570811980936915,
+  //               -0.7665403705017886, -0.3736408604742532, 0.4947226024634424,
+  //               -0.3032110323317654,  0.8998114670494881, 0.6283940115157876,
+  //               0.1053912590957002, -0.2936564640984622, -0.7793965434104730
+  VLOAD_64(v2, 0x3feba8d9296c7e74, 0x3fdefda0947f3460, 0x3fed8915c5665532,
+           0xbfee55c27d3d743e, 0xbfc0c0dbc6990b38, 0xbfd84eacd38c6ca4,
+           0x3fc41b3c98507fe0, 0xbfe8877fabcbce12, 0xbfd7e9bb5b0beaf8,
+           0x3fdfa988fd8b0a24, 0xbfd367cf3ee9af68, 0x3feccb416af162fc,
+           0x3fe41bcdc20ecd40, 0x3fbafaebeb19acf0, 0xbfd2cb447b63f610,
+           0xbfe8f0d105120796);
+  //               0.8643613633211786,  0.4842301798024149,  0.6176167733891369,
+  //               0.9703747829163081, -0.0909539316920625, -0.1057326828885887,
+  //               -0.8792039527057112, -0.1745056251010144, 0.3110320594479206,
+  //               0.3238986651420683, -0.9079294226891812, -0.9490909352855985,
+  //               0.6962970677624296,  0.7585780695949504, -0.5927175227484118,
+  //               -0.7793965434104730
+  VLOAD_64(v3, 0x3feba8d9296c7e74, 0x3fdefda0947f3460, 0x3fed8915c5665532,
+           0xbfee55c27d3d743e, 0xbfb748c1c20f5de0, 0xbfbb114c0f1ff4b0,
+           0xbfec227053ec5198, 0xbfc6563348637140, 0x3fd3e7f302d586b4,
+           0x3fd4bac177803510, 0xbfed0dc20130d694, 0xbfee5ef3f3ff6a12,
+           0x3fe64810c9cae3fe, 0x3fe84645840bf0a2, 0xbfe2f78abcff0ede,
+           0xbfe8f0d105120796);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmfeq.vv v1, v2, v3, v0.t");
+  VSET(1, e16, m1);
+  VCMP_U16(6, v1, 0x800a);
+};
+
+// Simple random test with similar values (vector-scalar)
+void TEST_CASE3(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //                             -0.2649
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0xb43d);
+  //              -0.0651,  0.5806,  0.2563, -0.4783,  0.7393, -0.2649, -0.4590,
+  //              0.5469, -0.9082,  0.6235, -0.8276, -0.7939, -0.0236, -0.1166,
+  //              0.4026,  0.0022
+  VLOAD_16(v2, 0xac2a, 0x38a5, 0x341a, 0xb7a7, 0x39ea, 0xb43d, 0xb758, 0x3860,
+           0xbb44, 0x38fd, 0xba9f, 0xba5a, 0xa60b, 0xaf76, 0x3671, 0x1896);
+  asm volatile("vmfeq.vf v1, v2, %[A]" ::[A] "f"(dscalar_16));
+  VSET(1, e16, m1);
+  VCMP_U16(7, v1, 0x0020);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                               0.80517912
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0x3f4e2038);
+  //              -0.15601152, -0.92020410, -0.29387674,  0.98594254,
+  //              0.88163614, -0.44641387,  0.88191622,  0.15161350,
+  //              -0.79952192, -0.03668820, -0.38464722, -0.54745716,
+  //              0.09956384,  0.21655059, -0.37557366, -0.79342169
+  VLOAD_32(v2, 0xbe1fc17c, 0x3f4e2038, 0x3f4e2038, 0x3f4e2038, 0x3f4e2038,
+           0x3f4e2038, 0x3f4e2038, 0x3f4e2038, 0x3f4e2038, 0x3f4e2038,
+           0x3f4e2038, 0x3f4e2038, 0x3f4e2038, 0x3f4e2038, 0x3f4e2038,
+           0xbf4b1daf);
+  asm volatile("vmfeq.vf v1, v2, %[A]" ::[A] "f"(dscalar_32));
+  VSET(1, e16, m1);
+  VCMP_U16(8, v1, 0x7ffe);
+
+  VSET(16, e64, m1);
+  double dscalar_64;
+  //                               -0.3394093097660049
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0xbfd5b8e1d359c984);
+  //                0.8852775142880511, -0.1502080091211320,
+  //                -0.7804423569145378,  0.4585094341291300,
+  //                0.8417440789882031, -0.1215927835809432, 0.9442717441528423,
+  //                -0.3993868853091622,  0.5719771249018739,
+  //                0.0497853851400327,  0.6627817945481365, 0.2150621318612425,
+  //                -0.8506676370622683, -0.4531982633526939,
+  //                0.5943189287417812, -0.5034380636605356
+  VLOAD_64(v2, 0x3fec543182780b14, 0xbfc33a041b62e250, 0xbfe8f9623feb8e20,
+           0xbfd5b8e1d359c984, 0x3feaef91475b6422, 0xbfbf20b464e8e5d0,
+           0x3fee377960758bfa, 0xbfd98f8e02b6aa78, 0x3fe24da2f8b06fde,
+           0x3fa97d7851fd8b80, 0x3fe535822a7efd70, 0x3fcb8727eb79dda0,
+           0xbfeb38ab561e5658, 0xbfdd013349ed0b50, 0x3fe304a9214adedc,
+           0xbfe01c2a245f7960);
+  asm volatile("vmfeq.vf v1, v2, %[A]" ::[A] "f"(dscalar_64));
+  VSET(1, e16, m1);
+  VCMP_U16(9, v1, 0x0008);
+};
+
+// Simple random test with similar values (vector-scalar) (masked)
+void TEST_CASE4(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //                             -0.2649
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0xb43d);
+  //               -0.2649,  0.5806, -0.2649, -0.4783, -0.2649, -0.2649,
+  //               -0.2649, -0.2649, -0.2649, -0.2649, -0.2649, -0.2649,
+  //               -0.2649, -0.2649, -0.2649, -0.2649,
+  VLOAD_16(v2, 0xb43d, 0x7653, 0xad3d, 0x033d, 0xb43d, 0xb43d, 0xb43d, 0xb43d,
+           0xb43d, 0xb43d, 0xb43d, 0xb43d, 0xb43d, 0xb43d, 0xb43d, 0xb43d);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmfeq.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_16));
+  VSET(1, e16, m1);
+  VCMP_U16(10, v1, 0xaaa0);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                               0.80517912
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0x3f4e2038);
+  //                0.80517912,  0.80517912, -0.29387674,  0.98594254,
+  //                0.88163614, -0.44641387,  0.88191622,  0.15161350,
+  //                -0.79952192, -0.03668820, -0.38464722, -0.54745716,
+  //                0.09956384,  0.21655059, -0.37557366, -0.79342169
+  VLOAD_32(v2, 0x3f4e2038, 0x3f4e2038, 0xbe967703, 0x3f7c66bb, 0x3f61b2e8,
+           0xbee4905c, 0x3f61c543, 0x3e1b4092, 0xbf4cad78, 0xbd16465d,
+           0xbec4f07b, 0xbf0c2627, 0x3dcbe820, 0x3e5dbf70, 0xbec04b31,
+           0xbf4b1daf);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmfeq.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_32));
+  VSET(1, e16, m1);
+  VCMP_U16(11, v1, 0x0002);
+
+  VSET(16, e64, m1);
+  double dscalar_64;
+  //                               -0.3394093097660049
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0xbfd5b8e1d359c984);
+  //                 0.8852775142880511, -0.1502080091211320,
+  //                 -0.7804423569145378, -0.3394093097660049,
+  //                 0.8417440789882031, -0.1215927835809432,
+  //                 0.9442717441528423, -0.3993868853091622,
+  //                 0.5719771249018739,  0.0497853851400327,
+  //                 0.6627817945481365,  0.2150621318612425,
+  //                 -0.8506676370622683, -0.4531982633526939,
+  //                 0.5943189287417812, -0.5034380636605356
+  VLOAD_64(v2, 0x3fec543182780b14, 0xbfc33a041b62e250, 0xbfe8f9623feb8e20,
+           0xbfd5b8e1d359c984, 0x3feaef91475b6422, 0xbfbf20b464e8e5d0,
+           0x3fee377960758bfa, 0xbfd98f8e02b6aa78, 0x3fe24da2f8b06fde,
+           0x3fa97d7851fd8b80, 0x3fe535822a7efd70, 0x3fcb8727eb79dda0,
+           0xbfeb38ab561e5658, 0xbfdd013349ed0b50, 0x3fe304a9214adedc,
+           0xbfe01c2a245f7960);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmfeq.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_64));
+  VSET(1, e16, m1);
+  VCMP_U16(12, v1, 0x0008);
+};
+
+// Check if only the correct destination bits are written
+void TEST_CASE5(void) {
+  // Fill 64-bits with 1
+  VSET(1, e64, m1);
+  VLOAD_64(v1, 0xffffffffffffffff);
+  // Perform vmfeq.vv on 16 different elements, and then check that the last (64
+  // - 16 = 48) bits were not overwritten with zeroes
+  VSET(16, e16, m1);
+  //               0.2434,  0.7285,  0.7241, -0.2678,  0.0027, -0.7114,  0.2622,
+  //               0.8701, -0.5786, -0.4229,  0.5981,  0.6968,  0.7217, -0.2842,
+  //               0.1328,  0.1659
+  VLOAD_16(v2, 0x33ca, 0x39d4, 0x39cb, 0xb449, 0x1975, 0xb9b1, 0x3432, 0x3af6,
+           0xb8a1, 0xb6c4, 0x38c9, 0x3993, 0x39c6, 0xb48c, 0x3040, 0x314f);
+  //               0.7319,  0.0590,  0.7593, -0.6606, -0.4758,  0.8530,  0.0453,
+  //               0.0987,  0.1777,  0.3047,  0.2330, -0.3467, -0.4153,  0.7080,
+  //               0.3142, -0.9492
+  VLOAD_16(v3, 0x33ca, 0x2b8c, 0x3a13, 0xb949, 0xb79d, 0x3ad3, 0x29cc, 0x2e51,
+           0x31b0, 0x34e0, 0x3375, 0xb58c, 0xb6a5, 0x39aa, 0x3041, 0xbb98);
+  asm volatile("vmfeq.vv v1, v2, v3");
+  VSET(1, e64, m1);
+  VCMP_U64(13, v1, 0xffffffffffff0001);
+
+  // Fill 64-bits with 1
+  VSET(1, e64, m1);
+  VLOAD_64(v1, 0xffffffffffffffff);
+  // Perform vmfeq.vv on 16 different elements, and then check that the last (64
+  // - 16 = 48) bits were not overwritten with zeroes
+  VSET(16, e32, m1);
+  //              -0.72077256,        sNaN, -0.34645590, -0.06222415,
+  //              0.96037650, -0.81018746, -0.69337404,  0.70466602,
+  //              -0.30920035, -0.31596854, -0.92116749,  0.51336122,
+  //              0.22002794,  0.48599416,  0.69166088,  0.85755372
+  VLOAD_32(v2, 0x70000000, 0xffffffff, 0xbeb162ab, 0xbd7edebf, 0x3f75db3c,
+           0xbf4f6872, 0xbf3180f6, 0x3f3464fe, 0xbe9e4f82, 0xbea1c6a1,
+           0xbf6bd1a2, 0x3f036ba4, 0x3e614f01, 0x3ef8d43a, 0x3f3110b0,
+           0x3f5b88a4);
+  //               0.79994357,        sNaN, -0.34645590, -0.81853813,
+  //               0.24656086, -0.71423489, -0.44735566, -0.25510681,
+  //               -0.94378990, -0.30138883,  0.19188073, -0.29310879,
+  //               -0.22981364, -0.58626360, -0.80913633, -0.00670803
+  VLOAD_32(v3, 0x80000000, 0xffffffff, 0xbeb162ab, 0xbf518bb7, 0x3e7c7a73,
+           0xbf36d819, 0xbee50bcd, 0xbe829d5c, 0xbf719c37, 0xbe9a4fa3,
+           0x3e447c62, 0xbe96125b, 0xbe6b5444, 0xbf16155f, 0xbf4f238f,
+           0xbbdbcefe);
+  asm volatile("vmfeq.vv v1, v2, v3");
+  VSET(1, e64, m1);
+  VCMP_U64(14, v1, 0xffffffffffff0004);
+
+  // Fill 64-bits with 1
+  VSET(1, e64, m1);
+  VLOAD_64(v1, 0xffffffffffffffff);
+  // Perform vmfeq.vv on 16 different elements, and then check that the last (64
+  // - 16 = 48) bits were not overwritten with zeroes
+  VSET(16, e64, m1);
+  //               0.8643613633211786,  0.4842301798024149,  0.9229840140784857,
+  //               -0.9479687162489723, -0.1308855743137316,
+  //               -0.3798019472030296,  0.1570811980936915,
+  //               -0.7665403705017886, -0.3736408604742532, 0.4947226024634424,
+  //               -0.3032110323317654,  0.8998114670494881, 0.6283940115157876,
+  //               0.1053912590957002, -0.2936564640984622,  0.4329957213663693
+  VLOAD_64(v2, 0x3feba8d9296c7e74, 0x3fdefda0947f3460, 0xbf3180f63f75db3c,
+           0xbfee55c27d3d743e, 0xbfc0c0dbc6990b38, 0xbfd84eacd38c6ca4,
+           0x3fc41b3c98507fe0, 0xbfe8877fabcbce12, 0xbfd7e9bb5b0beaf8,
+           0x3fdfa988fd8b0a24, 0xbfd367cf3ee9af68, 0x3feccb416af162fc,
+           0x3fe41bcdc20ecd40, 0x3fbafaebeb19acf0, 0xbfd2cb447b63f610,
+           0x3fdbb633afa4e520);
+  //               0.8643613633211786, -0.0135629748736219,  0.6176167733891369,
+  //               0.9703747829163081, -0.0909539316920625, -0.1057326828885887,
+  //               -0.8792039527057112, -0.1745056251010144, 0.3110320594479206,
+  //               0.3238986651420683, -0.9079294226891812, -0.9490909352855985,
+  //               0.6962970677624296,  0.7585780695949504, -0.5927175227484118,
+  //               -0.7793965434104730
+  VLOAD_64(v3, 0x3feba8d9296c7e74, 0xbf8bc6e7ac263f80, 0x3fed8915c5665532,
+           0x3fef0d4f6aafa2f6, 0xbfb748c1c20f5de0, 0xbfbb114c0f1ff4b0,
+           0xbfec227053ec5198, 0xbfc6563348637140, 0x3fd3e7f302d586b4,
+           0x3fd4bac177803510, 0xbfed0dc20130d694, 0xbfee5ef3f3ff6a12,
+           0x3fe64810c9cae3fe, 0x3fe84645840bf0a2, 0xbfe2f78abcff0ede,
+           0xbfe8f0d105120796);
+  asm volatile("vmfeq.vv v1, v2, v3");
+  VSET(1, e64, m1);
+  VCMP_U64(15, v1, 0xffffffffffff0001);
+};
+
+// Write to v0 during a masked operation, WAR dependency should be respected
+void TEST_CASE6(void) {
+  VSET(16, e16, m1);
+  //               0.2434,  0.7285,  0.7241,  0.7241,  0.0027, -0.7114,  0.8701,
+  //               0.8701, -0.5786, -0.4229,  0.6968,  0.6968,  0.7217, -0.2842,
+  //               0.1659,  0.1659
+  VLOAD_16(v2, 0x33ca, 0x39d4, 0x39cb, 0xb449, 0x1975, 0xb9b1, 0x3af6, 0x3af6,
+           0xb8a1, 0xb6c4, 0x3993, 0x3993, 0x39c6, 0xb48c, 0x314f, 0x314f);
+  //               0.2434,  0.7285, -0.2678, -0.2678,  0.0027, -0.7114,  0.2622,
+  //               0.2622, -0.5786, -0.4229,  0.5981,  0.5981,  0.7217, -0.2842,
+  //               0.1328,  0.1328
+  VLOAD_16(v3, 0x33ca, 0x39d4, 0xb449, 0x39cb, 0x1975, 0xb9b1, 0x3432, 0x3432,
+           0xb8a1, 0xb6c4, 0x38c9, 0x38c9, 0x39c6, 0xb48c, 0x3040, 0x3040);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmfeq.vv v0, v2, v3, v0.t");
+  VSET(1, e16, m1);
+  VCMP_U16(16, v0, 0x2222);
+
+  VSET(16, e32, m1);
+  //               0x00000000,  0.09933749, -0.34645590, -0.06222415,
+  //               0.96037650, -0.81018746, -0.69337404,  0.70466602,
+  //               -0.30920035, -0.31596854, -0.92116749,  0.51336122,
+  //               0.22002794,  0.48599416,  0.69166088,  0.85755372
+  VLOAD_32(v2, 0x00000000, 0x3dcb7174, 0xbeb162ab, 0xbd7edebf, 0x3f75db3c,
+           0xbf4f6872, 0xbf3180f6, 0x3f3464fe, 0xbe9e4f82, 0xbea1c6a1,
+           0xbf6bd1a2, 0x3f036ba4, 0x3e614f01, 0x3ef8d43a, 0x3f3110b0,
+           0x3f5d88a4);
+  //               0x00000000,  0.09933749,  0.39402914, -0.81853813,
+  //               0.96037650, -0.81018746, -0.44735566, -0.25510681,
+  //               -0.30920035, -0.31596854,  0.19188073, -0.29310879,
+  //               0.22002794,  0.48599416, -0.80913633, -0.30138883
+  VLOAD_32(v3, 0x00000000, 0x3dcb7174, 0x3ec9be30, 0xbf518bb7, 0x3f75db3c,
+           0xbf4f6872, 0xbee50bcd, 0xbe829d5c, 0xbe9e4f82, 0xbea1c6a1,
+           0x3e447c62, 0xbe96125b, 0x3e614f01, 0x3ef8d43a, 0xbf4f238f,
+           0xbe9a4fa3);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmfeq.vv v0, v2, v3, v0.t");
+  VSET(1, e16, m1);
+  VCMP_U16(17, v0, 0x2222);
+
+  VSET(16, e64, m1);
+  //               0.8643613633211786,  0.4842301798024149,  0.9229840140784857,
+  //               -0.8792039527057112, -0.1308855743137316,
+  //               -0.3798019472030296,  0.1570811980936915,
+  //               -0.7665403705017886, -0.3736408604742532, 0.4947226024634424,
+  //               -0.3032110323317654,  0.8998114670494881, 0.6283940115157876,
+  //               0.1053912590957002, -0.2936564640984622, -0.7793965434104730
+  VLOAD_64(v2, 0x3feba8d9296c7e74, 0x3fdefda0947f3460, 0x3fed8915c5665532,
+           0xbfec227053ec5198, 0xbfc0c0dbc6990b38, 0xbfd84eacd38c6ca4,
+           0x3fc41b3c98507fe0, 0xbfe8877fabcbce12, 0xbfd7e9bb5b0beaf8,
+           0x3fdfa988fd8b0a24, 0xbfd367cf3ee9af68, 0x3feccb416af162fc,
+           0x3fe41bcdc20ecd40, 0x3fbafaebeb19acf0, 0xbfd2cb447b63f610,
+           0xbfe8f0d105120796);
+  //               0.8643613633211786,  0.4842301798024149, -0.8792039527057112,
+  //               0.9703747829163081, -0.1308855743137316, -0.3798019472030296,
+  //               -0.8792039527057112, -0.1745056251010144,
+  //               -0.3736408604742532,  0.4947226024634424,
+  //               -0.9079294226891812, -0.9490909352855985, 0.6283940115157876,
+  //               0.1053912590957002, -0.5927175227484118, -0.3032110323317654
+  VLOAD_64(v3, 0x3feba8d9296c7e74, 0x3fdefda0947f3460, 0xbfec227053ec5198,
+           0x9fee55c27d3d743e, 0xbfc0c0dbc6990b38, 0xbfd84eacd38c6ca4,
+           0xbfec227053ec5198, 0xbfc6563348637140, 0xbfd7e9bb5b0beaf8,
+           0x3fdfa988fd8b0a24, 0xbfed0dc20130d694, 0xbfee5ef3f3ff6a12,
+           0x3fe41bcdc20ecd40, 0x3fbafaebeb19acf0, 0xbfe2f78abcff0ede,
+           0xbfd367cf3ee9af68);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmfeq.vv v0, v2, v3, v0.t");
+  VSET(1, e16, m1);
+  VCMP_U16(18, v0, 0x2222);
+};
+
+// Test sNaN/qNaN behaviour
+void TEST_CASE7(void) {
+  CLEAR_FFLAGS;
+  // First, give only qNaN (no exception is generated)
+  VSET(16, e16, m1);
+  CHECK_FFLAGS(0);
+  VLOAD_16(v2, qNaNh, qNaNh, 0x39cb, qNaNh, 0x1975, 0xb9b1, 0x3af6, 0x3af6,
+           0xb8a1, 0xb6c4, 0x3993, 0x3993, qNaNh, 0xb48c, qNaNh, qNaNh);
+  VLOAD_16(v3, 0x33ca, qNaNh, qNaNh, 0x39cb, 0x1975, 0xb9b1, 0x3432, 0x3432,
+           0xb8a1, 0xb6c4, 0x38c9, 0x38c9, 0x39c6, qNaNh, qNaNh, 0x3040);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmfeq.vv v0, v2, v3");
+  VSET(1, e16, m1);
+  VCMP_U16(19, v0, 0x0330);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x3f75db3c, qNaNf, qNaNf, qNaNf, 0x3f75db3c, 0xbf4f6872,
+           0xbf3180f6, 0x3f3464fe, 0xbe9e4f82, 0xbea1c6a1, 0xbf6bd1a2,
+           0x3f036ba4, qNaNf, qNaNf, 0x3f3110b0, qNaNf);
+  VLOAD_32(v3, 0x3f75db3c, 0x3dcb7174, qNaNf, 0xbf518bb7, 0x3f75db3c,
+           0xbf4f6872, 0xbee50bcd, 0xbe829d5c, 0xbe9e4f82, 0xbea1c6a1,
+           0x3e447c62, 0xbe96125b, qNaNf, 0x3ef8d43a, qNaNf, qNaNf);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmfeq.vv v0, v2, v3");
+  VSET(1, e16, m1);
+  VCMP_U16(20, v0, 0x0331);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, qNaNd, qNaNd, 0x3fed8915c5665532, 0xbfec227053ec5198,
+           0xbfc0c0dbc6990b38, 0xbfd84eacd38c6ca4, 0x3fc41b3c98507fe0,
+           0xbfe8877fabcbce12, 0xbfd7e9bb5b0beaf8, 0x3fdfa988fd8b0a24,
+           0xbfd367cf3ee9af68, 0x3feccb416af162fc, qNaNd, qNaNd,
+           0xbfd2cb447b63f610, qNaNd);
+  VLOAD_64(v3, qNaNd, 0x3fdefda0947f3460, qNaNd, 0x9fee55c27d3d743e,
+           0xbfc0c0dbc6990b38, 0xbfd84eacd38c6ca4, 0xbfec227053ec5198,
+           0xbfc6563348637140, 0xbfd7e9bb5b0beaf8, 0x3fdfa988fd8b0a24,
+           0xbfed0dc20130d694, 0xbfee5ef3f3ff6a12, qNaNd, 0x3fbafaebeb19acf0,
+           qNaNd, qNaNd);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmfeq.vv v0, v2, v3");
+  VSET(1, e16, m1);
+  VCMP_U16(21, v0, 0x0330);
+  CHECK_FFLAGS(0);
+
+  // Give sNaN (Invalid operation)
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x3f75db3c, sNaNf, sNaNf, qNaNf, 0x3f75db3c, 0xbf4f6872,
+           0xbf3180f6, 0x3f3464fe, 0xbe9e4f82, 0xbea1c6a1, 0xbf6bd1a2,
+           0x3f036ba4, qNaNf, qNaNf, 0x3f3110b0, qNaNf);
+  VLOAD_32(v3, 0x3f75db3c, 0x3dcb7174, qNaNf, 0xbf518bb7, 0x3f75db3c,
+           0xbf4f6872, 0xbee50bcd, 0xbe829d5c, 0xbe9e4f82, 0xbea1c6a1,
+           0x3e447c62, 0xbe96125b, qNaNf, 0x3ef8d43a, qNaNf, qNaNf);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmfeq.vv v0, v2, v3");
+  VSET(1, e16, m1);
+  VCMP_U16(22, v0, 0x0331);
+  CHECK_FFLAGS(NV);
+};
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+  enable_fp();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  //  TEST_CASE5();
+  TEST_CASE6();
+  TEST_CASE7();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vmfge.c b/apps/riscv-tests/isa/rv64uv/vmfge.c
new file mode 100644
index 0000000..8a82ae7
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vmfge.c
@@ -0,0 +1,134 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+//         Matteo Perotti <mperotti@iis.ee.ethz.ch>
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+// Simple random test with similar values (vector-scalar)
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //                             -0.2649
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0xb43d);
+  //              -0.0651,  0.5806,  0.2563, -0.4783,  0.7393, -0.2649, -0.4590,
+  //              0.5469, -0.9082,  0.6235, -0.8276, -0.7939, -0.0236, -0.1166,
+  //              0.4026,  0.0022
+  VLOAD_16(v2, 0xac2a, 0x38a5, 0x341a, 0xb7a7, 0x39ea, 0xb43d, 0xb758, 0x3860,
+           0xbb44, 0x38fd, 0xba9f, 0xba5a, 0xa60b, 0xaf76, 0x3671, 0x1896);
+  asm volatile("vmfge.vf v1, v2, %[A]" ::[A] "f"(dscalar_16));
+  VSET(1, e16, m1);
+  VCMP_U16(1, v1, 0xf2b7);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                               0.80517912
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0x3f4e2038);
+  //              -0.15601152, -0.92020410, -0.29387674,  0.98594254,
+  //              0.88163614, -0.44641387,  0.88191622,  0.15161350,
+  //              -0.79952192, -0.03668820, -0.38464722, -0.54745716,
+  //              0.09956384,  0.21655059, -0.37557366, -0.79342169
+  VLOAD_32(v2, 0xbe1fc17c, 0x3f4e2038, 0x3f4e2038, 0x3f4e2038, 0x3f4e2038,
+           0x3f4e2038, 0x3f4e2038, 0x3f4e2038, 0x3f4e2038, 0x3f4e2038,
+           0x3f4e2038, 0x3f4e2038, 0x3f4e2038, 0x3f4e2038, 0x3f4e2038,
+           0xbf4b1daf);
+  asm volatile("vmfge.vf v1, v2, %[A]" ::[A] "f"(dscalar_32));
+  VSET(1, e16, m1);
+  VCMP_U16(2, v1, 0x7ffe);
+
+  VSET(16, e64, m1);
+  double dscalar_64;
+  //                               -0.3394093097660049
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0xbfd5b8e1d359c984);
+  //                0.8852775142880511, -0.1502080091211320,
+  //                -0.7804423569145378,  0.4585094341291300,
+  //                0.8417440789882031, -0.1215927835809432, 0.9442717441528423,
+  //                -0.3993868853091622,  0.5719771249018739,
+  //                0.0497853851400327,  0.6627817945481365, 0.2150621318612425,
+  //                -0.8506676370622683, -0.4531982633526939,
+  //                0.5943189287417812, -0.5034380636605356
+  VLOAD_64(v2, 0x3fec543182780b14, 0xbfc33a041b62e250, 0xbfe8f9623feb8e20,
+           0xbfd5b8e1d359c984, 0x3feaef91475b6422, 0xbfbf20b464e8e5d0,
+           0x3fee377960758bfa, 0xbfd98f8e02b6aa78, 0x3fe24da2f8b06fde,
+           0x3fa97d7851fd8b80, 0x3fe535822a7efd70, 0x3fcb8727eb79dda0,
+           0xbfeb38ab561e5658, 0xbfdd013349ed0b50, 0x3fe304a9214adedc,
+           0xbfe01c2a245f7960);
+  asm volatile("vmfge.vf v1, v2, %[A]" ::[A] "f"(dscalar_64));
+  VSET(1, e16, m1);
+  VCMP_U16(3, v1, 0x4f7b);
+};
+
+// Simple random test with similar values (vector-scalar) (masked)
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //                             -0.2649
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0xb43d);
+  //               -0.2649,  0.5806, -0.2649, -0.4783, -0.2649, -0.2649,
+  //               -0.2649, -0.2649, -0.2649, -0.2649, -0.2649, -0.2649,
+  //               -0.2649, -0.2649, -0.2649, -0.2649,
+  VLOAD_16(v2, 0xb43d, 0x7653, 0xad3d, 0x033d, 0xb43d, 0xb43d, 0xb43d, 0xb43d,
+           0xb43d, 0xb43d, 0xb43d, 0xb43d, 0xb43d, 0xb43d, 0xb43d, 0xb43d);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmfge.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_16));
+  VSET(1, e16, m1);
+  VCMP_U16(4, v1, 0xaaaa);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                               0.80517912
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0x3f4e2038);
+  //                0.80517912,  0.80517912, -0.29387674,  0.98594254,
+  //                0.88163614, -0.44641387,  0.88191622,  0.15161350,
+  //                -0.79952192, -0.03668820, -0.38464722, -0.54745716,
+  //                0.09956384,  0.21655059, -0.37557366, -0.79342169
+  VLOAD_32(v2, 0x3f4e2038, 0x3f4e2038, 0xbe967703, 0x3f7c66bb, 0x3f61b2e8,
+           0xbee4905c, 0x3f61c543, 0x3e1b4092, 0xbf4cad78, 0xbd16465d,
+           0xbec4f07b, 0xbf0c2627, 0x3dcbe820, 0x3e5dbf70, 0xbec04b31,
+           0xbf4b1daf);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmfge.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_32));
+  VSET(1, e16, m1);
+  VCMP_U16(5, v1, 0x000a);
+
+  VSET(16, e64, m1);
+  double dscalar_64;
+  //                               -0.3394093097660049
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0xbfd5b8e1d359c984);
+  //                 0.8852775142880511, -0.1502080091211320,
+  //                 -0.7804423569145378, -0.3394093097660049,
+  //                 0.8417440789882031, -0.1215927835809432,
+  //                 0.9442717441528423, -0.3993868853091622,
+  //                 0.5719771249018739,  0.0497853851400327,
+  //                 0.6627817945481365,  0.2150621318612425,
+  //                 -0.8506676370622683, -0.4531982633526939,
+  //                 0.5943189287417812, -0.5034380636605356
+  VLOAD_64(v2, 0x3fec543182780b14, 0xbfc33a041b62e250, 0xbfe8f9623feb8e20,
+           0xbfd5b8e1d359c984, 0x3feaef91475b6422, 0xbfbf20b464e8e5d0,
+           0x3fee377960758bfa, 0xbfd98f8e02b6aa78, 0x3fe24da2f8b06fde,
+           0x3fa97d7851fd8b80, 0x3fe535822a7efd70, 0x3fcb8727eb79dda0,
+           0xbfeb38ab561e5658, 0xbfdd013349ed0b50, 0x3fe304a9214adedc,
+           0xbfe01c2a245f7960);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmfge.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_64));
+  VSET(1, e16, m1);
+  VCMP_U16(6, v1, 0x0a2a);
+};
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+  enable_fp();
+
+  TEST_CASE1();
+  TEST_CASE2();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vmfgt.c b/apps/riscv-tests/isa/rv64uv/vmfgt.c
new file mode 100644
index 0000000..83b053b
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vmfgt.c
@@ -0,0 +1,134 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+//         Matteo Perotti <mperotti@iis.ee.ethz.ch>
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+// Simple random test with similar values (vector-scalar)
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //                             -0.2649
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0xb43d);
+  //              -0.0651,  0.5806,  0.2563, -0.4783,  0.7393, -0.2649, -0.4590,
+  //              0.5469, -0.9082,  0.6235, -0.8276, -0.7939, -0.0236, -0.1166,
+  //              0.4026,  0.0022
+  VLOAD_16(v2, 0xac2a, 0x38a5, 0x341a, 0xb7a7, 0x39ea, 0xb43d, 0xb758, 0x3860,
+           0xbb44, 0x38fd, 0xba9f, 0xba5a, 0xa60b, 0xaf76, 0x3671, 0x1896);
+  asm volatile("vmfgt.vf v1, v2, %[A]" ::[A] "f"(dscalar_16));
+  VSET(1, e16, m1);
+  VCMP_U16(1, v1, 0xf297);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                               0.80517912
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0x3f4e2038);
+  //              -0.15601152, -0.92020410, -0.29387674,  0.98594254,
+  //              0.88163614, -0.44641387,  0.88191622,  0.15161350,
+  //              -0.79952192, -0.03668820, -0.38464722, -0.54745716,
+  //              0.09956384,  0.21655059, -0.37557366, -0.79342169
+  VLOAD_32(v2, 0xbe1fc17c, 0x3f4e2038, 0x3f4e2038, 0x3f4e2038, 0x3f4e2038,
+           0x3f4e2038, 0x3f4e2038, 0x3f4e2038, 0x3f4e2038, 0x3f4e2038,
+           0x3f4e2038, 0x3f4e2038, 0x3f4e2038, 0x3f4e2038, 0x3f4e2038,
+           0xbf4b1daf);
+  asm volatile("vmfgt.vf v1, v2, %[A]" ::[A] "f"(dscalar_32));
+  VSET(1, e16, m1);
+  VCMP_U16(2, v1, 0x0000);
+
+  VSET(16, e64, m1);
+  double dscalar_64;
+  //                               -0.3394093097660049
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0xbfd5b8e1d359c984);
+  //                0.8852775142880511, -0.1502080091211320,
+  //                -0.7804423569145378,  0.4585094341291300,
+  //                0.8417440789882031, -0.1215927835809432, 0.9442717441528423,
+  //                -0.3993868853091622,  0.5719771249018739,
+  //                0.0497853851400327,  0.6627817945481365, 0.2150621318612425,
+  //                -0.8506676370622683, -0.4531982633526939,
+  //                0.5943189287417812, -0.5034380636605356
+  VLOAD_64(v2, 0x3fec543182780b14, 0xbfc33a041b62e250, 0xbfe8f9623feb8e20,
+           0xbfd5b8e1d359c984, 0x3feaef91475b6422, 0xbfbf20b464e8e5d0,
+           0x3fee377960758bfa, 0xbfd98f8e02b6aa78, 0x3fe24da2f8b06fde,
+           0x3fa97d7851fd8b80, 0x3fe535822a7efd70, 0x3fcb8727eb79dda0,
+           0xbfeb38ab561e5658, 0xbfdd013349ed0b50, 0x3fe304a9214adedc,
+           0xbfe01c2a245f7960);
+  asm volatile("vmfgt.vf v1, v2, %[A]" ::[A] "f"(dscalar_64));
+  VSET(1, e16, m1);
+  VCMP_U16(3, v1, 0x4f73);
+};
+
+// Simple random test with similar values (vector-scalar) (masked)
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //                             -0.2649
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0xb43d);
+  //               -0.2649,  0.5806, -0.2649, -0.4783, -0.2649, -0.2649,
+  //               -0.2649, -0.2649, -0.2649, -0.2649, -0.2649, -0.2649,
+  //               -0.2649, -0.2649, -0.2649, -0.2649,
+  VLOAD_16(v2, 0xb43d, 0x7653, 0xad3d, 0x033d, 0xb43d, 0xb43d, 0xb43d, 0xb43d,
+           0xb43d, 0xb43d, 0xb43d, 0xb43d, 0xb43d, 0xb43d, 0xb43d, 0xb43d);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmfgt.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_16));
+  VSET(1, e16, m1);
+  VCMP_U16(4, v1, 0x000a);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                               0.80517912
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0x3f4e2038);
+  //                0.80517912,  0.80517912, -0.29387674,  0.98594254,
+  //                0.88163614, -0.44641387,  0.88191622,  0.15161350,
+  //                -0.79952192, -0.03668820, -0.38464722, -0.54745716,
+  //                0.09956384,  0.21655059, -0.37557366, -0.79342169
+  VLOAD_32(v2, 0x3f4e2038, 0x3f4e2038, 0xbe967703, 0x3f7c66bb, 0x3f61b2e8,
+           0xbee4905c, 0x3f61c543, 0x3e1b4092, 0xbf4cad78, 0xbd16465d,
+           0xbec4f07b, 0xbf0c2627, 0x3dcbe820, 0x3e5dbf70, 0xbec04b31,
+           0xbf4b1daf);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmfgt.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_32));
+  VSET(1, e16, m1);
+  VCMP_U16(5, v1, 0x0008);
+
+  VSET(16, e64, m1);
+  double dscalar_64;
+  //                               -0.3394093097660049
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0xbfd5b8e1d359c984);
+  //                 0.8852775142880511, -0.1502080091211320,
+  //                 -0.7804423569145378, -0.3394093097660049,
+  //                 0.8417440789882031, -0.1215927835809432,
+  //                 0.9442717441528423, -0.3993868853091622,
+  //                 0.5719771249018739,  0.0497853851400327,
+  //                 0.6627817945481365,  0.2150621318612425,
+  //                 -0.8506676370622683, -0.4531982633526939,
+  //                 0.5943189287417812, -0.5034380636605356
+  VLOAD_64(v2, 0x3fec543182780b14, 0xbfc33a041b62e250, 0xbfe8f9623feb8e20,
+           0xbfd5b8e1d359c984, 0x3feaef91475b6422, 0xbfbf20b464e8e5d0,
+           0x3fee377960758bfa, 0xbfd98f8e02b6aa78, 0x3fe24da2f8b06fde,
+           0x3fa97d7851fd8b80, 0x3fe535822a7efd70, 0x3fcb8727eb79dda0,
+           0xbfeb38ab561e5658, 0xbfdd013349ed0b50, 0x3fe304a9214adedc,
+           0xbfe01c2a245f7960);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmfgt.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_64));
+  VSET(1, e16, m1);
+  VCMP_U16(6, v1, 0x0a22);
+};
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+  enable_fp();
+
+  TEST_CASE1();
+  TEST_CASE2();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vmfle.c b/apps/riscv-tests/isa/rv64uv/vmfle.c
new file mode 100644
index 0000000..43b41c7
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vmfle.c
@@ -0,0 +1,273 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+//         Matteo Perotti <mperotti@iis.ee.ethz.ch>
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+// This instruction writes a mask to a register, with a layout of elements as
+// described in section "Mask Register Layout"
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  //               0.2434,  0.7285,  0.7241, -0.2678,  0.0027, -0.7114,  0.2622,
+  //               0.8701, -0.5786, -0.4229,  0.5981,  0.6968,  0.7217, -0.2842,
+  //               0.1328,  0.1659
+  VLOAD_16(v2, 0x33ca, 0x39d4, 0x39cb, 0xb449, 0x1975, 0xb9b1, 0x3432, 0x3af6,
+           0xb8a1, 0xb6c4, 0x38c9, 0x3993, 0x39c6, 0xb48c, 0x3040, 0x314f);
+  //               0.7319,  0.0590,  0.7593, -0.6606, -0.4758,  0.8530,  0.0453,
+  //               0.0987,  0.1777,  0.3047,  0.2330, -0.3467, -0.4153,  0.7080,
+  //               0.3142, -0.9492
+  VLOAD_16(v3, 0x39db, 0x2b8c, 0x3a13, 0xb949, 0xb79d, 0x3ad3, 0x29cc, 0x2e51,
+           0x31b0, 0x34e0, 0x3375, 0xb58c, 0xb6a5, 0x39aa, 0x3041, 0xbb98);
+  asm volatile("vmfle.vv v1, v2, v3");
+  VSET(1, e16, m1);
+  VCMP_U16(1, v1, 0x6325);
+
+  VSET(16, e32, m1);
+  //                       +0,        sNaN, -0.34645590, -0.06222415,
+  //                       0.96037650, -0.81018746, -0.69337404,  0.70466602,
+  //                       -0.30920035, -0.31596854, -0.92116749,  0.51336122,
+  //                       0.22002794,  0.48599416,  0.69166088,  0.85755372
+  VLOAD_32(v2, 0x00000000, 0xffffffff, 0xbeb162ab, 0xbd7edebf, 0x3f75db3c,
+           0xbf4f6872, 0xbf3180f6, 0x3f3464fe, 0xbe9e4f82, 0xbea1c6a1,
+           0xbf6bd1a2, 0x3f036ba4, 0x3e614f01, 0x3ef8d43a, 0x3f3110b0,
+           0x3f5b88a4);
+  //                       -0,        sNaN,  0.39402914, -0.81853813,
+  //                       0.24656086, -0.71423489, -0.44735566, -0.25510681,
+  //                       -0.94378990, -0.30138883,  0.19188073, -0.29310879,
+  //                       -0.22981364, -0.58626360, -0.80913633, -0.00670803
+  VLOAD_32(v3, 0x80000000, 0xffffffff, 0x3ec9be30, 0xbf518bb7, 0x3e7c7a73,
+           0xbf36d819, 0xbee50bcd, 0xbe829d5c, 0xbf719c37, 0xbe9a4fa3,
+           0x3e447c62, 0xbe96125b, 0xbe6b5444, 0xbf16155f, 0xbf4f238f,
+           0xbbdbcefe);
+  asm volatile("vmfle.vv v1, v2, v3");
+  VSET(1, e16, m1);
+  VCMP_U16(2, v1, 0x0665);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x3feba8d9296c7e74, 0x3fdefda0947f3460, 0x3fed8915c5665532,
+           0xbfee55c27d3d743e, 0xbfc0c0dbc6990b38, 0xbfd84eacd38c6ca4,
+           0x3fc41b3c98507fe0, 0xbfe8877fabcbce12, 0xbfd7e9bb5b0beaf8,
+           0x3fdfa988fd8b0a24, 0xbfd367cf3ee9af68, 0x3feccb416af162fc,
+           0x3fe41bcdc20ecd40, 0x3fbafaebeb19acf0, 0xbfd2cb447b63f610,
+           0x3fdbb633afa4e520);
+  //              -0.3562510538138417, -0.0135629748736219,  0.6176167733891369,
+  //              0.9703747829163081, -0.0909539316920625, -0.1057326828885887,
+  //              -0.8792039527057112, -0.1745056251010144,  0.3110320594479206,
+  //              0.3238986651420683, -0.9079294226891812, -0.9490909352855985,
+  //              0.6962970677624296,  0.7585780695949504, -0.5927175227484118,
+  //              -0.7793965434104730
+  VLOAD_64(v3, 0xbfd6ccd13852f170, 0xbf8bc6e7ac263f80, 0x3fed8915c5665532,
+           0x3fef0d4f6aafa2f6, 0xbfb748c1c20f5de0, 0xbfbb114c0f1ff4b0,
+           0xbfec227053ec5198, 0xbfc6563348637140, 0x3fd3e7f302d586b4,
+           0x3fd4bac177803510, 0xbfed0dc20130d694, 0xbfee5ef3f3ff6a12,
+           0x3fe64810c9cae3fe, 0x3fe84645840bf0a2, 0xbfe2f78abcff0ede,
+           0xbfe8f0d105120796);
+  asm volatile("vmfle.vv v1, v2, v3");
+  VSET(1, e16, m1);
+  VCMP_U16(3, v1, 0x31bc);
+};
+
+// Simple random test with similar values + 1 subnormal (masked)
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  //               0.2434,  0.7285,  0.7241, -0.2678,  0.0027, -0.7114,  0.2622,
+  //               0.8701, -0.5786, -0.4229,  0.5981,  0.6968,  0.7217, -0.2842,
+  //               0.1328,  0.1659
+  VLOAD_16(v2, 0x33ca, 0x39d4, 0x39cb, 0xb449, 0x1975, 0xb9b1, 0x3432, 0x3af6,
+           0xb8a1, 0xb6c4, 0x38c9, 0x3993, 0x39c6, 0xb48c, 0x3040, 0x314f);
+  //               0.7319,  0.7285,  0.7593, -0.6606, -0.4758,  0.8530,  0.0453,
+  //               0.0987,  0.1777,  0.3047,  0.2330, -0.3467, -0.4153,  0.7080,
+  //               0.3142, -0.9492
+  VLOAD_16(v3, 0x39db, 0x39d4, 0x3a13, 0xb949, 0xb79d, 0x3ad3, 0x29cc, 0x2e51,
+           0x31b0, 0x34e0, 0x3375, 0xb58c, 0xb6a5, 0x39aa, 0x3507, 0xbb98);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmfle.vv v1, v2, v3, v0.t");
+  VSET(1, e16, m1);
+  VCMP_U16(4, v1, 0x2222);
+
+  VSET(16, e32, m1);
+  //               0x00000000,  0.09933749, -0.34645590, -0.06222415,
+  //               0.96037650, -0.81018746, -0.69337404,  0.70466602,
+  //               -0.30920035, -0.31596854, -0.92116749,  0.51336122,
+  //               0.22002794,  0.48599416,  0.69166088,  0.85755372
+  VLOAD_32(v2, 0x00000000, 0x3dcb7174, 0xbeb162ab, 0xbd7edebf, 0x3f75db3c,
+           0xbf4f6872, 0xbf3180f6, 0x3f3464fe, 0xbe9e4f82, 0xbea1c6a1,
+           0xbf6bd1a2, 0x3f036ba4, 0x3e614f01, 0x3ef8d43a, 0x3f3110b0,
+           0x3f5d88a4);
+  //               0x00000000, -0.64782482,  0.39402914, -0.81853813,
+  //               0.24656086, -0.71423489, -0.44735566, -0.25510681,
+  //               -0.94378990, -0.30138883,  0.19188073, -0.29310879,
+  //               -0.22981364, -0.58626360, -0.80913633,  0.85755372
+  VLOAD_32(v3, 0x00000000, 0xbf25d7d9, 0x3ec9be30, 0xbf518bb7, 0x3e7c7a73,
+           0xbf36d819, 0xbee50bcd, 0xbe829d5c, 0xbf719c37, 0xbe9a4fa3,
+           0x3e447c62, 0xbe96125b, 0xbe6b5444, 0xbf16155f, 0xbf4f238f,
+           0x3f5d88a4);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmfle.vv v1, v2, v3, v0.t");
+  VSET(1, e16, m1);
+  VCMP_U16(5, v1, 0x8220);
+
+  VSET(16, e64, m1);
+  //               0.8643613633211786,  0.4842301798024149,  0.9229840140784857,
+  //               -0.9479687162489723, -0.1308855743137316,
+  //               -0.3798019472030296,  0.1570811980936915,
+  //               -0.7665403705017886, -0.3736408604742532, 0.4947226024634424,
+  //               -0.3032110323317654,  0.8998114670494881, 0.6283940115157876,
+  //               0.1053912590957002, -0.2936564640984622, -0.7793965434104730
+  VLOAD_64(v2, 0x3feba8d9296c7e74, 0x3fdefda0947f3460, 0x3fed8915c5665532,
+           0xbfee55c27d3d743e, 0xbfc0c0dbc6990b38, 0xbfd84eacd38c6ca4,
+           0x3fc41b3c98507fe0, 0xbfe8877fabcbce12, 0xbfd7e9bb5b0beaf8,
+           0x3fdfa988fd8b0a24, 0xbfd367cf3ee9af68, 0x3feccb416af162fc,
+           0x3fe41bcdc20ecd40, 0x3fbafaebeb19acf0, 0xbfd2cb447b63f610,
+           0xbfe8f0d105120796);
+  //               0.8643613633211786,  0.4842301798024149,  0.6176167733891369,
+  //               0.9703747829163081, -0.0909539316920625, -0.1057326828885887,
+  //               -0.8792039527057112, -0.1745056251010144, 0.3110320594479206,
+  //               0.3238986651420683, -0.9079294226891812, -0.9490909352855985,
+  //               0.6962970677624296,  0.7585780695949504, -0.5927175227484118,
+  //               -0.7793965434104730
+  VLOAD_64(v3, 0x3feba8d9296c7e74, 0x3fdefda0947f3460, 0x3fed8915c5665532,
+           0xbfee55c27d3d743e, 0xbfb748c1c20f5de0, 0xbfbb114c0f1ff4b0,
+           0xbfec227053ec5198, 0xbfc6563348637140, 0x3fd3e7f302d586b4,
+           0x3fd4bac177803510, 0xbfed0dc20130d694, 0xbfee5ef3f3ff6a12,
+           0x3fe64810c9cae3fe, 0x3fe84645840bf0a2, 0xbfe2f78abcff0ede,
+           0xbfe8f0d105120796);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmfle.vv v1, v2, v3, v0.t");
+  VSET(1, e16, m1);
+  VCMP_U16(6, v1, 0xa0aa);
+};
+
+// Simple random test with similar values (vector-scalar)
+void TEST_CASE3(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //                             -0.2649
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0xb43d);
+  //              -0.0651,  0.5806,  0.2563, -0.4783,  0.7393, -0.2649, -0.4590,
+  //              0.5469, -0.9082,  0.6235, -0.8276, -0.7939, -0.0236, -0.1166,
+  //              0.4026,  0.0022
+  VLOAD_16(v2, 0xac2a, 0x38a5, 0x341a, 0xb7a7, 0x39ea, 0xb43d, 0xb758, 0x3860,
+           0xbb44, 0x38fd, 0xba9f, 0xba5a, 0xa60b, 0xaf76, 0x3671, 0x1896);
+  asm volatile("vmfle.vf v1, v2, %[A]" ::[A] "f"(dscalar_16));
+  VSET(1, e16, m1);
+  VCMP_U16(7, v1, 0x0d68);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                               0.80517912
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0x3f4e2038);
+  //              -0.15601152, -0.92020410, -0.29387674,  0.98594254,
+  //              0.88163614, -0.44641387,  0.88191622,  0.15161350,
+  //              -0.79952192, -0.03668820, -0.38464722, -0.54745716,
+  //              0.09956384,  0.21655059, -0.37557366, -0.79342169
+  VLOAD_32(v2, 0xbe1fc17c, 0x3f4e2038, 0x3f4e2038, 0x3f4e2038, 0x3f4e2038,
+           0x3f4e2038, 0x3f4e2038, 0x3f4e2038, 0x3f4e2038, 0x3f4e2038,
+           0x3f4e2038, 0x3f4e2038, 0x3f4e2038, 0x3f4e2038, 0x3f4e2038,
+           0xbf4b1daf);
+  asm volatile("vmfle.vf v1, v2, %[A]" ::[A] "f"(dscalar_32));
+  VSET(1, e16, m1);
+  VCMP_U16(8, v1, 0xffff);
+
+  VSET(16, e64, m1);
+  double dscalar_64;
+  //                               -0.3394093097660049
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0xbfd5b8e1d359c984);
+  //                0.8852775142880511, -0.1502080091211320,
+  //                -0.7804423569145378,  0.4585094341291300,
+  //                0.8417440789882031, -0.1215927835809432, 0.9442717441528423,
+  //                -0.3993868853091622,  0.5719771249018739,
+  //                0.0497853851400327,  0.6627817945481365, 0.2150621318612425,
+  //                -0.8506676370622683, -0.4531982633526939,
+  //                0.5943189287417812, -0.5034380636605356
+  VLOAD_64(v2, 0x3fec543182780b14, 0xbfc33a041b62e250, 0xbfe8f9623feb8e20,
+           0xbfd5b8e1d359c984, 0x3feaef91475b6422, 0xbfbf20b464e8e5d0,
+           0x3fee377960758bfa, 0xbfd98f8e02b6aa78, 0x3fe24da2f8b06fde,
+           0x3fa97d7851fd8b80, 0x3fe535822a7efd70, 0x3fcb8727eb79dda0,
+           0xbfeb38ab561e5658, 0xbfdd013349ed0b50, 0x3fe304a9214adedc,
+           0xbfe01c2a245f7960);
+  asm volatile("vmfle.vf v1, v2, %[A]" ::[A] "f"(dscalar_64));
+  VSET(1, e16, m1);
+  VCMP_U16(9, v1, 0xb08c);
+};
+
+// Simple random test with similar values (vector-scalar) (masked)
+void TEST_CASE4(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //                             -0.2649
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0xb43d);
+  //               -0.2649,  0.5806, -0.2649, -0.4783, -0.2649, -0.2649,
+  //               -0.2649, -0.2649, -0.2649, -0.2649, -0.2649, -0.2649,
+  //               -0.2649, -0.2649, -0.2649, -0.2649,
+  VLOAD_16(v2, 0xb43d, 0x7653, 0xad3d, 0x033d, 0xb43d, 0xb43d, 0xb43d, 0xb43d,
+           0xb43d, 0xb43d, 0xb43d, 0xb43d, 0xb43d, 0xb43d, 0xb43d, 0xb43d);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmfle.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_16));
+  VSET(1, e16, m1);
+  VCMP_U16(10, v1, 0xaaa0);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                               0.80517912
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0x3f4e2038);
+  //                0.80517912,  0.80517912, -0.29387674,  0.98594254,
+  //                0.88163614, -0.44641387,  0.88191622,  0.15161350,
+  //                -0.79952192, -0.03668820, -0.38464722, -0.54745716,
+  //                0.09956384,  0.21655059, -0.37557366, -0.79342169
+  VLOAD_32(v2, 0x3f4e2038, 0x3f4e2038, 0xbe967703, 0x3f7c66bb, 0x3f61b2e8,
+           0xbee4905c, 0x3f61c543, 0x3e1b4092, 0xbf4cad78, 0xbd16465d,
+           0xbec4f07b, 0xbf0c2627, 0x3dcbe820, 0x3e5dbf70, 0xbec04b31,
+           0xbf4b1daf);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmfle.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_32));
+  VSET(1, e16, m1);
+  VCMP_U16(11, v1, 0xaaa2);
+
+  VSET(16, e64, m1);
+  double dscalar_64;
+  //                               -0.3394093097660049
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0xbfd5b8e1d359c984);
+  //                 0.8852775142880511, -0.1502080091211320,
+  //                 -0.7804423569145378, -0.3394093097660049,
+  //                 0.8417440789882031, -0.1215927835809432,
+  //                 0.9442717441528423, -0.3993868853091622,
+  //                 0.5719771249018739,  0.0497853851400327,
+  //                 0.6627817945481365,  0.2150621318612425,
+  //                 -0.8506676370622683, -0.4531982633526939,
+  //                 0.5943189287417812, -0.5034380636605356
+  VLOAD_64(v2, 0x3fec543182780b14, 0xbfc33a041b62e250, 0xbfe8f9623feb8e20,
+           0xbfd5b8e1d359c984, 0x3feaef91475b6422, 0xbfbf20b464e8e5d0,
+           0x3fee377960758bfa, 0xbfd98f8e02b6aa78, 0x3fe24da2f8b06fde,
+           0x3fa97d7851fd8b80, 0x3fe535822a7efd70, 0x3fcb8727eb79dda0,
+           0xbfeb38ab561e5658, 0xbfdd013349ed0b50, 0x3fe304a9214adedc,
+           0xbfe01c2a245f7960);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmfle.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_64));
+  VSET(1, e16, m1);
+  VCMP_U16(12, v1, 0xa088);
+};
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+  enable_fp();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vmflt.c b/apps/riscv-tests/isa/rv64uv/vmflt.c
new file mode 100644
index 0000000..912863d
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vmflt.c
@@ -0,0 +1,279 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+//         Matteo Perotti <mperotti@iis.ee.ethz.ch>
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+// This instruction writes a mask to a register, with a layout of elements as
+// described in section "Mask Register Layout"
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  //               0.2434,  0.7285,  0.7241, -0.2678,  0.0027, -0.7114,  0.2622,
+  //               0.8701, -0.5786, -0.4229,  0.5981,  0.6968,  0.7217, -0.2842,
+  //               0.1328,  0.1659
+  VLOAD_16(v2, 0x33ca, 0x39d4, 0x39cb, 0xb449, 0x1975, 0xb9b1, 0x3432, 0x3af6,
+           0xb8a1, 0xb6c4, 0x38c9, 0x3993, 0x39c6, 0xb48c, 0x3040, 0x314f);
+  //               0.7319,  0.0590,  0.7593, -0.6606, -0.4758,  0.8530,  0.0453,
+  //               0.0987,  0.1777,  0.3047,  0.2330, -0.3467, -0.4153,  0.7080,
+  //               0.3142, -0.9492
+  VLOAD_16(v3, 0x39db, 0x2b8c, 0x3a13, 0xb949, 0xb79d, 0x3ad3, 0x29cc, 0x2e51,
+           0x31b0, 0x34e0, 0x3375, 0xb58c, 0xb6a5, 0x39aa, 0x3041, 0xbb98);
+  asm volatile("vmflt.vv v1, v2, v3");
+  VSET(1, e16, m1);
+  VCMP_U16(1, v1, 0x6325);
+
+  VSET(16, e32, m1);
+  //                       +0,        sNaN, -0.34645590, -0.06222415,
+  //                       0.96037650, -0.81018746, -0.69337404,  0.70466602,
+  //                       -0.30920035, -0.31596854, -0.92116749,  0.51336122,
+  //                       0.22002794,  0.48599416,  0.69166088,  0.85755372
+  VLOAD_32(v2, 0x00000000, 0xffffffff, 0xbeb162ab, 0xbd7edebf, 0x3f75db3c,
+           0xbf4f6872, 0xbf3180f6, 0x3f3464fe, 0xbe9e4f82, 0xbea1c6a1,
+           0xbf6bd1a2, 0x3f036ba4, 0x3e614f01, 0x3ef8d43a, 0x3f3110b0,
+           0x3f5b88a4);
+  //                       -0,        sNaN,  0.39402914, -0.81853813,
+  //                       0.24656086, -0.71423489, -0.44735566, -0.25510681,
+  //                       -0.94378990, -0.30138883,  0.19188073, -0.29310879,
+  //                       -0.22981364, -0.58626360, -0.80913633, -0.00670803
+  VLOAD_32(v3, 0x80000000, 0xffffffff, 0x3ec9be30, 0xbf518bb7, 0x3e7c7a73,
+           0xbf36d819, 0xbee50bcd, 0xbe829d5c, 0xbf719c37, 0xbe9a4fa3,
+           0x3e447c62, 0xbe96125b, 0xbe6b5444, 0xbf16155f, 0xbf4f238f,
+           0xbbdbcefe);
+  asm volatile("vmflt.vv v1, v2, v3");
+  VSET(1, e16, m1);
+  VCMP_U16(2, v1, 0x0664);
+
+  VSET(16, e64, m1);
+  //               0.8643613633211786,  0.4842301798024149,  0.9229840140784857,
+  //               -0.9479687162489723, -0.1308855743137316,
+  //               -0.3798019472030296,  0.1570811980936915,
+  //               -0.7665403705017886, -0.3736408604742532, 0.4947226024634424,
+  //               -0.3032110323317654,  0.8998114670494881, 0.6283940115157876,
+  //               0.1053912590957002, -0.2936564640984622,  0.4329957213663693
+  VLOAD_64(v2, 0x3feba8d9296c7e74, 0x3fdefda0947f3460, 0x3fed8915c5665532,
+           0xbfee55c27d3d743e, 0xbfc0c0dbc6990b38, 0xbfd84eacd38c6ca4,
+           0x3fc41b3c98507fe0, 0xbfe8877fabcbce12, 0xbfd7e9bb5b0beaf8,
+           0x3fdfa988fd8b0a24, 0xbfd367cf3ee9af68, 0x3feccb416af162fc,
+           0x3fe41bcdc20ecd40, 0x3fbafaebeb19acf0, 0xbfd2cb447b63f610,
+           0x3fdbb633afa4e520);
+  //              -0.3562510538138417, -0.0135629748736219,  0.6176167733891369,
+  //              0.9703747829163081, -0.0909539316920625, -0.1057326828885887,
+  //              -0.8792039527057112, -0.1745056251010144,  0.3110320594479206,
+  //              0.3238986651420683, -0.9079294226891812, -0.9490909352855985,
+  //              0.6962970677624296,  0.7585780695949504, -0.5927175227484118,
+  //              -0.7793965434104730
+  VLOAD_64(v3, 0xbfd6ccd13852f170, 0xbf8bc6e7ac263f80, 0x3fed8915c5665532,
+           0x3fef0d4f6aafa2f6, 0xbfb748c1c20f5de0, 0xbfbb114c0f1ff4b0,
+           0xbfec227053ec5198, 0xbfc6563348637140, 0x3fd3e7f302d586b4,
+           0x3fd4bac177803510, 0xbfed0dc20130d694, 0xbfee5ef3f3ff6a12,
+           0x3fe64810c9cae3fe, 0x3fe84645840bf0a2, 0xbfe2f78abcff0ede,
+           0xbfe8f0d105120796);
+  asm volatile("vmflt.vv v1, v2, v3");
+  VSET(1, e16, m1);
+  VCMP_U16(3, v1, 0x31b8);
+};
+
+// Simple random test with similar values + 1 subnormal (masked)
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  //               0.2434,  0.7285,  0.7241, -0.2678,  0.0027, -0.7114,  0.2622,
+  //               0.8701, -0.5786, -0.4229,  0.5981,  0.6968,  0.7217, -0.2842,
+  //               0.1328,  0.1659
+  VLOAD_16(v2, 0x33ca, 0x39d4, 0x39cb, 0xb449, 0x1975, 0xb9b1, 0x3432, 0x3af6,
+           0xb8a1, 0xb6c4, 0x38c9, 0x3993, 0x39c6, 0xb48c, 0x3040, 0x314f);
+  //               0.7319,  0.7285,  0.7593, -0.6606, -0.4758,  0.8530,  0.0453,
+  //               0.0987,  0.1777,  0.3047,  0.2330, -0.3467, -0.4153,  0.7080,
+  //               0.3142, -0.9492
+  VLOAD_16(v3, 0x39db, 0x39d4, 0x3a13, 0xb949, 0xb79d, 0x3ad3, 0x29cc, 0x2e51,
+           0x31b0, 0x34e0, 0x3375, 0xb58c, 0xb6a5, 0x39aa, 0x3507, 0xbb98);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmflt.vv v1, v2, v3, v0.t");
+  VSET(1, e16, m1);
+  VCMP_U16(4, v1, 0x2220);
+
+  VSET(16, e32, m1);
+  //               0x00000000,  0.09933749, -0.34645590, -0.06222415,
+  //               0.96037650, -0.81018746, -0.69337404,  0.70466602,
+  //               -0.30920035, -0.31596854, -0.92116749,  0.51336122,
+  //               0.22002794,  0.48599416,  0.69166088,  0.85755372
+  VLOAD_32(v2, 0x00000000, 0x3dcb7174, 0xbeb162ab, 0xbd7edebf, 0x3f75db3c,
+           0xbf4f6872, 0xbf3180f6, 0x3f3464fe, 0xbe9e4f82, 0xbea1c6a1,
+           0xbf6bd1a2, 0x3f036ba4, 0x3e614f01, 0x3ef8d43a, 0x3f3110b0,
+           0x3f5d88a4);
+  //               0x00000000, -0.64782482,  0.39402914, -0.81853813,
+  //               0.24656086, -0.71423489, -0.44735566, -0.25510681,
+  //               -0.94378990, -0.30138883,  0.19188073, -0.29310879,
+  //               -0.22981364, -0.58626360, -0.80913633,  0.85755372
+  VLOAD_32(v3, 0x00000000, 0xbf25d7d9, 0x3ec9be30, 0xbf518bb7, 0x3e7c7a73,
+           0xbf36d819, 0xbee50bcd, 0xbe829d5c, 0xbf719c37, 0xbe9a4fa3,
+           0x3e447c62, 0xbe96125b, 0xbe6b5444, 0xbf16155f, 0xbf4f238f,
+           0x3f5d88a4);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmflt.vv v1, v2, v3, v0.t");
+  VSET(1, e16, m1);
+  VCMP_U16(5, v1, 0x0220);
+
+  VSET(16, e64, m1);
+  //               0.8643613633211786,  0.4842301798024149,  0.9229840140784857,
+  //               -0.9479687162489723, -0.1308855743137316,
+  //               -0.3798019472030296,  0.1570811980936915,
+  //               -0.7665403705017886, -0.3736408604742532, 0.4947226024634424,
+  //               -0.3032110323317654,  0.8998114670494881, 0.6283940115157876,
+  //               0.1053912590957002, -0.2936564640984622, -0.7793965434104730
+  VLOAD_64(v2, 0x3feba8d9296c7e74, 0x3fdefda0947f3460, 0x3fed8915c5665532,
+           0xbfee55c27d3d743e, 0xbfc0c0dbc6990b38, 0xbfd84eacd38c6ca4,
+           0x3fc41b3c98507fe0, 0xbfe8877fabcbce12, 0xbfd7e9bb5b0beaf8,
+           0x3fdfa988fd8b0a24, 0xbfd367cf3ee9af68, 0x3feccb416af162fc,
+           0x3fe41bcdc20ecd40, 0x3fbafaebeb19acf0, 0xbfd2cb447b63f610,
+           0xbfe8f0d105120796);
+  //               0.8643613633211786,  0.4842301798024149,  0.6176167733891369,
+  //               0.9703747829163081, -0.0909539316920625, -0.1057326828885887,
+  //               -0.8792039527057112, -0.1745056251010144, 0.3110320594479206,
+  //               0.3238986651420683, -0.9079294226891812, -0.9490909352855985,
+  //               0.6962970677624296,  0.7585780695949504, -0.5927175227484118,
+  //               -0.7793965434104730
+  VLOAD_64(v3, 0x3feba8d9296c7e74, 0x3fdefda0947f3460, 0x3fed8915c5665532,
+           0xbfee55c27d3d743e, 0xbfb748c1c20f5de0, 0xbfbb114c0f1ff4b0,
+           0xbfec227053ec5198, 0xbfc6563348637140, 0x3fd3e7f302d586b4,
+           0x3fd4bac177803510, 0xbfed0dc20130d694, 0xbfee5ef3f3ff6a12,
+           0x3fe64810c9cae3fe, 0x3fe84645840bf0a2, 0xbfe2f78abcff0ede,
+           0xbfe8f0d105120796);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmflt.vv v1, v2, v3, v0.t");
+  VSET(1, e16, m1);
+  VCMP_U16(6, v1, 0x20a0);
+};
+
+// Simple random test with similar values (vector-scalar)
+void TEST_CASE3(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //                             -0.2649
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0xb43d);
+  //              -0.0651,  0.5806,  0.2563, -0.4783,  0.7393, -0.2649, -0.4590,
+  //              0.5469, -0.9082,  0.6235, -0.8276, -0.7939, -0.0236, -0.1166,
+  //              0.4026,  0.0022
+  VLOAD_16(v2, 0xac2a, 0x38a5, 0x341a, 0xb7a7, 0x39ea, 0xb43d, 0xb758, 0x3860,
+           0xbb44, 0x38fd, 0xba9f, 0xba5a, 0xa60b, 0xaf76, 0x3671, 0x1896);
+  asm volatile("vmflt.vf v1, v2, %[A]" ::[A] "f"(dscalar_16));
+  VSET(1, e16, m1);
+  VCMP_U16(7, v1, 0x0d48);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                               0.80517912
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0x3f4e2038);
+  //              -0.15601152, -0.92020410, -0.29387674,  0.98594254,
+  //              0.88163614, -0.44641387,  0.88191622,  0.15161350,
+  //              -0.79952192, -0.03668820, -0.38464722, -0.54745716,
+  //              0.09956384,  0.21655059, -0.37557366, -0.79342169
+  VLOAD_32(v2, 0xbe1fc17c, 0x3f4e2038, 0x3f4e2038, 0x3f4e2038, 0x3f4e2038,
+           0x3f4e2038, 0x3f4e2038, 0x3f4e2038, 0x3f4e2038, 0x3f4e2038,
+           0x3f4e2038, 0x3f4e2038, 0x3f4e2038, 0x3f4e2038, 0x3f4e2038,
+           0xbf4b1daf);
+  asm volatile("vmflt.vf v1, v2, %[A]" ::[A] "f"(dscalar_32));
+  VSET(1, e16, m1);
+  VCMP_U16(8, v1, 0x8001);
+
+  VSET(16, e64, m1);
+  double dscalar_64;
+  //                               -0.3394093097660049
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0xbfd5b8e1d359c984);
+  //                0.8852775142880511, -0.1502080091211320,
+  //                -0.7804423569145378,  0.4585094341291300,
+  //                0.8417440789882031, -0.1215927835809432, 0.9442717441528423,
+  //                -0.3993868853091622,  0.5719771249018739,
+  //                0.0497853851400327,  0.6627817945481365, 0.2150621318612425,
+  //                -0.8506676370622683, -0.4531982633526939,
+  //                0.5943189287417812, -0.5034380636605356
+  VLOAD_64(v2, 0x3fec543182780b14, 0xbfc33a041b62e250, 0xbfe8f9623feb8e20,
+           0xbfd5b8e1d359c984, 0x3feaef91475b6422, 0xbfbf20b464e8e5d0,
+           0x3fee377960758bfa, 0xbfd98f8e02b6aa78, 0x3fe24da2f8b06fde,
+           0x3fa97d7851fd8b80, 0x3fe535822a7efd70, 0x3fcb8727eb79dda0,
+           0xbfeb38ab561e5658, 0xbfdd013349ed0b50, 0x3fe304a9214adedc,
+           0xbfe01c2a245f7960);
+  asm volatile("vmflt.vf v1, v2, %[A]" ::[A] "f"(dscalar_64));
+  VSET(1, e16, m1);
+  VCMP_U16(9, v1, 0xb084);
+};
+
+// Simple random test with similar values (vector-scalar) (masked)
+void TEST_CASE4(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //                             -0.2649
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0xb43d);
+  //               -0.2649,  0.5806, -0.2649, -0.4783, -0.2649, -0.2649,
+  //               -0.2649, -0.2649, -0.2649, -0.2649, -0.2649, -0.2649,
+  //               -0.2649, -0.2649, -0.2649, -0.2649,
+  VLOAD_16(v2, 0xb43d, 0x7653, 0xad3d, 0x033d, 0xb43d, 0xb43d, 0xb43d, 0xb43d,
+           0xb43d, 0xb43d, 0xb43d, 0xb43d, 0xb43d, 0xb43d, 0xb43d, 0xb43d);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmflt.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_16));
+  VSET(1, e16, m1);
+  VCMP_U16(10, v1, 0x0000);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                               0.80517912
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0x3f4e2038);
+  //                0.80517912,  0.80517912, -0.29387674,  0.98594254,
+  //                0.88163614, -0.44641387,  0.88191622,  0.15161350,
+  //                -0.79952192, -0.03668820, -0.38464722, -0.54745716,
+  //                0.09956384,  0.21655059, -0.37557366, -0.79342169
+  VLOAD_32(v2, 0x3f4e2038, 0x3f4e2038, 0xbe967703, 0x3f7c66bb, 0x3f61b2e8,
+           0xbee4905c, 0x3f61c543, 0x3e1b4092, 0xbf4cad78, 0xbd16465d,
+           0xbec4f07b, 0xbf0c2627, 0x3dcbe820, 0x3e5dbf70, 0xbec04b31,
+           0xbf4b1daf);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmflt.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_32));
+  VSET(1, e16, m1);
+  VCMP_U16(11, v1, 0xaaa0);
+
+  VSET(16, e64, m1);
+  double dscalar_64;
+  //                               -0.3394093097660049
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0xbfd5b8e1d359c984);
+  //                 0.8852775142880511, -0.1502080091211320,
+  //                 -0.7804423569145378, -0.3394093097660049,
+  //                 0.8417440789882031, -0.1215927835809432,
+  //                 0.9442717441528423, -0.3993868853091622,
+  //                 0.5719771249018739,  0.0497853851400327,
+  //                 0.6627817945481365,  0.2150621318612425,
+  //                 -0.8506676370622683, -0.4531982633526939,
+  //                 0.5943189287417812, -0.5034380636605356
+  VLOAD_64(v2, 0x3fec543182780b14, 0xbfc33a041b62e250, 0xbfe8f9623feb8e20,
+           0xbfd5b8e1d359c984, 0x3feaef91475b6422, 0xbfbf20b464e8e5d0,
+           0x3fee377960758bfa, 0xbfd98f8e02b6aa78, 0x3fe24da2f8b06fde,
+           0x3fa97d7851fd8b80, 0x3fe535822a7efd70, 0x3fcb8727eb79dda0,
+           0xbfeb38ab561e5658, 0xbfdd013349ed0b50, 0x3fe304a9214adedc,
+           0xbfe01c2a245f7960);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmflt.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_64));
+  VSET(1, e16, m1);
+  VCMP_U16(12, v1, 0xa080);
+};
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+  enable_fp();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vmfne.c b/apps/riscv-tests/isa/rv64uv/vmfne.c
new file mode 100644
index 0000000..bc19a2e
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vmfne.c
@@ -0,0 +1,503 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+//         Matteo Perotti <mperotti@iis.ee.ethz.ch>
+
+#include "float_macros.h"
+#include "vector_macros.h"
+
+// This instruction writes a mask to a register, with a layout of elements as
+// described in section "Mask Register Layout"
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  //               0.2434,  0.7285,  0.7241, -0.2678,  0.0027, -0.7114,  0.2622,
+  //               0.8701, -0.5786, -0.4229,  0.5981,  0.6968,  0.7217, -0.2842,
+  //               0.1328,  0.1659
+  VLOAD_16(v2, 0x33ca, 0x39d4, 0x39cb, 0xb449, 0x1975, 0xb9b1, 0x3432, 0x3af6,
+           0xb8a1, 0xb6c4, 0x38c9, 0x3993, 0x39c6, 0xb48c, 0x3040, 0x314f);
+  //               0.7319,  0.0590,  0.7593, -0.6606, -0.4758,  0.8530,  0.0453,
+  //               0.0987,  0.1777,  0.3047,  0.2330, -0.3467, -0.4153,  0.7080,
+  //               0.3142, -0.9492
+  VLOAD_16(v3, 0x39db, 0x2b8c, 0x3a13, 0xb949, 0xb79d, 0x3ad3, 0x29cc, 0x2e51,
+           0x31b0, 0x34e0, 0x3375, 0xb58c, 0xb6a5, 0x39aa, 0x3041, 0xbb98);
+  asm volatile("vmfne.vv v1, v2, v3");
+  VSET(1, e16, m1);
+  VCMP_U16(1, v1, 0xffff);
+
+  VSET(16, e32, m1);
+  //                       +0,        sNaN, -0.34645590, -0.06222415,
+  //                       0.96037650, -0.81018746, -0.69337404,  0.70466602,
+  //                       -0.30920035, -0.31596854, -0.92116749,  0.51336122,
+  //                       0.22002794,  0.48599416,  0.69166088,  0.85755372
+  VLOAD_32(v2, 0x00000000, 0xffffffff, 0xbeb162ab, 0xbd7edebf, 0x3f75db3c,
+           0xbf4f6872, 0xbf3180f6, 0x3f3464fe, 0xbe9e4f82, 0xbea1c6a1,
+           0xbf6bd1a2, 0x3f036ba4, 0x3e614f01, 0x3ef8d43a, 0x3f3110b0,
+           0x3f5b88a4);
+  //                       -0,        sNaN,  0.39402914, -0.81853813,
+  //                       0.24656086, -0.71423489, -0.44735566, -0.25510681,
+  //                       -0.94378990, -0.30138883,  0.19188073, -0.29310879,
+  //                       -0.22981364, -0.58626360, -0.80913633, -0.00670803
+  VLOAD_32(v3, 0x80000000, 0xffffffff, 0x3ec9be30, 0xbf518bb7, 0x3e7c7a73,
+           0xbf36d819, 0xbee50bcd, 0xbe829d5c, 0xbf719c37, 0xbe9a4fa3,
+           0x3e447c62, 0xbe96125b, 0xbe6b5444, 0xbf16155f, 0xbf4f238f,
+           0xbbdbcefe);
+  asm volatile("vmfne.vv v1, v2, v3");
+  VSET(1, e16, m1);
+  VCMP_U16(2, v1, 0xfffe);
+
+  VSET(16, e64, m1);
+  //               0.8643613633211786,  0.4842301798024149,  0.9229840140784857,
+  //               -0.9479687162489723, -0.1308855743137316,
+  //               -0.3798019472030296,  0.1570811980936915,
+  //               -0.7665403705017886, -0.3736408604742532, 0.4947226024634424,
+  //               -0.3032110323317654,  0.8998114670494881, 0.6283940115157876,
+  //               0.1053912590957002, -0.2936564640984622,  0.4329957213663693
+  VLOAD_64(v2, 0x3feba8d9296c7e74, 0x3fdefda0947f3460, 0x3fed8915c5665532,
+           0xbfee55c27d3d743e, 0xbfc0c0dbc6990b38, 0xbfd84eacd38c6ca4,
+           0x3fc41b3c98507fe0, 0xbfe8877fabcbce12, 0xbfd7e9bb5b0beaf8,
+           0x3fdfa988fd8b0a24, 0xbfd367cf3ee9af68, 0x3feccb416af162fc,
+           0x3fe41bcdc20ecd40, 0x3fbafaebeb19acf0, 0xbfd2cb447b63f610,
+           0x3fdbb633afa4e520);
+  //              -0.3562510538138417, -0.0135629748736219,  0.6176167733891369,
+  //              0.9703747829163081, -0.0909539316920625, -0.1057326828885887,
+  //              -0.8792039527057112, -0.1745056251010144,  0.3110320594479206,
+  //              0.3238986651420683, -0.9079294226891812, -0.9490909352855985,
+  //              0.6962970677624296,  0.7585780695949504, -0.5927175227484118,
+  //              -0.7793965434104730
+  VLOAD_64(v3, 0xbfd6ccd13852f170, 0xbf8bc6e7ac263f80, 0x3fed8915c5665532,
+           0x3fef0d4f6aafa2f6, 0xbfb748c1c20f5de0, 0xbfbb114c0f1ff4b0,
+           0xbfec227053ec5198, 0xbfc6563348637140, 0x3fd3e7f302d586b4,
+           0x3fd4bac177803510, 0xbfed0dc20130d694, 0xbfee5ef3f3ff6a12,
+           0x3fe64810c9cae3fe, 0x3fe84645840bf0a2, 0xbfe2f78abcff0ede,
+           0xbfe8f0d105120796);
+  asm volatile("vmfne.vv v1, v2, v3");
+  VSET(1, e16, m1);
+  VCMP_U16(3, v1, 0xfffb);
+};
+
+// Simple random test with similar values + 1 subnormal (masked)
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  //               0.2434,  0.7285,  0.7241, -0.2678,  0.0027, -0.7114,  0.2622,
+  //               0.8701, -0.5786, -0.4229,  0.5981,  0.6968,  0.7217, -0.2842,
+  //               0.1328,  0.1659
+  VLOAD_16(v2, 0x33ca, 0x39d4, 0x39cb, 0xb449, 0x1975, 0xb9b1, 0x3432, 0x3af6,
+           0xb8a1, 0xb6c4, 0x38c9, 0x3993, 0x39c6, 0xb48c, 0x3040, 0x314f);
+  //               0.7319,  0.7285,  0.7593, -0.6606, -0.4758,  0.8530,  0.0453,
+  //               0.0987,  0.1777,  0.3047,  0.2330, -0.3467, -0.4153,  0.7080,
+  //               0.3142, -0.9492
+  VLOAD_16(v3, 0x39db, 0x39d4, 0x3a13, 0xb949, 0xb79d, 0x3ad3, 0x29cc, 0x2e51,
+           0x31b0, 0x34e0, 0x3375, 0xb58c, 0xb6a5, 0x39aa, 0x3507, 0xbb98);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmfne.vv v1, v2, v3, v0.t");
+  VSET(1, e16, m1);
+  VCMP_U16(4, v1, 0xaaa8);
+
+  VSET(16, e32, m1);
+  //               0x00000000,  0.09933749, -0.34645590, -0.06222415,
+  //               0.96037650, -0.81018746, -0.69337404,  0.70466602,
+  //               -0.30920035, -0.31596854, -0.92116749,  0.51336122,
+  //               0.22002794,  0.48599416,  0.69166088,  0.85755372
+  VLOAD_32(v2, 0x00000000, 0x3dcb7174, 0xbeb162ab, 0xbd7edebf, 0x3f75db3c,
+           0xbf4f6872, 0xbf3180f6, 0x3f3464fe, 0xbe9e4f82, 0xbea1c6a1,
+           0xbf6bd1a2, 0x3f036ba4, 0x3e614f01, 0x3ef8d43a, 0x3f3110b0,
+           0x3f5d88a4);
+  //               0x00000000, -0.64782482,  0.39402914, -0.81853813,
+  //               0.24656086, -0.71423489, -0.44735566, -0.25510681,
+  //               -0.94378990, -0.30138883,  0.19188073, -0.29310879,
+  //               -0.22981364, -0.58626360, -0.80913633,  0.85755372
+  VLOAD_32(v3, 0x00000000, 0xbf25d7d9, 0x3ec9be30, 0xbf518bb7, 0x3e7c7a73,
+           0xbf36d819, 0xbee50bcd, 0xbe829d5c, 0xbf719c37, 0xbe9a4fa3,
+           0x3e447c62, 0xbe96125b, 0xbe6b5444, 0xbf16155f, 0xbf4f238f,
+           0x3f5d88a4);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmfne.vv v1, v2, v3, v0.t");
+  VSET(1, e16, m1);
+  VCMP_U16(5, v1, 0x2aaa);
+
+  VSET(16, e64, m1);
+  //               0.8643613633211786,  0.4842301798024149,  0.9229840140784857,
+  //               -0.9479687162489723, -0.1308855743137316,
+  //               -0.3798019472030296,  0.1570811980936915,
+  //               -0.7665403705017886, -0.3736408604742532, 0.4947226024634424,
+  //               -0.3032110323317654,  0.8998114670494881, 0.6283940115157876,
+  //               0.1053912590957002, -0.2936564640984622, -0.7793965434104730
+  VLOAD_64(v2, 0x3feba8d9296c7e74, 0x3fdefda0947f3460, 0x3fed8915c5665532,
+           0xbfee55c27d3d743e, 0xbfc0c0dbc6990b38, 0xbfd84eacd38c6ca4,
+           0x3fc41b3c98507fe0, 0xbfe8877fabcbce12, 0xbfd7e9bb5b0beaf8,
+           0x3fdfa988fd8b0a24, 0xbfd367cf3ee9af68, 0x3feccb416af162fc,
+           0x3fe41bcdc20ecd40, 0x3fbafaebeb19acf0, 0xbfd2cb447b63f610,
+           0xbfe8f0d105120796);
+  //               0.8643613633211786,  0.4842301798024149,  0.6176167733891369,
+  //               0.9703747829163081, -0.0909539316920625, -0.1057326828885887,
+  //               -0.8792039527057112, -0.1745056251010144, 0.3110320594479206,
+  //               0.3238986651420683, -0.9079294226891812, -0.9490909352855985,
+  //               0.6962970677624296,  0.7585780695949504, -0.5927175227484118,
+  //               -0.7793965434104730
+  VLOAD_64(v3, 0x3feba8d9296c7e74, 0x3fdefda0947f3460, 0x3fed8915c5665532,
+           0xbfee55c27d3d743e, 0xbfb748c1c20f5de0, 0xbfbb114c0f1ff4b0,
+           0xbfec227053ec5198, 0xbfc6563348637140, 0x3fd3e7f302d586b4,
+           0x3fd4bac177803510, 0xbfed0dc20130d694, 0xbfee5ef3f3ff6a12,
+           0x3fe64810c9cae3fe, 0x3fe84645840bf0a2, 0xbfe2f78abcff0ede,
+           0xbfe8f0d105120796);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmfne.vv v1, v2, v3, v0.t");
+  VSET(1, e16, m1);
+  VCMP_U16(6, v1, 0x2aa0);
+};
+
+// Simple random test with similar values (vector-scalar)
+void TEST_CASE3(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //                             -0.2649
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0xb43d);
+  //              -0.0651,  0.5806,  0.2563, -0.4783,  0.7393, -0.2649, -0.4590,
+  //              0.5469, -0.9082,  0.6235, -0.8276, -0.7939, -0.0236, -0.1166,
+  //              0.4026,  0.0022
+  VLOAD_16(v2, 0xac2a, 0x38a5, 0x341a, 0xb7a7, 0x39ea, 0xb43d, 0xb758, 0x3860,
+           0xbb44, 0x38fd, 0xba9f, 0xba5a, 0xa60b, 0xaf76, 0x3671, 0x1896);
+  asm volatile("vmfne.vf v1, v2, %[A]" ::[A] "f"(dscalar_16));
+  VSET(1, e16, m1);
+  VCMP_U16(7, v1, 0xffdf);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                               0.80517912
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0x3f4e2038);
+  //              -0.15601152, -0.92020410, -0.29387674,  0.98594254,
+  //              0.88163614, -0.44641387,  0.88191622,  0.15161350,
+  //              -0.79952192, -0.03668820, -0.38464722, -0.54745716,
+  //              0.09956384,  0.21655059, -0.37557366, -0.79342169
+  VLOAD_32(v2, 0xbe1fc17c, 0x3f4e2038, 0x3f4e2038, 0x3f4e2038, 0x3f4e2038,
+           0x3f4e2038, 0x3f4e2038, 0x3f4e2038, 0x3f4e2038, 0x3f4e2038,
+           0x3f4e2038, 0x3f4e2038, 0x3f4e2038, 0x3f4e2038, 0x3f4e2038,
+           0xbf4b1daf);
+  asm volatile("vmfne.vf v1, v2, %[A]" ::[A] "f"(dscalar_32));
+  VSET(1, e16, m1);
+  VCMP_U16(8, v1, 0x8001);
+
+  VSET(16, e64, m1);
+  double dscalar_64;
+  //                               -0.3394093097660049
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0xbfd5b8e1d359c984);
+  //                0.8852775142880511, -0.1502080091211320,
+  //                -0.7804423569145378,  0.4585094341291300,
+  //                0.8417440789882031, -0.1215927835809432, 0.9442717441528423,
+  //                -0.3993868853091622,  0.5719771249018739,
+  //                0.0497853851400327,  0.6627817945481365, 0.2150621318612425,
+  //                -0.8506676370622683, -0.4531982633526939,
+  //                0.5943189287417812, -0.5034380636605356
+  VLOAD_64(v2, 0x3fec543182780b14, 0xbfc33a041b62e250, 0xbfe8f9623feb8e20,
+           0xbfd5b8e1d359c984, 0x3feaef91475b6422, 0xbfbf20b464e8e5d0,
+           0x3fee377960758bfa, 0xbfd98f8e02b6aa78, 0x3fe24da2f8b06fde,
+           0x3fa97d7851fd8b80, 0x3fe535822a7efd70, 0x3fcb8727eb79dda0,
+           0xbfeb38ab561e5658, 0xbfdd013349ed0b50, 0x3fe304a9214adedc,
+           0xbfe01c2a245f7960);
+  asm volatile("vmfne.vf v1, v2, %[A]" ::[A] "f"(dscalar_64));
+  VSET(1, e16, m1);
+  VCMP_U16(9, v1, 0xfff7);
+};
+
+// Simple random test with similar values (vector-scalar) (masked)
+void TEST_CASE4(void) {
+  VSET(16, e16, m1);
+  double dscalar_16;
+  //                             -0.2649
+  BOX_HALF_IN_DOUBLE(dscalar_16, 0xb43d);
+  //               -0.2649,  0.5806, -0.2649, -0.4783, -0.2649, -0.2649,
+  //               -0.2649, -0.2649, -0.2649, -0.2649, -0.2649, -0.2649,
+  //               -0.2649, -0.2649, -0.2649, -0.2649,
+  VLOAD_16(v2, 0xb43d, 0x7653, 0xad3d, 0x033d, 0xb43d, 0xb43d, 0xb43d, 0xb43d,
+           0xb43d, 0xb43d, 0xb43d, 0xb43d, 0xb43d, 0xb43d, 0xb43d, 0xb43d);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmfne.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_16));
+  VSET(1, e16, m1);
+  VCMP_U16(10, v1, 0x000a);
+
+  VSET(16, e32, m1);
+  double dscalar_32;
+  //                               0.80517912
+  BOX_FLOAT_IN_DOUBLE(dscalar_32, 0x3f4e2038);
+  //                0.80517912,  0.80517912, -0.29387674,  0.98594254,
+  //                0.88163614, -0.44641387,  0.88191622,  0.15161350,
+  //                -0.79952192, -0.03668820, -0.38464722, -0.54745716,
+  //                0.09956384,  0.21655059, -0.37557366, -0.79342169
+  VLOAD_32(v2, 0x3f4e2038, 0x3f4e2038, 0xbe967703, 0x3f7c66bb, 0x3f61b2e8,
+           0xbee4905c, 0x3f61c543, 0x3e1b4092, 0xbf4cad78, 0xbd16465d,
+           0xbec4f07b, 0xbf0c2627, 0x3dcbe820, 0x3e5dbf70, 0xbec04b31,
+           0xbf4b1daf);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmfne.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_32));
+  VSET(1, e16, m1);
+  VCMP_U16(11, v1, 0xaaa8);
+
+  VSET(16, e64, m1);
+  double dscalar_64;
+  //                               -0.3394093097660049
+  BOX_DOUBLE_IN_DOUBLE(dscalar_64, 0xbfd5b8e1d359c984);
+  //                 0.8852775142880511, -0.1502080091211320,
+  //                 -0.7804423569145378, -0.3394093097660049,
+  //                 0.8417440789882031, -0.1215927835809432,
+  //                 0.9442717441528423, -0.3993868853091622,
+  //                 0.5719771249018739,  0.0497853851400327,
+  //                 0.6627817945481365,  0.2150621318612425,
+  //                 -0.8506676370622683, -0.4531982633526939,
+  //                 0.5943189287417812, -0.5034380636605356
+  VLOAD_64(v2, 0x3fec543182780b14, 0xbfc33a041b62e250, 0xbfe8f9623feb8e20,
+           0xbfd5b8e1d359c984, 0x3feaef91475b6422, 0xbfbf20b464e8e5d0,
+           0x3fee377960758bfa, 0xbfd98f8e02b6aa78, 0x3fe24da2f8b06fde,
+           0x3fa97d7851fd8b80, 0x3fe535822a7efd70, 0x3fcb8727eb79dda0,
+           0xbfeb38ab561e5658, 0xbfdd013349ed0b50, 0x3fe304a9214adedc,
+           0xbfe01c2a245f7960);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmfne.vf v1, v2, %[A], v0.t" ::[A] "f"(dscalar_64));
+  VSET(1, e16, m1);
+  VCMP_U16(12, v1, 0xaaa2);
+};
+
+// Check if only the correct destination bits are written
+void TEST_CASE5(void) {
+  // Fill 64-bits with 1
+  VSET(1, e64, m1);
+  VLOAD_64(v1, 0xffffffffffffffff);
+  // Perform vmfne.vv on 16 different elements, and then check that the last (64
+  // - 16 = 48) bits were not overwritten with zeroes
+  VSET(16, e16, m1);
+  //               0.2434,  0.7285,  0.7241, -0.2678,  0.0027, -0.7114,  0.2622,
+  //               0.8701, -0.5786, -0.4229,  0.5981,  0.6968,  0.7217, -0.2842,
+  //               0.1328,  0.1659
+  VLOAD_16(v2, 0x33ca, 0x39d4, 0x39cb, 0xb449, 0x1975, 0xb9b1, 0x3432, 0x3af6,
+           0xb8a1, 0xb6c4, 0x38c9, 0x3993, 0x39c6, 0xb48c, 0x3040, 0x314f);
+  //               0.7319,  0.0590,  0.7593, -0.6606, -0.4758,  0.8530,  0.0453,
+  //               0.0987,  0.1777,  0.3047,  0.2330, -0.3467, -0.4153,  0.7080,
+  //               0.3142, -0.9492
+  VLOAD_16(v3, 0x33ca, 0x2b8c, 0x3a13, 0xb949, 0xb79d, 0x3ad3, 0x29cc, 0x2e51,
+           0x31b0, 0x34e0, 0x3375, 0xb58c, 0xb6a5, 0x39aa, 0x3041, 0xbb98);
+  asm volatile("vmfne.vv v1, v2, v3");
+  VSET(1, e64, m1);
+  VCMP_U64(13, v1, 0xfffffffffffffffe);
+
+  // Fill 64-bits with 1
+  VSET(1, e64, m1);
+  VLOAD_64(v1, 0xffffffffffffffff);
+  // Perform vmfne.vv on 16 different elements, and then check that the last (64
+  // - 16 = 48) bits were not overwritten with zeroes
+  VSET(16, e32, m1);
+  //              -0.72077256,        sNaN, -0.34645590, -0.06222415,
+  //              0.96037650, -0.81018746, -0.69337404,  0.70466602,
+  //              -0.30920035, -0.31596854, -0.92116749,  0.51336122,
+  //              0.22002794,  0.48599416,  0.69166088,  0.85755372
+  VLOAD_32(v2, 0x70000000, 0xffffffff, 0xbeb162ab, 0xbd7edebf, 0x3f75db3c,
+           0xbf4f6872, 0xbf3180f6, 0x3f3464fe, 0xbe9e4f82, 0xbea1c6a1,
+           0xbf6bd1a2, 0x3f036ba4, 0x3e614f01, 0x3ef8d43a, 0x3f3110b0,
+           0x3f5b88a4);
+  //               0.79994357,        sNaN, -0.34645590, -0.81853813,
+  //               0.24656086, -0.71423489, -0.44735566, -0.25510681,
+  //               -0.94378990, -0.30138883,  0.19188073, -0.29310879,
+  //               -0.22981364, -0.58626360, -0.80913633, -0.00670803
+  VLOAD_32(v3, 0x80000000, 0xffffffff, 0xbeb162ab, 0xbf518bb7, 0x3e7c7a73,
+           0xbf36d819, 0xbee50bcd, 0xbe829d5c, 0xbf719c37, 0xbe9a4fa3,
+           0x3e447c62, 0xbe96125b, 0xbe6b5444, 0xbf16155f, 0xbf4f238f,
+           0xbbdbcefe);
+  asm volatile("vmfne.vv v1, v2, v3");
+  VSET(1, e64, m1);
+  VCMP_U64(14, v1, 0xfffffffffffffffb);
+
+  // Fill 64-bits with 1
+  VSET(1, e64, m1);
+  VLOAD_64(v1, 0xffffffffffffffff);
+  // Perform vmfne.vv on 16 different elements, and then check that the last (64
+  // - 16 = 48) bits were not overwritten with zeroes
+  VSET(16, e64, m1);
+  //               0.8643613633211786,  0.4842301798024149,  0.9229840140784857,
+  //               -0.9479687162489723, -0.1308855743137316,
+  //               -0.3798019472030296,  0.1570811980936915,
+  //               -0.7665403705017886, -0.3736408604742532, 0.4947226024634424,
+  //               -0.3032110323317654,  0.8998114670494881, 0.6283940115157876,
+  //               0.1053912590957002, -0.2936564640984622,  0.4329957213663693
+  VLOAD_64(v2, 0x3feba8d9296c7e74, 0x3fdefda0947f3460, 0xbf3180f63f75db3c,
+           0xbfee55c27d3d743e, 0xbfc0c0dbc6990b38, 0xbfd84eacd38c6ca4,
+           0x3fc41b3c98507fe0, 0xbfe8877fabcbce12, 0xbfd7e9bb5b0beaf8,
+           0x3fdfa988fd8b0a24, 0xbfd367cf3ee9af68, 0x3feccb416af162fc,
+           0x3fe41bcdc20ecd40, 0x3fbafaebeb19acf0, 0xbfd2cb447b63f610,
+           0x3fdbb633afa4e520);
+  //               0.8643613633211786, -0.0135629748736219,  0.6176167733891369,
+  //               0.9703747829163081, -0.0909539316920625, -0.1057326828885887,
+  //               -0.8792039527057112, -0.1745056251010144, 0.3110320594479206,
+  //               0.3238986651420683, -0.9079294226891812, -0.9490909352855985,
+  //               0.6962970677624296,  0.7585780695949504, -0.5927175227484118,
+  //               -0.7793965434104730
+  VLOAD_64(v3, 0x3feba8d9296c7e74, 0xbf8bc6e7ac263f80, 0x3fed8915c5665532,
+           0x3fef0d4f6aafa2f6, 0xbfb748c1c20f5de0, 0xbfbb114c0f1ff4b0,
+           0xbfec227053ec5198, 0xbfc6563348637140, 0x3fd3e7f302d586b4,
+           0x3fd4bac177803510, 0xbfed0dc20130d694, 0xbfee5ef3f3ff6a12,
+           0x3fe64810c9cae3fe, 0x3fe84645840bf0a2, 0xbfe2f78abcff0ede,
+           0xbfe8f0d105120796);
+  asm volatile("vmfne.vv v1, v2, v3");
+  VSET(1, e64, m1);
+  VCMP_U64(15, v1, 0xfffffffffffffffe);
+};
+
+// Write to v0 during a masked operation, WAR dependency should be respected
+void TEST_CASE6(void) {
+  VSET(16, e16, m1);
+  //               0.2434,  0.7285,  0.7241,  0.7241,  0.0027, -0.7114,  0.8701,
+  //               0.8701, -0.5786, -0.4229,  0.6968,  0.6968,  0.7217, -0.2842,
+  //               0.1659,  0.1659
+  VLOAD_16(v2, 0x33ca, 0x39d4, 0x39cb, 0xb449, 0x1975, 0xb9b1, 0x3af6, 0x3af6,
+           0xb8a1, 0xb6c4, 0x3993, 0x3993, 0x39c6, 0xb48c, 0x314f, 0x314f);
+  //               0.2434,  0.7285, -0.2678, -0.2678,  0.0027, -0.7114,  0.2622,
+  //               0.2622, -0.5786, -0.4229,  0.5981,  0.5981,  0.7217, -0.2842,
+  //               0.1328,  0.1328
+  VLOAD_16(v3, 0x33ca, 0x39d4, 0xb449, 0x39cb, 0x1975, 0xb9b1, 0x3432, 0x3432,
+           0xb8a1, 0xb6c4, 0x38c9, 0x38c9, 0x39c6, 0xb48c, 0x3040, 0x3040);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmfne.vv v0, v2, v3, v0.t");
+  VSET(1, e16, m1);
+  VCMP_U16(16, v0, 0x8888);
+
+  VSET(16, e32, m1);
+  //               0x00000000,  0.09933749, -0.34645590, -0.06222415,
+  //               0.96037650, -0.81018746, -0.69337404,  0.70466602,
+  //               -0.30920035, -0.31596854, -0.92116749,  0.51336122,
+  //               0.22002794,  0.48599416,  0.69166088,  0.85755372
+  VLOAD_32(v2, 0x00000000, 0x3dcb7174, 0xbeb162ab, 0xbd7edebf, 0x3f75db3c,
+           0xbf4f6872, 0xbf3180f6, 0x3f3464fe, 0xbe9e4f82, 0xbea1c6a1,
+           0xbf6bd1a2, 0x3f036ba4, 0x3e614f01, 0x3ef8d43a, 0x3f3110b0,
+           0x3f5d88a4);
+  //               0x00000000,  0.09933749,  0.39402914, -0.81853813,
+  //               0.96037650, -0.81018746, -0.44735566, -0.25510681,
+  //               -0.30920035, -0.31596854,  0.19188073, -0.29310879,
+  //               0.22002794,  0.48599416, -0.80913633, -0.30138883
+  VLOAD_32(v3, 0x00000000, 0x3dcb7174, 0x3ec9be30, 0xbf518bb7, 0x3f75db3c,
+           0xbf4f6872, 0xbee50bcd, 0xbe829d5c, 0xbe9e4f82, 0xbea1c6a1,
+           0x3e447c62, 0xbe96125b, 0x3e614f01, 0x3ef8d43a, 0xbf4f238f,
+           0xbe9a4fa3);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmfne.vv v0, v2, v3, v0.t");
+  VSET(1, e16, m1);
+  VCMP_U16(17, v0, 0x8888);
+
+  VSET(16, e64, m1);
+  //               0.8643613633211786,  0.4842301798024149,  0.9229840140784857,
+  //               -0.8792039527057112, -0.1308855743137316,
+  //               -0.3798019472030296,  0.1570811980936915,
+  //               -0.7665403705017886, -0.3736408604742532, 0.4947226024634424,
+  //               -0.3032110323317654,  0.8998114670494881, 0.6283940115157876,
+  //               0.1053912590957002, -0.2936564640984622, -0.7793965434104730
+  VLOAD_64(v2, 0x3feba8d9296c7e74, 0x3fdefda0947f3460, 0x3fed8915c5665532,
+           0xbfec227053ec5198, 0xbfc0c0dbc6990b38, 0xbfd84eacd38c6ca4,
+           0x3fc41b3c98507fe0, 0xbfe8877fabcbce12, 0xbfd7e9bb5b0beaf8,
+           0x3fdfa988fd8b0a24, 0xbfd367cf3ee9af68, 0x3feccb416af162fc,
+           0x3fe41bcdc20ecd40, 0x3fbafaebeb19acf0, 0xbfd2cb447b63f610,
+           0xbfe8f0d105120796);
+  //               0.8643613633211786,  0.4842301798024149, -0.8792039527057112,
+  //               0.9703747829163081, -0.1308855743137316, -0.3798019472030296,
+  //               -0.8792039527057112, -0.1745056251010144,
+  //               -0.3736408604742532,  0.4947226024634424,
+  //               -0.9079294226891812, -0.9490909352855985, 0.6283940115157876,
+  //               0.1053912590957002, -0.5927175227484118, -0.3032110323317654
+  VLOAD_64(v3, 0x3feba8d9296c7e74, 0x3fdefda0947f3460, 0xbfec227053ec5198,
+           0x9fee55c27d3d743e, 0xbfc0c0dbc6990b38, 0xbfd84eacd38c6ca4,
+           0xbfec227053ec5198, 0xbfc6563348637140, 0xbfd7e9bb5b0beaf8,
+           0x3fdfa988fd8b0a24, 0xbfed0dc20130d694, 0xbfee5ef3f3ff6a12,
+           0x3fe41bcdc20ecd40, 0x3fbafaebeb19acf0, 0xbfe2f78abcff0ede,
+           0xbfd367cf3ee9af68);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmfne.vv v0, v2, v3, v0.t");
+  VSET(1, e16, m1);
+  VCMP_U16(18, v0, 0x8888);
+};
+
+// Test sNaN/qNaN behaviour
+void TEST_CASE7(void) {
+  CLEAR_FFLAGS;
+  // First, give only qNaN (no exception is generated)
+  VSET(16, e16, m1);
+  CHECK_FFLAGS(0);
+  VLOAD_16(v2, qNaNh, qNaNh, 0x39cb, qNaNh, 0x1975, 0xb9b1, 0x3af6, 0x3af6,
+           0xb8a1, 0xb6c4, 0x3993, 0x3993, qNaNh, 0xb48c, qNaNh, qNaNh);
+  VLOAD_16(v3, 0x33ca, qNaNh, qNaNh, 0x39cb, 0x1975, 0xb9b1, 0x3432, 0x3432,
+           0xb8a1, 0xb6c4, 0x38c9, 0x38c9, 0x39c6, qNaNh, qNaNh, 0x3040);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmfne.vv v0, v2, v3");
+  VSET(1, e16, m1);
+  VCMP_U16(19, v0, 0xfccf);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x3f75db3c, qNaNf, qNaNf, qNaNf, 0x3f75db3c, 0xbf4f6872,
+           0xbf3180f6, 0x3f3464fe, 0xbe9e4f82, 0xbea1c6a1, 0xbf6bd1a2,
+           0x3f036ba4, qNaNf, qNaNf, 0x3f3110b0, qNaNf);
+  VLOAD_32(v3, 0x3f75db3c, 0x3dcb7174, qNaNf, 0xbf518bb7, 0x3f75db3c,
+           0xbf4f6872, 0xbee50bcd, 0xbe829d5c, 0xbe9e4f82, 0xbea1c6a1,
+           0x3e447c62, 0xbe96125b, qNaNf, 0x3ef8d43a, qNaNf, qNaNf);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmfne.vv v0, v2, v3");
+  VSET(1, e16, m1);
+  VCMP_U16(20, v0, 0xfcce);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, qNaNd, qNaNd, 0x3fed8915c5665532, 0xbfec227053ec5198,
+           0xbfc0c0dbc6990b38, 0xbfd84eacd38c6ca4, 0x3fc41b3c98507fe0,
+           0xbfe8877fabcbce12, 0xbfd7e9bb5b0beaf8, 0x3fdfa988fd8b0a24,
+           0xbfd367cf3ee9af68, 0x3feccb416af162fc, qNaNd, qNaNd,
+           0xbfd2cb447b63f610, qNaNd);
+  VLOAD_64(v3, qNaNd, 0x3fdefda0947f3460, qNaNd, 0x9fee55c27d3d743e,
+           0xbfc0c0dbc6990b38, 0xbfd84eacd38c6ca4, 0xbfec227053ec5198,
+           0xbfc6563348637140, 0xbfd7e9bb5b0beaf8, 0x3fdfa988fd8b0a24,
+           0xbfed0dc20130d694, 0xbfee5ef3f3ff6a12, qNaNd, 0x3fbafaebeb19acf0,
+           qNaNd, qNaNd);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmfne.vv v0, v2, v3");
+  VSET(1, e16, m1);
+  VCMP_U16(21, v0, 0xfccf);
+  CHECK_FFLAGS(0);
+
+  // Give sNaN (Invalid operation)
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x3f75db3c, sNaNf, sNaNf, qNaNf, 0x3f75db3c, 0xbf4f6872,
+           0xbf3180f6, 0x3f3464fe, 0xbe9e4f82, 0xbea1c6a1, 0xbf6bd1a2,
+           0x3f036ba4, qNaNf, qNaNf, 0x3f3110b0, qNaNf);
+  VLOAD_32(v3, 0x3f75db3c, 0x3dcb7174, qNaNf, 0xbf518bb7, 0x3f75db3c,
+           0xbf4f6872, 0xbee50bcd, 0xbe829d5c, 0xbe9e4f82, 0xbea1c6a1,
+           0x3e447c62, 0xbe96125b, qNaNf, 0x3ef8d43a, qNaNf, qNaNf);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmfne.vv v0, v2, v3");
+  VSET(1, e16, m1);
+  VCMP_U16(22, v0, 0xfcce);
+  CHECK_FFLAGS(NV);
+};
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+  enable_fp();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  //  TEST_CASE5();
+  TEST_CASE6();
+  TEST_CASE7();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vmin.c b/apps/riscv-tests/isa/rv64uv/vmin.c
new file mode 100644
index 0000000..65ec23e
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vmin.c
@@ -0,0 +1,181 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 12345, -80, 2560, -19900, 12345, -80, 2560, -19900, 12345, -80,
+           2560, -19900, 12345, -80, 2560, -19900);
+  VLOAD_16(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  asm volatile("vmin.vv v1, v2, v3");
+  VCMP_I16(1, v1, 50, -80, 400, -19900, 50, -80, 400, -19900, 50, -80, 400,
+           -19900, 50, -80, 400, -19900);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 12345, -80, 2560, -19900, 12345, -80, 2560, -19900, 12345, -80,
+           2560, -19900, 12345, -80, 2560, -19900);
+  VLOAD_32(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  asm volatile("vmin.vv v1, v2, v3");
+  VCMP_I32(2, v1, 50, -80, 400, -19900, 50, -80, 400, -19900, 50, -80, 400,
+           -19900, 50, -80, 400, -19900);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 12345, -80, 2560, -19900, 12345, -80, 2560, -19900, 12345, -80,
+           2560, -19900, 12345, -80, 2560, -19900);
+  VLOAD_64(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  asm volatile("vmin.vv v1, v2, v3");
+  VCMP_I64(3, v1, 50, -80, 400, -19900, 50, -80, 400, -19900, 50, -80, 400,
+           -19900, 50, -80, 400, -19900);
+};
+
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 12345, -80, 2560, -19900, 12345, -80, 2560, -19900, 12345, -80,
+           2560, -19900, 12345, -80, 2560, -19900);
+  VLOAD_16(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VLOAD_16(v1, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef,
+           0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef);
+  asm volatile("vmin.vv v1, v2, v3, v0.t");
+  VCMP_I16(4, v1, 0xbeef, 0xbeef, 400, -19900, 0xbeef, 0xbeef, 400, -19900,
+           0xbeef, 0xbeef, 400, -19900, 0xbeef, 0xbeef, 400, -19900);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 12345, -80, 2560, -19900, 12345, -80, 2560, -19900, 12345, -80,
+           2560, -19900, 12345, -80, 2560, -19900);
+  VLOAD_32(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VLOAD_32(v1, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
+           0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
+           0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
+           0xdeadbeef);
+  asm volatile("vmin.vv v1, v2, v3, v0.t");
+  VCMP_I32(5, v1, 0xdeadbeef, 0xdeadbeef, 400, -19900, 0xdeadbeef, 0xdeadbeef,
+           400, -19900, 0xdeadbeef, 0xdeadbeef, 400, -19900, 0xdeadbeef,
+           0xdeadbeef, 400, -19900);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 12345, -80, 2560, -19900, 12345, -80, 2560, -19900, 12345, -80,
+           2560, -19900, 12345, -80, 2560, -19900);
+  VLOAD_64(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VLOAD_64(v1, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef);
+  asm volatile("vmin.vv v1, v2, v3, v0.t");
+  VCMP_I64(6, v1, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 400, -19900,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 400, -19900,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 400, -19900,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 400, -19900);
+};
+
+void TEST_CASE3(void) {
+  const uint64_t scalar = 40;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 123, -8, -25, 99, 123, -8, -25, 99, 123, -8, -25, 99, 123, -8,
+          -25, 99);
+  asm volatile("vmin.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_I8(7, v1, 40, -8, -25, 40, 40, -8, -25, 40, 40, -8, -25, 40, 40, -8, -25,
+          40);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 12345, -8, -25, 199, 12345, -8, -25, 199, 12345, -8, -25, 199,
+           12345, -8, -25, 199);
+  asm volatile("vmin.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_I16(8, v1, 40, -8, -25, 40, 40, -8, -25, 40, 40, -8, -25, 40, 40, -8,
+           -25, 40);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 12345, -8, -25, 199, 12345, -8, -25, 199, 12345, -8, -25, 199,
+           12345, -8, -25, 199);
+  asm volatile("vmin.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_I32(9, v1, 40, -8, -25, 40, 40, -8, -25, 40, 40, -8, -25, 40, 40, -8,
+           -25, 40);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 12345, -8, -25, 199, 12345, -8, -25, 199, 12345, -8, -25, 199,
+           12345, -8, -25, 199);
+  asm volatile("vmin.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_I64(10, v1, 40, -8, -25, 40, 40, -8, -25, 40, 40, -8, -25, 40, 40, -8,
+           -25, 40);
+};
+
+void TEST_CASE4(void) {
+  const uint64_t scalar = 40;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 123, -8, -25, 99, 123, -8, -25, 99, 123, -8, -25, 99, 123, -8,
+          -25, 99);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VLOAD_8(v1, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef,
+          0xef, 0xef, 0xef, 0xef, 0xef);
+  asm volatile("vmin.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_I8(11, v1, 0xef, 0xef, -25, 40, 0xef, 0xef, -25, 40, 0xef, 0xef, -25, 40,
+          0xef, 0xef, -25, 40);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 12345, -8, -25, 199, 12345, -8, -25, 199, 12345, -8, -25, 199,
+           12345, -8, -25, 199);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VLOAD_16(v1, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef,
+           0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef);
+  asm volatile("vmin.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_I16(12, v1, 0xbeef, 0xbeef, -25, 40, 0xbeef, 0xbeef, -25, 40, 0xbeef,
+           0xbeef, -25, 40, 0xbeef, 0xbeef, -25, 40);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 12345, -8, -25, 199, 12345, -8, -25, 199, 12345, -8, -25, 199,
+           12345, -8, -25, 199);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VLOAD_32(v1, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
+           0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
+           0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
+           0xdeadbeef);
+  asm volatile("vmin.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_I32(13, v1, 0xdeadbeef, 0xdeadbeef, -25, 40, 0xdeadbeef, 0xdeadbeef, -25,
+           40, 0xdeadbeef, 0xdeadbeef, -25, 40, 0xdeadbeef, 0xdeadbeef, -25,
+           40);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 12345, -8, -25, 199, 12345, -8, -25, 199, 12345, -8, -25, 199,
+           12345, -8, -25, 199);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VLOAD_64(v1, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef);
+  asm volatile("vmin.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_I64(14, v1, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, -25, 40,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, -25, 40, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, -25, 40, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           -25, 40);
+};
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vminu.c b/apps/riscv-tests/isa/rv64uv/vminu.c
new file mode 100644
index 0000000..f6d8058
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vminu.c
@@ -0,0 +1,176 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 12345, 80, 2560, 19900, 12345, 80, 2560, 19900, 12345, 80, 2560,
+           19900, 12345, 80, 2560, 19900);
+  VLOAD_16(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  asm volatile("vminu.vv v1, v2, v3");
+  VCMP_U16(1, v1, 50, 80, 400, 19900, 50, 80, 400, 19900, 50, 80, 400, 19900,
+           50, 80, 400, 19900);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 12345, 80, 2560, 19900, 12345, 80, 2560, 19900, 12345, 80, 2560,
+           19900, 12345, 80, 2560, 19900);
+  VLOAD_32(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  asm volatile("vminu.vv v1, v2, v3");
+  VCMP_U32(2, v1, 50, 80, 400, 19900, 50, 80, 400, 19900, 50, 80, 400, 19900,
+           50, 80, 400, 19900);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 12345, 80, 2560, 19900, 12345, 80, 2560, 19900, 12345, 80, 2560,
+           19900, 12345, 80, 2560, 19900);
+  VLOAD_64(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  asm volatile("vminu.vv v1, v2, v3");
+  VCMP_U64(3, v1, 50, 80, 400, 19900, 50, 80, 400, 19900, 50, 80, 400, 19900,
+           50, 80, 400, 19900);
+};
+
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 12345, 80, 2560, 19900, 12345, 80, 2560, 19900, 12345, 80, 2560,
+           19900, 12345, 80, 2560, 19900);
+  VLOAD_16(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VLOAD_16(v1, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef,
+           0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef);
+  asm volatile("vminu.vv v1, v2, v3, v0.t");
+  VCMP_U16(4, v1, 0xbeef, 0xbeef, 400, 19900, 0xbeef, 0xbeef, 400, 19900,
+           0xbeef, 0xbeef, 400, 19900, 0xbeef, 0xbeef, 400, 19900);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 12345, 80, 2560, 19900, 12345, 80, 2560, 19900, 12345, 80, 2560,
+           19900, 12345, 80, 2560, 19900);
+  VLOAD_32(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VLOAD_32(v1, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
+           0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
+           0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
+           0xdeadbeef);
+  asm volatile("vminu.vv v1, v2, v3, v0.t");
+  VCMP_U32(5, v1, 0xdeadbeef, 0xdeadbeef, 400, 19900, 0xdeadbeef, 0xdeadbeef,
+           400, 19900, 0xdeadbeef, 0xdeadbeef, 400, 19900, 0xdeadbeef,
+           0xdeadbeef, 400, 19900);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 12345, 80, 2560, 19900, 12345, 80, 2560, 19900, 12345, 80, 2560,
+           19900, 12345, 80, 2560, 19900);
+  VLOAD_64(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VLOAD_64(v1, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef);
+  asm volatile("vminu.vv v1, v2, v3, v0.t");
+  VCMP_U64(6, v1, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 400, 19900,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 400, 19900,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 400, 19900,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 400, 19900);
+};
+
+void TEST_CASE3(void) {
+  const uint64_t scalar = 40;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 123, 8, 25, 199, 123, 8, 25, 199, 123, 8, 25, 199, 123, 8, 25,
+          199);
+  asm volatile("vminu.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U8(7, v1, 40, 8, 25, 40, 40, 8, 25, 40, 40, 8, 25, 40, 40, 8, 25, 40);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345,
+           8, 25, 199);
+  asm volatile("vminu.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U16(8, v1, 40, 8, 25, 40, 40, 8, 25, 40, 40, 8, 25, 40, 40, 8, 25, 40);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345,
+           8, 25, 199);
+  asm volatile("vminu.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U32(9, v1, 40, 8, 25, 40, 40, 8, 25, 40, 40, 8, 25, 40, 40, 8, 25, 40);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345,
+           8, 25, 199);
+  asm volatile("vminu.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U64(10, v1, 40, 8, 25, 40, 40, 8, 25, 40, 40, 8, 25, 40, 40, 8, 25, 40);
+};
+
+void TEST_CASE4(void) {
+  const uint64_t scalar = 40;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 123, 8, 25, 199, 123, 8, 25, 199, 123, 8, 25, 199, 123, 8, 25,
+          199);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VLOAD_8(v1, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef,
+          0xef, 0xef, 0xef, 0xef, 0xef);
+  asm volatile("vminu.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U8(11, v1, 0xef, 0xef, 25, 40, 0xef, 0xef, 25, 40, 0xef, 0xef, 25, 40,
+          0xef, 0xef, 25, 40);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345,
+           8, 25, 199);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VLOAD_16(v1, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef,
+           0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef);
+  asm volatile("vminu.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U16(12, v1, 0xbeef, 0xbeef, 25, 40, 0xbeef, 0xbeef, 25, 40, 0xbeef,
+           0xbeef, 25, 40, 0xbeef, 0xbeef, 25, 40);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345,
+           8, 25, 199);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VLOAD_32(v1, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
+           0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
+           0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
+           0xdeadbeef);
+  asm volatile("vminu.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U32(13, v1, 0xdeadbeef, 0xdeadbeef, 25, 40, 0xdeadbeef, 0xdeadbeef, 25,
+           40, 0xdeadbeef, 0xdeadbeef, 25, 40, 0xdeadbeef, 0xdeadbeef, 25, 40);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345,
+           8, 25, 199);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VLOAD_64(v1, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef);
+  asm volatile("vminu.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U64(14, v1, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 25, 40,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 25, 40, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 25, 40, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           25, 40);
+};
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vmnand.c b/apps/riscv-tests/isa/rv64uv/vmnand.c
new file mode 100644
index 0000000..543fb28
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vmnand.c
@@ -0,0 +1,68 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1() {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xCD, 0xEF);
+  VLOAD_8(v3, 0x84, 0x21);
+  asm volatile("vmnand.mm v1, v2, v3");
+  VSET(16, e8, m1);
+  VCMP_U8(1, v1, 0x7B, 0xDE);
+}
+
+void TEST_CASE2() {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xCD, 0xEF);
+  VLOAD_8(v3, 0xFF, 0xFF);
+  asm volatile("vmnand.mm v1, v2, v3");
+  VSET(16, e8, m1);
+  VCMP_U8(2, v1, 0x32, 0x10);
+}
+
+void TEST_CASE3() {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xCD, 0xEF);
+  VLOAD_8(v3, 0x00, 0x00);
+  asm volatile("vmnand.mm v1, v2, v3");
+  VSET(16, e8, m1);
+  VCMP_U8(3, v1, 0xFF, 0xFF);
+}
+
+void TEST_CASE4() {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xCD, 0xEF);
+  VLOAD_8(v3, 0x0F, 0xF0);
+  asm volatile("vmnand.mm v1, v2, v3");
+  VSET(16, e8, m1);
+  VCMP_U8(4, v1, 0xF2, 0x1F);
+}
+
+void TEST_CASE5() {
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 0xFF, 0xFF);
+  VLOAD_8(v2, 0xCD, 0xEF);
+  VLOAD_8(v3, 0x84, 0x21);
+  VSET(16, e8, m1);
+  asm volatile("vmnand.mm v1, v2, v3");
+  VSET(16, e8, m1);
+  VCMP_U8(5, v1, 0x7B, 0xDE);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vmnor.c b/apps/riscv-tests/isa/rv64uv/vmnor.c
new file mode 100644
index 0000000..61a2f81
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vmnor.c
@@ -0,0 +1,68 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1() {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xCD, 0xEF);
+  VLOAD_8(v3, 0x84, 0x21);
+  asm volatile("vmnor.mm v1, v2, v3");
+  VSET(16, e8, m1);
+  VCMP_U8(1, v1, 0x32, 0x10);
+}
+
+void TEST_CASE2() {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xCD, 0xEF);
+  VLOAD_8(v3, 0xFF, 0xFF);
+  asm volatile("vmnor.mm v1, v2, v3");
+  VSET(16, e8, m1);
+  VCMP_U8(2, v1, 0x00, 0x00);
+}
+
+void TEST_CASE3() {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xCD, 0xEF);
+  VLOAD_8(v3, 0x00, 0x00);
+  asm volatile("vmnor.mm v1, v2, v3");
+  VSET(16, e8, m1);
+  VCMP_U8(3, v1, 0x32, 0x10);
+}
+
+void TEST_CASE4() {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xCD, 0xEF);
+  VLOAD_8(v3, 0x0F, 0xF0);
+  asm volatile("vmnor.mm v1, v2, v3");
+  VSET(16, e8, m1);
+  VCMP_U8(4, v1, 0x30, 0x00);
+}
+
+void TEST_CASE5() {
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 0xFF, 0xFF);
+  VLOAD_8(v2, 0xCD, 0xEF);
+  VLOAD_8(v3, 0x84, 0x21);
+  VSET(16, e8, m1);
+  asm volatile("vmnor.mm v1, v2, v3");
+  VSET(16, e8, m1);
+  VCMP_U8(5, v1, 0x32, 0x10);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vmor.c b/apps/riscv-tests/isa/rv64uv/vmor.c
new file mode 100644
index 0000000..2ba46e4
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vmor.c
@@ -0,0 +1,68 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1() {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xCD, 0xEF);
+  VLOAD_8(v3, 0x84, 0x21);
+  asm volatile("vmor.mm v1, v2, v3");
+  VSET(16, e8, m1);
+  VCMP_U8(1, v1, 0xCD, 0xEF);
+}
+
+void TEST_CASE2() {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xCD, 0xEF);
+  VLOAD_8(v3, 0xFF, 0xFF);
+  asm volatile("vmor.mm v1, v2, v3");
+  VSET(16, e8, m1);
+  VCMP_U8(2, v1, 0xFF, 0xFF);
+}
+
+void TEST_CASE3() {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xCD, 0xEF);
+  VLOAD_8(v3, 0x00, 0x00);
+  asm volatile("vmor.mm v1, v2, v3");
+  VSET(16, e8, m1);
+  VCMP_U8(3, v1, 0xCD, 0xEF);
+}
+
+void TEST_CASE4() {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xCD, 0xEF);
+  VLOAD_8(v3, 0x0F, 0xF0);
+  asm volatile("vmor.mm v1, v2, v3");
+  VSET(16, e8, m1);
+  VCMP_U8(4, v1, 0xCF, 0xFF);
+}
+
+void TEST_CASE5() {
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 0xFF, 0xFF);
+  VLOAD_8(v2, 0xCD, 0xEF);
+  VLOAD_8(v3, 0x84, 0x21);
+  VSET(16, e8, m1);
+  asm volatile("vmor.mm v1, v2, v3");
+  VSET(16, e8, m1);
+  VCMP_U8(5, v1, 0xCD, 0xEF);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vmornot.c b/apps/riscv-tests/isa/rv64uv/vmornot.c
new file mode 100644
index 0000000..51ca143
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vmornot.c
@@ -0,0 +1,68 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1() {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xCD, 0xEF);
+  VLOAD_8(v3, 0x84, 0x21);
+  asm volatile("vmornot.mm v1, v2, v3");
+  VSET(16, e8, m1);
+  VCMP_U8(1, v1, 0xFF, 0xFF);
+}
+
+void TEST_CASE2() {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xCD, 0xEF);
+  VLOAD_8(v3, 0xFF, 0xFF);
+  asm volatile("vmornot.mm v1, v2, v3");
+  VSET(16, e8, m1);
+  VCMP_U8(2, v1, 0xCD, 0xEF);
+}
+
+void TEST_CASE3() {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xCD, 0xEF);
+  VLOAD_8(v3, 0x00, 0x00);
+  asm volatile("vmornot.mm v1, v2, v3");
+  VSET(16, e8, m1);
+  VCMP_U8(3, v1, 0xFF, 0xFF);
+}
+
+void TEST_CASE4() {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xCD, 0xEF);
+  VLOAD_8(v3, 0x0F, 0xF0);
+  asm volatile("vmornot.mm v1, v2, v3");
+  VSET(16, e8, m1);
+  VCMP_U8(4, v1, 0xFD, 0xEF);
+}
+
+void TEST_CASE5() {
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 0xFF, 0xFF);
+  VLOAD_8(v2, 0xCD, 0xEF);
+  VLOAD_8(v3, 0x84, 0x21);
+  VSET(16, e8, m1);
+  asm volatile("vmornot.mm v1, v2, v3");
+  VSET(16, e8, m1);
+  VCMP_U8(5, v1, 0xFF, 0xFF);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vmsbc.c b/apps/riscv-tests/isa/rv64uv/vmsbc.c
new file mode 100644
index 0000000..19b9a41
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vmsbc.c
@@ -0,0 +1,168 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 16, 0xef, 10, 0xff, 16, 0xef, 10, 0xff, 16, 0xef, 10, 0xff, 16,
+          0xef, 10, 0xff);
+  VLOAD_8(v2, 4, 0xef, 12, 0x80, 4, 0xef, 12, 0x80, 4, 0xef, 12, 0x80, 4, 0xef,
+          12, 0x80);
+  VLOAD_8(v0, 0x99, 0x99);
+  asm volatile("vmsbc.vvm v3, v1, v2, v0");
+  VSET(2, e8, m1);
+  VCMP_U8(1, v3, 0x44, 0x44);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 16, 0xbeef, 10, 0xffff, 16, 0xbeef, 10, 0xffff, 16, 0xbeef, 10,
+           0xffff, 16, 0xbeef, 10, 0xffff);
+  VLOAD_16(v2, 4, 0xbeef, 12, 0x8000, 4, 0xbeef, 12, 0x8000, 4, 0xbeef, 12,
+           0x8000, 4, 0xbeef, 12, 0x8000);
+  VLOAD_8(v0, 0x99, 0x99);
+  asm volatile("vmsbc.vvm v3, v1, v2, v0");
+  VSET(2, e8, m1);
+  VCMP_U8(2, v3, 0x44, 0x44);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 16, 0xdeadbeef, 10, 0xffffffff, 16, 0xdeadbeef, 10, 0xffffffff,
+           16, 0xdeadbeef, 10, 0xffffffff, 16, 0xdeadbeef, 10, 0xffffffff);
+  VLOAD_32(v2, 4, 0xdeadbeef, 12, 0x80000000, 4, 0xdeadbeef, 12, 0x80000000, 4,
+           0xdeadbeef, 12, 0x80000000, 4, 0xdeadbeef, 12, 0x80000000);
+  VLOAD_8(v0, 0x99, 0x99);
+  asm volatile("vmsbc.vvm v3, v1, v2, v0");
+  VSET(2, e8, m1);
+  VCMP_U8(3, v3, 0x44, 0x44);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 16, 0xdeadbeefdeadbeef, 10, 0xffffffffffffffff, 16,
+           0xdeadbeefdeadbeef, 10, 0xffffffffffffffff, 16, 0xdeadbeefdeadbeef,
+           10, 0xffffffffffffffff, 16, 0xdeadbeefdeadbeef, 10,
+           0xffffffffffffffff);
+  VLOAD_64(v2, 4, 0xdeadbeefdeadbeef, 12, 0x8000000000000000, 4,
+           0xdeadbeefdeadbeef, 12, 0x8000000000000000, 4, 0xdeadbeefdeadbeef,
+           12, 0x8000000000000000, 4, 0xdeadbeefdeadbeef, 12,
+           0x8000000000000000);
+  VLOAD_8(v0, 0x99, 0x99);
+  asm volatile("vmsbc.vvm v3, v1, v2, v0");
+  VSET(2, e8, m1);
+  VCMP_U8(4, v3, 0x44, 0x44);
+};
+
+void TEST_CASE2(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 16, 0xef, 10, 0xff, 16, 0xef, 10, 0xff, 16, 0xef, 10, 0xff, 16,
+          0xef, 10, 0xff);
+  VLOAD_8(v2, 4, 0xef, 12, 0x80, 4, 0xef, 12, 0x80, 4, 0xef, 12, 0x80, 4, 0xef,
+          12, 0x80);
+  asm volatile("vmsbc.vv v3, v1, v2");
+  VSET(2, e8, m1);
+  VCMP_U8(5, v3, 0x44, 0x44);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 16, 0xbeef, 10, 0xffff, 16, 0xbeef, 10, 0xffff, 16, 0xbeef, 10,
+           0xffff, 16, 0xbeef, 10, 0xffff);
+  VLOAD_16(v2, 4, 0xbeef, 12, 0x8000, 4, 0xbeef, 12, 0x8000, 4, 0xbeef, 12,
+           0x8000, 4, 0xbeef, 12, 0x8000);
+  asm volatile("vmsbc.vv v3, v1, v2");
+  VSET(2, e8, m1);
+  VCMP_U8(6, v3, 0x44, 0x44);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 16, 0xdeadbeef, 10, 0xffffffff, 16, 0xdeadbeef, 10, 0xffffffff,
+           16, 0xdeadbeef, 10, 0xffffffff, 16, 0xdeadbeef, 10, 0xffffffff);
+  VLOAD_32(v2, 4, 0xdeadbeef, 12, 0x80000000, 4, 0xdeadbeef, 12, 0x80000000, 4,
+           0xdeadbeef, 12, 0x80000000, 4, 0xdeadbeef, 12, 0x80000000);
+  asm volatile("vmsbc.vv v3, v1, v2");
+  VSET(2, e8, m1);
+  VCMP_U8(7, v3, 0x44, 0x44);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 16, 0xdeadbeefdeadbeef, 10, 0xffffffffffffffff, 16,
+           0xdeadbeefdeadbeef, 10, 0xffffffffffffffff, 16, 0xdeadbeefdeadbeef,
+           10, 0xffffffffffffffff, 16, 0xdeadbeefdeadbeef, 10,
+           0xffffffffffffffff);
+  VLOAD_64(v2, 4, 0xdeadbeefdeadbeef, 12, 0x8000000000000000, 4,
+           0xdeadbeefdeadbeef, 12, 0x8000000000000000, 4, 0xdeadbeefdeadbeef,
+           12, 0x8000000000000000, 4, 0xdeadbeefdeadbeef, 12,
+           0x8000000000000000);
+  asm volatile("vmsbc.vv v3, v1, v2");
+  VSET(2, e8, m1);
+  VCMP_U8(8, v3, 0x44, 0x44);
+};
+
+void TEST_CASE3(void) {
+  const uint64_t scalar = 20;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 20, 10, 30, 25, 20, 10, 30, 25, 20, 10, 30, 25, 20, 10, 30, 25);
+  VLOAD_8(v0, 8, 0, 0, 0, 8, 0, 0, 0, 8, 0, 0, 0, 8, 0, 0, 0);
+  asm volatile("vmsbc.vxm v3, v1, %[A], v0" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(9, v3, 0x22, 0x22);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 20, 10, 30, 25, 20, 10, 30, 25, 20, 10, 30, 25, 20, 10, 30, 25);
+  VLOAD_16(v0, 8, 0, 0, 0, 8, 0, 0, 0, 8, 0, 0, 0, 8, 0, 0, 0);
+  asm volatile("vmsbc.vxm v3, v1, %[A], v0" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(10, v3, 0x22, 0x22);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 20, 10, 30, 25, 20, 10, 30, 25, 20, 10, 30, 25, 20, 10, 30, 25);
+  VLOAD_32(v0, 8, 0, 0, 0, 8, 0, 0, 0, 8, 0, 0, 0, 8, 0, 0, 0);
+  asm volatile("vmsbc.vxm v3, v1, %[A], v0" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(11, v3, 0x22, 0x22);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 20, 10, 30, 25, 20, 10, 30, 25, 20, 10, 30, 25, 20, 10, 30, 25);
+  VLOAD_64(v0, 8, 0, 0, 0, 8, 0, 0, 0, 8, 0, 0, 0, 8, 0, 0, 0);
+  asm volatile("vmsbc.vxm v3, v1, %[A], v0" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(12, v3, 0x22, 0x22);
+};
+
+void TEST_CASE4(void) {
+  const uint64_t scalar = 20;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 20, 10, 30, 25, 20, 10, 30, 25, 20, 10, 30, 25, 20, 10, 30, 25);
+  asm volatile("vmsbc.vx v3, v1, %[A]" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(13, v3, 0x22, 0x22);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 20, 10, 30, 25, 20, 10, 30, 25, 20, 10, 30, 25, 20, 10, 30, 25);
+  asm volatile("vmsbc.vx v3, v1, %[A]" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(14, v3, 0x22, 0x22);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 20, 10, 30, 25, 20, 10, 30, 25, 20, 10, 30, 25, 20, 10, 30, 25);
+  asm volatile("vmsbc.vx v3, v1, %[A]" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(15, v3, 0x22, 0x22);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 20, 10, 30, 25, 20, 10, 30, 25, 20, 10, 30, 25, 20, 10, 30, 25);
+  asm volatile("vmsbc.vx v3, v1, %[A]" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(16, v3, 0x22, 0x22);
+};
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vmsbf.c b/apps/riscv-tests/isa/rv64uv/vmsbf.c
new file mode 100644
index 0000000..eb92f3d
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vmsbf.c
@@ -0,0 +1,160 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1() {
+  VSET(16, e8, m1);
+  VLOAD_8(v3, 8, 0, 0, 0, 0, 0, 0, 0);
+  asm volatile("vmsbf.m v2, v3");
+  VSET(2, e8, m1);
+  VCMP_U8(1, v2, 7, 0);
+}
+
+void TEST_CASE2() {
+  VSET(16, e8, m1);
+  VLOAD_8(v3, 4, 0, 0, 0, 0, 0, 0, 0);
+  asm volatile("vmsbf.m v2, v3");
+  VSET(2, e8, m1);
+  VCMP_U8(2, v2, 3, 0);
+}
+
+void TEST_CASE3() {
+  VSET(16, e8, m1);
+  VLOAD_8(v3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+  asm volatile("vmsbf.m v2, v3");
+  VSET(2, e8, m1);
+  VCMP_U8(3, v2, 0xff, 0xff);
+
+  VSET(16, e8, m1);
+  VLOAD_8(v3, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+  asm volatile("vmsbf.m v2, v3");
+  VSET(2, e8, m1);
+  VCMP_U8(4, v2, 0, 0);
+
+  VSET(16, e8, m1);
+  VLOAD_8(v3, 0x08, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+  VSET(16, e32, m1);
+  asm volatile("vmsbf.m v2, v3");
+  VSET(2, e8, m1);
+  VCMP_U8(5, v2, 0x07, 0x00);
+
+  VSET(8, e64, m2);
+  VLOAD_64(v4, 0, 0, 0, 0, 0, 1, 0, 0);
+  VSET(512, e8, m2);
+  asm volatile("vmsbf.m v2, v4");
+  VSET(16, e32, m2);
+  VCMP_U32(6, v2, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+           0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0, 0, 0,
+           0, 0, 0);
+
+  VSET(16, e64, m2);
+  VLOAD_64(v4, 0, 0, 0, 0, 0, 1, 0, 0, 1685, 0, 0, 1, 0, 0, 0, 0);
+  VSET(1024, e8, m2);
+  asm volatile("vmsbf.m v2, v4");
+  VSET(32, e32, m2);
+  VCMP_U32(7, v2, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+           0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0, 0, 0,
+           0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+}
+
+void TEST_CASE4() {
+  VSET(16, e8, m1);
+  VLOAD_8(v3, 8, 0, 0, 0, 0, 0, 0, 0);
+  VLOAD_8(v0, 3, 0, 0, 0, 0, 0, 0, 0);
+  VCLEAR(v2);
+  VSET(2, e8, m1);
+  asm volatile("vmsbf.m v2, v3, v0.t");
+  VCMP_U8(8, v2, 3, 0);
+
+  VSET(16, e8, m1);
+  VLOAD_8(v3, 8, 0, 0, 0, 0, 0, 0, 0);
+  VLOAD_8(v0, 5, 0, 0, 0, 0, 0, 0, 0);
+  VCLEAR(v2);
+  VSET(16, e8, m1);
+  asm volatile("vmsbf.m v2, v3, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(9, v2, 5, 0);
+
+  VSET(16, e8, m1);
+  VLOAD_8(v3, 0x18, 0, 0, 0, 0, 0, 0, 0);
+  VLOAD_8(v0, 0xf7, 0, 0, 0, 0, 0, 0, 0);
+  VCLEAR(v2);
+  asm volatile("vmsbf.m v2, v3, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(10, v2, 0x07, 0);
+
+  VSET(16, e8, m1);
+  VLOAD_8(v3, 0x18, 0, 0, 0, 0, 0, 0, 0);
+  VLOAD_8(v0, 0xef, 0, 0, 0, 0, 0, 0, 0);
+  VCLEAR(v2);
+  asm volatile("vmsbf.m v2, v3, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(11, v2, 0x07, 0);
+
+  VSET(16, e8, m1);
+  VLOAD_8(v3, 0x8, 0, 0, 0, 0, 0, 0, 0);
+  VLOAD_8(v0, 0xf7, 0xff, 0, 0, 0, 0, 0, 0);
+  VCLEAR(v2);
+  asm volatile("vmsbf.m v2, v3, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(12, v2, 0xf7, 0xff);
+
+  VSET(16, e8, m1);
+  VLOAD_8(v3, 0x38, 0, 0, 0, 0, 0, 0, 0);
+  VLOAD_8(v0, 0xf7, 0, 0, 0, 0, 0, 0, 0);
+  VCLEAR(v2);
+  asm volatile("vmsbf.m v2, v3, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(13, v2, 0x7, 0);
+
+  VSET(16, e8, m1);
+  VLOAD_8(v3, 8, 0, 0, 0, 0, 0, 0, 0);
+  VLOAD_8(v0, 5, 0, 0, 0, 0, 0, 0, 0);
+  VCLEAR(v2);
+  VSET(16, e8, m1);
+  asm volatile("vmsbf.m v2, v3, v0.t");
+  VCMP_U8(14, v2, 5, 0);
+}
+
+void TEST_CASE5() {
+  VSET(16, e8, m1);
+  VLOAD_8(v3, 8, 0, 0, 0, 0, 0, 0, 0);
+  VLOAD_8(v0, 11, 0, 0, 0, 0, 0, 0, 0);
+  VCLEAR(v2);
+  asm volatile("vmsbf.m v2, v3, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(15, v2, 3, 0);
+
+  VSET(16, e8, m1);
+  VLOAD_8(v3, 8, 0, 0, 0, 0, 0, 0, 0);
+  VLOAD_8(v0, 11, 0, 0, 0, 0, 0, 0, 0);
+  VCLEAR_AT_ONE(v2);
+  asm volatile("vmsbf.m v2, v3, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(16, v2, 0xf7, 0xff);
+
+  VSET(8, e8, m1);
+  VLOAD_8(v3, 0x94, 0, 0, 0, 0, 0, 0, 0);
+  VLOAD_8(v0, 0xC3, 0, 0, 0, 0, 0, 0, 0);
+  VCLEAR(v2);
+  asm volatile("vmsbf.m v2, v3, v0.t");
+  VSET(1, e8, m1);
+  VCMP_U8(17, v2, 0x43);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+  enable_fp();
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vmseq.c b/apps/riscv-tests/isa/rv64uv/vmseq.c
new file mode 100644
index 0000000..b881857
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vmseq.c
@@ -0,0 +1,365 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xff, 0x00, 0xf0, 0x0f, 0xff, 0x00, 0xf0, 0x0f, 0xff, 0x00, 0xf0,
+          0x0f, 0xff, 0x00, 0xf0, 0x0f);
+  VLOAD_8(v3, 0xf2, 0x01, 0xf0, 0x0f, 0xf2, 0x01, 0xf0, 0x0f, 0xf2, 0x01, 0xf0,
+          0x0f, 0xf2, 0x01, 0xf0, 0x0f);
+  VCLEAR(v1);
+  asm volatile("vmseq.vv v1, v2, v3");
+  VSET(2, e8, m1);
+  VCMP_U8(1, v1, 0xcc, 0xcc);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0xffff, 0x0000, 0xf0f0, 0x0f0f, 0xffff, 0x0000, 0xf0f0, 0x0f0f,
+           0xffff, 0x0000, 0xf0f0, 0x0f0f, 0xffff, 0x0000, 0xf0f0, 0x0f0f);
+  VLOAD_16(v3, 0xf2ff, 0x0100, 0xf0f0, 0x0f0f, 0xf2ff, 0x0100, 0xf0f0, 0x0f0f,
+           0xf2ff, 0x0100, 0xf0f0, 0x0f0f, 0xf2ff, 0x0100, 0xf0f0, 0x0f0f);
+  VCLEAR(v1);
+  asm volatile("vmseq.vv v1, v2, v3");
+  VSET(2, e8, m1);
+  VCMP_U8(2, v1, 0xcc, 0xcc);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0xffffffff, 0x00000000, 0xf0f0f0f0, 0x0f0f0f0f, 0xffffffff,
+           0x00000000, 0xf0f0f0f0, 0x0f0f0f0f, 0xffffffff, 0x00000000,
+           0xf0f0f0f0, 0x0f0f0f0f, 0xffffffff, 0x00000000, 0xf0f0f0f0,
+           0x0f0f0f0f);
+  VLOAD_32(v3, 0xfff2ffff, 0x01000000, 0xf0f0f0f0, 0x0f0f0f0f, 0xfff2ffff,
+           0x01000000, 0xf0f0f0f0, 0x0f0f0f0f, 0xfff2ffff, 0x01000000,
+           0xf0f0f0f0, 0x0f0f0f0f, 0xfff2ffff, 0x01000000, 0xf0f0f0f0,
+           0x0f0f0f0f);
+  VCLEAR(v1);
+  asm volatile("vmseq.vv v1, v2, v3");
+  VSET(2, e8, m1);
+  VCMP_U8(3, v1, 0xcc, 0xcc);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0xffffffffffffffff, 0x0000000000000000, 0xf0f0f0f0f0f0f0f0,
+           0x0f0f0f0f0f0f0f0f, 0xffffffffffffffff, 0x0000000000000000,
+           0xf0f0f0f0f0f0f0f0, 0x0f0f0f0f0f0f0f0f, 0xffffffffffffffff,
+           0x0000000000000000, 0xf0f0f0f0f0f0f0f0, 0x0f0f0f0f0f0f0f0f,
+           0xffffffffffffffff, 0x0000000000000000, 0xf0f0f0f0f0f0f0f0,
+           0x0f0f0f0f0f0f0f0f);
+  VLOAD_64(v3, 0xfff2ffffffffffff, 0x0100000000000000, 0xf0f0f0f0f0f0f0f0,
+           0x0f0f0f0f0f0f0f0f, 0xfff2ffffffffffff, 0x0100000000000000,
+           0xf0f0f0f0f0f0f0f0, 0x0f0f0f0f0f0f0f0f, 0xfff2ffffffffffff,
+           0x0100000000000000, 0xf0f0f0f0f0f0f0f0, 0x0f0f0f0f0f0f0f0f,
+           0xfff2ffffffffffff, 0x0100000000000000, 0xf0f0f0f0f0f0f0f0,
+           0x0f0f0f0f0f0f0f0f);
+  VCLEAR(v1);
+  asm volatile("vmseq.vv v1, v2, v3");
+  VSET(2, e8, m1);
+  VCMP_U8(4, v1, 0xcc, 0xcc);
+};
+
+void TEST_CASE2(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xff, 0x00, 0xf0, 0x0f, 0xff, 0x00, 0xf0, 0x0f, 0xff, 0x00, 0xf0,
+          0x0f, 0xff, 0x00, 0xf0, 0x0f);
+  VLOAD_8(v3, 0xf2, 0x01, 0xf0, 0x0f, 0xf2, 0x01, 0xf0, 0x0f, 0xf2, 0x01, 0xf0,
+          0x0f, 0xf2, 0x01, 0xf0, 0x0f);
+  VLOAD_8(v0, 0xaa, 0xaa);
+  VCLEAR(v1);
+  asm volatile("vmseq.vv v1, v2, v3, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(5, v1, 0x88, 0x88);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0xffff, 0x0000, 0xf0f0, 0x0f0f, 0xffff, 0x0000, 0xf0f0, 0x0f0f,
+           0xffff, 0x0000, 0xf0f0, 0x0f0f, 0xffff, 0x0000, 0xf0f0, 0x0f0f);
+  VLOAD_16(v3, 0xf2ff, 0x0100, 0xf0f0, 0x0f0f, 0xf2ff, 0x0100, 0xf0f0, 0x0f0f,
+           0xf2ff, 0x0100, 0xf0f0, 0x0f0f, 0xf2ff, 0x0100, 0xf0f0, 0x0f0f);
+  VLOAD_8(v0, 0xaa, 0xaa);
+  VCLEAR(v1);
+  asm volatile("vmseq.vv v1, v2, v3, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(6, v1, 0x88, 0x88);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0xffffffff, 0x00000000, 0xf0f0f0f0, 0x0f0f0f0f, 0xffffffff,
+           0x00000000, 0xf0f0f0f0, 0x0f0f0f0f, 0xffffffff, 0x00000000,
+           0xf0f0f0f0, 0x0f0f0f0f, 0xffffffff, 0x00000000, 0xf0f0f0f0,
+           0x0f0f0f0f);
+  VLOAD_32(v3, 0xfff2ffff, 0x01000000, 0xf0f0f0f0, 0x0f0f0f0f, 0xfff2ffff,
+           0x01000000, 0xf0f0f0f0, 0x0f0f0f0f, 0xfff2ffff, 0x01000000,
+           0xf0f0f0f0, 0x0f0f0f0f, 0xfff2ffff, 0x01000000, 0xf0f0f0f0,
+           0x0f0f0f0f);
+  VLOAD_8(v0, 0xaa, 0xaa);
+  VCLEAR(v1);
+  asm volatile("vmseq.vv v1, v2, v3, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(7, v1, 0x88, 0x88);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0xffffffffffffffff, 0x0000000000000000, 0xf0f0f0f0f0f0f0f0,
+           0x0f0f0f0f0f0f0f0f, 0xffffffffffffffff, 0x0000000000000000,
+           0xf0f0f0f0f0f0f0f0, 0x0f0f0f0f0f0f0f0f, 0xffffffffffffffff,
+           0x0000000000000000, 0xf0f0f0f0f0f0f0f0, 0x0f0f0f0f0f0f0f0f,
+           0xffffffffffffffff, 0x0000000000000000, 0xf0f0f0f0f0f0f0f0,
+           0x0f0f0f0f0f0f0f0f);
+  VLOAD_64(v3, 0xfff2ffffffffffff, 0x0100000000000000, 0xf0f0f0f0f0f0f0f0,
+           0x0f0f0f0f0f0f0f0f, 0xfff2ffffffffffff, 0x0100000000000000,
+           0xf0f0f0f0f0f0f0f0, 0x0f0f0f0f0f0f0f0f, 0xfff2ffffffffffff,
+           0x0100000000000000, 0xf0f0f0f0f0f0f0f0, 0x0f0f0f0f0f0f0f0f,
+           0xfff2ffffffffffff, 0x0100000000000000, 0xf0f0f0f0f0f0f0f0,
+           0x0f0f0f0f0f0f0f0f);
+  VLOAD_8(v0, 0xaa, 0xaa);
+  VCLEAR(v1);
+  asm volatile("vmseq.vv v1, v2, v3, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(8, v1, 0x88, 0x88);
+};
+
+void TEST_CASE3(void) {
+  const uint64_t scalar = 0x00000000ffffffff;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xff, 0x00, 0xf0, 0x0f, 0xff, 0x00, 0xf0, 0x0f, 0xff, 0x00, 0xf0,
+          0x0f, 0xff, 0x00, 0xf0, 0x0f);
+  VCLEAR(v1);
+  asm volatile("vmseq.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(9, v1, 0x11, 0x11);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0xffff, 0x0000, 0xf0f0, 0x0f0f, 0xffff, 0x0000, 0xf0f0, 0x0f0f,
+           0xffff, 0x0000, 0xf0f0, 0x0f0f, 0xffff, 0x0000, 0xf0f0, 0x0f0f);
+  VCLEAR(v1);
+  asm volatile("vmseq.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(10, v1, 0x11, 0x11);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0xffffffff, 0x00000000, 0xf0f0f0f0, 0x0f0f0f0f, 0xffffffff,
+           0x00000000, 0xf0f0f0f0, 0x0f0f0f0f, 0xffffffff, 0x00000000,
+           0xf0f0f0f0, 0x0f0f0f0f, 0xffffffff, 0x00000000, 0xf0f0f0f0,
+           0x0f0f0f0f);
+  VCLEAR(v1);
+  asm volatile("vmseq.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(11, v1, 0x11, 0x11);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0xffffffffffffffff, 0x0000000000000000, 0xf0f0f0f0f0f0f0f0,
+           0x0f0f0f0f0f0f0f0f, 0xffffffffffffffff, 0x0000000000000000,
+           0xf0f0f0f0f0f0f0f0, 0x0f0f0f0f0f0f0f0f, 0xffffffffffffffff,
+           0x0000000000000000, 0xf0f0f0f0f0f0f0f0, 0x0f0f0f0f0f0f0f0f,
+           0xffffffffffffffff, 0x0000000000000000, 0xf0f0f0f0f0f0f0f0,
+           0x0f0f0f0f0f0f0f0f);
+  VCLEAR(v1);
+  asm volatile("vmseq.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(12, v1, 0x00, 0x00);
+};
+
+void TEST_CASE4(void) {
+  const uint64_t scalar = 0x00000000ffffffff;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xff, 0x00, 0xf0, 0x0f, 0xff, 0x00, 0xf0, 0x0f, 0xff, 0x00, 0xf0,
+          0x0f, 0xff, 0x00, 0xf0, 0x0f);
+  VLOAD_8(v0, 0x10, 0x10);
+  VCLEAR(v1);
+  asm volatile("vmseq.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(13, v1, 0x10, 0x10);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0xffff, 0x0000, 0xf0f0, 0x0f0f, 0xffff, 0x0000, 0xf0f0, 0x0f0f,
+           0xffff, 0x0000, 0xf0f0, 0x0f0f, 0xffff, 0x0000, 0xf0f0, 0x0f0f);
+  VLOAD_8(v0, 0x10, 0x10);
+  VCLEAR(v1);
+  asm volatile("vmseq.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(14, v1, 0x10, 0x10);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0xffffffff, 0x00000000, 0xf0f0f0f0, 0x0f0f0f0f, 0xffffffff,
+           0x00000000, 0xf0f0f0f0, 0x0f0f0f0f, 0xffffffff, 0x00000000,
+           0xf0f0f0f0, 0x0f0f0f0f, 0xffffffff, 0x00000000, 0xf0f0f0f0,
+           0x0f0f0f0f);
+  VLOAD_8(v0, 0x10, 0x10);
+  VCLEAR(v1);
+  asm volatile("vmseq.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(15, v1, 0x10, 0x10);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0xffffffffffffffff, 0x0000000000000000, 0xf0f0f0f0f0f0f0f0,
+           0x0f0f0f0f0f0f0f0f, 0xffffffffffffffff, 0x0000000000000000,
+           0xf0f0f0f0f0f0f0f0, 0x0f0f0f0f0f0f0f0f, 0xffffffffffffffff,
+           0x0000000000000000, 0xf0f0f0f0f0f0f0f0, 0x0f0f0f0f0f0f0f0f,
+           0xffffffffffffffff, 0x0000000000000000, 0xf0f0f0f0f0f0f0f0,
+           0x0f0f0f0f0f0f0f0f);
+  VLOAD_8(v0, 0x10, 0x10);
+  VCLEAR(v1);
+  asm volatile("vmseq.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(16, v1, 0x00, 0x00);
+};
+
+void TEST_CASE5(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x0f, 0x00, 0xf0, 0x0f, 0x0f, 0x00, 0xf0, 0x0f, 0x0f, 0x00, 0xf0,
+          0x0f, 0x0f, 0x00, 0xf0, 0x0f);
+  VCLEAR(v1);
+  asm volatile("vmseq.vi v1, v2, 15");
+  VSET(2, e8, m1);
+  VCMP_U8(17, v1, 0x99, 0x99);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x000f, 0x0000, 0xf0f0, 0x0f0f, 0x000f, 0x0000, 0xf0f0, 0x0f0f,
+           0x000f, 0x0000, 0xf0f0, 0x0f0f, 0x000f, 0x0000, 0xf0f0, 0x0f0f);
+  VCLEAR(v1);
+  asm volatile("vmseq.vi v1, v2, 15");
+  VSET(2, e8, m1);
+  VCMP_U8(18, v1, 0x11, 0x11);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x0000000f, 0x00000000, 0xf0f0f0f0, 0x0f0f0f0f, 0x0000000f,
+           0x00000000, 0xf0f0f0f0, 0x0f0f0f0f, 0x0000000f, 0x00000000,
+           0xf0f0f0f0, 0x0f0f0f0f, 0x0000000f, 0x00000000, 0xf0f0f0f0,
+           0x0f0f0f0f);
+  VCLEAR(v1);
+  asm volatile("vmseq.vi v1, v2, 15");
+  VSET(2, e8, m1);
+  VCMP_U8(19, v1, 0x11, 0x11);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x000000000000000f, 0x0000000000000000, 0xf0f0f0f0f0f0f0f0,
+           0x0f0f0f0f0f0f0f0f, 0x000000000000000f, 0x0000000000000000,
+           0xf0f0f0f0f0f0f0f0, 0x0f0f0f0f0f0f0f0f, 0x000000000000000f,
+           0x0000000000000000, 0xf0f0f0f0f0f0f0f0, 0x0f0f0f0f0f0f0f0f,
+           0x000000000000000f, 0x0000000000000000, 0xf0f0f0f0f0f0f0f0,
+           0x0f0f0f0f0f0f0f0f);
+  VCLEAR(v1);
+  asm volatile("vmseq.vi v1, v2, 15");
+  VSET(2, e8, m1);
+  VCMP_U8(20, v1, 0x11, 0x11);
+};
+
+void TEST_CASE6(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x0f, 0x00, 0xf0, 0x0f, 0x0f, 0x00, 0xf0, 0x0f, 0x0f, 0x00, 0xf0,
+          0x0f, 0x0f, 0x00, 0xf0, 0x0f);
+  VLOAD_8(v0, 0x10, 0x10);
+  VCLEAR(v1);
+  asm volatile("vmseq.vi v1, v2, 15, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(21, v1, 0x10, 0x10);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x000f, 0x0000, 0xf0f0, 0x0f0f, 0x000f, 0x0000, 0xf0f0, 0x0f0f,
+           0x000f, 0x0000, 0xf0f0, 0x0f0f, 0x000f, 0x0000, 0xf0f0, 0x0f0f);
+  VLOAD_8(v0, 0x10, 0x10);
+  VCLEAR(v1);
+  asm volatile("vmseq.vi v1, v2, 15, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(22, v1, 0x10, 0x10);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x0000000f, 0x00000000, 0xf0f0f0f0, 0x0f0f0f0f, 0x0000000f,
+           0x00000000, 0xf0f0f0f0, 0x0f0f0f0f, 0x0000000f, 0x00000000,
+           0xf0f0f0f0, 0x0f0f0f0f, 0x0000000f, 0x00000000, 0xf0f0f0f0,
+           0x0f0f0f0f);
+  VLOAD_8(v0, 0x10, 0x10);
+  VCLEAR(v1);
+  asm volatile("vmseq.vi v1, v2, 15, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(23, v1, 0x10, 0x10);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x000000000000000f, 0x0000000000000000, 0xf0f0f0f0f0f0f0f0,
+           0x0f0f0f0f0f0f0f0f, 0x000000000000000f, 0x0000000000000000,
+           0xf0f0f0f0f0f0f0f0, 0x0f0f0f0f0f0f0f0f, 0x000000000000000f,
+           0x0000000000000000, 0xf0f0f0f0f0f0f0f0, 0x0f0f0f0f0f0f0f0f,
+           0x000000000000000f, 0x0000000000000000, 0xf0f0f0f0f0f0f0f0,
+           0x0f0f0f0f0f0f0f0f);
+  VLOAD_8(v0, 0x10, 0x10);
+  VCLEAR(v1);
+  asm volatile("vmseq.vi v1, v2, 15, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(24, v1, 0x10, 0x10);
+};
+
+void TEST_CASE7(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xff, 0x00, 0xf0, 0x0f, 0xff, 0x00, 0xf0, 0x0f, 0xff, 0x00, 0xf0,
+          0x0f, 0xff, 0x00, 0xf0, 0x0f);
+  VLOAD_8(v3, 0xf2, 0x01, 0xf0, 0x0f, 0xf2, 0x01, 0xf0, 0x0f, 0xf2, 0x01, 0xf0,
+          0x0f, 0xf2, 0x01, 0xf0, 0x0f);
+  VLOAD_8(v0, 0xaa, 0xaa);
+  VCLEAR_AT_ONE(v1);
+  asm volatile("vmseq.vv v1, v2, v3, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(25, v1, 0xdd, 0xdd);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0xffff, 0x0000, 0xf0f0, 0x0f0f, 0xffff, 0x0000, 0xf0f0, 0x0f0f,
+           0xffff, 0x0000, 0xf0f0, 0x0f0f, 0xffff, 0x0000, 0xf0f0, 0x0f0f);
+  VLOAD_16(v3, 0xf2ff, 0x0100, 0xf0f0, 0x0f0f, 0xf2ff, 0x0100, 0xf0f0, 0x0f0f,
+           0xf2ff, 0x0100, 0xf0f0, 0x0f0f, 0xf2ff, 0x0100, 0xf0f0, 0x0f0f);
+  VLOAD_8(v0, 0xaa, 0xaa);
+  VCLEAR_AT_ONE(v1);
+  asm volatile("vmseq.vv v1, v2, v3, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(26, v1, 0xdd, 0xdd);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0xffffffff, 0x00000000, 0xf0f0f0f0, 0x0f0f0f0f, 0xffffffff,
+           0x00000000, 0xf0f0f0f0, 0x0f0f0f0f, 0xffffffff, 0x00000000,
+           0xf0f0f0f0, 0x0f0f0f0f, 0xffffffff, 0x00000000, 0xf0f0f0f0,
+           0x0f0f0f0f);
+  VLOAD_32(v3, 0xfff2ffff, 0x01000000, 0xf0f0f0f0, 0x0f0f0f0f, 0xfff2ffff,
+           0x01000000, 0xf0f0f0f0, 0x0f0f0f0f, 0xfff2ffff, 0x01000000,
+           0xf0f0f0f0, 0x0f0f0f0f, 0xfff2ffff, 0x01000000, 0xf0f0f0f0,
+           0x0f0f0f0f);
+  VLOAD_8(v0, 0xaa, 0xaa);
+  VCLEAR_AT_ONE(v1);
+  asm volatile("vmseq.vv v1, v2, v3, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(27, v1, 0xdd, 0xdd);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0xffffffffffffffff, 0x0000000000000000, 0xf0f0f0f0f0f0f0f0,
+           0x0f0f0f0f0f0f0f0f, 0xffffffffffffffff, 0x0000000000000000,
+           0xf0f0f0f0f0f0f0f0, 0x0f0f0f0f0f0f0f0f, 0xffffffffffffffff,
+           0x0000000000000000, 0xf0f0f0f0f0f0f0f0, 0x0f0f0f0f0f0f0f0f,
+           0xffffffffffffffff, 0x0000000000000000, 0xf0f0f0f0f0f0f0f0,
+           0x0f0f0f0f0f0f0f0f);
+  VLOAD_64(v3, 0xfff2ffffffffffff, 0x0100000000000000, 0xf0f0f0f0f0f0f0f0,
+           0x0f0f0f0f0f0f0f0f, 0xfff2ffffffffffff, 0x0100000000000000,
+           0xf0f0f0f0f0f0f0f0, 0x0f0f0f0f0f0f0f0f, 0xfff2ffffffffffff,
+           0x0100000000000000, 0xf0f0f0f0f0f0f0f0, 0x0f0f0f0f0f0f0f0f,
+           0xfff2ffffffffffff, 0x0100000000000000, 0xf0f0f0f0f0f0f0f0,
+           0x0f0f0f0f0f0f0f0f);
+  VLOAD_8(v0, 0xaa, 0xaa);
+  VCLEAR_AT_ONE(v1);
+  asm volatile("vmseq.vv v1, v2, v3, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(28, v1, 0xdd, 0xdd);
+};
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+  TEST_CASE6();
+  TEST_CASE7();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vmsgt.c b/apps/riscv-tests/isa/rv64uv/vmsgt.c
new file mode 100644
index 0000000..8fb6978
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vmsgt.c
@@ -0,0 +1,168 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  const uint64_t scalar = 40;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 123, -8, -25, 99, 123, -8, -25, 99, 123, -8, -25, 99, 123, -8,
+          -25, 99);
+  VCLEAR(v1);
+  asm volatile("vmsgt.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(1, v1, 0x99, 0x99);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 12345, -8, -25, 199, 12345, -8, -25, 199, 12345, -8, -25, 199,
+           12345, -8, -25, 199);
+  VCLEAR(v1);
+  asm volatile("vmsgt.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(2, v1, 0x99, 0x99);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 12345, -8, -25, 199, 12345, -8, -25, 199, 12345, -8, -25, 199,
+           12345, -8, -25, 199);
+  VCLEAR(v1);
+  asm volatile("vmsgt.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(3, v1, 0x99, 0x99);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 12345, -8, -25, 199, 12345, -8, -25, 199, 12345, -8, -25, 199,
+           12345, -8, -25, 199);
+  VCLEAR(v1);
+  asm volatile("vmsgt.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(4, v1, 0x99, 0x99);
+};
+
+void TEST_CASE2(void) {
+  const uint64_t scalar = 40;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 123, -8, -25, 99, 123, -8, -25, 99, 123, -8, -25, 99, 123, -8,
+          -25, 99);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmsgt.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(5, v1, 0x88, 0x88);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 12345, -8, -25, 199, 12345, -8, -25, 199, 12345, -8, -25, 199,
+           12345, -8, -25, 199);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmsgt.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(6, v1, 0x88, 0x88);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 12345, -8, -25, 199, 12345, -8, -25, 199, 12345, -8, -25, 199,
+           12345, -8, -25, 199);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmsgt.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(7, v1, 0x88, 0x88);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 12345, -8, -25, 199, 12345, -8, -25, 199, 12345, -8, -25, 199,
+           12345, -8, -25, 199);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmsgt.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(8, v1, 0x88, 0x88);
+};
+
+void TEST_CASE3(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 123, -8, -25, 99, 123, -8, -25, 99, 123, -8, -25, 99, 123, -8,
+          -25, 99);
+  VCLEAR(v1);
+  asm volatile("vmsgt.vi v1, v2, 15");
+  VSET(2, e8, m1);
+  VCMP_U8(9, v1, 0x99, 0x99);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 12345, -8, -25, 199, 12345, -8, -25, 199, 12345, -8, -25, 199,
+           12345, -8, -25, 199);
+  VCLEAR(v1);
+  asm volatile("vmsgt.vi v1, v2, 15");
+  VSET(2, e8, m1);
+  VCMP_U8(10, v1, 0x99, 0x99);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 12345, -8, -25, 199, 12345, -8, -25, 199, 12345, -8, -25, 199,
+           12345, -8, -25, 199);
+  VCLEAR(v1);
+  asm volatile("vmsgt.vi v1, v2, 15");
+  VSET(2, e8, m1);
+  VCMP_U8(11, v1, 0x99, 0x99);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 12345, -8, -25, 199, 12345, -8, -25, 199, 12345, -8, -25, 199,
+           12345, -8, -25, 199);
+  VCLEAR(v1);
+  asm volatile("vmsgt.vi v1, v2, 15");
+  VSET(2, e8, m1);
+  VCMP_U8(12, v1, 0x99, 0x99);
+};
+
+void TEST_CASE4(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 123, -8, -25, 99, 123, -8, -25, 99, 123, -8, -25, 99, 123, -8,
+          -25, 99);
+  VLOAD_8(v0, 0x88, 0x88);
+  VCLEAR(v1);
+  asm volatile("vmsgt.vi v1, v2, 15, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(13, v1, 0x88, 0x88);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 12345, -8, -25, 199, 12345, -8, -25, 199, 12345, -8, -25, 199,
+           12345, -8, -25, 199);
+  VLOAD_8(v0, 0x88, 0x88);
+  VCLEAR(v1);
+  asm volatile("vmsgt.vi v1, v2, 15, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(14, v1, 0x88, 0x88);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 12345, -8, -25, 199, 12345, -8, -25, 199, 12345, -8, -25, 199,
+           12345, -8, -25, 199);
+  VLOAD_8(v0, 0x88, 0x88);
+  VCLEAR(v1);
+  asm volatile("vmsgt.vi v1, v2, 15, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(15, v1, 0x88, 0x88);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 12345, -8, -25, 199, 12345, -8, -25, 199, 12345, -8, -25, 199,
+           12345, -8, -25, 199);
+  VLOAD_8(v0, 0x88, 0x88);
+  VCLEAR(v1);
+  asm volatile("vmsgt.vi v1, v2, 15, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(16, v1, 0x88, 0x88);
+};
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vmsgtu.c b/apps/riscv-tests/isa/rv64uv/vmsgtu.c
new file mode 100644
index 0000000..09fb63d
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vmsgtu.c
@@ -0,0 +1,168 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  const uint64_t scalar = 40;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 123, 8, 25, 199, 123, 8, 25, 199, 123, 8, 25, 199, 123, 8, 25,
+          199);
+  VCLEAR(v1);
+  asm volatile("vmsgtu.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(1, v1, 0x99, 0x99);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345,
+           8, 25, 199);
+  VCLEAR(v1);
+  asm volatile("vmsgtu.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(2, v1, 0x99, 0x99);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345,
+           8, 25, 199);
+  VCLEAR(v1);
+  asm volatile("vmsgtu.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(3, v1, 0x99, 0x99);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345,
+           8, 25, 199);
+  VCLEAR(v1);
+  asm volatile("vmsgtu.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(4, v1, 0x99, 0x99);
+};
+
+void TEST_CASE2(void) {
+  const uint64_t scalar = 40;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 123, 8, 25, 199, 123, 8, 25, 199, 123, 8, 25, 199, 123, 8, 25,
+          199);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmsgtu.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(5, v1, 0x88, 0x88);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345,
+           8, 25, 199);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmsgtu.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(6, v1, 0x88, 0x88);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345,
+           8, 25, 199);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmsgtu.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(7, v1, 0x88, 0x88);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345,
+           8, 25, 199);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmsgtu.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(8, v1, 0x88, 0x88);
+};
+
+void TEST_CASE3(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 123, 8, 25, 199, 123, 8, 25, 199, 123, 8, 25, 199, 123, 8, 25,
+          199);
+  VCLEAR(v1);
+  asm volatile("vmsgtu.vi v1, v2, 15");
+  VSET(2, e8, m1);
+  VCMP_U8(9, v1, 0xDD, 0xDD);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345,
+           8, 25, 199);
+  VCLEAR(v1);
+  asm volatile("vmsgtu.vi v1, v2, 15");
+  VSET(2, e8, m1);
+  VCMP_U8(10, v1, 0xDD, 0xDD);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345,
+           8, 25, 199);
+  VCLEAR(v1);
+  asm volatile("vmsgtu.vi v1, v2, 15");
+  VSET(2, e8, m1);
+  VCMP_U8(11, v1, 0xDD, 0xDD);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345,
+           8, 25, 199);
+  VCLEAR(v1);
+  asm volatile("vmsgtu.vi v1, v2, 15");
+  VSET(2, e8, m1);
+  VCMP_U8(12, v1, 0xDD, 0xDD);
+};
+
+void TEST_CASE4(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 123, 8, 25, 199, 123, 8, 25, 199, 123, 8, 25, 199, 123, 8, 25,
+          199);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmsgtu.vi v1, v2, 15, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(13, v1, 0xCC, 0xCC);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345,
+           8, 25, 199);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmsgtu.vi v1, v2, 15, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(14, v1, 0xCC, 0xCC);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345,
+           8, 25, 199);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmsgtu.vi v1, v2, 15, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(15, v1, 0xCC, 0xCC);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345,
+           8, 25, 199);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmsgtu.vi v1, v2, 15, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(16, v1, 0xCC, 0xCC);
+};
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vmsif.c b/apps/riscv-tests/isa/rv64uv/vmsif.c
new file mode 100644
index 0000000..24a5f3f
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vmsif.c
@@ -0,0 +1,75 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1() {
+  VSET(16, e8, m1);
+  VLOAD_8(v3, 8, 0, 0, 0, 0, 0, 0, 0);
+  asm volatile("vmsif.m v2, v3");
+  VSET(2, e8, m1);
+  VCMP_U8(1, v2, 15, 0);
+}
+
+void TEST_CASE2() {
+  VSET(16, e8, m1);
+  VLOAD_8(v3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+  asm volatile("vmsif.m v2, v3");
+  VSET(2, e8, m1);
+  VCMP_U8(2, v2, 0xff, 0xff);
+
+  VSET(16, e8, m1);
+  VLOAD_8(v3, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+  asm volatile("vmsif.m v2, v3");
+  VSET(2, e8, m1);
+  VCMP_U8(3, v2, 1, 0);
+
+  VSET(16, e8, m1);
+  VLOAD_8(v3, 0x08, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+  VSET(16, e32, m1);
+  asm volatile("vmsif.m v2, v3");
+  VSET(2, e8, m1);
+  VCMP_U8(4, v2, 0x0F, 0x00);
+
+  VSET(8, e64, m2);
+  VLOAD_64(v4, 0, 0, 0, 0, 0, 1, 0, 0);
+  VSET(512, e8, m2);
+  asm volatile("vmsif.m v2, v4");
+  VSET(16, e32, m2);
+  VCMP_U32(5, v2, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+           0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 1, 0, 0,
+           0, 0, 0);
+
+  VSET(16, e64, m2);
+  VLOAD_64(v4, 0, 0, 0, 0, 0, 1, 0, 0, 1685, 0, 0, 1, 0, 0, 0, 0);
+  VSET(1024, e8, m4);
+  asm volatile("vmsif.m v0, v4");
+  VSET(32, e32, m2);
+  VCMP_U32(6, v0, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+           0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 1, 0, 0,
+           0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+}
+
+void TEST_CASE3() {
+  VSET(16, e8, m1);
+  VLOAD_8(v3, 8, 0, 0, 0, 0, 0, 0, 0);
+  VLOAD_8(v0, 11, 0, 0, 0, 0, 0, 0, 0);
+  VCLEAR(v2);
+  asm volatile("vmsif.m v2, v3, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(7, v2, 11, 0, 0, 0, 0, 0, 0, 0);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+  enable_fp();
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vmsle.c b/apps/riscv-tests/isa/rv64uv/vmsle.c
new file mode 100644
index 0000000..00fe0b2
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vmsle.c
@@ -0,0 +1,237 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 50, -80, 2560, -19900, 12345, -80, 2560, -19900, 12345, -80,
+           2560, -19900, 12345, -80, 2560, -19900);
+  VLOAD_16(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  VCLEAR(v1);
+  asm volatile("vmsle.vv v1, v2, v3");
+  VSET(2, e8, m1);
+  VCMP_U8(1, v1, 0xAB, 0xAA);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 50, -80, 2560, -19900, 12345, -80, 2560, -19900, 12345, -80,
+           2560, -19900, 12345, -80, 2560, -19900);
+  VLOAD_32(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  VCLEAR(v1);
+  asm volatile("vmsle.vv v1, v2, v3");
+  VSET(2, e8, m1);
+  VCMP_U8(2, v1, 0xAB, 0xAA);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 50, -80, 2560, -19900, 12345, -80, 2560, -19900, 12345, -80,
+           2560, -19900, 12345, -80, 2560, -19900);
+  VLOAD_64(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  VCLEAR(v1);
+  asm volatile("vmsle.vv v1, v2, v3");
+  VSET(2, e8, m1);
+  VCMP_U8(3, v1, 0xAB, 0xAA);
+};
+
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 12345, -80, 2560, -19900, 12345, -80, 2560, -19900, 12345, -80,
+           2560, -19900, 12345, -80, 2560, -19900);
+  VLOAD_16(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmsle.vv v1, v2, v3, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(4, v1, 0x88, 0x88);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 12345, -80, 2560, -19900, 12345, -80, 2560, -19900, 12345, -80,
+           2560, -19900, 12345, -80, 2560, -19900);
+  VLOAD_32(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmsle.vv v1, v2, v3, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(5, v1, 0x88, 0x88);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 12345, -80, 2560, -19900, 12345, -80, 2560, -19900, 12345, -80,
+           2560, -19900, 12345, -80, 2560, -19900);
+  VLOAD_64(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmsle.vv v1, v2, v3, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(6, v1, 0x88, 0x88);
+};
+
+void TEST_CASE3(void) {
+  const uint64_t scalar = 40;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 123, -8, -25, 99, 123, -8, -25, 99, 123, -8, -25, 99, 123, -8,
+          -25, 99);
+  VCLEAR(v1);
+  asm volatile("vmsle.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(7, v1, 0x66, 0x66);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 12345, -8, -25, 199, 12345, -8, -25, 199, 12345, -8, -25, 199,
+           12345, -8, -25, 199);
+  VCLEAR(v1);
+  asm volatile("vmsle.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(8, v1, 0x66, 0x66);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 12345, -8, -25, 199, 12345, -8, -25, 199, 12345, -8, -25, 199,
+           12345, -8, -25, 199);
+  VCLEAR(v1);
+  asm volatile("vmsle.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(9, v1, 0x66, 0x66);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 12345, -8, -25, 199, 12345, -8, -25, 199, 12345, -8, -25, 199,
+           12345, -8, -25, 199);
+  VCLEAR(v1);
+  asm volatile("vmsle.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(10, v1, 0x66, 0x66);
+};
+
+void TEST_CASE4(void) {
+  const uint64_t scalar = 40;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 123, -8, -25, 99, 123, -8, -25, 99, 123, -8, -25, 99, 123, -8,
+          -25, 99);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmsle.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(11, v1, 0x44, 0x44);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 12345, -8, -25, 199, 12345, -8, -25, 199, 12345, -8, -25, 199,
+           12345, -8, -25, 199);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmsle.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(12, v1, 0x44, 0x44);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 12345, -8, -25, 199, 12345, -8, -25, 199, 12345, -8, -25, 199,
+           12345, -8, -25, 199);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmsle.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(13, v1, 0x44, 0x44);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 12345, -8, -25, 199, 12345, -8, -25, 199, 12345, -8, -25, 199,
+           12345, -8, -25, 199);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmsle.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(14, v1, 0x44, 0x44);
+};
+
+void TEST_CASE5(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 123, -8, -25, 99, 123, -8, -25, 99, 123, -8, -25, 99, 123, -8,
+          -25, 99);
+  VCLEAR(v1);
+  asm volatile("vmsle.vi v1, v2, 15");
+  VSET(2, e8, m1);
+  VCMP_U8(15, v1, 0x66, 0x66);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 12345, -8, -25, 199, 12345, -8, -25, 199, 12345, -8, -25, 199,
+           12345, -8, -25, 199);
+  VCLEAR(v1);
+  asm volatile("vmsle.vi v1, v2, 15");
+  VSET(2, e8, m1);
+  VCMP_U8(16, v1, 0x66, 0x66);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 12345, -8, -25, 199, 12345, -8, -25, 199, 12345, -8, -25, 199,
+           12345, -8, -25, 199);
+  VCLEAR(v1);
+  asm volatile("vmsle.vi v1, v2, 15");
+  VSET(2, e8, m1);
+  VCMP_U8(17, v1, 0x66, 0x66);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 12345, -8, -25, 199, 12345, -8, -25, 199, 12345, -8, -25, 199,
+           12345, -8, -25, 199);
+  VCLEAR(v1);
+  asm volatile("vmsle.vi v1, v2, 15");
+  VSET(2, e8, m1);
+  VCMP_U8(18, v1, 0x66, 0x66);
+};
+
+void TEST_CASE6(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 123, -8, -25, 99, 123, -8, -25, 99, 123, -8, -25, 99, 123, -8,
+          -25, 99);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmsle.vi v1, v2, 15, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(19, v1, 0x44, 0x44);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 12345, -8, -25, 199, 12345, -8, -25, 199, 12345, -8, -25, 199,
+           12345, -8, -25, 199);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmsle.vi v1, v2, 15, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(20, v1, 0x44, 0x44);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 12345, -8, -25, 199, 12345, -8, -25, 199, 12345, -8, -25, 199,
+           12345, -8, -25, 199);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmsle.vi v1, v2, 15, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(21, v1, 0x44, 0x44);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 12345, -8, -25, 199, 12345, -8, -25, 199, 12345, -8, -25, 199,
+           12345, -8, -25, 199);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmsle.vi v1, v2, 15, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(22, v1, 0x44, 0x44);
+};
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+  TEST_CASE6();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vmsleu.c b/apps/riscv-tests/isa/rv64uv/vmsleu.c
new file mode 100644
index 0000000..0ca9b9d
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vmsleu.c
@@ -0,0 +1,237 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 50, 80, 2560, 19900, 12345, 80, 2560, 19900, 12345, 80, 2560,
+           19900, 12345, 80, 2560, 19900);
+  VLOAD_16(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  VCLEAR(v1);
+  asm volatile("vmsleu.vv v1, v2, v3");
+  VSET(2, e8, m1);
+  VCMP_U8(1, v1, 0xAB, 0xAA);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 50, 80, 2560, 19900, 12345, 80, 2560, 19900, 12345, 80, 2560,
+           19900, 12345, 80, 2560, 19900);
+  VLOAD_32(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  VCLEAR(v1);
+  asm volatile("vmsleu.vv v1, v2, v3");
+  VSET(2, e8, m1);
+  VCMP_U8(2, v1, 0xAB, 0xAA);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 50, 80, 2560, 19900, 12345, 80, 2560, 19900, 12345, 80, 2560,
+           19900, 12345, 80, 2560, 19900);
+  VLOAD_64(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  VCLEAR(v1);
+  asm volatile("vmsleu.vv v1, v2, v3");
+  VSET(2, e8, m1);
+  VCMP_U8(3, v1, 0xAB, 0xAA);
+};
+
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 12345, 80, 2560, 19900, 12345, 80, 2560, 19900, 12345, 80, 2560,
+           19900, 12345, 80, 2560, 19900);
+  VLOAD_16(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmsleu.vv v1, v2, v3, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(4, v1, 0x88, 0x88);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 12345, 80, 2560, 19900, 12345, 80, 2560, 19900, 12345, 80, 2560,
+           19900, 12345, 80, 2560, 19900);
+  VLOAD_32(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmsleu.vv v1, v2, v3, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(5, v1, 0x88, 0x88);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 12345, 80, 2560, 19900, 12345, 80, 2560, 19900, 12345, 80, 2560,
+           19900, 12345, 80, 2560, 19900);
+  VLOAD_64(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmsleu.vv v1, v2, v3, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(6, v1, 0x88, 0x88);
+};
+
+void TEST_CASE3(void) {
+  const uint64_t scalar = 40;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 123, 8, 25, 199, 123, 8, 25, 199, 123, 8, 25, 199, 123, 8, 25,
+          199);
+  VCLEAR(v1);
+  asm volatile("vmsleu.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(7, v1, 0x66, 0x66);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345,
+           8, 25, 199);
+  VCLEAR(v1);
+  asm volatile("vmsleu.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(8, v1, 0x66, 0x66);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345,
+           8, 25, 199);
+  VCLEAR(v1);
+  asm volatile("vmsleu.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(9, v1, 0x66, 0x66);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345,
+           8, 25, 199);
+  VCLEAR(v1);
+  asm volatile("vmsleu.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(10, v1, 0x66, 0x66);
+};
+
+void TEST_CASE4(void) {
+  const uint64_t scalar = 40;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 123, 8, 25, 199, 123, 8, 25, 199, 123, 8, 25, 199, 123, 8, 25,
+          199);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmsleu.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(11, v1, 0x44, 0x44);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345,
+           8, 25, 199);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmsleu.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(12, v1, 0x44, 0x44);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345,
+           8, 25, 199);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmsleu.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(13, v1, 0x44, 0x44);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345,
+           8, 25, 199);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmsleu.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(14, v1, 0x44, 0x44);
+};
+
+void TEST_CASE5(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 123, 8, 25, 199, 123, 8, 25, 199, 123, 8, 25, 199, 123, 8, 25,
+          199);
+  VCLEAR(v1);
+  asm volatile("vmsleu.vi v1, v2, 15");
+  VSET(2, e8, m1);
+  VCMP_U8(15, v1, 0x22, 0x22);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345,
+           8, 25, 199);
+  VCLEAR(v1);
+  asm volatile("vmsleu.vi v1, v2, 15");
+  VSET(2, e8, m1);
+  VCMP_U8(16, v1, 0x22, 0x22);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345,
+           8, 25, 199);
+  VCLEAR(v1);
+  asm volatile("vmsleu.vi v1, v2, 15");
+  VSET(2, e8, m1);
+  VCMP_U8(17, v1, 0x22, 0x22);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345,
+           8, 25, 199);
+  VCLEAR(v1);
+  asm volatile("vmsleu.vi v1, v2, 15");
+  VSET(2, e8, m1);
+  VCMP_U8(18, v1, 0x22, 0x22);
+};
+
+void TEST_CASE6(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 123, 8, 25, 199, 123, 8, 25, 199, 123, 8, 25, 199, 123, 8, 25,
+          199);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmsleu.vi v1, v2, 15, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(19, v1, 0x00, 0x00);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345,
+           8, 25, 199);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmsleu.vi v1, v2, 15, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(20, v1, 0x00, 0x00);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345,
+           8, 25, 199);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmsleu.vi v1, v2, 15, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(21, v1, 0x00, 0x00);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345,
+           8, 25, 199);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmsleu.vi v1, v2, 15, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(22, v1, 0x00, 0x00);
+};
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+  TEST_CASE6();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vmslt.c b/apps/riscv-tests/isa/rv64uv/vmslt.c
new file mode 100644
index 0000000..839604e
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vmslt.c
@@ -0,0 +1,163 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 12345, -80, 2560, -19900, 12345, -80, 2560, -19900, 12345, -80,
+           2560, -19900, 12345, -80, 2560, -19900);
+  VLOAD_16(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  VCLEAR(v1);
+  asm volatile("vmslt.vv v1, v2, v3");
+  VSET(2, e8, m1);
+  VCMP_U8(1, v1, 0xAA, 0xAA);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 12345, -80, 2560, -19900, 12345, -80, 2560, -19900, 12345, -80,
+           2560, -19900, 12345, -80, 2560, -19900);
+  VLOAD_32(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  VCLEAR(v1);
+  asm volatile("vmslt.vv v1, v2, v3");
+  VSET(2, e8, m1);
+  VCMP_U8(2, v1, 0xAA, 0xAA);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 12345, -80, 2560, -19900, 12345, -80, 2560, -19900, 12345, -80,
+           2560, -19900, 12345, -80, 2560, -19900);
+  VLOAD_64(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  VCLEAR(v1);
+  asm volatile("vmslt.vv v1, v2, v3");
+  VSET(2, e8, m1);
+  VCMP_U8(3, v1, 0xAA, 0xAA);
+};
+
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 12345, -80, 2560, -19900, 12345, -80, 2560, -19900, 12345, -80,
+           2560, -19900, 12345, -80, 2560, -19900);
+  VLOAD_16(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmslt.vv v1, v2, v3, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(4, v1, 0x88, 0x88);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 12345, -80, 2560, -19900, 12345, -80, 2560, -19900, 12345, -80,
+           2560, -19900, 12345, -80, 2560, -19900);
+  VLOAD_32(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmslt.vv v1, v2, v3, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(5, v1, 0x88, 0x88);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 12345, -80, 2560, -19900, 12345, -80, 2560, -19900, 12345, -80,
+           2560, -19900, 12345, -80, 2560, -19900);
+  VLOAD_64(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmslt.vv v1, v2, v3, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(6, v1, 0x88, 0x88);
+};
+
+void TEST_CASE3(void) {
+  const uint64_t scalar = 40;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 123, -8, -25, 99, 123, -8, -25, 99, 123, -8, -25, 99, 123, -8,
+          -25, 99);
+  VCLEAR(v1);
+  asm volatile("vmslt.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(7, v1, 0x66, 0x66);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 12345, -8, -25, 199, 12345, -8, -25, 199, 12345, -8, -25, 199,
+           12345, -8, -25, 199);
+  VCLEAR(v1);
+  asm volatile("vmslt.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(8, v1, 0x66, 0x66);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 12345, -8, -25, 199, 12345, -8, -25, 199, 12345, -8, -25, 199,
+           12345, -8, -25, 199);
+  VCLEAR(v1);
+  asm volatile("vmslt.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(9, v1, 0x66, 0x66);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 12345, -8, -25, 199, 12345, -8, -25, 199, 12345, -8, -25, 199,
+           12345, -8, -25, 199);
+  VCLEAR(v1);
+  asm volatile("vmslt.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(10, v1, 0x66, 0x66);
+};
+
+void TEST_CASE4(void) {
+  const uint64_t scalar = 40;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 123, -8, -25, 99, 123, -8, -25, 99, 123, -8, -25, 99, 123, -8,
+          -25, 99);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmslt.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(11, v1, 0x44, 0x44);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 12345, -8, -25, 199, 12345, -8, -25, 199, 12345, -8, -25, 199,
+           12345, -8, -25, 199);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmslt.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(12, v1, 0x44, 0x44);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 12345, -8, -25, 199, 12345, -8, -25, 199, 12345, -8, -25, 199,
+           12345, -8, -25, 199);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmslt.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(13, v1, 0x44, 0x44);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 12345, -8, -25, 199, 12345, -8, -25, 199, 12345, -8, -25, 199,
+           12345, -8, -25, 199);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmslt.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(14, v1, 0x44, 0x44);
+};
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vmsltu.c b/apps/riscv-tests/isa/rv64uv/vmsltu.c
new file mode 100644
index 0000000..4b70a26
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vmsltu.c
@@ -0,0 +1,163 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 12345, 80, 2560, 19900, 12345, 80, 2560, 19900, 12345, 80, 2560,
+           19900, 12345, 80, 2560, 19900);
+  VLOAD_16(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  VCLEAR(v1);
+  asm volatile("vmsltu.vv v1, v2, v3");
+  VSET(2, e8, m1);
+  VCMP_U8(1, v1, 0xAA, 0xAA);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 12345, 80, 2560, 19900, 12345, 80, 2560, 19900, 12345, 80, 2560,
+           19900, 12345, 80, 2560, 19900);
+  VLOAD_32(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  VCLEAR(v1);
+  asm volatile("vmsltu.vv v1, v2, v3");
+  VSET(2, e8, m1);
+  VCMP_U8(2, v1, 0xAA, 0xAA);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 12345, 80, 2560, 19900, 12345, 80, 2560, 19900, 12345, 80, 2560,
+           19900, 12345, 80, 2560, 19900);
+  VLOAD_64(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  VCLEAR(v1);
+  asm volatile("vmsltu.vv v1, v2, v3");
+  VSET(2, e8, m1);
+  VCMP_U8(3, v1, 0xAA, 0xAA);
+};
+
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 12345, 80, 2560, 19900, 12345, 80, 2560, 19900, 12345, 80, 2560,
+           19900, 12345, 80, 2560, 19900);
+  VLOAD_16(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmsltu.vv v1, v2, v3, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(4, v1, 0x88, 0x88);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 12345, 80, 2560, 19900, 12345, 80, 2560, 19900, 12345, 80, 2560,
+           19900, 12345, 80, 2560, 19900);
+  VLOAD_32(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmsltu.vv v1, v2, v3, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(5, v1, 0x88, 0x88);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 12345, 80, 2560, 19900, 12345, 80, 2560, 19900, 12345, 80, 2560,
+           19900, 12345, 80, 2560, 19900);
+  VLOAD_64(v3, 50, 7000, 400, 19901, 50, 7000, 400, 19901, 50, 7000, 400, 19901,
+           50, 7000, 400, 19901);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmsltu.vv v1, v2, v3, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(6, v1, 0x88, 0x88);
+};
+
+void TEST_CASE3(void) {
+  const uint64_t scalar = 40;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 123, 8, 25, 199, 123, 8, 25, 199, 123, 8, 25, 199, 123, 8, 25,
+          199);
+  VCLEAR(v1);
+  asm volatile("vmsltu.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(7, v1, 0x66, 0x66);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345,
+           8, 25, 199);
+  VCLEAR(v1);
+  asm volatile("vmsltu.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(8, v1, 0x66, 0x66);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345,
+           8, 25, 199);
+  VCLEAR(v1);
+  asm volatile("vmsltu.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(9, v1, 0x66, 0x66);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345,
+           8, 25, 199);
+  VCLEAR(v1);
+  asm volatile("vmsltu.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(10, v1, 0x66, 0x66);
+};
+
+void TEST_CASE4(void) {
+  const uint64_t scalar = 40;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 123, 8, 25, 199, 123, 8, 25, 199, 123, 8, 25, 199, 123, 8, 25,
+          199);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmsltu.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(11, v1, 0x44, 0x44);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345,
+           8, 25, 199);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmsltu.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(12, v1, 0x44, 0x44);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345,
+           8, 25, 199);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmsltu.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(13, v1, 0x44, 0x44);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345, 8, 25, 199, 12345,
+           8, 25, 199);
+  VLOAD_8(v0, 0xCC, 0xCC);
+  VCLEAR(v1);
+  asm volatile("vmsltu.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(14, v1, 0x44, 0x44);
+};
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vmsne.c b/apps/riscv-tests/isa/rv64uv/vmsne.c
new file mode 100644
index 0000000..814e19d
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vmsne.c
@@ -0,0 +1,306 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xff, 0x00, 0xf0, 0x0f, 0xff, 0x00, 0xf0, 0x0f, 0xff, 0x00, 0xf0,
+          0x0f, 0xff, 0x00, 0xf0, 0x0f);
+  VLOAD_8(v3, 0xf2, 0x01, 0xf0, 0x0f, 0xf2, 0x01, 0xf0, 0x0f, 0xf2, 0x01, 0xf0,
+          0x0f, 0xf2, 0x01, 0xf0, 0x0f);
+  VCLEAR(v1);
+  asm volatile("vmsne.vv v1, v2, v3");
+  VSET(2, e8, m1);
+  VCMP_U8(1, v1, 0x33, 0x33);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0xffff, 0x0000, 0xf0f0, 0x0f0f, 0xffff, 0x0000, 0xf0f0, 0x0f0f,
+           0xffff, 0x0000, 0xf0f0, 0x0f0f, 0xffff, 0x0000, 0xf0f0, 0x0f0f);
+  VLOAD_16(v3, 0xf2ff, 0x0100, 0xf0f0, 0x0f0f, 0xf2ff, 0x0100, 0xf0f0, 0x0f0f,
+           0xf2ff, 0x0100, 0xf0f0, 0x0f0f, 0xf2ff, 0x0100, 0xf0f0, 0x0f0f);
+  VCLEAR(v1);
+  asm volatile("vmsne.vv v1, v2, v3");
+  VSET(2, e8, m1);
+  VCMP_U8(2, v1, 0x33, 0x33);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0xffffffff, 0x00000000, 0xf0f0f0f0, 0x0f0f0f0f, 0xffffffff,
+           0x00000000, 0xf0f0f0f0, 0x0f0f0f0f, 0xffffffff, 0x00000000,
+           0xf0f0f0f0, 0x0f0f0f0f, 0xffffffff, 0x00000000, 0xf0f0f0f0,
+           0x0f0f0f0f);
+  VLOAD_32(v3, 0xfff2ffff, 0x01000000, 0xf0f0f0f0, 0x0f0f0f0f, 0xfff2ffff,
+           0x01000000, 0xf0f0f0f0, 0x0f0f0f0f, 0xfff2ffff, 0x01000000,
+           0xf0f0f0f0, 0x0f0f0f0f, 0xfff2ffff, 0x01000000, 0xf0f0f0f0,
+           0x0f0f0f0f);
+  VCLEAR(v1);
+  asm volatile("vmsne.vv v1, v2, v3");
+  VSET(2, e8, m1);
+  VCMP_U8(3, v1, 0x33, 0x33);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0xffffffffffffffff, 0x0000000000000000, 0xf0f0f0f0f0f0f0f0,
+           0x0f0f0f0f0f0f0f0f, 0xffffffffffffffff, 0x0000000000000000,
+           0xf0f0f0f0f0f0f0f0, 0x0f0f0f0f0f0f0f0f, 0xffffffffffffffff,
+           0x0000000000000000, 0xf0f0f0f0f0f0f0f0, 0x0f0f0f0f0f0f0f0f,
+           0xffffffffffffffff, 0x0000000000000000, 0xf0f0f0f0f0f0f0f0,
+           0x0f0f0f0f0f0f0f0f);
+  VLOAD_64(v3, 0xfff2ffffffffffff, 0x0100000000000000, 0xf0f0f0f0f0f0f0f0,
+           0x0f0f0f0f0f0f0f0f, 0xfff2ffffffffffff, 0x0100000000000000,
+           0xf0f0f0f0f0f0f0f0, 0x0f0f0f0f0f0f0f0f, 0xfff2ffffffffffff,
+           0x0100000000000000, 0xf0f0f0f0f0f0f0f0, 0x0f0f0f0f0f0f0f0f,
+           0xfff2ffffffffffff, 0x0100000000000000, 0xf0f0f0f0f0f0f0f0,
+           0x0f0f0f0f0f0f0f0f);
+  VCLEAR(v1);
+  asm volatile("vmsne.vv v1, v2, v3");
+  VSET(2, e8, m1);
+  VCMP_U8(4, v1, 0x33, 0x33);
+};
+
+void TEST_CASE2(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xff, 0x00, 0xf0, 0x0f, 0xff, 0x00, 0xf0, 0x0f, 0xff, 0x00, 0xf0,
+          0x0f, 0xff, 0x00, 0xf0, 0x0f);
+  VLOAD_8(v3, 0xf2, 0x01, 0xf0, 0x0f, 0xf2, 0x01, 0xf0, 0x0f, 0xf2, 0x01, 0xf0,
+          0x0f, 0xf2, 0x01, 0xf0, 0x0f);
+  VLOAD_8(v0, 0xaa, 0xaa);
+  VCLEAR(v1);
+  asm volatile("vmsne.vv v1, v2, v3, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(5, v1, 0x22, 0x22);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0xffff, 0x0000, 0xf0f0, 0x0f0f, 0xffff, 0x0000, 0xf0f0, 0x0f0f,
+           0xffff, 0x0000, 0xf0f0, 0x0f0f, 0xffff, 0x0000, 0xf0f0, 0x0f0f);
+  VLOAD_16(v3, 0xf2ff, 0x0100, 0xf0f0, 0x0f0f, 0xf2ff, 0x0100, 0xf0f0, 0x0f0f,
+           0xf2ff, 0x0100, 0xf0f0, 0x0f0f, 0xf2ff, 0x0100, 0xf0f0, 0x0f0f);
+  VLOAD_8(v0, 0xaa, 0xaa);
+  VCLEAR(v1);
+  asm volatile("vmsne.vv v1, v2, v3, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(6, v1, 0x22, 0x22);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0xffffffff, 0x00000000, 0xf0f0f0f0, 0x0f0f0f0f, 0xffffffff,
+           0x00000000, 0xf0f0f0f0, 0x0f0f0f0f, 0xffffffff, 0x00000000,
+           0xf0f0f0f0, 0x0f0f0f0f, 0xffffffff, 0x00000000, 0xf0f0f0f0,
+           0x0f0f0f0f);
+  VLOAD_32(v3, 0xfff2ffff, 0x01000000, 0xf0f0f0f0, 0x0f0f0f0f, 0xfff2ffff,
+           0x01000000, 0xf0f0f0f0, 0x0f0f0f0f, 0xfff2ffff, 0x01000000,
+           0xf0f0f0f0, 0x0f0f0f0f, 0xfff2ffff, 0x01000000, 0xf0f0f0f0,
+           0x0f0f0f0f);
+  VLOAD_8(v0, 0xaa, 0xaa);
+  VCLEAR(v1);
+  asm volatile("vmsne.vv v1, v2, v3, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(7, v1, 0x22, 0x22);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0xffffffffffffffff, 0x0000000000000000, 0xf0f0f0f0f0f0f0f0,
+           0x0f0f0f0f0f0f0f0f, 0xffffffffffffffff, 0x0000000000000000,
+           0xf0f0f0f0f0f0f0f0, 0x0f0f0f0f0f0f0f0f, 0xffffffffffffffff,
+           0x0000000000000000, 0xf0f0f0f0f0f0f0f0, 0x0f0f0f0f0f0f0f0f,
+           0xffffffffffffffff, 0x0000000000000000, 0xf0f0f0f0f0f0f0f0,
+           0x0f0f0f0f0f0f0f0f);
+  VLOAD_64(v3, 0xfff2ffffffffffff, 0x0100000000000000, 0xf0f0f0f0f0f0f0f0,
+           0x0f0f0f0f0f0f0f0f, 0xfff2ffffffffffff, 0x0100000000000000,
+           0xf0f0f0f0f0f0f0f0, 0x0f0f0f0f0f0f0f0f, 0xfff2ffffffffffff,
+           0x0100000000000000, 0xf0f0f0f0f0f0f0f0, 0x0f0f0f0f0f0f0f0f,
+           0xfff2ffffffffffff, 0x0100000000000000, 0xf0f0f0f0f0f0f0f0,
+           0x0f0f0f0f0f0f0f0f);
+  VLOAD_8(v0, 0xaa, 0xaa);
+  VCLEAR(v1);
+  asm volatile("vmsne.vv v1, v2, v3, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(8, v1, 0x22, 0x22);
+};
+
+void TEST_CASE3(void) {
+  const uint64_t scalar = 0x00000000ffffffff;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xff, 0x00, 0xf0, 0x0f, 0xff, 0x00, 0xf0, 0x0f, 0xff, 0x00, 0xf0,
+          0x0f, 0xff, 0x00, 0xf0, 0x0f);
+  VCLEAR(v1);
+  asm volatile("vmsne.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(9, v1, 0xee, 0xee);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0xffff, 0x0000, 0xf0f0, 0x0f0f, 0xffff, 0x0000, 0xf0f0, 0x0f0f,
+           0xffff, 0x0000, 0xf0f0, 0x0f0f, 0xffff, 0x0000, 0xf0f0, 0x0f0f);
+  VCLEAR(v1);
+  asm volatile("vmsne.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(10, v1, 0xee, 0xee);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0xffffffff, 0x00000000, 0xf0f0f0f0, 0x0f0f0f0f, 0xffffffff,
+           0x00000000, 0xf0f0f0f0, 0x0f0f0f0f, 0xffffffff, 0x00000000,
+           0xf0f0f0f0, 0x0f0f0f0f, 0xffffffff, 0x00000000, 0xf0f0f0f0,
+           0x0f0f0f0f);
+  VCLEAR(v1);
+  asm volatile("vmsne.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(11, v1, 0xee, 0xee);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0xffffffffffffffff, 0x0000000000000000, 0xf0f0f0f0f0f0f0f0,
+           0x0f0f0f0f0f0f0f0f, 0xffffffffffffffff, 0x0000000000000000,
+           0xf0f0f0f0f0f0f0f0, 0x0f0f0f0f0f0f0f0f, 0xffffffffffffffff,
+           0x0000000000000000, 0xf0f0f0f0f0f0f0f0, 0x0f0f0f0f0f0f0f0f,
+           0xffffffffffffffff, 0x0000000000000000, 0xf0f0f0f0f0f0f0f0,
+           0x0f0f0f0f0f0f0f0f);
+  VCLEAR(v1);
+  asm volatile("vmsne.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(12, v1, 0xff, 0xff);
+};
+
+void TEST_CASE4(void) {
+  const uint64_t scalar = 0x00000000ffffffff;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xff, 0x00, 0xf0, 0x0f, 0xff, 0x00, 0xf0, 0x0f, 0xff, 0x00, 0xf0,
+          0x0f, 0xff, 0x00, 0xf0, 0x0f);
+  VLOAD_8(v0, 0x10, 0x10);
+  VCLEAR(v1);
+  asm volatile("vmsne.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(13, v1, 0x00, 0x00);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0xffff, 0x0000, 0xf0f0, 0x0f0f, 0xffff, 0x0000, 0xf0f0, 0x0f0f,
+           0xffff, 0x0000, 0xf0f0, 0x0f0f, 0xffff, 0x0000, 0xf0f0, 0x0f0f);
+  VLOAD_8(v0, 0x10, 0x10);
+  VCLEAR(v1);
+  asm volatile("vmsne.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(14, v1, 0x00, 0x00);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0xffffffff, 0x00000000, 0xf0f0f0f0, 0x0f0f0f0f, 0xffffffff,
+           0x00000000, 0xf0f0f0f0, 0x0f0f0f0f, 0xffffffff, 0x00000000,
+           0xf0f0f0f0, 0x0f0f0f0f, 0xffffffff, 0x00000000, 0xf0f0f0f0,
+           0x0f0f0f0f);
+  VLOAD_8(v0, 0x10, 0x10);
+  VCLEAR(v1);
+  asm volatile("vmsne.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(15, v1, 0x00, 0x00);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0xffffffffffffffff, 0x0000000000000000, 0xf0f0f0f0f0f0f0f0,
+           0x0f0f0f0f0f0f0f0f, 0xffffffffffffffff, 0x0000000000000000,
+           0xf0f0f0f0f0f0f0f0, 0x0f0f0f0f0f0f0f0f, 0xffffffffffffffff,
+           0x0000000000000000, 0xf0f0f0f0f0f0f0f0, 0x0f0f0f0f0f0f0f0f,
+           0xffffffffffffffff, 0x0000000000000000, 0xf0f0f0f0f0f0f0f0,
+           0x0f0f0f0f0f0f0f0f);
+  VLOAD_8(v0, 0x10, 0x10);
+  VCLEAR(v1);
+  asm volatile("vmsne.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(2, e8, m1);
+  VCMP_U8(16, v1, 0x10, 0x10);
+};
+
+void TEST_CASE5(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x0f, 0x00, 0xf0, 0x0f, 0x0f, 0x00, 0xf0, 0x0f, 0x0f, 0x00, 0xf0,
+          0x0f, 0x0f, 0x00, 0xf0, 0x0f);
+  VCLEAR(v1);
+  asm volatile("vmsne.vi v1, v2, 15");
+  VSET(2, e8, m1);
+  VCMP_U8(17, v1, 0x66, 0x66);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x000f, 0x0000, 0xf0f0, 0x0f0f, 0x000f, 0x0000, 0xf0f0, 0x0f0f,
+           0x000f, 0x0000, 0xf0f0, 0x0f0f, 0x000f, 0x0000, 0xf0f0, 0x0f0f);
+  VCLEAR(v1);
+  asm volatile("vmsne.vi v1, v2, 15");
+  VSET(2, e8, m1);
+  VCMP_U8(18, v1, 0xee, 0xee);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x0000000f, 0x00000000, 0xf0f0f0f0, 0x0f0f0f0f, 0x0000000f,
+           0x00000000, 0xf0f0f0f0, 0x0f0f0f0f, 0x0000000f, 0x00000000,
+           0xf0f0f0f0, 0x0f0f0f0f, 0x0000000f, 0x00000000, 0xf0f0f0f0,
+           0x0f0f0f0f);
+  VCLEAR(v1);
+  asm volatile("vmsne.vi v1, v2, 15");
+  VSET(2, e8, m1);
+  VCMP_U8(19, v1, 0xee, 0xee);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x000000000000000f, 0x0000000000000000, 0xf0f0f0f0f0f0f0f0,
+           0x0f0f0f0f0f0f0f0f, 0x000000000000000f, 0x0000000000000000,
+           0xf0f0f0f0f0f0f0f0, 0x0f0f0f0f0f0f0f0f, 0x000000000000000f,
+           0x0000000000000000, 0xf0f0f0f0f0f0f0f0, 0x0f0f0f0f0f0f0f0f,
+           0x000000000000000f, 0x0000000000000000, 0xf0f0f0f0f0f0f0f0,
+           0x0f0f0f0f0f0f0f0f);
+  VCLEAR(v1);
+  asm volatile("vmsne.vi v1, v2, 15");
+  VSET(2, e8, m1);
+  VCMP_U8(20, v1, 0xee, 0xee);
+};
+
+void TEST_CASE6(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x0f, 0x00, 0xf0, 0x0f, 0x0f, 0x00, 0xf0, 0x0f, 0x0f, 0x00, 0xf0,
+          0x0f, 0x0f, 0x00, 0xf0, 0x0f);
+  VLOAD_8(v0, 0x10, 0x10);
+  VCLEAR(v1);
+  asm volatile("vmsne.vi v1, v2, 15, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(21, v1, 0x00, 0x00);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x000f, 0x0000, 0xf0f0, 0x0f0f, 0x000f, 0x0000, 0xf0f0, 0x0f0f,
+           0x000f, 0x0000, 0xf0f0, 0x0f0f, 0x000f, 0x0000, 0xf0f0, 0x0f0f);
+  VLOAD_8(v0, 0x10, 0x10);
+  VCLEAR(v1);
+  asm volatile("vmsne.vi v1, v2, 15, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(22, v1, 0x00, 0x00);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x0000000f, 0x00000000, 0xf0f0f0f0, 0x0f0f0f0f, 0x0000000f,
+           0x00000000, 0xf0f0f0f0, 0x0f0f0f0f, 0x0000000f, 0x00000000,
+           0xf0f0f0f0, 0x0f0f0f0f, 0x0000000f, 0x00000000, 0xf0f0f0f0,
+           0x0f0f0f0f);
+  VLOAD_8(v0, 0x10, 0x10);
+  VCLEAR(v1);
+  asm volatile("vmsne.vi v1, v2, 15, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(23, v1, 0x00, 0x00);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x000000000000000f, 0x0000000000000000, 0xf0f0f0f0f0f0f0f0,
+           0x0f0f0f0f0f0f0f0f, 0x000000000000000f, 0x0000000000000000,
+           0xf0f0f0f0f0f0f0f0, 0x0f0f0f0f0f0f0f0f, 0x000000000000000f,
+           0x0000000000000000, 0xf0f0f0f0f0f0f0f0, 0x0f0f0f0f0f0f0f0f,
+           0x000000000000000f, 0x0000000000000000, 0xf0f0f0f0f0f0f0f0,
+           0x0f0f0f0f0f0f0f0f);
+  VLOAD_8(v0, 0x10, 0x10);
+  VCLEAR(v1);
+  asm volatile("vmsne.vi v1, v2, 15, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(24, v1, 0x00, 0x00);
+};
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+  TEST_CASE6();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vmsof.c b/apps/riscv-tests/isa/rv64uv/vmsof.c
new file mode 100644
index 0000000..24db475
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vmsof.c
@@ -0,0 +1,43 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1() {
+  VSET(16, e8, m1);
+  VLOAD_8(v3, 8, 0, 0, 0, 0, 0, 0, 0);
+  asm volatile("vmsof.m v2, v3");
+  VSET(2, e8, m1);
+  VCMP_U8(1, v2, 8, 0);
+}
+
+void TEST_CASE2() {
+  VSET(16, e8, m1);
+  VLOAD_8(v3, 0, 0, 0, 1, 0, 0, 0, 0);
+  VLOAD_8(v0, 3, 0, 0, 0, 0, 0, 0, 0);
+  VCLEAR(v2);
+  asm volatile("vmsof.m v2, v3, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(2, v2, 0, 0);
+
+  VSET(16, e8, m1);
+  VLOAD_8(v3, 0x38, 0, 0, 0, 0, 0, 0, 0);
+  VLOAD_8(v0, 0xf7, 0, 0, 0, 0, 0, 0, 0);
+  VCLEAR(v2);
+  asm volatile("vmsof.m v2, v3, v0.t");
+  VSET(2, e8, m1);
+  VCMP_U8(3, v2, 0x10, 0);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+  enable_fp();
+  TEST_CASE1();
+  TEST_CASE2();
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vmul.c b/apps/riscv-tests/isa/rv64uv/vmul.c
new file mode 100644
index 0000000..58ef107
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vmul.c
@@ -0,0 +1,232 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xb3, 0x5d, 0x3d, 0xa4, 0xbf, 0xc7, 0x6b, 0x95, 0xf9, 0x64, 0x52,
+          0x57, 0xbc, 0x1f, 0xd5, 0x13);
+  VLOAD_8(v3, 0x46, 0x37, 0xf5, 0x2b, 0x55, 0x05, 0xcb, 0x76, 0x31, 0x30, 0x78,
+          0xb3, 0x6a, 0xae, 0x5a, 0xe1);
+  asm volatile("vmul.vv v1, v2, v3");
+  VCMP_I8(1, v1, 0xf2, 0xfb, 0x61, 0x8c, 0x6b, 0xe3, 0xd9, 0xae, 0xa9, 0xc0,
+          0x70, 0xd5, 0xd8, 0x12, 0xe2, 0xb3);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x8132, 0x94b5, 0x245c, 0xd15d, 0xbfca, 0x18b6, 0xd5ba, 0x9299,
+           0xccbd, 0x9ad4, 0xce46, 0xfbba, 0x10cc, 0xc463, 0x5298, 0x7b3e);
+  VLOAD_16(v3, 0xede6, 0x010b, 0xa570, 0x21c5, 0xfe5a, 0x5386, 0x16c9, 0x45fb,
+           0x1439, 0x436f, 0x6f56, 0x90f7, 0x77c0, 0x0751, 0x64c3, 0x36e8);
+  asm volatile("vmul.vv v1, v2, v3");
+  VCMP_I16(2, v1, 0x5cec, 0x18c7, 0x3440, 0x1991, 0xd904, 0xf144, 0xcb0a,
+           0xf903, 0x5a15, 0x9dec, 0xa584, 0x8076, 0x6d00, 0xd853, 0x49c8,
+           0xc430);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x9c2bdc58, 0xe3995899, 0xbbbc0eda, 0x0729ff92, 0xa757a2c5,
+           0xd5f3a23e, 0x9a295390, 0xb2367b2e, 0xfee5b6a2, 0x07cb59c1,
+           0x6bf5cf9a, 0x7d75506b, 0x013c1e90, 0x600f9ca8, 0x6d4d0522,
+           0x0a225ff0);
+  VLOAD_32(v3, 0xc51e02f8, 0xae06b334, 0x397b1ec7, 0xc46f34fe, 0x4f9db2ab,
+           0x957c2534, 0x70f8e127, 0xa79ebcec, 0x0a542044, 0x20e6ac3e,
+           0xd61caed7, 0x6f4e7820, 0x27c56901, 0x0aaf1d61, 0xa95c6f5c,
+           0x5b7aedf3);
+  asm volatile("vmul.vv v1, v2, v3");
+  VCMP_I32(3, v1, 0x2c862540, 0x85aefa14, 0xa5ab1776, 0x3be33adc, 0x5487b397,
+           0x57f7ea98, 0xc23d4af0, 0x55135668, 0xad00c308, 0x46f368be,
+           0x2f640656, 0x91f63560, 0x1e952e90, 0xd18163a8, 0xf71f9638,
+           0x79d240d0);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x077de9270ce00632, 0x2dadf4e020f3d47a, 0xb54ca84f9fe0573b,
+           0x7be639dfdb02db6f, 0x61bb44569da93eff, 0xcd7f973ce822182b,
+           0x5434a22e7432397c, 0xcaadfd89d8dd1ad5, 0x5474c56d9089d672,
+           0x700e415c07b99bf9, 0xb89d409d4323a9c8, 0x68ccc7411db0ab09,
+           0xdf4fe3fa4e113e98, 0xa98a2e2575b04c41, 0x26ddf248ccb4a7aa,
+           0xdda1822d4972ee47);
+  VLOAD_64(v3, 0xcd2888c8bb07b736, 0xf20013627ac47d4f, 0xc05dbcd989ef329c,
+           0xc272db2ebcf7cfad, 0x8869302db041176d, 0xd3d90968a9ee01c2,
+           0x9cdb9f91a3381f51, 0x99ad38b70907ee8d, 0xf7d629b266c67cf1,
+           0x706f9b996cdd60f2, 0x4caa2335622bd6a0, 0x94171c9dfbbb186f,
+           0x7b6e42290f54ecc6, 0xa545b8670143bfbc, 0x9f430bf94b2805c9,
+           0xb45030fc2b4cef12);
+  asm volatile("vmul.vv v1, v2, v3");
+  VCMP_I64(4, v1, 0x90d27e278d0d0c8c, 0x5ea9d3e60b6623a6, 0x6823b3e240d3adf4,
+           0xc0dcea378c760b03, 0x17692726a477bb93, 0x784c7f2ee6e87b96,
+           0xd1aae9975ffa343c, 0xfdcd46ca398ccd51, 0x405f01791dce1952,
+           0x16063fbe99e7d162, 0xc9d244cddacf4d00, 0x22024848323600e7,
+           0xb6dfea3bb8ea8990, 0x566db9e82c5f7ebc, 0x5fc0f2db41adf67a,
+           0xdaab68ca209d09fe);
+};
+
+void TEST_CASE2(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xb3, 0x5d, 0x3d, 0xa4, 0xbf, 0xc7, 0x6b, 0x95, 0xf9, 0x64, 0x52,
+          0x57, 0xbc, 0x1f, 0xd5, 0x13);
+  VLOAD_8(v3, 0x46, 0x37, 0xf5, 0x2b, 0x55, 0x05, 0xcb, 0x76, 0x31, 0x30, 0x78,
+          0xb3, 0x6a, 0xae, 0x5a, 0xe1);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmul.vv v1, v2, v3, v0.t");
+  VCMP_I8(5, v1, 0, 0xfb, 0, 0x8c, 0, 0xe3, 0, 0xae, 0, 0xc0, 0, 0xd5, 0, 0x12,
+          0, 0xb3);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x8132, 0x94b5, 0x245c, 0xd15d, 0xbfca, 0x18b6, 0xd5ba, 0x9299,
+           0xccbd, 0x9ad4, 0xce46, 0xfbba, 0x10cc, 0xc463, 0x5298, 0x7b3e);
+  VLOAD_16(v3, 0xede6, 0x010b, 0xa570, 0x21c5, 0xfe5a, 0x5386, 0x16c9, 0x45fb,
+           0x1439, 0x436f, 0x6f56, 0x90f7, 0x77c0, 0x0751, 0x64c3, 0x36e8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmul.vv v1, v2, v3, v0.t");
+  VCMP_I16(6, v1, 0, 0x18c7, 0, 0x1991, 0, 0xf144, 0, 0xf903, 0, 0x9dec, 0,
+           0x8076, 0, 0xd853, 0, 0xc430);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x9c2bdc58, 0xe3995899, 0xbbbc0eda, 0x0729ff92, 0xa757a2c5,
+           0xd5f3a23e, 0x9a295390, 0xb2367b2e, 0xfee5b6a2, 0x07cb59c1,
+           0x6bf5cf9a, 0x7d75506b, 0x013c1e90, 0x600f9ca8, 0x6d4d0522,
+           0x0a225ff0);
+  VLOAD_32(v3, 0xc51e02f8, 0xae06b334, 0x397b1ec7, 0xc46f34fe, 0x4f9db2ab,
+           0x957c2534, 0x70f8e127, 0xa79ebcec, 0x0a542044, 0x20e6ac3e,
+           0xd61caed7, 0x6f4e7820, 0x27c56901, 0x0aaf1d61, 0xa95c6f5c,
+           0x5b7aedf3);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmul.vv v1, v2, v3, v0.t");
+  VCMP_I32(7, v1, 0, 0x85aefa14, 0, 0x3be33adc, 0, 0x57f7ea98, 0, 0x55135668, 0,
+           0x46f368be, 0, 0x91f63560, 0, 0xd18163a8, 0, 0x79d240d0);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x077de9270ce00632, 0x2dadf4e020f3d47a, 0xb54ca84f9fe0573b,
+           0x7be639dfdb02db6f, 0x61bb44569da93eff, 0xcd7f973ce822182b,
+           0x5434a22e7432397c, 0xcaadfd89d8dd1ad5, 0x5474c56d9089d672,
+           0x700e415c07b99bf9, 0xb89d409d4323a9c8, 0x68ccc7411db0ab09,
+           0xdf4fe3fa4e113e98, 0xa98a2e2575b04c41, 0x26ddf248ccb4a7aa,
+           0xdda1822d4972ee47);
+  VLOAD_64(v3, 0xcd2888c8bb07b736, 0xf20013627ac47d4f, 0xc05dbcd989ef329c,
+           0xc272db2ebcf7cfad, 0x8869302db041176d, 0xd3d90968a9ee01c2,
+           0x9cdb9f91a3381f51, 0x99ad38b70907ee8d, 0xf7d629b266c67cf1,
+           0x706f9b996cdd60f2, 0x4caa2335622bd6a0, 0x94171c9dfbbb186f,
+           0x7b6e42290f54ecc6, 0xa545b8670143bfbc, 0x9f430bf94b2805c9,
+           0xb45030fc2b4cef12);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmul.vv v1, v2, v3, v0.t");
+  VCMP_I64(8, v1, 0, 0x5ea9d3e60b6623a6, 0, 0xc0dcea378c760b03, 0,
+           0x784c7f2ee6e87b96, 0, 0xfdcd46ca398ccd51, 0, 0x16063fbe99e7d162, 0,
+           0x22024848323600e7, 0, 0x566db9e82c5f7ebc, 0, 0xdaab68ca209d09fe);
+};
+
+void TEST_CASE3(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x80, 0xb2, 0xb6, 0xd7, 0x4f, 0xbe, 0xee, 0x53, 0xab, 0x57, 0xe4,
+          0x28, 0x6a, 0x91, 0x14, 0x4f);
+  int64_t scalar = 5;
+  asm volatile("vmul.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_I8(9, v1, 0x80, 0x7a, 0x8e, 0x33, 0x8b, 0xb6, 0xa6, 0x9f, 0x57, 0xb3,
+          0x74, 0xc8, 0x12, 0xd5, 0x64, 0x8b);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0xbab0, 0x83a5, 0x06b6, 0x22ba, 0x91b8, 0x7720, 0xc2c7, 0x3494,
+           0xd281, 0x6d38, 0x378d, 0xa91d, 0xd731, 0xa4c7, 0x4d8f, 0x2422);
+  scalar = -5383;
+  asm volatile("vmul.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_I16(10, v1, 0x7530, 0xdd7d, 0xe306, 0xcaea, 0xebf8, 0x1e20, 0x598f,
+           0x6bf4, 0xa979, 0x6b78, 0xea25, 0xff35, 0x18a9, 0x2b8f, 0x2617,
+           0x3912);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x8bb4a8bc, 0x9799b344, 0xcd8c1672, 0xeb2d7c0f, 0x55474d7d,
+           0x3dae9eaf, 0xc19a3519, 0x6922f03c, 0x42edfa01, 0x1f60b344,
+           0x82f31d5e, 0x0faa2e5c, 0x74e95cfa, 0x9fcdae3b, 0xe6c4e0a0,
+           0x45549cbc);
+  scalar = 6474219;
+  asm volatile("vmul.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_I32(11, v1, 0xaf4a8094, 0x77dff36c, 0x44dc1ca6, 0x16e6a8c5, 0xee2546bf,
+           0x78e111a5, 0x1fd15ef3, 0xe8a9a314, 0xfe2147eb, 0x5a8cf36c,
+           0x5536c34a, 0xbed6ca74, 0x23eca37e, 0xe2314329, 0x6857d2e0,
+           0x13b37c94);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0xc238e0a3df21299c, 0xb642655c3ab064d5, 0xd19f84bab77e5602,
+           0x4e6e3c114a19f160, 0xfd403cbcc59407a1, 0xef3e81a68ae0e48c,
+           0xd93a7b1ab54d024e, 0x5f7460aa9f4c4920, 0x4c91150cd4b54f60,
+           0x18f2a6528629633f, 0x201b8bdb3c140400, 0x6be03c1074d46ada,
+           0xcd0e6874555602d4, 0xb70264bd366ff52f, 0xc0b1fa64cec9368d,
+           0x13e86249a0235941);
+  scalar = -598189234597999223;
+  asm volatile("vmul.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_I64(12, v1, 0x61ead1213f09307c, 0x7d03f4c84c5e86fd, 0x4aa0acc4e01fa112,
+           0x77bc957fdeec0c60, 0x762b14c112e60229, 0xbac65562e2366aec,
+           0xcc243dd1e80ab1be, 0xa871135122a1c220, 0x3d0db00992575a60,
+           0x8b07763affcd8fb7, 0xc8377fc475ea2400, 0xd8827c839711c0aa,
+           0x5a5779ec4f334774, 0x243fd844e74ed927, 0x49204b7602871a75,
+           0x33ae5ea6d335d0c9);
+};
+
+void TEST_CASE4(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x80, 0xb2, 0xb6, 0xd7, 0x4f, 0xbe, 0xee, 0x53, 0xab, 0x57, 0xe4,
+          0x28, 0x6a, 0x91, 0x14, 0x4f);
+  int64_t scalar = 5;
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmul.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_I8(13, v1, 0, 0x7a, 0, 0x33, 0, 0xb6, 0, 0x9f, 0, 0xb3, 0, 0xc8, 0, 0xd5,
+          0, 0x8b);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0xbab0, 0x83a5, 0x06b6, 0x22ba, 0x91b8, 0x7720, 0xc2c7, 0x3494,
+           0xd281, 0x6d38, 0x378d, 0xa91d, 0xd731, 0xa4c7, 0x4d8f, 0x2422);
+  scalar = -5383;
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmul.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_I16(14, v1, 0, 0xdd7d, 0, 0xcaea, 0, 0x1e20, 0, 0x6bf4, 0, 0x6b78, 0,
+           0xff35, 0, 0x2b8f, 0, 0x3912);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x8bb4a8bc, 0x9799b344, 0xcd8c1672, 0xeb2d7c0f, 0x55474d7d,
+           0x3dae9eaf, 0xc19a3519, 0x6922f03c, 0x42edfa01, 0x1f60b344,
+           0x82f31d5e, 0x0faa2e5c, 0x74e95cfa, 0x9fcdae3b, 0xe6c4e0a0,
+           0x45549cbc);
+  scalar = 6474219;
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmul.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_I32(15, v1, 0, 0x77dff36c, 0, 0x16e6a8c5, 0, 0x78e111a5, 0, 0xe8a9a314,
+           0, 0x5a8cf36c, 0, 0xbed6ca74, 0, 0xe2314329, 0, 0x13b37c94);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0xc238e0a3df21299c, 0xb642655c3ab064d5, 0xd19f84bab77e5602,
+           0x4e6e3c114a19f160, 0xfd403cbcc59407a1, 0xef3e81a68ae0e48c,
+           0xd93a7b1ab54d024e, 0x5f7460aa9f4c4920, 0x4c91150cd4b54f60,
+           0x18f2a6528629633f, 0x201b8bdb3c140400, 0x6be03c1074d46ada,
+           0xcd0e6874555602d4, 0xb70264bd366ff52f, 0xc0b1fa64cec9368d,
+           0x13e86249a0235941);
+  scalar = -598189234597999223;
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmul.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_I64(16, v1, 0, 0x7d03f4c84c5e86fd, 0, 0x77bc957fdeec0c60, 0,
+           0xbac65562e2366aec, 0, 0xa871135122a1c220, 0, 0x8b07763affcd8fb7, 0,
+           0xd8827c839711c0aa, 0, 0x243fd844e74ed927, 0, 0x33ae5ea6d335d0c9);
+};
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vmulh.c b/apps/riscv-tests/isa/rv64uv/vmulh.c
new file mode 100644
index 0000000..035111b
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vmulh.c
@@ -0,0 +1,232 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xc2, 0xf6, 0xad, 0x0f, 0xc6, 0xeb, 0xca, 0xf3, 0xf3, 0xd9, 0xf4,
+          0xf6, 0x27, 0x57, 0x4f, 0xef);
+  VLOAD_8(v3, 0xf9, 0x0c, 0xa8, 0x05, 0x23, 0xff, 0x48, 0x74, 0xd4, 0x6b, 0x5b,
+          0x07, 0x8b, 0x2e, 0x9e, 0x5f);
+  asm volatile("vmulh.vv v1, v2, v3");
+  VCMP_I8(1, v1, 0x01, 0xff, 0x1c, 0x00, 0xf8, 0x00, 0xf0, 0xfa, 0x02, 0xef,
+          0xfb, 0xff, 0xee, 0x0f, 0xe1, 0xf9);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x911a, 0x9f44, 0x3d2a, 0xa2a8, 0x5aae, 0x0231, 0x56fa, 0xb8b8,
+           0x55df, 0x8a78, 0x413c, 0xeb32, 0x6bc4, 0x3e47, 0x3d79, 0x2c8f);
+  VLOAD_16(v3, 0x89fd, 0x6bb7, 0x4a94, 0x770c, 0x7c87, 0x8b01, 0xbb6a, 0x900d,
+           0xb589, 0x709e, 0xc75d, 0xafa5, 0x4fd5, 0x2d77, 0x8dbf, 0x3a0a);
+  asm volatile("vmulh.vv v1, v2, v3");
+  VCMP_I16(2, v1, 0x331f, 0xd74c, 0x11d1, 0xd497, 0x2c1c, 0xfeff, 0xe8b2,
+           0x1f2b, 0xe705, 0xcc4b, 0xf191, 0x0687, 0x219b, 0x0b0f, 0xe490,
+           0x0a1a);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0xc66253f4, 0x710c314c, 0xa6fe579b, 0xa7947b70, 0xbf94259f,
+           0x211088fe, 0x64bfd390, 0x1d49c8d8, 0x7a12a08a, 0x190ee9ae,
+           0x361172f8, 0x52457515, 0x05d4b17b, 0x7bb6d43b, 0x96270cc7,
+           0x62d35f88);
+  VLOAD_32(v3, 0xd14a266e, 0xe4f43ca5, 0x1c067312, 0xa1909d51, 0x35b8d1aa,
+           0xdcd3e2ea, 0x05cec46d, 0xbe70ebd4, 0xe15e49c5, 0x81be068b,
+           0x49fd9ad8, 0x6c2a5abd, 0x26216dd6, 0x9e3188ac, 0x14af13c4,
+           0xd98c6d7f);
+  asm volatile("vmulh.vv v1, v2, v3");
+  VCMP_I32(3, v1, 0x0a83425c, 0xf40e8502, 0xf6419389, 0x209df360, 0xf27b2982,
+           0xfb750aac, 0x02491ecb, 0xf87fe57b, 0xf164b493, 0xf3a433c8,
+           0x0fa089bb, 0x22c2e9f3, 0x00de5543, 0xd0bbf2cc, 0xf772a985,
+           0xf128024f);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x9def74822cdf1a42, 0x29307e854b225449, 0x071cdf51785d150e,
+           0xe8ced2e9009d363f, 0xa88c741be4e81893, 0x4a7655ec12afe587,
+           0x50c5efa017138cb9, 0x88e076b6ef49619d, 0x5745683769adf333,
+           0x5b3b01f4b1c4fd42, 0x8a3d55e48864d144, 0x2eac97fae4174cac,
+           0xdb8804ccf6f55686, 0xf7bea87bac575241, 0x250ed7ddade1432d,
+           0x06ae542295f32453);
+  VLOAD_64(v3, 0xc5c41e47b5f3de5f, 0xa03833fb95a7e7e2, 0x74f0573dba05b058,
+           0x687968e9ba2a98ad, 0x29f4aaf3e5e4f2b6, 0x2c40a650d53f6f08,
+           0x491da2c816388b78, 0x2822d8207421ec15, 0x5dd8d394b292512a,
+           0x4169844eea56920d, 0x97183b6e1e85fd70, 0x224077bf8899614c,
+           0x3a9c0520417d4f32, 0xee47b09a33f49fca, 0x3f9f1140fbd02e0a,
+           0x6106ad88eabfc3e2);
+  asm volatile("vmulh.vv v1, v2, v3");
+  VCMP_I64(4, v1, 0x164eafe1cab0639c, 0xf096db86d4d06824, 0x033fc2aecddc0dd7,
+           0xf68905ef31703000, 0xf1aaea11162383ae, 0x0cdf24ba4cf3be38,
+           0x1711cb1d2f008de9, 0xed52dbcaa3de5ca2, 0x1ffe218cf60b6bf9,
+           0x174f95d97aff7bf9, 0x3041b22ecc97909a, 0x063ead2a7756c9da,
+           0xf7a6973e6c9e5ce6, 0x0092485623082173, 0x0935add704f8cec8,
+           0x02883a7e75391040);
+};
+
+void TEST_CASE2(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xc2, 0xf6, 0xad, 0x0f, 0xc6, 0xeb, 0xca, 0xf3, 0xf3, 0xd9, 0xf4,
+          0xf6, 0x27, 0x57, 0x4f, 0xef);
+  VLOAD_8(v3, 0xf9, 0x0c, 0xa8, 0x05, 0x23, 0xff, 0x48, 0x74, 0xd4, 0x6b, 0x5b,
+          0x07, 0x8b, 0x2e, 0x9e, 0x5f);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmulh.vv v1, v2, v3, v0.t");
+  VCMP_I8(5, v1, 0, 0xff, 0, 0x00, 0, 0x00, 0, 0xfa, 0, 0xef, 0, 0xff, 0, 0x0f,
+          0, 0xf9);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x911a, 0x9f44, 0x3d2a, 0xa2a8, 0x5aae, 0x0231, 0x56fa, 0xb8b8,
+           0x55df, 0x8a78, 0x413c, 0xeb32, 0x6bc4, 0x3e47, 0x3d79, 0x2c8f);
+  VLOAD_16(v3, 0x89fd, 0x6bb7, 0x4a94, 0x770c, 0x7c87, 0x8b01, 0xbb6a, 0x900d,
+           0xb589, 0x709e, 0xc75d, 0xafa5, 0x4fd5, 0x2d77, 0x8dbf, 0x3a0a);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmulh.vv v1, v2, v3, v0.t");
+  VCMP_I16(6, v1, 0, 0xd74c, 0, 0xd497, 0, 0xfeff, 0, 0x1f2b, 0, 0xcc4b, 0,
+           0x0687, 0, 0x0b0f, 0, 0x0a1a);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0xc66253f4, 0x710c314c, 0xa6fe579b, 0xa7947b70, 0xbf94259f,
+           0x211088fe, 0x64bfd390, 0x1d49c8d8, 0x7a12a08a, 0x190ee9ae,
+           0x361172f8, 0x52457515, 0x05d4b17b, 0x7bb6d43b, 0x96270cc7,
+           0x62d35f88);
+  VLOAD_32(v3, 0xd14a266e, 0xe4f43ca5, 0x1c067312, 0xa1909d51, 0x35b8d1aa,
+           0xdcd3e2ea, 0x05cec46d, 0xbe70ebd4, 0xe15e49c5, 0x81be068b,
+           0x49fd9ad8, 0x6c2a5abd, 0x26216dd6, 0x9e3188ac, 0x14af13c4,
+           0xd98c6d7f);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmulh.vv v1, v2, v3, v0.t");
+  VCMP_I32(7, v1, 0, 0xf40e8502, 0, 0x209df360, 0, 0xfb750aac, 0, 0xf87fe57b, 0,
+           0xf3a433c8, 0, 0x22c2e9f3, 0, 0xd0bbf2cc, 0, 0xf128024f);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x9def74822cdf1a42, 0x29307e854b225449, 0x071cdf51785d150e,
+           0xe8ced2e9009d363f, 0xa88c741be4e81893, 0x4a7655ec12afe587,
+           0x50c5efa017138cb9, 0x88e076b6ef49619d, 0x5745683769adf333,
+           0x5b3b01f4b1c4fd42, 0x8a3d55e48864d144, 0x2eac97fae4174cac,
+           0xdb8804ccf6f55686, 0xf7bea87bac575241, 0x250ed7ddade1432d,
+           0x06ae542295f32453);
+  VLOAD_64(v3, 0xc5c41e47b5f3de5f, 0xa03833fb95a7e7e2, 0x74f0573dba05b058,
+           0x687968e9ba2a98ad, 0x29f4aaf3e5e4f2b6, 0x2c40a650d53f6f08,
+           0x491da2c816388b78, 0x2822d8207421ec15, 0x5dd8d394b292512a,
+           0x4169844eea56920d, 0x97183b6e1e85fd70, 0x224077bf8899614c,
+           0x3a9c0520417d4f32, 0xee47b09a33f49fca, 0x3f9f1140fbd02e0a,
+           0x6106ad88eabfc3e2);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmulh.vv v1, v2, v3, v0.t");
+  VCMP_I64(8, v1, 0, 0xf096db86d4d06824, 0, 0xf68905ef31703000, 0,
+           0x0cdf24ba4cf3be38, 0, 0xed52dbcaa3de5ca2, 0, 0x174f95d97aff7bf9, 0,
+           0x063ead2a7756c9da, 0, 0x0092485623082173, 0, 0x02883a7e75391040);
+};
+
+void TEST_CASE3(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x92, 0xce, 0xdd, 0x64, 0x60, 0x29, 0xa6, 0xd5, 0x07, 0x8c, 0x71,
+          0x94, 0x95, 0xf6, 0xd4, 0xbd);
+  int64_t scalar = 5;
+  asm volatile("vmulh.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_I8(9, v1, 0xfd, 0xff, 0xff, 0x01, 0x01, 0x00, 0xfe, 0xff, 0x00, 0xfd,
+          0x02, 0xfd, 0xfd, 0xff, 0xff, 0xfe);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x3b9b, 0x7758, 0x030f, 0x9f60, 0x13e2, 0x8f0d, 0xfc9d, 0x3922,
+           0x3a43, 0x58b5, 0xb9e9, 0xa4e8, 0x4bac, 0x5636, 0x9f4a, 0xbd52);
+  scalar = -5383;
+  asm volatile("vmulh.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_I16(10, v1, 0xfb1a, 0xf632, 0xffbf, 0x07ef, 0xfe5d, 0x0947, 0x0047,
+           0xfb4e, 0xfb36, 0xf8b6, 0x05c1, 0x077b, 0xf9c8, 0xf8eb, 0x07f1,
+           0x057a);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x7efca225, 0xdbc0a9ca, 0x0cf02cf8, 0xc19bdc84, 0x7fa3ca90,
+           0x3d878c29, 0x15809928, 0x7b0b7421, 0x48b872f5, 0xafbfeab4,
+           0xe79dc9ba, 0xe60a8fc0, 0x1fd7e866, 0xed7df17c, 0x0684a7ee,
+           0xb2b01a61);
+  scalar = 6474219;
+  asm volatile("vmulh.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_I32(11, v1, 0x003100de, 0xfff20329, 0x0004fe25, 0xffe7ec74, 0x00314160,
+           0x0017be6b, 0x00084c30, 0x002f7b6f, 0x001c0ff7, 0xffe1082b,
+           0xfff6972b, 0xfff5fb91, 0x000c49c4, 0xfff8db9d, 0x000283ec,
+           0xffe22a6f);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x42e9b386e7453715, 0xd6aae3fda4b2f3e8, 0xfcbec1ad7996a0b2,
+           0x4fcb68f516b589c9, 0x414b0eeb29c35e62, 0x038c6221829f4241,
+           0xf2c2c11f26e326b0, 0xed9ad0ce4d50a009, 0xc57105a57d435897,
+           0x90c1615935c1abd0, 0xf5b41f9a0a988065, 0xb09790bdcbecee7b,
+           0x1d9da4f87df33b54, 0xe347aadb53bdc879, 0x7a39a7269cbae2a7,
+           0x422ed2952e246f26);
+  scalar = -598189234597999223;
+  asm volatile("vmulh.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_I64(12, v1, 0xfdd4850b300f6008, 0x01571f899f226d57, 0x001b0534decdc9a2,
+           0xfd6994f8de6e51aa, 0xfde1f73873e6758a, 0xffe28b043b9b8971,
+           0x006de7f819baba3d, 0x0098b57f65f599e1, 0x01e62040839e971b,
+           0x039b807e6f36fd81, 0x005579d7e0c206af, 0x0293356120e5cee9,
+           0xff0a24a69d9af87b, 0x00ee6bb505683322, 0xfc095797a6198143,
+           0xfdda946cdb2f169c);
+};
+
+void TEST_CASE4(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x92, 0xce, 0xdd, 0x64, 0x60, 0x29, 0xa6, 0xd5, 0x07, 0x8c, 0x71,
+          0x94, 0x95, 0xf6, 0xd4, 0xbd);
+  int64_t scalar = 5;
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmulh.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_I8(13, v1, 0, 0xff, 0, 0x01, 0, 0x00, 0, 0xff, 0, 0xfd, 0, 0xfd, 0, 0xff,
+          0, 0xfe);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x3b9b, 0x7758, 0x030f, 0x9f60, 0x13e2, 0x8f0d, 0xfc9d, 0x3922,
+           0x3a43, 0x58b5, 0xb9e9, 0xa4e8, 0x4bac, 0x5636, 0x9f4a, 0xbd52);
+  scalar = -5383;
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmulh.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_I16(14, v1, 0, 0xf632, 0, 0x07ef, 0, 0x0947, 0, 0xfb4e, 0, 0xf8b6, 0,
+           0x077b, 0, 0xf8eb, 0, 0x057a);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x7efca225, 0xdbc0a9ca, 0x0cf02cf8, 0xc19bdc84, 0x7fa3ca90,
+           0x3d878c29, 0x15809928, 0x7b0b7421, 0x48b872f5, 0xafbfeab4,
+           0xe79dc9ba, 0xe60a8fc0, 0x1fd7e866, 0xed7df17c, 0x0684a7ee,
+           0xb2b01a61);
+  scalar = 6474219;
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmulh.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_I32(15, v1, 0, 0xfff20329, 0, 0xffe7ec74, 0, 0x0017be6b, 0, 0x002f7b6f,
+           0, 0xffe1082b, 0, 0xfff5fb91, 0, 0xfff8db9d, 0, 0xffe22a6f);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x42e9b386e7453715, 0xd6aae3fda4b2f3e8, 0xfcbec1ad7996a0b2,
+           0x4fcb68f516b589c9, 0x414b0eeb29c35e62, 0x038c6221829f4241,
+           0xf2c2c11f26e326b0, 0xed9ad0ce4d50a009, 0xc57105a57d435897,
+           0x90c1615935c1abd0, 0xf5b41f9a0a988065, 0xb09790bdcbecee7b,
+           0x1d9da4f87df33b54, 0xe347aadb53bdc879, 0x7a39a7269cbae2a7,
+           0x422ed2952e246f26);
+  scalar = -598189234597999223;
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmulh.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_I64(16, v1, 0, 0x01571f899f226d57, 0, 0xfd6994f8de6e51aa, 0,
+           0xffe28b043b9b8971, 0, 0x0098b57f65f599e1, 0, 0x039b807e6f36fd81, 0,
+           0x0293356120e5cee9, 0, 0x00ee6bb505683322, 0, 0xfdda946cdb2f169c);
+};
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vmulhsu.c b/apps/riscv-tests/isa/rv64uv/vmulhsu.c
new file mode 100644
index 0000000..efb53b5
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vmulhsu.c
@@ -0,0 +1,232 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x53, 0x4f, 0xde, 0xea, 0x47, 0x3c, 0x41, 0xf8, 0xd6, 0xd0, 0x93,
+          0x35, 0xfc, 0x70, 0x33, 0xe4);
+  VLOAD_8(v3, 0xaa, 0x24, 0xaa, 0xde, 0x92, 0x00, 0x7f, 0xe5, 0xb3, 0xf8, 0xa0,
+          0xa8, 0xbb, 0xc6, 0x65, 0x81);
+  asm volatile("vmulhsu.vv v1, v2, v3");
+  VCMP_I8(1, v1, 0x37, 0x0b, 0xe9, 0xec, 0x28, 0x00, 0x20, 0xf8, 0xe2, 0xd1,
+          0xbb, 0x22, 0xfd, 0x56, 0x14, 0xf1);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x0f50, 0x47f9, 0xa4ca, 0xf94d, 0x720c, 0x444c, 0x3681, 0x96bd,
+           0x5d37, 0xd64e, 0xe792, 0xdb64, 0xfaa6, 0xafe6, 0xf4e8, 0xe5ea);
+  VLOAD_16(v3, 0x7784, 0xa42e, 0x499b, 0x0c01, 0x9d2b, 0x600d, 0x2bbd, 0xcb41,
+           0xdda1, 0xb5d7, 0xafbc, 0xc74f, 0xab45, 0x986f, 0xf0f2, 0xcf3c);
+  asm volatile("vmulhsu.vv v1, v2, v3");
+  VCMP_I16(2, v1, 0x0726, 0x2e28, 0xe5c6, 0xffaf, 0x4604, 0x199f, 0x094f,
+           0xac6d, 0x50b3, 0xe262, 0xef3a, 0xe37f, 0xfc6b, 0xd04d, 0xf58f,
+           0xeae2);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0xeded4bf3, 0xc9e27167, 0x4175509c, 0x80a3ae04, 0x9f1b2c07,
+           0x87ea397b, 0x862e2800, 0x3cd09f37, 0x9a313d78, 0x596661ee,
+           0x31f99717, 0x64e65802, 0xbd567027, 0xf7c459be, 0x57b6d9cd,
+           0x94bc3eb4);
+  VLOAD_32(v3, 0xa147b233, 0x19880f3d, 0x8dd8815e, 0xbc318dca, 0x2c436b94,
+           0x29ba4191, 0x637f89b7, 0xe39d7818, 0xf48ff2d6, 0xb1dc7c7e,
+           0xfa5da298, 0x5c1aae36, 0x83e04069, 0xecf36c08, 0x40d2e3a3,
+           0xe7468a97);
+  asm volatile("vmulhsu.vv v1, v2, v3");
+  VCMP_I32(3, v1, 0xf49d2cff, 0xfa9a5a26, 0x2444f976, 0xa25f8c94, 0xef3f26f6,
+           0xec6d24a0, 0xd0a728d5, 0x361265a6, 0x9ebdaf85, 0x3e1cc92b,
+           0x30e004f5, 0x244d4baf, 0xdda8d640, 0xf8612ea2, 0x1635f870,
+           0x9f184dfb);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x2b1f761d24dcff24, 0x1174fcea60fbf146, 0xaa5068c22e71489d,
+           0x422ad458a7cbf321, 0x01e0f752e5d8bb37, 0xe7762162abff4c4c,
+           0x36279dbbf009199d, 0x188dda33d835d9e4, 0xa0f5a67450e87d77,
+           0xb43066649033e7ac, 0xb47ff6241cc77c2c, 0xfce0bafc1d36b615,
+           0x045b90f3b63e0f7f, 0x514e5121be1f02e5, 0x06c9e97573723e47,
+           0x406879d908a80b41);
+  VLOAD_64(v3, 0xd50adee8d491db29, 0xc7d423514dd58616, 0x5b22f7a3971e17f9,
+           0xb9ad8b0339e659cd, 0x5af15755f3954b0f, 0x6b2fb3e49bd48e69,
+           0x084244757fba5561, 0xf2d5b41ee89411fa, 0x8585111aaee16c07,
+           0xcd1a427644b0ad59, 0x2356738fd6b04f3a, 0x89d936a76f0a518a,
+           0x5f2df66443ff24b3, 0x6cbfcf273c43ae6b, 0xabb59d9f05a03eef,
+           0xb84832df19fc19b6);
+  asm volatile("vmulhsu.vv v1, v2, v3");
+  VCMP_I64(4, v1, 0x23e3020d5d8e40d8, 0x0da067e42d62fa2a, 0xe17ee107c3fdd97f,
+           0x2ffdce53a7ef7aa4, 0x00aadc600f6180bd, 0xf5b9cd660e9f294b,
+           0x01bf419feafa3fe5, 0x174a979243e0945b, 0xce6e38c0508aba17,
+           0xc342fb3a620dde75, 0xf593ff8eafcca075, 0xfe519de4c807844e,
+           0x019ec3149daf2fc0, 0x2289f5738e0e6d23, 0x048dafe18fe3288b,
+           0x2e5d41c2cc9b604f);
+};
+
+void TEST_CASE2(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x53, 0x4f, 0xde, 0xea, 0x47, 0x3c, 0x41, 0xf8, 0xd6, 0xd0, 0x93,
+          0x35, 0xfc, 0x70, 0x33, 0xe4);
+  VLOAD_8(v3, 0xaa, 0x24, 0xaa, 0xde, 0x92, 0x00, 0x7f, 0xe5, 0xb3, 0xf8, 0xa0,
+          0xa8, 0xbb, 0xc6, 0x65, 0x81);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmulhsu.vv v1, v2, v3, v0.t");
+  VCMP_I8(5, v1, 0, 0x0b, 0, 0xec, 0, 0x00, 0, 0xf8, 0, 0xd1, 0, 0x22, 0, 0x56,
+          0, 0xf1);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x0f50, 0x47f9, 0xa4ca, 0xf94d, 0x720c, 0x444c, 0x3681, 0x96bd,
+           0x5d37, 0xd64e, 0xe792, 0xdb64, 0xfaa6, 0xafe6, 0xf4e8, 0xe5ea);
+  VLOAD_16(v3, 0x7784, 0xa42e, 0x499b, 0x0c01, 0x9d2b, 0x600d, 0x2bbd, 0xcb41,
+           0xdda1, 0xb5d7, 0xafbc, 0xc74f, 0xab45, 0x986f, 0xf0f2, 0xcf3c);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmulhsu.vv v1, v2, v3, v0.t");
+  VCMP_I16(6, v1, 0, 0x2e28, 0, 0xffaf, 0, 0x199f, 0, 0xac6d, 0, 0xe262, 0,
+           0xe37f, 0, 0xd04d, 0, 0xeae2);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0xeded4bf3, 0xc9e27167, 0x4175509c, 0x80a3ae04, 0x9f1b2c07,
+           0x87ea397b, 0x862e2800, 0x3cd09f37, 0x9a313d78, 0x596661ee,
+           0x31f99717, 0x64e65802, 0xbd567027, 0xf7c459be, 0x57b6d9cd,
+           0x94bc3eb4);
+  VLOAD_32(v3, 0xa147b233, 0x19880f3d, 0x8dd8815e, 0xbc318dca, 0x2c436b94,
+           0x29ba4191, 0x637f89b7, 0xe39d7818, 0xf48ff2d6, 0xb1dc7c7e,
+           0xfa5da298, 0x5c1aae36, 0x83e04069, 0xecf36c08, 0x40d2e3a3,
+           0xe7468a97);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmulhsu.vv v1, v2, v3, v0.t");
+  VCMP_I32(7, v1, 0, 0xfa9a5a26, 0, 0xa25f8c94, 0, 0xec6d24a0, 0, 0x361265a6, 0,
+           0x3e1cc92b, 0, 0x244d4baf, 0, 0xf8612ea2, 0, 0x9f184dfb);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x2b1f761d24dcff24, 0x1174fcea60fbf146, 0xaa5068c22e71489d,
+           0x422ad458a7cbf321, 0x01e0f752e5d8bb37, 0xe7762162abff4c4c,
+           0x36279dbbf009199d, 0x188dda33d835d9e4, 0xa0f5a67450e87d77,
+           0xb43066649033e7ac, 0xb47ff6241cc77c2c, 0xfce0bafc1d36b615,
+           0x045b90f3b63e0f7f, 0x514e5121be1f02e5, 0x06c9e97573723e47,
+           0x406879d908a80b41);
+  VLOAD_64(v3, 0xd50adee8d491db29, 0xc7d423514dd58616, 0x5b22f7a3971e17f9,
+           0xb9ad8b0339e659cd, 0x5af15755f3954b0f, 0x6b2fb3e49bd48e69,
+           0x084244757fba5561, 0xf2d5b41ee89411fa, 0x8585111aaee16c07,
+           0xcd1a427644b0ad59, 0x2356738fd6b04f3a, 0x89d936a76f0a518a,
+           0x5f2df66443ff24b3, 0x6cbfcf273c43ae6b, 0xabb59d9f05a03eef,
+           0xb84832df19fc19b6);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmulhsu.vv v1, v2, v3, v0.t");
+  VCMP_I64(8, v1, 0, 0x0da067e42d62fa2a, 0, 0x2ffdce53a7ef7aa4, 0,
+           0xf5b9cd660e9f294b, 0, 0x174a979243e0945b, 0, 0xc342fb3a620dde75, 0,
+           0xfe519de4c807844e, 0, 0x2289f5738e0e6d23, 0, 0x2e5d41c2cc9b604f);
+};
+
+void TEST_CASE3(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x21, 0x87, 0xa0, 0xa8, 0x6a, 0x6f, 0x6a, 0x6b, 0x74, 0x99, 0x37,
+          0xa4, 0xdc, 0x4f, 0xc3, 0x55);
+  uint64_t scalar = 5;
+  asm volatile("vmulhsu.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_I8(9, v1, 0x00, 0xfd, 0xfe, 0xfe, 0x02, 0x02, 0x02, 0x02, 0x02, 0xfd,
+          0x01, 0xfe, 0xff, 0x01, 0xfe, 0x01);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x62b8, 0xc1e3, 0xb151, 0x08ce, 0x06c4, 0x1d2f, 0x7448, 0xfcd5,
+           0x398c, 0xb933, 0x436d, 0x748f, 0x58d9, 0x1cd6, 0x86db, 0x20f2);
+  scalar = 816;
+  asm volatile("vmulhsu.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_I16(10, v1, 0x013a, 0xff3a, 0xff05, 0x001c, 0x0015, 0x005d, 0x0172,
+           0xfff5, 0x00b7, 0xff1e, 0x00d6, 0x0173, 0x011b, 0x005b, 0xfe7d,
+           0x0069);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0xa7cac3f7, 0xb3894e05, 0xbac8e70b, 0x05479577, 0x19d8bf63,
+           0xb952c1ad, 0x9eaa74c0, 0x9e38d5c8, 0x51c77b3b, 0xa5f44521,
+           0x65042faa, 0x8e7e5345, 0x76ae481c, 0x0ab27b6f, 0xa388cf2b,
+           0x58218f7f);
+  scalar = 7389998;
+  asm volatile("vmulhsu.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_I32(11, v1, 0xffd92575, 0xffde51c5, 0xffe1831f, 0x00025357, 0x000b6288,
+           0xffe0de52, 0xffd5205d, 0xffd4ee51, 0x0024059f, 0xffd85637,
+           0x002c7ed9, 0xffce00ba, 0x003446bb, 0x0004b63d, 0xffd7455b,
+           0x0026d1e0);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x43c5f863d4be9b51, 0x70b017b4c5d0d11e, 0x9e008a07f48796fe,
+           0x6f0fa9a63860308a, 0x07b5d372a7be167c, 0x234be9472899553e,
+           0x25655d82cb668037, 0x959d6233470780ee, 0xf3d683308326232a,
+           0x7b6dddfcd86d6737, 0x02b8177716c29a3e, 0x11220f42ce0594b4,
+           0x8382e0c79caa1e6c, 0x0d1593d36c1dc00e, 0x9f8eb889cc8e98c6,
+           0x37411f40369680d2);
+  scalar = 321156886679781445;
+  asm volatile("vmulhsu.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_I64(12, v1, 0x012e0fe6705cf26d, 0x01f63e6c65840868, 0xfe4b3a837bcf749f,
+           0x01eefe6ad67c584e, 0x00225d3cec11ae29, 0x009d50942207fb0e,
+           0x00a6abfb9cc735df, 0xfe25d8c13270b026, 0xffc9cb59c445c91a,
+           0x02261e05ece3e474, 0x000c1e7198242fc2, 0x004c5c6f8fd9129e,
+           0xfdd529022c30504c, 0x003a50e3baabab1e, 0xfe522930314d6d7d,
+           0x00f6440fa9591c62);
+};
+
+void TEST_CASE4(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x21, 0x87, 0xa0, 0xa8, 0x6a, 0x6f, 0x6a, 0x6b, 0x74, 0x99, 0x37,
+          0xa4, 0xdc, 0x4f, 0xc3, 0x55);
+  uint64_t scalar = 5;
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmulhsu.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_I8(13, v1, 0, 0xfd, 0, 0xfe, 0, 0x02, 0, 0x02, 0, 0xfd, 0, 0xfe, 0, 0x01,
+          0, 0x01);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x62b8, 0xc1e3, 0xb151, 0x08ce, 0x06c4, 0x1d2f, 0x7448, 0xfcd5,
+           0x398c, 0xb933, 0x436d, 0x748f, 0x58d9, 0x1cd6, 0x86db, 0x20f2);
+  scalar = 816;
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmulhsu.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_I16(14, v1, 0, 0xff3a, 0, 0x001c, 0, 0x005d, 0, 0xfff5, 0, 0xff1e, 0,
+           0x0173, 0, 0x005b, 0, 0x0069);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0xa7cac3f7, 0xb3894e05, 0xbac8e70b, 0x05479577, 0x19d8bf63,
+           0xb952c1ad, 0x9eaa74c0, 0x9e38d5c8, 0x51c77b3b, 0xa5f44521,
+           0x65042faa, 0x8e7e5345, 0x76ae481c, 0x0ab27b6f, 0xa388cf2b,
+           0x58218f7f);
+  scalar = 7389998;
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmulhsu.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_I32(15, v1, 0, 0xffde51c5, 0, 0x00025357, 0, 0xffe0de52, 0, 0xffd4ee51,
+           0, 0xffd85637, 0, 0xffce00ba, 0, 0x0004b63d, 0, 0x0026d1e0);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x43c5f863d4be9b51, 0x70b017b4c5d0d11e, 0x9e008a07f48796fe,
+           0x6f0fa9a63860308a, 0x07b5d372a7be167c, 0x234be9472899553e,
+           0x25655d82cb668037, 0x959d6233470780ee, 0xf3d683308326232a,
+           0x7b6dddfcd86d6737, 0x02b8177716c29a3e, 0x11220f42ce0594b4,
+           0x8382e0c79caa1e6c, 0x0d1593d36c1dc00e, 0x9f8eb889cc8e98c6,
+           0x37411f40369680d2);
+  scalar = 321156886679781445;
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmulhsu.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_I64(16, v1, 0, 0x01f63e6c65840868, 0, 0x01eefe6ad67c584e, 0,
+           0x009d50942207fb0e, 0, 0xfe25d8c13270b026, 0, 0x02261e05ece3e474, 0,
+           0x004c5c6f8fd9129e, 0, 0x003a50e3baabab1e, 0, 0x00f6440fa9591c62);
+};
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vmulhu.c b/apps/riscv-tests/isa/rv64uv/vmulhu.c
new file mode 100644
index 0000000..b72691e
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vmulhu.c
@@ -0,0 +1,232 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x3b, 0xb2, 0xd1, 0x3e, 0x39, 0x2c, 0x08, 0xc5, 0xbf, 0x54, 0x6c,
+          0xde, 0x87, 0xcb, 0x7a, 0x83);
+  VLOAD_8(v3, 0x55, 0xde, 0xf4, 0x14, 0x3c, 0xed, 0x47, 0x1b, 0xca, 0x0b, 0xc4,
+          0xe3, 0xd8, 0x8f, 0xa0, 0x0d);
+  asm volatile("vmulhu.vv v1, v2, v3");
+  VCMP_U8(1, v1, 0x13, 0x9a, 0xc7, 0x04, 0x0d, 0x28, 0x02, 0x14, 0x96, 0x03,
+          0x52, 0xc4, 0x71, 0x71, 0x4c, 0x06);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0xe6e1, 0x02a1, 0x2911, 0xe3c3, 0xe141, 0x69e6, 0x4133, 0xf783,
+           0x91ef, 0x1897, 0xf0bb, 0x0e07, 0xb8eb, 0x3f5a, 0x9f5d, 0xa626);
+  VLOAD_16(v3, 0x4fcb, 0x8a38, 0xbaa0, 0x8a97, 0xe409, 0x558e, 0x582b, 0x62b1,
+           0xf7bb, 0x181f, 0x2b5a, 0xdf85, 0x44f3, 0x27fe, 0x8412, 0xcda0);
+  asm volatile("vmulhu.vv v1, v2, v3");
+  VCMP_U16(2, v1, 0x47f6, 0x016b, 0x1df0, 0x7b4d, 0xc8a5, 0x2364, 0x1674,
+           0x5f6b, 0x8d38, 0x0251, 0x28c4, 0x0c3f, 0x31cd, 0x09e5, 0x5237,
+           0x8574);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0xf129e694, 0x8dfc72a3, 0xc9911598, 0xd20083ec, 0xe7f36604,
+           0x1ab510aa, 0xc290b86c, 0xa7e9a02e, 0x5c3f3bb3, 0x70a3dfae,
+           0x16baad22, 0x21758cfb, 0x09033e60, 0x8b31075e, 0x6439b7bf,
+           0xead33cf0);
+  VLOAD_32(v3, 0x3f2ef56d, 0x12649032, 0x6c0a880b, 0x7cb2477a, 0x41525037,
+           0x02a39cfa, 0xf7595181, 0x0c230035, 0x86cf9ea9, 0x0f66ddd3,
+           0x13351370, 0xbe489ce5, 0x4127f488, 0xe6b5e1b3, 0xc6918270,
+           0xccc8626a);
+  asm volatile("vmulhu.vv v1, v2, v3");
+  VCMP_U32(3, v1, 0x3b858c79, 0x0a3386a5, 0x55117fe4, 0x664a7ee4, 0x3b2f618b,
+           0x00467bcb, 0xbbfd8432, 0x07f5e895, 0x3093e98c, 0x06c6dd00,
+           0x01b49139, 0x18debc33, 0x024b3af0, 0x7d70f100, 0x4dbd9bdf,
+           0xbbd823dc);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x4aee1e4f9775ff4b, 0x045a804c3d3e7dc0, 0x1a2f38060efcd306,
+           0x34e09e5173ee6301, 0xd1f03c2e38769683, 0x1b1f454816d4ed10,
+           0xed4a4f231da4abb3, 0xc87b025e6da277dc, 0x8da43ddf6feb6aae,
+           0x7dcf10ced634db74, 0x736fd9583bc2de91, 0xa66de0036d350cbc,
+           0x40bf5ec7afca9ec2, 0x5bb552a7b134ba79, 0x6ae5d02d7c121603,
+           0x8a7621ad8d6f104a);
+  VLOAD_64(v3, 0x8f2c0088bea2739e, 0x4ed8c54dad60d3cb, 0x51e715e5cf56b2e6,
+           0xa1b1262536ea3c57, 0x67f334468e5cde4f, 0x8ae5618164bd63fd,
+           0x2f8be93c1d7807c3, 0x0444a9f4ccff2a2c, 0x6cac5e35bf847d59,
+           0x1d92c5117b87a392, 0x124597d21d757a4e, 0x4ec5a9fb5b8a6591,
+           0xb5b4189dd6080734, 0xf75ddacea0effff6, 0x5c3cb19fbc1c7580,
+           0xff93a562f06d3641);
+  asm volatile("vmulhu.vv v1, v2, v3");
+  VCMP_U64(4, v1, 0x29e7e403b1955330, 0x015742ce71e2c757, 0x08609392d9402e03,
+           0x2165dabfb788d03d, 0x553f1a1e61409141, 0x0eb728a66479b5fb,
+           0x2c125410c5448322, 0x0357b1cf05241ad9, 0x3c20a893e10635bb,
+           0x0e8895d7f39e953c, 0x083d3ee38137c9b0, 0x3335fb506009220b,
+           0x2df4dacbb013b6b0, 0x589d920140d7dd8c, 0x2683eed8bb77fa43,
+           0x8a3b86d4dd8169cf);
+};
+
+void TEST_CASE2(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x3b, 0xb2, 0xd1, 0x3e, 0x39, 0x2c, 0x08, 0xc5, 0xbf, 0x54, 0x6c,
+          0xde, 0x87, 0xcb, 0x7a, 0x83);
+  VLOAD_8(v3, 0x55, 0xde, 0xf4, 0x14, 0x3c, 0xed, 0x47, 0x1b, 0xca, 0x0b, 0xc4,
+          0xe3, 0xd8, 0x8f, 0xa0, 0x0d);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmulhu.vv v1, v2, v3, v0.t");
+  VCMP_U8(5, v1, 0, 0x9a, 0, 0x04, 0, 0x28, 0, 0x14, 0, 0x03, 0, 0xc4, 0, 0x71,
+          0, 0x06);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0xe6e1, 0x02a1, 0x2911, 0xe3c3, 0xe141, 0x69e6, 0x4133, 0xf783,
+           0x91ef, 0x1897, 0xf0bb, 0x0e07, 0xb8eb, 0x3f5a, 0x9f5d, 0xa626);
+  VLOAD_16(v3, 0x4fcb, 0x8a38, 0xbaa0, 0x8a97, 0xe409, 0x558e, 0x582b, 0x62b1,
+           0xf7bb, 0x181f, 0x2b5a, 0xdf85, 0x44f3, 0x27fe, 0x8412, 0xcda0);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmulhu.vv v1, v2, v3, v0.t");
+  VCMP_U16(6, v1, 0, 0x016b, 0, 0x7b4d, 0, 0x2364, 0, 0x5f6b, 0, 0x0251, 0,
+           0x0c3f, 0, 0x09e5, 0, 0x8574);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0xf129e694, 0x8dfc72a3, 0xc9911598, 0xd20083ec, 0xe7f36604,
+           0x1ab510aa, 0xc290b86c, 0xa7e9a02e, 0x5c3f3bb3, 0x70a3dfae,
+           0x16baad22, 0x21758cfb, 0x09033e60, 0x8b31075e, 0x6439b7bf,
+           0xead33cf0);
+  VLOAD_32(v3, 0x3f2ef56d, 0x12649032, 0x6c0a880b, 0x7cb2477a, 0x41525037,
+           0x02a39cfa, 0xf7595181, 0x0c230035, 0x86cf9ea9, 0x0f66ddd3,
+           0x13351370, 0xbe489ce5, 0x4127f488, 0xe6b5e1b3, 0xc6918270,
+           0xccc8626a);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmulhu.vv v1, v2, v3, v0.t");
+  VCMP_U32(7, v1, 0, 0x0a3386a5, 0, 0x664a7ee4, 0, 0x00467bcb, 0, 0x07f5e895, 0,
+           0x06c6dd00, 0, 0x18debc33, 0, 0x7d70f100, 0, 0xbbd823dc);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x4aee1e4f9775ff4b, 0x045a804c3d3e7dc0, 0x1a2f38060efcd306,
+           0x34e09e5173ee6301, 0xd1f03c2e38769683, 0x1b1f454816d4ed10,
+           0xed4a4f231da4abb3, 0xc87b025e6da277dc, 0x8da43ddf6feb6aae,
+           0x7dcf10ced634db74, 0x736fd9583bc2de91, 0xa66de0036d350cbc,
+           0x40bf5ec7afca9ec2, 0x5bb552a7b134ba79, 0x6ae5d02d7c121603,
+           0x8a7621ad8d6f104a);
+  VLOAD_64(v3, 0x8f2c0088bea2739e, 0x4ed8c54dad60d3cb, 0x51e715e5cf56b2e6,
+           0xa1b1262536ea3c57, 0x67f334468e5cde4f, 0x8ae5618164bd63fd,
+           0x2f8be93c1d7807c3, 0x0444a9f4ccff2a2c, 0x6cac5e35bf847d59,
+           0x1d92c5117b87a392, 0x124597d21d757a4e, 0x4ec5a9fb5b8a6591,
+           0xb5b4189dd6080734, 0xf75ddacea0effff6, 0x5c3cb19fbc1c7580,
+           0xff93a562f06d3641);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmulhu.vv v1, v2, v3, v0.t");
+  VCMP_U64(8, v1, 0, 0x015742ce71e2c757, 0, 0x2165dabfb788d03d, 0,
+           0x0eb728a66479b5fb, 0, 0x0357b1cf05241ad9, 0, 0x0e8895d7f39e953c, 0,
+           0x3335fb506009220b, 0, 0x589d920140d7dd8c, 0, 0x8a3b86d4dd8169cf);
+};
+
+void TEST_CASE3(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x5c, 0x3c, 0x86, 0x65, 0x41, 0x38, 0x20, 0x9e, 0x88, 0x28, 0x19,
+          0xc2, 0x5f, 0xa3, 0x7c, 0xca);
+  uint64_t scalar = 5;
+  asm volatile("vmulhu.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U8(9, v1, 0x01, 0x01, 0x02, 0x01, 0x01, 0x01, 0x00, 0x03, 0x02, 0x00,
+          0x00, 0x03, 0x01, 0x03, 0x02, 0x03);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x4e7f, 0xfe41, 0x1346, 0x6c1a, 0x38ce, 0x5fa7, 0x5e39, 0xf7a2,
+           0x61aa, 0x0a3a, 0xfe0a, 0x30f1, 0x5852, 0xbb6b, 0x42f7, 0x58d9);
+  scalar = 816;
+  asm volatile("vmulhu.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U16(10, v1, 0x00fa, 0x032a, 0x003d, 0x0158, 0x00b5, 0x0130, 0x012c,
+           0x0315, 0x0137, 0x0020, 0x0329, 0x009c, 0x0119, 0x0255, 0x00d5,
+           0x011b);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x15c6221c, 0x0d704417, 0x3d90ffd1, 0x4e168273, 0xc3bd5e20,
+           0xd75f62df, 0x3002ed42, 0x74269b1d, 0xc77bc0dd, 0x36f2552d,
+           0x71b5888c, 0x02eb291b, 0x790cb3b1, 0xa3cf03c4, 0x8f90730a,
+           0xf41b555a);
+  scalar = 7389998;
+  asm volatile("vmulhu.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U32(11, v1, 0x00099748, 0x0005eb5c, 0x001b1e60, 0x00226562, 0x00563815,
+           0x005eddef, 0x001525e2, 0x00332972, 0x0057de3b, 0x001833e9,
+           0x0032161d, 0x0001491b, 0x003551d9, 0x00482775, 0x003f3ca7,
+           0x006b8612);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x96304201a90be11f, 0x11654d4226322e4b, 0xe16e5cf2c1183b63,
+           0x447b5f4710764817, 0xb62589a3d309672c, 0x5ddec2e6716fd0d3,
+           0xf31034a096a6d0fa, 0x9cb4dca46ce577f7, 0x30cf2e2dc6773d82,
+           0x6129247d49c42f4b, 0x3d9ee22336a4e216, 0x3c9b9d533797be90,
+           0x0c0c54042a20ddc8, 0xf309bda968a3a583, 0x550697570a1e9645,
+           0x5beaf5933973231f);
+  scalar = 321156886679781445;
+  asm volatile("vmulhu.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U64(12, v1, 0x029d61da2f470da8, 0x004d882170361dd2, 0x03ecbc09716942cd,
+           0x013138661b0ea1a1, 0x032bd162449d3f20, 0x01a25fd52874e6a2,
+           0x043b51fe85cf352c, 0x02ba6ebb77802a7c, 0x00d98a5bba81dc57,
+           0x01b10a47f99f8c44, 0x0112a3d22e03b6e9, 0x010e20461059ad6b,
+           0x0035b2b00a44dfe2, 0x043b352e6dc32a00, 0x017af48bc4f5ad70,
+           0x0199ac3dc8053978);
+};
+
+void TEST_CASE4(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x5c, 0x3c, 0x86, 0x65, 0x41, 0x38, 0x20, 0x9e, 0x88, 0x28, 0x19,
+          0xc2, 0x5f, 0xa3, 0x7c, 0xca);
+  uint64_t scalar = 5;
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmulhu.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U8(13, v1, 0, 0x01, 0, 0x01, 0, 0x01, 0, 0x03, 0, 0x00, 0, 0x03, 0, 0x03,
+          0, 0x03);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x4e7f, 0xfe41, 0x1346, 0x6c1a, 0x38ce, 0x5fa7, 0x5e39, 0xf7a2,
+           0x61aa, 0x0a3a, 0xfe0a, 0x30f1, 0x5852, 0xbb6b, 0x42f7, 0x58d9);
+  scalar = 816;
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmulhu.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U16(14, v1, 0, 0x032a, 0, 0x0158, 0, 0x0130, 0, 0x0315, 0, 0x0020, 0,
+           0x009c, 0, 0x0255, 0, 0x011b);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x15c6221c, 0x0d704417, 0x3d90ffd1, 0x4e168273, 0xc3bd5e20,
+           0xd75f62df, 0x3002ed42, 0x74269b1d, 0xc77bc0dd, 0x36f2552d,
+           0x71b5888c, 0x02eb291b, 0x790cb3b1, 0xa3cf03c4, 0x8f90730a,
+           0xf41b555a);
+  scalar = 7389998;
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmulhu.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U32(15, v1, 0, 0x0005eb5c, 0, 0x00226562, 0, 0x005eddef, 0, 0x00332972,
+           0, 0x001833e9, 0, 0x0001491b, 0, 0x00482775, 0, 0x006b8612);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x96304201a90be11f, 0x11654d4226322e4b, 0xe16e5cf2c1183b63,
+           0x447b5f4710764817, 0xb62589a3d309672c, 0x5ddec2e6716fd0d3,
+           0xf31034a096a6d0fa, 0x9cb4dca46ce577f7, 0x30cf2e2dc6773d82,
+           0x6129247d49c42f4b, 0x3d9ee22336a4e216, 0x3c9b9d533797be90,
+           0x0c0c54042a20ddc8, 0xf309bda968a3a583, 0x550697570a1e9645,
+           0x5beaf5933973231f);
+  scalar = 321156886679781445;
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vmulhu.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U64(16, v1, 0, 0x004d882170361dd2, 0, 0x013138661b0ea1a1, 0,
+           0x01a25fd52874e6a2, 0, 0x02ba6ebb77802a7c, 0, 0x01b10a47f99f8c44, 0,
+           0x010e20461059ad6b, 0, 0x043b352e6dc32a00, 0, 0x0199ac3dc8053978);
+};
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vmv.c b/apps/riscv-tests/isa/rv64uv/vmv.c
new file mode 100644
index 0000000..a913ec7
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vmv.c
@@ -0,0 +1,104 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1() {
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vmv.v.v v3, v1");
+  VCMP_U8(1, v3, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v2, 8, 7, 6, 5, 4, 3, 2, 1, 8, 7, 6, 5, 4, 3, 2, 1);
+  asm volatile("vmv.v.v v3, v1");
+  VCMP_U16(2, v3, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v2, 8, 7, 6, 5, 4, 3, 2, 1, 8, 7, 6, 5, 4, 3, 2, 1);
+  asm volatile("vmv.v.v v3, v1");
+  VCMP_U32(3, v3, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_64(v2, 8, 7, 6, 5, 4, 3, 2, 1, 8, 7, 6, 5, 4, 3, 2, 1);
+  asm volatile("vmv.v.v v3, v1");
+  VCMP_U64(4, v3, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+}
+
+void TEST_CASE2() {
+  const uint64_t scalar = 0x00000000deadbeef;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vmv.v.x v3, %[A]" ::[A] "r"(scalar));
+  VCMP_U8(5, v3, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef,
+          0xef, 0xef, 0xef, 0xef, 0xef, 0xef);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vmv.v.x v3, %[A]" ::[A] "r"(scalar));
+  VCMP_U16(6, v3, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef,
+           0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef,
+           0xbeef);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vmv.v.x v3, %[A]" ::[A] "r"(scalar));
+  VCMP_U32(7, v3, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
+           0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
+           0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vmv.v.x v3, %[A]" ::[A] "r"(scalar));
+  VCMP_U64(8, v3, 0x00000000deadbeef, 0x00000000deadbeef, 0x00000000deadbeef,
+           0x00000000deadbeef, 0x00000000deadbeef, 0x00000000deadbeef,
+           0x00000000deadbeef, 0x00000000deadbeef, 0x00000000deadbeef,
+           0x00000000deadbeef, 0x00000000deadbeef, 0x00000000deadbeef,
+           0x00000000deadbeef, 0x00000000deadbeef, 0x00000000deadbeef,
+           0x00000000deadbeef);
+}
+
+void TEST_CASE3() {
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vmv.v.i v3, -9");
+  VCMP_U8(9, v3, -9, -9, -9, -9, -9, -9, -9, -9, -9, -9, -9, -9, -9, -9, -9,
+          -9);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vmv.v.i v3, -10");
+  VCMP_U16(10, v3, -10, -10, -10, -10, -10, -10, -10, -10, -10, -10, -10, -10,
+           -10, -10, -10, -10);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vmv.v.i v3, -11");
+  VCMP_U32(11, v3, -11, -11, -11, -11, -11, -11, -11, -11, -11, -11, -11, -11,
+           -11, -11, -11, -11);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vmv.v.i v3, -12");
+  VCMP_U64(12, v3, -12, -12, -12, -12, -12, -12, -12, -12, -12, -12, -12, -12,
+           -12, -12, -12, -12);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vmvnrr.c b/apps/riscv-tests/isa/rv64uv/vmvnrr.c
new file mode 100644
index 0000000..10c9e32
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vmvnrr.c
@@ -0,0 +1,146 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti
+//
+// For simplicity, this test depends on vl1r and vs1r
+
+#include "vector_macros.h"
+
+uint64_t counter;
+
+// Maximum size: (VLEN/8 Bytes * (MAX_LMUL == 8)) = VLEN
+// Define VLEN before compiling me
+// #define VLEN VLEN
+uint8_t gold_vec_8b[VLEN];
+uint8_t buf_vec_8b[VLEN];
+
+///////////
+// vmv1r //
+///////////
+
+// 1 whole register load
+void TEST_CASE1(void) {
+  // Initialize a golden vector
+  INIT_MEM_CNT(gold_vec_8b, VLEN / 8);
+  // Reserve space for a buffer in memory
+  INIT_MEM_ZEROES(buf_vec_8b, VLEN / 8);
+  // Set vl and vtype to super short values
+  VSET(1, e64, m2);
+  // Initialize register + neighbours to pattern value
+  VCLEAR(v16);
+  // Load a buffer from memory - whole register load
+  asm volatile("vl1re8.v v16, (%0)" ::"r"(gold_vec_8b));
+  // Move the content to another register
+  asm volatile("vmv1r.v v1, v16");
+  // Check that the whole register was loaded
+  asm volatile("vs1r.v v1, (%0)" ::"r"(buf_vec_8b));
+  VMCMP(uint8_t, % hhu, 0, buf_vec_8b, gold_vec_8b, VLEN / 8);
+}
+
+///////////
+// vmv2r //
+///////////
+
+// 2 whole registers load
+void TEST_CASE2(void) {
+  // Initialize a golden vector
+  INIT_MEM_CNT(gold_vec_8b, VLEN / 4);
+  // Reserve space for a buffer in memory
+  INIT_MEM_ZEROES(buf_vec_8b, VLEN / 4);
+  // Set vl and vtype to super short values
+  VSET(1, e64, m4);
+  // Initialize register + neighbours to pattern value
+  VCLEAR(v16);
+  // Load a buffer from memory - whole register load
+  asm volatile("vl2re8.v v16, (%0)" ::"r"(gold_vec_8b));
+  // Move the content to another register
+  asm volatile("vmv2r.v v2, v16");
+  // Check that the whole register was loaded
+  asm volatile("vs2r.v v2, (%0)" ::"r"(buf_vec_8b));
+  VMCMP(uint8_t, % hhu, 1, buf_vec_8b, gold_vec_8b, VLEN / 4);
+}
+
+///////////
+// vmv4r //
+///////////
+
+// 4 whole registers load
+void TEST_CASE3(void) {
+  // Initialize a golden vector
+  INIT_MEM_CNT(gold_vec_8b, VLEN / 2);
+  // Reserve space for a buffer in memory
+  INIT_MEM_ZEROES(buf_vec_8b, VLEN / 2);
+  // Set vl and vtype to super short values
+  VSET(1, e64, m8);
+  // Initialize register + neighbours to pattern value
+  VCLEAR(v16);
+  // Load a buffer from memory - whole register load
+  asm volatile("vl4re8.v v16, (%0)" ::"r"(gold_vec_8b));
+  // Move the content to another register
+  asm volatile("vmv4r.v v4, v16");
+  // Check that the whole register was loaded
+  asm volatile("vs4r.v v4, (%0)" ::"r"(buf_vec_8b));
+  VMCMP(uint8_t, % hhu, 2, buf_vec_8b, gold_vec_8b, VLEN / 2);
+}
+
+///////////
+// vmv8r //
+///////////
+
+// 8 whole registers load
+void TEST_CASE4(void) {
+  // Initialize a golden vector
+  INIT_MEM_CNT(gold_vec_8b, VLEN);
+  // Reserve space for a buffer in memory
+  INIT_MEM_ZEROES(buf_vec_8b, VLEN);
+  // Set vl and vtype to super short values
+  VSET(1, e64, m8);
+  // Initialize register + neighbours to pattern value
+  VCLEAR(v16);
+  VCLEAR(v24);
+  // Load a buffer from memory - whole register load
+  asm volatile("vl8re8.v v16, (%0)" ::"r"(gold_vec_8b));
+  // Move the content to another register
+  asm volatile("vmv8r.v v8, v16");
+  // Check that the whole register was loaded
+  asm volatile("vs8r.v v8, (%0)" ::"r"(buf_vec_8b));
+  VMCMP(uint8_t, % hhu, 3, buf_vec_8b, gold_vec_8b, VLEN);
+}
+
+////////////
+// Others //
+////////////
+
+// Check with initial vl == 0
+void TEST_CASE5(void) {
+  // Initialize a golden vector
+  INIT_MEM_CNT(gold_vec_8b, VLEN / 8);
+  // Reserve space for a buffer in memory
+  INIT_MEM_ZEROES(buf_vec_8b, VLEN / 8);
+  // Set vl and vtype to super short values
+  VSET(0, e64, m2);
+  // Initialize register + neighbours to pattern value
+  VCLEAR(v16);
+  // Load a buffer from memory - whole register load
+  asm volatile("vl1re8.v v16, (%0)" ::"r"(gold_vec_8b));
+  // Move the content to another register
+  asm volatile("vmv1r.v v1, v16");
+  // Check that the whole register was loaded
+  asm volatile("vs1r.v v1, (%0)" ::"r"(buf_vec_8b));
+  VMCMP(uint8_t, % hhu, 4, buf_vec_8b, gold_vec_8b, VLEN / 8);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vmvsx.c b/apps/riscv-tests/isa/rv64uv/vmvsx.c
new file mode 100644
index 0000000..9ad5cc0
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vmvsx.c
@@ -0,0 +1,75 @@
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+
+#include "vector_macros.h"
+
+int8_t scalar_8b;
+int16_t scalar_16b;
+int32_t scalar_32b;
+int64_t scalar_64b;
+
+void TEST_CASE1() {
+  scalar_8b = 55 << 0;
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vmv.s.x v1, %0" ::"r"(scalar_8b));
+  VCMP_I8(1, v1, scalar_8b);
+
+  scalar_16b = 55 << 8;
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vmv.s.x v1, %0" ::"r"(scalar_16b));
+  VCMP_I16(2, v1, scalar_16b);
+
+  scalar_32b = 55 << 16;
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vmv.s.x v1, %0" ::"r"(scalar_32b));
+  VCMP_I32(3, v1, scalar_32b);
+
+  scalar_64b = 55 << 32;
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vmv.s.x v1, %0" ::"r"(scalar_64b));
+  VCMP_I64(4, v1, scalar_64b);
+}
+
+// Check special cases
+void TEST_CASE2() {
+  scalar_64b = 55 << 32;
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VSET(16, e64, m8);
+  asm volatile("vmv.s.x v1, %0" ::"r"(scalar_64b));
+  VSET(1, e64, m1);
+  VCMP_I64(5, v1, scalar_64b);
+
+  scalar_64b = 55 << 32;
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VSET_ZERO(e64, m1);
+  asm volatile("vmv.s.x v1, %0" ::"r"(scalar_64b));
+  VSET(1, e64, m1);
+  VCMP_I64(6, v1, 1);
+
+  scalar_64b = 55 << 32;
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VSET_ZERO(e64, m8);
+  asm volatile("vmv.s.x v1, %0" ::"r"(scalar_64b));
+  VSET(1, e64, m1);
+  VCMP_I64(7, v1, 1);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vmvxs.c b/apps/riscv-tests/isa/rv64uv/vmvxs.c
new file mode 100644
index 0000000..5d96ca5
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vmvxs.c
@@ -0,0 +1,72 @@
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+
+#include "vector_macros.h"
+
+int8_t scalar_8b;
+int16_t scalar_16b;
+int32_t scalar_32b;
+int64_t scalar_64b;
+
+void TEST_CASE1() {
+  scalar_8b = 0;
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 55 << 0, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vmv.x.s %0, v1" : "=r"(scalar_8b));
+  XCMP(1, scalar_8b, 55 << 0);
+
+  scalar_16b = 0;
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 55 << 8, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vmv.x.s %0, v1" : "=r"(scalar_16b));
+  XCMP(2, scalar_16b, 55 << 8);
+
+  scalar_32b = 0;
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 55 << 16, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vmv.x.s %0, v1" : "=r"(scalar_32b));
+  XCMP(3, scalar_32b, 55 << 16);
+
+  scalar_64b = 0;
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 55 << 30, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vmv.x.s %0, v1" : "=r"(scalar_64b));
+  XCMP(4, scalar_64b, 55 << 30);
+}
+
+// Check special cases
+void TEST_CASE2() {
+  scalar_64b = 0;
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 55 << 30, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VSET(16, e64, m8);
+  asm volatile("vmv.x.s %0, v1" : "=r"(scalar_64b));
+  XCMP(5, scalar_64b, 55 << 30);
+
+  scalar_64b = 0;
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 55 << 30, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VSET_ZERO(e64, m1);
+  asm volatile("vmv.x.s %0, v1" : "=r"(scalar_64b));
+  XCMP(6, scalar_64b, 55 << 30);
+
+  scalar_64b = 0;
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 55 << 30, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VSET_ZERO(e64, m8);
+  asm volatile("vmv.x.s %0, v1" : "=r"(scalar_64b));
+  XCMP(7, scalar_64b, 55 << 30);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vmxnor.c b/apps/riscv-tests/isa/rv64uv/vmxnor.c
new file mode 100644
index 0000000..74820c1
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vmxnor.c
@@ -0,0 +1,68 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1() {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xCD, 0xEF);
+  VLOAD_8(v3, 0x84, 0x21);
+  asm volatile("vmxnor.mm v1, v2, v3");
+  VSET(16, e8, m1);
+  VCMP_U8(1, v1, 0xB6, 0x31);
+}
+
+void TEST_CASE2() {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xCD, 0xEF);
+  VLOAD_8(v3, 0xFF, 0xFF);
+  asm volatile("vmxnor.mm v1, v2, v3");
+  VSET(16, e8, m1);
+  VCMP_U8(2, v1, 0xCD, 0xEF);
+}
+
+void TEST_CASE3() {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xCD, 0xEF);
+  VLOAD_8(v3, 0x00, 0x00);
+  asm volatile("vmxnor.mm v1, v2, v3");
+  VSET(16, e8, m1);
+  VCMP_U8(3, v1, 0x32, 0x10);
+}
+
+void TEST_CASE4() {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xCD, 0xEF);
+  VLOAD_8(v3, 0x0F, 0xF0);
+  asm volatile("vmxnor.mm v1, v2, v3");
+  VSET(16, e8, m1);
+  VCMP_U8(4, v1, 0x3D, 0xE0);
+}
+
+void TEST_CASE5() {
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 0xFF, 0xFF);
+  VLOAD_8(v2, 0xCD, 0xEF);
+  VLOAD_8(v3, 0x84, 0x21);
+  VSET(16, e8, m1);
+  asm volatile("vmxnor.mm v1, v2, v3");
+  VSET(16, e8, m1);
+  VCMP_U8(5, v1, 0xB6, 0x31);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vmxor.c b/apps/riscv-tests/isa/rv64uv/vmxor.c
new file mode 100644
index 0000000..444814a
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vmxor.c
@@ -0,0 +1,68 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1() {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xCD, 0xEF);
+  VLOAD_8(v3, 0x84, 0x21);
+  asm volatile("vmxor.mm v1, v2, v3");
+  VSET(16, e8, m1);
+  VCMP_U8(1, v1, 0x49, 0xCE);
+}
+
+void TEST_CASE2() {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xCD, 0xEF);
+  VLOAD_8(v3, 0xFF, 0xFF);
+  asm volatile("vmxor.mm v1, v2, v3");
+  VSET(16, e8, m1);
+  VCMP_U8(2, v1, 0x32, 0x10);
+}
+
+void TEST_CASE3() {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xCD, 0xEF);
+  VLOAD_8(v3, 0x00, 0x00);
+  asm volatile("vmxor.mm v1, v2, v3");
+  VSET(16, e8, m1);
+  VCMP_U8(3, v1, 0xCD, 0xEF);
+}
+
+void TEST_CASE4() {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xCD, 0xEF);
+  VLOAD_8(v3, 0x0F, 0xF0);
+  asm volatile("vmxor.mm v1, v2, v3");
+  VSET(16, e8, m1);
+  VCMP_U8(4, v1, 0xC2, 0x1F);
+}
+
+void TEST_CASE5() {
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 0xFF, 0xFF);
+  VLOAD_8(v2, 0xCD, 0xEF);
+  VLOAD_8(v3, 0x84, 0x21);
+  VSET(16, e8, m1);
+  asm volatile("vmxor.mm v1, v2, v3");
+  VSET(16, e8, m1);
+  VCMP_U8(5, v1, 0x49, 0xCE);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vnclip.c b/apps/riscv-tests/isa/rv64uv/vnclip.c
new file mode 100644
index 0000000..f66136e
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vnclip.c
@@ -0,0 +1,78 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Muhammad Ijaz
+
+#include "vector_macros.h"
+
+void TEST_CASE1() {
+  VSET(4, e8, m1);
+  VLOAD_16(v2, 800, 65535, -50, 25);
+  VLOAD_8(v4, 7, 7, 7, 7);
+  __asm__ volatile("csrw vxrm, 2");
+  __asm__ volatile("vnclip.wv v1, v2, v4");
+  VCMP_I8(1, v1, 6, 0xff, 0xff, 0);
+}
+
+void TEST_CASE2() {
+  VSET(4, e8, m1);
+  VLOAD_16(v2, 800, 65535, -50, 25);
+  VLOAD_8(v4, 7, 7, 7, 7);
+  VLOAD_8(v0, 0x5, 0, 0, 0);
+  VCLEAR(v1);
+  __asm__ volatile("csrw vxrm, 2");
+  __asm__ volatile("vnclip.wv v1, v2, v4, v0.t");
+  VCMP_I8(2, v1, 6, 0, 0xff, 0);
+}
+
+void TEST_CASE3() {
+  VSET(4, e8, m1);
+  VLOAD_16(v2, 800, 65535, -50, 25);
+  int8_t scalar = 7;
+  __asm__ volatile("csrw vxrm, 2");
+  __asm__ volatile("vnclip.wx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_I8(3, v1, 6, 0xff, 0xff, 0);
+}
+
+void TEST_CASE4() {
+  VSET(4, e8, m1);
+  VLOAD_16(v2, 800, 65535, -50, 25);
+  int8_t scalar = 7;
+  VLOAD_8(v0, 0x5, 0, 0);
+  VCLEAR(v1);
+  __asm__ volatile("csrw vxrm, 2");
+  __asm__ volatile("vnclip.wx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_I8(4, v1, 6, 0, 0xff, 0);
+}
+
+void TEST_CASE5() {
+  VSET(4, e8, m1);
+  VLOAD_16(v2, 800, 65535, -50, 25);
+  __asm__ volatile("csrw vxrm, 2");
+  __asm__ volatile("vnclip.wi v1, v2, 7");
+  VCMP_I8(5, v1, 6, 0xff, 0xff, 0);
+}
+
+void TEST_CASE6() {
+  VSET(4, e8, m1);
+  VLOAD_16(v2, 800, 65535, -50, 25);
+  VLOAD_8(v0, 0x5, 0, 0, 0);
+  VCLEAR(v1);
+  __asm__ volatile("csrw vxrm, 2");
+  __asm__ volatile("vnclip.wi v1, v2, 7, v0.t");
+  VCMP_I8(6, v1, 6, 0, 0xff, 0);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+  enable_fp();
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+  TEST_CASE6();
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vnclipu.c b/apps/riscv-tests/isa/rv64uv/vnclipu.c
new file mode 100644
index 0000000..e98ac08
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vnclipu.c
@@ -0,0 +1,78 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Muhammad Ijaz
+
+#include "vector_macros.h"
+
+void TEST_CASE1() {
+  VSET(4, e8, m1);
+  VLOAD_16(v2, 800, 65535, -50, 25);
+  VLOAD_8(v4, 7, 7, 7, 7);
+  __asm__ volatile("csrw vxrm, 2");
+  __asm__ volatile("vnclipu.wv v1, v2, v4");
+  VCMP_U8(1, v1, 6, 0xff, 0xff, 0);
+}
+
+void TEST_CASE2() {
+  VSET(4, e8, m1);
+  VLOAD_16(v2, 800, 65535, -50, 25);
+  VLOAD_8(v4, 7, 7, 7, 7);
+  VLOAD_8(v0, 0x5, 0, 0, 0);
+  VCLEAR(v1);
+  __asm__ volatile("csrw vxrm, 2");
+  __asm__ volatile("vnclipu.wv v1, v2, v4, v0.t");
+  VCMP_U8(2, v1, 6, 0, 0xff, 0);
+}
+
+void TEST_CASE3() {
+  VSET(4, e8, m1);
+  VLOAD_16(v2, 800, 65535, -50, 25);
+  int8_t scalar = 7;
+  __asm__ volatile("csrw vxrm, 2");
+  __asm__ volatile("vnclipu.wx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U8(3, v1, 6, 0xff, 0xff, 0);
+}
+
+void TEST_CASE4() {
+  VSET(4, e8, m1);
+  VLOAD_16(v2, 800, 65535, -50, 25);
+  int8_t scalar = 7;
+  VLOAD_8(v0, 0x5, 0, 0);
+  VCLEAR(v1);
+  __asm__ volatile("csrw vxrm, 2");
+  __asm__ volatile("vnclipu.wx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U8(4, v1, 6, 0, 0xff, 0);
+}
+
+void TEST_CASE5() {
+  VSET(4, e8, m1);
+  VLOAD_16(v2, 800, 65535, -50, 25);
+  __asm__ volatile("csrw vxrm, 2");
+  __asm__ volatile("vnclipu.wi v1, v2, 7");
+  VCMP_U8(5, v1, 6, 0xff, 0xff, 0);
+}
+
+void TEST_CASE6() {
+  VSET(4, e8, m1);
+  VLOAD_16(v2, 800, 65535, -50, 25);
+  VLOAD_8(v0, 0x5, 0, 0, 0);
+  VCLEAR(v1);
+  __asm__ volatile("csrw vxrm, 2");
+  __asm__ volatile("vnclipu.wi v1, v2, 7, v0.t");
+  VCMP_U8(6, v1, 6, 0, 0xff, 0);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+  enable_fp();
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+  TEST_CASE6();
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vnmsac.c b/apps/riscv-tests/isa/rv64uv/vnmsac.c
new file mode 100644
index 0000000..34909b6
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vnmsac.c
@@ -0,0 +1,292 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1() {
+  VSET(16, e8, m1);
+  VLOAD_8(v3, 0x41, 0x5b, 0xd0, 0x04, 0xc4, 0x7a, 0x91, 0xd1, 0x7b, 0x09, 0x85,
+          0x59, 0x2b, 0xe3, 0x33, 0xb9);
+  VLOAD_8(v2, 0xc5, 0x4d, 0xad, 0x35, 0x81, 0x18, 0x48, 0x50, 0xe7, 0x95, 0x7b,
+          0x18, 0xe6, 0x44, 0x57, 0xaf);
+  VLOAD_8(v1, 0x53, 0x13, 0x2c, 0xd8, 0x4a, 0xc3, 0xa3, 0xd7, 0x7e, 0x1f, 0x4c,
+          0x4e, 0x2e, 0x7d, 0x13, 0x5a);
+  asm volatile("vnmsac.vv v1, v2, v3");
+  VCMP_U8(1, v1, 0x4e, 0xb4, 0x9c, 0x04, 0x86, 0x53, 0xdb, 0x87, 0x81, 0xe2,
+          0x65, 0xf6, 0x8c, 0x31, 0xbe, 0xe3);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v3, 0x9904, 0x5982, 0xa6cb, 0x73a1, 0x227e, 0xc8f6, 0x3eeb, 0xb010,
+           0x14a1, 0xef2d, 0x3376, 0x371a, 0x4fc8, 0xbcca, 0xccd7, 0x9097);
+  VLOAD_16(v2, 0xb2dd, 0x9ca4, 0x72fe, 0xecab, 0x9909, 0xe1b0, 0x1769, 0x6759,
+           0x9500, 0x3aae, 0x0637, 0xeadc, 0x7523, 0xa53c, 0xecc7, 0xaccc);
+  VLOAD_16(v1, 0xb917, 0x6a27, 0x0f0c, 0x04a2, 0xe0b6, 0x9fb1, 0x5c69, 0x21e2,
+           0x3588, 0x8d19, 0x65d9, 0x6458, 0xfbff, 0xf949, 0x34a4, 0x0710);
+  asm volatile("vnmsac.vv v1, v2, v3");
+  VCMP_U16(2, v1, 0xd8a3, 0xdadf, 0x2ba2, 0x5c17, 0x5c48, 0x4091, 0x7106,
+           0x7c52, 0x8088, 0xca83, 0x937f, 0x4600, 0xaba7, 0x87f1, 0xc583,
+           0x5abc);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v3, 0xe6f4ff60, 0xbf6a38db, 0x30f2ea92, 0x1763619e, 0x815c1c28,
+           0x5f1b57db, 0xdb2cdc06, 0xab577f4a, 0x214746ac, 0xd3a08c15,
+           0x35887ce9, 0x9d5a0f65, 0x76adea2b, 0x91b7f299, 0x6e2977fe,
+           0xdcbcb1d7);
+  VLOAD_32(v2, 0x885c8baa, 0xbe200324, 0x9eaa49d7, 0x4e208dde, 0x802bbe9f,
+           0x7633680e, 0xf1a79717, 0xe62e371e, 0x0fc25b48, 0x11067f38,
+           0xc654ccb4, 0x6702a66c, 0x7a0b229d, 0x25c2b688, 0x82b68b3d,
+           0x4224aa5e);
+  VLOAD_32(v1, 0x3a582428, 0x61c55f94, 0xb445799b, 0xcca5a657, 0x51a7fe9e,
+           0x0840b4f8, 0xfb0a701b, 0x1b5361d7, 0xd10c9064, 0xa899d63d,
+           0xbb1779fd, 0x1b35390c, 0xd04c0f6c, 0xd8c9db62, 0x90a09dc8,
+           0x463438b4);
+  asm volatile("vnmsac.vv v1, v2, v3");
+  VCMP_U32(3, v1, 0x0e7d6e68, 0x92cacfc8, 0x726ad6fd, 0x6ff2f953, 0xe1d4d1c6,
+           0x466feefe, 0xa6512191, 0xdf6d912b, 0x7c898c04, 0x0a7ec6a5,
+           0x2121fa29, 0x91713c70, 0x60b0bd0d, 0xb3a6341a, 0x82041c42,
+           0x7a9625c2);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v3, 0xb8d79a755b98580a, 0xceefb8be6deb3a3d, 0x670688aed7c97cdd,
+           0x0ced1db5e1b7da8f, 0x58993c2ae4a62e89, 0x864439a0768dce1b,
+           0x7882d6539128d119, 0xfe6469348911945b, 0x6da189493780c328,
+           0xf8c4931b61dc54dc, 0xd5ac914ccbf735f0, 0xba0a5bf3b2b528d1,
+           0x74d814e6ebcebe81, 0xfc44af3a74cfee8c, 0xea0cb63d1bf7d5dc,
+           0xbe98c841d80bd077);
+  VLOAD_64(v2, 0x5517b401c8fbd5ec, 0x021c52c329edd200, 0xff61d899305d1423,
+           0xd886035fdcfe3186, 0x694b857cb1cc3bc3, 0x52376b9a996e1925,
+           0x5785c45d41ec230d, 0x950f08c23f6da73d, 0xe5dc4e9a35834719,
+           0x9a08d0e965e96a19, 0xb80c2107151bdcf6, 0xd0612e4d4bc314b7,
+           0xdfb23a142b750482, 0xedc5e4b79881bdaf, 0x72c493d9df55bf13,
+           0xfd4b1328b8f7773a);
+  VLOAD_64(v1, 0xc265b2d19ad92bbb, 0x81a4ef527fc2e042, 0xe490f5981f64a313,
+           0xf12edb410132b013, 0xc475df4b52276fe9, 0x069e283bf74ca195,
+           0x8dd5189f3a66f166, 0x297726422e620380, 0x7b74d167bd1b22fd,
+           0x08e88e9642656a52, 0x0ab0c3f0f7ddeb66, 0x00b155918c8646c0,
+           0x84d4df4b2a3768c7, 0xc31234734867ae09, 0x79320b8da693a84e,
+           0x30727b2d1bccd396);
+  asm volatile("vnmsac.vv v1, v2, v3");
+  VCMP_U64(4, v1, 0x231a763b4759b083, 0x68b16397da83d642, 0x7081592414ce4cdc,
+           0x084dc189ec3eea39, 0x72cb55f70cac6a8e, 0xc713321c491334ae,
+           0xa21580bb2ab1e821, 0x3d84da5e7dab4cd1, 0x735a758175effc15,
+           0x91e8df24708208d6, 0x5133f0cd25a5d6c6, 0x2f1a889653a2c559,
+           0x5f9f0ac7744ba745, 0xba1bbac1969a4055, 0x275025160493a4fa,
+           0x21c02801006747a0);
+}
+
+void TEST_CASE2() {
+  VSET(16, e8, m1);
+  VLOAD_8(v3, 0x41, 0x5b, 0xd0, 0x04, 0xc4, 0x7a, 0x91, 0xd1, 0x7b, 0x09, 0x85,
+          0x59, 0x2b, 0xe3, 0x33, 0xb9);
+  VLOAD_8(v2, 0xc5, 0x4d, 0xad, 0x35, 0x81, 0x18, 0x48, 0x50, 0xe7, 0x95, 0x7b,
+          0x18, 0xe6, 0x44, 0x57, 0xaf);
+  VLOAD_8(v1, 0x53, 0x13, 0x2c, 0xd8, 0x4a, 0xc3, 0xa3, 0xd7, 0x7e, 0x1f, 0x4c,
+          0x4e, 0x2e, 0x7d, 0x13, 0x5a);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vnmsac.vv v1, v2, v3, v0.t");
+  VCMP_U8(5, v1, 0x53, 0xb4, 0x2c, 0x04, 0x4a, 0x53, 0xa3, 0x87, 0x7e, 0xe2,
+          0x4c, 0xf6, 0x2e, 0x31, 0x13, 0xe3);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v3, 0x9904, 0x5982, 0xa6cb, 0x73a1, 0x227e, 0xc8f6, 0x3eeb, 0xb010,
+           0x14a1, 0xef2d, 0x3376, 0x371a, 0x4fc8, 0xbcca, 0xccd7, 0x9097);
+  VLOAD_16(v2, 0xb2dd, 0x9ca4, 0x72fe, 0xecab, 0x9909, 0xe1b0, 0x1769, 0x6759,
+           0x9500, 0x3aae, 0x0637, 0xeadc, 0x7523, 0xa53c, 0xecc7, 0xaccc);
+  VLOAD_16(v1, 0xb917, 0x6a27, 0x0f0c, 0x04a2, 0xe0b6, 0x9fb1, 0x5c69, 0x21e2,
+           0x3588, 0x8d19, 0x65d9, 0x6458, 0xfbff, 0xf949, 0x34a4, 0x0710);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vnmsac.vv v1, v2, v3, v0.t");
+  VCMP_U16(6, v1, 0xb917, 0xdadf, 0x0f0c, 0x5c17, 0xe0b6, 0x4091, 0x5c69,
+           0x7c52, 0x3588, 0xca83, 0x65d9, 0x4600, 0xfbff, 0x87f1, 0x34a4,
+           0x5abc);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v3, 0xe6f4ff60, 0xbf6a38db, 0x30f2ea92, 0x1763619e, 0x815c1c28,
+           0x5f1b57db, 0xdb2cdc06, 0xab577f4a, 0x214746ac, 0xd3a08c15,
+           0x35887ce9, 0x9d5a0f65, 0x76adea2b, 0x91b7f299, 0x6e2977fe,
+           0xdcbcb1d7);
+  VLOAD_32(v2, 0x885c8baa, 0xbe200324, 0x9eaa49d7, 0x4e208dde, 0x802bbe9f,
+           0x7633680e, 0xf1a79717, 0xe62e371e, 0x0fc25b48, 0x11067f38,
+           0xc654ccb4, 0x6702a66c, 0x7a0b229d, 0x25c2b688, 0x82b68b3d,
+           0x4224aa5e);
+  VLOAD_32(v1, 0x3a582428, 0x61c55f94, 0xb445799b, 0xcca5a657, 0x51a7fe9e,
+           0x0840b4f8, 0xfb0a701b, 0x1b5361d7, 0xd10c9064, 0xa899d63d,
+           0xbb1779fd, 0x1b35390c, 0xd04c0f6c, 0xd8c9db62, 0x90a09dc8,
+           0x463438b4);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vnmsac.vv v1, v2, v3, v0.t");
+  VCMP_U32(7, v1, 0x3a582428, 0x92cacfc8, 0xb445799b, 0x6ff2f953, 0x51a7fe9e,
+           0x466feefe, 0xfb0a701b, 0xdf6d912b, 0xd10c9064, 0x0a7ec6a5,
+           0xbb1779fd, 0x91713c70, 0xd04c0f6c, 0xb3a6341a, 0x90a09dc8,
+           0x7a9625c2);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v3, 0xb8d79a755b98580a, 0xceefb8be6deb3a3d, 0x670688aed7c97cdd,
+           0x0ced1db5e1b7da8f, 0x58993c2ae4a62e89, 0x864439a0768dce1b,
+           0x7882d6539128d119, 0xfe6469348911945b, 0x6da189493780c328,
+           0xf8c4931b61dc54dc, 0xd5ac914ccbf735f0, 0xba0a5bf3b2b528d1,
+           0x74d814e6ebcebe81, 0xfc44af3a74cfee8c, 0xea0cb63d1bf7d5dc,
+           0xbe98c841d80bd077);
+  VLOAD_64(v2, 0x5517b401c8fbd5ec, 0x021c52c329edd200, 0xff61d899305d1423,
+           0xd886035fdcfe3186, 0x694b857cb1cc3bc3, 0x52376b9a996e1925,
+           0x5785c45d41ec230d, 0x950f08c23f6da73d, 0xe5dc4e9a35834719,
+           0x9a08d0e965e96a19, 0xb80c2107151bdcf6, 0xd0612e4d4bc314b7,
+           0xdfb23a142b750482, 0xedc5e4b79881bdaf, 0x72c493d9df55bf13,
+           0xfd4b1328b8f7773a);
+  VLOAD_64(v1, 0xc265b2d19ad92bbb, 0x81a4ef527fc2e042, 0xe490f5981f64a313,
+           0xf12edb410132b013, 0xc475df4b52276fe9, 0x069e283bf74ca195,
+           0x8dd5189f3a66f166, 0x297726422e620380, 0x7b74d167bd1b22fd,
+           0x08e88e9642656a52, 0x0ab0c3f0f7ddeb66, 0x00b155918c8646c0,
+           0x84d4df4b2a3768c7, 0xc31234734867ae09, 0x79320b8da693a84e,
+           0x30727b2d1bccd396);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vnmsac.vv v1, v2, v3, v0.t");
+  VCMP_U64(8, v1, 0xc265b2d19ad92bbb, 0x68b16397da83d642, 0xe490f5981f64a313,
+           0x084dc189ec3eea39, 0xc475df4b52276fe9, 0xc713321c491334ae,
+           0x8dd5189f3a66f166, 0x3d84da5e7dab4cd1, 0x7b74d167bd1b22fd,
+           0x91e8df24708208d6, 0x0ab0c3f0f7ddeb66, 0x2f1a889653a2c559,
+           0x84d4df4b2a3768c7, 0xba1bbac1969a4055, 0x79320b8da693a84e,
+           0x21c02801006747a0);
+}
+
+void TEST_CASE3() {
+  VSET(16, e8, m1);
+  int64_t scalar = 5;
+  VLOAD_8(v3, 0x5e, 0xf5, 0xa9, 0x0b, 0x14, 0x3c, 0x84, 0x22, 0xd7, 0xb6, 0x5c,
+          0x90, 0xa2, 0x67, 0x3d, 0xf5);
+  VLOAD_8(v1, 0xfa, 0xd9, 0x2a, 0xe2, 0xe7, 0x1f, 0x8c, 0xbd, 0x40, 0x5d, 0x50,
+          0x1f, 0xe0, 0xdd, 0x1f, 0xd7);
+  asm volatile("vnmsac.vx v1, %[A], v3" ::[A] "r"(scalar));
+  VCMP_U8(9, v1, 0x24, 0x10, 0xdd, 0xab, 0x83, 0xf3, 0xf8, 0x13, 0x0d, 0xcf,
+          0x84, 0x4f, 0xb6, 0xda, 0xee, 0x0e);
+
+  VSET(16, e16, m1);
+  scalar = -5383;
+  VLOAD_16(v3, 0xfe80, 0x3910, 0x5313, 0xefef, 0xecfc, 0x7983, 0xcc0d, 0x731f,
+           0xf384, 0xfde3, 0x9cd1, 0xf20b, 0xa41b, 0x949a, 0x5886, 0xa1a9);
+  VLOAD_16(v1, 0xe886, 0xf1f9, 0x1857, 0xd0bb, 0x522e, 0x2de0, 0xa6c2, 0xd624,
+           0xd024, 0x40a2, 0xdd99, 0xd517, 0xf00a, 0xae8d, 0x79a5, 0x519d);
+  asm volatile("vnmsac.vx v1, %[A], v3" ::[A] "r"(scalar));
+  VCMP_U16(10, v1, 0x5e06, 0xd169, 0xecdc, 0xfb44, 0x7912, 0x3f75, 0x4c1d,
+           0x86fd, 0x4cc0, 0xd0d7, 0x4c50, 0x5a64, 0xa3c7, 0x60c3, 0xe34f,
+           0x9a3c);
+
+  VSET(16, e32, m1);
+  scalar = 6474219;
+  VLOAD_32(v3, 0x48da7aac, 0x54e98600, 0xf49f26e5, 0x338e8406, 0x40ca82f5,
+           0x75d0b8f6, 0x38c88af2, 0x96bb5c03, 0x6f61c0a9, 0x3626dd69,
+           0x31aba619, 0x7d974a55, 0xbc63c280, 0x502334bf, 0x9451b955,
+           0x6a8bae19);
+  VLOAD_32(v1, 0xcbd8537e, 0x36928a6c, 0x60cf8444, 0xa19ea650, 0x8f2a8694,
+           0x050956bf, 0x1ef799f5, 0x43c0f327, 0x4bfd5a25, 0x7be439e4,
+           0xed89a52a, 0x2bbf028d, 0x872392b9, 0x0ad55495, 0x865c7264,
+           0xfcce4b64);
+  asm volatile("vnmsac.vx v1, %[A], v3" ::[A] "r"(scalar));
+  VCMP_U32(11, v1, 0x6b20ab9a, 0x9dfe886c, 0xf983030d, 0xddd6bece, 0xf2a7f2ad,
+           0x2f0a66ed, 0x59240bcf, 0x915f2166, 0x8c4ace02, 0x802d8981,
+           0xf9fc8b37, 0xa3f70986, 0xced98739, 0xa4fbf240, 0x4249945d,
+           0xdd51d971);
+
+  VSET(16, e64, m1);
+  scalar = -598189234597999223;
+  VLOAD_64(v3, 0x93adc14539897782, 0xa8d5d41c19b1455a, 0x55e01165195d2d9b,
+           0xe81a26a17fef30f2, 0x33a71ede19aec0aa, 0x49598be14c5bc1cd,
+           0x1c27bde3f488bfc6, 0x4188f9b8611e5d90, 0xd53289cca28a3b6b,
+           0x3b435e1078e3bee9, 0x5e3f4c08c869abf4, 0x3c004920e9c39fb6,
+           0x4b42a451b264b153, 0x110a6db11a7c2801, 0x7c0f358ac41d49fa,
+           0x6e8c6ae4d14bd1a5);
+  VLOAD_64(v1, 0x3b0c6a3a651beecc, 0xb612caa033bc9bca, 0xda94340ac428ca78,
+           0xf774b16ef94a22ea, 0x87df3c47c8113e43, 0x38487d57a064f677,
+           0x358706b57ce6d6c7, 0xda111b3ac946811c, 0xe9ffed5b39f1ea1d,
+           0x3c7e5a675c779870, 0x5d2ea63ac910e42e, 0xb3e832dbe2332203,
+           0x05d366b426005f47, 0x00b3b58815a860d8, 0x023bbf8109263e1d,
+           0x5fbc2f647d6c1153);
+  asm volatile("vnmsac.vx v1, %[A], v3" ::[A] "r"(scalar));
+  VCMP_U64(12, v1, 0x60dd7609c833e03a, 0x79abe3a30a816ca0, 0x983ca4c97f204385,
+           0x59a9303f04932768, 0x59c29659b4d00149, 0x59a15b1bb66f16c2,
+           0x37b0445a8ebaa7d1, 0x65e0c3ab56fa1f0c, 0x94a740971b1d6eda,
+           0xa1c7ff743113d8bf, 0xe8198a4799a97a9a, 0x5ccf06fd8751eb9d,
+           0xa36557d05e8802dc, 0x10aae67f31dc2b4f, 0xe878939fd1287553,
+           0x594538a8571dbf06);
+}
+
+void TEST_CASE4() {
+  VSET(16, e8, m1);
+  int64_t scalar = 5;
+  VLOAD_8(v3, 0x5e, 0xf5, 0xa9, 0x0b, 0x14, 0x3c, 0x84, 0x22, 0xd7, 0xb6, 0x5c,
+          0x90, 0xa2, 0x67, 0x3d, 0xf5);
+  VLOAD_8(v1, 0xfa, 0xd9, 0x2a, 0xe2, 0xe7, 0x1f, 0x8c, 0xbd, 0x40, 0x5d, 0x50,
+          0x1f, 0xe0, 0xdd, 0x1f, 0xd7);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vnmsac.vx v1, %[A], v3, v0.t" ::[A] "r"(scalar));
+  VCMP_U8(13, v1, 0xfa, 0x10, 0x2a, 0xab, 0xe7, 0xf3, 0x8c, 0x13, 0x40, 0xcf,
+          0x50, 0x4f, 0xe0, 0xda, 0x1f, 0x0e);
+
+  VSET(16, e16, m1);
+  scalar = -5383;
+  VLOAD_16(v3, 0xfe80, 0x3910, 0x5313, 0xefef, 0xecfc, 0x7983, 0xcc0d, 0x731f,
+           0xf384, 0xfde3, 0x9cd1, 0xf20b, 0xa41b, 0x949a, 0x5886, 0xa1a9);
+  VLOAD_16(v1, 0xe886, 0xf1f9, 0x1857, 0xd0bb, 0x522e, 0x2de0, 0xa6c2, 0xd624,
+           0xd024, 0x40a2, 0xdd99, 0xd517, 0xf00a, 0xae8d, 0x79a5, 0x519d);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vnmsac.vx v1, %[A], v3, v0.t" ::[A] "r"(scalar));
+  VCMP_U16(14, v1, 0xe886, 0xd169, 0x1857, 0xfb44, 0x522e, 0x3f75, 0xa6c2,
+           0x86fd, 0xd024, 0xd0d7, 0xdd99, 0x5a64, 0xf00a, 0x60c3, 0x79a5,
+           0x9a3c);
+
+  VSET(16, e32, m1);
+  scalar = 6474219;
+  VLOAD_32(v3, 0x48da7aac, 0x54e98600, 0xf49f26e5, 0x338e8406, 0x40ca82f5,
+           0x75d0b8f6, 0x38c88af2, 0x96bb5c03, 0x6f61c0a9, 0x3626dd69,
+           0x31aba619, 0x7d974a55, 0xbc63c280, 0x502334bf, 0x9451b955,
+           0x6a8bae19);
+  VLOAD_32(v1, 0xcbd8537e, 0x36928a6c, 0x60cf8444, 0xa19ea650, 0x8f2a8694,
+           0x050956bf, 0x1ef799f5, 0x43c0f327, 0x4bfd5a25, 0x7be439e4,
+           0xed89a52a, 0x2bbf028d, 0x872392b9, 0x0ad55495, 0x865c7264,
+           0xfcce4b64);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vnmsac.vx v1, %[A], v3, v0.t" ::[A] "r"(scalar));
+  VCMP_U32(15, v1, 0xcbd8537e, 0x9dfe886c, 0x60cf8444, 0xddd6bece, 0x8f2a8694,
+           0x2f0a66ed, 0x1ef799f5, 0x915f2166, 0x4bfd5a25, 0x802d8981,
+           0xed89a52a, 0xa3f70986, 0x872392b9, 0xa4fbf240, 0x865c7264,
+           0xdd51d971);
+
+  VSET(16, e64, m1);
+  scalar = -598189234597999223;
+  VLOAD_64(v3, 0x93adc14539897782, 0xa8d5d41c19b1455a, 0x55e01165195d2d9b,
+           0xe81a26a17fef30f2, 0x33a71ede19aec0aa, 0x49598be14c5bc1cd,
+           0x1c27bde3f488bfc6, 0x4188f9b8611e5d90, 0xd53289cca28a3b6b,
+           0x3b435e1078e3bee9, 0x5e3f4c08c869abf4, 0x3c004920e9c39fb6,
+           0x4b42a451b264b153, 0x110a6db11a7c2801, 0x7c0f358ac41d49fa,
+           0x6e8c6ae4d14bd1a5);
+  VLOAD_64(v1, 0x3b0c6a3a651beecc, 0xb612caa033bc9bca, 0xda94340ac428ca78,
+           0xf774b16ef94a22ea, 0x87df3c47c8113e43, 0x38487d57a064f677,
+           0x358706b57ce6d6c7, 0xda111b3ac946811c, 0xe9ffed5b39f1ea1d,
+           0x3c7e5a675c779870, 0x5d2ea63ac910e42e, 0xb3e832dbe2332203,
+           0x05d366b426005f47, 0x00b3b58815a860d8, 0x023bbf8109263e1d,
+           0x5fbc2f647d6c1153);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vnmsac.vx v1, %[A], v3, v0.t" ::[A] "r"(scalar));
+  VCMP_U64(16, v1, 0x3b0c6a3a651beecc, 0x79abe3a30a816ca0, 0xda94340ac428ca78,
+           0x59a9303f04932768, 0x87df3c47c8113e43, 0x59a15b1bb66f16c2,
+           0x358706b57ce6d6c7, 0x65e0c3ab56fa1f0c, 0xe9ffed5b39f1ea1d,
+           0xa1c7ff743113d8bf, 0x5d2ea63ac910e42e, 0x5ccf06fd8751eb9d,
+           0x05d366b426005f47, 0x10aae67f31dc2b4f, 0x023bbf8109263e1d,
+           0x594538a8571dbf06);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vnmsub.c b/apps/riscv-tests/isa/rv64uv/vnmsub.c
new file mode 100644
index 0000000..48a8b48
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vnmsub.c
@@ -0,0 +1,292 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1() {
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 0x41, 0x5b, 0xd0, 0x04, 0xc4, 0x7a, 0x91, 0xd1, 0x7b, 0x09, 0x85,
+          0x59, 0x2b, 0xe3, 0x33, 0xb9);
+  VLOAD_8(v2, 0xc5, 0x4d, 0xad, 0x35, 0x81, 0x18, 0x48, 0x50, 0xe7, 0x95, 0x7b,
+          0x18, 0xe6, 0x44, 0x57, 0xaf);
+  VLOAD_8(v3, 0x53, 0x13, 0x2c, 0xd8, 0x4a, 0xc3, 0xa3, 0xd7, 0x7e, 0x1f, 0x4c,
+          0x4e, 0x2e, 0x7d, 0x13, 0x5a);
+  asm volatile("vnmsub.vv v1, v2, v3");
+  VCMP_U8(1, v1, 0x4e, 0xb4, 0x9c, 0x04, 0x86, 0x53, 0xdb, 0x87, 0x81, 0xe2,
+          0x65, 0xf6, 0x8c, 0x31, 0xbe, 0xe3);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 0x9904, 0x5982, 0xa6cb, 0x73a1, 0x227e, 0xc8f6, 0x3eeb, 0xb010,
+           0x14a1, 0xef2d, 0x3376, 0x371a, 0x4fc8, 0xbcca, 0xccd7, 0x9097);
+  VLOAD_16(v2, 0xb2dd, 0x9ca4, 0x72fe, 0xecab, 0x9909, 0xe1b0, 0x1769, 0x6759,
+           0x9500, 0x3aae, 0x0637, 0xeadc, 0x7523, 0xa53c, 0xecc7, 0xaccc);
+  VLOAD_16(v3, 0xb917, 0x6a27, 0x0f0c, 0x04a2, 0xe0b6, 0x9fb1, 0x5c69, 0x21e2,
+           0x3588, 0x8d19, 0x65d9, 0x6458, 0xfbff, 0xf949, 0x34a4, 0x0710);
+  asm volatile("vnmsub.vv v1, v2, v3");
+  VCMP_U16(2, v1, 0xd8a3, 0xdadf, 0x2ba2, 0x5c17, 0x5c48, 0x4091, 0x7106,
+           0x7c52, 0x8088, 0xca83, 0x937f, 0x4600, 0xaba7, 0x87f1, 0xc583,
+           0x5abc);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 0xe6f4ff60, 0xbf6a38db, 0x30f2ea92, 0x1763619e, 0x815c1c28,
+           0x5f1b57db, 0xdb2cdc06, 0xab577f4a, 0x214746ac, 0xd3a08c15,
+           0x35887ce9, 0x9d5a0f65, 0x76adea2b, 0x91b7f299, 0x6e2977fe,
+           0xdcbcb1d7);
+  VLOAD_32(v2, 0x885c8baa, 0xbe200324, 0x9eaa49d7, 0x4e208dde, 0x802bbe9f,
+           0x7633680e, 0xf1a79717, 0xe62e371e, 0x0fc25b48, 0x11067f38,
+           0xc654ccb4, 0x6702a66c, 0x7a0b229d, 0x25c2b688, 0x82b68b3d,
+           0x4224aa5e);
+  VLOAD_32(v3, 0x3a582428, 0x61c55f94, 0xb445799b, 0xcca5a657, 0x51a7fe9e,
+           0x0840b4f8, 0xfb0a701b, 0x1b5361d7, 0xd10c9064, 0xa899d63d,
+           0xbb1779fd, 0x1b35390c, 0xd04c0f6c, 0xd8c9db62, 0x90a09dc8,
+           0x463438b4);
+  asm volatile("vnmsub.vv v1, v2, v3");
+  VCMP_U32(3, v1, 0x0e7d6e68, 0x92cacfc8, 0x726ad6fd, 0x6ff2f953, 0xe1d4d1c6,
+           0x466feefe, 0xa6512191, 0xdf6d912b, 0x7c898c04, 0x0a7ec6a5,
+           0x2121fa29, 0x91713c70, 0x60b0bd0d, 0xb3a6341a, 0x82041c42,
+           0x7a9625c2);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 0xb8d79a755b98580a, 0xceefb8be6deb3a3d, 0x670688aed7c97cdd,
+           0x0ced1db5e1b7da8f, 0x58993c2ae4a62e89, 0x864439a0768dce1b,
+           0x7882d6539128d119, 0xfe6469348911945b, 0x6da189493780c328,
+           0xf8c4931b61dc54dc, 0xd5ac914ccbf735f0, 0xba0a5bf3b2b528d1,
+           0x74d814e6ebcebe81, 0xfc44af3a74cfee8c, 0xea0cb63d1bf7d5dc,
+           0xbe98c841d80bd077);
+  VLOAD_64(v2, 0x5517b401c8fbd5ec, 0x021c52c329edd200, 0xff61d899305d1423,
+           0xd886035fdcfe3186, 0x694b857cb1cc3bc3, 0x52376b9a996e1925,
+           0x5785c45d41ec230d, 0x950f08c23f6da73d, 0xe5dc4e9a35834719,
+           0x9a08d0e965e96a19, 0xb80c2107151bdcf6, 0xd0612e4d4bc314b7,
+           0xdfb23a142b750482, 0xedc5e4b79881bdaf, 0x72c493d9df55bf13,
+           0xfd4b1328b8f7773a);
+  VLOAD_64(v3, 0xc265b2d19ad92bbb, 0x81a4ef527fc2e042, 0xe490f5981f64a313,
+           0xf12edb410132b013, 0xc475df4b52276fe9, 0x069e283bf74ca195,
+           0x8dd5189f3a66f166, 0x297726422e620380, 0x7b74d167bd1b22fd,
+           0x08e88e9642656a52, 0x0ab0c3f0f7ddeb66, 0x00b155918c8646c0,
+           0x84d4df4b2a3768c7, 0xc31234734867ae09, 0x79320b8da693a84e,
+           0x30727b2d1bccd396);
+  asm volatile("vnmsub.vv v1, v2, v3");
+  VCMP_U64(4, v1, 0x231a763b4759b083, 0x68b16397da83d642, 0x7081592414ce4cdc,
+           0x084dc189ec3eea39, 0x72cb55f70cac6a8e, 0xc713321c491334ae,
+           0xa21580bb2ab1e821, 0x3d84da5e7dab4cd1, 0x735a758175effc15,
+           0x91e8df24708208d6, 0x5133f0cd25a5d6c6, 0x2f1a889653a2c559,
+           0x5f9f0ac7744ba745, 0xba1bbac1969a4055, 0x275025160493a4fa,
+           0x21c02801006747a0);
+}
+
+void TEST_CASE2() {
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 0x41, 0x5b, 0xd0, 0x04, 0xc4, 0x7a, 0x91, 0xd1, 0x7b, 0x09, 0x85,
+          0x59, 0x2b, 0xe3, 0x33, 0xb9);
+  VLOAD_8(v2, 0xc5, 0x4d, 0xad, 0x35, 0x81, 0x18, 0x48, 0x50, 0xe7, 0x95, 0x7b,
+          0x18, 0xe6, 0x44, 0x57, 0xaf);
+  VLOAD_8(v3, 0x53, 0x13, 0x2c, 0xd8, 0x4a, 0xc3, 0xa3, 0xd7, 0x7e, 0x1f, 0x4c,
+          0x4e, 0x2e, 0x7d, 0x13, 0x5a);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vnmsub.vv v1, v2, v3, v0.t");
+  VCMP_U8(5, v1, 0x41, 0xb4, 0xd0, 0x04, 0xc4, 0x53, 0x91, 0x87, 0x7b, 0xe2,
+          0x85, 0xf6, 0x2b, 0x31, 0x33, 0xe3);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 0x9904, 0x5982, 0xa6cb, 0x73a1, 0x227e, 0xc8f6, 0x3eeb, 0xb010,
+           0x14a1, 0xef2d, 0x3376, 0x371a, 0x4fc8, 0xbcca, 0xccd7, 0x9097);
+  VLOAD_16(v2, 0xb2dd, 0x9ca4, 0x72fe, 0xecab, 0x9909, 0xe1b0, 0x1769, 0x6759,
+           0x9500, 0x3aae, 0x0637, 0xeadc, 0x7523, 0xa53c, 0xecc7, 0xaccc);
+  VLOAD_16(v3, 0xb917, 0x6a27, 0x0f0c, 0x04a2, 0xe0b6, 0x9fb1, 0x5c69, 0x21e2,
+           0x3588, 0x8d19, 0x65d9, 0x6458, 0xfbff, 0xf949, 0x34a4, 0x0710);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vnmsub.vv v1, v2, v3, v0.t");
+  VCMP_U16(6, v1, 0x9904, 0xdadf, 0xa6cb, 0x5c17, 0x227e, 0x4091, 0x3eeb,
+           0x7c52, 0x14a1, 0xca83, 0x3376, 0x4600, 0x4fc8, 0x87f1, 0xccd7,
+           0x5abc);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 0xe6f4ff60, 0xbf6a38db, 0x30f2ea92, 0x1763619e, 0x815c1c28,
+           0x5f1b57db, 0xdb2cdc06, 0xab577f4a, 0x214746ac, 0xd3a08c15,
+           0x35887ce9, 0x9d5a0f65, 0x76adea2b, 0x91b7f299, 0x6e2977fe,
+           0xdcbcb1d7);
+  VLOAD_32(v2, 0x885c8baa, 0xbe200324, 0x9eaa49d7, 0x4e208dde, 0x802bbe9f,
+           0x7633680e, 0xf1a79717, 0xe62e371e, 0x0fc25b48, 0x11067f38,
+           0xc654ccb4, 0x6702a66c, 0x7a0b229d, 0x25c2b688, 0x82b68b3d,
+           0x4224aa5e);
+  VLOAD_32(v3, 0x3a582428, 0x61c55f94, 0xb445799b, 0xcca5a657, 0x51a7fe9e,
+           0x0840b4f8, 0xfb0a701b, 0x1b5361d7, 0xd10c9064, 0xa899d63d,
+           0xbb1779fd, 0x1b35390c, 0xd04c0f6c, 0xd8c9db62, 0x90a09dc8,
+           0x463438b4);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vnmsub.vv v1, v2, v3, v0.t");
+  VCMP_U32(7, v1, 0xe6f4ff60, 0x92cacfc8, 0x30f2ea92, 0x6ff2f953, 0x815c1c28,
+           0x466feefe, 0xdb2cdc06, 0xdf6d912b, 0x214746ac, 0x0a7ec6a5,
+           0x35887ce9, 0x91713c70, 0x76adea2b, 0xb3a6341a, 0x6e2977fe,
+           0x7a9625c2);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 0xb8d79a755b98580a, 0xceefb8be6deb3a3d, 0x670688aed7c97cdd,
+           0x0ced1db5e1b7da8f, 0x58993c2ae4a62e89, 0x864439a0768dce1b,
+           0x7882d6539128d119, 0xfe6469348911945b, 0x6da189493780c328,
+           0xf8c4931b61dc54dc, 0xd5ac914ccbf735f0, 0xba0a5bf3b2b528d1,
+           0x74d814e6ebcebe81, 0xfc44af3a74cfee8c, 0xea0cb63d1bf7d5dc,
+           0xbe98c841d80bd077);
+  VLOAD_64(v2, 0x5517b401c8fbd5ec, 0x021c52c329edd200, 0xff61d899305d1423,
+           0xd886035fdcfe3186, 0x694b857cb1cc3bc3, 0x52376b9a996e1925,
+           0x5785c45d41ec230d, 0x950f08c23f6da73d, 0xe5dc4e9a35834719,
+           0x9a08d0e965e96a19, 0xb80c2107151bdcf6, 0xd0612e4d4bc314b7,
+           0xdfb23a142b750482, 0xedc5e4b79881bdaf, 0x72c493d9df55bf13,
+           0xfd4b1328b8f7773a);
+  VLOAD_64(v3, 0xc265b2d19ad92bbb, 0x81a4ef527fc2e042, 0xe490f5981f64a313,
+           0xf12edb410132b013, 0xc475df4b52276fe9, 0x069e283bf74ca195,
+           0x8dd5189f3a66f166, 0x297726422e620380, 0x7b74d167bd1b22fd,
+           0x08e88e9642656a52, 0x0ab0c3f0f7ddeb66, 0x00b155918c8646c0,
+           0x84d4df4b2a3768c7, 0xc31234734867ae09, 0x79320b8da693a84e,
+           0x30727b2d1bccd396);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vnmsub.vv v1, v2, v3, v0.t");
+  VCMP_U64(8, v1, 0xb8d79a755b98580a, 0x68b16397da83d642, 0x670688aed7c97cdd,
+           0x084dc189ec3eea39, 0x58993c2ae4a62e89, 0xc713321c491334ae,
+           0x7882d6539128d119, 0x3d84da5e7dab4cd1, 0x6da189493780c328,
+           0x91e8df24708208d6, 0xd5ac914ccbf735f0, 0x2f1a889653a2c559,
+           0x74d814e6ebcebe81, 0xba1bbac1969a4055, 0xea0cb63d1bf7d5dc,
+           0x21c02801006747a0);
+}
+
+void TEST_CASE3() {
+  VSET(16, e8, m1);
+  int64_t scalar = 5;
+  VLOAD_8(v1, 0x5e, 0xf5, 0xa9, 0x0b, 0x14, 0x3c, 0x84, 0x22, 0xd7, 0xb6, 0x5c,
+          0x90, 0xa2, 0x67, 0x3d, 0xf5);
+  VLOAD_8(v3, 0xfa, 0xd9, 0x2a, 0xe2, 0xe7, 0x1f, 0x8c, 0xbd, 0x40, 0x5d, 0x50,
+          0x1f, 0xe0, 0xdd, 0x1f, 0xd7);
+  asm volatile("vnmsub.vx v1, %[A], v3" ::[A] "r"(scalar));
+  VCMP_U8(9, v1, 0x24, 0x10, 0xdd, 0xab, 0x83, 0xf3, 0xf8, 0x13, 0x0d, 0xcf,
+          0x84, 0x4f, 0xb6, 0xda, 0xee, 0x0e);
+
+  VSET(16, e16, m1);
+  scalar = -5383;
+  VLOAD_16(v1, 0xfe80, 0x3910, 0x5313, 0xefef, 0xecfc, 0x7983, 0xcc0d, 0x731f,
+           0xf384, 0xfde3, 0x9cd1, 0xf20b, 0xa41b, 0x949a, 0x5886, 0xa1a9);
+  VLOAD_16(v3, 0xe886, 0xf1f9, 0x1857, 0xd0bb, 0x522e, 0x2de0, 0xa6c2, 0xd624,
+           0xd024, 0x40a2, 0xdd99, 0xd517, 0xf00a, 0xae8d, 0x79a5, 0x519d);
+  asm volatile("vnmsub.vx v1, %[A], v3" ::[A] "r"(scalar));
+  VCMP_U16(10, v1, 0x5e06, 0xd169, 0xecdc, 0xfb44, 0x7912, 0x3f75, 0x4c1d,
+           0x86fd, 0x4cc0, 0xd0d7, 0x4c50, 0x5a64, 0xa3c7, 0x60c3, 0xe34f,
+           0x9a3c);
+
+  VSET(16, e32, m1);
+  scalar = 6474219;
+  VLOAD_32(v1, 0x48da7aac, 0x54e98600, 0xf49f26e5, 0x338e8406, 0x40ca82f5,
+           0x75d0b8f6, 0x38c88af2, 0x96bb5c03, 0x6f61c0a9, 0x3626dd69,
+           0x31aba619, 0x7d974a55, 0xbc63c280, 0x502334bf, 0x9451b955,
+           0x6a8bae19);
+  VLOAD_32(v3, 0xcbd8537e, 0x36928a6c, 0x60cf8444, 0xa19ea650, 0x8f2a8694,
+           0x050956bf, 0x1ef799f5, 0x43c0f327, 0x4bfd5a25, 0x7be439e4,
+           0xed89a52a, 0x2bbf028d, 0x872392b9, 0x0ad55495, 0x865c7264,
+           0xfcce4b64);
+  asm volatile("vnmsub.vx v1, %[A], v3" ::[A] "r"(scalar));
+  VCMP_U32(11, v1, 0x6b20ab9a, 0x9dfe886c, 0xf983030d, 0xddd6bece, 0xf2a7f2ad,
+           0x2f0a66ed, 0x59240bcf, 0x915f2166, 0x8c4ace02, 0x802d8981,
+           0xf9fc8b37, 0xa3f70986, 0xced98739, 0xa4fbf240, 0x4249945d,
+           0xdd51d971);
+
+  VSET(16, e64, m1);
+  scalar = -598189234597999223;
+  VLOAD_64(v1, 0x93adc14539897782, 0xa8d5d41c19b1455a, 0x55e01165195d2d9b,
+           0xe81a26a17fef30f2, 0x33a71ede19aec0aa, 0x49598be14c5bc1cd,
+           0x1c27bde3f488bfc6, 0x4188f9b8611e5d90, 0xd53289cca28a3b6b,
+           0x3b435e1078e3bee9, 0x5e3f4c08c869abf4, 0x3c004920e9c39fb6,
+           0x4b42a451b264b153, 0x110a6db11a7c2801, 0x7c0f358ac41d49fa,
+           0x6e8c6ae4d14bd1a5);
+  VLOAD_64(v3, 0x3b0c6a3a651beecc, 0xb612caa033bc9bca, 0xda94340ac428ca78,
+           0xf774b16ef94a22ea, 0x87df3c47c8113e43, 0x38487d57a064f677,
+           0x358706b57ce6d6c7, 0xda111b3ac946811c, 0xe9ffed5b39f1ea1d,
+           0x3c7e5a675c779870, 0x5d2ea63ac910e42e, 0xb3e832dbe2332203,
+           0x05d366b426005f47, 0x00b3b58815a860d8, 0x023bbf8109263e1d,
+           0x5fbc2f647d6c1153);
+  asm volatile("vnmsub.vx v1, %[A], v3" ::[A] "r"(scalar));
+  VCMP_U64(12, v1, 0x60dd7609c833e03a, 0x79abe3a30a816ca0, 0x983ca4c97f204385,
+           0x59a9303f04932768, 0x59c29659b4d00149, 0x59a15b1bb66f16c2,
+           0x37b0445a8ebaa7d1, 0x65e0c3ab56fa1f0c, 0x94a740971b1d6eda,
+           0xa1c7ff743113d8bf, 0xe8198a4799a97a9a, 0x5ccf06fd8751eb9d,
+           0xa36557d05e8802dc, 0x10aae67f31dc2b4f, 0xe878939fd1287553,
+           0x594538a8571dbf06);
+}
+
+void TEST_CASE4() {
+  VSET(16, e8, m1);
+  int64_t scalar = 5;
+  VLOAD_8(v1, 0x5e, 0xf5, 0xa9, 0x0b, 0x14, 0x3c, 0x84, 0x22, 0xd7, 0xb6, 0x5c,
+          0x90, 0xa2, 0x67, 0x3d, 0xf5);
+  VLOAD_8(v3, 0xfa, 0xd9, 0x2a, 0xe2, 0xe7, 0x1f, 0x8c, 0xbd, 0x40, 0x5d, 0x50,
+          0x1f, 0xe0, 0xdd, 0x1f, 0xd7);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vnmsub.vx v1, %[A], v3, v0.t" ::[A] "r"(scalar));
+  VCMP_U8(13, v1, 0x5e, 0x10, 0xa9, 0xab, 0x14, 0xf3, 0x84, 0x13, 0xd7, 0xcf,
+          0x5c, 0x4f, 0xa2, 0xda, 0x3d, 0x0e);
+
+  VSET(16, e16, m1);
+  scalar = -5383;
+  VLOAD_16(v1, 0xfe80, 0x3910, 0x5313, 0xefef, 0xecfc, 0x7983, 0xcc0d, 0x731f,
+           0xf384, 0xfde3, 0x9cd1, 0xf20b, 0xa41b, 0x949a, 0x5886, 0xa1a9);
+  VLOAD_16(v3, 0xe886, 0xf1f9, 0x1857, 0xd0bb, 0x522e, 0x2de0, 0xa6c2, 0xd624,
+           0xd024, 0x40a2, 0xdd99, 0xd517, 0xf00a, 0xae8d, 0x79a5, 0x519d);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vnmsub.vx v1, %[A], v3, v0.t" ::[A] "r"(scalar));
+  VCMP_U16(14, v1, 0xfe80, 0xd169, 0x5313, 0xfb44, 0xecfc, 0x3f75, 0xcc0d,
+           0x86fd, 0xf384, 0xd0d7, 0x9cd1, 0x5a64, 0xa41b, 0x60c3, 0x5886,
+           0x9a3c);
+
+  VSET(16, e32, m1);
+  scalar = 6474219;
+  VLOAD_32(v1, 0x48da7aac, 0x54e98600, 0xf49f26e5, 0x338e8406, 0x40ca82f5,
+           0x75d0b8f6, 0x38c88af2, 0x96bb5c03, 0x6f61c0a9, 0x3626dd69,
+           0x31aba619, 0x7d974a55, 0xbc63c280, 0x502334bf, 0x9451b955,
+           0x6a8bae19);
+  VLOAD_32(v3, 0xcbd8537e, 0x36928a6c, 0x60cf8444, 0xa19ea650, 0x8f2a8694,
+           0x050956bf, 0x1ef799f5, 0x43c0f327, 0x4bfd5a25, 0x7be439e4,
+           0xed89a52a, 0x2bbf028d, 0x872392b9, 0x0ad55495, 0x865c7264,
+           0xfcce4b64);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vnmsub.vx v1, %[A], v3, v0.t" ::[A] "r"(scalar));
+  VCMP_U32(15, v1, 0x48da7aac, 0x9dfe886c, 0xf49f26e5, 0xddd6bece, 0x40ca82f5,
+           0x2f0a66ed, 0x38c88af2, 0x915f2166, 0x6f61c0a9, 0x802d8981,
+           0x31aba619, 0xa3f70986, 0xbc63c280, 0xa4fbf240, 0x9451b955,
+           0xdd51d971);
+
+  VSET(16, e64, m1);
+  scalar = -598189234597999223;
+  VLOAD_64(v1, 0x93adc14539897782, 0xa8d5d41c19b1455a, 0x55e01165195d2d9b,
+           0xe81a26a17fef30f2, 0x33a71ede19aec0aa, 0x49598be14c5bc1cd,
+           0x1c27bde3f488bfc6, 0x4188f9b8611e5d90, 0xd53289cca28a3b6b,
+           0x3b435e1078e3bee9, 0x5e3f4c08c869abf4, 0x3c004920e9c39fb6,
+           0x4b42a451b264b153, 0x110a6db11a7c2801, 0x7c0f358ac41d49fa,
+           0x6e8c6ae4d14bd1a5);
+  VLOAD_64(v3, 0x3b0c6a3a651beecc, 0xb612caa033bc9bca, 0xda94340ac428ca78,
+           0xf774b16ef94a22ea, 0x87df3c47c8113e43, 0x38487d57a064f677,
+           0x358706b57ce6d6c7, 0xda111b3ac946811c, 0xe9ffed5b39f1ea1d,
+           0x3c7e5a675c779870, 0x5d2ea63ac910e42e, 0xb3e832dbe2332203,
+           0x05d366b426005f47, 0x00b3b58815a860d8, 0x023bbf8109263e1d,
+           0x5fbc2f647d6c1153);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vnmsub.vx v1, %[A], v3, v0.t" ::[A] "r"(scalar));
+  VCMP_U64(16, v1, 0x93adc14539897782, 0x79abe3a30a816ca0, 0x55e01165195d2d9b,
+           0x59a9303f04932768, 0x33a71ede19aec0aa, 0x59a15b1bb66f16c2,
+           0x1c27bde3f488bfc6, 0x65e0c3ab56fa1f0c, 0xd53289cca28a3b6b,
+           0xa1c7ff743113d8bf, 0x5e3f4c08c869abf4, 0x5ccf06fd8751eb9d,
+           0x4b42a451b264b153, 0x10aae67f31dc2b4f, 0x7c0f358ac41d49fa,
+           0x594538a8571dbf06);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vnsra.c b/apps/riscv-tests/isa/rv64uv/vnsra.c
new file mode 100644
index 0000000..ed3986b
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vnsra.c
@@ -0,0 +1,242 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(16, e8, m1);
+  VLOAD_16(v2, 0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00,
+           0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00);
+  VLOAD_8(v3, 0, 1, 2, 3, 7, 15, 31, 32, 0, 1, 2, 3, 7, 15, 31, 32);
+  asm volatile("vnsra.wv v4, v2, v3");
+  VCMP_U8(1, v4, 0x00, 0x80, 0xC0, 0xE0, 0xFE, 0xFF, 0xFF, 0x00, 0x00, 0x80,
+          0xC0, 0xE0, 0xFE, 0xFF, 0xFF, 0x00);
+
+  VSET(16, e16, m1);
+  VLOAD_32(v2, 0xFFFF0000, 0xFFFF0000, 0xFFFF0000, 0xFFFF0000, 0xFFFF0000,
+           0xFFFF0000, 0xFFFF0000, 0xFFFF0000, 0xFFFF0000, 0xFFFF0000,
+           0xFFFF0000, 0xFFFF0000, 0xFFFF0000, 0xFFFF0000, 0xFFFF0000,
+           0xFFFF0000);
+  VLOAD_16(v3, 0, 1, 2, 3, 7, 15, 31, 32, 0, 1, 2, 3, 7, 15, 31, 32);
+  asm volatile("vnsra.wv v4, v2, v3");
+  VCMP_U16(2, v4, 0x0000, 0x8000, 0xC000, 0xE000, 0xFE00, 0xFFFE, 0xFFFF,
+           0x0000, 0x0000, 0x8000, 0xC000, 0xE000, 0xFE00, 0xFFFE, 0xFFFF,
+           0x0000);
+
+  VSET(16, e32, m1);
+  VLOAD_64(v2, 0xFFFFFFFF00000000, 0xFFFFFFFF00000000, 0xFFFFFFFF00000000,
+           0xFFFFFFFF00000000, 0xFFFFFFFF00000000, 0xFFFFFFFF00000000,
+           0xFFFFFFFF00000000, 0xFFFFFFFF00000000, 0xFFFFFFFF00000000,
+           0xFFFFFFFF00000000, 0xFFFFFFFF00000000, 0xFFFFFFFF00000000,
+           0xFFFFFFFF00000000, 0xFFFFFFFF00000000, 0xFFFFFFFF00000000,
+           0xFFFFFFFF00000000);
+  VLOAD_32(v3, 0, 1, 2, 3, 7, 15, 31, 32, 0, 1, 2, 3, 7, 15, 31, 32);
+  asm volatile("vnsra.wv v4, v2, v3");
+  VCMP_U32(3, v4, 0x00000000, 0x80000000, 0xC0000000, 0xE0000000, 0xFE000000,
+           0xFFFE0000, 0xFFFFFFFE, 0xFFFFFFFF, 0x00000000, 0x80000000,
+           0xC0000000, 0xE0000000, 0xFE000000, 0xFFFE0000, 0xFFFFFFFE,
+           0xFFFFFFFF);
+};
+
+void TEST_CASE2(void) {
+  VSET(16, e8, m1);
+  VLOAD_16(v2, 0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00,
+           0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00);
+  VLOAD_8(v3, 0, 1, 2, 3, 7, 15, 31, 32, 0, 1, 2, 3, 7, 15, 31, 32);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vnsra.wv v4, v2, v3, v0.t");
+  VCMP_U8(4, v4, 0x00, 0x80, 0x00, 0xE0, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x80,
+          0x00, 0xE0, 0x00, 0xFF, 0x00, 0x00);
+
+  VSET(16, e16, m1);
+  VLOAD_32(v2, 0xFFFF0000, 0xFFFF0000, 0xFFFF0000, 0xFFFF0000, 0xFFFF0000,
+           0xFFFF0000, 0xFFFF0000, 0xFFFF0000, 0xFFFF0000, 0xFFFF0000,
+           0xFFFF0000, 0xFFFF0000, 0xFFFF0000, 0xFFFF0000, 0xFFFF0000,
+           0xFFFF0000);
+  VLOAD_16(v3, 0, 1, 2, 3, 7, 15, 31, 32, 0, 1, 2, 3, 7, 15, 31, 32);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vnsra.wv v4, v2, v3, v0.t");
+  VCMP_U16(5, v4, 0x0000, 0x8000, 0x0000, 0xE000, 0x0000, 0xFFFE, 0x0000,
+           0x0000, 0x0000, 0x8000, 0x0000, 0xE000, 0x0000, 0xFFFE, 0x0000,
+           0x0000);
+
+  VSET(16, e32, m1);
+  VLOAD_64(v2, 0xFFFFFFFF00000000, 0xFFFFFFFF00000000, 0xFFFFFFFF00000000,
+           0xFFFFFFFF00000000, 0xFFFFFFFF00000000, 0xFFFFFFFF00000000,
+           0xFFFFFFFF00000000, 0xFFFFFFFF00000000, 0xFFFFFFFF00000000,
+           0xFFFFFFFF00000000, 0xFFFFFFFF00000000, 0xFFFFFFFF00000000,
+           0xFFFFFFFF00000000, 0xFFFFFFFF00000000, 0xFFFFFFFF00000000,
+           0xFFFFFFFF00000000);
+  VLOAD_32(v3, 0, 1, 2, 3, 7, 15, 31, 32, 0, 1, 2, 3, 7, 15, 31, 32);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vnsra.wv v4, v2, v3, v0.t");
+  VCMP_U32(6, v4, 0x00000000, 0x80000000, 0x00000000, 0xE0000000, 0x00000000,
+           0xFFFE0000, 0x00000000, 0xFFFFFFFF, 0x00000000, 0x80000000,
+           0x00000000, 0xE0000000, 0x00000000, 0xFFFE0000, 0x00000000,
+           0xFFFFFFFF);
+};
+
+void TEST_CASE3(void) {
+  const uint64_t scalar = 2;
+
+  VSET(16, e8, m1);
+  VLOAD_16(v2, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018, 0x001C, 0x0020,
+           0xFFE0, 0xFFE4, 0xFFE8, 0xFFEC, 0xFFF0, 0xFFF4, 0xFFF8, 0xFFFC);
+  asm volatile("vnsra.wx v4, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U8(7, v4, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0xF8, 0xF9,
+          0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF);
+
+  VSET(16, e16, m1);
+  VLOAD_32(v2, 0x00000004, 0x00000008, 0x0000000C, 0x00000010, 0x00000014,
+           0x00000018, 0x0000001C, 0x00000020, 0xFFFFFFE0, 0xFFFFFFE4,
+           0xFFFFFFE8, 0xFFFFFFEC, 0xFFFFFFF0, 0xFFFFFFF4, 0xFFFFFFF8,
+           0xFFFFFFFC);
+  asm volatile("vnsra.wx v4, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U16(8, v4, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007,
+           0x0008, 0xFFF8, 0xFFF9, 0xFFFA, 0xFFFB, 0xFFFC, 0xFFFD, 0xFFFE,
+           0xFFFF);
+
+  VSET(16, e32, m1);
+  VLOAD_64(v2, 0x0000000000000004, 0x0000000000000008, 0x000000000000000C,
+           0x0000000000000010, 0x0000000000000014, 0x0000000000000018,
+           0x000000000000001C, 0x0000000000000020, 0xFFFFFFFFFFFFFFE0,
+           0xFFFFFFFFFFFFFFE4, 0xFFFFFFFFFFFFFFE8, 0xFFFFFFFFFFFFFFEC,
+           0xFFFFFFFFFFFFFFF0, 0xFFFFFFFFFFFFFFF4, 0xFFFFFFFFFFFFFFF8,
+           0xFFFFFFFFFFFFFFFC);
+  asm volatile("vnsra.wx v4, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U32(9, v4, 0x00000001, 0x00000002, 0x00000003, 0x00000004, 0x00000005,
+           0x00000006, 0x00000007, 0x00000008, 0xFFFFFFF8, 0xFFFFFFF9,
+           0xFFFFFFFA, 0xFFFFFFFB, 0xFFFFFFFC, 0xFFFFFFFD, 0xFFFFFFFE,
+           0xFFFFFFFF);
+};
+
+void TEST_CASE4(void) {
+  const uint64_t scalar = 2;
+
+  VSET(16, e8, m1);
+  VLOAD_16(v2, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018, 0x001C, 0x0020,
+           0xFFE0, 0xFFE4, 0xFFE8, 0xFFEC, 0xFFF0, 0xFFF4, 0xFFF8, 0xFFFC);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vnsra.wx v4, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U8(10, v4, 0x00, 0x02, 0x00, 0x04, 0x00, 0x06, 0x00, 0x08, 0x00, 0xF9,
+          0x00, 0xFB, 0x00, 0xFD, 0x00, 0xFF);
+
+  VSET(16, e16, m1);
+  VLOAD_32(v2, 0x00000004, 0x00000008, 0x0000000C, 0x00000010, 0x00000014,
+           0x00000018, 0x0000001C, 0x00000020, 0xFFFFFFE0, 0xFFFFFFE4,
+           0xFFFFFFE8, 0xFFFFFFEC, 0xFFFFFFF0, 0xFFFFFFF4, 0xFFFFFFF8,
+           0xFFFFFFFC);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vnsra.wx v4, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U16(11, v4, 0x0000, 0x0002, 0x0000, 0x0004, 0x0000, 0x0006, 0x0000,
+           0x0008, 0x0000, 0xFFF9, 0x0000, 0xFFFB, 0x0000, 0xFFFD, 0x0000,
+           0xFFFF);
+
+  VSET(16, e32, m1);
+  VLOAD_64(v2, 0x0000000000000004, 0x0000000000000008, 0x000000000000000C,
+           0x0000000000000010, 0x0000000000000014, 0x0000000000000018,
+           0x000000000000001C, 0x0000000000000020, 0xFFFFFFFFFFFFFFE0,
+           0xFFFFFFFFFFFFFFE4, 0xFFFFFFFFFFFFFFE8, 0xFFFFFFFFFFFFFFEC,
+           0xFFFFFFFFFFFFFFF0, 0xFFFFFFFFFFFFFFF4, 0xFFFFFFFFFFFFFFF8,
+           0xFFFFFFFFFFFFFFFC);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vnsra.wx v4, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U32(12, v4, 0x00000000, 0x00000002, 0x00000000, 0x00000004, 0x00000000,
+           0x00000006, 0x00000000, 0x00000008, 0x00000000, 0xFFFFFFF9,
+           0x00000000, 0xFFFFFFFB, 0x00000000, 0xFFFFFFFD, 0x00000000,
+           0xFFFFFFFF);
+};
+
+void TEST_CASE5(void) {
+  VSET(16, e8, m1);
+  VLOAD_16(v2, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018, 0x001C, 0x0020,
+           0xFFE0, 0xFFE4, 0xFFE8, 0xFFEC, 0xFFF0, 0xFFF4, 0xFFF8, 0xFFFC);
+  asm volatile("vnsra.wi v4, v2, 2");
+  VCMP_U8(13, v4, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0xF8, 0xF9,
+          0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF);
+
+  VSET(16, e16, m1);
+  VLOAD_32(v2, 0x00000004, 0x00000008, 0x0000000C, 0x00000010, 0x00000014,
+           0x00000018, 0x0000001C, 0x00000020, 0xFFFFFFE0, 0xFFFFFFE4,
+           0xFFFFFFE8, 0xFFFFFFEC, 0xFFFFFFF0, 0xFFFFFFF4, 0xFFFFFFF8,
+           0xFFFFFFFC);
+  asm volatile("vnsra.wi v4, v2, 2");
+  VCMP_U16(14, v4, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007,
+           0x0008, 0xFFF8, 0xFFF9, 0xFFFA, 0xFFFB, 0xFFFC, 0xFFFD, 0xFFFE,
+           0xFFFF);
+
+  VSET(16, e32, m1);
+  VLOAD_64(v2, 0x0000000000000004, 0x0000000000000008, 0x000000000000000C,
+           0x0000000000000010, 0x0000000000000014, 0x0000000000000018,
+           0x000000000000001C, 0x0000000000000020, 0xFFFFFFFFFFFFFFE0,
+           0xFFFFFFFFFFFFFFE4, 0xFFFFFFFFFFFFFFE8, 0xFFFFFFFFFFFFFFEC,
+           0xFFFFFFFFFFFFFFF0, 0xFFFFFFFFFFFFFFF4, 0xFFFFFFFFFFFFFFF8,
+           0xFFFFFFFFFFFFFFFC);
+  asm volatile("vnsra.wi v4, v2, 2");
+  VCMP_U32(15, v4, 0x00000001, 0x00000002, 0x00000003, 0x00000004, 0x00000005,
+           0x00000006, 0x00000007, 0x00000008, 0xFFFFFFF8, 0xFFFFFFF9,
+           0xFFFFFFFA, 0xFFFFFFFB, 0xFFFFFFFC, 0xFFFFFFFD, 0xFFFFFFFE,
+           0xFFFFFFFF);
+};
+
+void TEST_CASE6(void) {
+  VSET(16, e8, m1);
+  VLOAD_16(v2, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018, 0x001C, 0x0020,
+           0xFFE0, 0xFFE4, 0xFFE8, 0xFFEC, 0xFFF0, 0xFFF4, 0xFFF8, 0xFFFC);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vnsra.wi v4, v2, 2, v0.t");
+  VCMP_U8(16, v4, 0x00, 0x02, 0x00, 0x04, 0x00, 0x06, 0x00, 0x08, 0x00, 0xF9,
+          0x00, 0xFB, 0x00, 0xFD, 0x00, 0xFF);
+
+  VSET(16, e16, m1);
+  VLOAD_32(v2, 0x00000004, 0x00000008, 0x0000000C, 0x00000010, 0x00000014,
+           0x00000018, 0x0000001C, 0x00000020, 0xFFFFFFE0, 0xFFFFFFE4,
+           0xFFFFFFE8, 0xFFFFFFEC, 0xFFFFFFF0, 0xFFFFFFF4, 0xFFFFFFF8,
+           0xFFFFFFFC);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vnsra.wi v4, v2, 2, v0.t");
+  VCMP_U16(17, v4, 0x0000, 0x0002, 0x0000, 0x0004, 0x0000, 0x0006, 0x0000,
+           0x0008, 0x0000, 0xFFF9, 0x0000, 0xFFFB, 0x0000, 0xFFFD, 0x0000,
+           0xFFFF);
+
+  VSET(16, e32, m1);
+  VLOAD_64(v2, 0x0000000000000004, 0x0000000000000008, 0x000000000000000C,
+           0x0000000000000010, 0x0000000000000014, 0x0000000000000018,
+           0x000000000000001C, 0x0000000000000020, 0xFFFFFFFFFFFFFFE0,
+           0xFFFFFFFFFFFFFFE4, 0xFFFFFFFFFFFFFFE8, 0xFFFFFFFFFFFFFFEC,
+           0xFFFFFFFFFFFFFFF0, 0xFFFFFFFFFFFFFFF4, 0xFFFFFFFFFFFFFFF8,
+           0xFFFFFFFFFFFFFFFC);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vnsra.wi v4, v2, 2, v0.t");
+  VCMP_U32(18, v4, 0x00000000, 0x00000002, 0x00000000, 0x00000004, 0x00000000,
+           0x00000006, 0x00000000, 0x00000008, 0x00000000, 0xFFFFFFF9,
+           0x00000000, 0xFFFFFFFB, 0x00000000, 0xFFFFFFFD, 0x00000000,
+           0xFFFFFFFF);
+};
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+  TEST_CASE6();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vnsrl.c b/apps/riscv-tests/isa/rv64uv/vnsrl.c
new file mode 100644
index 0000000..604322f
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vnsrl.c
@@ -0,0 +1,242 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(16, e8, m1);
+  VLOAD_16(v2, 0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00,
+           0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00);
+  VLOAD_8(v3, 0, 1, 2, 3, 7, 15, 31, 32, 0, 1, 2, 3, 7, 15, 31, 32);
+  asm volatile("vnsrl.wv v4, v2, v3");
+  VCMP_U8(1, v4, 0x00, 0x80, 0xC0, 0xE0, 0xFE, 0x01, 0x01, 0x00, 0x00, 0x80,
+          0xC0, 0xE0, 0xFE, 0x01, 0x01, 0x00);
+
+  VSET(16, e16, m1);
+  VLOAD_32(v2, 0xFFFF0000, 0xFFFF0000, 0xFFFF0000, 0xFFFF0000, 0xFFFF0000,
+           0xFFFF0000, 0xFFFF0000, 0xFFFF0000, 0xFFFF0000, 0xFFFF0000,
+           0xFFFF0000, 0xFFFF0000, 0xFFFF0000, 0xFFFF0000, 0xFFFF0000,
+           0xFFFF0000);
+  VLOAD_16(v3, 0, 1, 2, 3, 7, 15, 31, 32, 0, 1, 2, 3, 7, 15, 31, 32);
+  asm volatile("vnsrl.wv v4, v2, v3");
+  VCMP_U16(2, v4, 0x0000, 0x8000, 0xC000, 0xE000, 0xFE00, 0xFFFE, 0x0001,
+           0x0000, 0x0000, 0x8000, 0xC000, 0xE000, 0xFE00, 0xFFFE, 0x0001,
+           0x0000);
+
+  VSET(16, e32, m1);
+  VLOAD_64(v2, 0xFFFFFFFF00000000, 0xFFFFFFFF00000000, 0xFFFFFFFF00000000,
+           0xFFFFFFFF00000000, 0xFFFFFFFF00000000, 0xFFFFFFFF00000000,
+           0xFFFFFFFF00000000, 0xFFFFFFFF00000000, 0xFFFFFFFF00000000,
+           0xFFFFFFFF00000000, 0xFFFFFFFF00000000, 0xFFFFFFFF00000000,
+           0xFFFFFFFF00000000, 0xFFFFFFFF00000000, 0xFFFFFFFF00000000,
+           0xFFFFFFFF00000000);
+  VLOAD_32(v3, 0, 1, 2, 3, 7, 15, 31, 32, 0, 1, 2, 3, 7, 15, 31, 32);
+  asm volatile("vnsrl.wv v4, v2, v3");
+  VCMP_U32(3, v4, 0x00000000, 0x80000000, 0xC0000000, 0xE0000000, 0xFE000000,
+           0xFFFE0000, 0xFFFFFFFE, 0xFFFFFFFF, 0x00000000, 0x80000000,
+           0xC0000000, 0xE0000000, 0xFE000000, 0xFFFE0000, 0xFFFFFFFE,
+           0xFFFFFFFF);
+};
+
+void TEST_CASE2(void) {
+  VSET(16, e8, m1);
+  VLOAD_16(v2, 0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00,
+           0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00, 0xFF00);
+  VLOAD_8(v3, 0, 1, 2, 3, 7, 15, 31, 32, 0, 1, 2, 3, 7, 15, 31, 32);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vnsrl.wv v4, v2, v3, v0.t");
+  VCMP_U8(4, v4, 0x00, 0x80, 0x00, 0xE0, 0x00, 0x01, 0x00, 0x00, 0x00, 0x80,
+          0x00, 0xE0, 0x00, 0x01, 0x00, 0x00);
+
+  VSET(16, e16, m1);
+  VLOAD_32(v2, 0xFFFF0000, 0xFFFF0000, 0xFFFF0000, 0xFFFF0000, 0xFFFF0000,
+           0xFFFF0000, 0xFFFF0000, 0xFFFF0000, 0xFFFF0000, 0xFFFF0000,
+           0xFFFF0000, 0xFFFF0000, 0xFFFF0000, 0xFFFF0000, 0xFFFF0000,
+           0xFFFF0000);
+  VLOAD_16(v3, 0, 1, 2, 3, 7, 15, 31, 32, 0, 1, 2, 3, 7, 15, 31, 32);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vnsrl.wv v4, v2, v3, v0.t");
+  VCMP_U16(5, v4, 0x0000, 0x8000, 0x0000, 0xE000, 0x0000, 0xFFFE, 0x0000,
+           0x0000, 0x0000, 0x8000, 0x0000, 0xE000, 0x0000, 0xFFFE, 0x0000,
+           0x0000);
+
+  VSET(16, e32, m1);
+  VLOAD_64(v2, 0xFFFFFFFF00000000, 0xFFFFFFFF00000000, 0xFFFFFFFF00000000,
+           0xFFFFFFFF00000000, 0xFFFFFFFF00000000, 0xFFFFFFFF00000000,
+           0xFFFFFFFF00000000, 0xFFFFFFFF00000000, 0xFFFFFFFF00000000,
+           0xFFFFFFFF00000000, 0xFFFFFFFF00000000, 0xFFFFFFFF00000000,
+           0xFFFFFFFF00000000, 0xFFFFFFFF00000000, 0xFFFFFFFF00000000,
+           0xFFFFFFFF00000000);
+  VLOAD_32(v3, 0, 1, 2, 3, 7, 15, 31, 32, 0, 1, 2, 3, 7, 15, 31, 32);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vnsrl.wv v4, v2, v3, v0.t");
+  VCMP_U32(6, v4, 0x00000000, 0x80000000, 0x00000000, 0xE0000000, 0x00000000,
+           0xFFFE0000, 0x00000000, 0xFFFFFFFF, 0x00000000, 0x80000000,
+           0x00000000, 0xE0000000, 0x00000000, 0xFFFE0000, 0x00000000,
+           0xFFFFFFFF);
+};
+
+void TEST_CASE3(void) {
+  const uint64_t scalar = 2;
+
+  VSET(16, e8, m1);
+  VLOAD_16(v2, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018, 0x001C, 0x0020,
+           0xFFE0, 0xFFE4, 0xFFE8, 0xFFEC, 0xFFF0, 0xFFF4, 0xFFF8, 0xFFFC);
+  asm volatile("vnsrl.wx v4, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U8(7, v4, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0xF8, 0xF9,
+          0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF);
+
+  VSET(16, e16, m1);
+  VLOAD_32(v2, 0x00000004, 0x00000008, 0x0000000C, 0x00000010, 0x00000014,
+           0x00000018, 0x0000001C, 0x00000020, 0xFFFFFFE0, 0xFFFFFFE4,
+           0xFFFFFFE8, 0xFFFFFFEC, 0xFFFFFFF0, 0xFFFFFFF4, 0xFFFFFFF8,
+           0xFFFFFFFC);
+  asm volatile("vnsrl.wx v4, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U16(8, v4, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007,
+           0x0008, 0xFFF8, 0xFFF9, 0xFFFA, 0xFFFB, 0xFFFC, 0xFFFD, 0xFFFE,
+           0xFFFF);
+
+  VSET(16, e32, m1);
+  VLOAD_64(v2, 0x0000000000000004, 0x0000000000000008, 0x000000000000000C,
+           0x0000000000000010, 0x0000000000000014, 0x0000000000000018,
+           0x000000000000001C, 0x0000000000000020, 0xFFFFFFFFFFFFFFE0,
+           0xFFFFFFFFFFFFFFE4, 0xFFFFFFFFFFFFFFE8, 0xFFFFFFFFFFFFFFEC,
+           0xFFFFFFFFFFFFFFF0, 0xFFFFFFFFFFFFFFF4, 0xFFFFFFFFFFFFFFF8,
+           0xFFFFFFFFFFFFFFFC);
+  asm volatile("vnsrl.wx v4, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U32(9, v4, 0x00000001, 0x00000002, 0x00000003, 0x00000004, 0x00000005,
+           0x00000006, 0x00000007, 0x00000008, 0xFFFFFFF8, 0xFFFFFFF9,
+           0xFFFFFFFA, 0xFFFFFFFB, 0xFFFFFFFC, 0xFFFFFFFD, 0xFFFFFFFE,
+           0xFFFFFFFF);
+};
+
+void TEST_CASE4(void) {
+  const uint64_t scalar = 2;
+
+  VSET(16, e8, m1);
+  VLOAD_16(v2, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018, 0x001C, 0x0020,
+           0xFFE0, 0xFFE4, 0xFFE8, 0xFFEC, 0xFFF0, 0xFFF4, 0xFFF8, 0xFFFC);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vnsrl.wx v4, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U8(10, v4, 0x00, 0x02, 0x00, 0x04, 0x00, 0x06, 0x00, 0x08, 0x00, 0xF9,
+          0x00, 0xFB, 0x00, 0xFD, 0x00, 0xFF);
+
+  VSET(16, e16, m1);
+  VLOAD_32(v2, 0x00000004, 0x00000008, 0x0000000C, 0x00000010, 0x00000014,
+           0x00000018, 0x0000001C, 0x00000020, 0xFFFFFFE0, 0xFFFFFFE4,
+           0xFFFFFFE8, 0xFFFFFFEC, 0xFFFFFFF0, 0xFFFFFFF4, 0xFFFFFFF8,
+           0xFFFFFFFC);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vnsrl.wx v4, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U16(11, v4, 0x0000, 0x0002, 0x0000, 0x0004, 0x0000, 0x0006, 0x0000,
+           0x0008, 0x0000, 0xFFF9, 0x0000, 0xFFFB, 0x0000, 0xFFFD, 0x0000,
+           0xFFFF);
+
+  VSET(16, e32, m1);
+  VLOAD_64(v2, 0x0000000000000004, 0x0000000000000008, 0x000000000000000C,
+           0x0000000000000010, 0x0000000000000014, 0x0000000000000018,
+           0x000000000000001C, 0x0000000000000020, 0xFFFFFFFFFFFFFFE0,
+           0xFFFFFFFFFFFFFFE4, 0xFFFFFFFFFFFFFFE8, 0xFFFFFFFFFFFFFFEC,
+           0xFFFFFFFFFFFFFFF0, 0xFFFFFFFFFFFFFFF4, 0xFFFFFFFFFFFFFFF8,
+           0xFFFFFFFFFFFFFFFC);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vnsrl.wx v4, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U32(12, v4, 0x00000000, 0x00000002, 0x00000000, 0x00000004, 0x00000000,
+           0x00000006, 0x00000000, 0x00000008, 0x00000000, 0xFFFFFFF9,
+           0x00000000, 0xFFFFFFFB, 0x00000000, 0xFFFFFFFD, 0x00000000,
+           0xFFFFFFFF);
+};
+
+void TEST_CASE5(void) {
+  VSET(16, e8, m1);
+  VLOAD_16(v2, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018, 0x001C, 0x0020,
+           0xFFE0, 0xFFE4, 0xFFE8, 0xFFEC, 0xFFF0, 0xFFF4, 0xFFF8, 0xFFFC);
+  asm volatile("vnsrl.wi v4, v2, 2");
+  VCMP_U8(13, v4, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0xF8, 0xF9,
+          0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF);
+
+  VSET(16, e16, m1);
+  VLOAD_32(v2, 0x00000004, 0x00000008, 0x0000000C, 0x00000010, 0x00000014,
+           0x00000018, 0x0000001C, 0x00000020, 0xFFFFFFE0, 0xFFFFFFE4,
+           0xFFFFFFE8, 0xFFFFFFEC, 0xFFFFFFF0, 0xFFFFFFF4, 0xFFFFFFF8,
+           0xFFFFFFFC);
+  asm volatile("vnsrl.wi v4, v2, 2");
+  VCMP_U16(14, v4, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007,
+           0x0008, 0xFFF8, 0xFFF9, 0xFFFA, 0xFFFB, 0xFFFC, 0xFFFD, 0xFFFE,
+           0xFFFF);
+
+  VSET(16, e32, m1);
+  VLOAD_64(v2, 0x0000000000000004, 0x0000000000000008, 0x000000000000000C,
+           0x0000000000000010, 0x0000000000000014, 0x0000000000000018,
+           0x000000000000001C, 0x0000000000000020, 0xFFFFFFFFFFFFFFE0,
+           0xFFFFFFFFFFFFFFE4, 0xFFFFFFFFFFFFFFE8, 0xFFFFFFFFFFFFFFEC,
+           0xFFFFFFFFFFFFFFF0, 0xFFFFFFFFFFFFFFF4, 0xFFFFFFFFFFFFFFF8,
+           0xFFFFFFFFFFFFFFFC);
+  asm volatile("vnsrl.wi v4, v2, 2");
+  VCMP_U32(15, v4, 0x00000001, 0x00000002, 0x00000003, 0x00000004, 0x00000005,
+           0x00000006, 0x00000007, 0x00000008, 0xFFFFFFF8, 0xFFFFFFF9,
+           0xFFFFFFFA, 0xFFFFFFFB, 0xFFFFFFFC, 0xFFFFFFFD, 0xFFFFFFFE,
+           0xFFFFFFFF);
+};
+
+void TEST_CASE6(void) {
+  VSET(16, e8, m1);
+  VLOAD_16(v2, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018, 0x001C, 0x0020,
+           0xFFE0, 0xFFE4, 0xFFE8, 0xFFEC, 0xFFF0, 0xFFF4, 0xFFF8, 0xFFFC);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vnsrl.wi v4, v2, 2, v0.t");
+  VCMP_U8(16, v4, 0x00, 0x02, 0x00, 0x04, 0x00, 0x06, 0x00, 0x08, 0x00, 0xF9,
+          0x00, 0xFB, 0x00, 0xFD, 0x00, 0xFF);
+
+  VSET(16, e16, m1);
+  VLOAD_32(v2, 0x00000004, 0x00000008, 0x0000000C, 0x00000010, 0x00000014,
+           0x00000018, 0x0000001C, 0x00000020, 0xFFFFFFE0, 0xFFFFFFE4,
+           0xFFFFFFE8, 0xFFFFFFEC, 0xFFFFFFF0, 0xFFFFFFF4, 0xFFFFFFF8,
+           0xFFFFFFFC);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vnsrl.wi v4, v2, 2, v0.t");
+  VCMP_U16(17, v4, 0x0000, 0x0002, 0x0000, 0x0004, 0x0000, 0x0006, 0x0000,
+           0x0008, 0x0000, 0xFFF9, 0x0000, 0xFFFB, 0x0000, 0xFFFD, 0x0000,
+           0xFFFF);
+
+  VSET(16, e32, m1);
+  VLOAD_64(v2, 0x0000000000000004, 0x0000000000000008, 0x000000000000000C,
+           0x0000000000000010, 0x0000000000000014, 0x0000000000000018,
+           0x000000000000001C, 0x0000000000000020, 0xFFFFFFFFFFFFFFE0,
+           0xFFFFFFFFFFFFFFE4, 0xFFFFFFFFFFFFFFE8, 0xFFFFFFFFFFFFFFEC,
+           0xFFFFFFFFFFFFFFF0, 0xFFFFFFFFFFFFFFF4, 0xFFFFFFFFFFFFFFF8,
+           0xFFFFFFFFFFFFFFFC);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vnsrl.wi v4, v2, 2, v0.t");
+  VCMP_U32(18, v4, 0x00000000, 0x00000002, 0x00000000, 0x00000004, 0x00000000,
+           0x00000006, 0x00000000, 0x00000008, 0x00000000, 0xFFFFFFF9,
+           0x00000000, 0xFFFFFFFB, 0x00000000, 0xFFFFFFFD, 0x00000000,
+           0xFFFFFFFF);
+};
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+  TEST_CASE6();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vor.c b/apps/riscv-tests/isa/rv64uv/vor.c
new file mode 100644
index 0000000..54e3eb2
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vor.c
@@ -0,0 +1,309 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1() {
+  VSET(12, e8, m1);
+  VLOAD_8(v2, 0xff, 0x01, 0xf0, 0xff, 0x01, 0xf0, 0xff, 0x01, 0xf0, 0xff, 0x01,
+          0xf0);
+  VLOAD_8(v3, 0xf0, 0x03, 0xf0, 0xf0, 0x03, 0xf0, 0xf0, 0x03, 0xf0, 0xf0, 0x03,
+          0xf0);
+  asm volatile("vor.vv v1, v2, v3");
+  VCMP_U8(1, v1, 0xff, 0x03, 0xf0, 0xff, 0x03, 0xf0, 0xff, 0x03, 0xf0, 0xff,
+          0x03, 0xf0);
+
+  VSET(12, e16, m1);
+  VLOAD_16(v2, 0xffff, 0x0001, 0xf0f0, 0xffff, 0x0001, 0xf0f0, 0xffff, 0x0001,
+           0xf0f0, 0xffff, 0x0001, 0xf0f0);
+  VLOAD_16(v3, 0xff00, 0x0003, 0xf0f0, 0xff00, 0x0003, 0xf0f0, 0xff00, 0x0003,
+           0xf0f0, 0xff00, 0x0003, 0xf0f0);
+  asm volatile("vor.vv v1, v2, v3");
+  VCMP_U16(2, v1, 0xffff, 0x0003, 0xf0f0, 0xffff, 0x0003, 0xf0f0, 0xffff,
+           0x0003, 0xf0f0, 0xffff, 0x0003, 0xf0f0);
+
+  VSET(12, e32, m1);
+  VLOAD_32(v2, 0xffffffff, 0x00000001, 0xf0f0f0f0, 0xffffffff, 0x00000001,
+           0xf0f0f0f0, 0xffffffff, 0x00000001, 0xf0f0f0f0, 0xffffffff,
+           0x00000001, 0xf0f0f0f0);
+  VLOAD_32(v3, 0xffff0000, 0x00000003, 0xf0f0f0f0, 0xffff0000, 0x00000003,
+           0xf0f0f0f0, 0xffff0000, 0x00000003, 0xf0f0f0f0, 0xffff0000,
+           0x00000003, 0xf0f0f0f0);
+  asm volatile("vor.vv v1, v2, v3");
+  VCMP_U32(3, v1, 0xffffffff, 0x00000003, 0xf0f0f0f0, 0xffffffff, 0x00000003,
+           0xf0f0f0f0, 0xffffffff, 0x00000003, 0xf0f0f0f0, 0xffffffff,
+           0x00000003, 0xf0f0f0f0);
+
+  VSET(12, e64, m1);
+  VLOAD_64(v2, 0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0);
+  VLOAD_64(v3, 0xffffffff00000000, 0x0000000000000003, 0xf0f0f0f0f0f0f0f0,
+           0xffffffff00000000, 0x0000000000000003, 0xf0f0f0f0f0f0f0f0,
+           0xffffffff00000000, 0x0000000000000003, 0xf0f0f0f0f0f0f0f0,
+           0xffffffff00000000, 0x0000000000000003, 0xf0f0f0f0f0f0f0f0);
+  asm volatile("vor.vv v1, v2, v3");
+  VCMP_U64(4, v1, 0xffffffffffffffff, 0x0000000000000003, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000003, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000003, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000003, 0xf0f0f0f0f0f0f0f0);
+}
+
+void TEST_CASE2() {
+  VSET(12, e8, m1);
+  VLOAD_8(v2, 0xff, 0x01, 0xf0, 0xff, 0x01, 0xf0, 0xff, 0x01, 0xf0, 0xff, 0x01,
+          0xf0);
+  VLOAD_8(v3, 0xf0, 0x03, 0xf0, 0xf0, 0x03, 0xf0, 0xf0, 0x03, 0xf0, 0xf0, 0x03,
+          0xf0);
+  VLOAD_8(v0, 0x6D, 0x0B);
+  VLOAD_8(v1, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef,
+          0xef);
+  asm volatile("vor.vv v1, v2, v3, v0.t");
+  VCMP_U8(5, v1, 0xff, 0xef, 0xf0, 0xff, 0xef, 0xf0, 0xff, 0xef, 0xf0, 0xff,
+          0xef, 0xf0);
+
+  VSET(12, e16, m1);
+  VLOAD_16(v2, 0xffff, 0x0001, 0xf0f0, 0xffff, 0x0001, 0xf0f0, 0xffff, 0x0001,
+           0xf0f0, 0xffff, 0x0001, 0xf0f0);
+  VLOAD_16(v3, 0xff00, 0x0003, 0xf0f0, 0xff00, 0x0003, 0xf0f0, 0xff00, 0x0003,
+           0xf0f0, 0xff00, 0x0003, 0xf0f0);
+  VLOAD_8(v0, 0x6D, 0x0B);
+  VLOAD_16(v1, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef,
+           0xbeef, 0xbeef, 0xbeef, 0xbeef);
+  asm volatile("vor.vv v1, v2, v3, v0.t");
+  VCMP_U16(6, v1, 0xffff, 0xbeef, 0xf0f0, 0xffff, 0xbeef, 0xf0f0, 0xffff,
+           0xbeef, 0xf0f0, 0xffff, 0xbeef, 0xf0f0);
+
+  VSET(12, e32, m1);
+  VLOAD_32(v2, 0xffffffff, 0x00000001, 0xf0f0f0f0, 0xffffffff, 0x00000001,
+           0xf0f0f0f0, 0xffffffff, 0x00000001, 0xf0f0f0f0, 0xffffffff,
+           0x00000001, 0xf0f0f0f0);
+  VLOAD_32(v3, 0xffff0000, 0x00000003, 0xf0f0f0f0, 0xffff0000, 0x00000003,
+           0xf0f0f0f0, 0xffff0000, 0x00000003, 0xf0f0f0f0, 0xffff0000,
+           0x00000003, 0xf0f0f0f0);
+  VLOAD_8(v0, 0x6D, 0x0B);
+  VLOAD_32(v1, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
+           0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
+           0xdeadbeef, 0xdeadbeef);
+  asm volatile("vor.vv v1, v2, v3, v0.t");
+  VCMP_U32(7, v1, 0xffffffff, 0xdeadbeef, 0xf0f0f0f0, 0xffffffff, 0xdeadbeef,
+           0xf0f0f0f0, 0xffffffff, 0xdeadbeef, 0xf0f0f0f0, 0xffffffff,
+           0xdeadbeef, 0xf0f0f0f0);
+
+  VSET(12, e64, m1);
+  VLOAD_64(v2, 0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0);
+  VLOAD_64(v3, 0xffffffff00000000, 0x0000000000000003, 0xf0f0f0f0f0f0f0f0,
+           0xffffffff00000000, 0x0000000000000003, 0xf0f0f0f0f0f0f0f0,
+           0xffffffff00000000, 0x0000000000000003, 0xf0f0f0f0f0f0f0f0,
+           0xffffffff00000000, 0x0000000000000003, 0xf0f0f0f0f0f0f0f0);
+  VLOAD_8(v0, 0x6D, 0x0B);
+  VLOAD_64(v1, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef);
+  asm volatile("vor.vv v1, v2, v3, v0.t");
+  VCMP_U64(8, v1, 0xffffffffffffffff, 0xdeadbeefdeadbeef, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0xdeadbeefdeadbeef, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0xdeadbeefdeadbeef, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0xdeadbeefdeadbeef, 0xf0f0f0f0f0f0f0f0);
+}
+
+void TEST_CASE3() {
+  const uint64_t scalar = 0x0ff00ff00ff00ff0;
+
+  VSET(12, e8, m1);
+  VLOAD_8(v2, 0xff, 0x01, 0xf0, 0xff, 0x01, 0xf0, 0xff, 0x01, 0xf0, 0xff, 0x01,
+          0xf0);
+  asm volatile("vor.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U8(9, v1, 0xff, 0xf1, 0xf0, 0xff, 0xf1, 0xf0, 0xff, 0xf1, 0xf0, 0xff,
+          0xf1, 0xf0);
+
+  VSET(12, e16, m1);
+  VLOAD_16(v2, 0xffff, 0x0001, 0xf0f0, 0xffff, 0x0001, 0xf0f0, 0xffff, 0x0001,
+           0xf0f0, 0xffff, 0x0001, 0xf0f0);
+  asm volatile("vor.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U16(10, v1, 0xffff, 0x0ff1, 0xfff0, 0xffff, 0x0ff1, 0xfff0, 0xffff,
+           0x0ff1, 0xfff0, 0xffff, 0x0ff1, 0xfff0);
+
+  VSET(12, e32, m1);
+  VLOAD_32(v2, 0xffffffff, 0x00000001, 0xf0f0f0f0, 0xffffffff, 0x00000001,
+           0xf0f0f0f0, 0xffffffff, 0x00000001, 0xf0f0f0f0, 0xffffffff,
+           0x00000001, 0xf0f0f0f0);
+  asm volatile("vor.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U32(11, v1, 0xffffffff, 0x0ff00ff1, 0xfff0fff0, 0xffffffff, 0x0ff00ff1,
+           0xfff0fff0, 0xffffffff, 0x0ff00ff1, 0xfff0fff0, 0xffffffff,
+           0x0ff00ff1, 0xfff0fff0);
+
+  VSET(12, e64, m1);
+  VLOAD_64(v2, 0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0);
+  asm volatile("vor.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U64(12, v1, 0xffffffffffffffff, 0x0ff00ff00ff00ff1, 0xfff0fff0fff0fff0,
+           0xffffffffffffffff, 0x0ff00ff00ff00ff1, 0xfff0fff0fff0fff0,
+           0xffffffffffffffff, 0x0ff00ff00ff00ff1, 0xfff0fff0fff0fff0,
+           0xffffffffffffffff, 0x0ff00ff00ff00ff1, 0xfff0fff0fff0fff0);
+}
+
+void TEST_CASE4() {
+  const uint64_t scalar = 0x0ff00ff00ff00ff0;
+
+  VSET(12, e8, m1);
+  VLOAD_8(v2, 0xff, 0x01, 0xf0, 0xff, 0x01, 0xf0, 0xff, 0x01, 0xf0, 0xff, 0x01,
+          0xf0);
+  VLOAD_8(v0, 0x6D, 0x0B);
+  VLOAD_8(v1, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef,
+          0xef);
+  asm volatile("vor.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U8(13, v1, 0xff, 0xef, 0xf0, 0xff, 0xef, 0xf0, 0xff, 0xef, 0xf0, 0xff,
+          0xef, 0xf0);
+
+  VSET(12, e16, m1);
+  VLOAD_16(v2, 0xffff, 0x0001, 0xf0f0, 0xffff, 0x0001, 0xf0f0, 0xffff, 0x0001,
+           0xf0f0, 0xffff, 0x0001, 0xf0f0);
+  VLOAD_8(v0, 0x6D, 0x0B);
+  VLOAD_16(v1, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef,
+           0xbeef, 0xbeef, 0xbeef, 0xbeef);
+  asm volatile("vor.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U16(14, v1, 0xffff, 0xbeef, 0xfff0, 0xffff, 0xbeef, 0xfff0, 0xffff,
+           0xbeef, 0xfff0, 0xffff, 0xbeef, 0xfff0);
+
+  VSET(12, e32, m1);
+  VLOAD_32(v2, 0xffffffff, 0x00000001, 0xf0f0f0f0, 0xffffffff, 0x00000001,
+           0xf0f0f0f0, 0xffffffff, 0x00000001, 0xf0f0f0f0, 0xffffffff,
+           0x00000001, 0xf0f0f0f0);
+  VLOAD_8(v0, 0x6D, 0x0B);
+  VLOAD_32(v1, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
+           0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
+           0xdeadbeef, 0xdeadbeef);
+  asm volatile("vor.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U32(15, v1, 0xffffffff, 0xdeadbeef, 0xfff0fff0, 0xffffffff, 0xdeadbeef,
+           0xfff0fff0, 0xffffffff, 0xdeadbeef, 0xfff0fff0, 0xffffffff,
+           0xdeadbeef, 0xfff0fff0);
+
+  VSET(12, e64, m1);
+  VLOAD_64(v2, 0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0);
+  VLOAD_8(v0, 0x6D, 0x0B);
+  VLOAD_64(v1, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef);
+  asm volatile("vor.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U64(16, v1, 0xffffffffffffffff, 0xdeadbeefdeadbeef, 0xfff0fff0fff0fff0,
+           0xffffffffffffffff, 0xdeadbeefdeadbeef, 0xfff0fff0fff0fff0,
+           0xffffffffffffffff, 0xdeadbeefdeadbeef, 0xfff0fff0fff0fff0,
+           0xffffffffffffffff, 0xdeadbeefdeadbeef, 0xfff0fff0fff0fff0);
+}
+
+void TEST_CASE5() {
+  VSET(12, e8, m1);
+  VLOAD_8(v2, 0xff, 0x01, 0xf0, 0xff, 0x01, 0xf0, 0xff, 0x01, 0xf0, 0xff, 0x01,
+          0xf0);
+  asm volatile("vor.vi v1, v2, 15");
+  VCMP_U8(17, v1, 0xff, 0x0f, 0xff, 0xff, 0x0f, 0xff, 0xff, 0x0f, 0xff, 0xff,
+          0x0f, 0xff);
+
+  VSET(12, e16, m1);
+  VLOAD_16(v2, 0xffff, 0x0001, 0xf0f0, 0xffff, 0x0001, 0xf0f0, 0xffff, 0x0001,
+           0xf0f0, 0xffff, 0x0001, 0xf0f0);
+  asm volatile("vor.vi v1, v2, 15");
+  VCMP_U16(18, v1, 0xffff, 0x000f, 0xf0ff, 0xffff, 0x000f, 0xf0ff, 0xffff,
+           0x000f, 0xf0ff, 0xffff, 0x000f, 0xf0ff);
+
+  VSET(12, e32, m1);
+  VLOAD_32(v2, 0xffffffff, 0x00000001, 0xf0f0f0f0, 0xffffffff, 0x00000001,
+           0xf0f0f0f0, 0xffffffff, 0x00000001, 0xf0f0f0f0, 0xffffffff,
+           0x00000001, 0xf0f0f0f0);
+  asm volatile("vor.vi v1, v2, 15");
+  VCMP_U32(19, v1, 0xffffffff, 0x0000000f, 0xf0f0f0ff, 0xffffffff, 0x0000000f,
+           0xf0f0f0ff, 0xffffffff, 0x0000000f, 0xf0f0f0ff, 0xffffffff,
+           0x0000000f, 0xf0f0f0ff);
+
+  VSET(12, e64, m1);
+  VLOAD_64(v2, 0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0);
+  asm volatile("vor.vi v1, v2, 15");
+  VCMP_U64(20, v1, 0xffffffffffffffff, 0x000000000000000f, 0xf0f0f0f0f0f0f0ff,
+           0xffffffffffffffff, 0x000000000000000f, 0xf0f0f0f0f0f0f0ff,
+           0xffffffffffffffff, 0x000000000000000f, 0xf0f0f0f0f0f0f0ff,
+           0xffffffffffffffff, 0x000000000000000f, 0xf0f0f0f0f0f0f0ff);
+}
+
+void TEST_CASE6() {
+  VSET(12, e8, m1);
+  VLOAD_8(v2, 0xff, 0x01, 0xf0, 0xff, 0x01, 0xf0, 0xff, 0x01, 0xf0, 0xff, 0x01,
+          0xf0);
+  VLOAD_8(v0, 0x6D, 0x0B);
+  VLOAD_8(v1, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef,
+          0xef);
+  asm volatile("vor.vi v1, v2, 15, v0.t");
+  VCMP_U8(21, v1, 0xff, 0xef, 0xff, 0xff, 0xef, 0xff, 0xff, 0xef, 0xff, 0xff,
+          0xef, 0xff);
+
+  VSET(12, e16, m1);
+  VLOAD_16(v2, 0xffff, 0x0001, 0xf0f0, 0xffff, 0x0001, 0xf0f0, 0xffff, 0x0001,
+           0xf0f0, 0xffff, 0x0001, 0xf0f0);
+  VLOAD_8(v0, 0x6D, 0x0B);
+  VLOAD_16(v1, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef,
+           0xbeef, 0xbeef, 0xbeef, 0xbeef);
+  asm volatile("vor.vi v1, v2, 15, v0.t");
+  VCMP_U16(22, v1, 0xffff, 0xbeef, 0xf0ff, 0xffff, 0xbeef, 0xf0ff, 0xffff,
+           0xbeef, 0xf0ff, 0xffff, 0xbeef, 0xf0ff);
+
+  VSET(12, e32, m1);
+  VLOAD_32(v2, 0xffffffff, 0x00000001, 0xf0f0f0f0, 0xffffffff, 0x00000001,
+           0xf0f0f0f0, 0xffffffff, 0x00000001, 0xf0f0f0f0, 0xffffffff,
+           0x00000001, 0xf0f0f0f0);
+  VLOAD_8(v0, 0x6D, 0x0B);
+  VLOAD_32(v1, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
+           0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
+           0xdeadbeef, 0xdeadbeef);
+  asm volatile("vor.vi v1, v2, 15, v0.t");
+  VCMP_U32(23, v1, 0xffffffff, 0xdeadbeef, 0xf0f0f0ff, 0xffffffff, 0xdeadbeef,
+           0xf0f0f0ff, 0xffffffff, 0xdeadbeef, 0xf0f0f0ff, 0xffffffff,
+           0xdeadbeef, 0xf0f0f0ff);
+
+  VSET(12, e64, m1);
+  VLOAD_64(v2, 0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0);
+  VLOAD_8(v0, 0x6D, 0x0B);
+  VLOAD_64(v1, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef);
+  asm volatile("vor.vi v1, v2, 15, v0.t");
+  VCMP_U64(24, v1, 0xffffffffffffffff, 0xdeadbeefdeadbeef, 0xf0f0f0f0f0f0f0ff,
+           0xffffffffffffffff, 0xdeadbeefdeadbeef, 0xf0f0f0f0f0f0f0ff,
+           0xffffffffffffffff, 0xdeadbeefdeadbeef, 0xf0f0f0f0f0f0f0ff,
+           0xffffffffffffffff, 0xdeadbeefdeadbeef, 0xf0f0f0f0f0f0f0ff);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+  TEST_CASE6();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vpopc_m.c b/apps/riscv-tests/isa/rv64uv/vpopc_m.c
new file mode 100644
index 0000000..d66b9b8
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vpopc_m.c
@@ -0,0 +1,29 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1() {
+  VSET(4, e32, m1);
+  VLOAD_U32(v2, 7, 0, 0, 0);
+  VLOAD_U32(v0, 5, 0, 0, 0);
+  volatile uint32_t scalar = 1337;
+  volatile uint32_t OUP[] = {0, 0, 0, 0};
+  __asm__ volatile("vpopc.m %[A], v2, v0.t \n"
+                   "sw %[A], (%1) \n"
+                   :
+                   : [A] "r"(scalar), "r"(OUP));
+  XCMP(1, OUP[0], 2);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+  enable_fp();
+  TEST_CASE1();
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vredand.c b/apps/riscv-tests/isa/rv64uv/vredand.c
new file mode 100644
index 0000000..9e2842d
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vredand.c
@@ -0,0 +1,93 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+
+#include "vector_macros.h"
+
+// Naive test
+void TEST_CASE1(void) {
+  VSET(12, e8, m1);
+  VLOAD_8(v1, 0xff, 0xf1, 0xf0, 0xff, 0xf1, 0xf0, 0xff, 0xf1, 0xf0, 0xff, 0xf1,
+          0xf0);
+  VLOAD_8(v2, 0xf0);
+  asm volatile("vredand.vs v3, v1, v2");
+  VCMP_U8(1, v3, 0xf0);
+
+  VSET(12, e16, m1);
+  VLOAD_16(v1, 0xffff, 0x0301, 0xf1f0, 0xffff, 0x0101, 0xf7f0, 0xffff, 0x0701,
+           0xfff0, 0xffff, 0x0101, 0xf1f0);
+  VLOAD_16(v2, 0xefff);
+  asm volatile("vredand.vs v3, v1, v2");
+  VCMP_U16(2, v3, 0x0100);
+
+  VSET(12, e32, m1);
+  VLOAD_32(v1, 0xffffffff, 0x100ff001, 0xf0f0f0f0, 0xffffffff, 0x100ff001,
+           0xf0f0f0f0, 0xffffffff, 0x100ff001, 0xf0f0f0f0, 0xffffffff,
+           0x100ff001, 0xf0f0f0f0);
+  VLOAD_32(v2, 0x00f010f0);
+  asm volatile("vredand.vs v3, v1, v2");
+  VCMP_U32(3, v3, 0x00001000);
+
+  VSET(12, e64, m1);
+  VLOAD_64(v1, 0xffffffffffffffff, 0x1000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x1000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x1000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x1000000000000001, 0xf0f0f0f0f0f0f0f0);
+  VLOAD_64(v2, 0xfffffffffffffff7);
+  asm volatile("vredand.vs v3, v1, v2");
+  VCMP_U64(4, v3, 0x1000000000000000);
+}
+
+// Masked naive test
+void TEST_CASE2(void) {
+  VSET(12, e8, m1);
+  VLOAD_8(v0, 0xf7, 0xff);
+  VLOAD_8(v1, 0xff, 0xf1, 0xff, 0x00, 0xf1, 0xf0, 0xff, 0xf1, 0xf0, 0xff, 0xf1,
+          0xf0);
+  VLOAD_8(v2, 0xf0);
+  VLOAD_8(v3, 1);
+  asm volatile("vredand.vs v3, v1, v2, v0.t");
+  VCMP_U8(5, v3, 0xf0);
+
+  VSET(12, e16, m1);
+  VLOAD_8(v0, 0x00, 0x08);
+  VLOAD_16(v1, 0xffff, 0x0301, 0xf1f0, 0xffff, 0x0101, 0xf7f0, 0xffff, 0x9701,
+           0xfff0, 0xffff, 0x0101, 0xf1f0);
+  VLOAD_16(v2, 0xefff);
+  VLOAD_16(v3, 1);
+  asm volatile("vredand.vs v3, v1, v2, v0.t");
+  VCMP_U16(6, v3, 0xe1f0);
+
+  VSET(12, e32, m1);
+  VLOAD_8(v0, 0xfe, 0xff);
+  VLOAD_32(v1, 0x00000000, 0x100ff001, 0xf0f0f0f0, 0xffffffff, 0x100ff001,
+           0xf0f0f0f0, 0xffffffff, 0x100ff001, 0xf0f0f0f0, 0xffffffff,
+           0x100ff001, 0xf0f0f0f0);
+  VLOAD_32(v2, 0x00f010f0);
+  VLOAD_32(v3, 1);
+  asm volatile("vredand.vs v3, v1, v2, v0.t");
+  VCMP_U32(7, v3, 0x00001000);
+
+  VSET(12, e64, m1);
+  VLOAD_8(v0, 0xaa, 0x55);
+  VLOAD_64(v1, 0xffffffffffffffff, 0x1000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x1000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x1000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x1000000000000001, 0xf0f0f0f0f0f0f0f0);
+  VLOAD_64(v2, 0xfffffffffffffff7);
+  VLOAD_64(v3, 1);
+  asm volatile("vredand.vs v3, v1, v2, v0.t");
+  VCMP_U64(8, v3, 0x1000000000000000);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vredmax.c b/apps/riscv-tests/isa/rv64uv/vredmax.c
new file mode 100644
index 0000000..4179d00
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vredmax.c
@@ -0,0 +1,79 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+
+#include "vector_macros.h"
+
+// Naive test
+void TEST_CASE1(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 1, 2, 3, 4, 5, 6, -7, 8, 1, 9, 3, 4, 5, -6, 7, 8);
+  VLOAD_8(v2, -1);
+  asm volatile("vredmax.vs v3, v1, v2");
+  VCMP_U8(1, v3, 9);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v1, -1, 2, -3, 4, 5, 6, 7, 8, 1, 2, 3, -4, 5, 6, 7, 8);
+  VLOAD_16(v2, 9);
+  asm volatile("vredmax.vs v3, v1, v2");
+  VCMP_U16(2, v3, 9);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 9, 2, 3, -4, 5, 6, 7, 8, 1, 2, 3, 4, -5, 6, 7, 8);
+  VLOAD_32(v2, 1);
+  asm volatile("vredmax.vs v3, v1, v2");
+  VCMP_U32(3, v3, 9);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v1, -1, 2, 3, -4, 5, 6, 7, 9, 1, 2, 3, 4, 5, 6, 7, -8);
+  VLOAD_64(v2, -1);
+  asm volatile("vredmax.vs v3, v1, v2");
+  VCMP_U64(4, v3, 9);
+}
+
+// Masked naive test
+void TEST_CASE2(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v0, 0x03, 0x00);
+  VLOAD_8(v1, -1, 2, 3, -4, 5, 6, 7, 9, 1, -2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v2, 1);
+  VLOAD_8(v3, 1);
+  asm volatile("vredmax.vs v3, v1, v2, v0.t");
+  VCMP_U8(5, v3, 2);
+
+  VSET(16, e16, m1);
+  VLOAD_8(v0, 0x00, 0xc0);
+  VLOAD_16(v1, 1, 2, 3, 4, 5, 6, -7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v2, 9);
+  VLOAD_16(v3, 1);
+  asm volatile("vredmax.vs v3, v1, v2, v0.t");
+  VCMP_U16(6, v3, 9);
+
+  VSET(16, e32, m1);
+  VLOAD_8(v0, 0x00, 0xc0);
+  VLOAD_32(v1, -1, 2, 3, 4, 5, 6, 7, -8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v2, 1);
+  VLOAD_32(v3, 1);
+  asm volatile("vredmax.vs v3, v1, v2, v0.t");
+  VCMP_U32(7, v3, 8);
+
+  VSET(16, e64, m1);
+  VLOAD_8(v0, 0xaa, 0x55);
+  VLOAD_64(v1, 1, -2, 3, 4, 5, 6, -7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_64(v2, 4);
+  VLOAD_64(v3, 1);
+  asm volatile("vredmax.vs v3, v1, v2, v0.t");
+  VCMP_U64(8, v3, 8);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vredmaxu.c b/apps/riscv-tests/isa/rv64uv/vredmaxu.c
new file mode 100644
index 0000000..3a5253b
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vredmaxu.c
@@ -0,0 +1,106 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+
+#include "vector_macros.h"
+
+// Naive test
+void TEST_CASE1(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 9, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v2, 1);
+  asm volatile("vredmaxu.vs v3, v1, v2");
+  VCMP_U8(1, v3, 9);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v2, 9);
+  asm volatile("vredmaxu.vs v3, v1, v2");
+  VCMP_U16(2, v3, 9);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 9, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v2, 1);
+  asm volatile("vredmaxu.vs v3, v1, v2");
+  VCMP_U32(3, v3, 9);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 1, 2, 3, 4, 5, 6, 7, 9, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_64(v2, 1);
+  asm volatile("vredmaxu.vs v3, v1, v2");
+  VCMP_U64(4, v3, 9);
+}
+// Masked naive test
+void TEST_CASE2(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v0, 0x03, 0x00);
+  VLOAD_8(v1, 1, 2, 3, 4, 5, 6, 7, 9, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v2, 1);
+  VLOAD_8(v3, 1);
+  asm volatile("vredmaxu.vs v3, v1, v2, v0.t");
+  VCMP_U8(5, v3, 2);
+
+  VSET(16, e16, m1);
+  VLOAD_8(v0, 0x00, 0xc0);
+  VLOAD_16(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v2, 9);
+  VLOAD_16(v3, 1);
+  asm volatile("vredmaxu.vs v3, v1, v2, v0.t");
+  VCMP_U16(6, v3, 9);
+
+  VSET(16, e32, m1);
+  VLOAD_8(v0, 0x00, 0xc0);
+  VLOAD_32(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v2, 1);
+  VLOAD_32(v3, 1);
+  asm volatile("vredmaxu.vs v3, v1, v2, v0.t");
+  VCMP_U32(7, v3, 8);
+
+  VSET(16, e64, m1);
+  VLOAD_8(v0, 0xaa, 0x55);
+  VLOAD_64(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_64(v2, 4);
+  VLOAD_64(v3, 1);
+  asm volatile("vredmaxu.vs v3, v1, v2, v0.t");
+  VCMP_U64(8, v3, 8);
+}
+
+// Naive test with negative values
+void TEST_CASE3(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 9, -3, 4, 5, 6, 7, 8);
+  VLOAD_8(v2, 1);
+  asm volatile("vredmaxu.vs v3, v1, v2");
+  VCMP_U8(9, v3, -3);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v2, -9);
+  asm volatile("vredmaxu.vs v3, v1, v2");
+  VCMP_U16(10, v3, -9);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 9, 2, 3, 4, -5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v2, 1);
+  asm volatile("vredmaxu.vs v3, v1, v2");
+  VCMP_U32(11, v3, -5);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 1, 2, 3, -4, 5, 6, 7, 9, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_64(v2, -1);
+  asm volatile("vredmaxu.vs v3, v1, v2");
+  VCMP_U64(12, v3, -1);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vredmin.c b/apps/riscv-tests/isa/rv64uv/vredmin.c
new file mode 100644
index 0000000..0183cc1
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vredmin.c
@@ -0,0 +1,78 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+
+#include "vector_macros.h"
+
+// Naive test
+void TEST_CASE1(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 1, 2, 3, 4, 5, 6, 7, 0, 1, 9, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v2, 1);
+  asm volatile("vredmin.vs v3, v1, v2");
+  VCMP_U8(1, v3, 0);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 1, 2, -3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v2, 0);
+  asm volatile("vredmin.vs v3, v1, v2");
+  VCMP_U16(2, v3, -3);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 9, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v2, -1);
+  asm volatile("vredmin.vs v3, v1, v2");
+  VCMP_U32(3, v3, -1);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v1, -1, 2, 3, 4, 5, -6, 7, -9, -1, -2, 3, 4, 5, 6, 7, 8);
+  VLOAD_64(v2, -1);
+  asm volatile("vredmin.vs v3, v1, v2");
+  VCMP_U64(4, v3, -9);
+}
+// Masked naive test
+void TEST_CASE2(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v0, 0x03, 0x00);
+  VLOAD_8(v1, 1, -2, 3, 4, 5, 6, 7, 9, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v2, 1);
+  VLOAD_8(v3, 1);
+  asm volatile("vredmin.vs v3, v1, v2, v0.t");
+  VCMP_U8(5, v3, -2);
+
+  VSET(16, e16, m1);
+  VLOAD_8(v0, 0x00, 0xc0);
+  VLOAD_16(v1, -1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v2, 3);
+  VLOAD_16(v3, 1);
+  asm volatile("vredmin.vs v3, v1, v2, v0.t");
+  VCMP_U16(6, v3, 3);
+
+  VSET(16, e32, m1);
+  VLOAD_8(v0, 0x00, 0xc0);
+  VLOAD_32(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v2, 8);
+  VLOAD_32(v3, 1);
+  asm volatile("vredmin.vs v3, v1, v2, v0.t");
+  VCMP_U32(7, v3, 7);
+
+  VSET(16, e64, m1);
+  VLOAD_8(v0, 0xaa, 0x55);
+  VLOAD_64(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_64(v2, 4);
+  VLOAD_64(v3, 1);
+  asm volatile("vredmin.vs v3, v1, v2, v0.t");
+  VCMP_U64(8, v3, 1);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vredminu.c b/apps/riscv-tests/isa/rv64uv/vredminu.c
new file mode 100644
index 0000000..72a11b6
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vredminu.c
@@ -0,0 +1,78 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+
+#include "vector_macros.h"
+
+// Naive test
+void TEST_CASE1(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 1, 2, 3, 4, 5, 6, 7, 0, 1, 9, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v2, 1);
+  asm volatile("vredminu.vs v3, v1, v2");
+  VCMP_U8(1, v3, 0);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 1, 2, -3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v2, 0);
+  asm volatile("vredminu.vs v3, v1, v2");
+  VCMP_U16(2, v3, 0);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 9, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v2, -1);
+  asm volatile("vredminu.vs v3, v1, v2");
+  VCMP_U32(3, v3, 1);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v1, -1, 2, 3, 4, 5, -6, 7, -9, -1, -2, 3, 4, 5, 6, 7, 8);
+  VLOAD_64(v2, -1);
+  asm volatile("vredminu.vs v3, v1, v2");
+  VCMP_U64(4, v3, 2);
+}
+// Masked naive test
+void TEST_CASE2(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v0, 0x03, 0x00);
+  VLOAD_8(v1, 1, -2, 3, 4, 5, 6, 7, 9, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v2, 1);
+  VLOAD_8(v3, 1);
+  asm volatile("vredminu.vs v3, v1, v2, v0.t");
+  VCMP_U8(5, v3, 1);
+
+  VSET(16, e16, m1);
+  VLOAD_8(v0, 0x00, 0xc0);
+  VLOAD_16(v1, -1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v2, 3);
+  VLOAD_16(v3, 1);
+  asm volatile("vredminu.vs v3, v1, v2, v0.t");
+  VCMP_U16(6, v3, 3);
+
+  VSET(16, e32, m1);
+  VLOAD_8(v0, 0x00, 0xc0);
+  VLOAD_32(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v2, 8);
+  VLOAD_32(v3, 1);
+  asm volatile("vredminu.vs v3, v1, v2, v0.t");
+  VCMP_U32(7, v3, 7);
+
+  VSET(16, e64, m1);
+  VLOAD_8(v0, 0xaa, 0x55);
+  VLOAD_64(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_64(v2, 4);
+  VLOAD_64(v3, 1);
+  asm volatile("vredminu.vs v3, v1, v2, v0.t");
+  VCMP_U64(8, v3, 1);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vredor.c b/apps/riscv-tests/isa/rv64uv/vredor.c
new file mode 100644
index 0000000..e67eb10
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vredor.c
@@ -0,0 +1,93 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+
+#include "vector_macros.h"
+
+// Naive test
+void TEST_CASE1(void) {
+  VSET(12, e8, m1);
+  VLOAD_8(v1, 0x00, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x01,
+          0x00);
+  VLOAD_8(v2, 0x10);
+  asm volatile("vredor.vs v3, v1, v2");
+  VCMP_U8(1, v3, 0x11);
+
+  VSET(12, e16, m1);
+  VLOAD_16(v1, 0x0000, 0x0301, 0x0100, 0x0000, 0x0101, 0x0700, 0x0000, 0x0701,
+           0x0000, 0x0000, 0x0101, 0x0100);
+  VLOAD_16(v2, 0xe000);
+  asm volatile("vredor.vs v3, v1, v2");
+  VCMP_U16(2, v3, 0xe701);
+
+  VSET(12, e32, m1);
+  VLOAD_32(v1, 0x00000000, 0x10000001, 0x00000000, 0x00000000, 0x10000001,
+           0x00000000, 0x00000000, 0x10000001, 0x00000000, 0x00000000,
+           0x10000001, 0x00000000);
+  VLOAD_32(v2, 0x00001000);
+  asm volatile("vredor.vs v3, v1, v2");
+  VCMP_U32(3, v3, 0x10001001);
+
+  VSET(12, e64, m1);
+  VLOAD_64(v1, 0x0000000000000000, 0x1000000000000001, 0x0000000000000000,
+           0x0000000000000000, 0x1000000000000001, 0x0000000000000000,
+           0x0000000000000000, 0x1000000000000001, 0x0000000000000000,
+           0x0000000000000000, 0x1000000000000001, 0x0000000000000000);
+  VLOAD_64(v2, 0x0000000000000007);
+  asm volatile("vredor.vs v3, v1, v2");
+  VCMP_U64(4, v3, 0x1000000000000007);
+}
+
+// Masked naive test
+void TEST_CASE2(void) {
+  VSET(12, e8, m1);
+  VLOAD_8(v0, 0x07, 0x00);
+  VLOAD_8(v1, 0x00, 0x01, 0x00, 0xff, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x01,
+          0x00);
+  VLOAD_8(v2, 0x00);
+  VLOAD_8(v3, 1);
+  asm volatile("vredor.vs v3, v1, v2, v0.t");
+  VCMP_U8(5, v3, 0x01);
+
+  VSET(12, e16, m1);
+  VLOAD_8(v0, 0x00, 0x08);
+  VLOAD_16(v1, 0x0f00, 0x0301, 0x0100, 0x0000, 0x0101, 0x0700, 0x0000, 0x9701,
+           0x0000, 0x0000, 0x0101, 0x0100);
+  VLOAD_16(v2, 0xe000);
+  VLOAD_16(v3, 1);
+  asm volatile("vredor.vs v3, v1, v2, v0.t");
+  VCMP_U16(6, v3, 0xe100);
+
+  VSET(12, e32, m1);
+  VLOAD_8(v0, 0x0e, 0x00);
+  VLOAD_32(v1, 0xf0000fff, 0x10000001, 0x00000000, 0x00000000, 0x10000001,
+           0x00000000, 0x00000000, 0x10000001, 0x00000000, 0x00000000,
+           0x10000001, 0x00000000);
+  VLOAD_32(v2, 0x00001000);
+  VLOAD_32(v3, 1);
+  asm volatile("vredor.vs v3, v1, v2, v0.t");
+  VCMP_U32(7, v3, 0x10001001);
+
+  VSET(12, e64, m1);
+  VLOAD_8(v0, 0xaa, 0x55);
+  VLOAD_64(v1, 0x0000000000000000, 0x1000000000000001, 0x0000f00000000000,
+           0x0000000000000000, 0x1000000000000001, 0x0000000000000000,
+           0x0000000000000000, 0x1000000000000001, 0x0000000000000000,
+           0x0000000000000000, 0x1000000000000001, 0x0000000000000000);
+  VLOAD_64(v2, 0x0000000000000007);
+  VLOAD_64(v3, 1);
+  asm volatile("vredor.vs v3, v1, v2, v0.t");
+  VCMP_U64(8, v3, 0x1000000000000007);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vredsum.c b/apps/riscv-tests/isa/rv64uv/vredsum.c
new file mode 100644
index 0000000..09a1a9b
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vredsum.c
@@ -0,0 +1,178 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+
+#include "vector_macros.h"
+
+// Naive test
+void TEST_CASE1(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v2, 1);
+  asm volatile("vredsum.vs v3, v1, v2");
+  VCMP_U8(1, v3, 73);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v2, 1);
+  asm volatile("vredsum.vs v3, v1, v2");
+  VCMP_U16(2, v3, 73);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v2, 1);
+  asm volatile("vredsum.vs v3, v1, v2");
+  VCMP_U32(3, v3, 73);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_64(v2, 1);
+  asm volatile("vredsum.vs v3, v1, v2");
+  VCMP_U64(4, v3, 73);
+}
+
+// Masked naive test
+void TEST_CASE2(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v0, 0xaa, 0x55);
+  VLOAD_8(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v2, 1);
+  VLOAD_8(v3, 1);
+  asm volatile("vredsum.vs v3, v1, v2, v0.t");
+  VCMP_U8(5, v3, 37);
+
+  VSET(16, e16, m1);
+  VLOAD_8(v0, 0xaa, 0x55);
+  VLOAD_16(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v2, 1);
+  VLOAD_16(v3, 1);
+  asm volatile("vredsum.vs v3, v1, v2, v0.t");
+  VCMP_U16(6, v3, 37);
+
+  VSET(16, e32, m1);
+  VLOAD_8(v0, 0xaa, 0x55);
+  VLOAD_32(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v2, 1);
+  VLOAD_32(v3, 1);
+  asm volatile("vredsum.vs v3, v1, v2, v0.t");
+  VCMP_U32(7, v3, 37);
+
+  VSET(16, e64, m1);
+  VLOAD_8(v0, 0xaa, 0x55);
+  VLOAD_64(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_64(v2, 1);
+  VLOAD_64(v3, 1);
+  asm volatile("vredsum.vs v3, v1, v2, v0.t");
+  VCMP_U64(8, v3, 37);
+}
+
+// Are we respecting the undisturbed tail policy?
+void TEST_CASE3(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v3, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vredsum.vs v3, v1, v2");
+  VCMP_U8(9, v3, 73, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v3, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vredsum.vs v3, v1, v2");
+  VCMP_U16(10, v3, 73, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v3, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vredsum.vs v3, v1, v2");
+  VCMP_U32(11, v3, 73, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_64(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_64(v3, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vredsum.vs v3, v1, v2");
+  VCMP_U64(12, v3, 73, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+}
+
+// Odd number of elements, undisturbed policy
+void TEST_CASE4(void) {
+  VSET(15, e8, m1);
+  VLOAD_8(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v3, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vredsum.vs v3, v1, v2");
+  VCMP_U8(13, v3, 65, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+
+  VSET(1, e16, m1);
+  VLOAD_16(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v3, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vredsum.vs v3, v1, v2");
+  VCMP_U16(14, v3, 2, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+
+  VSET(3, e32, m1);
+  VLOAD_32(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v3, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vredsum.vs v3, v1, v2");
+  VCMP_U32(15, v3, 7, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+
+  VSET(7, e64, m1);
+  VLOAD_64(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_64(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_64(v3, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vredsum.vs v3, v1, v2");
+  VCMP_U64(16, v3, 29, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+
+  VSET(15, e64, m1);
+  VLOAD_64(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_64(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_64(v3, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vredsum.vs v3, v1, v2");
+  VCMP_U64(17, v3, 65, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+}
+
+// Odd number of elements, undisturbed policy, and mask
+void TEST_CASE5(void) {
+  VSET(15, e8, m1);
+  VLOAD_8(v0, 0x00, 0x40);
+  VLOAD_8(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v2, 100, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v3, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vredsum.vs v3, v1, v2, v0.t");
+  VCMP_U8(18, v3, 107, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+
+  VSET(1, e16, m1);
+  VLOAD_8(v0, 0xaa, 0x55);
+  VLOAD_16(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v3, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vredsum.vs v3, v1, v2, v0.t");
+  VCMP_U16(19, v3, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+
+  VSET(3, e32, m1);
+  VLOAD_8(v0, 0xaa, 0x55);
+  VLOAD_32(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v3, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vredsum.vs v3, v1, v2, v0.t");
+  VCMP_U32(20, v3, 3, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vredxor.c b/apps/riscv-tests/isa/rv64uv/vredxor.c
new file mode 100644
index 0000000..0d06f85
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vredxor.c
@@ -0,0 +1,44 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+
+#include "vector_macros.h"
+
+// Naive test
+void TEST_CASE1(void) {
+  VSET(4, e8, m1);
+  VLOAD_8(v1, 0x00, 0x01, 0x01, 0x00);
+  VLOAD_8(v2, 0x11);
+  asm volatile("vredxor.vs v3, v1, v2");
+  VCMP_U8(1, v3, 0x11);
+
+  VSET(4, e16, m1);
+  VLOAD_16(v1, 0x8000, 0x0301, 0x0101, 0x0001);
+  VLOAD_16(v2, 0xe001);
+  asm volatile("vredxor.vs v3, v1, v2");
+  VCMP_U16(2, v3, 0x6200);
+
+  VSET(4, e32, m1);
+  VLOAD_32(v1, 0x00000001, 0x10000001, 0x00000000, 0x00000000);
+  VLOAD_32(v2, 0x00001000);
+  asm volatile("vredxor.vs v3, v1, v2");
+  VCMP_U32(3, v3, 0x10001000);
+
+  VSET(4, e64, m1);
+  VLOAD_64(v1, 0x0000000000000000, 0x1000000000000001, 0x0000000000000000,
+           0x0000000000000000);
+  VLOAD_64(v2, 0x0000000000000007);
+  asm volatile("vredxor.vs v3, v1, v2");
+  VCMP_U64(4, v3, 0x1000000000000006);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vrem.c b/apps/riscv-tests/isa/rv64uv/vrem.c
new file mode 100644
index 0000000..f77ebd5
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vrem.c
@@ -0,0 +1,232 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x9b, 0x28, 0xec, 0x86, 0x26, 0x85, 0xf7, 0x33, 0x46, 0x37, 0x2c,
+          0x0c, 0x8e, 0xae, 0xa1, 0x93);
+  VLOAD_8(v3, 0x84, 0x5e, 0x3b, 0xdf, 0x10, 0xfc, 0x05, 0xcf, 0x42, 0xbe, 0x23,
+          0xdb, 0x37, 0x78, 0xe2, 0x85);
+  asm volatile("vrem.vv v1, v2, v3");
+  VCMP_I8(1, v1, 0x9b, 0x28, 0xec, 0xe9, 0x06, 0xfd, 0xfc, 0x02, 0x04, 0x37,
+          0x09, 0x0c, 0xfc, 0xae, 0xfb, 0x93);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0xb58f, 0xa184, 0xdcf9, 0xd084, 0xbbc6, 0xcf0e, 0xbbd4, 0xa20c,
+           0xe04c, 0xd954, 0xda74, 0xa394, 0x207a, 0x8975, 0xddd3, 0x897d);
+  VLOAD_16(v3, 0x4534, 0xafd7, 0xf703, 0x92c2, 0x97e3, 0xd85a, 0x1540, 0x8c5c,
+           0x4a71, 0x43a7, 0xe65d, 0x2bdc, 0x497b, 0x6aa0, 0x6071, 0xf431);
+  asm volatile("vrem.vv v1, v2, v3");
+  VCMP_I16(2, v1, 0xfac3, 0xf1ad, 0xf7f0, 0xd084, 0xbbc6, 0xf6b4, 0xfb94,
+           0xa20c, 0xe04c, 0xd954, 0xf417, 0xfb4c, 0x207a, 0xf415, 0xddd3,
+           0xff93);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x620db972, 0x60b1f870, 0x7d1badcf, 0x90a85eb6, 0xca41954b,
+           0x10dc3772, 0xf7749e82, 0x027ed4d3, 0xdcb6a562, 0xa979baf0,
+           0xb480c184, 0x979555c6, 0x3f894108, 0x803bd362, 0x9038beec,
+           0x22d7ca24);
+  VLOAD_32(v3, 0xb9b52c0c, 0x30b52d8c, 0x832f89ea, 0x95181d9c, 0x85a6a24f,
+           0x2f2c64a7, 0xebe4120c, 0x83852646, 0xfb1857b5, 0x25400571,
+           0xab2d7393, 0xddb87ac8, 0x01149cdf, 0x62b2c8dc, 0xaed39563,
+           0x41ec046e);
+  asm volatile("vrem.vv v1, v2, v3");
+  VCMP_I32(3, v1, 0x1bc2e57e, 0x2ffccae4, 0x004b37b9, 0xfb90411a, 0xca41954b,
+           0x10dc3772, 0xf7749e82, 0x027ed4d3, 0xff0c3f6f, 0xf3f9c5d2,
+           0xb480c184, 0xfe6be56e, 0x00ddb682, 0xe2ee9c3e, 0xe1652989,
+           0x22d7ca24);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x9fc0a4e82116b913, 0xbd1a679edd2667e1, 0x559913931b91caf2,
+           0xecfe6fb53a8b043d, 0xd8a48a111d080e66, 0x7baccec6b5a29e3e,
+           0x8746dc00d1d7ff0b, 0x467babd497d4931b, 0x6f7f3e669faa900c,
+           0x36e81d34c3ee3445, 0x99bcc4a480c648c5, 0xc8ae527a2cc4d908,
+           0xce3b4c1da847fe6a, 0x3709710bc016c1fc, 0x81471426bbe09e45,
+           0x0f0389282729456f);
+  VLOAD_64(v3, 0xf2473f877dd9c3df, 0xd2471da7c8ff8466, 0x7e93451b38765d03,
+           0xf7e905f27777369f, 0x73cbef014fd0f311, 0x4c3e4fc36800b443,
+           0x4c283e06a5067444, 0xdc8295e57f30e905, 0x08207a363067024e,
+           0x42aba773f21efc47, 0x5f00e9093d50b50f, 0x5ff0dcd41bf799fa,
+           0xe8c1d1110518742a, 0x34fe1a3555bf07f0, 0xd1bce4800f79700f,
+           0xff00f7d87b2c7068);
+  asm volatile("vrem.vv v1, v2, v3");
+  VCMP_I64(4, v1, 0xffcde833b0225dfa, 0xead349f71426e37b, 0x559913931b91caf2,
+           0xfd2c63d04b9c96ff, 0xd8a48a111d080e66, 0x2f6e7f034da1e9fb,
+           0xd36f1a0776de734f, 0x22fe41ba17057c20, 0x05d909a62a6f7216,
+           0x36e81d34c3ee3445, 0xf8bdadadbe16fdd4, 0xc8ae527a2cc4d908,
+           0xfcb7a9fb9e171616, 0x020b56d66a57ba0c, 0xddcd4b269cedbe27,
+           0x00120ed75ec3db87);
+};
+
+void TEST_CASE2(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x9b, 0x28, 0xec, 0x86, 0x26, 0x85, 0xf7, 0x33, 0x46, 0x37, 0x2c,
+          0x0c, 0x8e, 0xae, 0xa1, 0x93);
+  VLOAD_8(v3, 0x84, 0x5e, 0x3b, 0xdf, 0x10, 0xfc, 0x05, 0xcf, 0x42, 0xbe, 0x23,
+          0xdb, 0x37, 0x78, 0xe2, 0x85);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vrem.vv v1, v2, v3, v0.t");
+  VCMP_I8(5, v1, 0, 0x28, 0, 0xe9, 0, 0xfd, 0, 0x02, 0, 0x37, 0, 0x0c, 0, 0xae,
+          0, 0x93);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0xb58f, 0xa184, 0xdcf9, 0xd084, 0xbbc6, 0xcf0e, 0xbbd4, 0xa20c,
+           0xe04c, 0xd954, 0xda74, 0xa394, 0x207a, 0x8975, 0xddd3, 0x897d);
+  VLOAD_16(v3, 0x4534, 0xafd7, 0xf703, 0x92c2, 0x97e3, 0xd85a, 0x1540, 0x8c5c,
+           0x4a71, 0x43a7, 0xe65d, 0x2bdc, 0x497b, 0x6aa0, 0x6071, 0xf431);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vrem.vv v1, v2, v3, v0.t");
+  VCMP_I16(6, v1, 0, 0xf1ad, 0, 0xd084, 0, 0xf6b4, 0, 0xa20c, 0, 0xd954, 0,
+           0xfb4c, 0, 0xf415, 0, 0xff93);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x620db972, 0x60b1f870, 0x7d1badcf, 0x90a85eb6, 0xca41954b,
+           0x10dc3772, 0xf7749e82, 0x027ed4d3, 0xdcb6a562, 0xa979baf0,
+           0xb480c184, 0x979555c6, 0x3f894108, 0x803bd362, 0x9038beec,
+           0x22d7ca24);
+  VLOAD_32(v3, 0xb9b52c0c, 0x30b52d8c, 0x832f89ea, 0x95181d9c, 0x85a6a24f,
+           0x2f2c64a7, 0xebe4120c, 0x83852646, 0xfb1857b5, 0x25400571,
+           0xab2d7393, 0xddb87ac8, 0x01149cdf, 0x62b2c8dc, 0xaed39563,
+           0x41ec046e);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vrem.vv v1, v2, v3, v0.t");
+  VCMP_I32(7, v1, 0, 0x2ffccae4, 0, 0xfb90411a, 0, 0x10dc3772, 0, 0x027ed4d3, 0,
+           0xf3f9c5d2, 0, 0xfe6be56e, 0, 0xe2ee9c3e, 0, 0x22d7ca24);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x9fc0a4e82116b913, 0xbd1a679edd2667e1, 0x559913931b91caf2,
+           0xecfe6fb53a8b043d, 0xd8a48a111d080e66, 0x7baccec6b5a29e3e,
+           0x8746dc00d1d7ff0b, 0x467babd497d4931b, 0x6f7f3e669faa900c,
+           0x36e81d34c3ee3445, 0x99bcc4a480c648c5, 0xc8ae527a2cc4d908,
+           0xce3b4c1da847fe6a, 0x3709710bc016c1fc, 0x81471426bbe09e45,
+           0x0f0389282729456f);
+  VLOAD_64(v3, 0xf2473f877dd9c3df, 0xd2471da7c8ff8466, 0x7e93451b38765d03,
+           0xf7e905f27777369f, 0x73cbef014fd0f311, 0x4c3e4fc36800b443,
+           0x4c283e06a5067444, 0xdc8295e57f30e905, 0x08207a363067024e,
+           0x42aba773f21efc47, 0x5f00e9093d50b50f, 0x5ff0dcd41bf799fa,
+           0xe8c1d1110518742a, 0x34fe1a3555bf07f0, 0xd1bce4800f79700f,
+           0xff00f7d87b2c7068);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vrem.vv v1, v2, v3, v0.t");
+  VCMP_I64(8, v1, 0, 0xead349f71426e37b, 0, 0xfd2c63d04b9c96ff, 0,
+           0x2f6e7f034da1e9fb, 0, 0x22fe41ba17057c20, 0, 0x36e81d34c3ee3445, 0,
+           0xc8ae527a2cc4d908, 0, 0x020b56d66a57ba0c, 0, 0x00120ed75ec3db87);
+};
+
+void TEST_CASE3(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x5b, 0x3b, 0xc4, 0x95, 0x41, 0x71, 0x9b, 0x67, 0x84, 0x2e, 0x0a,
+          0x2a, 0xb2, 0x57, 0xe5, 0x6c);
+  int64_t scalar = 5;
+  asm volatile("vrem.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_I8(9, v1, 0x01, 0x04, 0x00, 0xfe, 0x00, 0x03, 0xff, 0x03, 0xfc, 0x01,
+          0x00, 0x02, 0xfd, 0x02, 0xfe, 0x03);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0xc670, 0x8f3b, 0x200f, 0x52ea, 0xfdce, 0xcf06, 0x57f1, 0x1936,
+           0xb6ec, 0x69e8, 0x0abf, 0x441e, 0xa420, 0x396c, 0xe7c9, 0xa464);
+  scalar = -538;
+  asm volatile("vrem.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_I16(10, v1, 0xff2e, 0xfe9d, 0x0089, 0x00f4, 0xffe8, 0xff5c, 0x01c7,
+           0x0218, 0xfe60, 0x00d4, 0x003d, 0x00de, 0xfe7e, 0x00ae, 0xfee7,
+           0xfec2);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0xf937dbf9, 0x6d855b59, 0x3bd09126, 0xaed11886, 0x6eb6f4bd,
+           0x5c639253, 0xca0f2abf, 0x57fec97b, 0x39496099, 0x8bfcdd58,
+           0x0f19f6e2, 0x2070c8d4, 0x8c689324, 0x2eecd9d7, 0xe2907e94,
+           0xb6cc2d44);
+  scalar = 649;
+  asm volatile("vrem.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_I32(11, v1, 0xfffffee4, 0x00000116, 0x00000160, 0xffffffef, 0x00000217,
+           0x00000275, 0xfffffea6, 0x000000a9, 0x000000e4, 0xfffffe09,
+           0x00000272, 0x0000023c, 0xffffff79, 0x000000ce, 0xffffffb3,
+           0xfffffe0e);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x94236504e03e6525, 0x8d219d7afe5b2fb0, 0xc65a0b252860ab73,
+           0x2ca68636bacbc0bb, 0x275575f3e3fea940, 0x8f546251aaad354a,
+           0xb1462969035e0fa7, 0x5c9cdc19273ce111, 0x25a8487741ee75db,
+           0x38819f95e162663e, 0x698d19ce0e74ff8d, 0xb525257a9b5cd972,
+           0xb308a4fe0dcbb2f3, 0xf2fa735abc2db4d0, 0xc73c476461ac3f28,
+           0xb2830c2607bfffcc);
+  scalar = -59223;
+  asm volatile("vrem.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_I64(12, v1, 0xffffffffffff299e, 0xffffffffffff1f8a, 0xffffffffffff57aa,
+           0x000000000000cc8c, 0x000000000000416e, 0xffffffffffffcecd,
+           0xffffffffffff7e24, 0x000000000000397b, 0x000000000000bb50,
+           0x0000000000006b00, 0x0000000000004f3f, 0xffffffffffff9a21,
+           0xffffffffffffae24, 0xffffffffffffca84, 0xffffffffffffa7fb,
+           0xffffffffffff84dd);
+};
+
+void TEST_CASE4(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x5b, 0x3b, 0xc4, 0x95, 0x41, 0x71, 0x9b, 0x67, 0x84, 0x2e, 0x0a,
+          0x2a, 0xb2, 0x57, 0xe5, 0x6c);
+  int64_t scalar = 5;
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vrem.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_I8(13, v1, 0, 0x04, 0, 0xfe, 0, 0x03, 0, 0x03, 0, 0x01, 0, 0x02, 0, 0x02,
+          0, 0x03);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0xc670, 0x8f3b, 0x200f, 0x52ea, 0xfdce, 0xcf06, 0x57f1, 0x1936,
+           0xb6ec, 0x69e8, 0x0abf, 0x441e, 0xa420, 0x396c, 0xe7c9, 0xa464);
+  scalar = -538;
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vrem.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_I16(14, v1, 0, 0xfe9d, 0, 0x00f4, 0, 0xff5c, 0, 0x0218, 0, 0x00d4, 0,
+           0x00de, 0, 0x00ae, 0, 0xfec2);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0xf937dbf9, 0x6d855b59, 0x3bd09126, 0xaed11886, 0x6eb6f4bd,
+           0x5c639253, 0xca0f2abf, 0x57fec97b, 0x39496099, 0x8bfcdd58,
+           0x0f19f6e2, 0x2070c8d4, 0x8c689324, 0x2eecd9d7, 0xe2907e94,
+           0xb6cc2d44);
+  scalar = 649;
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vrem.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_I32(15, v1, 0, 0x00000116, 0, 0xffffffef, 0, 0x00000275, 0, 0x000000a9,
+           0, 0xfffffe09, 0, 0x0000023c, 0, 0x000000ce, 0, 0xfffffe0e);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x94236504e03e6525, 0x8d219d7afe5b2fb0, 0xc65a0b252860ab73,
+           0x2ca68636bacbc0bb, 0x275575f3e3fea940, 0x8f546251aaad354a,
+           0xb1462969035e0fa7, 0x5c9cdc19273ce111, 0x25a8487741ee75db,
+           0x38819f95e162663e, 0x698d19ce0e74ff8d, 0xb525257a9b5cd972,
+           0xb308a4fe0dcbb2f3, 0xf2fa735abc2db4d0, 0xc73c476461ac3f28,
+           0xb2830c2607bfffcc);
+  scalar = -59223;
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vrem.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_I64(16, v1, 0, 0xffffffffffff1f8a, 0, 0x000000000000cc8c, 0,
+           0xffffffffffffcecd, 0, 0x000000000000397b, 0, 0x0000000000006b00, 0,
+           0xffffffffffff9a21, 0, 0xffffffffffffca84, 0, 0xffffffffffff84dd);
+};
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vremu.c b/apps/riscv-tests/isa/rv64uv/vremu.c
new file mode 100644
index 0000000..b8d8681
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vremu.c
@@ -0,0 +1,232 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x11, 0xd2, 0x6a, 0xcc, 0x14, 0xe4, 0x2c, 0x7f, 0xd2, 0x6b, 0x34,
+          0x5c, 0x75, 0xdd, 0x0c, 0x42);
+  VLOAD_8(v3, 0x77, 0xb2, 0xd1, 0x95, 0x6f, 0xbe, 0x0d, 0x5a, 0x93, 0x02, 0xaf,
+          0xfd, 0x94, 0xe0, 0xb7, 0xe6);
+  asm volatile("vremu.vv v1, v2, v3");
+  VCMP_I8(1, v1, 0x11, 0x20, 0x6a, 0x37, 0x14, 0x26, 0x05, 0x25, 0x3f, 0x01,
+          0x34, 0x5c, 0x75, 0xdd, 0x0c, 0x42);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0xf77a, 0x54d7, 0xe527, 0xe28f, 0x53ed, 0x9301, 0xde4f, 0xcb17,
+           0xae43, 0x9e4a, 0xa0c2, 0xdf31, 0xb66f, 0x286d, 0x1d15, 0x0480);
+  VLOAD_16(v3, 0x5bfa, 0x0571, 0x8a43, 0x6350, 0xb962, 0x71fc, 0x0b54, 0x1e8b,
+           0x6c25, 0x9c0d, 0x5950, 0x1887, 0xbc18, 0x628e, 0x6561, 0x407f);
+  asm volatile("vremu.vv v1, v2, v3");
+  VCMP_I16(2, v1, 0x3f86, 0x0338, 0x5ae4, 0x1bef, 0x53ed, 0x2105, 0x0713,
+           0x13d5, 0x421e, 0x023d, 0x4772, 0x0272, 0xb66f, 0x286d, 0x1d15,
+           0x0480);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x647d8841, 0xf9e0aabf, 0xea4aa122, 0xd6178d3e, 0x64a7afe5,
+           0xe0350cba, 0xc72768ec, 0x9f977a31, 0x5e1c2ac4, 0xcd44b950,
+           0x39dc32f4, 0x1dc82ea3, 0xd1cf125f, 0xc677269c, 0x6405ec5b,
+           0x653a05ee);
+  VLOAD_32(v3, 0x89828d99, 0x5c7c7db0, 0x2911efb6, 0x1f6982ff, 0x564e4bd4,
+           0xc4576bff, 0x8e998104, 0x4a23ba44, 0x994b4630, 0x017ee935,
+           0xa38c7dae, 0x893dfb15, 0x4969125f, 0x9a951d27, 0x09b6017f,
+           0x5a0a7906);
+  asm volatile("vremu.vv v1, v2, v3");
+  VCMP_I32(3, v1, 0x647d8841, 0x40e7af5f, 0x1cf0f294, 0x199e7b44, 0x0e596411,
+           0x1bdda0bb, 0x388de7e8, 0x0b5005a9, 0x5e1c2ac4, 0x0059ebf3,
+           0x39dc32f4, 0x1dc82ea3, 0x3efceda1, 0x2be20975, 0x02e9dd65,
+           0x0b2f8ce8);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x09ab27501ccac4a6, 0x97eb5bf189b39a0e, 0x26f588069b0858c4,
+           0x9a251c274a394df3, 0x54b3587602f8d9d2, 0xc3cc623deda95ca7,
+           0x118c4335397980bf, 0xc3e2d283cb39133d, 0x71837e24114813fc,
+           0x85a1f65867438a09, 0x80f01e0588afc9a0, 0x60e89a1e5a43d9f5,
+           0x93a87cf6308ad888, 0xca3976f49ac6a681, 0xcfc7c8f225b47766,
+           0xeaa4ce2cf507b527);
+  VLOAD_64(v3, 0x9fed81c550326301, 0x445bb7ac18d0eaa1, 0x040f8ff58f5adf72,
+           0xafc4ff6b8eb4d201, 0xfba36cabfc3fb4a0, 0x9c3ed271bf173d29,
+           0xe8b7e325c9ff594b, 0x05169e56693600d7, 0x08e72c4bb62ad267,
+           0xbd9677ee996d5fa5, 0x900295e8502a9817, 0x39e0bfa9927679a8,
+           0xdd0ca7797d532524, 0x6f8f78c47ddee88a, 0x2f40f7661cca9eee,
+           0x8e4a3b2358129e92);
+  asm volatile("vremu.vv v1, v2, v3");
+  VCMP_I64(4, v1, 0x09ab27501ccac4a6, 0x0f33ec995811c4cc, 0x0269786490d67dc2,
+           0x9a251c274a394df3, 0x54b3587602f8d9d2, 0x278d8fcc2e921f7e,
+           0x118c4335397980bf, 0x028751b02d34f353, 0x06ad6a9787463728,
+           0x85a1f65867438a09, 0x80f01e0588afc9a0, 0x2707da74c7cd604d,
+           0x93a87cf6308ad888, 0x5aa9fe301ce7bdf7, 0x12c3eb59b289fbae,
+           0x5c5a93099cf51695);
+};
+
+void TEST_CASE2(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x11, 0xd2, 0x6a, 0xcc, 0x14, 0xe4, 0x2c, 0x7f, 0xd2, 0x6b, 0x34,
+          0x5c, 0x75, 0xdd, 0x0c, 0x42);
+  VLOAD_8(v3, 0x77, 0xb2, 0xd1, 0x95, 0x6f, 0xbe, 0x0d, 0x5a, 0x93, 0x02, 0xaf,
+          0xfd, 0x94, 0xe0, 0xb7, 0xe6);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vremu.vv v1, v2, v3, v0.t");
+  VCMP_I8(5, v1, 0, 0x20, 0, 0x37, 0, 0x26, 0, 0x25, 0, 0x01, 0, 0x5c, 0, 0xdd,
+          0, 0x42);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0xf77a, 0x54d7, 0xe527, 0xe28f, 0x53ed, 0x9301, 0xde4f, 0xcb17,
+           0xae43, 0x9e4a, 0xa0c2, 0xdf31, 0xb66f, 0x286d, 0x1d15, 0x0480);
+  VLOAD_16(v3, 0x5bfa, 0x0571, 0x8a43, 0x6350, 0xb962, 0x71fc, 0x0b54, 0x1e8b,
+           0x6c25, 0x9c0d, 0x5950, 0x1887, 0xbc18, 0x628e, 0x6561, 0x407f);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vremu.vv v1, v2, v3, v0.t");
+  VCMP_I16(6, v1, 0, 0x0338, 0, 0x1bef, 0, 0x2105, 0, 0x13d5, 0, 0x023d, 0,
+           0x0272, 0, 0x286d, 0, 0x0480);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x647d8841, 0xf9e0aabf, 0xea4aa122, 0xd6178d3e, 0x64a7afe5,
+           0xe0350cba, 0xc72768ec, 0x9f977a31, 0x5e1c2ac4, 0xcd44b950,
+           0x39dc32f4, 0x1dc82ea3, 0xd1cf125f, 0xc677269c, 0x6405ec5b,
+           0x653a05ee);
+  VLOAD_32(v3, 0x89828d99, 0x5c7c7db0, 0x2911efb6, 0x1f6982ff, 0x564e4bd4,
+           0xc4576bff, 0x8e998104, 0x4a23ba44, 0x994b4630, 0x017ee935,
+           0xa38c7dae, 0x893dfb15, 0x4969125f, 0x9a951d27, 0x09b6017f,
+           0x5a0a7906);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vremu.vv v1, v2, v3, v0.t");
+  VCMP_I32(7, v1, 0, 0x40e7af5f, 0, 0x199e7b44, 0, 0x1bdda0bb, 0, 0x0b5005a9, 0,
+           0x0059ebf3, 0, 0x1dc82ea3, 0, 0x2be20975, 0, 0x0b2f8ce8);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x09ab27501ccac4a6, 0x97eb5bf189b39a0e, 0x26f588069b0858c4,
+           0x9a251c274a394df3, 0x54b3587602f8d9d2, 0xc3cc623deda95ca7,
+           0x118c4335397980bf, 0xc3e2d283cb39133d, 0x71837e24114813fc,
+           0x85a1f65867438a09, 0x80f01e0588afc9a0, 0x60e89a1e5a43d9f5,
+           0x93a87cf6308ad888, 0xca3976f49ac6a681, 0xcfc7c8f225b47766,
+           0xeaa4ce2cf507b527);
+  VLOAD_64(v3, 0x9fed81c550326301, 0x445bb7ac18d0eaa1, 0x040f8ff58f5adf72,
+           0xafc4ff6b8eb4d201, 0xfba36cabfc3fb4a0, 0x9c3ed271bf173d29,
+           0xe8b7e325c9ff594b, 0x05169e56693600d7, 0x08e72c4bb62ad267,
+           0xbd9677ee996d5fa5, 0x900295e8502a9817, 0x39e0bfa9927679a8,
+           0xdd0ca7797d532524, 0x6f8f78c47ddee88a, 0x2f40f7661cca9eee,
+           0x8e4a3b2358129e92);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vremu.vv v1, v2, v3, v0.t");
+  VCMP_I64(8, v1, 0, 0x0f33ec995811c4cc, 0, 0x9a251c274a394df3, 0,
+           0x278d8fcc2e921f7e, 0, 0x028751b02d34f353, 0, 0x85a1f65867438a09, 0,
+           0x2707da74c7cd604d, 0, 0x5aa9fe301ce7bdf7, 0, 0x5c5a93099cf51695);
+};
+
+void TEST_CASE3(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x98, 0x1a, 0xbe, 0x48, 0x7c, 0xd9, 0x5e, 0x58, 0x2e, 0x46, 0x0c,
+          0x24, 0xc5, 0x2b, 0x37, 0xbe);
+  uint64_t scalar = 5;
+  asm volatile("vremu.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_I8(9, v1, 0x02, 0x01, 0x00, 0x02, 0x04, 0x02, 0x04, 0x03, 0x01, 0x00,
+          0x02, 0x01, 0x02, 0x03, 0x00, 0x00);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0xf11f, 0xb8cd, 0xb686, 0xc226, 0xc35a, 0xd724, 0x03f1, 0xcf10,
+           0xbae0, 0x9f01, 0x1d0f, 0xf53c, 0x5461, 0x341e, 0x9ae7, 0x032b);
+  scalar = 538;
+  asm volatile("vremu.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_I16(10, v1, 0x018b, 0x01f7, 0x01ca, 0x00ce, 0x0202, 0x00c8, 0x01d7,
+           0x011c, 0x01f0, 0x0163, 0x01bd, 0x0174, 0x0051, 0x01ae, 0x017d,
+           0x0111);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x9c36da54, 0x1b1dea93, 0x80be8651, 0x03a23fcf, 0x26973d17,
+           0x521f01df, 0x09e8f77a, 0x5b231aa2, 0xd4bea1df, 0x529b4f34,
+           0x800a5d88, 0xe7b02512, 0xf7954032, 0x48652b8c, 0x8b14b883,
+           0x121a9b8b);
+  scalar = 649;
+  asm volatile("vremu.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_I32(11, v1, 0x00000039, 0x00000141, 0x0000020b, 0x0000015f, 0x0000008a,
+           0x00000199, 0x00000214, 0x0000006c, 0x0000025d, 0x000001a6,
+           0x000000d2, 0x00000168, 0x000001e6, 0x00000266, 0x00000188,
+           0x00000159);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x1882c5f4b911b949, 0x6ca37133428ed155, 0xbacb9408aa8251bf,
+           0x62d79deed97681f5, 0x56258335e007492c, 0x2428afa90a14fa61,
+           0xd62824119c3084c6, 0xef97986ae9ea2da7, 0xfc28c84e37024f10,
+           0x1f475f820dec67e1, 0x9c180cfef468c050, 0x4be017933813e27e,
+           0xafd2b5edb83df693, 0xddd4766a628d4c30, 0xa1f4d0f48a6ac917,
+           0x827a07db9e6a8897);
+  scalar = 9223;
+  asm volatile("vremu.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_I64(12, v1, 0x000000000000167d, 0x00000000000015f2, 0x00000000000019be,
+           0x00000000000003fd, 0x00000000000010ce, 0x0000000000001863,
+           0x0000000000000750, 0x0000000000000062, 0x0000000000002237,
+           0x00000000000002bc, 0x0000000000000061, 0x0000000000001b82,
+           0x0000000000001109, 0x0000000000000fb7, 0x00000000000011e8,
+           0x0000000000000545);
+};
+
+void TEST_CASE4(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x98, 0x1a, 0xbe, 0x48, 0x7c, 0xd9, 0x5e, 0x58, 0x2e, 0x46, 0x0c,
+          0x24, 0xc5, 0x2b, 0x37, 0xbe);
+  uint64_t scalar = 5;
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vremu.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_I8(13, v1, 0, 0x01, 0, 0x02, 0, 0x02, 0, 0x03, 0, 0x00, 0, 0x01, 0, 0x03,
+          0, 0x00);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0xf11f, 0xb8cd, 0xb686, 0xc226, 0xc35a, 0xd724, 0x03f1, 0xcf10,
+           0xbae0, 0x9f01, 0x1d0f, 0xf53c, 0x5461, 0x341e, 0x9ae7, 0x032b);
+  scalar = 538;
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vremu.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_I16(14, v1, 0, 0x01f7, 0, 0x00ce, 0, 0x00c8, 0, 0x011c, 0, 0x0163, 0,
+           0x0174, 0, 0x01ae, 0, 0x0111);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x9c36da54, 0x1b1dea93, 0x80be8651, 0x03a23fcf, 0x26973d17,
+           0x521f01df, 0x09e8f77a, 0x5b231aa2, 0xd4bea1df, 0x529b4f34,
+           0x800a5d88, 0xe7b02512, 0xf7954032, 0x48652b8c, 0x8b14b883,
+           0x121a9b8b);
+  scalar = 649;
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vremu.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_I32(15, v1, 0, 0x00000141, 0, 0x0000015f, 0, 0x00000199, 0, 0x0000006c,
+           0, 0x000001a6, 0, 0x00000168, 0, 0x00000266, 0, 0x00000159);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x1882c5f4b911b949, 0x6ca37133428ed155, 0xbacb9408aa8251bf,
+           0x62d79deed97681f5, 0x56258335e007492c, 0x2428afa90a14fa61,
+           0xd62824119c3084c6, 0xef97986ae9ea2da7, 0xfc28c84e37024f10,
+           0x1f475f820dec67e1, 0x9c180cfef468c050, 0x4be017933813e27e,
+           0xafd2b5edb83df693, 0xddd4766a628d4c30, 0xa1f4d0f48a6ac917,
+           0x827a07db9e6a8897);
+  scalar = 9223;
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v1);
+  asm volatile("vremu.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_I64(16, v1, 0, 0x00000000000015f2, 0, 0x00000000000003fd, 0,
+           0x0000000000001863, 0, 0x0000000000000062, 0, 0x00000000000002bc, 0,
+           0x0000000000001b82, 0, 0x0000000000000fb7, 0, 0x0000000000000545);
+};
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vrgather.c b/apps/riscv-tests/isa/rv64uv/vrgather.c
new file mode 100644
index 0000000..60fe8a9
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vrgather.c
@@ -0,0 +1,340 @@
+// Copyright 2024 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1() {
+  VSET(5, e8, m1);
+  VLOAD_8(v4, 10, 20, 30, 40, 50);
+  VLOAD_8(v6, 1, 0, 4, 3, 2);
+  asm volatile("vrgather.vv v2, v4, v6");
+  VCMP_U8(1, v2, 20, 10, 50, 40, 30);
+
+  VSET(2, e8, m1);
+  VLOAD_8(v4, 10, 20);
+  VLOAD_8(v6, 1, 1);
+  asm volatile("vrgather.vv v2, v4, v6");
+  VCMP_U8(2, v2, 20, 20);
+
+  VSET(256, e32, m4);
+  VLOAD_32(
+      v24, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
+      20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37,
+      38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55,
+      56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73,
+      74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91,
+      92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
+      108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122,
+      123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137,
+      138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152,
+      153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167,
+      168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182,
+      183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197,
+      198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212,
+      213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227,
+      228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242,
+      243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 351);
+  VLOAD_32(v28, 255, 254, 253, 252, 251, 250, 249, 248, 247, 246, 245, 244, 243,
+           242, 241, 240, 239, 238, 237, 236, 235, 234, 233, 232, 231, 230, 229,
+           228, 227, 226, 225, 224, 223, 222, 221, 220, 219, 218, 217, 216, 215,
+           214, 213, 212, 211, 210, 209, 208, 207, 206, 205, 204, 203, 202, 201,
+           200, 199, 198, 197, 196, 195, 194, 193, 192, 191, 190, 189, 188, 187,
+           186, 185, 184, 183, 182, 181, 180, 179, 178, 177, 176, 175, 174, 173,
+           172, 171, 170, 169, 168, 167, 166, 165, 164, 163, 162, 161, 160, 159,
+           158, 157, 156, 155, 154, 153, 152, 151, 150, 149, 148, 147, 146, 145,
+           144, 143, 142, 141, 140, 139, 138, 137, 136, 135, 134, 133, 132, 131,
+           130, 129, 128, 127, 126, 125, 124, 123, 122, 121, 120, 119, 118, 117,
+           116, 115, 114, 113, 112, 111, 110, 109, 108, 107, 106, 105, 104, 103,
+           102, 101, 100, 99, 98, 97, 96, 95, 94, 93, 92, 91, 90, 89, 88, 87,
+           86, 85, 84, 83, 82, 81, 80, 79, 78, 77, 76, 75, 74, 73, 72, 71, 70,
+           69, 68, 67, 66, 65, 64, 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53,
+           52, 51, 50, 49, 48, 47, 46, 45, 44, 43, 42, 41, 40, 39, 38, 37, 36,
+           35, 34, 33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19,
+           18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 255);
+  asm volatile("vrgather.vv v4, v24, v28");
+  VCMP_U32(
+      3, v4, 351, 254, 253, 252, 251, 250, 249, 248, 247, 246, 245, 244, 243,
+      242, 241, 240, 239, 238, 237, 236, 235, 234, 233, 232, 231, 230, 229, 228,
+      227, 226, 225, 224, 223, 222, 221, 220, 219, 218, 217, 216, 215, 214, 213,
+      212, 211, 210, 209, 208, 207, 206, 205, 204, 203, 202, 201, 200, 199, 198,
+      197, 196, 195, 194, 193, 192, 191, 190, 189, 188, 187, 186, 185, 184, 183,
+      182, 181, 180, 179, 178, 177, 176, 175, 174, 173, 172, 171, 170, 169, 168,
+      167, 166, 165, 164, 163, 162, 161, 160, 159, 158, 157, 156, 155, 154, 153,
+      152, 151, 150, 149, 148, 147, 146, 145, 144, 143, 142, 141, 140, 139, 138,
+      137, 136, 135, 134, 133, 132, 131, 130, 129, 128, 127, 126, 125, 124, 123,
+      122, 121, 120, 119, 118, 117, 116, 115, 114, 113, 112, 111, 110, 109, 108,
+      107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, 96, 95, 94, 93, 92,
+      91, 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, 79, 78, 77, 76, 75, 74,
+      73, 72, 71, 70, 69, 68, 67, 66, 65, 64, 63, 62, 61, 60, 59, 58, 57, 56,
+      55, 54, 53, 52, 51, 50, 49, 48, 47, 46, 45, 44, 43, 42, 41, 40, 39, 38,
+      37, 36, 35, 34, 33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20,
+      19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 351);
+
+  VSET(256, e16, m4);
+  VLOAD_32(v24, 255, 254, 253, 252, 251, 250, 249, 248, 247, 246, 245, 244, 243,
+           242, 241, 240, 239, 238, 237, 236, 235, 234, 233, 232, 231, 230, 229,
+           228, 227, 226, 225, 224, 223, 222, 221, 220, 219, 218, 217, 216, 215,
+           214, 213, 212, 211, 210, 209, 208, 207, 206, 205, 204, 203, 202, 201,
+           200, 199, 198, 197, 196, 195, 194, 193, 192, 191, 190, 189, 188, 187,
+           186, 185, 184, 183, 182, 181, 180, 179, 178, 177, 176, 175, 174, 173,
+           172, 171, 170, 169, 168, 167, 166, 165, 164, 163, 162, 161, 160, 159,
+           158, 157, 156, 155, 154, 153, 152, 151, 150, 149, 148, 147, 146, 145,
+           144, 143, 142, 141, 140, 139, 138, 137, 136, 135, 134, 133, 132, 131,
+           130, 129, 128, 127, 126, 125, 124, 123, 122, 121, 120, 119, 118, 117,
+           116, 115, 114, 113, 112, 111, 110, 109, 108, 107, 106, 105, 104, 103,
+           102, 101, 100, 99, 98, 97, 96, 95, 94, 93, 92, 91, 90, 89, 88, 87,
+           86, 85, 84, 83, 82, 81, 80, 79, 78, 77, 76, 75, 74, 73, 72, 71, 70,
+           69, 68, 67, 66, 65, 64, 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53,
+           52, 51, 50, 49, 48, 47, 46, 45, 44, 43, 42, 41, 40, 39, 38, 37, 36,
+           35, 34, 33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19,
+           18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 467);
+  VSET(256, e32, m4);
+  VLOAD_16(
+      v28, 0, 255, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18,
+      19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,
+      37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54,
+      55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72,
+      73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90,
+      91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106,
+      107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121,
+      122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136,
+      137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151,
+      152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166,
+      167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181,
+      182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196,
+      197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211,
+      212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226,
+      227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241,
+      242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255);
+  asm volatile("vrgatherei16.vv v4, v24, v28");
+  VCMP_U32(
+      4, v4, 255, 467, 253, 252, 251, 250, 249, 248, 247, 246, 245, 244, 243,
+      242, 241, 240, 239, 238, 237, 236, 235, 234, 233, 232, 231, 230, 229, 228,
+      227, 226, 225, 224, 223, 222, 221, 220, 219, 218, 217, 216, 215, 214, 213,
+      212, 211, 210, 209, 208, 207, 206, 205, 204, 203, 202, 201, 200, 199, 198,
+      197, 196, 195, 194, 193, 192, 191, 190, 189, 188, 187, 186, 185, 184, 183,
+      182, 181, 180, 179, 178, 177, 176, 175, 174, 173, 172, 171, 170, 169, 168,
+      167, 166, 165, 164, 163, 162, 161, 160, 159, 158, 157, 156, 155, 154, 153,
+      152, 151, 150, 149, 148, 147, 146, 145, 144, 143, 142, 141, 140, 139, 138,
+      137, 136, 135, 134, 133, 132, 131, 130, 129, 128, 127, 126, 125, 124, 123,
+      122, 121, 120, 119, 118, 117, 116, 115, 114, 113, 112, 111, 110, 109, 108,
+      107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, 96, 95, 94, 93, 92,
+      91, 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, 79, 78, 77, 76, 75, 74,
+      73, 72, 71, 70, 69, 68, 67, 66, 65, 64, 63, 62, 61, 60, 59, 58, 57, 56,
+      55, 54, 53, 52, 51, 50, 49, 48, 47, 46, 45, 44, 43, 42, 41, 40, 39, 38,
+      37, 36, 35, 34, 33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20,
+      19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 467);
+}
+
+void TEST_CASE2() {
+  VSET(5, e8, m1);
+  VLOAD_8(v4, 10, 20, 30, 40, 50);
+  VLOAD_8(v6, 1, 0, 4, 3, 2);
+  VLOAD_8(v0, 26, 0, 0, 0, 0);
+  VCLEAR(v2);
+  asm volatile("vrgather.vv v2, v4, v6, v0.t");
+  VCMP_U8(5, v2, 0, 10, 0, 40, 30);
+
+  VSET(1, e64, m4);
+  VLOAD_64(v0, -1);
+  VSET(64, e32, m4);
+  VLOAD_32(v24, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
+           18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34,
+           35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,
+           52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63);
+  VLOAD_32(v12, 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, 50, 49, 48,
+           47, 46, 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, 33, 32, 31,
+           30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14,
+           13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
+  VCLEAR_AT_ONE(v4);
+  asm volatile("vrgather.vv v4, v24, v12, v0.t");
+  VCMP_U32(6, v4, 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, 50, 49,
+           48, 47, 46, 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, 33, 32,
+           31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15,
+           14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
+
+  VSET(1, e64, m4);
+  VLOAD_64(v0, 0xf1ffffffffffffff);
+  VSET(64, e32, m4);
+  VLOAD_32(v24, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
+           18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34,
+           35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,
+           52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63);
+  VLOAD_32(v16, 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, 50, 49, 48,
+           47, 46, 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, 33, 32, 31,
+           30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14,
+           13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0);
+  VCLEAR_AT_ONE(v28);
+  asm volatile("vrgather.vv v28, v24, v16, v0.t");
+  VCMP_U32(7, v28, 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, 50, 49,
+           48, 47, 46, 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, 33, 32,
+           31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15,
+           14, 13, 12, 11, 10, 9, 8, 7, 0xffffffff, 0xffffffff, 0xffffffff, 3,
+           2, 1, 0);
+
+  VSET(4, e64, m4);
+  VLOAD_64(v0, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff,
+           0xffffffffffffffff);
+  VSET(255, e32, m4);
+  VLOAD_32(v24, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
+           18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34,
+           35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,
+           52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68,
+           69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85,
+           86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101,
+           102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115,
+           116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129,
+           130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143,
+           144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157,
+           158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171,
+           172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185,
+           186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199,
+           200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213,
+           214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227,
+           228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241,
+           242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254);
+  VLOAD_32(v28, 253, 254, 253, 252, 251, 250, 249, 248, 247, 246, 245, 244, 243,
+           242, 241, 240, 239, 238, 237, 236, 235, 234, 233, 232, 231, 230, 229,
+           228, 227, 226, 225, 224, 223, 222, 221, 220, 219, 218, 217, 216, 215,
+           214, 213, 212, 211, 210, 209, 208, 207, 206, 205, 204, 203, 202, 201,
+           200, 199, 198, 197, 196, 195, 194, 193, 192, 191, 190, 189, 188, 187,
+           186, 185, 184, 183, 182, 181, 180, 179, 178, 177, 176, 175, 174, 173,
+           172, 171, 170, 169, 168, 167, 166, 165, 164, 163, 162, 161, 160, 159,
+           158, 157, 156, 155, 154, 153, 152, 151, 150, 149, 148, 147, 146, 145,
+           144, 143, 142, 141, 140, 139, 138, 137, 136, 135, 134, 133, 132, 131,
+           130, 129, 128, 127, 126, 125, 124, 123, 122, 121, 120, 119, 118, 117,
+           116, 115, 114, 113, 112, 111, 110, 109, 108, 107, 106, 105, 104, 103,
+           102, 101, 100, 99, 98, 97, 96, 95, 94, 93, 92, 91, 90, 89, 88, 87,
+           86, 85, 84, 83, 82, 81, 80, 79, 78, 77, 76, 75, 74, 73, 72, 71, 70,
+           69, 68, 67, 66, 65, 64, 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53,
+           52, 51, 50, 49, 48, 47, 46, 45, 44, 43, 42, 41, 40, 39, 38, 37, 36,
+           35, 34, 33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19,
+           18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 254);
+  VCLEAR_AT_ONE(v4);
+  asm volatile("vrgather.vv v4, v24, v28, v0.t");
+  VCMP_U32(8, v4, 253, 254, 253, 252, 251, 250, 249, 248, 247, 246, 245, 244,
+           243, 242, 241, 240, 239, 238, 237, 236, 235, 234, 233, 232, 231, 230,
+           229, 228, 227, 226, 225, 224, 223, 222, 221, 220, 219, 218, 217, 216,
+           215, 214, 213, 212, 211, 210, 209, 208, 207, 206, 205, 204, 203, 202,
+           201, 200, 199, 198, 197, 196, 195, 194, 193, 192, 191, 190, 189, 188,
+           187, 186, 185, 184, 183, 182, 181, 180, 179, 178, 177, 176, 175, 174,
+           173, 172, 171, 170, 169, 168, 167, 166, 165, 164, 163, 162, 161, 160,
+           159, 158, 157, 156, 155, 154, 153, 152, 151, 150, 149, 148, 147, 146,
+           145, 144, 143, 142, 141, 140, 139, 138, 137, 136, 135, 134, 133, 132,
+           131, 130, 129, 128, 127, 126, 125, 124, 123, 122, 121, 120, 119, 118,
+           117, 116, 115, 114, 113, 112, 111, 110, 109, 108, 107, 106, 105, 104,
+           103, 102, 101, 100, 99, 98, 97, 96, 95, 94, 93, 92, 91, 90, 89, 88,
+           87, 86, 85, 84, 83, 82, 81, 80, 79, 78, 77, 76, 75, 74, 73, 72, 71,
+           70, 69, 68, 67, 66, 65, 64, 63, 62, 61, 60, 59, 58, 57, 56, 55, 54,
+           53, 52, 51, 50, 49, 48, 47, 46, 45, 44, 43, 42, 41, 40, 39, 38, 37,
+           36, 35, 34, 33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20,
+           19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 254);
+
+  VSET(4, e64, m4);
+  VLOAD_64(v0, -1, -1, -1, 0xf1ffffffffffffff);
+  VSET(255, e32, m4);
+  VLOAD_32(v24, 3, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
+           18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34,
+           35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,
+           52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68,
+           69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85,
+           86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101,
+           102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115,
+           116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129,
+           130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143,
+           144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157,
+           158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171,
+           172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185,
+           186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199,
+           200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213,
+           214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227,
+           228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241,
+           242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254);
+  VLOAD_32(v28, 0, 254, 253, 252, 251, 250, 249, 248, 247, 246, 245, 244, 243,
+           242, 241, 240, 239, 238, 237, 236, 235, 234, 233, 232, 231, 230, 229,
+           228, 227, 226, 225, 224, 223, 222, 221, 220, 219, 218, 217, 216, 215,
+           214, 213, 212, 211, 210, 209, 208, 207, 206, 205, 204, 203, 202, 201,
+           200, 199, 198, 197, 196, 195, 194, 193, 192, 191, 190, 189, 188, 187,
+           186, 185, 184, 183, 182, 181, 180, 179, 178, 177, 176, 175, 174, 173,
+           172, 171, 170, 169, 168, 167, 166, 165, 164, 163, 162, 161, 160, 159,
+           158, 157, 156, 155, 154, 153, 152, 151, 150, 149, 148, 147, 146, 145,
+           144, 143, 142, 141, 140, 139, 138, 137, 136, 135, 134, 133, 132, 131,
+           130, 129, 128, 127, 126, 125, 124, 123, 122, 121, 120, 119, 118, 117,
+           116, 115, 114, 113, 112, 111, 110, 109, 108, 107, 106, 105, 104, 103,
+           102, 101, 100, 99, 98, 97, 96, 95, 94, 93, 92, 91, 90, 89, 88, 87,
+           86, 85, 84, 83, 82, 81, 80, 79, 78, 77, 76, 75, 74, 73, 72, 71, 70,
+           69, 68, 67, 66, 65, 64, 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53,
+           52, 51, 50, 49, 48, 47, 46, 45, 44, 43, 42, 41, 40, 39, 38, 37, 36,
+           35, 34, 33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19,
+           18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1);
+  VCLEAR_AT_ONE(v4);
+  asm volatile("vrgather.vv v4, v24, v28, v0.t");
+  VCMP_U32(9, v4, 3, 254, 253, 252, 251, 250, 249, 248, 247, 246, 245, 244, 243,
+           242, 241, 240, 239, 238, 237, 236, 235, 234, 233, 232, 231, 230, 229,
+           228, 227, 226, 225, 224, 223, 222, 221, 220, 219, 218, 217, 216, 215,
+           214, 213, 212, 211, 210, 209, 208, 207, 206, 205, 204, 203, 202, 201,
+           200, 199, 198, 197, 196, 195, 194, 193, 192, 191, 190, 189, 188, 187,
+           186, 185, 184, 183, 182, 181, 180, 179, 178, 177, 176, 175, 174, 173,
+           172, 171, 170, 169, 168, 167, 166, 165, 164, 163, 162, 161, 160, 159,
+           158, 157, 156, 155, 154, 153, 152, 151, 150, 149, 148, 147, 146, 145,
+           144, 143, 142, 141, 140, 139, 138, 137, 136, 135, 134, 133, 132, 131,
+           130, 129, 128, 127, 126, 125, 124, 123, 122, 121, 120, 119, 118, 117,
+           116, 115, 114, 113, 112, 111, 110, 109, 108, 107, 106, 105, 104, 103,
+           102, 101, 100, 99, 98, 97, 96, 95, 94, 93, 92, 91, 90, 89, 88, 87,
+           86, 85, 84, 83, 82, 81, 80, 79, 78, 77, 76, 75, 74, 73, 72, 71, 70,
+           69, 68, 67, 66, 65, 64, 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53,
+           52, 51, 50, 49, 48, 47, 46, 45, 44, 43, 42, 41, 40, 39, 38, 37, 36,
+           35, 34, 33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19,
+           18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 0xffffffff, 0xffffffff,
+           0xffffffff, 3, 2, 1);
+}
+
+void TEST_CASE3() {
+  VSET(5, e8, m1);
+  VLOAD_8(v4, 10, 20, 30, 40, 50);
+  uint64_t scalar = 3;
+  asm volatile("vrgather.vx v2, v4, %[A]" ::[A] "r"(scalar));
+  VCMP_U8(10, v2, 40, 40, 40, 40, 40);
+}
+
+void TEST_CASE4() {
+  VSET(5, e8, m1);
+  VLOAD_8(v4, 10, 20, 30, 40, 50);
+  uint64_t scalar = 3;
+  VLOAD_8(v0, 7, 0, 0, 0, 0);
+  VCLEAR(v2);
+  asm volatile("vrgather.vx v2, v4, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U8(11, v2, 40, 40, 40, 0, 0);
+}
+
+void TEST_CASE5() {
+  VSET(5, e8, m1);
+  VLOAD_8(v4, 10, 20, 30, 40, 50);
+  asm volatile("vrgather.vi v2, v4, 3");
+  VCMP_U8(12, v2, 40, 40, 40, 40, 40);
+}
+
+void TEST_CASE6() {
+  VSET(5, e8, m1);
+  VLOAD_8(v4, 10, 20, 30, 40, 50);
+  VLOAD_8(v0, 7, 0, 0, 0, 0);
+  VCLEAR(v2);
+  asm volatile("vrgather.vi v2, v4, 3, v0.t");
+  VCMP_U8(13, v2, 40, 40, 40, 0, 0);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+  TEST_CASE6();
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vrsub.c b/apps/riscv-tests/isa/rv64uv/vrsub.c
new file mode 100644
index 0000000..d181c37
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vrsub.c
@@ -0,0 +1,136 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 5, 10, 15, 20, 25, 30, 35, 40, 5, 10, 15, 20, 25, 30, 35, 40);
+  asm volatile("vrsub.vi v3, v1, 10");
+  VCMP_U8(1, v3, 5, 0, -5, -10, -15, -20, -25, -30, 5, 0, -5, -10, -15, -20,
+          -25, -30);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 5, 10, 15, 20, 25, 30, 35, 40, 5, 10, 15, 20, 25, 30, 35, 40);
+  asm volatile("vrsub.vi v3, v1, 10");
+  VCMP_U16(2, v3, 5, 0, -5, -10, -15, -20, -25, -30, 5, 0, -5, -10, -15, -20,
+           -25, -30);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 5, 10, 15, 20, 25, 30, 35, 40, 5, 10, 15, 20, 25, 30, 35, 40);
+  asm volatile("vrsub.vi v3, v1, 10");
+  VCMP_U32(3, v3, 5, 0, -5, -10, -15, -20, -25, -30, 5, 0, -5, -10, -15, -20,
+           -25, -30);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 5, 10, 15, 20, 25, 30, 35, 40, 5, 10, 15, 20, 25, 30, 35, 40);
+  asm volatile("vrsub.vi v3, v1, 10");
+  VCMP_U64(4, v3, 5, 0, -5, -10, -15, -20, -25, -30, 5, 0, -5, -10, -15, -20,
+           -25, -30);
+}
+
+void TEST_CASE2(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 5, 10, 15, 20, 25, 30, 35, 40, 5, 10, 15, 20, 25, 30, 35, 40);
+  VLOAD_8(v0, 0x33, 0x33);
+  VCLEAR(v3);
+  asm volatile("vrsub.vi v3, v1, 10, v0.t");
+  VCMP_U8(5, v3, 5, 0, 0, 0, -15, -20, 0, 0, 5, 0, 0, 0, -15, -20, 0, 0);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 5, 10, 15, 20, 25, 30, 35, 40, 5, 10, 15, 20, 25, 30, 35, 40);
+  VLOAD_8(v0, 0x33, 0x33);
+  VCLEAR(v3);
+  asm volatile("vrsub.vi v3, v1, 10, v0.t");
+  VCMP_U16(6, v3, 5, 0, 0, 0, -15, -20, 0, 0, 5, 0, 0, 0, -15, -20, 0, 0);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 5, 10, 15, 20, 25, 30, 35, 40, 5, 10, 15, 20, 25, 30, 35, 40);
+  VLOAD_8(v0, 0x33, 0x33);
+  VCLEAR(v3);
+  asm volatile("vrsub.vi v3, v1, 10, v0.t");
+  VCMP_U32(7, v3, 5, 0, 0, 0, -15, -20, 0, 0, 5, 0, 0, 0, -15, -20, 0, 0);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 5, 10, 15, 20, 25, 30, 35, 40, 5, 10, 15, 20, 25, 30, 35, 40);
+  VLOAD_8(v0, 0x33, 0x33);
+  VCLEAR(v3);
+  asm volatile("vrsub.vi v3, v1, 10, v0.t");
+  VCMP_U64(8, v3, 5, 0, 0, 0, -15, -20, 0, 0, 5, 0, 0, 0, -15, -20, 0, 0);
+}
+
+void TEST_CASE3(void) {
+  const uint64_t scalar = 25;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 5, 10, 15, 20, 25, 30, 35, 40, 5, 10, 15, 20, 25, 30, 35, 40);
+  asm volatile("vrsub.vx v3, v1, %[A]" ::[A] "r"(scalar));
+  VCMP_U8(9, v3, 20, 15, 10, 5, 0, -5, -10, -15, 20, 15, 10, 5, 0, -5, -10,
+          -15);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 5, 10, 15, 20, 25, 30, 35, 40, 5, 10, 15, 20, 25, 30, 35, 40);
+  asm volatile("vrsub.vx v3, v1, %[A]" ::[A] "r"(scalar));
+  VCMP_U16(10, v3, 20, 15, 10, 5, 0, -5, -10, -15, 20, 15, 10, 5, 0, -5, -10,
+           -15);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 5, 10, 15, 20, 25, 30, 35, 40, 5, 10, 15, 20, 25, 30, 35, 40);
+  asm volatile("vrsub.vx v3, v1, %[A]" ::[A] "r"(scalar));
+  VCMP_U32(11, v3, 20, 15, 10, 5, 0, -5, -10, -15, 20, 15, 10, 5, 0, -5, -10,
+           -15);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 5, 10, 15, 20, 25, 30, 35, 40, 5, 10, 15, 20, 25, 30, 35, 40);
+  asm volatile("vrsub.vx v3, v1, %[A]" ::[A] "r"(scalar));
+  VCMP_U64(12, v3, 20, 15, 10, 5, 0, -5, -10, -15, 20, 15, 10, 5, 0, -5, -10,
+           -15);
+}
+
+void TEST_CASE4(void) {
+  const uint64_t scalar = 25;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 5, 10, 15, 20, 25, 30, 35, 40, 5, 10, 15, 20, 25, 30, 35, 40);
+  VLOAD_8(v0, 0x33, 0x33);
+  VCLEAR(v3);
+  asm volatile("vrsub.vx v3, v1, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U8(13, v3, 20, 15, 0, 0, 0, -5, 0, 0, 20, 15, 0, 0, 0, -5, 0, 0);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 5, 10, 15, 20, 25, 30, 35, 40, 5, 10, 15, 20, 25, 30, 35, 40);
+  VLOAD_8(v0, 0x33, 0x33);
+  VCLEAR(v3);
+  asm volatile("vrsub.vx v3, v1, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U16(14, v3, 20, 15, 0, 0, 0, -5, 0, 0, 20, 15, 0, 0, 0, -5, 0, 0);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 5, 10, 15, 20, 25, 30, 35, 40, 5, 10, 15, 20, 25, 30, 35, 40);
+  VLOAD_8(v0, 0x33, 0x33);
+  VCLEAR(v3);
+  asm volatile("vrsub.vx v3, v1, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U32(15, v3, 20, 15, 0, 0, 0, -5, 0, 0, 20, 15, 0, 0, 0, -5, 0, 0);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 5, 10, 15, 20, 25, 30, 35, 40, 5, 10, 15, 20, 25, 30, 35, 40);
+  VLOAD_8(v0, 0x33, 0x33);
+  VCLEAR(v3);
+  asm volatile("vrsub.vx v3, v1, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U64(16, v3, 20, 15, 0, 0, 0, -5, 0, 0, 20, 15, 0, 0, 0, -5, 0, 0);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vs.c b/apps/riscv-tests/isa/rv64uv/vs.c
new file mode 100644
index 0000000..5db3a5c
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vs.c
@@ -0,0 +1,93 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+
+#include "vector_macros.h"
+
+#define AXI_DWIDTH 128
+
+static volatile uint8_t ALIGNED_O8[16] __attribute__((aligned(AXI_DWIDTH))) = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
+
+static volatile uint16_t ALIGNED_O16[16]
+    __attribute__((aligned(AXI_DWIDTH))) = {
+        0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+        0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000};
+
+static volatile uint32_t ALIGNED_O32[16]
+    __attribute__((aligned(AXI_DWIDTH))) = {
+        0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+        0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+        0x00000000, 0x00000000, 0x00000000, 0x00000000};
+
+static volatile uint64_t ALIGNED_O64[16]
+    __attribute__((aligned(AXI_DWIDTH))) = {
+        0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+        0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+        0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+        0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+        0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+        0x0000000000000000};
+
+// Misaligned access wrt 128-bit
+void TEST_CASE1(void) {
+  VSET(15, e8, m1);
+  VLOAD_8(v1, 0xe4, 0x19, 0x20, 0x9f, 0xe4, 0x19, 0x20, 0x9f, 0xe4, 0x19, 0x20,
+          0x9f, 0xe4, 0x19, 0x20);
+  asm volatile("vse8.v v1, (%0)" ::"r"(&ALIGNED_O8[1]));
+  VVCMP_U8(1, ALIGNED_O8, 0x00, 0xe4, 0x19, 0x20, 0x9f, 0xe4, 0x19, 0x20, 0x9f,
+           0xe4, 0x19, 0x20, 0x9f, 0xe4, 0x19, 0x20);
+}
+
+void TEST_CASE2(void) {
+  VSET(15, e16, m1);
+  VLOAD_16(v1, 0xe478, 0x1549, 0x3240, 0x2f11, 0xe448, 0x1546, 0x3220, 0x9f11,
+           0xe478, 0x1549, 0x3240, 0x2f11, 0xe448, 0x1546, 0x3220);
+  asm volatile("vse16.v v1, (%0)" ::"r"(&ALIGNED_O16[1]));
+  VVCMP_U16(2, ALIGNED_O16, 0x0000, 0xe478, 0x1549, 0x3240, 0x2f11, 0xe448,
+            0x1546, 0x3220, 0x9f11, 0xe478, 0x1549, 0x3240, 0x2f11, 0xe448,
+            0x1546, 0x3220);
+}
+
+void TEST_CASE3(void) {
+  VSET(15, e32, m1);
+  VLOAD_32(v1, 0xe1356784, 0x13241139, 0x20862497, 0x9f872456, 0xe1356784,
+           0x13241139, 0x20862497, 0x9f872456, 0xe1356784, 0x13241139,
+           0x20862497, 0x9f872456, 0xe1356784, 0x13241139, 0x20862497);
+  asm volatile("vse32.v v1, (%0)" ::"r"(&ALIGNED_O32[1]));
+  VVCMP_U32(3, ALIGNED_O32, 0x00000000, 0xe1356784, 0x13241139, 0x20862497,
+            0x9f872456, 0xe1356784, 0x13241139, 0x20862497, 0x9f872456,
+            0xe1356784, 0x13241139, 0x20862497, 0x9f872456, 0xe1356784,
+            0x13241139, 0x20862497);
+}
+
+void TEST_CASE4(void) {
+  VSET(15, e64, m1);
+  VLOAD_64(v1, 0xe135578794246784, 0x1315345345241139, 0x2086252110062497,
+           0x1100229933847136, 0xaaffaaffaaffaaff, 0xaf87245315434136,
+           0xa135578794246784, 0x2315345345241139, 0x1086252110062497,
+           0x1100229933847134, 0xaaffaaffaaffaaf4, 0x9315345345241139,
+           0x9086252110062497, 0x9100229933847134, 0x9affaaffaaffaaf4);
+  asm volatile("vse64.v v1, (%0)" ::"r"(&ALIGNED_O64[1]));
+  VVCMP_U64(4, ALIGNED_O64, 0x0000000000000000, 0xe135578794246784,
+            0x1315345345241139, 0x2086252110062497, 0x1100229933847136,
+            0xaaffaaffaaffaaff, 0xaf87245315434136, 0xa135578794246784,
+            0x2315345345241139, 0x1086252110062497, 0x1100229933847134,
+            0xaaffaaffaaffaaf4, 0x9315345345241139, 0x9086252110062497,
+            0x9100229933847134, 0x9affaaffaaffaaf4);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vs1r.c b/apps/riscv-tests/isa/rv64uv/vs1r.c
new file mode 100644
index 0000000..ffcbd3f
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vs1r.c
@@ -0,0 +1,162 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti
+//
+// For simplicity, this test depends on vl1r
+
+#include "vector_macros.h"
+
+uint64_t counter;
+
+// Maximum size: (VLEN/8 Bytes * (MAX_LMUL == 8)) = VLEN
+// Define VLEN before compiling me
+// #define VLEN 4096
+uint8_t gold_vec_8b[VLEN];
+uint8_t zero_vec_8b[VLEN];
+uint8_t buf_vec_8b[VLEN];
+
+//////////
+// vs1r //
+//////////
+
+// 1 whole register load
+void TEST_CASE1(void) {
+  // Initialize a golden vector
+  INIT_MEM_CNT(gold_vec_8b, VLEN / 8);
+  // Initialize a zero golden vector
+  INIT_MEM_ZEROES(zero_vec_8b, VLEN / 8);
+  // Reserve space for a buffer in memory
+  INIT_MEM_ZEROES(buf_vec_8b, VLEN / 8);
+  // Set vl and vtype to super short values
+  VSET(1, e64, m2);
+  // Initialize register + neighbours to pattern value
+  VCLEAR(v16);
+  // Load a buffer from memory - whole register load
+  asm volatile("vl1re8.v v16, (%0)" ::"r"(gold_vec_8b));
+  // Check that the whole register was loaded
+  asm volatile("vs1r.v v16, (%0)" ::"r"(buf_vec_8b));
+  VMCMP(uint8_t, % hhu, 0, buf_vec_8b, gold_vec_8b, VLEN / 8);
+  // Check that the neighbour registers are okay
+  asm volatile("vs1r.v v17, (%0)" ::"r"(buf_vec_8b));
+  VMCMP(uint8_t, % hhu, 0, buf_vec_8b, zero_vec_8b, VLEN / 8);
+}
+
+//////////
+// vs2r //
+//////////
+
+// 2 whole registers load
+void TEST_CASE2(void) {
+  // Initialize a golden vector
+  INIT_MEM_CNT(gold_vec_8b, VLEN / 4);
+  // Initialize a zero golden vector
+  INIT_MEM_ZEROES(zero_vec_8b, VLEN / 4);
+  // Reserve space for a buffer in memory
+  INIT_MEM_ZEROES(buf_vec_8b, VLEN / 4);
+  // Set vl and vtype to super short values
+  VSET(1, e64, m4);
+  // Initialize register + neighbours to pattern value
+  VCLEAR(v16);
+  // Load a buffer from memory - whole register load
+  asm volatile("vl2re8.v v16, (%0)" ::"r"(gold_vec_8b));
+  // Check that the whole register was loaded
+  asm volatile("vs2r.v v16, (%0)" ::"r"(buf_vec_8b));
+  VMCMP(uint8_t, % hhu, 1, buf_vec_8b, gold_vec_8b, VLEN / 8);
+  // Check that the neighbour registers are okay
+  asm volatile("vs2r.v v18, (%0)" ::"r"(buf_vec_8b));
+  VMCMP(uint8_t, % hhu, 1, buf_vec_8b, zero_vec_8b, VLEN / 8);
+}
+
+//////////
+// vs4r //
+//////////
+
+// 4 whole registers load
+void TEST_CASE3(void) {
+  // Initialize a golden vector
+  INIT_MEM_CNT(gold_vec_8b, VLEN / 2);
+  // Initialize a zero golden vector
+  INIT_MEM_ZEROES(zero_vec_8b, VLEN / 2);
+  // Reserve space for a buffer in memory
+  INIT_MEM_ZEROES(buf_vec_8b, VLEN / 2);
+  // Set vl and vtype to super short values
+  VSET(1, e64, m8);
+  // Initialize register + neighbours to pattern value
+  VCLEAR(v16);
+  // Load a buffer from memory - whole register load
+  asm volatile("vl4re8.v v16, (%0)" ::"r"(gold_vec_8b));
+  // Check that the whole register was loaded
+  asm volatile("vs4r.v v16, (%0)" ::"r"(buf_vec_8b));
+  VMCMP(uint8_t, % hhu, 2, buf_vec_8b, gold_vec_8b, VLEN / 8);
+  // Check that the neighbour registers are okay
+  asm volatile("vs4r.v v20, (%0)" ::"r"(buf_vec_8b));
+  VMCMP(uint8_t, % hhu, 2, buf_vec_8b, zero_vec_8b, VLEN / 8);
+}
+
+//////////
+// vs8r //
+//////////
+
+// 8 whole registers load
+void TEST_CASE4(void) {
+  // Initialize a golden vector
+  INIT_MEM_CNT(gold_vec_8b, VLEN);
+  // Initialize a zero golden vector
+  INIT_MEM_ZEROES(zero_vec_8b, VLEN);
+  // Reserve space for a buffer in memory
+  INIT_MEM_ZEROES(buf_vec_8b, VLEN);
+  // Set vl and vtype to super short values
+  VSET(1, e64, m8);
+  // Initialize register + neighbours to pattern value
+  VCLEAR(v16);
+  VCLEAR(v24);
+  // Load a buffer from memory - whole register load
+  asm volatile("vl8re8.v v16, (%0)" ::"r"(gold_vec_8b));
+  // Check that the whole register was loaded
+  asm volatile("vs8r.v v16, (%0)" ::"r"(buf_vec_8b));
+  VMCMP(uint8_t, % hhu, 3, buf_vec_8b, gold_vec_8b, VLEN / 8);
+  // Check that the neighbour registers are okay
+  asm volatile("vs8r.v v24, (%0)" ::"r"(buf_vec_8b));
+  VMCMP(uint8_t, % hhu, 3, buf_vec_8b, zero_vec_8b, VLEN / 8);
+}
+
+////////////
+// Others //
+////////////
+
+// Check with initial vl == 0
+void TEST_CASE5(void) {
+  // Initialize a golden vector
+  INIT_MEM_CNT(gold_vec_8b, VLEN / 8);
+  // Initialize a zero golden vector
+  INIT_MEM_ZEROES(zero_vec_8b, VLEN / 8);
+  // Reserve space for a buffer in memory
+  INIT_MEM_ZEROES(buf_vec_8b, VLEN / 8);
+  // Set vl and vtype to super short values
+  VSET(0, e64, m2);
+  // Initialize register + neighbours to pattern value
+  VCLEAR(v16);
+  // Load a buffer from memory - whole register load
+  asm volatile("vl1re8.v v16, (%0)" ::"r"(gold_vec_8b));
+  // Check that the whole register was loaded
+  asm volatile("vs1r.v v16, (%0)" ::"r"(buf_vec_8b));
+  VMCMP(uint8_t, % hhu, 4, buf_vec_8b, gold_vec_8b, VLEN / 8);
+  // Check that the neighbour registers are okay
+  asm volatile("vs1r.v v17, (%0)" ::"r"(buf_vec_8b));
+  VMCMP(uint8_t, % hhu, 4, buf_vec_8b, zero_vec_8b, VLEN / 8);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vsadd.c b/apps/riscv-tests/isa/rv64uv/vsadd.c
new file mode 100644
index 0000000..cd224c7
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vsadd.c
@@ -0,0 +1,99 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  uint64_t vxsat;
+  VSET(4, e8, m1);
+  VLOAD_8(v1, -80, 2, 100, 4);
+  VLOAD_8(v2, -90, 2, 50, 4);
+  __asm__ volatile("vsadd.vv v3, v1, v2" ::);
+  VCMP_U8(1, v3, 0x80, 4, 127, 8);
+  read_vxsat(vxsat);
+  check_vxsat(1, vxsat, 1);
+  reset_vxsat;
+}
+
+void TEST_CASE2(void) {
+  uint64_t vxsat;
+  VSET(4, e8, m1);
+  VLOAD_8(v1, -80, 2, 100, 4);
+  VLOAD_8(v2, -90, 2, 50, 4);
+  VLOAD_8(v0, 0xA, 0x0, 0x0, 0x0);
+  VCLEAR(v3);
+  __asm__ volatile("vsadd.vv v3, v1, v2, v0.t" ::);
+  VCMP_U8(2, v3, 0, 4, 0, 8);
+  read_vxsat(vxsat);
+  check_vxsat(2, vxsat, 0);
+  reset_vxsat;
+}
+
+void TEST_CASE3(void) {
+  uint64_t vxsat;
+  VSET(4, e32, m1);
+  VLOAD_32(v1, 1, 0x7FFFFFFB, 3, 4);
+  __asm__ volatile("vsadd.vi v3, v1, 5" ::);
+  VCMP_U32(3, v3, 6, 0x7FFFFFFF, 8, 9);
+  read_vxsat(vxsat);
+  check_vxsat(3, vxsat, 1);
+  reset_vxsat;
+}
+
+// Dont use VCLEAR here, it results in a glitch where are values are off by 1
+void TEST_CASE4(void) {
+  uint64_t vxsat;
+  VSET(4, e32, m1);
+  VLOAD_32(v1, 1, 2, 0xFFFFFFFD, 0x7FFFFFFC);
+  VLOAD_32(v0, 0xA, 0x0, 0x0, 0x0);
+  VCLEAR(v3);
+  __asm__ volatile("vsadd.vi v3, v1, 5, v0.t" ::);
+  VCMP_U32(4, v3, 0, 7, 0, 0x7FFFFFFF);
+  read_vxsat(vxsat);
+  check_vxsat(4, vxsat, 1);
+  reset_vxsat;
+}
+
+void TEST_CASE5(void) {
+  uint64_t vxsat;
+  VSET(4, e32, m1);
+  VLOAD_32(v1, 0x7FFFFFFD, 2, 3, 4);
+  const uint32_t scalar = 5;
+  __asm__ volatile("vsadd.vx v3, v1, %[A]" ::[A] "r"(scalar));
+  VCMP_U32(5, v3, 0x7FFFFFFF, 7, 8, 9);
+  read_vxsat(vxsat);
+  check_vxsat(5, vxsat, 1);
+  reset_vxsat;
+}
+
+// Dont use VCLEAR here, it results in a glitch where are values are off by 1
+void TEST_CASE6(void) {
+  uint64_t vxsat;
+  VSET(4, e32, m1);
+  VLOAD_32(v1, 1, 0x7ffffffC, 3, 4);
+  const uint32_t scalar = 5;
+  VLOAD_32(v0, 0xA, 0x0, 0x0, 0x0);
+  VCLEAR(v3);
+  __asm__ volatile("vsadd.vx v3, v1, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U32(6, v3, 0, 0x7FFFFFFF, 0, 9);
+  read_vxsat(vxsat);
+  check_vxsat(6, vxsat, 1);
+  reset_vxsat;
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+  enable_fp();
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+  TEST_CASE6();
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vsaddu.c b/apps/riscv-tests/isa/rv64uv/vsaddu.c
new file mode 100644
index 0000000..bdfa154
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vsaddu.c
@@ -0,0 +1,113 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  uint64_t vxsat;
+  VSET(4, e8, m1);
+  VLOAD_8(v1, 133, 2, 220, 4);
+  VLOAD_8(v2, 133, 2, 50, 4);
+  __asm__ volatile("vsaddu.vv v3, v1, v2" ::);
+  VCMP_U8(1, v3, 255, 4, 255, 8);
+  read_vxsat(vxsat);
+  check_vxsat(1, vxsat, 1);
+  reset_vxsat;
+}
+
+void TEST_CASE2(void) {
+  uint64_t vxsat;
+  VSET(4, e8, m1);
+  VLOAD_8(v1, 1, 2, 3, 154);
+  VLOAD_8(v2, 1, 2, 3, 124);
+  VLOAD_8(v0, 0xA, 0x0, 0x0, 0x0);
+  VCLEAR(v3);
+  __asm__ volatile("vsaddu.vv v3, v1, v2, v0.t" ::);
+  VCMP_U8(2, v3, 0, 4, 0, 255);
+  read_vxsat(vxsat);
+  check_vxsat(2, vxsat, 1);
+  reset_vxsat;
+}
+
+void TEST_CASE3(void) {
+  uint64_t vxsat;
+  VSET(4, e32, m1);
+  VLOAD_32(v1, 1, 0xFFFFFFFB, 3, 4);
+  __asm__ volatile("vsaddu.vi v3, v1, 5" ::);
+  VCMP_U32(3, v3, 6, 0xFFFFFFFF, 8, 9);
+  read_vxsat(vxsat);
+  check_vxsat(3, vxsat, 1);
+  reset_vxsat;
+}
+
+// Dont use VCLEAR here, it results in a glitch where are values are off by 1
+void TEST_CASE4(void) {
+  uint64_t vxsat;
+  VSET(4, e32, m1);
+  VLOAD_32(v1, 1, 2, 0xFFFFFFFD, 0xFFFFFFFC);
+  VLOAD_32(v0, 0xA, 0x0, 0x0, 0x0);
+  VCLEAR(v3);
+  __asm__ volatile("vsaddu.vi v3, v1, 5, v0.t" ::);
+  VCMP_U32(4, v3, 0, 7, 0, 0xFFFFFFFF);
+  read_vxsat(vxsat);
+  check_vxsat(4, vxsat, 1);
+  reset_vxsat;
+}
+
+void TEST_CASE5(void) {
+  uint64_t vxsat;
+  VSET(4, e32, m1);
+  VLOAD_32(v1, 0xFFFFFFFD, 2, 3, 4);
+  const uint32_t scalar = 5;
+  __asm__ volatile("vsaddu.vx v3, v1, %[A]" ::[A] "r"(scalar));
+  VCMP_U32(5, v3, 0xFFFFFFFF, 7, 8, 9);
+  read_vxsat(vxsat);
+  check_vxsat(5, vxsat, 1);
+  reset_vxsat;
+}
+
+// Dont use VCLEAR here, it results in a glitch where are values are off by 1
+void TEST_CASE6(void) {
+  uint64_t vxsat;
+  VSET(4, e32, m1);
+  VLOAD_32(v1, 1, 0xfffffffC, 3, 4);
+  const uint32_t scalar = 5;
+  VLOAD_32(v0, 0xA, 0x0, 0x0, 0x0);
+  VCLEAR(v3);
+  __asm__ volatile("vsaddu.vx v3, v1, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U32(6, v3, 0, 0xFFFFFFFF, 0, 9);
+  read_vxsat(vxsat);
+  check_vxsat(6, vxsat, 1);
+  reset_vxsat;
+}
+
+void TEST_CASE7(void) {
+  uint64_t vxsat;
+  VSET(4, e32, m1);
+  VLOAD_32(v1, 1, 0x0000FFFF, 3, 4);
+  VLOAD_32(v2, 0xA, 0xFFFF0000, 0x0, 0x0);
+  VCLEAR(v3);
+  __asm__ volatile("vsaddu.vv v3, v1, v2" ::);
+  VCMP_U32(7, v3, 0xB, 0xFFFFFFFF, 3, 4);
+  read_vxsat(vxsat);
+  check_vxsat(7, vxsat, 0);
+  reset_vxsat;
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+  enable_fp();
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+  TEST_CASE6();
+  TEST_CASE7();
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vsbc.c b/apps/riscv-tests/isa/rv64uv/vsbc.c
new file mode 100644
index 0000000..763c32c
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vsbc.c
@@ -0,0 +1,76 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v2, 8, 7, 6, 5, 4, 3, 2, 1, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vsbc.vvm v3, v1, v2, v0");
+  VCMP_U8(1, v3, -7, -6, -3, -2, 1, 2, 5, 6, 0, -1, 0, -1, 0, -1, 0, -1);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v2, 8, 7, 6, 5, 4, 3, 2, 1, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vsbc.vvm v3, v1, v2, v0");
+  VCMP_U16(2, v3, -7, -6, -3, -2, 1, 2, 5, 6, 0, -1, 0, -1, 0, -1, 0, -1);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v2, 8, 7, 6, 5, 4, 3, 2, 1, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vsbc.vvm v3, v1, v2, v0");
+  VCMP_U32(3, v3, -7, -6, -3, -2, 1, 2, 5, 6, 0, -1, 0, -1, 0, -1, 0, -1);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_64(v2, 8, 7, 6, 5, 4, 3, 2, 1, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vsbc.vvm v3, v1, v2, v0");
+  VCMP_U64(4, v3, -7, -6, -3, -2, 1, 2, 5, 6, 0, -1, 0, -1, 0, -1, 0, -1);
+};
+
+void TEST_CASE2(void) {
+  const uint32_t scalar = 5;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vsbc.vxm v3, v1, %[A], v0" ::[A] "r"(scalar));
+  VCMP_U8(5, v3, -4, -4, -2, -2, 0, 0, 2, 2, -4, -4, -2, -2, 0, 0, 2, 2);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vsbc.vxm v3, v1, %[A], v0" ::[A] "r"(scalar));
+  VCMP_U16(6, v3, -4, -4, -2, -2, 0, 0, 2, 2, -4, -4, -2, -2, 0, 0, 2, 2);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vsbc.vxm v3, v1, %[A], v0" ::[A] "r"(scalar));
+  VCMP_U32(7, v3, -4, -4, -2, -2, 0, 0, 2, 2, -4, -4, -2, -2, 0, 0, 2, 2);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vsbc.vxm v3, v1, %[A], v0" ::[A] "r"(scalar));
+  VCMP_U64(8, v3, -4, -4, -2, -2, 0, 0, 2, 2, -4, -4, -2, -2, 0, 0, 2, 2);
+};
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vse1.c b/apps/riscv-tests/isa/rv64uv/vse1.c
new file mode 100644
index 0000000..517caf5
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vse1.c
@@ -0,0 +1,57 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+//
+// For simplicity, this test depends on vle1
+
+#include "vector_macros.h"
+
+#define AXI_DWIDTH 128
+
+static volatile uint8_t ALIGNED_I8_GOLD[16]
+    __attribute__((aligned(AXI_DWIDTH))) = {0xe0, 0xd3, 0x40, 0xd1, 0x84, 0x48,
+                                            0x89, 0x88, 0x88, 0xae, 0x08, 0x91,
+                                            0x02, 0x59, 0x11, 0x89};
+
+static volatile uint8_t ALIGNED_I8_BUF[16]
+    __attribute__((aligned(AXI_DWIDTH))) = {0x00, 0x00, 0x00, 0x0,  0x00, 0x00,
+                                            0x00, 0x0,  0x00, 0x00, 0x00, 0x0,
+                                            0x00, 0x00, 0x00, 0x0};
+
+void TEST_CASE1(void) {
+  VSET(32, e8, m1);
+  asm volatile("vle1.v v0, (%0)" ::"r"(ALIGNED_I8_GOLD));
+  asm volatile("vse1.v v0, (%0)" ::"r"(ALIGNED_I8_BUF));
+  VMCMP(uint8_t, % hhu, 1, ALIGNED_I8_BUF, ALIGNED_I8_GOLD, 4);
+
+  VSET(29, e8, m1);
+  asm volatile("vle1.v v0, (%0)" ::"r"(ALIGNED_I8_GOLD));
+  asm volatile("vse1.v v0, (%0)" ::"r"(ALIGNED_I8_BUF));
+  VMCMP(uint8_t, % hhu, 2, ALIGNED_I8_BUF, ALIGNED_I8_GOLD, 4);
+
+  VSET(29, e64, m1);
+  asm volatile("vle1.v v0, (%0)" ::"r"(ALIGNED_I8_GOLD));
+  asm volatile("vse1.v v0, (%0)" ::"r"(ALIGNED_I8_BUF));
+  VMCMP(uint8_t, % hhu, 3, ALIGNED_I8_BUF, ALIGNED_I8_GOLD, 4);
+
+  VSET(29, e64, m8);
+  asm volatile("vle1.v v0, (%0)" ::"r"(ALIGNED_I8_GOLD));
+  asm volatile("vse1.v v0, (%0)" ::"r"(ALIGNED_I8_BUF));
+  VMCMP(uint8_t, % hhu, 4, ALIGNED_I8_BUF, ALIGNED_I8_GOLD, 4);
+
+  VSET(29, e64, m8);
+  asm volatile("vle1.v v1, (%0)" ::"r"(ALIGNED_I8_GOLD));
+  asm volatile("vse1.v v1, (%0)" ::"r"(ALIGNED_I8_BUF));
+  VMCMP(uint8_t, % hhu, 5, ALIGNED_I8_BUF, ALIGNED_I8_GOLD, 4);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vse16.c b/apps/riscv-tests/isa/rv64uv/vse16.c
new file mode 100644
index 0000000..23a998e
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vse16.c
@@ -0,0 +1,360 @@
+// TODO uncomment TEST_CASE13 and TEST_CASE 15 after issue of vl=0 and
+// non-zero vstart is resolved
+// TODO uncomment TEST_CASE2 after issue of exception is resolved
+#include "long_array.h"
+#include "vector_macros.h"
+
+#define AXI_DWIDTH 128
+void mtvec_handler(void) {
+  asm volatile("csrr t0, mcause"); // Read mcause
+
+  // Read mepc
+  asm volatile("csrr t1, mepc");
+
+  // Increment return address by 4
+  asm volatile("addi t1, t1, 4");
+  asm volatile("csrw mepc, t1");
+
+  // Filter with mcause and handle here
+
+  asm volatile("mret");
+}
+
+// Exception Handler for spike
+void handle_trap(void) {
+  // Read mepc
+  asm volatile("csrr t1, mepc");
+
+  // Increment return address by 4
+  asm volatile("addi t1, t1, 4");
+  asm volatile("csrw mepc, t1");
+
+  asm volatile("ld ra, 8(sp)");
+  asm volatile("ld sp, 16(sp)");
+  asm volatile("ld gp, 24(sp)");
+  asm volatile("ld tp, 32(sp)");
+  asm volatile("ld t0, 40(sp)");
+  asm volatile("ld t0, 40(sp)");
+  asm volatile("ld t1, 48(sp)");
+  asm volatile("ld t2, 56(sp)");
+  asm volatile("ld s0, 64(sp)");
+  asm volatile("ld s1, 72(sp)");
+  asm volatile("ld a0, 80(sp)");
+  asm volatile("ld a1, 88(sp)");
+  asm volatile("ld a2, 96(sp)");
+  asm volatile("ld a3, 104(sp)");
+  asm volatile("ld a4, 112(sp)");
+  asm volatile("ld a5, 120(sp)");
+  asm volatile("ld a6, 128(sp)");
+  asm volatile("ld a7, 136(sp)");
+  asm volatile("ld s2, 144(sp)");
+  asm volatile("ld s3, 152(sp)");
+  asm volatile("ld s4, 160(sp)");
+  asm volatile("ld s5, 168(sp)");
+  asm volatile("ld s6, 176(sp)");
+  asm volatile("ld s7, 184(sp)");
+  asm volatile("ld s8, 192(sp)");
+  asm volatile("ld s9, 200(sp)");
+  asm volatile("ld s10, 208(sp)");
+  asm volatile("ld s11, 216(sp)");
+  asm volatile("ld t3, 224(sp)");
+  asm volatile("ld t4, 232(sp)");
+  asm volatile("ld t5, 240(sp)");
+  asm volatile("ld t6, 248(sp)");
+
+  // Read mcause
+  asm volatile("csrr t3, mcause");
+
+  asm volatile("addi sp, sp, 272");
+
+  // Filter with mcause and handle here
+
+  asm volatile("mret");
+}
+
+void reset_vec16(volatile uint16_t *vec) {
+  for (uint64_t i = 0; i < 1024; ++i)
+    vec[i] = 0;
+}
+
+static volatile uint16_t ALIGNED_I16[1024] __attribute__((aligned(AXI_DWIDTH)));
+
+//**********Checking functionality of vse16 ********//
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  VLOAD_16(v0, 0x05e0, 0xbbd3, 0x3840, 0x8cd1, 0x9384, 0x7548, 0x3489, 0x9388,
+           0x8188, 0x11ae, 0x5808, 0x4891, 0x4902, 0x8759, 0x1111, 0x1989);
+  asm volatile("vse16.v v0, (%0)" ::"r"(ALIGNED_I16));
+  VVCMP_U16(1, ALIGNED_I16, 0x05e0, 0xbbd3, 0x3840, 0x8cd1, 0x9384, 0x7548,
+            0x3489, 0x9388, 0x8188, 0x11ae, 0x5808, 0x4891, 0x4902, 0x8759,
+            0x1111, 0x1989);
+}
+
+//******Checking functionality of  with illegal destination register
+// specifier for EMUL********//
+// In this test case EMUL=2 and register is v1 which will cause illegal
+// instruction exception and set mcause = 2
+void TEST_CASE2(void) {
+  uint8_t mcause;
+  reset_vec16(ALIGNED_I16);
+  VSET(16, e16, m2);
+  VLOAD_16(v1, 0x05e0, 0xbbd3, 0x3840, 0x8cd1, 0x9384, 0x7548, 0x3489, 0x9388,
+           0x8188, 0x11ae, 0x5808, 0x4891, 0x4902, 0x8759, 0x1111, 0x1989);
+  VSET(16, e16, m2);
+  asm volatile("vse16.v v1, (%0)" ::"r"(ALIGNED_I16));
+  asm volatile("addi %[A], t3, 0" : [A] "=r"(mcause));
+  XCMP(2, mcause, 2);
+}
+
+//*******Checking functionality of vse16 with different values of masking
+// register******//
+void TEST_CASE3(void) {
+  reset_vec16(ALIGNED_I16);
+  VSET(16, e16, m1);
+  VLOAD_16(v3, 0x05e0, 0xbbd3, 0x3840, 0x8cd1, 0x9384, 0x7548, 0x3489, 0x9388,
+           0x8188, 0x11ae, 0x5808, 0x4891, 0x4902, 0x8759, 0x1111, 0x1989);
+  VLOAD_8(v0, 0xFF, 0xFF);
+  asm volatile("vse16.v v3, (%0), v0.t" ::"r"(ALIGNED_I16));
+  VCLEAR(v3);
+  VVCMP_U16(3, ALIGNED_I16, 0x05e0, 0xbbd3, 0x3840, 0x8cd1, 0x9384, 0x7548,
+            0x3489, 0x9388, 0x8188, 0x11ae, 0x5808, 0x4891, 0x4902, 0x8759,
+            0x1111, 0x1989);
+}
+
+void TEST_CASE4(void) {
+  VSET(16, e16, m1);
+  VLOAD_16(v3, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  asm volatile("vse16.v v3, (%0)" ::"r"(ALIGNED_I16));
+  VCLEAR(v3);
+  VLOAD_16(v3, 0x05e0, 0xbbd3, 0x3840, 0x8cd1, 0x9384, 0x7548, 0x3489, 0x9388,
+           0x8188, 0x11ae, 0x5808, 0x4891, 0x4902, 0x8759, 0x1111, 0x1989);
+  VLOAD_8(v0, 0x00, 0x00);
+  asm volatile("vse16.v v3, (%0), v0.t" ::"r"(ALIGNED_I16));
+  VCLEAR(v3);
+  VVCMP_U16(4, ALIGNED_I16, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+            16);
+}
+
+void TEST_CASE5(void) {
+  VSET(16, e16, m1);
+  VLOAD_16(v3, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  asm volatile("vse16.v v3, (%0)" ::"r"(ALIGNED_I16));
+  VCLEAR(v3);
+  VLOAD_16(v3, 0x05e0, 0xbbd3, 0x3840, 0x8cd1, 0x9384, 0x7548, 0x3489, 0x9388,
+           0x8188, 0x11ae, 0x5808, 0x4891, 0x4902, 0x8759, 0x1111, 0x1989);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vse16.v v3, (%0), v0.t" ::"r"(ALIGNED_I16));
+  VCLEAR(v3);
+  VVCMP_U16(5, ALIGNED_I16, 1, 0xbbd3, 3, 0x8cd1, 5, 0x7548, 7, 0x9388, 9,
+            0x11ae, 11, 0x4891, 13, 0x8759, 15, 0x1989);
+}
+
+//******Checking functionality with different combinations of vta and vma*****//
+// **** It uses undisturbed policy for tail agnostic and mask agnostic****//
+void TEST_CASE6(void) {
+  uint64_t avl;
+  VSET(16, e16, m1);
+  VLOAD_16(v4, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  asm volatile("vse16.v v4, (%0)" ::"r"(ALIGNED_I16));
+  VCLEAR(v4);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VLOAD_16(v4, 0x05e0, 0xbbd3, 0x3840, 0x8cd1, 0x9384, 0x7548, 0x3489, 0x9388,
+           0x8188, 0x11ae, 0x5808, 0x4891, 0x4902, 0x8759, 0x1111, 0x1989);
+  __asm__ volatile("vsetivli %[A], 12, e16, m1, ta, ma" : [A] "=r"(avl));
+  asm volatile("vse16.v v4, (%0),v0.t" ::"r"(ALIGNED_I16));
+  VCLEAR(v4);
+  VVCMP_U16(6, ALIGNED_I16, 1, 0xbbd3, 3, 0x8cd1, 5, 0x7548, 7, 0x9388, 9,
+            0x11ae, 11, 0x4891, 13, 14, 15, 16);
+}
+
+void TEST_CASE7(void) {
+  reset_vec16(ALIGNED_I16);
+  uint64_t avl;
+  VSET(16, e16, m1);
+  VLOAD_16(v4, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  asm volatile("vse16.v v4, (%0)" ::"r"(ALIGNED_I16));
+  VCLEAR(v4);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VLOAD_16(v4, 0x05e0, 0xbbd3, 0x3840, 0x8cd1, 0x9384, 0x7548, 0x3489, 0x9388,
+           0x8188, 0x11ae, 0x5808, 0x4891, 0x4902, 0x8759, 0x1111, 0x1989);
+  __asm__ volatile("vsetivli %[A], 12, e16, m1, ta, mu" : [A] "=r"(avl));
+  asm volatile("vse16.v v4, (%0), v0.t" ::"r"(ALIGNED_I16));
+  VCLEAR(v4);
+  VVCMP_U16(7, ALIGNED_I16, 1, 0xbbd3, 3, 0x8cd1, 5, 0x7548, 7, 0x9388, 9,
+            0x11ae, 11, 0x4891, 13, 14, 15, 16);
+}
+
+void TEST_CASE8(void) {
+  reset_vec16(ALIGNED_I16);
+  uint64_t avl;
+  VSET(16, e8, m1);
+  VLOAD_16(v4, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  asm volatile("vse16.v v4, (%0)" ::"r"(ALIGNED_I16));
+  VCLEAR(v4);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VLOAD_16(v4, 0x05e0, 0xbbd3, 0x3840, 0x8cd1, 0x9384, 0x7548, 0x3489, 0x9388,
+           0x8188, 0x11ae, 0x5808, 0x4891, 0x4902, 0x8759, 0x1111, 0x1989);
+  __asm__ volatile("vsetivli %[A], 12, e16, m1, tu, ma" : [A] "=r"(avl));
+  asm volatile("vse16.v v4, (%0), v0.t" ::"r"(ALIGNED_I16));
+  VCLEAR(v4);
+  VVCMP_U16(8, ALIGNED_I16, 1, 0xbbd3, 3, 0x8cd1, 5, 0x7548, 7, 0x9388, 9,
+            0x11ae, 11, 0x4891, 13, 14, 15, 16);
+}
+
+void TEST_CASE9(void) {
+  uint64_t avl;
+  VSET(16, e8, m1);
+  VLOAD_16(v4, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  asm volatile("vse16.v v4, (%0)" ::"r"(ALIGNED_I16));
+  VCLEAR(v4);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VLOAD_16(v4, 0x05e0, 0xbbd3, 0x3840, 0x8cd1, 0x9384, 0x7548, 0x3489, 0x9388,
+           0x8188, 0x11ae, 0x5808, 0x4891, 0x4902, 0x8759, 0x1111, 0x1989);
+  __asm__ volatile("vsetivli %[A], 12, e16, m1, tu, mu" : [A] "=r"(avl));
+  asm volatile("vse16.v v4, (%0), v0.t" ::"r"(ALIGNED_I16));
+  VCLEAR(v4);
+  VVCMP_U16(9, ALIGNED_I16, 1, 0xbbd3, 3, 0x8cd1, 5, 0x7548, 7, 0x9388, 9,
+            0x11ae, 11, 0x4891, 13, 14, 15, 16);
+}
+
+//*******Checking functionality if encoded EEW is not supported for given SEW
+// and LMUL values because EMUL become out of range*****//
+// This test case cover corner case for EEW = 16.If LMUL is changed to
+// mf8 it will give error because emul become less than 1/8 (EMUL = 1/16)
+// But it does not support this configuration because SEW/LMUL > ELEN
+void TEST_CASE10(void) {
+  VSET(16, e16, m1);
+  VLOAD_16(v5, 0x05e0, 0xbbd3, 0x3840, 0x8cd1, 0x9384, 0x7548, 0x3489, 0x9388,
+           0x8188, 0x11ae, 0x5808, 0x4891, 0x4902, 0x8759, 0x1111, 0x1989);
+  VSET(16, e32, mf2);
+  asm volatile("vse16.v v5, (%0)" ::"r"(ALIGNED_I16));
+  VCLEAR(v5);
+  VVCMP_U16(10, ALIGNED_I16, 0x05e0, 0xbbd3, 0x3840, 0x8cd1, 0x9384, 0x7548,
+            0x3489, 0x9388, 0x8188, 0x11ae, 0x5808, 0x4891, 0x4902, 0x8759,
+            0x1111, 0x1989);
+}
+
+// This test case execute upper bound case of EMUL (8)
+// If LMUL is changed to m8 it will give error because emul become greater than
+// 8 (EMUL = 16)
+void TEST_CASE11(void) {
+  reset_vec16(ALIGNED_I16);
+  VSET(16, e16, m1);
+  VLOAD_16(v8, 0x05e0, 0xbbd3, 0x3840, 0x8cd1, 0x9384, 0x7548, 0x3489, 0x9388,
+           0x8188, 0x11ae, 0x5808, 0x4891, 0x4902, 0x8759, 0x1111, 0x1989);
+  VSET(16, e8, m4);
+  asm volatile("vse16.v v8, (%0)" ::"r"(ALIGNED_I16));
+  VCLEAR(v8);
+  VVCMP_U16(11, ALIGNED_I16, 0x05e0, 0xbbd3, 0x3840, 0x8cd1, 0x9384, 0x7548,
+            0x3489, 0x9388, 0x8188, 0x11ae, 0x5808, 0x4891, 0x4902, 0x8759,
+            0x1111, 0x1989);
+}
+
+//******Checking functionality with different values of vl******//
+void TEST_CASE12(void) {
+  reset_vec16(ALIGNED_I16);
+  VSET(16, e16, m1);
+  VLOAD_16(v6, 0x05e0, 0xbbd3, 0x3840, 0x8cd1, 0x9384, 0x7548, 0x3489, 0x9388,
+           0x8188, 0x11ae, 0x5808, 0x4891, 0x4902, 0x8759, 0x1111, 0x1989);
+  asm volatile("vse16.v v6, (%0)" ::"r"(ALIGNED_I16));
+  VCLEAR(v6);
+  VVCMP_U16(12, ALIGNED_I16, 0x05e0, 0xbbd3, 0x3840, 0x8cd1, 0x9384, 0x7548,
+            0x3489, 0x9388, 0x8188, 0x11ae, 0x5808, 0x4891, 0x4902, 0x8759,
+            0x1111, 0x1989);
+}
+
+void TEST_CASE13(void) {
+  uint64_t avl;
+  VSET(16, e8, m1);
+  VLOAD_16(v6, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  asm volatile("vse16.v v6, (%0)" ::"r"(ALIGNED_I16));
+  VCLEAR(v6);
+  VLOAD_16(v6, 0xe0, 0xd3, 0x40, 0xd1, 0x84, 0x48, 0x89, 0x88, 0x88, 0xae, 0x08,
+           0x91, 0x02, 0x59, 0x11, 0x89);
+  __asm__ volatile("vsetivli %[A], 0, e8, m1, tu, ma" : [A] "=r"(avl));
+  asm volatile("vse16.v v6, (%0)" ::"r"(ALIGNED_I16));
+  VSET(16, e16, m1);
+  VVCMP_U16(13, ALIGNED_I16, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+            16);
+}
+
+void TEST_CASE14(void) {
+  VSET(16, e16, m1);
+  VLOAD_16(v6, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  asm volatile("vse16.v v6, (%0)" ::"r"(ALIGNED_I16));
+  VCLEAR(v6);
+  VLOAD_16(v6, 0x05e0, 0xbbd3, 0x3840, 0x8cd1, 0x9384, 0x7548, 0x3489, 0x9388,
+           0x8188, 0x11ae, 0x5808, 0x4891, 0x4902, 0x8759, 0x1111, 0x1989);
+  VSET(13, e8, m1);
+  asm volatile("vse16.v v6, (%0)" ::"r"(ALIGNED_I16));
+  VVCMP_U16(14, ALIGNED_I16, 0x05e0, 0xbbd3, 0x3840, 0x8cd1, 0x9384, 0x7548,
+            0x3489, 0x9388, 0x8188, 0x11ae, 0x5808, 0x4891, 0x4902, 14, 15, 16);
+}
+
+//******Checking functionality with different vstart value*****//
+void TEST_CASE15(void) {
+  VSET(16, e16, m1);
+  VLOAD_16(v7, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  asm volatile("vse16.v v7, (%0)" ::"r"(ALIGNED_I16));
+  VCLEAR(v7);
+  VLOAD_16(v7, 0x05e0, 0xbbd3, 0x3840, 0x8cd1, 0x9384, 0x7548, 0x3489, 0x9388,
+           0x8188, 0x11ae, 0x5808, 0x4891, 0x4902, 0x8759, 0x1111, 0x1989);
+  VSET(13, e16, m1);
+  write_csr(vstart, 2);
+  asm volatile("vse16.v v7, (%0)" ::"r"(ALIGNED_I16));
+  VVCMP_U16(15, ALIGNED_I16, 1, 2, 0x3840, 0x8cd1, 0x9384, 0x7548, 0x3489,
+            0x9388, 0x8188, 0x11ae, 0x5808, 0x4891, 0x4902, 14, 15, 16);
+}
+
+//****Checking functionality with different values of EMUL and
+// large number of elements *******//
+void TEST_CASE16(void) {
+  reset_vec16(ALIGNED_I16);
+  VSET(1024, e16, m4);
+  asm volatile("vle16.v v8, (%0)" ::"r"(&LONG_I16[0]));
+  asm volatile("vse16.v v8, (%0)" ::"r"(ALIGNED_I16));
+  LVVCMP_U16(16, ALIGNED_I16, LONG_I16);
+}
+
+void TEST_CASE17(void) {
+  reset_vec16(ALIGNED_I16);
+  VSET(512, e16, m2);
+  asm volatile("vle16.v v10, (%0)" ::"r"(&LONG_I16[0]));
+  asm volatile("vse16.v v10, (%0)" ::"r"(ALIGNED_I16));
+  LVVCMP_U16(17, ALIGNED_I16, LONG_I16);
+}
+
+void TEST_CASE18(void) {
+  reset_vec16(ALIGNED_I16);
+  VSET(300, e16, m2);
+  asm volatile("vle16.v v10, (%0)" ::"r"(&LONG_I16[0]));
+  asm volatile("vse16.v v10, (%0)" ::"r"(ALIGNED_I16));
+  LVVCMP_U16(18, ALIGNED_I16, LONG_I16);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  printf("*****Running tests for vse16.v*****\n");
+  TEST_CASE1();
+  // TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+  TEST_CASE6();
+  TEST_CASE7();
+  TEST_CASE8();
+  TEST_CASE9();
+  TEST_CASE10();
+  TEST_CASE11();
+  TEST_CASE12();
+  // TEST_CASE13();
+  TEST_CASE14();
+  // TEST_CASE15();
+  TEST_CASE16();
+  TEST_CASE17();
+  TEST_CASE18();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vse32.c b/apps/riscv-tests/isa/rv64uv/vse32.c
new file mode 100644
index 0000000..ac7c0ad
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vse32.c
@@ -0,0 +1,412 @@
+// TODO uncomment TEST_CASE13 and TEST_CASE 15 after issue of vl=0 and
+// non-zero vstart is resolved
+// TODO uncomment TEST_CASE2 after issue of exception is resolved
+#include "long_array.h"
+#include "vector_macros.h"
+#define AXI_DWIDTH 128
+void mtvec_handler(void) {
+  asm volatile("csrr t0, mcause"); // Read mcause
+
+  // Read mepc
+  asm volatile("csrr t1, mepc");
+
+  // Increment return address by 4
+  asm volatile("addi t1, t1, 4");
+  asm volatile("csrw mepc, t1");
+
+  // Filter with mcause and handle here
+
+  asm volatile("mret");
+}
+
+// Exception Handler for spike
+void handle_trap(void) {
+  // Read mepc
+  asm volatile("csrr t1, mepc");
+
+  // Increment return address by 4
+  asm volatile("addi t1, t1, 4");
+  asm volatile("csrw mepc, t1");
+
+  asm volatile("ld ra, 8(sp)");
+  asm volatile("ld sp, 16(sp)");
+  asm volatile("ld gp, 24(sp)");
+  asm volatile("ld tp, 32(sp)");
+  asm volatile("ld t0, 40(sp)");
+  asm volatile("ld t0, 40(sp)");
+  asm volatile("ld t1, 48(sp)");
+  asm volatile("ld t2, 56(sp)");
+  asm volatile("ld s0, 64(sp)");
+  asm volatile("ld s1, 72(sp)");
+  asm volatile("ld a0, 80(sp)");
+  asm volatile("ld a1, 88(sp)");
+  asm volatile("ld a2, 96(sp)");
+  asm volatile("ld a3, 104(sp)");
+  asm volatile("ld a4, 112(sp)");
+  asm volatile("ld a5, 120(sp)");
+  asm volatile("ld a6, 128(sp)");
+  asm volatile("ld a7, 136(sp)");
+  asm volatile("ld s2, 144(sp)");
+  asm volatile("ld s3, 152(sp)");
+  asm volatile("ld s4, 160(sp)");
+  asm volatile("ld s5, 168(sp)");
+  asm volatile("ld s6, 176(sp)");
+  asm volatile("ld s7, 184(sp)");
+  asm volatile("ld s8, 192(sp)");
+  asm volatile("ld s9, 200(sp)");
+  asm volatile("ld s10, 208(sp)");
+  asm volatile("ld s11, 216(sp)");
+  asm volatile("ld t3, 224(sp)");
+  asm volatile("ld t4, 232(sp)");
+  asm volatile("ld t5, 240(sp)");
+  asm volatile("ld t6, 248(sp)");
+
+  // Read mcause
+  asm volatile("csrr t3, mcause");
+
+  asm volatile("addi sp, sp, 272");
+
+  // Filter with mcause and handle here
+
+  asm volatile("mret");
+}
+
+void reset_vec32(volatile uint32_t *vec) {
+  for (uint64_t i = 0; i < 1024; ++i)
+    vec[i] = 0;
+}
+
+static volatile uint32_t ALIGNED_I32[1024] __attribute__((aligned(AXI_DWIDTH)));
+
+//**********Checking functionality of vse32********//
+void TEST_CASE1(void) {
+  VSET(16, e32, m1);
+  VLOAD_32(v0, 0x9fe41920, 0xf9aa71f0, 0xa11a9384, 0x99991348, 0x9fa831c7,
+           0x38197598, 0x18931795, 0x81937598, 0x18747547, 0x3eeeeeee,
+           0x90139301, 0xab8b9148, 0x90318509, 0x31897598, 0x83195999,
+           0x89139848);
+  asm volatile("vse32.v v0, (%0)" ::"r"(ALIGNED_I32));
+  VVCMP_U32(1, ALIGNED_I32, 0x9fe41920, 0xf9aa71f0, 0xa11a9384, 0x99991348,
+            0x9fa831c7, 0x38197598, 0x18931795, 0x81937598, 0x18747547,
+            0x3eeeeeee, 0x90139301, 0xab8b9148, 0x90318509, 0x31897598,
+            0x83195999, 0x89139848);
+}
+
+//******Checking functionality of  with illegal destination register
+// specifier for EMUL********//
+// In this test case EMUL=2 and register is v1 which will cause illegal
+// instruction exception and set mcause = 2
+void TEST_CASE2(void) {
+  uint8_t mcause;
+  reset_vec32(ALIGNED_I32);
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 0x9fe41920, 0xf9aa71f0, 0xa11a9384, 0x99991348, 0x9fa831c7,
+           0x38197598, 0x18931795, 0x81937598, 0x18747547, 0x3eeeeeee,
+           0x90139301, 0xab8b9148, 0x90318509, 0x31897598, 0x83195999,
+           0x89139848);
+  VSET(16, e64, m4);
+  asm volatile("vse32.v v1, (%0)" ::"r"(ALIGNED_I32));
+  asm volatile("addi %[A], t3, 0" : [A] "=r"(mcause));
+  XCMP(2, mcause, 2);
+}
+
+//*******Checking functionality of vse16 with different values of masking
+// register******//
+void TEST_CASE3(void) {
+  reset_vec32(ALIGNED_I32);
+  VSET(16, e32, m1);
+  VLOAD_32(v3, 0x9fe41920, 0xf9aa71f0, 0xa11a9384, 0x99991348, 0x9fa831c7,
+           0x38197598, 0x18931795, 0x81937598, 0x18747547, 0x3eeeeeee,
+           0x90139301, 0xab8b9148, 0x90318509, 0x31897598, 0x83195999,
+           0x89139848);
+  VLOAD_8(v0, 0xFF, 0xFF);
+  asm volatile("vse32.v v3, (%0), v0.t" ::"r"(ALIGNED_I32));
+  VCLEAR(v3);
+  VVCMP_U32(3, ALIGNED_I32, 0x9fe41920, 0xf9aa71f0, 0xa11a9384, 0x99991348,
+            0x9fa831c7, 0x38197598, 0x18931795, 0x81937598, 0x18747547,
+            0x3eeeeeee, 0x90139301, 0xab8b9148, 0x90318509, 0x31897598,
+            0x83195999, 0x89139848);
+}
+
+void TEST_CASE4(void) {
+  VSET(16, e32, m1);
+  VLOAD_32(v3, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  asm volatile("vse32.v v3, (%0)" ::"r"(ALIGNED_I32));
+  VCLEAR(v3);
+  VLOAD_32(v3, 0x9fe41920, 0xf9aa71f0, 0xa11a9384, 0x99991348, 0x9fa831c7,
+           0x38197598, 0x18931795, 0x81937598, 0x18747547, 0x3eeeeeee,
+           0x90139301, 0xab8b9148, 0x90318509, 0x31897598, 0x83195999,
+           0x89139848);
+  VLOAD_8(v0, 0x00, 0x00);
+  asm volatile("vse32.v v3, (%0), v0.t" ::"r"(ALIGNED_I32));
+  VCLEAR(v3);
+  VVCMP_U32(4, ALIGNED_I32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+            16);
+}
+
+void TEST_CASE5(void) {
+  VSET(16, e32, m1);
+  VLOAD_32(v3, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  asm volatile("vse32.v v3, (%0)" ::"r"(ALIGNED_I32));
+  VCLEAR(v3);
+  VLOAD_32(v3, 0x9fe41920, 0xf9aa71f0, 0xa11a9384, 0x99991348, 0x9fa831c7,
+           0x38197598, 0x18931795, 0x81937598, 0x18747547, 0x3eeeeeee,
+           0x90139301, 0xab8b9148, 0x90318509, 0x31897598, 0x83195999,
+           0x89139848);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vse32.v v3, (%0), v0.t" ::"r"(ALIGNED_I32));
+  VCLEAR(v3);
+  VVCMP_U32(5, ALIGNED_I32, 1, 0xf9aa71f0, 3, 0x99991348, 5, 0x38197598, 7,
+            0x81937598, 9, 0x3eeeeeee, 11, 0xab8b9148, 13, 0x31897598, 15,
+            0x89139848);
+}
+
+//******Checking functionality with different combinations of vta and vma*****//
+// **** It uses undisturbed policy for tail agnostic and mask agnostic****//
+void TEST_CASE6(void) {
+  reset_vec32(ALIGNED_I32);
+  uint64_t avl;
+  VSET(16, e32, m1);
+  VLOAD_32(v4, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  asm volatile("vse32.v v4, (%0)" ::"r"(ALIGNED_I32));
+  VCLEAR(v4);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VLOAD_32(v4, 0x9fe41920, 0xf9aa71f0, 0xa11a9384, 0x99991348, 0x9fa831c7,
+           0x38197598, 0x18931795, 0x81937598, 0x18747547, 0x3eeeeeee,
+           0x90139301, 0xab8b9148, 0x90318509, 0x31897598, 0x83195999,
+           0x89139848);
+  __asm__ volatile("vsetivli %[A], 12, e32, m1, ta, ma" : [A] "=r"(avl));
+  asm volatile("vse32.v v4, (%0),v0.t" ::"r"(ALIGNED_I32));
+  VCLEAR(v4);
+  VVCMP_U32(6, ALIGNED_I32, 1, 0xf9aa71f0, 3, 0x99991348, 5, 0x38197598, 7,
+            0x81937598, 9, 0x3eeeeeee, 11, 0xab8b9148, 13, 14, 15, 16);
+}
+
+void TEST_CASE7(void) {
+  reset_vec32(ALIGNED_I32);
+  uint64_t avl;
+  VSET(16, e32, m1);
+  VLOAD_32(v4, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  asm volatile("vse32.v v4, (%0)" ::"r"(ALIGNED_I32));
+  VCLEAR(v4);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VLOAD_32(v4, 0x9fe41920, 0xf9aa71f0, 0xa11a9384, 0x99991348, 0x9fa831c7,
+           0x38197598, 0x18931795, 0x81937598, 0x18747547, 0x3eeeeeee,
+           0x90139301, 0xab8b9148, 0x90318509, 0x31897598, 0x83195999,
+           0x89139848);
+  __asm__ volatile("vsetivli %[A], 12, e32, m1, ta, mu" : [A] "=r"(avl));
+  asm volatile("vse32.v v4, (%0), v0.t" ::"r"(ALIGNED_I32));
+  VCLEAR(v4);
+  VVCMP_U32(7, ALIGNED_I32, 1, 0xf9aa71f0, 3, 0x99991348, 5, 0x38197598, 7,
+            0x81937598, 9, 0x3eeeeeee, 11, 0xab8b9148, 13, 14, 15, 16);
+}
+
+void TEST_CASE8(void) {
+  reset_vec32(ALIGNED_I32);
+  uint64_t avl;
+  VSET(16, e32, m1);
+  VLOAD_32(v4, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  asm volatile("vse32.v v4, (%0)" ::"r"(ALIGNED_I32));
+  VCLEAR(v4);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VLOAD_32(v4, 0x9fe41920, 0xf9aa71f0, 0xa11a9384, 0x99991348, 0x9fa831c7,
+           0x38197598, 0x18931795, 0x81937598, 0x18747547, 0x3eeeeeee,
+           0x90139301, 0xab8b9148, 0x90318509, 0x31897598, 0x83195999,
+           0x89139848);
+  __asm__ volatile("vsetivli %[A], 12, e32, m1, tu, ma" : [A] "=r"(avl));
+  asm volatile("vse32.v v4, (%0), v0.t" ::"r"(ALIGNED_I32));
+  VCLEAR(v4);
+  VVCMP_U32(8, ALIGNED_I32, 1, 0xf9aa71f0, 3, 0x99991348, 5, 0x38197598, 7,
+            0x81937598, 9, 0x3eeeeeee, 11, 0xab8b9148, 13, 14, 15, 16);
+}
+
+void TEST_CASE9(void) {
+  reset_vec32(ALIGNED_I32);
+  uint64_t avl;
+  VSET(16, e32, m1);
+  VLOAD_32(v4, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  asm volatile("vse32.v v4, (%0)" ::"r"(ALIGNED_I32));
+  VCLEAR(v4);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VLOAD_32(v4, 0x9fe41920, 0xf9aa71f0, 0xa11a9384, 0x99991348, 0x9fa831c7,
+           0x38197598, 0x18931795, 0x81937598, 0x18747547, 0x3eeeeeee,
+           0x90139301, 0xab8b9148, 0x90318509, 0x31897598, 0x83195999,
+           0x89139848);
+  __asm__ volatile("vsetivli %[A], 12, e16, m1, tu, mu" : [A] "=r"(avl));
+  asm volatile("vse32.v v4, (%0), v0.t" ::"r"(ALIGNED_I32));
+  VCLEAR(v4);
+  VVCMP_U32(9, ALIGNED_I32, 1, 0xf9aa71f0, 3, 0x99991348, 5, 0x38197598, 7,
+            0x81937598, 9, 0x3eeeeeee, 11, 0xab8b9148, 13, 14, 15, 16);
+}
+
+//*******Checking functionality if encoded EEW is not supported for given SEW
+// and LMUL values because EMUL become out of range*****//
+// This test case cover corner case for EEW = 32.If LMUL is changed to
+// mf8 and SEW is changed to e64 it will give error because emul become less
+// than 1/8 (EMUL = 1/16) But it does not support this configuration because
+// SEW/LMUL > ELEN
+void TEST_CASE10(void) {
+  reset_vec32(ALIGNED_I32);
+  VSET(16, e32, m1);
+  VLOAD_32(v5, 0x9fe41920, 0xf9aa71f0, 0xa11a9384, 0x99991348, 0x9fa831c7,
+           0x38197598, 0x18931795, 0x81937598, 0x18747547, 0x3eeeeeee,
+           0x90139301, 0xab8b9148, 0x90318509, 0x31897598, 0x83195999,
+           0x89139848);
+  VSET(16, e32, mf2);
+  asm volatile("vse32.v v5, (%0)" ::"r"(ALIGNED_I32));
+  VCLEAR(v5);
+  VVCMP_U32(10, ALIGNED_I32, 0x9fe41920, 0xf9aa71f0, 0xa11a9384, 0x99991348,
+            0x9fa831c7, 0x38197598, 0x18931795, 0x81937598, 0x18747547,
+            0x3eeeeeee, 0x90139301, 0xab8b9148, 0x90318509, 0x31897598,
+            0x83195999, 0x89139848);
+}
+
+// This test case execute upper bound case of EMUL (8)
+// If LMUL is changed to m8 it will give error because emul become greater than
+// 8 (EMUL = 16)
+void TEST_CASE11(void) {
+  reset_vec32(ALIGNED_I32);
+  VSET(16, e32, m1);
+  VLOAD_32(v8, 0x9fe41920, 0xf9aa71f0, 0xa11a9384, 0x99991348, 0x9fa831c7,
+           0x38197598, 0x18931795, 0x81937598, 0x18747547, 0x3eeeeeee,
+           0x90139301, 0xab8b9148, 0x90318509, 0x31897598, 0x83195999,
+           0x89139848);
+  VSET(16, e8, m2);
+  asm volatile("vse32.v v8, (%0)" ::"r"(ALIGNED_I32));
+  VCLEAR(v8);
+  VVCMP_U32(11, ALIGNED_I32, 0x9fe41920, 0xf9aa71f0, 0xa11a9384, 0x99991348,
+            0x9fa831c7, 0x38197598, 0x18931795, 0x81937598, 0x18747547,
+            0x3eeeeeee, 0x90139301, 0xab8b9148, 0x90318509, 0x31897598,
+            0x83195999, 0x89139848);
+}
+
+//******Checking functionality with different values of vl******//
+void TEST_CASE12(void) {
+  reset_vec32(ALIGNED_I32);
+  VSET(16, e32, m1);
+  VLOAD_32(v6, 0x9fe41920, 0xf9aa71f0, 0xa11a9384, 0x99991348, 0x9fa831c7,
+           0x38197598, 0x18931795, 0x81937598, 0x18747547, 0x3eeeeeee,
+           0x90139301, 0xab8b9148, 0x90318509, 0x31897598, 0x83195999,
+           0x89139848);
+  asm volatile("vse32.v v6, (%0)" ::"r"(ALIGNED_I32));
+  VCLEAR(v6);
+  VVCMP_U32(12, ALIGNED_I32, 0x9fe41920, 0xf9aa71f0, 0xa11a9384, 0x99991348,
+            0x9fa831c7, 0x38197598, 0x18931795, 0x81937598, 0x18747547,
+            0x3eeeeeee, 0x90139301, 0xab8b9148, 0x90318509, 0x31897598,
+            0x83195999, 0x89139848);
+}
+
+void TEST_CASE13(void) {
+  uint64_t avl;
+  VSET(16, e32, m1);
+  VLOAD_32(v6, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  asm volatile("vse32.v v6, (%0)" ::"r"(ALIGNED_I32));
+  VCLEAR(v6);
+  VLOAD_32(v6, 0x9fe41920, 0xf9aa71f0, 0xa11a9384, 0x99991348, 0x9fa831c7,
+           0x38197598, 0x18931795, 0x81937598, 0x18747547, 0x3eeeeeee,
+           0x90139301, 0xab8b9148, 0x90318509, 0x31897598, 0x83195999,
+           0x89139848);
+  __asm__ volatile("vsetivli %[A], 0, e32, m1, tu, ma" : [A] "=r"(avl));
+  asm volatile("vse32.v v6, (%0)" ::"r"(ALIGNED_I32));
+  VSET(16, e32, m1);
+  VVCMP_U32(13, ALIGNED_I32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+            16);
+}
+
+void TEST_CASE14(void) {
+  VSET(16, e32, m1);
+  VLOAD_32(v6, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  asm volatile("vse32.v v6, (%0)" ::"r"(ALIGNED_I32));
+  VCLEAR(v6);
+  VLOAD_32(v6, 0x9fe41920, 0xf9aa71f0, 0xa11a9384, 0x99991348, 0x9fa831c7,
+           0x38197598, 0x18931795, 0x81937598, 0x18747547, 0x3eeeeeee,
+           0x90139301, 0xab8b9148, 0x90318509, 0x31897598, 0x83195999,
+           0x89139848);
+  VSET(13, e32, m1);
+  asm volatile("vse32.v v6, (%0)" ::"r"(ALIGNED_I32));
+  VSET(16, e32, m1);
+  VVCMP_U32(14, ALIGNED_I32, 0x9fe41920, 0xf9aa71f0, 0xa11a9384, 0x99991348,
+            0x9fa831c7, 0x38197598, 0x18931795, 0x81937598, 0x18747547,
+            0x3eeeeeee, 0x90139301, 0xab8b9148, 0x90318509, 14, 15, 16);
+}
+
+//******Checking functionality with different vstart value*****//
+void TEST_CASE15(void) {
+  reset_vec32(ALIGNED_I32);
+  VSET(16, e32, m1);
+  VLOAD_32(v7, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  asm volatile("vse32.v v7, (%0)" ::"r"(ALIGNED_I32));
+  VCLEAR(v7);
+  VLOAD_32(v7, 0x9fe41920, 0xf9aa71f0, 0xa11a9384, 0x99991348, 0x9fa831c7,
+           0x38197598, 0x18931795, 0x81937598, 0x18747547, 0x3eeeeeee,
+           0x90139301, 0xab8b9148, 0x90318509, 0x31897598, 0x83195999,
+           0x89139848);
+  VSET(13, e32, m1);
+  write_csr(vstart, 2);
+  asm volatile("vse32.v v7, (%0)" ::"r"(ALIGNED_I32));
+  VVCMP_U32(15, ALIGNED_I32, 1, 2, 0xa11a9384, 0x99991348, 0x9fa831c7,
+            0x38197598, 0x18931795, 0x81937598, 0x18747547, 0x3eeeeeee,
+            0x90139301, 0xab8b9148, 0x90318509, 14, 15, 16);
+}
+
+//****Checking functionality with different values of EMUL and
+// large number of elements *******//
+void TEST_CASE16(void) {
+  reset_vec32(ALIGNED_I32);
+  VSET(1024, e32, m8);
+  asm volatile("vle32.v v8, (%0)" ::"r"(&LONG_I32[0]));
+  asm volatile("vse32.v v8, (%0)" ::"r"(ALIGNED_I32));
+  LVVCMP_U32(16, ALIGNED_I32, LONG_I32);
+}
+
+void TEST_CASE17(void) {
+  reset_vec32(ALIGNED_I32);
+  VSET(512, e32, m4);
+  asm volatile("vle32.v v12, (%0)" ::"r"(&LONG_I32[0]));
+  asm volatile("vse32.v v12, (%0)" ::"r"(ALIGNED_I32));
+  LVVCMP_U32(17, ALIGNED_I32, LONG_I32);
+}
+
+void TEST_CASE18(void) {
+  reset_vec32(ALIGNED_I32);
+  VSET(256, e32, m2);
+  asm volatile("vle32.v v10, (%0)" ::"r"(&LONG_I32[0]));
+  asm volatile("vse32.v v10, (%0)" ::"r"(ALIGNED_I32));
+  LVVCMP_U32(18, ALIGNED_I32, LONG_I32);
+}
+
+void TEST_CASE19(void) {
+  reset_vec32(ALIGNED_I32);
+  VSET(200, e32, m2);
+  asm volatile("vle32.v v8, (%0)" ::"r"(&LONG_I32[0]));
+  asm volatile("vse32.v v8, (%0)" ::"r"(ALIGNED_I32));
+  LVVCMP_U32(19, ALIGNED_I32, LONG_I32);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  printf("*****Running tests for vse32.v*****\n");
+  TEST_CASE1();
+  // TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+  TEST_CASE6();
+  TEST_CASE7();
+  TEST_CASE8();
+  TEST_CASE9();
+  TEST_CASE10();
+  TEST_CASE11();
+  TEST_CASE12();
+  // TEST_CASE13();
+  TEST_CASE14();
+  // TEST_CASE15();
+  TEST_CASE16();
+  TEST_CASE17();
+  TEST_CASE18();
+  TEST_CASE19();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vse64.c b/apps/riscv-tests/isa/rv64uv/vse64.c
new file mode 100644
index 0000000..f4a5b09
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vse64.c
@@ -0,0 +1,436 @@
+// TODO uncomment TEST_CASE12 and TEST_CASE 14 after issue of vl=0 and
+// non-zero vstart is resolved
+// TODO uncomment TEST_CASE2 after issue of exception is resolved
+#include "long_array.h"
+#include "vector_macros.h"
+
+#define AXI_DWIDTH 128
+void mtvec_handler(void) {
+  asm volatile("csrr t0, mcause"); // Read mcause
+
+  // Read mepc
+  asm volatile("csrr t1, mepc");
+
+  // Increment return address by 4
+  asm volatile("addi t1, t1, 4");
+  asm volatile("csrw mepc, t1");
+
+  // Filter with mcause and handle here
+
+  asm volatile("mret");
+}
+
+// Exception Handler for spike
+void handle_trap(void) {
+  // Read mepc
+  asm volatile("csrr t1, mepc");
+
+  // Increment return address by 4
+  asm volatile("addi t1, t1, 4");
+  asm volatile("csrw mepc, t1");
+
+  asm volatile("ld ra, 8(sp)");
+  asm volatile("ld sp, 16(sp)");
+  asm volatile("ld gp, 24(sp)");
+  asm volatile("ld tp, 32(sp)");
+  asm volatile("ld t0, 40(sp)");
+  asm volatile("ld t0, 40(sp)");
+  asm volatile("ld t1, 48(sp)");
+  asm volatile("ld t2, 56(sp)");
+  asm volatile("ld s0, 64(sp)");
+  asm volatile("ld s1, 72(sp)");
+  asm volatile("ld a0, 80(sp)");
+  asm volatile("ld a1, 88(sp)");
+  asm volatile("ld a2, 96(sp)");
+  asm volatile("ld a3, 104(sp)");
+  asm volatile("ld a4, 112(sp)");
+  asm volatile("ld a5, 120(sp)");
+  asm volatile("ld a6, 128(sp)");
+  asm volatile("ld a7, 136(sp)");
+  asm volatile("ld s2, 144(sp)");
+  asm volatile("ld s3, 152(sp)");
+  asm volatile("ld s4, 160(sp)");
+  asm volatile("ld s5, 168(sp)");
+  asm volatile("ld s6, 176(sp)");
+  asm volatile("ld s7, 184(sp)");
+  asm volatile("ld s8, 192(sp)");
+  asm volatile("ld s9, 200(sp)");
+  asm volatile("ld s10, 208(sp)");
+  asm volatile("ld s11, 216(sp)");
+  asm volatile("ld t3, 224(sp)");
+  asm volatile("ld t4, 232(sp)");
+  asm volatile("ld t5, 240(sp)");
+  asm volatile("ld t6, 248(sp)");
+
+  // Read mcause
+  asm volatile("csrr t3, mcause");
+
+  asm volatile("addi sp, sp, 272");
+
+  // Filter with mcause and handle here
+
+  asm volatile("mret");
+}
+
+void reset_vec64(volatile uint64_t *vec) {
+  for (uint64_t i = 0; i < 1024; ++i)
+    vec[i] = 0;
+}
+
+static volatile uint64_t ALIGNED_I64[1024] __attribute__((aligned(AXI_DWIDTH)));
+
+//**********Checking functionality of vse64 with different destination
+// registers********//
+void TEST_CASE1(void) {
+  VSET(16, e64, m1);
+  VLOAD_64(v0, 0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3, 0xa11a9384a7163840,
+           0x99991348a9f38cd1, 0x9fa831c7a11a9384, 0x3819759853987548,
+           0x1893179501093489, 0x81937598aa819388, 0x1874754791888188,
+           0x3eeeeeeee33111ae, 0x9013930148815808, 0xab8b914891484891,
+           0x9031850931584902, 0x3189759837598759, 0x8319599991911111,
+           0x8913984898951989);
+  asm volatile("vse64.v v0, (%0)" ::"r"(ALIGNED_I64));
+  VVCMP_U64(1, ALIGNED_I64, 0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3,
+            0xa11a9384a7163840, 0x99991348a9f38cd1, 0x9fa831c7a11a9384,
+            0x3819759853987548, 0x1893179501093489, 0x81937598aa819388,
+            0x1874754791888188, 0x3eeeeeeee33111ae, 0x9013930148815808,
+            0xab8b914891484891, 0x9031850931584902, 0x3189759837598759,
+            0x8319599991911111, 0x8913984898951989);
+}
+
+//******Checking functionality of  with illegal destination register
+// specifier for EMUL********//
+// In this test case EMUL=2 and register is v1 which will cause illegal
+// instruction exception and set mcause = 2
+void TEST_CASE2(void) {
+  uint8_t mcause;
+  reset_vec64(ALIGNED_I64);
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3, 0xa11a9384a7163840,
+           0x99991348a9f38cd1, 0x9fa831c7a11a9384, 0x3819759853987548,
+           0x1893179501093489, 0x81937598aa819388, 0x1874754791888188,
+           0x3eeeeeeee33111ae, 0x9013930148815808, 0xab8b914891484891,
+           0x9031850931584902, 0x3189759837598759, 0x8319599991911111,
+           0x8913984898951989);
+  VSET(16, e64, m2);
+  asm volatile("vse64.v v1, (%0)" ::"r"(ALIGNED_I64));
+  asm volatile("addi %[A], t3, 0" : [A] "=r"(mcause));
+  XCMP(2, mcause, 2);
+}
+
+//*******Checking functionality of vse16 with different values of masking
+// register******//
+void TEST_CASE3(void) {
+  reset_vec64(ALIGNED_I64);
+  VSET(16, e64, m1);
+  VLOAD_64(v3, 0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3, 0xa11a9384a7163840,
+           0x99991348a9f38cd1, 0x9fa831c7a11a9384, 0x3819759853987548,
+           0x1893179501093489, 0x81937598aa819388, 0x1874754791888188,
+           0x3eeeeeeee33111ae, 0x9013930148815808, 0xab8b914891484891,
+           0x9031850931584902, 0x3189759837598759, 0x8319599991911111,
+           0x8913984898951989);
+  VLOAD_8(v0, 0xFF, 0xFF);
+  asm volatile("vse64.v v3, (%0), v0.t" ::"r"(ALIGNED_I64));
+  VCLEAR(v3);
+  VVCMP_U64(3, ALIGNED_I64, 0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3,
+            0xa11a9384a7163840, 0x99991348a9f38cd1, 0x9fa831c7a11a9384,
+            0x3819759853987548, 0x1893179501093489, 0x81937598aa819388,
+            0x1874754791888188, 0x3eeeeeeee33111ae, 0x9013930148815808,
+            0xab8b914891484891, 0x9031850931584902, 0x3189759837598759,
+            0x8319599991911111, 0x8913984898951989);
+}
+
+void TEST_CASE4(void) {
+  VSET(16, e64, m1);
+  VLOAD_64(v3, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  asm volatile("vse64.v v3, (%0)" ::"r"(ALIGNED_I64));
+  VCLEAR(v3);
+  VLOAD_64(v3, 0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3, 0xa11a9384a7163840,
+           0x99991348a9f38cd1, 0x9fa831c7a11a9384, 0x3819759853987548,
+           0x1893179501093489, 0x81937598aa819388, 0x1874754791888188,
+           0x3eeeeeeee33111ae, 0x9013930148815808, 0xab8b914891484891,
+           0x9031850931584902, 0x3189759837598759, 0x8319599991911111,
+           0x8913984898951989);
+  VLOAD_8(v0, 0x00, 0x00);
+  asm volatile("vse64.v v3, (%0), v0.t" ::"r"(ALIGNED_I64));
+  VCLEAR(v3);
+  VVCMP_U64(4, ALIGNED_I64, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+            16);
+}
+
+void TEST_CASE5(void) {
+  VSET(16, e64, m1);
+  VLOAD_64(v3, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  asm volatile("vse64.v v3, (%0)" ::"r"(ALIGNED_I64));
+  VCLEAR(v3);
+  VLOAD_64(v3, 0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3, 0xa11a9384a7163840,
+           0x99991348a9f38cd1, 0x9fa831c7a11a9384, 0x3819759853987548,
+           0x1893179501093489, 0x81937598aa819388, 0x1874754791888188,
+           0x3eeeeeeee33111ae, 0x9013930148815808, 0xab8b914891484891,
+           0x9031850931584902, 0x3189759837598759, 0x8319599991911111,
+           0x8913984898951989);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vse64.v v3, (%0), v0.t" ::"r"(ALIGNED_I64));
+  VCLEAR(v3);
+  VVCMP_U64(5, ALIGNED_I64, 1, 0xf9aa71f0c394bbd3, 3, 0x99991348a9f38cd1, 5,
+            0x3819759853987548, 7, 0x81937598aa819388, 9, 0x3eeeeeeee33111ae,
+            11, 0xab8b914891484891, 13, 0x3189759837598759, 15,
+            0x8913984898951989);
+}
+
+//******Checking functionality with different combinations of vta and vma*****//
+// **** It uses undisturbed policy for tail agnostic and mask agnostic****//
+void TEST_CASE6(void) {
+  reset_vec64(ALIGNED_I64);
+  uint64_t avl;
+  VSET(16, e64, m1);
+  VLOAD_64(v4, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  asm volatile("vse64.v v4, (%0)" ::"r"(ALIGNED_I64));
+  VCLEAR(v4);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VLOAD_64(v4, 0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3, 0xa11a9384a7163840,
+           0x99991348a9f38cd1, 0x9fa831c7a11a9384, 0x3819759853987548,
+           0x1893179501093489, 0x81937598aa819388, 0x1874754791888188,
+           0x3eeeeeeee33111ae, 0x9013930148815808, 0xab8b914891484891,
+           0x9031850931584902, 0x3189759837598759, 0x8319599991911111,
+           0x8913984898951989);
+  __asm__ volatile("vsetivli %[A], 12, e64, m1, ta, ma" : [A] "=r"(avl));
+  asm volatile("vse64.v v4, (%0),v0.t" ::"r"(ALIGNED_I64));
+  VCLEAR(v4);
+  VVCMP_U64(6, ALIGNED_I64, 1, 0xf9aa71f0c394bbd3, 3, 0x99991348a9f38cd1, 5,
+            0x3819759853987548, 7, 0x81937598aa819388, 9, 0x3eeeeeeee33111ae,
+            11, 0xab8b914891484891, 13, 14, 15, 16);
+}
+
+void TEST_CASE7(void) {
+  reset_vec64(ALIGNED_I64);
+  uint64_t avl;
+  VSET(16, e64, m1);
+  VLOAD_64(v4, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  asm volatile("vse64.v v4, (%0)" ::"r"(ALIGNED_I64));
+  VCLEAR(v4);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VLOAD_64(v4, 0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3, 0xa11a9384a7163840,
+           0x99991348a9f38cd1, 0x9fa831c7a11a9384, 0x3819759853987548,
+           0x1893179501093489, 0x81937598aa819388, 0x1874754791888188,
+           0x3eeeeeeee33111ae, 0x9013930148815808, 0xab8b914891484891,
+           0x9031850931584902, 0x3189759837598759, 0x8319599991911111,
+           0x8913984898951989);
+  __asm__ volatile("vsetivli %[A], 12, e64, m1, ta, mu" : [A] "=r"(avl));
+  asm volatile("vse64.v v4, (%0), v0.t" ::"r"(ALIGNED_I64));
+  VCLEAR(v4);
+  VVCMP_U64(7, ALIGNED_I64, 1, 0xf9aa71f0c394bbd3, 3, 0x99991348a9f38cd1, 5,
+            0x3819759853987548, 7, 0x81937598aa819388, 9, 0x3eeeeeeee33111ae,
+            11, 0xab8b914891484891, 13, 14, 15, 16);
+}
+
+void TEST_CASE8(void) {
+  reset_vec64(ALIGNED_I64);
+  uint64_t avl;
+  VSET(16, e64, m1);
+  VLOAD_64(v4, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  asm volatile("vse64.v v4, (%0)" ::"r"(ALIGNED_I64));
+  VCLEAR(v4);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VLOAD_64(v4, 0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3, 0xa11a9384a7163840,
+           0x99991348a9f38cd1, 0x9fa831c7a11a9384, 0x3819759853987548,
+           0x1893179501093489, 0x81937598aa819388, 0x1874754791888188,
+           0x3eeeeeeee33111ae, 0x9013930148815808, 0xab8b914891484891,
+           0x9031850931584902, 0x3189759837598759, 0x8319599991911111,
+           0x8913984898951989);
+  __asm__ volatile("vsetivli %[A], 12, e64, m1, tu, ma" : [A] "=r"(avl));
+  asm volatile("vse64.v v4, (%0), v0.t" ::"r"(ALIGNED_I64));
+  VCLEAR(v4);
+  VVCMP_U64(8, ALIGNED_I64, 1, 0xf9aa71f0c394bbd3, 3, 0x99991348a9f38cd1, 5,
+            0x3819759853987548, 7, 0x81937598aa819388, 9, 0x3eeeeeeee33111ae,
+            11, 0xab8b914891484891, 13, 14, 15, 16);
+}
+
+void TEST_CASE9(void) {
+  reset_vec64(ALIGNED_I64);
+  uint64_t avl;
+  VSET(16, e64, m1);
+  VLOAD_64(v4, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  asm volatile("vse64.v v4, (%0)" ::"r"(ALIGNED_I64));
+  VCLEAR(v4);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VLOAD_64(v4, 0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3, 0xa11a9384a7163840,
+           0x99991348a9f38cd1, 0x9fa831c7a11a9384, 0x3819759853987548,
+           0x1893179501093489, 0x81937598aa819388, 0x1874754791888188,
+           0x3eeeeeeee33111ae, 0x9013930148815808, 0xab8b914891484891,
+           0x9031850931584902, 0x3189759837598759, 0x8319599991911111,
+           0x8913984898951989);
+  __asm__ volatile("vsetivli %[A], 12, e16, m1, tu, mu" : [A] "=r"(avl));
+  asm volatile("vse64.v v4, (%0), v0.t" ::"r"(ALIGNED_I64));
+  VCLEAR(v4);
+  VVCMP_U64(9, ALIGNED_I64, 1, 0xf9aa71f0c394bbd3, 3, 0x99991348a9f38cd1, 5,
+            0x3819759853987548, 7, 0x81937598aa819388, 9, 0x3eeeeeeee33111ae,
+            11, 0xab8b914891484891, 13, 14, 15, 16);
+}
+
+//*******Checking functionality if encoded EEW is not supported for given SEW
+// and LMUL values because EMUL become out of range*****//
+// This test case cover upper bound of EMUL(8). If LMUL is changed to
+// m2 it will give error because emul become greater than 8 (EMUL = 16)
+void TEST_CASE10(void) {
+  VSET(16, e64, m1);
+  VLOAD_64(v8, 0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3, 0xa11a9384a7163840,
+           0x99991348a9f38cd1, 0x9fa831c7a11a9384, 0x3819759853987548,
+           0x1893179501093489, 0x81937598aa819388, 0x1874754791888188,
+           0x3eeeeeeee33111ae, 0x9013930148815808, 0xab8b914891484891,
+           0x9031850931584902, 0x3189759837598759, 0x8319599991911111,
+           0x8913984898951989);
+  VSET(16, e8, m1);
+  asm volatile("vse64.v v8, (%0)" ::"r"(ALIGNED_I64));
+  VCLEAR(v8);
+  VVCMP_U64(10, ALIGNED_I64, 0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3,
+            0xa11a9384a7163840, 0x99991348a9f38cd1, 0x9fa831c7a11a9384,
+            0x3819759853987548, 0x1893179501093489, 0x81937598aa819388,
+            0x1874754791888188, 0x3eeeeeeee33111ae, 0x9013930148815808,
+            0xab8b914891484891, 0x9031850931584902, 0x3189759837598759,
+            0x8319599991911111, 0x8913984898951989);
+}
+
+//******Checking functionality with different values of vl******//
+void TEST_CASE11(void) {
+  reset_vec64(ALIGNED_I64);
+  VSET(16, e64, m1);
+  VLOAD_64(v6, 0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3, 0xa11a9384a7163840,
+           0x99991348a9f38cd1, 0x9fa831c7a11a9384, 0x3819759853987548,
+           0x1893179501093489, 0x81937598aa819388, 0x1874754791888188,
+           0x3eeeeeeee33111ae, 0x9013930148815808, 0xab8b914891484891,
+           0x9031850931584902, 0x3189759837598759, 0x8319599991911111,
+           0x8913984898951989);
+  asm volatile("vse64.v v6, (%0)" ::"r"(ALIGNED_I64));
+  VCLEAR(v6);
+  VVCMP_U64(11, ALIGNED_I64, 0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3,
+            0xa11a9384a7163840, 0x99991348a9f38cd1, 0x9fa831c7a11a9384,
+            0x3819759853987548, 0x1893179501093489, 0x81937598aa819388,
+            0x1874754791888188, 0x3eeeeeeee33111ae, 0x9013930148815808,
+            0xab8b914891484891, 0x9031850931584902, 0x3189759837598759,
+            0x8319599991911111, 0x8913984898951989);
+}
+
+void TEST_CASE12(void) {
+  uint64_t avl;
+  VSET(16, e64, m1);
+  VLOAD_64(v6, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  asm volatile("vse64.v v6, (%0)" ::"r"(ALIGNED_I64));
+  VCLEAR(v6);
+  VLOAD_64(v6, 0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3, 0xa11a9384a7163840,
+           0x99991348a9f38cd1, 0x9fa831c7a11a9384, 0x3819759853987548,
+           0x1893179501093489, 0x81937598aa819388, 0x1874754791888188,
+           0x3eeeeeeee33111ae, 0x9013930148815808, 0xab8b914891484891,
+           0x9031850931584902, 0x3189759837598759, 0x8319599991911111,
+           0x8913984898951989);
+  __asm__ volatile("vsetivli %[A], 0, e64, m1, tu, ma" : [A] "=r"(avl));
+  asm volatile("vse64.v v6, (%0)" ::"r"(ALIGNED_I64));
+  VSET(16, e64, m1);
+  VVCMP_U64(12, ALIGNED_I64, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+            16);
+}
+
+void TEST_CASE13(void) {
+  VSET(16, e64, m1);
+  VLOAD_64(v6, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  asm volatile("vse64.v v6, (%0)" ::"r"(ALIGNED_I64));
+  VCLEAR(v6);
+  VLOAD_64(v6, 0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3, 0xa11a9384a7163840,
+           0x99991348a9f38cd1, 0x9fa831c7a11a9384, 0x3819759853987548,
+           0x1893179501093489, 0x81937598aa819388, 0x1874754791888188,
+           0x3eeeeeeee33111ae, 0x9013930148815808, 0xab8b914891484891,
+           0x9031850931584902, 0x3189759837598759, 0x8319599991911111,
+           0x8913984898951989);
+  VSET(13, e64, m1);
+  asm volatile("vse64.v v6, (%0)" ::"r"(ALIGNED_I64));
+  VSET(16, e64, m1);
+  VVCMP_U64(13, ALIGNED_I64, 0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3,
+            0xa11a9384a7163840, 0x99991348a9f38cd1, 0x9fa831c7a11a9384,
+            0x3819759853987548, 0x1893179501093489, 0x81937598aa819388,
+            0x1874754791888188, 0x3eeeeeeee33111ae, 0x9013930148815808,
+            0xab8b914891484891, 0x9031850931584902, 14, 15, 16);
+}
+
+//******Checking functionality with different vstart value*****//
+void TEST_CASE14(void) {
+  reset_vec64(ALIGNED_I64);
+  VSET(16, e64, m1);
+  VLOAD_64(v7, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  asm volatile("vse64.v v7, (%0)" ::"r"(ALIGNED_I64));
+  VCLEAR(v7);
+  VLOAD_64(v7, 0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3, 0xa11a9384a7163840,
+           0x99991348a9f38cd1, 0x9fa831c7a11a9384, 0x3819759853987548,
+           0x1893179501093489, 0x81937598aa819388, 0x1874754791888188,
+           0x3eeeeeeee33111ae, 0x9013930148815808, 0xab8b914891484891,
+           0x9031850931584902, 0x3189759837598759, 0x8319599991911111,
+           0x8913984898951989);
+  VSET(13, e64, m1);
+  write_csr(vstart, 2);
+  asm volatile("vse64.v v7, (%0)" ::"r"(ALIGNED_I64));
+  VVCMP_U64(14, ALIGNED_I64, 1, 2, 0xa11a9384a7163840, 0x99991348a9f38cd1,
+            0x9fa831c7a11a9384, 0x3819759853987548, 0x1893179501093489,
+            0x81937598aa819388, 0x1874754791888188, 0x3eeeeeeee33111ae,
+            0x9013930148815808, 0xab8b914891484891, 0x9031850931584902, 14, 15,
+            16);
+}
+
+//****Checking functionality with different values of EMUL and
+// large number of elements *******//
+void TEST_CASE15(void) {
+  reset_vec64(ALIGNED_I64);
+  VSET(512, e64, m8);
+  asm volatile("vle64.v v8, (%0)" ::"r"(&LONG_I64[0]));
+  asm volatile("vse64.v v8, (%0)" ::"r"(ALIGNED_I64));
+  LVVCMP_U64(15, ALIGNED_I64, LONG_I64);
+}
+
+void TEST_CASE16(void) {
+  reset_vec64(ALIGNED_I64);
+  VSET(256, e64, m4);
+  asm volatile("vle64.v v8, (%0)" ::"r"(&LONG_I64[0]));
+  asm volatile("vse64.v v8, (%0)" ::"r"(ALIGNED_I64));
+  LVVCMP_U64(16, ALIGNED_I64, LONG_I64);
+}
+
+void TEST_CASE17(void) {
+  reset_vec64(ALIGNED_I64);
+  VSET(128, e64, m2);
+  asm volatile("vle64.v v8, (%0)" ::"r"(&LONG_I64[0]));
+  asm volatile("vse64.v v8, (%0)" ::"r"(ALIGNED_I64));
+  LVVCMP_U64(17, ALIGNED_I64, LONG_I64);
+}
+
+void TEST_CASE18(void) {
+  reset_vec64(ALIGNED_I64);
+  VSET(100, e64, m2);
+  asm volatile("vle64.v v8, (%0)" ::"r"(&LONG_I64[0]));
+  asm volatile("vse64.v v8, (%0)" ::"r"(ALIGNED_I64));
+  LVVCMP_U64(18, ALIGNED_I64, LONG_I64);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  printf("*****Running tests for vse64.v*****\n");
+  TEST_CASE1();
+  // TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+  TEST_CASE6();
+  TEST_CASE7();
+  TEST_CASE8();
+  TEST_CASE9();
+  TEST_CASE10();
+  TEST_CASE11();
+  // TEST_CASE12();
+  TEST_CASE13();
+  // TEST_CASE14();
+  TEST_CASE15();
+  TEST_CASE16();
+  TEST_CASE17();
+  TEST_CASE18();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vse8.c b/apps/riscv-tests/isa/rv64uv/vse8.c
new file mode 100644
index 0000000..3542d2f
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vse8.c
@@ -0,0 +1,333 @@
+// TODO uncomment TEST_CASE12 and TEST_CASE 14 after issue of vl=0 and
+// non-zero vstart is resolved
+// TODO uncomment TEST_CASE2 after issue of exception is resolved
+#include "long_array.h"
+#include "vector_macros.h"
+
+#define AXI_DWIDTH 128
+void mtvec_handler(void) {
+  asm volatile("csrr t0, mcause"); // Read mcause
+
+  // Read mepc
+  asm volatile("csrr t1, mepc");
+
+  // Increment return address by 4
+  asm volatile("addi t1, t1, 4");
+  asm volatile("csrw mepc, t1");
+
+  // Filter with mcause and handle here
+
+  asm volatile("mret");
+}
+
+// Exception Handler for spike
+void handle_trap(void) {
+  // Read mepc
+  asm volatile("csrr t1, mepc");
+
+  // Increment return address by 4
+  asm volatile("addi t1, t1, 4");
+  asm volatile("csrw mepc, t1");
+
+  asm volatile("ld ra, 8(sp)");
+  asm volatile("ld sp, 16(sp)");
+  asm volatile("ld gp, 24(sp)");
+  asm volatile("ld tp, 32(sp)");
+  asm volatile("ld t0, 40(sp)");
+  asm volatile("ld t0, 40(sp)");
+  asm volatile("ld t1, 48(sp)");
+  asm volatile("ld t2, 56(sp)");
+  asm volatile("ld s0, 64(sp)");
+  asm volatile("ld s1, 72(sp)");
+  asm volatile("ld a0, 80(sp)");
+  asm volatile("ld a1, 88(sp)");
+  asm volatile("ld a2, 96(sp)");
+  asm volatile("ld a3, 104(sp)");
+  asm volatile("ld a4, 112(sp)");
+  asm volatile("ld a5, 120(sp)");
+  asm volatile("ld a6, 128(sp)");
+  asm volatile("ld a7, 136(sp)");
+  asm volatile("ld s2, 144(sp)");
+  asm volatile("ld s3, 152(sp)");
+  asm volatile("ld s4, 160(sp)");
+  asm volatile("ld s5, 168(sp)");
+  asm volatile("ld s6, 176(sp)");
+  asm volatile("ld s7, 184(sp)");
+  asm volatile("ld s8, 192(sp)");
+  asm volatile("ld s9, 200(sp)");
+  asm volatile("ld s10, 208(sp)");
+  asm volatile("ld s11, 216(sp)");
+  asm volatile("ld t3, 224(sp)");
+  asm volatile("ld t4, 232(sp)");
+  asm volatile("ld t5, 240(sp)");
+  asm volatile("ld t6, 248(sp)");
+
+  // Read mcause
+  asm volatile("csrr t3, mcause");
+
+  asm volatile("addi sp, sp, 272");
+
+  // Filter with mcause and handle here
+
+  asm volatile("mret");
+}
+
+void reset_vec8(volatile uint8_t *vec) {
+  for (uint64_t i = 0; i < 1024; ++i)
+    vec[i] = 0;
+}
+
+static volatile uint8_t ALIGNED_I8[1024] __attribute__((aligned(AXI_DWIDTH)));
+
+//**********Checking functionality of vse8 ********//
+void TEST_CASE1(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v0, 0xe0, 0xd3, 0x40, 0xd1, 0x84, 0x48, 0x89, 0x88, 0x88, 0xae, 0x08,
+          0x91, 0x02, 0x59, 0x11, 0x89);
+  asm volatile("vse8.v v0, (%0)" ::"r"(ALIGNED_I8));
+  VVCMP_U8(1, ALIGNED_I8, 0xe0, 0xd3, 0x40, 0xd1, 0x84, 0x48, 0x89, 0x88, 0x88,
+           0xae, 0x08, 0x91, 0x02, 0x59, 0x11, 0x89);
+}
+
+//******Checking functionality of  with illegal destination register
+// specifier for EMUL********//
+// In this test case EMUL=2 and register is v1 which will cause illegal
+// instruction exception and set mcause = 2
+void TEST_CASE2(void) {
+  uint8_t mcause;
+  reset_vec8(ALIGNED_I8);
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 0xe0, 0xd3, 0x40, 0xd1, 0x84, 0x48, 0x89, 0x88, 0x88, 0xae, 0x08,
+          0x91, 0x02, 0x59, 0x11, 0x89);
+  VSET(16, e16, m4);
+  asm volatile("vse8.v v1, (%0)" ::"r"(ALIGNED_I8));
+  asm volatile("addi %[A], t3, 0" : [A] "=r"(mcause));
+  XCMP(2, mcause, 2);
+}
+
+//*******Checking functionality of vse8 with different values of masking
+// register******//
+void TEST_CASE3(void) {
+  reset_vec8(ALIGNED_I8);
+  VSET(16, e8, m1);
+  VLOAD_8(v3, 0xe0, 0xd3, 0x40, 0xd1, 0x84, 0x48, 0x89, 0x88, 0x88, 0xae, 0x08,
+          0x91, 0x02, 0x59, 0x11, 0x89);
+  VLOAD_8(v0, 0xFF, 0xFF);
+  asm volatile("vse8.v v3, (%0), v0.t" ::"r"(ALIGNED_I8));
+  VCLEAR(v3);
+  VVCMP_U8(3, ALIGNED_I8, 0xe0, 0xd3, 0x40, 0xd1, 0x84, 0x48, 0x89, 0x88, 0x88,
+           0xae, 0x08, 0x91, 0x02, 0x59, 0x11, 0x89);
+}
+
+void TEST_CASE4(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v3, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  asm volatile("vse8.v v3, (%0)" ::"r"(ALIGNED_I8));
+  VCLEAR(v3);
+  VLOAD_8(v3, 0xe0, 0xd3, 0x40, 0xd1, 0x84, 0x48, 0x89, 0x88, 0x88, 0xae, 0x08,
+          0x91, 0x02, 0x59, 0x11, 0x89);
+  VLOAD_8(v0, 0x00, 0x00);
+  asm volatile("vse8.v v3, (%0), v0.t" ::"r"(ALIGNED_I8));
+  VCLEAR(v3);
+  VVCMP_U8(4, ALIGNED_I8, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+           16);
+}
+
+void TEST_CASE5(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v3, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  asm volatile("vse8.v v3, (%0)" ::"r"(ALIGNED_I8));
+  VCLEAR(v3);
+  VLOAD_8(v3, 0xe0, 0xd3, 0x40, 0xd1, 0x84, 0x48, 0x89, 0x88, 0x88, 0xae, 0x08,
+          0x91, 0x02, 0x59, 0x11, 0x89);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vse8.v v3, (%0), v0.t" ::"r"(ALIGNED_I8));
+  VCLEAR(v3);
+  VVCMP_U8(5, ALIGNED_I8, 1, 0xd3, 3, 0xd1, 5, 0x48, 7, 0x88, 9, 0xae, 11, 0x91,
+           13, 0x59, 15, 0x89);
+}
+
+//******Checking functionality with different combinations of vta and vma*****//
+// **** It uses undisturbed policy for tail agnostic and mask agnostic****//
+void TEST_CASE6(void) {
+  uint64_t avl;
+  VSET(16, e8, m1);
+  VLOAD_8(v4, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  asm volatile("vse8.v v4, (%0)" ::"r"(ALIGNED_I8));
+  VCLEAR(v4);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VLOAD_8(v4, 0xe0, 0xd3, 0x40, 0xd1, 0x84, 0x48, 0x89, 0x88, 0x88, 0xae, 0x08,
+          0x91, 0x02, 0x59, 0x11, 0x89);
+  __asm__ volatile("vsetivli %[A], 12, e8, m1, ta, ma" : [A] "=r"(avl));
+  asm volatile("vse8.v v4, (%0),v0.t" ::"r"(ALIGNED_I8));
+  VCLEAR(v4);
+  VVCMP_U8(6, ALIGNED_I8, 1, 0xd3, 3, 0xd1, 5, 0x48, 7, 0x88, 9, 0xae, 11, 0x91,
+           13, 14, 15, 16);
+}
+
+void TEST_CASE7(void) {
+  reset_vec8(ALIGNED_I8);
+  uint64_t avl;
+  VSET(16, e8, m1);
+  VLOAD_8(v4, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  asm volatile("vse8.v v4, (%0)" ::"r"(ALIGNED_I8));
+  VCLEAR(v4);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VLOAD_8(v4, 0xe0, 0xd3, 0x40, 0xd1, 0x84, 0x48, 0x89, 0x88, 0x88, 0xae, 0x08,
+          0x91, 0x02, 0x59, 0x11, 0x89);
+  __asm__ volatile("vsetivli %[A], 12, e8, m1, ta, mu" : [A] "=r"(avl));
+  asm volatile("vse8.v v4, (%0), v0.t" ::"r"(ALIGNED_I8));
+  VCLEAR(v4);
+  VVCMP_U8(7, ALIGNED_I8, 1, 0xd3, 3, 0xd1, 5, 0x48, 7, 0x88, 9, 0xae, 11, 0x91,
+           13, 14, 15, 16);
+}
+
+void TEST_CASE8(void) {
+  reset_vec8(ALIGNED_I8);
+  uint64_t avl;
+  VSET(16, e8, m1);
+  VLOAD_8(v4, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  asm volatile("vse8.v v4, (%0)" ::"r"(ALIGNED_I8));
+  VCLEAR(v4);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VLOAD_8(v4, 0xe0, 0xd3, 0x40, 0xd1, 0x84, 0x48, 0x89, 0x88, 0x88, 0xae, 0x08,
+          0x91, 0x02, 0x59, 0x11, 0x89);
+  __asm__ volatile("vsetivli %[A], 12, e8, m1, tu, ma" : [A] "=r"(avl));
+  asm volatile("vse8.v v4, (%0), v0.t" ::"r"(ALIGNED_I8));
+  VCLEAR(v4);
+  VVCMP_U8(8, ALIGNED_I8, 1, 0xd3, 3, 0xd1, 5, 0x48, 7, 0x88, 9, 0xae, 11, 0x91,
+           13, 14, 15, 16);
+}
+
+void TEST_CASE9(void) {
+  reset_vec8(ALIGNED_I8);
+  uint64_t avl;
+  VSET(16, e8, m1);
+  VLOAD_8(v4, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  asm volatile("vse8.v v4, (%0)" ::"r"(ALIGNED_I8));
+  VCLEAR(v4);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VLOAD_8(v4, 0xe0, 0xd3, 0x40, 0xd1, 0x84, 0x48, 0x89, 0x88, 0x88, 0xae, 0x08,
+          0x91, 0x02, 0x59, 0x11, 0x89);
+  __asm__ volatile("vsetivli %[A], 12, e8, m1, tu, mu" : [A] "=r"(avl));
+  asm volatile("vse8.v v4, (%0), v0.t" ::"r"(ALIGNED_I8));
+  VCLEAR(v4);
+  VVCMP_U8(9, ALIGNED_I8, 1, 0xd3, 3, 0xd1, 5, 0x48, 7, 0x88, 9, 0xae, 11, 0x91,
+           13, 14, 15, 16);
+}
+
+//*******Checking functionality if encoded EEW is not supported for given SEW
+// and LMUL values because EMUL become out of range*****//
+// This test case execute lower bound case of EMUL (1/8). If LMUL is changed to
+// mf4 or mf8 it will give error because emul become out of range
+void TEST_CASE10(void) {
+  reset_vec8(ALIGNED_I8);
+  VSET(16, e8, m1);
+  VLOAD_8(v5, 0xe0, 0xd3, 0x40, 0xd1, 0x84, 0x48, 0x89, 0x88, 0x88, 0xae, 0x08,
+          0x91, 0x02, 0x59, 0x11, 0x89);
+  VSET(16, e32, mf2);
+  asm volatile("vse8.v v5, (%0)" ::"r"(ALIGNED_I8));
+  VCLEAR(v5);
+  VVCMP_U8(10, ALIGNED_I8, 0xe0, 0xd3, 0x40, 0xd1, 0x84, 0x48, 0x89, 0x88, 0x88,
+           0xae, 0x08, 0x91, 0x02, 0x59, 0x11, 0x89);
+}
+
+//******Checking functionality with different values of vl******//
+void TEST_CASE11(void) {
+  reset_vec8(ALIGNED_I8);
+  VSET(16, e8, m1);
+  VLOAD_8(v6, 0xe0, 0xd3, 0x40, 0xd1, 0x84, 0x48, 0x89, 0x88, 0x88, 0xae, 0x08,
+          0x91, 0x02, 0x59, 0x11, 0x89);
+  asm volatile("vse8.v v6, (%0)" ::"r"(ALIGNED_I8));
+  VCLEAR(v6);
+  VVCMP_U8(11, ALIGNED_I8, 0xe0, 0xd3, 0x40, 0xd1, 0x84, 0x48, 0x89, 0x88, 0x88,
+           0xae, 0x08, 0x91, 0x02, 0x59, 0x11, 0x89);
+}
+
+void TEST_CASE12(void) {
+  uint64_t avl;
+  VSET(16, e8, m1);
+  VLOAD_8(v6, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  asm volatile("vse8.v v6, (%0)" ::"r"(ALIGNED_I8));
+  VCLEAR(v6);
+  VLOAD_8(v6, 0xe0, 0xd3, 0x40, 0xd1, 0x84, 0x48, 0x89, 0x88, 0x88, 0xae, 0x08,
+          0x91, 0x02, 0x59, 0x11, 0x89);
+  __asm__ volatile("vsetivli %[A], 0, e8, m1, tu, ma" : [A] "=r"(avl));
+  asm volatile("vse8.v v6, (%0)" ::"r"(ALIGNED_I8));
+  VSET(16, e8, m1);
+  VVCMP_U8(12, ALIGNED_I8, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+           16);
+}
+
+void TEST_CASE13(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v6, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  asm volatile("vse8.v v6, (%0)" ::"r"(ALIGNED_I8));
+  VCLEAR(v6);
+  VLOAD_8(v6, 0xe0, 0xd3, 0x40, 0xd1, 0x84, 0x48, 0x89, 0x88, 0x88, 0xae, 0x08,
+          0x91, 0x02, 0x59, 0x11, 0x89);
+  VSET(13, e8, m1);
+  asm volatile("vse8.v v6, (%0)" ::"r"(ALIGNED_I8));
+  VVCMP_U8(13, ALIGNED_I8, 0xe0, 0xd3, 0x40, 0xd1, 0x84, 0x48, 0x89, 0x88, 0x88,
+           0xae, 0x08, 0x91, 0x02, 14, 15, 16);
+}
+
+//******Checking functionality with different vstart value*****//
+void TEST_CASE14(void) {
+  reset_vec8(ALIGNED_I8);
+  VSET(16, e8, m1);
+  VLOAD_8(v7, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  asm volatile("vse8.v v7, (%0)" ::"r"(ALIGNED_I8));
+  VCLEAR(v7);
+  VLOAD_8(v7, 0xe0, 0xd3, 0x40, 0xd1, 0x84, 0x48, 0x89, 0x88, 0x88, 0xae, 0x08,
+          0x91, 0x02, 0x59, 0x11, 0x89);
+  VSET(13, e8, m1);
+  write_csr(vstart, 2);
+  asm volatile("vse8.v v7, (%0)" ::"r"(ALIGNED_I8));
+  write_csr(vstart, 0);
+  VVCMP_U8(14, ALIGNED_I8, 1, 2, 0x40, 0xd1, 0x84, 0x48, 0x89, 0x88, 0x88, 0xae,
+           0x08, 0x91, 0x02, 14, 15, 16);
+}
+
+//****Checking functionality with different values of EMUL and
+// large number of elements *******//
+
+void TEST_CASE15(void) {
+  reset_vec8(ALIGNED_I8);
+  VSET(1024, e8, m2);
+  asm volatile("vle8.v v8, (%0)" ::"r"(&LONG_I8[0]));
+  asm volatile("vse8.v v8, (%0)" ::"r"(ALIGNED_I8));
+  LVVCMP_U8(15, ALIGNED_I8, LONG_I8);
+}
+
+void TEST_CASE16(void) {
+  reset_vec8(ALIGNED_I8);
+  VSET(800, e8, m2);
+  asm volatile("vle8.v v8, (%0)" ::"r"(&LONG_I8[0]));
+  asm volatile("vse8.v v8, (%0)" ::"r"(ALIGNED_I8));
+  LVVCMP_U8(16, ALIGNED_I8, LONG_I8);
+}
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  printf("*****Running tests for vse8.v*****\n");
+  TEST_CASE1();
+  // TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+  TEST_CASE6();
+  TEST_CASE7();
+  TEST_CASE8();
+  TEST_CASE9();
+  TEST_CASE10();
+  TEST_CASE11();
+  // TEST_CASE12();
+  TEST_CASE13();
+  // TEST_CASE14();
+  TEST_CASE15();
+  TEST_CASE16();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vsetivli.c b/apps/riscv-tests/isa/rv64uv/vsetivli.c
new file mode 100644
index 0000000..4fb9d45
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vsetivli.c
@@ -0,0 +1,466 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+
+#include "vector_macros.h"
+
+//***********LMUL = 1**********//
+void TEST_CASE1(void) {
+  uint64_t avl, vtype,
+      vl; // Declaring avl,vtype and vl variables to pass for comparison
+  uint64_t vlmul = 0;    // Setting value of vlmul
+  uint64_t vsew = 0;     // Setting value of vsew
+  uint64_t vta = 1;      // Setting value of vta
+  uint64_t vma = 1;      // Setting value of vma
+  uint64_t golden_vtype; // Declaring variable to use as a reference value
+  vtype(golden_vtype, vlmul, vsew, vta,
+        vma); // Setting up reference variable golden_vtype by assigning
+              // different fields of configurations
+  __asm__ volatile("vsetivli %[A], 30, e8, m1, ta, ma"
+                   : [A] "=r"(avl)); // Executing vsetivli instruction
+  read_vtype(vtype);                 // Reading vtype CSR
+  read_vl(vl);                       // Reading vl CSR
+  check_vtype_vl(
+      1, vtype, golden_vtype, avl, vl, vsew,
+      vlmul); // Passsing actual values and reference values for comparison
+}
+
+void TEST_CASE2(void) {
+  uint64_t avl, vtype, vl;
+  uint64_t vlmul = 0;
+  uint64_t vsew = 1;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetivli %[A], 20, e16, m1,ta,ma" : [A] "=r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(2, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+void TEST_CASE3(void) {
+  uint64_t avl, vtype, vl;
+  uint64_t vlmul = 0;
+  uint64_t vsew = 2;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetivli %[A],10, e32, m1,ta,ma" : [A] "=r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(3, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+void TEST_CASE4(void) {
+  uint64_t avl, vtype, vl;
+  uint64_t vlmul = 0;
+  uint64_t vsew = 3;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetivli %[A],16, e64, m1,ta,ma" : [A] "=r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(4, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+/////////////////////////////////////////////////////////////////////////////////
+
+//***********LMUL = 2**********//
+void TEST_CASE5(void) {
+  uint64_t avl, vtype, vl;
+  uint64_t vlmul = 1;
+  uint64_t vsew = 0;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetivli %[A],30, e8, m2,ta,ma" : [A] "=r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(5, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+void TEST_CASE6(void) {
+  uint64_t avl, vtype, vl;
+  uint64_t vlmul = 1;
+  uint64_t vsew = 1;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetivli %[A],20, e16, m2,ta,ma" : [A] "=r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(6, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+void TEST_CASE7(void) {
+  uint64_t avl, vtype, vl;
+  uint64_t vlmul = 1;
+  uint64_t vsew = 2;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetivli %[A],10, e32, m2,ta,ma" : [A] "=r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(7, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+void TEST_CASE8(void) {
+  uint64_t avl, vtype, vl;
+  uint64_t vlmul = 1;
+  uint64_t vsew = 3;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetivli %[A],16, e64, m2,ta,ma" : [A] "=r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(8, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+///////////////////////////////////////////////////////////////////////////
+
+//***********LMUL = 4**********//
+
+void TEST_CASE9(void) {
+  uint64_t avl, vtype, vl;
+  uint64_t vlmul = 2;
+  uint64_t vsew = 0;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetivli %[A],30, e8, m4,ta,ma" : [A] "=r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(9, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+void TEST_CASE10(void) {
+  uint64_t avl, vtype, vl;
+  uint64_t vlmul = 2;
+  uint64_t vsew = 1;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetivli %[A],20, e16, m4,ta,ma" : [A] "=r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(10, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+void TEST_CASE11(void) {
+  uint64_t avl, vtype, vl;
+  uint64_t vlmul = 2;
+  uint64_t vsew = 2;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetivli %[A],10, e32, m4,ta,ma" : [A] "=r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(11, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+void TEST_CASE12(void) {
+  uint64_t avl, vtype, vl;
+  uint64_t vlmul = 2;
+  uint64_t vsew = 3;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetivli %[A],10, e64, m4,ta,ma" : [A] "=r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(12, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+/////////////////////////////////////////////////////////////////////////////////
+
+//***********LMUL = 8**********//
+
+void TEST_CASE13(void) {
+  uint64_t avl, vtype, vl;
+  uint64_t vlmul = 3;
+  uint64_t vsew = 0;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetivli %[A], 30, e8, m8,ta,ma" : [A] "=r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(13, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+void TEST_CASE14(void) {
+  uint64_t avl, vtype, vl;
+  uint64_t vlmul = 3;
+  uint64_t vsew = 1;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetivli %[A], 20, e16, m8,ta,ma" : [A] "=r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(14, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+void TEST_CASE15(void) {
+  uint64_t avl, vtype, vl;
+  uint64_t vlmul = 3;
+  uint64_t vsew = 2;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetivli %[A],10, e32, m8,ta,ma" : [A] "=r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(15, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+void TEST_CASE16(void) {
+  uint64_t avl, vtype, vl;
+  uint64_t vlmul = 3;
+  uint64_t vsew = 3;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetivli %[A], 10, e64, m8,ta,ma" : [A] "=r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(16, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+/////////////////////////////////////////////////////////////////////////////////
+
+//***********LMUL = 1/8**********//
+
+void TEST_CASE17(void) {
+  uint64_t avl, vtype, vl;
+  uint64_t vlmul = 5;
+  uint64_t vsew = 0;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetivli %[A], 10, e8, mf8,ta,ma" : [A] "=r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(17, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+void TEST_CASE18(void) {
+  uint64_t avl, vtype, vl;
+  uint64_t vlmul = 5;
+  uint64_t vsew = 1;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetivli %[A], 10, e16,mf8,ta,ma" : [A] "=r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(18, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+void TEST_CASE19(void) {
+  uint64_t avl, vtype, vl;
+  uint64_t vlmul = 5;
+  uint64_t vsew = 2;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetivli %[A], 5, e32, mf8,ta,ma" : [A] "=r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(19, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+void TEST_CASE20(void) {
+  uint64_t avl, vtype, vl;
+  uint64_t vlmul = 5;
+  uint64_t vsew = 3;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetivli %[A],7, e64, mf8,ta,ma" : [A] "=r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(20, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+///////////////////////////////////////////////////////////////////////////
+
+//***********LMUL = 1/4**********//
+
+void TEST_CASE21(void) {
+  uint64_t avl, vtype, vl;
+  uint64_t vlmul = 6;
+  uint64_t vsew = 0;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetivli %[A], 10, e8, mf4,ta,ma" : [A] "=r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(21, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+void TEST_CASE22(void) {
+  uint64_t avl, vtype, vl;
+  uint64_t vlmul = 6;
+  uint64_t vsew = 1;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetivli %[A], 10, e16, mf4,ta,ma" : [A] "=r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(22, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+void TEST_CASE23(void) {
+  uint64_t avl, vtype, vl;
+  uint64_t vlmul = 6;
+  uint64_t vsew = 2;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetivli %[A],5, e32, mf4,ta,ma" : [A] "=r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(23, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+void TEST_CASE24(void) {
+  uint64_t avl, vtype, vl;
+  uint64_t vlmul = 6;
+  uint64_t vsew = 3;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetivli %[A],15, e64, mf4,ta,ma" : [A] "=r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(24, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+/////////////////////////////////////////////////////////////////////////////////
+
+//***********LMUL = 1/2**********//
+
+void TEST_CASE25(void) {
+  uint64_t avl, vtype, vl;
+  uint64_t vlmul = 7;
+  uint64_t vsew = 0;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetivli %[A],20, e8, mf2,ta,ma" : [A] "=r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(25, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+void TEST_CASE26(void) {
+  uint64_t avl, vtype, vl;
+  uint64_t vlmul = 7;
+  uint64_t vsew = 1;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetivli %[A], 20, e16, mf2,ta,ma" : [A] "=r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(26, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+void TEST_CASE27(void) {
+  uint64_t avl, vtype, vl;
+  uint64_t vlmul = 7;
+  uint64_t vsew = 2;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetivli %[A], 20, e32, mf2,ta,ma" : [A] "=r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(27, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+void TEST_CASE28(void) {
+  uint64_t avl, vtype, vl;
+  uint64_t vlmul = 7;
+  uint64_t vsew = 3;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetivli %[A], 30, e64, mf2,ta,ma" : [A] "=r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(28, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  printf("************* Running Test for vsetivli *************\n");
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+  TEST_CASE6();
+  TEST_CASE7();
+  TEST_CASE8();
+  TEST_CASE9();
+  TEST_CASE10();
+  TEST_CASE11();
+  TEST_CASE12();
+  TEST_CASE13();
+  TEST_CASE14();
+  TEST_CASE15();
+  TEST_CASE16();
+  TEST_CASE17();
+  TEST_CASE18();
+  TEST_CASE19();
+  TEST_CASE20();
+  TEST_CASE21();
+  TEST_CASE22();
+  TEST_CASE23();
+  TEST_CASE24();
+  TEST_CASE25();
+  TEST_CASE26();
+  TEST_CASE27();
+  TEST_CASE28();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vsetvl.c b/apps/riscv-tests/isa/rv64uv/vsetvl.c
new file mode 100644
index 0000000..6486aad
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vsetvl.c
@@ -0,0 +1,497 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include <stdint.h>
+
+#include "vector_macros.h"
+
+//***********LMUL = 1**********//
+void TEST_CASE1(void) {
+  uint64_t avl = 250, vtype, vl; // Setting avl and declaring vtype and vl
+                                 // variables to pass for comparison
+  uint64_t vlmul = 0;            // Setting value of vlmul
+  uint64_t vsew = 0;             // Setting value of vsew
+  uint64_t vta = 1;              // Setting value of vta
+  uint64_t vma = 1;              // Setting value of vma
+  uint64_t golden_vtype; // Declaring variable to use as a reference value
+  vtype(golden_vtype, vlmul, vsew, vta,
+        vma); // Setting up reference variable golden_vtype by assigning
+              // different fields of configurations
+  __asm__ volatile("vsetvl t0, %[A], %[B]" ::[A] "r"(avl),
+                   [B] "r"(golden_vtype)); // Executing vsetvl instruction
+  read_vtype(vtype);                       // Reading vtype CSR
+  read_vl(vl);                             // Reading vl CSR
+  check_vtype_vl(
+      1, vtype, golden_vtype, avl, vl, vsew,
+      vlmul); // Passsing actual values and reference values for comparison
+}
+
+void TEST_CASE2(void) {
+  uint64_t avl = 120, vtype, vl;
+  uint64_t vlmul = 0;
+  uint64_t vsew = 1;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile(
+      "vsetvl t0, %[A], %[B]" ::[A] "r"(avl), [B] "r"(golden_vtype));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(2, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+void TEST_CASE3(void) {
+  uint64_t avl = 60, vtype, vl;
+  uint64_t vlmul = 0;
+  uint64_t vsew = 2;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile(
+      "vsetvl t0, %[A], %[B]" ::[A] "r"(avl), [B] "r"(golden_vtype));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(3, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+void TEST_CASE4(void) {
+  uint64_t avl = 30, vtype, vl;
+  uint64_t vlmul = 0;
+  uint64_t vsew = 3;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile(
+      "vsetvl t0, %[A], %[B]" ::[A] "r"(avl), [B] "r"(golden_vtype));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(4, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+/////////////////////////////////////////////////////////////////////////////////
+
+//***********LMUL = 2**********//
+void TEST_CASE5(void) {
+  uint64_t avl = 350, vtype, vl;
+  uint64_t vlmul = 1;
+  uint64_t vsew = 0;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile(
+      "vsetvl t0, %[A], %[B]" ::[A] "r"(avl), [B] "r"(golden_vtype));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(5, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+void TEST_CASE6(void) {
+  uint64_t avl = 250, vtype, vl;
+  uint64_t vlmul = 1;
+  uint64_t vsew = 1;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile(
+      "vsetvl t0, %[A], %[B]" ::[A] "r"(avl), [B] "r"(golden_vtype));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(6, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+void TEST_CASE7(void) {
+  uint64_t avl = 120, vtype, vl;
+  uint64_t vlmul = 1;
+  uint64_t vsew = 2;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile(
+      "vsetvl t0, %[A], %[B]" ::[A] "r"(avl), [B] "r"(golden_vtype));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(7, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+void TEST_CASE8(void) {
+  uint64_t avl = 60, vtype, vl;
+  uint64_t vlmul = 1;
+  uint64_t vsew = 3;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile(
+      "vsetvl t0, %[A], %[B]" ::[A] "r"(avl), [B] "r"(golden_vtype));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(8, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+///////////////////////////////////////////////////////////////////////////
+
+//***********LMUL = 4**********//
+
+void TEST_CASE9(void) {
+  uint64_t avl = 350, vtype, vl;
+  uint64_t vlmul = 2;
+  uint64_t vsew = 0;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile(
+      "vsetvl t0, %[A], %[B]" ::[A] "r"(avl), [B] "r"(golden_vtype));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(9, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+void TEST_CASE10(void) {
+  uint64_t avl = 250, vtype, vl;
+  uint64_t vlmul = 2;
+  uint64_t vsew = 1;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile(
+      "vsetvl t0, %[A], %[B]" ::[A] "r"(avl), [B] "r"(golden_vtype));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(10, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+void TEST_CASE11(void) {
+  uint64_t avl = 120, vtype, vl;
+  uint64_t vlmul = 2;
+  uint64_t vsew = 2;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile(
+      "vsetvl t0, %[A], %[B]" ::[A] "r"(avl), [B] "r"(golden_vtype));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(11, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+void TEST_CASE12(void) {
+  uint64_t avl = 60, vtype, vl;
+  uint64_t vlmul = 2;
+  uint64_t vsew = 3;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile(
+      "vsetvl t0, %[A], %[B]" ::[A] "r"(avl), [B] "r"(golden_vtype));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(12, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+/////////////////////////////////////////////////////////////////////////////////
+
+//***********LMUL = 8**********//
+
+void TEST_CASE13(void) {
+  uint64_t avl = 350, vtype, vl;
+  uint64_t vlmul = 3;
+  uint64_t vsew = 0;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile(
+      "vsetvl t0, %[A], %[B]" ::[A] "r"(avl), [B] "r"(golden_vtype));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(13, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+void TEST_CASE14(void) {
+  uint64_t avl = 250, vtype, vl;
+  uint64_t vlmul = 3;
+  uint64_t vsew = 1;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile(
+      "vsetvl t0, %[A], %[B]" ::[A] "r"(avl), [B] "r"(golden_vtype));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(14, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+void TEST_CASE15(void) {
+  uint64_t avl = 120, vtype, vl;
+  uint64_t vlmul = 3;
+  uint64_t vsew = 2;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile(
+      "vsetvl t0, %[A], %[B]" ::[A] "r"(avl), [B] "r"(golden_vtype));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(15, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+void TEST_CASE16(void) {
+  uint64_t avl = 60, vtype, vl;
+  uint64_t vlmul = 3;
+  uint64_t vsew = 3;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile(
+      "vsetvl t0, %[A], %[B]" ::[A] "r"(avl), [B] "r"(golden_vtype));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(16, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+/////////////////////////////////////////////////////////////////////////////////
+
+//***********LMUL = 1/8**********//
+
+void TEST_CASE17(void) {
+  uint64_t avl = 30, vtype, vl;
+  uint64_t vlmul = 5;
+  uint64_t vsew = 0;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile(
+      "vsetvl t0, %[A], %[B]" ::[A] "r"(avl), [B] "r"(golden_vtype));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(17, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+void TEST_CASE18(void) {
+  uint64_t avl = 30, vtype, vl;
+  uint64_t vlmul = 5;
+  uint64_t vsew = 1;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile(
+      "vsetvl t0, %[A], %[B]" ::[A] "r"(avl), [B] "r"(golden_vtype));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(18, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+void TEST_CASE19(void) {
+  uint64_t avl = 15, vtype, vl;
+  uint64_t vlmul = 5;
+  uint64_t vsew = 2;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile(
+      "vsetvl t0, %[A], %[B]" ::[A] "r"(avl), [B] "r"(golden_vtype));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(19, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+void TEST_CASE20(void) {
+  uint64_t avl = 7, vtype, vl;
+  uint64_t vlmul = 5;
+  uint64_t vsew = 3;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile(
+      "vsetvl t0, %[A], %[B]" ::[A] "r"(avl), [B] "r"(golden_vtype));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(20, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+///////////////////////////////////////////////////////////////////////////
+
+//***********LMUL = 1/4**********//
+
+void TEST_CASE21(void) {
+  uint64_t avl = 60, vtype, vl;
+  uint64_t vlmul = 6;
+  uint64_t vsew = 0;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile(
+      "vsetvl t0, %[A], %[B]" ::[A] "r"(avl), [B] "r"(golden_vtype));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(21, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+void TEST_CASE22(void) {
+  uint64_t avl = 30, vtype, vl;
+  uint64_t vlmul = 6;
+  uint64_t vsew = 1;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile(
+      "vsetvl t0, %[A], %[B]" ::[A] "r"(avl), [B] "r"(golden_vtype));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(22, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+void TEST_CASE23(void) {
+  uint64_t avl = 30, vtype, vl;
+  uint64_t vlmul = 6;
+  uint64_t vsew = 2;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile(
+      "vsetvl t0, %[A], %[B]" ::[A] "r"(avl), [B] "r"(golden_vtype));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(23, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+void TEST_CASE24(void) {
+  uint64_t avl = 15, vtype, vl;
+  uint64_t vlmul = 6;
+  uint64_t vsew = 3;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile(
+      "vsetvl t0, %[A], %[B]" ::[A] "r"(avl), [B] "r"(golden_vtype));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(24, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+/////////////////////////////////////////////////////////////////////////////////
+
+//***********LMUL = 1/2**********//
+
+void TEST_CASE25(void) {
+  uint64_t avl = 120, vtype, vl;
+  uint64_t vlmul = 7;
+  uint64_t vsew = 0;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile(
+      "vsetvl t0, %[A], %[B]" ::[A] "r"(avl), [B] "r"(golden_vtype));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(25, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+void TEST_CASE26(void) {
+  uint64_t avl = 60, vtype, vl;
+  uint64_t vlmul = 7;
+  uint64_t vsew = 1;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile(
+      "vsetvl t0, %[A], %[B]" ::[A] "r"(avl), [B] "r"(golden_vtype));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(26, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+void TEST_CASE27(void) {
+  uint64_t avl = 30, vtype, vl;
+  uint64_t vlmul = 7;
+  uint64_t vsew = 2;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile(
+      "vsetvl t0, %[A], %[B]" ::[A] "r"(avl), [B] "r"(golden_vtype));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(27, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+void TEST_CASE28(void) {
+  uint64_t avl = 30, vtype, vl;
+  uint64_t vlmul = 7;
+  uint64_t vsew = 3;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile(
+      "vsetvl t0, %[A], %[B]" ::[A] "r"(avl), [B] "r"(golden_vtype));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(28, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  printf("************* Running Test for vsetvl *************\n");
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+  TEST_CASE6();
+  TEST_CASE7();
+  TEST_CASE8();
+  TEST_CASE9();
+  TEST_CASE10();
+  TEST_CASE11();
+  TEST_CASE12();
+  TEST_CASE13();
+  TEST_CASE14();
+  TEST_CASE15();
+  TEST_CASE16();
+  TEST_CASE17();
+  TEST_CASE18();
+  TEST_CASE19();
+  TEST_CASE20();
+  TEST_CASE21();
+  TEST_CASE22();
+  TEST_CASE23();
+  TEST_CASE24();
+  TEST_CASE25();
+  TEST_CASE26();
+  TEST_CASE27();
+  TEST_CASE28();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vsetvli.c b/apps/riscv-tests/isa/rv64uv/vsetvli.c
new file mode 100644
index 0000000..f8eb762
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vsetvli.c
@@ -0,0 +1,498 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include <stdint.h>
+
+#include "vector_macros.h"
+
+//***********LMUL = 1**********//
+
+//****** SEW = 8
+void TEST_CASE1(void) {
+  uint64_t avl = 250, vtype, vl; // Setting avl and declaring vtype and vl
+                                 // variables to pass for comparison
+  uint64_t vlmul = 0;            // Setting value of vlmul
+  uint64_t vsew = 0;             // Setting value of vsew
+  uint64_t vta = 1;              // Setting value of vta
+  uint64_t vma = 1;              // Setting value of vma
+  uint64_t golden_vtype; // Declaring variable to use as a reference value
+  vtype(golden_vtype, vlmul, vsew, vta,
+        vma); // Setting up reference variable golden_vtype by assigning
+              // different fields of configurations
+  __asm__ volatile("vsetvli t0, %[A], e8, m1,ta,ma" ::[A] "r"(
+      avl));         // Executing vsetvli instruction
+  read_vtype(vtype); // Reading vtype CSR
+  read_vl(vl);       // Reading vl CSR
+  check_vtype_vl(
+      1, vtype, golden_vtype, avl, vl, vsew,
+      vlmul); // Passsing actual values and reference values for comparison
+}
+
+//****** SEW = 16
+void TEST_CASE2(void) {
+  uint64_t avl = 120, vtype, vl;
+  uint64_t vlmul = 0;
+  uint64_t vsew = 1;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetvli t0, %[A], e16, m1,ta,ma" ::[A] "r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(2, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+//****** SEW = 32
+void TEST_CASE3(void) {
+  uint64_t avl = 60, vtype, vl;
+  uint64_t vlmul = 0;
+  uint64_t vsew = 2;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetvli t0, %[A], e32, m1,ta,ma" ::[A] "r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(3, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+//****** SEW = 64
+void TEST_CASE4(void) {
+  uint64_t avl = 30, vtype, vl;
+  uint64_t vlmul = 0;
+  uint64_t vsew = 3;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetvli t0, %[A], e64, m1,ta,ma" ::[A] "r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(4, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+/////////////////////////////////////////////////////////////////////////////////
+
+//***********LMUL = 2**********//
+//****** SEW = 8
+void TEST_CASE5(void) {
+  uint64_t avl = 350, vtype, vl;
+  uint64_t vlmul = 1;
+  uint64_t vsew = 0;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetvli t0, %[A], e8, m2,ta,ma" ::[A] "r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(5, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+//****** SEW = 16
+void TEST_CASE6(void) {
+  uint64_t avl = 250, vtype, vl;
+  uint64_t vlmul = 1;
+  uint64_t vsew = 1;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetvli t0, %[A], e16, m2,ta,ma" ::[A] "r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(6, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+//****** SEW = 32
+void TEST_CASE7(void) {
+  uint64_t avl = 120, vtype, vl;
+  uint64_t vlmul = 1;
+  uint64_t vsew = 2;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetvli t0, %[A], e32, m2,ta,ma" ::[A] "r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(7, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+//****** SEW = 64
+void TEST_CASE8(void) {
+  uint64_t avl = 60, vtype, vl;
+  uint64_t vlmul = 1;
+  uint64_t vsew = 3;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetvli t0, %[A], e64, m2,ta,ma" ::[A] "r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(8, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+///////////////////////////////////////////////////////////////////////////
+
+//***********LMUL = 4**********//
+
+//****** SEW = 8
+void TEST_CASE9(void) {
+  uint64_t avl = 350, vtype, vl;
+  uint64_t vlmul = 2;
+  uint64_t vsew = 0;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetvli t0, %[A], e8, m4,ta,ma" ::[A] "r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(9, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+//****** SEW = 16
+void TEST_CASE10(void) {
+  uint64_t avl = 250, vtype, vl;
+  uint64_t vlmul = 2;
+  uint64_t vsew = 1;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetvli t0, %[A], e16, m4,ta,ma" ::[A] "r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(10, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+//****** SEW = 32
+void TEST_CASE11(void) {
+  uint64_t avl = 120, vtype, vl;
+  uint64_t vlmul = 2;
+  uint64_t vsew = 2;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetvli t0, %[A], e32, m4,ta,ma" ::[A] "r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(11, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+//****** SEW = 64
+void TEST_CASE12(void) {
+  uint64_t avl = 60, vtype, vl;
+  uint64_t vlmul = 2;
+  uint64_t vsew = 3;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetvli t0, %[A], e64, m4,ta,ma" ::[A] "r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(12, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+/////////////////////////////////////////////////////////////////////////////////
+
+//***********LMUL = 8**********//
+
+//****** SEW = 8
+void TEST_CASE13(void) {
+  uint64_t avl = 350, vtype, vl;
+  uint64_t vlmul = 3;
+  uint64_t vsew = 0;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetvli t0, %[A], e8, m8,ta,ma" ::[A] "r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(13, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+//****** SEW = 16
+void TEST_CASE14(void) {
+  uint64_t avl = 250, vtype, vl;
+  uint64_t vlmul = 3;
+  uint64_t vsew = 1;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetvli t0, %[A], e16, m8,ta,ma" ::[A] "r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(14, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+//****** SEW = 32
+void TEST_CASE15(void) {
+  uint64_t avl = 120, vtype, vl;
+  uint64_t vlmul = 3;
+  uint64_t vsew = 2;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetvli t0, %[A], e32, m8,ta,ma" ::[A] "r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(15, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+//****** SEW = 64
+void TEST_CASE16(void) {
+  uint64_t avl = 60, vtype, vl;
+  uint64_t vlmul = 3;
+  uint64_t vsew = 3;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetvli t0, %[A], e64, m8,ta,ma" ::[A] "r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(16, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+/////////////////////////////////////////////////////////////////////////////////
+
+//***********LMUL = 1/8**********//
+
+//****** SEW = 8
+void TEST_CASE17(void) {
+  uint64_t avl = 30, vtype, vl;
+  uint64_t vlmul = 5;
+  uint64_t vsew = 0;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetvli t0, %[A], e8, mf8,ta,ma" ::[A] "r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(17, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+//****** SEW = 16
+void TEST_CASE18(void) {
+  uint64_t avl = 30, vtype, vl;
+  uint64_t vlmul = 5;
+  uint64_t vsew = 1;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetvli t0, %[A], e16,mf8,ta,ma" ::[A] "r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(18, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+//****** SEW = 32
+void TEST_CASE19(void) {
+  uint64_t avl = 15, vtype, vl;
+  uint64_t vlmul = 5;
+  uint64_t vsew = 2;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetvli t0, %[A], e32, mf8,ta,ma" ::[A] "r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(19, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+//****** SEW = 64
+void TEST_CASE20(void) {
+  uint64_t avl = 7, vtype, vl;
+  uint64_t vlmul = 5;
+  uint64_t vsew = 3;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetvli t0, %[A], e64, mf8,ta,ma" ::[A] "r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(20, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+///////////////////////////////////////////////////////////////////////////
+
+//***********LMUL = 1/4**********//
+
+//****** SEW = 8
+void TEST_CASE21(void) {
+  uint64_t avl = 60, vtype, vl;
+  uint64_t vlmul = 6;
+  uint64_t vsew = 0;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetvli t0, %[A], e8, mf4,ta,ma" ::[A] "r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(21, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+//****** SEW = 16
+void TEST_CASE22(void) {
+  uint64_t avl = 30, vtype, vl;
+  uint64_t vlmul = 6;
+  uint64_t vsew = 1;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetvli t0, %[A], e16, mf4,ta,ma" ::[A] "r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(22, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+//****** SEW = 32
+void TEST_CASE23(void) {
+  uint64_t avl = 30, vtype, vl;
+  uint64_t vlmul = 6;
+  uint64_t vsew = 2;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetvli t0, %[A], e32, mf4,ta,ma" ::[A] "r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(23, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+//****** SEW = 64
+void TEST_CASE24(void) {
+  uint64_t avl = 15, vtype, vl;
+  uint64_t vlmul = 6;
+  uint64_t vsew = 3;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetvli t0, %[A], e64, mf4,ta,ma" ::[A] "r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(24, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+/////////////////////////////////////////////////////////////////////////////////
+
+//***********LMUL = 1/2**********//
+
+//****** SEW = 8
+void TEST_CASE25(void) {
+  uint64_t avl = 120, vtype, vl;
+  uint64_t vlmul = 7;
+  uint64_t vsew = 0;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetvli t0, %[A], e8, mf2,ta,ma" ::[A] "r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(25, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+//****** SEW = 16
+void TEST_CASE26(void) {
+  uint64_t avl = 60, vtype, vl;
+  uint64_t vlmul = 7;
+  uint64_t vsew = 1;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetvli t0, %[A], e16, mf2,ta,ma" ::[A] "r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(26, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+//****** SEW = 32
+void TEST_CASE27(void) {
+  uint64_t avl = 30, vtype, vl;
+  uint64_t vlmul = 7;
+  uint64_t vsew = 2;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetvli t0, %[A], e32, mf2,ta,ma" ::[A] "r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(27, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+//****** SEW = 64
+void TEST_CASE28(void) {
+  uint64_t avl = 30, vtype, vl;
+  uint64_t vlmul = 7;
+  uint64_t vsew = 3;
+  uint64_t vta = 1;
+  uint64_t vma = 1;
+  uint64_t golden_vtype;
+  vtype(golden_vtype, vlmul, vsew, vta, vma);
+  __asm__ volatile("vsetvli t0, %[A], e64, mf2,ta,ma" ::[A] "r"(avl));
+  read_vtype(vtype);
+  read_vl(vl);
+  check_vtype_vl(28, vtype, golden_vtype, avl, vl, vsew, vlmul);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  printf("************* Running Test for vsetvli *************\n");
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+  TEST_CASE6();
+  TEST_CASE7();
+  TEST_CASE8();
+  TEST_CASE9();
+  TEST_CASE10();
+  TEST_CASE11();
+  TEST_CASE12();
+  TEST_CASE13();
+  TEST_CASE14();
+  TEST_CASE15();
+  TEST_CASE16();
+  TEST_CASE17();
+  TEST_CASE18();
+  TEST_CASE19();
+  TEST_CASE20();
+  TEST_CASE21();
+  TEST_CASE22();
+  TEST_CASE23();
+  TEST_CASE24();
+  TEST_CASE25();
+  TEST_CASE26();
+  TEST_CASE27();
+  TEST_CASE28();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vsext.c b/apps/riscv-tests/isa/rv64uv/vsext.c
new file mode 100644
index 0000000..81d74e6
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vsext.c
@@ -0,0 +1,106 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  VLOAD_8(v1, 1, 2, -3, -4, 5, 6, -7, -8, -1, -2, 3, 4, -5, -6, 7, 8);
+  asm volatile("vsext.vf2 v2, v1");
+  VCMP_U16(1, v2, 1, 2, -3, -4, 5, 6, -7, -8, -1, -2, 3, 4, -5, -6, 7, 8);
+
+  VSET(16, e32, m1);
+  VLOAD_16(v1, 1, 2, -3, -4, 5, 6, -7, -8, -1, -2, 3, 4, -5, -6, 7, 8);
+  asm volatile("vsext.vf2 v2, v1");
+  VCMP_U32(2, v2, 1, 2, -3, -4, 5, 6, -7, -8, -1, -2, 3, 4, -5, -6, 7, 8);
+
+  VSET(16, e64, m1);
+  VLOAD_32(v1, 1, 2, -3, -4, 5, 6, -7, -8, -1, -2, 3, 4, -5, -6, 7, 8);
+  asm volatile("vsext.vf2 v2, v1");
+  VCMP_U64(3, v2, 1, 2, -3, -4, 5, 6, -7, -8, -1, -2, 3, 4, -5, -6, 7, 8);
+}
+
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  VLOAD_8(v1, 1, 2, -3, -4, 5, 6, -7, -8, -1, -2, 3, 4, -5, -6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v2);
+  asm volatile("vsext.vf2 v2, v1, v0.t");
+  VCMP_U16(4, v2, 0, 2, 0, -4, 0, 6, 0, -8, 0, -2, 0, 4, 0, -6, 0, 8);
+
+  VSET(16, e32, m1);
+  VLOAD_16(v1, 1, 2, -3, -4, 5, 6, -7, -8, -1, -2, 3, 4, -5, -6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v2);
+  asm volatile("vsext.vf2 v2, v1, v0.t");
+  VCMP_U32(5, v2, 0, 2, 0, -4, 0, 6, 0, -8, 0, -2, 0, 4, 0, -6, 0, 8);
+
+  VSET(16, e64, m1);
+  VLOAD_32(v1, 1, 2, -3, -4, 5, 6, -7, -8, -1, -2, 3, 4, -5, -6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v2);
+  asm volatile("vsext.vf2 v2, v1, v0.t");
+  VCMP_U64(6, v2, 0, 2, 0, -4, 0, 6, 0, -8, 0, -2, 0, 4, 0, -6, 0, 8);
+}
+
+void TEST_CASE3(void) {
+  VSET(16, e32, m1);
+  VLOAD_8(v1, 1, 2, -3, -4, 5, 6, -7, -8, -1, -2, 3, 4, -5, -6, 7, 8);
+  asm volatile("vsext.vf4 v2, v1");
+  VCMP_U32(7, v2, 1, 2, -3, -4, 5, 6, -7, -8, -1, -2, 3, 4, -5, -6, 7, 8);
+
+  VSET(16, e64, m1);
+  VLOAD_16(v1, 1, 2, -3, -4, 5, 6, -7, -8, -1, -2, 3, 4, -5, -6, 7, 8);
+  asm volatile("vsext.vf4 v2, v1");
+  VCMP_U64(8, v2, 1, 2, -3, -4, 5, 6, -7, -8, -1, -2, 3, 4, -5, -6, 7, 8);
+}
+
+void TEST_CASE4(void) {
+  VSET(16, e32, m1);
+  VLOAD_8(v1, 1, 2, -3, -4, 5, 6, -7, -8, -1, -2, 3, 4, -5, -6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v2);
+  asm volatile("vsext.vf4 v2, v1, v0.t");
+  VCMP_U32(9, v2, 0, 2, 0, -4, 0, 6, 0, -8, 0, -2, 0, 4, 0, -6, 0, 8);
+
+  VSET(16, e64, m1);
+  VLOAD_16(v1, 1, 2, -3, -4, 5, 6, -7, -8, -1, -2, 3, 4, -5, -6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v2);
+  asm volatile("vsext.vf4 v2, v1, v0.t");
+  VCMP_U64(10, v2, 0, 2, 0, -4, 0, 6, 0, -8, 0, -2, 0, 4, 0, -6, 0, 8);
+}
+
+void TEST_CASE5(void) {
+  VSET(16, e64, m1);
+  VLOAD_8(v1, 1, 2, -3, -4, 5, 6, -7, -8, -1, -2, 3, 4, -5, -6, 7, 8);
+  asm volatile("vsext.vf8 v2, v1");
+  VCMP_U64(11, v2, 1, 2, -3, -4, 5, 6, -7, -8, -1, -2, 3, 4, -5, -6, 7, 8);
+}
+
+void TEST_CASE6(void) {
+  VSET(16, e64, m1);
+  VLOAD_8(v1, 1, 2, -3, -4, 5, 6, -7, -8, -1, -2, 3, 4, -5, -6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v2);
+  asm volatile("vsext.vf8 v2, v1, v0.t");
+  VCMP_U64(12, v2, 0, 2, 0, -4, 0, 6, 0, -8, 0, -2, 0, 4, 0, -6, 0, 8);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+  TEST_CASE6();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vslide1down.c b/apps/riscv-tests/isa/rv64uv/vslide1down.c
new file mode 100644
index 0000000..8d339da
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vslide1down.c
@@ -0,0 +1,102 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1() {
+  uint64_t scalar = 99;
+
+  VSET(32, e8, m1);
+  VLOAD_8(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
+          20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_8(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  asm volatile("vslide1down.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U8(1, v1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 99);
+
+  VSET(32, e16, m1);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18,
+           19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_16(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  asm volatile("vslide1down.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U16(2, v1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 99);
+
+  VSET(32, e32, m1);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18,
+           19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_32(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  asm volatile("vslide1down.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U32(3, v1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 99);
+
+  VSET(32, e64, m1);
+  VLOAD_64(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18,
+           19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_64(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  asm volatile("vslide1down.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U64(4, v1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 99);
+}
+
+void TEST_CASE2() {
+  uint64_t scalar = 99;
+
+  VSET(32, e8, m1);
+  VLOAD_8(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
+          20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_8(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vslide1down.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U8(5, v1, -1, 3, -1, 5, -1, 7, -1, 9, -1, 11, -1, 13, -1, 15, -1, 99);
+
+  VSET(32, e16, m1);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18,
+           19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_16(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  VLOAD_8(v0, 0x55, 0x55);
+  asm volatile("vslide1down.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U16(6, v1, 2, -1, 4, -1, 6, -1, 8, -1, 10, -1, 12, -1, 14, -1, 16, -1);
+
+  VSET(32, e32, m1);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18,
+           19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_32(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vslide1down.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U32(7, v1, -1, 3, -1, 5, -1, 7, -1, 9, -1, 11, -1, 13, -1, 15, -1, 99);
+
+  VSET(32, e64, m1);
+  VLOAD_64(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18,
+           19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_64(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  VLOAD_8(v0, 0x55, 0x55);
+  asm volatile("vslide1down.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U64(8, v1, 2, -1, 4, -1, 6, -1, 8, -1, 10, -1, 12, -1, 14, -1, 16, -1);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vslide1up.c b/apps/riscv-tests/isa/rv64uv/vslide1up.c
new file mode 100644
index 0000000..f1a3fb8
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vslide1up.c
@@ -0,0 +1,78 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1() {
+  uint64_t scalar = 99;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_8(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  asm volatile("vslide1up.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U8(1, v1, 99, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_16(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  asm volatile("vslide1up.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U16(2, v1, 99, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_32(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  asm volatile("vslide1up.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U32(3, v1, 99, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_64(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  asm volatile("vslide1up.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U64(4, v1, 99, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+}
+
+void TEST_CASE2() {
+  uint64_t scalar = 99;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_8(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vslide1up.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U8(5, v1, -1, 1, -1, 3, -1, 5, -1, 7, -1, 9, -1, 11, -1, 13, -1, 15);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_16(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  VLOAD_8(v0, 0x55, 0x55);
+  asm volatile("vslide1up.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U16(6, v1, 99, -1, 2, -1, 4, -1, 6, -1, 8, -1, 10, -1, 12, -1, 14, -1);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_32(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vslide1up.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U32(7, v1, -1, 1, -1, 3, -1, 5, -1, 7, -1, 9, -1, 11, -1, 13, -1, 15);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_64(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  VLOAD_8(v0, 0x55, 0x55);
+  asm volatile("vslide1up.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U64(8, v1, 99, -1, 2, -1, 4, -1, 6, -1, 8, -1, 10, -1, 12, -1, 14, -1);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vslidedown.c b/apps/riscv-tests/isa/rv64uv/vslidedown.c
new file mode 100644
index 0000000..e46e680
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vslidedown.c
@@ -0,0 +1,181 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1() {
+  VSET(32, e8, m1);
+  VLOAD_8(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
+          20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
+  VSET(16, e8, m1);
+  VLOAD_8(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  asm volatile("vslidedown.vi v1, v2, 3");
+  VCMP_U8(1, v1, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19);
+
+  VSET(32, e16, m1);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18,
+           19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
+  VSET(16, e16, m1);
+  VLOAD_16(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  asm volatile("vslidedown.vi v1, v2, 4");
+  VCMP_U16(2, v1, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20);
+
+  VSET(32, e32, m1);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18,
+           19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
+  VSET(16, e32, m1);
+  VLOAD_32(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  asm volatile("vslidedown.vi v1, v2, 5");
+  VCMP_U32(3, v1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21);
+
+  VSET(32, e64, m1);
+  VLOAD_64(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18,
+           19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
+  VSET(16, e64, m1);
+  VLOAD_64(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  asm volatile("vslidedown.vi v1, v2, 6");
+  VCMP_U64(4, v1, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22);
+}
+
+void TEST_CASE2() {
+  VSET(32, e8, m1);
+  VLOAD_8(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
+          20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
+  VSET(16, e8, m1);
+  VLOAD_8(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vslidedown.vi v1, v2, 3, v0.t");
+  VCMP_U8(5, v1, -1, 5, -1, 7, -1, 9, -1, 11, -1, 13, -1, 15, -1, 17, -1, 19);
+
+  VSET(32, e16, m1);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18,
+           19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
+  VSET(16, e16, m1);
+  VLOAD_16(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  asm volatile("vslidedown.vi v1, v2, 4, v0.t");
+  VCMP_U16(6, v1, -1, 6, -1, 8, -1, 10, -1, 12, -1, 14, -1, 16, -1, 18, -1, 20);
+
+  VSET(32, e32, m1);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18,
+           19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
+  VSET(16, e32, m1);
+  VLOAD_32(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  asm volatile("vslidedown.vi v1, v2, 5, v0.t");
+  VCMP_U32(7, v1, -1, 7, -1, 9, -1, 11, -1, 13, -1, 15, -1, 17, -1, 19, -1, 21);
+
+  VSET(32, e64, m1);
+  VLOAD_64(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18,
+           19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
+  VSET(16, e64, m1);
+  VLOAD_64(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  asm volatile("vslidedown.vi v1, v2, 6, v0.t");
+  VCMP_U64(8, v1, -1, 8, -1, 10, -1, 12, -1, 14, -1, 16, -1, 18, -1, 20, -1,
+           22);
+}
+
+void TEST_CASE3() {
+  uint64_t scalar = 3;
+
+  VSET(32, e8, m1);
+  VLOAD_8(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
+          20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
+  VSET(16, e8, m1);
+  VLOAD_8(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  asm volatile("vslidedown.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U8(9, v1, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19);
+
+  VSET(32, e16, m1);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18,
+           19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
+  VSET(16, e16, m1);
+  VLOAD_16(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  asm volatile("vslidedown.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U16(10, v1, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19);
+
+  VSET(32, e32, m1);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18,
+           19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
+  VSET(16, e32, m1);
+  VLOAD_32(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  asm volatile("vslidedown.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U32(11, v1, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19);
+
+  VSET(32, e64, m1);
+  VLOAD_64(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18,
+           19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
+  VSET(16, e64, m1);
+  VLOAD_64(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  asm volatile("vslidedown.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U64(12, v1, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19);
+}
+
+void TEST_CASE4() {
+  uint64_t scalar = 3;
+
+  VSET(32, e8, m1);
+  VLOAD_8(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
+          20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
+  VSET(16, e8, m1);
+  VLOAD_8(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vslidedown.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U8(13, v1, -1, 5, -1, 7, -1, 9, -1, 11, -1, 13, -1, 15, -1, 17, -1, 19);
+
+  VSET(32, e16, m1);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18,
+           19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
+  VSET(16, e16, m1);
+  VLOAD_16(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vslidedown.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U16(14, v1, -1, 5, -1, 7, -1, 9, -1, 11, -1, 13, -1, 15, -1, 17, -1, 19);
+
+  VSET(32, e32, m1);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18,
+           19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
+  VSET(16, e32, m1);
+  VLOAD_32(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vslidedown.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U32(15, v1, -1, 5, -1, 7, -1, 9, -1, 11, -1, 13, -1, 15, -1, 17, -1, 19);
+
+  VSET(32, e64, m1);
+  VLOAD_64(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18,
+           19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
+  VSET(16, e64, m1);
+  VLOAD_64(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vslidedown.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U64(16, v1, -1, 5, -1, 7, -1, 9, -1, 11, -1, 13, -1, 15, -1, 17, -1, 19);
+}
+
+// Corner case: NrLanes divides vl, but the stride requires the operand
+// requester to request an additional 64-bit packet per lane, and not only an
+// additional 32-bit element per lane. Otherwise, it gets stuck
+void TEST_CASE5() {
+  VSET(32, e32, m1);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18,
+           19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
+  VSET(12, e32, m1);
+  VLOAD_32(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  asm volatile("vslidedown.vi v1, v2, 7");
+  VCMP_U32(17, v1, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  TEST_CASE5();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vslideup.c b/apps/riscv-tests/isa/rv64uv/vslideup.c
new file mode 100644
index 0000000..862a1a9
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vslideup.c
@@ -0,0 +1,166 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1() {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_8(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  asm volatile("vslideup.vi v1, v2, 3");
+  VCMP_U8(1, v1, -1, -1, -1, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_16(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  asm volatile("vslideup.vi v1, v2, 4");
+  VCMP_U16(2, v1, -1, -1, -1, -1, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_32(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  asm volatile("vslideup.vi v1, v2, 5");
+  VCMP_U32(3, v1, -1, -1, -1, -1, -1, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_64(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  asm volatile("vslideup.vi v1, v2, 6");
+  VCMP_U64(4, v1, -1, -1, -1, -1, -1, -1, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10);
+}
+
+void TEST_CASE2() {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_8(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vslideup.vi v1, v2, 3, v0.t");
+  VCMP_U8(5, v1, -1, -1, -1, 1, -1, 3, -1, 5, -1, 7, -1, 9, -1, 11, -1, 13);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_16(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  asm volatile("vslideup.vi v1, v2, 4, v0.t");
+  VCMP_U16(6, v1, -1, -1, -1, -1, -1, 2, -1, 4, -1, 6, -1, 8, -1, 10, -1, 12);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_32(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  asm volatile("vslideup.vi v1, v2, 5, v0.t");
+  VCMP_U32(7, v1, -1, -1, -1, -1, -1, 1, -1, 3, -1, 5, -1, 7, -1, 9, -1, 11);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_64(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  asm volatile("vslideup.vi v1, v2, 6, v0.t");
+  VCMP_U64(8, v1, -1, -1, -1, -1, -1, -1, -1, 2, -1, 4, -1, 6, -1, 8, -1, 10);
+}
+
+void TEST_CASE3() {
+  uint64_t scalar = 3;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_8(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  asm volatile("vslideup.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U8(9, v1, -1, -1, -1, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_16(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  asm volatile("vslideup.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U16(10, v1, -1, -1, -1, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_32(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  asm volatile("vslideup.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U32(11, v1, -1, -1, -1, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_64(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  asm volatile("vslideup.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U64(12, v1, -1, -1, -1, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13);
+}
+
+void TEST_CASE4() {
+  uint64_t scalar = 3;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_8(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vslideup.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U8(13, v1, -1, -1, -1, 1, -1, 3, -1, 5, -1, 7, -1, 9, -1, 11, -1, 13);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_16(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vslideup.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U16(14, v1, -1, -1, -1, 1, -1, 3, -1, 5, -1, 7, -1, 9, -1, 11, -1, 13);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_32(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vslideup.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U32(15, v1, -1, -1, -1, 1, -1, 3, -1, 5, -1, 7, -1, 9, -1, 11, -1, 13);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_64(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vslideup.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U64(16, v1, -1, -1, -1, 1, -1, 3, -1, 5, -1, 7, -1, 9, -1, 11, -1, 13);
+}
+
+// Stress the masked VSLIDEUP to enforce that the used mask bit indices should
+// follow the output vector element indices and not the input ones
+void TEST_CASE5() {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_8(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  VLOAD_8(v0, 0xAA, 0x80);
+  asm volatile("vslideup.vi v1, v2, 3, v0.t");
+  VCMP_U8(17, v1, -1, -1, -1, 1, -1, 3, -1, 5, -1, -1, -1, -1, -1, -1, -1, 13);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_16(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  asm volatile("vslideup.vi v1, v2, 4, v0.t");
+  VCMP_U16(18, v1, -1, -1, -1, -1, -1, 2, -1, 4, -1, -1, -1, -1, -1, -1, -1,
+           12);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_32(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  asm volatile("vslideup.vi v1, v2, 5, v0.t");
+  VCMP_U32(19, v1, -1, -1, -1, -1, -1, 1, -1, 3, -1, -1, -1, -1, -1, -1, -1,
+           11);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16);
+  VLOAD_64(v1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1);
+  asm volatile("vslideup.vi v1, v2, 6, v0.t");
+  VCMP_U64(20, v1, -1, -1, -1, -1, -1, -1, -1, 2, -1, -1, -1, -1, -1, -1, -1,
+           10);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vsll.c b/apps/riscv-tests/isa/rv64uv/vsll.c
new file mode 100644
index 0000000..b8710fb
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vsll.c
@@ -0,0 +1,316 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+          0x01, 0x01, 0x01, 0x01, 0x01);
+  VLOAD_8(v3, 0, 1, 2, 3, 7, 15, 31, 32, 0, 1, 2, 3, 7, 15, 31, 32);
+  asm volatile("vsll.vv v4, v2, v3");
+  VCMP_U8(1, v4, 0x01, 0x02, 0x04, 0x08, 0x80, 0x80, 0x80, 0x01, 0x01, 0x02,
+          0x04, 0x08, 0x80, 0x80, 0x80, 0x01);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001,
+           0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001);
+  VLOAD_16(v3, 0, 1, 2, 3, 7, 15, 31, 32, 0, 1, 2, 3, 7, 15, 31, 32);
+  asm volatile("vsll.vv v4, v2, v3");
+  VCMP_U16(2, v4, 0x0001, 0x0002, 0x0004, 0x0008, 0x0080, 0x8000, 0x8000,
+           0x0001, 0x0001, 0x0002, 0x0004, 0x0008, 0x0080, 0x8000, 0x8000,
+           0x0001);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001,
+           0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001,
+           0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001,
+           0x00000001);
+  VLOAD_32(v3, 0, 1, 2, 3, 7, 15, 31, 32, 0, 1, 2, 3, 7, 15, 31, 32);
+  asm volatile("vsll.vv v4, v2, v3");
+  VCMP_U32(3, v4, 0x00000001, 0x00000002, 0x00000004, 0x00000008, 0x00000080,
+           0x00008000, 0x80000000, 0x00000001, 0x00000001, 0x00000002,
+           0x00000004, 0x00000008, 0x00000080, 0x00008000, 0x80000000,
+           0x00000001);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x0000000000000001, 0x0000000000000001, 0x0000000000000001,
+           0x0000000000000001, 0x0000000000000001, 0x0000000000000001,
+           0x0000000000000001, 0x0000000000000001, 0x0000000000000001,
+           0x0000000000000001, 0x0000000000000001, 0x0000000000000001,
+           0x0000000000000001, 0x0000000000000001, 0x0000000000000001,
+           0x0000000000000001);
+  VLOAD_64(v3, 0, 1, 2, 3, 7, 15, 31, 32, 0, 1, 2, 3, 7, 15, 31, 32);
+  asm volatile("vsll.vv v4, v2, v3");
+  VCMP_U64(4, v4, 0x000000000000001, 0x0000000000000002, 0x0000000000000004,
+           0x0000000000000008, 0x0000000000000080, 0x0000000000008000,
+           0x0000000080000000, 0x0000000100000000, 0x0000000000000001,
+           0x0000000000000002, 0x0000000000000004, 0x0000000000000008,
+           0x0000000000000080, 0x0000000000008000, 0x0000000080000000,
+           0x0000000100000000);
+};
+
+void TEST_CASE2(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+          0x01, 0x01, 0x01, 0x01, 0x01);
+  VLOAD_8(v3, 0, 1, 2, 3, 7, 15, 31, 32, 0, 1, 2, 3, 7, 15, 31, 32);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vsll.vv v4, v2, v3, v0.t");
+  VCMP_U8(5, v4, 0x00, 0x02, 0x00, 0x08, 0x00, 0x80, 0x00, 0x01, 0x00, 0x02,
+          0x00, 0x08, 0x00, 0x80, 0x00, 0x01);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001,
+           0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001);
+  VLOAD_16(v3, 0, 1, 2, 3, 7, 15, 31, 32, 0, 1, 2, 3, 7, 15, 31, 32);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vsll.vv v4, v2, v3, v0.t");
+  VCMP_U16(6, v4, 0x0000, 0x0002, 0x0000, 0x0008, 0x0000, 0x8000, 0x0000,
+           0x0001, 0x0000, 0x0002, 0x0000, 0x0008, 0x0000, 0x8000, 0x0000,
+           0x0001);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001,
+           0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001,
+           0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001,
+           0x00000001);
+  VLOAD_32(v3, 0, 1, 2, 3, 7, 15, 31, 32, 0, 1, 2, 3, 7, 15, 31, 32);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vsll.vv v4, v2, v3, v0.t");
+  VCMP_U32(7, v4, 0x00000000, 0x00000002, 0x00000000, 0x00000008, 0x00000000,
+           0x00008000, 0x00000000, 0x00000001, 0x00000000, 0x00000002,
+           0x00000000, 0x00000008, 0x00000000, 0x00008000, 0x00000000,
+           0x00000001);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x0000000000000001, 0x0000000000000001, 0x0000000000000001,
+           0x0000000000000001, 0x0000000000000001, 0x0000000000000001,
+           0x0000000000000001, 0x0000000000000001, 0x0000000000000001,
+           0x0000000000000001, 0x0000000000000001, 0x0000000000000001,
+           0x0000000000000001, 0x0000000000000001, 0x0000000000000001,
+           0x0000000000000001);
+  VLOAD_64(v3, 0, 1, 2, 3, 7, 15, 31, 32, 0, 1, 2, 3, 7, 15, 31, 32);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vsll.vv v4, v2, v3, v0.t");
+  VCMP_U64(8, v4, 0x000000000000000, 0x0000000000000002, 0x0000000000000000,
+           0x0000000000000008, 0x0000000000000000, 0x0000000000008000,
+           0x0000000000000000, 0x0000000100000000, 0x0000000000000000,
+           0x0000000000000002, 0x0000000000000000, 0x0000000000000008,
+           0x0000000000000000, 0x0000000000008000, 0x0000000000000000,
+           0x0000000100000000);
+};
+
+void TEST_CASE3(void) {
+  const uint64_t scalar = 2;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0xF8, 0xF9, 0xFA,
+          0xFB, 0xFC, 0xFD, 0xFE, 0xFF);
+  asm volatile("vsll.vx v4, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U8(9, v4, 0x04, 0x08, 0x0C, 0x10, 0x14, 0x18, 0x1C, 0x20, 0xE0, 0xE4,
+          0xE8, 0xEC, 0xF0, 0xF4, 0xF8, 0xFC);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007, 0x0008,
+           0xFFF8, 0xFFF9, 0xFFFA, 0xFFFB, 0xFFFC, 0xFFFD, 0xFFFE, 0x00FF);
+  asm volatile("vsll.vx v4, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U16(10, v4, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018, 0x001C,
+           0x0020, 0xFFE0, 0xFFE4, 0xFFE8, 0xFFEC, 0xFFF0, 0xFFF4, 0xFFF8,
+           0x03FC);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x00000001, 0x00000002, 0x00000003, 0x00000004, 0x00000005,
+           0x00000006, 0x00000007, 0x00000008, 0xFFFFFFF8, 0xFFFFFFF9,
+           0xFFFFFFFA, 0xFFFFFFFB, 0xFFFFFFFC, 0xFFFFFFFD, 0xFFFFFFFE,
+           0x000000FF);
+  asm volatile("vsll.vx v4, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U32(11, v4, 0x00000004, 0x00000008, 0x0000000C, 0x00000010, 0x00000014,
+           0x00000018, 0x0000001C, 0x00000020, 0xFFFFFFE0, 0xFFFFFFE4,
+           0xFFFFFFE8, 0xFFFFFFEC, 0xFFFFFFF0, 0xFFFFFFF4, 0xFFFFFFF8,
+           0x000003FC);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x0000000000000001, 0x0000000000000002, 0x0000000000000003,
+           0x0000000000000004, 0x0000000000000005, 0x0000000000000006,
+           0x0000000000000007, 0x0000000000000008, 0xFFFFFFFFFFFFFFF8,
+           0xFFFFFFFFFFFFFFF9, 0xFFFFFFFFFFFFFFFA, 0xFFFFFFFFFFFFFFFB,
+           0xFFFFFFFFFFFFFFFC, 0xFFFFFFFFFFFFFFFD, 0xFFFFFFFFFFFFFFFE,
+           0x00000000000000FF);
+  asm volatile("vsll.vx v4, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U64(12, v4, 0x0000000000000004, 0x0000000000000008, 0x000000000000000C,
+           0x0000000000000010, 0x0000000000000014, 0x0000000000000018,
+           0x000000000000001C, 0x0000000000000020, 0xFFFFFFFFFFFFFFE0,
+           0xFFFFFFFFFFFFFFE4, 0xFFFFFFFFFFFFFFE8, 0xFFFFFFFFFFFFFFEC,
+           0xFFFFFFFFFFFFFFF0, 0xFFFFFFFFFFFFFFF4, 0xFFFFFFFFFFFFFFF8,
+           0x00000000000003FC);
+};
+
+void TEST_CASE4(void) {
+  const uint64_t scalar = 2;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0xF8, 0xF9, 0xFA,
+          0xFB, 0xFC, 0xFD, 0xFE, 0xFF);
+  VCLEAR(v4);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vsll.vx v4, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U8(13, v4, 0x00, 0x08, 0x00, 0x10, 0x00, 0x18, 0x00, 0x20, 0x00, 0xE4,
+          0x00, 0xEC, 0x00, 0xF4, 0x00, 0xFC);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007, 0x0008,
+           0xFFF8, 0xFFF9, 0xFFFA, 0xFFFB, 0xFFFC, 0xFFFD, 0xFFFE, 0x00FF);
+  VCLEAR(v4);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vsll.vx v4, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U16(14, v4, 0x0000, 0x0008, 0x0000, 0x0010, 0x0000, 0x0018, 0x0000,
+           0x0020, 0x0000, 0xFFE4, 0x0000, 0xFFEC, 0x0000, 0xFFF4, 0x0000,
+           0x03FC);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x00000001, 0x00000002, 0x00000003, 0x00000004, 0x00000005,
+           0x00000006, 0x00000007, 0x00000008, 0xFFFFFFF8, 0xFFFFFFF9,
+           0xFFFFFFFA, 0xFFFFFFFB, 0xFFFFFFFC, 0xFFFFFFFD, 0xFFFFFFFE,
+           0x000000FF);
+  VCLEAR(v4);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vsll.vx v4, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U32(15, v4, 0x00000000, 0x00000008, 0x00000000, 0x00000010, 0x00000000,
+           0x00000018, 0x00000000, 0x00000020, 0x00000000, 0xFFFFFFE4,
+           0x00000000, 0xFFFFFFEC, 0x00000000, 0xFFFFFFF4, 0x00000000,
+           0x000003FC);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x0000000000000001, 0x0000000000000002, 0x0000000000000003,
+           0x0000000000000004, 0x0000000000000005, 0x0000000000000006,
+           0x0000000000000007, 0x0000000000000008, 0xFFFFFFFFFFFFFFF8,
+           0xFFFFFFFFFFFFFFF9, 0xFFFFFFFFFFFFFFFA, 0xFFFFFFFFFFFFFFFB,
+           0xFFFFFFFFFFFFFFFC, 0xFFFFFFFFFFFFFFFD, 0xFFFFFFFFFFFFFFFE,
+           0x00000000000000FF);
+  VCLEAR(v4);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vsll.vx v4, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U64(16, v4, 0x0000000000000000, 0x0000000000000008, 0x0000000000000000,
+           0x0000000000000010, 0x0000000000000000, 0x0000000000000018,
+           0x0000000000000000, 0x0000000000000020, 0x0000000000000000,
+           0xFFFFFFFFFFFFFFE4, 0x0000000000000000, 0xFFFFFFFFFFFFFFEC,
+           0x0000000000000000, 0xFFFFFFFFFFFFFFF4, 0x0000000000000000,
+           0x00000000000003FC);
+};
+
+void TEST_CASE5(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0xF8, 0xF9, 0xFA,
+          0xFB, 0xFC, 0xFD, 0xFE, 0xFF);
+  asm volatile("vsll.vi v4, v2, 2");
+  VCMP_U8(17, v4, 0x04, 0x08, 0x0C, 0x10, 0x14, 0x18, 0x1C, 0x20, 0xE0, 0xE4,
+          0xE8, 0xEC, 0xF0, 0xF4, 0xF8, 0xFC);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007, 0x0008,
+           0xFFF8, 0xFFF9, 0xFFFA, 0xFFFB, 0xFFFC, 0xFFFD, 0xFFFE, 0x00FF);
+  asm volatile("vsll.vi v4, v2, 2");
+  VCMP_U16(18, v4, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018, 0x001C,
+           0x0020, 0xFFE0, 0xFFE4, 0xFFE8, 0xFFEC, 0xFFF0, 0xFFF4, 0xFFF8,
+           0x03FC);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x00000001, 0x00000002, 0x00000003, 0x00000004, 0x00000005,
+           0x00000006, 0x00000007, 0x00000008, 0xFFFFFFF8, 0xFFFFFFF9,
+           0xFFFFFFFA, 0xFFFFFFFB, 0xFFFFFFFC, 0xFFFFFFFD, 0xFFFFFFFE,
+           0x000000FF);
+  asm volatile("vsll.vi v4, v2, 2");
+  VCMP_U32(19, v4, 0x00000004, 0x00000008, 0x0000000C, 0x00000010, 0x00000014,
+           0x00000018, 0x0000001C, 0x00000020, 0xFFFFFFE0, 0xFFFFFFE4,
+           0xFFFFFFE8, 0xFFFFFFEC, 0xFFFFFFF0, 0xFFFFFFF4, 0xFFFFFFF8,
+           0x000003FC);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x0000000000000001, 0x0000000000000002, 0x0000000000000003,
+           0x0000000000000004, 0x0000000000000005, 0x0000000000000006,
+           0x0000000000000007, 0x0000000000000008, 0xFFFFFFFFFFFFFFF8,
+           0xFFFFFFFFFFFFFFF9, 0xFFFFFFFFFFFFFFFA, 0xFFFFFFFFFFFFFFFB,
+           0xFFFFFFFFFFFFFFFC, 0xFFFFFFFFFFFFFFFD, 0xFFFFFFFFFFFFFFFE,
+           0x00000000000000FF);
+  asm volatile("vsll.vi v4, v2, 2");
+  VCMP_U64(20, v4, 0x0000000000000004, 0x0000000000000008, 0x000000000000000C,
+           0x0000000000000010, 0x0000000000000014, 0x0000000000000018,
+           0x000000000000001C, 0x0000000000000020, 0xFFFFFFFFFFFFFFE0,
+           0xFFFFFFFFFFFFFFE4, 0xFFFFFFFFFFFFFFE8, 0xFFFFFFFFFFFFFFEC,
+           0xFFFFFFFFFFFFFFF0, 0xFFFFFFFFFFFFFFF4, 0xFFFFFFFFFFFFFFF8,
+           0x00000000000003FC);
+};
+
+void TEST_CASE6(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0xF8, 0xF9, 0xFA,
+          0xFB, 0xFC, 0xFD, 0xFE, 0xFF);
+  VCLEAR(v4);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vsll.vi v4, v2, 2, v0.t");
+  VCMP_U8(21, v4, 0x00, 0x08, 0x00, 0x10, 0x00, 0x18, 0x00, 0x20, 0x00, 0xE4,
+          0x00, 0xEC, 0x00, 0xF4, 0x00, 0xFC);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007, 0x0008,
+           0xFFF8, 0xFFF9, 0xFFFA, 0xFFFB, 0xFFFC, 0xFFFD, 0xFFFE, 0x00FF);
+  VCLEAR(v4);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vsll.vi v4, v2, 2, v0.t");
+  VCMP_U16(22, v4, 0x0000, 0x0008, 0x0000, 0x0010, 0x0000, 0x0018, 0x0000,
+           0x0020, 0x0000, 0xFFE4, 0x0000, 0xFFEC, 0x0000, 0xFFF4, 0x0000,
+           0x03FC);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x00000001, 0x00000002, 0x00000003, 0x00000004, 0x00000005,
+           0x00000006, 0x00000007, 0x00000008, 0xFFFFFFF8, 0xFFFFFFF9,
+           0xFFFFFFFA, 0xFFFFFFFB, 0xFFFFFFFC, 0xFFFFFFFD, 0xFFFFFFFE,
+           0x000000FF);
+  VCLEAR(v4);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vsll.vi v4, v2, 2, v0.t");
+  VCMP_U32(23, v4, 0x00000000, 0x00000008, 0x00000000, 0x00000010, 0x00000000,
+           0x00000018, 0x00000000, 0x00000020, 0x00000000, 0xFFFFFFE4,
+           0x00000000, 0xFFFFFFEC, 0x00000000, 0xFFFFFFF4, 0x00000000,
+           0x000003FC);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x0000000000000001, 0x0000000000000002, 0x0000000000000003,
+           0x0000000000000004, 0x0000000000000005, 0x0000000000000006,
+           0x0000000000000007, 0x0000000000000008, 0xFFFFFFFFFFFFFFF8,
+           0xFFFFFFFFFFFFFFF9, 0xFFFFFFFFFFFFFFFA, 0xFFFFFFFFFFFFFFFB,
+           0xFFFFFFFFFFFFFFFC, 0xFFFFFFFFFFFFFFFD, 0xFFFFFFFFFFFFFFFE,
+           0x00000000000000FF);
+  VCLEAR(v4);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vsll.vi v4, v2, 2, v0.t");
+  VCMP_U64(24, v4, 0x0000000000000000, 0x0000000000000008, 0x0000000000000000,
+           0x0000000000000010, 0x0000000000000000, 0x0000000000000018,
+           0x0000000000000000, 0x0000000000000020, 0x0000000000000000,
+           0xFFFFFFFFFFFFFFE4, 0x0000000000000000, 0xFFFFFFFFFFFFFFEC,
+           0x0000000000000000, 0xFFFFFFFFFFFFFFF4, 0x0000000000000000,
+           0x00000000000003FC);
+};
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+  TEST_CASE6();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vsmul.c b/apps/riscv-tests/isa/rv64uv/vsmul.c
new file mode 100644
index 0000000..0b97f2d
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vsmul.c
@@ -0,0 +1,59 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1() {
+  VSET(3, e8, m1);
+  VLOAD_8(v2, 127, 127, -50);
+  VLOAD_8(v3, 127, 10, 127);
+  __asm__ volatile("csrw vxrm, 2");
+  __asm__ volatile("vsmul.vv v1, v2, v3");
+  VCMP_I8(1, v1, 126, 9, -50);
+}
+
+void TEST_CASE2() {
+  VSET(3, e8, m1);
+  VLOAD_8(v2, 127, 127, -50);
+  VLOAD_8(v3, 127, 10, 127);
+  VLOAD_8(v0, 5, 0, 0);
+  VCLEAR(v1);
+  __asm__ volatile("csrw vxrm, 2");
+  __asm__ volatile("vsmul.vv v1, v2, v3, v0.t");
+  VCMP_I8(2, v1, 126, 0, -50);
+}
+
+void TEST_CASE3() {
+  VSET(3, e8, m1);
+  VLOAD_8(v2, 127, 63, -50);
+  int8_t scalar = 55;
+  __asm__ volatile("csrw vxrm, 2");
+  __asm__ volatile("vsmul.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_I8(3, v1, 54, 27, -22);
+}
+
+void TEST_CASE4() {
+  VSET(3, e8, m1);
+  VLOAD_8(v2, 127, 127, -50);
+  int8_t scalar = 55;
+  VLOAD_8(v0, 5, 0, 0);
+  VCLEAR(v1);
+  __asm__ volatile("csrw vxrm, 2");
+  __asm__ volatile("vsmul.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_I8(4, v1, 54, 0, -22);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+  enable_fp();
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  EXIT_CHECK();
+}
\ No newline at end of file
diff --git a/apps/riscv-tests/isa/rv64uv/vsra.c b/apps/riscv-tests/isa/rv64uv/vsra.c
new file mode 100644
index 0000000..e6e432c
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vsra.c
@@ -0,0 +1,316 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+          0x80, 0x80, 0x80, 0x80, 0x80);
+  VLOAD_8(v3, 0, 1, 2, 3, 7, 15, 31, 32, 0, 1, 2, 3, 7, 15, 31, 32);
+  asm volatile("vsra.vv v4, v2, v3");
+  VCMP_U8(1, v4, 0x80, 0xC0, 0xE0, 0xF0, 0xFF, 0xFF, 0xFF, 0x80, 0x80, 0xC0,
+          0xE0, 0xF0, 0xFF, 0xFF, 0xFF, 0x80);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000,
+           0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000);
+  VLOAD_16(v3, 0, 1, 2, 3, 7, 15, 31, 32, 0, 1, 2, 3, 7, 15, 31, 32);
+  asm volatile("vsra.vv v4, v2, v3");
+  VCMP_U16(2, v4, 0x8000, 0xC000, 0xE000, 0xF000, 0xFF00, 0xFFFF, 0xFFFF,
+           0x8000, 0x8000, 0xC000, 0xE000, 0xF000, 0xFF00, 0xFFFF, 0xFFFF,
+           0x8000);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000,
+           0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000,
+           0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000,
+           0x80000000);
+  VLOAD_32(v3, 0, 1, 2, 3, 7, 15, 31, 32, 0, 1, 2, 3, 7, 15, 31, 32);
+  asm volatile("vsra.vv v4, v2, v3");
+  VCMP_U32(3, v4, 0x80000000, 0xC0000000, 0xE0000000, 0xF0000000, 0xFF000000,
+           0xFFFF0000, 0xFFFFFFFF, 0x80000000, 0x80000000, 0xC0000000,
+           0xE0000000, 0xF0000000, 0xFF000000, 0xFFFF0000, 0xFFFFFFFF,
+           0x80000000);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x8000000000000000, 0x8000000000000000, 0x8000000000000000,
+           0x8000000000000000, 0x8000000000000000, 0x8000000000000000,
+           0x8000000000000000, 0x8000000000000000, 0x8000000000000000,
+           0x8000000000000000, 0x8000000000000000, 0x8000000000000000,
+           0x8000000000000000, 0x8000000000000000, 0x8000000000000000,
+           0x8000000000000000);
+  VLOAD_64(v3, 0, 1, 2, 3, 7, 15, 31, 32, 0, 1, 2, 3, 7, 15, 31, 32);
+  asm volatile("vsra.vv v4, v2, v3");
+  VCMP_U64(4, v4, 0x8000000000000000, 0xC000000000000000, 0xE000000000000000,
+           0xF000000000000000, 0xFF00000000000000, 0xFFFF000000000000,
+           0xFFFFFFFF00000000, 0xFFFFFFFF80000000, 0x8000000000000000,
+           0xC000000000000000, 0xE000000000000000, 0xF000000000000000,
+           0xFF00000000000000, 0xFFFF000000000000, 0xFFFFFFFF00000000,
+           0xFFFFFFFF80000000);
+};
+
+void TEST_CASE2(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+          0x80, 0x80, 0x80, 0x80, 0x80);
+  VLOAD_8(v3, 0, 1, 2, 3, 7, 15, 31, 32, 0, 1, 2, 3, 7, 15, 31, 32);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vsra.vv v4, v2, v3, v0.t");
+  VCMP_U8(5, v4, 0x00, 0xC0, 0x00, 0xF0, 0x00, 0xFF, 0x00, 0x80, 0x00, 0xC0,
+          0x00, 0xF0, 0x00, 0xFF, 0x00, 0x80);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000,
+           0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000);
+  VLOAD_16(v3, 0, 1, 2, 3, 7, 15, 31, 32, 0, 1, 2, 3, 7, 15, 31, 32);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vsra.vv v4, v2, v3, v0.t");
+  VCMP_U16(6, v4, 0x0000, 0xC000, 0x0000, 0xF000, 0x0000, 0xFFFF, 0x0000,
+           0x8000, 0x0000, 0xC000, 0x0000, 0xF000, 0x0000, 0xFFFF, 0x0000,
+           0x8000);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000,
+           0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000,
+           0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000,
+           0x80000000);
+  VLOAD_32(v3, 0, 1, 2, 3, 7, 15, 31, 32, 0, 1, 2, 3, 7, 15, 31, 32);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vsra.vv v4, v2, v3, v0.t");
+  VCMP_U32(7, v4, 0x00000000, 0xC0000000, 0x00000000, 0xF0000000, 0x00000000,
+           0xFFFF0000, 0x00000000, 0x80000000, 0x00000000, 0xC0000000,
+           0x00000000, 0xF0000000, 0x00000000, 0xFFFF0000, 0x00000000,
+           0x80000000);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x8000000000000000, 0x8000000000000000, 0x8000000000000000,
+           0x8000000000000000, 0x8000000000000000, 0x8000000000000000,
+           0x8000000000000000, 0x8000000000000000, 0x8000000000000000,
+           0x8000000000000000, 0x8000000000000000, 0x8000000000000000,
+           0x8000000000000000, 0x8000000000000000, 0x8000000000000000,
+           0x8000000000000000);
+  VLOAD_64(v3, 0, 1, 2, 3, 7, 15, 31, 32, 0, 1, 2, 3, 7, 15, 31, 32);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vsra.vv v4, v2, v3, v0.t");
+  VCMP_U64(8, v4, 0x0000000000000000, 0xC000000000000000, 0x0000000000000000,
+           0xF000000000000000, 0x0000000000000000, 0xFFFF000000000000,
+           0x0000000000000000, 0xFFFFFFFF80000000, 0x0000000000000000,
+           0xC000000000000000, 0x0000000000000000, 0xF000000000000000,
+           0x0000000000000000, 0xFFFF000000000000, 0x0000000000000000,
+           0xFFFFFFFF80000000);
+};
+
+void TEST_CASE3(void) {
+  const uint64_t scalar = 2;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x04, 0x08, 0x0C, 0x10, 0x14, 0x18, 0x1C, 0x20, 0xE0, 0xE4, 0xE8,
+          0xEC, 0xF0, 0xF4, 0xF8, 0xFC);
+  asm volatile("vsra.vx v4, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U8(9, v4, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0xF8, 0xF9,
+          0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018, 0x001C, 0x0020,
+           0xFFE0, 0xFFE4, 0xFFE8, 0xFFEC, 0xFFF0, 0xFFF4, 0xFFF8, 0xFFFC);
+  asm volatile("vsra.vx v4, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U16(10, v4, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007,
+           0x0008, 0xFFF8, 0xFFF9, 0xFFFA, 0xFFFB, 0xFFFC, 0xFFFD, 0xFFFE,
+           0xFFFF);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x00000004, 0x00000008, 0x0000000C, 0x00000010, 0x00000014,
+           0x00000018, 0x0000001C, 0x00000020, 0xFFFFFFE0, 0xFFFFFFE4,
+           0xFFFFFFE8, 0xFFFFFFEC, 0xFFFFFFF0, 0xFFFFFFF4, 0xFFFFFFF8,
+           0xFFFFFFFC);
+  asm volatile("vsra.vx v4, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U32(11, v4, 0x00000001, 0x00000002, 0x00000003, 0x00000004, 0x00000005,
+           0x00000006, 0x00000007, 0x00000008, 0xFFFFFFF8, 0xFFFFFFF9,
+           0xFFFFFFFA, 0xFFFFFFFB, 0xFFFFFFFC, 0xFFFFFFFD, 0xFFFFFFFE,
+           0xFFFFFFFF);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x0000000000000004, 0x0000000000000008, 0x000000000000000C,
+           0x0000000000000010, 0x0000000000000014, 0x0000000000000018,
+           0x000000000000001C, 0x0000000000000020, 0xFFFFFFFFFFFFFFE0,
+           0xFFFFFFFFFFFFFFE4, 0xFFFFFFFFFFFFFFE8, 0xFFFFFFFFFFFFFFEC,
+           0xFFFFFFFFFFFFFFF0, 0xFFFFFFFFFFFFFFF4, 0xFFFFFFFFFFFFFFF8,
+           0xFFFFFFFFFFFFFFFC);
+  asm volatile("vsra.vx v4, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U64(12, v4, 0x0000000000000001, 0x0000000000000002, 0x0000000000000003,
+           0x0000000000000004, 0x0000000000000005, 0x0000000000000006,
+           0x0000000000000007, 0x0000000000000008, 0xFFFFFFFFFFFFFFF8,
+           0xFFFFFFFFFFFFFFF9, 0xFFFFFFFFFFFFFFFA, 0xFFFFFFFFFFFFFFFB,
+           0xFFFFFFFFFFFFFFFC, 0xFFFFFFFFFFFFFFFD, 0xFFFFFFFFFFFFFFFE,
+           0xFFFFFFFFFFFFFFFF);
+};
+
+void TEST_CASE4(void) {
+  const uint64_t scalar = 2;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x04, 0x08, 0x0C, 0x10, 0x14, 0x18, 0x1C, 0x20, 0xE0, 0xE4, 0xE8,
+          0xEC, 0xF0, 0xF4, 0xF8, 0xFC);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vsra.vx v4, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U8(13, v4, 0x00, 0x02, 0x00, 0x04, 0x00, 0x06, 0x00, 0x08, 0x00, 0xF9,
+          0x00, 0xFB, 0x00, 0xFD, 0x00, 0xFF);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018, 0x001C, 0x0020,
+           0xFFE0, 0xFFE4, 0xFFE8, 0xFFEC, 0xFFF0, 0xFFF4, 0xFFF8, 0xFFFC);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vsra.vx v4, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U16(14, v4, 0x0000, 0x0002, 0x0000, 0x0004, 0x0000, 0x0006, 0x0000,
+           0x0008, 0x0000, 0xFFF9, 0x0000, 0xFFFB, 0x0000, 0xFFFD, 0x0000,
+           0xFFFF);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x00000004, 0x00000008, 0x0000000C, 0x00000010, 0x00000014,
+           0x00000018, 0x0000001C, 0x00000020, 0xFFFFFFE0, 0xFFFFFFE4,
+           0xFFFFFFE8, 0xFFFFFFEC, 0xFFFFFFF0, 0xFFFFFFF4, 0xFFFFFFF8,
+           0xFFFFFFFC);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vsra.vx v4, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U32(15, v4, 0x00000000, 0x00000002, 0x00000000, 0x00000004, 0x00000000,
+           0x00000006, 0x00000000, 0x00000008, 0x00000000, 0xFFFFFFF9,
+           0x00000000, 0xFFFFFFFB, 0x00000000, 0xFFFFFFFD, 0x00000000,
+           0xFFFFFFFF);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x0000000000000004, 0x0000000000000008, 0x000000000000000C,
+           0x0000000000000010, 0x0000000000000014, 0x0000000000000018,
+           0x000000000000001C, 0x0000000000000020, 0xFFFFFFFFFFFFFFE0,
+           0xFFFFFFFFFFFFFFE4, 0xFFFFFFFFFFFFFFE8, 0xFFFFFFFFFFFFFFEC,
+           0xFFFFFFFFFFFFFFF0, 0xFFFFFFFFFFFFFFF4, 0xFFFFFFFFFFFFFFF8,
+           0xFFFFFFFFFFFFFFFC);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vsra.vx v4, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U64(16, v4, 0x0000000000000000, 0x0000000000000002, 0x0000000000000000,
+           0x0000000000000004, 0x0000000000000000, 0x0000000000000006,
+           0x0000000000000000, 0x0000000000000008, 0x0000000000000000,
+           0xFFFFFFFFFFFFFFF9, 0x0000000000000000, 0xFFFFFFFFFFFFFFFB,
+           0x0000000000000000, 0xFFFFFFFFFFFFFFFD, 0x0000000000000000,
+           0xFFFFFFFFFFFFFFFF);
+};
+
+void TEST_CASE5(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x04, 0x08, 0x0C, 0x10, 0x14, 0x18, 0x1C, 0x20, 0xE0, 0xE4, 0xE8,
+          0xEC, 0xF0, 0xF4, 0xF8, 0xFC);
+  asm volatile("vsra.vi v4, v2, 2");
+  VCMP_U8(17, v4, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0xF8, 0xF9,
+          0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018, 0x001C, 0x0020,
+           0xFFE0, 0xFFE4, 0xFFE8, 0xFFEC, 0xFFF0, 0xFFF4, 0xFFF8, 0xFFFC);
+  asm volatile("vsra.vi v4, v2, 2");
+  VCMP_U16(18, v4, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007,
+           0x0008, 0xFFF8, 0xFFF9, 0xFFFA, 0xFFFB, 0xFFFC, 0xFFFD, 0xFFFE,
+           0xFFFF);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x00000004, 0x00000008, 0x0000000C, 0x00000010, 0x00000014,
+           0x00000018, 0x0000001C, 0x00000020, 0xFFFFFFE0, 0xFFFFFFE4,
+           0xFFFFFFE8, 0xFFFFFFEC, 0xFFFFFFF0, 0xFFFFFFF4, 0xFFFFFFF8,
+           0xFFFFFFFC);
+  asm volatile("vsra.vi v4, v2, 2");
+  VCMP_U32(19, v4, 0x00000001, 0x00000002, 0x00000003, 0x00000004, 0x00000005,
+           0x00000006, 0x00000007, 0x00000008, 0xFFFFFFF8, 0xFFFFFFF9,
+           0xFFFFFFFA, 0xFFFFFFFB, 0xFFFFFFFC, 0xFFFFFFFD, 0xFFFFFFFE,
+           0xFFFFFFFF);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x0000000000000004, 0x0000000000000008, 0x000000000000000C,
+           0x0000000000000010, 0x0000000000000014, 0x0000000000000018,
+           0x000000000000001C, 0x0000000000000020, 0xFFFFFFFFFFFFFFE0,
+           0xFFFFFFFFFFFFFFE4, 0xFFFFFFFFFFFFFFE8, 0xFFFFFFFFFFFFFFEC,
+           0xFFFFFFFFFFFFFFF0, 0xFFFFFFFFFFFFFFF4, 0xFFFFFFFFFFFFFFF8,
+           0xFFFFFFFFFFFFFFFC);
+  asm volatile("vsra.vi v4, v2, 2");
+  VCMP_U64(20, v4, 0x0000000000000001, 0x0000000000000002, 0x0000000000000003,
+           0x0000000000000004, 0x0000000000000005, 0x0000000000000006,
+           0x0000000000000007, 0x0000000000000008, 0xFFFFFFFFFFFFFFF8,
+           0xFFFFFFFFFFFFFFF9, 0xFFFFFFFFFFFFFFFA, 0xFFFFFFFFFFFFFFFB,
+           0xFFFFFFFFFFFFFFFC, 0xFFFFFFFFFFFFFFFD, 0xFFFFFFFFFFFFFFFE,
+           0xFFFFFFFFFFFFFFFF);
+};
+
+void TEST_CASE6(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x04, 0x08, 0x0C, 0x10, 0x14, 0x18, 0x1C, 0x20, 0xE0, 0xE4, 0xE8,
+          0xEC, 0xF0, 0xF4, 0xF8, 0xFC);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vsra.vi v4, v2, 2, v0.t");
+  VCMP_U8(21, v4, 0x00, 0x02, 0x00, 0x04, 0x00, 0x06, 0x00, 0x08, 0x00, 0xF9,
+          0x00, 0xFB, 0x00, 0xFD, 0x00, 0xFF);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018, 0x001C, 0x0020,
+           0xFFE0, 0xFFE4, 0xFFE8, 0xFFEC, 0xFFF0, 0xFFF4, 0xFFF8, 0xFFFC);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vsra.vi v4, v2, 2, v0.t");
+  VCMP_U16(22, v4, 0x0000, 0x0002, 0x0000, 0x0004, 0x0000, 0x0006, 0x0000,
+           0x0008, 0x0000, 0xFFF9, 0x0000, 0xFFFB, 0x0000, 0xFFFD, 0x0000,
+           0xFFFF);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x00000004, 0x00000008, 0x0000000C, 0x00000010, 0x00000014,
+           0x00000018, 0x0000001C, 0x00000020, 0xFFFFFFE0, 0xFFFFFFE4,
+           0xFFFFFFE8, 0xFFFFFFEC, 0xFFFFFFF0, 0xFFFFFFF4, 0xFFFFFFF8,
+           0xFFFFFFFC);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vsra.vi v4, v2, 2, v0.t");
+  VCMP_U32(23, v4, 0x00000000, 0x00000002, 0x00000000, 0x00000004, 0x00000000,
+           0x00000006, 0x00000000, 0x00000008, 0x00000000, 0xFFFFFFF9,
+           0x00000000, 0xFFFFFFFB, 0x00000000, 0xFFFFFFFD, 0x00000000,
+           0xFFFFFFFF);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x0000000000000004, 0x0000000000000008, 0x000000000000000C,
+           0x0000000000000010, 0x0000000000000014, 0x0000000000000018,
+           0x000000000000001C, 0x0000000000000020, 0xFFFFFFFFFFFFFFE0,
+           0xFFFFFFFFFFFFFFE4, 0xFFFFFFFFFFFFFFE8, 0xFFFFFFFFFFFFFFEC,
+           0xFFFFFFFFFFFFFFF0, 0xFFFFFFFFFFFFFFF4, 0xFFFFFFFFFFFFFFF8,
+           0xFFFFFFFFFFFFFFFC);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vsra.vi v4, v2, 2, v0.t");
+  VCMP_U64(24, v4, 0x0000000000000000, 0x0000000000000002, 0x0000000000000000,
+           0x0000000000000004, 0x0000000000000000, 0x0000000000000006,
+           0x0000000000000000, 0x0000000000000008, 0x0000000000000000,
+           0xFFFFFFFFFFFFFFF9, 0x0000000000000000, 0xFFFFFFFFFFFFFFFB,
+           0x0000000000000000, 0xFFFFFFFFFFFFFFFD, 0x0000000000000000,
+           0xFFFFFFFFFFFFFFFF);
+};
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+  TEST_CASE6();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vsrl.c b/apps/riscv-tests/isa/rv64uv/vsrl.c
new file mode 100644
index 0000000..e479481
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vsrl.c
@@ -0,0 +1,316 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+          0x80, 0x80, 0x80, 0x80, 0x80);
+  VLOAD_8(v3, 0, 1, 2, 3, 7, 15, 31, 32, 0, 1, 2, 3, 7, 15, 31, 32);
+  asm volatile("vsrl.vv v4, v2, v3");
+  VCMP_U8(1, v4, 0x80, 0x40, 0x20, 0x10, 0x01, 0x01, 0x01, 0x80, 0x80, 0x40,
+          0x20, 0x10, 0x01, 0x01, 0x01, 0x80);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000,
+           0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000);
+  VLOAD_16(v3, 0, 1, 2, 3, 7, 15, 31, 32, 0, 1, 2, 3, 7, 15, 31, 32);
+  asm volatile("vsrl.vv v4, v2, v3");
+  VCMP_U16(2, v4, 0x8000, 0x4000, 0x2000, 0x1000, 0x0100, 0x0001, 0x0001,
+           0x8000, 0x8000, 0x4000, 0x2000, 0x1000, 0x0100, 0x0001, 0x0001,
+           0x8000);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000,
+           0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000,
+           0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000,
+           0x80000000);
+  VLOAD_32(v3, 0, 1, 2, 3, 7, 15, 31, 32, 0, 1, 2, 3, 7, 15, 31, 32);
+  asm volatile("vsrl.vv v4, v2, v3");
+  VCMP_U32(3, v4, 0x80000000, 0x40000000, 0x20000000, 0x10000000, 0x01000000,
+           0x00010000, 0x00000001, 0x80000000, 0x80000000, 0x40000000,
+           0x20000000, 0x10000000, 0x01000000, 0x00010000, 0x00000001,
+           0x80000000);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x8000000000000000, 0x8000000000000000, 0x8000000000000000,
+           0x8000000000000000, 0x8000000000000000, 0x8000000000000000,
+           0x8000000000000000, 0x8000000000000000, 0x8000000000000000,
+           0x8000000000000000, 0x8000000000000000, 0x8000000000000000,
+           0x8000000000000000, 0x8000000000000000, 0x8000000000000000,
+           0x8000000000000000);
+  VLOAD_64(v3, 0, 1, 2, 3, 7, 15, 31, 32, 0, 1, 2, 3, 7, 15, 31, 32);
+  asm volatile("vsrl.vv v4, v2, v3");
+  VCMP_U64(4, v4, 0x8000000000000000, 0x4000000000000000, 0x2000000000000000,
+           0x1000000000000000, 0x0100000000000000, 0x0001000000000000,
+           0x0000000100000000, 0x0000000080000000, 0x8000000000000000,
+           0x4000000000000000, 0x2000000000000000, 0x1000000000000000,
+           0x0100000000000000, 0x0001000000000000, 0x0000000100000000,
+           0x0000000080000000);
+};
+
+void TEST_CASE2(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+          0x80, 0x80, 0x80, 0x80, 0x80);
+  VLOAD_8(v3, 0, 1, 2, 3, 7, 15, 31, 32, 0, 1, 2, 3, 7, 15, 31, 32);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vsrl.vv v4, v2, v3, v0.t");
+  VCMP_U8(5, v4, 0x00, 0x40, 0x00, 0x10, 0x00, 0x01, 0x00, 0x80, 0x00, 0x40,
+          0x00, 0x10, 0x00, 0x01, 0x00, 0x80);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000,
+           0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000);
+  VLOAD_16(v3, 0, 1, 2, 3, 7, 15, 31, 32, 0, 1, 2, 3, 7, 15, 31, 32);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vsrl.vv v4, v2, v3, v0.t");
+  VCMP_U16(6, v4, 0x0000, 0x4000, 0x0000, 0x1000, 0x0000, 0x0001, 0x0000,
+           0x8000, 0x0000, 0x4000, 0x0000, 0x1000, 0x0000, 0x0001, 0x0000,
+           0x8000);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000,
+           0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000,
+           0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000,
+           0x80000000);
+  VLOAD_32(v3, 0, 1, 2, 3, 7, 15, 31, 32, 0, 1, 2, 3, 7, 15, 31, 32);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vsrl.vv v4, v2, v3, v0.t");
+  VCMP_U32(7, v4, 0x00000000, 0x40000000, 0x00000000, 0x10000000, 0x00000000,
+           0x00010000, 0x00000000, 0x80000000, 0x00000000, 0x40000000,
+           0x00000000, 0x10000000, 0x00000000, 0x00010000, 0x00000000,
+           0x80000000);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x8000000000000000, 0x8000000000000000, 0x8000000000000000,
+           0x8000000000000000, 0x8000000000000000, 0x8000000000000000,
+           0x8000000000000000, 0x8000000000000000, 0x8000000000000000,
+           0x8000000000000000, 0x8000000000000000, 0x8000000000000000,
+           0x8000000000000000, 0x8000000000000000, 0x8000000000000000,
+           0x8000000000000000);
+  VLOAD_64(v3, 0, 1, 2, 3, 7, 15, 31, 32, 0, 1, 2, 3, 7, 15, 31, 32);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vsrl.vv v4, v2, v3, v0.t");
+  VCMP_U64(8, v4, 0x0000000000000000, 0x4000000000000000, 0x0000000000000000,
+           0x1000000000000000, 0x0000000000000000, 0x0001000000000000,
+           0x0000000000000000, 0x0000000080000000, 0x0000000000000000,
+           0x4000000000000000, 0x0000000000000000, 0x1000000000000000,
+           0x0000000000000000, 0x0001000000000000, 0x0000000000000000,
+           0x0000000080000000);
+};
+
+void TEST_CASE3(void) {
+  const uint64_t scalar = 2;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x04, 0x08, 0x0C, 0x10, 0x14, 0x18, 0x1C, 0x20, 0xE0, 0xE4, 0xE8,
+          0xEC, 0xF0, 0xF4, 0xF8, 0xFC);
+  asm volatile("vsrl.vx v4, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U8(9, v4, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x38, 0x39,
+          0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018, 0x001C, 0x0020,
+           0xFFE0, 0xFFE4, 0xFFE8, 0xFFEC, 0xFFF0, 0xFFF4, 0xFFF8, 0xFFFC);
+  asm volatile("vsrl.vx v4, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U16(10, v4, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007,
+           0x0008, 0x3FF8, 0x3FF9, 0x3FFA, 0x3FFB, 0x3FFC, 0x3FFD, 0x3FFE,
+           0x3FFF);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x00000004, 0x00000008, 0x0000000C, 0x00000010, 0x00000014,
+           0x00000018, 0x0000001C, 0x00000020, 0xFFFFFFE0, 0xFFFFFFE4,
+           0xFFFFFFE8, 0xFFFFFFEC, 0xFFFFFFF0, 0xFFFFFFF4, 0xFFFFFFF8,
+           0xFFFFFFFC);
+  asm volatile("vsrl.vx v4, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U32(11, v4, 0x00000001, 0x00000002, 0x00000003, 0x00000004, 0x00000005,
+           0x00000006, 0x00000007, 0x00000008, 0x3FFFFFF8, 0x3FFFFFF9,
+           0x3FFFFFFA, 0x3FFFFFFB, 0x3FFFFFFC, 0x3FFFFFFD, 0x3FFFFFFE,
+           0x3FFFFFFF);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x0000000000000004, 0x0000000000000008, 0x000000000000000C,
+           0x0000000000000010, 0x0000000000000014, 0x0000000000000018,
+           0x000000000000001C, 0x0000000000000020, 0xFFFFFFFFFFFFFFE0,
+           0xFFFFFFFFFFFFFFE4, 0xFFFFFFFFFFFFFFE8, 0xFFFFFFFFFFFFFFEC,
+           0xFFFFFFFFFFFFFFF0, 0xFFFFFFFFFFFFFFF4, 0xFFFFFFFFFFFFFFF8,
+           0xFFFFFFFFFFFFFFFC);
+  asm volatile("vsrl.vx v4, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U64(12, v4, 0x0000000000000001, 0x0000000000000002, 0x0000000000000003,
+           0x0000000000000004, 0x0000000000000005, 0x0000000000000006,
+           0x0000000000000007, 0x0000000000000008, 0x3FFFFFFFFFFFFFF8,
+           0x3FFFFFFFFFFFFFF9, 0x3FFFFFFFFFFFFFFA, 0x3FFFFFFFFFFFFFFB,
+           0x3FFFFFFFFFFFFFFC, 0x3FFFFFFFFFFFFFFD, 0x3FFFFFFFFFFFFFFE,
+           0x3FFFFFFFFFFFFFFF);
+};
+
+void TEST_CASE4(void) {
+  const uint64_t scalar = 2;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x04, 0x08, 0x0C, 0x10, 0x14, 0x18, 0x1C, 0x20, 0xE0, 0xE4, 0xE8,
+          0xEC, 0xF0, 0xF4, 0xF8, 0xFC);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vsrl.vx v4, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U8(13, v4, 0x00, 0x02, 0x00, 0x04, 0x00, 0x06, 0x00, 0x08, 0x00, 0x39,
+          0x00, 0x3B, 0x00, 0x3D, 0x00, 0x3F);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018, 0x001C, 0x0020,
+           0xFFE0, 0xFFE4, 0xFFE8, 0xFFEC, 0xFFF0, 0xFFF4, 0xFFF8, 0xFFFC);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vsrl.vx v4, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U16(14, v4, 0x0000, 0x0002, 0x0000, 0x0004, 0x0000, 0x0006, 0x0000,
+           0x0008, 0x0000, 0x3FF9, 0x0000, 0x3FFB, 0x0000, 0x3FFD, 0x0000,
+           0x3FFF);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x00000004, 0x00000008, 0x0000000C, 0x00000010, 0x00000014,
+           0x00000018, 0x0000001C, 0x00000020, 0xFFFFFFE0, 0xFFFFFFE4,
+           0xFFFFFFE8, 0xFFFFFFEC, 0xFFFFFFF0, 0xFFFFFFF4, 0xFFFFFFF8,
+           0xFFFFFFFC);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vsrl.vx v4, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U32(15, v4, 0x00000000, 0x00000002, 0x00000000, 0x00000004, 0x00000000,
+           0x00000006, 0x00000000, 0x00000008, 0x00000000, 0x3FFFFFF9,
+           0x00000000, 0x3FFFFFFB, 0x00000000, 0x3FFFFFFD, 0x00000000,
+           0x3FFFFFFF);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x0000000000000004, 0x0000000000000008, 0x000000000000000C,
+           0x0000000000000010, 0x0000000000000014, 0x0000000000000018,
+           0x000000000000001C, 0x0000000000000020, 0xFFFFFFFFFFFFFFE0,
+           0xFFFFFFFFFFFFFFE4, 0xFFFFFFFFFFFFFFE8, 0xFFFFFFFFFFFFFFEC,
+           0xFFFFFFFFFFFFFFF0, 0xFFFFFFFFFFFFFFF4, 0xFFFFFFFFFFFFFFF8,
+           0xFFFFFFFFFFFFFFFC);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vsrl.vx v4, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U64(16, v4, 0x0000000000000000, 0x0000000000000002, 0x0000000000000000,
+           0x0000000000000004, 0x0000000000000000, 0x0000000000000006,
+           0x0000000000000000, 0x0000000000000008, 0x0000000000000000,
+           0x3FFFFFFFFFFFFFF9, 0x0000000000000000, 0x3FFFFFFFFFFFFFFB,
+           0x0000000000000000, 0x3FFFFFFFFFFFFFFD, 0x0000000000000000,
+           0x3FFFFFFFFFFFFFFF);
+};
+
+void TEST_CASE5(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x04, 0x08, 0x0C, 0x10, 0x14, 0x18, 0x1C, 0x20, 0xE0, 0xE4, 0xE8,
+          0xEC, 0xF0, 0xF4, 0xF8, 0xFC);
+  asm volatile("vsrl.vi v4, v2, 2");
+  VCMP_U8(17, v4, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x38, 0x39,
+          0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018, 0x001C, 0x0020,
+           0xFFE0, 0xFFE4, 0xFFE8, 0xFFEC, 0xFFF0, 0xFFF4, 0xFFF8, 0xFFFC);
+  asm volatile("vsrl.vi v4, v2, 2");
+  VCMP_U16(18, v4, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007,
+           0x0008, 0x3FF8, 0x3FF9, 0x3FFA, 0x3FFB, 0x3FFC, 0x3FFD, 0x3FFE,
+           0x3FFF);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x00000004, 0x00000008, 0x0000000C, 0x00000010, 0x00000014,
+           0x00000018, 0x0000001C, 0x00000020, 0xFFFFFFE0, 0xFFFFFFE4,
+           0xFFFFFFE8, 0xFFFFFFEC, 0xFFFFFFF0, 0xFFFFFFF4, 0xFFFFFFF8,
+           0xFFFFFFFC);
+  asm volatile("vsrl.vi v4, v2, 2");
+  VCMP_U32(19, v4, 0x00000001, 0x00000002, 0x00000003, 0x00000004, 0x00000005,
+           0x00000006, 0x00000007, 0x00000008, 0x3FFFFFF8, 0x3FFFFFF9,
+           0x3FFFFFFA, 0x3FFFFFFB, 0x3FFFFFFC, 0x3FFFFFFD, 0x3FFFFFFE,
+           0x3FFFFFFF);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x0000000000000004, 0x0000000000000008, 0x000000000000000C,
+           0x0000000000000010, 0x0000000000000014, 0x0000000000000018,
+           0x000000000000001C, 0x0000000000000020, 0xFFFFFFFFFFFFFFE0,
+           0xFFFFFFFFFFFFFFE4, 0xFFFFFFFFFFFFFFE8, 0xFFFFFFFFFFFFFFEC,
+           0xFFFFFFFFFFFFFFF0, 0xFFFFFFFFFFFFFFF4, 0xFFFFFFFFFFFFFFF8,
+           0xFFFFFFFFFFFFFFFC);
+  asm volatile("vsrl.vi v4, v2, 2");
+  VCMP_U64(20, v4, 0x0000000000000001, 0x0000000000000002, 0x0000000000000003,
+           0x0000000000000004, 0x0000000000000005, 0x0000000000000006,
+           0x0000000000000007, 0x0000000000000008, 0x3FFFFFFFFFFFFFF8,
+           0x3FFFFFFFFFFFFFF9, 0x3FFFFFFFFFFFFFFA, 0x3FFFFFFFFFFFFFFB,
+           0x3FFFFFFFFFFFFFFC, 0x3FFFFFFFFFFFFFFD, 0x3FFFFFFFFFFFFFFE,
+           0x3FFFFFFFFFFFFFFF);
+};
+
+void TEST_CASE6(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x04, 0x08, 0x0C, 0x10, 0x14, 0x18, 0x1C, 0x20, 0xE0, 0xE4, 0xE8,
+          0xEC, 0xF0, 0xF4, 0xF8, 0xFC);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vsrl.vi v4, v2, 2, v0.t");
+  VCMP_U8(21, v4, 0x00, 0x02, 0x00, 0x04, 0x00, 0x06, 0x00, 0x08, 0x00, 0x39,
+          0x00, 0x3B, 0x00, 0x3D, 0x00, 0x3F);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018, 0x001C, 0x0020,
+           0xFFE0, 0xFFE4, 0xFFE8, 0xFFEC, 0xFFF0, 0xFFF4, 0xFFF8, 0xFFFC);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vsrl.vi v4, v2, 2, v0.t");
+  VCMP_U16(22, v4, 0x0000, 0x0002, 0x0000, 0x0004, 0x0000, 0x0006, 0x0000,
+           0x0008, 0x0000, 0x3FF9, 0x0000, 0x3FFB, 0x0000, 0x3FFD, 0x0000,
+           0x3FFF);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x00000004, 0x00000008, 0x0000000C, 0x00000010, 0x00000014,
+           0x00000018, 0x0000001C, 0x00000020, 0xFFFFFFE0, 0xFFFFFFE4,
+           0xFFFFFFE8, 0xFFFFFFEC, 0xFFFFFFF0, 0xFFFFFFF4, 0xFFFFFFF8,
+           0xFFFFFFFC);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vsrl.vi v4, v2, 2, v0.t");
+  VCMP_U32(23, v4, 0x00000000, 0x00000002, 0x00000000, 0x00000004, 0x00000000,
+           0x00000006, 0x00000000, 0x00000008, 0x00000000, 0x3FFFFFF9,
+           0x00000000, 0x3FFFFFFB, 0x00000000, 0x3FFFFFFD, 0x00000000,
+           0x3FFFFFFF);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v2, 0x0000000000000004, 0x0000000000000008, 0x000000000000000C,
+           0x0000000000000010, 0x0000000000000014, 0x0000000000000018,
+           0x000000000000001C, 0x0000000000000020, 0xFFFFFFFFFFFFFFE0,
+           0xFFFFFFFFFFFFFFE4, 0xFFFFFFFFFFFFFFE8, 0xFFFFFFFFFFFFFFEC,
+           0xFFFFFFFFFFFFFFF0, 0xFFFFFFFFFFFFFFF4, 0xFFFFFFFFFFFFFFF8,
+           0xFFFFFFFFFFFFFFFC);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v4);
+  asm volatile("vsrl.vi v4, v2, 2, v0.t");
+  VCMP_U64(24, v4, 0x0000000000000000, 0x0000000000000002, 0x0000000000000000,
+           0x0000000000000004, 0x0000000000000000, 0x0000000000000006,
+           0x0000000000000000, 0x0000000000000008, 0x0000000000000000,
+           0x3FFFFFFFFFFFFFF9, 0x0000000000000000, 0x3FFFFFFFFFFFFFFB,
+           0x0000000000000000, 0x3FFFFFFFFFFFFFFD, 0x0000000000000000,
+           0x3FFFFFFFFFFFFFFF);
+};
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+  TEST_CASE6();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vss.c b/apps/riscv-tests/isa/rv64uv/vss.c
new file mode 100644
index 0000000..5f34498
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vss.c
@@ -0,0 +1,146 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+
+#include "vector_macros.h"
+
+// Positive-stride tests
+void TEST_CASE1(void) {
+  VSET(4, e8, m1);
+  volatile uint8_t OUT1[] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+                             0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
+  uint64_t stride = 3;
+  VLOAD_8(v1, 0x9f, 0xe4, 0x19, 0x20);
+  asm volatile("vsse8.v v1, (%0), %1" ::"r"(OUT1), "r"(stride));
+  VVCMP_U8(1, OUT1, 0x9f, 0x00, 0x00, 0xe4, 0x00, 0x00, 0x19, 0x00, 0x00, 0x20,
+           0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
+}
+
+void TEST_CASE2(void) {
+  VSET(8, e16, m1);
+  volatile uint16_t OUT1[] = {0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+                              0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+                              0x0000, 0x0000, 0x0000, 0x0000};
+  uint64_t stride = 4;
+  VLOAD_16(v1, 0x9f11, 0xe478, 0x1549, 0x3240, 0x2f11, 0xe448, 0x1546, 0x3220);
+  asm volatile("vsse16.v v1, (%0), %1" ::"r"(OUT1), "r"(stride));
+  VVCMP_U16(2, OUT1, 0x9f11, 0x0000, 0xe478, 0x0000, 0x1549, 0x0000, 0x3240,
+            0x0000, 0x2f11, 0x0000, 0xe448, 0x0000, 0x1546, 0x0000, 0x3220,
+            0x0000);
+}
+
+void TEST_CASE3(void) {
+  VSET(4, e32, m1);
+  volatile uint32_t OUT1[] = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
+                              0x00000000, 0x00000000, 0x00000000, 0x00000000,
+                              0x00000000, 0x00000000, 0x00000000, 0x00000000,
+                              0x00000000, 0x00000000, 0x00000000, 0x00000000};
+  uint64_t stride = 8;
+  VLOAD_32(v1, 0x9f872456, 0xe1356784, 0x13241139, 0x20862497);
+  asm volatile("vsse32.v v1, (%0), %1" ::"r"(OUT1), "r"(stride));
+  VVCMP_U32(3, OUT1, 0x9f872456, 0x00000000, 0xe1356784, 0x00000000, 0x13241139,
+            0x00000000, 0x20862497, 0x00000000, 0x00000000, 0x00000000,
+            0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+            0x00000000);
+}
+
+void TEST_CASE4(void) {
+  VSET(16, e64, m1);
+  volatile uint64_t OUT1[] = {
+      0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+      0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+      0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+      0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+      0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+      0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+      0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+      0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+      0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+      0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+      0x0000000000000000, 0x0000000000000000};
+  uint64_t stride = 16;
+  VLOAD_64(v1, 0x9f87245315434136, 0xe135578794246784, 0x1315345345241139,
+           0x2086252110062497, 0x1100229933847136, 0xaaffaaffaaffaaff,
+           0xaf87245315434136, 0xa135578794246784, 0x2315345345241139,
+           0x1086252110062497, 0x1100229933847134, 0xaaffaaffaaffaaf4,
+           0x9315345345241139, 0x9086252110062497, 0x9100229933847134,
+           0x9affaaffaaffaaf4);
+  asm volatile("vsse64.v v1, (%0), %1" ::"r"(OUT1), "r"(stride));
+  VVCMP_U64(4, OUT1, 0x9f87245315434136, 0x0000000000000000, 0xe135578794246784,
+            0x0000000000000000, 0x1315345345241139, 0x0000000000000000,
+            0x2086252110062497, 0x0000000000000000, 0x1100229933847136,
+            0x0000000000000000, 0xaaffaaffaaffaaff, 0x0000000000000000,
+            0xaf87245315434136, 0x0000000000000000, 0xa135578794246784,
+            0x0000000000000000, 0x2315345345241139, 0x0000000000000000,
+            0x1086252110062497, 0x0000000000000000, 0x1100229933847134,
+            0x0000000000000000, 0xaaffaaffaaffaaf4, 0x0000000000000000,
+            0x9315345345241139, 0x0000000000000000, 0x9086252110062497,
+            0x0000000000000000, 0x9100229933847134, 0x0000000000000000,
+            0x9affaaffaaffaaf4, 0x0000000000000000);
+}
+
+// Masked strided store
+void TEST_CASE5(void) {
+  VSET(4, e8, m1);
+  volatile uint8_t OUT1[] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+                             0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
+  uint64_t stride = 3;
+  VLOAD_8(v0, 0xAA);
+  VLOAD_8(v1, 0x9f, 0xe4, 0x19, 0x20);
+  asm volatile("vsse8.v v1, (%0), %1, v0.t" ::"r"(OUT1), "r"(stride));
+  VVCMP_U8(5, OUT1, 0x00, 0x00, 0x00, 0xe4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
+           0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
+}
+
+void TEST_CASE6(void) {
+  VSET(16, e64, m1);
+  volatile uint64_t OUT1[] = {
+      0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+      0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+      0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+      0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+      0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+      0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+      0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+      0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+      0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+      0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+      0x0000000000000000, 0x0000000000000000};
+  uint64_t stride = 16;
+  VLOAD_64(v1, 0x9f87245315434136, 0xe135578794246784, 0x1315345345241139,
+           0x2086252110062497, 0x1100229933847136, 0xaaffaaffaaffaaff,
+           0xaf87245315434136, 0xa135578794246784, 0x2315345345241139,
+           0x1086252110062497, 0x1100229933847134, 0xaaffaaffaaffaaf4,
+           0x9315345345241139, 0x9086252110062497, 0x9100229933847134,
+           0x9affaaffaaffaaf4);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vsse64.v v1, (%0), %1, v0.t" ::"r"(OUT1), "r"(stride));
+  VVCMP_U64(6, OUT1, 0x0000000000000000, 0x0000000000000000, 0xe135578794246784,
+            0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+            0x2086252110062497, 0x0000000000000000, 0x0000000000000000,
+            0x0000000000000000, 0xaaffaaffaaffaaff, 0x0000000000000000,
+            0x0000000000000000, 0x0000000000000000, 0xa135578794246784,
+            0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+            0x1086252110062497, 0x0000000000000000, 0x0000000000000000,
+            0x0000000000000000, 0xaaffaaffaaffaaf4, 0x0000000000000000,
+            0x0000000000000000, 0x0000000000000000, 0x9086252110062497,
+            0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+            0x9affaaffaaffaaf4, 0x0000000000000000);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  TEST_CASE5();
+  TEST_CASE6();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vsseg.c b/apps/riscv-tests/isa/rv64uv/vsseg.c
new file mode 100644
index 0000000..259f59e
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vsseg.c
@@ -0,0 +1,407 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+
+#include "vector_macros.h"
+
+#define AXI_DWIDTH_MAX 512
+#define MEM_VEC_SIZE 16
+
+#define MEM_VCLEAR(vec)                                                        \
+  {                                                                            \
+    for (int i = 0; i < MEM_VEC_SIZE; ++i)                                     \
+      vec[i] = 0;                                                              \
+  }
+
+static volatile uint8_t ALIGNED_O8[MEM_VEC_SIZE]
+    __attribute__((aligned(AXI_DWIDTH_MAX))) = {
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
+
+static volatile uint16_t ALIGNED_O16[MEM_VEC_SIZE]
+    __attribute__((aligned(AXI_DWIDTH_MAX))) = {
+        0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+        0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000};
+
+static volatile uint32_t ALIGNED_O32[MEM_VEC_SIZE]
+    __attribute__((aligned(AXI_DWIDTH_MAX))) = {
+        0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+        0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+        0x00000000, 0x00000000, 0x00000000, 0x00000000};
+
+static volatile uint64_t ALIGNED_O64[MEM_VEC_SIZE]
+    __attribute__((aligned(AXI_DWIDTH_MAX))) = {
+        0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+        0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+        0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+        0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+        0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+        0x0000000000000000};
+
+// Segment-2
+void TEST_CASE1_8(void) {
+  VSET(4, e8, m1);
+  volatile uint8_t INP1[] = {0x9f, 0xe4, 0x19, 0x20, 0x8f, 0x2e, 0x05, 0xe0,
+                             0xf9, 0xaa, 0x71, 0xf0, 0xc3, 0x94, 0xbb, 0xd3};
+  VCLEAR(v1);
+  VCLEAR(v2);
+  asm volatile("vlseg2e8.v v1, (%0)" ::"r"(INP1));
+  asm volatile("vsseg2e8.v v1, (%0)" ::"r"(ALIGNED_O8));
+  VVCMP_U8(1, ALIGNED_O8, 0x9f, 0xe4, 0x19, 0x20, 0x8f, 0x2e, 0x05, 0xe0);
+}
+
+// Segment-3
+void TEST_CASE2_8(void) {
+  VSET(4, e8, m1);
+  volatile uint8_t INP1[] = {0x9f, 0xe4, 0x19, 0x20, 0x8f, 0x2e, 0x05, 0xe0,
+                             0xf9, 0xaa, 0x71, 0xf0, 0xc3, 0x94, 0xbb, 0xd3};
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  asm volatile("vlseg3e8.v v1, (%0)" ::"r"(INP1));
+  asm volatile("vsseg3e8.v v1, (%0)" ::"r"(ALIGNED_O8));
+  VVCMP_U8(2, ALIGNED_O8, 0x9f, 0xe4, 0x19, 0x20, 0x8f, 0x2e, 0x05, 0xe0, 0xf9,
+           0xaa, 0x71, 0xf0);
+}
+
+// Segment-4
+void TEST_CASE3_8(void) {
+  VSET(4, e8, m1);
+  volatile uint8_t INP1[] = {0x9f, 0xe4, 0x19, 0x20, 0x8f, 0x2e, 0x05, 0xe0,
+                             0xf9, 0xaa, 0x71, 0xf0, 0xc3, 0x94, 0xbb, 0xd3};
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  asm volatile("vlseg4e8.v v1, (%0)" ::"r"(INP1));
+  asm volatile("vsseg4e8.v v1, (%0)" ::"r"(ALIGNED_O8));
+  VVCMP_U8(3, ALIGNED_O8, 0x9f, 0xe4, 0x19, 0x20, 0x8f, 0x2e, 0x05, 0xe0, 0xf9,
+           0xaa, 0x71, 0xf0, 0xc3, 0x94, 0xbb, 0xd3);
+}
+
+// Segment-8
+void TEST_CASE4_8(void) {
+  VSET(2, e8, m1);
+  volatile uint8_t INP1[] = {0x9f, 0xe4, 0x19, 0x20, 0x8f, 0x2e, 0x05, 0xe0,
+                             0xf9, 0xaa, 0x71, 0xf0, 0xc3, 0x94, 0xbb, 0xd3};
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  VCLEAR(v5);
+  VCLEAR(v6);
+  VCLEAR(v7);
+  VCLEAR(v8);
+  asm volatile("vlseg8e8.v v1, (%0)" ::"r"(INP1));
+  asm volatile("vsseg8e8.v v1, (%0)" ::"r"(ALIGNED_O8));
+  VVCMP_U8(4, ALIGNED_O8, 0x9f, 0xe4, 0x19, 0x20, 0x8f, 0x2e, 0x05, 0xe0, 0xf9,
+           0xaa, 0x71, 0xf0, 0xc3, 0x94, 0xbb, 0xd3);
+}
+
+// Segment-2 for 16-bit
+void TEST_CASE1_16(void) {
+  VSET(4, e16, m1);
+  volatile uint16_t INP1[] = {0x9fe4, 0x1920, 0x8f2e, 0x05e0, 0xf9aa, 0x71f0,
+                              0xc394, 0xbbd3, 0x1234, 0x5678, 0x9abc, 0xdef0,
+                              0x1357, 0x2468, 0x369b, 0x48ac};
+  VCLEAR(v1);
+  VCLEAR(v2);
+  asm volatile("vlseg2e16.v v1, (%0)" ::"r"(INP1));
+  asm volatile("vsseg2e16.v v1, (%0)" ::"r"(ALIGNED_O16));
+  VVCMP_U16(5, ALIGNED_O16, 0x9fe4, 0x1920, 0x8f2e, 0x05e0, 0xf9aa, 0x71f0,
+            0xc394, 0xbbd3);
+}
+
+// Segment-3 for 16-bit
+void TEST_CASE2_16(void) {
+  VSET(4, e16, m1);
+  volatile uint16_t INP1[] = {0x9fe4, 0x1920, 0x8f2e, 0x05e0, 0xf9aa, 0x71f0,
+                              0xc394, 0xbbd3, 0x1234, 0x5678, 0x9abc, 0xdef0,
+                              0x1357, 0x2468, 0x369b, 0x48ac};
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  asm volatile("vlseg3e16.v v1, (%0)" ::"r"(INP1));
+  asm volatile("vsseg3e16.v v1, (%0)" ::"r"(ALIGNED_O16));
+  VVCMP_U16(6, ALIGNED_O16, 0x9fe4, 0x1920, 0x8f2e, 0x05e0, 0xf9aa, 0x71f0,
+            0xc394, 0xbbd3, 0x1234, 0x5678, 0x9abc, 0xdef0);
+}
+
+// Segment-4 for 16-bit
+void TEST_CASE3_16(void) {
+  VSET(4, e16, m1);
+  volatile uint16_t INP1[] = {0x9fe4, 0x1920, 0x8f2e, 0x05e0, 0xf9aa, 0x71f0,
+                              0xc394, 0xbbd3, 0x1234, 0x5678, 0x9abc, 0xdef0,
+                              0x1357, 0x2468, 0x369b, 0x48ac};
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  asm volatile("vlseg4e16.v v1, (%0)" ::"r"(INP1));
+  asm volatile("vsseg4e16.v v1, (%0)" ::"r"(ALIGNED_O16));
+  VVCMP_U16(7, ALIGNED_O16, 0x9fe4, 0x1920, 0x8f2e, 0x05e0, 0xf9aa, 0x71f0,
+            0xc394, 0xbbd3, 0x1234, 0x5678, 0x9abc, 0xdef0, 0x1357, 0x2468,
+            0x369b, 0x48ac);
+}
+
+// Segment-8 for 16-bit
+void TEST_CASE4_16(void) {
+  VSET(2, e16, m1);
+  volatile uint16_t INP1[] = {0x9fe4, 0x1920, 0x8f2e, 0x05e0, 0xf9aa, 0x71f0,
+                              0xc394, 0xbbd3, 0x1234, 0x5678, 0x9abc, 0xdef0,
+                              0x1357, 0x2468, 0x369b, 0x48ac};
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  VCLEAR(v5);
+  VCLEAR(v6);
+  VCLEAR(v7);
+  VCLEAR(v8);
+  asm volatile("vlseg8e16.v v1, (%0)" ::"r"(INP1));
+  asm volatile("vsseg8e16.v v1, (%0)" ::"r"(ALIGNED_O16));
+  VVCMP_U16(8, ALIGNED_O16, 0x9fe4, 0x1920, 0x8f2e, 0x05e0, 0xf9aa, 0x71f0,
+            0xc394, 0xbbd3, 0x1234, 0x5678, 0x9abc, 0xdef0, 0x1357, 0x2468,
+            0x369b, 0x48ac);
+}
+
+// Segment-2 for 32-bit
+void TEST_CASE1_32(void) {
+  VSET(4, e32, m1);
+  volatile uint32_t INP1[] = {0x9fe41920, 0x8f2e05e0, 0xf9aa71f0, 0xc394bbd3,
+                              0x12345678, 0x9abcdef0, 0x13572468, 0x369b48ac,
+                              0xdeadbeef, 0xcafebabe, 0x01234567, 0x89abcdef,
+                              0x55aa55aa, 0x77889900, 0xabcdef12, 0x34567890};
+  VCLEAR(v1);
+  VCLEAR(v2);
+  asm volatile("vlseg2e32.v v1, (%0)" ::"r"(INP1));
+  asm volatile("vsseg2e32.v v1, (%0)" ::"r"(ALIGNED_O32));
+  VVCMP_U32(9, ALIGNED_O32, 0x9fe41920, 0x8f2e05e0, 0xf9aa71f0, 0xc394bbd3,
+            0x12345678, 0x9abcdef0, 0x13572468, 0x369b48ac);
+}
+
+// Segment-3 for 32-bit
+void TEST_CASE2_32(void) {
+  VSET(4, e32, m1);
+  volatile uint32_t INP1[] = {0x9fe41920, 0x8f2e05e0, 0xf9aa71f0, 0xc394bbd3,
+                              0x12345678, 0x9abcdef0, 0x13572468, 0x369b48ac,
+                              0xdeadbeef, 0xcafebabe, 0x01234567, 0x89abcdef,
+                              0x55aa55aa, 0x77889900, 0xabcdef12, 0x34567890};
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  asm volatile("vlseg3e32.v v1, (%0)" ::"r"(INP1));
+  asm volatile("vsseg3e32.v v1, (%0)" ::"r"(ALIGNED_O32));
+  VVCMP_U32(10, ALIGNED_O32, 0x9fe41920, 0x8f2e05e0, 0xf9aa71f0, 0xc394bbd3,
+            0x12345678, 0x9abcdef0, 0x13572468, 0x369b48ac, 0xdeadbeef,
+            0xcafebabe, 0x01234567, 0x89abcdef);
+}
+
+// Segment-4 for 32-bit
+void TEST_CASE3_32(void) {
+  VSET(4, e32, m1);
+  volatile uint32_t INP1[] = {0x9fe41920, 0x8f2e05e0, 0xf9aa71f0, 0xc394bbd3,
+                              0x12345678, 0x9abcdef0, 0x13572468, 0x369b48ac,
+                              0xdeadbeef, 0xcafebabe, 0x01234567, 0x89abcdef,
+                              0x55aa55aa, 0x77889900, 0xabcdef12, 0x34567890};
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  asm volatile("vlseg4e32.v v1, (%0)" ::"r"(INP1));
+  asm volatile("vsseg4e32.v v1, (%0)" ::"r"(ALIGNED_O32));
+  VVCMP_U32(11, ALIGNED_O32, 0x9fe41920, 0x8f2e05e0, 0xf9aa71f0, 0xc394bbd3,
+            0x12345678, 0x9abcdef0, 0x13572468, 0x369b48ac, 0xdeadbeef,
+            0xcafebabe, 0x01234567, 0x89abcdef, 0x55aa55aa, 0x77889900,
+            0xabcdef12, 0x34567890);
+}
+
+// Segment-8 for 32-bit
+void TEST_CASE4_32(void) {
+  VSET(2, e32, m1);
+  volatile uint32_t INP1[] = {0x9fe41920, 0x8f2e05e0, 0xf9aa71f0, 0xc394bbd3,
+                              0x12345678, 0x9abcdef0, 0x13572468, 0x369b48ac,
+                              0xdeadbeef, 0xcafebabe, 0x01234567, 0x89abcdef,
+                              0x55aa55aa, 0x77889900, 0xabcdef12, 0x34567890};
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  VCLEAR(v5);
+  VCLEAR(v6);
+  VCLEAR(v7);
+  VCLEAR(v8);
+  asm volatile("vlseg8e32.v v1, (%0)" ::"r"(INP1));
+  asm volatile("vsseg8e32.v v1, (%0)" ::"r"(ALIGNED_O32));
+  VVCMP_U32(12, ALIGNED_O32, 0x9fe41920, 0x8f2e05e0, 0xf9aa71f0, 0xc394bbd3,
+            0x12345678, 0x9abcdef0, 0x13572468, 0x369b48ac, 0xdeadbeef,
+            0xcafebabe, 0x01234567, 0x89abcdef, 0x55aa55aa, 0x77889900,
+            0xabcdef12, 0x34567890);
+}
+
+// Segment-2 for 64-bit
+void TEST_CASE1_64(void) {
+  VSET(4, e64, m1);
+  volatile uint64_t INP1[] = {
+      0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3, 0x123456789abcdef0,
+      0x13572468369b48ac, 0xdeadbeefcafebabe, 0x0123456789abcdef,
+      0x55aa55aa77889900, 0xabcdef1234567890, 0xfeedfacecafebabe,
+      0x123456789abcdef0, 0x1357246855aa55aa, 0x369b48acdeadbeef,
+      0xcafebabe12345678, 0xabcdef0987654321, 0x012345670abcdef1,
+      0x987654321fedcba0};
+  VCLEAR(v1);
+  VCLEAR(v2);
+  asm volatile("vlseg2e64.v v1, (%0)" ::"r"(INP1));
+  asm volatile("vsseg2e64.v v1, (%0)" ::"r"(ALIGNED_O64));
+  VVCMP_U64(13, ALIGNED_O64, 0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3,
+            0x123456789abcdef0, 0x13572468369b48ac);
+}
+
+// Segment-3 for 64-bit
+void TEST_CASE2_64(void) {
+  VSET(4, e64, m1);
+  volatile uint64_t INP1[] = {
+      0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3, 0x123456789abcdef0,
+      0x13572468369b48ac, 0xdeadbeefcafebabe, 0x0123456789abcdef,
+      0x55aa55aa77889900, 0xabcdef1234567890, 0xfeedfacecafebabe,
+      0x123456789abcdef0, 0x1357246855aa55aa, 0x369b48acdeadbeef,
+      0xcafebabe12345678, 0xabcdef0987654321, 0x012345670abcdef1,
+      0x987654321fedcba0};
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  asm volatile("vlseg3e64.v v1, (%0)" ::"r"(INP1));
+  asm volatile("vsseg3e64.v v1, (%0)" ::"r"(ALIGNED_O64));
+  VVCMP_U64(14, ALIGNED_O64, 0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3,
+            0x123456789abcdef0, 0x13572468369b48ac, 0xdeadbeefcafebabe,
+            0x0123456789abcdef, 0x55aa55aa77889900, 0xabcdef1234567890);
+}
+
+// Segment-4 for 64-bit
+void TEST_CASE3_64(void) {
+  VSET(4, e64, m1);
+  volatile uint64_t INP1[] = {
+      0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3, 0x123456789abcdef0,
+      0x13572468369b48ac, 0xdeadbeefcafebabe, 0x0123456789abcdef,
+      0x55aa55aa77889900, 0xabcdef1234567890, 0xfeedfacecafebabe,
+      0x123456789abcdef0, 0x1357246855aa55aa, 0x369b48acdeadbeef,
+      0xcafebabe12345678, 0xabcdef0987654321, 0x012345670abcdef1,
+      0x987654321fedcba0};
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  asm volatile("vlseg4e64.v v1, (%0)" ::"r"(INP1));
+  asm volatile("vsseg4e64.v v1, (%0)" ::"r"(ALIGNED_O64));
+  VVCMP_U64(15, ALIGNED_O64, 0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3,
+            0x123456789abcdef0, 0x13572468369b48ac, 0xdeadbeefcafebabe,
+            0x0123456789abcdef, 0x55aa55aa77889900, 0xabcdef1234567890,
+            0xfeedfacecafebabe, 0x123456789abcdef0, 0x1357246855aa55aa,
+            0x369b48acdeadbeef, 0xcafebabe12345678, 0xabcdef0987654321,
+            0x012345670abcdef1, 0x987654321fedcba0);
+}
+
+// Segment-8 for 64-bit
+void TEST_CASE4_64(void) {
+  VSET(2, e64, m1);
+  volatile uint64_t INP1[] = {
+      0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3, 0x123456789abcdef0,
+      0x13572468369b48ac, 0xdeadbeefcafebabe, 0x0123456789abcdef,
+      0x55aa55aa77889900, 0xabcdef1234567890, 0xfeedfacecafebabe,
+      0x123456789abcdef0, 0x1357246855aa55aa, 0x369b48acdeadbeef,
+      0xcafebabe12345678, 0xabcdef0987654321, 0x012345670abcdef1,
+      0x987654321fedcba0};
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  VCLEAR(v5);
+  VCLEAR(v6);
+  VCLEAR(v7);
+  VCLEAR(v8);
+  asm volatile("vlseg8e64.v v1, (%0)" ::"r"(INP1));
+  asm volatile("vsseg8e64.v v1, (%0)" ::"r"(ALIGNED_O64));
+  VVCMP_U64(16, ALIGNED_O64, 0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3,
+            0x123456789abcdef0, 0x13572468369b48ac, 0xdeadbeefcafebabe,
+            0x0123456789abcdef, 0x55aa55aa77889900, 0xabcdef1234567890,
+            0xfeedfacecafebabe, 0x123456789abcdef0, 0x1357246855aa55aa,
+            0x369b48acdeadbeef, 0xcafebabe12345678, 0xabcdef0987654321,
+            0x012345670abcdef1, 0x987654321fedcba0);
+}
+
+// Segment-8 for 64-bit
+void TEST_CASE4_64_m(void) {
+  VSET(2, e64, m1);
+  volatile uint64_t INP1[] = {
+      0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3, 0x123456789abcdef0,
+      0x13572468369b48ac, 0xdeadbeefcafebabe, 0x0123456789abcdef,
+      0x55aa55aa77889900, 0xabcdef1234567890, 0xfeedfacecafebabe,
+      0x123456789abcdef0, 0x1357246855aa55aa, 0x369b48acdeadbeef,
+      0xcafebabe12345678, 0xabcdef0987654321, 0x012345670abcdef1,
+      0x987654321fedcba0};
+
+  VCLEAR(v0);
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  VCLEAR(v5);
+  VCLEAR(v6);
+  VCLEAR(v7);
+  VCLEAR(v8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vlseg8e64.v v1, (%0)" ::"r"(INP1));
+  asm volatile("vsseg8e64.v v1, (%0), v0.t" ::"r"(ALIGNED_O64));
+  VVCMP_U64(17, ALIGNED_O64, 0, 0, 0, 0, 0, 0, 0, 0, 0xfeedfacecafebabe,
+            0x123456789abcdef0, 0x1357246855aa55aa, 0x369b48acdeadbeef,
+            0xcafebabe12345678, 0xabcdef0987654321, 0x012345670abcdef1,
+            0x987654321fedcba0);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1_8();
+  MEM_VCLEAR(ALIGNED_O8);
+  TEST_CASE2_8();
+  MEM_VCLEAR(ALIGNED_O8);
+  TEST_CASE3_8();
+  MEM_VCLEAR(ALIGNED_O8);
+  TEST_CASE4_8();
+  MEM_VCLEAR(ALIGNED_O8);
+
+  TEST_CASE1_16();
+  MEM_VCLEAR(ALIGNED_O16);
+  TEST_CASE2_16();
+  MEM_VCLEAR(ALIGNED_O16);
+  TEST_CASE3_16();
+  MEM_VCLEAR(ALIGNED_O16);
+  TEST_CASE4_16();
+  MEM_VCLEAR(ALIGNED_O16);
+
+  TEST_CASE1_32();
+  MEM_VCLEAR(ALIGNED_O32);
+  TEST_CASE2_32();
+  MEM_VCLEAR(ALIGNED_O32);
+  TEST_CASE3_32();
+  MEM_VCLEAR(ALIGNED_O32);
+  TEST_CASE4_32();
+  MEM_VCLEAR(ALIGNED_O32);
+
+  TEST_CASE1_64();
+  MEM_VCLEAR(ALIGNED_O64);
+  TEST_CASE2_64();
+  MEM_VCLEAR(ALIGNED_O64);
+  TEST_CASE3_64();
+  MEM_VCLEAR(ALIGNED_O64);
+  TEST_CASE4_64();
+  MEM_VCLEAR(ALIGNED_O64);
+
+  TEST_CASE4_64_m();
+  MEM_VCLEAR(ALIGNED_O64);
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vssra.c b/apps/riscv-tests/isa/rv64uv/vssra.c
new file mode 100644
index 0000000..a21d6aa
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vssra.c
@@ -0,0 +1,79 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1() {
+  VSET(4, e8, m1);
+  VLOAD_8(v2, 0xff, 0x00, 0xf0, 0x0f);
+  VLOAD_8(v3, 1, 2, 3, 4);
+  __asm__ volatile("csrw vxrm, 2");
+  __asm__ volatile("vssra.vv v1, v2, v3");
+  VCMP_I8(1, v1, 0xff, 0, 0xfe, 0);
+}
+
+void TEST_CASE2() {
+  VSET(4, e8, m1);
+  VLOAD_8(v2, 0xff, 0x00, 0xf0, 0x0f);
+  VLOAD_8(v3, 1, 2, 3, 4);
+  VLOAD_8(v0, 5, 0, 0, 0);
+  VCLEAR(v1);
+  __asm__ volatile("csrw vxrm, 2");
+  __asm__ volatile("vssra.vv v1, v2, v3, v0.t");
+  VCMP_I8(2, v1, 0xff, 0, 0xfe, 0);
+}
+
+void TEST_CASE3() {
+  VSET(4, e8, m1);
+  VLOAD_8(v2, 0xff, 0x00, 0xf0, 0x0f);
+  __asm__ volatile("csrw vxrm, 2");
+  __asm__ volatile("vssra.vi v1, v2, 2");
+  VCMP_I8(3, v1, 0xff, 0, 0xfc, 3);
+}
+
+void TEST_CASE4() {
+  VSET(4, e8, m1);
+  VLOAD_8(v2, 0xff, 0x00, 0xf0, 0x0f);
+  VLOAD_8(v0, 5, 0, 0, 0);
+  VCLEAR(v1);
+  __asm__ volatile("csrw vxrm, 2");
+  __asm__ volatile("vssra.vi v1, v2, 2, v0.t");
+  VCMP_I8(4, v1, 0xff, 0, 0xfc, 0);
+}
+
+void TEST_CASE5() {
+  VSET(4, e8, m1);
+  VLOAD_8(v2, 0xff, 0x00, 0xf0, 0x0f);
+  uint64_t scalar = 2;
+  __asm__ volatile("csrw vxrm, 2");
+  __asm__ volatile("vssra.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_I8(5, v1, 0xff, 0, 0xfc, 3);
+}
+
+void TEST_CASE6() {
+  VSET(4, e8, m1);
+  VLOAD_8(v2, 0xff, 0x00, 0xf0, 0x0f);
+  uint64_t scalar = 2;
+  VLOAD_8(v0, 5, 0, 0, 0);
+  VCLEAR(v1);
+  __asm__ volatile("csrw vxrm, 2");
+  __asm__ volatile("vssra.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_I8(6, v1, 0xff, 0, 0xfc, 0);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+  enable_fp();
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+  TEST_CASE6();
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vssrl.c b/apps/riscv-tests/isa/rv64uv/vssrl.c
new file mode 100644
index 0000000..de73e9f
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vssrl.c
@@ -0,0 +1,79 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1() {
+  VSET(4, e8, m1);
+  VLOAD_8(v2, 0xff, 0x00, 0xf0, 0x0f);
+  VLOAD_8(v3, 1, 2, 3, 4);
+  __asm__ volatile("csrw vxrm, 2");
+  __asm__ volatile("vssrl.vv v1, v2, v3");
+  VCMP_U8(1, v1, 0x7f, 0, 0x1e, 0x00);
+}
+
+void TEST_CASE2() {
+  VSET(4, e8, m1);
+  VLOAD_8(v2, 0xff, 0x00, 0xf0, 0x0f);
+  VLOAD_8(v3, 1, 2, 3, 4);
+  VLOAD_8(v0, 5, 0, 0, 0);
+  VCLEAR(v1);
+  __asm__ volatile("csrw vxrm, 2");
+  __asm__ volatile("vssrl.vv v1, v2, v3, v0.t");
+  VCMP_U8(2, v1, 0x7f, 0, 0x1e, 0);
+}
+
+void TEST_CASE3() {
+  VSET(4, e8, m1);
+  VLOAD_8(v2, 0xff, 0x00, 0xf0, 0x0f);
+  __asm__ volatile("csrw vxrm, 2");
+  __asm__ volatile("vssrl.vi v1, v2, 5");
+  VCMP_U8(3, v1, 7, 0, 7, 0);
+}
+
+void TEST_CASE4() {
+  VSET(4, e8, m1);
+  VLOAD_8(v2, 0xff, 0x00, 0xf0, 0x0f);
+  VLOAD_8(v0, 5, 0, 0, 0);
+  VCLEAR(v1);
+  __asm__ volatile("csrw vxrm, 2");
+  __asm__ volatile("vssrl.vi v1, v2, 5, v0.t");
+  VCMP_U8(4, v1, 7, 0, 7, 0);
+}
+
+void TEST_CASE5() {
+  VSET(4, e8, m1);
+  VLOAD_8(v2, 0xff, 0x00, 0xf0, 0x0f);
+  uint64_t scalar = 5;
+  __asm__ volatile("csrw vxrm, 2");
+  __asm__ volatile("vssrl.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U8(5, v1, 7, 0, 7, 0);
+}
+
+void TEST_CASE6() {
+  VSET(4, e8, m1);
+  VLOAD_8(v2, 0xff, 0x00, 0xf0, 0x0f);
+  uint64_t scalar = 5;
+  VLOAD_8(v0, 5, 0, 0, 0);
+  VCLEAR(v1);
+  __asm__ volatile("csrw vxrm, 2");
+  __asm__ volatile("vssrl.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U8(6, v1, 7, 0, 7, 0);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+  enable_fp();
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+  TEST_CASE6();
+  EXIT_CHECK();
+}
\ No newline at end of file
diff --git a/apps/riscv-tests/isa/rv64uv/vssseg.c b/apps/riscv-tests/isa/rv64uv/vssseg.c
new file mode 100644
index 0000000..9352474
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vssseg.c
@@ -0,0 +1,425 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+
+#include "vector_macros.h"
+
+#define AXI_DWIDTH_MAX 512
+#define MEM_VEC_SIZE 64
+
+#define MEM_VCLEAR(vec)                                                        \
+  {                                                                            \
+    for (int i = 0; i < MEM_VEC_SIZE; ++i)                                     \
+      vec[i] = 0;                                                              \
+  }
+
+static volatile uint8_t ALIGNED_O8[MEM_VEC_SIZE]
+    __attribute__((aligned(AXI_DWIDTH_MAX))) = {
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
+
+static volatile uint16_t ALIGNED_O16[MEM_VEC_SIZE]
+    __attribute__((aligned(AXI_DWIDTH_MAX))) = {
+        0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+        0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000};
+
+static volatile uint32_t ALIGNED_O32[MEM_VEC_SIZE]
+    __attribute__((aligned(AXI_DWIDTH_MAX))) = {
+        0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+        0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+        0x00000000, 0x00000000, 0x00000000, 0x00000000};
+
+static volatile uint64_t ALIGNED_O64[MEM_VEC_SIZE]
+    __attribute__((aligned(AXI_DWIDTH_MAX))) = {
+        0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+        0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+        0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+        0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+        0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+        0x0000000000000000};
+
+int stride;
+
+// Segment-2
+void TEST_CASE1_8(void) {
+
+  VSET(-1, e8, m1);
+  volatile uint8_t INP1[] = {
+      0x9f, 0xe4, 0x19, 0x20, 0x8f, 0x2e, 0x05, 0xe0, 0xf9, 0xaa, 0x71,
+      0xf0, 0xc3, 0x94, 0xbb, 0xd3, 0x31, 0x4a, 0x57, 0x6b, 0x83, 0x7d,
+      0x1a, 0x45, 0xb2, 0xda, 0x22, 0x56, 0x63, 0x8c, 0xf7, 0x3e, 0x6c,
+      0x27, 0x74, 0x9d, 0xab, 0xcd, 0x13, 0x38, 0x5e, 0x42, 0xdf, 0x80,
+      0x60, 0xa4, 0x7b, 0x0b, 0xc6, 0xad, 0x91, 0xec, 0x3c, 0x69, 0xf5,
+      0x18, 0xe8, 0x6d, 0xb9, 0x82, 0x97, 0x2a, 0x51, 0x70};
+  VCLEAR(v1);
+  VCLEAR(v2);
+  stride = 0;
+  VSET(5, e8, m1);
+  asm volatile("vlsseg2e8.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  asm volatile("vssseg2e8.v v1, (%0), %1" ::"r"(ALIGNED_O8), "r"(stride));
+  VVCMP_U8(1, ALIGNED_O8, 0x9f, 0xe4, 0, 0, 0, 0, 0, 0);
+
+  MEM_VCLEAR(ALIGNED_O8);
+  VCLEAR(v1);
+  VCLEAR(v2);
+  stride = 2;
+  VSET(32, e8, m1);
+  asm volatile("vlsseg2e8.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  asm volatile("vssseg2e8.v v1, (%0), %1" ::"r"(ALIGNED_O8), "r"(stride));
+  VVCMP_U8(2, ALIGNED_O8, 0x9f, 0xe4, 0x19, 0x20, 0x8f, 0x2e, 0x05, 0xe0, 0xf9,
+           0xaa, 0x71, 0xf0, 0xc3, 0x94, 0xbb, 0xd3, 0x31, 0x4a, 0x57, 0x6b,
+           0x83, 0x7d, 0x1a, 0x45, 0xb2, 0xda, 0x22, 0x56, 0x63, 0x8c, 0xf7,
+           0x3e, 0x6c, 0x27, 0x74, 0x9d, 0xab, 0xcd, 0x13, 0x38, 0x5e, 0x42,
+           0xdf, 0x80, 0x60, 0xa4, 0x7b, 0x0b, 0xc6, 0xad, 0x91, 0xec, 0x3c,
+           0x69, 0xf5, 0x18, 0xe8, 0x6d, 0xb9, 0x82, 0x97, 0x2a, 0x51, 0x70);
+
+  MEM_VCLEAR(ALIGNED_O8);
+  VCLEAR(v1);
+  VCLEAR(v2);
+  stride = 3;
+  VSET(22, e8, m1);
+  asm volatile("vlsseg2e8.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  asm volatile("vssseg2e8.v v1, (%0), %1" ::"r"(ALIGNED_O8), "r"(stride));
+  VVCMP_U8(3, ALIGNED_O8, 0x9f, 0xe4, 0, 0x20, 0x8f, 0, 0x05, 0xe0, 0, 0xaa,
+           0x71, 0, 0xc3, 0x94, 0, 0xd3, 0x31, 0, 0x57, 0x6b, 0, 0x7d, 0x1a, 0,
+           0xb2, 0xda, 0, 0x56, 0x63, 0, 0xf7, 0x3e, 0, 0x27, 0x74, 0, 0xab,
+           0xcd, 0, 0x38, 0x5e, 0, 0xdf, 0x80, 0, 0xa4, 0x7b, 0, 0xc6, 0xad, 0,
+           0xec, 0x3c, 0, 0xf5, 0x18, 0, 0x6d, 0xb9, 0, 0x97, 0x2a, 0, 0x70);
+}
+
+// Segment-3
+void TEST_CASE2_8(void) {
+  VSET(-1, e8, m1);
+  volatile uint8_t INP1[] = {
+      0x9f, 0xe4, 0x19, 0x20, 0x8f, 0x2e, 0x05, 0xe0, 0xf9, 0xaa, 0x71,
+      0xf0, 0xc3, 0x94, 0xbb, 0xd3, 0x31, 0x4a, 0x57, 0x6b, 0x83, 0x7d,
+      0x1a, 0x45, 0xb2, 0xda, 0x22, 0x56, 0x63, 0x8c, 0xf7, 0x3e, 0x6c,
+      0x27, 0x74, 0x9d, 0xab, 0xcd, 0x13, 0x38, 0x5e, 0x42, 0xdf, 0x80,
+      0x60, 0xa4, 0x7b, 0x0b, 0xc6, 0xad, 0x91, 0xec, 0x3c, 0x69, 0xf5,
+      0x18, 0xe8, 0x6d, 0xb9, 0x82, 0x97, 0x2a, 0x51, 0x70};
+
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  stride = 3;
+  VSET(22, e8, m1);
+  asm volatile("vlsseg3e8.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  asm volatile("vssseg3e8.v v1, (%0), %1" ::"r"(ALIGNED_O8), "r"(stride));
+  VVCMP_U8(4, ALIGNED_O8, 0x9f, 0xe4, 0x19, 0x20, 0x8f, 0x2e, 0x05, 0xe0, 0xf9,
+           0xaa, 0x71, 0xf0, 0xc3, 0x94, 0xbb, 0xd3, 0x31, 0x4a, 0x57, 0x6b,
+           0x83, 0x7d, 0x1a, 0x45, 0xb2, 0xda, 0x22, 0x56, 0x63, 0x8c, 0xf7,
+           0x3e, 0x6c, 0x27, 0x74, 0x9d, 0xab, 0xcd, 0x13, 0x38, 0x5e, 0x42,
+           0xdf, 0x80, 0x60, 0xa4, 0x7b, 0x0b, 0xc6, 0xad, 0x91, 0xec, 0x3c,
+           0x69, 0xf5, 0x18, 0xe8, 0x6d, 0xb9, 0x82, 0x97, 0x2a, 0x51, 0x70);
+}
+
+// Segment-8
+void TEST_CASE4_16(void) {
+  VSET(-1, e16, m1);
+  volatile uint16_t INP1[] = {
+      0x1234, 0x5678, 0x9abc, 0xdef0, 0x1111, 0x2222, 0x3333, 0x4444,
+      0x5555, 0x6666, 0x7777, 0x8888, 0x9999, 0xaaaa, 0xbbbb, 0xcccc,
+      0xdddd, 0xeeee, 0xffff, 0x0101, 0x0202, 0x0303, 0x0404, 0x0505,
+      0x0606, 0x0707, 0x0808, 0x0909, 0x0a0a, 0x0b0b, 0x0c0c, 0x0d0d,
+      0x0e0e, 0x0f0f, 0x1010, 0x1111, 0x1212, 0x1313, 0x1414, 0x1515,
+      0x1616, 0x1717, 0x1818, 0x1919, 0x1a1a, 0x1b1b, 0x1c1c, 0x1d1d,
+      0x1e1e, 0x1f1f, 0x2020, 0x2121, 0x2222, 0x2323, 0x2424, 0x2525,
+      0x2626, 0x2727, 0x2828, 0x2929, 0x2a2a, 0x2b2b, 0x2c2c, 0x2d2d};
+
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  VCLEAR(v5);
+  VCLEAR(v6);
+  VCLEAR(v7);
+  VCLEAR(v8);
+  stride = 16;
+  VSET(8, e16, m1);
+  asm volatile("vlsseg8e16.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  asm volatile("vssseg8e16.v v1, (%0), %1" ::"r"(ALIGNED_O16), "r"(stride));
+  VVCMP_U16(5, ALIGNED_O16, 0x1234, 0x5678, 0x9abc, 0xdef0, 0x1111, 0x2222,
+            0x3333, 0x4444, 0x5555, 0x6666, 0x7777, 0x8888, 0x9999, 0xaaaa,
+            0xbbbb, 0xcccc, 0xdddd, 0xeeee, 0xffff, 0x0101, 0x0202, 0x0303,
+            0x0404, 0x0505, 0x0606, 0x0707, 0x0808, 0x0909, 0x0a0a, 0x0b0b,
+            0x0c0c, 0x0d0d, 0x0e0e, 0x0f0f, 0x1010, 0x1111, 0x1212, 0x1313,
+            0x1414, 0x1515, 0x1616, 0x1717, 0x1818, 0x1919, 0x1a1a, 0x1b1b,
+            0x1c1c, 0x1d1d, 0x1e1e, 0x1f1f, 0x2020, 0x2121, 0x2222, 0x2323,
+            0x2424, 0x2525, 0x2626, 0x2727, 0x2828, 0x2929, 0x2a2a, 0x2b2b,
+            0x2c2c, 0x2d2d);
+}
+
+// Segment-3
+void TEST_CASE2_32(void) {
+  VSET(-1, e32, m1);
+  volatile uint32_t INP1[] = {
+      0xe19afa6b, 0x8c10145c, 0xbca44cc5, 0x11ffa54e, 0x82f92af6, 0x9af29daa,
+      0x956eb527, 0x575c2e05, 0x68fb4cc5, 0xcf7a1d98, 0x53a0be4e, 0x26439a12,
+      0x785cc853, 0x35659121, 0xf7a96b8c, 0xa87678a2, 0xb11d757e, 0x67dd4037,
+      0xd29ad01e, 0xb7600abf, 0x2e572002, 0xaadc6195, 0xcefce71b, 0x64d90d0c,
+      0x6c3b54b0, 0xcc6da682, 0xd8b7ae76, 0x8533b185, 0xa2cd798c, 0x2a4339cc,
+      0xcf9238fb, 0x7e70281b, 0xdf162ee9, 0x4f2ea60f, 0x4b32bcdd, 0xbf3b8546,
+      0x52b26ff5, 0x18cbcecd, 0xc364c8f8, 0x5bf0c67b, 0x60914005, 0x93265d9d,
+      0xcff3c77d, 0x788529c3, 0xdda63ceb, 0x4edd7f48, 0xddcd4d07, 0x3266d631,
+      0x3b2f25a6, 0x7bfd8a81, 0x9db64ef5, 0xa06a42d4, 0x687f8a39, 0xb9272633,
+      0xb009319e, 0xf542d689, 0x45ef05c9, 0xf547c96e, 0x2a143e76, 0x17a38eec,
+      0x9a73626c, 0xca064493, 0x582140dd, 0x97df3c7a};
+
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  stride = 12;
+  VSET(22, e32, m1);
+  asm volatile("vlsseg3e32.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  asm volatile("vssseg3e32.v v1, (%0), %1" ::"r"(ALIGNED_O32), "r"(stride));
+  VVCMP_U32(
+      6, ALIGNED_O32, 0xe19afa6b, 0x8c10145c, 0xbca44cc5, 0x11ffa54e,
+      0x82f92af6, 0x9af29daa, 0x956eb527, 0x575c2e05, 0x68fb4cc5, 0xcf7a1d98,
+      0x53a0be4e, 0x26439a12, 0x785cc853, 0x35659121, 0xf7a96b8c, 0xa87678a2,
+      0xb11d757e, 0x67dd4037, 0xd29ad01e, 0xb7600abf, 0x2e572002, 0xaadc6195,
+      0xcefce71b, 0x64d90d0c, 0x6c3b54b0, 0xcc6da682, 0xd8b7ae76, 0x8533b185,
+      0xa2cd798c, 0x2a4339cc, 0xcf9238fb, 0x7e70281b, 0xdf162ee9, 0x4f2ea60f,
+      0x4b32bcdd, 0xbf3b8546, 0x52b26ff5, 0x18cbcecd, 0xc364c8f8, 0x5bf0c67b,
+      0x60914005, 0x93265d9d, 0xcff3c77d, 0x788529c3, 0xdda63ceb, 0x4edd7f48,
+      0xddcd4d07, 0x3266d631, 0x3b2f25a6, 0x7bfd8a81, 0x9db64ef5, 0xa06a42d4,
+      0x687f8a39, 0xb9272633, 0xb009319e, 0xf542d689, 0x45ef05c9, 0xf547c96e,
+      0x2a143e76, 0x17a38eec, 0x9a73626c, 0xca064493, 0x582140dd, 0x97df3c7a);
+}
+
+// Segment-2
+void TEST_CASE1_64(void) {
+
+  VSET(-1, e64, m1);
+  volatile uint64_t INP1[] = {
+      0xfa3a99086b4b64aa, 0x57bb4a671118fdc0, 0xbb8df43b65bac0d2,
+      0xa41351c301c72b5b, 0x511e175802d24608, 0x64d7a5514d544e52,
+      0xbf1d53ca3e3c6bf7, 0xd31ac04eea8ecc07, 0x52edd3cfec205090,
+      0x891a1820b423c29c, 0xfc8e3370b171c315, 0xa30da5c56e052f67,
+      0x9f79ec1cdf33c0bc, 0x5d2c78d9927dfa33, 0x52b80462b7e072f9,
+      0x3e0efee7a99a28e7, 0x3216edfad69d8286, 0x7409095aa2433e2e,
+      0x45efda30062c904b, 0x2b707d3fbaef7019, 0xde9483fe82609c40,
+      0x9d5e63fed3019ea6, 0xc4bae94e8d757c0f, 0x7c917722900ef4d8,
+      0x693f603446fb64e6, 0x42cb1e2132c3d7d5, 0xd77ba2e13e47d589,
+      0x45887508688c93b2, 0xac730ac471f57a8e, 0x708ca6623c11c1ff,
+      0x90c7d0d2a8aa883c, 0xdb0427f14bb4d5ba, 0x3adf5823d1051252,
+      0xc31b51ef18e6dc16, 0xa96c56ed56947466, 0x5e0f5c76fdd72450,
+      0xada6b728b9b84f27, 0x9ef5b07ca6742028, 0x2d52c2213e1497ab,
+      0x201b60e0fbbc4acd, 0x5428920ecca684b1, 0xc826aff176ba9a29,
+      0x6f8c8820840f716e, 0x4a2bb5a96b1f24f5, 0x8aac4c04213d26aa,
+      0xecd584f402152e19, 0x89f5805801f25a66, 0xbad7cab9c4062ffc,
+      0xb6715b7275106bc1, 0x53112b0cc2123035, 0x8ec585926ed7af58,
+      0xce4722d4b56cd330, 0x14041ab000c9c396, 0x928220385ce8c56d,
+      0xdb402f4b0fd38776, 0x180002d7d73b1ae2, 0x76c882042e57f707,
+      0xd13e73308658ad1f, 0x5142eb4c19644e7d, 0x23def41d77db2d38,
+      0x34affa8555d23fd9, 0xa311951efe71188d, 0xf96089370f7fa0a7,
+      0xb0899dfea0b44c26};
+
+  VCLEAR(v1);
+  VCLEAR(v2);
+  stride = 0;
+  VSET(5, e64, m1);
+  asm volatile("vlsseg2e64.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  asm volatile("vssseg2e64.v v1, (%0), %1" ::"r"(ALIGNED_O64), "r"(stride));
+  VVCMP_U64(7, ALIGNED_O64, 0xfa3a99086b4b64aa, 0x57bb4a671118fdc0, 0, 0, 0, 0);
+
+  VSET(-1, e64, m1);
+  VCLEAR(v1);
+  VCLEAR(v2);
+  stride = 16;
+  VSET(32, e64, m1);
+  asm volatile("vlsseg2e64.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  asm volatile("vssseg2e64.v v1, (%0), %1" ::"r"(ALIGNED_O64), "r"(stride));
+  VVCMP_U64(8, ALIGNED_O64, 0xfa3a99086b4b64aa, 0x57bb4a671118fdc0,
+            0xbb8df43b65bac0d2, 0xa41351c301c72b5b, 0x511e175802d24608,
+            0x64d7a5514d544e52, 0xbf1d53ca3e3c6bf7, 0xd31ac04eea8ecc07,
+            0x52edd3cfec205090, 0x891a1820b423c29c, 0xfc8e3370b171c315,
+            0xa30da5c56e052f67, 0x9f79ec1cdf33c0bc, 0x5d2c78d9927dfa33,
+            0x52b80462b7e072f9, 0x3e0efee7a99a28e7, 0x3216edfad69d8286,
+            0x7409095aa2433e2e, 0x45efda30062c904b, 0x2b707d3fbaef7019,
+            0xde9483fe82609c40, 0x9d5e63fed3019ea6, 0xc4bae94e8d757c0f,
+            0x7c917722900ef4d8, 0x693f603446fb64e6, 0x42cb1e2132c3d7d5,
+            0xd77ba2e13e47d589, 0x45887508688c93b2, 0xac730ac471f57a8e,
+            0x708ca6623c11c1ff, 0x90c7d0d2a8aa883c, 0xdb0427f14bb4d5ba,
+            0x3adf5823d1051252, 0xc31b51ef18e6dc16, 0xa96c56ed56947466,
+            0x5e0f5c76fdd72450, 0xada6b728b9b84f27, 0x9ef5b07ca6742028,
+            0x2d52c2213e1497ab, 0x201b60e0fbbc4acd, 0x5428920ecca684b1,
+            0xc826aff176ba9a29, 0x6f8c8820840f716e, 0x4a2bb5a96b1f24f5,
+            0x8aac4c04213d26aa, 0xecd584f402152e19, 0x89f5805801f25a66,
+            0xbad7cab9c4062ffc, 0xb6715b7275106bc1, 0x53112b0cc2123035,
+            0x8ec585926ed7af58, 0xce4722d4b56cd330, 0x14041ab000c9c396,
+            0x928220385ce8c56d, 0xdb402f4b0fd38776, 0x180002d7d73b1ae2,
+            0x76c882042e57f707, 0xd13e73308658ad1f, 0x5142eb4c19644e7d,
+            0x23def41d77db2d38, 0x34affa8555d23fd9, 0xa311951efe71188d,
+            0xf96089370f7fa0a7, 0xb0899dfea0b44c26);
+}
+
+// Segment-8
+void TEST_CASE4_64(void) {
+  VSET(-1, e64, m1);
+  volatile uint64_t INP1[] = {
+      0xfa3a99086b4b64aa, 0x57bb4a671118fdc0, 0xbb8df43b65bac0d2,
+      0xa41351c301c72b5b, 0x511e175802d24608, 0x64d7a5514d544e52,
+      0xbf1d53ca3e3c6bf7, 0xd31ac04eea8ecc07, 0x52edd3cfec205090,
+      0x891a1820b423c29c, 0xfc8e3370b171c315, 0xa30da5c56e052f67,
+      0x9f79ec1cdf33c0bc, 0x5d2c78d9927dfa33, 0x52b80462b7e072f9,
+      0x3e0efee7a99a28e7, 0x3216edfad69d8286, 0x7409095aa2433e2e,
+      0x45efda30062c904b, 0x2b707d3fbaef7019, 0xde9483fe82609c40,
+      0x9d5e63fed3019ea6, 0xc4bae94e8d757c0f, 0x7c917722900ef4d8,
+      0x693f603446fb64e6, 0x42cb1e2132c3d7d5, 0xd77ba2e13e47d589,
+      0x45887508688c93b2, 0xac730ac471f57a8e, 0x708ca6623c11c1ff,
+      0x90c7d0d2a8aa883c, 0xdb0427f14bb4d5ba, 0x3adf5823d1051252,
+      0xc31b51ef18e6dc16, 0xa96c56ed56947466, 0x5e0f5c76fdd72450,
+      0xada6b728b9b84f27, 0x9ef5b07ca6742028, 0x2d52c2213e1497ab,
+      0x201b60e0fbbc4acd, 0x5428920ecca684b1, 0xc826aff176ba9a29,
+      0x6f8c8820840f716e, 0x4a2bb5a96b1f24f5, 0x8aac4c04213d26aa,
+      0xecd584f402152e19, 0x89f5805801f25a66, 0xbad7cab9c4062ffc,
+      0xb6715b7275106bc1, 0x53112b0cc2123035, 0x8ec585926ed7af58,
+      0xce4722d4b56cd330, 0x14041ab000c9c396, 0x928220385ce8c56d,
+      0xdb402f4b0fd38776, 0x180002d7d73b1ae2, 0x76c882042e57f707,
+      0xd13e73308658ad1f, 0x5142eb4c19644e7d, 0x23def41d77db2d38,
+      0x34affa8555d23fd9, 0xa311951efe71188d, 0xf96089370f7fa0a7,
+      0xb0899dfea0b44c26};
+
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  VCLEAR(v5);
+  VCLEAR(v6);
+  VCLEAR(v7);
+  VCLEAR(v8);
+  stride = 64;
+  VSET(8, e64, m1);
+  asm volatile("vlsseg8e64.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  asm volatile("vssseg8e64.v v1, (%0), %1" ::"r"(ALIGNED_O64), "r"(stride));
+  VVCMP_U64(9, ALIGNED_O64, 0xfa3a99086b4b64aa, 0x57bb4a671118fdc0,
+            0xbb8df43b65bac0d2, 0xa41351c301c72b5b, 0x511e175802d24608,
+            0x64d7a5514d544e52, 0xbf1d53ca3e3c6bf7, 0xd31ac04eea8ecc07,
+            0x52edd3cfec205090, 0x891a1820b423c29c, 0xfc8e3370b171c315,
+            0xa30da5c56e052f67, 0x9f79ec1cdf33c0bc, 0x5d2c78d9927dfa33,
+            0x52b80462b7e072f9, 0x3e0efee7a99a28e7, 0x3216edfad69d8286,
+            0x7409095aa2433e2e, 0x45efda30062c904b, 0x2b707d3fbaef7019,
+            0xde9483fe82609c40, 0x9d5e63fed3019ea6, 0xc4bae94e8d757c0f,
+            0x7c917722900ef4d8, 0x693f603446fb64e6, 0x42cb1e2132c3d7d5,
+            0xd77ba2e13e47d589, 0x45887508688c93b2, 0xac730ac471f57a8e,
+            0x708ca6623c11c1ff, 0x90c7d0d2a8aa883c, 0xdb0427f14bb4d5ba,
+            0x3adf5823d1051252, 0xc31b51ef18e6dc16, 0xa96c56ed56947466,
+            0x5e0f5c76fdd72450, 0xada6b728b9b84f27, 0x9ef5b07ca6742028,
+            0x2d52c2213e1497ab, 0x201b60e0fbbc4acd, 0x5428920ecca684b1,
+            0xc826aff176ba9a29, 0x6f8c8820840f716e, 0x4a2bb5a96b1f24f5,
+            0x8aac4c04213d26aa, 0xecd584f402152e19, 0x89f5805801f25a66,
+            0xbad7cab9c4062ffc, 0xb6715b7275106bc1, 0x53112b0cc2123035,
+            0x8ec585926ed7af58, 0xce4722d4b56cd330, 0x14041ab000c9c396,
+            0x928220385ce8c56d, 0xdb402f4b0fd38776, 0x180002d7d73b1ae2,
+            0x76c882042e57f707, 0xd13e73308658ad1f, 0x5142eb4c19644e7d,
+            0x23def41d77db2d38, 0x34affa8555d23fd9, 0xa311951efe71188d,
+            0xf96089370f7fa0a7, 0xb0899dfea0b44c26);
+}
+
+// Segment-3
+void TEST_CASE2_8_m(void) {
+  VSET(-1, e8, m1);
+  volatile uint8_t INP1[] = {
+      0x9f, 0xe4, 0x19, 0x20, 0x8f, 0x2e, 0x05, 0xe0, 0xf9, 0xaa, 0x71,
+      0xf0, 0xc3, 0x94, 0xbb, 0xd3, 0x31, 0x4a, 0x57, 0x6b, 0x83, 0x7d,
+      0x1a, 0x45, 0xb2, 0xda, 0x22, 0x56, 0x63, 0x8c, 0xf7, 0x3e, 0x6c,
+      0x27, 0x74, 0x9d, 0xab, 0xcd, 0x13, 0x38, 0x5e, 0x42, 0xdf, 0x80,
+      0x60, 0xa4, 0x7b, 0x0b, 0xc6, 0xad, 0x91, 0xec, 0x3c, 0x69, 0xf5,
+      0x18, 0xe8, 0x6d, 0xb9, 0x82, 0x97, 0x2a, 0x51, 0x70};
+
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  stride = 3;
+  VSET(8, e8, m1);
+  VLOAD_8(v0, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA);
+  VSET(22, e8, m1);
+  asm volatile("vlsseg3e8.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  asm volatile("vssseg3e8.v v1, (%0), %1, v0.t" ::"r"(ALIGNED_O8), "r"(stride));
+  VVCMP_U8(10, ALIGNED_O8, 0, 0, 0, 0x20, 0x8f, 0x2e, 0, 0, 0, 0xaa, 0x71, 0xf0,
+           0, 0, 0, 0xd3, 0x31, 0x4a, 0, 0, 0, 0x7d, 0x1a, 0x45, 0, 0, 0, 0x56,
+           0x63, 0x8c, 0, 0, 0, 0x27, 0x74, 0x9d);
+}
+
+// Segment-8
+void TEST_CASE4_64_m(void) {
+  VSET(-1, e64, m1);
+  volatile uint64_t INP1[] = {
+      0xfa3a99086b4b64aa, 0x57bb4a671118fdc0, 0xbb8df43b65bac0d2,
+      0xa41351c301c72b5b, 0x511e175802d24608, 0x64d7a5514d544e52,
+      0xbf1d53ca3e3c6bf7, 0xd31ac04eea8ecc07, 0x52edd3cfec205090,
+      0x891a1820b423c29c, 0xfc8e3370b171c315, 0xa30da5c56e052f67,
+      0x9f79ec1cdf33c0bc, 0x5d2c78d9927dfa33, 0x52b80462b7e072f9,
+      0x3e0efee7a99a28e7, 0x3216edfad69d8286, 0x7409095aa2433e2e,
+      0x45efda30062c904b, 0x2b707d3fbaef7019, 0xde9483fe82609c40,
+      0x9d5e63fed3019ea6, 0xc4bae94e8d757c0f, 0x7c917722900ef4d8,
+      0x693f603446fb64e6, 0x42cb1e2132c3d7d5, 0xd77ba2e13e47d589,
+      0x45887508688c93b2, 0xac730ac471f57a8e, 0x708ca6623c11c1ff,
+      0x90c7d0d2a8aa883c, 0xdb0427f14bb4d5ba, 0x3adf5823d1051252,
+      0xc31b51ef18e6dc16, 0xa96c56ed56947466, 0x5e0f5c76fdd72450,
+      0xada6b728b9b84f27, 0x9ef5b07ca6742028, 0x2d52c2213e1497ab,
+      0x201b60e0fbbc4acd, 0x5428920ecca684b1, 0xc826aff176ba9a29,
+      0x6f8c8820840f716e, 0x4a2bb5a96b1f24f5, 0x8aac4c04213d26aa,
+      0xecd584f402152e19, 0x89f5805801f25a66, 0xbad7cab9c4062ffc,
+      0xb6715b7275106bc1, 0x53112b0cc2123035, 0x8ec585926ed7af58,
+      0xce4722d4b56cd330, 0x14041ab000c9c396, 0x928220385ce8c56d,
+      0xdb402f4b0fd38776, 0x180002d7d73b1ae2, 0x76c882042e57f707,
+      0xd13e73308658ad1f, 0x5142eb4c19644e7d, 0x23def41d77db2d38,
+      0x34affa8555d23fd9, 0xa311951efe71188d, 0xf96089370f7fa0a7,
+      0xb0899dfea0b44c26};
+
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  VCLEAR(v5);
+  VCLEAR(v6);
+  VCLEAR(v7);
+  VCLEAR(v8);
+  stride = 64;
+  VSET(8, e8, m1);
+  VLOAD_8(v0, 0xA8, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA);
+  VSET(8, e64, m1);
+  asm volatile("vlsseg8e64.v v1, (%0), %1" ::"r"(INP1), "r"(stride));
+  asm volatile("vssseg8e64.v v1, (%0), %1, v0.t" ::"r"(ALIGNED_O64),
+               "r"(stride));
+  VVCMP_U64(11, ALIGNED_O64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+            0, 0, 0, 0, 0, 0, 0, 0x693f603446fb64e6, 0x42cb1e2132c3d7d5,
+            0xd77ba2e13e47d589, 0x45887508688c93b2, 0xac730ac471f57a8e,
+            0x708ca6623c11c1ff, 0x90c7d0d2a8aa883c, 0xdb0427f14bb4d5ba, 0, 0, 0,
+            0, 0, 0, 0, 0, 0x5428920ecca684b1, 0xc826aff176ba9a29,
+            0x6f8c8820840f716e, 0x4a2bb5a96b1f24f5, 0x8aac4c04213d26aa,
+            0xecd584f402152e19, 0x89f5805801f25a66, 0xbad7cab9c4062ffc, 0, 0, 0,
+            0, 0, 0, 0, 0, 0x76c882042e57f707, 0xd13e73308658ad1f,
+            0x5142eb4c19644e7d, 0x23def41d77db2d38, 0x34affa8555d23fd9,
+            0xa311951efe71188d, 0xf96089370f7fa0a7, 0xb0899dfea0b44c26);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1_8();
+  MEM_VCLEAR(ALIGNED_O8);
+  TEST_CASE2_8();
+  MEM_VCLEAR(ALIGNED_O8);
+
+  TEST_CASE4_16();
+  MEM_VCLEAR(ALIGNED_O16);
+
+  TEST_CASE2_32();
+  MEM_VCLEAR(ALIGNED_O32);
+
+  TEST_CASE1_64();
+  MEM_VCLEAR(ALIGNED_O64);
+  TEST_CASE4_64();
+  MEM_VCLEAR(ALIGNED_O64);
+
+  // Masked // Todo: fix masked
+  //  TEST_CASE2_8_m();
+  //  TEST_CASE4_64_m();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vssub.c b/apps/riscv-tests/isa/rv64uv/vssub.c
new file mode 100644
index 0000000..bf36c49
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vssub.c
@@ -0,0 +1,68 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  uint64_t vxsat;
+  VSET(4, e32, m1);
+  VLOAD_32(v1, 0xfffffff0, 0x7FFFFFFC, 15, 20);
+  VLOAD_32(v2, 0x7ffffff0, -500, 3, 25);
+  __asm__ volatile("vssub.vv v3, v1, v2" ::);
+  VCMP_U32(1, v3, 0x80000000, 0x7fffffff, 12, -5);
+  read_vxsat(vxsat);
+  check_vxsat(1, vxsat, 1);
+  reset_vxsat;
+}
+
+void TEST_CASE2(void) {
+  uint64_t vxsat;
+  VSET(4, e32, m1);
+  VLOAD_32(v1, 0xfffffff0, 0x7FFFFFFC, 15, 20);
+  VLOAD_32(v2, 0x7ffffff0, -500, 3, 25);
+  VLOAD_32(v0, 10, 0, 0, 0);
+  VCLEAR(v3);
+  __asm__ volatile("vssub.vv v3, v1, v2, v0.t" ::);
+  VCMP_U32(1, v3, 0, 0x7fffffff, 0, -5);
+  read_vxsat(vxsat);
+  check_vxsat(2, vxsat, 1);
+  reset_vxsat;
+}
+
+void TEST_CASE3(void) {
+  uint64_t vxsat;
+  VSET(4, e32, m1);
+  VLOAD_32(v1, 5, -2147483645, 15, 20);
+  const int64_t scalar = 5;
+  __asm__ volatile("vssub.vx v3, v1, %[A]" ::[A] "r"(scalar));
+  VCMP_U32(3, v3, 0, 0x80000000, 10, 15);
+  read_vxsat(vxsat);
+  check_vxsat(3, vxsat, 1);
+  reset_vxsat;
+}
+
+void TEST_CASE4(void) {
+  VSET(4, e32, m1);
+  VLOAD_32(v1, 5, -2147483645, 15, 20);
+  const int64_t scalar = 5;
+  VLOAD_32(v0, 10, 0, 0, 0);
+  VCLEAR(v3);
+  __asm__ volatile("vssub.vx v3, v1, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U32(4, v3, 0, 0x80000000, 0, 15);
+  reset_vxsat;
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+  enable_fp();
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vssubu.c b/apps/riscv-tests/isa/rv64uv/vssubu.c
new file mode 100644
index 0000000..b05e514
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vssubu.c
@@ -0,0 +1,55 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(4, e32, m1);
+  VLOAD_32(v1, 5, 10, 15, 20);
+  VLOAD_32(v2, 1, 2, 3, 25);
+  __asm__ volatile("vssubu.vv v3, v1, v2" ::);
+  VCMP_U32(1, v3, 4, 8, 12, 0);
+}
+
+void TEST_CASE2(void) {
+  VSET(4, e32, m1);
+  VLOAD_32(v1, 5, 10, 15, 20);
+  VLOAD_32(v2, 1, 2, 3, 120);
+  VLOAD_32(v0, 10, 0, 0, 0);
+  VCLEAR(v3);
+  __asm__ volatile("vssubu.vv v3, v1, v2, v0.t" ::);
+  VCMP_U32(2, v3, 0, 8, 0, 0);
+}
+
+void TEST_CASE3(void) {
+  VSET(4, e32, m1);
+  VLOAD_32(v1, 5, 1, 15, 20);
+  const uint64_t scalar = 5;
+  __asm__ volatile("vssubu.vx v3, v1, %[A]" ::[A] "r"(scalar));
+  VCMP_U32(3, v3, 0, 0, 10, 15);
+}
+
+void TEST_CASE4(void) {
+  VSET(4, e32, m1);
+  VLOAD_32(v1, 5, 1, 15, 20);
+  const uint64_t scalar = 5;
+  VLOAD_32(v0, 10, 0, 0, 0);
+  VCLEAR(v3);
+  __asm__ volatile("vssubu.vx v3, v1, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U32(4, v3, 0, 0, 0, 15);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+  enable_fp();
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vsub.c b/apps/riscv-tests/isa/rv64uv/vsub.c
new file mode 100644
index 0000000..4a1258f
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vsub.c
@@ -0,0 +1,136 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 5, 10, 15, 20, 25, 30, 35, 40, 5, 10, 15, 20, 25, 30, 35, 40);
+  VLOAD_8(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vsub.vv v3, v1, v2");
+  VCMP_U8(1, v3, 4, 8, 12, 16, 20, 24, 28, 32, 4, 8, 12, 16, 20, 24, 28, 32);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 5, 10, 15, 20, 25, 30, 35, 40, 5, 10, 15, 20, 25, 30, 35, 40);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vsub.vv v3, v1, v2");
+  VCMP_U16(2, v3, 4, 8, 12, 16, 20, 24, 28, 32, 4, 8, 12, 16, 20, 24, 28, 32);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 5, 10, 15, 20, 25, 30, 35, 40, 5, 10, 15, 20, 25, 30, 35, 40);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vsub.vv v3, v1, v2");
+  VCMP_U32(3, v3, 4, 8, 12, 16, 20, 24, 28, 32, 4, 8, 12, 16, 20, 24, 28, 32);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 5, 10, 15, 20, 25, 30, 35, 40, 5, 10, 15, 20, 25, 30, 35, 40);
+  VLOAD_64(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vsub.vv v3, v1, v2");
+  VCMP_U64(4, v3, 4, 8, 12, 16, 20, 24, 28, 32, 4, 8, 12, 16, 20, 24, 28, 32);
+}
+
+void TEST_CASE2(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 5, 10, 15, 20, 25, 30, 35, 40, 5, 10, 15, 20, 25, 30, 35, 40);
+  VLOAD_8(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v3);
+  asm volatile("vsub.vv v3, v1, v2, v0.t");
+  VCMP_U8(5, v3, 0, 8, 0, 16, 0, 24, 0, 32, 0, 8, 0, 16, 0, 24, 0, 32);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 5, 10, 15, 20, 25, 30, 35, 40, 5, 10, 15, 20, 25, 30, 35, 40);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v3);
+  asm volatile("vsub.vv v3, v1, v2, v0.t");
+  VCMP_U16(6, v3, 0, 8, 0, 16, 0, 24, 0, 32, 0, 8, 0, 16, 0, 24, 0, 32);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 5, 10, 15, 20, 25, 30, 35, 40, 5, 10, 15, 20, 25, 30, 35, 40);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v3);
+  asm volatile("vsub.vv v3, v1, v2, v0.t");
+  VCMP_U32(7, v3, 0, 8, 0, 16, 0, 24, 0, 32, 0, 8, 0, 16, 0, 24, 0, 32);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 5, 10, 15, 20, 25, 30, 35, 40, 5, 10, 15, 20, 25, 30, 35, 40);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v3);
+  asm volatile("vsub.vv v3, v1, v2, v0.t");
+  VCMP_U32(8, v3, 0, 8, 0, 16, 0, 24, 0, 32, 0, 8, 0, 16, 0, 24, 0, 32);
+}
+
+void TEST_CASE3(void) {
+  const uint64_t scalar = 5;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 5, 10, 15, 20, 25, 30, 35, 40, 5, 10, 15, 20, 25, 30, 35, 40);
+  asm volatile("vsub.vx v3, v1, %[A]" ::[A] "r"(scalar));
+  VCMP_U8(9, v3, 0, 5, 10, 15, 20, 25, 30, 35, 0, 5, 10, 15, 20, 25, 30, 35);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 5, 10, 15, 20, 25, 30, 35, 40, 5, 10, 15, 20, 25, 30, 35, 40);
+  asm volatile("vsub.vx v3, v1, %[A]" ::[A] "r"(scalar));
+  VCMP_U16(10, v3, 0, 5, 10, 15, 20, 25, 30, 35, 0, 5, 10, 15, 20, 25, 30, 35);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 5, 10, 15, 20, 25, 30, 35, 40, 5, 10, 15, 20, 25, 30, 35, 40);
+  asm volatile("vsub.vx v3, v1, %[A]" ::[A] "r"(scalar));
+  VCMP_U32(11, v3, 0, 5, 10, 15, 20, 25, 30, 35, 0, 5, 10, 15, 20, 25, 30, 35);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 5, 10, 15, 20, 25, 30, 35, 40, 5, 10, 15, 20, 25, 30, 35, 40);
+  asm volatile("vsub.vx v3, v1, %[A]" ::[A] "r"(scalar));
+  VCMP_U64(12, v3, 0, 5, 10, 15, 20, 25, 30, 35, 0, 5, 10, 15, 20, 25, 30, 35);
+}
+
+void TEST_CASE4(void) {
+  const uint64_t scalar = 5;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v1, 5, 10, 15, 20, 25, 30, 35, 40, 5, 10, 15, 20, 25, 30, 35, 40);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v3);
+  asm volatile("vsub.vx v3, v1, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U8(13, v3, 0, 5, 0, 15, 0, 25, 0, 35, 0, 5, 0, 15, 0, 25, 0, 35);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v1, 5, 10, 15, 20, 25, 30, 35, 40, 5, 10, 15, 20, 25, 30, 35, 40);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v3);
+  asm volatile("vsub.vx v3, v1, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U16(14, v3, 0, 5, 0, 15, 0, 25, 0, 35, 0, 5, 0, 15, 0, 25, 0, 35);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v1, 5, 10, 15, 20, 25, 30, 35, 40, 5, 10, 15, 20, 25, 30, 35, 40);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v3);
+  asm volatile("vsub.vx v3, v1, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U32(15, v3, 0, 5, 0, 15, 0, 25, 0, 35, 0, 5, 0, 15, 0, 25, 0, 35);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v1, 5, 10, 15, 20, 25, 30, 35, 40, 5, 10, 15, 20, 25, 30, 35, 40);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v3);
+  asm volatile("vsub.vx v3, v1, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U64(16, v3, 0, 5, 0, 15, 0, 25, 0, 35, 0, 5, 0, 15, 0, 25, 0, 35);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vsux.c b/apps/riscv-tests/isa/rv64uv/vsux.c
new file mode 100644
index 0000000..5f21ec8
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vsux.c
@@ -0,0 +1,104 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(4, e8, m1);
+  VLOAD_U8(v2, 0, 1, 2, 3);
+  volatile uint8_t OUP[] = {0xef, 0xef, 0xef, 0xef};
+  VLOAD_U8(v1, 0xff, 0x00, 0xf0, 0x0f);
+  __asm__ volatile("vsuxei8.v v1, (%0), v2" ::"r"(OUP));
+  VEC_EQUAL_U8_RAW(1, OUP, 0xff, 0x00, 0xf0, 0x0f);
+}
+
+// void TEST_CASE2(void) {
+//   VSET(4,e8,m1);
+//   VLOAD_U8(v2,0,1,2,3);
+//   volatile uint8_t OUP[] = {0xef, 0xef, 0xef, 0xef};
+//   VLOAD_U8(v1,0xff,0x00,0xf0,0x0f);
+//   VLOAD_U8(v0,0x12,0x0,0x0,0x0);
+//   __asm__ volatile("vsuxei8.v v1, (%0), v2, v0.t"::"r"(OUP));
+//   VEC_EQUAL_U8_RAW(2,OUP,0xef,0x00,0xef,0xef);
+// }
+
+void TEST_CASE3(void) {
+  VSET(4, e16, m1);
+  VLOAD_U16(v2, 0, 2, 4, 6);
+  volatile uint16_t OUP[] = {0xdead, 0xbeef, 0xdead, 0xbeef};
+  VLOAD_U16(v1, 0xffff, 0x0000, 0xf0f0, 0x0f0f);
+  __asm__ volatile("vsuxei16.v v1, (%0), v2" ::"r"(OUP));
+  VEC_EQUAL_U16_RAW(3, OUP, 0xffff, 0x0000, 0xf0f0, 0x0f0f);
+}
+
+// void TEST_CASE4(void) {
+//   VSET(4,e16,m1);
+//   VLOAD_U16(v2,0,2,4,6);
+//   volatile uint16_t OUP[] = {0xdead, 0xbeef, 0xdead, 0xbeef};
+//   VLOAD_U16(v1,0xffff,0x0000,0xf0f0,0x0f0f);
+//   VLOAD_U16(v0,0x12,0x0,0x0,0x0);
+//   __asm__ volatile("vsuxei16.v v1, (%0), v2, v0.t"::"r"(OUP));
+//   MEMBARRIER;
+//   VEC_EQUAL_U16_RAW(4,OUP,0xdead,0x0000,0xdead,0xbeef);
+// }
+
+void TEST_CASE5(void) {
+  VSET(4, e32, m1);
+  VLOAD_U32(v2, 0, 4, 8, 12);
+  volatile uint32_t OUP[] = {0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef};
+  VLOAD_U32(v1, 0xffffffff, 0x00000000, 0xf0f0f0f0, 0x0f0f0f0f);
+  __asm__ volatile("vsuxei32.v v1, (%0), v2" ::"r"(OUP));
+  VEC_EQUAL_U32_RAW(5, OUP, 0xffffffff, 0x00000000, 0xf0f0f0f0, 0x0f0f0f0f);
+}
+
+// void TEST_CASE6(void) {
+//   VSET(4,e32,m1);
+//   VLOAD_U32(v2,0,4,8,12);
+//   volatile uint32_t OUP[] = {0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef};
+//   VLOAD_U32(v1,0xffffffff,0x00000000,0xf0f0f0f0,0x0f0f0f0f);
+//   VLOAD_U32(v0,0x12,0x0,0x0,0x0);
+//   __asm__ volatile("vsuxei32.v v1, (%0), v2, v0.t"::"r"(OUP));
+//   MEMBARRIER;
+//   VEC_EQUAL_U32_RAW(6,OUP,0xdeadbeef,0x00000000,0xdeadbeef,0xdeadbeef);
+// }
+
+void TEST_CASE7(void) {
+  VSET(4, e64, m1);
+  VLOAD_U64(v2, 0, 8, 16, 24);
+  volatile uint64_t OUP[] = {0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+                             0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef};
+  VLOAD_U64(v1, 0xdeadbeef00000000, 0xdeadbeefffffffff, 0xdeadbeeff0f0f0f0,
+            0xdeadbeef0f0f0f0f);
+  __asm__ volatile("vsuxei64.v v1, (%0), v2" ::"r"(OUP));
+  VEC_EQUAL_U64_RAW(7, OUP, 0xdeadbeef00000000, 0xdeadbeefffffffff,
+                    0xdeadbeeff0f0f0f0, 0xdeadbeef0f0f0f0f);
+}
+
+// void TEST_CASE8(void) {
+//   VSET(4,e64,m1);
+//   VLOAD_U64(v2,0,8,16,24);
+//   volatile uint64_t OUP[] =
+//   {0xdeadbeefdeadbeef,0xdeadbeefdeadbeef,0xdeadbeefdeadbeef,0xdeadbeefdeadbeef};
+//   VLOAD_U64(v1,0xdeadbeef00000000,0xdeadbeefffffffff,0xdeadbeeff0f0f0f0,0xdeadbeef0f0f0f0f);
+//   VLOAD_U64(v0,0x6,0x0,0x0,0x0);
+//   __asm__ volatile("vsuxei64.v v1, (%0), v2, v0.t"::"r"(OUP));
+//   VEC_EQUAL_U64_RAW(8,OUP,0xdeadbeefdeadbeef,0xdeadbeefffffffff,0xdeadbeeff0f0f0f0,0xdeadbeefdeadbeef);
+// }
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+  TEST_CASE1();
+  TEST_CASE3();
+  TEST_CASE5();
+  TEST_CASE7();
+  // TEST_CASE2();
+  // TEST_CASE4();
+  // TEST_CASE6();
+  // TEST_CASE8();
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vsuxei.c b/apps/riscv-tests/isa/rv64uv/vsuxei.c
new file mode 100644
index 0000000..8709d66
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vsuxei.c
@@ -0,0 +1,141 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+
+#include "vector_macros.h"
+
+#define AXI_DWIDTH 128
+
+#define INIT 98
+
+void reset_vec8(volatile uint8_t *vec, int rst_val, uint64_t len) {
+  for (uint64_t i = 0; i < len; ++i)
+    vec[i] = rst_val;
+}
+void reset_vec16(volatile uint16_t *vec, int rst_val, uint64_t len) {
+  for (uint64_t i = 0; i < len; ++i)
+    vec[i] = rst_val;
+}
+void reset_vec32(volatile uint32_t *vec, int rst_val, uint64_t len) {
+  for (uint64_t i = 0; i < len; ++i)
+    vec[i] = rst_val;
+}
+void reset_vec64(volatile uint64_t *vec, int rst_val, uint64_t len) {
+  for (uint64_t i = 0; i < len; ++i)
+    vec[i] = rst_val;
+}
+static volatile uint8_t BUFFER_O8[16] __attribute__((aligned(AXI_DWIDTH))) = {
+    INIT, INIT, INIT, INIT, INIT, INIT, INIT, INIT,
+    INIT, INIT, INIT, INIT, INIT, INIT, INIT, INIT};
+static volatile uint16_t BUFFER_O16[16] __attribute__((aligned(AXI_DWIDTH))) = {
+    INIT, INIT, INIT, INIT, INIT, INIT, INIT, INIT,
+    INIT, INIT, INIT, INIT, INIT, INIT, INIT, INIT};
+static volatile uint32_t BUFFER_O32[16] __attribute__((aligned(AXI_DWIDTH))) = {
+    INIT, INIT, INIT, INIT, INIT, INIT, INIT, INIT,
+    INIT, INIT, INIT, INIT, INIT, INIT, INIT, INIT};
+static volatile uint64_t BUFFER_O64[16] __attribute__((aligned(AXI_DWIDTH))) = {
+    INIT, INIT, INIT, INIT, INIT, INIT, INIT, INIT,
+    INIT, INIT, INIT, INIT, INIT, INIT, INIT, INIT};
+
+// Naive test
+void TEST_CASE1(void) {
+  VSET(12, e8, m1);
+  VLOAD_8(v1, 0xd3, 0x40, 0xd1, 0x84, 0x48, 0x88, 0x88, 0xae, 0x91, 0x02, 0x59,
+          0x89);
+  VLOAD_8(v2, 1, 2, 3, 4, 5, 7, 8, 9, 11, 12, 13, 15);
+  asm volatile("vsuxei8.v v1, (%0), v2" ::"r"(&BUFFER_O8[0]));
+  VVCMP_U8(1, BUFFER_O8, INIT, 0xd3, 0x40, 0xd1, 0x84, 0x48, INIT, 0x88, 0x88,
+           0xae, INIT, 0x91, 0x02, 0x59, INIT, 0x89);
+
+  VSET(12, e16, m1);
+  VLOAD_16(v1, 0xbbd3, 0x3840, 0x8cd1, 0x9384, 0x7548, 0x9388, 0x8188, 0x11ae,
+           0x4891, 0x4902, 0x8759, 0x1989);
+  VLOAD_16(v2, 2, 4, 6, 8, 10, 14, 16, 18, 22, 24, 26, 30);
+  asm volatile("vsuxei16.v v1, (%0), v2" ::"r"(&BUFFER_O16[0]));
+  VVCMP_U16(2, BUFFER_O16, INIT, 0xbbd3, 0x3840, 0x8cd1, 0x9384, 0x7548, INIT,
+            0x9388, 0x8188, 0x11ae, INIT, 0x4891, 0x4902, 0x8759, INIT, 0x1989);
+
+  VSET(12, e32, m1);
+  VLOAD_32(v1, 0xf9aa71f0, 0xa11a9384, 0x99991348, 0x9fa831c7, 0x38197598,
+           0x81937598, 0x18747547, 0x3eeeeeee, 0xab8b9148, 0x90318509,
+           0x31897598, 0x89139848);
+  VLOAD_32(v2, 4, 8, 12, 16, 20, 28, 32, 36, 44, 48, 52, 60);
+  asm volatile("vsuxei32.v v1, (%0), v2" ::"r"(&BUFFER_O32[0]));
+  VVCMP_U32(3, BUFFER_O32, INIT, 0xf9aa71f0, 0xa11a9384, 0x99991348, 0x9fa831c7,
+            0x38197598, INIT, 0x81937598, 0x18747547, 0x3eeeeeee, INIT,
+            0xab8b9148, 0x90318509, 0x31897598, INIT, 0x89139848);
+
+  VSET(12, e64, m1);
+  VLOAD_64(v1, 0xf9aa71f0c394bbd3, 0xa11a9384a7163840, 0x99991348a9f38cd1,
+           0x9fa831c7a11a9384, 0x3819759853987548, 0x81937598aa819388,
+           0x1874754791888188, 0x3eeeeeeee33111ae, 0xab8b914891484891,
+           0x9031850931584902, 0x3189759837598759, 0x8913984898951989);
+  VLOAD_64(v2, 8, 16, 24, 32, 40, 56, 64, 72, 88, 96, 104, 120);
+  asm volatile("vsuxei64.v v1, (%0), v2" ::"r"(&BUFFER_O64[0]));
+  VVCMP_U64(4, BUFFER_O64, INIT, 0xf9aa71f0c394bbd3, 0xa11a9384a7163840,
+            0x99991348a9f38cd1, 0x9fa831c7a11a9384, 0x3819759853987548, INIT,
+            0x81937598aa819388, 0x1874754791888188, 0x3eeeeeeee33111ae, INIT,
+            0xab8b914891484891, 0x9031850931584902, 0x3189759837598759, INIT,
+            0x8913984898951989);
+}
+
+// Naive test, masked
+void TEST_CASE2(void) {
+  reset_vec8(&BUFFER_O8[0], INIT, 16);
+  VSET(12, e8, m1);
+  VLOAD_8(v0, 0xAA, 0x0A);
+  VLOAD_8(v1, 0xd3, 0x40, 0xd1, 0x84, 0x48, 0x88, 0x88, 0xae, 0x91, 0x02, 0x59,
+          0x89);
+  VLOAD_8(v2, 1, 2, 3, 4, 5, 7, 8, 9, 11, 12, 13, 15);
+  asm volatile("vsuxei8.v v1, (%0), v2, v0.t" ::"r"(&BUFFER_O8[0]));
+  VVCMP_U8(5, BUFFER_O8, INIT, INIT, 0x40, INIT, 0x84, INIT, INIT, 0x88, INIT,
+           0xae, INIT, INIT, 0x02, INIT, INIT, 0x89);
+
+  reset_vec16(&BUFFER_O16[0], INIT, 16);
+  VSET(12, e16, m1);
+  VLOAD_8(v0, 0xAA, 0x0A);
+  VLOAD_16(v1, 0xbbd3, 0x3840, 0x8cd1, 0x9384, 0x7548, 0x9388, 0x8188, 0x11ae,
+           0x4891, 0x4902, 0x8759, 0x1989);
+  VLOAD_16(v2, 2, 4, 6, 8, 10, 14, 16, 18, 22, 24, 26, 30);
+  asm volatile("vsuxei16.v v1, (%0), v2, v0.t" ::"r"(&BUFFER_O16[0]));
+  VVCMP_U16(6, BUFFER_O16, INIT, INIT, 0x3840, INIT, 0x9384, INIT, INIT, 0x9388,
+            INIT, 0x11ae, INIT, INIT, 0x4902, INIT, INIT, 0x1989);
+
+  reset_vec32(&BUFFER_O32[0], INIT, 16);
+  VSET(12, e32, m1);
+  VLOAD_8(v0, 0xAA, 0x0A);
+  VLOAD_32(v1, 0xf9aa71f0, 0xa11a9384, 0x99991348, 0x9fa831c7, 0x38197598,
+           0x81937598, 0x18747547, 0x3eeeeeee, 0xab8b9148, 0x90318509,
+           0x31897598, 0x89139848);
+  VLOAD_32(v2, 4, 8, 12, 16, 20, 28, 32, 36, 44, 48, 52, 60);
+  asm volatile("vsuxei32.v v1, (%0), v2, v0.t" ::"r"(&BUFFER_O32[0]));
+  VVCMP_U32(7, BUFFER_O32, INIT, INIT, 0xa11a9384, INIT, 0x9fa831c7, INIT, INIT,
+            0x81937598, INIT, 0x3eeeeeee, INIT, INIT, 0x90318509, INIT, INIT,
+            0x89139848);
+
+  reset_vec64(&BUFFER_O64[0], INIT, 16);
+  VSET(12, e64, m1);
+  VLOAD_8(v0, 0xAA, 0x0A);
+  VLOAD_64(v1, 0xf9aa71f0c394bbd3, 0xa11a9384a7163840, 0x99991348a9f38cd1,
+           0x9fa831c7a11a9384, 0x3819759853987548, 0x81937598aa819388,
+           0x1874754791888188, 0x3eeeeeeee33111ae, 0xab8b914891484891,
+           0x9031850931584902, 0x3189759837598759, 0x8913984898951989);
+  VLOAD_64(v2, 8, 16, 24, 32, 40, 56, 64, 72, 88, 96, 104, 120);
+  asm volatile("vsuxei64.v v1, (%0), v2, v0.t" ::"r"(&BUFFER_O64[0]));
+  VVCMP_U64(8, BUFFER_O64, INIT, INIT, 0xa11a9384a7163840, INIT,
+            0x9fa831c7a11a9384, INIT, INIT, 0x81937598aa819388, INIT,
+            0x3eeeeeeee33111ae, INIT, INIT, 0x9031850931584902, INIT, INIT,
+            0x8913984898951989);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vsuxseg.c b/apps/riscv-tests/isa/rv64uv/vsuxseg.c
new file mode 100644
index 0000000..c2aaff3
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vsuxseg.c
@@ -0,0 +1,196 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+
+#include "vector_macros.h"
+
+#define AXI_DWIDTH_MAX 512
+#define MEM_VEC_SIZE 64
+
+#define MEM_VCLEAR(vec)                                                        \
+  {                                                                            \
+    for (int i = 0; i < MEM_VEC_SIZE; ++i)                                     \
+      vec[i] = 0;                                                              \
+  }
+
+static volatile uint8_t ALIGNED_O8[MEM_VEC_SIZE]
+    __attribute__((aligned(AXI_DWIDTH_MAX))) = {
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
+
+static volatile uint16_t ALIGNED_O16[MEM_VEC_SIZE]
+    __attribute__((aligned(AXI_DWIDTH_MAX))) = {
+        0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+        0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000};
+
+static volatile uint32_t ALIGNED_O32[MEM_VEC_SIZE]
+    __attribute__((aligned(AXI_DWIDTH_MAX))) = {
+        0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+        0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+        0x00000000, 0x00000000, 0x00000000, 0x00000000};
+
+static volatile uint64_t ALIGNED_O64[MEM_VEC_SIZE]
+    __attribute__((aligned(AXI_DWIDTH_MAX))) = {
+        0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+        0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+        0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+        0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+        0x0000000000000000, 0x0000000000000000, 0x0000000000000000,
+        0x0000000000000000};
+
+// Segment-2
+void TEST_CASE1_8(void) {
+  VSET(4, e8, m1);
+  volatile uint8_t INP1[] = {0x9f, 0xe4, 0x19, 0x20, 0x8f, 0x2e, 0x05, 0xe0,
+                             0xf9, 0xaa, 0x71, 0xf0, 0xc3, 0x94, 0xbb, 0xd3};
+
+  MEM_VCLEAR(ALIGNED_O8);
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VLOAD_8(v24, 1, 1, 0, 2);
+  asm volatile("vluxseg2ei8.v v1, (%0), v24" ::"r"(INP1));
+  asm volatile("vsuxseg2ei8.v v1, (%0), v24" ::"r"(ALIGNED_O8));
+  VVCMP_U8(1, ALIGNED_O8, 0x9f, 0xe4, 0x19, 0x20, 0, 0, 0, 0);
+}
+
+// Segment-3
+void TEST_CASE2_8(void) {
+  VSET(4, e8, m1);
+  volatile uint8_t INP1[] = {0x9f, 0xe4, 0x19, 0x20, 0x8f, 0x2e, 0x05, 0xe0,
+                             0xf9, 0xaa, 0x71, 0xf0, 0xc3, 0x94, 0xbb, 0xd3};
+
+  MEM_VCLEAR(ALIGNED_O8);
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VLOAD_16(v24, 0, 1, 0, 3);
+  asm volatile("vluxseg3ei16.v v1, (%0), v24" ::"r"(INP1));
+  VLOAD_16(v24, 3, 2, 1, 0);
+  asm volatile("vsuxseg3ei16.v v1, (%0), v24" ::"r"(ALIGNED_O8));
+  VVCMP_U8(2, ALIGNED_O8, 0x20, 0x8f, 0x2e, 0x19, 0x20, 0x19);
+}
+
+// Segment-4
+void TEST_CASE3_8(void) {
+  VSET(4, e8, m1);
+  volatile uint8_t INP1[] = {0x9f, 0xe4, 0x19, 0x20, 0x8f, 0x2e, 0x05, 0xe0,
+                             0xf9, 0xaa, 0x71, 0xf0, 0xc3, 0x94, 0xbb, 0xd3};
+
+  MEM_VCLEAR(ALIGNED_O8);
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  VLOAD_64(v24, 1, 1, 0, 5);
+  asm volatile("vluxseg4ei64.v v1, (%0), v24" ::"r"(INP1));
+  asm volatile("vsuxseg4ei64.v v1, (%0), v24" ::"r"(ALIGNED_O8));
+  VVCMP_U8(3, ALIGNED_O8, 0x9f, 0xe4, 0x19, 0x20, 0x8f, 0x2e, 0x05, 0xe0, 0xf9);
+}
+
+// Segment-4 for 64-bit
+void TEST_CASE3_64(void) {
+  VSET(4, e64, m1);
+  volatile uint64_t INP1[] = {
+      0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3, 0x123456789abcdef0,
+      0x13572468369b48ac, 0xdeadbeefcafebabe, 0x0123456789abcdef,
+      0x55aa55aa77889900, 0xabcdef1234567890, 0xfeedfacecafebabe,
+      0x123456789abcdef0, 0x1357246855aa55aa, 0x369b48acdeadbeef,
+      0xcafebabe12345678, 0xabcdef0987654321, 0x012345670abcdef1,
+      0x987654321fedcba0};
+
+  MEM_VCLEAR(ALIGNED_O64);
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  VLOAD_8(v24, 8, 8, 0, 40);
+  asm volatile("vluxseg4ei8.v v1, (%0), v24" ::"r"(INP1));
+  asm volatile("vsuxseg4ei8.v v1, (%0), v24" ::"r"(ALIGNED_O64));
+  VVCMP_U64(4, ALIGNED_O64, 0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3,
+            0x123456789abcdef0, 0x13572468369b48ac, 0xdeadbeefcafebabe,
+            0x0123456789abcdef, 0x55aa55aa77889900, 0xabcdef1234567890,
+            0xfeedfacecafebabe, 0);
+}
+
+// Segment-8 for 64-bit
+void TEST_CASE4_64_m(void) {
+  VSET(2, e64, m1);
+  volatile uint64_t INP1[] = {
+      0x9fe419208f2e05e0, 0xf9aa71f0c394bbd3, 0x123456789abcdef0,
+      0x13572468369b48ac, 0xdeadbeefcafebabe, 0x0123456789abcdef,
+      0x55aa55aa77889900, 0xabcdef1234567890, 0xfeedfacecafebabe,
+      0x123456789abcdef0, 0x1357246855aa55aa, 0x369b48acdeadbeef,
+      0xcafebabe12345678, 0xabcdef0987654321, 0x012345670abcdef1,
+      0x987654321fedcba0};
+
+  MEM_VCLEAR(ALIGNED_O64);
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  VCLEAR(v5);
+  VCLEAR(v6);
+  VCLEAR(v7);
+  VCLEAR(v8);
+  VLOAD_8(v0, 0xAF, 0xAA);
+  VLOAD_8(v24, 8, 32);
+  asm volatile("vluxseg8ei8.v v1, (%0), v24" ::"r"(INP1));
+  asm volatile("vsuxseg8ei8.v v1, (%0), v24, v0.t" ::"r"(ALIGNED_O64));
+  VVCMP_U64(5, ALIGNED_O64, 0, 0xf9aa71f0c394bbd3, 0x123456789abcdef0,
+            0x13572468369b48ac, 0xdeadbeefcafebabe, 0x0123456789abcdef,
+            0x55aa55aa77889900, 0xabcdef1234567890, 0xfeedfacecafebabe,
+            0x123456789abcdef0, 0x1357246855aa55aa, 0x369b48acdeadbeef);
+
+  MEM_VCLEAR(ALIGNED_O64);
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  VCLEAR(v5);
+  VCLEAR(v6);
+  VCLEAR(v7);
+  VCLEAR(v8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VLOAD_8(v24, 8, 32);
+  asm volatile("vluxseg8ei8.v v1, (%0), v24" ::"r"(INP1));
+  asm volatile("vsuxseg8ei8.v v1, (%0), v24, v0.t" ::"r"(ALIGNED_O64));
+  VVCMP_U64(6, ALIGNED_O64, 0, 0, 0, 0, 0xdeadbeefcafebabe, 0x0123456789abcdef,
+            0x55aa55aa77889900, 0xabcdef1234567890, 0xfeedfacecafebabe,
+            0x123456789abcdef0, 0x1357246855aa55aa, 0x369b48acdeadbeef);
+
+  MEM_VCLEAR(ALIGNED_O64);
+  VCLEAR(v1);
+  VCLEAR(v2);
+  VCLEAR(v3);
+  VCLEAR(v4);
+  VCLEAR(v5);
+  VCLEAR(v6);
+  VCLEAR(v7);
+  VCLEAR(v8);
+  VLOAD_8(v0, 0xA1, 0xAA);
+  VLOAD_32(v24, 8, 32);
+  asm volatile("vluxseg8ei32.v v1, (%0), v24" ::"r"(INP1));
+  asm volatile("vsuxseg8ei32.v v1, (%0), v24, v0.t" ::"r"(ALIGNED_O64));
+  VVCMP_U64(7, ALIGNED_O64, 0, 0xf9aa71f0c394bbd3, 0x123456789abcdef0,
+            0x13572468369b48ac, 0xdeadbeefcafebabe, 0x0123456789abcdef,
+            0x55aa55aa77889900, 0xabcdef1234567890, 0xfeedfacecafebabe, 0, 0,
+            0);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1_8();
+  TEST_CASE2_8();
+  TEST_CASE3_8();
+
+  TEST_CASE3_64();
+
+  // Masked
+  TEST_CASE4_64_m();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vsx.c b/apps/riscv-tests/isa/rv64uv/vsx.c
new file mode 100644
index 0000000..fc91e81
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vsx.c
@@ -0,0 +1,102 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(4, e8, m1);
+  VLOAD_U8(v2, 0, 1, 2, 3);
+  volatile uint8_t OUP[] = {0xef, 0xef, 0xef, 0xef};
+  VLOAD_U8(v1, 0xff, 0x00, 0xf0, 0x0f);
+  __asm__ volatile("vsxei8.v v1, (%0), v2" ::"r"(OUP));
+  VEC_EQUAL_U8_RAW(1, OUP, 0xff, 0x00, 0xf0, 0x0f);
+}
+
+// void TEST_CASE2(void) {
+//   VSET(4,e8,m1);
+//   VLOAD_8(v2,0,1,2,3);
+//   volatile int8_t OUP[] = {0xef, 0xef, 0xef, 0xef};
+//   VLOAD_8(v1,0xff,0x00,0xf0,0x0f);
+//   VLOAD_8(v0,12,0,0,0);
+//   __asm__ volatile("vsxei8.v v1, (%0), v2, v0.t"::"r"(OUP));
+//   VEC_EQUAL_8_RAW(2,OUP,0xef,0xef,0xf0,0x0f);
+// }
+
+void TEST_CASE3(void) {
+  VSET(4, e16, m1);
+  VLOAD_U16(v2, 0, 2, 4, 6);
+  volatile uint16_t OUP[] = {0xdead, 0xbeef, 0xdead, 0xbeef};
+  VLOAD_U16(v1, 0xffff, 0x0000, 0xf0f0, 0x0f0f);
+  __asm__ volatile("vsxei16.v v1, (%0), v2" ::"r"(OUP));
+  VEC_EQUAL_U16_RAW(3, OUP, 0xffff, 0x0000, 0xf0f0, 0x0f0f);
+}
+
+// void TEST_CASE4(void) {
+//   VSET(4,e16,m1);
+//   VLOAD_16(v2,0,2,4,6);
+//   volatile int16_t OUP[] = {0xdead, 0xbeef, 0xdead, 0xbeef};
+//   VLOAD_16(v1,0xffff,0x0000,0xf0f0,0x0f0f);
+//   VLOAD_16(v0,12,0,0,0);
+//   __asm__ volatile("vsxei16.v v1, (%0), v2, v0.t"::"r"(OUP));
+//   VEC_EQUAL_16_RAW(4,OUP,0xdead,0xbeef,0xf0f0,0x0f0f);
+// }
+
+void TEST_CASE5(void) {
+  VSET(4, e32, m1);
+  VLOAD_U32(v2, 0, 4, 8, 12);
+  volatile uint32_t OUP[] = {0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef};
+  VLOAD_U32(v1, 0xffffffff, 0x00000000, 0xf0f0f0f0, 0x0f0f0f0f);
+  __asm__ volatile("vsxei32.v v1, (%0), v2" ::"r"(OUP));
+  VEC_EQUAL_U32_RAW(5, OUP, 0xffffffff, 0x00000000, 0xf0f0f0f0, 0x0f0f0f0f);
+}
+
+// void TEST_CASE6(void) {
+//   VSET(4,e32,m1);
+//   VLOAD_U32(v2,0,4,8,12);
+//   volatile int32_t OUP[] = {0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef};
+//   VLOAD_32(v1,0xffffffff,0x00000000,0xf0f0f0f0,0x0f0f0f0f);
+//   VLOAD_32(v0,12,0,0,0);
+//   __asm__ volatile("vsxei32.v v1, (%0), v2, v0.t"::"r"(OUP));
+//   VEC_EQUAL_32_RAW(6,OUP,0xdeadbeef,0xdeadbeef,0xf0f0f0f0,0x0f0f0f0f);
+// }
+
+void TEST_CASE7(void) {
+  VSET(4, e64, m1);
+  VLOAD_U64(v2, 0, 8, 16, 24);
+  volatile uint64_t OUP[] = {0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+                             0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef};
+  VLOAD_U64(v1, 0xdeadbeef00000000, 0xdeadbeefffffffff, 0xdeadbeeff0f0f0f0,
+            0xdeadbeef0f0f0f0f);
+  __asm__ volatile("vsxei64.v v1, (%0), v2" ::"r"(OUP));
+  VEC_EQUAL_U64_RAW(7, OUP, 0xdeadbeef00000000, 0xdeadbeefffffffff,
+                    0xdeadbeeff0f0f0f0, 0xdeadbeef0f0f0f0f);
+}
+
+// void TEST_CASE8(void) {
+//   VSET(4,e64,m1);
+//   VLOAD_64(v2,0,8,16,24);
+//   volatile int64_t OUP[] =
+//   {0xdeadbeefdeadbeef,0xdeadbeefdeadbeef,0xdeadbeefdeadbeef,0xdeadbeefdeadbeef};
+//   VLOAD_64(v1,0xdeadbeef00000000,0xdeadbeefffffffff,0xdeadbeeff0f0f0f0,0xdeadbeef0f0f0f0f);
+//   VLOAD_64(v0,6,0,0,0);
+//   __asm__ volatile("vsxei64.v v1, (%0), v2, v0.t"::"r"(OUP));
+//   VEC_EQUAL_64_RAW(8,OUP,0xdeadbeefdeadbeef,0xdeadbeefffffffff,0xdeadbeeff0f0f0f0,0xdeadbeefdeadbeef);
+// }
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+  TEST_CASE1();
+  TEST_CASE3();
+  TEST_CASE5();
+  TEST_CASE7();
+  // TEST_CASE2();
+  // TEST_CASE4();
+  // TEST_CASE6();
+  // TEST_CASE8();
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vwadd.c b/apps/riscv-tests/isa/rv64uv/vwadd.c
new file mode 100644
index 0000000..ccd5fdb
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vwadd.c
@@ -0,0 +1,228 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v4, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vwadd.vv v6, v2, v4");
+  VSET(16, e16, m1);
+  VCMP_U16(1, v6, 2, 4, 6, 8, 10, 12, 14, 16, 2, 4, 6, 8, 10, 12, 14, 16);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v4, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vwadd.vv v6, v2, v4");
+  VSET(16, e32, m1);
+  VCMP_U32(2, v6, 2, 4, 6, 8, 10, 12, 14, 16, 2, 4, 6, 8, 10, 12, 14, 16);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v4, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vwadd.vv v6, v2, v4");
+  VSET(16, e64, m1);
+  VCMP_U64(3, v6, 2, 4, 6, 8, 10, 12, 14, 16, 2, 4, 6, 8, 10, 12, 14, 16);
+}
+
+void TEST_CASE2(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v4, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwadd.vv v6, v2, v4, v0.t");
+  VSET(16, e16, m1);
+  VCMP_U16(4, v6, 0, 4, 0, 8, 0, 12, 0, 16, 0, 4, 0, 8, 0, 12, 0, 16);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v4, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwadd.vv v6, v2, v4, v0.t");
+  VSET(16, e32, m1);
+  VCMP_U32(5, v6, 0, 4, 0, 8, 0, 12, 0, 16, 0, 4, 0, 8, 0, 12, 0, 16);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v4, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwadd.vv v6, v2, v4, v0.t");
+  VSET(16, e64, m1);
+  VCMP_U64(6, v6, 0, 4, 0, 8, 0, 12, 0, 16, 0, 4, 0, 8, 0, 12, 0, 16);
+}
+
+void TEST_CASE3(void) {
+  const uint32_t scalar = 5;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 1, -2, 3, -4, 5, -6, 7, -8, 9, -10, 11, -12, 13, -14, 15, -16);
+  asm volatile("vwadd.vx v6, v2, %[A]" ::[A] "r"(scalar));
+  VSET(16, e16, m1);
+  VCMP_U16(7, v6, 6, 3, 8, 1, 10, -1, 12, -3, 14, -5, 16, -7, 18, -9, 20, -11);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 1, -2, 3, -4, 5, -6, 7, -8, 9, -10, 11, -12, 13, -14, 15, -16);
+  asm volatile("vwadd.vx v6, v2, %[A]" ::[A] "r"(scalar));
+  VSET(16, e32, m1);
+  VCMP_U32(8, v6, 6, 3, 8, 1, 10, -1, 12, -3, 14, -5, 16, -7, 18, -9, 20, -11);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 1, -2, 3, -4, 5, -6, 7, -8, 9, -10, 11, -12, 13, -14, 15, -16);
+  asm volatile("vwadd.vx v6, v2, %[A]" ::[A] "r"(scalar));
+  VSET(16, e64, m1);
+  VCMP_U64(9, v6, 6, 3, 8, 1, 10, -1, 12, -3, 14, -5, 16, -7, 18, -9, 20, -11);
+}
+
+void TEST_CASE4(void) {
+  const uint32_t scalar = 5;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwadd.vx v6, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(16, e16, m1);
+  VCMP_U16(10, v6, 0, 7, 0, 9, 0, 11, 0, 13, 0, 7, 0, 9, 0, 11, 0, 13);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwadd.vx v6, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(16, e32, m1);
+  VCMP_U32(11, v6, 0, 7, 0, 9, 0, 11, 0, 13, 0, 7, 0, 9, 0, 11, 0, 13);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwadd.vx v6, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(16, e64, m1);
+  VCMP_U64(12, v6, 0, 7, 0, 9, 0, 11, 0, 13, 0, 7, 0, 9, 0, 11, 0, 13);
+}
+
+void TEST_CASE5(void) {
+  VSET(16, e8, m1);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v4, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vwadd.wv v6, v2, v4");
+  VSET(16, e16, m1);
+  VCMP_U16(13, v6, 2, 4, 6, 8, 10, 12, 14, 16, 2, 4, 6, 8, 10, 12, 14, 16);
+
+  VSET(16, e16, m1);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v4, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vwadd.wv v6, v2, v4");
+  VSET(16, e32, m1);
+  VCMP_U32(14, v6, 2, 4, 6, 8, 10, 12, 14, 16, 2, 4, 6, 8, 10, 12, 14, 16);
+
+  VSET(16, e32, m1);
+  VLOAD_64(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v4, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vwadd.wv v6, v2, v4");
+  VSET(16, e64, m1);
+  VCMP_U64(15, v6, 2, 4, 6, 8, 10, 12, 14, 16, 2, 4, 6, 8, 10, 12, 14, 16);
+}
+
+void TEST_CASE6(void) {
+  VSET(16, e8, m1);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v4, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwadd.wv v6, v2, v4, v0.t");
+  VSET(16, e16, m1);
+  VCMP_U16(16, v6, 0, 4, 0, 8, 0, 12, 0, 16, 0, 4, 0, 8, 0, 12, 0, 16);
+
+  VSET(16, e16, m1);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v4, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwadd.wv v6, v2, v4, v0.t");
+  VSET(16, e32, m1);
+  VCMP_U32(17, v6, 0, 4, 0, 8, 0, 12, 0, 16, 0, 4, 0, 8, 0, 12, 0, 16);
+
+  VSET(16, e32, m1);
+  VLOAD_64(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v4, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwadd.wv v6, v2, v4, v0.t");
+  VSET(16, e64, m1);
+  VCMP_U64(18, v6, 0, 4, 0, 8, 0, 12, 0, 16, 0, 4, 0, 8, 0, 12, 0, 16);
+}
+
+void TEST_CASE7(void) {
+  const uint32_t scalar = 5;
+
+  VSET(16, e8, m1);
+  VLOAD_16(v2, 1, -2, 3, -4, 5, -6, 7, -8, 9, -10, 11, -12, 13, -14, 15, -16);
+  asm volatile("vwadd.wx v6, v2, %[A]" ::[A] "r"(scalar));
+  VSET(16, e16, m1);
+  VCMP_U16(19, v6, 6, 3, 8, 1, 10, -1, 12, -3, 14, -5, 16, -7, 18, -9, 20, -11);
+
+  VSET(16, e16, m1);
+  VLOAD_32(v2, 1, -2, 3, -4, 5, -6, 7, -8, 9, -10, 11, -12, 13, -14, 15, -16);
+  asm volatile("vwadd.wx v6, v2, %[A]" ::[A] "r"(scalar));
+  VSET(16, e32, m1);
+  VCMP_U32(20, v6, 6, 3, 8, 1, 10, -1, 12, -3, 14, -5, 16, -7, 18, -9, 20, -11);
+
+  VSET(16, e32, m1);
+  VLOAD_64(v2, 1, -2, 3, -4, 5, -6, 7, -8, 9, -10, 11, -12, 13, -14, 15, -16);
+  asm volatile("vwadd.wx v6, v2, %[A]" ::[A] "r"(scalar));
+  VSET(16, e64, m1);
+  VCMP_U64(21, v6, 6, 3, 8, 1, 10, -1, 12, -3, 14, -5, 16, -7, 18, -9, 20, -11);
+}
+
+void TEST_CASE8(void) {
+  const uint32_t scalar = 5;
+
+  VSET(16, e8, m1);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwadd.wx v6, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(16, e16, m1);
+  VCMP_U16(22, v6, 0, 7, 0, 9, 0, 11, 0, 13, 0, 7, 0, 9, 0, 11, 0, 13);
+
+  VSET(16, e16, m1);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwadd.wx v6, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(16, e32, m1);
+  VCMP_U32(23, v6, 0, 7, 0, 9, 0, 11, 0, 13, 0, 7, 0, 9, 0, 11, 0, 13);
+
+  VSET(16, e32, m1);
+  VLOAD_64(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwadd.wx v6, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(16, e64, m1);
+  VCMP_U64(24, v6, 0, 7, 0, 9, 0, 11, 0, 13, 0, 7, 0, 9, 0, 11, 0, 13);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+  TEST_CASE6();
+  TEST_CASE7();
+  TEST_CASE8();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vwaddu.c b/apps/riscv-tests/isa/rv64uv/vwaddu.c
new file mode 100644
index 0000000..b913556
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vwaddu.c
@@ -0,0 +1,231 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v4, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vwaddu.vv v6, v2, v4");
+  VSET(16, e16, m1);
+  VCMP_U16(1, v6, 2, 4, 6, 8, 10, 12, 14, 16, 2, 4, 6, 8, 10, 12, 14, 16);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v4, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vwaddu.vv v6, v2, v4");
+  VSET(16, e32, m1);
+  VCMP_U32(2, v6, 2, 4, 6, 8, 10, 12, 14, 16, 2, 4, 6, 8, 10, 12, 14, 16);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v4, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vwaddu.vv v6, v2, v4");
+  VSET(16, e64, m1);
+  VCMP_U64(3, v6, 2, 4, 6, 8, 10, 12, 14, 16, 2, 4, 6, 8, 10, 12, 14, 16);
+}
+
+void TEST_CASE2(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v4, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwaddu.vv v6, v2, v4, v0.t");
+  VSET(16, e16, m1);
+  VCMP_U16(4, v6, 0, 4, 0, 8, 0, 12, 0, 16, 0, 4, 0, 8, 0, 12, 0, 16);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v4, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwaddu.vv v6, v2, v4, v0.t");
+  VSET(16, e32, m1);
+  VCMP_U32(5, v6, 0, 4, 0, 8, 0, 12, 0, 16, 0, 4, 0, 8, 0, 12, 0, 16);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v4, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwaddu.vv v6, v2, v4, v0.t");
+  VSET(16, e64, m1);
+  VCMP_U64(6, v6, 0, 4, 0, 8, 0, 12, 0, 16, 0, 4, 0, 8, 0, 12, 0, 16);
+}
+
+void TEST_CASE3(void) {
+  const uint32_t scalar = 5;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 1, -2, 3, -4, 5, -6, 7, -8, 9, -10, 11, -12, 13, -14, 15, -16);
+  asm volatile("vwaddu.vx v6, v2, %[A]" ::[A] "r"(scalar));
+  VSET(16, e16, m1);
+  VCMP_U16(7, v6, 6, 259, 8, 257, 10, 255, 12, 253, 14, 251, 16, 249, 18, 247,
+           20, 245);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 1, -2, 3, -4, 5, -6, 7, -8, 9, -10, 11, -12, 13, -14, 15, -16);
+  asm volatile("vwaddu.vx v6, v2, %[A]" ::[A] "r"(scalar));
+  VSET(16, e32, m1);
+  VCMP_U32(8, v6, 6, 65539, 8, 65537, 10, 65535, 12, 65533, 14, 65531, 16,
+           65529, 18, 65527, 20, 65525);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 1, -2, 3, -4, 5, -6, 7, -8, 9, -10, 11, -12, 13, -14, 15, -16);
+  asm volatile("vwaddu.vx v6, v2, %[A]" ::[A] "r"(scalar));
+  VSET(16, e64, m1);
+  VCMP_U64(9, v6, 6, 4294967299, 8, 4294967297, 10, 4294967295, 12, 4294967293,
+           14, 4294967291, 16, 4294967289, 18, 4294967287, 20, 4294967285);
+}
+
+void TEST_CASE4(void) {
+  const uint32_t scalar = 5;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwaddu.vx v6, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(16, e16, m1);
+  VCMP_U16(10, v6, 0, 7, 0, 9, 0, 11, 0, 13, 0, 7, 0, 9, 0, 11, 0, 13);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwaddu.vx v6, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(16, e32, m1);
+  VCMP_U32(11, v6, 0, 7, 0, 9, 0, 11, 0, 13, 0, 7, 0, 9, 0, 11, 0, 13);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwaddu.vx v6, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(16, e64, m1);
+  VCMP_U64(12, v6, 0, 7, 0, 9, 0, 11, 0, 13, 0, 7, 0, 9, 0, 11, 0, 13);
+}
+
+void TEST_CASE5(void) {
+  VSET(16, e8, m1);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v4, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vwaddu.wv v6, v2, v4");
+  VSET(16, e16, m1);
+  VCMP_U16(13, v6, 2, 4, 6, 8, 10, 12, 14, 16, 2, 4, 6, 8, 10, 12, 14, 16);
+
+  VSET(16, e16, m1);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v4, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vwaddu.wv v6, v2, v4");
+  VSET(16, e32, m1);
+  VCMP_U32(14, v6, 2, 4, 6, 8, 10, 12, 14, 16, 2, 4, 6, 8, 10, 12, 14, 16);
+
+  VSET(16, e32, m1);
+  VLOAD_64(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v4, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vwaddu.wv v6, v2, v4");
+  VSET(16, e64, m1);
+  VCMP_U64(15, v6, 2, 4, 6, 8, 10, 12, 14, 16, 2, 4, 6, 8, 10, 12, 14, 16);
+}
+
+void TEST_CASE6(void) {
+  VSET(16, e8, m1);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v4, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwaddu.wv v6, v2, v4, v0.t");
+  VSET(16, e16, m1);
+  VCMP_U16(16, v6, 0, 4, 0, 8, 0, 12, 0, 16, 0, 4, 0, 8, 0, 12, 0, 16);
+
+  VSET(16, e16, m1);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v4, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwaddu.wv v6, v2, v4, v0.t");
+  VSET(16, e32, m1);
+  VCMP_U32(17, v6, 0, 4, 0, 8, 0, 12, 0, 16, 0, 4, 0, 8, 0, 12, 0, 16);
+
+  VSET(16, e32, m1);
+  VLOAD_64(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v4, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwaddu.wv v6, v2, v4, v0.t");
+  VSET(16, e64, m1);
+  VCMP_U64(18, v6, 0, 4, 0, 8, 0, 12, 0, 16, 0, 4, 0, 8, 0, 12, 0, 16);
+}
+
+void TEST_CASE7(void) {
+  const uint32_t scalar = 5;
+
+  VSET(16, e8, m1);
+  VLOAD_16(v2, 1, -2, 3, -4, 5, -6, 7, -8, 9, -10, 11, -12, 13, -14, 15, -16);
+  asm volatile("vwaddu.wx v6, v2, %[A]" ::[A] "r"(scalar));
+  VSET(16, e16, m1);
+  VCMP_U16(19, v6, 6, 3, 8, 1, 10, -1, 12, -3, 14, -5, 16, -7, 18, -9, 20, -11);
+
+  VSET(16, e16, m1);
+  VLOAD_32(v2, 1, -2, 3, -4, 5, -6, 7, -8, 9, -10, 11, -12, 13, -14, 15, -16);
+  asm volatile("vwaddu.wx v6, v2, %[A]" ::[A] "r"(scalar));
+  VSET(16, e32, m1);
+  VCMP_U32(20, v6, 6, 3, 8, 1, 10, -1, 12, -3, 14, -5, 16, -7, 18, -9, 20, -11);
+
+  VSET(16, e32, m1);
+  VLOAD_64(v2, 1, -2, 3, -4, 5, -6, 7, -8, 9, -10, 11, -12, 13, -14, 15, -16);
+  asm volatile("vwaddu.wx v6, v2, %[A]" ::[A] "r"(scalar));
+  VSET(16, e64, m1);
+  VCMP_U64(21, v6, 6, 3, 8, 1, 10, -1, 12, -3, 14, -5, 16, -7, 18, -9, 20, -11);
+}
+
+void TEST_CASE8(void) {
+  const uint32_t scalar = 5;
+
+  VSET(16, e8, m1);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwaddu.wx v6, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(16, e16, m1);
+  VCMP_U16(22, v6, 0, 7, 0, 9, 0, 11, 0, 13, 0, 7, 0, 9, 0, 11, 0, 13);
+
+  VSET(16, e16, m1);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwaddu.wx v6, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(16, e32, m1);
+  VCMP_U32(23, v6, 0, 7, 0, 9, 0, 11, 0, 13, 0, 7, 0, 9, 0, 11, 0, 13);
+
+  VSET(16, e32, m1);
+  VLOAD_64(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwaddu.wx v6, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(16, e64, m1);
+  VCMP_U64(24, v6, 0, 7, 0, 9, 0, 11, 0, 13, 0, 7, 0, 9, 0, 11, 0, 13);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+  TEST_CASE6();
+  TEST_CASE7();
+  TEST_CASE8();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vwmacc.c b/apps/riscv-tests/isa/rv64uv/vwmacc.c
new file mode 100644
index 0000000..fa228a1
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vwmacc.c
@@ -0,0 +1,248 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1() {
+  VSET(16, e16, m1);
+  VLOAD_16(v6, 0x460f, 0x1c3e, 0xa322, 0xa7de, 0xd343, 0xa068, 0xf7a8, 0x3a62,
+           0x3f7f, 0x0ae0, 0x0e38, 0x57fe, 0xdc97, 0x61e5, 0xe3f4, 0xb1bd);
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x19, 0x87, 0x46, 0xf5, 0x3d, 0x66, 0xd7, 0xcf, 0x9f, 0x73, 0x35,
+          0x92, 0xb4, 0xc4, 0xdb, 0x1a);
+  VLOAD_8(v4, 0xd0, 0x62, 0xb7, 0xd9, 0x39, 0xdf, 0x3e, 0x3d, 0xa2, 0xbb, 0xf1,
+          0xba, 0xe2, 0xd7, 0x51, 0x5d);
+  asm volatile("vwmacc.vv v6, v2, v4");
+  VSET(16, e16, m1);
+  VCMP_I16(1, v6, 0x415f, 0xedec, 0x8f2c, 0xa98b, 0xe0d8, 0x9342, 0xedba,
+           0x2eb5, 0x631d, 0xebe1, 0x0b1d, 0x7612, 0xe57f, 0x6b81, 0xd83f,
+           0xbb2f);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v6, 0x1d5e4130, 0x9a736c84, 0xe2c407c1, 0x62baf7c8, 0xc157159f,
+           0x6cea275d, 0x0c385a3e, 0xf8f640d1, 0x484e89df, 0xb7720e91,
+           0x17a7a4cf, 0x9cba6dac, 0x177e67d2, 0x491950da, 0x5b48691f,
+           0x03289e10);
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x6930, 0x239f, 0x2214, 0x555e, 0x9868, 0x02e7, 0x784f, 0x8c32,
+           0xe8d1, 0xe941, 0xaaaf, 0x4833, 0xc773, 0x6156, 0xdad9, 0x02a5);
+  VLOAD_16(v4, 0xe798, 0x1fe5, 0xca4f, 0xb93c, 0xafe4, 0x5641, 0x4848, 0x82a3,
+           0x6065, 0x1385, 0x5a53, 0x3318, 0xd488, 0xb1cf, 0x5142, 0x0277);
+  asm volatile("vwmacc.vv v6, v2, v4");
+  VSET(16, e32, m1);
+  VCMP_I32(2, v6, 0x135705b0, 0x9ee38abf, 0xdb9e53ed, 0x4b21e7d0, 0xe1c1ea3f,
+           0x6de47e04, 0x2e306876, 0x31abe8a7, 0x3f93c454, 0xb5b61056,
+           0xf98d818c, 0xab235b74, 0x211898ea, 0x2b5e7b64, 0x4f7d7e11,
+           0x032f22c3);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v6, 0x37abc1433be408eb, 0xb3af312be2d38e09, 0x3a99dc46913b03d2,
+           0xb2cca27c11815d4d, 0x456749124aaf479a, 0xc11d5ef0eaa5ee72,
+           0x1e6a624541e03978, 0x36ce0e391abb8a91, 0x552a61c1f7116723,
+           0x621ae1e17b7074c2, 0x4c3f1888b5df72b9, 0xde3961024df8c2cf,
+           0x37cd59f214853904, 0xe76372440eb37d3d, 0x0f0ff8cee2000142,
+           0x061e905b827b9818);
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0xb5c0475b, 0xda0c4af7, 0xa939123e, 0xb7261aa3, 0x510b75c1,
+           0x7d5e66d9, 0x3b263bb7, 0xc35c07a0, 0x03b0bb28, 0xba423d88,
+           0xb4ddeabb, 0x97b1e0ce, 0x01d07d01, 0x16174f78, 0x40c6b24f,
+           0x7fab39a9);
+  VLOAD_32(v4, 0x376ce1ba, 0x9cc53665, 0x9292669b, 0xcaec0663, 0x174f60ba,
+           0x5fc79836, 0x6597295d, 0x737b18f1, 0x8cb86656, 0x044f320e,
+           0x2a881643, 0x2e1a8f59, 0xfdc331d1, 0xca03d155, 0x0a51ebfe,
+           0xcac2c353);
+  asm volatile("vwmacc.vv v6, v2, v4");
+  VSET(16, e64, m1);
+  VCMP_I64(3, v6, 0x27987c3defb2dc09, 0xc2652748b5903b7c, 0x5fb1b6348769c35c,
+           0xc1e76e2cf6217c56, 0x4cc871cf26ba35d4, 0xf0052607e34f7838,
+           0x35e364f04a4539f3, 0x1b733cf52ef5b831, 0x5380f57403c23693,
+           0x60ee57a5b80c6232, 0x3fc390677f77f3aa, 0xcb708510404efc6d,
+           0x37c94aa4ac6b77d5, 0xe2badbd70ab9d815, 0x11ac765b0dd270a4,
+           0xeb91935c5ffd04e3);
+}
+
+void TEST_CASE2() {
+  VSET(16, e16, m1);
+  VLOAD_16(v6, 0x460f, 0x1c3e, 0xa322, 0xa7de, 0xd343, 0xa068, 0xf7a8, 0x3a62,
+           0x3f7f, 0x0ae0, 0x0e38, 0x57fe, 0xdc97, 0x61e5, 0xe3f4, 0xb1bd);
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x19, 0x87, 0x46, 0xf5, 0x3d, 0x66, 0xd7, 0xcf, 0x9f, 0x73, 0x35,
+          0x92, 0xb4, 0xc4, 0xdb, 0x1a);
+  VLOAD_8(v4, 0xd0, 0x62, 0xb7, 0xd9, 0x39, 0xdf, 0x3e, 0x3d, 0xa2, 0xbb, 0xf1,
+          0xba, 0xe2, 0xd7, 0x51, 0x5d);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vwmacc.vv v6, v2, v4, v0.t");
+  VSET(16, e16, m1);
+  VCMP_I16(4, v6, 0x460f, 0xedec, 0xa322, 0xa98b, 0xd343, 0x9342, 0xf7a8,
+           0x2eb5, 0x3f7f, 0xebe1, 0x0e38, 0x7612, 0xdc97, 0x6b81, 0xe3f4,
+           0xbb2f);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v6, 0x1d5e4130, 0x9a736c84, 0xe2c407c1, 0x62baf7c8, 0xc157159f,
+           0x6cea275d, 0x0c385a3e, 0xf8f640d1, 0x484e89df, 0xb7720e91,
+           0x17a7a4cf, 0x9cba6dac, 0x177e67d2, 0x491950da, 0x5b48691f,
+           0x03289e10);
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x6930, 0x239f, 0x2214, 0x555e, 0x9868, 0x02e7, 0x784f, 0x8c32,
+           0xe8d1, 0xe941, 0xaaaf, 0x4833, 0xc773, 0x6156, 0xdad9, 0x02a5);
+  VLOAD_16(v4, 0xe798, 0x1fe5, 0xca4f, 0xb93c, 0xafe4, 0x5641, 0x4848, 0x82a3,
+           0x6065, 0x1385, 0x5a53, 0x3318, 0xd488, 0xb1cf, 0x5142, 0x0277);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vwmacc.vv v6, v2, v4, v0.t");
+  VSET(16, e32, m1);
+  VCMP_I32(5, v6, 0x1d5e4130, 0x9ee38abf, 0xe2c407c1, 0x4b21e7d0, 0xc157159f,
+           0x6de47e04, 0x0c385a3e, 0x31abe8a7, 0x484e89df, 0xb5b61056,
+           0x17a7a4cf, 0xab235b74, 0x177e67d2, 0x2b5e7b64, 0x5b48691f,
+           0x032f22c3);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v6, 0x37abc1433be408eb, 0xb3af312be2d38e09, 0x3a99dc46913b03d2,
+           0xb2cca27c11815d4d, 0x456749124aaf479a, 0xc11d5ef0eaa5ee72,
+           0x1e6a624541e03978, 0x36ce0e391abb8a91, 0x552a61c1f7116723,
+           0x621ae1e17b7074c2, 0x4c3f1888b5df72b9, 0xde3961024df8c2cf,
+           0x37cd59f214853904, 0xe76372440eb37d3d, 0x0f0ff8cee2000142,
+           0x061e905b827b9818);
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0xb5c0475b, 0xda0c4af7, 0xa939123e, 0xb7261aa3, 0x510b75c1,
+           0x7d5e66d9, 0x3b263bb7, 0xc35c07a0, 0x03b0bb28, 0xba423d88,
+           0xb4ddeabb, 0x97b1e0ce, 0x01d07d01, 0x16174f78, 0x40c6b24f,
+           0x7fab39a9);
+  VLOAD_32(v4, 0x376ce1ba, 0x9cc53665, 0x9292669b, 0xcaec0663, 0x174f60ba,
+           0x5fc79836, 0x6597295d, 0x737b18f1, 0x8cb86656, 0x044f320e,
+           0x2a881643, 0x2e1a8f59, 0xfdc331d1, 0xca03d155, 0x0a51ebfe,
+           0xcac2c353);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vwmacc.vv v6, v2, v4, v0.t");
+  VSET(16, e64, m1);
+  VCMP_I64(6, v6, 0x37abc1433be408eb, 0xc2652748b5903b7c, 0x3a99dc46913b03d2,
+           0xc1e76e2cf6217c56, 0x456749124aaf479a, 0xf0052607e34f7838,
+           0x1e6a624541e03978, 0x1b733cf52ef5b831, 0x552a61c1f7116723,
+           0x60ee57a5b80c6232, 0x4c3f1888b5df72b9, 0xcb708510404efc6d,
+           0x37cd59f214853904, 0xe2badbd70ab9d815, 0x0f0ff8cee2000142,
+           0xeb91935c5ffd04e3);
+}
+
+void TEST_CASE3() {
+  VSET(16, e16, m1);
+  VLOAD_16(v6, 0x17db, 0x9069, 0x8e1f, 0x3584, 0xbb3d, 0x39b2, 0x82cf, 0x015b,
+           0xd556, 0xd603, 0x85d1, 0x66a6, 0x4e3e, 0xb965, 0xaa7b, 0x9d27);
+  VSET(16, e8, m1);
+  int64_t scalar = 5;
+  VLOAD_8(v4, 0x50, 0x56, 0x94, 0x1e, 0x09, 0x8f, 0xe1, 0x9e, 0x86, 0x97, 0x71,
+          0x5e, 0x55, 0x09, 0xdd, 0x23);
+  asm volatile("vwmacc.vx v6, %[A], v4" ::[A] "r"(scalar));
+  VSET(16, e16, m1);
+  VCMP_I16(7, v6, 0x196b, 0x9217, 0x8c03, 0x361a, 0xbb6a, 0x377d, 0x8234,
+           0xff71, 0xd2f4, 0xd3f6, 0x8806, 0x687c, 0x4fe7, 0xb992, 0xa9cc,
+           0x9dd6);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v6, 0xc9b9ade8, 0xfc9c14a8, 0xe1ace4f7, 0x43ea8b48, 0x3ab3025c,
+           0xe545695b, 0x538304ce, 0xf430c148, 0xd126fac1, 0xbf51d251,
+           0x85ebc0a4, 0x2167faaf, 0x0a2e18cc, 0x0ae19395, 0x03cc9899,
+           0x05524f83);
+  VSET(16, e16, m1);
+  scalar = -5383;
+  VLOAD_16(v4, 0x4324, 0xd762, 0xc34b, 0x6f67, 0x5134, 0x4d9d, 0xfa05, 0xacb7,
+           0xb7d2, 0xb079, 0x5bb2, 0x7949, 0x51df, 0xbadd, 0xee81, 0x3b49);
+  asm volatile("vwmacc.vx v6, %[A], v4" ::[A] "r"(scalar));
+  VSET(16, e32, m1);
+  VCMP_I32(8, v6, 0xc435e3ec, 0xfff226fa, 0xe6a966ea, 0x3ac40c77, 0x340785f0,
+           0xdee56910, 0x5400c5ab, 0xfb080547, 0xd714ba03, 0xc5da1202,
+           0x7e63a4c6, 0x1771acb0, 0x037490b3, 0x108f568a, 0x053c7e12,
+           0x0073b384);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v6, 0xc3afd90f697a742a, 0x585e39767c2959ab, 0xfd5f5c31e16d95ba,
+           0x2c39235d58ff74a1, 0x4a793d202092aeac, 0x6d31f07b7bdfb6ea,
+           0x902b8e28be41b10d, 0x89114b9383c4b511, 0x1f9a7e912f5a51f0,
+           0x5494b9380432890c, 0xfd260f5f1fc1eb45, 0x80381e728c1baa95,
+           0xa6be6d48744a823b, 0xd37b8ae766a82bf8, 0x7992c128f1c1f6ab,
+           0xbeca06f79871e7e8);
+  VSET(16, e32, m1);
+  scalar = 6474219;
+  VLOAD_32(v4, 0x56545434, 0x99cd1438, 0xa1d42f8a, 0x3500b207, 0x642cd563,
+           0x7405746d, 0xe92c3246, 0xdab496dc, 0xcbe26107, 0x6bb989c7,
+           0xc8542e0c, 0x5849a179, 0x04aac7de, 0x7b5ce579, 0x0ce6e7ea,
+           0x77402b10);
+  asm volatile("vwmacc.vx v6, %[A], v4" ::[A] "r"(scalar));
+  VSET(16, e64, m1);
+  VCMP_I64(9, v6, 0xc3d1296f1ae893e6, 0x5836c95c6dbae113, 0xfd3b05253b5c9368,
+           0x2c4d976fb318600e, 0x4a9fe54cf92b4b8d, 0x6d5eb614d7052bf9,
+           0x9022bf12bc18cd4f, 0x8902e74ad235ed05, 0x1f86621f3b05e25d,
+           0x54be4b3652df41b9, 0xfd1093afbdc79c49, 0x805a304537cce5a8,
+           0xa6c03a5756f94905, 0xd3ab25c46d6cd30b, 0x7997bbbadd639479,
+           0xbef80b96ee48ff98);
+}
+
+void TEST_CASE4() {
+  VSET(16, e16, m1);
+  VLOAD_16(v6, 0x17db, 0x9069, 0x8e1f, 0x3584, 0xbb3d, 0x39b2, 0x82cf, 0x015b,
+           0xd556, 0xd603, 0x85d1, 0x66a6, 0x4e3e, 0xb965, 0xaa7b, 0x9d27);
+  VSET(16, e8, m1);
+  int64_t scalar = 5;
+  VLOAD_8(v4, 0x50, 0x56, 0x94, 0x1e, 0x09, 0x8f, 0xe1, 0x9e, 0x86, 0x97, 0x71,
+          0x5e, 0x55, 0x09, 0xdd, 0x23);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vwmacc.vx v6, %[A], v4, v0.t" ::[A] "r"(scalar));
+  VSET(16, e16, m1);
+  VCMP_I16(10, v6, 0x17db, 0x9217, 0x8e1f, 0x361a, 0xbb3d, 0x377d, 0x82cf,
+           0xff71, 0xd556, 0xd3f6, 0x85d1, 0x687c, 0x4e3e, 0xb992, 0xaa7b,
+           0x9dd6);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v6, 0xc9b9ade8, 0xfc9c14a8, 0xe1ace4f7, 0x43ea8b48, 0x3ab3025c,
+           0xe545695b, 0x538304ce, 0xf430c148, 0xd126fac1, 0xbf51d251,
+           0x85ebc0a4, 0x2167faaf, 0x0a2e18cc, 0x0ae19395, 0x03cc9899,
+           0x05524f83);
+  VSET(16, e16, m1);
+  scalar = -5383;
+  VLOAD_16(v4, 0x4324, 0xd762, 0xc34b, 0x6f67, 0x5134, 0x4d9d, 0xfa05, 0xacb7,
+           0xb7d2, 0xb079, 0x5bb2, 0x7949, 0x51df, 0xbadd, 0xee81, 0x3b49);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vwmacc.vx v6, %[A], v4, v0.t" ::[A] "r"(scalar));
+  VSET(16, e32, m1);
+  VCMP_I32(11, v6, 0xc9b9ade8, 0xfff226fa, 0xe1ace4f7, 0x3ac40c77, 0x3ab3025c,
+           0xdee56910, 0x538304ce, 0xfb080547, 0xd126fac1, 0xc5da1202,
+           0x85ebc0a4, 0x1771acb0, 0x0a2e18cc, 0x108f568a, 0x03cc9899,
+           0x0073b384);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v6, 0xc3afd90f697a742a, 0x585e39767c2959ab, 0xfd5f5c31e16d95ba,
+           0x2c39235d58ff74a1, 0x4a793d202092aeac, 0x6d31f07b7bdfb6ea,
+           0x902b8e28be41b10d, 0x89114b9383c4b511, 0x1f9a7e912f5a51f0,
+           0x5494b9380432890c, 0xfd260f5f1fc1eb45, 0x80381e728c1baa95,
+           0xa6be6d48744a823b, 0xd37b8ae766a82bf8, 0x7992c128f1c1f6ab,
+           0xbeca06f79871e7e8);
+  VSET(16, e32, m1);
+  scalar = 6474219;
+  VLOAD_32(v4, 0x56545434, 0x99cd1438, 0xa1d42f8a, 0x3500b207, 0x642cd563,
+           0x7405746d, 0xe92c3246, 0xdab496dc, 0xcbe26107, 0x6bb989c7,
+           0xc8542e0c, 0x5849a179, 0x04aac7de, 0x7b5ce579, 0x0ce6e7ea,
+           0x77402b10);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vwmacc.vx v6, %[A], v4, v0.t" ::[A] "r"(scalar));
+  VSET(16, e64, m1);
+  VCMP_I64(12, v6, 0xc3afd90f697a742a, 0x5836c95c6dbae113, 0xfd5f5c31e16d95ba,
+           0x2c4d976fb318600e, 0x4a793d202092aeac, 0x6d5eb614d7052bf9,
+           0x902b8e28be41b10d, 0x8902e74ad235ed05, 0x1f9a7e912f5a51f0,
+           0x54be4b3652df41b9, 0xfd260f5f1fc1eb45, 0x805a304537cce5a8,
+           0xa6be6d48744a823b, 0xd3ab25c46d6cd30b, 0x7992c128f1c1f6ab,
+           0xbef80b96ee48ff98);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vwmaccsu.c b/apps/riscv-tests/isa/rv64uv/vwmaccsu.c
new file mode 100644
index 0000000..e87bc9e
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vwmaccsu.c
@@ -0,0 +1,248 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1() {
+  VSET(16, e16, m1);
+  VLOAD_16(v6, 0x30dc, 0x7235, 0xd5f6, 0xa008, 0x6e79, 0xa159, 0xa05c, 0x5914,
+           0xd06f, 0x69c5, 0x9475, 0x5625, 0xa5bd, 0x7be7, 0x823c, 0x5fb2);
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xb6, 0xbb, 0xb6, 0x57, 0xf9, 0x7c, 0xbf, 0x62, 0x1a, 0xeb, 0xa4,
+          0x34, 0xde, 0x96, 0x80, 0xe6);
+  VLOAD_8(v4, 0x26, 0xea, 0xe8, 0x85, 0x2e, 0xf1, 0x46, 0x8f, 0x68, 0x29, 0xbb,
+          0x9b, 0xec, 0x5c, 0x8e, 0x77);
+  asm volatile("vwmaccsu.vv v6, v2, v4");
+  VSET(16, e16, m1);
+  VCMP_I16(1, v6, 0x25e0, 0x3323, 0x92e6, 0xcd3b, 0x6d37, 0x1615, 0x8e96,
+           0x8fd2, 0xdaff, 0x6668, 0x5141, 0x75a1, 0x8665, 0x55cf, 0x3b3c,
+           0x539c);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v6, 0xdbc5b23d, 0x86bd7dad, 0xb744b5c2, 0xc32f4a47, 0x237edfc4,
+           0x5d6e851a, 0xbd3110cd, 0x18c61b57, 0x7ade2943, 0x7e4f5ed6,
+           0x90e5ba77, 0xce45b744, 0x82d1976e, 0xa88bb4e1, 0x989fbb9a,
+           0xab29da17);
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x23fb, 0xcee7, 0xa704, 0xc00f, 0xed9f, 0x2cf0, 0x4b53, 0xc0ba,
+           0x775b, 0x557c, 0x57b7, 0xbb06, 0xf9ba, 0x178f, 0xec73, 0x8240);
+  VLOAD_16(v4, 0xad9d, 0x104d, 0xdc56, 0x96af, 0x8c68, 0x1d25, 0x2d70, 0x467a,
+           0xc27c, 0x96e2, 0x1c85, 0xe8b6, 0xf7e0, 0xd069, 0x0bca, 0x4f36);
+  asm volatile("vwmaccsu.vv v6, v2, v4");
+  VSET(16, e32, m1);
+  VCMP_I32(2, v6, 0xf42c622c, 0x839d2928, 0x6aae411a, 0x9d8c5e88, 0x196a5c5c,
+           0x628c33ca, 0xca8f9c1d, 0x075acffb, 0xd58aef57, 0xb0b17e4e,
+           0x9aab508a, 0x8f921d88, 0x7cbe902e, 0xbbb98e88, 0x97b93f58,
+           0x84411397);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v6, 0xf8e162af4fefb46a, 0x8e859cff3b076a9d, 0xa7279ec622e749eb,
+           0x67bbdace6d6bf1a9, 0xf2090d8d3b00e5b8, 0x9259e92430c5a337,
+           0x7cc51e4cc8fd46c6, 0xe5c6946a8e9787fd, 0x0d36e747a75534cc,
+           0x9c1a70c0989504f9, 0xa7b0f15e7b51c000, 0x4566f8ffa299d104,
+           0xf385b581a4c1c25b, 0xb067f1a7621f9cdd, 0x54ffc96dc442d7b5,
+           0x3fc18a6aa65ab8d5);
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x189138d0, 0xe2f3f48f, 0x58448029, 0x44298d07, 0x6f6b15cf,
+           0x13e9cf30, 0x23b6edb8, 0xd532420a, 0xdab302ee, 0xa5e6854e,
+           0x538f91b0, 0xc5d4db0e, 0xbc6d31b3, 0x754d418c, 0x96198b07,
+           0xf54f785a);
+  VLOAD_32(v4, 0x52d1517d, 0xa592227e, 0xbb122792, 0x531a3046, 0x88193da7,
+           0x13db3502, 0x64efb3f9, 0x55c57a21, 0x31cd5a79, 0x5c0b4048,
+           0x899cfb88, 0xfab9de9d, 0x6fa41232, 0x9462cda3, 0x0f8de6ea,
+           0x8064029f);
+  asm volatile("vwmaccsu.vv v6, v2, v4");
+  VSET(16, e64, m1);
+  VCMP_I64(3, v6, 0x00d3fd4343a241fa, 0x7bbc44d6fa22c6ff, 0xe7a7ead9df60a04d,
+           0x7ddc4c9a72efd193, 0x2d44ed6d874572c1, 0x93e550a88e8e3197,
+           0x8ada040c3cea26be, 0xd76f3f99213ccf47, 0x05f53f01db8f434a,
+           0x7bb552f0a51802e9, 0xd49c03ec9aaeb580, 0x0c6e9b2885384c9a,
+           0xd60dbf3493400d51, 0xf465e158f7657501, 0x4e90951ee65f361b,
+           0x3a651986a4cf2cbb);
+}
+
+void TEST_CASE2() {
+  VSET(16, e16, m1);
+  VLOAD_16(v6, 0x30dc, 0x7235, 0xd5f6, 0xa008, 0x6e79, 0xa159, 0xa05c, 0x5914,
+           0xd06f, 0x69c5, 0x9475, 0x5625, 0xa5bd, 0x7be7, 0x823c, 0x5fb2);
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xb6, 0xbb, 0xb6, 0x57, 0xf9, 0x7c, 0xbf, 0x62, 0x1a, 0xeb, 0xa4,
+          0x34, 0xde, 0x96, 0x80, 0xe6);
+  VLOAD_8(v4, 0x26, 0xea, 0xe8, 0x85, 0x2e, 0xf1, 0x46, 0x8f, 0x68, 0x29, 0xbb,
+          0x9b, 0xec, 0x5c, 0x8e, 0x77);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vwmaccsu.vv v6, v2, v4, v0.t");
+  VSET(16, e16, m1);
+  VCMP_I16(4, v6, 0x30dc, 0x3323, 0xd5f6, 0xcd3b, 0x6e79, 0x1615, 0xa05c,
+           0x8fd2, 0xd06f, 0x6668, 0x9475, 0x75a1, 0xa5bd, 0x55cf, 0x823c,
+           0x539c);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v6, 0xdbc5b23d, 0x86bd7dad, 0xb744b5c2, 0xc32f4a47, 0x237edfc4,
+           0x5d6e851a, 0xbd3110cd, 0x18c61b57, 0x7ade2943, 0x7e4f5ed6,
+           0x90e5ba77, 0xce45b744, 0x82d1976e, 0xa88bb4e1, 0x989fbb9a,
+           0xab29da17);
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x23fb, 0xcee7, 0xa704, 0xc00f, 0xed9f, 0x2cf0, 0x4b53, 0xc0ba,
+           0x775b, 0x557c, 0x57b7, 0xbb06, 0xf9ba, 0x178f, 0xec73, 0x8240);
+  VLOAD_16(v4, 0xad9d, 0x104d, 0xdc56, 0x96af, 0x8c68, 0x1d25, 0x2d70, 0x467a,
+           0xc27c, 0x96e2, 0x1c85, 0xe8b6, 0xf7e0, 0xd069, 0x0bca, 0x4f36);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vwmaccsu.vv v6, v2, v4, v0.t");
+  VSET(16, e32, m1);
+  VCMP_I32(5, v6, 0xdbc5b23d, 0x839d2928, 0xb744b5c2, 0x9d8c5e88, 0x237edfc4,
+           0x628c33ca, 0xbd3110cd, 0x075acffb, 0x7ade2943, 0xb0b17e4e,
+           0x90e5ba77, 0x8f921d88, 0x82d1976e, 0xbbb98e88, 0x989fbb9a,
+           0x84411397);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v6, 0xf8e162af4fefb46a, 0x8e859cff3b076a9d, 0xa7279ec622e749eb,
+           0x67bbdace6d6bf1a9, 0xf2090d8d3b00e5b8, 0x9259e92430c5a337,
+           0x7cc51e4cc8fd46c6, 0xe5c6946a8e9787fd, 0x0d36e747a75534cc,
+           0x9c1a70c0989504f9, 0xa7b0f15e7b51c000, 0x4566f8ffa299d104,
+           0xf385b581a4c1c25b, 0xb067f1a7621f9cdd, 0x54ffc96dc442d7b5,
+           0x3fc18a6aa65ab8d5);
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x189138d0, 0xe2f3f48f, 0x58448029, 0x44298d07, 0x6f6b15cf,
+           0x13e9cf30, 0x23b6edb8, 0xd532420a, 0xdab302ee, 0xa5e6854e,
+           0x538f91b0, 0xc5d4db0e, 0xbc6d31b3, 0x754d418c, 0x96198b07,
+           0xf54f785a);
+  VLOAD_32(v4, 0x52d1517d, 0xa592227e, 0xbb122792, 0x531a3046, 0x88193da7,
+           0x13db3502, 0x64efb3f9, 0x55c57a21, 0x31cd5a79, 0x5c0b4048,
+           0x899cfb88, 0xfab9de9d, 0x6fa41232, 0x9462cda3, 0x0f8de6ea,
+           0x8064029f);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vwmaccsu.vv v6, v2, v4, v0.t");
+  VSET(16, e64, m1);
+  VCMP_I64(6, v6, 0xf8e162af4fefb46a, 0x7bbc44d6fa22c6ff, 0xa7279ec622e749eb,
+           0x7ddc4c9a72efd193, 0xf2090d8d3b00e5b8, 0x93e550a88e8e3197,
+           0x7cc51e4cc8fd46c6, 0xd76f3f99213ccf47, 0x0d36e747a75534cc,
+           0x7bb552f0a51802e9, 0xa7b0f15e7b51c000, 0x0c6e9b2885384c9a,
+           0xf385b581a4c1c25b, 0xf465e158f7657501, 0x54ffc96dc442d7b5,
+           0x3a651986a4cf2cbb);
+}
+
+void TEST_CASE3() {
+  VSET(16, e16, m1);
+  VLOAD_16(v6, 0xadd2, 0x2112, 0xbbc6, 0xd113, 0xc6f7, 0xbd07, 0xfd9a, 0x0c0e,
+           0xe110, 0xe81b, 0xb432, 0x5c2c, 0x4da9, 0x8c48, 0x6f94, 0x6250);
+  VSET(16, e8, m1);
+  int64_t scalar = 5;
+  VLOAD_8(v4, 0xfe, 0xd1, 0xc2, 0x3b, 0x79, 0x2f, 0xf5, 0xe8, 0x7f, 0x4b, 0x64,
+          0x57, 0x2b, 0x4f, 0x4e, 0xda);
+  asm volatile("vwmaccsu.vx v6, %[A], v4" ::[A] "r"(scalar));
+  VSET(16, e16, m1);
+  VCMP_I16(7, v6, 0xb2c8, 0x2527, 0xbf90, 0xd23a, 0xc954, 0xbdf2, 0x0263,
+           0x1096, 0xe38b, 0xe992, 0xb626, 0x5ddf, 0x4e80, 0x8dd3, 0x711a,
+           0x6692);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v6, 0x39d3ea89, 0x451d8e1a, 0x83edb2d7, 0xc1919ab3, 0x243c3d4d,
+           0xd4745be8, 0x50a58cbe, 0x53b75e9f, 0x2a648b62, 0xd74ce1cf,
+           0xa2c6a2e7, 0xc30eadb0, 0x7a908fb9, 0xd4455b56, 0x48109ee2,
+           0x2f5b537a);
+  VSET(16, e16, m1);
+  scalar = -5383;
+  VLOAD_16(v4, 0x29f8, 0x6958, 0x6635, 0x03a0, 0x07bc, 0x4881, 0x7d4e, 0x37e3,
+           0x8370, 0x405f, 0x1f0d, 0x1252, 0xacf1, 0x06ee, 0x790d, 0x73af);
+  asm volatile("vwmaccsu.vx v6, %[A], v4" ::[A] "r"(scalar));
+  VSET(16, e32, m1);
+  VCMP_I32(8, v6, 0x36616cc1, 0x3c7674b2, 0x7b888e64, 0xc1456153, 0x23999b29,
+           0xce7fcb61, 0x465ab99c, 0x4f20386a, 0x1f98c352, 0xd2035436,
+           0xa039b88c, 0xc18d7372, 0x6c5c1022, 0xd3b3a4d4, 0x3e1f3e87,
+           0x25daceb1);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v6, 0xd860771ff910e8a1, 0xd8de9ddf3be66e90, 0xe55e25348ff4c406,
+           0x6ee24d9ebeda1c54, 0x78437fc8299017d1, 0x46a2833ed69dec1d,
+           0x0331761dcc2485b7, 0x99c00b7ecbecb5bf, 0xd68d230a95510605,
+           0x0e82f981980d47c8, 0x7bb0e1dd5f273626, 0x044cc7c24be55121,
+           0x341b063e01c35796, 0xb77a96fdf1826215, 0xdcbd3fe115470433,
+           0xc2797417b552325b);
+  VSET(16, e32, m1);
+  scalar = 6474219;
+  VLOAD_32(v4, 0x53046c2d, 0x3b0c65ed, 0x6565f981, 0xaa4c1d70, 0x0a18c71e,
+           0xbc91ff46, 0xa52c32d1, 0x73cca3fc, 0xb2a7e5d2, 0x1939af0a,
+           0xe4fdb1f5, 0x783f5c5d, 0x3514c875, 0xce346d04, 0x68047428,
+           0x72ca548f);
+  asm volatile("vwmaccsu.vx v6, %[A], v4" ::[A] "r"(scalar));
+  VSET(16, e64, m1);
+  VCMP_I64(9, v6, 0xd880804c10498af0, 0xd8f567313109141f, 0xe585463838d91671,
+           0x6f2405141ab61224, 0x7847653b1c216e5b, 0x46eb47de4add375f,
+           0x03713350939f4492, 0x99ecbb2b8c001a13, 0xd6d2143a6346dfcb,
+           0x0e8cb57c0c43cff6, 0x7c093f98e48cef0d, 0x047b2edbc92e1f80,
+           0x342f8210ca0537fd, 0xb7ca29b420c298c1, 0xdce563a087e10ceb,
+           0xc2a5c016503018a0);
+}
+
+void TEST_CASE4() {
+  VSET(16, e16, m1);
+  VLOAD_16(v6, 0xadd2, 0x2112, 0xbbc6, 0xd113, 0xc6f7, 0xbd07, 0xfd9a, 0x0c0e,
+           0xe110, 0xe81b, 0xb432, 0x5c2c, 0x4da9, 0x8c48, 0x6f94, 0x6250);
+  VSET(16, e8, m1);
+  int64_t scalar = 5;
+  VLOAD_8(v4, 0xfe, 0xd1, 0xc2, 0x3b, 0x79, 0x2f, 0xf5, 0xe8, 0x7f, 0x4b, 0x64,
+          0x57, 0x2b, 0x4f, 0x4e, 0xda);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vwmaccsu.vx v6, %[A], v4, v0.t" ::[A] "r"(scalar));
+  VSET(16, e16, m1);
+  VCMP_I16(10, v6, 0xadd2, 0x2527, 0xbbc6, 0xd23a, 0xc6f7, 0xbdf2, 0xfd9a,
+           0x1096, 0xe110, 0xe992, 0xb432, 0x5ddf, 0x4da9, 0x8dd3, 0x6f94,
+           0x6692);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v6, 0x39d3ea89, 0x451d8e1a, 0x83edb2d7, 0xc1919ab3, 0x243c3d4d,
+           0xd4745be8, 0x50a58cbe, 0x53b75e9f, 0x2a648b62, 0xd74ce1cf,
+           0xa2c6a2e7, 0xc30eadb0, 0x7a908fb9, 0xd4455b56, 0x48109ee2,
+           0x2f5b537a);
+  VSET(16, e16, m1);
+  scalar = -5383;
+  VLOAD_16(v4, 0x29f8, 0x6958, 0x6635, 0x03a0, 0x07bc, 0x4881, 0x7d4e, 0x37e3,
+           0x8370, 0x405f, 0x1f0d, 0x1252, 0xacf1, 0x06ee, 0x790d, 0x73af);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vwmaccsu.vx v6, %[A], v4, v0.t" ::[A] "r"(scalar));
+  VSET(16, e32, m1);
+  VCMP_I32(11, v6, 0x39d3ea89, 0x3c7674b2, 0x83edb2d7, 0xc1456153, 0x243c3d4d,
+           0xce7fcb61, 0x50a58cbe, 0x4f20386a, 0x2a648b62, 0xd2035436,
+           0xa2c6a2e7, 0xc18d7372, 0x7a908fb9, 0xd3b3a4d4, 0x48109ee2,
+           0x25daceb1);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v6, 0xd860771ff910e8a1, 0xd8de9ddf3be66e90, 0xe55e25348ff4c406,
+           0x6ee24d9ebeda1c54, 0x78437fc8299017d1, 0x46a2833ed69dec1d,
+           0x0331761dcc2485b7, 0x99c00b7ecbecb5bf, 0xd68d230a95510605,
+           0x0e82f981980d47c8, 0x7bb0e1dd5f273626, 0x044cc7c24be55121,
+           0x341b063e01c35796, 0xb77a96fdf1826215, 0xdcbd3fe115470433,
+           0xc2797417b552325b);
+  VSET(16, e32, m1);
+  scalar = 6474219;
+  VLOAD_32(v4, 0x53046c2d, 0x3b0c65ed, 0x6565f981, 0xaa4c1d70, 0x0a18c71e,
+           0xbc91ff46, 0xa52c32d1, 0x73cca3fc, 0xb2a7e5d2, 0x1939af0a,
+           0xe4fdb1f5, 0x783f5c5d, 0x3514c875, 0xce346d04, 0x68047428,
+           0x72ca548f);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vwmaccsu.vx v6, %[A], v4, v0.t" ::[A] "r"(scalar));
+  VSET(16, e64, m1);
+  VCMP_I64(12, v6, 0xd860771ff910e8a1, 0xd8f567313109141f, 0xe55e25348ff4c406,
+           0x6f2405141ab61224, 0x78437fc8299017d1, 0x46eb47de4add375f,
+           0x0331761dcc2485b7, 0x99ecbb2b8c001a13, 0xd68d230a95510605,
+           0x0e8cb57c0c43cff6, 0x7bb0e1dd5f273626, 0x047b2edbc92e1f80,
+           0x341b063e01c35796, 0xb7ca29b420c298c1, 0xdcbd3fe115470433,
+           0xc2a5c016503018a0);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vwmaccu.c b/apps/riscv-tests/isa/rv64uv/vwmaccu.c
new file mode 100644
index 0000000..8afd184
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vwmaccu.c
@@ -0,0 +1,248 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1() {
+  VSET(16, e16, m1);
+  VLOAD_16(v6, 0x519d, 0x7122, 0x672c, 0x4d97, 0x436e, 0x3f1f, 0x423d, 0x44e8,
+           0x3d7b, 0x5570, 0x1e90, 0x79f4, 0x456b, 0x0283, 0x02b5, 0x6865);
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xce, 0x96, 0x33, 0x88, 0xf8, 0x3f, 0x0c, 0xde, 0x1e, 0x9d, 0x5a,
+          0x75, 0x73, 0x43, 0xd9, 0x43);
+  VLOAD_8(v4, 0x51, 0x88, 0x16, 0xf6, 0x57, 0xab, 0xd8, 0x26, 0x2e, 0x35, 0x94,
+          0xd1, 0xf0, 0xb9, 0x09, 0x8a);
+  asm volatile("vwmaccu.vv v6, v2, v4");
+  VSET(16, e16, m1);
+  VCMP_U16(1, v6, 0x92cb, 0xc0d2, 0x6b8e, 0xd047, 0x97b6, 0x6934, 0x4c5d,
+           0x65dc, 0x42df, 0x75f1, 0x5298, 0xd979, 0xb13b, 0x32ee, 0x0a56,
+           0x8c83);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v6, 0x1f50b763, 0x6d1a7f46, 0x17b8b2b5, 0x6b69c966, 0x25d945cb,
+           0x3e6c375b, 0x314db8d3, 0x35ade27d, 0x74fa2d58, 0x735f513d,
+           0x3cad4e4d, 0x628eb81a, 0x1c48c2f9, 0x14f08921, 0x77de05bf,
+           0x528c354b);
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x4ed5, 0xcf74, 0x3442, 0x280f, 0x795e, 0x3007, 0xdf3e, 0xb348,
+           0x3865, 0xcb59, 0x1291, 0xa04b, 0xc5bd, 0x957f, 0xefe4, 0xe75d);
+  VLOAD_16(v4, 0x7d39, 0xddd8, 0x17d7, 0x0574, 0x251a, 0x4ce4, 0x4817, 0x9de1,
+           0xd773, 0xdcc8, 0xeb92, 0x8fa8, 0x9382, 0x4369, 0xb1c7, 0x9185);
+  asm volatile("vwmaccu.vv v6, v2, v4");
+  VSET(16, e32, m1);
+  VCMP_U32(2, v6, 0x45e045d0, 0x20e0ad26, 0x1c968423, 0x6c443b32, 0x37702f57,
+           0x4cd91197, 0x702b3765, 0xa43e9cc5, 0xa47055b7, 0x22beaac5,
+           0x4dc2ffff, 0xbc81ce52, 0x8e38b3f3, 0x3c4e1738, 0x1e7523fb,
+           0xd610159c);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v6, 0x5118504f9237ea08, 0x6b71d4ee88073dde, 0x4420559f61e6927c,
+           0x24eea54c6530475c, 0x289211cb16ebbbc9, 0x1a0b2b7644ecd474,
+           0x159c16af3e71f736, 0x12dda0d2ca288012, 0x790fab107c1346b6,
+           0x589cc8132c869645, 0x323623bba87568ce, 0x5ce2e94d5e335c5d,
+           0x6e6b3c19c0d78ca0, 0x0502bed40a0600bc, 0x5ff6f4b3610e009c,
+           0x40d6eb0605052915);
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0xd1247b78, 0xfd5d326b, 0x7fe40cf5, 0xfd802d90, 0x9ec23b7e,
+           0x67219fe8, 0x9dc7f026, 0x257d8b7f, 0x782bc512, 0x42fa808b,
+           0x48d3273d, 0x7ca0371d, 0x06409254, 0xb77ce3ba, 0x28aac174,
+           0xd2e4cdbf);
+  VLOAD_32(v4, 0xab3b5969, 0xe91aa966, 0x336c2f4c, 0xfcc75a99, 0x1854180c,
+           0xeec0354b, 0x8b4595bf, 0x9200fb5c, 0x0d627fcf, 0xdf0a8280,
+           0x4b5733be, 0x4f3bd496, 0x10f5d788, 0x3499c99d, 0xdeee29dd,
+           0x7e8643a4);
+  asm volatile("vwmaccu.vv v6, v2, v4");
+  VSET(16, e64, m1);
+  VCMP_U64(3, v6, 0xdcfc2b3ca5c34640, 0x52260af0834ff780, 0x5dd0d00a7e576638,
+           0x1f3e3a8021c0226c, 0x37a86e0412f255b1, 0x7a39dcd00fe1b56c,
+           0x6b728942b1a24190, 0x283f5f30c90c26b6, 0x7f5820d2b91f8e44,
+           0x92f7bdf9f97b71c5, 0x47a4ceb4fab8af14, 0x83757ab9b866ab5b,
+           0x6ed5464e986dd540, 0x2ab6573b8294b3ce, 0x8360dddc474a95c0,
+           0xa91223c6b56bf471);
+}
+
+void TEST_CASE2() {
+  VSET(16, e16, m1);
+  VLOAD_16(v6, 0x519d, 0x7122, 0x672c, 0x4d97, 0x436e, 0x3f1f, 0x423d, 0x44e8,
+           0x3d7b, 0x5570, 0x1e90, 0x79f4, 0x456b, 0x0283, 0x02b5, 0x6865);
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xce, 0x96, 0x33, 0x88, 0xf8, 0x3f, 0x0c, 0xde, 0x1e, 0x9d, 0x5a,
+          0x75, 0x73, 0x43, 0xd9, 0x43);
+  VLOAD_8(v4, 0x51, 0x88, 0x16, 0xf6, 0x57, 0xab, 0xd8, 0x26, 0x2e, 0x35, 0x94,
+          0xd1, 0xf0, 0xb9, 0x09, 0x8a);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vwmaccu.vv v6, v2, v4, v0.t");
+  VSET(16, e16, m1);
+  VCMP_U16(4, v6, 0x519d, 0xc0d2, 0x672c, 0xd047, 0x436e, 0x6934, 0x423d,
+           0x65dc, 0x3d7b, 0x75f1, 0x1e90, 0xd979, 0x456b, 0x32ee, 0x02b5,
+           0x8c83);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v6, 0x1f50b763, 0x6d1a7f46, 0x17b8b2b5, 0x6b69c966, 0x25d945cb,
+           0x3e6c375b, 0x314db8d3, 0x35ade27d, 0x74fa2d58, 0x735f513d,
+           0x3cad4e4d, 0x628eb81a, 0x1c48c2f9, 0x14f08921, 0x77de05bf,
+           0x528c354b);
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x4ed5, 0xcf74, 0x3442, 0x280f, 0x795e, 0x3007, 0xdf3e, 0xb348,
+           0x3865, 0xcb59, 0x1291, 0xa04b, 0xc5bd, 0x957f, 0xefe4, 0xe75d);
+  VLOAD_16(v4, 0x7d39, 0xddd8, 0x17d7, 0x0574, 0x251a, 0x4ce4, 0x4817, 0x9de1,
+           0xd773, 0xdcc8, 0xeb92, 0x8fa8, 0x9382, 0x4369, 0xb1c7, 0x9185);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vwmaccu.vv v6, v2, v4, v0.t");
+  VSET(16, e32, m1);
+  VCMP_U32(5, v6, 0x1f50b763, 0x20e0ad26, 0x17b8b2b5, 0x6c443b32, 0x25d945cb,
+           0x4cd91197, 0x314db8d3, 0xa43e9cc5, 0x74fa2d58, 0x22beaac5,
+           0x3cad4e4d, 0xbc81ce52, 0x1c48c2f9, 0x3c4e1738, 0x77de05bf,
+           0xd610159c);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v6, 0x5118504f9237ea08, 0x6b71d4ee88073dde, 0x4420559f61e6927c,
+           0x24eea54c6530475c, 0x289211cb16ebbbc9, 0x1a0b2b7644ecd474,
+           0x159c16af3e71f736, 0x12dda0d2ca288012, 0x790fab107c1346b6,
+           0x589cc8132c869645, 0x323623bba87568ce, 0x5ce2e94d5e335c5d,
+           0x6e6b3c19c0d78ca0, 0x0502bed40a0600bc, 0x5ff6f4b3610e009c,
+           0x40d6eb0605052915);
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0xd1247b78, 0xfd5d326b, 0x7fe40cf5, 0xfd802d90, 0x9ec23b7e,
+           0x67219fe8, 0x9dc7f026, 0x257d8b7f, 0x782bc512, 0x42fa808b,
+           0x48d3273d, 0x7ca0371d, 0x06409254, 0xb77ce3ba, 0x28aac174,
+           0xd2e4cdbf);
+  VLOAD_32(v4, 0xab3b5969, 0xe91aa966, 0x336c2f4c, 0xfcc75a99, 0x1854180c,
+           0xeec0354b, 0x8b4595bf, 0x9200fb5c, 0x0d627fcf, 0xdf0a8280,
+           0x4b5733be, 0x4f3bd496, 0x10f5d788, 0x3499c99d, 0xdeee29dd,
+           0x7e8643a4);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vwmaccu.vv v6, v2, v4, v0.t");
+  VSET(16, e64, m1);
+  VCMP_U64(6, v6, 0x5118504f9237ea08, 0x52260af0834ff780, 0x4420559f61e6927c,
+           0x1f3e3a8021c0226c, 0x289211cb16ebbbc9, 0x7a39dcd00fe1b56c,
+           0x159c16af3e71f736, 0x283f5f30c90c26b6, 0x790fab107c1346b6,
+           0x92f7bdf9f97b71c5, 0x323623bba87568ce, 0x83757ab9b866ab5b,
+           0x6e6b3c19c0d78ca0, 0x2ab6573b8294b3ce, 0x5ff6f4b3610e009c,
+           0xa91223c6b56bf471);
+}
+
+void TEST_CASE3() {
+  VSET(16, e16, m1);
+  VLOAD_16(v6, 0x6f50, 0x0299, 0x3578, 0x0e45, 0x752b, 0x60c7, 0x7d0c, 0x0943,
+           0x3f2d, 0x47bc, 0x4468, 0x616d, 0x5844, 0x3a7d, 0x32fe, 0x7813);
+  VSET(16, e8, m1);
+  uint64_t scalar = 5;
+  VLOAD_8(v4, 0x01, 0xd6, 0x1e, 0x57, 0xcc, 0x31, 0x29, 0x06, 0x5a, 0xab, 0x1e,
+          0x0a, 0x97, 0x6f, 0xe0, 0xfc);
+  asm volatile("vwmaccu.vx v6, %[A], v4" ::[A] "r"(scalar));
+  VSET(16, e16, m1);
+  VCMP_U16(7, v6, 0x6f55, 0x06c7, 0x360e, 0x0ff8, 0x7927, 0x61bc, 0x7dd9,
+           0x0961, 0x40ef, 0x4b13, 0x44fe, 0x619f, 0x5b37, 0x3ca8, 0x375e,
+           0x7cff);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v6, 0x681721c9, 0x5c07924a, 0x5147143e, 0x14da5785, 0x30a43e20,
+           0x3498177e, 0x551df71d, 0x29656468, 0x12550807, 0x7dc95cbd,
+           0x2167ff36, 0x194b0d6c, 0x79119a1d, 0x6d77fab6, 0x3e32c755,
+           0x6e479bf4);
+  VSET(16, e16, m1);
+  scalar = 5383;
+  VLOAD_16(v4, 0x9752, 0x45a4, 0xfde9, 0xa659, 0x957b, 0x1a3f, 0x2212, 0x5d43,
+           0xdc08, 0x1fb8, 0x5e15, 0x08da, 0x0468, 0x4458, 0xe1e2, 0x4ef7);
+  asm volatile("vwmaccu.vx v6, %[A], v4" ::[A] "r"(scalar));
+  VSET(16, e32, m1);
+  VCMP_U32(8, v6, 0x7484ff07, 0x61bfedc6, 0x6622229d, 0x228430f4, 0x3ceb6b7d,
+           0x36bffa37, 0x57ea5f9b, 0x310e703d, 0x2467b43f, 0x806452c5,
+           0x29224ac9, 0x1a052d62, 0x796e40f5, 0x7315111e, 0x50c07e83,
+           0x74c407b5);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v6, 0x27a0a02f7e9757d4, 0x7ff7bb4d394926a0, 0x09d25e3173571efd,
+           0x11661c8ece6711ac, 0x1e5ffff32ed851dd, 0x0698334d63d206a9,
+           0x79598c88fd85995f, 0x2fa78b4b7d90a222, 0x7d65cbfdfc7f2e1d,
+           0x6c0101ef46924df6, 0x59ff3d4e018b50f4, 0x2c8ec8409f219401,
+           0x20b183b4bb89c200, 0x28bee831261ca372, 0x5b9d142326bcef0a,
+           0x1c2ad051e4e7281e);
+  VSET(16, e32, m1);
+  scalar = 6474219;
+  VLOAD_32(v4, 0x307dc235, 0x92187481, 0xa69319d1, 0x682b9abe, 0x8bdce4be,
+           0x95ec65ce, 0x46915d6f, 0xd59243e6, 0x1d0943e5, 0x3ae27787,
+           0x33c32e03, 0x8be66da2, 0x0fc78147, 0x2ce8d421, 0x9c9bc2fb,
+           0x10c8c9f7);
+  asm volatile("vwmaccu.vx v6, %[A], v4" ::[A] "r"(scalar));
+  VSET(16, e64, m1);
+  VCMP_U64(9, v6, 0x27b3569317ce3b7b, 0x80301be52297620b, 0x0a12a5e3bda6ead8,
+           0x118e4f69e7a94c16, 0x1e95f8d392f37a47, 0x06d20e0c989e38c3,
+           0x7974c7d7abd08544, 0x2ff9f5bd60308c44, 0x7d710070e7f94e54,
+           0x6c17bb12e5fd05e3, 0x5a1336d961fce8b5, 0x2cc4c4ceefc069b7,
+           0x20b79a86595c2d2d, 0x28d03cbe630746bd, 0x5bd98349d9e5fe73,
+           0x1c314a6c44597cdb);
+}
+
+void TEST_CASE4() {
+  VSET(16, e16, m1);
+  VLOAD_16(v6, 0x6f50, 0x0299, 0x3578, 0x0e45, 0x752b, 0x60c7, 0x7d0c, 0x0943,
+           0x3f2d, 0x47bc, 0x4468, 0x616d, 0x5844, 0x3a7d, 0x32fe, 0x7813);
+  VSET(16, e8, m1);
+  uint64_t scalar = 5;
+  VLOAD_8(v4, 0x01, 0xd6, 0x1e, 0x57, 0xcc, 0x31, 0x29, 0x06, 0x5a, 0xab, 0x1e,
+          0x0a, 0x97, 0x6f, 0xe0, 0xfc);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vwmaccu.vx v6, %[A], v4, v0.t" ::[A] "r"(scalar));
+  VSET(16, e16, m1);
+  VCMP_U16(10, v6, 0x6f50, 0x06c7, 0x3578, 0x0ff8, 0x752b, 0x61bc, 0x7d0c,
+           0x0961, 0x3f2d, 0x4b13, 0x4468, 0x619f, 0x5844, 0x3ca8, 0x32fe,
+           0x7cff);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v6, 0x681721c9, 0x5c07924a, 0x5147143e, 0x14da5785, 0x30a43e20,
+           0x3498177e, 0x551df71d, 0x29656468, 0x12550807, 0x7dc95cbd,
+           0x2167ff36, 0x194b0d6c, 0x79119a1d, 0x6d77fab6, 0x3e32c755,
+           0x6e479bf4);
+  VSET(16, e16, m1);
+  scalar = 5383;
+  VLOAD_16(v4, 0x9752, 0x45a4, 0xfde9, 0xa659, 0x957b, 0x1a3f, 0x2212, 0x5d43,
+           0xdc08, 0x1fb8, 0x5e15, 0x08da, 0x0468, 0x4458, 0xe1e2, 0x4ef7);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vwmaccu.vx v6, %[A], v4, v0.t" ::[A] "r"(scalar));
+  VSET(16, e32, m1);
+  VCMP_U32(11, v6, 0x681721c9, 0x61bfedc6, 0x5147143e, 0x228430f4, 0x30a43e20,
+           0x36bffa37, 0x551df71d, 0x310e703d, 0x12550807, 0x806452c5,
+           0x2167ff36, 0x1a052d62, 0x79119a1d, 0x7315111e, 0x3e32c755,
+           0x74c407b5);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v6, 0x27a0a02f7e9757d4, 0x7ff7bb4d394926a0, 0x09d25e3173571efd,
+           0x11661c8ece6711ac, 0x1e5ffff32ed851dd, 0x0698334d63d206a9,
+           0x79598c88fd85995f, 0x2fa78b4b7d90a222, 0x7d65cbfdfc7f2e1d,
+           0x6c0101ef46924df6, 0x59ff3d4e018b50f4, 0x2c8ec8409f219401,
+           0x20b183b4bb89c200, 0x28bee831261ca372, 0x5b9d142326bcef0a,
+           0x1c2ad051e4e7281e);
+  VSET(16, e32, m1);
+  scalar = 6474219;
+  VLOAD_32(v4, 0x307dc235, 0x92187481, 0xa69319d1, 0x682b9abe, 0x8bdce4be,
+           0x95ec65ce, 0x46915d6f, 0xd59243e6, 0x1d0943e5, 0x3ae27787,
+           0x33c32e03, 0x8be66da2, 0x0fc78147, 0x2ce8d421, 0x9c9bc2fb,
+           0x10c8c9f7);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vwmaccu.vx v6, %[A], v4, v0.t" ::[A] "r"(scalar));
+  VSET(16, e64, m1);
+  VCMP_U64(12, v6, 0x27a0a02f7e9757d4, 0x80301be52297620b, 0x09d25e3173571efd,
+           0x118e4f69e7a94c16, 0x1e5ffff32ed851dd, 0x06d20e0c989e38c3,
+           0x79598c88fd85995f, 0x2ff9f5bd60308c44, 0x7d65cbfdfc7f2e1d,
+           0x6c17bb12e5fd05e3, 0x59ff3d4e018b50f4, 0x2cc4c4ceefc069b7,
+           0x20b183b4bb89c200, 0x28d03cbe630746bd, 0x5b9d142326bcef0a,
+           0x1c314a6c44597cdb);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vwmaccus.c b/apps/riscv-tests/isa/rv64uv/vwmaccus.c
new file mode 100644
index 0000000..d1e4be5
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vwmaccus.c
@@ -0,0 +1,127 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1() {
+  VSET(16, e16, m1);
+  VLOAD_16(v6, 0x4c8e, 0xd449, 0xe266, 0xb6d1, 0xf28a, 0x1655, 0x3111, 0x4bde,
+           0x8787, 0x2ce4, 0x1083, 0xaa0c, 0x9fdf, 0x3e42, 0x98e7, 0xe33b);
+  VSET(16, e8, m1);
+  uint64_t scalar = 5;
+  VLOAD_8(v4, 0x83, 0xfe, 0xa2, 0xc3, 0xa6, 0x18, 0xd9, 0x4c, 0x6e, 0xeb, 0x43,
+          0xb7, 0xec, 0x48, 0xb7, 0xe5);
+  asm volatile("vwmaccus.vx v6, %[A], v4" ::[A] "r"(scalar));
+  VSET(16, e16, m1);
+  VCMP_I16(1, v6, 0x4a1d, 0xd43f, 0xe090, 0xb5a0, 0xf0c8, 0x16cd, 0x304e,
+           0x4d5a, 0x89ad, 0x2c7b, 0x11d2, 0xa89f, 0x9f7b, 0x3faa, 0x977a,
+           0xe2b4);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v6, 0xe318cc7a, 0x489815a8, 0x6e6fc053, 0x8d746807, 0xbc3e6244,
+           0xcdfeb4fe, 0x22d24149, 0x26962240, 0x5ef85b7e, 0x2f61a9e8,
+           0x373dc202, 0x1567a6b5, 0x763c5239, 0x60dd0502, 0xab178102,
+           0x753e0a11);
+  VSET(16, e16, m1);
+  scalar = 5383;
+  VLOAD_16(v4, 0xce02, 0x6935, 0xc803, 0x75bc, 0x80b7, 0x19d2, 0x3b7c, 0xc269,
+           0xb639, 0x66f1, 0x678b, 0xc83e, 0x5a5c, 0x389e, 0x9e46, 0xfae9);
+  asm volatile("vwmaccus.vx v6, %[A], v4" ::[A] "r"(scalar));
+  VSET(16, e32, m1);
+  VCMP_I32(2, v6, 0xdefd9888, 0x513c4f1b, 0x69d67768, 0x97200c2b, 0xb1c9ea45,
+           0xd01da3bc, 0x27b50dad, 0x2187101f, 0x58e9040d, 0x37d63f7f,
+           0x3fbefdcf, 0x10d33667, 0x7da856bd, 0x65838754, 0xa31092ec,
+           0x74d30370);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v6, 0xb6a5b1c3c6d69abb, 0x3c6a647eb0d79a41, 0xf0c3eb8821045259,
+           0x91d74be946352cae, 0x524c6db6c58f9da6, 0x39185a920f7787e8,
+           0x4080fbf0fdcc64ec, 0x9ed1fb83f53270fc, 0xff0661a19269f0c0,
+           0x47d26c599193fe0b, 0xd8cc0342dc3104ce, 0xc51f802bc93381cd,
+           0xe7d6522aa1c51245, 0x6fa0a9d3f57bc667, 0xd140731478a147a8,
+           0x5d716379591922f4);
+  VSET(16, e32, m1);
+  scalar = 6474219;
+  VLOAD_32(v4, 0x09377def, 0x99ee4d30, 0x8b8452d1, 0xc9e17667, 0x2254aa29,
+           0xb56ca9f5, 0xa1276371, 0x32ac1413, 0x59ff6af3, 0x6b61bf57,
+           0xc0eb37b3, 0x26f06be7, 0x0e9b21b2, 0x22898a93, 0xe3646841,
+           0xdd301fdc);
+  asm volatile("vwmaccus.vx v6, %[A], v4" ::[A] "r"(scalar));
+  VSET(16, e64, m1);
+  VCMP_I64(3, v6, 0xb6a940470425dc20, 0x3c430136a5932551, 0xf096f84fcc847134,
+           0x91c26988f191bc3b, 0x5259ad33e6940249, 0x38fb9358fb72e8cf,
+           0x405c6235eb4a66a7, 0x9ee5895b4431c96d, 0xff291c64abdfe8d1,
+           0x47fbdc7722d7f1e8, 0xd8b3ab8cf55eb11f, 0xc52e86eb9b0cedda,
+           0xe7dbf512bdc5c2ab, 0x6fadfdb8b3d16658, 0xd13568f3f48a0453,
+           0x5d63f4705f821de8);
+}
+
+void TEST_CASE2() {
+  VSET(16, e16, m1);
+  VLOAD_16(v6, 0x4c8e, 0xd449, 0xe266, 0xb6d1, 0xf28a, 0x1655, 0x3111, 0x4bde,
+           0x8787, 0x2ce4, 0x1083, 0xaa0c, 0x9fdf, 0x3e42, 0x98e7, 0xe33b);
+  VSET(16, e8, m1);
+  uint64_t scalar = 5;
+  VLOAD_8(v4, 0x83, 0xfe, 0xa2, 0xc3, 0xa6, 0x18, 0xd9, 0x4c, 0x6e, 0xeb, 0x43,
+          0xb7, 0xec, 0x48, 0xb7, 0xe5);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vwmaccus.vx v6, %[A], v4, v0.t" ::[A] "r"(scalar));
+  VSET(16, e16, m1);
+  VCMP_I16(4, v6, 0x4c8e, 0xd43f, 0xe266, 0xb5a0, 0xf28a, 0x16cd, 0x3111,
+           0x4d5a, 0x8787, 0x2c7b, 0x1083, 0xa89f, 0x9fdf, 0x3faa, 0x98e7,
+           0xe2b4);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v6, 0xe318cc7a, 0x489815a8, 0x6e6fc053, 0x8d746807, 0xbc3e6244,
+           0xcdfeb4fe, 0x22d24149, 0x26962240, 0x5ef85b7e, 0x2f61a9e8,
+           0x373dc202, 0x1567a6b5, 0x763c5239, 0x60dd0502, 0xab178102,
+           0x753e0a11);
+  VSET(16, e16, m1);
+  scalar = 5383;
+  VLOAD_16(v4, 0xce02, 0x6935, 0xc803, 0x75bc, 0x80b7, 0x19d2, 0x3b7c, 0xc269,
+           0xb639, 0x66f1, 0x678b, 0xc83e, 0x5a5c, 0x389e, 0x9e46, 0xfae9);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vwmaccus.vx v6, %[A], v4, v0.t" ::[A] "r"(scalar));
+  VSET(16, e32, m1);
+  VCMP_I32(5, v6, 0xe318cc7a, 0x513c4f1b, 0x6e6fc053, 0x97200c2b, 0xbc3e6244,
+           0xd01da3bc, 0x22d24149, 0x2187101f, 0x5ef85b7e, 0x37d63f7f,
+           0x373dc202, 0x10d33667, 0x763c5239, 0x65838754, 0xab178102,
+           0x74d30370);
+
+  VSET(16, e64, m1);
+  VLOAD_64(v6, 0xb6a5b1c3c6d69abb, 0x3c6a647eb0d79a41, 0xf0c3eb8821045259,
+           0x91d74be946352cae, 0x524c6db6c58f9da6, 0x39185a920f7787e8,
+           0x4080fbf0fdcc64ec, 0x9ed1fb83f53270fc, 0xff0661a19269f0c0,
+           0x47d26c599193fe0b, 0xd8cc0342dc3104ce, 0xc51f802bc93381cd,
+           0xe7d6522aa1c51245, 0x6fa0a9d3f57bc667, 0xd140731478a147a8,
+           0x5d716379591922f4);
+  VSET(16, e32, m1);
+  scalar = 6474219;
+  VLOAD_32(v4, 0x09377def, 0x99ee4d30, 0x8b8452d1, 0xc9e17667, 0x2254aa29,
+           0xb56ca9f5, 0xa1276371, 0x32ac1413, 0x59ff6af3, 0x6b61bf57,
+           0xc0eb37b3, 0x26f06be7, 0x0e9b21b2, 0x22898a93, 0xe3646841,
+           0xdd301fdc);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  asm volatile("vwmaccus.vx v6, %[A], v4, v0.t" ::[A] "r"(scalar));
+  VSET(16, e64, m1);
+  VCMP_I64(6, v6, 0xb6a5b1c3c6d69abb, 0x3c430136a5932551, 0xf0c3eb8821045259,
+           0x91c26988f191bc3b, 0x524c6db6c58f9da6, 0x38fb9358fb72e8cf,
+           0x4080fbf0fdcc64ec, 0x9ee5895b4431c96d, 0xff0661a19269f0c0,
+           0x47fbdc7722d7f1e8, 0xd8cc0342dc3104ce, 0xc52e86eb9b0cedda,
+           0xe7d6522aa1c51245, 0x6fadfdb8b3d16658, 0xd140731478a147a8,
+           0x5d63f4705f821de8);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vwmul.c b/apps/riscv-tests/isa/rv64uv/vwmul.c
new file mode 100644
index 0000000..c379e39
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vwmul.c
@@ -0,0 +1,182 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xee, 0xfe, 0xbd, 0xc2, 0x02, 0xa4, 0x34, 0x33, 0x2b, 0x35, 0x16,
+          0x9b, 0x3b, 0x5f, 0xfc, 0x8b);
+  VLOAD_8(v4, 0xcb, 0x24, 0xe8, 0xb2, 0xeb, 0x24, 0x80, 0x67, 0x43, 0x11, 0x7c,
+          0x94, 0x22, 0x71, 0xca, 0x80);
+  asm volatile("vwmul.vv v6, v2, v4");
+  VSET(16, e16, m1);
+  VCMP_I16(1, v6, 0x03ba, 0xffb8, 0x0648, 0x12e4, 0xffd6, 0xf310, 0xe600,
+           0x1485, 0x0b41, 0x0385, 0x0aa8, 0x2a9c, 0x07d6, 0x29ef, 0x00d8,
+           0x3a80);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x8aed, 0x2153, 0x5377, 0xc19c, 0x1051, 0x1b75, 0xbafd, 0xb200,
+           0xb209, 0xa9a2, 0xbdc4, 0x1653, 0x5965, 0x145e, 0xb626, 0xd79c);
+  VLOAD_16(v4, 0x778d, 0xc104, 0x6eac, 0x78e8, 0xacd2, 0x698b, 0xc7d3, 0x1e29,
+           0x0a58, 0x58b5, 0x29f9, 0x2fb0, 0x2166, 0x0ac4, 0x44e5, 0xbc40);
+  asm volatile("vwmul.vv v6, v2, v4");
+  VSET(16, e32, m1);
+  VCMP_I32(2, v6, 0xc953af89, 0xf7cd184c, 0x241535f4, 0xe2889560, 0xfab2ce72,
+           0x0b51e587, 0x0f24c987, 0xf6cf8200, 0xfcd98d18, 0xe2129f8a,
+           0xf523f7a4, 0x04289610, 0x0ba9a33e, 0x00db43f8, 0xec2007fe,
+           0x0ab07700);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0xbbc467cb, 0xfbb3efda, 0x652f8490, 0x5e7ea848, 0x21fbc400,
+           0xbb409fde, 0x98413836, 0x14652ba4, 0xc3d3c86f, 0xc84d3ae3,
+           0x3df53027, 0xbda29a2c, 0xa1d7d949, 0x60a3d06e, 0xa91e405d,
+           0x7eea498f);
+  VLOAD_32(v4, 0x80407791, 0x3e51b6e0, 0xd0be8bc1, 0x683f33bd, 0xeddda6c8,
+           0x34e351f2, 0xa6a93ab2, 0xc8893cb8, 0xcb61ddc1, 0x341a4cdc,
+           0xd377dc52, 0x2f3f3dbf, 0xa97f8c35, 0x38a44020, 0x28e1cc8b,
+           0x52d0e17a);
+  asm volatile("vwmul.vv v6, v2, v4");
+  VSET(16, e64, m1);
+  VCMP_I64(3, v6, 0x220c9d56193e26fb, 0xfef434f3d9f0dac0, 0xed5267a678ad2090,
+           0x267ac8a1a8c09528, 0xfd97bcf001c92000, 0xf1cc14c54f865ddc,
+           0x24347d81c3bb518c, 0xfb94cd6ed9b5cde0, 0x0c5e26a06dc0eeaf,
+           0xf4a9f71526e7ff14, 0xf538e8d5150bf07e, 0xf3c075503fe182d4,
+           0x1fd0bbab88bae81d, 0x1561d6be9f0d8dc0, 0xf220183a08740e7f,
+           0x290e99b3f87dbd26);
+};
+
+void TEST_CASE2(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xee, 0xfe, 0xbd, 0xc2, 0x02, 0xa4, 0x34, 0x33, 0x2b, 0x35, 0x16,
+          0x9b, 0x3b, 0x5f, 0xfc, 0x8b);
+  VLOAD_8(v4, 0xcb, 0x24, 0xe8, 0xb2, 0xeb, 0x24, 0x80, 0x67, 0x43, 0x11, 0x7c,
+          0x94, 0x22, 0x71, 0xca, 0x80);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwmul.vv v6, v2, v4, v0.t");
+  VSET(16, e16, m1);
+  VCMP_I16(4, v6, 0, 0xffb8, 0, 0x12e4, 0, 0xf310, 0, 0x1485, 0, 0x0385, 0,
+           0x2a9c, 0, 0x29ef, 0, 0x3a80);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x8aed, 0x2153, 0x5377, 0xc19c, 0x1051, 0x1b75, 0xbafd, 0xb200,
+           0xb209, 0xa9a2, 0xbdc4, 0x1653, 0x5965, 0x145e, 0xb626, 0xd79c);
+  VLOAD_16(v4, 0x778d, 0xc104, 0x6eac, 0x78e8, 0xacd2, 0x698b, 0xc7d3, 0x1e29,
+           0x0a58, 0x58b5, 0x29f9, 0x2fb0, 0x2166, 0x0ac4, 0x44e5, 0xbc40);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwmul.vv v6, v2, v4, v0.t");
+  VSET(16, e32, m1);
+  VCMP_I32(5, v6, 0, 0xf7cd184c, 0, 0xe2889560, 0, 0x0b51e587, 0, 0xf6cf8200, 0,
+           0xe2129f8a, 0, 0x04289610, 0, 0x00db43f8, 0, 0x0ab07700);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0xbbc467cb, 0xfbb3efda, 0x652f8490, 0x5e7ea848, 0x21fbc400,
+           0xbb409fde, 0x98413836, 0x14652ba4, 0xc3d3c86f, 0xc84d3ae3,
+           0x3df53027, 0xbda29a2c, 0xa1d7d949, 0x60a3d06e, 0xa91e405d,
+           0x7eea498f);
+  VLOAD_32(v4, 0x80407791, 0x3e51b6e0, 0xd0be8bc1, 0x683f33bd, 0xeddda6c8,
+           0x34e351f2, 0xa6a93ab2, 0xc8893cb8, 0xcb61ddc1, 0x341a4cdc,
+           0xd377dc52, 0x2f3f3dbf, 0xa97f8c35, 0x38a44020, 0x28e1cc8b,
+           0x52d0e17a);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwmul.vv v6, v2, v4, v0.t");
+  VSET(16, e64, m1);
+  VCMP_I64(6, v6, 0, 0xfef434f3d9f0dac0, 0, 0x267ac8a1a8c09528, 0,
+           0xf1cc14c54f865ddc, 0, 0xfb94cd6ed9b5cde0, 0, 0xf4a9f71526e7ff14, 0,
+           0xf3c075503fe182d4, 0, 0x1561d6be9f0d8dc0, 0, 0x290e99b3f87dbd26);
+};
+
+void TEST_CASE3(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x86, 0x79, 0xa0, 0x8a, 0x3e, 0xc3, 0x3e, 0x0c, 0x1b, 0xca, 0x80,
+          0x41, 0x0e, 0xee, 0x94, 0xdf);
+  int64_t scalar = 5;
+  asm volatile("vwmul.vx v6, v2, %[A]" ::[A] "r"(scalar));
+  VSET(16, e16, m1);
+  VCMP_I16(7, v6, 0xfd9e, 0x025d, 0xfe20, 0xfdb2, 0x0136, 0xfecf, 0x0136,
+           0x003c, 0x0087, 0xfef2, 0xfd80, 0x0145, 0x0046, 0xffa6, 0xfde4,
+           0xff5b);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0xb0ab, 0xcccb, 0x5fad, 0x9e24, 0x1496, 0xd4a0, 0x2552, 0xcef6,
+           0x34b8, 0xef22, 0x69c3, 0xbb05, 0xbe72, 0x315b, 0x3f03, 0xf58b);
+  scalar = -5383;
+  asm volatile("vwmul.vx v6, v2, %[A]" ::[A] "r"(scalar));
+  VSET(16, e32, m1);
+  VCMP_I32(8, v6, 0x06842453, 0x0434bf73, 0xf8243145, 0x0809b904, 0xfe4f21e6,
+           0x03900fa0, 0xfcef40c2, 0x04072946, 0xfbab76f8, 0x0162ac12,
+           0xf7501cab, 0x05aa79dd, 0x056270e2, 0xfbf22f83, 0xfad307eb,
+           0x00dbe233);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x71c6753d, 0x66646cc2, 0x23065c23, 0xde594cad, 0xa2f87c53,
+           0xaebb2bcb, 0xc53688b8, 0xf0c161dd, 0x2d856780, 0xa520cce5,
+           0x677c5e13, 0x83d288f4, 0x78b6acdc, 0x5b635dd1, 0x97dc75c8,
+           0x1a1aa6d4);
+  scalar = 6474219;
+  asm volatile("vwmul.vx v6, v2, %[A]" ::[A] "r"(scalar));
+  VSET(16, e64, m1);
+  VCMP_I64(9, v6, 0x002be7b6249483ff, 0x0027833479d82816, 0x000d840f6a940f21,
+           0xfff303a4936737cf, 0xffdc19bf4b7d4b31, 0xffe0a38d1ee99659,
+           0xffe9508230d7f8e8, 0xfffa1e014df55adf, 0x001190f926b98280,
+           0xffdceee1c5a5e337, 0x0027ef3ba84d4671, 0xffd014a6bd334bfc,
+           0x002e952469a169f4, 0x0023441ed2e237db, 0xffd7d041966a2698,
+           0x000a12cac09b989c);
+};
+
+void TEST_CASE4(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x86, 0x79, 0xa0, 0x8a, 0x3e, 0xc3, 0x3e, 0x0c, 0x1b, 0xca, 0x80,
+          0x41, 0x0e, 0xee, 0x94, 0xdf);
+  int64_t scalar = 5;
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwmul.vx v6, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(16, e16, m1);
+  VCMP_I16(10, v6, 0, 0x025d, 0, 0xfdb2, 0, 0xfecf, 0, 0x003c, 0, 0xfef2, 0,
+           0x0145, 0, 0xffa6, 0, 0xff5b);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0xb0ab, 0xcccb, 0x5fad, 0x9e24, 0x1496, 0xd4a0, 0x2552, 0xcef6,
+           0x34b8, 0xef22, 0x69c3, 0xbb05, 0xbe72, 0x315b, 0x3f03, 0xf58b);
+  scalar = -5383;
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwmul.vx v6, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(16, e32, m1);
+  VCMP_I32(11, v6, 0, 0x0434bf73, 0, 0x0809b904, 0, 0x03900fa0, 0, 0x04072946,
+           0, 0x0162ac12, 0, 0x05aa79dd, 0, 0xfbf22f83, 0, 0x00dbe233);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x71c6753d, 0x66646cc2, 0x23065c23, 0xde594cad, 0xa2f87c53,
+           0xaebb2bcb, 0xc53688b8, 0xf0c161dd, 0x2d856780, 0xa520cce5,
+           0x677c5e13, 0x83d288f4, 0x78b6acdc, 0x5b635dd1, 0x97dc75c8,
+           0x1a1aa6d4);
+  scalar = 6474219;
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwmul.vx v6, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(16, e64, m1);
+  VCMP_I64(12, v6, 0, 0x0027833479d82816, 0, 0xfff303a4936737cf, 0,
+           0xffe0a38d1ee99659, 0, 0xfffa1e014df55adf, 0, 0xffdceee1c5a5e337, 0,
+           0xffd014a6bd334bfc, 0, 0x0023441ed2e237db, 0, 0x000a12cac09b989c);
+};
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vwmulsu.c b/apps/riscv-tests/isa/rv64uv/vwmulsu.c
new file mode 100644
index 0000000..c980d02
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vwmulsu.c
@@ -0,0 +1,182 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x37, 0x4e, 0x9a, 0x08, 0x12, 0xfd, 0xa4, 0x21, 0x44, 0x58, 0x5a,
+          0xa9, 0x1d, 0x5e, 0xd4, 0x8e);
+  VLOAD_8(v4, 0x60, 0x5b, 0x0e, 0x78, 0x67, 0xf4, 0xd3, 0x0f, 0x75, 0x34, 0xc3,
+          0xb1, 0x62, 0x42, 0xa9, 0x75);
+  asm volatile("vwmulsu.vv v6, v2, v4");
+  VSET(16, e16, m1);
+  VCMP_I16(1, v6, 0x14a0, 0x1bba, 0xfa6c, 0x03c0, 0x073e, 0xfd24, 0xb42c,
+           0x01ef, 0x1f14, 0x11e0, 0x448e, 0xc3d9, 0x0b1a, 0x183c, 0xe2f4,
+           0xcbe6);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0xba33, 0x3a22, 0x9f52, 0x0c6a, 0xcb67, 0x790c, 0x1a85, 0x958e,
+           0xe967, 0x52b6, 0xa453, 0xe306, 0x3c91, 0x0309, 0xcbad, 0x9b78);
+  VLOAD_16(v4, 0x84ef, 0xf522, 0x6224, 0x6e02, 0xeedb, 0x5a1f, 0x98d7, 0xa498,
+           0x7a66, 0xdc69, 0xd88b, 0xa611, 0x5a08, 0x6836, 0x9130, 0x85be);
+  asm volatile("vwmulsu.vv v6, v2, v4");
+  VSET(16, e32, m1);
+  VCMP_I32(2, v6, 0xdbc1219d, 0x37aa4284, 0xdaefcb88, 0x0555a4d4, 0xceecc31d,
+           0x2a9ce074, 0x0fd53db3, 0xbb8fc450, 0xf532150a, 0x473654a6,
+           0xb2744111, 0xed33f766, 0x154cde88, 0x013c4be6, 0xe2532d70,
+           0xcb7abb10);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x8bc45f0a, 0x8a60bc63, 0xf3fcddb9, 0xa810b1c8, 0x8cb59934,
+           0x8d3334b0, 0x4387cb58, 0xc59d7a46, 0x939dd006, 0xfbd1dfc1,
+           0x75307321, 0xb46b5a27, 0xfd2fbdda, 0xec141137, 0x3a1bc8a7,
+           0xf0b1eb21);
+  VLOAD_32(v4, 0xe193ae9a, 0x57eccb97, 0x41d9eeff, 0xe8d58ddd, 0x2057ccc2,
+           0x3122b84c, 0x003bb317, 0xcdfc6918, 0xb5883636, 0x52788c1f,
+           0xab90d0a1, 0x6d890387, 0xf9bf35e7, 0xf88259a4, 0x79d9e6f0,
+           0x8203a804);
+  asm volatile("vwmulsu.vv v6, v2, v4");
+  VSET(16, e64, m1);
+  VCMP_I64(3, v6, 0x99948a03e977f804, 0xd79a13a8a4b59f65, 0xfce8fa6d09d3d947,
+           0xb005c64673bca1a8, 0xf16f28a6e85f8968, 0xe9f73b3d68722440,
+           0x000fbf89e1a9cce8, 0xd10589f688d22c90, 0xb324e8f72e5b2544,
+           0xfea741c2f93fa45f, 0x4e89a7a8de9337c1, 0xdfa941cb4089ff91,
+           0xfd4155b0080871b6, 0xeca94be43cc5263c, 0x1ba897cf74e12690,
+           0xf83a217108785484);
+};
+
+void TEST_CASE2(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x37, 0x4e, 0x9a, 0x08, 0x12, 0xfd, 0xa4, 0x21, 0x44, 0x58, 0x5a,
+          0xa9, 0x1d, 0x5e, 0xd4, 0x8e);
+  VLOAD_8(v4, 0x60, 0x5b, 0x0e, 0x78, 0x67, 0xf4, 0xd3, 0x0f, 0x75, 0x34, 0xc3,
+          0xb1, 0x62, 0x42, 0xa9, 0x75);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwmulsu.vv v6, v2, v4, v0.t");
+  VSET(16, e16, m1);
+  VCMP_I16(4, v6, 0, 0x1bba, 0, 0x03c0, 0, 0xfd24, 0, 0x01ef, 0, 0x11e0, 0,
+           0xc3d9, 0, 0x183c, 0, 0xcbe6);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0xba33, 0x3a22, 0x9f52, 0x0c6a, 0xcb67, 0x790c, 0x1a85, 0x958e,
+           0xe967, 0x52b6, 0xa453, 0xe306, 0x3c91, 0x0309, 0xcbad, 0x9b78);
+  VLOAD_16(v4, 0x84ef, 0xf522, 0x6224, 0x6e02, 0xeedb, 0x5a1f, 0x98d7, 0xa498,
+           0x7a66, 0xdc69, 0xd88b, 0xa611, 0x5a08, 0x6836, 0x9130, 0x85be);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwmulsu.vv v6, v2, v4, v0.t");
+  VSET(16, e32, m1);
+  VCMP_I32(5, v6, 0, 0x37aa4284, 0, 0x0555a4d4, 0, 0x2a9ce074, 0, 0xbb8fc450, 0,
+           0x473654a6, 0, 0xed33f766, 0, 0x013c4be6, 0, 0xcb7abb10);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x8bc45f0a, 0x8a60bc63, 0xf3fcddb9, 0xa810b1c8, 0x8cb59934,
+           0x8d3334b0, 0x4387cb58, 0xc59d7a46, 0x939dd006, 0xfbd1dfc1,
+           0x75307321, 0xb46b5a27, 0xfd2fbdda, 0xec141137, 0x3a1bc8a7,
+           0xf0b1eb21);
+  VLOAD_32(v4, 0xe193ae9a, 0x57eccb97, 0x41d9eeff, 0xe8d58ddd, 0x2057ccc2,
+           0x3122b84c, 0x003bb317, 0xcdfc6918, 0xb5883636, 0x52788c1f,
+           0xab90d0a1, 0x6d890387, 0xf9bf35e7, 0xf88259a4, 0x79d9e6f0,
+           0x8203a804);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwmulsu.vv v6, v2, v4, v0.t");
+  VSET(16, e64, m1);
+  VCMP_I64(6, v6, 0, 0xd79a13a8a4b59f65, 0, 0xb005c64673bca1a8, 0,
+           0xe9f73b3d68722440, 0, 0xd10589f688d22c90, 0, 0xfea741c2f93fa45f, 0,
+           0xdfa941cb4089ff91, 0, 0xeca94be43cc5263c, 0, 0xf83a217108785484);
+};
+
+void TEST_CASE3(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x16, 0x39, 0x0d, 0xcb, 0x02, 0x2b, 0xcd, 0x30, 0xec, 0x03, 0x18,
+          0x78, 0xec, 0xba, 0xf8, 0x49);
+  uint64_t scalar = 5;
+  asm volatile("vwmulsu.vx v6, v2, %[A]" ::[A] "r"(scalar));
+  VSET(16, e16, m1);
+  VCMP_I16(7, v6, 0x006e, 0x011d, 0x0041, 0xfef7, 0x000a, 0x00d7, 0xff01,
+           0x00f0, 0xff9c, 0x000f, 0x0078, 0x0258, 0xff9c, 0xfea2, 0xffd8,
+           0x016d);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x602f, 0x1b08, 0xfdd6, 0x7e53, 0x59f7, 0x70f1, 0x8a33, 0x5d93,
+           0x02a3, 0x9f70, 0x3919, 0x8f2b, 0xc9d3, 0x1b65, 0x15bd, 0xf8be);
+  scalar = 5383;
+  asm volatile("vwmulsu.vx v6, v2, %[A]" ::[A] "r"(scalar));
+  VSET(16, e32, m1);
+  VCMP_I32(8, v6, 0x07e67c49, 0x02386538, 0xffd27eda, 0x0a604345, 0x0763b8c1,
+           0x0946db97, 0xf652f665, 0x07af9e05, 0x00377175, 0xf8118c10,
+           0x04b09caf, 0xf6bb712d, 0xfb8cd3c5, 0x024008c3, 0x01c9192b,
+           0xff676332);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x77036e08, 0xeb7bd8dc, 0x9c0d7f6a, 0x19d320f6, 0xb0c0d792,
+           0x3f02203c, 0xf72a9ea9, 0x392f2986, 0x85b78fe8, 0xdc6a281b,
+           0x146ffa52, 0x61f96c3c, 0x876cda10, 0x24d22032, 0xb6ffba3d,
+           0xbbd29543);
+  scalar = 6474219;
+  asm volatile("vwmulsu.vx v6, v2, %[A]" ::[A] "r"(scalar));
+  VSET(16, e64, m1);
+  VCMP_I64(9, v6, 0x002ded2f109a4958, 0xfff8153a6c2ccdf4, 0xffd96e55a002304e,
+           0x0009f73117dc67d2, 0xffe16b51302b8506, 0x00185082d93ab314,
+           0xfffc975917645623, 0x001611286b315402, 0xffd0cfd1f64e41f8,
+           0xfff24492094603c9, 0x0007e2fc81b92b46, 0x0025cec234e97714,
+           0xffd178914242bcb0, 0x000e357b1b4ecfe6, 0xffe3d4511153daff,
+           0xffe5b0d6e5269f81);
+};
+
+void TEST_CASE4(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x16, 0x39, 0x0d, 0xcb, 0x02, 0x2b, 0xcd, 0x30, 0xec, 0x03, 0x18,
+          0x78, 0xec, 0xba, 0xf8, 0x49);
+  uint64_t scalar = 5;
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwmulsu.vx v6, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(16, e16, m1);
+  VCMP_I16(10, v6, 0, 0x011d, 0, 0xfef7, 0, 0x00d7, 0, 0x00f0, 0, 0x000f, 0,
+           0x0258, 0, 0xfea2, 0, 0x016d);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0x602f, 0x1b08, 0xfdd6, 0x7e53, 0x59f7, 0x70f1, 0x8a33, 0x5d93,
+           0x02a3, 0x9f70, 0x3919, 0x8f2b, 0xc9d3, 0x1b65, 0x15bd, 0xf8be);
+  scalar = 5383;
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwmulsu.vx v6, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(16, e32, m1);
+  VCMP_I32(11, v6, 0, 0x02386538, 0, 0x0a604345, 0, 0x0946db97, 0, 0x07af9e05,
+           0, 0xf8118c10, 0, 0xf6bb712d, 0, 0x024008c3, 0, 0xff676332);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0x77036e08, 0xeb7bd8dc, 0x9c0d7f6a, 0x19d320f6, 0xb0c0d792,
+           0x3f02203c, 0xf72a9ea9, 0x392f2986, 0x85b78fe8, 0xdc6a281b,
+           0x146ffa52, 0x61f96c3c, 0x876cda10, 0x24d22032, 0xb6ffba3d,
+           0xbbd29543);
+  scalar = 6474219;
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwmulsu.vx v6, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(16, e64, m1);
+  VCMP_I64(12, v6, 0, 0xfff8153a6c2ccdf4, 0, 0x0009f73117dc67d2, 0,
+           0x00185082d93ab314, 0, 0x001611286b315402, 0, 0xfff24492094603c9, 0,
+           0x0025cec234e97714, 0, 0x000e357b1b4ecfe6, 0, 0xffe5b0d6e5269f81);
+};
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vwmulu.c b/apps/riscv-tests/isa/rv64uv/vwmulu.c
new file mode 100644
index 0000000..aa3c819
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vwmulu.c
@@ -0,0 +1,182 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x74, 0xfb, 0xf4, 0xe9, 0xe5, 0x4e, 0x02, 0x27, 0xe9, 0x83, 0xfe,
+          0x03, 0xb2, 0xb9, 0x9a, 0x71);
+  VLOAD_8(v4, 0x67, 0xa9, 0x07, 0x0f, 0xe3, 0x0d, 0xce, 0x81, 0xa2, 0xa5, 0x59,
+          0x18, 0x0d, 0xac, 0x80, 0x31);
+  asm volatile("vwmulu.vv v6, v2, v4");
+  VSET(16, e16, m1);
+  VCMP_U16(1, v6, 0x2eac, 0xa5b3, 0x06ac, 0x0da7, 0xcb0f, 0x03f6, 0x019c,
+           0x13a7, 0x9372, 0x546f, 0x584e, 0x0048, 0x090a, 0x7c4c, 0x4d00,
+           0x15a1);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0xcf44, 0x249f, 0x3b1d, 0xea59, 0x0c47, 0xd24b, 0xce3e, 0xdb61,
+           0x3506, 0xcee2, 0x3c7e, 0xc169, 0x05fd, 0x7fe6, 0xf7db, 0xb7cd);
+  VLOAD_16(v4, 0xaa0b, 0x2176, 0x34bc, 0x4aa6, 0x221e, 0x9f98, 0x63f5, 0x8da7,
+           0x001d, 0x18d7, 0x1dbb, 0x5f2d, 0x0783, 0xd756, 0xa08d, 0x9c49);
+  asm volatile("vwmulu.vv v6, v2, v4");
+  VSET(16, e32, m1);
+  VCMP_U32(2, v6, 0x89ac0fec, 0x04c9604a, 0x0c2d4d4c, 0x4455afb6, 0x01a2de52,
+           0x83197188, 0x50875b56, 0x79638947, 0x000601ae, 0x1412efce,
+           0x0706760a, 0x47e7f675, 0x002cfb77, 0x6b952144, 0x9b71639f,
+           0x70355575);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0xd6f59ab7, 0x3b760112, 0x185928a9, 0x344f2f98, 0x07084e45,
+           0x0af492c5, 0x5de6f51a, 0x76783522, 0x36835490, 0x043d016f,
+           0xf583b765, 0xd8796652, 0x1bd09e8f, 0xeecf0026, 0xdb725a7d,
+           0x3a4c3ab3);
+  VLOAD_32(v4, 0x19f9f18b, 0x801fde9f, 0xaf759e4c, 0x9206cfd4, 0x2dc70e82,
+           0xb57cb666, 0xc4ab14ac, 0xbf231e21, 0xdc6caaf4, 0x5bbc4031,
+           0x2021a0db, 0x4e68ad25, 0xb090da86, 0xe32bd2c2, 0xf45e06d0,
+           0xa5320284);
+  asm volatile("vwmulu.vv v6, v2, v4");
+  VSET(16, e64, m1);
+  VCMP_U64(3, v6, 0x15cfdbd14900485d, 0x1dc267886466462e, 0x10b022995dcd602c,
+           0x1dd68d77269f51e0, 0x0141ed9cff22850a, 0x07c4420a9e36887e,
+           0x48239482c2b0b578, 0x5873f004fd5ed562, 0x2ef0007a98143940,
+           0x0184cd5f928d063f, 0x1ed0b72b9e520367, 0x424d80e7e10133da,
+           0x132f2a19b6a8c4da, 0xd3ea6e817f5f48cc, 0xd179981358ee7390,
+           0x259e854b7db9aa4c);
+};
+
+void TEST_CASE2(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0x74, 0xfb, 0xf4, 0xe9, 0xe5, 0x4e, 0x02, 0x27, 0xe9, 0x83, 0xfe,
+          0x03, 0xb2, 0xb9, 0x9a, 0x71);
+  VLOAD_8(v4, 0x67, 0xa9, 0x07, 0x0f, 0xe3, 0x0d, 0xce, 0x81, 0xa2, 0xa5, 0x59,
+          0x18, 0x0d, 0xac, 0x80, 0x31);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwmulu.vv v6, v2, v4, v0.t");
+  VSET(16, e16, m1);
+  VCMP_U16(4, v6, 0, 0xa5b3, 0, 0x0da7, 0, 0x03f6, 0, 0x13a7, 0, 0x546f, 0,
+           0x0048, 0, 0x7c4c, 0, 0x15a1);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0xcf44, 0x249f, 0x3b1d, 0xea59, 0x0c47, 0xd24b, 0xce3e, 0xdb61,
+           0x3506, 0xcee2, 0x3c7e, 0xc169, 0x05fd, 0x7fe6, 0xf7db, 0xb7cd);
+  VLOAD_16(v4, 0xaa0b, 0x2176, 0x34bc, 0x4aa6, 0x221e, 0x9f98, 0x63f5, 0x8da7,
+           0x001d, 0x18d7, 0x1dbb, 0x5f2d, 0x0783, 0xd756, 0xa08d, 0x9c49);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwmulu.vv v6, v2, v4, v0.t");
+  VSET(16, e32, m1);
+  VCMP_U32(5, v6, 0, 0x04c9604a, 0, 0x4455afb6, 0, 0x83197188, 0, 0x79638947, 0,
+           0x1412efce, 0, 0x47e7f675, 0, 0x6b952144, 0, 0x70355575);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0xd6f59ab7, 0x3b760112, 0x185928a9, 0x344f2f98, 0x07084e45,
+           0x0af492c5, 0x5de6f51a, 0x76783522, 0x36835490, 0x043d016f,
+           0xf583b765, 0xd8796652, 0x1bd09e8f, 0xeecf0026, 0xdb725a7d,
+           0x3a4c3ab3);
+  VLOAD_32(v4, 0x19f9f18b, 0x801fde9f, 0xaf759e4c, 0x9206cfd4, 0x2dc70e82,
+           0xb57cb666, 0xc4ab14ac, 0xbf231e21, 0xdc6caaf4, 0x5bbc4031,
+           0x2021a0db, 0x4e68ad25, 0xb090da86, 0xe32bd2c2, 0xf45e06d0,
+           0xa5320284);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwmulu.vv v6, v2, v4, v0.t");
+  VSET(16, e64, m1);
+  VCMP_U64(6, v6, 0, 0x1dc267886466462e, 0, 0x1dd68d77269f51e0, 0,
+           0x07c4420a9e36887e, 0, 0x5873f004fd5ed562, 0, 0x0184cd5f928d063f, 0,
+           0x424d80e7e10133da, 0, 0xd3ea6e817f5f48cc, 0, 0x259e854b7db9aa4c);
+};
+
+void TEST_CASE3(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xf8, 0x11, 0x12, 0xf1, 0x63, 0x21, 0x88, 0x3b, 0x01, 0xf5, 0x6d,
+          0xf5, 0xb1, 0x54, 0xcd, 0xb0);
+  uint64_t scalar = 5;
+  asm volatile("vwmulu.vx v6, v2, %[A]" ::[A] "r"(scalar));
+  VSET(16, e16, m1);
+  VCMP_U16(7, v6, 0x04d8, 0x0055, 0x005a, 0x04b5, 0x01ef, 0x00a5, 0x02a8,
+           0x0127, 0x0005, 0x04c9, 0x0221, 0x04c9, 0x0375, 0x01a4, 0x0401,
+           0x0370);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0xf8e5, 0x6a23, 0xb52f, 0x8838, 0xb6d4, 0x5279, 0xf80e, 0xa450,
+           0x13ec, 0x916f, 0x8edd, 0x0162, 0x9350, 0x9f74, 0xe1e7, 0x2719);
+  scalar = 5383;
+  asm volatile("vwmulu.vx v6, v2, %[A]" ::[A] "r"(scalar));
+  VSET(16, e32, m1);
+  VCMP_U32(8, v6, 0x14719743, 0x08b7c5f5, 0x0ee1cf49, 0x0b305188, 0x0f0463cc,
+           0x06c62e4f, 0x145fee62, 0x0d7f0e30, 0x01a2e774, 0x0bf21509,
+           0x0bbc090b, 0x001d13ae, 0x0c199730, 0x0d18e02c, 0x128e2051,
+           0x03361eaf);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0xc41bf344, 0xad5aef4c, 0xf2b11789, 0xeb0d7526, 0xd6c67427,
+           0x73724130, 0x440f954a, 0x0661455f, 0x450070ca, 0xc258c90c,
+           0xf095d838, 0x358b0916, 0x6e1f1918, 0x4ebf2685, 0x3805d683,
+           0x73715886);
+  scalar = 6474219;
+  asm volatile("vwmulu.vx v6, v2, %[A]" ::[A] "r"(scalar));
+  VSET(16, e64, m1);
+  VCMP_U64(9, v6, 0x004bad6117b0b36c, 0x0042e58b237456c4, 0x005da736d67d2bc3,
+           0x005ab48c2ee15fe2, 0x0052e15f704d3ecd, 0x002c8ccba3708710,
+           0x001a43a5dcd924ee, 0x00027644c9204535, 0x001aa097dd4a236e,
+           0x004aff4713f2fa04, 0x005cd71f45c17368, 0x0014a974cb2f9d32,
+           0x002a7ec31c6fe108, 0x001e63491da0c917, 0x00159e6c20eec541,
+           0x002c8c71dad97902);
+};
+
+void TEST_CASE4(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 0xf8, 0x11, 0x12, 0xf1, 0x63, 0x21, 0x88, 0x3b, 0x01, 0xf5, 0x6d,
+          0xf5, 0xb1, 0x54, 0xcd, 0xb0);
+  uint64_t scalar = 5;
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwmulu.vx v6, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(16, e16, m1);
+  VCMP_U16(10, v6, 0, 0x0055, 0, 0x04b5, 0, 0x00a5, 0, 0x0127, 0, 0x04c9, 0,
+           0x04c9, 0, 0x01a4, 0, 0x0370);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 0xf8e5, 0x6a23, 0xb52f, 0x8838, 0xb6d4, 0x5279, 0xf80e, 0xa450,
+           0x13ec, 0x916f, 0x8edd, 0x0162, 0x9350, 0x9f74, 0xe1e7, 0x2719);
+  scalar = 5383;
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwmulu.vx v6, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(16, e32, m1);
+  VCMP_U32(11, v6, 0, 0x08b7c5f5, 0, 0x0b305188, 0, 0x06c62e4f, 0, 0x0d7f0e30,
+           0, 0x0bf21509, 0, 0x001d13ae, 0, 0x0d18e02c, 0, 0x03361eaf);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 0xc41bf344, 0xad5aef4c, 0xf2b11789, 0xeb0d7526, 0xd6c67427,
+           0x73724130, 0x440f954a, 0x0661455f, 0x450070ca, 0xc258c90c,
+           0xf095d838, 0x358b0916, 0x6e1f1918, 0x4ebf2685, 0x3805d683,
+           0x73715886);
+  scalar = 6474219;
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwmulu.vx v6, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(16, e64, m1);
+  VCMP_U64(12, v6, 0, 0x0042e58b237456c4, 0, 0x005ab48c2ee15fe2, 0,
+           0x002c8ccba3708710, 0, 0x00027644c9204535, 0, 0x004aff4713f2fa04, 0,
+           0x0014a974cb2f9d32, 0, 0x001e63491da0c917, 0, 0x002c8c71dad97902);
+};
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vwredsum.c b/apps/riscv-tests/isa/rv64uv/vwredsum.c
new file mode 100644
index 0000000..729831c
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vwredsum.c
@@ -0,0 +1,153 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+
+#include "vector_macros.h"
+
+// Naive test
+void TEST_CASE1(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v6, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v2, 255);
+  asm volatile("vwredsum.vs v4, v6, v2");
+  VCMP_U16(1, v4, 327);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v6, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v2, 1);
+  asm volatile("vwredsum.vs v4, v6, v2");
+  VCMP_U32(2, v4, 73);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v6, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_64(v2, 1);
+  asm volatile("vwredsum.vs v4, v6, v2");
+  VCMP_U64(3, v4, 73);
+}
+
+// Masked naive test
+void TEST_CASE2(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v0, 0xaa, 0x55);
+  VLOAD_8(v6, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v2, 255);
+  VLOAD_16(v4, 1);
+  asm volatile("vwredsum.vs v4, v6, v2, v0.t");
+  VCMP_U16(4, v4, 291);
+
+  VSET(16, e16, m1);
+  VLOAD_8(v0, 0xaa, 0x55);
+  VLOAD_16(v6, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v2, 1);
+  VLOAD_32(v4, 1);
+  asm volatile("vwredsum.vs v4, v6, v2, v0.t");
+  VCMP_U32(5, v4, 37);
+
+  VSET(16, e32, m1);
+  VLOAD_8(v0, 0xaa, 0x55);
+  VLOAD_32(v6, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_64(v2, 1);
+  VLOAD_64(v4, 1);
+  asm volatile("vwredsum.vs v4, v6, v2, v0.t");
+  VCMP_U64(6, v4, 37);
+}
+
+// Are we respecting the undisturbed tail policy?
+void TEST_CASE3(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v6, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v4, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vwredsum.vs v4, v6, v2");
+  VCMP_U16(7, v4, 73, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v6, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v4, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vwredsum.vs v4, v6, v2");
+  VCMP_U32(8, v4, 73, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v6, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_64(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_64(v4, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vwredsum.vs v4, v6, v2");
+  VCMP_U64(9, v4, 73, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+}
+
+// Odd number of elements, undisturbed policy
+void TEST_CASE4(void) {
+  VSET(15, e8, m1);
+  VLOAD_8(v6, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v4, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vwredsum.vs v4, v6, v2");
+  VCMP_U16(10, v4, 65, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+
+  VSET(1, e16, m1);
+  VLOAD_16(v6, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v4, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vwredsum.vs v4, v6, v2");
+  VCMP_U32(11, v4, 2, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+
+  VSET(3, e32, m1);
+  VLOAD_32(v6, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_64(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_64(v4, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vwredsum.vs v4, v6, v2");
+  VCMP_U64(12, v4, 7, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+}
+
+// Odd number of elements, undisturbed policy, and mask
+void TEST_CASE5(void) {
+  VSET(15, e8, m1);
+  VLOAD_8(v0, 0x00, 0x40);
+  VLOAD_8(v6, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v2, 100, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v4, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vwredsum.vs v4, v6, v2, v0.t");
+  VCMP_U16(13, v4, 107, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+
+  VSET(1, e16, m1);
+  VLOAD_8(v0, 0xaa, 0x55);
+  VLOAD_16(v6, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v4, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vwredsum.vs v4, v6, v2, v0.t");
+  VCMP_U32(14, v4, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+
+  VSET(3, e32, m1);
+  VLOAD_8(v0, 0xaa, 0x55);
+  VLOAD_32(v6, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_64(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_64(v4, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vwredsum.vs v4, v6, v2, v0.t");
+  VCMP_U64(15, v4, 3, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+}
+
+// Test difference from vwredsumu
+void TEST_CASE6(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v6, 1, 2, 3, 4, 5, 6, 7, 8, 255, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v2, 255);
+  asm volatile("vwredsum.vs v4, v6, v2");
+  VCMP_U16(16, v4, 325);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+  TEST_CASE6();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vwredsumu.c b/apps/riscv-tests/isa/rv64uv/vwredsumu.c
new file mode 100644
index 0000000..f088976
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vwredsumu.c
@@ -0,0 +1,153 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matteo Perotti <mperotti@iis.ee.ethz.ch>
+
+#include "vector_macros.h"
+
+// Naive test
+void TEST_CASE1(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v6, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v2, 255);
+  asm volatile("vwredsumu.vs v4, v6, v2");
+  VCMP_U16(1, v4, 327);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v6, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v2, 1);
+  asm volatile("vwredsumu.vs v4, v6, v2");
+  VCMP_U32(2, v4, 73);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v6, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_64(v2, 1);
+  asm volatile("vwredsumu.vs v4, v6, v2");
+  VCMP_U64(3, v4, 73);
+}
+
+// Masked naive test
+void TEST_CASE2(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v0, 0xaa, 0x55);
+  VLOAD_8(v6, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v2, 255);
+  VLOAD_16(v4, 1);
+  asm volatile("vwredsumu.vs v4, v6, v2, v0.t");
+  VCMP_U16(4, v4, 291);
+
+  VSET(16, e16, m1);
+  VLOAD_8(v0, 0xaa, 0x55);
+  VLOAD_16(v6, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v2, 1);
+  VLOAD_32(v4, 1);
+  asm volatile("vwredsumu.vs v4, v6, v2, v0.t");
+  VCMP_U32(5, v4, 37);
+
+  VSET(16, e32, m1);
+  VLOAD_8(v0, 0xaa, 0x55);
+  VLOAD_32(v6, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_64(v2, 1);
+  VLOAD_64(v4, 1);
+  asm volatile("vwredsumu.vs v4, v6, v2, v0.t");
+  VCMP_U64(6, v4, 37);
+}
+
+// Are we respecting the undisturbed tail policy?
+void TEST_CASE3(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v6, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v4, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vwredsumu.vs v4, v6, v2");
+  VCMP_U16(7, v4, 73, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v6, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v4, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vwredsumu.vs v4, v6, v2");
+  VCMP_U32(8, v4, 73, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v6, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_64(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_64(v4, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vwredsumu.vs v4, v6, v2");
+  VCMP_U64(9, v4, 73, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+}
+
+// Odd number of elements, undisturbed policy
+void TEST_CASE4(void) {
+  VSET(15, e8, m1);
+  VLOAD_8(v6, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v4, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vwredsumu.vs v4, v6, v2");
+  VCMP_U16(10, v4, 65, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+
+  VSET(1, e16, m1);
+  VLOAD_16(v6, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v4, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vwredsumu.vs v4, v6, v2");
+  VCMP_U32(11, v4, 2, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+
+  VSET(3, e32, m1);
+  VLOAD_32(v6, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_64(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_64(v4, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vwredsumu.vs v4, v6, v2");
+  VCMP_U64(12, v4, 7, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+}
+
+// Odd number of elements, undisturbed policy, and mask
+void TEST_CASE5(void) {
+  VSET(15, e8, m1);
+  VLOAD_8(v0, 0x00, 0x40);
+  VLOAD_8(v6, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v2, 100, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v4, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vwredsumu.vs v4, v6, v2, v0.t");
+  VCMP_U16(13, v4, 107, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+
+  VSET(1, e16, m1);
+  VLOAD_8(v0, 0xaa, 0x55);
+  VLOAD_16(v6, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v4, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vwredsumu.vs v4, v6, v2, v0.t");
+  VCMP_U32(14, v4, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+
+  VSET(3, e32, m1);
+  VLOAD_8(v0, 0xaa, 0x55);
+  VLOAD_32(v6, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_64(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_64(v4, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  asm volatile("vwredsumu.vs v4, v6, v2, v0.t");
+  VCMP_U64(15, v4, 3, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+}
+
+// Test difference from vwredsumu
+void TEST_CASE6(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v6, 1, 2, 3, 4, 5, 6, 7, 8, 255, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v2, 255);
+  asm volatile("vwredsumu.vs v4, v6, v2");
+  VCMP_U16(16, v4, 581);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+  TEST_CASE6();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vwsub.c b/apps/riscv-tests/isa/rv64uv/vwsub.c
new file mode 100644
index 0000000..29f3531
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vwsub.c
@@ -0,0 +1,234 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v4, 8, 7, 6, 5, 4, 3, 2, 1, 8, 7, 6, 5, 4, 3, 2, 1);
+  asm volatile("vwsub.vv v6, v2, v4");
+  VSET(16, e16, m1);
+  VCMP_U16(1, v6, -7, -5, -3, -1, 1, 3, 5, 7, -7, -5, -3, -1, 1, 3, 5, 7);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v4, 8, 7, 6, 5, 4, 3, 2, 1, 8, 7, 6, 5, 4, 3, 2, 1);
+  asm volatile("vwsub.vv v6, v2, v4");
+  VSET(16, e32, m1);
+  VCMP_U32(2, v6, -7, -5, -3, -1, 1, 3, 5, 7, -7, -5, -3, -1, 1, 3, 5, 7);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v4, 8, 7, 6, 5, 4, 3, 2, 1, 8, 7, 6, 5, 4, 3, 2, 1);
+  asm volatile("vwsub.vv v6, v2, v4");
+  VSET(16, e64, m1);
+  VCMP_U64(3, v6, -7, -5, -3, -1, 1, 3, 5, 7, -7, -5, -3, -1, 1, 3, 5, 7);
+}
+
+void TEST_CASE2(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v4, 8, 7, 6, 5, 4, 3, 2, 1, 8, 7, 6, 5, 4, 3, 2, 1);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwsub.vv v6, v2, v4, v0.t");
+  VSET(16, e16, m1);
+  VCMP_U16(4, v6, 0, -5, 0, -1, 0, 3, 0, 7, 0, -5, 0, -1, 0, 3, 0, 7);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v4, 8, 7, 6, 5, 4, 3, 2, 1, 8, 7, 6, 5, 4, 3, 2, 1);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwsub.vv v6, v2, v4, v0.t");
+  VSET(16, e32, m1);
+  VCMP_U32(5, v6, 0, -5, 0, -1, 0, 3, 0, 7, 0, -5, 0, -1, 0, 3, 0, 7);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v4, 8, 7, 6, 5, 4, 3, 2, 1, 8, 7, 6, 5, 4, 3, 2, 1);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwsub.vv v6, v2, v4, v0.t");
+  VSET(16, e64, m1);
+  VCMP_U64(6, v6, 0, -5, 0, -1, 0, 3, 0, 7, 0, -5, 0, -1, 0, 3, 0, 7);
+}
+
+void TEST_CASE3(void) {
+  const uint32_t scalar = 5;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 1, -2, 3, -4, 5, -6, 7, -8, 9, -10, 11, -12, 13, -14, 15, -16);
+  asm volatile("vwsub.vx v6, v2, %[A]" ::[A] "r"(scalar));
+  VSET(16, e16, m1);
+  VCMP_U16(7, v6, -4, -7, -2, -9, 0, -11, 2, -13, 4, -15, 6, -17, 8, -19, 10,
+           -21);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 1, -2, 3, -4, 5, -6, 7, -8, 9, -10, 11, -12, 13, -14, 15, -16);
+  asm volatile("vwsub.vx v6, v2, %[A]" ::[A] "r"(scalar));
+  VSET(16, e32, m1);
+  VCMP_U32(8, v6, -4, -7, -2, -9, 0, -11, 2, -13, 4, -15, 6, -17, 8, -19, 10,
+           -21);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 1, -2, 3, -4, 5, -6, 7, -8, 9, -10, 11, -12, 13, -14, 15, -16);
+  asm volatile("vwsub.vx v6, v2, %[A]" ::[A] "r"(scalar));
+  VSET(16, e64, m1);
+  VCMP_U64(9, v6, -4, -7, -2, -9, 0, -11, 2, -13, 4, -15, 6, -17, 8, -19, 10,
+           -21);
+}
+
+void TEST_CASE4(void) {
+  const uint32_t scalar = 5;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwsub.vx v6, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(16, e16, m1);
+  VCMP_U16(10, v6, 0, -3, 0, -1, 0, 1, 0, 3, 0, -3, 0, -1, 0, 1, 0, 3);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwsub.vx v6, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(16, e32, m1);
+  VCMP_U32(11, v6, 0, -3, 0, -1, 0, 1, 0, 3, 0, -3, 0, -1, 0, 1, 0, 3);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwsub.vx v6, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(16, e64, m1);
+  VCMP_U64(12, v6, 0, -3, 0, -1, 0, 1, 0, 3, 0, -3, 0, -1, 0, 1, 0, 3);
+}
+
+void TEST_CASE5(void) {
+  VSET(16, e8, m1);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v4, 8, 7, 6, 5, 4, 3, 2, 1, 8, 7, 6, 5, 4, 3, 2, 1);
+  asm volatile("vwsub.wv v6, v2, v4");
+  VSET(16, e16, m1);
+  VCMP_U16(13, v6, -7, -5, -3, -1, 1, 3, 5, 7, -7, -5, -3, -1, 1, 3, 5, 7);
+
+  VSET(16, e16, m1);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v4, 8, 7, 6, 5, 4, 3, 2, 1, 8, 7, 6, 5, 4, 3, 2, 1);
+  asm volatile("vwsub.wv v6, v2, v4");
+  VSET(16, e32, m1);
+  VCMP_U32(14, v6, -7, -5, -3, -1, 1, 3, 5, 7, -7, -5, -3, -1, 1, 3, 5, 7);
+
+  VSET(16, e32, m1);
+  VLOAD_64(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v4, 8, 7, 6, 5, 4, 3, 2, 1, 8, 7, 6, 5, 4, 3, 2, 1);
+  asm volatile("vwsub.wv v6, v2, v4");
+  VSET(16, e64, m1);
+  VCMP_U64(15, v6, -7, -5, -3, -1, 1, 3, 5, 7, -7, -5, -3, -1, 1, 3, 5, 7);
+}
+
+void TEST_CASE6(void) {
+  VSET(16, e8, m1);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v4, 8, 7, 6, 5, 4, 3, 2, 1, 8, 7, 6, 5, 4, 3, 2, 1);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwsub.wv v6, v2, v4, v0.t");
+  VSET(16, e16, m1);
+  VCMP_U16(16, v6, 0, -5, 0, -1, 0, 3, 0, 7, 0, -5, 0, -1, 0, 3, 0, 7);
+
+  VSET(16, e16, m1);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v4, 8, 7, 6, 5, 4, 3, 2, 1, 8, 7, 6, 5, 4, 3, 2, 1);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwsub.wv v6, v2, v4, v0.t");
+  VSET(16, e32, m1);
+  VCMP_U32(17, v6, 0, -5, 0, -1, 0, 3, 0, 7, 0, -5, 0, -1, 0, 3, 0, 7);
+
+  VSET(16, e32, m1);
+  VLOAD_64(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v4, 8, 7, 6, 5, 4, 3, 2, 1, 8, 7, 6, 5, 4, 3, 2, 1);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwsub.wv v6, v2, v4, v0.t");
+  VSET(16, e64, m1);
+  VCMP_U64(18, v6, 0, -5, 0, -1, 0, 3, 0, 7, 0, -5, 0, -1, 0, 3, 0, 7);
+}
+
+void TEST_CASE7(void) {
+  const uint32_t scalar = 5;
+
+  VSET(16, e8, m1);
+  VLOAD_16(v2, 1, -2, 3, -4, 5, -6, 7, -8, 9, -10, 11, -12, 13, -14, 15, -16);
+  asm volatile("vwsub.wx v6, v2, %[A]" ::[A] "r"(scalar));
+  VSET(16, e16, m1);
+  VCMP_U16(19, v6, -4, -7, -2, -9, 0, -11, 2, -13, 4, -15, 6, -17, 8, -19, 10,
+           -21);
+
+  VSET(16, e16, m1);
+  VLOAD_32(v2, 1, -2, 3, -4, 5, -6, 7, -8, 9, -10, 11, -12, 13, -14, 15, -16);
+  asm volatile("vwsub.wx v6, v2, %[A]" ::[A] "r"(scalar));
+  VSET(16, e32, m1);
+  VCMP_U32(20, v6, -4, -7, -2, -9, 0, -11, 2, -13, 4, -15, 6, -17, 8, -19, 10,
+           -21);
+
+  VSET(16, e32, m1);
+  VLOAD_64(v2, 1, -2, 3, -4, 5, -6, 7, -8, 9, -10, 11, -12, 13, -14, 15, -16);
+  asm volatile("vwsub.wx v6, v2, %[A]" ::[A] "r"(scalar));
+  VSET(16, e64, m1);
+  VCMP_U64(21, v6, -4, -7, -2, -9, 0, -11, 2, -13, 4, -15, 6, -17, 8, -19, 10,
+           -21);
+}
+
+void TEST_CASE8(void) {
+  const uint32_t scalar = 5;
+
+  VSET(16, e8, m1);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwsub.wx v6, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(16, e16, m1);
+  VCMP_U16(22, v6, 0, -3, 0, -1, 0, 1, 0, 3, 0, -3, 0, -1, 0, 1, 0, 3);
+
+  VSET(16, e16, m1);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwsub.wx v6, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(16, e32, m1);
+  VCMP_U32(23, v6, 0, -3, 0, -1, 0, 1, 0, 3, 0, -3, 0, -1, 0, 1, 0, 3);
+
+  VSET(16, e32, m1);
+  VLOAD_64(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwsub.wx v6, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(16, e64, m1);
+  VCMP_U64(24, v6, 0, -3, 0, -1, 0, 1, 0, 3, 0, -3, 0, -1, 0, 1, 0, 3);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+  TEST_CASE6();
+  TEST_CASE7();
+  TEST_CASE8();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vwsubu.c b/apps/riscv-tests/isa/rv64uv/vwsubu.c
new file mode 100644
index 0000000..760e605
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vwsubu.c
@@ -0,0 +1,234 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v4, 8, 7, 6, 5, 4, 3, 2, 1, 8, 7, 6, 5, 4, 3, 2, 1);
+  asm volatile("vwsubu.vv v6, v2, v4");
+  VSET(16, e16, m1);
+  VCMP_U16(1, v6, -7, -5, -3, -1, 1, 3, 5, 7, -7, -5, -3, -1, 1, 3, 5, 7);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v4, 8, 7, 6, 5, 4, 3, 2, 1, 8, 7, 6, 5, 4, 3, 2, 1);
+  asm volatile("vwsubu.vv v6, v2, v4");
+  VSET(16, e32, m1);
+  VCMP_U32(2, v6, -7, -5, -3, -1, 1, 3, 5, 7, -7, -5, -3, -1, 1, 3, 5, 7);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v4, 8, 7, 6, 5, 4, 3, 2, 1, 8, 7, 6, 5, 4, 3, 2, 1);
+  asm volatile("vwsubu.vv v6, v2, v4");
+  VSET(16, e64, m1);
+  VCMP_U64(3, v6, -7, -5, -3, -1, 1, 3, 5, 7, -7, -5, -3, -1, 1, 3, 5, 7);
+}
+
+void TEST_CASE2(void) {
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v4, 8, 7, 6, 5, 4, 3, 2, 1, 8, 7, 6, 5, 4, 3, 2, 1);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwsubu.vv v6, v2, v4, v0.t");
+  VSET(16, e16, m1);
+  VCMP_U16(4, v6, 0, -5, 0, -1, 0, 3, 0, 7, 0, -5, 0, -1, 0, 3, 0, 7);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v4, 8, 7, 6, 5, 4, 3, 2, 1, 8, 7, 6, 5, 4, 3, 2, 1);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwsubu.vv v6, v2, v4, v0.t");
+  VSET(16, e32, m1);
+  VCMP_U32(5, v6, 0, -5, 0, -1, 0, 3, 0, 7, 0, -5, 0, -1, 0, 3, 0, 7);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v4, 8, 7, 6, 5, 4, 3, 2, 1, 8, 7, 6, 5, 4, 3, 2, 1);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwsubu.vv v6, v2, v4, v0.t");
+  VSET(16, e64, m1);
+  VCMP_U64(6, v6, 0, -5, 0, -1, 0, 3, 0, 7, 0, -5, 0, -1, 0, 3, 0, 7);
+}
+
+void TEST_CASE3(void) {
+  const uint32_t scalar = 5;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 1, -2, 3, -4, 5, -6, 7, -8, 9, -10, 11, -12, 13, -14, 15, -16);
+  asm volatile("vwsubu.vx v6, v2, %[A]" ::[A] "r"(scalar));
+  VSET(16, e16, m1);
+  VCMP_U16(7, v6, -4, 249, -2, 247, 0, 245, 2, 243, 4, 241, 6, 239, 8, 237, 10,
+           235);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 1, -2, 3, -4, 5, -6, 7, -8, 9, -10, 11, -12, 13, -14, 15, -16);
+  asm volatile("vwsubu.vx v6, v2, %[A]" ::[A] "r"(scalar));
+  VSET(16, e32, m1);
+  VCMP_U32(8, v6, -4, 65529, -2, 65527, 0, 65525, 2, 65523, 4, 65521, 6, 65519,
+           8, 65517, 10, 65515);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 1, -2, 3, -4, 5, -6, 7, -8, 9, -10, 11, -12, 13, -14, 15, -16);
+  asm volatile("vwsubu.vx v6, v2, %[A]" ::[A] "r"(scalar));
+  VSET(16, e64, m1);
+  VCMP_U64(9, v6, -4, 4294967289, -2, 4294967287, 0, 4294967285, 2, 4294967283,
+           4, 4294967281, 6, 4294967279, 8, 4294967277, 10, 4294967275);
+}
+
+void TEST_CASE4(void) {
+  const uint32_t scalar = 5;
+
+  VSET(16, e8, m1);
+  VLOAD_8(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwsubu.vx v6, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(16, e16, m1);
+  VCMP_U16(10, v6, 0, -3, 0, -1, 0, 1, 0, 3, 0, -3, 0, -1, 0, 1, 0, 3);
+
+  VSET(16, e16, m1);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwsubu.vx v6, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(16, e32, m1);
+  VCMP_U32(11, v6, 0, -3, 0, -1, 0, 1, 0, 3, 0, -3, 0, -1, 0, 1, 0, 3);
+
+  VSET(16, e32, m1);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwsubu.vx v6, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(16, e64, m1);
+  VCMP_U64(12, v6, 0, -3, 0, -1, 0, 1, 0, 3, 0, -3, 0, -1, 0, 1, 0, 3);
+}
+
+void TEST_CASE5(void) {
+  VSET(16, e8, m1);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v4, 8, 7, 6, 5, 4, 3, 2, 1, 8, 7, 6, 5, 4, 3, 2, 1);
+  asm volatile("vwsubu.wv v6, v2, v4");
+  VSET(16, e16, m1);
+  VCMP_U16(13, v6, -7, -5, -3, -1, 1, 3, 5, 7, -7, -5, -3, -1, 1, 3, 5, 7);
+
+  VSET(16, e16, m1);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v4, 8, 7, 6, 5, 4, 3, 2, 1, 8, 7, 6, 5, 4, 3, 2, 1);
+  asm volatile("vwsubu.wv v6, v2, v4");
+  VSET(16, e32, m1);
+  VCMP_U32(14, v6, -7, -5, -3, -1, 1, 3, 5, 7, -7, -5, -3, -1, 1, 3, 5, 7);
+
+  VSET(16, e32, m1);
+  VLOAD_64(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v4, 8, 7, 6, 5, 4, 3, 2, 1, 8, 7, 6, 5, 4, 3, 2, 1);
+  asm volatile("vwsubu.wv v6, v2, v4");
+  VSET(16, e64, m1);
+  VCMP_U64(15, v6, -7, -5, -3, -1, 1, 3, 5, 7, -7, -5, -3, -1, 1, 3, 5, 7);
+}
+
+void TEST_CASE6(void) {
+  VSET(16, e8, m1);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v4, 8, 7, 6, 5, 4, 3, 2, 1, 8, 7, 6, 5, 4, 3, 2, 1);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwsubu.wv v6, v2, v4, v0.t");
+  VSET(16, e16, m1);
+  VCMP_U16(16, v6, 0, -5, 0, -1, 0, 3, 0, 7, 0, -5, 0, -1, 0, 3, 0, 7);
+
+  VSET(16, e16, m1);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_16(v4, 8, 7, 6, 5, 4, 3, 2, 1, 8, 7, 6, 5, 4, 3, 2, 1);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwsubu.wv v6, v2, v4, v0.t");
+  VSET(16, e32, m1);
+  VCMP_U32(17, v6, 0, -5, 0, -1, 0, 3, 0, 7, 0, -5, 0, -1, 0, 3, 0, 7);
+
+  VSET(16, e32, m1);
+  VLOAD_64(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_32(v4, 8, 7, 6, 5, 4, 3, 2, 1, 8, 7, 6, 5, 4, 3, 2, 1);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwsubu.wv v6, v2, v4, v0.t");
+  VSET(16, e64, m1);
+  VCMP_U64(18, v6, 0, -5, 0, -1, 0, 3, 0, 7, 0, -5, 0, -1, 0, 3, 0, 7);
+}
+
+void TEST_CASE7(void) {
+  const uint32_t scalar = 5;
+
+  VSET(16, e8, m1);
+  VLOAD_16(v2, 1, -2, 3, -4, 5, -6, 7, -8, 9, -10, 11, -12, 13, -14, 15, -16);
+  asm volatile("vwsubu.wx v6, v2, %[A]" ::[A] "r"(scalar));
+  VSET(16, e16, m1);
+  VCMP_U16(19, v6, -4, -7, -2, -9, 0, -11, 2, -13, 4, -15, 6, -17, 8, -19, 10,
+           -21);
+
+  VSET(16, e16, m1);
+  VLOAD_32(v2, 1, -2, 3, -4, 5, -6, 7, -8, 9, -10, 11, -12, 13, -14, 15, -16);
+  asm volatile("vwsubu.wx v6, v2, %[A]" ::[A] "r"(scalar));
+  VSET(16, e32, m1);
+  VCMP_U32(20, v6, -4, -7, -2, -9, 0, -11, 2, -13, 4, -15, 6, -17, 8, -19, 10,
+           -21);
+
+  VSET(16, e32, m1);
+  VLOAD_64(v2, 1, -2, 3, -4, 5, -6, 7, -8, 9, -10, 11, -12, 13, -14, 15, -16);
+  asm volatile("vwsubu.wx v6, v2, %[A]" ::[A] "r"(scalar));
+  VSET(16, e64, m1);
+  VCMP_U64(21, v6, -4, -7, -2, -9, 0, -11, 2, -13, 4, -15, 6, -17, 8, -19, 10,
+           -21);
+}
+
+void TEST_CASE8(void) {
+  const uint32_t scalar = 5;
+
+  VSET(16, e8, m1);
+  VLOAD_16(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwsubu.wx v6, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(16, e16, m1);
+  VCMP_U16(22, v6, 0, -3, 0, -1, 0, 1, 0, 3, 0, -3, 0, -1, 0, 1, 0, 3);
+
+  VSET(16, e16, m1);
+  VLOAD_32(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwsubu.wx v6, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(16, e32, m1);
+  VCMP_U32(23, v6, 0, -3, 0, -1, 0, 1, 0, 3, 0, -3, 0, -1, 0, 1, 0, 3);
+
+  VSET(16, e32, m1);
+  VLOAD_64(v2, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v6);
+  asm volatile("vwsubu.wx v6, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VSET(16, e64, m1);
+  VCMP_U64(24, v6, 0, -3, 0, -1, 0, 1, 0, 3, 0, -3, 0, -1, 0, 1, 0, 3);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+  TEST_CASE6();
+  TEST_CASE7();
+  TEST_CASE8();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vxor.c b/apps/riscv-tests/isa/rv64uv/vxor.c
new file mode 100644
index 0000000..361f4d7
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vxor.c
@@ -0,0 +1,309 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1() {
+  VSET(12, e8, m1);
+  VLOAD_8(v2, 0xff, 0x01, 0xf0, 0xff, 0x01, 0xf0, 0xff, 0x01, 0xf0, 0xff, 0x01,
+          0xf0);
+  VLOAD_8(v3, 0xf0, 0x03, 0xf0, 0xf0, 0x03, 0xf0, 0xf0, 0x03, 0xf0, 0xf0, 0x03,
+          0xf0);
+  asm volatile("vxor.vv v1, v2, v3");
+  VCMP_U8(1, v1, 0x0f, 0x02, 0x00, 0x0f, 0x02, 0x00, 0x0f, 0x02, 0x00, 0x0f,
+          0x02, 0x00);
+
+  VSET(12, e16, m1);
+  VLOAD_16(v2, 0xffff, 0x0001, 0xf0f0, 0xffff, 0x0001, 0xf0f0, 0xffff, 0x0001,
+           0xf0f0, 0xffff, 0x0001, 0xf0f0);
+  VLOAD_16(v3, 0xff00, 0x0003, 0xf0f0, 0xff00, 0x0003, 0xf0f0, 0xff00, 0x0003,
+           0xf0f0, 0xff00, 0x0003, 0xf0f0);
+  asm volatile("vxor.vv v1, v2, v3");
+  VCMP_U16(2, v1, 0x00ff, 0x0002, 0x0000, 0x00ff, 0x0002, 0x0000, 0x00ff,
+           0x0002, 0x0000, 0x00ff, 0x0002, 0x0000);
+
+  VSET(12, e32, m1);
+  VLOAD_32(v2, 0xffffffff, 0x00000001, 0xf0f0f0f0, 0xffffffff, 0x00000001,
+           0xf0f0f0f0, 0xffffffff, 0x00000001, 0xf0f0f0f0, 0xffffffff,
+           0x00000001, 0xf0f0f0f0);
+  VLOAD_32(v3, 0xffff0000, 0x00000003, 0xf0f0f0f0, 0xffff0000, 0x00000003,
+           0xf0f0f0f0, 0xffff0000, 0x00000003, 0xf0f0f0f0, 0xffff0000,
+           0x00000003, 0xf0f0f0f0);
+  asm volatile("vxor.vv v1, v2, v3");
+  VCMP_U32(3, v1, 0x0000ffff, 0x00000002, 0x00000000, 0x0000ffff, 0x00000002,
+           0x00000000, 0x0000ffff, 0x00000002, 0x00000000, 0x0000ffff,
+           0x00000002, 0x00000000);
+
+  VSET(12, e64, m1);
+  VLOAD_64(v2, 0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0);
+  VLOAD_64(v3, 0xffffffff00000000, 0x0000000000000003, 0xf0f0f0f0f0f0f0f0,
+           0xffffffff00000000, 0x0000000000000003, 0xf0f0f0f0f0f0f0f0,
+           0xffffffff00000000, 0x0000000000000003, 0xf0f0f0f0f0f0f0f0,
+           0xffffffff00000000, 0x0000000000000003, 0xf0f0f0f0f0f0f0f0);
+  asm volatile("vxor.vv v1, v2, v3");
+  VCMP_U64(4, v1, 0x00000000ffffffff, 0x0000000000000002, 0x0000000000000000,
+           0x00000000ffffffff, 0x0000000000000002, 0x0000000000000000,
+           0x00000000ffffffff, 0x0000000000000002, 0x0000000000000000,
+           0x00000000ffffffff, 0x0000000000000002, 0x0000000000000000);
+}
+
+void TEST_CASE2() {
+  VSET(12, e8, m1);
+  VLOAD_8(v2, 0xff, 0x01, 0xf0, 0xff, 0x01, 0xf0, 0xff, 0x01, 0xf0, 0xff, 0x01,
+          0xf0);
+  VLOAD_8(v3, 0xf0, 0x03, 0xf0, 0xf0, 0x03, 0xf0, 0xf0, 0x03, 0xf0, 0xf0, 0x03,
+          0xf0);
+  VLOAD_8(v0, 0x6D, 0x0B);
+  VLOAD_8(v1, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef,
+          0xef);
+  asm volatile("vxor.vv v1, v2, v3, v0.t");
+  VCMP_U8(5, v1, 0x0f, 0xef, 0x00, 0x0f, 0xef, 0x00, 0x0f, 0xef, 0x00, 0x0f,
+          0xef, 0x00);
+
+  VSET(12, e16, m1);
+  VLOAD_16(v2, 0xffff, 0x0001, 0xf0f0, 0xffff, 0x0001, 0xf0f0, 0xffff, 0x0001,
+           0xf0f0, 0xffff, 0x0001, 0xf0f0);
+  VLOAD_16(v3, 0xff00, 0x0003, 0xf0f0, 0xff00, 0x0003, 0xf0f0, 0xff00, 0x0003,
+           0xf0f0, 0xff00, 0x0003, 0xf0f0);
+  VLOAD_8(v0, 0x6D, 0x0B);
+  VLOAD_16(v1, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef,
+           0xbeef, 0xbeef, 0xbeef, 0xbeef);
+  asm volatile("vxor.vv v1, v2, v3, v0.t");
+  VCMP_U16(6, v1, 0x00ff, 0xbeef, 0x0000, 0x00ff, 0xbeef, 0x0000, 0x00ff,
+           0xbeef, 0x0000, 0x00ff, 0xbeef, 0x0000);
+
+  VSET(12, e32, m1);
+  VLOAD_32(v2, 0xffffffff, 0x00000001, 0xf0f0f0f0, 0xffffffff, 0x00000001,
+           0xf0f0f0f0, 0xffffffff, 0x00000001, 0xf0f0f0f0, 0xffffffff,
+           0x00000001, 0xf0f0f0f0);
+  VLOAD_32(v3, 0xffff0000, 0x00000003, 0xf0f0f0f0, 0xffff0000, 0x00000003,
+           0xf0f0f0f0, 0xffff0000, 0x00000003, 0xf0f0f0f0, 0xffff0000,
+           0x00000003, 0xf0f0f0f0);
+  VLOAD_8(v0, 0x6D, 0x0B);
+  VLOAD_32(v1, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
+           0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
+           0xdeadbeef, 0xdeadbeef);
+  asm volatile("vxor.vv v1, v2, v3, v0.t");
+  VCMP_U32(7, v1, 0x0000ffff, 0xdeadbeef, 0x00000000, 0x0000ffff, 0xdeadbeef,
+           0x00000000, 0x0000ffff, 0xdeadbeef, 0x00000000, 0x0000ffff,
+           0xdeadbeef, 0x00000000);
+
+  VSET(12, e64, m1);
+  VLOAD_64(v2, 0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0);
+  VLOAD_64(v3, 0xffffffff00000000, 0x0000000000000003, 0xf0f0f0f0f0f0f0f0,
+           0xffffffff00000000, 0x0000000000000003, 0xf0f0f0f0f0f0f0f0,
+           0xffffffff00000000, 0x0000000000000003, 0xf0f0f0f0f0f0f0f0,
+           0xffffffff00000000, 0x0000000000000003, 0xf0f0f0f0f0f0f0f0);
+  VLOAD_8(v0, 0x6D, 0x0B);
+  VLOAD_64(v1, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef);
+  asm volatile("vxor.vv v1, v2, v3, v0.t");
+  VCMP_U64(8, v1, 0x00000000ffffffff, 0xdeadbeefdeadbeef, 0x0000000000000000,
+           0x00000000ffffffff, 0xdeadbeefdeadbeef, 0x0000000000000000,
+           0x00000000ffffffff, 0xdeadbeefdeadbeef, 0x0000000000000000,
+           0x00000000ffffffff, 0xdeadbeefdeadbeef, 0x0000000000000000);
+}
+
+void TEST_CASE3() {
+  const uint64_t scalar = 0x0ff00ff00ff00ff0;
+
+  VSET(12, e8, m1);
+  VLOAD_8(v2, 0xff, 0x01, 0xf0, 0xff, 0x01, 0xf0, 0xff, 0x01, 0xf0, 0xff, 0x01,
+          0xf0);
+  asm volatile("vxor.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U8(9, v1, 0x0f, 0xf1, 0x00, 0x0f, 0xf1, 0x00, 0x0f, 0xf1, 0x00, 0x0f,
+          0xf1, 0x00);
+
+  VSET(12, e16, m1);
+  VLOAD_16(v2, 0xffff, 0x0001, 0xf0f0, 0xffff, 0x0001, 0xf0f0, 0xffff, 0x0001,
+           0xf0f0, 0xffff, 0x0001, 0xf0f0);
+  asm volatile("vxor.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U16(10, v1, 0xf00f, 0x0ff1, 0xff00, 0xf00f, 0x0ff1, 0xff00, 0xf00f,
+           0x0ff1, 0xff00, 0xf00f, 0x0ff1, 0xff00);
+
+  VSET(12, e32, m1);
+  VLOAD_32(v2, 0xffffffff, 0x00000001, 0xf0f0f0f0, 0xffffffff, 0x00000001,
+           0xf0f0f0f0, 0xffffffff, 0x00000001, 0xf0f0f0f0, 0xffffffff,
+           0x00000001, 0xf0f0f0f0);
+  asm volatile("vxor.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U32(11, v1, 0xf00ff00f, 0x0ff00ff1, 0xff00ff00, 0xf00ff00f, 0x0ff00ff1,
+           0xff00ff00, 0xf00ff00f, 0x0ff00ff1, 0xff00ff00, 0xf00ff00f,
+           0x0ff00ff1, 0xff00ff00);
+
+  VSET(12, e64, m1);
+  VLOAD_64(v2, 0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0);
+  asm volatile("vxor.vx v1, v2, %[A]" ::[A] "r"(scalar));
+  VCMP_U64(12, v1, 0xf00ff00ff00ff00f, 0x0ff00ff00ff00ff1, 0xff00ff00ff00ff00,
+           0xf00ff00ff00ff00f, 0x0ff00ff00ff00ff1, 0xff00ff00ff00ff00,
+           0xf00ff00ff00ff00f, 0x0ff00ff00ff00ff1, 0xff00ff00ff00ff00,
+           0xf00ff00ff00ff00f, 0x0ff00ff00ff00ff1, 0xff00ff00ff00ff00);
+}
+
+void TEST_CASE4() {
+  const uint64_t scalar = 0x0ff00ff00ff00ff0;
+
+  VSET(12, e8, m1);
+  VLOAD_8(v2, 0xff, 0x01, 0xf0, 0xff, 0x01, 0xf0, 0xff, 0x01, 0xf0, 0xff, 0x01,
+          0xf0);
+  VLOAD_8(v0, 0x6D, 0x0B);
+  VLOAD_8(v1, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef,
+          0xef);
+  asm volatile("vxor.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U8(13, v1, 0x0f, 0xef, 0x00, 0x0f, 0xef, 0x00, 0x0f, 0xef, 0x00, 0x0f,
+          0xef, 0x00);
+
+  VSET(12, e16, m1);
+  VLOAD_16(v2, 0xffff, 0x0001, 0xf0f0, 0xffff, 0x0001, 0xf0f0, 0xffff, 0x0001,
+           0xf0f0, 0xffff, 0x0001, 0xf0f0);
+  VLOAD_8(v0, 0x6D, 0x0B);
+  VLOAD_16(v1, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef,
+           0xbeef, 0xbeef, 0xbeef, 0xbeef);
+  asm volatile("vxor.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U16(14, v1, 0xf00f, 0xbeef, 0xff00, 0xf00f, 0xbeef, 0xff00, 0xf00f,
+           0xbeef, 0xff00, 0xf00f, 0xbeef, 0xff00);
+
+  VSET(12, e32, m1);
+  VLOAD_32(v2, 0xffffffff, 0x00000001, 0xf0f0f0f0, 0xffffffff, 0x00000001,
+           0xf0f0f0f0, 0xffffffff, 0x00000001, 0xf0f0f0f0, 0xffffffff,
+           0x00000001, 0xf0f0f0f0);
+  VLOAD_8(v0, 0x6D, 0x0B);
+  VLOAD_32(v1, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
+           0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
+           0xdeadbeef, 0xdeadbeef);
+  asm volatile("vxor.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U32(15, v1, 0xf00ff00f, 0xdeadbeef, 0xff00ff00, 0xf00ff00f, 0xdeadbeef,
+           0xff00ff00, 0xf00ff00f, 0xdeadbeef, 0xff00ff00, 0xf00ff00f,
+           0xdeadbeef, 0xff00ff00);
+
+  VSET(12, e64, m1);
+  VLOAD_64(v2, 0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0);
+  VLOAD_8(v0, 0x6D, 0x0B);
+  VLOAD_64(v1, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef);
+  asm volatile("vxor.vx v1, v2, %[A], v0.t" ::[A] "r"(scalar));
+  VCMP_U64(16, v1, 0xf00ff00ff00ff00f, 0xdeadbeefdeadbeef, 0xff00ff00ff00ff00,
+           0xf00ff00ff00ff00f, 0xdeadbeefdeadbeef, 0xff00ff00ff00ff00,
+           0xf00ff00ff00ff00f, 0xdeadbeefdeadbeef, 0xff00ff00ff00ff00,
+           0xf00ff00ff00ff00f, 0xdeadbeefdeadbeef, 0xff00ff00ff00ff00);
+}
+
+void TEST_CASE5() {
+  VSET(12, e8, m1);
+  VLOAD_8(v2, 0xff, 0x01, 0xf0, 0xff, 0x01, 0xf0, 0xff, 0x01, 0xf0, 0xff, 0x01,
+          0xf0);
+  asm volatile("vxor.vi v1, v2, 15");
+  VCMP_U8(17, v1, 0xf0, 0x0e, 0xff, 0xf0, 0x0e, 0xff, 0xf0, 0x0e, 0xff, 0xf0,
+          0x0e, 0xff);
+
+  VSET(12, e16, m1);
+  VLOAD_16(v2, 0xffff, 0x0001, 0xf0f0, 0xffff, 0x0001, 0xf0f0, 0xffff, 0x0001,
+           0xf0f0, 0xffff, 0x0001, 0xf0f0);
+  asm volatile("vxor.vi v1, v2, 15");
+  VCMP_U16(18, v1, 0xfff0, 0x000e, 0xf0ff, 0xfff0, 0x000e, 0xf0ff, 0xfff0,
+           0x000e, 0xf0ff, 0xfff0, 0x000e, 0xf0ff);
+
+  VSET(12, e32, m1);
+  VLOAD_32(v2, 0xffffffff, 0x00000001, 0xf0f0f0f0, 0xffffffff, 0x00000001,
+           0xf0f0f0f0, 0xffffffff, 0x00000001, 0xf0f0f0f0, 0xffffffff,
+           0x00000001, 0xf0f0f0f0);
+  asm volatile("vxor.vi v1, v2, 15");
+  VCMP_U32(19, v1, 0xfffffff0, 0x0000000e, 0xf0f0f0ff, 0xfffffff0, 0x0000000e,
+           0xf0f0f0ff, 0xfffffff0, 0x0000000e, 0xf0f0f0ff, 0xfffffff0,
+           0x0000000e, 0xf0f0f0ff);
+
+  VSET(12, e64, m1);
+  VLOAD_64(v2, 0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0);
+  asm volatile("vxor.vi v1, v2, 15");
+  VCMP_U64(20, v1, 0xfffffffffffffff0, 0x000000000000000e, 0xf0f0f0f0f0f0f0ff,
+           0xfffffffffffffff0, 0x000000000000000e, 0xf0f0f0f0f0f0f0ff,
+           0xfffffffffffffff0, 0x000000000000000e, 0xf0f0f0f0f0f0f0ff,
+           0xfffffffffffffff0, 0x000000000000000e, 0xf0f0f0f0f0f0f0ff);
+}
+
+void TEST_CASE6() {
+  VSET(12, e8, m1);
+  VLOAD_8(v2, 0xff, 0x01, 0xf0, 0xff, 0x01, 0xf0, 0xff, 0x01, 0xf0, 0xff, 0x01,
+          0xf0);
+  VLOAD_8(v0, 0x6D, 0x0B);
+  VLOAD_8(v1, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef, 0xef,
+          0xef);
+  asm volatile("vxor.vi v1, v2, 15, v0.t");
+  VCMP_U8(21, v1, 0xf0, 0xef, 0xff, 0xf0, 0xef, 0xff, 0xf0, 0xef, 0xff, 0xf0,
+          0xef, 0xff);
+
+  VSET(12, e16, m1);
+  VLOAD_16(v2, 0xffff, 0x0001, 0xf0f0, 0xffff, 0x0001, 0xf0f0, 0xffff, 0x0001,
+           0xf0f0, 0xffff, 0x0001, 0xf0f0);
+  VLOAD_8(v0, 0x6D, 0x0B);
+  VLOAD_16(v1, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef, 0xbeef,
+           0xbeef, 0xbeef, 0xbeef, 0xbeef);
+  asm volatile("vxor.vi v1, v2, 15, v0.t");
+  VCMP_U16(22, v1, 0xfff0, 0xbeef, 0xf0ff, 0xfff0, 0xbeef, 0xf0ff, 0xfff0,
+           0xbeef, 0xf0ff, 0xfff0, 0xbeef, 0xf0ff);
+
+  VSET(12, e32, m1);
+  VLOAD_32(v2, 0xffffffff, 0x00000001, 0xf0f0f0f0, 0xffffffff, 0x00000001,
+           0xf0f0f0f0, 0xffffffff, 0x00000001, 0xf0f0f0f0, 0xffffffff,
+           0x00000001, 0xf0f0f0f0);
+  VLOAD_8(v0, 0x6D, 0x0B);
+  VLOAD_32(v1, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
+           0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
+           0xdeadbeef, 0xdeadbeef);
+  asm volatile("vxor.vi v1, v2, 15, v0.t");
+  VCMP_U32(23, v1, 0xfffffff0, 0xdeadbeef, 0xf0f0f0ff, 0xfffffff0, 0xdeadbeef,
+           0xf0f0f0ff, 0xfffffff0, 0xdeadbeef, 0xf0f0f0ff, 0xfffffff0,
+           0xdeadbeef, 0xf0f0f0ff);
+
+  VSET(12, e64, m1);
+  VLOAD_64(v2, 0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0,
+           0xffffffffffffffff, 0x0000000000000001, 0xf0f0f0f0f0f0f0f0);
+  VLOAD_8(v0, 0x6D, 0x0B);
+  VLOAD_64(v1, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef,
+           0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef);
+  asm volatile("vxor.vi v1, v2, 15, v0.t");
+  VCMP_U64(40, v1, 0xfffffffffffffff0, 0xdeadbeefdeadbeef, 0xf0f0f0f0f0f0f0ff,
+           0xfffffffffffffff0, 0xdeadbeefdeadbeef, 0xf0f0f0f0f0f0f0ff,
+           0xfffffffffffffff0, 0xdeadbeefdeadbeef, 0xf0f0f0f0f0f0f0ff,
+           0xfffffffffffffff0, 0xdeadbeefdeadbeef, 0xf0f0f0f0f0f0f0ff);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+  TEST_CASE6();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/isa/rv64uv/vzext.c b/apps/riscv-tests/isa/rv64uv/vzext.c
new file mode 100644
index 0000000..5434dd5
--- /dev/null
+++ b/apps/riscv-tests/isa/rv64uv/vzext.c
@@ -0,0 +1,115 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Author: Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
+//         Basile Bougenot <bbougenot@student.ethz.ch>
+
+#include "vector_macros.h"
+
+void TEST_CASE1(void) {
+  VSET(16, e16, m1);
+  VLOAD_8(v1, 1, 2, -3, -4, 5, 6, -7, -8, -1, -2, 3, 4, -5, -6, 7, 8);
+  asm volatile("vzext.vf2 v2, v1");
+  VCMP_U16(1, v2, 1, 2, 253, 252, 5, 6, 249, 248, 255, 254, 3, 4, 251, 250, 7,
+           8);
+
+  VSET(16, e32, m1);
+  VLOAD_16(v1, 1, 2, -3, -4, 5, 6, -7, -8, -1, -2, 3, 4, -5, -6, 7, 8);
+  asm volatile("vzext.vf2 v2, v1");
+  VCMP_U32(2, v2, 1, 2, 65533, 65532, 5, 6, 65529, 65528, 65535, 65534, 3, 4,
+           65531, 65530, 7, 8);
+
+  VSET(16, e64, m1);
+  VLOAD_32(v1, 1, 2, -3, -4, 5, 6, -7, -8, -1, -2, 3, 4, -5, -6, 7, 8);
+  asm volatile("vzext.vf2 v2, v1");
+  VCMP_U64(3, v2, 1, 2, 4294967293, 4294967292, 5, 6, 4294967289, 4294967288,
+           4294967295, 4294967294, 3, 4, 4294967291, 4294967290, 7, 8);
+}
+
+void TEST_CASE2(void) {
+  VSET(16, e16, m1);
+  VLOAD_8(v1, 1, 2, -3, -4, 5, 6, -7, -8, -1, -2, 3, 4, -5, -6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v2);
+  asm volatile("vzext.vf2 v2, v1, v0.t");
+  VCMP_U16(4, v2, 0, 2, 0, 252, 0, 6, 0, 248, 0, 254, 0, 4, 0, 250, 0, 8);
+
+  VSET(16, e32, m1);
+  VLOAD_16(v1, 1, 2, -3, -4, 5, 6, -7, -8, -1, -2, 3, 4, -5, -6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v2);
+  asm volatile("vzext.vf2 v2, v1, v0.t");
+  VCMP_U32(5, v2, 0, 2, 0, 65532, 0, 6, 0, 65528, 0, 65534, 0, 4, 0, 65530, 0,
+           8);
+
+  VSET(16, e64, m1);
+  VLOAD_32(v1, 1, 2, -3, -4, 5, 6, -7, -8, -1, -2, 3, 4, -5, -6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v2);
+  asm volatile("vzext.vf2 v2, v1, v0.t");
+  VCMP_U64(6, v2, 0, 2, 0, 4294967292, 0, 6, 0, 4294967288, 0, 4294967294, 0, 4,
+           0, 4294967290, 0, 8);
+}
+
+void TEST_CASE3(void) {
+  VSET(16, e32, m1);
+  VLOAD_8(v1, 1, 2, -3, -4, 5, 6, -7, -8, -1, -2, 3, 4, -5, -6, 7, 8);
+  asm volatile("vzext.vf4 v2, v1");
+  VCMP_U32(7, v2, 1, 2, 253, 252, 5, 6, 249, 248, 255, 254, 3, 4, 251, 250, 7,
+           8);
+
+  VSET(16, e64, m1);
+  VLOAD_16(v1, 1, 2, -3, -4, 5, 6, -7, -8, -1, -2, 3, 4, -5, -6, 7, 8);
+  asm volatile("vzext.vf4 v2, v1");
+  VCMP_U64(8, v2, 1, 2, 65533, 65532, 5, 6, 65529, 65528, 65535, 65534, 3, 4,
+           65531, 65530, 7, 8);
+}
+
+void TEST_CASE4(void) {
+  VSET(16, e32, m1);
+  VLOAD_8(v1, 1, 2, -3, -4, 5, 6, -7, -8, -1, -2, 3, 4, -5, -6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v2);
+  asm volatile("vzext.vf4 v2, v1, v0.t");
+  VCMP_U32(9, v2, 0, 2, 0, 252, 0, 6, 0, 248, 0, 254, 0, 4, 0, 250, 0, 8);
+
+  VSET(16, e64, m1);
+  VLOAD_16(v1, 1, 2, -3, -4, 5, 6, -7, -8, -1, -2, 3, 4, -5, -6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v2);
+  asm volatile("vzext.vf4 v2, v1, v0.t");
+  VCMP_U64(10, v2, 0, 2, 0, 65532, 0, 6, 0, 65528, 0, 65534, 0, 4, 0, 65530, 0,
+           8);
+}
+
+void TEST_CASE5(void) {
+  VSET(16, e64, m1);
+  VLOAD_8(v1, 1, 2, -3, -4, 5, 6, -7, -8, -1, -2, 3, 4, -5, -6, 7, 8);
+  asm volatile("vzext.vf8 v2, v1");
+  VCMP_U64(11, v2, 1, 2, 253, 252, 5, 6, 249, 248, 255, 254, 3, 4, 251, 250, 7,
+           8);
+}
+
+void TEST_CASE6(void) {
+  VSET(16, e64, m1);
+  VLOAD_8(v1, 1, 2, -3, -4, 5, 6, -7, -8, -1, -2, 3, 4, -5, -6, 7, 8);
+  VLOAD_8(v0, 0xAA, 0xAA);
+  VCLEAR(v2);
+  asm volatile("vzext.vf8 v2, v1, v0.t");
+  VCMP_U64(12, v2, 0, 2, 0, 252, 0, 6, 0, 248, 0, 254, 0, 4, 0, 250, 0, 8);
+}
+
+int main(void) {
+  INIT_CHECK();
+  enable_vec();
+
+  TEST_CASE1();
+  TEST_CASE2();
+  TEST_CASE3();
+  TEST_CASE4();
+  TEST_CASE5();
+  TEST_CASE6();
+
+  EXIT_CHECK();
+}
diff --git a/apps/riscv-tests/mt/.gitignore b/apps/riscv-tests/mt/.gitignore
new file mode 100644
index 0000000..131616e
--- /dev/null
+++ b/apps/riscv-tests/mt/.gitignore
@@ -0,0 +1,6 @@
+*.riscv
+*.host
+*.o
+*.dump
+*.out
+*.hex
diff --git a/apps/riscv-tests/mt/Makefile b/apps/riscv-tests/mt/Makefile
new file mode 100644
index 0000000..b45e551
--- /dev/null
+++ b/apps/riscv-tests/mt/Makefile
@@ -0,0 +1,162 @@
+#/=======================================================================
+# UCB VLSI FLOW: Makefile for riscv-bmarks/mt
+#-----------------------------------------------------------------------
+# Henry Cook (hcook@cs.berkeley.edu)
+#
+
+default: all
+
+bmarkdir = .
+common = ../benchmarks/common
+
+instname = riscv-bmarks-mt
+instbasedir = $(UCB_VLSI_HOME)/install
+
+#--------------------------------------------------------------------
+# Sources
+#--------------------------------------------------------------------
+
+bmarks_matmul = \
+ad_matmul\
+ae_matmul\
+af_matmul\
+ag_matmul\
+ai_matmul\
+ak_matmul\
+al_matmul\
+am_matmul\
+an_matmul\
+ap_matmul\
+aq_matmul\
+ar_matmul\
+at_matmul\
+av_matmul\
+ay_matmul\
+az_matmul\
+bb_matmul\
+bc_matmul\
+bf_matmul\
+bh_matmul\
+bj_matmul\
+bk_matmul\
+bm_matmul\
+bo_matmul\
+br_matmul\
+bs_matmul\
+ce_matmul\
+cf_matmul\
+cg_matmul\
+ci_matmul\
+ck_matmul\
+cl_matmul\
+cm_matmul\
+cs_matmul\
+cv_matmul\
+cy_matmul\
+dc_matmul\
+df_matmul\
+dm_matmul\
+do_matmul\
+dr_matmul\
+ds_matmul\
+du_matmul\
+dv_matmul\
+
+bmarks_vvadd = \
+vvadd0\
+vvadd1\
+vvadd2\
+vvadd3\
+vvadd4\
+
+bmarks = $(bmarks_vvadd) $(bmarks_matmul)
+
+#--------------------------------------------------------------------
+# Build rules
+#--------------------------------------------------------------------
+
+RISCV_PREFIX=riscv$(XLEN)-unknown-elf-
+RISCV_GCC = $(RISCV_PREFIX)gcc
+RISCV_GCC_OPTS = -std=gnu99 -O2 -ffast-math
+RISCV_LINK = $(RISCV_GCC) -T $(common)/test.ld $(incs)
+RISCV_LINK_OPTS = -nostdlib -nostartfiles -ffast-math -lc
+RISCV_OBJDUMP = $(RISCV_PREFIX)objdump --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.data
+RISCV_SIM = spike -p2
+
+VPATH += $(common) $(common)/../mt-matmul $(common)/../mt-vvadd 
+
+incs  += -I. -I$(bmarkdir)/../env -I$(common) -I$(common)/../mt-matmul -I$(common)/../mt-vvadd
+objs  :=
+
+#include $(patsubst %, $(bmarkdir)/%/bmark.mk, $(bmarks))
+
+#------------------------------------------------------------
+# Build and run benchmarks on riscv simulator
+#------------------------------------------------------------
+
+bmarks_riscv_obj  = $(addsuffix .o,  $(bmarks))
+bmarks_riscv_matmul_bin  = $(addsuffix .riscv,  $(bmarks_matmul))
+bmarks_riscv_vvadd_bin  = $(addsuffix .riscv,  $(bmarks_vvadd))
+bmarks_riscv_dump = $(addsuffix .riscv.dump, $(bmarks))
+bmarks_riscv_hex = $(addsuffix .riscv.hex, $(bmarks))
+bmarks_riscv_out  = $(addsuffix .riscv.out,  $(bmarks))
+bmarks_riscv_bin = $(bmarks_riscv_matmul_bin) $(bmarks_riscv_vvadd_bin)
+
+bmarks_defs   = -DPREALLOCATE=1 -DHOST_DEBUG=0
+bmarks_cycles = 80000
+
+%.hex: %
+	elf2hex 16 32768 $< > $@
+
+$(bmarks_riscv_vvadd_bin): %.riscv: %.o mt-vvadd.o syscalls.o crt.o
+	$(RISCV_LINK) $< mt-vvadd.o syscalls.o crt.o $(RISCV_LINK_OPTS) -o $@
+
+$(bmarks_riscv_matmul_bin): %.riscv: %.o mt-matmul.o syscalls.o crt.o
+	$(RISCV_LINK) $< mt-matmul.o syscalls.o crt.o $(RISCV_LINK_OPTS) -o $@
+
+$(bmarks_riscv_dump): %.riscv.dump: %.riscv
+	$(RISCV_OBJDUMP) $< > $@
+
+$(bmarks_riscv_out): %.riscv.out: %.riscv
+	$(RISCV_SIM) $< > $@
+
+%.o: %.c
+	$(RISCV_GCC) $(RISCV_GCC_OPTS) $(bmarks_defs)  -D__ASSEMBLY__=1 \
+	             -c $(incs) $< -o $@
+
+%.o: %.S
+	$(RISCV_GCC) $(RISCV_GCC_OPTS) $(bmarks_defs) \
+	             -c $(incs) $< -o $@
+
+riscv: $(bmarks_riscv_dump) $(bmarks_riscv_hex)
+run-riscv: $(bmarks_riscv_out)
+	echo; perl -ne 'print "  [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' \
+ 
+junk += $(bmarks_riscv_bin) $(bmarks_riscv_dump) $(bmarks_riscv_hex) $(bmarks_riscv_out) $(bmarks_riscv_obj)
+
+ 
+#------------------------------------------------------------
+# Default
+ 
+all:  riscv
+ 
+#------------------------------------------------------------
+# Install
+
+date_suffix = $(shell date +%Y-%m-%d_%H-%M)
+install_dir = $(instbasedir)/$(instname)-$(date_suffix)
+latest_install = $(shell ls -1 -d $(instbasedir)/$(instname)* | tail -n 1)
+
+install:
+	mkdir $(install_dir)
+	cp -r $(bmarks_riscv_bin) $(bmarks_riscv_dump) $(install_dir)
+
+install-link:
+	rm -rf $(instbasedir)/$(instname)
+	ln -s $(latest_install) $(instbasedir)/$(instname)
+
+#------------------------------------------------------------
+# Clean up
+
+clean:
+	rm -rf $(objs) $(junk) syscall.o crt.o mt-matmul.o mt-vvadd.o
diff --git a/apps/riscv-tests/mt/ad_matmul.c b/apps/riscv-tests/mt/ad_matmul.c
new file mode 100644
index 0000000..60e6e6c
--- /dev/null
+++ b/apps/riscv-tests/mt/ad_matmul.c
@@ -0,0 +1,37 @@
+#include "stdlib.h"
+
+#include "util.h"
+
+#include "dataset.h"
+void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda,  const data_t A[], const data_t B[], data_t C[] )
+{
+   int i, k;
+   int j = coreid*(lda/ncores);
+   int jend = (coreid+1)*(lda/ncores);
+   for ( ; j < jend; j++ )
+   {
+      int j32 = j << 5;
+      data_t* Cj32 = C + j32;
+      for ( k = 0; k < 32; k+=2 )
+      {
+	 data_t Aj32k  = A[k + j32];
+	 data_t Aj32k2 = A[k + 1 + j32];
+	 data_t* Bk32  = B + (k << 5);
+	 data_t* Bk322 = Bk32 + 32;
+	 for ( i = 0; i < 32; i+=4 )
+	 {
+            Cj32[i]   += Aj32k  * Bk32   [i];
+            Cj32[i]   += Aj32k2 * Bk322  [i];
+            Cj32[i+1] += Aj32k  * Bk32 [i+1];
+            Cj32[i+1] += Aj32k2 * Bk322[i+1];
+            Cj32[i+2] += Aj32k  * Bk32 [i+2];
+            Cj32[i+2] += Aj32k2 * Bk322[i+2];
+            Cj32[i+3] += Aj32k  * Bk32 [i+3];
+            Cj32[i+3] += Aj32k2 * Bk322[i+3];
+	 }
+         barrier(ncores);
+      }
+   }
+   
+ 
+}
diff --git a/apps/riscv-tests/mt/ae_matmul.c b/apps/riscv-tests/mt/ae_matmul.c
new file mode 100644
index 0000000..a1f97b2
--- /dev/null
+++ b/apps/riscv-tests/mt/ae_matmul.c
@@ -0,0 +1,110 @@
+#include "stdlib.h"
+
+#include "util.h"
+
+#include "dataset.h"
+void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda,  const data_t A[], const data_t B[], data_t C[] )
+{
+   
+   // ***************************** //
+   // **** ADD YOUR CODE HERE ***** //
+   // ***************************** //
+   //
+   // feel free to make a separate function for MI and MSI versions.
+
+
+ 
+	data_t *b1;
+	data_t *b2;
+	data_t *b3;
+	data_t *b4;
+	data_t c1;
+	data_t c2;
+	data_t c3;
+	data_t c4;
+	data_t a1;
+	data_t a2;
+	data_t a3;
+	data_t a4;
+	data_t a5;
+	data_t a6;
+	data_t a7;
+	data_t a8;
+	int i, j, k;
+	static data_t BB[1024];
+
+
+
+	//transpose B
+		for ( k = 0; k < lda; k++) {
+			for ( i = coreid*(lda/ncores); i < (coreid+1)*(lda/ncores); i++ )  {
+				BB[i*lda + k] = B[k*lda + i];
+			}
+                  barrier(ncores);
+		}
+
+	for ( i = 0; i < lda; i+=4 ) {
+		for ( j = coreid*(lda/ncores); j < (coreid+1)*(lda/ncores); j++ )  {
+			c1 = 0; c2 = 0; c3 = 0; c4 = 0;
+			b1 = &BB[(i+0)*lda];
+			b2 = &BB[(i+1)*lda];
+			b3 = &BB[(i+2)*lda];
+			b4 = &BB[(i+3)*lda];
+			for ( k = 0; k < lda; k+=8 ) { 
+
+				a1 = A[j*lda + k+0];
+				a2 = A[j*lda + k+1];
+				a3 = A[j*lda + k+2];
+				a4 = A[j*lda + k+3];
+				a5 = A[j*lda + k+4];
+				a6 = A[j*lda + k+5];
+				a7 = A[j*lda + k+6];
+				a8 = A[j*lda + k+7];
+
+				c1 += a1 * b1[k+0];
+				c1 += a2 * b1[k+1];
+				c1 += a3 * b1[k+2];
+				c1 += a4 * b1[k+3];
+				c1 += a5 * b1[k+4];
+				c1 += a6 * b1[k+5];
+				c1 += a7 * b1[k+6];
+				c1 += a8 * b1[k+7];
+
+				c2 += a1 * b2[k+0];
+				c2 += a2 * b2[k+1];
+				c2 += a3 * b2[k+2];
+				c2 += a4 * b2[k+3];
+				c2 += a5 * b2[k+4];
+				c2 += a6 * b2[k+5];
+				c2 += a7 * b2[k+6];
+				c2 += a8 * b2[k+7];
+
+				c3 += a1 * b3[k+0];
+				c3 += a2 * b3[k+1];
+				c3 += a3 * b3[k+2];
+				c3 += a4 * b3[k+3];
+				c3 += a5 * b3[k+4];
+				c3 += a6 * b3[k+5];
+				c3 += a7 * b3[k+6];
+				c3 += a8 * b3[k+7];
+
+				c4 += a1 * b4[k+0];
+				c4 += a2 * b4[k+1];
+				c4 += a3 * b4[k+2];
+				c4 += a4 * b4[k+3];
+				c4 += a5 * b4[k+4];
+				c4 += a6 * b4[k+5];
+				c4 += a7 * b4[k+6];
+				c4 += a8 * b4[k+7];
+
+
+			}
+			C[i+0 + j*lda] = c1;
+			C[i+1 + j*lda] = c2;
+			C[i+2 + j*lda] = c3;
+			C[i+3 + j*lda] = c4;
+                  barrier(ncores);
+		}
+	}
+
+}
diff --git a/apps/riscv-tests/mt/af_matmul.c b/apps/riscv-tests/mt/af_matmul.c
new file mode 100644
index 0000000..a147b62
--- /dev/null
+++ b/apps/riscv-tests/mt/af_matmul.c
@@ -0,0 +1,79 @@
+#include "stdlib.h"
+
+#include "util.h"
+
+#include "dataset.h"
+void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda,  const data_t A[], const data_t B[], data_t C[] )
+{
+    size_t i, j, k, l;
+  int row,row2, column, column2, column3, column4, column5, column6, column7, column8;
+  data_t element, element2, element3, element4, element5, element6, element7, element8;
+	data_t B1, B2, B3, B4;
+  data_t temp_mat[32]={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
+  data_t temp_mat2[32]={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
+	int local_lda = lda;
+
+  for (l=coreid*local_lda/ncores; l<local_lda*(1+coreid)/ncores; l+=2){
+    row=l*32;
+    row2=(l+1)*32;
+		//element = A[row];
+		//element5 = A[row2];
+    for (i=0; i<local_lda; i+=4){
+      element = A[row+i];
+      element2 = A[row+i+1];
+      element3 = A[row+i+2];
+      element4 = A[row+i+3];
+
+      element5 = A[row2+i];
+      element6 = A[row2+i+1];
+      element7 = A[row2+i+2];
+      element8 = A[row2+i+3];
+
+      column=i*local_lda;
+      column2=(i+1)*local_lda;
+      column3=(i+2)*local_lda;
+      column4=(i+3)*local_lda;
+
+			B1 = B[column];
+			B2 = B[column2];
+			B3 = B[column3];
+			B4 = B[column4];
+	
+      for (j=0; j<lda; j+=4){		
+				temp_mat[j]+=element*B1+element2*B2+element3*B3+element4*B4;
+				temp_mat[j+1]+=element*B[column+j+1]+element2*B[column2+j+1]+element3*B[column3+j+1]+element4*B[column4+j+1];
+				temp_mat[j+2]+=element*B[column+j+2]+element2*B[column2+j+2]+element3*B[column3+j+2]+element4*B[column4+j+2];
+				temp_mat[j+3]+=element*B[column+j+3]+element2*B[column2+j+3]+element3*B[column3+j+3]+element4*B[column4+j+3];
+
+				temp_mat2[j]+=element5*B1+element6*B2+element7*B3+element8*B4;
+				temp_mat2[j+1]+=element5*B[column+j+1]+element6*B[column2+j+1]+element7*B[column3+j+1]+element8*B[column4+j+1];
+				temp_mat2[j+2]+=element5*B[column+j+2]+element6*B[column2+j+2]+element7*B[column3+j+2]+element8*B[column4+j+2];
+				temp_mat2[j+3]+=element5*B[column+j+3]+element6*B[column2+j+3]+element7*B[column3+j+3]+element8*B[column4+j+3];
+
+				B1 = B[column+j+4];
+				B2 = B[column2+j+4];
+				B3 = B[column3+j+4];
+				B4 = B[column4+j+4];
+		
+				}
+			//element = A[row+i+4];
+			//element5 = A[row2+i+4];
+      }
+
+			for(k=0; k<local_lda; k++){
+				C[row+k]=temp_mat[k];
+				temp_mat[k]=0;
+				C[row2+k]=temp_mat2[k];
+				temp_mat2[k]=0;
+
+				}
+
+	
+  }
+   // ***************************** //
+   // **** ADD YOUR CODE HERE ***** //
+   // ***************************** //
+   //
+   // feel free to make a separate function for MI and MSI versions.
+
+}
diff --git a/apps/riscv-tests/mt/ag_matmul.c b/apps/riscv-tests/mt/ag_matmul.c
new file mode 100644
index 0000000..0b9cc6e
--- /dev/null
+++ b/apps/riscv-tests/mt/ag_matmul.c
@@ -0,0 +1,79 @@
+#include "stdlib.h"
+
+#include "util.h"
+
+#include "dataset.h"
+#include "util.h"
+void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda,  const data_t A[], const data_t B[], data_t C[] )
+{    
+    int i, j, k;
+    
+    for ( i = 0; i < lda; i+=2 )
+    {
+        for (k = 0; k < lda; k+=4)
+        {
+            int d0 = B[k*lda + i];
+            int c0 = B[k*lda + i + 1];
+            int d1 = B[(k+1)*lda + i];
+            int c1 = B[(k+1)*lda + i + 1];
+            int d2 = B[(k+2)*lda + i];
+            int c2 = B[(k+2)*lda + i + 1];
+            int d3 = B[(k+3)*lda + i];
+            int c3 = B[(k+3)*lda + i + 1];
+            
+            for ( j = coreid*(lda/ncores); j < (coreid+1)*(lda/ncores); j+=4)
+            {
+                
+                int sum = A[j*lda + k] * d0;
+                sum += A[j*lda + k + 1] * d1;
+                sum += A[j*lda + k + 2] * d2;
+                sum += A[j*lda + k + 3] * d3;
+                C[j*lda +i] += sum;
+                
+                sum = A[j*lda + k] * c0;
+                sum += A[j*lda + k + 1] * c1;
+                sum += A[j*lda + k + 2] * c2;
+                sum += A[j*lda + k + 3] * c3;
+                C[j*lda + i + 1] += sum;
+                
+                sum = A[(j+1)*lda + k] * d0;
+                sum += A[(j+1)*lda + k + 1] * d1;
+                sum += A[(j+1)*lda + k + 2] * d2;
+                sum += A[(j+1)*lda + k + 3] * d3;
+                C[(j+1)*lda +i] += sum;
+                
+                sum = A[(j+1)*lda + k] * c0;
+                sum += A[(j+1)*lda + k + 1] * c1;
+                sum += A[(j+1)*lda + k + 2] * c2;
+                sum += A[(j+1)*lda + k + 3] * c3;
+                C[(j+1)*lda + i + 1] += sum;
+                
+                sum = A[(j+2)*lda + k] * d0;
+                sum += A[(j+2)*lda + k + 1] * d1;
+                sum += A[(j+2)*lda + k + 2] * d2;
+                sum += A[(j+2)*lda + k + 3] * d3;
+                C[(j+2)*lda +i] += sum;
+                
+                sum = A[(j+2)*lda + k] * c0;
+                sum += A[(j+2)*lda + k + 1] * c1;
+                sum += A[(j+2)*lda + k + 2] * c2;
+                sum += A[(j+2)*lda + k + 3] * c3;
+                C[(j+2)*lda + i + 1] += sum;
+                
+                sum = A[(j+3)*lda + k] * d0;
+                sum += A[(j+3)*lda + k + 1] * d1;
+                sum += A[(j+3)*lda + k + 2] * d2;
+                sum += A[(j+3)*lda + k + 3] * d3;
+                C[(j+3)*lda +i] += sum;
+                
+                sum = A[(j+3)*lda + k] * c0;
+                sum += A[(j+3)*lda + k + 1] * c1;
+                sum += A[(j+3)*lda + k + 2] * c2;
+                sum += A[(j+3)*lda + k + 3] * c3;
+                C[(j+3)*lda + i + 1] += sum;
+                
+            }
+            barrier(ncores);
+        }
+    }
+}
diff --git a/apps/riscv-tests/mt/ai_matmul.c b/apps/riscv-tests/mt/ai_matmul.c
new file mode 100644
index 0000000..9d808f3
--- /dev/null
+++ b/apps/riscv-tests/mt/ai_matmul.c
@@ -0,0 +1,72 @@
+#include "stdlib.h"
+
+#include "util.h"
+
+#include "dataset.h"
+#include "util.h"
+void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda,  const data_t A[], const data_t B[], data_t C[] )
+{
+   
+   // ***************************** //
+   // **** ADD YOUR CODE HERE ***** //
+   // ***************************** //
+   //
+   // feel free to make a separate function for MI and MSI versions.
+   
+//----------MSI--------------
+///*
+   int i,j,k;
+   barrier(ncores);
+   for(j = coreid*lda/ncores; j < coreid*lda/ncores + lda/ncores; j++) {
+	for(i = 0; i < lda; i+=4) {
+		data_t Cval0 = 0;
+		data_t Cval1 = 0;
+		data_t Cval2 = 0;
+		data_t Cval3 = 0;
+		for(k = 0; k < lda; k++) {
+			Cval0 += A[j*lda+k]*B[k*lda+i];
+			Cval1 += A[j*lda+k]*B[k*lda+i+1];
+			Cval2 += A[j*lda+k]*B[k*lda+i+2];
+			Cval3 += A[j*lda+k]*B[k*lda+i+3];
+		}
+		C[j*lda+i] = Cval0;
+		C[j*lda+i+1] = Cval1;
+		C[j*lda+i+2] = Cval2;
+		C[j*lda+i+3] = Cval3;
+	}
+   }
+//*/
+
+//------------------MI-------------------
+/*
+   int i,j,k;
+   barrier(nc);
+   for(j = coreid*lda/ncores; j < coreid*lda/ncores + lda/ncores; j++) {
+        for(i = 0; i < lda; i+=4) {
+		data_t Cval0 = 0;
+	        data_t Cval1 = 0;
+        	data_t Cval2 = 0;
+		data_t Cval3 = 0;
+		if(coreid == 0) {
+	               	for(k = 0; k < lda; k++) {
+        	              	Cval0 += A[j*lda+k]*B[k*lda+i];
+				Cval1 += A[j*lda+k]*B[k*lda+i+1];
+				Cval2 += A[j*lda+k]*B[k*lda+i+2];
+				Cval3 += A[j*lda+k]*B[k*lda+i+3];
+			}
+		} else {
+			for(k = lda-1; k >= 0; k--) {
+                                Cval0 += A[j*lda+k]*B[k*lda+i];
+	                        Cval1 += A[j*lda+k]*B[k*lda+i+1];
+                                Cval2 += A[j*lda+k]*B[k*lda+i+2];
+                                Cval3 += A[j*lda+k]*B[k*lda+i+3];
+                        }
+		}
+		C[j*lda+i] = Cval0;
+                C[j*lda+i+1] = Cval1;
+                C[j*lda+i+2] = Cval2;
+                C[j*lda+i+3] = Cval3;
+	}
+   }
+*/
+}
diff --git a/apps/riscv-tests/mt/ak_matmul.c b/apps/riscv-tests/mt/ak_matmul.c
new file mode 100644
index 0000000..e4b34e4
--- /dev/null
+++ b/apps/riscv-tests/mt/ak_matmul.c
@@ -0,0 +1,62 @@
+#include "stdlib.h"
+
+#include "util.h"
+
+#include "dataset.h"
+void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda,  const data_t A[], const data_t B[], data_t C[] )
+{
+   
+   // ***************************** //
+   // **** ADD YOUR CODE HERE ***** //
+   // ***************************** //
+   //
+   // feel free to make a separate function for MI and MSI versions.
+  int i, j, k, ii, jj, bsize;
+  bsize = 16;
+  for ( jj = bsize*coreid; jj < lda; jj += bsize*ncores) {
+    for ( ii = 0; ii < lda; ii += bsize) {
+      for ( j = jj; j < lda && j < jj + bsize; j++) {
+	for ( i = ii; i < lda && i < ii + bsize; i += 8) {
+	  data_t c1 = C[i + j*lda];
+	  data_t c2 = C[i + j*lda + 1];
+	  data_t c3 = C[i + j*lda + 2];
+	  data_t c4 = C[i + j*lda + 3];
+	  data_t c5 = C[i + j*lda + 4];
+	  data_t c6 = C[i + j*lda + 5];
+	  data_t c7 = C[i + j*lda + 6];
+	  data_t c8 = C[i + j*lda + 7];
+	  for ( k = 0; k < lda; k+=4 ) {
+	    for (int x = 0; x < 4; x++) {
+	      data_t a = A[j*lda + k+x];
+	      data_t b1 = B[(k+x)*lda + i];
+	      data_t b2 = B[(k+x)*lda + i + 1];
+	      data_t b3 = B[(k+x)*lda + i + 2];
+	      data_t b4 = B[(k+x)*lda + i + 3];
+	      data_t b5 = B[(k+x)*lda + i + 4];
+	      data_t b6 = B[(k+x)*lda + i + 5];
+	      data_t b7 = B[(k+x)*lda + i + 6];
+	      data_t b8 = B[(k+x)*lda + i + 7];
+	      c1 += a * b1;
+	      c2 += a * b2;
+	      c3 += a * b3;
+	      c4 += a * b4;
+	      c5 += a * b5;
+	      c6 += a * b6;
+	      c7 += a * b7;
+	      c8 += a * b8;
+	    }
+	  }
+	  C[i + j*lda] = c1;
+	  C[i + j*lda + 1] = c2;
+	  C[i + j*lda + 2] = c3;
+	  C[i + j*lda + 3] = c4;
+	  C[i + j*lda + 4] = c5;
+	  C[i + j*lda + 5] = c6;
+	  C[i + j*lda + 6] = c7;
+	  C[i + j*lda + 7] = c8;
+	}
+      }
+    }
+  }
+  
+}
diff --git a/apps/riscv-tests/mt/al_matmul.c b/apps/riscv-tests/mt/al_matmul.c
new file mode 100644
index 0000000..e5ee410
--- /dev/null
+++ b/apps/riscv-tests/mt/al_matmul.c
@@ -0,0 +1,123 @@
+#include "stdlib.h"
+
+#include "util.h"
+
+#include "dataset.h"
+void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda,  const data_t A[], const data_t B[], data_t C[] )
+{
+    int i, j, k, x;
+    data_t temp0, temp1, temp2, temp3, temp4, temp5, temp6, temp7;
+    data_t temp8, temp9, temp10, temp11, temp12, temp13, temp14, temp15;
+ 
+    //complete Q1
+   if(coreid > 1) return; 
+   if(coreid == 0)   {
+      for(j = 0; j < 32; j++) {
+         temp0  = C[j*lda];
+         temp1  = C[1  + j*lda];
+         temp2  = C[2  + j*lda];
+         temp3  = C[3  + j*lda];
+         temp4  = C[4  + j*lda];
+         temp5  = C[5  + j*lda];
+         temp6  = C[6  + j*lda];
+         temp7  = C[7  + j*lda];
+         temp8  = C[8  + j*lda];
+         temp9  = C[9  + j*lda];
+         temp10 = C[10 + j*lda];
+         temp11 = C[11 + j*lda];
+         temp12 = C[12 + j*lda];
+         temp13 = C[13 + j*lda];
+         temp14 = C[14 + j*lda];
+         temp15 = C[15 + j*lda];
+         for(k = 0; k < 32; k++) {
+            temp0  += A[j*lda + k] * B[k*lda];
+            temp1  += A[j*lda + k] * B[1+k*lda];
+            temp2  += A[j*lda + k] * B[2+k*lda];
+            temp3  += A[j*lda + k] * B[3+k*lda];
+            temp4  += A[j*lda + k] * B[4+k*lda];
+            temp5  += A[j*lda + k] * B[5+k*lda];
+            temp6  += A[j*lda + k] * B[6+k*lda];
+            temp7  += A[j*lda + k] * B[7+k*lda];
+            temp8  += A[j*lda + k] * B[8+k*lda];
+            temp9  += A[j*lda + k] * B[9+k*lda];
+            temp10 += A[j*lda + k] * B[10+k*lda];
+            temp11 += A[j*lda + k] * B[11+k*lda];
+            temp12 += A[j*lda + k] * B[12+k*lda];
+            temp13 += A[j*lda + k] * B[13+k*lda];
+            temp14 += A[j*lda + k] * B[14+k*lda];
+            temp15 += A[j*lda + k] * B[15+k*lda];
+         }
+         C[j*lda] = temp0;
+         C[1  + j*lda] = temp1;
+         C[2  + j*lda] = temp2;
+         C[3  + j*lda] = temp3;
+         C[4  + j*lda] = temp4;
+         C[5  + j*lda] = temp5;
+         C[6  + j*lda] = temp6;
+         C[7  + j*lda] = temp7;
+         C[8  + j*lda] = temp8;
+         C[9  + j*lda] = temp9;
+         C[10 + j*lda] = temp10;
+         C[11 + j*lda] = temp11;
+         C[12 + j*lda] = temp12;
+         C[13 + j*lda] = temp13;
+         C[14 + j*lda] = temp14;
+         C[15 + j*lda] = temp15;
+      }
+   }
+
+   if( coreid == 1 || ncores == 1) {
+      for(j = 0; j < 32; j++) {
+         temp0  = C[16 + j*lda];
+         temp1  = C[17 + j*lda];
+         temp2  = C[18 + j*lda];
+         temp3  = C[19 + j*lda];
+         temp4  = C[20 + j*lda];
+         temp5  = C[21 + j*lda];
+         temp6  = C[22 + j*lda];
+         temp7  = C[23 + j*lda];
+         temp8  = C[24 + j*lda];
+         temp9  = C[25 + j*lda];
+         temp10 = C[26 + j*lda];
+         temp11 = C[27 + j*lda];
+         temp12 = C[28 + j*lda];
+         temp13 = C[29 + j*lda];
+         temp14 = C[30 + j*lda];
+         temp15 = C[31 + j*lda];
+         for(k = 0; k < 32; k++) {
+            temp0  += A[j*lda + k] * B[16 + k*lda];
+            temp1  += A[j*lda + k] * B[17 + k*lda];
+            temp2  += A[j*lda + k] * B[18 + k*lda];
+            temp3  += A[j*lda + k] * B[19 + k*lda];
+            temp4  += A[j*lda + k] * B[20 + k*lda];
+            temp5  += A[j*lda + k] * B[21 + k*lda];
+            temp6  += A[j*lda + k] * B[22 + k*lda];
+            temp7  += A[j*lda + k] * B[23 + k*lda];
+            temp8  += A[j*lda + k] * B[24 + k*lda];
+            temp9  += A[j*lda + k] * B[25 + k*lda];
+            temp10 += A[j*lda + k] * B[26 + k*lda];
+            temp11 += A[j*lda + k] * B[27 + k*lda];
+            temp12 += A[j*lda + k] * B[28 + k*lda];
+            temp13 += A[j*lda + k] * B[29 + k*lda];
+            temp14 += A[j*lda + k] * B[30 + k*lda];
+            temp15 += A[j*lda + k] * B[31 + k*lda];
+         }
+         C[16 + j*lda] = temp0;
+         C[17 + j*lda] = temp1;
+         C[18 + j*lda] = temp2;
+         C[19 + j*lda] = temp3;
+         C[20 + j*lda] = temp4;
+         C[21 + j*lda] = temp5;
+         C[22 + j*lda] = temp6;
+         C[23 + j*lda] = temp7;
+         C[24 + j*lda] = temp8;
+         C[25 + j*lda] = temp9;
+         C[26 + j*lda] = temp10;
+         C[27 + j*lda] = temp11;
+         C[28 + j*lda] = temp12;
+         C[29 + j*lda] = temp13;
+         C[30 + j*lda] = temp14;
+         C[31 + j*lda] = temp15;
+      }
+   }
+}
diff --git a/apps/riscv-tests/mt/am_matmul.c b/apps/riscv-tests/mt/am_matmul.c
new file mode 100644
index 0000000..a5622fe
--- /dev/null
+++ b/apps/riscv-tests/mt/am_matmul.c
@@ -0,0 +1,64 @@
+#include "stdlib.h"
+
+#include "util.h"
+
+#include "dataset.h"
+void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda,  const data_t A[], const data_t B[], data_t C[] )
+{
+  size_t i, j, k, l;
+  int row,row2, column, column2, column3, column4, column5, column6, column7, column8;
+  size_t max_dim = 32*32;
+  data_t element, element2, element3, element4, element5, element6, element7, element8;
+  data_t temp_mat[32]={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
+  data_t temp_mat2[32]={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
+  //for (i=coreid*max_dim/ncores; i<(max_dim/ncores+coreid*max_dim/ncores); i+=8){
+  for (l=coreid*32/ncores; l<32*(1+coreid)/ncores; l+=2){
+    row=l*32;
+    row2=(l+1)*32;
+    for (i=0; i<lda; i+=4){
+      element = A[row+i];
+      element2 = A[row+i+1];
+      element3 = A[row+i+2];
+      element4 = A[row+i+3];
+      element5 = A[row2+i];
+      element6 = A[row2+i+1];
+      element7 = A[row2+i+2];
+      element8 = A[row2+i+3];
+      column=i*32;
+      column2=(i+1)*32;
+      column3=(i+2)*32;
+      column4=(i+3)*32;
+      for (j=0; j<32; j+=4){
+	temp_mat[j]+=element*B[column+j]+element2*B[column2+j]+element3*B[column3+j]+element4*B[column4+j];
+	temp_mat[j+1]+=element*B[column+j+1]+element2*B[column2+j+1]+element3*B[column3+j+1]+element4*B[column4+j+1];
+	temp_mat[j+2]+=element*B[column+j+2]+element2*B[column2+j+2]+element3*B[column3+j+2]+element4*B[column4+j+2];
+	temp_mat[j+3]+=element*B[column+j+3]+element2*B[column2+j+3]+element3*B[column3+j+3]+element4*B[column4+j+3];
+	temp_mat2[j]+=element5*B[column+j]+element6*B[column2+j]+element7*B[column3+j]+element8*B[column4+j];
+	temp_mat2[j+1]+=element5*B[column+j+1]+element6*B[column2+j+1]+element7*B[column3+j+1]+element8*B[column4+j+1];
+	temp_mat2[j+2]+=element5*B[column+j+2]+element6*B[column2+j+2]+element7*B[column3+j+2]+element8*B[column4+j+2];
+	temp_mat2[j+3]+=element5*B[column+j+3]+element6*B[column2+j+3]+element7*B[column3+j+3]+element8*B[column4+j+3];
+      }
+      /*if (i==28){
+	for(k=0; k<32; k++){
+	  C[row+k]=temp_mat[k];
+	  C[row2+k]=temp_mat2[k];
+	  temp_mat[k]=0;
+	  temp_mat2[k]=0;
+	}
+	}*/
+    }
+    for(k=0; k<32; k++){
+	  C[row+k]=temp_mat[k];
+	  C[row2+k]=temp_mat2[k];
+	  temp_mat[k]=0;
+	  temp_mat2[k]=0;
+    }
+  }
+  
+   // ***************************** //
+   // **** ADD YOUR CODE HERE ***** //
+   // ***************************** //
+   //
+   // feel free to make a separate function for MI and MSI versions.
+
+}
diff --git a/apps/riscv-tests/mt/an_matmul.c b/apps/riscv-tests/mt/an_matmul.c
new file mode 100644
index 0000000..eb76ffa
--- /dev/null
+++ b/apps/riscv-tests/mt/an_matmul.c
@@ -0,0 +1,40 @@
+#include "stdlib.h"
+
+#include "util.h"
+
+#include "dataset.h"
+void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda,  const data_t A[], const data_t B[], data_t C[] )
+{
+   
+   // ***************************** //
+   // **** ADD YOUR CODE HERE ***** //
+    int i, j, k, limit, end, kblock, iblock, r, jblock;
+    int tempA1;
+    int tempB1;
+
+    limit = lda / ncores;
+    j = (coreid)*limit;
+    end = (coreid+1)*limit;
+    
+    kblock = 1;
+    iblock = 1;
+    jblock = 1;
+   for (; j < end; j+= jblock)
+      for ( k = 0; k < lda; k = k + kblock )  
+      {
+	  r = j*lda + k;
+	  tempA1 = A[r];
+
+        for ( i = 0; i < lda; i = i + iblock )  {
+     	  tempB1 = k*lda + i;
+	 
+            C[i + j*lda] +=  tempA1*B[tempB1]; 
+
+	 }
+         barrier(ncores);
+   }
+   // ***************************** //
+   //
+   // feel free to make a separate function for MI and MSI versions.
+ 
+}
diff --git a/apps/riscv-tests/mt/ap_matmul.c b/apps/riscv-tests/mt/ap_matmul.c
new file mode 100644
index 0000000..ef376cb
--- /dev/null
+++ b/apps/riscv-tests/mt/ap_matmul.c
@@ -0,0 +1,29 @@
+#include "stdlib.h"
+
+#include "util.h"
+
+#include "dataset.h"
+void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda,  const data_t A[], const data_t B[], data_t C[] )
+{
+   
+   // ***************************** //
+   // **** ADD YOUR CODE HERE ***** //
+   // ***************************** //
+   //
+   // feel free to make a separate function for MI and MSI versions.
+   int i, j, k, ii, jj, kk;
+   int block = lda / ncores;
+   int leftover = lda % ncores;
+   int start = block * coreid;
+
+
+ 
+   for ( j = start; j < (start+block); j++ )
+      for ( k = 0; k < lda; k++ )  
+      {
+         for ( i = 0; i < lda; i++ ) 
+         {
+            C[i + j*lda] += A[j*lda + k] * B[k*lda + i];
+         }
+      }
+}
diff --git a/apps/riscv-tests/mt/aq_matmul.c b/apps/riscv-tests/mt/aq_matmul.c
new file mode 100644
index 0000000..f2fb3e0
--- /dev/null
+++ b/apps/riscv-tests/mt/aq_matmul.c
@@ -0,0 +1,30 @@
+#include "stdlib.h"
+
+#include "util.h"
+
+#include "dataset.h"
+void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda,  const data_t A[], const data_t B[], data_t C[] )
+{
+   
+   // ***************************** //
+   // **** ADD YOUR CODE HERE ***** //
+   // ***************************** //
+   //
+   // feel free to make a separate function for MI and MSI versions.
+   
+   	for (int  i = coreid; i < lda; i+=ncores*2)
+       	{
+		for (int j = 0; j < lda; j++)
+       		{	
+         		for (int k = 0; k < lda; k++)
+	 		{	 
+	    			int A12 = A[j*lda + k];
+	    			int B1 = B[k*lda + i];
+            			int B2 = B[k*lda + i + ncores];
+	    			C[i+j*lda] += A12 * B1;
+	    			C[i+ncores+j*lda] += A12 * B2;
+	   		 	//C[i+j*lda] += A[j*lda +k] * B[k*lda +i];
+	 		}
+       		}
+	}
+}
diff --git a/apps/riscv-tests/mt/ar_matmul.c b/apps/riscv-tests/mt/ar_matmul.c
new file mode 100644
index 0000000..2299906
--- /dev/null
+++ b/apps/riscv-tests/mt/ar_matmul.c
@@ -0,0 +1,41 @@
+#include "stdlib.h"
+
+#include "util.h"
+
+#include "dataset.h"
+void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda,  const data_t A[], const data_t B[], data_t C[] )
+{
+   
+   // ***************************** //
+   // **** ADD YOUR CODE HERE ***** //
+   // ***************************** //
+   //
+   // feel free to make a separate function for MI and MSI versions.
+   
+   int i, j, k, B_t[32*32], x, y;
+   int ALoc, BLoc, CLoc;
+//   int ii = 0, done = 0;
+   //for(x = coreid*(lda/ncores); x < (coreid+1)*(lda/ncores) && x < lda; x++) {
+   for (x = 0; x < lda; x++) {
+   		for(y = 0; y < lda; y++) {
+   			B_t[y*lda + x] = B[x*lda + y];
+   		}
+   }
+  // for ( ii = lda/4 ; ii < lda ; ii += lda/4)
+   //{
+//   	   for ( i = coreid*(ii/ncores); i < (coreid+1)*(ii/ncores) && i < ii; i++ )
+	   for ( i = coreid*(lda/ncores); i < (coreid+1)*(lda/ncores) && i < lda; i++ )
+	   {
+   		  ALoc = i*lda;
+    	  for ( j = 0; j < lda; j++ ) 
+	      {
+	      	 BLoc = j*lda;
+      		 CLoc = i*lda + j;
+    	     for ( k = 0; k < lda; k++ ) 
+	         {
+            	C[CLoc] += A[ALoc + k] * B_t[BLoc + k];
+        	 }
+    	  }
+	   }
+   //}
+}
diff --git a/apps/riscv-tests/mt/at_matmul.c b/apps/riscv-tests/mt/at_matmul.c
new file mode 100644
index 0000000..1e4eeb3
--- /dev/null
+++ b/apps/riscv-tests/mt/at_matmul.c
@@ -0,0 +1,164 @@
+#include "stdlib.h"
+
+#include "util.h"
+
+#include "dataset.h"
+void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda,  const data_t A[], const data_t B[], data_t C[] )
+{
+	
+	// ***************************** //
+	// **** ADD YOUR CODE HERE ***** //
+	// ***************************** //
+	//
+	// feel free to make a separate function for MI and MSI versions.
+	
+	int i, j, k;
+	
+	/*547287
+	 for ( i = coreid*lda/ncores; i < (coreid+1)*lda/ncores; i++ )
+	 {
+	 for ( j = 0; j < lda; j++ )  
+	 {
+	 int aIndex = j*lda;
+	 int cIndex = i + aIndex;
+	 C[cIndex] += A[aIndex] * B[i];
+	 C[cIndex] += A[aIndex + 1] * B[1*lda + i];
+	 C[cIndex] += A[aIndex + 2] * B[2*lda + i];
+	 C[cIndex] += A[aIndex + 3] * B[3*lda + i];
+	 C[cIndex] += A[aIndex + 4] * B[4*lda + i];
+	 C[cIndex] += A[aIndex + 5] * B[5*lda + i];
+	 C[cIndex] += A[aIndex + 6] * B[6*lda + i];
+	 C[cIndex] += A[aIndex + 7] * B[7*lda + i];
+	 C[cIndex] += A[aIndex + 8] * B[8*lda + i];
+	 C[cIndex] += A[aIndex + 9] * B[9*lda + i];
+	 C[cIndex] += A[aIndex + 10] * B[10*lda + i];
+	 C[cIndex] += A[aIndex + 11] * B[11*lda + i];
+	 C[cIndex] += A[aIndex + 12] * B[12*lda + i];
+	 C[cIndex] += A[aIndex + 13] * B[13*lda + i];
+	 C[cIndex] += A[aIndex + 14] * B[14*lda + i];
+	 C[cIndex] += A[aIndex + 15] * B[15*lda + i];
+	 C[cIndex] += A[aIndex + 16] * B[16*lda + i];
+	 C[cIndex] += A[aIndex + 17] * B[17*lda + i];
+	 C[cIndex] += A[aIndex + 18] * B[18*lda + i];
+	 C[cIndex] += A[aIndex + 19] * B[19*lda + i];
+	 C[cIndex] += A[aIndex + 20] * B[20*lda + i];
+	 C[cIndex] += A[aIndex + 21] * B[21*lda + i];
+	 C[cIndex] += A[aIndex + 22] * B[22*lda + i];
+	 C[cIndex] += A[aIndex + 23] * B[23*lda + i];
+	 C[cIndex] += A[aIndex + 24] * B[24*lda + i];
+	 C[cIndex] += A[aIndex + 25] * B[25*lda + i];
+	 C[cIndex] += A[aIndex + 26] * B[26*lda + i];
+	 C[cIndex] += A[aIndex + 27] * B[27*lda + i];
+	 C[cIndex] += A[aIndex + 28] * B[28*lda + i];
+	 C[cIndex] += A[aIndex + 29] * B[29*lda + i];
+	 C[cIndex] += A[aIndex + 30] * B[30*lda + i];
+	 C[cIndex] += A[aIndex + 31] * B[31*lda + i];	
+	 }
+	 }
+	 */
+  
+	//492827
+	/*	for ( i = coreid*lda/ncores; i < (coreid+1)*lda/ncores; i++ )
+	 {
+	 for ( j = 0; j < lda; j++ )  
+	 {
+	 
+	 int aIndex = j*lda;
+	 int cIndex = i + aIndex;
+	 for ( k = 0; k < lda; k++) 
+	 {
+	 C[cIndex] += A[aIndex + k] * B[k*lda + i];
+	 /*	C[cIndex] += A[aIndex + k+1] * B[(k+1)*lda + i];
+	 C[cIndex] += A[aIndex + k+2] * B[(k+2)*lda + i];
+	 C[cIndex] += A[aIndex + k+3] * B[(k+3)*lda + i];
+	 C[cIndex] += A[aIndex + k+4] * B[(k+4)*lda + i];
+	 C[cIndex] += A[aIndex + k+5] * B[(k+5)*lda + i];
+	 C[cIndex] += A[aIndex + k+6] * B[(k+6)*lda + i];
+	 C[cIndex] += A[aIndex + k+7] * B[(k+7)*lda + i];
+	 C[cIndex] += A[aIndex + k+8] * B[(k+8)*lda + i];
+	 C[cIndex] += A[aIndex + k+9] * B[(k+9)*lda + i];
+	 C[cIndex] += A[aIndex + k+10] * B[(k+10)*lda + i];
+	 C[cIndex] += A[aIndex + k+11] * B[(k+11)*lda + i];
+	 C[cIndex] += A[aIndex + k+12] * B[(k+12)*lda + i];
+	 C[cIndex] += A[aIndex + k+13] * B[(k+13)*lda + i];
+	 C[cIndex] += A[aIndex + k+14] * B[(k+14)*lda + i];
+	 C[cIndex] += A[aIndex + k+15] * B[(k+15)*lda + i];*/
+	/*		}
+	 }
+	 }*/
+	/*
+	 //326378
+	 data_t bTrans[1024];
+	 
+	 for (int counti = 0; counti < 32; counti++) {
+	 for (int countj = 0; countj < 32; countj++) {
+	 *(bTrans + counti + countj*lda) = *(B + countj + counti*lda);
+	 }
+	 }
+	 
+	 
+	 int BLOCKSIZE = 8;
+	 for ( i = 0; i < lda; i+=BLOCKSIZE )
+	 {
+	 for ( int iTemp = i; iTemp < i + BLOCKSIZE; iTemp++ ) {
+	 int iFlag = iTemp*lda;
+	 for ( j = coreid*lda/ncores; j < (coreid+1)*lda/ncores; j++ ) {
+	 int jFlag = j*lda;
+	 int cLoc = jFlag+iTemp;
+	 for ( k = 0; k < lda; k+=8) {
+	 *(C+cLoc) += *(A+jFlag+k) * *(bTrans+iFlag+k);
+	 *(C+cLoc) += *(A+jFlag+k+1) * *(bTrans+iFlag+k+1);
+	 *(C+cLoc) += *(A+jFlag+k+2) * *(bTrans+iFlag+k+2);
+	 *(C+cLoc) += *(A+jFlag+k+3) * *(bTrans+iFlag+k+3);
+	 *(C+cLoc) += *(A+jFlag+k+4) * *(bTrans+iFlag+k+4);
+	 *(C+cLoc) += *(A+jFlag+k+5) * *(bTrans+iFlag+k+5);
+	 *(C+cLoc) += *(A+jFlag+k+6) * *(bTrans+iFlag+k+6);
+	 *(C+cLoc) += *(A+jFlag+k+7) * *(bTrans+iFlag+k+7);
+	 }
+	 }
+	 }
+	 }*/
+	data_t bTrans[1024];
+	
+	for (int counti = 0; counti < 32; counti++) {
+		for (int countj = 0; countj < 32; countj++) {
+			*(bTrans + counti + countj*lda) = *(B + countj + counti*lda);
+		}
+	}
+	
+	
+	int BLOCKSIZE = 8;
+	for ( j = 0; j < lda; j++ )
+	{
+		//for ( int jTemp = j; jTemp < j + BLOCKSIZE; jTemp++ ) {
+		int jFlag = j*lda;
+		for ( i = coreid*lda/ncores; i < (coreid+1)*lda/ncores; i+=BLOCKSIZE ) {
+			for ( int iTemp = i; iTemp < i + BLOCKSIZE; iTemp++ ) {
+				
+				int iFlag = iTemp*lda;
+				int cLoc = jFlag+iTemp;
+				for ( k = 0; k < lda; k+=16) {
+					*(C+cLoc) += *(A+jFlag+k) * *(bTrans+iFlag+k);
+					*(C+cLoc) += *(A+jFlag+k+1) * *(bTrans+iFlag+k+1);
+					*(C+cLoc) += *(A+jFlag+k+2) * *(bTrans+iFlag+k+2);
+					*(C+cLoc) += *(A+jFlag+k+3) * *(bTrans+iFlag+k+3);
+					*(C+cLoc) += *(A+jFlag+k+4) * *(bTrans+iFlag+k+4);
+					*(C+cLoc) += *(A+jFlag+k+5) * *(bTrans+iFlag+k+5);
+					*(C+cLoc) += *(A+jFlag+k+6) * *(bTrans+iFlag+k+6);
+					*(C+cLoc) += *(A+jFlag+k+7) * *(bTrans+iFlag+k+7);
+					*(C+cLoc) += *(A+jFlag+k+8) * *(bTrans+iFlag+k+8);
+					*(C+cLoc) += *(A+jFlag+k+9) * *(bTrans+iFlag+k+9);
+					*(C+cLoc) += *(A+jFlag+k+10) * *(bTrans+iFlag+k+10);
+					*(C+cLoc) += *(A+jFlag+k+11) * *(bTrans+iFlag+k+11);
+					*(C+cLoc) += *(A+jFlag+k+12) * *(bTrans+iFlag+k+12);
+					*(C+cLoc) += *(A+jFlag+k+13) * *(bTrans+iFlag+k+13);
+					*(C+cLoc) += *(A+jFlag+k+14) * *(bTrans+iFlag+k+14);
+					*(C+cLoc) += *(A+jFlag+k+15) * *(bTrans+iFlag+k+15);
+				}
+			}
+		}
+		//}
+	}
+	
+	
+}
diff --git a/apps/riscv-tests/mt/av_matmul.c b/apps/riscv-tests/mt/av_matmul.c
new file mode 100644
index 0000000..0f0dbae
--- /dev/null
+++ b/apps/riscv-tests/mt/av_matmul.c
@@ -0,0 +1,259 @@
+#include "stdlib.h"
+
+#include "util.h"
+
+#include "dataset.h"
+void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda,  const data_t A[], const data_t B[], data_t C[] )
+{
+   
+	//-----------------------------------------------------------------version 2.16, optimize v2.15 get rid of tempb. MSI 83K.w/ test one 81K.
+
+	
+	static __thread data_t TempA[8];
+	static __thread data_t TempB[8];
+	static __thread data_t TempC[8];
+	static __thread int j,m,n;
+	
+			if(coreid == 1 || ncores == 1 )
+	{
+	for ( j = 16; j < 32; j++ )
+     {		
+		  
+      for ( m = 0; m < 4; m++ )  
+      {
+		  
+		 TempA[0] = A[j*lda+0+8*m];
+		 TempA[1] = A[j*lda+1+8*m];
+		 TempA[2] = A[j*lda+2+8*m];
+		 TempA[3] = A[j*lda+3+8*m];
+		 TempA[4] = A[j*lda+4+8*m];
+		 TempA[5] = A[j*lda+5+8*m];
+		 TempA[6] = A[j*lda+6+8*m];
+		 TempA[7] = A[j*lda+7+8*m];
+		 
+
+		 
+		for( n = 0; n < 4; n++)
+		{
+	     
+		 
+
+		 
+		 
+		 TempC[0] = TempA[0] * B[(0+8*m)*lda+0+8*n]; 
+		 TempC[1] = TempA[0] * B[(0+8*m)*lda+1+8*n]; 
+		 TempC[2] = TempA[0] * B[(0+8*m)*lda+2+8*n]; 
+		 TempC[3] = TempA[0] * B[(0+8*m)*lda+3+8*n]; 
+		 TempC[4] = TempA[0] * B[(0+8*m)*lda+4+8*n]; 
+		 TempC[5] = TempA[0] * B[(0+8*m)*lda+5+8*n]; 
+		 TempC[6] = TempA[0] * B[(0+8*m)*lda+6+8*n]; 
+		 TempC[7] = TempA[0] * B[(0+8*m)*lda+7+8*n]; 
+		 
+		 
+		 TempC[0] += TempA[1] * B[(1+8*m)*lda+0+8*n]; 
+		 TempC[1] += TempA[1] * B[(1+8*m)*lda+1+8*n]; 
+		 TempC[2] += TempA[1] * B[(1+8*m)*lda+2+8*n]; 
+		 TempC[3] += TempA[1] * B[(1+8*m)*lda+3+8*n]; 
+		 TempC[4] += TempA[1] * B[(1+8*m)*lda+4+8*n]; 
+		 TempC[5] += TempA[1] * B[(1+8*m)*lda+5+8*n]; 
+		 TempC[6] += TempA[1] * B[(1+8*m)*lda+6+8*n]; 
+		 TempC[7] += TempA[1] * B[(1+8*m)*lda+7+8*n]; 
+		 
+
+
+		 TempC[0] += TempA[2] * B[(2+8*m)*lda+0+8*n]; 
+		 TempC[1] += TempA[2] * B[(2+8*m)*lda+1+8*n]; 
+		 TempC[2] += TempA[2] * B[(2+8*m)*lda+2+8*n]; 
+		 TempC[3] += TempA[2] * B[(2+8*m)*lda+3+8*n]; 
+		 TempC[4] += TempA[2] * B[(2+8*m)*lda+4+8*n]; 
+		 TempC[5] += TempA[2] * B[(2+8*m)*lda+5+8*n]; 
+		 TempC[6] += TempA[2] * B[(2+8*m)*lda+6+8*n]; 
+		 TempC[7] += TempA[2] * B[(2+8*m)*lda+7+8*n]; 
+		 
+
+
+		 TempC[0] += TempA[3] * B[(3+8*m)*lda+0+8*n]; 
+		 TempC[1] += TempA[3] * B[(3+8*m)*lda+1+8*n]; 
+		 TempC[2] += TempA[3] * B[(3+8*m)*lda+2+8*n]; 
+		 TempC[3] += TempA[3] * B[(3+8*m)*lda+3+8*n]; 
+		 TempC[4] += TempA[3] * B[(3+8*m)*lda+4+8*n]; 
+		 TempC[5] += TempA[3] * B[(3+8*m)*lda+5+8*n]; 
+		 TempC[6] += TempA[3] * B[(3+8*m)*lda+6+8*n]; 
+		 TempC[7] += TempA[3] * B[(3+8*m)*lda+7+8*n]; 
+
+		 TempC[0] += TempA[4] * B[(4+8*m)*lda+0+8*n]; 
+		 TempC[1] += TempA[4] * B[(4+8*m)*lda+1+8*n]; 
+		 TempC[2] += TempA[4] * B[(4+8*m)*lda+2+8*n]; 
+		 TempC[3] += TempA[4] * B[(4+8*m)*lda+3+8*n]; 
+		 TempC[4] += TempA[4] * B[(4+8*m)*lda+4+8*n]; 
+		 TempC[5] += TempA[4] * B[(4+8*m)*lda+5+8*n]; 
+		 TempC[6] += TempA[4] * B[(4+8*m)*lda+6+8*n]; 
+		 TempC[7] += TempA[4] * B[(4+8*m)*lda+7+8*n]; 
+
+
+		 TempC[0] += TempA[5] * B[(5+8*m)*lda+0+8*n]; 
+		 TempC[1] += TempA[5] * B[(5+8*m)*lda+1+8*n]; 
+		 TempC[2] += TempA[5] * B[(5+8*m)*lda+2+8*n]; 
+		 TempC[3] += TempA[5] * B[(5+8*m)*lda+3+8*n]; 
+		 TempC[4] += TempA[5] * B[(5+8*m)*lda+4+8*n]; 
+		 TempC[5] += TempA[5] * B[(5+8*m)*lda+5+8*n]; 
+		 TempC[6] += TempA[5] * B[(5+8*m)*lda+6+8*n]; 
+		 TempC[7] += TempA[5] * B[(5+8*m)*lda+7+8*n]; 
+		 
+
+
+		 TempC[0] += TempA[6] * B[(6+8*m)*lda+0+8*n]; 
+		 TempC[1] += TempA[6] * B[(6+8*m)*lda+1+8*n]; 
+		 TempC[2] += TempA[6] * B[(6+8*m)*lda+2+8*n]; 
+		 TempC[3] += TempA[6] * B[(6+8*m)*lda+3+8*n]; 
+		 TempC[4] += TempA[6] * B[(6+8*m)*lda+4+8*n]; 
+		 TempC[5] += TempA[6] * B[(6+8*m)*lda+5+8*n]; 
+		 TempC[6] += TempA[6] * B[(6+8*m)*lda+6+8*n]; 
+		 TempC[7] += TempA[6] * B[(6+8*m)*lda+7+8*n]; 
+
+
+		 TempC[0] += TempA[7] * B[(7+8*m)*lda+0+8*n]; 
+		 TempC[1] += TempA[7] * B[(7+8*m)*lda+1+8*n]; 
+		 TempC[2] += TempA[7] * B[(7+8*m)*lda+2+8*n]; 
+		 TempC[3] += TempA[7] * B[(7+8*m)*lda+3+8*n]; 
+		 TempC[4] += TempA[7] * B[(7+8*m)*lda+4+8*n]; 
+		 TempC[5] += TempA[7] * B[(7+8*m)*lda+5+8*n]; 
+		 TempC[6] += TempA[7] * B[(7+8*m)*lda+6+8*n]; 
+		 TempC[7] += TempA[7] * B[(7+8*m)*lda+7+8*n]; 
+		 
+
+		
+		 C[0+8*n+j*lda] += TempC[0];
+		 C[1+8*n+j*lda] += TempC[1];
+		 C[2+8*n+j*lda] += TempC[2];
+		 C[3+8*n+j*lda] += TempC[3];
+		 C[4+8*n+j*lda] += TempC[4];
+		 C[5+8*n+j*lda] += TempC[5];
+		 C[6+8*n+j*lda] += TempC[6];
+		 C[7+8*n+j*lda] += TempC[7];
+		 }
+      }
+	 }
+	}
+			if(coreid == 0)
+	{
+	for ( j = 0; j < 16; j++ )
+     {		
+		  
+      for ( m = 0; m < 4; m++ )  
+      {
+		  
+		 TempA[0] = A[j*lda+0+8*m];
+		 TempA[1] = A[j*lda+1+8*m];
+		 TempA[2] = A[j*lda+2+8*m];
+		 TempA[3] = A[j*lda+3+8*m];
+		 TempA[4] = A[j*lda+4+8*m];
+		 TempA[5] = A[j*lda+5+8*m];
+		 TempA[6] = A[j*lda+6+8*m];
+		 TempA[7] = A[j*lda+7+8*m];
+		 
+
+		 
+		for( n = 0; n < 4; n++)
+		{
+	     
+		 
+
+		 
+		 
+		 TempC[0] = TempA[0] * B[(0+8*m)*lda+0+8*n]; 
+		 TempC[1] = TempA[0] * B[(0+8*m)*lda+1+8*n]; 
+		 TempC[2] = TempA[0] * B[(0+8*m)*lda+2+8*n]; 
+		 TempC[3] = TempA[0] * B[(0+8*m)*lda+3+8*n]; 
+		 TempC[4] = TempA[0] * B[(0+8*m)*lda+4+8*n]; 
+		 TempC[5] = TempA[0] * B[(0+8*m)*lda+5+8*n]; 
+		 TempC[6] = TempA[0] * B[(0+8*m)*lda+6+8*n]; 
+		 TempC[7] = TempA[0] * B[(0+8*m)*lda+7+8*n]; 
+		 
+		 
+		 TempC[0] += TempA[1] * B[(1+8*m)*lda+0+8*n]; 
+		 TempC[1] += TempA[1] * B[(1+8*m)*lda+1+8*n]; 
+		 TempC[2] += TempA[1] * B[(1+8*m)*lda+2+8*n]; 
+		 TempC[3] += TempA[1] * B[(1+8*m)*lda+3+8*n]; 
+		 TempC[4] += TempA[1] * B[(1+8*m)*lda+4+8*n]; 
+		 TempC[5] += TempA[1] * B[(1+8*m)*lda+5+8*n]; 
+		 TempC[6] += TempA[1] * B[(1+8*m)*lda+6+8*n]; 
+		 TempC[7] += TempA[1] * B[(1+8*m)*lda+7+8*n]; 
+		 
+
+
+		 TempC[0] += TempA[2] * B[(2+8*m)*lda+0+8*n]; 
+		 TempC[1] += TempA[2] * B[(2+8*m)*lda+1+8*n]; 
+		 TempC[2] += TempA[2] * B[(2+8*m)*lda+2+8*n]; 
+		 TempC[3] += TempA[2] * B[(2+8*m)*lda+3+8*n]; 
+		 TempC[4] += TempA[2] * B[(2+8*m)*lda+4+8*n]; 
+		 TempC[5] += TempA[2] * B[(2+8*m)*lda+5+8*n]; 
+		 TempC[6] += TempA[2] * B[(2+8*m)*lda+6+8*n]; 
+		 TempC[7] += TempA[2] * B[(2+8*m)*lda+7+8*n]; 
+		 
+
+
+		 TempC[0] += TempA[3] * B[(3+8*m)*lda+0+8*n]; 
+		 TempC[1] += TempA[3] * B[(3+8*m)*lda+1+8*n]; 
+		 TempC[2] += TempA[3] * B[(3+8*m)*lda+2+8*n]; 
+		 TempC[3] += TempA[3] * B[(3+8*m)*lda+3+8*n]; 
+		 TempC[4] += TempA[3] * B[(3+8*m)*lda+4+8*n]; 
+		 TempC[5] += TempA[3] * B[(3+8*m)*lda+5+8*n]; 
+		 TempC[6] += TempA[3] * B[(3+8*m)*lda+6+8*n]; 
+		 TempC[7] += TempA[3] * B[(3+8*m)*lda+7+8*n]; 
+
+		 TempC[0] += TempA[4] * B[(4+8*m)*lda+0+8*n]; 
+		 TempC[1] += TempA[4] * B[(4+8*m)*lda+1+8*n]; 
+		 TempC[2] += TempA[4] * B[(4+8*m)*lda+2+8*n]; 
+		 TempC[3] += TempA[4] * B[(4+8*m)*lda+3+8*n]; 
+		 TempC[4] += TempA[4] * B[(4+8*m)*lda+4+8*n]; 
+		 TempC[5] += TempA[4] * B[(4+8*m)*lda+5+8*n]; 
+		 TempC[6] += TempA[4] * B[(4+8*m)*lda+6+8*n]; 
+		 TempC[7] += TempA[4] * B[(4+8*m)*lda+7+8*n]; 
+
+
+		 TempC[0] += TempA[5] * B[(5+8*m)*lda+0+8*n]; 
+		 TempC[1] += TempA[5] * B[(5+8*m)*lda+1+8*n]; 
+		 TempC[2] += TempA[5] * B[(5+8*m)*lda+2+8*n]; 
+		 TempC[3] += TempA[5] * B[(5+8*m)*lda+3+8*n]; 
+		 TempC[4] += TempA[5] * B[(5+8*m)*lda+4+8*n]; 
+		 TempC[5] += TempA[5] * B[(5+8*m)*lda+5+8*n]; 
+		 TempC[6] += TempA[5] * B[(5+8*m)*lda+6+8*n]; 
+		 TempC[7] += TempA[5] * B[(5+8*m)*lda+7+8*n]; 
+		 
+
+
+		 TempC[0] += TempA[6] * B[(6+8*m)*lda+0+8*n]; 
+		 TempC[1] += TempA[6] * B[(6+8*m)*lda+1+8*n]; 
+		 TempC[2] += TempA[6] * B[(6+8*m)*lda+2+8*n]; 
+		 TempC[3] += TempA[6] * B[(6+8*m)*lda+3+8*n]; 
+		 TempC[4] += TempA[6] * B[(6+8*m)*lda+4+8*n]; 
+		 TempC[5] += TempA[6] * B[(6+8*m)*lda+5+8*n]; 
+		 TempC[6] += TempA[6] * B[(6+8*m)*lda+6+8*n]; 
+		 TempC[7] += TempA[6] * B[(6+8*m)*lda+7+8*n]; 
+
+
+		 TempC[0] += TempA[7] * B[(7+8*m)*lda+0+8*n]; 
+		 TempC[1] += TempA[7] * B[(7+8*m)*lda+1+8*n]; 
+		 TempC[2] += TempA[7] * B[(7+8*m)*lda+2+8*n]; 
+		 TempC[3] += TempA[7] * B[(7+8*m)*lda+3+8*n]; 
+		 TempC[4] += TempA[7] * B[(7+8*m)*lda+4+8*n]; 
+		 TempC[5] += TempA[7] * B[(7+8*m)*lda+5+8*n]; 
+		 TempC[6] += TempA[7] * B[(7+8*m)*lda+6+8*n]; 
+		 TempC[7] += TempA[7] * B[(7+8*m)*lda+7+8*n]; 
+		 
+
+		
+		 C[0+8*n+j*lda] += TempC[0];
+		 C[1+8*n+j*lda] += TempC[1];
+		 C[2+8*n+j*lda] += TempC[2];
+		 C[3+8*n+j*lda] += TempC[3];
+		 C[4+8*n+j*lda] += TempC[4];
+		 C[5+8*n+j*lda] += TempC[5];
+		 C[6+8*n+j*lda] += TempC[6];
+		 C[7+8*n+j*lda] += TempC[7];
+		 }
+      }
+	 }
+	}
+}
diff --git a/apps/riscv-tests/mt/ay_matmul.c b/apps/riscv-tests/mt/ay_matmul.c
new file mode 100644
index 0000000..45fb194
--- /dev/null
+++ b/apps/riscv-tests/mt/ay_matmul.c
@@ -0,0 +1,60 @@
+#include "stdlib.h"
+
+#include "util.h"
+
+#include "dataset.h"
+void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda,  const data_t A[], const data_t B[], data_t C[] )
+{
+  if(coreid > 1) return; 
+  static __thread int i, j, k;
+  static __thread data_t tempA0, tempA1, tempA2, tempA3, tempA4, tempA5, tempA6, tempA7;
+  static __thread data_t tempC0, tempC1, tempC2, tempC3, tempC4, tempC5, tempC6, tempC7, tempC8, tempC9, tempC10, tempC11, tempC12, tempC13, tempC14, tempC15;
+
+  static __thread int start, end, jStride, jToRow, jToCol;
+  
+  start = coreid << 9;
+  end = ((ncores == 1) ? 2 : (coreid+1) ) << 9;
+  jStride = 8;
+
+  for (j=start; j < end; j+=jStride) {
+    jToRow = (j>>5)<<5;
+    jToCol = j%32;
+    tempC0  = 0;
+    tempC1  = 0;
+    tempC2  = 0;
+    tempC3  = 0;
+    tempC4  = 0;
+    tempC5  = 0;
+    tempC6  = 0;
+    tempC7  = 0;
+    for ( i=0; i < lda; i+=2 ) {
+      tempA0 = A[i   + jToRow];
+      tempA1 = A[i+1 + jToRow];
+      tempC0  += tempA0 * B[(jToCol   ) + (i<<5)];
+      tempC1  += tempA0 * B[(jToCol+1 ) + (i<<5)];
+      tempC2  += tempA0 * B[(jToCol+2 ) + (i<<5)];
+      tempC3  += tempA0 * B[(jToCol+3 ) + (i<<5)];
+      tempC4  += tempA0 * B[(jToCol+4 ) + (i<<5)];
+      tempC5  += tempA0 * B[(jToCol+5 ) + (i<<5)];
+      tempC6  += tempA0 * B[(jToCol+6 ) + (i<<5)];
+      tempC7  += tempA0 * B[(jToCol+7 ) + (i<<5)];
+      tempC0  += tempA1 * B[(jToCol   ) + ((i+1)<<5)];
+      tempC1  += tempA1 * B[(jToCol+1 ) + ((i+1)<<5)];
+      tempC2  += tempA1 * B[(jToCol+2 ) + ((i+1)<<5)];
+      tempC3  += tempA1 * B[(jToCol+3 ) + ((i+1)<<5)];
+      tempC4  += tempA1 * B[(jToCol+4 ) + ((i+1)<<5)];
+      tempC5  += tempA1 * B[(jToCol+5 ) + ((i+1)<<5)];
+      tempC6  += tempA1 * B[(jToCol+6 ) + ((i+1)<<5)];
+      tempC7  += tempA1 * B[(jToCol+7 ) + ((i+1)<<5)];
+    }
+    C[j] =tempC0;
+    C[j + 1 ]=tempC1;
+    C[j + 2 ]=tempC2;
+    C[j + 3 ]=tempC3;
+    C[j + 4 ]=tempC4;
+    C[j + 5 ]=tempC5;
+    C[j + 6 ]=tempC6;
+    C[j + 7 ]=tempC7;
+  }
+  
+}
diff --git a/apps/riscv-tests/mt/az_matmul.c b/apps/riscv-tests/mt/az_matmul.c
new file mode 100644
index 0000000..1668fb0
--- /dev/null
+++ b/apps/riscv-tests/mt/az_matmul.c
@@ -0,0 +1,181 @@
+#include "stdlib.h"
+
+#include "util.h"
+
+#include "dataset.h"
+void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda,  const data_t A[], const data_t B[], data_t C[] )
+{
+   
+    if(coreid > 1) return; 
+    static __thread int i, j, k;
+    static __thread data_t tempA0, tempA1, tempA2, tempA3, tempA4, tempA5, tempA6, tempA7;
+    static __thread data_t tempC0, tempC1, tempC2, tempC3, tempC4, tempC5, tempC6, tempC7; //tempC8, tempC9, tempC10, tempC11, tempC12, tempC13, tempC14, tempC15;
+
+    static __thread int start, end, jStride, jToRow, jToCol, iToRow;
+
+    start = coreid << 9;
+    end = ((ncores == 1) ? 2 : (coreid+1)) << 9;
+    jStride = 8;
+
+    for (j=start; j < end; j+=jStride) {
+      jToRow = (j>>5)<<5;
+      jToCol = j%32;
+      tempC0  = 0;
+      tempC1  = 0;
+      tempC2  = 0;
+      tempC3  = 0;
+      tempC4  = 0;
+      tempC5  = 0;
+      tempC6  = 0;
+      tempC7  = 0;
+      //tempC8  = 0;
+      //tempC9  = 0;
+      //tempC10 = 0;
+      //tempC11 = 0;
+      //tempC12 = 0;
+      //tempC13 = 0;
+      //tempC14 = 0;
+      //tempC15 = 0;
+      
+      for ( i=0; i < lda; i+=2 ) {
+        iToRow = i << 5;
+
+        tempA0 = A[i   + jToRow];
+        tempA1 = A[i+1 + jToRow];
+        //tempA2 = A[i+2 + jToRow];
+        //tempA3 = A[i+3 + jToRow];
+        //tempA4 = A[i+4 + jToRow];
+        //tempA5 = A[i+5 + jToRow];
+        //tempA6 = A[i+6 + jToRow];
+        //tempA7 = A[i+7 + jToRow];
+        
+        tempC0  += tempA0 * B[(jToCol   ) + (iToRow)];
+        tempC1  += tempA0 * B[(jToCol+1 ) + (iToRow)];
+        tempC2  += tempA0 * B[(jToCol+2 ) + (iToRow)];
+        tempC3  += tempA0 * B[(jToCol+3 ) + (iToRow)];
+        tempC4  += tempA0 * B[(jToCol+4 ) + (iToRow)];
+        tempC5  += tempA0 * B[(jToCol+5 ) + (iToRow)];
+        tempC6  += tempA0 * B[(jToCol+6 ) + (iToRow)];
+        tempC7  += tempA0 * B[(jToCol+7 ) + (iToRow)];
+        //tempC8  += tempA0 * B[(jToCol+8 ) + (iToRow)];
+        //tempC9  += tempA0 * B[(jToCol+9 ) + (iToRow)];
+        //tempC10 += tempA0 * B[(jToCol+10) + (iToRow)];
+        //tempC11 += tempA0 * B[(jToCol+11) + (iToRow)];
+        //tempC12 += tempA0 * B[(jToCol+12) + (iToRow)];
+        //tempC13 += tempA0 * B[(jToCol+13) + (iToRow)];
+        //tempC14 += tempA0 * B[(jToCol+14) + (iToRow)];
+        //tempC15 += tempA0 * B[(jToCol+15) + (iToRow)];
+        
+        iToRow += 32;
+        tempC0  += tempA1 * B[(jToCol   ) + (iToRow)];
+        tempC1  += tempA1 * B[(jToCol+1 ) + (iToRow)];
+        tempC2  += tempA1 * B[(jToCol+2 ) + (iToRow)];
+        tempC3  += tempA1 * B[(jToCol+3 ) + (iToRow)];
+        tempC4  += tempA1 * B[(jToCol+4 ) + (iToRow)];
+        tempC5  += tempA1 * B[(jToCol+5 ) + (iToRow)];
+        tempC6  += tempA1 * B[(jToCol+6 ) + (iToRow)];
+        tempC7  += tempA1 * B[(jToCol+7 ) + (iToRow)];
+        //tempC8  += tempA1 * B[(jToCol+8 ) + (iToRow+32)];
+        //tempC9  += tempA1 * B[(jToCol+9 ) + (iToRow+32)];
+        //tempC10 += tempA1 * B[(jToCol+10) + (iToRow+32)];
+        //tempC11 += tempA1 * B[(jToCol+11) + (iToRow+32)];
+        //tempC12 += tempA1 * B[(jToCol+12) + (iToRow+32)];
+        //tempC13 += tempA1 * B[(jToCol+13) + (iToRow+32)];
+        //tempC14 += tempA1 * B[(jToCol+14) + (iToRow+32)];
+        //tempC15 += tempA1 * B[(jToCol+15) + (iToRow+32)];
+        
+        //iToRow += 32;
+        //tempC0  += tempA2 * B[(jToCol   ) + (iToRow)];
+        //tempC1  += tempA2 * B[(jToCol+1 ) + (iToRow)];
+        //tempC2  += tempA2 * B[(jToCol+2 ) + (iToRow)];
+        //tempC3  += tempA2 * B[(jToCol+3 ) + (iToRow)];
+        //tempC4  += tempA2 * B[(jToCol+4 ) + (iToRow)];
+        //tempC5  += tempA2 * B[(jToCol+5 ) + (iToRow)];
+        //tempC6  += tempA2 * B[(jToCol+6 ) + (iToRow)];
+        //tempC7  += tempA2 * B[(jToCol+7 ) + (iToRow)];
+        //tempC8  += tempA2 * B[(jToCol+8 ) + (iToRow)];
+        //tempC9  += tempA2 * B[(jToCol+9 ) + (iToRow)];
+        //tempC10 += tempA2 * B[(jToCol+10) + (iToRow)];
+        //tempC11 += tempA2 * B[(jToCol+11) + (iToRow)];
+        //tempC12 += tempA2 * B[(jToCol+12) + (iToRow)];
+        //tempC13 += tempA2 * B[(jToCol+13) + (iToRow)];
+        //tempC14 += tempA2 * B[(jToCol+14) + (iToRow)];
+        //tempC15 += tempA2 * B[(jToCol+15) + (iToRow)];
+        
+        //iToRow += 32;
+        //tempC0  += tempA3 * B[(jToCol   ) + (iToRow)];
+        //tempC1  += tempA3 * B[(jToCol+1 ) + (iToRow)];
+        //tempC2  += tempA3 * B[(jToCol+2 ) + (iToRow)];
+        //tempC3  += tempA3 * B[(jToCol+3 ) + (iToRow)];
+        //tempC4  += tempA3 * B[(jToCol+4 ) + (iToRow)];
+        //tempC5  += tempA3 * B[(jToCol+5 ) + (iToRow)];
+        //tempC6  += tempA3 * B[(jToCol+6 ) + (iToRow)];
+        //tempC7  += tempA3 * B[(jToCol+7 ) + (iToRow)];
+        //tempC8  += tempA3 * B[(jToCol+8 ) + (iToRow)];
+        //tempC9  += tempA3 * B[(jToCol+9 ) + (iToRow)];
+        //tempC10 += tempA3 * B[(jToCol+10) + (iToRow)];
+        //tempC11 += tempA3 * B[(jToCol+11) + (iToRow)];
+        //tempC12 += tempA3 * B[(jToCol+12) + (iToRow)];
+        //tempC13 += tempA3 * B[(jToCol+13) + (iToRow)];
+        //tempC14 += tempA3 * B[(jToCol+14) + (iToRow)];
+        //tempC15 += tempA3 * B[(jToCol+15) + (iToRow)];
+        
+        //iToRow += 32;
+        //tempC0 += tempA4 * B[(jToCol   ) + (iToRow)];
+        //tempC1 += tempA4 * B[(jToCol+1 ) + (iToRow)];
+        //tempC2 += tempA4 * B[(jToCol+2 ) + (iToRow)];
+        //tempC3 += tempA4 * B[(jToCol+3 ) + (iToRow)];
+        //tempC4 += tempA4 * B[(jToCol+4 ) + (iToRow)];
+        //tempC5 += tempA4 * B[(jToCol+5 ) + (iToRow)];
+        //tempC6 += tempA4 * B[(jToCol+6 ) + (iToRow)];
+        //tempC7 += tempA4 * B[(jToCol+7 ) + (iToRow)];
+        //
+        //iToRow += 32;
+        //tempC0 += tempA5 * B[(jToCol   ) + (iToRow)];
+        //tempC1 += tempA5 * B[(jToCol+1 ) + (iToRow)];
+        //tempC2 += tempA5 * B[(jToCol+2 ) + (iToRow)];
+        //tempC3 += tempA5 * B[(jToCol+3 ) + (iToRow)];
+        //tempC4 += tempA5 * B[(jToCol+4 ) + (iToRow)];
+        //tempC5 += tempA5 * B[(jToCol+5 ) + (iToRow)];
+        //tempC6 += tempA5 * B[(jToCol+6 ) + (iToRow)];
+        //tempC7 += tempA5 * B[(jToCol+7 ) + (iToRow)];
+        //
+        //iToRow += 32;
+        //tempC0 += tempA6 * B[(jToCol   ) + (iToRow)];
+        //tempC1 += tempA6 * B[(jToCol+1 ) + (iToRow)];
+        //tempC2 += tempA6 * B[(jToCol+2 ) + (iToRow)];
+        //tempC3 += tempA6 * B[(jToCol+3 ) + (iToRow)];
+        //tempC4 += tempA6 * B[(jToCol+4 ) + (iToRow)];
+        //tempC5 += tempA6 * B[(jToCol+5 ) + (iToRow)];
+        //tempC6 += tempA6 * B[(jToCol+6 ) + (iToRow)];
+        //tempC7 += tempA6 * B[(jToCol+7 ) + (iToRow)];
+        //
+        //iToRow += 32;
+        //tempC0 += tempA7 * B[(jToCol   ) + (iToRow)];
+        //tempC1 += tempA7 * B[(jToCol+1 ) + (iToRow)];
+        //tempC2 += tempA7 * B[(jToCol+2 ) + (iToRow)];
+        //tempC3 += tempA7 * B[(jToCol+3 ) + (iToRow)];
+        //tempC4 += tempA7 * B[(jToCol+4 ) + (iToRow)];
+        //tempC5 += tempA7 * B[(jToCol+5 ) + (iToRow)];
+        //tempC6 += tempA7 * B[(jToCol+6 ) + (iToRow)];
+        //tempC7 += tempA7 * B[(jToCol+7 ) + (iToRow)];
+        
+      }
+      C[j     ] = tempC0;
+      C[j + 1 ] = tempC1;
+      C[j + 2 ] = tempC2;
+      C[j + 3 ] = tempC3;
+      C[j + 4 ] = tempC4;
+      C[j + 5 ] = tempC5;
+      C[j + 6 ] = tempC6;
+      C[j + 7 ] = tempC7;
+      //C[j + 8 ] = tempC8 ;
+      //C[j + 9 ] = tempC9 ;
+      //C[j + 10] = tempC10;
+      //C[j + 11] = tempC11;
+      //C[j + 12] = tempC12;
+      //C[j + 13] = tempC13;
+      //C[j + 14] = tempC14;
+      //C[j + 15] = tempC15;
+    }
+}
diff --git a/apps/riscv-tests/mt/bb_matmul.c b/apps/riscv-tests/mt/bb_matmul.c
new file mode 100644
index 0000000..c335ed3
--- /dev/null
+++ b/apps/riscv-tests/mt/bb_matmul.c
@@ -0,0 +1,35 @@
+#include "dataset.h"
+void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda,  const data_t A[], const data_t B[], data_t C[] )
+{
+  int i, j, k;
+
+  for (i = 0; i < lda; i += 2) {
+    for (j = coreid * (lda / ncores); j < (coreid + 1) * (lda / ncores); j += 4) {
+      register data_t c00 = 0, c01 = 0;
+      register data_t c10 = 0, c11 = 0;
+      register data_t c20 = 0, c21 = 0;
+      register data_t c30 = 0, c31 = 0;
+
+      register data_t a0, a1, a2, a3, b0, b1;
+      for (k = 0; k < lda; k++) {
+        a0 = A[j*lda + k + 0*lda];
+        a1 = A[j*lda + k + 1*lda];
+        a2 = A[j*lda + k + 2*lda];
+        a3 = A[j*lda + k + 3*lda];
+
+        b0 = B[k*lda + i + 0];
+        b1 = B[k*lda + i + 1];
+
+        c00 += a0 * b0; c01 += a0 * b1;
+        c10 += a1 * b0; c11 += a1 * b1;
+        c20 += a2 * b0; c21 += a2 * b1;
+        c30 += a3 * b0; c31 += a3 * b1;
+      }
+
+      C[i + j*lda + 0 + 0*lda] = c00; C[i + j*lda + 1 + 0*lda] = c01;
+      C[i + j*lda + 0 + 1*lda] = c10; C[i + j*lda + 1 + 1*lda] = c11;
+      C[i + j*lda + 0 + 2*lda] = c20; C[i + j*lda + 1 + 2*lda] = c21;
+      C[i + j*lda + 0 + 3*lda] = c30; C[i + j*lda + 1 + 3*lda] = c31;
+    }
+  }
+}
diff --git a/apps/riscv-tests/mt/bc_matmul.c b/apps/riscv-tests/mt/bc_matmul.c
new file mode 100644
index 0000000..61c4054
--- /dev/null
+++ b/apps/riscv-tests/mt/bc_matmul.c
@@ -0,0 +1,137 @@
+#include "stdlib.h"
+
+#include "util.h"
+
+#include "dataset.h"
+
+#define REG_I 8
+#define REG_J 2
+//#define BLOCK_I 32
+#define BLOCK_J 16
+#define BLOCK_K 16
+#define LDA 32
+#define NCORES 2
+#define MIN(X,Y) (X < Y ? X : Y)
+
+void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda,  const data_t A[], const data_t B[], data_t C[] )
+{
+   
+   // ***************************** //
+   // **** ADD YOUR CODE HERE ***** //
+   // ***************************** //
+   //
+   // feel free to make a separate function for MI and MSI versions.
+
+  int i, j, k, ri, rj, ii, jj, kk;
+  data_t *Aj, *Cj, *Bi;
+  data_t c[REG_I][REG_J], a[REG_J], b[REG_I];
+  size_t start = coreid * (LDA / NCORES), end = (coreid == NCORES - 1 ? LDA : (coreid + 1) * (LDA / NCORES));
+     
+  /* if (coreid > 0) { */
+  /*   return; */
+  /* } */
+  /* start = 0, end = lda; */
+  if (ncores == NCORES && lda == LDA) {
+    for (jj = start; jj < end; jj += BLOCK_J)
+      for (kk = 0; kk < LDA; kk += BLOCK_K)
+	//for (ii = 0; ii < LDA; ii += BLOCK_I)
+	for (j = jj; j < MIN(end, jj + BLOCK_J); j += REG_J) {
+	  Aj = A + j*LDA;
+	  Cj = C + j*LDA;
+	  for (i = 0; i < LDA; i += REG_I) {
+	    /* Load C in register blocks. */
+	    Bi = B + i;
+	    for (ri = 0; ri < REG_I; ri++) {
+	      for (rj = 0; rj < REG_J; rj++) {
+		c[ri][rj] = Cj[i + ri + ( rj)*LDA];
+	      }
+	    }
+	    
+	    
+	    for (k = kk; k < MIN(LDA, kk + BLOCK_K); k++) {
+	      /* Load a,b in register blocks. */
+	      /*	  for (rj = 0; rj < REG_J; rj++) {
+			  a[rj] = A[(j + rj)*LDA + k];
+			  }*/
+	      /* for (ri = 0; ri < REG_I; ri++) { */
+	      /* 	b[ri] = Bi[k*LDA  + ri]; */
+	      /* } */
+	      /* /\* Compute C in register blocks. *\/ */
+	      /* for (rj = 0; rj < REG_J; rj++) { */
+	      /* 	a[rj] = Aj[( rj)*LDA + k]; */
+	      /* 	for (ri = 0; ri < REG_I; ri++) { */
+	      /* 	  c[ri][rj] += a[rj] * b[ri]; */
+	      /* 	} */
+	      /* } */
+	      a[0] = Aj[k];
+	      a[1] = Aj[k + LDA];
+	      b[0] = Bi[k*LDA];
+	      b[1] = Bi[k*LDA + 1];
+	      b[2] = Bi[k*LDA + 2];
+	      b[3] = Bi[k*LDA + 3];
+	      b[4] = Bi[k*LDA + 4];
+	      b[5] = Bi[k*LDA + 5];
+	      b[6] = Bi[k*LDA + 6];
+	      b[7] = Bi[k*LDA + 7];
+
+	      
+	      c[0][0] += b[0] * a[0];
+	      c[0][1] += b[0] * a[1];
+	      c[1][0] += b[1] * a[0];
+	      c[1][1] += b[1] * a[1];
+	      c[2][0] += b[2] * a[0];
+	      c[2][1] += b[2] * a[1];
+	      c[3][0] += b[3] * a[0];
+	      c[3][1] += b[3] * a[1];
+	      c[4][0] += b[4] * a[0];
+	      c[4][1] += b[4] * a[1];
+	      c[5][0] += b[5] * a[0];
+	      c[5][1] += b[5] * a[1];
+	      c[6][0] += b[6] * a[0];
+	      c[6][1] += b[6] * a[1];
+	      c[7][0] += b[7] * a[0];
+	      c[7][1] += b[7] * a[1];
+	      
+
+	      /* c[0][0] +=  b[0] * a[0];	       */
+	      /* c[1][1] +=  b[1] * a[1];              */
+	      /* c[2][0] +=  b[2] * a[0];	       */
+	      /* c[3][1] +=  b[3] * a[1];	       */
+	      /* c[4][0] +=  b[4] * a[0];	       */
+	      /* c[5][1] +=  b[5] * a[1];	       */
+	      /* c[6][0] +=  b[6] * a[0];	       */
+	      /* c[7][1] +=  b[7] * a[1];	       */
+	      /* c[0][0] +=  b[0] * a[0];	       */
+	      /* c[1][1] +=  b[1] * a[1];	       */
+	      /* c[2][0] +=  b[2] * a[0];	       */
+	      /* c[3][1] +=  b[3] * a[1];	       */
+	      /* c[4][0] +=  b[4] * a[0];	       */
+	      /* c[5][1] +=  b[5] * a[1];	       */
+	      /* c[6][0] +=  b[6] * a[0];	       */
+	      /* c[7][1] +=  b[7] * a[1];	       */
+
+	    }
+      
+	    /* store C in register blocks. */
+	    for (ri = 0; ri < REG_I; ri++) {
+	      for (rj = 0; rj < REG_J; rj++) {
+		Cj[i + ri + (rj)*LDA] = c[ri][rj];
+	      }
+	    }
+	  }
+	  
+	  
+	  
+	  
+	}
+    /* We only care about performance for 32x32 matrices and 2 cores. Otherwise just naive mat_mul */
+  } else {
+    if (coreid > 0)
+      return;
+    
+    for ( i = 0; i < lda; i++ )
+      for ( j = 0; j < lda; j++ )  
+	for ( k = 0; k < lda; k++ ) 
+	  C[i + j*lda] += A[j*lda + k] * B[k*lda + i];
+  }
+}
diff --git a/apps/riscv-tests/mt/bf_matmul.c b/apps/riscv-tests/mt/bf_matmul.c
new file mode 100644
index 0000000..04904b9
--- /dev/null
+++ b/apps/riscv-tests/mt/bf_matmul.c
@@ -0,0 +1,127 @@
+#include "stdlib.h"
+
+#include "util.h"
+
+#include "dataset.h"
+void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda,  const data_t A[], const data_t B[], data_t C[] )
+{
+   
+   // ***************************** //
+   // **** ADD YOUR CODE HERE ***** //
+   // ***************************** //
+   //
+   // feel free to make a separate function for MI and MSI versions.
+   int j, k, i;
+   data_t temp0, temp1, temp2, temp3, temp4, temp5, temp6, temp7;
+   data_t temp8, temp9, temp10, temp11, temp12, temp13, temp14, temp15;
+   if(coreid == 0)   {
+      for(j = 0; j < 32; j++) {
+         temp0  = 0; //C[j*lda];
+         temp1  = 0; //C[1  + j*lda];
+         temp2  = 0; //C[2  + j*lda];
+         temp3  = 0; //C[3  + j*lda];
+         temp4  = 0; //C[4  + j*lda];
+         temp5  = 0; //C[5  + j*lda];
+         temp6  = 0; //C[6  + j*lda];
+         temp7  = 0; //C[7  + j*lda];
+         temp8  = 0; //C[8  + j*lda];
+         temp9  = 0; //C[9  + j*lda];
+         temp10 = 0; //C[10 + j*lda];
+         temp11 = 0; //C[11 + j*lda];
+         temp12 = 0; //C[12 + j*lda];
+         temp13 = 0; //C[13 + j*lda];
+         temp14 = 0; //C[14 + j*lda];
+         temp15 = 0; //C[15 + j*lda];
+         for(k = 0; k < 32; k++) {
+            temp0  += A[j*lda + k] * B[k*lda];
+            temp1  += A[j*lda + k] * B[1+k*lda];
+            temp2  += A[j*lda + k] * B[2+k*lda];
+            temp3  += A[j*lda + k] * B[3+k*lda];
+            temp4  += A[j*lda + k] * B[4+k*lda];
+            temp5  += A[j*lda + k] * B[5+k*lda];
+            temp6  += A[j*lda + k] * B[6+k*lda];
+            temp7  += A[j*lda + k] * B[7+k*lda];
+            temp8  += A[j*lda + k] * B[8+k*lda];
+            temp9  += A[j*lda + k] * B[9+k*lda];
+            temp10 += A[j*lda + k] * B[10+k*lda];
+            temp11 += A[j*lda + k] * B[11+k*lda];
+            temp12 += A[j*lda + k] * B[12+k*lda];
+            temp13 += A[j*lda + k] * B[13+k*lda];
+            temp14 += A[j*lda + k] * B[14+k*lda];
+            temp15 += A[j*lda + k] * B[15+k*lda];
+         }
+         C[j*lda] = temp0;
+         C[1  + j*lda] = temp1;
+         C[2  + j*lda] = temp2;
+         C[3  + j*lda] = temp3;
+         C[4  + j*lda] = temp4;
+         C[5  + j*lda] = temp5;
+         C[6  + j*lda] = temp6;
+         C[7  + j*lda] = temp7;
+         C[8  + j*lda] = temp8;
+         C[9  + j*lda] = temp9;
+         C[10 + j*lda] = temp10;
+         C[11 + j*lda] = temp11;
+         C[12 + j*lda] = temp12;
+         C[13 + j*lda] = temp13;
+         C[14 + j*lda] = temp14;
+         C[15 + j*lda] = temp15;
+      }
+   }
+
+   if(coreid == 1 || ncores == 1)  {
+      for(j = 0; j < 32; j++) {
+         temp0  = 0; //C[16+j*lda];
+         temp1  = 0; //C[17+j*lda];
+         temp2  = 0; //C[18+j*lda];
+         temp3  = 0; //C[19+j*lda];
+         temp4  = 0; //C[20+j*lda];
+         temp5  = 0; //C[21+j*lda];
+         temp6  = 0; //C[22+j*lda];
+         temp7  = 0; //C[23+j*lda];
+         temp8  = 0; //C[24+j*lda];
+         temp9  = 0; //C[25+j*lda];
+         temp10 = 0; //C[26+j*lda];
+         temp11 = 0; //C[27+j*lda];
+         temp12 = 0; //C[28+j*lda];
+         temp13 = 0; //C[29+j*lda];
+         temp14 = 0; //C[30+j*lda];
+         temp15 = 0; //C[31+j*lda];
+         for(k = 0; k < 32; k++) {
+            temp0  += A[j*lda + k] * B[16+k*lda];
+            temp1  += A[j*lda + k] * B[17+k*lda];
+            temp2  += A[j*lda + k] * B[18+k*lda];
+            temp3  += A[j*lda + k] * B[19+k*lda];
+            temp4  += A[j*lda + k] * B[20+k*lda];
+            temp5  += A[j*lda + k] * B[21+k*lda];
+            temp6  += A[j*lda + k] * B[22+k*lda];
+            temp7  += A[j*lda + k] * B[23+k*lda];
+            temp8  += A[j*lda + k] * B[24+k*lda];
+            temp9  += A[j*lda + k] * B[25+k*lda];
+            temp10 += A[j*lda + k] * B[26+k*lda];
+            temp11 += A[j*lda + k] * B[27+k*lda];
+            temp12 += A[j*lda + k] * B[28+k*lda];
+            temp13 += A[j*lda + k] * B[29+k*lda];
+            temp14 += A[j*lda + k] * B[30+k*lda];
+            temp15 += A[j*lda + k] * B[31+k*lda];
+         }
+         C[16 + j*lda] = temp0;
+         C[17 + j*lda] = temp1;
+         C[18 + j*lda] = temp2;
+         C[19 + j*lda] = temp3;
+         C[20 + j*lda] = temp4;
+         C[21 + j*lda] = temp5;
+         C[22 + j*lda] = temp6;
+         C[23 + j*lda] = temp7;
+         C[24 + j*lda] = temp8;
+         C[25 + j*lda] = temp9;
+         C[26 + j*lda] = temp10;
+         C[27 + j*lda] = temp11;
+         C[28 + j*lda] = temp12;
+         C[29 + j*lda] = temp13;
+         C[30 + j*lda] = temp14;
+         C[31 + j*lda] = temp15;
+      }
+   }
+ 
+}
diff --git a/apps/riscv-tests/mt/bh_matmul.c b/apps/riscv-tests/mt/bh_matmul.c
new file mode 100644
index 0000000..c8d6f2b
--- /dev/null
+++ b/apps/riscv-tests/mt/bh_matmul.c
@@ -0,0 +1,97 @@
+#include "stdlib.h"
+
+#include "util.h"
+
+#include "dataset.h"
+void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda,  const data_t A[], const data_t B[], data_t C[] )
+{
+   
+   // ***************************** //
+   // **** ADD YOUR CODE HERE ***** //
+   // ***************************** //
+   //
+   // feel free to make a separate function for MI and MSI versions.
+   if(coreid > 1) return; 
+
+    int m, i, j, k, iB0, iB1;
+    data_t tempC0, tempC1, tempC2, tempC3, tempC4, tempC5, tempC6, tempC7;
+    data_t tempA0, tempA1;
+  
+    if (coreid == 0){
+        for (m = 0; m < 2; m++){
+            for (j = 0; j < lda/2; j++){
+                for (i = 0; i < lda; i+=8){
+                    tempC0 = C[i + j*lda];
+                    tempC1 = C[i + j*lda+1];
+                    tempC2 = C[i + j*lda+2];
+                    tempC3 = C[i + j*lda+3];
+                    tempC4 = C[i + j*lda+4];
+                    tempC5 = C[i + j*lda+5];
+                    tempC6 = C[i + j*lda+6];
+                    tempC7 = C[i + j*lda+7];
+                    iB0 = m*lda*lda/2+i;
+                    iB1 = iB0+lda;
+                    for (k = m*lda/2; k < (m+1)*lda/2; k+=2){
+                        tempA0 = A[j*lda+k];
+                        tempA1 = A[j*lda+k+1];
+                        tempC0 += tempA0*B[iB0]+tempA1*B[iB1];
+                        tempC1 += tempA0*B[iB0+1]+tempA1*B[iB1+1];
+                        tempC2 += tempA0*B[iB0+2]+tempA1*B[iB1+2];
+                        tempC3 += tempA0*B[iB0+3]+tempA1*B[iB1+3];
+                        tempC4 += tempA0*B[iB0+4]+tempA1*B[iB1+4];
+                        tempC5 += tempA0*B[iB0+5]+tempA1*B[iB1+5];
+                        tempC6 += tempA0*B[iB0+6]+tempA1*B[iB1+6];
+                        tempC7 += tempA0*B[iB0+7]+tempA1*B[iB1+7];
+                        iB0 += 2*lda;
+                        iB1 += 2*lda;
+                        
+                    }
+                    C[i + j*lda] = tempC0;
+                    C[i + j*lda + 1] = tempC1;
+                    C[i + j*lda + 2] = tempC2;
+                    C[i + j*lda + 3] = tempC3;
+                    C[i + j*lda + 4] = tempC4;
+                    C[i + j*lda + 5] = tempC5;
+                    C[i + j*lda + 6] = tempC6;
+                    C[i + j*lda + 7] = tempC7;
+                }
+            }
+        }
+    } 
+    if(coreid == 1 || ncores == 1) {
+        for (m = 2; m > 0; m--){
+            for (j = lda-1; j >= lda/2; j--){
+                for (i = lda-1; i >= 0; i-=8){
+                    tempC0 = C[i + j*lda];
+                    tempC1 = C[i + j*lda - 1];
+                    tempC2 = C[i + j*lda - 2];
+                    tempC3 = C[i + j*lda - 3];
+                    tempC4 = C[i + j*lda - 4];
+                    tempC5 = C[i + j*lda - 5];
+                    tempC6 = C[i + j*lda - 6];
+                    tempC7 = C[i + j*lda - 7];
+                    for (k = m*lda/2-1; k >= (m-1)*lda/2; k-=2){
+                        tempA0 = A[j*lda+k];
+                        tempA1 = A[j*lda+k-1];
+                        tempC0 += tempA0*B[k*lda+i]+tempA1*B[(k-1)*lda+i];
+                        tempC1 += tempA0*B[k*lda+i-1]+tempA1*B[(k-1)*lda+i-1];
+                        tempC2 += tempA0*B[k*lda+i-2]+tempA1*B[(k-1)*lda+i-2];
+                        tempC3 += tempA0*B[k*lda+i-3]+tempA1*B[(k-1)*lda+i-3];
+                        tempC4 += tempA0*B[k*lda+i-4]+tempA1*B[(k-1)*lda+i-4];
+                        tempC5 += tempA0*B[k*lda+i-5]+tempA1*B[(k-1)*lda+i-5];
+                        tempC6 += tempA0*B[k*lda+i-6]+tempA1*B[(k-1)*lda+i-6];
+                        tempC7 += tempA0*B[k*lda+i-7]+tempA1*B[(k-1)*lda+i-7];
+                    }
+                    C[i + j*lda] = tempC0;
+                    C[i + j*lda - 1] = tempC1;
+                    C[i + j*lda - 2] = tempC2;
+                    C[i + j*lda - 3] = tempC3;
+                    C[i + j*lda - 4] = tempC4;
+                    C[i + j*lda - 5] = tempC5;
+                    C[i + j*lda - 6] = tempC6;
+                    C[i + j*lda - 7] = tempC7;
+                }
+            }
+        }
+    }
+}
diff --git a/apps/riscv-tests/mt/bj_matmul.c b/apps/riscv-tests/mt/bj_matmul.c
new file mode 100644
index 0000000..df1f880
--- /dev/null
+++ b/apps/riscv-tests/mt/bj_matmul.c
@@ -0,0 +1,97 @@
+#include "stdlib.h"
+
+#include "util.h"
+
+#include "dataset.h"
+void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda,  const data_t A[], const data_t B[], data_t C[] )
+{
+    
+    // ***************************** //
+    // **** ADD YOUR CODE HERE ***** //
+    // ***************************** //
+    //
+    // feel free to make a separate function for MI and MSI versions.
+    
+    int m, i, j, k, iB0, iB1;
+    data_t tempC0, tempC1, tempC2, tempC3, tempC4, tempC5, tempC6, tempC7;
+    data_t tempA0, tempA1;
+    
+   if(coreid > 1) return; 
+    if (coreid == 0){
+        for (m = 0; m < 2; m++){
+            for (j = 0; j < lda/2; j++){
+                for (i = 0; i < lda; i+=8){
+                    tempC0 = C[i + j*lda];
+                    tempC1 = C[i + j*lda+1];
+                    tempC2 = C[i + j*lda+2];
+                    tempC3 = C[i + j*lda+3];
+                    tempC4 = C[i + j*lda+4];
+                    tempC5 = C[i + j*lda+5];
+                    tempC6 = C[i + j*lda+6];
+                    tempC7 = C[i + j*lda+7];
+                    iB0 = m*lda*lda/2+i;
+                    iB1 = iB0+lda;
+                    for (k = m*lda/2; k < (m+1)*lda/2; k+=2){
+                        tempA0 = A[j*lda+k];
+                        tempA1 = A[j*lda+k+1];
+                        tempC0 += tempA0*B[iB0]+tempA1*B[iB1];
+                        tempC1 += tempA0*B[iB0+1]+tempA1*B[iB1+1];
+                        tempC2 += tempA0*B[iB0+2]+tempA1*B[iB1+2];
+                        tempC3 += tempA0*B[iB0+3]+tempA1*B[iB1+3];
+                        tempC4 += tempA0*B[iB0+4]+tempA1*B[iB1+4];
+                        tempC5 += tempA0*B[iB0+5]+tempA1*B[iB1+5];
+                        tempC6 += tempA0*B[iB0+6]+tempA1*B[iB1+6];
+                        tempC7 += tempA0*B[iB0+7]+tempA1*B[iB1+7];
+                        iB0 += 2*lda;
+                        iB1 += 2*lda;
+                        
+                    }
+                    C[i + j*lda] = tempC0;
+                    C[i + j*lda + 1] = tempC1;
+                    C[i + j*lda + 2] = tempC2;
+                    C[i + j*lda + 3] = tempC3;
+                    C[i + j*lda + 4] = tempC4;
+                    C[i + j*lda + 5] = tempC5;
+                    C[i + j*lda + 6] = tempC6;
+                    C[i + j*lda + 7] = tempC7;
+                }
+            }
+        }
+    }
+    if(coreid == 1  || ncores == 1) {
+        for (m = 2; m > 0; m--){
+            for (j = lda-1; j >= lda/2; j--){
+                for (i = lda-1; i >= 0; i-=8){
+                    tempC0 = C[i + j*lda];
+                    tempC1 = C[i + j*lda - 1];
+                    tempC2 = C[i + j*lda - 2];
+                    tempC3 = C[i + j*lda - 3];
+                    tempC4 = C[i + j*lda - 4];
+                    tempC5 = C[i + j*lda - 5];
+                    tempC6 = C[i + j*lda - 6];
+                    tempC7 = C[i + j*lda - 7];
+                    for (k = m*lda/2-1; k >= (m-1)*lda/2; k-=2){
+                        tempA0 = A[j*lda+k];
+                        tempA1 = A[j*lda+k-1];
+                        tempC0 += tempA0*B[k*lda+i]+tempA1*B[(k-1)*lda+i];
+                        tempC1 += tempA0*B[k*lda+i-1]+tempA1*B[(k-1)*lda+i-1];
+                        tempC2 += tempA0*B[k*lda+i-2]+tempA1*B[(k-1)*lda+i-2];
+                        tempC3 += tempA0*B[k*lda+i-3]+tempA1*B[(k-1)*lda+i-3];
+                        tempC4 += tempA0*B[k*lda+i-4]+tempA1*B[(k-1)*lda+i-4];
+                        tempC5 += tempA0*B[k*lda+i-5]+tempA1*B[(k-1)*lda+i-5];
+                        tempC6 += tempA0*B[k*lda+i-6]+tempA1*B[(k-1)*lda+i-6];
+                        tempC7 += tempA0*B[k*lda+i-7]+tempA1*B[(k-1)*lda+i-7];
+                    }
+                    C[i + j*lda] = tempC0;
+                    C[i + j*lda - 1] = tempC1;
+                    C[i + j*lda - 2] = tempC2;
+                    C[i + j*lda - 3] = tempC3;
+                    C[i + j*lda - 4] = tempC4;
+                    C[i + j*lda - 5] = tempC5;
+                    C[i + j*lda - 6] = tempC6;
+                    C[i + j*lda - 7] = tempC7;
+                }
+            }
+        }
+    }
+}
diff --git a/apps/riscv-tests/mt/bk_matmul.c b/apps/riscv-tests/mt/bk_matmul.c
new file mode 100644
index 0000000..dae49fc
--- /dev/null
+++ b/apps/riscv-tests/mt/bk_matmul.c
@@ -0,0 +1,92 @@
+#include "stdlib.h"
+
+#include "util.h"
+
+#include "dataset.h"
+void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda,  const data_t A[], const data_t B[], data_t C[] )
+{
+   int i, j, k, ii, jj, kk; 
+   if(coreid > 1) return; 
+  if (coreid == 0) { 
+// for ( ii = 0; ii < 32; ii+=IC )
+         for ( kk = 0; kk < 32; kk+=16 ) 
+   for ( j = 0; j < 16; j++ )  
+// for ( j = 0; j < 16; j++ )  
+   {
+      for ( i =  0; i < 32; i+=8 )
+//    for ( i = ii; i < ii + IC && i < 32; i+=8 )
+      {
+         data_t temp0 = C[i+j*32];
+         data_t temp1 = C[i+j*32+1];
+         data_t temp2 = C[i+j*32+2];
+         data_t temp3 = C[i+j*32+3];
+         data_t temp4 = C[i+j*32+4];
+         data_t temp5 = C[i+j*32+5];
+         data_t temp6 = C[i+j*32+6];
+         data_t temp7 = C[i+j*32+7];
+         for ( k = kk; k < kk+16 && k < 32; k++ ) 
+//       for ( k = 0; k < 32; k++ ) 
+         {
+            data_t tempA = A[j*32+k];
+            temp0 += tempA * B[k*32 + i];
+            temp1 += tempA * B[k*32 + i+1];
+            temp2 += tempA * B[k*32 + i+2];
+            temp3 += tempA * B[k*32 + i+3];
+            temp4 += tempA * B[k*32 + i+4];
+            temp5 += tempA * B[k*32 + i+5];
+            temp6 += tempA * B[k*32 + i+6];
+            temp7 += tempA * B[k*32 + i+7];
+         }
+         C[i+j*32] = temp0;
+         C[i+j*32+1] = temp1;
+         C[i+j*32+2] = temp2;
+         C[i+j*32+3] = temp3;
+         C[i+j*32+4] = temp4;
+         C[i+j*32+5] = temp5;
+         C[i+j*32+6] = temp6;
+         C[i+j*32+7] = temp7;
+      }
+   } 
+  } 
+  if(coreid == 1 || ncores == 1) {
+// for ( ii = 0; ii < 32; ii+=IC )
+         for ( kk = 0; kk < 32; kk+=16 ) 
+   for ( j = 16; j < 32; j++ )  
+// for ( j = 16; j < 32; j++ )  
+   {
+      for ( i =   0; i < 32; i+=8 )
+//    for ( i = ii; i < ii + IC && i < 32; i+=8 )
+      {
+         data_t temp0 = C[i+j*32];
+         data_t temp1 = C[i+j*32+1];
+         data_t temp2 = C[i+j*32+2];
+         data_t temp3 = C[i+j*32+3];
+         data_t temp4 = C[i+j*32+4];
+         data_t temp5 = C[i+j*32+5];
+         data_t temp6 = C[i+j*32+6];
+         data_t temp7 = C[i+j*32+7];
+         for ( k = kk; k < kk+16 && k < 32; k++ ) 
+         {
+            data_t tempA = A[j*32+k];
+            temp0 += tempA * B[k*32 + i];
+            temp1 += tempA * B[k*32 + i+1];
+            temp2 += tempA * B[k*32 + i+2];
+            temp3 += tempA * B[k*32 + i+3];
+            temp4 += tempA * B[k*32 + i+4];
+            temp5 += tempA * B[k*32 + i+5];
+            temp6 += tempA * B[k*32 + i+6];
+            temp7 += tempA * B[k*32 + i+7];
+         }
+         C[i+j*32] = temp0;
+         C[i+j*32+1] = temp1;
+         C[i+j*32+2] = temp2;
+         C[i+j*32+3] = temp3;
+         C[i+j*32+4] = temp4;
+         C[i+j*32+5] = temp5;
+         C[i+j*32+6] = temp6;
+         C[i+j*32+7] = temp7;
+      }
+
+   }
+  } 
+}
diff --git a/apps/riscv-tests/mt/bm_matmul.c b/apps/riscv-tests/mt/bm_matmul.c
new file mode 100644
index 0000000..ae225d4
--- /dev/null
+++ b/apps/riscv-tests/mt/bm_matmul.c
@@ -0,0 +1,205 @@
+#include "stdlib.h"
+
+#include "util.h"
+
+#include "dataset.h"
+void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda,  const data_t A[], const data_t B[], data_t C[] )
+{
+   
+   // ***************************** //
+   // **** ADD YOUR CODE HERE ***** //
+   // ***************************** //
+   //
+   // feel free to make a separate function for MI and MSI versions.
+    int i, j, k;
+    int space=lda/ncores;
+    int max= space*coreid+space;
+	data_t temp=0;
+
+	data_t temp1=0;
+	data_t temp2=0;
+	data_t temp3=0;
+	data_t temp4=0;
+	
+	data_t temp_1=0;
+
+	data_t temp1_1=0;
+	data_t temp2_1=0;
+	data_t temp3_1=0;
+	data_t temp4_1=0;
+	
+	data_t temp_2=0;
+
+	data_t temp1_2=0;
+	data_t temp2_2=0;
+	data_t temp3_2=0;
+	data_t temp4_2=0;
+	
+	data_t temp_3=0;
+
+	data_t temp1_3=0;
+	data_t temp2_3=0;
+	data_t temp3_3=0;
+	data_t temp4_3=0;
+
+	if (coreid!=ncores-1){
+	//main loop
+		for (i=space*coreid;i<max/4*4;i+=4)
+		{
+			for(j=0;j<lda;j+=4)
+			{
+				temp1=C[j+i*lda];
+				temp2=C[j+1+i*lda];
+				temp3=C[j+2+i*lda];
+				temp4=C[j+3+i*lda];
+		
+				temp1_1=C[j+(i+1)*lda];
+				temp2_1=C[j+1+(i+1)*lda];
+				temp3_1=C[j+2+(i+1)*lda];
+				temp4_1=C[j+3+(i+1)*lda];
+				
+				temp1_2=C[j+(i+2)*lda];
+				temp2_2=C[j+1+(i+2)*lda];
+				temp3_2=C[j+2+(i+2)*lda];
+				temp4_2=C[j+3+(i+2)*lda];
+				
+				temp1_3=C[j+(i+3)*lda];
+				temp2_3=C[j+1+(i+3)*lda];
+				temp3_3=C[j+2+(i+3)*lda];
+				temp4_3=C[j+3+(i+3)*lda];
+				for (k=0;k<lda;k++)
+				{
+					temp=A[k+i*lda];
+					temp1+=temp*B[j+k*lda];
+					temp2+=temp*B[j+1+k*lda];
+					temp3+=temp*B[j+2+k*lda];
+					temp4+=temp*B[j+3+k*lda];
+					
+					temp_1=A[k+(i+1)*lda];
+					temp1_1+=temp_1*B[j+k*lda];
+					temp2_1+=temp_1*B[j+1+k*lda];
+					temp3_1+=temp_1*B[j+2+k*lda];
+					temp4_1+=temp_1*B[j+3+k*lda];
+					
+					temp_2=A[k+(i+2)*lda];
+					temp1_2+=temp_2*B[j+k*lda];
+					temp2_2+=temp_2*B[j+1+k*lda];
+					temp3_2+=temp_2*B[j+2+k*lda];
+					temp4_2+=temp_2*B[j+3+k*lda];
+					
+					temp_3=A[k+(i+3)*lda];
+					temp1_3+=temp_3*B[j+k*lda];
+					temp2_3+=temp_3*B[j+1+k*lda];
+					temp3_3+=temp_3*B[j+2+k*lda];
+					temp4_3+=temp_3*B[j+3+k*lda];
+
+				}
+				C[j+i*lda]=temp1;
+				C[j+1+i*lda]=temp2;
+				C[j+2+i*lda]=temp3;
+				C[j+3+i*lda]=temp4;
+				
+				C[j+(i+1)*lda]=temp1_1;
+				C[j+1+(i+1)*lda]=temp2_1;
+				C[j+2+(i+1)*lda]=temp3_1;
+				C[j+3+(i+1)*lda]=temp4_1;
+				
+				C[j+(i+2)*lda]=temp1_2;
+				C[j+1+(i+2)*lda]=temp2_2;
+				C[j+2+(i+2)*lda]=temp3_2;
+				C[j+3+(i+2)*lda]=temp4_2;
+				
+				C[j+(i+3)*lda]=temp1_3;
+				C[j+1+(i+3)*lda]=temp2_3;
+				C[j+2+(i+3)*lda]=temp3_3;
+				C[j+3+(i+3)*lda]=temp4_3;
+
+			}
+			
+		}
+		
+	
+		
+	}
+	
+	//second core
+	else{
+		for (i=space*coreid;i<lda/4*4;i+=4)
+		{
+			for(j=0;j<lda;j+=4)
+			{
+				temp1=C[j+i*lda];
+				temp2=C[j+1+i*lda];
+				temp3=C[j+2+i*lda];
+				temp4=C[j+3+i*lda];
+		
+				temp1_1=C[j+(i+1)*lda];
+				temp2_1=C[j+1+(i+1)*lda];
+				temp3_1=C[j+2+(i+1)*lda];
+				temp4_1=C[j+3+(i+1)*lda];
+				
+				temp1_2=C[j+(i+2)*lda];
+				temp2_2=C[j+1+(i+2)*lda];
+				temp3_2=C[j+2+(i+2)*lda];
+				temp4_2=C[j+3+(i+2)*lda];
+				
+				temp1_3=C[j+(i+3)*lda];
+				temp2_3=C[j+1+(i+3)*lda];
+				temp3_3=C[j+2+(i+3)*lda];
+				temp4_3=C[j+3+(i+3)*lda];
+				for (k=0;k<lda;k++)
+				{
+					temp=A[k+i*lda];
+					temp1+=temp*B[j+k*lda];
+					temp2+=temp*B[j+1+k*lda];
+					temp3+=temp*B[j+2+k*lda];
+					temp4+=temp*B[j+3+k*lda];
+					
+					temp_1=A[k+(i+1)*lda];
+					temp1_1+=temp_1*B[j+k*lda];
+					temp2_1+=temp_1*B[j+1+k*lda];
+					temp3_1+=temp_1*B[j+2+k*lda];
+					temp4_1+=temp_1*B[j+3+k*lda];
+					
+					temp_2=A[k+(i+2)*lda];
+					temp1_2+=temp_2*B[j+k*lda];
+					temp2_2+=temp_2*B[j+1+k*lda];
+					temp3_2+=temp_2*B[j+2+k*lda];
+					temp4_2+=temp_2*B[j+3+k*lda];
+					
+					temp_3=A[k+(i+3)*lda];
+					temp1_3+=temp_3*B[j+k*lda];
+					temp2_3+=temp_3*B[j+1+k*lda];
+					temp3_3+=temp_3*B[j+2+k*lda];
+					temp4_3+=temp_3*B[j+3+k*lda];
+
+				}
+				C[j+i*lda]=temp1;
+				C[j+1+i*lda]=temp2;
+				C[j+2+i*lda]=temp3;
+				C[j+3+i*lda]=temp4;
+				
+				C[j+(i+1)*lda]=temp1_1;
+				C[j+1+(i+1)*lda]=temp2_1;
+				C[j+2+(i+1)*lda]=temp3_1;
+				C[j+3+(i+1)*lda]=temp4_1;
+				
+				C[j+(i+2)*lda]=temp1_2;
+				C[j+1+(i+2)*lda]=temp2_2;
+				C[j+2+(i+2)*lda]=temp3_2;
+				C[j+3+(i+2)*lda]=temp4_2;
+				
+				C[j+(i+3)*lda]=temp1_3;
+				C[j+1+(i+3)*lda]=temp2_3;
+				C[j+2+(i+3)*lda]=temp3_3;
+				C[j+3+(i+3)*lda]=temp4_3;
+
+			}
+			
+		}
+		
+	
+	}
+	
+ 
+}
diff --git a/apps/riscv-tests/mt/bo_matmul.c b/apps/riscv-tests/mt/bo_matmul.c
new file mode 100644
index 0000000..2fb24ab
--- /dev/null
+++ b/apps/riscv-tests/mt/bo_matmul.c
@@ -0,0 +1,98 @@
+#include "stdlib.h"
+
+#include "util.h"
+
+#include "dataset.h"
+void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda,  const data_t A[], const data_t B[], data_t C[] )
+{
+    int i, j, k;
+    data_t B_trans[32*32];
+    data_t acc_temp0, acc_temp1;
+    data_t *A_j, *B_i;
+    data_t *A_j_k, *B_i_k;
+    int z;
+
+    //for (i = 0; i < 32; i++) {
+    //    for (j = 0; j < 32; j++) {
+    //        B_trans[i*lda+j] = B[i+j*lda];
+    //    }
+    //}
+
+    if (coreid == 0) {
+        for (i = 0; i < 32; i++) {
+            B_i = B_trans+i*32;
+            for (z = 0; z < 32; z++) {
+                *(B_i+z) = B[i+z*32];
+            }
+            for (j = 0; j < 16; j+=2) {
+                A_j = A+j*lda;
+                acc_temp0 = 0;
+                for (k = 0; k < 32; k+=8) {
+                    A_j_k = A_j+k;
+                    B_i_k = B_i+k;
+                    acc_temp0 += *(A_j_k)     * *(B_i_k);
+                    acc_temp0 += *(A_j_k + 1) * *(B_i_k + 1);
+                    acc_temp0 += *(A_j_k + 2) * *(B_i_k + 2);
+                    acc_temp0 += *(A_j_k + 3) * *(B_i_k + 3);
+                    acc_temp0 += *(A_j_k + 4) * *(B_i_k + 4);
+                    acc_temp0 += *(A_j_k + 5) * *(B_i_k + 5);
+                    acc_temp0 += *(A_j_k + 6) * *(B_i_k + 6);
+                    acc_temp0 += *(A_j_k + 7) * *(B_i_k + 7);
+                }
+                A_j += 32;
+
+                acc_temp1 = 0;
+                for (k = 0; k < 32; k+=8) {
+                    acc_temp1 += *(A_j+k) * *(B_i+k);
+                    acc_temp1 += *(A_j+k + 1) * *(B_i+k + 1);
+                    acc_temp1 += *(A_j+k + 2) * *(B_i+k + 2);
+                    acc_temp1 += *(A_j+k + 3) * *(B_i+k + 3);
+                    acc_temp1 += *(A_j+k + 4) * *(B_i+k + 4);
+                    acc_temp1 += *(A_j+k + 5) * *(B_i+k + 5);
+                    acc_temp1 += *(A_j+k + 6) * *(B_i+k + 6);
+                    acc_temp1 += *(A_j+k + 7) * *(B_i+k + 7);
+                }
+
+                C[i + j*lda] = acc_temp0;
+                C[i + (j+1)*lda] = acc_temp1;
+            }
+        }
+    }
+    if (coreid == 1 || ncores == 1) {
+        for (i = 0; i < 32; i++) {
+            B_i = B_trans+i*32;
+            for (z = 0; z < 32; z++) {
+                *(B_i+z) = B[i+z*32];
+            }
+            for (j = 16; j < 32; j+=2) {
+                A_j = A+j*lda;
+                acc_temp0 = 0;
+                for (k = 0; k < 32; k+=8) {
+                    acc_temp0 += *(A_j+k) * *(B_i+k);
+                    acc_temp0 += *(A_j+k + 1) * *(B_i+k + 1);
+                    acc_temp0 += *(A_j+k + 2) * *(B_i+k + 2);
+                    acc_temp0 += *(A_j+k + 3) * *(B_i+k + 3);
+                    acc_temp0 += *(A_j+k + 4) * *(B_i+k + 4);
+                    acc_temp0 += *(A_j+k + 5) * *(B_i+k + 5);
+                    acc_temp0 += *(A_j+k + 6) * *(B_i+k + 6);
+                    acc_temp0 += *(A_j+k + 7) * *(B_i+k + 7);
+                }
+                A_j += 32;
+
+                acc_temp1 = 0;
+                for (k = 0; k < 32; k+=8) {
+                    acc_temp1 += *(A_j+k) * *(B_i+k);
+                    acc_temp1 += *(A_j+k + 1) * *(B_i+k + 1);
+                    acc_temp1 += *(A_j+k + 2) * *(B_i+k + 2);
+                    acc_temp1 += *(A_j+k + 3) * *(B_i+k + 3);
+                    acc_temp1 += *(A_j+k + 4) * *(B_i+k + 4);
+                    acc_temp1 += *(A_j+k + 5) * *(B_i+k + 5);
+                    acc_temp1 += *(A_j+k + 6) * *(B_i+k + 6);
+                    acc_temp1 += *(A_j+k + 7) * *(B_i+k + 7);
+                }
+                C[i + j*lda] = acc_temp0;
+                C[i + (j+1)*lda] = acc_temp1;
+            }
+        }
+    }
+}
diff --git a/apps/riscv-tests/mt/br_matmul.c b/apps/riscv-tests/mt/br_matmul.c
new file mode 100644
index 0000000..13263e4
--- /dev/null
+++ b/apps/riscv-tests/mt/br_matmul.c
@@ -0,0 +1,128 @@
+#include "stdlib.h"
+
+#include "util.h"
+
+#include "dataset.h"
+void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda,  const data_t A[], const data_t B[], data_t C[] )
+{
+   
+  // ***************************** //
+  // **** ADD YOUR CODE HERE ***** //
+  // ***************************** //
+  //
+  // feel free to make a separate function for MI and MSI versions.
+  int j2, i2, k2, j, i, k; 
+  int tmpC00, tmpC01, tmpC02, tmpC03, tmpC04, tmpC05, tmpC06, tmpC07;
+  int tmpC10, tmpC11, tmpC12, tmpC13, tmpC14, tmpC15, tmpC16, tmpC17;
+  int jBLOCK = 32;
+  int iBLOCK = 16;
+  int kBLOCK = 32;
+  static __thread int tB[4096]; //__thread
+  int startInd = coreid*(lda/ncores);
+  int endInd = (coreid+1)*(lda/ncores);
+
+  //tranpose B (block?)
+  for (i = 0; i < lda; i += 2) {
+    for (j = startInd; j < endInd; j += 2) {
+      tB[j*lda + i] = B[i*lda + j];
+      tB[(j + 1)*lda + i] = B[i*lda + j + 1];
+      tB[j*lda + i + 1] = B[(i + 1)*lda + j];
+      tB[(j + 1)*lda + i + 1] = B[(i + 1)*lda + j + 1];
+    }
+    barrier(ncores);
+  }
+
+  // compute C[j*n + i] += A[j*n + k] + Btranspose[i*n + k]
+  for ( j2 = 0; j2 < lda; j2 += jBLOCK )
+    for ( i2 = startInd; i2 < endInd; i2 += iBLOCK )
+      for ( j = j2; j < j2 + jBLOCK; j += 2 ) 
+	for ( k2 = 0; k2 < lda; k2 += kBLOCK )
+	  for ( i = i2; i < i2 + iBLOCK; i += 4) {
+	    tmpC00 = C[j*lda + i + 0]; tmpC10 = C[(j + 1)*lda + i + 0];
+	    tmpC01 = C[j*lda + i + 1]; tmpC11 = C[(j + 1)*lda + i + 1];
+	    tmpC02 = C[j*lda + i + 2]; tmpC12 = C[(j + 1)*lda + i + 2];
+	    tmpC03 = C[j*lda + i + 3]; tmpC13 = C[(j + 1)*lda + i + 3];
+	    //tmpC04 = C[j*lda + i + 4]; tmpC14 = C[(j + 1)*lda + i + 4];
+	    //tmpC05 = C[j*lda + i + 5]; tmpC15 = C[(j + 1)*lda + i + 5];
+	    //tmpC06 = C[j*lda + i + 6]; tmpC16 = C[(j + 1)*lda + i + 6];
+	    //tmpC07 = C[j*lda + i + 7]; tmpC17 = C[(j + 1)*lda + i + 7];
+	    for ( k = k2; k < k2 + kBLOCK; k += 4) {
+	      tmpC00 += A[j*lda + k] * tB[(i + 0)*lda + k]; 
+	      tmpC01 += A[j*lda + k] * tB[(i + 1)*lda + k]; 
+	      tmpC02 += A[j*lda + k] * tB[(i + 2)*lda + k]; 
+	      tmpC03 += A[j*lda + k] * tB[(i + 3)*lda + k]; 
+	      //tmpC04 += A[j*lda + k] * tB[(i + 4)*lda + k]; 
+	      //tmpC05 += A[j*lda + k] * tB[(i + 5)*lda + k]; 
+	      //tmpC06 += A[j*lda + k] * tB[(i + 6)*lda + k]; 
+	      //tmpC07 += A[j*lda + k] * tB[(i + 7)*lda + k]; 
+	      tmpC10 += A[(j + 1)*lda + k] * tB[(i + 0)*lda + k]; 
+	      tmpC11 += A[(j + 1)*lda + k] * tB[(i + 1)*lda + k]; 
+	      tmpC12 += A[(j + 1)*lda + k] * tB[(i + 2)*lda + k]; 
+	      tmpC13 += A[(j + 1)*lda + k] * tB[(i + 3)*lda + k]; 
+	      //tmpC14 += A[(j + 1)*lda + k] * tB[(i + 4)*lda + k]; 
+	      //tmpC15 += A[(j + 1)*lda + k] * tB[(i + 5)*lda + k]; 
+	      //tmpC16 += A[(j + 1)*lda + k] * tB[(i + 6)*lda + k]; 
+	      //tmpC17 += A[(j + 1)*lda + k] * tB[(i + 7)*lda + k]; 
+
+	      tmpC00 += A[j*lda + k + 1] * tB[(i + 0)*lda + k + 1];
+	      tmpC01 += A[j*lda + k + 1] * tB[(i + 1)*lda + k + 1];
+	      tmpC02 += A[j*lda + k + 1] * tB[(i + 2)*lda + k + 1];
+	      tmpC03 += A[j*lda + k + 1] * tB[(i + 3)*lda + k + 1];
+	      //tmpC04 += A[j*lda + k + 1] * tB[(i + 4)*lda + k + 1];
+	      //tmpC05 += A[j*lda + k + 1] * tB[(i + 5)*lda + k + 1];
+	      //tmpC06 += A[j*lda + k + 1] * tB[(i + 6)*lda + k + 1];
+	      //tmpC07 += A[j*lda + k + 1] * tB[(i + 7)*lda + k + 1];
+	      tmpC10 += A[(j + 1)*lda + k + 1] * tB[(i + 0)*lda + k + 1];
+	      tmpC11 += A[(j + 1)*lda + k + 1] * tB[(i + 1)*lda + k + 1];
+	      tmpC12 += A[(j + 1)*lda + k + 1] * tB[(i + 2)*lda + k + 1];
+	      tmpC13 += A[(j + 1)*lda + k + 1] * tB[(i + 3)*lda + k + 1];
+	      //tmpC14 += A[(j + 1)*lda + k + 1] * tB[(i + 4)*lda + k + 1];
+	      //tmpC15 += A[(j + 1)*lda + k + 1] * tB[(i + 5)*lda + k + 1];
+	      //tmpC16 += A[(j + 1)*lda + k + 1] * tB[(i + 6)*lda + k + 1];
+	      //tmpC17 += A[(j + 1)*lda + k + 1] * tB[(i + 7)*lda + k + 1];
+
+	      tmpC00 += A[j*lda + k + 2] * tB[(i + 0)*lda + k + 2]; 
+	      tmpC01 += A[j*lda + k + 2] * tB[(i + 1)*lda + k + 2]; 
+	      tmpC02 += A[j*lda + k + 2] * tB[(i + 2)*lda + k + 2]; 
+	      tmpC03 += A[j*lda + k + 2] * tB[(i + 3)*lda + k + 2]; 
+	      //tmpC04 += A[j*lda + k + 2] * tB[(i + 4)*lda + k + 2]; 
+	      //tmpC05 += A[j*lda + k + 2] * tB[(i + 5)*lda + k + 2]; 
+	      //tmpC06 += A[j*lda + k + 2] * tB[(i + 6)*lda + k + 2]; 
+	      //tmpC07 += A[j*lda + k + 2] * tB[(i + 7)*lda + k + 2]; 
+	      tmpC10 += A[(j + 1)*lda + k + 2] * tB[(i + 0)*lda + k + 2]; 
+	      tmpC11 += A[(j + 1)*lda + k + 2] * tB[(i + 1)*lda + k + 2]; 
+	      tmpC12 += A[(j + 1)*lda + k + 2] * tB[(i + 2)*lda + k + 2]; 
+	      tmpC13 += A[(j + 1)*lda + k + 2] * tB[(i + 3)*lda + k + 2]; 
+	      //tmpC14 += A[(j + 1)*lda + k + 2] * tB[(i + 4)*lda + k + 2]; 
+	      //tmpC15 += A[(j + 1)*lda + k + 2] * tB[(i + 5)*lda + k + 2]; 
+	      //tmpC16 += A[(j + 1)*lda + k + 2] * tB[(i + 6)*lda + k + 2]; 
+	      //tmpC17 += A[(j + 1)*lda + k + 2] * tB[(i + 7)*lda + k + 2]; 
+
+	      tmpC00 += A[j*lda + k + 3] * tB[(i + 0)*lda + k + 3];
+	      tmpC01 += A[j*lda + k + 3] * tB[(i + 1)*lda + k + 3];
+	      tmpC02 += A[j*lda + k + 3] * tB[(i + 2)*lda + k + 3];
+	      tmpC03 += A[j*lda + k + 3] * tB[(i + 3)*lda + k + 3];
+	      //tmpC04 += A[j*lda + k + 3] * tB[(i + 4)*lda + k + 3];
+	      //tmpC05 += A[j*lda + k + 3] * tB[(i + 5)*lda + k + 3];
+	      //tmpC06 += A[j*lda + k + 3] * tB[(i + 6)*lda + k + 3];
+	      //tmpC07 += A[j*lda + k + 3] * tB[(i + 7)*lda + k + 3]; 
+	      tmpC10 += A[(j + 1)*lda + k + 3] * tB[(i + 0)*lda + k + 3];
+	      tmpC11 += A[(j + 1)*lda + k + 3] * tB[(i + 1)*lda + k + 3];
+	      tmpC12 += A[(j + 1)*lda + k + 3] * tB[(i + 2)*lda + k + 3];
+	      tmpC13 += A[(j + 1)*lda + k + 3] * tB[(i + 3)*lda + k + 3];
+	      //tmpC14 += A[(j + 1)*lda + k + 3] * tB[(i + 4)*lda + k + 3];
+	      //tmpC15 += A[(j + 1)*lda + k + 3] * tB[(i + 5)*lda + k + 3];
+	      //tmpC16 += A[(j + 1)*lda + k + 3] * tB[(i + 6)*lda + k + 3];
+	      //tmpC17 += A[(j + 1)*lda + k + 3] * tB[(i + 7)*lda + k + 3];
+	    }
+	    C[j*lda + i + 0] = tmpC00; C[(j + 1)*lda + i + 0] = tmpC10; 
+	    C[j*lda + i + 1] = tmpC01; C[(j + 1)*lda + i + 1] = tmpC11; 
+	    C[j*lda + i + 2] = tmpC02; C[(j + 1)*lda + i + 2] = tmpC12; 
+	    C[j*lda + i + 3] = tmpC03; C[(j + 1)*lda + i + 3] = tmpC13; 
+	    //C[j*lda + i + 4] = tmpC04; C[(j + 1)*lda + i + 4] = tmpC14; 
+	    //C[j*lda + i + 5] = tmpC05; C[(j + 1)*lda + i + 5] = tmpC15; 
+	    //C[j*lda + i + 6] = tmpC06; C[(j + 1)*lda + i + 6] = tmpC16; 
+	    //C[j*lda + i + 7] = tmpC07; C[(j + 1)*lda + i + 7] = tmpC17; 
+            barrier(ncores);
+	  }
+}
diff --git a/apps/riscv-tests/mt/bs_matmul.c b/apps/riscv-tests/mt/bs_matmul.c
new file mode 100644
index 0000000..f80c7e1
--- /dev/null
+++ b/apps/riscv-tests/mt/bs_matmul.c
@@ -0,0 +1,26 @@
+#include "stdlib.h"
+
+#include "util.h"
+
+#include "dataset.h"
+void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda,  const data_t A[], const data_t B[], data_t C[] )
+{
+   int i,j,k,a,b,a1,a2,a3,c;
+        for (j=coreid; j<lda; j+=4*ncores){
+                a=j*lda;
+                a1=(j+1*ncores)*lda;
+                a2=(j+2*ncores)*lda;
+                a3=(j+3*ncores)*lda;
+               for (k=0;k<lda; k++)
+                {
+                        b = k*lda;
+                        for (i=0;i<lda;i++){
+                                c = B[b+i];
+                                C[i+a]+=A[a+k]*c;
+                                C[i+a1]+=A[a1+k]*c;
+                                C[i+a2]+=A[a2+k]*c;
+                                C[i+a3]+=A[a3+k]*c;
+}
+}
+}
+}
diff --git a/apps/riscv-tests/mt/ce_matmul.c b/apps/riscv-tests/mt/ce_matmul.c
new file mode 100644
index 0000000..49ad295
--- /dev/null
+++ b/apps/riscv-tests/mt/ce_matmul.c
@@ -0,0 +1,157 @@
+#include "stdlib.h"
+
+#include "util.h"
+
+#include "dataset.h"
+void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda,  const data_t A[], const data_t B[], data_t C[] )
+{
+   
+	data_t a1;
+	data_t a2;
+	data_t a3;
+	data_t a4;
+	data_t a5;
+	data_t a6;
+	data_t a7;
+	data_t a8;
+	data_t *b1;
+	data_t *b2;
+	data_t *b3;
+	data_t *b4;
+	data_t *b5;
+	data_t *b6;
+	data_t *b7;
+	data_t *b8;
+	data_t c1;
+	data_t c2;
+	data_t c3;
+	data_t c4;
+	data_t c5;
+	data_t c6;
+	data_t c7;
+	data_t c8;
+	int i, j, k;
+	int start, end;
+        static data_t BB[1024];
+
+
+        //transpose B
+                for ( k = 0; k < lda; k++) {
+                        for ( i = coreid*(lda/ncores); i < (coreid+1)*(lda/ncores); i++ )  {
+                                BB[i*lda + k] = B[k*lda + i];
+                        }
+                        barrier(ncores);
+                }
+
+	for ( int x = 0; x < ncores; x++) {
+		//split the i values into two chunks so the threads don't interfere on the B loads
+		//this could be generalized if needed, but I won't bother since it would be tricky
+		//and we already know the size and numthreads
+		start = x * (32 / ncores);
+		end = (x+1) * (32 / ncores);
+		for ( i = start; i < end; i+=8 ) { 
+			for ( j = coreid*(lda/ncores); j < (coreid+1)*(lda/ncores); j++ )  {
+				c1=0;c2=0;c3=0;c4=0;c5=0;c6=0;c7=0;c8=0;
+			        b1 = &BB[(i+0)*lda];
+				b2 = &BB[(i+1)*lda];
+				b3 = &BB[(i+2)*lda];
+				b4 = &BB[(i+3)*lda];
+			        b5 = &BB[(i+4)*lda];
+				b6 = &BB[(i+5)*lda];
+				b7 = &BB[(i+6)*lda];
+				b8 = &BB[(i+7)*lda];
+
+				for ( k = 0; k < lda; k+=8 ) {
+					a1 = A[j*lda + k+0];
+					a2 = A[j*lda + k+1];
+					a3 = A[j*lda + k+2];
+					a4 = A[j*lda + k+3];
+					a5 = A[j*lda + k+4];
+					a6 = A[j*lda + k+5];
+					a7 = A[j*lda + k+6];
+					a8 = A[j*lda + k+7];
+
+					c1 += a1 * b1[k+0];
+					c1 += a2 * b1[k+1];
+					c1 += a3 * b1[k+2];
+					c1 += a4 * b1[k+3];
+					c1 += a5 * b1[k+4];
+					c1 += a6 * b1[k+5];
+					c1 += a7 * b1[k+6];
+					c1 += a8 * b1[k+7];
+
+					c2 += a1 * b2[k+0];
+					c2 += a2 * b2[k+1];
+					c2 += a3 * b2[k+2];
+					c2 += a4 * b2[k+3];
+					c2 += a5 * b2[k+4];
+					c2 += a6 * b2[k+5];
+					c2 += a7 * b2[k+6];
+					c2 += a8 * b2[k+7];
+
+					c3 += a1 * b3[k+0];
+					c3 += a2 * b3[k+1];
+					c3 += a3 * b3[k+2];
+					c3 += a4 * b3[k+3];
+					c3 += a5 * b3[k+4];
+					c3 += a6 * b3[k+5];
+					c3 += a7 * b3[k+6];
+					c3 += a8 * b3[k+7];
+
+					c4 += a1 * b4[k+0];
+					c4 += a2 * b4[k+1];
+					c4 += a3 * b4[k+2];
+					c4 += a4 * b4[k+3];
+					c4 += a5 * b4[k+4];
+					c4 += a6 * b4[k+5];
+					c4 += a7 * b4[k+6];
+					c4 += a8 * b4[k+7];
+
+					c5 += a1 * b5[k+0];
+					c5 += a2 * b5[k+1];
+					c5 += a3 * b5[k+2];
+					c5 += a4 * b5[k+3];
+					c5 += a5 * b5[k+4];
+					c5 += a6 * b5[k+5];
+					c5 += a7 * b5[k+6];
+					c5 += a8 * b5[k+7];
+
+					c6 += a1 * b6[k+0];
+					c6 += a2 * b6[k+1];
+					c6 += a3 * b6[k+2];
+					c6 += a4 * b6[k+3];
+					c6 += a5 * b6[k+4];
+					c6 += a6 * b6[k+5];
+					c6 += a7 * b6[k+6];
+					c6 += a8 * b6[k+7];
+
+					c7 += a1 * b7[k+0];
+					c7 += a2 * b7[k+1];
+					c7 += a3 * b7[k+2];
+					c7 += a4 * b7[k+3];
+					c7 += a5 * b7[k+4];
+					c7 += a6 * b7[k+5];
+					c7 += a7 * b7[k+6];
+					c7 += a8 * b7[k+7];
+
+					c8 += a1 * b8[k+0];
+					c8 += a2 * b8[k+1];
+					c8 += a3 * b8[k+2];
+					c8 += a4 * b8[k+3];
+					c8 += a5 * b8[k+4];
+					c8 += a6 * b8[k+5];
+					c8 += a7 * b8[k+6];
+					c8 += a8 * b8[k+7];
+				}
+				C[i+0 + j*lda] += c1;
+				C[i+1 + j*lda] += c2;
+				C[i+2 + j*lda] += c3;
+				C[i+3 + j*lda] += c4;
+				C[i+4 + j*lda] += c5;
+				C[i+5 + j*lda] += c6;
+				C[i+6 + j*lda] += c7;
+				C[i+7 + j*lda] += c8;
+			}
+		}
+	}
+}
diff --git a/apps/riscv-tests/mt/cf_matmul.c b/apps/riscv-tests/mt/cf_matmul.c
new file mode 100644
index 0000000..ada9dec
--- /dev/null
+++ b/apps/riscv-tests/mt/cf_matmul.c
@@ -0,0 +1,100 @@
+#include "stdlib.h"
+
+#include "util.h"
+
+#include "dataset.h"
+void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda,  const data_t A[], const data_t B[], data_t C[] )
+{
+   if(coreid > 1) return; 
+    int i,j,k,l;
+    data_t element1, element2, element3, element4, element5, element6, element7, element8;
+    int row, row2;
+    int column1, column2, column3, column4, column5, column6, column7, column8;
+    data_t temp[32]={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
+    data_t temp2[32]={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
+    if (coreid == 0){
+      for (i=0; i<32; i+=2){
+	row = i*32;
+	row2 = (i+1)*32;
+	for (j=0; j<16; j+=4){
+	  element1 = A[row+j];
+	  element2 = A[row+j+1];
+	  element3 = A[row+j+2];
+	  element4 = A[row+j+3];
+	  column1 = j*32;
+	  column2 = (j+1)*32;
+	  column3 = (j+2)*32;
+	  column4 = (j+3)*32;
+	  element5 = A[row2+j];
+	  element6 = A[row2+j+1];
+	  element7 = A[row2+j+2];
+	  element8 = A[row2+j+3];
+
+	  for (k=0; k<32; k+=4){
+	    temp[k]+=element1*B[column1+k]+element2*B[column2+k]+element3*B[column3+k]+element4*B[column4+k];
+	    temp[k+1]+=element1*B[column1+k+1]+element2*B[column2+k+1]+element3*B[column3+k+1]+element4*B[column4+k+1];
+	    temp[k+2]+=element1*B[column1+k+2]+element2*B[column2+k+2]+element3*B[column3+k+2]+element4*B[column4+k+2];
+	    temp[k+3]+=element1*B[column1+k+3]+element2*B[column2+k+3]+element3*B[column3+k+3]+element4*B[column4+k+3];
+	    temp2[k]+=element5*B[column1+k]+element6*B[column2+k]+element7*B[column3+k]+element8*B[column4+k];
+	    temp2[k+1]+=element5*B[column1+k+1]+element6*B[column2+k+1]+element7*B[column3+k+1]+element8*B[column4+k+1];
+	    temp2[k+2]+=element5*B[column1+k+2]+element6*B[column2+k+2]+element7*B[column3+k+2]+element8*B[column4+k+2];
+	    temp2[k+3]+=element5*B[column1+k+3]+element6*B[column2+k+3]+element7*B[column3+k+3]+element8*B[column4+k+3];
+	  }
+
+	
+	}
+    for (l=0; l<32; l++){
+	      C[row+l]+=temp[l];
+	      C[row2+l]+=temp2[l];
+	      temp[l]=0;
+	      temp2[l]=0;
+	    }
+	  
+      }
+    }
+    if(coreid == 1 || ncores == 1) {
+      for (i=0; i<32; i+=2){
+	row = (31-i)*32;
+	row2 = (31-i-1)*32;
+	for (j=16; j<32; j+=4){
+	  element1 = A[row+j];
+	  element2 = A[row+j+1];
+	  element3 = A[row+j+2];
+	  element4 = A[row+j+3];
+	  element5 = A[row2+j];
+	  element6 = A[row2+j+1];
+	  element7 = A[row2+j+2];
+	  element8 = A[row2+j+3];
+	  column1 = j*32;
+	  column2 = (j+1)*32;
+	  column3 = (j+2)*32;
+	  column4 = (j+3)*32;
+	  for (k=0; k<32; k+=4){
+	    temp[k]+=element1*B[column1+k]+element2*B[column2+k]+element3*B[column3+k]+element4*B[column4+k];
+	    temp[k+1]+=element1*B[column1+k+1]+element2*B[column2+k+1]+element3*B[column3+k+1]+element4*B[column4+k+1];
+	    temp[k+2]+=element1*B[column1+k+2]+element2*B[column2+k+2]+element3*B[column3+k+2]+element4*B[column4+k+2];
+	    temp[k+3]+=element1*B[column1+k+3]+element2*B[column2+k+3]+element3*B[column3+k+3]+element4*B[column4+k+3];
+	    temp2[k]+=element5*B[column1+k]+element6*B[column2+k]+element7*B[column3+k]+element8*B[column4+k];
+	    temp2[k+1]+=element5*B[column1+k+1]+element6*B[column2+k+1]+element7*B[column3+k+1]+element8*B[column4+k+1];
+	    temp2[k+2]+=element5*B[column1+k+2]+element6*B[column2+k+2]+element7*B[column3+k+2]+element8*B[column4+k+2];
+	    temp2[k+3]+=element5*B[column1+k+3]+element6*B[column2+k+3]+element7*B[column3+k+3]+element8*B[column4+k+3];
+	  }
+
+
+	  
+	}
+	    for (l=0; l<32; l++){
+	      C[row+l]+=temp[l];
+	      C[row2+l]+=temp2[l];
+	      temp[l]=0;
+	      temp2[l]=0;
+	    }
+      }
+      }  
+   // ***************************** //
+   // **** ADD YOUR CODE HERE ***** //
+   // ***************************** //
+   //
+   // feel free to make a separate function for MI and MSI versions.
+
+}
diff --git a/apps/riscv-tests/mt/cg_matmul.c b/apps/riscv-tests/mt/cg_matmul.c
new file mode 100644
index 0000000..9db30cd
--- /dev/null
+++ b/apps/riscv-tests/mt/cg_matmul.c
@@ -0,0 +1,78 @@
+#include "stdlib.h"
+
+#include "util.h"
+
+#include "dataset.h"
+void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda,  const data_t A[], const data_t B[], data_t C[] )
+{    
+    int i, j, k;
+    
+    for ( i = 0; i < lda; i+=2 )
+    {
+        for (k = 0; k < lda; k+=4)
+        {
+            int d0 = B[k*lda + i];
+            int c0 = B[k*lda + i + 1];
+            int d1 = B[(k+1)*lda + i];
+            int c1 = B[(k+1)*lda + i + 1];
+            int d2 = B[(k+2)*lda + i];
+            int c2 = B[(k+2)*lda + i + 1];
+            int d3 = B[(k+3)*lda + i];
+            int c3 = B[(k+3)*lda + i + 1];
+            
+            for ( j = coreid*(lda/ncores); j < (coreid+1)*(lda/ncores); j+=4)
+            {
+                
+                int sum = A[j*lda + k] * d0;
+                sum += A[j*lda + k + 1] * d1;
+                sum += A[j*lda + k + 2] * d2;
+                sum += A[j*lda + k + 3] * d3;
+                C[j*lda +i] += sum;
+                
+                sum = A[j*lda + k] * c0;
+                sum += A[j*lda + k + 1] * c1;
+                sum += A[j*lda + k + 2] * c2;
+                sum += A[j*lda + k + 3] * c3;
+                C[j*lda + i + 1] += sum;
+                
+                sum = A[(j+1)*lda + k] * d0;
+                sum += A[(j+1)*lda + k + 1] * d1;
+                sum += A[(j+1)*lda + k + 2] * d2;
+                sum += A[(j+1)*lda + k + 3] * d3;
+                C[(j+1)*lda +i] += sum;
+                
+                sum = A[(j+1)*lda + k] * c0;
+                sum += A[(j+1)*lda + k + 1] * c1;
+                sum += A[(j+1)*lda + k + 2] * c2;
+                sum += A[(j+1)*lda + k + 3] * c3;
+                C[(j+1)*lda + i + 1] += sum;
+                
+                sum = A[(j+2)*lda + k] * d0;
+                sum += A[(j+2)*lda + k + 1] * d1;
+                sum += A[(j+2)*lda + k + 2] * d2;
+                sum += A[(j+2)*lda + k + 3] * d3;
+                C[(j+2)*lda +i] += sum;
+                
+                sum = A[(j+2)*lda + k] * c0;
+                sum += A[(j+2)*lda + k + 1] * c1;
+                sum += A[(j+2)*lda + k + 2] * c2;
+                sum += A[(j+2)*lda + k + 3] * c3;
+                C[(j+2)*lda + i + 1] += sum;
+                
+                sum = A[(j+3)*lda + k] * d0;
+                sum += A[(j+3)*lda + k + 1] * d1;
+                sum += A[(j+3)*lda + k + 2] * d2;
+                sum += A[(j+3)*lda + k + 3] * d3;
+                C[(j+3)*lda +i] += sum;
+                
+                sum = A[(j+3)*lda + k] * c0;
+                sum += A[(j+3)*lda + k + 1] * c1;
+                sum += A[(j+3)*lda + k + 2] * c2;
+                sum += A[(j+3)*lda + k + 3] * c3;
+                C[(j+3)*lda + i + 1] += sum;
+                
+            }
+            barrier(ncores);
+        }
+    }
+}
diff --git a/apps/riscv-tests/mt/ci_matmul.c b/apps/riscv-tests/mt/ci_matmul.c
new file mode 100644
index 0000000..3b7977d
--- /dev/null
+++ b/apps/riscv-tests/mt/ci_matmul.c
@@ -0,0 +1,70 @@
+#include "stdlib.h"
+
+#include "util.h"
+
+#include "dataset.h"
+void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda,  const data_t A[], const data_t B[], data_t C[] )
+{
+   
+   // ***************************** //
+   // **** ADD YOUR CODE HERE ***** //
+   // ***************************** //
+   //
+   // feel free to make a separate function for MI and MSI versions.
+   
+//----------MSI--------------
+/*
+   int i,j,k;
+   barrier(nc);
+   for(j = coreid*lda/ncores; j < coreid*lda/ncores + lda/ncores; j++) {
+	for(i = 0; i < lda; i+=4) {
+		data_t Cval0 = 0;
+		data_t Cval1 = 0;
+		data_t Cval2 = 0;
+		data_t Cval3 = 0;
+		for(k = 0; k < lda; k++) {
+			Cval0 += A[j*lda+k]*B[k*lda+i];
+			Cval1 += A[j*lda+k]*B[k*lda+i+1];
+			Cval2 += A[j*lda+k]*B[k*lda+i+2];
+			Cval3 += A[j*lda+k]*B[k*lda+i+3];
+		}
+		C[j*lda+i] = Cval0;
+		C[j*lda+i+1] = Cval1;
+		C[j*lda+i+2] = Cval2;
+		C[j*lda+i+3] = Cval3;
+	}
+   }
+*/
+
+//------------------MI-------------------
+
+   int i,j,k;
+   barrier(ncores);
+   for(j = coreid*lda/ncores; j < coreid*lda/ncores + lda/ncores; j++) {
+        for(i = 0; i < lda; i+=4) {
+		data_t Cval0 = 0;
+	        data_t Cval1 = 0;
+        	data_t Cval2 = 0;
+		data_t Cval3 = 0;
+		if(coreid == 0) {
+	               	for(k = 0; k < lda; k++) {
+        	              	Cval0 += A[j*lda+k]*B[k*lda+i];
+				Cval1 += A[j*lda+k]*B[k*lda+i+1];
+				Cval2 += A[j*lda+k]*B[k*lda+i+2];
+				Cval3 += A[j*lda+k]*B[k*lda+i+3];
+			}
+		} else {
+			for(k = lda-1; k >= 0; k--) {
+                                Cval0 += A[j*lda+k]*B[k*lda+i];
+	                        Cval1 += A[j*lda+k]*B[k*lda+i+1];
+                                Cval2 += A[j*lda+k]*B[k*lda+i+2];
+                                Cval3 += A[j*lda+k]*B[k*lda+i+3];
+                        }
+		}
+		C[j*lda+i] = Cval0;
+                C[j*lda+i+1] = Cval1;
+                C[j*lda+i+2] = Cval2;
+                C[j*lda+i+3] = Cval3;
+	}
+   }
+}
diff --git a/apps/riscv-tests/mt/ck_matmul.c b/apps/riscv-tests/mt/ck_matmul.c
new file mode 100644
index 0000000..753a36d
--- /dev/null
+++ b/apps/riscv-tests/mt/ck_matmul.c
@@ -0,0 +1,61 @@
+#include "stdlib.h"
+
+#include "util.h"
+
+#include "dataset.h"
+void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda,  const data_t A[], const data_t B[], data_t C[] )
+{
+   
+   // ***************************** //
+   // **** ADD YOUR CODE HERE ***** //
+   // ***************************** //
+   //
+   // feel free to make a separate function for MI and MSI versions.
+  int i, j, k, ii, jj, bsize, start;
+  bsize = 16;
+  start = bsize*coreid;
+  for ( jj = start; jj < lda; jj += bsize*ncores) {
+    int first = 1;
+    for ( ii = start; ii !=start || first; ii=(bsize+ii) % lda) {
+      first = 0;
+      for ( j = jj; j < lda && j < jj + bsize; j+=4) {
+	for ( i = ii; i < lda && i < ii + bsize; i+=2) {
+	  data_t c1 = C[i + j*lda];
+	  data_t c2 = C[i + j*lda + 1];
+	  data_t c3 = C[i + (j+1)*lda];
+	  data_t c4 = C[i + (j+1)*lda + 1];
+	  data_t c5 = C[i + (j+2)*lda];
+	  data_t c6 = C[i + (j+2)*lda + 1];
+	  data_t c7 = C[i + (j+3)*lda];
+	  data_t c8 = C[i + (j+3)*lda + 1];
+	  for ( k = 0; k < lda; k+=8){
+	    for (int x = 0; x < 8; x++) {
+	    data_t a = A[j*lda + k+x];
+	    data_t a1 = A[(j+1)*lda +k+x];
+	    data_t a2 = A[(j+2)*lda +k+x];
+	    data_t a3 = A[(j+3)*lda +k+x];
+	    data_t b1 = B[(k+x)*lda + i];
+	    data_t b2 = B[(k+x)*lda + i + 1];
+	    c1 += a * b1;
+	    c2 += a * b2;
+	    c3 += a1* b1;
+	    c4 += a1* b2;
+	    c5 += a2* b1;
+	    c6 += a2* b2;
+	    c7 += a3* b1;
+	    c8 += a3* b2;
+	    }
+	  }
+	  C[i + j*lda] = c1;
+	  C[i + j*lda + 1] = c2;
+	  C[i + (j+1)*lda] = c3;
+	  C[i + (j+1)*lda + 1] = c4;
+	  C[i + (j+2)*lda] = c5;
+	  C[i + (j+2)*lda + 1] = c6;
+	  C[i + (j+3)*lda] = c7;
+	  C[i + (j+3)*lda + 1] = c8;
+	}
+      }
+   }
+  }
+}
diff --git a/apps/riscv-tests/mt/cl_matmul.c b/apps/riscv-tests/mt/cl_matmul.c
new file mode 100644
index 0000000..086a614
--- /dev/null
+++ b/apps/riscv-tests/mt/cl_matmul.c
@@ -0,0 +1,176 @@
+#include "stdlib.h"
+
+#include "util.h"
+
+#include "dataset.h"
+void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda,  const data_t A[], const data_t B[], data_t C[] )
+{
+   if(coreid > 1) return; 
+   // feel free to make a separate function for MI and MSI versions.
+   int i, j, k, x;
+   data_t temp0, temp1, temp2, temp3, temp4, temp5, temp6, temp7;
+   data_t temp8, temp9, temp10, temp11, temp12, temp13, temp14, temp15;
+
+
+   if(coreid == 0) {
+      for(j = 0; j < 32; j++) {
+         temp0  = C[j*lda];
+         temp1  = C[1  + j*lda];
+         temp2  = C[2  + j*lda];
+         temp3  = C[3  + j*lda];
+         temp4  = C[4  + j*lda];
+         temp5  = C[5  + j*lda];
+         temp6  = C[6  + j*lda];
+         temp7  = C[7  + j*lda];
+         temp8  = C[8  + j*lda];
+         temp9  = C[9  + j*lda];
+         temp10 = C[10 + j*lda];
+         temp11 = C[11 + j*lda];
+         temp12 = C[12 + j*lda];
+         temp13 = C[13 + j*lda];
+         temp14 = C[14 + j*lda];
+         temp15 = C[15 + j*lda];
+         for(k = 0; k < 32; k++) {
+            temp0  += A[j*lda + k] * B[k*lda];
+            temp1  += A[j*lda + k] * B[1  + k*lda];
+            temp2  += A[j*lda + k] * B[2  + k*lda];
+            temp3  += A[j*lda + k] * B[3  + k*lda];
+            temp4  += A[j*lda + k] * B[4  + k*lda];
+            temp5  += A[j*lda + k] * B[5  + k*lda];
+            temp6  += A[j*lda + k] * B[6  + k*lda];
+            temp7  += A[j*lda + k] * B[7  + k*lda];
+            temp8  += A[j*lda + k] * B[8  + k*lda];
+            temp9  += A[j*lda + k] * B[9  + k*lda];
+            temp10 += A[j*lda + k] * B[10 + k*lda];
+            temp11 += A[j*lda + k] * B[11 + k*lda];
+            temp12 += A[j*lda + k] * B[12 + k*lda];
+            temp13 += A[j*lda + k] * B[13 + k*lda];
+            temp14 += A[j*lda + k] * B[14 + k*lda];
+            temp15 += A[j*lda + k] * B[15 + k*lda];
+         }
+         C[j*lda] = temp0;
+         C[1  + j*lda] = temp1;
+         C[2  + j*lda] = temp2;
+         C[3  + j*lda] = temp3;
+         C[4  + j*lda] = temp4;
+         C[5  + j*lda] = temp5;
+         C[6  + j*lda] = temp6;
+         C[7  + j*lda] = temp7;
+         C[8  + j*lda] = temp8;
+         C[9  + j*lda] = temp9;
+         C[10 + j*lda] = temp10;
+         C[11 + j*lda] = temp11;
+         C[12 + j*lda] = temp12;
+         C[13 + j*lda] = temp13;
+         C[14 + j*lda] = temp14;
+         C[15 + j*lda] = temp15;
+      }
+   }
+
+   if(coreid == 1 || ncores == 1)  {
+      for(j = 16; j < 32; j++) {
+         temp0  = C[16 + j*lda];
+         temp1  = C[17 + j*lda];
+         temp2  = C[18 + j*lda];
+         temp3  = C[19 + j*lda];
+         temp4  = C[20 + j*lda];
+         temp5  = C[21 + j*lda];
+         temp6  = C[22 + j*lda];
+         temp7  = C[23 + j*lda];
+         temp8  = C[24 + j*lda];
+         temp9  = C[25 + j*lda];
+         temp10 = C[26 + j*lda];
+         temp11 = C[27 + j*lda];
+         temp12 = C[28 + j*lda];
+         temp13 = C[29 + j*lda];
+         temp14 = C[30 + j*lda];
+         temp15 = C[31 + j*lda];
+         for(k = 0; k < 32; k++) {
+            temp0  += A[j*lda + k] * B[16 + k*lda];
+            temp1  += A[j*lda + k] * B[17 + k*lda];
+            temp2  += A[j*lda + k] * B[18 + k*lda];
+            temp3  += A[j*lda + k] * B[19 + k*lda];
+            temp4  += A[j*lda + k] * B[20 + k*lda];
+            temp5  += A[j*lda + k] * B[21 + k*lda];
+            temp6  += A[j*lda + k] * B[22 + k*lda];
+            temp7  += A[j*lda + k] * B[23 + k*lda];
+            temp8  += A[j*lda + k] * B[24 + k*lda];
+            temp9  += A[j*lda + k] * B[25 + k*lda];
+            temp10 += A[j*lda + k] * B[26 + k*lda];
+            temp11 += A[j*lda + k] * B[27 + k*lda];
+            temp12 += A[j*lda + k] * B[28 + k*lda];
+            temp13 += A[j*lda + k] * B[29 + k*lda];
+            temp14 += A[j*lda + k] * B[30 + k*lda];
+            temp15 += A[j*lda + k] * B[31 + k*lda];
+         }
+         C[16 + j*lda] = temp0;
+         C[17 + j*lda] = temp1;
+         C[18 + j*lda] = temp2;
+         C[19 + j*lda] = temp3;
+         C[20 + j*lda] = temp4;
+         C[21 + j*lda] = temp5;
+         C[22 + j*lda] = temp6;
+         C[23 + j*lda] = temp7;
+         C[24 + j*lda] = temp8;
+         C[25 + j*lda] = temp9;
+         C[26 + j*lda] = temp10;
+         C[27 + j*lda] = temp11;
+         C[28 + j*lda] = temp12;
+         C[29 + j*lda] = temp13;
+         C[30 + j*lda] = temp14;
+         C[31 + j*lda] = temp15;
+      }
+      for(j = 0; j <16; j++) {
+         temp0  = C[16 + j*lda];
+         temp1  = C[17 + j*lda];
+         temp2  = C[18 + j*lda];
+         temp3  = C[19 + j*lda];
+         temp4  = C[20 + j*lda];
+         temp5  = C[21 + j*lda];
+         temp6  = C[22 + j*lda];
+         temp7  = C[23 + j*lda];
+         temp8  = C[24 + j*lda];
+         temp9  = C[25 + j*lda];
+         temp10 = C[26 + j*lda];
+         temp11 = C[27 + j*lda];
+         temp12 = C[28 + j*lda];
+         temp13 = C[29 + j*lda];
+         temp14 = C[30 + j*lda];
+         temp15 = C[31 + j*lda];
+         for(k = 0; k < 32; k++) {
+            temp0  += A[j*lda + k] * B[16 + k*lda];
+            temp1  += A[j*lda + k] * B[17 + k*lda];
+            temp2  += A[j*lda + k] * B[18 + k*lda];
+            temp3  += A[j*lda + k] * B[19 + k*lda];
+            temp4  += A[j*lda + k] * B[20 + k*lda];
+            temp5  += A[j*lda + k] * B[21 + k*lda];
+            temp6  += A[j*lda + k] * B[22 + k*lda];
+            temp7  += A[j*lda + k] * B[23 + k*lda];
+            temp8  += A[j*lda + k] * B[24 + k*lda];
+            temp9  += A[j*lda + k] * B[25 + k*lda];
+            temp10 += A[j*lda + k] * B[26 + k*lda];
+            temp11 += A[j*lda + k] * B[27 + k*lda];
+            temp12 += A[j*lda + k] * B[28 + k*lda];
+            temp13 += A[j*lda + k] * B[29 + k*lda];
+            temp14 += A[j*lda + k] * B[30 + k*lda];
+            temp15 += A[j*lda + k] * B[31 + k*lda];
+         }
+         C[16 + j*lda] = temp0;
+         C[17 + j*lda] = temp1;
+         C[18 + j*lda] = temp2;
+         C[19 + j*lda] = temp3;
+         C[20 + j*lda] = temp4;
+         C[21 + j*lda] = temp5;
+         C[22 + j*lda] = temp6;
+         C[23 + j*lda] = temp7;
+         C[24 + j*lda] = temp8;
+         C[25 + j*lda] = temp9;
+         C[26 + j*lda] = temp10;
+         C[27 + j*lda] = temp11;
+         C[28 + j*lda] = temp12;
+         C[29 + j*lda] = temp13;
+         C[30 + j*lda] = temp14;
+         C[31 + j*lda] = temp15;
+      }
+   } 
+}
diff --git a/apps/riscv-tests/mt/cm_matmul.c b/apps/riscv-tests/mt/cm_matmul.c
new file mode 100644
index 0000000..ae52b27
--- /dev/null
+++ b/apps/riscv-tests/mt/cm_matmul.c
@@ -0,0 +1,91 @@
+#include "stdlib.h"
+
+#include "util.h"
+
+#include "dataset.h"
+void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda,  const data_t A[], const data_t B[], data_t C[] )
+{
+    int i,j,k,l;
+    data_t element1, element2, element3, element4, element5, element6, element7, element8;
+    int row, row2;
+    int column1, column2, column3, column4, column5, column6, column7, column8;
+    data_t temp[32]={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
+    data_t temp2[32]={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
+    if (coreid == 0){
+      for (i=0; i<lda; i+=2){
+	row = i*lda;
+	row2 = (i+1)*lda;
+	for (j=0; j<16; j+=4){
+	  element1 = A[row+j];
+	  element2 = A[row+j+1];
+	  element3 = A[row+j+2];
+	  element4 = A[row+j+3];
+	  column1 = j*32;
+	  column2 = (j+1)*32;
+	  column3 = (j+2)*32;
+	  column4 = (j+3)*32;
+	  element5 = A[row2+j];
+	  element6 = A[row2+j+1];
+	  element7 = A[row2+j+2];
+	  element8 = A[row2+j+3];
+
+	  for (k=0; k<32; k+=4){
+	    temp[k]+=element1*B[column1+k]+element2*B[column2+k]+element3*B[column3+k]+element4*B[column4+k];
+	    temp[k+1]+=element1*B[column1+k+1]+element2*B[column2+k+1]+element3*B[column3+k+1]+element4*B[column4+k+1];
+	    temp[k+2]+=element1*B[column1+k+2]+element2*B[column2+k+2]+element3*B[column3+k+2]+element4*B[column4+k+2];
+	    temp[k+3]+=element1*B[column1+k+3]+element2*B[column2+k+3]+element3*B[column3+k+3]+element4*B[column4+k+3];
+	    temp2[k]+=element5*B[column1+k]+element6*B[column2+k]+element7*B[column3+k]+element8*B[column4+k];
+	    temp2[k+1]+=element5*B[column1+k+1]+element6*B[column2+k+1]+element7*B[column3+k+1]+element8*B[column4+k+1];
+	    temp2[k+2]+=element5*B[column1+k+2]+element6*B[column2+k+2]+element7*B[column3+k+2]+element8*B[column4+k+2];
+	    temp2[k+3]+=element5*B[column1+k+3]+element6*B[column2+k+3]+element7*B[column3+k+3]+element8*B[column4+k+3];
+	  }
+	  if (j==12){
+	    for (l=0; l<32; l++){
+	      C[row+l]+=temp[l];
+	      C[row2+l]+=temp2[l];
+	      temp[l]=0;
+	      temp2[l]=0;
+	    }
+	  }
+	}
+      }
+    }
+    if (coreid==1 || ncores == 1){
+      for (i=0; i<32; i+=2){
+	row = (31-i)*lda;
+	row2 = (31-i-1)*lda;
+	for (j=16; j<32; j+=4){
+	  element1 = A[row+j];
+	  element2 = A[row+j+1];
+	  element3 = A[row+j+2];
+	  element4 = A[row+j+3];
+	  element5 = A[row2+j];
+	  element6 = A[row2+j+1];
+	  element7 = A[row2+j+2];
+	  element8 = A[row2+j+3];
+	  column1 = j*32;
+	  column2 = (j+1)*32;
+	  column3 = (j+2)*32;
+	  column4 = (j+3)*32;
+	  for (k=0; k<32; k+=4){
+	    temp[k]+=element1*B[column1+k]+element2*B[column2+k]+element3*B[column3+k]+element4*B[column4+k];
+	    temp[k+1]+=element1*B[column1+k+1]+element2*B[column2+k+1]+element3*B[column3+k+1]+element4*B[column4+k+1];
+	    temp[k+2]+=element1*B[column1+k+2]+element2*B[column2+k+2]+element3*B[column3+k+2]+element4*B[column4+k+2];
+	    temp[k+3]+=element1*B[column1+k+3]+element2*B[column2+k+3]+element3*B[column3+k+3]+element4*B[column4+k+3];
+	    temp2[k]+=element5*B[column1+k]+element6*B[column2+k]+element7*B[column3+k]+element8*B[column4+k];
+	    temp2[k+1]+=element5*B[column1+k+1]+element6*B[column2+k+1]+element7*B[column3+k+1]+element8*B[column4+k+1];
+	    temp2[k+2]+=element5*B[column1+k+2]+element6*B[column2+k+2]+element7*B[column3+k+2]+element8*B[column4+k+2];
+	    temp2[k+3]+=element5*B[column1+k+3]+element6*B[column2+k+3]+element7*B[column3+k+3]+element8*B[column4+k+3];
+	  }
+	  if (j==28){
+	    for (l=0; l<32; l++){
+	      C[row+l]+=temp[l];
+	      C[row2+l]+=temp2[l];
+	      temp[l]=0;
+	      temp2[l]=0;
+	    }
+	  }
+	}
+      }
+      }  
+}
diff --git a/apps/riscv-tests/mt/cs_matmul.c b/apps/riscv-tests/mt/cs_matmul.c
new file mode 100644
index 0000000..858b05e
--- /dev/null
+++ b/apps/riscv-tests/mt/cs_matmul.c
@@ -0,0 +1,24 @@
+#include "stdlib.h"
+
+#include "util.h"
+
+#include "dataset.h"
+void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda,  const data_t A[], const data_t B[], data_t C[] )
+{
+   int i, j, k, n, m, c1, c2;
+   for ( j = coreid; j < lda; j += 2*ncores ) {
+      for ( i = 0; i < lda; i += 1 ){
+         c1 = 0;     //global vars c1, c2
+         c2 = 0;
+         for ( k = 0; k < lda; k += 1 ) {
+            c1 += A[j * lda + k] * B[k*lda + i];
+            c2 += A[(j+ncores) * lda + k] * B[k*lda + i];
+         }
+
+         C[i + j * lda] = c1;
+         C[i + (j+ncores) * lda] = c2;
+         barrier(ncores);
+      }
+   }
+   
+}
diff --git a/apps/riscv-tests/mt/cv_matmul.c b/apps/riscv-tests/mt/cv_matmul.c
new file mode 100644
index 0000000..2a06919
--- /dev/null
+++ b/apps/riscv-tests/mt/cv_matmul.c
@@ -0,0 +1,374 @@
+#include "stdlib.h"
+
+#include "util.h"
+
+#include "dataset.h"
+void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda,  const data_t A[], const data_t B[], data_t C[] )
+{
+	//----------------------------------------------------------------version 2.11 optmize j,use core 1 j from 0 to 15 MSI 98k i = j*lda
+	//----------------------------------------------------------------version 2.12 not use i = j *lda MSI  95k
+	static __thread data_t TempA[8];
+	static __thread data_t TempB[8];
+	static __thread int j,m,n,i,k;
+	
+	if(coreid == 1 || ncores == 1)
+	{
+	for ( j = 16; j < 32; j++ )
+     {		
+		  
+      for ( m = 0; m < 4; m++ )  
+      {
+		  
+		 TempA[0] = A[j*lda+0+8*m];
+		 TempA[1] = A[j*lda+1+8*m];
+		 TempA[2] = A[j*lda+2+8*m];
+		 TempA[3] = A[j*lda+3+8*m];
+		 TempA[4] = A[j*lda+4+8*m];
+		 TempA[5] = A[j*lda+5+8*m];
+		 TempA[6] = A[j*lda+6+8*m];
+		 TempA[7] = A[j*lda+7+8*m];
+		 
+		for( n = 0; n < 4; n++)
+		{
+		 TempB[0] = B[(0+8*m)*lda+0+8*n]; 
+		 TempB[1] = B[(0+8*m)*lda+1+8*n]; 
+		 TempB[2] = B[(0+8*m)*lda+2+8*n]; 
+		 TempB[3] = B[(0+8*m)*lda+3+8*n]; 
+		 TempB[4] = B[(0+8*m)*lda+4+8*n]; 
+		 TempB[5] = B[(0+8*m)*lda+5+8*n]; 
+		 TempB[6] = B[(0+8*m)*lda+6+8*n]; 
+		 TempB[7] = B[(0+8*m)*lda+7+8*n]; 
+		 
+		 C[0+8*n+j*lda] += TempA[0] * TempB[0];
+		 C[1+8*n+j*lda] += TempA[0] * TempB[1];
+		 C[2+8*n+j*lda] += TempA[0] * TempB[2];
+		 C[3+8*n+j*lda] += TempA[0] * TempB[3];
+		 C[4+8*n+j*lda] += TempA[0] * TempB[4];
+		 C[5+8*n+j*lda] += TempA[0] * TempB[5];
+		 C[6+8*n+j*lda] += TempA[0] * TempB[6];
+		 C[7+8*n+j*lda] += TempA[0] * TempB[7];
+		 
+
+
+		 TempB[0] = B[(1+8*m)*lda+0+8*n]; 
+		 TempB[1] = B[(1+8*m)*lda+1+8*n]; 
+		 TempB[2] = B[(1+8*m)*lda+2+8*n]; 
+		 TempB[3] = B[(1+8*m)*lda+3+8*n]; 
+		 TempB[4] = B[(1+8*m)*lda+4+8*n]; 
+		 TempB[5] = B[(1+8*m)*lda+5+8*n]; 
+		 TempB[6] = B[(1+8*m)*lda+6+8*n]; 
+		 TempB[7] = B[(1+8*m)*lda+7+8*n]; 
+		 
+		 C[0+8*n+j*lda] += TempA[1] * TempB[0];
+		 C[1+8*n+j*lda] += TempA[1] * TempB[1];
+		 C[2+8*n+j*lda] += TempA[1] * TempB[2];
+		 C[3+8*n+j*lda] += TempA[1] * TempB[3];
+		 C[4+8*n+j*lda] += TempA[1] * TempB[4];
+		 C[5+8*n+j*lda] += TempA[1] * TempB[5];
+		 C[6+8*n+j*lda] += TempA[1] * TempB[6];
+		 C[7+8*n+j*lda] += TempA[1] * TempB[7];
+		 
+
+
+		 TempB[0] = B[(2+8*m)*lda+0+8*n]; 
+		 TempB[1] = B[(2+8*m)*lda+1+8*n]; 
+		 TempB[2] = B[(2+8*m)*lda+2+8*n]; 
+		 TempB[3] = B[(2+8*m)*lda+3+8*n]; 
+		 TempB[4] = B[(2+8*m)*lda+4+8*n]; 
+		 TempB[5] = B[(2+8*m)*lda+5+8*n]; 
+		 TempB[6] = B[(2+8*m)*lda+6+8*n]; 
+		 TempB[7] = B[(2+8*m)*lda+7+8*n]; 
+		 
+		 C[0+8*n+j*lda] += TempA[2] * TempB[0];
+		 C[1+8*n+j*lda] += TempA[2] * TempB[1];
+		 C[2+8*n+j*lda] += TempA[2] * TempB[2];
+		 C[3+8*n+j*lda] += TempA[2] * TempB[3];
+		 C[4+8*n+j*lda] += TempA[2] * TempB[4];
+		 C[5+8*n+j*lda] += TempA[2] * TempB[5];
+		 C[6+8*n+j*lda] += TempA[2] * TempB[6];
+		 C[7+8*n+j*lda] += TempA[2] * TempB[7];
+		 
+
+
+		 TempB[0] = B[(3+8*m)*lda+0+8*n]; 
+		 TempB[1] = B[(3+8*m)*lda+1+8*n]; 
+		 TempB[2] = B[(3+8*m)*lda+2+8*n]; 
+		 TempB[3] = B[(3+8*m)*lda+3+8*n]; 
+		 TempB[4] = B[(3+8*m)*lda+4+8*n]; 
+		 TempB[5] = B[(3+8*m)*lda+5+8*n]; 
+		 TempB[6] = B[(3+8*m)*lda+6+8*n]; 
+		 TempB[7] = B[(3+8*m)*lda+7+8*n]; 
+		 
+		 C[0+8*n+j*lda] += TempA[3] * TempB[0];
+		 C[1+8*n+j*lda] += TempA[3] * TempB[1];
+		 C[2+8*n+j*lda] += TempA[3] * TempB[2];
+		 C[3+8*n+j*lda] += TempA[3] * TempB[3];
+		 C[4+8*n+j*lda] += TempA[3] * TempB[4];
+		 C[5+8*n+j*lda] += TempA[3] * TempB[5];
+		 C[6+8*n+j*lda] += TempA[3] * TempB[6];
+		 C[7+8*n+j*lda] += TempA[3] * TempB[7];
+
+
+		 TempB[0] = B[(4+8*m)*lda+0+8*n]; 
+		 TempB[1] = B[(4+8*m)*lda+1+8*n]; 
+		 TempB[2] = B[(4+8*m)*lda+2+8*n]; 
+		 TempB[3] = B[(4+8*m)*lda+3+8*n]; 
+		 TempB[4] = B[(4+8*m)*lda+4+8*n]; 
+		 TempB[5] = B[(4+8*m)*lda+5+8*n]; 
+		 TempB[6] = B[(4+8*m)*lda+6+8*n]; 
+		 TempB[7] = B[(4+8*m)*lda+7+8*n]; 
+		 
+		 C[0+8*n+j*lda] += TempA[4] * TempB[0];
+		 C[1+8*n+j*lda] += TempA[4] * TempB[1];
+		 C[2+8*n+j*lda] += TempA[4] * TempB[2];
+		 C[3+8*n+j*lda] += TempA[4] * TempB[3];
+		 C[4+8*n+j*lda] += TempA[4] * TempB[4];
+		 C[5+8*n+j*lda] += TempA[4] * TempB[5];
+		 C[6+8*n+j*lda] += TempA[4] * TempB[6];
+		 C[7+8*n+j*lda] += TempA[4] * TempB[7];
+		 
+
+
+		 TempB[0] = B[(5+8*m)*lda+0+8*n]; 
+		 TempB[1] = B[(5+8*m)*lda+1+8*n]; 
+		 TempB[2] = B[(5+8*m)*lda+2+8*n]; 
+		 TempB[3] = B[(5+8*m)*lda+3+8*n]; 
+		 TempB[4] = B[(5+8*m)*lda+4+8*n]; 
+		 TempB[5] = B[(5+8*m)*lda+5+8*n]; 
+		 TempB[6] = B[(5+8*m)*lda+6+8*n]; 
+		 TempB[7] = B[(5+8*m)*lda+7+8*n]; 
+		 
+		 C[0+8*n+j*lda] += TempA[5] * TempB[0];
+		 C[1+8*n+j*lda] += TempA[5] * TempB[1];
+		 C[2+8*n+j*lda] += TempA[5] * TempB[2];
+		 C[3+8*n+j*lda] += TempA[5] * TempB[3];
+		 C[4+8*n+j*lda] += TempA[5] * TempB[4];
+		 C[5+8*n+j*lda] += TempA[5] * TempB[5];
+		 C[6+8*n+j*lda] += TempA[5] * TempB[6];
+		 C[7+8*n+j*lda] += TempA[5] * TempB[7];
+		 
+
+
+		 TempB[0] = B[(6+8*m)*lda+0+8*n]; 
+		 TempB[1] = B[(6+8*m)*lda+1+8*n]; 
+		 TempB[2] = B[(6+8*m)*lda+2+8*n]; 
+		 TempB[3] = B[(6+8*m)*lda+3+8*n]; 
+		 TempB[4] = B[(6+8*m)*lda+4+8*n]; 
+		 TempB[5] = B[(6+8*m)*lda+5+8*n]; 
+		 TempB[6] = B[(6+8*m)*lda+6+8*n]; 
+		 TempB[7] = B[(6+8*m)*lda+7+8*n]; 
+		 
+		 C[0+8*n+j*lda] += TempA[6] * TempB[0];
+		 C[1+8*n+j*lda] += TempA[6] * TempB[1];
+		 C[2+8*n+j*lda] += TempA[6] * TempB[2];
+		 C[3+8*n+j*lda] += TempA[6] * TempB[3];
+		 C[4+8*n+j*lda] += TempA[6] * TempB[4];
+		 C[5+8*n+j*lda] += TempA[6] * TempB[5];
+		 C[6+8*n+j*lda] += TempA[6] * TempB[6];
+		 C[7+8*n+j*lda] += TempA[6] * TempB[7];
+
+
+		 TempB[0] = B[(7+8*m)*lda+0+8*n]; 
+		 TempB[1] = B[(7+8*m)*lda+1+8*n]; 
+		 TempB[2] = B[(7+8*m)*lda+2+8*n]; 
+		 TempB[3] = B[(7+8*m)*lda+3+8*n]; 
+		 TempB[4] = B[(7+8*m)*lda+4+8*n]; 
+		 TempB[5] = B[(7+8*m)*lda+5+8*n]; 
+		 TempB[6] = B[(7+8*m)*lda+6+8*n]; 
+		 TempB[7] = B[(7+8*m)*lda+7+8*n]; 
+		 
+		 C[0+8*n+j*lda] += TempA[7] * TempB[0];
+		 C[1+8*n+j*lda] += TempA[7] * TempB[1];
+		 C[2+8*n+j*lda] += TempA[7] * TempB[2];
+		 C[3+8*n+j*lda] += TempA[7] * TempB[3];
+		 C[4+8*n+j*lda] += TempA[7] * TempB[4];
+		 C[5+8*n+j*lda] += TempA[7] * TempB[5];
+		 C[6+8*n+j*lda] += TempA[7] * TempB[6];
+		 C[7+8*n+j*lda] += TempA[7] * TempB[7];
+		}
+
+      }
+	 }
+	}
+	if(coreid ==0)
+		{
+	for ( j = 0; j < 16; j++ )
+     {		
+		  
+      for ( m = 0; m < 4; m++ )  
+      {
+		  
+		 TempA[0] = A[j*lda+0+8*m];
+		 TempA[1] = A[j*lda+1+8*m];
+		 TempA[2] = A[j*lda+2+8*m];
+		 TempA[3] = A[j*lda+3+8*m];
+		 TempA[4] = A[j*lda+4+8*m];
+		 TempA[5] = A[j*lda+5+8*m];
+		 TempA[6] = A[j*lda+6+8*m];
+		 TempA[7] = A[j*lda+7+8*m];
+		 
+		for( n = 0; n < 4; n++)
+		{
+		 TempB[0] = B[(0+8*m)*lda+0+8*n]; 
+		 TempB[1] = B[(0+8*m)*lda+1+8*n]; 
+		 TempB[2] = B[(0+8*m)*lda+2+8*n]; 
+		 TempB[3] = B[(0+8*m)*lda+3+8*n]; 
+		 TempB[4] = B[(0+8*m)*lda+4+8*n]; 
+		 TempB[5] = B[(0+8*m)*lda+5+8*n]; 
+		 TempB[6] = B[(0+8*m)*lda+6+8*n]; 
+		 TempB[7] = B[(0+8*m)*lda+7+8*n]; 
+		 
+		 C[0+8*n+j*lda] += TempA[0] * TempB[0];
+		 C[1+8*n+j*lda] += TempA[0] * TempB[1];
+		 C[2+8*n+j*lda] += TempA[0] * TempB[2];
+		 C[3+8*n+j*lda] += TempA[0] * TempB[3];
+		 C[4+8*n+j*lda] += TempA[0] * TempB[4];
+		 C[5+8*n+j*lda] += TempA[0] * TempB[5];
+		 C[6+8*n+j*lda] += TempA[0] * TempB[6];
+		 C[7+8*n+j*lda] += TempA[0] * TempB[7];
+		 
+
+
+		 TempB[0] = B[(1+8*m)*lda+0+8*n]; 
+		 TempB[1] = B[(1+8*m)*lda+1+8*n]; 
+		 TempB[2] = B[(1+8*m)*lda+2+8*n]; 
+		 TempB[3] = B[(1+8*m)*lda+3+8*n]; 
+		 TempB[4] = B[(1+8*m)*lda+4+8*n]; 
+		 TempB[5] = B[(1+8*m)*lda+5+8*n]; 
+		 TempB[6] = B[(1+8*m)*lda+6+8*n]; 
+		 TempB[7] = B[(1+8*m)*lda+7+8*n]; 
+		 
+		 C[0+8*n+j*lda] += TempA[1] * TempB[0];
+		 C[1+8*n+j*lda] += TempA[1] * TempB[1];
+		 C[2+8*n+j*lda] += TempA[1] * TempB[2];
+		 C[3+8*n+j*lda] += TempA[1] * TempB[3];
+		 C[4+8*n+j*lda] += TempA[1] * TempB[4];
+		 C[5+8*n+j*lda] += TempA[1] * TempB[5];
+		 C[6+8*n+j*lda] += TempA[1] * TempB[6];
+		 C[7+8*n+j*lda] += TempA[1] * TempB[7];
+		 
+
+
+		 TempB[0] = B[(2+8*m)*lda+0+8*n]; 
+		 TempB[1] = B[(2+8*m)*lda+1+8*n]; 
+		 TempB[2] = B[(2+8*m)*lda+2+8*n]; 
+		 TempB[3] = B[(2+8*m)*lda+3+8*n]; 
+		 TempB[4] = B[(2+8*m)*lda+4+8*n]; 
+		 TempB[5] = B[(2+8*m)*lda+5+8*n]; 
+		 TempB[6] = B[(2+8*m)*lda+6+8*n]; 
+		 TempB[7] = B[(2+8*m)*lda+7+8*n]; 
+		 
+		 C[0+8*n+j*lda] += TempA[2] * TempB[0];
+		 C[1+8*n+j*lda] += TempA[2] * TempB[1];
+		 C[2+8*n+j*lda] += TempA[2] * TempB[2];
+		 C[3+8*n+j*lda] += TempA[2] * TempB[3];
+		 C[4+8*n+j*lda] += TempA[2] * TempB[4];
+		 C[5+8*n+j*lda] += TempA[2] * TempB[5];
+		 C[6+8*n+j*lda] += TempA[2] * TempB[6];
+		 C[7+8*n+j*lda] += TempA[2] * TempB[7];
+		 
+
+
+		 TempB[0] = B[(3+8*m)*lda+0+8*n]; 
+		 TempB[1] = B[(3+8*m)*lda+1+8*n]; 
+		 TempB[2] = B[(3+8*m)*lda+2+8*n]; 
+		 TempB[3] = B[(3+8*m)*lda+3+8*n]; 
+		 TempB[4] = B[(3+8*m)*lda+4+8*n]; 
+		 TempB[5] = B[(3+8*m)*lda+5+8*n]; 
+		 TempB[6] = B[(3+8*m)*lda+6+8*n]; 
+		 TempB[7] = B[(3+8*m)*lda+7+8*n]; 
+		 
+		 C[0+8*n+j*lda] += TempA[3] * TempB[0];
+		 C[1+8*n+j*lda] += TempA[3] * TempB[1];
+		 C[2+8*n+j*lda] += TempA[3] * TempB[2];
+		 C[3+8*n+j*lda] += TempA[3] * TempB[3];
+		 C[4+8*n+j*lda] += TempA[3] * TempB[4];
+		 C[5+8*n+j*lda] += TempA[3] * TempB[5];
+		 C[6+8*n+j*lda] += TempA[3] * TempB[6];
+		 C[7+8*n+j*lda] += TempA[3] * TempB[7];
+
+
+		 TempB[0] = B[(4+8*m)*lda+0+8*n]; 
+		 TempB[1] = B[(4+8*m)*lda+1+8*n]; 
+		 TempB[2] = B[(4+8*m)*lda+2+8*n]; 
+		 TempB[3] = B[(4+8*m)*lda+3+8*n]; 
+		 TempB[4] = B[(4+8*m)*lda+4+8*n]; 
+		 TempB[5] = B[(4+8*m)*lda+5+8*n]; 
+		 TempB[6] = B[(4+8*m)*lda+6+8*n]; 
+		 TempB[7] = B[(4+8*m)*lda+7+8*n]; 
+		 
+		 C[0+8*n+j*lda] += TempA[4] * TempB[0];
+		 C[1+8*n+j*lda] += TempA[4] * TempB[1];
+		 C[2+8*n+j*lda] += TempA[4] * TempB[2];
+		 C[3+8*n+j*lda] += TempA[4] * TempB[3];
+		 C[4+8*n+j*lda] += TempA[4] * TempB[4];
+		 C[5+8*n+j*lda] += TempA[4] * TempB[5];
+		 C[6+8*n+j*lda] += TempA[4] * TempB[6];
+		 C[7+8*n+j*lda] += TempA[4] * TempB[7];
+		 
+
+
+		 TempB[0] = B[(5+8*m)*lda+0+8*n]; 
+		 TempB[1] = B[(5+8*m)*lda+1+8*n]; 
+		 TempB[2] = B[(5+8*m)*lda+2+8*n]; 
+		 TempB[3] = B[(5+8*m)*lda+3+8*n]; 
+		 TempB[4] = B[(5+8*m)*lda+4+8*n]; 
+		 TempB[5] = B[(5+8*m)*lda+5+8*n]; 
+		 TempB[6] = B[(5+8*m)*lda+6+8*n]; 
+		 TempB[7] = B[(5+8*m)*lda+7+8*n]; 
+		 
+		 C[0+8*n+j*lda] += TempA[5] * TempB[0];
+		 C[1+8*n+j*lda] += TempA[5] * TempB[1];
+		 C[2+8*n+j*lda] += TempA[5] * TempB[2];
+		 C[3+8*n+j*lda] += TempA[5] * TempB[3];
+		 C[4+8*n+j*lda] += TempA[5] * TempB[4];
+		 C[5+8*n+j*lda] += TempA[5] * TempB[5];
+		 C[6+8*n+j*lda] += TempA[5] * TempB[6];
+		 C[7+8*n+j*lda] += TempA[5] * TempB[7];
+		 
+
+
+		 TempB[0] = B[(6+8*m)*lda+0+8*n]; 
+		 TempB[1] = B[(6+8*m)*lda+1+8*n]; 
+		 TempB[2] = B[(6+8*m)*lda+2+8*n]; 
+		 TempB[3] = B[(6+8*m)*lda+3+8*n]; 
+		 TempB[4] = B[(6+8*m)*lda+4+8*n]; 
+		 TempB[5] = B[(6+8*m)*lda+5+8*n]; 
+		 TempB[6] = B[(6+8*m)*lda+6+8*n]; 
+		 TempB[7] = B[(6+8*m)*lda+7+8*n]; 
+		 
+		 C[0+8*n+j*lda] += TempA[6] * TempB[0];
+		 C[1+8*n+j*lda] += TempA[6] * TempB[1];
+		 C[2+8*n+j*lda] += TempA[6] * TempB[2];
+		 C[3+8*n+j*lda] += TempA[6] * TempB[3];
+		 C[4+8*n+j*lda] += TempA[6] * TempB[4];
+		 C[5+8*n+j*lda] += TempA[6] * TempB[5];
+		 C[6+8*n+j*lda] += TempA[6] * TempB[6];
+		 C[7+8*n+j*lda] += TempA[6] * TempB[7];
+
+
+		 TempB[0] = B[(7+8*m)*lda+0+8*n]; 
+		 TempB[1] = B[(7+8*m)*lda+1+8*n]; 
+		 TempB[2] = B[(7+8*m)*lda+2+8*n]; 
+		 TempB[3] = B[(7+8*m)*lda+3+8*n]; 
+		 TempB[4] = B[(7+8*m)*lda+4+8*n]; 
+		 TempB[5] = B[(7+8*m)*lda+5+8*n]; 
+		 TempB[6] = B[(7+8*m)*lda+6+8*n]; 
+		 TempB[7] = B[(7+8*m)*lda+7+8*n]; 
+		 
+		 C[0+8*n+j*lda] += TempA[7] * TempB[0];
+		 C[1+8*n+j*lda] += TempA[7] * TempB[1];
+		 C[2+8*n+j*lda] += TempA[7] * TempB[2];
+		 C[3+8*n+j*lda] += TempA[7] * TempB[3];
+		 C[4+8*n+j*lda] += TempA[7] * TempB[4];
+		 C[5+8*n+j*lda] += TempA[7] * TempB[5];
+		 C[6+8*n+j*lda] += TempA[7] * TempB[6];
+		 C[7+8*n+j*lda] += TempA[7] * TempB[7];
+		}
+
+      }
+	 }
+	}
+
+	
+}
diff --git a/apps/riscv-tests/mt/cy_matmul.c b/apps/riscv-tests/mt/cy_matmul.c
new file mode 100644
index 0000000..b0713cd
--- /dev/null
+++ b/apps/riscv-tests/mt/cy_matmul.c
@@ -0,0 +1,108 @@
+#include "stdlib.h"
+
+#include "util.h"
+
+#include "dataset.h"
+void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda,  const data_t A[], const data_t B[], data_t C[] )
+{
+   if(coreid > 1) return; 
+  static __thread int i, j, k;
+  static __thread data_t tempA0, tempA1, tempA2, tempA3, tempA4, tempA5, tempA6, tempA7;
+  static __thread data_t tempC0, tempC1, tempC2, tempC3, tempC4, tempC5, tempC6, tempC7, tempC8, tempC9, tempC10, tempC11, tempC12, tempC13, tempC14, tempC15;
+
+  static __thread int start, end, jStride, jToRow, jToCol;
+  static data_t A1[1024], B1[1024];;
+  
+  start = coreid << 9;
+  end = ((ncores == 1) ? 2 :(coreid+1)) << 9;
+  jStride = 8;
+
+  if (coreid == 0) { 
+    for (j=start; j < end; j+=jStride) {
+      jToRow = (j>>5)<<5;
+      jToCol = j%32;
+      tempC0  = 0;
+      tempC1  = 0;
+      tempC2  = 0;
+      tempC3  = 0;
+      tempC4  = 0;
+      tempC5  = 0;
+      tempC6  = 0;
+      tempC7  = 0;
+      for ( i=0; i < lda; i+=2 ) {
+        tempA0 = A[i   + jToRow];
+        tempA1 = A[i+1 + jToRow];
+        tempC0  += tempA0 * B[(jToCol   ) + (i<<5)];
+        tempC1  += tempA0 * B[(jToCol+1 ) + (i<<5)];
+        tempC2  += tempA0 * B[(jToCol+2 ) + (i<<5)];
+        tempC3  += tempA0 * B[(jToCol+3 ) + (i<<5)];
+        tempC4  += tempA0 * B[(jToCol+4 ) + (i<<5)];
+        tempC5  += tempA0 * B[(jToCol+5 ) + (i<<5)];
+        tempC6  += tempA0 * B[(jToCol+6 ) + (i<<5)];
+        tempC7  += tempA0 * B[(jToCol+7 ) + (i<<5)];
+        tempC0  += tempA1 * B[(jToCol   ) + ((i+1)<<5)];
+        tempC1  += tempA1 * B[(jToCol+1 ) + ((i+1)<<5)];
+        tempC2  += tempA1 * B[(jToCol+2 ) + ((i+1)<<5)];
+        tempC3  += tempA1 * B[(jToCol+3 ) + ((i+1)<<5)];
+        tempC4  += tempA1 * B[(jToCol+4 ) + ((i+1)<<5)];
+        tempC5  += tempA1 * B[(jToCol+5 ) + ((i+1)<<5)];
+        tempC6  += tempA1 * B[(jToCol+6 ) + ((i+1)<<5)];
+        tempC7  += tempA1 * B[(jToCol+7 ) + ((i+1)<<5)];
+      }
+      C[j] =tempC0;
+      C[j + 1 ]=tempC1;
+      C[j + 2 ]=tempC2;
+      C[j + 3 ]=tempC3;
+      C[j + 4 ]=tempC4;
+      C[j + 5 ]=tempC5;
+      C[j + 6 ]=tempC6;
+      C[j + 7 ]=tempC7;
+    }
+  }
+  else { 
+    for (i = 0; i < 1024; i++) {
+      A1[i] = A[i];
+      B1[i] = B[i];
+    }
+    for (j=start; j < end; j+=jStride) {
+      jToRow = (j>>5)<<5;
+      jToCol = j%32;
+      tempC0  = 0;
+      tempC1  = 0;
+      tempC2  = 0;
+      tempC3  = 0;
+      tempC4  = 0;
+      tempC5  = 0;
+      tempC6  = 0;
+      tempC7  = 0;
+      for ( i=0; i < lda; i+=2 ) {
+        tempA0 = A1[i   + jToRow];
+        tempA1 = A1[i+1 + jToRow];
+        tempC0  += tempA0 * B1[(jToCol   ) + (i<<5)];
+        tempC1  += tempA0 * B1[(jToCol+1 ) + (i<<5)];
+        tempC2  += tempA0 * B1[(jToCol+2 ) + (i<<5)];
+        tempC3  += tempA0 * B1[(jToCol+3 ) + (i<<5)];
+        tempC4  += tempA0 * B1[(jToCol+4 ) + (i<<5)];
+        tempC5  += tempA0 * B1[(jToCol+5 ) + (i<<5)];
+        tempC6  += tempA0 * B1[(jToCol+6 ) + (i<<5)];
+        tempC7  += tempA0 * B1[(jToCol+7 ) + (i<<5)];
+        tempC0  += tempA1 * B1[(jToCol   ) + ((i+1)<<5)];
+        tempC1  += tempA1 * B1[(jToCol+1 ) + ((i+1)<<5)];
+        tempC2  += tempA1 * B1[(jToCol+2 ) + ((i+1)<<5)];
+        tempC3  += tempA1 * B1[(jToCol+3 ) + ((i+1)<<5)];
+        tempC4  += tempA1 * B1[(jToCol+4 ) + ((i+1)<<5)];
+        tempC5  += tempA1 * B1[(jToCol+5 ) + ((i+1)<<5)];
+        tempC6  += tempA1 * B1[(jToCol+6 ) + ((i+1)<<5)];
+        tempC7  += tempA1 * B1[(jToCol+7 ) + ((i+1)<<5)];
+      }
+      C[j] =tempC0;
+      C[j + 1 ]=tempC1;
+      C[j + 2 ]=tempC2;
+      C[j + 3 ]=tempC3;
+      C[j + 4 ]=tempC4;
+      C[j + 5 ]=tempC5;
+      C[j + 6 ]=tempC6;
+      C[j + 7 ]=tempC7;
+    }
+  }
+}
diff --git a/apps/riscv-tests/mt/dc_matmul.c b/apps/riscv-tests/mt/dc_matmul.c
new file mode 100644
index 0000000..a2b583e
--- /dev/null
+++ b/apps/riscv-tests/mt/dc_matmul.c
@@ -0,0 +1,168 @@
+#include "stdlib.h"
+
+#include "util.h"
+
+#include "dataset.h"
+
+#define REG_I 8
+#define REG_J 2
+#define BLOCK_I 32
+#define BLOCK_J 16
+#define BLOCK_K 16
+#define LDA 32
+#define NCORES 2
+#define MIN(X,Y) (X < Y ? X : Y)
+
+void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda,  const data_t A[], const data_t B[], data_t C[] )
+{
+   
+   // ***************************** //
+   // **** ADD YOUR CODE HERE ***** //
+   // ***************************** //
+   //
+   // feel free to make a separate function for MI and MSI versions.
+
+  int i, j, k, ri, rj, ii, jj, kk;
+  data_t *Aj, *Cj, *Bi;
+  data_t c[REG_I][REG_J], a[REG_J], b[REG_I];
+  size_t start = coreid * (LDA / NCORES), end = (coreid == NCORES - 1 ? LDA : (coreid + 1) * (LDA / NCORES));
+     
+  /* if (coreid > 0) { */
+  /*   return; */
+  /* } */
+  /* start = 0, end = lda; */
+  if (ncores == NCORES && lda == LDA) {
+    for (jj = start; jj < end; jj += BLOCK_J) {
+      int kk_start= (coreid == 0 ? 0 : LDA/2) ,kk_end = (coreid == 0 ? LDA/2 : LDA);
+      for (kk = kk_start; kk < kk_end; kk += BLOCK_K) {
+	//  for (ii = 0; ii < LDA; ii += BLOCK_I)
+	for (j = jj; j < MIN(end, jj + BLOCK_J); j += REG_J) {
+	  Aj = A + j*LDA;
+	  Cj = C + j*LDA;
+	  for (i = 0; i < LDA/*, ii + BLOCK_I)*/; i += REG_I) {
+	    /* Load C in register blocks. */
+	    Bi = B + i;
+	    for (ri = 0; ri < REG_I; ri++) {
+	      for (rj = 0; rj < REG_J; rj++) {
+		c[ri][rj] = Cj[i + ri + ( rj)*LDA];
+	      }
+	    }
+	    
+	    
+	    for (k = kk; k < MIN(LDA, kk + BLOCK_K); k++) {
+	      for (ri = 0; ri < REG_I; ri++) {
+		b[ri] = Bi[k*LDA  + ri];
+	      }
+	      /* Compute C in register blocks. */
+	      for (rj = 0; rj < REG_J; rj++) {
+		a[rj] = Aj[(rj)*LDA + k];
+		for (ri = 0; ri < REG_I; ri++) {
+		  c[ri][rj] += a[rj] * b[ri];
+		}
+	      }
+	    }
+	    
+	    /* store C in register blocks. */
+	    for (ri = 0; ri < REG_I; ri++) {
+	      for (rj = 0; rj < REG_J; rj++) {
+		Cj[i + ri + ( rj)*LDA] = c[ri][rj];
+	      }
+	    }
+	  }
+	}
+	/* barrier(nc); */
+
+	/* kk_start= (coreid == 1 ? 0 : LDA/2); */
+	/* kk_end = (coreid == 1 ? LDA/2 : LDA); */
+	/* for (kk = kk_start; kk < kk_end; kk += BLOCK_K) { */
+	/* //  for (ii = 0; ii < LDA; ii += BLOCK_I) */
+	/* for (j = jj; j < MIN(end, jj + BLOCK_J); j += REG_J) { */
+	/*   Aj = A + j*LDA; */
+	/*   Cj = C + j*LDA; */
+	/*   for (i = 0; i < LDA/\*, ii + BLOCK_I)*\/; i += REG_I) { */
+	/*     /\* Load C in register blocks. *\/ */
+	/*     Bi = B + i; */
+	/*     for (ri = 0; ri < REG_I; ri++) { */
+	/*       for (rj = 0; rj < REG_J; rj++) { */
+	/* 	c[ri][rj] = Cj[i + ri + ( rj)*LDA]; */
+	/*       } */
+	/*     } */
+	    
+	    
+	/*     for (k = kk; k < MIN(LDA, kk + BLOCK_K); k++) { */
+	/*       for (ri = 0; ri < REG_I; ri++) { */
+	/* 	b[ri] = Bi[k*LDA  + ri]; */
+	/*       } */
+	/*       /\* Compute C in register blocks. *\/ */
+	/*       for (rj = 0; rj < REG_J; rj++) { */
+	/* 	a[rj] = Aj[(rj)*LDA + k]; */
+	/* 	for (ri = 0; ri < REG_I; ri++) { */
+	/* 	  c[ri][rj] += a[rj] * b[ri]; */
+	/* 	} */
+	/*       } */
+	/*     } */
+	      
+	    /* store C in register blocks. */
+	/*     for (ri = 0; ri < REG_I; ri++) { */
+    /* 	      for (rj = 0; rj < REG_J; rj++) { */
+    /* 		Cj[i + ri + ( rj)*LDA] = c[ri][rj]; */
+    /* 	      } */
+    /* 	    } */
+    /*   } */
+    /* } */
+      }
+    }
+  
+    
+    //barrier(nc);
+    for (jj = start; jj < end; jj += BLOCK_J) {
+      int kk_start= (coreid != 0 ? 0 : LDA/2), kk_end = (coreid != 0 ? LDA/2 : LDA);
+      for (kk = kk_start; kk < kk_end; kk += BLOCK_K) {
+    	//  for (ii = 0; ii < LDA; ii += BLOCK_I)
+    	for (j = jj; j < MIN(end, jj + BLOCK_J); j += REG_J) {
+    	  Aj = A + j*LDA;
+    	  Cj = C + j*LDA;
+    	  for (i = 0; i < LDA/*, ii + BLOCK_I)*/; i += REG_I) {
+    	    /* Load C in register blocks. */
+    	    Bi = B + i;
+    	    for (ri = 0; ri < REG_I; ri++) {
+    	      for (rj = 0; rj < REG_J; rj++) {
+    		c[ri][rj] = Cj[i + ri + ( rj)*LDA];
+    	      }
+    	    }
+	    
+	    
+    	    for (k = kk; k < MIN(LDA, kk + BLOCK_K); k++) {
+    	      for (ri = 0; ri < REG_I; ri++) {
+    		b[ri] = Bi[k*LDA  + ri];
+    	      }
+    	      /* Compute C in register blocks. */
+    	      for (rj = 0; rj < REG_J; rj++) {
+    		a[rj] = Aj[(rj)*LDA + k];
+    		for (ri = 0; ri < REG_I; ri++) {
+    		  c[ri][rj] += a[rj] * b[ri];
+    		}
+    	      }
+    	    }
+	    
+    	      /* store C in register blocks. */
+    	    for (ri = 0; ri < REG_I; ri++) {
+    	      for (rj = 0; rj < REG_J; rj++) {
+    		Cj[i + ri + ( rj)*LDA] = c[ri][rj];
+    	      }
+    	    }
+    	  }
+    	}
+      }
+    }
+    /* We only care about performance for 32x32 matrices and 2 cores. Otherwise just naive mat_mul */
+} else {
+      if (coreid > 0)
+	return;
+      
+      for ( i = 0; i < lda; i++ )
+	for ( j = 0; j < lda; j++ )  
+	  for ( k = 0; k < lda; k++ ) 
+	    C[i + j*lda] += A[j*lda + k] * B[k*lda + i];
+    }
+  }
diff --git a/apps/riscv-tests/mt/df_matmul.c b/apps/riscv-tests/mt/df_matmul.c
new file mode 100644
index 0000000..56d9c4b
--- /dev/null
+++ b/apps/riscv-tests/mt/df_matmul.c
@@ -0,0 +1,237 @@
+#include "stdlib.h"
+
+#include "util.h"
+
+#include "dataset.h"
+void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda,  const data_t A[], const data_t B[], data_t C[] )
+{
+   
+   // ***************************** //
+   // **** ADD YOUR CODE HERE ***** //
+   // ***************************** //
+   //
+   // feel free to make a separate function for MI and MSI versions.
+   int j, k;
+   data_t temp0, temp1, temp2, temp3, temp4, temp5, temp6, temp7;
+   data_t temp8, temp9, temp10, temp11, temp12, temp13, temp14, temp15;
+   if(coreid == 0) {
+      //16*0:16*(0+1) ;; 16*1+16*(1+1)
+      //0:16 ;; 16:32
+
+      //complete Q1
+      for(j = 0; j < 16; j++) {
+         temp0  = C[j*lda];
+         temp1  = C[1  + j*lda];
+         temp2  = C[2  + j*lda];
+         temp3  = C[3  + j*lda];
+         temp4  = C[4  + j*lda];
+         temp5  = C[5  + j*lda];
+         temp6  = C[6  + j*lda];
+         temp7  = C[7  + j*lda];
+         temp8  = C[8  + j*lda];
+         temp9  = C[9  + j*lda];
+         temp10 = C[10 + j*lda];
+         temp11 = C[11 + j*lda];
+         temp12 = C[12 + j*lda];
+         temp13 = C[13 + j*lda];
+         temp14 = C[14 + j*lda];
+         temp15 = C[15 + j*lda];
+         for(k = 0; k < 32; k++) {
+            temp0  += A[j*lda + k] * B[k*lda];
+            temp1  += A[j*lda + k] * B[1+k*lda];
+            temp2  += A[j*lda + k] * B[2+k*lda];
+            temp3  += A[j*lda + k] * B[3+k*lda];
+            temp4  += A[j*lda + k] * B[4+k*lda];
+            temp5  += A[j*lda + k] * B[5+k*lda];
+            temp6  += A[j*lda + k] * B[6+k*lda];
+            temp7  += A[j*lda + k] * B[7+k*lda];
+            temp8  += A[j*lda + k] * B[8+k*lda];
+            temp9  += A[j*lda + k] * B[9+k*lda];
+            temp10 += A[j*lda + k] * B[10+k*lda];
+            temp11 += A[j*lda + k] * B[11+k*lda];
+            temp12 += A[j*lda + k] * B[12+k*lda];
+            temp13 += A[j*lda + k] * B[13+k*lda];
+            temp14 += A[j*lda + k] * B[14+k*lda];
+            temp15 += A[j*lda + k] * B[15+k*lda];
+         }
+         C[j*lda] = temp0;
+         C[1  + j*lda] = temp1;
+         C[2  + j*lda] = temp2;
+         C[3  + j*lda] = temp3;
+         C[4  + j*lda] = temp4;
+         C[5  + j*lda] = temp5;
+         C[6  + j*lda] = temp6;
+         C[7  + j*lda] = temp7;
+         C[8  + j*lda] = temp8;
+         C[9  + j*lda] = temp9;
+         C[10 + j*lda] = temp10;
+         C[11 + j*lda] = temp11;
+         C[12 + j*lda] = temp12;
+         C[13 + j*lda] = temp13;
+         C[14 + j*lda] = temp14;
+         C[15 + j*lda] = temp15;
+      }
+      for(j = 16; j < 32; j++) {
+         temp0  = C[j*lda];
+         temp1  = C[1  + j*lda];
+         temp2  = C[2  + j*lda];
+         temp3  = C[3  + j*lda];
+         temp4  = C[4  + j*lda];
+         temp5  = C[5  + j*lda];
+         temp6  = C[6  + j*lda];
+         temp7  = C[7  + j*lda];
+         temp8  = C[8  + j*lda];
+         temp9  = C[9  + j*lda];
+         temp10 = C[10 + j*lda];
+         temp11 = C[11 + j*lda];
+         temp12 = C[12 + j*lda];
+         temp13 = C[13 + j*lda];
+         temp14 = C[14 + j*lda];
+         temp15 = C[15 + j*lda];
+         for(k = 0; k < 32; k++) {
+            temp0  += A[j*lda + k] * B[k*lda];
+            temp1  += A[j*lda + k] * B[1+k*lda];
+            temp2  += A[j*lda + k] * B[2+k*lda];
+            temp3  += A[j*lda + k] * B[3+k*lda];
+            temp4  += A[j*lda + k] * B[4+k*lda];
+            temp5  += A[j*lda + k] * B[5+k*lda];
+            temp6  += A[j*lda + k] * B[6+k*lda];
+            temp7  += A[j*lda + k] * B[7+k*lda];
+            temp8  += A[j*lda + k] * B[8+k*lda];
+            temp9  += A[j*lda + k] * B[9+k*lda];
+            temp10 += A[j*lda + k] * B[10+k*lda];
+            temp11 += A[j*lda + k] * B[11+k*lda];
+            temp12 += A[j*lda + k] * B[12+k*lda];
+            temp13 += A[j*lda + k] * B[13+k*lda];
+            temp14 += A[j*lda + k] * B[14+k*lda];
+            temp15 += A[j*lda + k] * B[15+k*lda];
+         }
+         C[j*lda] = temp0;
+         C[1  + j*lda] = temp1;
+         C[2  + j*lda] = temp2;
+         C[3  + j*lda] = temp3;
+         C[4  + j*lda] = temp4;
+         C[5  + j*lda] = temp5;
+         C[6  + j*lda] = temp6;
+         C[7  + j*lda] = temp7;
+         C[8  + j*lda] = temp8;
+         C[9  + j*lda] = temp9;
+         C[10 + j*lda] = temp10;
+         C[11 + j*lda] = temp11;
+         C[12 + j*lda] = temp12;
+         C[13 + j*lda] = temp13;
+         C[14 + j*lda] = temp14;
+         C[15 + j*lda] = temp15;
+      }
+   }
+   //16*(2-1) : 16*2 ;; 16*(1-1) : 16*1
+   //16:32 ;; 0:16 
+   if(coreid == 1 || ncores == 1)   {
+         //complete Q3
+      for(j = 16; j < 32; j++) {
+         temp0  = C[16+j*lda];
+         temp1  = C[17+j*lda];
+         temp2  = C[18+j*lda];
+         temp3  = C[19+j*lda];
+         temp4  = C[20+j*lda];
+         temp5  = C[21+j*lda];
+         temp6  = C[22+j*lda];
+         temp7  = C[23+j*lda];
+         temp8  = C[24+j*lda];
+         temp9  = C[25+j*lda];
+         temp10 = C[26+j*lda];
+         temp11 = C[27+j*lda];
+         temp12 = C[28+j*lda];
+         temp13 = C[29+j*lda];
+         temp14 = C[30+j*lda];
+         temp15 = C[31+j*lda];
+         for(k = 0; k < 32; k++) {
+            temp0  += A[j*lda + k] * B[16+k*lda];
+            temp1  += A[j*lda + k] * B[17+k*lda];
+            temp2  += A[j*lda + k] * B[18+k*lda];
+            temp3  += A[j*lda + k] * B[19+k*lda];
+            temp4  += A[j*lda + k] * B[20+k*lda];
+            temp5  += A[j*lda + k] * B[21+k*lda];
+            temp6  += A[j*lda + k] * B[22+k*lda];
+            temp7  += A[j*lda + k] * B[23+k*lda];
+            temp8  += A[j*lda + k] * B[24+k*lda];
+            temp9  += A[j*lda + k] * B[25+k*lda];
+            temp10 += A[j*lda + k] * B[26+k*lda];
+            temp11 += A[j*lda + k] * B[27+k*lda];
+            temp12 += A[j*lda + k] * B[28+k*lda];
+            temp13 += A[j*lda + k] * B[29+k*lda];
+            temp14 += A[j*lda + k] * B[30+k*lda];
+            temp15 += A[j*lda + k] * B[31+k*lda];
+         }
+         C[16 + j*lda] = temp0;
+         C[17 + j*lda] = temp1;
+         C[18 + j*lda] = temp2;
+         C[19 + j*lda] = temp3;
+         C[20 + j*lda] = temp4;
+         C[21 + j*lda] = temp5;
+         C[22 + j*lda] = temp6;
+         C[23 + j*lda] = temp7;
+         C[24 + j*lda] = temp8;
+         C[25 + j*lda] = temp9;
+         C[26 + j*lda] = temp10;
+         C[27 + j*lda] = temp11;
+         C[28 + j*lda] = temp12;
+         C[29 + j*lda] = temp13;
+         C[30 + j*lda] = temp14;
+         C[31 + j*lda] = temp15;
+      }
+      //complete Q4
+      for(j = 0; j < 16; j++) {
+         temp0  = C[16 + j*lda];
+         temp1  = C[17 + j*lda];
+         temp2  = C[18 + j*lda];
+         temp3  = C[19 + j*lda];
+         temp4  = C[20 + j*lda];
+         temp5  = C[21 + j*lda];
+         temp6  = C[22 + j*lda];
+         temp7  = C[23 + j*lda];
+         temp8  = C[24 + j*lda];
+         temp9  = C[25 + j*lda];
+         temp10 = C[26 + j*lda];
+         temp11 = C[27 + j*lda];
+         temp12 = C[28 + j*lda];
+         temp13 = C[29 + j*lda];
+         temp14 = C[30 + j*lda];
+         temp15 = C[31 + j*lda];
+         for(k = 0; k < 32; k++) {
+            temp0  += A[j*lda + k] * B[16 + k*lda];
+            temp1  += A[j*lda + k] * B[17 + k*lda];
+            temp2  += A[j*lda + k] * B[18 + k*lda];
+            temp3  += A[j*lda + k] * B[19 + k*lda];
+            temp4  += A[j*lda + k] * B[20 + k*lda];
+            temp5  += A[j*lda + k] * B[21 + k*lda];
+            temp6  += A[j*lda + k] * B[22 + k*lda];
+            temp7  += A[j*lda + k] * B[23 + k*lda];
+            temp8  += A[j*lda + k] * B[24 + k*lda];
+            temp9  += A[j*lda + k] * B[25 + k*lda];
+            temp10 += A[j*lda + k] * B[26 + k*lda];
+            temp11 += A[j*lda + k] * B[27 + k*lda];
+            temp12 += A[j*lda + k] * B[28 + k*lda];
+            temp13 += A[j*lda + k] * B[29 + k*lda];
+            temp14 += A[j*lda + k] * B[30 + k*lda];
+            temp15 += A[j*lda + k] * B[31 + k*lda];
+         }
+         C[16 + j*lda] = temp0;
+         C[17 + j*lda] = temp1;
+         C[18 + j*lda] = temp2;
+         C[19 + j*lda] = temp3;
+         C[20 + j*lda] = temp4;
+         C[21 + j*lda] = temp5;
+         C[22 + j*lda] = temp6;
+         C[23 + j*lda] = temp7;
+         C[24 + j*lda] = temp8;
+         C[25 + j*lda] = temp9;
+         C[26 + j*lda] = temp10;
+         C[27 + j*lda] = temp11;
+         C[28 + j*lda] = temp12;
+         C[29 + j*lda] = temp13;
+         C[30 + j*lda] = temp14;
+         C[31 + j*lda] = temp15;
+      }
+   }
+}
diff --git a/apps/riscv-tests/mt/dm_matmul.c b/apps/riscv-tests/mt/dm_matmul.c
new file mode 100644
index 0000000..1a777d9
--- /dev/null
+++ b/apps/riscv-tests/mt/dm_matmul.c
@@ -0,0 +1,196 @@
+#include "stdlib.h"
+
+#include "util.h"
+
+#include "dataset.h"
+void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda,  const data_t A[], const data_t B[], data_t C[] )
+{
+   
+   // ***************************** //
+   // **** ADD YOUR CODE HERE ***** //
+   // ***************************** //
+   //
+   // feel free to make a separate function for MI and MSI versions.
+	int i, j, k;
+    int space=lda/ncores;
+    int max= space*coreid+space;
+	static data_t B1[32*32];
+	if (coreid==ncores-1){	
+		for (i=0; i<lda*lda/ncores;i++)
+		{
+			B1[i]=B[i];
+		}
+	}
+	else{
+		for (i=lda*lda/ncores;i<lda*lda;i++)
+			B1[i]=B[i];	
+	}
+	data_t temp=0;
+	data_t temp1=0;
+	data_t temp2=0;
+	data_t temp3=0;
+	data_t tempB=0;
+
+	data_t temp_1=0;
+	data_t temp1_1=0;
+	data_t temp2_1=0;
+	data_t temp3_1=0;
+	data_t tempB_1=0;
+
+	data_t temp_2=0;
+	data_t temp1_2=0;
+	data_t temp2_2=0;
+	data_t temp3_2=0;
+	data_t tempB_2=0;
+
+	data_t temp_3=0;
+	data_t temp1_3=0;
+	data_t temp2_3=0;
+	data_t temp3_3=0;
+	data_t tempB_3=0;
+	barrier(ncores);
+	if (coreid!=ncores-1){
+		for (i=space*coreid;i<max/4*4;i+=4)
+		{
+			for(j=0;j<lda/4*4;j+=4)
+			{
+				temp=C[j+i*lda];
+				temp1=C[j+(i+1)*lda];
+				temp2=C[j+(i+2)*lda];
+				temp3=C[j+(i+3)*lda];
+				temp_1=C[j+1+i*lda];
+				temp1_1=C[j+1+(i+1)*lda];
+				temp2_1=C[j+1+(i+2)*lda];
+				temp3_1=C[j+1+(i+3)*lda];
+				temp_2=C[j+2+i*lda];
+				temp1_2=C[j+2+(i+1)*lda];
+				temp2_2=C[j+2+(i+2)*lda];
+				temp3_2=C[j+2+(i+3)*lda];
+				temp_3=C[j+3+i*lda];
+				temp1_3=C[j+3+(i+1)*lda];
+				temp2_3=C[j+3+(i+2)*lda];
+				temp3_3=C[j+3+(i+3)*lda];
+				for (k=0;k<lda;k++)
+				{
+					tempB=B[j+k*lda];
+					temp+=A[k+i*lda]*tempB;	
+					temp1+=A[k+(i+1)*lda]*tempB;
+					temp2+=A[k+(i+2)*lda]*tempB;
+					temp3+=A[k+(i+3)*lda]*tempB;
+					
+					tempB_1=B[j+1+k*lda];
+					temp_1+=A[k+i*lda]*tempB_1;	
+					temp1_1+=A[k+(i+1)*lda]*tempB_1;
+					temp2_1+=A[k+(i+2)*lda]*tempB_1;
+					temp3_1+=A[k+(i+3)*lda]*tempB_1;
+				
+					tempB_2=B[j+2+k*lda];
+					temp_2+=A[k+i*lda]*tempB_2;	
+					temp1_2+=A[k+(i+1)*lda]*tempB_2;
+					temp2_2+=A[k+(i+2)*lda]*tempB_2;
+					temp3_2+=A[k+(i+3)*lda]*tempB_2;
+				
+					tempB_3=B[j+3+k*lda];
+					temp_3+=A[k+i*lda]*tempB_3;	
+					temp1_3+=A[k+(i+1)*lda]*tempB_3;
+					temp2_3+=A[k+(i+2)*lda]*tempB_3;
+					temp3_3+=A[k+(i+3)*lda]*tempB_3;
+				}
+				C[j+i*lda]=temp;
+				C[j+(i+1)*lda]=temp1;
+				C[j+(i+2)*lda]=temp2;
+				C[j+(i+3)*lda]=temp3;
+				
+				C[j+1+i*lda]=temp_1;
+				C[j+1+(i+1)*lda]=temp1_1;
+				C[j+1+(i+2)*lda]=temp2_1;
+				C[j+1+(i+3)*lda]=temp3_1;
+				
+				C[j+2+i*lda]=temp_2;
+				C[j+2+(i+1)*lda]=temp1_2;
+				C[j+2+(i+2)*lda]=temp2_2;
+				C[j+2+(i+3)*lda]=temp3_2;
+
+				C[j+3+i*lda]=temp_3;
+				C[j+3+(i+1)*lda]=temp1_3;
+				C[j+3+(i+2)*lda]=temp2_3;
+				C[j+3+(i+3)*lda]=temp3_3;
+				
+			}
+		}
+	}
+	else{
+		for (i=space*coreid;i<lda/4*4;i+=4)
+		{
+			for(j=0;j<lda/4*4;j+=4)
+			{
+				temp=C[j+i*lda];
+				temp1=C[j+(i+1)*lda];
+				temp2=C[j+(i+2)*lda];
+				temp3=C[j+(i+3)*lda];
+				temp_1=C[j+1+i*lda];
+				temp1_1=C[j+1+(i+1)*lda];
+				temp2_1=C[j+1+(i+2)*lda];
+				temp3_1=C[j+1+(i+3)*lda];
+				temp_2=C[j+2+i*lda];
+				temp1_2=C[j+2+(i+1)*lda];
+				temp2_2=C[j+2+(i+2)*lda];
+				temp3_2=C[j+2+(i+3)*lda];
+				temp_3=C[j+3+i*lda];
+				temp1_3=C[j+3+(i+1)*lda];
+				temp2_3=C[j+3+(i+2)*lda];
+				temp3_3=C[j+3+(i+3)*lda];
+				for (k=0;k<lda;k++)
+				{
+					tempB=B1[j+k*lda];
+					temp+=A[k+i*lda]*tempB;	
+					temp1+=A[k+(i+1)*lda]*tempB;
+					temp2+=A[k+(i+2)*lda]*tempB;
+					temp3+=A[k+(i+3)*lda]*tempB;
+					
+					tempB_1=B1[j+1+k*lda];
+					temp_1+=A[k+i*lda]*tempB_1;	
+					temp1_1+=A[k+(i+1)*lda]*tempB_1;
+					temp2_1+=A[k+(i+2)*lda]*tempB_1;
+					temp3_1+=A[k+(i+3)*lda]*tempB_1;
+				
+					tempB_2=B1[j+2+k*lda];
+					temp_2+=A[k+i*lda]*tempB_2;	
+					temp1_2+=A[k+(i+1)*lda]*tempB_2;
+					temp2_2+=A[k+(i+2)*lda]*tempB_2;
+					temp3_2+=A[k+(i+3)*lda]*tempB_2;
+				
+					tempB_3=B1[j+3+k*lda];
+					temp_3+=A[k+i*lda]*tempB_3;	
+					temp1_3+=A[k+(i+1)*lda]*tempB_3;
+					temp2_3+=A[k+(i+2)*lda]*tempB_3;
+					temp3_3+=A[k+(i+3)*lda]*tempB_3;
+				}
+				C[j+i*lda]=temp;
+				C[j+(i+1)*lda]=temp1;
+				C[j+(i+2)*lda]=temp2;
+				C[j+(i+3)*lda]=temp3;
+				
+				C[j+1+i*lda]=temp_1;
+				C[j+1+(i+1)*lda]=temp1_1;
+				C[j+1+(i+2)*lda]=temp2_1;
+				C[j+1+(i+3)*lda]=temp3_1;
+				
+				C[j+2+i*lda]=temp_2;
+				C[j+2+(i+1)*lda]=temp1_2;
+				C[j+2+(i+2)*lda]=temp2_2;
+				C[j+2+(i+3)*lda]=temp3_2;
+
+				C[j+3+i*lda]=temp_3;
+				C[j+3+(i+1)*lda]=temp1_3;
+				C[j+3+(i+2)*lda]=temp2_3;
+				C[j+3+(i+3)*lda]=temp3_3;
+				
+			}
+		}
+	}
+
+
+	
+ 
+}
diff --git a/apps/riscv-tests/mt/do_matmul.c b/apps/riscv-tests/mt/do_matmul.c
new file mode 100644
index 0000000..7a6b755
--- /dev/null
+++ b/apps/riscv-tests/mt/do_matmul.c
@@ -0,0 +1,26 @@
+#include "stdlib.h"
+
+#include "util.h"
+
+#include "dataset.h"
+void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda,  const data_t A[], const data_t B[], data_t C[] )
+{
+    int i, j, k;
+    data_t acc_temp;
+    data_t *A_j, *B_i;
+    int j_start = coreid*(32/ncores);
+    int j_end = (coreid+1)*(32/ncores);
+    for ( i = 0; i < 32; i++ ) {
+        B_i = B + i;
+        for ( j = j_start; j < j_end; j++ )  
+        {
+            acc_temp = 0;
+            A_j = A + j*32;
+            for ( k = 0; k < 32; k++ ) 
+            {
+                acc_temp += *(A_j + k) * *(B_i + k*32);
+            }
+            C[i + j*32] = acc_temp;
+        }
+    }
+}
diff --git a/apps/riscv-tests/mt/dr_matmul.c b/apps/riscv-tests/mt/dr_matmul.c
new file mode 100644
index 0000000..8a3d57c
--- /dev/null
+++ b/apps/riscv-tests/mt/dr_matmul.c
@@ -0,0 +1,128 @@
+#include "stdlib.h"
+
+#include "util.h"
+
+#include "dataset.h"
+void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda,  const data_t A[], const data_t B[], data_t C[] )
+{
+   
+  // ***************************** //
+  // **** ADD YOUR CODE HERE ***** //
+  // ***************************** //
+  //
+  // feel free to make a separate function for MI and MSI versions.
+  int j2, i2, k2, j, i, k; 
+  int tmpC00, tmpC01, tmpC02, tmpC03, tmpC04, tmpC05, tmpC06, tmpC07;
+  int tmpC10, tmpC11, tmpC12, tmpC13, tmpC14, tmpC15, tmpC16, tmpC17;
+  int jBLOCK = 32;
+  int iBLOCK = 16;
+  int kBLOCK = 32;
+  static __thread int tB[4096]; //__thread
+  int startInd = coreid*(lda/ncores);
+  int endInd = (coreid+1)*(lda/ncores);
+
+  //tranpose B (block?)
+  for (i = 0; i < lda; i += 2) {
+    for (j = startInd; j < endInd; j += 2) {
+      tB[j*lda + i] = B[i*lda + j];
+      tB[(j + 1)*lda + i] = B[i*lda + j + 1];
+      tB[j*lda + i + 1] = B[(i + 1)*lda + j];
+      tB[(j + 1)*lda + i + 1] = B[(i + 1)*lda + j + 1];
+    }
+    barrier(ncores);
+  }
+
+  // compute C[j*n + i] += A[j*n + k] + Btranspose[i*n + k]
+  for ( j2 = 0; j2 < lda; j2 += jBLOCK )
+    for ( i2 = startInd; i2 < endInd; i2 += iBLOCK )
+      for ( j = j2; j < j2 + jBLOCK; j += 2 ) 
+	for ( k2 = 0; k2 < lda; k2 += kBLOCK )
+	  for ( i = i2; i < i2 + iBLOCK; i += 8) {
+	    tmpC00 = C[j*lda + i + 0]; tmpC10 = C[(j + 1)*lda + i + 0];
+	    tmpC01 = C[j*lda + i + 1]; tmpC11 = C[(j + 1)*lda + i + 1];
+	    tmpC02 = C[j*lda + i + 2]; tmpC12 = C[(j + 1)*lda + i + 2];
+	    tmpC03 = C[j*lda + i + 3]; tmpC13 = C[(j + 1)*lda + i + 3];
+	    tmpC04 = C[j*lda + i + 4]; tmpC14 = C[(j + 1)*lda + i + 4];
+	    tmpC05 = C[j*lda + i + 5]; tmpC15 = C[(j + 1)*lda + i + 5];
+	    tmpC06 = C[j*lda + i + 6]; tmpC16 = C[(j + 1)*lda + i + 6];
+	    tmpC07 = C[j*lda + i + 7]; tmpC17 = C[(j + 1)*lda + i + 7];
+	    for ( k = k2; k < k2 + kBLOCK; k += 4) {
+	      tmpC00 += A[j*lda + k] * tB[(i + 0)*lda + k]; 
+	      tmpC01 += A[j*lda + k] * tB[(i + 1)*lda + k]; 
+	      tmpC02 += A[j*lda + k] * tB[(i + 2)*lda + k]; 
+	      tmpC03 += A[j*lda + k] * tB[(i + 3)*lda + k]; 
+	      tmpC04 += A[j*lda + k] * tB[(i + 4)*lda + k]; 
+	      tmpC05 += A[j*lda + k] * tB[(i + 5)*lda + k]; 
+	      tmpC06 += A[j*lda + k] * tB[(i + 6)*lda + k]; 
+	      tmpC07 += A[j*lda + k] * tB[(i + 7)*lda + k]; 
+	      tmpC10 += A[(j + 1)*lda + k] * tB[(i + 0)*lda + k]; 
+	      tmpC11 += A[(j + 1)*lda + k] * tB[(i + 1)*lda + k]; 
+	      tmpC12 += A[(j + 1)*lda + k] * tB[(i + 2)*lda + k]; 
+	      tmpC13 += A[(j + 1)*lda + k] * tB[(i + 3)*lda + k]; 
+	      tmpC14 += A[(j + 1)*lda + k] * tB[(i + 4)*lda + k]; 
+	      tmpC15 += A[(j + 1)*lda + k] * tB[(i + 5)*lda + k]; 
+	      tmpC16 += A[(j + 1)*lda + k] * tB[(i + 6)*lda + k]; 
+	      tmpC17 += A[(j + 1)*lda + k] * tB[(i + 7)*lda + k]; 
+
+	      tmpC00 += A[j*lda + k + 1] * tB[(i + 0)*lda + k + 1];
+	      tmpC01 += A[j*lda + k + 1] * tB[(i + 1)*lda + k + 1];
+	      tmpC02 += A[j*lda + k + 1] * tB[(i + 2)*lda + k + 1];
+	      tmpC03 += A[j*lda + k + 1] * tB[(i + 3)*lda + k + 1];
+	      tmpC04 += A[j*lda + k + 1] * tB[(i + 4)*lda + k + 1];
+	      tmpC05 += A[j*lda + k + 1] * tB[(i + 5)*lda + k + 1];
+	      tmpC06 += A[j*lda + k + 1] * tB[(i + 6)*lda + k + 1];
+	      tmpC07 += A[j*lda + k + 1] * tB[(i + 7)*lda + k + 1];
+	      tmpC10 += A[(j + 1)*lda + k + 1] * tB[(i + 0)*lda + k + 1];
+	      tmpC11 += A[(j + 1)*lda + k + 1] * tB[(i + 1)*lda + k + 1];
+	      tmpC12 += A[(j + 1)*lda + k + 1] * tB[(i + 2)*lda + k + 1];
+	      tmpC13 += A[(j + 1)*lda + k + 1] * tB[(i + 3)*lda + k + 1];
+	      tmpC14 += A[(j + 1)*lda + k + 1] * tB[(i + 4)*lda + k + 1];
+	      tmpC15 += A[(j + 1)*lda + k + 1] * tB[(i + 5)*lda + k + 1];
+	      tmpC16 += A[(j + 1)*lda + k + 1] * tB[(i + 6)*lda + k + 1];
+	      tmpC17 += A[(j + 1)*lda + k + 1] * tB[(i + 7)*lda + k + 1];
+
+	      tmpC00 += A[j*lda + k + 2] * tB[(i + 0)*lda + k + 2]; 
+	      tmpC01 += A[j*lda + k + 2] * tB[(i + 1)*lda + k + 2]; 
+	      tmpC02 += A[j*lda + k + 2] * tB[(i + 2)*lda + k + 2]; 
+	      tmpC03 += A[j*lda + k + 2] * tB[(i + 3)*lda + k + 2]; 
+	      tmpC04 += A[j*lda + k + 2] * tB[(i + 4)*lda + k + 2]; 
+	      tmpC05 += A[j*lda + k + 2] * tB[(i + 5)*lda + k + 2]; 
+	      tmpC06 += A[j*lda + k + 2] * tB[(i + 6)*lda + k + 2]; 
+	      tmpC07 += A[j*lda + k + 2] * tB[(i + 7)*lda + k + 2]; 
+	      tmpC10 += A[(j + 1)*lda + k + 2] * tB[(i + 0)*lda + k + 2]; 
+	      tmpC11 += A[(j + 1)*lda + k + 2] * tB[(i + 1)*lda + k + 2]; 
+	      tmpC12 += A[(j + 1)*lda + k + 2] * tB[(i + 2)*lda + k + 2]; 
+	      tmpC13 += A[(j + 1)*lda + k + 2] * tB[(i + 3)*lda + k + 2]; 
+	      tmpC14 += A[(j + 1)*lda + k + 2] * tB[(i + 4)*lda + k + 2]; 
+	      tmpC15 += A[(j + 1)*lda + k + 2] * tB[(i + 5)*lda + k + 2]; 
+	      tmpC16 += A[(j + 1)*lda + k + 2] * tB[(i + 6)*lda + k + 2]; 
+	      tmpC17 += A[(j + 1)*lda + k + 2] * tB[(i + 7)*lda + k + 2]; 
+
+	      tmpC00 += A[j*lda + k + 3] * tB[(i + 0)*lda + k + 3];
+	      tmpC01 += A[j*lda + k + 3] * tB[(i + 1)*lda + k + 3];
+	      tmpC02 += A[j*lda + k + 3] * tB[(i + 2)*lda + k + 3];
+	      tmpC03 += A[j*lda + k + 3] * tB[(i + 3)*lda + k + 3];
+	      tmpC04 += A[j*lda + k + 3] * tB[(i + 4)*lda + k + 3];
+	      tmpC05 += A[j*lda + k + 3] * tB[(i + 5)*lda + k + 3];
+	      tmpC06 += A[j*lda + k + 3] * tB[(i + 6)*lda + k + 3];
+	      tmpC07 += A[j*lda + k + 3] * tB[(i + 7)*lda + k + 3]; 
+	      tmpC10 += A[(j + 1)*lda + k + 3] * tB[(i + 0)*lda + k + 3];
+	      tmpC11 += A[(j + 1)*lda + k + 3] * tB[(i + 1)*lda + k + 3];
+	      tmpC12 += A[(j + 1)*lda + k + 3] * tB[(i + 2)*lda + k + 3];
+	      tmpC13 += A[(j + 1)*lda + k + 3] * tB[(i + 3)*lda + k + 3];
+	      tmpC14 += A[(j + 1)*lda + k + 3] * tB[(i + 4)*lda + k + 3];
+	      tmpC15 += A[(j + 1)*lda + k + 3] * tB[(i + 5)*lda + k + 3];
+	      tmpC16 += A[(j + 1)*lda + k + 3] * tB[(i + 6)*lda + k + 3];
+	      tmpC17 += A[(j + 1)*lda + k + 3] * tB[(i + 7)*lda + k + 3];
+	    }
+	    C[j*lda + i + 0] = tmpC00; C[(j + 1)*lda + i + 0] = tmpC10; 
+	    C[j*lda + i + 1] = tmpC01; C[(j + 1)*lda + i + 1] = tmpC11; 
+	    C[j*lda + i + 2] = tmpC02; C[(j + 1)*lda + i + 2] = tmpC12; 
+	    C[j*lda + i + 3] = tmpC03; C[(j + 1)*lda + i + 3] = tmpC13; 
+	    C[j*lda + i + 4] = tmpC04; C[(j + 1)*lda + i + 4] = tmpC14; 
+	    C[j*lda + i + 5] = tmpC05; C[(j + 1)*lda + i + 5] = tmpC15; 
+	    C[j*lda + i + 6] = tmpC06; C[(j + 1)*lda + i + 6] = tmpC16; 
+	    C[j*lda + i + 7] = tmpC07; C[(j + 1)*lda + i + 7] = tmpC17; 
+            barrier(ncores);
+	  }
+}
diff --git a/apps/riscv-tests/mt/ds_matmul.c b/apps/riscv-tests/mt/ds_matmul.c
new file mode 100644
index 0000000..3b48267
--- /dev/null
+++ b/apps/riscv-tests/mt/ds_matmul.c
@@ -0,0 +1,32 @@
+#include "stdlib.h"
+
+#include "util.h"
+
+#include "dataset.h"
+void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda,  const data_t A[], const data_t B[], data_t C[] )
+{
+int i,j,k,a,b,b1,a1,a2,a3,c,c1,c2,c3,b2,b3;
+        for (j=coreid*4; j<lda; j+=4*ncores){
+                a=j*lda;
+                a1=(j+1)*lda;
+                a2=(j+2)*lda;
+                a3=(j+3)*lda;
+                for (k=0;k<lda; k+=2)
+                {
+                        b = k*lda;
+                        b1 = (k+1)*lda;
+                        for (i=0;i<lda;i++){
+                                c = B[b+i];
+                                c1 = B[b1+i];
+                                C[i+a]+=A[a+k]*c;
+                                C[i+a1]+=A[a1+k]*c;
+                                C[i+a2]+=A[a2+k]*c;
+                                C[i+a3]+=A[a3+k]*c;
+                                C[i+a]+=A[a+k+1]*c1;
+                                C[i+a1]+=A[a1+k+1]*c1;
+                                C[i+a2]+=A[a2+k+1]*c1;
+                                C[i+a3]+=A[a3+k+1]*c1;
+}
+}
+}
+}
diff --git a/apps/riscv-tests/mt/du_matmul.c b/apps/riscv-tests/mt/du_matmul.c
new file mode 100644
index 0000000..a5622fe
--- /dev/null
+++ b/apps/riscv-tests/mt/du_matmul.c
@@ -0,0 +1,64 @@
+#include "stdlib.h"
+
+#include "util.h"
+
+#include "dataset.h"
+void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda,  const data_t A[], const data_t B[], data_t C[] )
+{
+  size_t i, j, k, l;
+  int row,row2, column, column2, column3, column4, column5, column6, column7, column8;
+  size_t max_dim = 32*32;
+  data_t element, element2, element3, element4, element5, element6, element7, element8;
+  data_t temp_mat[32]={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
+  data_t temp_mat2[32]={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
+  //for (i=coreid*max_dim/ncores; i<(max_dim/ncores+coreid*max_dim/ncores); i+=8){
+  for (l=coreid*32/ncores; l<32*(1+coreid)/ncores; l+=2){
+    row=l*32;
+    row2=(l+1)*32;
+    for (i=0; i<lda; i+=4){
+      element = A[row+i];
+      element2 = A[row+i+1];
+      element3 = A[row+i+2];
+      element4 = A[row+i+3];
+      element5 = A[row2+i];
+      element6 = A[row2+i+1];
+      element7 = A[row2+i+2];
+      element8 = A[row2+i+3];
+      column=i*32;
+      column2=(i+1)*32;
+      column3=(i+2)*32;
+      column4=(i+3)*32;
+      for (j=0; j<32; j+=4){
+	temp_mat[j]+=element*B[column+j]+element2*B[column2+j]+element3*B[column3+j]+element4*B[column4+j];
+	temp_mat[j+1]+=element*B[column+j+1]+element2*B[column2+j+1]+element3*B[column3+j+1]+element4*B[column4+j+1];
+	temp_mat[j+2]+=element*B[column+j+2]+element2*B[column2+j+2]+element3*B[column3+j+2]+element4*B[column4+j+2];
+	temp_mat[j+3]+=element*B[column+j+3]+element2*B[column2+j+3]+element3*B[column3+j+3]+element4*B[column4+j+3];
+	temp_mat2[j]+=element5*B[column+j]+element6*B[column2+j]+element7*B[column3+j]+element8*B[column4+j];
+	temp_mat2[j+1]+=element5*B[column+j+1]+element6*B[column2+j+1]+element7*B[column3+j+1]+element8*B[column4+j+1];
+	temp_mat2[j+2]+=element5*B[column+j+2]+element6*B[column2+j+2]+element7*B[column3+j+2]+element8*B[column4+j+2];
+	temp_mat2[j+3]+=element5*B[column+j+3]+element6*B[column2+j+3]+element7*B[column3+j+3]+element8*B[column4+j+3];
+      }
+      /*if (i==28){
+	for(k=0; k<32; k++){
+	  C[row+k]=temp_mat[k];
+	  C[row2+k]=temp_mat2[k];
+	  temp_mat[k]=0;
+	  temp_mat2[k]=0;
+	}
+	}*/
+    }
+    for(k=0; k<32; k++){
+	  C[row+k]=temp_mat[k];
+	  C[row2+k]=temp_mat2[k];
+	  temp_mat[k]=0;
+	  temp_mat2[k]=0;
+    }
+  }
+  
+   // ***************************** //
+   // **** ADD YOUR CODE HERE ***** //
+   // ***************************** //
+   //
+   // feel free to make a separate function for MI and MSI versions.
+
+}
diff --git a/apps/riscv-tests/mt/dv_matmul.c b/apps/riscv-tests/mt/dv_matmul.c
new file mode 100644
index 0000000..f76386d
--- /dev/null
+++ b/apps/riscv-tests/mt/dv_matmul.c
@@ -0,0 +1,98 @@
+#include "stdlib.h"
+
+#include "util.h"
+
+#include "dataset.h"
+void __attribute__((noinline)) matmul(const int coreid, const int ncores, const int lda,  const data_t A[], const data_t B[], data_t C[] )
+{
+   
+   // ***************************** //
+   // **** ADD YOUR CODE HERE ***** //
+   // ***************************** //
+   //
+   // feel free to make a separate function for MI and MSI versions.
+   int i, j, k, ii, jj, kk; 
+   if(coreid > 1) return; 
+  if (coreid || ncores == 1) { 
+// for ( ii = 0; ii < 32; ii+=IC )
+         for ( kk = 0; kk < 32; kk+=16 ) 
+   for ( j = 0; j < 16; j++ )  
+// for ( j = 0; j < 16; j++ )  
+   {
+      for ( i =  0; i < 32; i+=8 )
+//    for ( i = ii; i < ii + IC && i < 32; i+=8 )
+      {
+         data_t temp0 = C[i+j*32];
+         data_t temp1 = C[i+j*32+1];
+         data_t temp2 = C[i+j*32+2];
+         data_t temp3 = C[i+j*32+3];
+         data_t temp4 = C[i+j*32+4];
+         data_t temp5 = C[i+j*32+5];
+         data_t temp6 = C[i+j*32+6];
+         data_t temp7 = C[i+j*32+7];
+         for ( k = kk; k < kk+16 && k < 32; k++ ) 
+//       for ( k = 0; k < 32; k++ ) 
+         {
+            data_t tempA = A[j*32+k];
+            temp0 += tempA * B[k*32 + i];
+            temp1 += tempA * B[k*32 + i+1];
+            temp2 += tempA * B[k*32 + i+2];
+            temp3 += tempA * B[k*32 + i+3];
+            temp4 += tempA * B[k*32 + i+4];
+            temp5 += tempA * B[k*32 + i+5];
+            temp6 += tempA * B[k*32 + i+6];
+            temp7 += tempA * B[k*32 + i+7];
+         }
+         C[i+j*32] = temp0;
+         C[i+j*32+1] = temp1;
+         C[i+j*32+2] = temp2;
+         C[i+j*32+3] = temp3;
+         C[i+j*32+4] = temp4;
+         C[i+j*32+5] = temp5;
+         C[i+j*32+6] = temp6;
+         C[i+j*32+7] = temp7;
+      }
+   } 
+  } 
+  if(coreid == 0){
+// for ( ii = 0; ii < 32; ii+=IC )
+         for ( kk = 0; kk < 32; kk+=16 ) 
+   for ( j = 16; j < 32; j++ )  
+// for ( j = 16; j < 32; j++ )  
+   {
+      for ( i =   0; i < 32; i+=8 )
+//    for ( i = ii; i < ii + IC && i < 32; i+=8 )
+      {
+         data_t temp0 = C[i+j*32];
+         data_t temp1 = C[i+j*32+1];
+         data_t temp2 = C[i+j*32+2];
+         data_t temp3 = C[i+j*32+3];
+         data_t temp4 = C[i+j*32+4];
+         data_t temp5 = C[i+j*32+5];
+         data_t temp6 = C[i+j*32+6];
+         data_t temp7 = C[i+j*32+7];
+         for ( k = kk; k < kk+16 && k < 32; k++ ) 
+         {
+            data_t tempA = A[j*32+k];
+            temp0 += tempA * B[k*32 + i];
+            temp1 += tempA * B[k*32 + i+1];
+            temp2 += tempA * B[k*32 + i+2];
+            temp3 += tempA * B[k*32 + i+3];
+            temp4 += tempA * B[k*32 + i+4];
+            temp5 += tempA * B[k*32 + i+5];
+            temp6 += tempA * B[k*32 + i+6];
+            temp7 += tempA * B[k*32 + i+7];
+         }
+         C[i+j*32] = temp0;
+         C[i+j*32+1] = temp1;
+         C[i+j*32+2] = temp2;
+         C[i+j*32+3] = temp3;
+         C[i+j*32+4] = temp4;
+         C[i+j*32+5] = temp5;
+         C[i+j*32+6] = temp6;
+         C[i+j*32+7] = temp7;
+      }
+
+   }
+  } 
+}
diff --git a/apps/riscv-tests/mt/vvadd0.c b/apps/riscv-tests/mt/vvadd0.c
new file mode 100644
index 0000000..4cc66b9
--- /dev/null
+++ b/apps/riscv-tests/mt/vvadd0.c
@@ -0,0 +1,14 @@
+#include "stdlib.h"
+#include "dataset.h"
+
+void __attribute__((noinline)) vvadd(int coreid, int ncores, size_t n, const data_t* x, const data_t* y, data_t* z)
+{
+  size_t i;
+  size_t leftover = n % (n / ncores);
+  for (i = coreid * (n / ncores); i < (coreid + 1) * (n / ncores); i++) {
+    z[i] = x[i] + y[i];
+  }
+  for (i = (n - leftover) + coreid; i < n; i += ncores) {
+    z[i] = x[i] + y[i];
+  }
+}
diff --git a/apps/riscv-tests/mt/vvadd1.c b/apps/riscv-tests/mt/vvadd1.c
new file mode 100644
index 0000000..b7e44a7
--- /dev/null
+++ b/apps/riscv-tests/mt/vvadd1.c
@@ -0,0 +1,17 @@
+#include "stdlib.h"
+#include "dataset.h"
+
+void __attribute__((noinline)) vvadd(int coreid, int ncores, size_t n, const data_t* x, const data_t* y, data_t* z)
+{
+   size_t i;
+   for (i = coreid*4; i < n; i += 8*ncores) {
+      z[i]   = x[i]   + y[i];
+      z[i+1] = x[i+1] + y[i+1];
+      z[i+2] = x[i+2] + y[i+2];
+      z[i+3] = x[i+3] + y[i+3];
+      z[i+ncores*4]   = x[i+ncores*4]   + y[i+ncores*4];
+      z[i+ncores*4+1] = x[i+ncores*4+1] + y[i+ncores*4+1];
+      z[i+ncores*4+2] = x[i+ncores*4+2] + y[i+ncores*4+2];
+      z[i+ncores*4+3] = x[i+ncores*4+3] + y[i+ncores*4+3];
+   }
+}
diff --git a/apps/riscv-tests/mt/vvadd2.c b/apps/riscv-tests/mt/vvadd2.c
new file mode 100644
index 0000000..937a2e9
--- /dev/null
+++ b/apps/riscv-tests/mt/vvadd2.c
@@ -0,0 +1,11 @@
+#include "stdlib.h"
+#include "dataset.h"
+
+void __attribute__((noinline)) vvadd(int coreid, int ncores, size_t n, const data_t* x, const data_t* y, data_t* z)
+{
+   size_t i;
+   for (i = coreid; i < n; i += 2*ncores) {
+      z[i] = x[i] + y[i];
+      z[i+ncores] = x[i+ncores] + y[i+ncores];
+   }
+}
diff --git a/apps/riscv-tests/mt/vvadd3.c b/apps/riscv-tests/mt/vvadd3.c
new file mode 100644
index 0000000..d18d2de
--- /dev/null
+++ b/apps/riscv-tests/mt/vvadd3.c
@@ -0,0 +1,22 @@
+#include "stdlib.h"
+#include "dataset.h"
+
+void __attribute__((noinline)) vvadd(int coreid, int ncores, size_t n, const data_t* x, const data_t* y, data_t* z)
+{
+  data_t* to = &z[coreid * (n / ncores)];
+  const data_t* from1 = &x[coreid * (n / ncores)];
+  const data_t* from2 = &y[coreid * (n / ncores)];
+  size_t count = n / ncores;
+  size_t c = (count + 7) / 8;
+  switch(count % 8) {
+    case 0: do {  *to++ = *from1++ + *from2++;
+    case 7:       *to++ = *from1++ + *from2++;
+    case 6:       *to++ = *from1++ + *from2++;
+    case 5:       *to++ = *from1++ + *from2++;
+    case 4:       *to++ = *from1++ + *from2++;
+    case 3:       *to++ = *from1++ + *from2++;
+    case 2:       *to++ = *from1++ + *from2++;
+    case 1:       *to++ = *from1++ + *from2++;
+  } while(--c > 0);
+  }
+}
diff --git a/apps/riscv-tests/mt/vvadd4.c b/apps/riscv-tests/mt/vvadd4.c
new file mode 100644
index 0000000..8f4d43f
--- /dev/null
+++ b/apps/riscv-tests/mt/vvadd4.c
@@ -0,0 +1,16 @@
+#include "stdlib.h"
+#include "dataset.h"
+
+//--------------------------------------------------------------------------
+// vvadd function
+
+void __attribute__((noinline)) vvadd(int coreid, int ncores, size_t n, const data_t* x, const data_t* y, data_t* z)
+{
+   size_t i;
+
+   // interleave accesses
+   for (i = coreid; i < n; i+=ncores)
+   {
+      z[i] = x[i] + y[i];
+   }
+}
diff --git a/config/16_lanes.mk b/config/16_lanes.mk
index a832ce3..3c520d0 100644
--- a/config/16_lanes.mk
+++ b/config/16_lanes.mk
@@ -19,6 +19,8 @@
 
 # Number of vector lanes
 nr_lanes ?= 16
+# Number of clusters
+nr_clusters ?= 4
 
 # Length of each vector register (in bits)
 # Constraints: VLEN > 128
diff --git a/config/2_lanes.mk b/config/2_lanes.mk
index 11ed9d6..5edb8a4 100644
--- a/config/2_lanes.mk
+++ b/config/2_lanes.mk
@@ -19,6 +19,8 @@
 
 # Number of vector lanes
 nr_lanes ?= 2
+# Number of clusters
+nr_clusters ?= 4
 
 # Length of each vector register (in bits)
 # Constraints: VLEN > 128
diff --git a/config/4_lanes.mk b/config/4_lanes.mk
index 67af28e..7edea50 100644
--- a/config/4_lanes.mk
+++ b/config/4_lanes.mk
@@ -19,6 +19,8 @@
 
 # Number of vector lanes
 nr_lanes ?= 4
+# Number of clusters
+nr_clusters ?= 4
 
 # Length of each vector register (in bits)
 # Constraints: VLEN > 128
diff --git a/config/8_lanes.mk b/config/8_lanes.mk
index 573f7a5..b07a3b9 100644
--- a/config/8_lanes.mk
+++ b/config/8_lanes.mk
@@ -19,6 +19,8 @@
 
 # Number of vector lanes
 nr_lanes ?= 8
+# Number of clusters
+nr_clusters ?= 4
 
 # Length of each vector register (in bits)
 # Constraints: VLEN > 128

From 951b411c2eb092dc8d584166b86a939c88115588 Mon Sep 17 00:00:00 2001
From: Hong Pang <hopang@larain5.ee.ethz.ch>
Date: Mon, 3 Nov 2025 19:35:28 +0100
Subject: [PATCH 07/37] [CI] delete sphinx.yml

---
 .github/workflows/{sphinx.yml => sphinx.txt} | 0
 1 file changed, 0 insertions(+), 0 deletions(-)
 rename .github/workflows/{sphinx.yml => sphinx.txt} (100%)

diff --git a/.github/workflows/sphinx.yml b/.github/workflows/sphinx.txt
similarity index 100%
rename from .github/workflows/sphinx.yml
rename to .github/workflows/sphinx.txt

From 2f3f5ef38fb129bbb75e50f134c8d5d98ae3ad23 Mon Sep 17 00:00:00 2001
From: Hong Pang <hopang@larain5.ee.ethz.ch>
Date: Mon, 3 Nov 2025 19:39:26 +0100
Subject: [PATCH 08/37] [CI] uncomment benchmark part

---
 .github/workflows/ci.yml | 102 +++++++++++++++++++--------------------
 1 file changed, 51 insertions(+), 51 deletions(-)

diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
index 9a64d12..8a03b8b 100644
--- a/.github/workflows/ci.yml
+++ b/.github/workflows/ci.yml
@@ -505,57 +505,57 @@ jobs:
 #  Benchmark stage  #
 #####################
 
-  # benchmark:
-  #   runs-on: ubuntu-22.04
-  #   strategy:
-  #     max-parallel: 1
-  #     matrix:
-  #       ara_config: [2_lanes, 4_lanes, 8_lanes, 16_lanes]
-  #   needs: ["compile-ara", "compile-apps"]
-  #   steps:
-  #   - uses: actions/checkout@v4
-  #   - uses: actions/setup-python@v4
-  #     with:
-  #       python-version: 3.12.0
-  #   - name: Install Python requirements
-  #     run: pip install -r python-requirements.txt
-  #   - name: Download the LLVM toolchain
-  #     uses: actions/download-artifact@v4
-  #     with:
-  #       name: tc-llvm
-  #   - name: Untar LLVM
-  #     run: tar xvf tc-llvm.tar
-  #   - name: Get Spike artifacts
-  #     uses: actions/download-artifact@v4
-  #     with:
-  #       name: tc-isa-sim
-  #   - name: Untar Spike
-  #     run: tar xvf tc-isa-sim.tar
-  #   - name: Get Verilated model of Ara
-  #     uses: actions/download-artifact@v4
-  #     with:
-  #       name: compile-ara-${{ matrix.ara_config }}
-  #   - name: Untar Verilated model of Ara
-  #     run: tar xvf ara.tar
-  #   - name: Benchmark Ara
-  #     run: config=${{ matrix.ara_config }} ./scripts/benchmark.sh ci
-  #   - name: Tar [f]dotproduct runtime results
-  #     run: |
-  #       tar -cvf dotproducts-${{ matrix.ara_config }}.tar *dotproduct*.benchmark
-  #       rm *dotproduct*.benchmark
-  #   - name: Tar runtime results
-  #     run: |
-  #       tar -cvf benchmarks-${{ matrix.ara_config }}.tar *.benchmark
-  #   - name: Upload [f]dotproduct runtime results
-  #     uses: actions/upload-artifact@v4
-  #     with:
-  #       name: dotproducts-${{ matrix.ara_config }}
-  #       path: dotproducts-${{ matrix.ara_config }}.tar
-  #   - name: Upload runtime results
-  #     uses: actions/upload-artifact@v4
-  #     with:
-  #       name: benchmark-${{ matrix.ara_config }}
-  #       path: benchmarks-${{ matrix.ara_config }}.tar
+  benchmark:
+    runs-on: ubuntu-22.04
+    strategy:
+      max-parallel: 1
+      matrix:
+        ara_config: [2_lanes, 4_lanes, 8_lanes, 16_lanes]
+    needs: ["compile-ara", "compile-apps"]
+    steps:
+    - uses: actions/checkout@v4
+    - uses: actions/setup-python@v4
+      with:
+        python-version: 3.12.0
+    - name: Install Python requirements
+      run: pip install -r python-requirements.txt
+    - name: Download the LLVM toolchain
+      uses: actions/download-artifact@v4
+      with:
+        name: tc-llvm
+    - name: Untar LLVM
+      run: tar xvf tc-llvm.tar
+    - name: Get Spike artifacts
+      uses: actions/download-artifact@v4
+      with:
+        name: tc-isa-sim
+    - name: Untar Spike
+      run: tar xvf tc-isa-sim.tar
+    - name: Get Verilated model of Ara
+      uses: actions/download-artifact@v4
+      with:
+        name: compile-ara-${{ matrix.ara_config }}
+    - name: Untar Verilated model of Ara
+      run: tar xvf ara.tar
+    - name: Benchmark Ara
+      run: config=${{ matrix.ara_config }} ./scripts/benchmark.sh ci
+    - name: Tar [f]dotproduct runtime results
+      run: |
+        tar -cvf dotproducts-${{ matrix.ara_config }}.tar *dotproduct*.benchmark
+        rm *dotproduct*.benchmark
+    - name: Tar runtime results
+      run: |
+        tar -cvf benchmarks-${{ matrix.ara_config }}.tar *.benchmark
+    - name: Upload [f]dotproduct runtime results
+      uses: actions/upload-artifact@v4
+      with:
+        name: dotproducts-${{ matrix.ara_config }}
+        path: dotproducts-${{ matrix.ara_config }}.tar
+    - name: Upload runtime results
+      uses: actions/upload-artifact@v4
+      with:
+        name: benchmark-${{ matrix.ara_config }}
+        path: benchmarks-${{ matrix.ara_config }}.tar
 
   # roofline:
   #   runs-on: ubuntu-22.04

From 74f1461dde02353cb55da15d367d4b44f94c149e Mon Sep 17 00:00:00 2001
From: Hong Pang <hopang@larain5.ee.ethz.ch>
Date: Mon, 3 Nov 2025 19:40:55 +0100
Subject: [PATCH 09/37] [CI] uncomment roofline part

---
 .github/workflows/ci.yml | 302 +++++++++++++++++++--------------------
 1 file changed, 151 insertions(+), 151 deletions(-)

diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
index 8a03b8b..fb89d67 100644
--- a/.github/workflows/ci.yml
+++ b/.github/workflows/ci.yml
@@ -557,157 +557,157 @@ jobs:
         name: benchmark-${{ matrix.ara_config }}
         path: benchmarks-${{ matrix.ara_config }}.tar
 
-  # roofline:
-  #   runs-on: ubuntu-22.04
-  #   needs: benchmark
-  #   steps:
-  #   - uses: actions/checkout@v4
-  #   - uses: actions/setup-python@v4
-  #     with:
-  #       python-version: 3.12.0
-  #   - name: Install Python requirements
-  #     run: pip install -r python-requirements.txt
-  #   - uses: actions/checkout@v4
-  #   - name: Get [f]dotproduct results (2 lanes)
-  #     uses: actions/download-artifact@v4
-  #     with:
-  #       name: dotproducts-2_lanes
-  #   - name: Get [f]dotproduct results (4 lanes)
-  #     uses: actions/download-artifact@v4
-  #     with:
-  #       name: dotproducts-4_lanes
-  #   - name: Get [f]dotproduct results (8 lanes)
-  #     uses: actions/download-artifact@v4
-  #     with:
-  #       name: dotproducts-8_lanes
-  #   - name: Get [f]dotproduct results (16 lanes)
-  #     uses: actions/download-artifact@v4
-  #     with:
-  #       name: dotproducts-16_lanes
-  #   - name: Get benchmark results (2 lanes)
-  #     uses: actions/download-artifact@v4
-  #     with:
-  #       name: benchmark-2_lanes
-  #   - name: Get benchmark results (4 lanes)
-  #     uses: actions/download-artifact@v4
-  #     with:
-  #       name: benchmark-4_lanes
-  #   - name: Get benchmark results (8 lanes)
-  #     uses: actions/download-artifact@v4
-  #     with:
-  #       name: benchmark-8_lanes
-  #   - name: Get benchmark results (16 lanes)
-  #     uses: actions/download-artifact@v4
-  #     with:
-  #       name: benchmark-16_lanes
-  #   - name: Untar the [f]dotproduct results
-  #     run: |
-  #       tar xvf dotproducts-2_lanes.tar
-  #       tar xvf dotproducts-4_lanes.tar
-  #       tar xvf dotproducts-8_lanes.tar
-  #       tar xvf dotproducts-16_lanes.tar
-  #   - name: Untar the results
-  #     run: |
-  #       tar xvf benchmarks-2_lanes.tar
-  #       tar xvf benchmarks-4_lanes.tar
-  #       tar xvf benchmarks-8_lanes.tar
-  #       tar xvf benchmarks-16_lanes.tar
-  #   - name: Install gnuplot
-  #     run: |
-  #       sudo apt-get update
-  #       sudo apt-get install gnuplot
-  #   - name: Plot [f]dotproduct plots
-  #     run: |
-  #       for kernel in fdotproduct dotproduct; do
-  #         > ${kernel}.benchmark
-  #         for nr_lanes in 2 4 8 16; do
-  #           cat ${kernel}_${nr_lanes}_bar_plots.benchmark >> ${kernel}.benchmark
-  #         done
-  #         python scripts/process_dotp.py ${kernel} ${kernel}.benchmark ${kernel}
-  #         tar -cvf ${kernel}.tar $(find . -name "${kernel}_*.png")
-  #       done
-  #   - name: Plot the rooflines
-  #     run: gnuplot -c scripts/benchmark.gnuplot
-  #   - name: Upload the imatmul roofline
-  #     uses: actions/upload-artifact@v4
-  #     with:
-  #       name: imatmul_roofline
-  #       path: imatmul.png
-  #   - name: Upload the fmatmul roofline
-  #     uses: actions/upload-artifact@v4
-  #     with:
-  #       name: fmatmul_roofline
-  #       path: fmatmul.png
-  #   - name: Upload the iconv2d roofline
-  #     uses: actions/upload-artifact@v4
-  #     with:
-  #       name: iconv2d_roofline
-  #       path: iconv2d.png
-  #   - name: Upload the fconv2d roofline
-  #     uses: actions/upload-artifact@v4
-  #     with:
-  #       name: fconv2d_roofline
-  #       path: fconv2d.png
-  #   - name: Upload the fconv3d roofline
-  #     uses: actions/upload-artifact@v4
-  #     with:
-  #       name: fconv3d_roofline
-  #       path: fconv3d.png
-  #   - name: Upload the jacobi2d roofline
-  #     uses: actions/upload-artifact@v4
-  #     with:
-  #       name: jacobi2d_roofline
-  #       path: jacobi2d.png
-  #   - name: Upload the dropout roofline
-  #     uses: actions/upload-artifact@v4
-  #     with:
-  #       name: dropout_roofline
-  #       path: dropout.png
-  #   - name: Upload the fft roofline
-  #     uses: actions/upload-artifact@v4
-  #     with:
-  #       name: fft_roofline
-  #       path: fft.png
-  #   - name: Upload the dwt roofline
-  #     uses: actions/upload-artifact@v4
-  #     with:
-  #       name: dwt_roofline
-  #       path: dwt.png
-  #   - name: Upload the exp roofline
-  #     uses: actions/upload-artifact@v4
-  #     with:
-  #       name: exp_roofline
-  #       path: exp.png
-  #   - name: Upload the softmax roofline
-  #     uses: actions/upload-artifact@v4
-  #     with:
-  #       name: softmax_roofline
-  #       path: softmax.png
-  #   - name: Upload the fdotproduct roofline
-  #     uses: actions/upload-artifact@v4
-  #     with:
-  #       name: fdotproduct_plots
-  #       path: fdotproduct.tar
-  #   - name: Upload the dotproduct roofline
-  #     uses: actions/upload-artifact@v4
-  #     with:
-  #       name: dotproduct_plots
-  #       path: dotproduct.tar
-  #   - name: Upload the pathfinder roofline
-  #     uses: actions/upload-artifact@v4
-  #     with:
-  #       name: pathfinder_roofline
-  #       path: pathfinder.png
-  #   - name: Upload the roi_align roofline
-  #     uses: actions/upload-artifact@v4
-  #     with:
-  #       name: roi_align_roofline
-  #       path: roi_align.png
-  #   - name: Upload the lavamd roofline
-  #     uses: actions/upload-artifact@v4
-  #     with:
-  #       name: lavamd_roofline
-  #       path: lavamd.png
+  roofline:
+    runs-on: ubuntu-22.04
+    needs: benchmark
+    steps:
+    - uses: actions/checkout@v4
+    - uses: actions/setup-python@v4
+      with:
+        python-version: 3.12.0
+    - name: Install Python requirements
+      run: pip install -r python-requirements.txt
+    - uses: actions/checkout@v4
+    - name: Get [f]dotproduct results (2 lanes)
+      uses: actions/download-artifact@v4
+      with:
+        name: dotproducts-2_lanes
+    - name: Get [f]dotproduct results (4 lanes)
+      uses: actions/download-artifact@v4
+      with:
+        name: dotproducts-4_lanes
+    - name: Get [f]dotproduct results (8 lanes)
+      uses: actions/download-artifact@v4
+      with:
+        name: dotproducts-8_lanes
+    - name: Get [f]dotproduct results (16 lanes)
+      uses: actions/download-artifact@v4
+      with:
+        name: dotproducts-16_lanes
+    - name: Get benchmark results (2 lanes)
+      uses: actions/download-artifact@v4
+      with:
+        name: benchmark-2_lanes
+    - name: Get benchmark results (4 lanes)
+      uses: actions/download-artifact@v4
+      with:
+        name: benchmark-4_lanes
+    - name: Get benchmark results (8 lanes)
+      uses: actions/download-artifact@v4
+      with:
+        name: benchmark-8_lanes
+    - name: Get benchmark results (16 lanes)
+      uses: actions/download-artifact@v4
+      with:
+        name: benchmark-16_lanes
+    - name: Untar the [f]dotproduct results
+      run: |
+        tar xvf dotproducts-2_lanes.tar
+        tar xvf dotproducts-4_lanes.tar
+        tar xvf dotproducts-8_lanes.tar
+        tar xvf dotproducts-16_lanes.tar
+    - name: Untar the results
+      run: |
+        tar xvf benchmarks-2_lanes.tar
+        tar xvf benchmarks-4_lanes.tar
+        tar xvf benchmarks-8_lanes.tar
+        tar xvf benchmarks-16_lanes.tar
+    - name: Install gnuplot
+      run: |
+        sudo apt-get update
+        sudo apt-get install gnuplot
+    - name: Plot [f]dotproduct plots
+      run: |
+        for kernel in fdotproduct dotproduct; do
+          > ${kernel}.benchmark
+          for nr_lanes in 2 4 8 16; do
+            cat ${kernel}_${nr_lanes}_bar_plots.benchmark >> ${kernel}.benchmark
+          done
+          python scripts/process_dotp.py ${kernel} ${kernel}.benchmark ${kernel}
+          tar -cvf ${kernel}.tar $(find . -name "${kernel}_*.png")
+        done
+    - name: Plot the rooflines
+      run: gnuplot -c scripts/benchmark.gnuplot
+    - name: Upload the imatmul roofline
+      uses: actions/upload-artifact@v4
+      with:
+        name: imatmul_roofline
+        path: imatmul.png
+    - name: Upload the fmatmul roofline
+      uses: actions/upload-artifact@v4
+      with:
+        name: fmatmul_roofline
+        path: fmatmul.png
+    - name: Upload the iconv2d roofline
+      uses: actions/upload-artifact@v4
+      with:
+        name: iconv2d_roofline
+        path: iconv2d.png
+    - name: Upload the fconv2d roofline
+      uses: actions/upload-artifact@v4
+      with:
+        name: fconv2d_roofline
+        path: fconv2d.png
+    - name: Upload the fconv3d roofline
+      uses: actions/upload-artifact@v4
+      with:
+        name: fconv3d_roofline
+        path: fconv3d.png
+    - name: Upload the jacobi2d roofline
+      uses: actions/upload-artifact@v4
+      with:
+        name: jacobi2d_roofline
+        path: jacobi2d.png
+    - name: Upload the dropout roofline
+      uses: actions/upload-artifact@v4
+      with:
+        name: dropout_roofline
+        path: dropout.png
+    - name: Upload the fft roofline
+      uses: actions/upload-artifact@v4
+      with:
+        name: fft_roofline
+        path: fft.png
+    - name: Upload the dwt roofline
+      uses: actions/upload-artifact@v4
+      with:
+        name: dwt_roofline
+        path: dwt.png
+    - name: Upload the exp roofline
+      uses: actions/upload-artifact@v4
+      with:
+        name: exp_roofline
+        path: exp.png
+    - name: Upload the softmax roofline
+      uses: actions/upload-artifact@v4
+      with:
+        name: softmax_roofline
+        path: softmax.png
+    - name: Upload the fdotproduct roofline
+      uses: actions/upload-artifact@v4
+      with:
+        name: fdotproduct_plots
+        path: fdotproduct.tar
+    - name: Upload the dotproduct roofline
+      uses: actions/upload-artifact@v4
+      with:
+        name: dotproduct_plots
+        path: dotproduct.tar
+    - name: Upload the pathfinder roofline
+      uses: actions/upload-artifact@v4
+      with:
+        name: pathfinder_roofline
+        path: pathfinder.png
+    - name: Upload the roi_align roofline
+      uses: actions/upload-artifact@v4
+      with:
+        name: roi_align_roofline
+        path: roi_align.png
+    - name: Upload the lavamd roofline
+      uses: actions/upload-artifact@v4
+      with:
+        name: lavamd_roofline
+        path: lavamd.png
 
 ####################
 #  Clean-up stage  #

From 85b07eb2986eebe15588cc6322eb93059d4127f3 Mon Sep 17 00:00:00 2001
From: Hong Pang <hopang@larain5.ee.ethz.ch>
Date: Mon, 3 Nov 2025 19:52:55 +0100
Subject: [PATCH 10/37] [CI] remove variables

---
 .github/workflows/ci.yml                     | 136 +++++++++----------
 .github/workflows/{sphinx.txt => sphinx.yml} |   0
 2 files changed, 68 insertions(+), 68 deletions(-)
 rename .github/workflows/{sphinx.txt => sphinx.yml} (100%)

diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
index fb89d67..4b9d5ed 100644
--- a/.github/workflows/ci.yml
+++ b/.github/workflows/ci.yml
@@ -7,8 +7,8 @@
 # Run functional regression checks
 name: ci
 on: [push, pull_request]
-variables:
-  TOOL_DIR=/usr/scratch2/tokyo/mperotti/tools/arathon/install
+# variables:
+#   TOOL_DIR=/usr/scratch2/tokyo/mperotti/tools/arathon/install
 
 # Only allow one workflow per PR/Branch (the last one)
 # https://docs.github.com/en/actions/learn-github-actions/expressions
@@ -75,7 +75,7 @@ jobs:
     #     sudo apt-get install -y ninja-build
     #     CC=gcc CXX=g++ make toolchain-llvm
     - name: Copy LLVM tools
-      run: cp -Lr ${TOOL_DIR}/riscv-llvm install
+      run: cp -Lr /usr/scratch2/tokyo/mperotti/tools/arathon/install/riscv-llvm install
     - name: Tar LLVM
       run: tar -cvf tc-llvm.tar install/riscv-llvm
     - name: Upload LLVM
@@ -128,7 +128,7 @@ jobs:
     #     sudo apt-get install libmpc-dev
     #     CC=gcc CXX=g++ make toolchain-gcc
     - name: Copy GCC tools
-      run: cp -Lr ${TOOL_DIR}/riscv-gcc install
+      run: cp -Lr /usr/scratch2/tokyo/mperotti/tools/arathon/install/riscv-gcc install
     - name: Tar GCC
       run: tar -cvf tc-gcc.tar install/riscv-gcc
     - name: Upload GCC
@@ -165,7 +165,7 @@ jobs:
     #   if: steps.tc-isa-sim-cache.outputs.cache-hit != 'true'
     #   run: make riscv-isa-sim
     - name: Copy Spike
-      run: cp -Lr ${TOOL_DIR}/riscv-isa-sim install
+      run: cp -Lr /usr/scratch2/tokyo/mperotti/tools/arathon/install/riscv-isa-sim install
     - name: Tar Spike
       run: tar -cvf tc-isa-sim.tar install/riscv-isa-sim
     - name: Upload Spike
@@ -203,7 +203,7 @@ jobs:
     #     sudo apt-get install flex libfl-dev help2man
     #     make verilator
     - name: Copy Verilator
-      run: cp -Lr ${TOOL_DIR}/verilator install
+      run: cp -Lr /usr/scratch2/tokyo/mperotti/tools/arathon/install/verilator install
     - name: Tar Verilator
       run: tar -cvf tc-verilator.tar install/verilator
     - name: Upload Verilator
@@ -371,69 +371,69 @@ jobs:
 #  RISC-V Tests stage  #
 ########################
 
-  # riscv-tests-simv:
-  #   runs-on: ubuntu-22.04
-  #   strategy:
-  #     max-parallel: 1
-  #     matrix:
-  #       ara_config: [2_lanes, 4_lanes, 8_lanes, 16_lanes]
-  #   needs: ["compile-ara", "compile-riscv-tests"]
-  #   steps:
-  #   - uses: actions/checkout@v4
-  #   - name: Get Spike artifacts
-  #     uses: actions/download-artifact@v4
-  #     with:
-  #       name: tc-isa-sim
-  #   - name: Untar Spike
-  #     run: tar xvf tc-isa-sim.tar
-  #   - name: Get Verilated model of Ara
-  #     uses: actions/download-artifact@v4
-  #     with:
-  #       name: compile-ara-${{ matrix.ara_config }}
-  #   - name: Untar Verilated model of Ara
-  #     run: tar xvf ara.tar
-  #   - name: Get RISC-V tests
-  #     uses: actions/download-artifact@v4
-  #     with:
-  #       name: compile-riscv-tests-${{ matrix.ara_config }}
-  #       path: apps/bin
-  #   - name: Run tests
-  #     run: config=${{ matrix.ara_config }} make -C hardware -j8 riscv_tests_simv
+  riscv-tests-simv:
+    runs-on: ubuntu-22.04
+    strategy:
+      max-parallel: 1
+      matrix:
+        ara_config: [2_lanes, 4_lanes, 8_lanes, 16_lanes]
+    needs: ["compile-ara", "compile-riscv-tests"]
+    steps:
+    - uses: actions/checkout@v4
+    - name: Get Spike artifacts
+      uses: actions/download-artifact@v4
+      with:
+        name: tc-isa-sim
+    - name: Untar Spike
+      run: tar xvf tc-isa-sim.tar
+    - name: Get Verilated model of Ara
+      uses: actions/download-artifact@v4
+      with:
+        name: compile-ara-${{ matrix.ara_config }}
+    - name: Untar Verilated model of Ara
+      run: tar xvf ara.tar
+    - name: Get RISC-V tests
+      uses: actions/download-artifact@v4
+      with:
+        name: compile-riscv-tests-${{ matrix.ara_config }}
+        path: apps/bin
+    - name: Run tests
+      run: config=${{ matrix.ara_config }} make -C hardware -j8 riscv_tests_simv
 
-  # riscv-tests-spike:
-  #   runs-on: ubuntu-22.04
-  #   needs: ["tc-isa-sim", "compile-riscv-tests"]
-  #   steps:
-  #   - uses: actions/checkout@v4
-  #   - name: Get Spike artifacts
-  #     uses: actions/download-artifact@v4
-  #     with:
-  #       name: tc-isa-sim
-  #   - name: Untar Spike
-  #     run: tar xvf tc-isa-sim.tar
-  #   - name: Download the LLVM toolchain
-  #     uses: actions/download-artifact@v4
-  #     with:
-  #       name: tc-llvm
-  #   - name: Untar LLVM
-  #     run: tar xvf tc-llvm.tar
-  #   - name: Download the GCC toolchain
-  #     uses: actions/download-artifact@v4
-  #     with:
-  #       name: tc-gcc
-  #   - name: Untar GCC
-  #     run: tar xvf tc-gcc.tar
-  #   - name: Run tests
-  #     run: |
-  #       make -C apps/riscv-tests/isa clean
-  #       make -C apps riscv_tests_spike
-  #   - name: Upload dumps
-  #     uses: actions/upload-artifact@v4
-  #     with:
-  #       name: riscv-tests-spike
-  #       path: |
-  #         apps/riscv-tests/isa/*.dump
-  #         apps/riscv-tests/isa/*.out32
+  riscv-tests-spike:
+    runs-on: ubuntu-22.04
+    needs: ["tc-isa-sim", "compile-riscv-tests"]
+    steps:
+    - uses: actions/checkout@v4
+    - name: Get Spike artifacts
+      uses: actions/download-artifact@v4
+      with:
+        name: tc-isa-sim
+    - name: Untar Spike
+      run: tar xvf tc-isa-sim.tar
+    - name: Download the LLVM toolchain
+      uses: actions/download-artifact@v4
+      with:
+        name: tc-llvm
+    - name: Untar LLVM
+      run: tar xvf tc-llvm.tar
+    - name: Download the GCC toolchain
+      uses: actions/download-artifact@v4
+      with:
+        name: tc-gcc
+    - name: Untar GCC
+      run: tar xvf tc-gcc.tar
+    - name: Run tests
+      run: |
+        make -C apps/riscv-tests/isa clean
+        make -C apps riscv_tests_spike
+    - name: Upload dumps
+      uses: actions/upload-artifact@v4
+      with:
+        name: riscv-tests-spike
+        path: |
+          apps/riscv-tests/isa/*.dump
+          apps/riscv-tests/isa/*.out32
 
 ###################
 #  Linting stage  #
diff --git a/.github/workflows/sphinx.txt b/.github/workflows/sphinx.yml
similarity index 100%
rename from .github/workflows/sphinx.txt
rename to .github/workflows/sphinx.yml

From 1b5a9c1bbc6ccc4f9522098342567ac20fcee3a9 Mon Sep 17 00:00:00 2001
From: Hong Pang <hopang@larain5.ee.ethz.ch>
Date: Mon, 3 Nov 2025 19:59:15 +0100
Subject: [PATCH 11/37] [CI]update sciki-learn kit

---
 python-requirements.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/python-requirements.txt b/python-requirements.txt
index cba2d9d..cf27f08 100644
--- a/python-requirements.txt
+++ b/python-requirements.txt
@@ -12,4 +12,4 @@ tabulate
 yamlfmt
 numpy
 matplotlib
-sklearn
+scikit-learn

From 62794b6061ccd3fd772b689d7f2011c81e08a00b Mon Sep 17 00:00:00 2001
From: Hong Pang <hopang@larain5.ee.ethz.ch>
Date: Mon, 3 Nov 2025 20:25:57 +0100
Subject: [PATCH 12/37] [CI] ci trial on toolchain

---
 .github/workflows/ci.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
index 4b9d5ed..bbf773c 100644
--- a/.github/workflows/ci.yml
+++ b/.github/workflows/ci.yml
@@ -165,7 +165,7 @@ jobs:
     #   if: steps.tc-isa-sim-cache.outputs.cache-hit != 'true'
     #   run: make riscv-isa-sim
     - name: Copy Spike
-      run: cp -Lr /usr/scratch2/tokyo/mperotti/tools/arathon/install/riscv-isa-sim install
+      run: cp -Lr $GITHUB_WORKSPACE/install/riscv-isa-sim install
     - name: Tar Spike
       run: tar -cvf tc-isa-sim.tar install/riscv-isa-sim
     - name: Upload Spike

From 1022af4605a391d92118bd0f511951a864f4befc Mon Sep 17 00:00:00 2001
From: Hong Pang <hopang@larain5.ee.ethz.ch>
Date: Mon, 3 Nov 2025 20:28:41 +0100
Subject: [PATCH 13/37] [CI] ci trial on toolchain

---
 .github/workflows/ci.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
index bbf773c..e1f1746 100644
--- a/.github/workflows/ci.yml
+++ b/.github/workflows/ci.yml
@@ -165,7 +165,7 @@ jobs:
     #   if: steps.tc-isa-sim-cache.outputs.cache-hit != 'true'
     #   run: make riscv-isa-sim
     - name: Copy Spike
-      run: cp -Lr $GITHUB_WORKSPACE/install/riscv-isa-sim install
+      run: cp -Lr $GITHUB_WORKSPACE/toolchain/riscv-isa-sim install
     - name: Tar Spike
       run: tar -cvf tc-isa-sim.tar install/riscv-isa-sim
     - name: Upload Spike

From 5a2d75efd2fe1d6c59a3303dbca9c8f585385ee3 Mon Sep 17 00:00:00 2001
From: Hong Pang <hopang@larain5.ee.ethz.ch>
Date: Mon, 3 Nov 2025 21:20:44 +0100
Subject: [PATCH 14/37] [spyglass] Fix license declaration

---
 hardware/spyglass/sdc/func.sdc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hardware/spyglass/sdc/func.sdc b/hardware/spyglass/sdc/func.sdc
index 3660b98..287db8d 100644
--- a/hardware/spyglass/sdc/func.sdc
+++ b/hardware/spyglass/sdc/func.sdc
@@ -1,4 +1,4 @@
-# Copyright 2022v ETH Zurich and University of Bologna.
+# Copyright 2022 ETH Zurich and University of Bologna.
 # Solderpad Hardware License, Version 0.51, see LICENSE for details.
 # SPDX-License-Identifier: SHL-0.51
 

From 4cde560e77ca1134475677564f88b9058016f6cd Mon Sep 17 00:00:00 2001
From: Hong Pang <hopang@larain5.ee.ethz.ch>
Date: Mon, 3 Nov 2025 21:34:52 +0100
Subject: [PATCH 15/37] [spyglass] Modify toolchain install flow

---
 .github/workflows/ci.yml | 138 +++++++++++++++++++--------------------
 1 file changed, 69 insertions(+), 69 deletions(-)

diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
index e1f1746..7254903 100644
--- a/.github/workflows/ci.yml
+++ b/.github/workflows/ci.yml
@@ -46,12 +46,12 @@ jobs:
         large-packages: true
         docker-images: true
         swap-storage: true
-    # - uses: actions/checkout@v4
-    # - name: Recover the submodule commit hash
-    #   id: recover_hash
-    #   run: |
-    #     git submodule status toolchain/riscv-llvm | cut -d' ' -f1
-    #     echo "tc-llvm-hash=`git submodule status toolchain/riscv-llvm | cut -d' ' -f1`" >> $GITHUB_ENV
+    - uses: actions/checkout@v4
+    - name: Recover the submodule commit hash
+      id: recover_hash
+      run: |
+        git submodule status toolchain/riscv-llvm | cut -d' ' -f1
+        echo "tc-llvm-hash=`git submodule status toolchain/riscv-llvm | cut -d' ' -f1`" >> $GITHUB_ENV
     - name: Cache the LLVM toolchain
       uses: actions/cache@v4
       id: tc-llvm-cache
@@ -62,20 +62,20 @@ jobs:
         key: ${{ runner.os }}-build-${{ env.cache-name }}-${{ env.tc-llvm-hash }}
         restore-keys:
           ${{ runner.os }}-build-${{ env.cache-name }}-${{ env.tc-llvm-hash }}
-    # - name: Download the LLVM toolchain
-    #   if: steps.tc-llvm-cache.outputs.cache-hit != 'true'
-    #   run: git submodule update --init --recursive --checkout -- toolchain/riscv-llvm
-    # - name: Download Newlib
-    #   if: steps.tc-llvm-cache.outputs.cache-hit != 'true'
-    #   run: git submodule update --init --recursive --checkout -- toolchain/newlib
-    # - name: Compile LLVM
-    #   if: steps.tc-llvm-cache.outputs.cache-hit != 'true'
-    #   run: |
-    #     sudo apt-get install libmpc-dev
-    #     sudo apt-get install -y ninja-build
-    #     CC=gcc CXX=g++ make toolchain-llvm
-    - name: Copy LLVM tools
-      run: cp -Lr /usr/scratch2/tokyo/mperotti/tools/arathon/install/riscv-llvm install
+    - name: Download the LLVM toolchain
+      if: steps.tc-llvm-cache.outputs.cache-hit != 'true'
+      run: git submodule update --init --recursive --checkout -- toolchain/riscv-llvm
+    - name: Download Newlib
+      if: steps.tc-llvm-cache.outputs.cache-hit != 'true'
+      run: git submodule update --init --recursive --checkout -- toolchain/newlib
+    - name: Compile LLVM
+      if: steps.tc-llvm-cache.outputs.cache-hit != 'true'
+      run: |
+        sudo apt-get install libmpc-dev
+        sudo apt-get install -y ninja-build
+        CC=gcc CXX=g++ make toolchain-llvm
+    # - name: Copy LLVM tools
+    #   run: cp -Lr /usr/scratch2/tokyo/mperotti/tools/arathon/install/riscv-llvm install
     - name: Tar LLVM
       run: tar -cvf tc-llvm.tar install/riscv-llvm
     - name: Upload LLVM
@@ -103,12 +103,12 @@ jobs:
         large-packages: true
         docker-images: true
         swap-storage: true
-    # - uses: actions/checkout@v4
-    # - name: Recover the submodule commit hash
-    #   id: recover_hash
-    #   run: |
-    #     git submodule status toolchain/riscv-gnu-toolchain | cut -d' ' -f1
-    #     echo "tc-gcc-hash=`git submodule status toolchain/riscv-gnu-toolchain | cut -d' ' -f1`" >> $GITHUB_ENV
+    - uses: actions/checkout@v4
+    - name: Recover the submodule commit hash
+      id: recover_hash
+      run: |
+        git submodule status toolchain/riscv-gnu-toolchain | cut -d' ' -f1
+        echo "tc-gcc-hash=`git submodule status toolchain/riscv-gnu-toolchain | cut -d' ' -f1`" >> $GITHUB_ENV
     - name: Cache the GCC toolchain
       uses: actions/cache@v4
       id: tc-gcc-cache
@@ -119,16 +119,16 @@ jobs:
         key: ${{ runner.os }}-build-${{ env.cache-name }}-${{ env.tc-gcc-hash }}
         restore-keys:
           ${{ runner.os }}-build-${{ env.cache-name }}-${{ env.tc-gcc-hash }}
-    # - name: Download the GCC toolchain
-    #   if: steps.tc-gcc-cache.outputs.cache-hit != 'true'
-    #   run: git submodule update --init --recursive --checkout -- toolchain/riscv-gnu-toolchain
-    # - name: Compile GCC
-    #   if: steps.tc-gcc-cache.outputs.cache-hit != 'true'
-    #   run: |
-    #     sudo apt-get install libmpc-dev
-    #     CC=gcc CXX=g++ make toolchain-gcc
-    - name: Copy GCC tools
-      run: cp -Lr /usr/scratch2/tokyo/mperotti/tools/arathon/install/riscv-gcc install
+    - name: Download the GCC toolchain
+      if: steps.tc-gcc-cache.outputs.cache-hit != 'true'
+      run: git submodule update --init --recursive --checkout -- toolchain/riscv-gnu-toolchain
+    - name: Compile GCC
+      if: steps.tc-gcc-cache.outputs.cache-hit != 'true'
+      run: |
+        sudo apt-get install libmpc-dev
+        CC=gcc CXX=g++ make toolchain-gcc
+    # - name: Copy GCC tools
+    #   run: cp -Lr /usr/scratch2/tokyo/mperotti/tools/arathon/install/riscv-gcc install
     - name: Tar GCC
       run: tar -cvf tc-gcc.tar install/riscv-gcc
     - name: Upload GCC
@@ -140,12 +140,12 @@ jobs:
   tc-isa-sim:
     runs-on: ubuntu-22.04
     steps:
-    # - uses: actions/checkout@v4
-    # - name: Recover the submodule commit hash
-    #   id: recover_hash
-    #   run: |
-    #     git submodule status toolchain/riscv-isa-sim | cut -d' ' -f1
-    #     echo "tc-isa-sim-hash=`git submodule status toolchain/riscv-isa-sim | cut -d' ' -f1`" >> $GITHUB_ENV
+    - uses: actions/checkout@v4
+    - name: Recover the submodule commit hash
+      id: recover_hash
+      run: |
+        git submodule status toolchain/riscv-isa-sim | cut -d' ' -f1
+        echo "tc-isa-sim-hash=`git submodule status toolchain/riscv-isa-sim | cut -d' ' -f1`" >> $GITHUB_ENV
     - name: Cache Spike
       uses: actions/cache@v4
       id: tc-isa-sim-cache
@@ -156,16 +156,16 @@ jobs:
         key: ${{ runner.os }}-build-${{ env.cache-name }}-${{ env.tc-isa-sim-hash }}
         restore-keys:
           ${{ runner.os }}-build-${{ env.cache-name }}-${{ env.tc-isa-sim-hash }}
-    # - name: Download Spike
-    #   if: steps.tc-isa-sim-cache.outputs.cache-hit != 'true'
-    #   run: |
-    #     git submodule update --init --recursive -- toolchain/riscv-isa-sim
-    #     git submodule foreach --recursive git reset --hard
-    # - name: Compile Spike
-    #   if: steps.tc-isa-sim-cache.outputs.cache-hit != 'true'
-    #   run: make riscv-isa-sim
-    - name: Copy Spike
-      run: cp -Lr $GITHUB_WORKSPACE/toolchain/riscv-isa-sim install
+    - name: Download Spike
+      if: steps.tc-isa-sim-cache.outputs.cache-hit != 'true'
+      run: |
+        git submodule update --init --recursive -- toolchain/riscv-isa-sim
+        git submodule foreach --recursive git reset --hard
+    - name: Compile Spike
+      if: steps.tc-isa-sim-cache.outputs.cache-hit != 'true'
+      run: make riscv-isa-sim
+    # - name: Copy Spike
+    #   run: cp -Lr $GITHUB_WORKSPACE/toolchain/riscv-isa-sim install
     - name: Tar Spike
       run: tar -cvf tc-isa-sim.tar install/riscv-isa-sim
     - name: Upload Spike
@@ -177,12 +177,12 @@ jobs:
   tc-verilator:
     runs-on: ubuntu-22.04
     steps:
-    # - uses: actions/checkout@v4
-    # - name: Recover the submodule commit hash
-    #   id: recover_hash
-    #   run: |
-    #     git submodule status toolchain/verilator | cut -d' ' -f1
-    #     echo "tc-verilator-hash=`git submodule status toolchain/verilator | cut -d' ' -f1`" >> $GITHUB_ENV
+    - uses: actions/checkout@v4
+    - name: Recover the submodule commit hash
+      id: recover_hash
+      run: |
+        git submodule status toolchain/verilator | cut -d' ' -f1
+        echo "tc-verilator-hash=`git submodule status toolchain/verilator | cut -d' ' -f1`" >> $GITHUB_ENV
     - name: Cache Verilator
       uses: actions/cache@v4
       id: tc-verilator-cache
@@ -193,17 +193,17 @@ jobs:
         key: ${{ runner.os }}-build-llvm10-${{ env.cache-name }}-${{ env.tc-verilator-hash }}
         restore-keys:
           ${{ runner.os }}-build-llvm10-${{ env.cache-name }}-${{ env.tc-verilator-hash }}
-    # - name: Download Verilator
-    #   if: steps.tc-verilator-cache.outputs.cache-hit != 'true'
-    #   run: |
-    #     git submodule update --init --recursive -- toolchain/verilator
-    # - name: Compile Verilator
-    #   if: steps.tc-verilator-cache.outputs.cache-hit != 'true'
-    #   run: |
-    #     sudo apt-get install flex libfl-dev help2man
-    #     make verilator
-    - name: Copy Verilator
-      run: cp -Lr /usr/scratch2/tokyo/mperotti/tools/arathon/install/verilator install
+    - name: Download Verilator
+      if: steps.tc-verilator-cache.outputs.cache-hit != 'true'
+      run: |
+        git submodule update --init --recursive -- toolchain/verilator
+    - name: Compile Verilator
+      if: steps.tc-verilator-cache.outputs.cache-hit != 'true'
+      run: |
+        sudo apt-get install flex libfl-dev help2man
+        make verilator
+    # - name: Copy Verilator
+    #   run: cp -Lr /usr/scratch2/tokyo/mperotti/tools/arathon/install/verilator install
     - name: Tar Verilator
       run: tar -cvf tc-verilator.tar install/verilator
     - name: Upload Verilator

From 13b36131ddaccb3c44ca3b3920b012370c51f083 Mon Sep 17 00:00:00 2001
From: Hong Pang <hopang@larain5.ee.ethz.ch>
Date: Mon, 3 Nov 2025 21:44:22 +0100
Subject: [PATCH 16/37] [makefile] update spike commit

---
 Makefile | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 76088c4..8d4e396 100644
--- a/Makefile
+++ b/Makefile
@@ -27,7 +27,8 @@ ISA_SIM_MOD_INSTALL_DIR ?= ${INSTALL_DIR}/riscv-isa-sim-mod
 VERIL_INSTALL_DIR       ?= ${INSTALL_DIR}/verilator
 RISCV_TESTS_INSTALL_DIR ?= ${INSTALL_DIR}/riscv_tests
 VERIL_VERSION           ?= v5.012
-DTC_COMMIT              ?= b6910bec11614980a21e46fbccc35934b671bd81
+# DTC_COMMIT              ?= b6910bec11614980a21e46fbccc35934b671bd81
+DTC_COMMIT              ?= 7f3184a6c550bb8fb59e93c9901d75dced889dcf
 
 CMAKE ?= cmake
 

From 348420f7f7c3e6d12db1539b1d67e82ec807a9a4 Mon Sep 17 00:00:00 2001
From: Hong Pang <hopang@larain5.ee.ethz.ch>
Date: Mon, 3 Nov 2025 21:57:22 +0100
Subject: [PATCH 17/37] [CI] try to clone dtc from github mirror

---
 .github/workflows/ci.yml | 3 ++-
 Makefile                 | 8 ++++----
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
index 7254903..18c94b7 100644
--- a/.github/workflows/ci.yml
+++ b/.github/workflows/ci.yml
@@ -163,7 +163,8 @@ jobs:
         git submodule foreach --recursive git reset --hard
     - name: Compile Spike
       if: steps.tc-isa-sim-cache.outputs.cache-hit != 'true'
-      run: make riscv-isa-sim
+      # run: make riscv-isa-sim
+      run: make riscv-isa-sim LDFLAGS="-static-libstdc++"
     # - name: Copy Spike
     #   run: cp -Lr $GITHUB_WORKSPACE/toolchain/riscv-isa-sim install
     - name: Tar Spike
diff --git a/Makefile b/Makefile
index 8d4e396..ee2a285 100644
--- a/Makefile
+++ b/Makefile
@@ -27,8 +27,8 @@ ISA_SIM_MOD_INSTALL_DIR ?= ${INSTALL_DIR}/riscv-isa-sim-mod
 VERIL_INSTALL_DIR       ?= ${INSTALL_DIR}/verilator
 RISCV_TESTS_INSTALL_DIR ?= ${INSTALL_DIR}/riscv_tests
 VERIL_VERSION           ?= v5.012
-# DTC_COMMIT              ?= b6910bec11614980a21e46fbccc35934b671bd81
-DTC_COMMIT              ?= 7f3184a6c550bb8fb59e93c9901d75dced889dcf
+DTC_COMMIT              ?= b6910bec11614980a21e46fbccc35934b671bd81
+# DTC_COMMIT              ?= 7f3184a6c550bb8fb59e93c9901d75dced889dcf
 
 CMAKE ?= cmake
 
@@ -146,7 +146,7 @@ ${ISA_SIM_MOD_INSTALL_DIR}: Makefile patches/0003-riscv-isa-sim-patch ${ISA_SIM_
 	# Spike was compiled successfully using gcc and g++ version 7.2.0.
 	cd toolchain/riscv-isa-sim && git stash && git apply ../../patches/0003-riscv-isa-sim-patch && \
 	rm -rf build && mkdir -p build && cd build; \
-	[ -d dtc ] || git clone https://git.kernel.org/pub/scm/utils/dtc/dtc.git && cd dtc && git checkout $(DTC_COMMIT); \
+	[ -d dtc ] || git clone https://github.com/dgibson/dtc.git dtc && cd dtc && git checkout $(DTC_COMMIT); \
 	make install SETUP_PREFIX=$(ISA_SIM_MOD_INSTALL_DIR) PREFIX=$(ISA_SIM_MOD_INSTALL_DIR) && \
 	PATH=$(ISA_SIM_MOD_INSTALL_DIR)/bin:$$PATH; cd ..; \
 	../configure --prefix=$(ISA_SIM_MOD_INSTALL_DIR) \
@@ -161,7 +161,7 @@ ${ISA_SIM_INSTALL_DIR}: Makefile
 	# make riscv-isa-sim LDFLAGS="-static-libstdc++"
 	# Spike was compiled successfully using gcc and g++ version 7.2.0.
 	cd toolchain/riscv-isa-sim && rm -rf build && mkdir -p build && cd build; \
-	[ -d dtc ] || git clone https://git.kernel.org/pub/scm/utils/dtc/dtc.git && cd dtc && git checkout $(DTC_COMMIT); \
+	[ -d dtc ] || git clone https://github.com/dgibson/dtc.git dtc && cd dtc && git checkout $(DTC_COMMIT); \
 	make install SETUP_PREFIX=$(ISA_SIM_INSTALL_DIR) PREFIX=$(ISA_SIM_INSTALL_DIR) && \
 	PATH=$(ISA_SIM_INSTALL_DIR)/bin:$$PATH; cd ..; \
 	../configure --prefix=$(ISA_SIM_INSTALL_DIR) \

From 881a2e9dca45634d698e62ca2856edd1ca61cb78 Mon Sep 17 00:00:00 2001
From: Hong Pang <hopang@larain5.ee.ethz.ch>
Date: Tue, 4 Nov 2025 00:08:34 +0100
Subject: [PATCH 18/37] [tb] Add cluster-related parameters in verilater tb

---
 hardware/tb/ara_tb_verilator.sv | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/hardware/tb/ara_tb_verilator.sv b/hardware/tb/ara_tb_verilator.sv
index e31c6ac..218ab6d 100644
--- a/hardware/tb/ara_tb_verilator.sv
+++ b/hardware/tb/ara_tb_verilator.sv
@@ -25,10 +25,22 @@ module ara_tb_verilator #(
    *  DUT  *
    *********/
 
+  // ara_testharness #(
+  //   .NrLanes     (NrLanes         ),
+  //   .AxiAddrWidth(AxiAddrWidth    ),
+  //   .AxiDataWidth(AxiWideDataWidth)
+  // ) dut (
+  //   .clk_i (clk_i ),
+  //   .rst_ni(rst_ni),
+  //   .exit_o(exit_o)
+  // );
+
   ara_testharness #(
     .NrLanes     (NrLanes         ),
+    .NrClusters  (NrClusters      ),
     .AxiAddrWidth(AxiAddrWidth    ),
-    .AxiDataWidth(AxiWideDataWidth)
+    .AxiDataWidth(AxiWideDataWidth),
+    .ClusterAxiDataWidth(ClusterAxiDataWidth)
   ) dut (
     .clk_i (clk_i ),
     .rst_ni(rst_ni),

From 49659b6c940ea5ddf70a97914be5a49048023e5c Mon Sep 17 00:00:00 2001
From: Hong Pang <hopang@larain5.ee.ethz.ch>
Date: Tue, 4 Nov 2025 00:25:31 +0100
Subject: [PATCH 19/37] [verilator] add cluster-related parameters verilator tb

---
 hardware/Makefile               |  2 ++
 hardware/tb/ara_tb_verilator.sv | 10 +++++++---
 2 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/hardware/Makefile b/hardware/Makefile
index a4ac10f..d3d3a2c 100644
--- a/hardware/Makefile
+++ b/hardware/Makefile
@@ -213,6 +213,7 @@ $(veril_library)/V$(veril_top): $(config_file) Makefile ../Bender.yml $(shell fi
 # Verilate the design
 	$(veril_path)/verilator -f $(veril_library)/bender_script_$(config)           \
   -GNrLanes=$(nr_lanes)                                                         \
+  -GNrClusters=$(nr_clusters)																										\
   -O3                                                                           \
   -Wno-fatal                                                                    \
   -Wno-PINCONNECTEMPTY                                                          \
@@ -235,6 +236,7 @@ $(veril_library)/V$(veril_top): $(config_file) Makefile ../Bender.yml $(shell fi
   --compiler clang                                                              \
   -CFLAGS "-DTOPLEVEL_NAME=$(veril_top)"                                        \
   -CFLAGS "-DNR_LANES=$(nr_lanes)"                                              \
+  -CFLAGS "-DNR_CLUSTERS=$(nr_clusters)"                                        \
   -CFLAGS -I$(ROOT_DIR)/tb/verilator/lowrisc_dv_verilator_memutil_dpi/cpp       \
   -CFLAGS -I$(ROOT_DIR)/tb/verilator/lowrisc_dv_verilator_memutil_verilator/cpp \
   -CFLAGS -I$(ROOT_DIR)/tb/verilator/lowrisc_dv_verilator_simutil_verilator/cpp \
diff --git a/hardware/tb/ara_tb_verilator.sv b/hardware/tb/ara_tb_verilator.sv
index 218ab6d..e0b136a 100644
--- a/hardware/tb/ara_tb_verilator.sv
+++ b/hardware/tb/ara_tb_verilator.sv
@@ -7,7 +7,8 @@
 // Description: Top level testbench module for Verilator.
 
 module ara_tb_verilator #(
-    parameter int unsigned NrLanes = 0
+    parameter int unsigned NrLanes = 0,
+    parameter int unsigned NrClusters = 0
   )(
     input  logic        clk_i,
     input  logic        rst_ni,
@@ -18,8 +19,11 @@ module ara_tb_verilator #(
    *  Definitions  *
    *****************/
 
-  localparam AxiAddrWidth     = 64;
-  localparam AxiWideDataWidth = 64 * NrLanes / 2;
+  // localparam AxiAddrWidth     = 64;
+  // localparam AxiWideDataWidth = 64 * NrLanes / 2;
+  localparam AxiAddrWidth          = 64;
+  localparam AxiWideDataWidth      = 32 * NrLanes * NrClusters;
+  localparam ClusterAxiDataWidth   = 32 * NrLanes;
 
   /*********
    *  DUT  *

From 1d9bb98f308a728535c2dee09cee696b6130bce7 Mon Sep 17 00:00:00 2001
From: Hong Pang <hopang@larain5.ee.ethz.ch>
Date: Tue, 4 Nov 2025 00:58:51 +0100
Subject: [PATCH 20/37] [verilater] update dram word width to
 32*NrLanes*NrClusters

---
 hardware/tb/verilator/ara_tb.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hardware/tb/verilator/ara_tb.cpp b/hardware/tb/verilator/ara_tb.cpp
index 6f27c68..99ae0b2 100644
--- a/hardware/tb/verilator/ara_tb.cpp
+++ b/hardware/tb/verilator/ara_tb.cpp
@@ -26,7 +26,7 @@ int main(int argc, char **argv) {
   // Initialize the DRAM
   MemAreaLoc l2_mem = {.base=0x80000000, .size=0x00100000};
   memutil.RegisterMemoryArea(
-                             "ram", "TOP.ara_tb_verilator.dut.i_ara_soc.i_dram", 64*NR_LANES/2, &l2_mem);
+                             "ram", "TOP.ara_tb_verilator.dut.i_ara_soc.i_dram", 32*NrLanes*NrClusters, &l2_mem);
   simctrl.RegisterExtension(&memutil);
 
   simctrl.SetInitialResetDelay(5);

From 1c8c60e056db4e47878c0853b3805b207a1ad82c Mon Sep 17 00:00:00 2001
From: Hong Pang <hopang@larain5.ee.ethz.ch>
Date: Tue, 4 Nov 2025 01:25:24 +0100
Subject: [PATCH 21/37] [verilator] change the ways how parameters are passed
 to top level tb

---
 hardware/Makefile | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hardware/Makefile b/hardware/Makefile
index d3d3a2c..7d1c032 100644
--- a/hardware/Makefile
+++ b/hardware/Makefile
@@ -212,8 +212,8 @@ $(veril_library)/V$(veril_top): $(config_file) Makefile ../Bender.yml $(shell fi
 	$(BENDER) script verilator $(bender_targs_veril) $(bender_defs) > $(veril_library)/bender_script_$(config)
 # Verilate the design
 	$(veril_path)/verilator -f $(veril_library)/bender_script_$(config)           \
-  -GNrLanes=$(nr_lanes)                                                         \
-  -GNrClusters=$(nr_clusters)																										\
+  -Gara_tb_verilator.NrLanes=2 																									\
+	-Gara_tb_verilator.NrClusters=4 																							\
   -O3                                                                           \
   -Wno-fatal                                                                    \
   -Wno-PINCONNECTEMPTY                                                          \

From 62eca9e0c3a1bd02753070b35b1966ca594885d6 Mon Sep 17 00:00:00 2001
From: Hong Pang <hopang@larain5.ee.ethz.ch>
Date: Tue, 4 Nov 2025 01:30:50 +0100
Subject: [PATCH 22/37] [verilator] pass NrLanes and NrClusters with defined
 value

---
 hardware/tb/ara_tb_verilator.sv | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hardware/tb/ara_tb_verilator.sv b/hardware/tb/ara_tb_verilator.sv
index e0b136a..6c3cc9a 100644
--- a/hardware/tb/ara_tb_verilator.sv
+++ b/hardware/tb/ara_tb_verilator.sv
@@ -7,8 +7,8 @@
 // Description: Top level testbench module for Verilator.
 
 module ara_tb_verilator #(
-    parameter int unsigned NrLanes = 0,
-    parameter int unsigned NrClusters = 0
+    parameter int unsigned NrLanes    = `NR_LANES,
+    parameter int unsigned NrClusters = `NR_CLUSTERS
   )(
     input  logic        clk_i,
     input  logic        rst_ni,

From adae12d516c91e2fbb5cfb4b6011b7810a25b505 Mon Sep 17 00:00:00 2001
From: Hong Pang <hopang@larain5.ee.ethz.ch>
Date: Tue, 4 Nov 2025 01:34:38 +0100
Subject: [PATCH 23/37] [verilator] remove GNrLanes and GNrClusters define

---
 hardware/Makefile | 2 --
 1 file changed, 2 deletions(-)

diff --git a/hardware/Makefile b/hardware/Makefile
index 7d1c032..7f78781 100644
--- a/hardware/Makefile
+++ b/hardware/Makefile
@@ -212,8 +212,6 @@ $(veril_library)/V$(veril_top): $(config_file) Makefile ../Bender.yml $(shell fi
 	$(BENDER) script verilator $(bender_targs_veril) $(bender_defs) > $(veril_library)/bender_script_$(config)
 # Verilate the design
 	$(veril_path)/verilator -f $(veril_library)/bender_script_$(config)           \
-  -Gara_tb_verilator.NrLanes=2 																									\
-	-Gara_tb_verilator.NrClusters=4 																							\
   -O3                                                                           \
   -Wno-fatal                                                                    \
   -Wno-PINCONNECTEMPTY                                                          \

From a763aa7881fbdfa1f05ab1d6db6309a3f6579ff0 Mon Sep 17 00:00:00 2001
From: Hong Pang <hopang@larain5.ee.ethz.ch>
Date: Tue, 4 Nov 2025 01:40:56 +0100
Subject: [PATCH 24/37] [verilator] fix parameter name unmatch

---
 hardware/tb/verilator/ara_tb.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hardware/tb/verilator/ara_tb.cpp b/hardware/tb/verilator/ara_tb.cpp
index 99ae0b2..ac5954a 100644
--- a/hardware/tb/verilator/ara_tb.cpp
+++ b/hardware/tb/verilator/ara_tb.cpp
@@ -26,7 +26,7 @@ int main(int argc, char **argv) {
   // Initialize the DRAM
   MemAreaLoc l2_mem = {.base=0x80000000, .size=0x00100000};
   memutil.RegisterMemoryArea(
-                             "ram", "TOP.ara_tb_verilator.dut.i_ara_soc.i_dram", 32*NrLanes*NrClusters, &l2_mem);
+                             "ram", "TOP.ara_tb_verilator.dut.i_ara_soc.i_dram", 32*Nr_Lanes*Nr_Clusters, &l2_mem);
   simctrl.RegisterExtension(&memutil);
 
   simctrl.SetInitialResetDelay(5);

From 0486a0cdff625c86e4cfa91f5a131991eb711887 Mon Sep 17 00:00:00 2001
From: Hong Pang <hopang@larain5.ee.ethz.ch>
Date: Tue, 4 Nov 2025 01:47:37 +0100
Subject: [PATCH 25/37] [verilator] fix parameter name unmatch

---
 hardware/tb/verilator/ara_tb.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hardware/tb/verilator/ara_tb.cpp b/hardware/tb/verilator/ara_tb.cpp
index ac5954a..9eab8a7 100644
--- a/hardware/tb/verilator/ara_tb.cpp
+++ b/hardware/tb/verilator/ara_tb.cpp
@@ -26,7 +26,7 @@ int main(int argc, char **argv) {
   // Initialize the DRAM
   MemAreaLoc l2_mem = {.base=0x80000000, .size=0x00100000};
   memutil.RegisterMemoryArea(
-                             "ram", "TOP.ara_tb_verilator.dut.i_ara_soc.i_dram", 32*Nr_Lanes*Nr_Clusters, &l2_mem);
+                             "ram", "TOP.ara_tb_verilator.dut.i_ara_soc.i_dram", 32*NR_LANES*NR_CLUSTERS, &l2_mem);
   simctrl.RegisterExtension(&memutil);
 
   simctrl.SetInitialResetDelay(5);

From 2837f772d9ac2b4d315fc6f0e81b15911f37d9c3 Mon Sep 17 00:00:00 2001
From: Hong Pang <hopang@larain5.ee.ethz.ch>
Date: Tue, 4 Nov 2025 09:30:15 +0100
Subject: [PATCH 26/37] [config] temporarily limit NrLanes to 16 in total

---
 config/16_lanes.mk | 2 +-
 config/8_lanes.mk  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/config/16_lanes.mk b/config/16_lanes.mk
index 3c520d0..86a776e 100644
--- a/config/16_lanes.mk
+++ b/config/16_lanes.mk
@@ -20,7 +20,7 @@
 # Number of vector lanes
 nr_lanes ?= 16
 # Number of clusters
-nr_clusters ?= 4
+nr_clusters ?= 1
 
 # Length of each vector register (in bits)
 # Constraints: VLEN > 128
diff --git a/config/8_lanes.mk b/config/8_lanes.mk
index b07a3b9..b6b9f97 100644
--- a/config/8_lanes.mk
+++ b/config/8_lanes.mk
@@ -20,7 +20,7 @@
 # Number of vector lanes
 nr_lanes ?= 8
 # Number of clusters
-nr_clusters ?= 4
+nr_clusters ?= 2
 
 # Length of each vector register (in bits)
 # Constraints: VLEN > 128

From 8944f39e3497ca45cedd7683b4c468ee5b89c4c6 Mon Sep 17 00:00:00 2001
From: Hong Pang <hopang@larain5.ee.ethz.ch>
Date: Tue, 4 Nov 2025 10:42:34 +0100
Subject: [PATCH 27/37] [apps] Add riscv-test header file and makefile

---
 apps/common/riscv_test.h   | 98 ++++++++++++++++++++++++++++++++++++++
 apps/common/riscv_tests.mk | 33 +++++++++++++
 2 files changed, 131 insertions(+)
 create mode 100644 apps/common/riscv_test.h
 create mode 100644 apps/common/riscv_tests.mk

diff --git a/apps/common/riscv_test.h b/apps/common/riscv_test.h
new file mode 100644
index 0000000..59ec2e2
--- /dev/null
+++ b/apps/common/riscv_test.h
@@ -0,0 +1,98 @@
+#ifndef _ENV_ARIANE_H
+#define _ENV_ARIANE_H
+
+#include "encoding.h"
+
+//-----------------------------------------------------------------------
+// Begin Macro
+//-----------------------------------------------------------------------
+
+#define RVTEST_RV64U
+
+#define RVTEST_RV64UF                                                          \
+  .globl rvtest_init;                                                          \
+  rvtest_init:                                                                 \
+  RVTEST_FP_ENABLE;                                                            \
+  ret
+
+#define RVTEST_RV64UV                                                          \
+  .globl rvtest_init;                                                          \
+  rvtest_init:                                                                 \
+  RVTEST_VECTOR_ENABLE;                                                        \
+  ret
+
+#define RVTEST_RV64M                                                           \
+  .globl rvtest_init;                                                          \
+  rvtest_init:                                                                 \
+  RVTEST_ENABLE_MACHINE;                                                       \
+  ret
+
+#define RVTEST_RV64S                                                           \
+  .globl rvtest_init;                                                          \
+  rvtest_init:                                                                 \
+  RVTEST_ENABLE_SUPERVISOR;                                                    \
+  ret
+
+#define RVTEST_ENABLE_SUPERVISOR                                               \
+  li a0, MSTATUS_MPP &(MSTATUS_MPP >> 1);                                      \
+  csrs mstatus, a0;                                                            \
+  li a0, SIP_SSIP | SIP_STIP;                                                  \
+  csrs mideleg, a0;
+
+#define RVTEST_ENABLE_MACHINE                                                  \
+  li a0, MSTATUS_MPP;                                                          \
+  csrs mstatus, a0;
+
+#define RVTEST_FP_ENABLE                                                       \
+  li a0, MSTATUS_FS &(MSTATUS_FS >> 1);                                        \
+  csrs mstatus, a0;                                                            \
+  csrwi fcsr, 0
+
+#define RVTEST_VECTOR_ENABLE                                                   \
+  li a0, (MSTATUS_VS & (MSTATUS_VS >> 1)) | (MSTATUS_FS & (MSTATUS_FS >> 1));  \
+  csrs mstatus, a0;                                                            \
+  csrwi fcsr, 0;                                                               \
+  csrwi vcsr, 0;
+
+#define RISCV_MULTICORE_DISABLE                                                \
+  csrr a0, mhartid;                                                            \
+  1 : bnez a0, 1b
+
+#define RVTEST_CODE_BEGIN                                                      \
+  .globl main;                                                                 \
+  .align 2;                                                                    \
+  main:
+
+//-----------------------------------------------------------------------
+// End Macro
+//-----------------------------------------------------------------------
+
+#define RVTEST_CODE_END unimp
+
+//-----------------------------------------------------------------------
+// Pass/Fail Macro
+//-----------------------------------------------------------------------
+
+#define RVTEST_PASS                                                            \
+  li a0, 0;                                                                    \
+  j _eoc
+
+#define TESTNUM gp
+#define RVTEST_FAIL                                                            \
+  fence;                                                                       \
+  1 : beqz TESTNUM, 1b;                                                        \
+  sll TESTNUM, TESTNUM, 1;                                                     \
+  or TESTNUM, TESTNUM, 1;                                                      \
+  addi a0, TESTNUM, 0;                                                         \
+  j _fail
+
+//-----------------------------------------------------------------------
+// Data Section Macro
+//-----------------------------------------------------------------------
+
+#define EXTRA_DATA
+
+#define RVTEST_DATA_BEGIN
+#define RVTEST_DATA_END
+
+#endif
diff --git a/apps/common/riscv_tests.mk b/apps/common/riscv_tests.mk
new file mode 100644
index 0000000..adf0ada
--- /dev/null
+++ b/apps/common/riscv_tests.mk
@@ -0,0 +1,33 @@
+#=======================================================================
+# Makefrag for instructions employed in CVA6
+#-----------------------------------------------------------------------
+
+include $(TESTS_DIR)/rv64ui/Makefrag
+include $(TESTS_DIR)/rv64uc/Makefrag
+include $(TESTS_DIR)/rv64um/Makefrag
+include $(TESTS_DIR)/rv64ua/Makefrag
+include $(TESTS_DIR)/rv64uf/Makefrag
+include $(TESTS_DIR)/rv64ud/Makefrag
+include $(TESTS_DIR)/rv64uv/Makefrag
+include $(TESTS_DIR)/rv64si/Makefrag
+
+rv64ui_ara_tests := $(addprefix rv64ui-ara-, $(rv64ui_sc_tests))
+rv64um_ara_tests := $(addprefix rv64um-ara-, $(rv64um_sc_tests))
+rv64ua_ara_tests := $(addprefix rv64ua-ara-, $(rv64ua_sc_tests))
+rv64uc_ara_tests := $(addprefix rv64uc-ara-, $(rv64uc_sc_tests))
+rv64uf_ara_tests := $(addprefix rv64uf-ara-, $(rv64uf_sc_tests))
+rv64ud_ara_tests := $(addprefix rv64ud-ara-, $(rv64ud_sc_tests))
+rv64uv_ara_tests := $(addprefix rv64uv-ara-, $(rv64uv_sc_tests))
+rv64si_ara_tests := $(addprefix rv64si-ara-, $(rv64si_sc_tests))
+
+cva6_tests := $(rv64ui_ara_tests) \
+							$(rv64um_ara_tests) \
+							$(rv64uc_ara_tests) \
+							$(rv64uf_ara_tests) \
+							$(rv64ud_ara_tests) \
+							$(rv64si_ara_tests)
+
+# Atomics are messy, since there is currently no memory region capable of handling them
+#							$(rv64ua_ara_tests) \
+
+ara_tests := $(rv64uv_ara_tests)

From 3b2ad21a32e6613ef08d4c53f10efa9f3c05150c Mon Sep 17 00:00:00 2001
From: Hong Pang <hopang@larain5.ee.ethz.ch>
Date: Tue, 4 Nov 2025 11:12:22 +0100
Subject: [PATCH 28/37] [riscv-tests] Include riscv-test makefile in apps
 makefile

---
 apps/Makefile                  | 1 +
 hardware/src/ara_dispatcher.sv | 6 ++++--
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/apps/Makefile b/apps/Makefile
index 7413a13..b1751ad 100644
--- a/apps/Makefile
+++ b/apps/Makefile
@@ -23,6 +23,7 @@ TESTS_DIR := $(ROOT_DIR)/riscv-tests/isa
 
 # This will overwrite the ROOT_DIR variable from the included makefile
 include $(COMMON_DIR)/runtime.mk
+include $(COMMON_DIR)/riscv_tests.mk
 include $(COMMON_DIR)/default_args.mk
 
 # Number of clusters
diff --git a/hardware/src/ara_dispatcher.sv b/hardware/src/ara_dispatcher.sv
index 992c9f3..8b3cc90 100644
--- a/hardware/src/ara_dispatcher.sv
+++ b/hardware/src/ara_dispatcher.sv
@@ -246,8 +246,10 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
   elen_t vfmvfs_result;
 
   vlen_t total_cluster_pieces;
+  id_cluster_t total_cluster_pieces_id;
   // assign total_cluster_pieces = vlen_t'(acc_req_i.rs1) >> $clog2(VLENB >> vtype_d.vsew);
   assign total_cluster_pieces = vlen_t'(acc_req_i.rs1) >> $clog2(NrLanes);
+  assign total_cluster_pieces_id = (NrClusters > 1) ? total_cluster_pieces[$clog2(NrClusters) - 1 : 0] : 0;
 
   vlen_t check_total_cluster_pieces;
   assign check_total_cluster_pieces = ((total_cluster_pieces >> $clog2(NrClusters)) + 1) * NrLanes;
@@ -532,9 +534,9 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
                         // Return the new vl
                         acc_resp_o.result = vl_d << num_clusters_i;
                       end else begin
-                        if (cluster_id_i < total_cluster_pieces[$clog2(NrClusters) - 1 : 0]) begin
+                        if (cluster_id_i < total_cluster_pieces_id) begin
                           vl_d = ((total_cluster_pieces >> $clog2(NrClusters)) + 1) * NrLanes;
-                        end else if (cluster_id_i == total_cluster_pieces[$clog2(NrClusters) - 1 : 0]) begin
+                        end else if (cluster_id_i == total_cluster_pieces_id) begin
                           vl_d = (total_cluster_pieces >> $clog2(NrClusters)) * NrLanes + 
                                   acc_req_i.rs1 % NrLanes;
                         end else begin

From 76fe0049ec1bed4ac1fcfeadbd3f76a845862fdd Mon Sep 17 00:00:00 2001
From: Hong Pang <hopang@larain5.ee.ethz.ch>
Date: Tue, 4 Nov 2025 17:22:34 +0100
Subject: [PATCH 29/37] [HW] adapt suhffle stage to support single cluster

---
 .github/workflows/ci.yml           |   2 +-
 hardware/src/ara_dispatcher.sv     |  11 +-
 hardware/src/vlsu/shuffle_stage.sv | 866 +++++++++++++++--------------
 3 files changed, 444 insertions(+), 435 deletions(-)

diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
index 18c94b7..81258d8 100644
--- a/.github/workflows/ci.yml
+++ b/.github/workflows/ci.yml
@@ -343,7 +343,7 @@ jobs:
     strategy:
       max-parallel: 1
       matrix:
-        app:        [hello_world, imatmul, fmatmul, iconv2d, fconv2d, fconv3d, jacobi2d, dropout, fft, dwt, exp, softmax, dotproduct, fdotproduct, pathfinder, roi_align, lavamd]
+        app:        [hello_world, imatmul, fmatmul, iconv2d, fconv2d, jacobi2d, exp, softmax, dotproduct, fdotproduct, fconv3d, pathfinder, roi_align, lavamd, dwt, dropout, fft, gemv]
         ara_config: [2_lanes, 4_lanes, 8_lanes, 16_lanes]
     needs: ["compile-ara", "compile-apps"]
     steps:
diff --git a/hardware/src/ara_dispatcher.sv b/hardware/src/ara_dispatcher.sv
index 8b3cc90..e25a7ca 100644
--- a/hardware/src/ara_dispatcher.sv
+++ b/hardware/src/ara_dispatcher.sv
@@ -223,7 +223,7 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
   // NP2 Slide support
   logic is_stride_np2;
   // logic [idx_width(idx_width(VLENB << 3)):0] sldu_popc;
-  logic [$clog2(NrLanes)-1:0] sldu_popc;
+  logic [$clog2($clog2(NrLanes)):0] sldu_popc;
 
   // Is the stride power of two?
   popcount #(
@@ -233,7 +233,7 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
   ) i_np2_stride (
     //.data_i    (ara_req_d.stride[idx_width(VLENB << 3)-1:0]),
     .data_i      (ara_req_d.stride[$clog2(NrLanes)-1:0]    ),
-    .popcount_o(sldu_popc                                  )
+    .popcount_o  (sldu_popc                                )
   );
 
   assign is_stride_np2 = sldu_popc > 1;
@@ -249,7 +249,12 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
   id_cluster_t total_cluster_pieces_id;
   // assign total_cluster_pieces = vlen_t'(acc_req_i.rs1) >> $clog2(VLENB >> vtype_d.vsew);
   assign total_cluster_pieces = vlen_t'(acc_req_i.rs1) >> $clog2(NrLanes);
-  assign total_cluster_pieces_id = (NrClusters > 1) ? total_cluster_pieces[$clog2(NrClusters) - 1 : 0] : 0;
+
+  if (NrClusters > 1) begin
+    assign total_cluster_pieces_id = total_cluster_pieces[$clog2(NrClusters) - 1 : 0];
+  end else begin
+    assign total_cluster_pieces_id = 0;
+  end
 
   vlen_t check_total_cluster_pieces;
   assign check_total_cluster_pieces = ((total_cluster_pieces >> $clog2(NrClusters)) + 1) * NrLanes;
diff --git a/hardware/src/vlsu/shuffle_stage.sv b/hardware/src/vlsu/shuffle_stage.sv
index abe0056..a232215 100644
--- a/hardware/src/vlsu/shuffle_stage.sv
+++ b/hardware/src/vlsu/shuffle_stage.sv
@@ -38,491 +38,495 @@ module shuffle_stage import ara_pkg::*; import rvv_pkg::*;  #(
   output  axi_resp_t [NrClusters-1:0] axi_resp_o
 );
 
-localparam int unsigned MAXVL_CL = VLEN * NrClusters;
-typedef logic [$clog2(MAXVL_CL+1)-1:0] vlen_cl_t;
-
-typedef struct packed {
-  axi_addr_t addr;
-  vlen_t [NrClusters-1:0] len;
-  elen_t stride;
-  vew_e vew;
-  logic is_load;
-  logic is_burst;
-  logic [NumStages-1:0] shuffle_en;
-  logic buffer_en;
-  logic valid;
-} req_track_t;
-
-localparam int unsigned NumTrackers=8;
-typedef logic [$clog2(NumTrackers)-1:0] pnt_t; 
-typedef logic [$clog2(NumTrackers):0] cnt_t; 
-
-req_track_t [NumTrackers-1:0] rd_tracker_d, rd_tracker_q;
-pnt_t rd_accept_pnt_d, rd_accept_pnt_q;
-pnt_t [NumStages-1:0] rd_issue_pnt_d, rd_issue_pnt_q;
-cnt_t rd_cnt_d, rd_cnt_q;
-
-req_track_t [NumTrackers-1:0] wr_tracker_d, wr_tracker_q;
-pnt_t wr_accept_pnt_d, wr_accept_pnt_q;
-pnt_t [NumStages-1:0] wr_issue_pnt_d, wr_issue_pnt_q;
-cnt_t wr_cnt_d, wr_cnt_q;
-
-typedef axi_r_t [NrClusters-1:0] stage_r_t;
-stage_r_t [NumStages-1:0] r_data_in, r_data_out;
-
-typedef axi_w_t [NrClusters-1:0] stage_w_t; 
-stage_w_t [NumStages-1:0] w_data_in, w_data_out;
-
-logic [NumStages-1:0] r_valid, r_ready, w_valid, w_ready;
-logic [NumStages-1:0] r_shuffle_en, w_shuffle_en;
-
-logic [NrClusters-1:0] r_ready_i, r_valid_o;
-logic [NrClusters-1:0] w_valid_i, w_ready_o;
-
-logic rd_full, wr_full;
-assign rd_full = (rd_cnt_q >= NumTrackers);
-assign wr_full = (wr_cnt_q >= NumTrackers);
-
-// To handle cases where vlsu of each cluster is ready to 
-// receive read resp or not.
-stream_fork #(
-  .N_OUP(NrClusters)
-) i_cluster_stream_fork (
-  .clk_i  (clk_i), 
-  .rst_ni (rst_ni),
-  .valid_o(r_valid_o            ),
-  .valid_i(r_valid[NumStages-1] ), 
-  .ready_i(r_ready_i            ),
-  .ready_o(r_ready[NumStages-1] )
-);
-
-// To handle cases where write data does not come simultaneously 
-// from all the clusters
-stream_join #(
-  .N_INP(NrClusters)
-) i_cluster_stream_join (
-  .inp_ready_o(w_ready_o),
-  .inp_valid_i(w_valid_i),
-  .oup_ready_i(w_ready[0]),
-  .oup_valid_o(w_valid[0])
-);
+if (NrClusters == 1) begin 
+  assign axi_req_o  = axi_req_i;
+  assign axi_resp_o = axi_resp_i;
+end else begin
+  localparam int unsigned MAXVL_CL = VLEN * NrClusters;
+  typedef logic [$clog2(MAXVL_CL+1)-1:0] vlen_cl_t;
+
+  typedef struct packed {
+    axi_addr_t addr;
+    vlen_t [NrClusters-1:0] len;
+    elen_t stride;
+    vew_e vew;
+    logic is_load;
+    logic is_burst;
+    logic [NumStages-1:0] shuffle_en;
+    logic buffer_en;
+    logic valid;
+  } req_track_t;
+
+  localparam int unsigned NumTrackers=8;
+  typedef logic [$clog2(NumTrackers)-1:0] pnt_t; 
+  typedef logic [$clog2(NumTrackers):0] cnt_t; 
+
+  req_track_t [NumTrackers-1:0] rd_tracker_d, rd_tracker_q;
+  pnt_t rd_accept_pnt_d, rd_accept_pnt_q;
+  pnt_t [NumStages-1:0] rd_issue_pnt_d, rd_issue_pnt_q;
+  cnt_t rd_cnt_d, rd_cnt_q;
+
+  req_track_t [NumTrackers-1:0] wr_tracker_d, wr_tracker_q;
+  pnt_t wr_accept_pnt_d, wr_accept_pnt_q;
+  pnt_t [NumStages-1:0] wr_issue_pnt_d, wr_issue_pnt_q;
+  cnt_t wr_cnt_d, wr_cnt_q;
+
+  typedef axi_r_t [NrClusters-1:0] stage_r_t;
+  stage_r_t [NumStages-1:0] r_data_in, r_data_out;
+
+  typedef axi_w_t [NrClusters-1:0] stage_w_t; 
+  stage_w_t [NumStages-1:0] w_data_in, w_data_out;
+
+  logic [NumStages-1:0] r_valid, r_ready, w_valid, w_ready;
+  logic [NumStages-1:0] r_shuffle_en, w_shuffle_en;
+
+  logic [NrClusters-1:0] r_ready_i, r_valid_o;
+  logic [NrClusters-1:0] w_valid_i, w_ready_o;
+
+  logic rd_full, wr_full;
+  assign rd_full = (rd_cnt_q >= NumTrackers);
+  assign wr_full = (wr_cnt_q >= NumTrackers);
+
+  // To handle cases where vlsu of each cluster is ready to 
+  // receive read resp or not.
+  stream_fork #(
+    .N_OUP(NrClusters)
+  ) i_cluster_stream_fork (
+    .clk_i  (clk_i), 
+    .rst_ni (rst_ni),
+    .valid_o(r_valid_o            ),
+    .valid_i(r_valid[NumStages-1] ), 
+    .ready_i(r_ready_i            ),
+    .ready_o(r_ready[NumStages-1] )
+  );
 
-for (genvar s=0; s<NumStages; s++) begin : p_stage
-
-  // Shuffling read data
-  shuffle #(
-    .NrLanes             (NrLanes),
-    .NrClusters          (NrClusters                  ),  
-    .ClusterAxiDataWidth (ClusterAxiDataWidth         ),
-    .T                   (stage_r_t                   ),
-    .scale               (s                           ),
-    .isRead              (1                           )
-  ) i_shuffle_rd (
-    .data_i       ( r_data_in  [s]  ),
-    .data_o       ( r_data_out [s]  ),
-    .enable_i     ( r_shuffle_en [s]  )
+  // To handle cases where write data does not come simultaneously 
+  // from all the clusters
+  stream_join #(
+    .N_INP(NrClusters)
+  ) i_cluster_stream_join (
+    .inp_ready_o(w_ready_o),
+    .inp_valid_i(w_valid_i),
+    .oup_ready_i(w_ready[0]),
+    .oup_valid_o(w_valid[0])
   );
 
-  if (s >= 1) begin
-    stream_register #(
-      .T       (stage_r_t)
-    ) i_shuffle_reg_r  (
-      .clk_i      ( clk_i                     ),
-      .rst_ni     ( rst_ni                    ),
-      .clr_i      ( 1'b0                      ),
-      .testmode_i ( 1'b0                      ),
-      // Input
-      .valid_i    ( r_valid    [s-1]          ),
-      .ready_o    ( r_ready    [s-1]          ),
-      .data_i     ( r_data_out [s-1]          ),
-      // Output
-      .valid_o    ( r_valid    [s]            ),
-      .ready_i    ( r_ready    [s]            ),
-      .data_o     ( r_data_in  [s]            )
+  for (genvar s=0; s<NumStages; s++) begin : p_stage
+
+    // Shuffling read data
+    shuffle #(
+      .NrLanes             (NrLanes),
+      .NrClusters          (NrClusters                  ),  
+      .ClusterAxiDataWidth (ClusterAxiDataWidth         ),
+      .T                   (stage_r_t                   ),
+      .scale               (s                           ),
+      .isRead              (1                           )
+    ) i_shuffle_rd (
+      .data_i       ( r_data_in  [s]  ),
+      .data_o       ( r_data_out [s]  ),
+      .enable_i     ( r_shuffle_en [s]  )
     );
-  end
 
-  // Shuffling write data
-  shuffle #(
-    .NrLanes             (NrLanes),
-    .NrClusters          (NrClusters                  ),  
-    .ClusterAxiDataWidth (ClusterAxiDataWidth         ),
-    .T                   (stage_w_t                   ),
-    .scale               (s                           ),
-    .isRead              (0                           )
-  ) i_shuffle_wr (
-    .data_i       ( w_data_in  [s]    ),
-    .data_o       ( w_data_out [s]    ),
-    .enable_i     ( w_shuffle_en [s]  )
-  );
+    if (s >= 1) begin
+      stream_register #(
+        .T       (stage_r_t)
+      ) i_shuffle_reg_r  (
+        .clk_i      ( clk_i                     ),
+        .rst_ni     ( rst_ni                    ),
+        .clr_i      ( 1'b0                      ),
+        .testmode_i ( 1'b0                      ),
+        // Input
+        .valid_i    ( r_valid    [s-1]          ),
+        .ready_o    ( r_ready    [s-1]          ),
+        .data_i     ( r_data_out [s-1]          ),
+        // Output
+        .valid_o    ( r_valid    [s]            ),
+        .ready_i    ( r_ready    [s]            ),
+        .data_o     ( r_data_in  [s]            )
+      );
+    end
 
-  if (s >= 1) begin
-    stream_register #(
-      .T       (stage_w_t)
-    ) i_shuffle_reg_w  (
-      .clk_i      ( clk_i                     ),
-      .rst_ni     ( rst_ni                    ),
-      .clr_i      ( 1'b0                      ),
-      .testmode_i ( 1'b0                      ),
-      // Input
-      .valid_i    ( w_valid    [s-1]          ),
-      .ready_o    ( w_ready    [s-1]          ),
-      .data_i     ( w_data_out [s-1]          ),
-      // Output
-      .valid_o    ( w_valid    [s]            ),
-      .ready_i    ( w_ready    [s]            ),
-      .data_o     ( w_data_in  [s]            )
+    // Shuffling write data
+    shuffle #(
+      .NrLanes             (NrLanes),
+      .NrClusters          (NrClusters                  ),  
+      .ClusterAxiDataWidth (ClusterAxiDataWidth         ),
+      .T                   (stage_w_t                   ),
+      .scale               (s                           ),
+      .isRead              (0                           )
+    ) i_shuffle_wr (
+      .data_i       ( w_data_in  [s]    ),
+      .data_o       ( w_data_out [s]    ),
+      .enable_i     ( w_shuffle_en [s]  )
     );
-  end
-end
-
-// Set status of shuffle stage to the current pointers
-for (genvar s=0; s<NumStages; s++) begin
-  assign r_shuffle_en[s] = rd_tracker_q[rd_issue_pnt_q[s]].shuffle_en[s];
-  assign w_shuffle_en[s] = wr_tracker_q[wr_issue_pnt_q[s]].shuffle_en[s];
-end
 
-///////////////
-// Buffering //
-///////////////
-
-// Read Responses
-typedef axi_r_t [NrClusters-1:0] axi_resp_ext_t;
-axi_resp_ext_t [NumBuffers-1:0] buf_d, buf_q;
-axi_resp_t [NrClusters-1:0]  axi_resp_buf_out;
-
-logic rdbuf_pnt_q, rdbuf_pnt_d;
-logic [NumBuffers-1:0] shift_d, shift_q;                           // For each buffer a single bit is needed. (For BW 32N only)
-logic [NumBuffers-1:0] buf_valid_d, buf_valid_q;
-logic r_ready_buf, r_ready_buf_q;
-
-logic rd_buffer_en, rd_buffer_en_last_stage; 
-assign rd_buffer_en = rd_tracker_q[rd_issue_pnt_q[0]].buffer_en;
-assign rd_buffer_en_last_stage = rd_tracker_q[rd_issue_pnt_q[NumStages-1]].buffer_en;
-
-// Write packets
-logic [NrClusters-1:0] [ClusterAxiDataWidth*2-1:0]  wrbuf_d, wrbuf_q;
-logic [NrClusters-1:0] [(ClusterAxiDataWidth*2/8)-1:0]  wrbuf_be_d, wrbuf_be_q;
-axi_req_t [NrClusters-1:0]  axi_req_buf_out;
-
-logic [$clog2(NrClusters)-1:0] wrbuf_pnt_q, wrbuf_pnt_d;
-logic [NrClusters-1:0] wr_shift_d, wr_shift_q;
-logic [NrClusters-1:0] wrbuf_valid, wrbuf_valid_q;
-logic [NrClusters-1:0] wrbuf_full, wrbuf_full_q;
-logic wr_out_ready, wr_out_valid;
-
-logic wr_buffer_en, wr_buffer_en_last_stage; 
-assign wr_buffer_en = wr_tracker_q[wr_issue_pnt_q[0]].buffer_en;
-assign wr_buffer_en_last_stage = wr_tracker_q[wr_issue_pnt_q[NumStages-1]].buffer_en;
-
-
-always_ff @(posedge clk_i or negedge rst_ni) begin
-  if(~rst_ni) begin
-    // R
-    buf_q              <= '0;
-    buf_valid_q        <= '0;
-    rdbuf_pnt_q        <= '0;
-    shift_q            <= '0;
-    r_ready_buf_q      <= 1'b1;
-    // W
-    wrbuf_q            <= '0;
-    wrbuf_pnt_q        <= '0; 
-    wr_shift_q         <= '0;
-    wrbuf_valid_q      <= '0;
-    wrbuf_full_q       <= '0;
-    wrbuf_be_q         <= '0;
-  end else begin
-    // R
-    buf_q              <= buf_d;
-    buf_valid_q        <= buf_valid_d;
-    rdbuf_pnt_q        <= rdbuf_pnt_d;
-    shift_q            <= shift_d;
-    r_ready_buf_q      <= r_ready_buf;
-    // W
-    wrbuf_q            <= wrbuf_d;
-    wrbuf_pnt_q        <= wrbuf_pnt_d; 
-    wr_shift_q         <= wr_shift_d;
-    wrbuf_valid_q      <= wrbuf_valid;
-    wrbuf_full_q       <= wrbuf_full;
-    wrbuf_be_q         <= wrbuf_be_d;
+    if (s >= 1) begin
+      stream_register #(
+        .T       (stage_w_t)
+      ) i_shuffle_reg_w  (
+        .clk_i      ( clk_i                     ),
+        .rst_ni     ( rst_ni                    ),
+        .clr_i      ( 1'b0                      ),
+        .testmode_i ( 1'b0                      ),
+        // Input
+        .valid_i    ( w_valid    [s-1]          ),
+        .ready_o    ( w_ready    [s-1]          ),
+        .data_i     ( w_data_out [s-1]          ),
+        // Output
+        .valid_o    ( w_valid    [s]            ),
+        .ready_i    ( w_ready    [s]            ),
+        .data_o     ( w_data_in  [s]            )
+      );
+    end
   end
-end
 
-always_ff @(posedge clk_i or negedge rst_ni) begin
-  if(~rst_ni) begin
-    rd_tracker_q    <= '0;
-    rd_accept_pnt_q <= '0;
-    rd_issue_pnt_q  <= '0;
-    rd_cnt_q        <= '0;
-
-    wr_tracker_q    <= '0;
-    wr_accept_pnt_q <= '0;
-    wr_issue_pnt_q  <= '0;
-    wr_cnt_q        <= '0;
-  end else begin
-    rd_tracker_q    <= rd_tracker_d;
-    rd_accept_pnt_q <= rd_accept_pnt_d;
-    rd_issue_pnt_q  <= rd_issue_pnt_d;
-    rd_cnt_q        <= rd_cnt_d;
-
-    wr_tracker_q    <= wr_tracker_d;
-    wr_accept_pnt_q <= wr_accept_pnt_d;
-    wr_issue_pnt_q  <= wr_issue_pnt_d;
-    wr_cnt_q        <= wr_cnt_d;
+  // Set status of shuffle stage to the current pointers
+  for (genvar s=0; s<NumStages; s++) begin
+    assign r_shuffle_en[s] = rd_tracker_q[rd_issue_pnt_q[s]].shuffle_en[s];
+    assign w_shuffle_en[s] = wr_tracker_q[wr_issue_pnt_q[s]].shuffle_en[s];
   end
-end
-
-always_comb begin
 
-  rd_tracker_d = rd_tracker_q;
-  rd_accept_pnt_d = rd_accept_pnt_q;
-  rd_issue_pnt_d = rd_issue_pnt_q;
-  rd_cnt_d = rd_cnt_q;
-
-  wr_tracker_d = wr_tracker_q;
-  wr_accept_pnt_d = wr_accept_pnt_q;
-  wr_issue_pnt_d = wr_issue_pnt_q;
-  wr_cnt_d = wr_cnt_q;
-
-  axi_resp_buf_out = '0;
-  axi_req_buf_out = '0;
-
-  //////////////
-  // Requests //
-  //////////////
-
-  // If a request arrives, add to tracker.
-  if (axi_req_i[0].ar_valid & axi_resp_o[0].ar_ready) begin
-    rd_tracker_d[rd_accept_pnt_q].vew = vew_ar_i; //vew_ar_i;
-    for (int c=0; c<NrClusters; c++)
-      rd_tracker_d[rd_accept_pnt_q].len[c] = axi_req_i[0].ar.len+1;
-    rd_accept_pnt_d = (rd_accept_pnt_q == NumTrackers-1) ? '0 : rd_accept_pnt_q + 1;
-    rd_cnt_d += 1;
+  ///////////////
+  // Buffering //
+  ///////////////
 
-    for (int s=0; s<NumStages; s++) begin
-      rd_tracker_d[rd_accept_pnt_q].shuffle_en[s] = (s >= vew_ar_i) ? 1'b1 : 1'b0;
+  // Read Responses
+  typedef axi_r_t [NrClusters-1:0] axi_resp_ext_t;
+  axi_resp_ext_t [NumBuffers-1:0] buf_d, buf_q;
+  axi_resp_t [NrClusters-1:0]  axi_resp_buf_out;
+
+  logic rdbuf_pnt_q, rdbuf_pnt_d;
+  logic [NumBuffers-1:0] shift_d, shift_q;                           // For each buffer a single bit is needed. (For BW 32N only)
+  logic [NumBuffers-1:0] buf_valid_d, buf_valid_q;
+  logic r_ready_buf, r_ready_buf_q;
+
+  logic rd_buffer_en, rd_buffer_en_last_stage; 
+  assign rd_buffer_en = rd_tracker_q[rd_issue_pnt_q[0]].buffer_en;
+  assign rd_buffer_en_last_stage = rd_tracker_q[rd_issue_pnt_q[NumStages-1]].buffer_en;
+
+  // Write packets
+  logic [NrClusters-1:0] [ClusterAxiDataWidth*2-1:0]  wrbuf_d, wrbuf_q;
+  logic [NrClusters-1:0] [(ClusterAxiDataWidth*2/8)-1:0]  wrbuf_be_d, wrbuf_be_q;
+  axi_req_t [NrClusters-1:0]  axi_req_buf_out;
+
+  logic [$clog2(NrClusters)-1:0] wrbuf_pnt_q, wrbuf_pnt_d;
+  logic [NrClusters-1:0] wr_shift_d, wr_shift_q;
+  logic [NrClusters-1:0] wrbuf_valid, wrbuf_valid_q;
+  logic [NrClusters-1:0] wrbuf_full, wrbuf_full_q;
+  logic wr_out_ready, wr_out_valid;
+
+  logic wr_buffer_en, wr_buffer_en_last_stage; 
+  assign wr_buffer_en = wr_tracker_q[wr_issue_pnt_q[0]].buffer_en;
+  assign wr_buffer_en_last_stage = wr_tracker_q[wr_issue_pnt_q[NumStages-1]].buffer_en;
+
+
+  always_ff @(posedge clk_i or negedge rst_ni) begin
+    if(~rst_ni) begin
+      // R
+      buf_q              <= '0;
+      buf_valid_q        <= '0;
+      rdbuf_pnt_q        <= '0;
+      shift_q            <= '0;
+      r_ready_buf_q      <= 1'b1;
+      // W
+      wrbuf_q            <= '0;
+      wrbuf_pnt_q        <= '0; 
+      wr_shift_q         <= '0;
+      wrbuf_valid_q      <= '0;
+      wrbuf_full_q       <= '0;
+      wrbuf_be_q         <= '0;
+    end else begin
+      // R
+      buf_q              <= buf_d;
+      buf_valid_q        <= buf_valid_d;
+      rdbuf_pnt_q        <= rdbuf_pnt_d;
+      shift_q            <= shift_d;
+      r_ready_buf_q      <= r_ready_buf;
+      // W
+      wrbuf_q            <= wrbuf_d;
+      wrbuf_pnt_q        <= wrbuf_pnt_d; 
+      wr_shift_q         <= wr_shift_d;
+      wrbuf_valid_q      <= wrbuf_valid;
+      wrbuf_full_q       <= wrbuf_full;
+      wrbuf_be_q         <= wrbuf_be_d;
     end
-    rd_tracker_d[rd_accept_pnt_q].buffer_en = NumStages < vew_ar_i ? 1'b1 : 1'b0;
   end
 
-  if (axi_req_i[0].aw_valid & axi_resp_o[0].aw_ready) begin
-    wr_tracker_d[wr_accept_pnt_q].vew = vew_aw_i; //vew_aw_i;
-    for (int c=0; c<NrClusters; c++)
-      wr_tracker_d[wr_accept_pnt_q].len[c] = axi_req_i[0].aw.len+1;
-    wr_accept_pnt_d = (wr_accept_pnt_q == NumTrackers-1) ? '0 : wr_accept_pnt_q + 1; 
-    wr_cnt_d += 1;
-
-    for (int s=0; s<NumStages; s++) begin
-      wr_tracker_d[wr_accept_pnt_q].shuffle_en[s] = (s >= vew_aw_i) ? 1'b1 : 1'b0;
+  always_ff @(posedge clk_i or negedge rst_ni) begin
+    if(~rst_ni) begin
+      rd_tracker_q    <= '0;
+      rd_accept_pnt_q <= '0;
+      rd_issue_pnt_q  <= '0;
+      rd_cnt_q        <= '0;
+
+      wr_tracker_q    <= '0;
+      wr_accept_pnt_q <= '0;
+      wr_issue_pnt_q  <= '0;
+      wr_cnt_q        <= '0;
+    end else begin
+      rd_tracker_q    <= rd_tracker_d;
+      rd_accept_pnt_q <= rd_accept_pnt_d;
+      rd_issue_pnt_q  <= rd_issue_pnt_d;
+      rd_cnt_q        <= rd_cnt_d;
+
+      wr_tracker_q    <= wr_tracker_d;
+      wr_accept_pnt_q <= wr_accept_pnt_d;
+      wr_issue_pnt_q  <= wr_issue_pnt_d;
+      wr_cnt_q        <= wr_cnt_d;
     end
-    wr_tracker_d[wr_accept_pnt_q].buffer_en = NumStages < vew_aw_i ? 1'b1 : 1'b0;
   end
 
-  // Update counters for shuffle stage
-  // Update issue pointer of each stage
-  // Once last packet is received by each stage, point to the next tracker.
-  for (int s=0; s < NumStages; s++) begin
-    
-    // Reset shuffle config for the read shuffle stages
-    // If the last stage sends the last packet, we need to go to the vew of the next request
-    if (r_data_out[s][0].last & r_valid[s] & r_ready[s]) begin
-      rd_issue_pnt_d[s] = (rd_issue_pnt_q[s] == NumTrackers-1) ? '0 : rd_issue_pnt_q[s] + 1;
-      // In the last stage, reset the shift enable for the tracker instance
-      if (s==NumStages-1) begin
-        rd_tracker_d[rd_issue_pnt_q[s]].shuffle_en = '0;
-        rd_cnt_d -= 1'b1;
+  always_comb begin
+
+    rd_tracker_d = rd_tracker_q;
+    rd_accept_pnt_d = rd_accept_pnt_q;
+    rd_issue_pnt_d = rd_issue_pnt_q;
+    rd_cnt_d = rd_cnt_q;
+
+    wr_tracker_d = wr_tracker_q;
+    wr_accept_pnt_d = wr_accept_pnt_q;
+    wr_issue_pnt_d = wr_issue_pnt_q;
+    wr_cnt_d = wr_cnt_q;
+
+    axi_resp_buf_out = '0;
+    axi_req_buf_out = '0;
+
+    //////////////
+    // Requests //
+    //////////////
+
+    // If a request arrives, add to tracker.
+    if (axi_req_i[0].ar_valid & axi_resp_o[0].ar_ready) begin
+      rd_tracker_d[rd_accept_pnt_q].vew = vew_ar_i; //vew_ar_i;
+      for (int c=0; c<NrClusters; c++)
+        rd_tracker_d[rd_accept_pnt_q].len[c] = axi_req_i[0].ar.len+1;
+      rd_accept_pnt_d = (rd_accept_pnt_q == NumTrackers-1) ? '0 : rd_accept_pnt_q + 1;
+      rd_cnt_d += 1;
+
+      for (int s=0; s<NumStages; s++) begin
+        rd_tracker_d[rd_accept_pnt_q].shuffle_en[s] = (s >= vew_ar_i) ? 1'b1 : 1'b0;
       end
+      rd_tracker_d[rd_accept_pnt_q].buffer_en = NumStages < vew_ar_i ? 1'b1 : 1'b0;
     end
-    
-    // Reset shuffle config for the write shuffle stages
-    if (w_data_out[s][0].last & w_valid[s] & w_ready[s]) begin
-      wr_issue_pnt_d[s] = (wr_issue_pnt_q[s] == NumTrackers-1) ? '0 : wr_issue_pnt_q[s] + 1;
-      // In the last stage, reset the shift enable for the tracker instance
-      if (s==NumStages-1) begin
-        wr_tracker_d[wr_issue_pnt_q[s]].shuffle_en = '0;
-        wr_cnt_d -= 1'b1;
+
+    if (axi_req_i[0].aw_valid & axi_resp_o[0].aw_ready) begin
+      wr_tracker_d[wr_accept_pnt_q].vew = vew_aw_i; //vew_aw_i;
+      for (int c=0; c<NrClusters; c++)
+        wr_tracker_d[wr_accept_pnt_q].len[c] = axi_req_i[0].aw.len+1;
+      wr_accept_pnt_d = (wr_accept_pnt_q == NumTrackers-1) ? '0 : wr_accept_pnt_q + 1; 
+      wr_cnt_d += 1;
+
+      for (int s=0; s<NumStages; s++) begin
+        wr_tracker_d[wr_accept_pnt_q].shuffle_en[s] = (s >= vew_aw_i) ? 1'b1 : 1'b0;
       end
+      wr_tracker_d[wr_accept_pnt_q].buffer_en = NumStages < vew_aw_i ? 1'b1 : 1'b0;
     end
-  end
 
-  ///////////////
-  // Buffering //
-  ///////////////
-  
-  // Handling buffering of read responses
-
-  // Handling cases where input data maps only to a single cluster e.g. ClusterAxiDataWidth=32N and EW=64
-  // In this case, need to buffer the current data to be used in the following cycles.
-  // NOTE : This buffering logic implemented only works for the default BW config.
-  // ClusterAxiDataWidth = 32N and AxiDataWidth=32NC
-
-  buf_d = buf_q;
-  buf_valid_d = buf_valid_q;
-  rdbuf_pnt_d = rdbuf_pnt_q;
-  shift_d = shift_q;
-  r_ready_buf = r_ready_buf_q;
-
-  if (rd_buffer_en) begin
-    // If have a valid handshake on response add to the buffer
-    if (axi_resp_i[0].r_valid && r_ready_buf_q) begin
-      for (int c=0; c<NrClusters; c++) begin
-        buf_d[rdbuf_pnt_q][c] = axi_resp_i[c].r;
+    // Update counters for shuffle stage
+    // Update issue pointer of each stage
+    // Once last packet is received by each stage, point to the next tracker.
+    for (int s=0; s < NumStages; s++) begin
+      
+      // Reset shuffle config for the read shuffle stages
+      // If the last stage sends the last packet, we need to go to the vew of the next request
+      if (r_data_out[s][0].last & r_valid[s] & r_ready[s]) begin
+        rd_issue_pnt_d[s] = (rd_issue_pnt_q[s] == NumTrackers-1) ? '0 : rd_issue_pnt_q[s] + 1;
+        // In the last stage, reset the shift enable for the tracker instance
+        if (s==NumStages-1) begin
+          rd_tracker_d[rd_issue_pnt_q[s]].shuffle_en = '0;
+          rd_cnt_d -= 1'b1;
+        end
+      end
+      
+      // Reset shuffle config for the write shuffle stages
+      if (w_data_out[s][0].last & w_valid[s] & w_ready[s]) begin
+        wr_issue_pnt_d[s] = (wr_issue_pnt_q[s] == NumTrackers-1) ? '0 : wr_issue_pnt_q[s] + 1;
+        // In the last stage, reset the shift enable for the tracker instance
+        if (s==NumStages-1) begin
+          wr_tracker_d[wr_issue_pnt_q[s]].shuffle_en = '0;
+          wr_cnt_d -= 1'b1;
+        end
       end
-      buf_valid_d[rdbuf_pnt_q] = 1'b1;
-      rdbuf_pnt_d = (rdbuf_pnt_q == 1'b1) ? 1'b0 : 1'b1;
     end
 
-    // Assign data in buffer to the output
-    for (int b=0; b < NumBuffers; b++) begin
-      if (buf_valid_d[b]) begin
-        automatic logic cluster_ready = 1'b1;
-        for (int c=0; c < (NrClusters / NumBuffers); c++) begin
-          automatic int cl = b ? (NrClusters / NumBuffers) + c : c;
-          
-          // First Half of the the clusters take data from buf[0]
-          axi_resp_buf_out[cl].r.data = buf_d[b][c*2 + shift_d[b]].data;  // 2 works for default 32N configuration to support EW=64
-          cluster_ready &= axi_req_i[cl].r_ready;
+    ///////////////
+    // Buffering //
+    ///////////////
+    
+    // Handling buffering of read responses
+
+    // Handling cases where input data maps only to a single cluster e.g. ClusterAxiDataWidth=32N and EW=64
+    // In this case, need to buffer the current data to be used in the following cycles.
+    // NOTE : This buffering logic implemented only works for the default BW config.
+    // ClusterAxiDataWidth = 32N and AxiDataWidth=32NC
+
+    buf_d = buf_q;
+    buf_valid_d = buf_valid_q;
+    rdbuf_pnt_d = rdbuf_pnt_q;
+    shift_d = shift_q;
+    r_ready_buf = r_ready_buf_q;
+
+    if (rd_buffer_en) begin
+      // If have a valid handshake on response add to the buffer
+      if (axi_resp_i[0].r_valid && r_ready_buf_q) begin
+        for (int c=0; c<NrClusters; c++) begin
+          buf_d[rdbuf_pnt_q][c] = axi_resp_i[c].r;
         end
-        if (cluster_ready) begin
-          // Only if handshake is valid, update pointers
+        buf_valid_d[rdbuf_pnt_q] = 1'b1;
+        rdbuf_pnt_d = (rdbuf_pnt_q == 1'b1) ? 1'b0 : 1'b1;
+      end
+
+      // Assign data in buffer to the output
+      for (int b=0; b < NumBuffers; b++) begin
+        if (buf_valid_d[b]) begin
+          automatic logic cluster_ready = 1'b1;
           for (int c=0; c < (NrClusters / NumBuffers); c++) begin
-            automatic int cl = b ? (NrClusters / NumBuffers) + c : c; //automatic int cl = b*(NrClusters / NumBuffers) + c;
-            axi_resp_buf_out[cl].r_valid = 1'b1;
-            rd_tracker_d[rd_issue_pnt_q[0]].len[cl] -= 1;
-            if (rd_tracker_q[rd_issue_pnt_q[0]].len[cl] <= 1) begin
-              axi_resp_buf_out[cl].r.last = 1'b1;
-            end
+            automatic int cl = b ? (NrClusters / NumBuffers) + c : c;
+            
+            // First Half of the the clusters take data from buf[0]
+            axi_resp_buf_out[cl].r.data = buf_d[b][c*2 + shift_d[b]].data;  // 2 works for default 32N configuration to support EW=64
+            cluster_ready &= axi_req_i[cl].r_ready;
           end
-          // Update the shift
-          shift_d[b] = (shift_q[b] == 1'b1) ? 1'b0 : 1'b1;
-          if (shift_q[b] == 1'b1) begin
-            buf_valid_d[b] = 1'b0;
+          if (cluster_ready) begin
+            // Only if handshake is valid, update pointers
+            for (int c=0; c < (NrClusters / NumBuffers); c++) begin
+              automatic int cl = b ? (NrClusters / NumBuffers) + c : c; //automatic int cl = b*(NrClusters / NumBuffers) + c;
+              axi_resp_buf_out[cl].r_valid = 1'b1;
+              rd_tracker_d[rd_issue_pnt_q[0]].len[cl] -= 1;
+              if (rd_tracker_q[rd_issue_pnt_q[0]].len[cl] <= 1) begin
+                axi_resp_buf_out[cl].r.last = 1'b1;
+              end
+            end
+            // Update the shift
+            shift_d[b] = (shift_q[b] == 1'b1) ? 1'b0 : 1'b1;
+            if (shift_q[b] == 1'b1) begin
+              buf_valid_d[b] = 1'b0;
+            end
           end
         end
       end
-    end
-    
-    // The next buffer has to be available only then ready to receive
-    r_ready_buf = (buf_valid_d[rdbuf_pnt_d] == 1'b0);
+      
+      // The next buffer has to be available only then ready to receive
+      r_ready_buf = (buf_valid_d[rdbuf_pnt_d] == 1'b0);
 
-    // If the last cluster sends the data, remove request from tracker
-    if (axi_resp_buf_out[NrClusters-1].r_valid & axi_resp_buf_out[NrClusters-1].r.last) begin
-      for (int s= 0; s < NumStages ; s++)
-        rd_issue_pnt_d[s] = (rd_issue_pnt_q[s] == NumTrackers-1) ? '0 : rd_issue_pnt_q[s] + 1;
-      rd_cnt_d -= 1'b1;
+      // If the last cluster sends the data, remove request from tracker
+      if (axi_resp_buf_out[NrClusters-1].r_valid & axi_resp_buf_out[NrClusters-1].r.last) begin
+        for (int s= 0; s < NumStages ; s++)
+          rd_issue_pnt_d[s] = (rd_issue_pnt_q[s] == NumTrackers-1) ? '0 : rd_issue_pnt_q[s] + 1;
+        rd_cnt_d -= 1'b1;
+      end
     end
-  end
 
-  // Handling buffering of write packets
-  wrbuf_d       = wrbuf_q;
-  wrbuf_pnt_d   = wrbuf_pnt_q; 
-  wr_shift_d    = wr_shift_q;
-  wrbuf_valid   = wrbuf_valid_q;
-  wrbuf_full    = wrbuf_full_q;
-  wrbuf_be_d    = wrbuf_be_q;
-  if (wr_buffer_en) begin
-    // If a valid write packet, add it to the buffer
-    for (int c=0; c < NrClusters; c++) begin
-      automatic axi_req_t req = axi_req_i[c];
-      if (req.w_valid & ~wrbuf_full_q[c]) begin
-        wrbuf_d[c][wr_shift_d[c] * ClusterAxiDataWidth +: ClusterAxiDataWidth] = req.w.data;
-        wrbuf_be_d[c][wr_shift_d[c] * ClusterAxiDataWidth/8 +: ClusterAxiDataWidth/8] = req.w.strb;
-        wr_shift_d[c] += 1'b1;
-        wrbuf_valid[c] = 1'b1;
-        if (wr_shift_q[c] == 1'b1) begin
-          wrbuf_full[c] = 1'b1;
-          wr_shift_d[c] = 1'b0;
+    // Handling buffering of write packets
+    wrbuf_d       = wrbuf_q;
+    wrbuf_pnt_d   = wrbuf_pnt_q; 
+    wr_shift_d    = wr_shift_q;
+    wrbuf_valid   = wrbuf_valid_q;
+    wrbuf_full    = wrbuf_full_q;
+    wrbuf_be_d    = wrbuf_be_q;
+    if (wr_buffer_en) begin
+      // If a valid write packet, add it to the buffer
+      for (int c=0; c < NrClusters; c++) begin
+        automatic axi_req_t req = axi_req_i[c];
+        if (req.w_valid & ~wrbuf_full_q[c]) begin
+          wrbuf_d[c][wr_shift_d[c] * ClusterAxiDataWidth +: ClusterAxiDataWidth] = req.w.data;
+          wrbuf_be_d[c][wr_shift_d[c] * ClusterAxiDataWidth/8 +: ClusterAxiDataWidth/8] = req.w.strb;
+          wr_shift_d[c] += 1'b1;
+          wrbuf_valid[c] = 1'b1;
+          if (wr_shift_q[c] == 1'b1) begin
+            wrbuf_full[c] = 1'b1;
+            wr_shift_d[c] = 1'b0;
+          end
         end
       end
-    end
 
-    // If a buff is full write it to the output
-    wr_out_valid = 1'b1;
-    wr_out_ready = 1'b1;
-    
-    for (int c=0; c < (NrClusters/2); c++) begin
-      automatic int cluster = wrbuf_pnt_q + c;
-      wr_out_valid &= wrbuf_full[cluster];
-      if (wrbuf_full[cluster]) begin
-        for (int b=0; b < 2; b++) begin
-          wr_out_ready &= axi_resp_i[c*2 + b].w_ready;
-          axi_req_buf_out[c*2 + b].w.data = wrbuf_d   [cluster][b*ClusterAxiDataWidth   +: ClusterAxiDataWidth  ];
-          axi_req_buf_out[c*2 + b].w.strb = wrbuf_be_d[cluster][b*ClusterAxiDataWidth/8 +: ClusterAxiDataWidth/8];
+      // If a buff is full write it to the output
+      wr_out_valid = 1'b1;
+      wr_out_ready = 1'b1;
+      
+      for (int c=0; c < (NrClusters/2); c++) begin
+        automatic int cluster = wrbuf_pnt_q + c;
+        wr_out_valid &= wrbuf_full[cluster];
+        if (wrbuf_full[cluster]) begin
+          for (int b=0; b < 2; b++) begin
+            wr_out_ready &= axi_resp_i[c*2 + b].w_ready;
+            axi_req_buf_out[c*2 + b].w.data = wrbuf_d   [cluster][b*ClusterAxiDataWidth   +: ClusterAxiDataWidth  ];
+            axi_req_buf_out[c*2 + b].w.strb = wrbuf_be_d[cluster][b*ClusterAxiDataWidth/8 +: ClusterAxiDataWidth/8];
+          end
         end
       end
-    end
 
-    if (wr_out_ready & wr_out_valid) begin
-      // For a valid handshake set valid to 1
-      for (int c=0; c<NrClusters; c++) 
-        axi_req_buf_out[c].w_valid = 1'b1;
-      wrbuf_pnt_d = wrbuf_pnt_q + (NrClusters/NumBuffers);
-      for (int c=0; c < (NrClusters/NumBuffers); c++) begin
-        wrbuf_valid[wrbuf_pnt_q + c] = 1'b0;
-        wrbuf_full [wrbuf_pnt_q + c] = 1'b0;
-        wr_tracker_d[wr_issue_pnt_q[0]].len[wrbuf_pnt_q + c] -= 2;
+      if (wr_out_ready & wr_out_valid) begin
+        // For a valid handshake set valid to 1
+        for (int c=0; c<NrClusters; c++) 
+          axi_req_buf_out[c].w_valid = 1'b1;
+        wrbuf_pnt_d = wrbuf_pnt_q + (NrClusters/NumBuffers);
+        for (int c=0; c < (NrClusters/NumBuffers); c++) begin
+          wrbuf_valid[wrbuf_pnt_q + c] = 1'b0;
+          wrbuf_full [wrbuf_pnt_q + c] = 1'b0;
+          wr_tracker_d[wr_issue_pnt_q[0]].len[wrbuf_pnt_q + c] -= 2;
+        end
+        if ((wrbuf_pnt_q == NrClusters/2) && (wr_tracker_q[wr_issue_pnt_q[0]].len[NrClusters/2] <= 2)) begin // check if the last NrClusters/2 is also completed
+          axi_req_buf_out[0].w.last = 1'b1;
+        end
       end
-      if ((wrbuf_pnt_q == NrClusters/2) && (wr_tracker_q[wr_issue_pnt_q[0]].len[NrClusters/2] <= 2)) begin // check if the last NrClusters/2 is also completed
-        axi_req_buf_out[0].w.last = 1'b1;
+
+      // If the last cluster sends the data, remove request from tracker
+      if (axi_req_buf_out[0].w_valid & axi_req_buf_out[0].w.last) begin
+        for (int s=0; s < NumStages ; s++)
+          wr_issue_pnt_d[s] = (wr_issue_pnt_q[s] == NumTrackers-1) ? '0 : wr_issue_pnt_q[s] + 1;
+        wr_cnt_d -= 1'b1;
       end
     end
 
-    // If the last cluster sends the data, remove request from tracker
-    if (axi_req_buf_out[0].w_valid & axi_req_buf_out[0].w.last) begin
-      for (int s=0; s < NumStages ; s++)
-        wr_issue_pnt_d[s] = (wr_issue_pnt_q[s] == NumTrackers-1) ? '0 : wr_issue_pnt_q[s] + 1;
-      wr_cnt_d -= 1'b1;
-    end
   end
 
-end
-
-/// Output input interface assignments
-// Handle Response path
-for (genvar c=0; c < NrClusters; c++) begin  
-  // Bypass the registers for signals other than R channel
-  assign axi_resp_o[c].aw_ready = axi_resp_i[c].aw_ready && !wr_full;
-  assign axi_resp_o[c].ar_ready = axi_resp_i[c].ar_ready && !rd_full; 
-  
-  assign axi_resp_o[c].b_valid = axi_resp_i[c].b_valid;
-  assign axi_resp_o[c].b = axi_resp_i[c].b;
+  /// Output input interface assignments
+  // Handle Response path
+  for (genvar c=0; c < NrClusters; c++) begin  
+    // Bypass the registers for signals other than R channel
+    assign axi_resp_o[c].aw_ready = axi_resp_i[c].aw_ready && !wr_full;
+    assign axi_resp_o[c].ar_ready = axi_resp_i[c].ar_ready && !rd_full; 
+    
+    assign axi_resp_o[c].b_valid = axi_resp_i[c].b_valid;
+    assign axi_resp_o[c].b = axi_resp_i[c].b;
 
-  // Reads  
-  assign r_data_in[0][c] = rd_buffer_en ? '0 : axi_resp_i[c].r;             // Copy input resp to first stage
-  // assign axi_resp_o[c].r = rd_buffer_en ? axi_resp_buf_out[c].r : r_data_out[NumStages-1][c];  // Copy output resp from last stage
-  // assign axi_resp_o[c].r_valid = rd_buffer_en ? axi_resp_buf_out[c].r_valid : r_valid_o[c];          // Copy valid from stream fork to output
-  assign axi_resp_o[c].r = rd_buffer_en_last_stage ? axi_resp_buf_out[c].r : r_data_out[NumStages-1][c];  // Copy output resp from last stage
-  assign axi_resp_o[c].r_valid = rd_buffer_en_last_stage ? axi_resp_buf_out[c].r_valid : r_valid_o[c];          // Copy valid from stream fork to output
+    // Reads  
+    assign r_data_in[0][c] = rd_buffer_en ? '0 : axi_resp_i[c].r;             // Copy input resp to first stage
+    // assign axi_resp_o[c].r = rd_buffer_en ? axi_resp_buf_out[c].r : r_data_out[NumStages-1][c];  // Copy output resp from last stage
+    // assign axi_resp_o[c].r_valid = rd_buffer_en ? axi_resp_buf_out[c].r_valid : r_valid_o[c];          // Copy valid from stream fork to output
+    assign axi_resp_o[c].r = rd_buffer_en_last_stage ? axi_resp_buf_out[c].r : r_data_out[NumStages-1][c];  // Copy output resp from last stage
+    assign axi_resp_o[c].r_valid = rd_buffer_en_last_stage ? axi_resp_buf_out[c].r_valid : r_valid_o[c];          // Copy valid from stream fork to output
 
-  // Writes
-  assign axi_resp_o[c].w_ready = wr_buffer_en ? ~wrbuf_full[c] : w_ready_o[c];          // Copy ready from stream join output to response
+    // Writes
+    assign axi_resp_o[c].w_ready = wr_buffer_en ? ~wrbuf_full[c] : w_ready_o[c];          // Copy ready from stream join output to response
 
-end
-assign r_valid[0]   = axi_resp_i[0].r_valid;            // From the Global Ld-St for now all clusters receive data together. 
-                                                        // Hence using only cluster-0 's indication of r_valid.
-
-// Handle Request path
-for (genvar c=0; c < NrClusters; c++) begin
-  assign axi_req_o[c].aw = axi_req_i[c].aw;
-  assign axi_req_o[c].aw_valid = axi_req_i[c].aw_valid;
-  assign axi_req_o[c].ar = axi_req_i[c].ar;
-  assign axi_req_o[c].ar_valid = axi_req_i[c].ar_valid;
-  assign axi_req_o[c].b_ready = axi_req_i[c].b_ready;
-  
-  // Reads
-  assign axi_req_o[c].r_ready = rd_buffer_en ? r_ready_buf_q : r_ready[0];        
-  assign r_ready_i[c] = axi_req_i[c].r_ready;           // From input request, get ready inputs to stream fork
+  end
+  assign r_valid[0]   = axi_resp_i[0].r_valid;            // From the Global Ld-St for now all clusters receive data together. 
+                                                          // Hence using only cluster-0 's indication of r_valid.
+
+  // Handle Request path
+  for (genvar c=0; c < NrClusters; c++) begin
+    assign axi_req_o[c].aw = axi_req_i[c].aw;
+    assign axi_req_o[c].aw_valid = axi_req_i[c].aw_valid;
+    assign axi_req_o[c].ar = axi_req_i[c].ar;
+    assign axi_req_o[c].ar_valid = axi_req_i[c].ar_valid;
+    assign axi_req_o[c].b_ready = axi_req_i[c].b_ready;
+    
+    // Reads
+    assign axi_req_o[c].r_ready = rd_buffer_en ? r_ready_buf_q : r_ready[0];        
+    assign r_ready_i[c] = axi_req_i[c].r_ready;           // From input request, get ready inputs to stream fork
 
-  // Writes
-  assign w_data_in[0][c] = wr_buffer_en ? '0 : axi_req_i[c].w;              // Copy input write data to first shuffle stage
-  assign w_valid_i[c]    = wr_buffer_en ? 1'b0 : axi_req_i[c].w_valid;           // Copy valid signals to stream join
-   
-  assign axi_req_o[c].w       = wr_buffer_en_last_stage ? axi_req_buf_out[c].w       : w_data_out[NumStages-1][c];  // Copy last stage data to req output
-  assign axi_req_o[c].w_valid = wr_buffer_en_last_stage ? axi_req_buf_out[c].w_valid : w_valid[NumStages-1];   // valid signal is the output valid of stream join
+    // Writes
+    assign w_data_in[0][c] = wr_buffer_en ? '0 : axi_req_i[c].w;              // Copy input write data to first shuffle stage
+    assign w_valid_i[c]    = wr_buffer_en ? 1'b0 : axi_req_i[c].w_valid;           // Copy valid signals to stream join
+     
+    assign axi_req_o[c].w       = wr_buffer_en_last_stage ? axi_req_buf_out[c].w       : w_data_out[NumStages-1][c];  // Copy last stage data to req output
+    assign axi_req_o[c].w_valid = wr_buffer_en_last_stage ? axi_req_buf_out[c].w_valid : w_valid[NumStages-1];   // valid signal is the output valid of stream join
 
+  end
+  assign w_ready[NumStages-1] = axi_resp_i[0].w_ready; // The Global Ld-St is ready to receive write packets together. Hence using only cluster-0 's w_ready.
 end
-assign w_ready[NumStages-1] = axi_resp_i[0].w_ready; // The Global Ld-St is ready to receive write packets together. Hence using only cluster-0 's w_ready.
-
 endmodule
 
 module shuffle import rvv_pkg::*; #(

From 5a75287668e0063b48f375e9419668670c48c608 Mon Sep 17 00:00:00 2001
From: Hong Pang <hopang@larain5.ee.ethz.ch>
Date: Tue, 4 Nov 2025 18:23:36 +0100
Subject: [PATCH 30/37] [makefiles] update makefiles for compilation

---
 apps/Makefile                      | 32 ++++++++++++-------
 apps/common/runtime.mk             | 51 +++++++++++++++++++++++-------
 config/8_lanes.mk                  |  2 +-
 hardware/Makefile                  |  4 ++-
 hardware/src/vlsu/shuffle_stage.sv |  2 +-
 5 files changed, 64 insertions(+), 27 deletions(-)

diff --git a/apps/Makefile b/apps/Makefile
index b1751ad..b9bf0e3 100644
--- a/apps/Makefile
+++ b/apps/Makefile
@@ -30,8 +30,9 @@ include $(COMMON_DIR)/default_args.mk
 nr_clusters ?= 2
 
 APPS := $(patsubst $(APPS_DIR)/%/main.c,%,$(shell find $(APPS_DIR) -name "main.c"))
+APPS += $(patsubst $(APPS_DIR)/%/main.cpp,%,$(shell find $(APPS_DIR) -name "main.cpp"))
 # Don't automatically compile the benchmark app, which is only a wrapper around the other apps
-BINARIES := $(filter-out bin/benchmarks, $(addprefix bin/,$(APPS)))
+BINARIES := $(filter-out bin/benchmarks bin/rivec-bmarks% bin/_%, $(addprefix bin/,$(APPS)))
 
 CVA6_EXTENSIONS := rv64ui rv64uc rv64um rv64uf rv64ud rv64si
 # Atomics are messy, since there is currently no memory region capable of handling them
@@ -40,6 +41,13 @@ CVA6_BINARIES := $(addprefix bin/, $(cva6_tests))
 ARA_EXTENSIONS := rv64uv
 ARA_BINARIES := $(addprefix bin/, $(ara_tests))
 
+# Suffix for binaries
+ifeq ($(LINUX),1)
+BIN_SUFFIX := -linux
+else
+BIN_SUFFIX :=
+endif
+
 # FFT requires special treatment because of its header files
 ifeq ($(ENV_DEFINES),)
 bin/fft:  ENV_DEFINES += -DFFT_SAMPLES=$(subst ",,$(firstword $(def_args_fft)))
@@ -93,17 +101,17 @@ endef
 $(foreach app,$(APPS),$(eval $(call app_compile_template_ideal,$(app))))
 
 define app_compile_template_spike
-bin/$1.spike: $1/data.S.o.spike $(addsuffix .o.spike, $(shell find $(1) -name "*.c" -o -name "*.S")) $(RUNTIME_SPIKE) $(COMMON_SPIKE) patch-spike-crt0
+bin/$1.spike: $1/data.S.o.spike $(addsuffix .o.spike, $(shell find $(1) -name "*.c" -o -name "*.cpp" -o -name "*.S")) $(RUNTIME_SPIKE) $(COMMON_SPIKE) patch-spike-crt0
 	mkdir -p bin/
-	$$(RISCV_CC) -Iinclude $$(RISCV_CCFLAGS_SPIKE) -o $$@ $$(addsuffix .o.spike, $$(shell find $(1) -name "*.c" -o -name "*.S")) $(RUNTIME_SPIKE) $$(RISCV_LDFLAGS_SPIKE) -DSPIKE
+	$$(RISCV_CC) -Iinclude $$(RISCV_CCFLAGS_SPIKE) -o $$@ $$(addsuffix .o.spike, $$(shell find $(1) -name "*.c" -o -name "*.cpp" -o -name "*.S")) $(RUNTIME_SPIKE) $$(RISCV_LDFLAGS_SPIKE) -DSPIKE
 	$$(RISCV_OBJDUMP) $$(RISCV_OBJDUMP_FLAGS) -D $$@ > $$@.dump
 endef
 $(foreach app,$(APPS),$(eval $(call app_compile_template_spike,$(app))))
 
 define app_compile_template
-bin/$1: $1/data.S.o $(addsuffix .o, $(shell find $(1) -name "*.c" -o -name "*.S")) $(RUNTIME_LLVM) linker_script
+bin/$1$(BIN_SUFFIX): $1/data.S.o $(addsuffix .o, $(shell find -L $(1) -name "*.c" -o -name "*.cpp" -o -name "*.S")) $(RUNTIME_LLVM) linker_script
 	mkdir -p bin/
-	$$(RISCV_CC) -Iinclude $(RISCV_CCFLAGS) -o $$@ $$(addsuffix .o, $$(shell find $(1) -name "*.c" -o -name "*.S")) $(RUNTIME_LLVM) $$(RISCV_LDFLAGS) -T$$(CURDIR)/common/link.ld
+	$$(RISCV_CC) -Iinclude $(RISCV_CCFLAGS) -o $$@ $$(addsuffix .o, $$(shell find -L $(1) -name "*.c" -o -name "*.cpp" -o -name "*.S")) $(RUNTIME_LLVM) $$(RISCV_LDFLAGS)
 	$$(RISCV_OBJDUMP) $$(RISCV_OBJDUMP_FLAGS) -D $$@ > $$@.dump
 	$$(RISCV_STRIP) $$@ -S --strip-unneeded
 endef
@@ -117,7 +125,7 @@ TESTS_$(1) := $(addprefix bin/, $($(addsuffix _ara_tests, $1)))
 
 bin/$(1)-ara-%: $(TESTS_DIR)/$(1)/%.$(2) $(RUNTIME_GCC) linker_script
 	mkdir -p bin/
-	$$(RISCV_CC_GCC) -Iinclude -I$$(TESTS_DIR)/macros/scalar -I$$(TESTS_DIR)/macros/vector $$(RISCV_CCFLAGS_GCC) $$(RISCV_LDFLAGS_GCC) -o $$@ $$< $(RUNTIME_GCC) -T$$(CURDIR)/common/link.ld
+	$$(RISCV_CC_GCC) -Iinclude -I$$(TESTS_DIR)/macros/scalar -I$$(TESTS_DIR)/macros/vector $$(RISCV_CCFLAGS_GCC) $$(RISCV_LDFLAGS_GCC) -o $$@ $$< $(RUNTIME_GCC)
 	$$(RISCV_OBJDUMP) $$(RISCV_OBJDUMP_FLAGS) -D $$@ > $$@.dump
 	$$(RISCV_STRIP) $$@ -S --strip-unneeded
 endef
@@ -127,7 +135,7 @@ TESTS_$(1) := $(addprefix bin/, $($(addsuffix _ara_tests, $1)))
 
 bin/$(1)-ara-%: $(TESTS_DIR)/$(1)/%.$(2) $(RUNTIME_LLVM) linker_script
 	mkdir -p bin/
-	$$(RISCV_CC) -Iinclude -I$$(TESTS_DIR)/macros/scalar -I$$(TESTS_DIR)/macros/vector $$(RISCV_CCFLAGS) $$(RISCV_LDFLAGS) -o $$@ $$< $(RUNTIME_LLVM) -T$$(CURDIR)/common/link.ld
+	$$(RISCV_CC) -Iinclude -I$$(TESTS_DIR)/macros/scalar -I$$(TESTS_DIR)/macros/vector $$(RISCV_CCFLAGS) $$(RISCV_LDFLAGS) -o $$@ $$< $(RUNTIME_LLVM)
 	$$(RISCV_OBJDUMP) $$(RISCV_OBJDUMP_FLAGS) -D $$@ > $$@.dump
 	$$(RISCV_STRIP) $$@ -S --strip-unneeded
 endef
@@ -166,11 +174,11 @@ $(foreach app,$(APPS),$(eval $(call run_benchmark_spike,$(app))))
 riscv_tests_spike_clean:
 	make -C riscv-tests/isa clean
 
-# Compile standardized riscv tests
-.PHONY: riscv_tests_compile
-riscv_tests_compile:
-	cd riscv-tests && \
-	make benchmarks && make isa -i
+# # Compile standardized riscv tests
+# .PHONY: riscv_tests_compile
+# riscv_tests_compile:
+# 	cd riscv-tests && \
+# 	make benchmarks && make isa -i
 
 .PHONY: benchmarks_clean
 benchmarks_clean:
diff --git a/apps/common/runtime.mk b/apps/common/runtime.mk
index a59dafc..a681a92 100644
--- a/apps/common/runtime.mk
+++ b/apps/common/runtime.mk
@@ -1,4 +1,4 @@
-# Copyright 2020-2025 ETH Zurich and University of Bologna.
+# Copyright 2020 ETH Zurich and University of Bologna.
 #
 # SPDX-License-Identifier: Apache-2.0
 #
@@ -44,7 +44,18 @@ RISCV_ARCH    ?= rv$(RISCV_XLEN)gcv
 RISCV_ABI     ?= lp64d
 RISCV_TARGET  ?= riscv$(RISCV_XLEN)-unknown-elf
 
-# Use LLVM
+# Use LLVM for bare-metal RVV and GCC for Linux RVV
+ifeq ($(LINUX),1)
+RISCV_PREFIX  ?= $(ARA_DIR)/cheshire/sw/cva6-sdk/buildroot/output/host/bin/riscv64-buildroot-linux-gnu-
+RISCV_CC      ?= $(RISCV_PREFIX)gcc
+RISCV_CXX     ?= $(RISCV_PREFIX)g++
+RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump
+RISCV_OBJCOPY ?= $(RISCV_PREFIX)objcopy
+RISCV_AS      ?= $(RISCV_PREFIX)as
+RISCV_AR      ?= $(RISCV_PREFIX)ar
+RISCV_LD      ?= $(RISCV_PREFIX)ld.lld
+RISCV_STRIP   ?= $(RISCV_PREFIX)strip
+else
 RISCV_PREFIX  ?= $(LLVM_INSTALL_DIR)/bin/
 RISCV_CC      ?= $(RISCV_PREFIX)clang
 RISCV_CXX     ?= $(RISCV_PREFIX)clang++
@@ -54,6 +65,7 @@ RISCV_AS      ?= $(RISCV_PREFIX)llvm-as
 RISCV_AR      ?= $(RISCV_PREFIX)llvm-ar
 RISCV_LD      ?= $(RISCV_PREFIX)ld.lld
 RISCV_STRIP   ?= $(RISCV_PREFIX)llvm-strip
+endif
 
 # Use gcc to compile scalar riscv-tests
 RISCV_CC_GCC  ?= $(GCC_INSTALL_DIR)/bin/$(RISCV_TARGET)-gcc
@@ -75,40 +87,55 @@ PYTHON ?= python3
 
 # Defines
 ENV_DEFINES ?=
+ifeq ($(LINUX),1)
+ENV_DEFINES += -DARA_LINUX=1
+endif
 ifeq ($(vcd_dump),1)
 ENV_DEFINES += -DVCD_DUMP=1
 endif
-MAKE_DEFINES = -DNR_LANES=$(nr_lanes) -DVLEN=$(vlen) -DNR_CLUSTERS=$(nr_clusters)
+MAKE_DEFINES = -DNR_LANES=$(nr_lanes) -DVLEN=$(vlen)
 DEFINES += $(ENV_DEFINES) $(MAKE_DEFINES)
 
 # Common flags
 RISCV_WARNINGS += -Wunused-variable -Wall -Wextra -Wno-unused-command-line-argument # -Werror
 
 # LLVM Flags
-LLVM_FLAGS     ?= -march=rv64gcv_zfh_zvfh -menable-experimental-extensions -mabi=$(RISCV_ABI) -mno-relax -fuse-ld=lld
+LLVM_FLAGS     ?= -march=rv64gcv_zfh_zvfh -mabi=$(RISCV_ABI) -mno-relax -fuse-ld=lld
 LLVM_V_FLAGS   ?= -fno-vectorize -mllvm -scalable-vectorization=off -mllvm -riscv-v-vector-bits-min=0 -mno-implicit-float
-RISCV_FLAGS    ?= $(LLVM_FLAGS) $(LLVM_V_FLAGS) -mcmodel=medany -I$(CURDIR)/common -std=gnu99 -O3 -ffast-math -fno-common -fno-builtin-printf $(DEFINES) $(RISCV_WARNINGS)
-RISCV_CCFLAGS  ?= $(RISCV_FLAGS) -ffunction-sections -fdata-sections
-RISCV_CCFLAGS_SPIKE  ?= $(RISCV_FLAGS) $(SPIKE_CCFLAGS) -ffunction-sections -fdata-sections
+RISCV_FLAGS    ?= $(LLVM_FLAGS) $(LLVM_V_FLAGS) -mcmodel=medany -I$(CURDIR)/common -O3 -ffast-math -fno-common -fno-builtin-printf $(DEFINES) $(RISCV_WARNINGS)
+ifeq ($(LINUX),1)
+RISCV_CCFLAGS  ?= -march=rv64gcv -mabi=$(RISCV_ABI) -I$(CURDIR)/common -O2 $(DEFINES)
+RISCV_LDFLAGS  ?= -lm -lstdc++
+RISCV_CXXFLAGS ?= -march=rv64gcv -mabi=$(RISCV_ABI) -I$(CURDIR)/common -O2 $(DEFINES)
+else
+RISCV_CCFLAGS  ?= $(RISCV_FLAGS) -ffunction-sections -fdata-sections -std=gnu99
+RISCV_LDFLAGS  ?= -static -nostartfiles -lm -Wl,--gc-sections -T$(CURDIR)/common/link.ld
+endif
+RISCV_CCFLAGS_SPIKE  ?= $(RISCV_FLAGS) $(SPIKE_CCFLAGS) -ffunction-sections -fdata-sections -std=gnu99
 RISCV_CXXFLAGS ?= $(RISCV_FLAGS) -ffunction-sections -fdata-sections
-RISCV_LDFLAGS  ?= -static -nostartfiles -lm -Wl,--gc-sections
-RISCV_LDFLAGS_SPIKE  ?= $(RISCV_LDFLAGS) $(SPIKE_LDFLAGS) -Wl,--gc-sections
+RISCV_LDFLAGS_SPIKE  ?= -static -nostartfiles -lm $(SPIKE_LDFLAGS) -Wl,--gc-sections
 
 # GCC Flags
-RISCV_FLAGS_GCC    ?= -mcmodel=medany -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI) -I$(CURDIR)/common -static -std=gnu99 -O3 -ffast-math -fno-common -fno-builtin-printf $(DEFINES) $(RISCV_WARNINGS)
-RISCV_CCFLAGS_GCC  ?= $(RISCV_FLAGS_GCC)
+RISCV_FLAGS_GCC    ?= -mcmodel=medany -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI) -I$(CURDIR)/common -static -O3 -ffast-math -fno-common -fno-builtin-printf $(DEFINES) $(RISCV_WARNINGS)
+RISCV_CCFLAGS_GCC  ?= $(RISCV_FLAGS_GCC) -std=gnu99
 RISCV_CXXFLAGS_GCC ?= $(RISCV_FLAGS_GCC)
-RISCV_LDFLAGS_GCC  ?= -static -nostartfiles -lm -lgcc $(RISCV_FLAGS_GCC)
+RISCV_LDFLAGS_GCC  ?= -static -nostartfiles -lm -lgcc $(RISCV_FLAGS_GCC) -std=gnu99 -T$(CURDIR)/common/link.ld
 
 ifeq ($(COMPILER),gcc)
 	RISCV_OBJDUMP_FLAGS ?=
 else
+ifneq ($(LINUX),1)
 	RISCV_OBJDUMP_FLAGS ?= --mattr=v
 endif
+endif
 
 # Compile two different versions of the runtime, since we cannot link code compiled with two different toolchains
 RUNTIME_GCC   ?= common/crt0-gcc.S.o common/printf-gcc.c.o common/string-gcc.c.o common/serial-gcc.c.o common/util-gcc.c.o
+ifeq ($(LINUX),1)
+RUNTIME_LLVM  ?= common/util-llvm.c.o
+else
 RUNTIME_LLVM  ?= common/crt0-llvm.S.o common/printf-llvm.c.o common/string-llvm.c.o common/serial-llvm.c.o common/util-llvm.c.o
+endif
 RUNTIME_SPIKE ?= $(spike_env_dir)/benchmarks/common/crt.S.o.spike $(spike_env_dir)/benchmarks/common/syscalls.c.o.spike common/util.c.o.spike
 
 .INTERMEDIATE: $(RUNTIME_GCC) $(RUNTIME_LLVM)
diff --git a/config/8_lanes.mk b/config/8_lanes.mk
index b6b9f97..b07a3b9 100644
--- a/config/8_lanes.mk
+++ b/config/8_lanes.mk
@@ -20,7 +20,7 @@
 # Number of vector lanes
 nr_lanes ?= 8
 # Number of clusters
-nr_clusters ?= 2
+nr_clusters ?= 4
 
 # Length of each vector register (in bits)
 # Constraints: VLEN > 128
diff --git a/hardware/Makefile b/hardware/Makefile
index 7f78781..aa88935 100644
--- a/hardware/Makefile
+++ b/hardware/Makefile
@@ -129,6 +129,8 @@ ifneq ($(ring_latency), 0)
 endif
 
 bender_defs += --define USE_EEW1
+bender_defs_veril := $(bender_defs) --define COMMON_CELLS_ASSERTS_OFF
+
 #use_eew1 ?= 0
 #ifneq ($(use_eew1), 0)
 #	bender_defs += --define USE_EEW1
@@ -209,7 +211,7 @@ verilate: $(buildpath) bender $(veril_library)/V$(veril_top)
 
 $(veril_library)/V$(veril_top): $(config_file) Makefile ../Bender.yml $(shell find src -type f) $(shell find ../config -type f) $(shell find include -type f) $(shell find tb -type f) $(shell find deps -type f)
 	rm -rf $(veril_library); mkdir -p $(veril_library)
-	$(BENDER) script verilator $(bender_targs_veril) $(bender_defs) > $(veril_library)/bender_script_$(config)
+	$(BENDER) script verilator $(bender_targs_veril) $(bender_defs_veril) > $(veril_library)/bender_script_$(config)
 # Verilate the design
 	$(veril_path)/verilator -f $(veril_library)/bender_script_$(config)           \
   -O3                                                                           \
diff --git a/hardware/src/vlsu/shuffle_stage.sv b/hardware/src/vlsu/shuffle_stage.sv
index a232215..5b452ce 100644
--- a/hardware/src/vlsu/shuffle_stage.sv
+++ b/hardware/src/vlsu/shuffle_stage.sv
@@ -38,7 +38,7 @@ module shuffle_stage import ara_pkg::*; import rvv_pkg::*;  #(
   output  axi_resp_t [NrClusters-1:0] axi_resp_o
 );
 
-if (NrClusters == 1) begin 
+if (NrClusters == 1) begin
   assign axi_req_o  = axi_req_i;
   assign axi_resp_o = axi_resp_i;
 end else begin

From 8971c765fa3e9ae9d4eeed93d905524f05427b83 Mon Sep 17 00:00:00 2001
From: Hong Pang <hopang@larain5.ee.ethz.ch>
Date: Tue, 4 Nov 2025 18:39:18 +0100
Subject: [PATCH 31/37] [makefile] add NrClusters param in runtime.mk

---
 apps/common/runtime.mk | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/apps/common/runtime.mk b/apps/common/runtime.mk
index a681a92..18ec921 100644
--- a/apps/common/runtime.mk
+++ b/apps/common/runtime.mk
@@ -93,7 +93,7 @@ endif
 ifeq ($(vcd_dump),1)
 ENV_DEFINES += -DVCD_DUMP=1
 endif
-MAKE_DEFINES = -DNR_LANES=$(nr_lanes) -DVLEN=$(vlen)
+MAKE_DEFINES = -DNR_LANES=$(nr_lanes) -DVLEN=$(vlen) -DNR_CLUSTERS=$(nr_clusters)
 DEFINES += $(ENV_DEFINES) $(MAKE_DEFINES)
 
 # Common flags

From e36bb6c3135a34157be7d75ff82295b0cadc8fea Mon Sep 17 00:00:00 2001
From: Hong Pang <hopang@larain5.ee.ethz.ch>
Date: Tue, 4 Nov 2025 19:19:59 +0100
Subject: [PATCH 32/37] [config] limited total number of lanes under 16

---
 config/8_lanes.mk | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/config/8_lanes.mk b/config/8_lanes.mk
index b07a3b9..b6b9f97 100644
--- a/config/8_lanes.mk
+++ b/config/8_lanes.mk
@@ -20,7 +20,7 @@
 # Number of vector lanes
 nr_lanes ?= 8
 # Number of clusters
-nr_clusters ?= 4
+nr_clusters ?= 2
 
 # Length of each vector register (in bits)
 # Constraints: VLEN > 128

From f7b48d3a976240c20d55cd0fbd3258ff9e1ab3de Mon Sep 17 00:00:00 2001
From: Hong Pang <hopang@larain5.ee.ethz.ch>
Date: Tue, 4 Nov 2025 19:33:25 +0100
Subject: [PATCH 33/37] [makefile] add rvv isa ara_tests

---
 hardware/Makefile | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hardware/Makefile b/hardware/Makefile
index aa88935..8c1c656 100644
--- a/hardware/Makefile
+++ b/hardware/Makefile
@@ -202,6 +202,7 @@ simc: compile
 # RISC-V Tests simulation
 APPS_DIR := $(abspath $(ROOT_DIR)/../apps)
 TESTS_DIR := $(APPS_DIR)/riscv-tests/isa
+include $(APPS_DIR)/common/riscv_tests.mk
 
 tests := $(ara_tests) $(cva6_tests)
 

From f08f3be07b9061edc5fd2e01fe14b1bd89223050 Mon Sep 17 00:00:00 2001
From: Hong Pang <hopang@larain5.ee.ethz.ch>
Date: Fri, 14 Nov 2025 15:59:30 +0100
Subject: [PATCH 34/37] [Config] Change configuration file for NrLanes and
 NrClusters

---
 config/16_lanes.mk | 4 ++--
 config/2_lanes.mk  | 2 +-
 config/4_lanes.mk  | 4 ++--
 config/8_lanes.mk  | 2 +-
 4 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/config/16_lanes.mk b/config/16_lanes.mk
index 86a776e..55e573d 100644
--- a/config/16_lanes.mk
+++ b/config/16_lanes.mk
@@ -18,9 +18,9 @@
 #         Matheus Cavalcante, ETH Zurich
 
 # Number of vector lanes
-nr_lanes ?= 16
+nr_lanes ?= 4
 # Number of clusters
-nr_clusters ?= 1
+nr_clusters ?= 4
 
 # Length of each vector register (in bits)
 # Constraints: VLEN > 128
diff --git a/config/2_lanes.mk b/config/2_lanes.mk
index 5edb8a4..6c0e0c8 100644
--- a/config/2_lanes.mk
+++ b/config/2_lanes.mk
@@ -20,7 +20,7 @@
 # Number of vector lanes
 nr_lanes ?= 2
 # Number of clusters
-nr_clusters ?= 4
+nr_clusters ?= 1
 
 # Length of each vector register (in bits)
 # Constraints: VLEN > 128
diff --git a/config/4_lanes.mk b/config/4_lanes.mk
index 7edea50..cf76672 100644
--- a/config/4_lanes.mk
+++ b/config/4_lanes.mk
@@ -18,9 +18,9 @@
 #         Matheus Cavalcante, ETH Zurich
 
 # Number of vector lanes
-nr_lanes ?= 4
+nr_lanes ?= 2
 # Number of clusters
-nr_clusters ?= 4
+nr_clusters ?= 2
 
 # Length of each vector register (in bits)
 # Constraints: VLEN > 128
diff --git a/config/8_lanes.mk b/config/8_lanes.mk
index b6b9f97..1a63aac 100644
--- a/config/8_lanes.mk
+++ b/config/8_lanes.mk
@@ -18,7 +18,7 @@
 #         Matheus Cavalcante, ETH Zurich
 
 # Number of vector lanes
-nr_lanes ?= 8
+nr_lanes ?= 4
 # Number of clusters
 nr_clusters ?= 2
 

From 6d8fa8b731c563cd67cb671c168dbc5d98385941 Mon Sep 17 00:00:00 2001
From: Hong Pang <hopang@larain5.ee.ethz.ch>
Date: Fri, 14 Nov 2025 16:12:09 +0100
Subject: [PATCH 35/37] [CI] Disable 2_lanes configuration first

---
 .github/workflows/ci.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
index 81258d8..d8224e0 100644
--- a/.github/workflows/ci.yml
+++ b/.github/workflows/ci.yml
@@ -222,7 +222,7 @@ jobs:
     strategy:
       max-parallel: 1
       matrix:
-        ara_config: [2_lanes, 4_lanes, 8_lanes, 16_lanes]
+        ara_config: [4_lanes, 8_lanes, 16_lanes]
     needs: tc-llvm
     steps:
     - uses: actions/checkout@v4

From b24b4df7a7e746ee02bd1b1b56be32c3753bc36d Mon Sep 17 00:00:00 2001
From: Hong Pang <hopang@larain5.ee.ethz.ch>
Date: Fri, 14 Nov 2025 16:22:38 +0100
Subject: [PATCH 36/37] [CI] Disable 2_lanes tests

---
 .github/workflows/ci.yml | 32 ++++++++++++++++----------------
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
index d8224e0..60782c3 100644
--- a/.github/workflows/ci.yml
+++ b/.github/workflows/ci.yml
@@ -254,7 +254,7 @@ jobs:
     strategy:
       max-parallel: 1
       matrix:
-        ara_config: [2_lanes, 4_lanes, 8_lanes, 16_lanes]
+        ara_config: [4_lanes, 8_lanes, 16_lanes]
     needs: ["tc-llvm", "tc-gcc", "tc-isa-sim"]
     steps:
     - uses: actions/checkout@v4
@@ -293,7 +293,7 @@ jobs:
     strategy:
       max-parallel: 1
       matrix:
-        ara_config: [2_lanes, 4_lanes, 8_lanes, 16_lanes]
+        ara_config: [4_lanes, 8_lanes, 16_lanes]
     needs: ["tc-verilator", "tc-isa-sim"]
     steps:
     - uses: actions/checkout@v4
@@ -344,7 +344,7 @@ jobs:
       max-parallel: 1
       matrix:
         app:        [hello_world, imatmul, fmatmul, iconv2d, fconv2d, jacobi2d, exp, softmax, dotproduct, fdotproduct, fconv3d, pathfinder, roi_align, lavamd, dwt, dropout, fft, gemv]
-        ara_config: [2_lanes, 4_lanes, 8_lanes, 16_lanes]
+        ara_config: [4_lanes, 8_lanes, 16_lanes]
     needs: ["compile-ara", "compile-apps"]
     steps:
     - uses: actions/checkout@v4
@@ -377,7 +377,7 @@ jobs:
     strategy:
       max-parallel: 1
       matrix:
-        ara_config: [2_lanes, 4_lanes, 8_lanes, 16_lanes]
+        ara_config: [4_lanes, 8_lanes, 16_lanes]
     needs: ["compile-ara", "compile-riscv-tests"]
     steps:
     - uses: actions/checkout@v4
@@ -511,7 +511,7 @@ jobs:
     strategy:
       max-parallel: 1
       matrix:
-        ara_config: [2_lanes, 4_lanes, 8_lanes, 16_lanes]
+        ara_config: [4_lanes, 8_lanes, 16_lanes]
     needs: ["compile-ara", "compile-apps"]
     steps:
     - uses: actions/checkout@v4
@@ -569,10 +569,10 @@ jobs:
     - name: Install Python requirements
       run: pip install -r python-requirements.txt
     - uses: actions/checkout@v4
-    - name: Get [f]dotproduct results (2 lanes)
-      uses: actions/download-artifact@v4
-      with:
-        name: dotproducts-2_lanes
+    # - name: Get [f]dotproduct results (2 lanes)
+    #   uses: actions/download-artifact@v4
+    #   with:
+    #     name: dotproducts-2_lanes
     - name: Get [f]dotproduct results (4 lanes)
       uses: actions/download-artifact@v4
       with:
@@ -585,10 +585,10 @@ jobs:
       uses: actions/download-artifact@v4
       with:
         name: dotproducts-16_lanes
-    - name: Get benchmark results (2 lanes)
-      uses: actions/download-artifact@v4
-      with:
-        name: benchmark-2_lanes
+    # - name: Get benchmark results (2 lanes)
+    #   uses: actions/download-artifact@v4
+    #   with:
+    #     name: benchmark-2_lanes
     - name: Get benchmark results (4 lanes)
       uses: actions/download-artifact@v4
       with:
@@ -603,13 +603,13 @@ jobs:
         name: benchmark-16_lanes
     - name: Untar the [f]dotproduct results
       run: |
-        tar xvf dotproducts-2_lanes.tar
+        # tar xvf dotproducts-2_lanes.tar
         tar xvf dotproducts-4_lanes.tar
         tar xvf dotproducts-8_lanes.tar
         tar xvf dotproducts-16_lanes.tar
     - name: Untar the results
       run: |
-        tar xvf benchmarks-2_lanes.tar
+        # tar xvf benchmarks-2_lanes.tar
         tar xvf benchmarks-4_lanes.tar
         tar xvf benchmarks-8_lanes.tar
         tar xvf benchmarks-16_lanes.tar
@@ -736,7 +736,7 @@ jobs:
     strategy:
       max-parallel: 1
       matrix:
-        ara_config: [2_lanes, 4_lanes, 8_lanes, 16_lanes]
+        ara_config: [4_lanes, 8_lanes, 16_lanes]
     if: always()
     # needs: ["simulate", "riscv-tests-spike", "riscv-tests-simv"]
     needs: ["simulate"]

From 36503b28bd862c1f386ec4e55ed0909e72a719da Mon Sep 17 00:00:00 2001
From: Hong Pang <hopang@larain5.ee.ethz.ch>
Date: Mon, 17 Nov 2025 14:21:43 +0100
Subject: [PATCH 37/37] [CI] Shrink kernel tests

---
 .github/workflows/ci.yml | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
index 60782c3..17bd4c8 100644
--- a/.github/workflows/ci.yml
+++ b/.github/workflows/ci.yml
@@ -343,7 +343,8 @@ jobs:
     strategy:
       max-parallel: 1
       matrix:
-        app:        [hello_world, imatmul, fmatmul, iconv2d, fconv2d, jacobi2d, exp, softmax, dotproduct, fdotproduct, fconv3d, pathfinder, roi_align, lavamd, dwt, dropout, fft, gemv]
+        # app:        [hello_world, imatmul, fmatmul, iconv2d, fconv2d, jacobi2d, exp, softmax, dotproduct, fdotproduct, fconv3d, pathfinder, roi_align, lavamd, dwt, dropout, fft, gemv]
+        app:        [hello_world, imatmul, fmatmul, exp, softmax, dotproduct, fdotproduct, gemv, fconv2d]
         ara_config: [4_lanes, 8_lanes, 16_lanes]
     needs: ["compile-ara", "compile-apps"]
     steps: