diff --git a/src/train/eda/chip-circuit/Part_2-chip_files/2_4_DEF.md b/src/train/eda/chip-circuit/Part_2-chip_files/2_4_DEF.md
index c1458e0..b3e31bc 100644
--- a/src/train/eda/chip-circuit/Part_2-chip_files/2_4_DEF.md
+++ b/src/train/eda/chip-circuit/Part_2-chip_files/2_4_DEF.md
@@ -25,7 +25,7 @@ DEF文件包含电路的特定设计信息，它是在物理设计过程中任
 - [ DESIGN 声明 ]
 - [ TECHNOLOGY 声明 ]
 - [ UNITS 声明 ]
-- [ DIAAREA 声明 ]  
+- [ DIEAREA 声明 ]  
 <br>
 - [ ROW 声明 ]
 - [ TRACKS 声明 ]
@@ -436,4 +436,4 @@ site & row 是布局的概念。site定义在LEF文件中，定义了其宽与
 ## 引用
 
 [1] https://teamvlsi.com/2020/08/def-file-in-vlsi-design-exchange.html
-[2] LEF/DEF Language Reference
\ No newline at end of file
+[2] LEF/DEF Language Reference