diff --git a/DEVELOP.md b/DEVELOP.md index a9b851c55..94f05fc3f 100644 --- a/DEVELOP.md +++ b/DEVELOP.md @@ -121,6 +121,47 @@ The following is a running list of those writings. * [How Bluesim provides implementations for import-BVI](https://groups.io/g/b-lang-discuss/topic/106520424) * [How the Bluesim C API is imported into Bluetcl](https://groups.io/g/b-lang-discuss/message/554) * There is a template for making Bluesim standalone programs (without Tcl) in `bsc/util/bsim_standalone/` +* `-c` (codegen mode): per-module byte-identity and object reuse (see below) + +#### `-c` (codegen mode): per-module byte-identity + +Terminology: a module generated as a `-e` link's *top* is in "top form" (its +interface methods are fired by the design schedule that the link also +generates); everywhere else -- under `-c`, or as a submodule of any design -- +it is in "block form". Block form is the shared, reusable output; top form +is private to the link that made it. + +`-sim -c M` emits `M`'s Bluesim C++ (and only `M`'s) without a runnable top, so +`M`'s object can be built once and reused wherever `M` appears in a design. +Reuse *trusts* byte-identity: `isStale` (`SimFileUtils.hs`) reuses an object on a +version/timestamp/`codeGenOptionDescr` match, never comparing content -- so +`M`'s `-c` output must equal the C++ it gets as a submodule. (A link's own +top is the exception: it is generated in "top form", which the descriptor +records as `top`, so the two forms are never mixed by reuse.) + +It does, because both are generated from the same already-elaborated `M.ba`; +only two things differ between the runs, and both are neutralized: + +* **Interned-`Id` order** varies with what else is compiled, but only *reorders* + output, and every per-module emission site is name-sorted (the four + "Canonicalize ... order" commits, plus pre-existing sorts). +* **The schedule** (`M`'s own, firing-suppressed, vs the whole design's) reaches + per-module codegen through three channels, each made `M`-intrinsic: + *top-ness* (`mkScheduleStmts` drops `M`'s own interface-method firing, so DCE + gives submodule form), *VCD clock annotation* (`clk_map`; the emitted domain + comes from `M.ba`), and *member-vs-local* (`moveDefsOntoStack`; a top + interface method's readiness is reached by the RDY call, as a parent would, + not a direct read). + +`check_block_codegen_modules` (`testsuite/config/unix.exp`) enforces it: it +rebuilds every multi-module test's submodules with `-c` and byte-compares. + +The Verilog backend has the same mode: `-verilog -c M` regenerates `M.v` from +`M.ba` (via `vGenMods` in `bsc.hs`), byte-identical to the `.v` that `-g` +writes for the same elaboration under the same generation flags. Codegen +flags are read from the `-c` invocation's command line (elaboration-affecting +flags are baked into the `.ba`), and foreign-function `.ba` files are found +via the same `-p`/`-bdir` search path as at link time. ### Bluetcl diff --git a/src/comp/ABin.hs b/src/comp/ABin.hs index 1dc6ce2b8..a20c951da 100644 --- a/src/comp/ABin.hs +++ b/src/comp/ABin.hs @@ -15,7 +15,6 @@ module ABin (ABin(..), abemi_rule_relation_db ) where -import Data.Maybe(isNothing) import PPrint import Id(Id) import Position(Position) @@ -28,7 +27,6 @@ import ADumpScheduleInfo(MethodDumpInfo) import VModInfo(VPathInfo) import ForeignFunctions(ForeignFunction(..)) import Flags(Flags(..)) -import Verilog(VProgram) -- =============== @@ -62,9 +60,7 @@ data ABinModInfo = abmi_oqt :: CQType, abmi_method_dump :: MethodDumpInfo, abmi_pathinfo :: VPathInfo, - abmi_flags :: Flags, - -- the generated Verilog - abmi_vprogram :: Maybe VProgram + abmi_flags :: Flags } data ABinForeignFuncInfo = @@ -113,7 +109,7 @@ instance PPrint ABin where instance PPrint ABinModInfo where - pPrint d p (ABinModInfo path srcName apkg aschedinfo pps oqt mi pathinfo flags vprog) = + pPrint d p (ABinModInfo path srcName apkg aschedinfo pps oqt mi pathinfo flags) = text "path:" <+> text path $+$ text "package:" <+> text srcName $+$ pPrint d 0 apkg $+$ @@ -121,11 +117,8 @@ instance PPrint ABinModInfo where text "pprop:" <+> pPrint d 0 pps $+$ text "oqt:" <+> pPrint d 0 oqt $+$ -- no dump of method info - text "pathinfo:" <+> pPrint d 0 pathinfo $+$ + text "pathinfo:" <+> pPrint d 0 pathinfo -- no dump of flags - text "vprog:" <+> (if (isNothing vprog) - then text "Nothing" - else text "Just ...") -- no dump of contents instance PPrint ABinForeignFuncInfo where diff --git a/src/comp/ABinUtil.hs b/src/comp/ABinUtil.hs index e28615f85..914f85924 100644 --- a/src/comp/ABinUtil.hs +++ b/src/comp/ABinUtil.hs @@ -4,6 +4,7 @@ module ABinUtil ( readAndCheckABin, readAndCheckABinPath, readAndCheckABinPathCatch, + isStaleABinFile, ) where import Data.List(nub, partition) @@ -16,7 +17,7 @@ import Control.Monad.State(StateT, runStateT, lift, get, put) import Version(bscVersionStr) import Backend import FileNameUtil(abinSuffix) -import FileIOUtil(readBinaryFileCatch, readBinFilePath) +import FileIOUtil(readBinaryFileCatch, readBinFilePath, readBinaryFileMaybe) import Util(fromMaybeM) import Error(internalError, EMsg, EMsgs(..), ErrMsg(..), @@ -29,7 +30,9 @@ import ASyntaxUtil(getForeignCallNames) import VModInfo(vName, getVNameString) import ForeignFunctions(ForeignFunction(..), ForeignFuncMap) import ABin -import GenABin(readABinFile) +import GenABin(readABinFile, readABinFileMaybe) + +import qualified Control.Exception as CE import qualified Data.Map as M @@ -532,4 +535,31 @@ decodeABin errh backend filename contents = -- from this point (ABinModSchedErr {}) -> Right abi +-- Tolerant counterpart of the decodeABin checks, for deciding whether +-- an existing .ba file can be used by the current compilation: it must +-- be readable, in the current format and BSC version, and elaborated +-- for a compatible backend. A missing file returns False (not stale); +-- absence is the timestamp check's concern. Used by the -u +-- recompilation check, where an unusable .ba (e.g. one left by +-- "-verilog -g" when compiling with -sim, or written by another BSC +-- version) must force re-elaboration rather than be trusted as an +-- up-to-date generated product. +isStaleABinFile :: Maybe Backend -> String -> IO Bool +isStaleABinFile be fname = do + mbytes <- readBinaryFileMaybe fname + case mbytes of + Nothing -> return False + Just bytes -> + let beOf (ABinMod mi _) = apkg_backend (abmi_apkg mi) + beOf (ABinModSchedErr mi _) = apkg_backend (abmsei_apkg mi) + beOf (ABinForeignFunc {}) = Nothing + stale = case readABinFileMaybe bytes of + Nothing -> True + Just abin -> + (ab_version abin /= bscVersionStr True) || + not (backendMatches be (beOf abin)) + in CE.evaluate stale `CE.catch` handler + where handler :: CE.SomeException -> IO Bool + handler _ = return True + -- =============== diff --git a/src/comp/Depend.hs b/src/comp/Depend.hs index 7bf3a03d4..4895aa85c 100644 --- a/src/comp/Depend.hs +++ b/src/comp/Depend.hs @@ -28,11 +28,12 @@ import FStringCompat import Lex import Parse import FileNameUtil(hasDotSuf, dropSuf, baseName, dirName, - bscSrcSuffix, bsvSrcSuffix, binSuffix, + bscSrcSuffix, bsvSrcSuffix, binSuffix, abinSuffix, mkAName, mkVName, mkVPIHName, mkVPICName, createEncodedFullFilePath) import FileIOUtil(readFilesPath, readBinFilePath, readFileCatch, writeFileCatch, removeFileCatch) +import ABinUtil(isStaleABinFile) import Id import PreIds(idPrelude, idPreludeBSV) import Parser.Classic(pPackage, errSyntax, classicWarnings) @@ -263,7 +264,14 @@ chkUpd flags doneMap resultList (pi:pis) = do --putStrLn (show genfs) genfsClks <- mapM getModTime genfs incfsClks <- mapM getModTime incfs - let needGenUpd = any (srcMod pi >) genfsClks + -- a .ba that exists (and is fresh by timestamp) is still not a + -- valid generated product if it cannot be read (another BSC + -- version's format) or was elaborated for an incompatible backend + -- (a Verilog-tagged .ba left by "-verilog -g" must not satisfy a + -- -sim compile, or vice versa); codegen must run again + staleAbins <- mapM (isStaleABinFile (backend flags)) + (filter (hasDotSuf abinSuffix) genfs) + let needGenUpd = any (srcMod pi >) genfsClks || or staleAbins needIncUpd = any (lastMod pi <) incfsClks --putStrLn (show (fileName pi, genfs, map (srcMod pi >) genfsClks)) --putStr (ppReadable (pkgName pi, imports pi, DM.keys doneMap)) diff --git a/src/comp/Error.hs b/src/comp/Error.hs index 424bdde54..690b823f3 100644 --- a/src/comp/Error.hs +++ b/src/comp/Error.hs @@ -1154,6 +1154,11 @@ data ErrMsg = -- Bluesim-specific errors/warnings | EBluesimNoXZ String + -- Errors for the .ba -> code generation mode (-c) + | EGenWithEntry String + | EGenWithSrcFile String + | EGenWithSystemC + -- Errors/warnings from the SystemC wrapper generator | ESystemCWrapperComboPaths String | ESystemCWrapperInvalidMethods [String] @@ -4500,6 +4505,22 @@ getErrorText (EMissingVPIWrapperFile fname is_dpi) = in s2par ("Cannot find the " ++ ifctype ++ " file " ++ ishow fname ++ " in the Verilog search path.")) +getErrorText (EGenWithEntry entry) = + (System 96, empty, + s2par ("The flag -c generates code from an elaborated module; " ++ + "it cannot be combined with -e (linking). To link " ++ + ishow entry ++ ", run bsc again with -e.")) + +getErrorText (EGenWithSrcFile fname) = + (System 97, empty, + s2par ("The flag -c operates on elaborated (.ba) files, so a " ++ + "source file (" ++ ishow fname ++ ") cannot be provided. " ++ + "To compile and generate from source, use -g.")) + +getErrorText EGenWithSystemC = + (System 98, empty, + s2par ("The flag -c is not supported with -systemc; use -sim.")) + -- Runtime errors getErrorText (EMutuallyExclusiveRulesFire r1 r2) = (Runtime 1, empty, diff --git a/src/comp/Flags.hs b/src/comp/Flags.hs index 5e002b084..bae934fec 100644 --- a/src/comp/Flags.hs +++ b/src/comp/Flags.hs @@ -26,6 +26,10 @@ data Flags = Flags { backend :: Maybe Backend, bdir :: Maybe String, biasMethodScheduling :: Bool, + -- internal: set by the driver when in -c mode (generate a module's + -- code from its .ba, as a reusable block rather than a runnable top); + -- never settable from the command line -- see codegenNames + blockCodegen :: Bool, bluespecDir :: String, cIncPath :: [String], cLibPath :: [String], @@ -45,13 +49,13 @@ data Flags = Flags { dumpAll :: Maybe (Maybe FilePath), -- maybe dump to file or stdout dumps :: [(DumpFlag, Maybe FilePath)], -- dump to file or stdout enablePoisonPills :: Bool, + codegenNames :: [String], entry :: Maybe String, expandATSlimit :: Int, expandIf :: Bool, fdir :: Maybe String, finalcleanup :: Int, genABin :: Bool, - genABinVerilog :: Bool, genName :: [String], genSysC :: Bool, ifcPathRaw :: [String], diff --git a/src/comp/FlagsDecode.hs b/src/comp/FlagsDecode.hs index 31b928d7b..94812e288 100644 --- a/src/comp/FlagsDecode.hs +++ b/src/comp/FlagsDecode.hs @@ -147,6 +147,8 @@ data Decoded = DHelp Flags -- Display the public help message | DVerLink Flags String [VFileName] [String] [String] -- entry, ABin files and C files to be generated and linked | DSimLink Flags String [String] [String] + -- modules to generate code for (-c) and ABin files + | DCodeGen Flags [String] [String] decodeArgs :: String -> [String] -> String -> ([WMsg], Decoded) decodeArgs prog args cdir = @@ -164,6 +166,11 @@ decodeArgs prog args cdir = (printFlagsHidden flags) || (printFlagsRaw flags)) then (warnings, DNoSrc flags) + else + -- -c mode needs no file names; the .ba files + -- are found by module name on the search path + if not (null (codegenNames flags)) + then (warnings, checkCodeGenFlags flags []) else -- We allow the file names to be omitted if the -- backend and entry point are both specified case (entry flags) of @@ -201,6 +208,12 @@ decodeArgs prog args cdir = ELinkFilesWithSrc name known_ext_names)] else DError [(cmdPosition, EUnrecognizedCmdLineText (head names))]) + -- -c mode consumes only .ba files; this must + -- come before the all-HDL case below, so that + -- "-c mkFoo foo.v" errors rather than being + -- treated as implicit-Verilog linking + ([], names) | not (null (codegenNames flags)) -> + (warnings, checkCodeGenFlags flags names) -- Backwards support for optional -verilog. ([], names) | all isHDLSrcFile names -> -- generation flag not supported during linking @@ -232,6 +245,10 @@ decodeArgs prog args cdir = -- check that the flags are OK for compiling Bluespec src file checkBSrcFlags :: Flags -> String -> Decoded checkBSrcFlags flags filename = + -- -c generates from .ba files, not from source + if not (null (codegenNames flags)) + then DError [(cmdPosition, EGenWithSrcFile filename)] + else -- if generate is requested, require a backend if not (null (genName flags)) && (backend flags == Nothing) then DError [(cmdPosition, ENoBackendCodeGen (genName flags))] @@ -309,6 +326,52 @@ checkLinkFlags flags names = else DError [(cmdPosition, ENoBackendLinking)] +-- check that the flags are OK for the .ba -> code generation mode (-c) +checkCodeGenFlags :: Flags -> [String] -> Decoded +checkCodeGenFlags flags names = + let (anames, bad_names) = partition isABinFile names + mods = codegenNames flags + errBadName name = + if not (elem '.' name) + then (cmdPosition, ENoSrcExt name) + else (cmdPosition, EUnknownSrcExt (takeSuf name)) + bad_name_errs = map errBadName bad_names + in -- check for flags after file names + checkNamesForFlag bad_names $ + -- -c consumes only .ba files (C and HDL files belong to link mode) + if not (null bad_names) + then DError bad_name_errs + else + -- -g compiles and generates from source, not from .ba + if not (null (genName flags)) + then DError [(cmdPosition, EGenNamesForLinking (genName flags))] + else + -- -e selects link mode, which is a separate step + case (entry flags) of + Just e -> DError [(cmdPosition, EGenWithEntry e)] + Nothing -> + -- SystemC generation has no per-module codegen mode + if (genSysC flags) + then DError [(cmdPosition, EGenWithSystemC)] + else + case (backend flags) of + Nothing -> DError [(cmdPosition, ENoBackendCodeGen mods)] + Just Bluesim -> + -- Only 2-state values are allowed for don't-cares + if ( (unSpecTo flags == "X") || (unSpecTo flags == "Z") ) + then DError [(cmdPosition, EBluesimNoXZ (unSpecTo flags))] + else + -- The -remove-dollar flag only applies to Verilog + if (removeVerilogDollar flags) + then DError [(cmdPosition, EDollarNoVerilog)] + else + -- Everything is OK for Bluesim code generation + DCodeGen flags mods anames + Just Verilog -> + -- Everything is OK for Verilog code generation + DCodeGen flags mods anames + + -- and, if so, error that flags must go before source files checkNamesForFlag :: [String] -> Decoded -> Decoded checkNamesForFlag bad_names dflt_result = @@ -518,6 +581,7 @@ defaultFlags bluespecdir = Flags { backend = Nothing, bdir = Nothing, biasMethodScheduling = False, + blockCodegen = False, bluespecDir = bluespecdir, cIncPath = [], cLibPath = [], @@ -528,6 +592,7 @@ defaultFlags bluespecdir = Flags { cppFlags = [], linkFlags = [], cdir = Nothing, + codegenNames = [], cpp = False, defines = [], demoteErrors = SomeMsgs [], @@ -543,7 +608,6 @@ defaultFlags bluespecdir = Flags { fdir = Nothing, finalcleanup = 1, genABin = False, - genABinVerilog = False, genName = [], genSysC = False, -- The ifcPath value will be produced from the raw value, @@ -1108,6 +1172,10 @@ externalFlags = [ (Toggle (\f x -> f {biasMethodScheduling=x}) (showIfTrue biasMethodScheduling), "schedule methods before rules when possible", Hidden)), + ("c", + (Arg "module" (\f s -> Left (f {codegenNames = codegenNames f ++ [s]})) (Just (FRTListString codegenNames)), + "generate code for `module' from its elaborated .ba file", Visible)), + ("check-assert", (Toggle (\f x -> f {testAssert=x}) (showIfTrue testAssert), "test assertions with the Assert library", Visible)), @@ -1153,11 +1221,7 @@ externalFlags = [ ("elab", (Toggle (\f x -> f {genABin=x}) (showIfTrue genABin), - "generate a .ba file after elaboration and scheduling", Visible)), - - ("elab-verilog", - (Toggle (\f x -> f {genABinVerilog=x}) (showIfTrue genABinVerilog), - "include generated Verilog in .ba files", Hidden)), + "generate a .ba file after elaboration and scheduling (on by default with -sim, -verilog and -systemc; -no-elab suppresses)", Visible)), ("expand-ATS-limit", (Arg "n" @@ -1677,7 +1741,9 @@ externalFlags = [ (Alias "quiet", "same as -quiet", Visible)), ("verilog", - let setFn f = setBackend f Verilog + let setFn f = case setBackend f Verilog of + Left f' -> Left f' { genABin = True } + Right e -> Right e getFn f = backend f == Just Verilog in (NoArg setFn (Just getFn), "compile BSV generating Verilog file", Visible)), @@ -1833,6 +1899,7 @@ showFlagsRaw flags = ("cLibPath", show (cLibPath flags)), ("cLibs", show (cLibs flags)), ("cdir", show (cdir flags)), + ("codegenNames", show (codegenNames flags)), ("cpp", show (cpp flags)), ("cppFlags", show (cppFlags flags)), ("cxxFlags", show (cxxFlags flags)), @@ -1850,7 +1917,6 @@ showFlagsRaw flags = ("fdir", show (fdir flags)), ("finalcleanup", show (finalcleanup flags)), ("genABin", show (genABin flags)), - ("genABinVerilog", show (genABinVerilog flags)), ("genName", show (genName flags)), ("genSysC", show (genSysC flags)), ("ifLift", show (ifLift flags)), diff --git a/src/comp/GenABin.hs b/src/comp/GenABin.hs index 55b34a360..73c15389f 100644 --- a/src/comp/GenABin.hs +++ b/src/comp/GenABin.hs @@ -1,7 +1,7 @@ {-# LANGUAGE CPP #-} {-# LANGUAGE FlexibleInstances #-} {-# OPTIONS_GHC -Werror -fwarn-incomplete-patterns #-} -module GenABin(genABinFile, readABinFile) where +module GenABin(genABinFile, readABinFile, readABinFileMaybe) where import Error(internalError, ErrMsg(..), ErrorHandle, bsErrorUnsafe) import Position @@ -34,7 +34,7 @@ import qualified Data.ByteString as B -- .ba file tag -- change this whenever the .ba format changes -- See also GenBin.header header :: [Byte] -header = B.unpack $ TE.encodeUtf8 $ T.pack "bsc-ba-20260712-1" +header = B.unpack $ TE.encodeUtf8 $ T.pack "bsc-ba-20260712-2" headerBS :: B.ByteString headerBS = B.pack header @@ -51,6 +51,15 @@ readABinFile errh nm s = --then (decodeWithHash (B.drop hlen s)) else bsErrorUnsafe errh [(noPosition, EBinFileVerMismatch nm)] +-- Tolerant variant: Nothing if the file tag does not match the current +-- format (e.g. the file was written by a different version of BSC) +readABinFileMaybe :: B.ByteString -> Maybe ABin +readABinFileMaybe s = + let hlen = B.length headerBS + in if B.take hlen s == headerBS + then Just (decode (B.drop hlen s)) + else Nothing + -- ---------- -- Bin ABin @@ -79,7 +88,6 @@ instance Bin ABin where toBin (abmi_method_dump modinfo) toBin (abmi_pathinfo modinfo) toBin (abmi_flags modinfo) - toBin (abmi_vprogram modinfo) writeBytes (ABinModSchedErr modinfo version) = section "ABinModSchedErr" $ do -- tag which kind of module @@ -110,10 +118,9 @@ instance Bin ABin where mi <- fromBin pathinfo <- fromBin flags <- fromBin - vprog <- fromBin let modinfo = ABinModInfo path srcName apkg asched pps - oqt mi pathinfo flags vprog + oqt mi pathinfo flags return (ABinMod modinfo version) 2 -> do path <- fromBin srcName <- fromBin @@ -561,9 +568,8 @@ instance Bin Flags where a_100 a_101 a_102 a_103 a_104 a_105 a_106 a_107 a_108 a_109 a_110 a_111 a_112 a_113 a_114 a_115 a_116 a_117 a_118 a_119 a_120 a_121 a_122 a_123 a_124 a_125 a_126 a_127 a_128 a_129 - a_130 a_131 a_132 a_133) = - do wr_chunk0; wr_chunk1; wr_chunk2; wr_chunk3; wr_chunk4; - wr_chunk5; wr_chunk6; wr_chunk7; wr_chunk8 + a_130 a_131 a_132 a_133 a_134) = + do wr_chunk0; wr_chunk1; wr_chunk2; wr_chunk3; wr_chunk4; wr_chunk5; wr_chunk6; wr_chunk7; wr_chunk8 where -- The 135-field serialization is split into NOINLINE chunks so -- that GHC optimizes bounded pieces: compiling it as a single @@ -612,7 +618,7 @@ instance Bin Flags where wr_chunk8 = do toBin a_120; toBin a_121; toBin a_122; toBin a_123; toBin a_124; toBin a_125; toBin a_126; toBin a_127; toBin a_128; toBin a_129; - toBin a_130; toBin a_131; toBin a_132; toBin a_133 + toBin a_130; toBin a_131; toBin a_132; toBin a_133; toBin a_134 readBytes = do (a_000, a_001, a_002, a_003, a_004, a_005, a_006, a_007, a_008, a_009, a_010, a_011, a_012, a_013, a_014) <- rd_chunk0 @@ -631,7 +637,7 @@ instance Bin Flags where (a_105, a_106, a_107, a_108, a_109, a_110, a_111, a_112, a_113, a_114, a_115, a_116, a_117, a_118, a_119) <- rd_chunk7 (a_120, a_121, a_122, a_123, a_124, a_125, a_126, a_127, - a_128, a_129, a_130, a_131, a_132, a_133) <- rd_chunk8 + a_128, a_129, a_130, a_131, a_132, a_133, a_134) <- rd_chunk8 return (Flags a_000 a_001 a_002 a_003 a_004 a_005 a_006 a_007 a_008 a_009 a_010 a_011 a_012 a_013 a_014 a_015 a_016 a_017 a_018 a_019 @@ -646,7 +652,7 @@ instance Bin Flags where a_100 a_101 a_102 a_103 a_104 a_105 a_106 a_107 a_108 a_109 a_110 a_111 a_112 a_113 a_114 a_115 a_116 a_117 a_118 a_119 a_120 a_121 a_122 a_123 a_124 a_125 a_126 a_127 a_128 a_129 - a_130 a_131 a_132 a_133) + a_130 a_131 a_132 a_133 a_134) where {-# NOINLINE rd_chunk0 #-} rd_chunk0 = @@ -708,9 +714,9 @@ instance Bin Flags where rd_chunk8 = do a_120 <- fromBin; a_121 <- fromBin; a_122 <- fromBin; a_123 <- fromBin; a_124 <- fromBin; a_125 <- fromBin; a_126 <- fromBin; a_127 <- fromBin; a_128 <- fromBin; a_129 <- fromBin; - a_130 <- fromBin; a_131 <- fromBin; a_132 <- fromBin; a_133 <- fromBin + a_130 <- fromBin; a_131 <- fromBin; a_132 <- fromBin; a_133 <- fromBin; a_134 <- fromBin return (a_120, a_121, a_122, a_123, a_124, a_125, a_126, a_127, - a_128, a_129, a_130, a_131, a_132, a_133) + a_128, a_129, a_130, a_131, a_132, a_133, a_134) -- ---------- diff --git a/src/comp/SimBlocksToC.hs b/src/comp/SimBlocksToC.hs index 94a05704d..18927d863 100644 --- a/src/comp/SimBlocksToC.hs +++ b/src/comp/SimBlocksToC.hs @@ -50,6 +50,7 @@ simBlocksToC flags time top_block def_clk def_rst -- within that block to the clock domain on which that signal is written. -- Since the Ids can be both in the port and def namespace, they are encoded as a pair -- "Bool,Id"). + -- (Emitted clock domain is from M.ba; see DEVELOP.md re -c mode.) matchesInst i1 = \(i2,_) -> q1' == getIdQual i2 where q1 = getIdQualString i1 q1' = mkFString $ if q1 == "top" then "" else drop 4 q1 @@ -94,9 +95,21 @@ simBlocksToC flags time top_block def_clk def_rst let wide_defs = M.findWithDefault [] mod wdef_mod_map ] let cvtModBlock = convertModuleBlock flags sb_map ff_map clk_map wdef_mod_map reused top_block - module_names <- concatMapM (cvtModBlock writeFileC) mod_blocks - schedule_names <- convertSchedules flags time top_block def_clk def_rst sb_map ff_map - wdef_inst_map scheds clk_groups gate_info writeFileC + -- In -c mode only the named root's files are written (the cc -c contract: + -- one module in, that module's outputs out). Submodules get their files + -- from their own -c invocations; their content is byte-identical either + -- way, so only which files are written changes, never their bytes. + let gen_blocks = if blockCodegen flags + then filter ((== top_block) . sb_id) mod_blocks + else mod_blocks + module_names <- concatMapM (cvtModBlock writeFileC) gen_blocks + -- In -c mode the root is a reusable block, not a runnable top: it + -- has no schedule of its own and no "model_" wrapper (whatever instantiates + -- it supplies the schedule), matching submodule form. + schedule_names <- if blockCodegen flags + then return [] + else convertSchedules flags time top_block def_clk def_rst sb_map ff_map + wdef_inst_map scheds clk_groups gate_info writeFileC return $ module_names ++ schedule_names lookupInstance :: SBMap -> Maybe SBId -> String -> Maybe SBId @@ -182,7 +195,10 @@ convertModuleBlock flags sb_map ff_map clk_map wdef_mod_map reused top_blk write wide_defs = M.findWithDefault [] (sb_id sb) wdef_mod_map wdef_inst_map = M.fromList [("", wide_defs)] uses_foreign_fn = blockCallsForeignFn sb - is_top = (sb_id sb) == top_blk + -- "top" here means generated in top form (the form the -e link's + -- schedule and model_ expect); in -c mode the root is generated + -- in block form, so its descriptor must say so + is_top = (sb_id sb) == top_blk && not (blockCodegen flags) -- list of subblocks that need to be included include_ids = nub (map (\(id,_,_)->id) (sb_state sb)) diff --git a/src/comp/SimCOpt.hs b/src/comp/SimCOpt.hs index 4d532d8e4..fbed4065a 100644 --- a/src/comp/SimCOpt.hs +++ b/src/comp/SimCOpt.hs @@ -6,7 +6,7 @@ import ASyntax import ASyntaxUtil import Id( Id, getIdBaseString, setIdBaseString , getIdQualString, setIdQualString - , unQualId, isFire ) + , unQualId, isFire, mkIdCanFire ) import ABinUtil(InstModMap) import ErrorUtil(internalError) import Util(mapSnd) @@ -123,7 +123,23 @@ moveDefsOntoStack flags instmodmap (blocks,scheds) = , let unqual_id = unQualId qual_id , let sbid = sb_id blk ] - sched_refs = [ (k, dr) | (k, (dr,_)) <- sched_tups ] + -- In -c mode, ignore reads of the root module's interface-method + -- CAN_FIRE defs made by the root's own schedule (which -c does not + -- emit). A parent module reaches that readiness through the RDY + -- method call rather than by reading the def, so ignoring these + -- reads gives each def the same member-vs-stack-local classification + -- it has in block (submodule) form. (See the DEVELOP.md section on + -- -c and byte-identity.) + bcgTopMethodCFs = + if not (blockCodegen flags) then S.empty + else case (do mod <- M.lookup "" instmodmap + find (\b -> sb_name b == mod) blocks) of + Nothing -> S.empty + Just tsb -> S.fromList [ (sb_id tsb, mkIdCanFire mid) + | (_, meths) <- sb_methods tsb + , (mid, _) <- meths ] + sched_refs = [ (k, dr) | (k, (dr,_)) <- sched_tups + , not (k `S.member` bcgTopMethodCFs) ] sched_defs = M.fromListWith combine_refs sched_refs sched_qids = M.fromListWith S.union [ (k, S.singleton q) | (k,(_,q)) <- sched_tups ] diff --git a/src/comp/SimExpand.hs b/src/comp/SimExpand.hs index 61de11f76..27a1e2f92 100644 --- a/src/comp/SimExpand.hs +++ b/src/comp/SimExpand.hs @@ -73,17 +73,20 @@ simExpand errh flags topname fabis = do assertNoSchedErr emodinfos_used_by_name -- reject top-level modules with always_enabled ifc, if generating - -- a Bluesim executable + -- a Bluesim executable; in -c mode the output is never + -- executed, so any module may serve as the codegen root let topModInfo = case (lookup (getIdString topmodId) modinfos_used_by_name) of Just (mi,_) -> mi Nothing -> internalError ("simExpand: topmodId not found") - when ((not (genSysC flags)) && (hasEnabledMethod topModInfo)) $ + when ((not (genSysC flags)) && (not (blockCodegen flags)) && + (hasEnabledMethod topModInfo)) $ bsError errh [(noPosition, EBSimEnablePragma)] -- reject top-level modules with arguments or params in Bluesim or SystemC let (top_args, top_params) = getArgsAndParams topModInfo - if (genSysC flags) + when (not (blockCodegen flags)) $ + if (genSysC flags) then when ((not (null top_args)) || (not (null top_params))) $ bsError errh [(noPosition, EBSimTopLevelArgOrParam True (top_args ++ top_params))] else when ((not (null top_args)) || (not (null top_params))) $ diff --git a/src/comp/SimFileUtils.hs b/src/comp/SimFileUtils.hs index 67084d86d..ea87989e5 100644 --- a/src/comp/SimFileUtils.hs +++ b/src/comp/SimFileUtils.hs @@ -31,10 +31,16 @@ getModTime f = return $ Just (modificationTime s) else return Nothing +-- Settings that make an object unreusable under a different setting (isStale +-- checks these before reuse). blockCodegen (-c mode) is omitted: its output +-- equals the submodule form (see DEVELOP.md). "top" marks top form (the +-- form the -e link's schedule and model_ expect), so a block-form artifact +-- can never be taken as a link's top, nor vice versa. codeGenOptionDescr :: Flags -> Bool -> String codeGenOptionDescr flags is_top = unwords $ [ "Generation options:" ] ++ (if (keepFires flags) then ["keep-fires"] else []) ++ + (if is_top then ["top"] else []) ++ (if (is_top && (genSysC flags)) then ["sysc-top"] else []) readCodeGenOptionDescr :: FilePath -> IO (Maybe String) diff --git a/src/comp/SimMakeCBlocks.hs b/src/comp/SimMakeCBlocks.hs index 8b2ab84fa..495103357 100644 --- a/src/comp/SimMakeCBlocks.hs +++ b/src/comp/SimMakeCBlocks.hs @@ -746,9 +746,22 @@ mkScheduleStmts flags top_ifc top_vmeth_set top_ameth_set top_gates internalError ("mkScheduleStmts: as = " ++ ppReadable as) gate_substs = mkGateSubstMap top_gates $ concatMap (di_clock_substs . snd) domain_infos - mkStmt = mkSchedStmts top_ifc top_vmeth_set top_ameth_set - inst_map full_def_map non_prim_calls - gate_substs sched_conflicts sched_ME_inhibits + mkStmt0 = mkSchedStmts top_ifc top_vmeth_set top_ameth_set + inst_map full_def_map non_prim_calls + gate_substs sched_conflicts sched_ME_inhibits + -- In -c mode the root is a reusable block, not a runnable top, + -- so its interface methods are not fired by its own schedule. Keep the + -- method nodes in the schedule graph (so edges from rules stay valid) but + -- emit no statements for them; their enable/argument ports then go + -- unreferenced and are optimized away, matching submodule form. (See + -- DEVELOP.md.) + isTopMethodNode (Sched rid) = + (rid `S.member` top_vmeth_set) || (rid `S.member` top_ameth_set) + isTopMethodNode (Exec rid) = + (rid `S.member` top_vmeth_set) || (rid `S.member` top_ameth_set) + mkStmt n = if (blockCodegen flags) && (isTopMethodNode n) + then [] + else mkStmt0 n (pos_rule_stmts, neg_rule_stmts) = if (ss_posedge sim_sched) then (stableOrdNub (concatMap mkStmt edge_sched_order), []) diff --git a/src/comp/bsc.hs b/src/comp/bsc.hs index 78344e22a..3104d29e1 100644 --- a/src/comp/bsc.hs +++ b/src/comp/bsc.hs @@ -226,6 +226,10 @@ hmain args = do do { setFlags flags; doWarnings; showPreamble flags; simLink errh flags top abinFiles cSrcFiles; exitOK errh } + DCodeGen flags mods abinFiles -> + do { setFlags flags; doWarnings; showPreamble flags; + codeGen errh flags mods abinFiles; + exitOK errh } main' :: ErrorHandle -> Flags -> String -> IO () @@ -948,23 +952,21 @@ genModule -- IO properties which can be included as attributes in the -- Cmoduleverilog (import-BVI) -- XXX it would be nice if the Bluesim backend had the same info - -- * vprog = the Verilog data structure, for recording in the .ba file, - -- so that it's available to bluetcl - (t, veriPortProps, vprog) + (t, veriPortProps) <- if (backend flags == Just Verilog) - then do (t', ips, v) + then do (t', ips, _v) <- genModuleVerilog errh pps flags dumpnames t prefix modstr blurb methodConflictBlurb methodConflictBVI vPathInfo sched_info'' amod_final - return (t', ips, Just v) - else return (t, [], Nothing) + return (t', ips) + else return (t, []) t <- if (genABin flags) then writeABin errh pps flags dumpnames t prefix modstr srcName (orig_cqt wi) sched_info'' methodConflict vPathInfo - amod_final vprog + amod_final else return t -- Wrapper generation @@ -992,9 +994,9 @@ genModule writeABin :: ErrorHandle -> [PProp] -> Flags -> DumpNames -> TimeInfo -> String -> String -> String -> CQType -> AScheduleInfo -> MethodDumpInfo -> VPathInfo -> - APackage -> Maybe VProgram -> IO (TimeInfo) + APackage -> IO (TimeInfo) writeABin errh pps flags dumpnames t prefix modstr srcName oqt - sched_info methodConflict vPathInfo amod vprog = + sched_info methodConflict vPathInfo amod = do start flags DFwriteABin @@ -1024,9 +1026,7 @@ writeABin errh pps flags dumpnames t prefix modstr srcName oqt abmi_oqt = oqt, abmi_method_dump = methodConflict, abmi_pathinfo = vPathInfo, - abmi_flags = flags, - abmi_vprogram = if (genABinVerilog flags) - then vprog else Nothing + abmi_flags = flags } abin = ABinMod modinfo (bscVersionStr True) genABinFile errh afilename abin @@ -1078,8 +1078,8 @@ genModuleVerilog :: ErrorHandle -> AScheduleInfo -> APackage -> IO (TimeInfo, - [VPort], -- port properties for the import-BVI - VProgram) -- generated Verilog + [VPort], -- port properties for the import-BVI + [VFileName]) -- the Verilog files written genModuleVerilog errh pprops flags dumpnames time0 prefix moduleName blurb methodConflictBlurb methodConflictBVI vPathInfo scheduleInfo atsPackage = @@ -1205,7 +1205,7 @@ genModuleVerilog errh pprops flags dumpnames time0 prefix moduleName -- Return -- * the port properties (to be included in the import-BVI) -- * the Verilog structure (for accessing in bluetcl) - return (t, ips, vprog) + return (t, ips, vfilenames) -- Write a Verilog program to file (along with its use file) @@ -1295,8 +1295,11 @@ genModuleC errh flags dumpnames time0 toplevel abis = -- extract file dependency structure and determine if any -- existing bluesim packages can reuse existing object files + -- (in -c mode, all files are always regenerated) start flags DFsimDepend - reused <- analyzeBluesimDependencies flags sim_system prefix + reused <- if (blockCodegen flags) + then return [] + else analyzeBluesimDependencies flags sim_system prefix time <- dump errh flags time DFsimDepend dumpnames reused -- optimize the SimPackages and SimSchedules @@ -1393,6 +1396,98 @@ genModuleC errh flags dumpnames time0 toplevel abis = -- XXX compiled return (time, names, reused_names, creation_time) +-- =============== +-- CodeGen + +-- The -c mode: generate code for a module from its elaborated (.ba) +-- file, the middle stage of the three-stage flow (elaborate -> codegen -> +-- link). For Bluesim this reuses the front half of simLink, which under +-- blockCodegen generates each module's C++ as a reusable block (no +-- schedule or top-level wrapper) and skips compiling and linking. For +-- Verilog each named module's .v is generated from its own .ba alone. +codeGen :: ErrorHandle -> Flags -> [String] -> [String] -> IO () +codeGen errh flags mods abinFiles = + case (backend flags) of + Just Verilog -> vCodeGen errh flags mods abinFiles + _ -> let flags' = flags { blockCodegen = True } + in mapM_ (\m -> simLink errh flags' m abinFiles []) mods + +-- Generate each named module's Verilog from its elaborated (.ba) file: +-- from a .ba given on the command line when one defines the module, and +-- otherwise found by module name on the search path. Root-only, which +-- is Verilog's native granularity: a module's .v needs only its own +-- ABinModInfo (children are referenced by name). +vCodeGen :: ErrorHandle -> Flags -> [String] -> [String] -> IO () +vCodeGen errh flags mods afilenames = do + tStart <- getNow + user_abis <- mapM (readAndCheckABin errh (Just Verilog)) (nub afilenames) + let abinModName (ABinMod mi _) = + getIdString (unQualId (apkg_name (abmi_apkg mi))) + abinModName _ = "" + findMod name = + case [ (fn, abin) | (fn, abin) <- user_abis + , abinModName abin == name ] of + ((fn, abin):_) -> return (fn, abin) + [] -> let err = (cmdPosition, + EMissingABinModFile name Nothing) + in readAndCheckABinPathCatch errh + (verbose flags) (ifcPath flags) (Just Verilog) + name err + assertMod (fn, ABinMod mi _) = return (fn, mi) + assertMod (_, ABinModSchedErr {}) = + bsError errh [(cmdPosition, EABinModSchedErr (unwords mods) Nothing)] + assertMod (fn, ABinForeignFunc {}) = + bsError errh [(cmdPosition, + EWrongABinTypeExpectedModule fn Nothing)] + named_abis <- mapM findMod mods + abmis <- mapM assertMod named_abis + _ <- vGenMods errh flags tStart abmis + return () + +-- Generate Verilog for modules from their elaborated (.ba) files, +-- reconstructing the inputs of genModuleVerilog from each ABinModInfo. +-- Codegen flags come from this invocation's command line, matching the +-- Bluesim path; elaboration-affecting flags are baked into the .ba. +vGenMods :: ErrorHandle -> Flags -> TimeInfo -> [(String, ABinModInfo)] -> + IO (TimeInfo, [VFileName]) +vGenMods errh flags t0 abmis = do + pwd <- getCurrentDirectory + -- output goes to the current directory unless -vdir overrides it + -- (a .ba's own directory is typically -bdir, which is not where + -- generated Verilog belongs) + let prefix = dirName (createEncodedFullFilePath "placeholder" pwd) ++ "/" + genV (t, vfns_so_far) (_, abmi) = do + let modId = apkg_name (abmi_apkg abmi) + modstr = getIdString (unQualId modId) + dumpnames = (Nothing, Nothing, Just modstr) + when (verbose flags) $ putStrLnF ("*****") + when (showCodeGen flags || verbose flags) $ + putStrLnF ("Verilog generation for " ++ modstr ++ " starts") + blurb <- mkGenFileHeader flags + let apkg = abmi_apkg abmi + pps = abmi_pps abmi + methodConflict = abmi_method_dump abmi + methodConflictBlurb + | methodConf flags = + ["Method conflict info:"] + ++ lines (pretty 78 78 + (vcat (dumpMethodInfo flags methodConflict))) + | otherwise = [] + methodConflictBVI + | methodBVI flags = + ["BVI format method schedule info:"] + ++ lines (pretty 78 78 + (vcat (dumpMethodBVIInfo methodConflict))) + | otherwise = [] + pathinfo = abmi_pathinfo abmi + aschedinfo = abmi_aschedinfo abmi + (t', _, vfns) <- + genModuleVerilog errh pps flags dumpnames t prefix modstr + blurb methodConflictBlurb methodConflictBVI + pathinfo aschedinfo apkg + return (t', vfns_so_far ++ vfns) + foldM genV (t0, []) abmis + -- =============== -- SimLink @@ -1446,7 +1541,10 @@ simLink errh flags toplevel afilenames cfilenames = do start flags DFbluesimcompile let jobs = parallelSimLink flags (gen_ofiles, compiled_user_ofiles) <- - if (jobs > 1) + if (blockCodegen flags) + then -- the user's build system compiles the generated files + return ([], []) + else if (jobs > 1) then do compileParallelCFiles errh flags False toplevel gen_cfiles user_cfiles @@ -1464,9 +1562,10 @@ simLink errh flags toplevel afilenames cfilenames = do t <- dump errh flags t_before_compilations DFbluesimcompile dumpnames ofiles - -- if not generating a SystemC model, link to a Bluesim executable + -- if generating a SystemC model or only generating code, + -- there is nothing to link; otherwise link a Bluesim executable start flags DFbluesimlink - when (not (genSysC flags)) $ + when (not (genSysC flags) && not (blockCodegen flags)) $ cxxLink errh flags toplevel ofiles creation_time t <- dump errh flags t DFbluesimlink dumpnames toplevel diff --git a/testsuite/bsc.arrays/dynamic/ImpCond.bsv.bsc-sched-out.expected b/testsuite/bsc.arrays/dynamic/ImpCond.bsv.bsc-sched-out.expected index d9681b13b..057fc5f9d 100644 --- a/testsuite/bsc.arrays/dynamic/ImpCond.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.arrays/dynamic/ImpCond.bsv.bsc-sched-out.expected @@ -43,4 +43,5 @@ Logical execution order: r ========================================== Verilog file created: sysImpCond.v +Elaborated module file created: sysImpCond.ba All packages are up to date. diff --git a/testsuite/bsc.bluesim/block_codegen/BlockCodegen.bsv b/testsuite/bsc.bluesim/block_codegen/BlockCodegen.bsv new file mode 100644 index 000000000..7a0fdeb1b --- /dev/null +++ b/testsuite/bsc.bluesim/block_codegen/BlockCodegen.bsv @@ -0,0 +1,7 @@ +// Minimal one-module design for testing the -c codegen mode +module mkBlockCodegen(); + rule done; + $display("done"); + $finish(0); + endrule +endmodule diff --git a/testsuite/bsc.bluesim/block_codegen/Enabled.bsv b/testsuite/bsc.bluesim/block_codegen/Enabled.bsv new file mode 100644 index 000000000..b8fe59632 --- /dev/null +++ b/testsuite/bsc.bluesim/block_codegen/Enabled.bsv @@ -0,0 +1,32 @@ +// A module whose interface has an always_enabled method. Such a module +// cannot be the top of a normal Bluesim simulation (it is rejected with +// G0062), but the -c codegen mode must accept it as a codegen root, since the +// generated model is never executed. mkUsesEnabled instantiates it so the +// testsuite can check that the -c output matches the submodule +// form for this (motivating) case too. +package Enabled; + +interface AlwaysEnabled; + (* always_enabled *) method Action poke(Bit#(8) x); + method Bit#(8) get(); +endinterface + +(* synthesize *) +module mkAlwaysEnabled(AlwaysEnabled); + Reg#(Bit#(8)) r <- mkReg(0); + method Action poke(Bit#(8) x); r <= x; endmethod + method Bit#(8) get(); return r; endmethod +endmodule + +(* synthesize *) +module mkUsesEnabled(); + AlwaysEnabled ae <- mkAlwaysEnabled; + Reg#(Bit#(8)) n <- mkReg(0); + rule drive; + ae.poke(n); + n <= n + 1; + if (n == 5) begin $display("ae=%0d", ae.get()); $finish(0); end + endrule +endmodule + +endpackage diff --git a/testsuite/bsc.bluesim/block_codegen/Hier.bsv b/testsuite/bsc.bluesim/block_codegen/Hier.bsv new file mode 100644 index 000000000..9e8a3c53b --- /dev/null +++ b/testsuite/bsc.bluesim/block_codegen/Hier.bsv @@ -0,0 +1,41 @@ +// Two different hierarchies that both instantiate mkSub from SharedSub, +// at different depths: +// mkTop -> mkSub (one level) +// mkTop2 -> mkMid -> mkSub (two levels) +// The per-module C++ generated for mkSub must be identical in both, since +// the whole point of per-module codegen (-c) is that a module's C++ does not depend +// on the surrounding hierarchy. +package Hier; + +import SharedSub::*; + +(* synthesize *) +module mkMid(Counter); + Counter c <- mkSub; + method Action inc(); c.inc(); endmethod + method Bit#(8) value(); return c.value(); endmethod +endmodule + +(* synthesize *) +module mkTop(); + Counter c <- mkSub; + Reg#(Bit#(8)) n <- mkReg(0); + rule go; + c.inc(); + n <= n + 1; + if (n == 5) begin $display("v=%0d", c.value()); $finish(0); end + endrule +endmodule + +(* synthesize *) +module mkTop2(); + Counter c <- mkMid; + Reg#(Bit#(8)) n <- mkReg(0); + rule go; + c.inc(); + n <= n + 1; + if (n == 5) begin $display("v=%0d", c.value()); $finish(0); end + endrule +endmodule + +endpackage diff --git a/testsuite/bsc.bluesim/block_codegen/Makefile b/testsuite/bsc.bluesim/block_codegen/Makefile new file mode 100644 index 000000000..010f89dc8 --- /dev/null +++ b/testsuite/bsc.bluesim/block_codegen/Makefile @@ -0,0 +1,7 @@ +# for "make clean" to work everywhere + +CONFDIR = $(realpath ../..) + +DONTKEEPFILES = simfiles enabled enabled_fail enabled_use sub_cg hierA hierB + +include $(CONFDIR)/clean.mk diff --git a/testsuite/bsc.bluesim/block_codegen/SharedSub.bsv b/testsuite/bsc.bluesim/block_codegen/SharedSub.bsv new file mode 100644 index 000000000..08c2deb5b --- /dev/null +++ b/testsuite/bsc.bluesim/block_codegen/SharedSub.bsv @@ -0,0 +1,21 @@ +// A leaf module that is reused, unchanged, in several different +// hierarchies. It is a valid Bluesim top in its own right (no +// always_enabled methods, no top-level arguments), so the *same* +// module can be code-generated both with the -c codegen mode and via a +// normal -sim build, which the testsuite uses to check that the two +// paths emit byte-identical per-module C++. +package SharedSub; + +interface Counter; + method Action inc(); + method Bit#(8) value(); +endinterface + +(* synthesize *) +module mkSub(Counter); + Reg#(Bit#(8)) r <- mkReg(0); + method Action inc(); r <= r + 1; endmethod + method Bit#(8) value(); return r; endmethod +endmodule + +endpackage diff --git a/testsuite/bsc.bluesim/block_codegen/block_codegen.exp b/testsuite/bsc.bluesim/block_codegen/block_codegen.exp new file mode 100644 index 000000000..2242f5974 --- /dev/null +++ b/testsuite/bsc.bluesim/block_codegen/block_codegen.exp @@ -0,0 +1,183 @@ +# +# Tests for the -c codegen mode +# +# "bsc -sim -c M" writes M's Bluesim C++ to the simdir and stops: it does +# not compile or link, it does not require the codegen root to be a runnable +# Bluesim top, and it generates the module exactly as it would appear as a +# *submodule* -- with no top-level "model_" wrapper and no top-level +# interface ports. That makes a module's per-module C++ independent of +# where it is used, so an external build system can generate and compile it +# once and share the object across simulations; the stock Bluesim dependency +# analysis then reuses it. -c is root-only (the cc -c contract: one module +# in, that module's outputs out); a build system fans out one -c invocation +# per module. The tests below check: +# * the mode generates only the named module's files (no submodule files, +# no compile, no link, and no "model_" wrapper), and accepts modules a +# normal Bluesim link would reject (always_enabled); and +# * the generated per-module C++ is byte-identical to the same module built +# as a submodule, and is the same across different hierarchies. +# + +# Check that none of the listed files exist +proc files_dont_exist { filenames } { + global subdir + + incr_stat "files_dont_exist" + + set foundfile "" + foreach filename $filenames { + set fullname [join [concat $subdir $filename] "/" ] + if {[file exists $fullname]} { + set foundfile $filename + break + } + } + + if {$foundfile == ""} { + pass "found none of the files: $filenames" + } else { + fail "file `$foundfile' should not exist" + } +} + +# ------------------------- +# "bsc -sim -c M" writes M's per-module C++ files to the simdir and exits +# successfully without compiling or linking them, and without generating a +# top-level "model_" wrapper (the block is never a runnable top). + +if { $ctest == 1 } { + +compile_object_pass BlockCodegen.bsv mkBlockCodegen + +mkdir simfiles +gen_modules_pass {mkBlockCodegen} {-simdir simfiles} + +# The per-module Bluesim C++ files are generated ... +files_exist { simfiles/mkBlockCodegen.cxx \ + simfiles/mkBlockCodegen.h } + +# ... but nothing is compiled or linked, and no "model_" wrapper is produced +files_dont_exist { simfiles/model_mkBlockCodegen.cxx \ + simfiles/model_mkBlockCodegen.h \ + simfiles/mkBlockCodegen.o \ + simfiles/model_mkBlockCodegen.o \ + mkBlockCodegen.cexe \ + mkBlockCodegen.cexe.so } + +} + +# ------------------------- +# A module whose interface is always_enabled cannot be the top of a normal +# Bluesim simulation, but -c accepts it as a codegen root, and generates it +# exactly as it appears when instantiated as a submodule. + +if { $ctest == 1 } { + +compile_object_pass Enabled.bsv mkAlwaysEnabled +compile_object_pass Enabled.bsv mkUsesEnabled + +# A normal Bluesim link rejects an always_enabled top ... +mkdir enabled_fail +link_objects_fail_error {} mkAlwaysEnabled G0062 1 {-simdir enabled_fail} + +# ... but -c generates its per-module C++ (and no model_) ... +mkdir enabled +gen_modules_pass {mkAlwaysEnabled} {-simdir enabled} +files_exist { enabled/mkAlwaysEnabled.cxx enabled/mkAlwaysEnabled.h } +files_dont_exist { enabled/model_mkAlwaysEnabled.cxx } + +# ... which is byte-identical to the module built as a submodule. +mkdir enabled_use +link_objects_pass {} mkUsesEnabled {-simdir enabled_use} +compare_file enabled/mkAlwaysEnabled.cxx enabled_use/mkAlwaysEnabled.cxx +compare_file enabled/mkAlwaysEnabled.h enabled_use/mkAlwaysEnabled.h + +} + +# ------------------------- +# The C++ generated by -c is byte-identical to the same module built as a +# submodule, and the submodule form does not depend on the surrounding +# hierarchy. (The testsuite always passes -no-show-timestamps +# -no-show-version, so the generated headers are deterministic.) + +if { $ctest == 1 } { + +compile_object_pass SharedSub.bsv mkSub +compile_object_pass Hier.bsv mkMid +compile_object_pass Hier.bsv mkTop +compile_object_pass Hier.bsv mkTop2 + +# generate the module on its own with -c +mkdir sub_cg +gen_modules_pass {mkSub} {-simdir sub_cg} + +# mkSub one level down in mkTop, and two levels down in mkTop2 +mkdir hierA +link_objects_pass {} mkTop {-simdir hierA} +mkdir hierB +link_objects_pass {} mkTop2 {-simdir hierB} + +# -c output is byte-identical to the submodule form ... +compare_file sub_cg/mkSub.cxx hierA/mkSub.cxx +compare_file sub_cg/mkSub.h hierA/mkSub.h + +# ... and the submodule form does not depend on the hierarchy +compare_file hierA/mkSub.cxx hierB/mkSub.cxx +compare_file hierA/mkSub.h hierB/mkSub.h + +} + +# ------------------------- +# -c is root-only: generating mkTop writes mkTop's files and nothing else +# (submodules get their files from their own -c invocations). + +if { $ctest == 1 } { + +mkdir top_only +gen_modules_pass {mkTop} {-simdir top_only} +files_exist { top_only/mkTop.cxx top_only/mkTop.h } +files_dont_exist { top_only/mkMid.cxx top_only/mkSub.cxx \ + top_only/model_mkTop.cxx } + +} + +# ------------------------- +# -c output is block form; a link's top is generated in top form. The +# generation-options descriptor in the .h records the form, so a fresh +# block-form artifact is never reused as the top of a link (and a +# top-form artifact from an earlier link of the same design still is). + +if { $ctest == 1 } { + +# generate block form into the current directory (where -e would look) +gen_modules_pass {mkBlockCodegen} +# fabricate an up-to-date object, so only the descriptor can reject reuse +exec touch [file join [absolute $srcdir] $subdir mkBlockCodegen.o] +# the link must regenerate its top rather than reuse the block form ... +link_objects_pass {} mkBlockCodegen +find_regexp_fail [make_bsc_ccomp_output_name mkBlockCodegen] \ + {Bluesim object reused} +# ... but relinking reuses the top-form artifact it just made +link_objects_pass {} mkBlockCodegen +find_regexp [make_bsc_ccomp_output_name mkBlockCodegen] \ + {Bluesim object reused: mkBlockCodegen} + +} + +# ------------------------- +# Command-line checks: -c is its own mode + +# -c cannot be combined with -e (linking is a separate step) +compile_no_source_fail_error "c_with_entry" \ + {-sim -c mkBlockCodegen -e mkBlockCodegen} S0096 + +# -c generates from .ba files, not from source +compile_fail_error BlockCodegen.bsv S0097 1 {-sim -c mkBlockCodegen} + +# -c is not supported with -systemc +compile_no_source_fail_error "systemc_c_mode" \ + {-systemc -c mkBlockCodegen} S0098 + +# -c requires a backend +compile_no_source_fail_error "no_backend_c_mode" \ + {-c mkBlockCodegen} S0014 diff --git a/testsuite/bsc.bluesim/block_codegen_sweep/Makefile b/testsuite/bsc.bluesim/block_codegen_sweep/Makefile new file mode 100644 index 000000000..b953e8132 --- /dev/null +++ b/testsuite/bsc.bluesim/block_codegen_sweep/Makefile @@ -0,0 +1,5 @@ +# for "make clean" to work everywhere + +CONFDIR = $(realpath ../..) + +include $(CONFDIR)/clean.mk diff --git a/testsuite/bsc.bluesim/block_codegen_sweep/SchedFix.bsv b/testsuite/bsc.bluesim/block_codegen_sweep/SchedFix.bsv new file mode 100644 index 000000000..3247e7cc0 --- /dev/null +++ b/testsuite/bsc.bluesim/block_codegen_sweep/SchedFix.bsv @@ -0,0 +1,180 @@ +// Pressure -c codegen-mode byte-identity across the "access count" dimensions, +// stepping each 0 -> 1 -> 2 -> n. Every module here is a submodule of the +// testbench in SchedFixTb.bsv; the testsuite's codegen-mode check then +// confirms each module's per-module C++ is byte-identical whether built on its +// own (-c) or as part of the design. +package SchedFix; + +// --------------------------------------------------------------------------- +// D1: number of internal rules that read a shared value (0,1,2,3 readers) +interface Acc; + method Action set(Bit#(8) x); + method Bit#(8) get(); +endinterface + +(* synthesize *) module mkD1_0 (Acc); // 0 reader rules + Reg#(Bit#(8)) r <- mkReg(0); + method Action set(Bit#(8) x); r <= x; endmethod + method Bit#(8) get(); return r; endmethod +endmodule + +(* synthesize *) module mkD1_1 (Acc); // 1 reader rule + Reg#(Bit#(8)) r <- mkReg(0); Reg#(Bit#(8)) a <- mkReg(0); + rule u1; a <= a + r; endrule + method Action set(Bit#(8) x); r <= x; endmethod + method Bit#(8) get(); return a; endmethod +endmodule + +(* synthesize *) module mkD1_2 (Acc); // 2 reader rules + Reg#(Bit#(8)) r <- mkReg(0); Reg#(Bit#(8)) a <- mkReg(0); Reg#(Bit#(8)) b <- mkReg(0); + rule u1; a <= a + r; endrule + rule u2; b <= b + (r << 1); endrule + method Action set(Bit#(8) x); r <= x; endmethod + method Bit#(8) get(); return a + b; endmethod +endmodule + +(* synthesize *) module mkD1_3 (Acc); // 3 reader rules + Reg#(Bit#(8)) r <- mkReg(0); + Reg#(Bit#(8)) a <- mkReg(0); Reg#(Bit#(8)) b <- mkReg(0); Reg#(Bit#(8)) c <- mkReg(0); + rule u1; a <= a + r; endrule + rule u2; b <= b + (r << 1); endrule + rule u3; c <= c + (r << 2); endrule + method Action set(Bit#(8) x); r <= x; endmethod + method Bit#(8) get(); return a + b + c; endmethod +endmodule + +// --------------------------------------------------------------------------- +// D2: number of method arguments (0,1,2,3) +interface Arg; + method Action go0(); + method Action go1(Bit#(8) a); + method Action go2(Bit#(8) a, Bit#(8) b); + method Action go3(Bit#(8) a, Bit#(8) b, Bit#(8) c); + method Bit#(8) v(); +endinterface + +(* synthesize *) module mkD2_args (Arg); + Reg#(Bit#(8)) r <- mkReg(0); + method Action go0(); r <= r + 1; endmethod + method Action go1(Bit#(8) a); r <= a; endmethod + method Action go2(Bit#(8) a, Bit#(8) b); r <= a + b; endmethod + method Action go3(Bit#(8) a, Bit#(8) b, Bit#(8) c); r <= a + b + c; endmethod + method Bit#(8) v(); return r; endmethod +endmodule + +// --------------------------------------------------------------------------- +// D3: number of methods in the interface (1,2,3 value methods) +interface M1; method Bit#(8) a(); endinterface +interface M2; method Bit#(8) a(); method Bit#(8) b(); endinterface +interface M3; method Bit#(8) a(); method Bit#(8) b(); method Bit#(8) c(); endinterface + +(* synthesize *) module mkD3_1 (M1); + Reg#(Bit#(8)) r <- mkReg(1); + method Bit#(8) a(); return r; endmethod +endmodule +(* synthesize *) module mkD3_2 (M2); + Reg#(Bit#(8)) r <- mkReg(1); + method Bit#(8) a(); return r; endmethod + method Bit#(8) b(); return r + 1; endmethod +endmodule +(* synthesize *) module mkD3_3 (M3); + Reg#(Bit#(8)) r <- mkReg(1); + method Bit#(8) a(); return r; endmethod + method Bit#(8) b(); return r + 1; endmethod + method Bit#(8) c(); return r + 2; endmethod +endmodule + +// --------------------------------------------------------------------------- +// D4: method kind (value, action, actionvalue) +interface KV; method Bit#(8) v(); endinterface +interface KA; method Action a(Bit#(8) x); endinterface +interface KAV; method ActionValue#(Bit#(8)) av(Bit#(8) x); endinterface + +(* synthesize *) module mkD4_val (KV); + Reg#(Bit#(8)) r <- mkReg(7); + method Bit#(8) v(); return r; endmethod +endmodule +(* synthesize *) module mkD4_act (KA); + Reg#(Bit#(8)) r <- mkReg(0); + method Action a(Bit#(8) x); r <= r + x; endmethod +endmodule +(* synthesize *) module mkD4_av (KAV); + Reg#(Bit#(8)) r <- mkReg(0); + method ActionValue#(Bit#(8)) av(Bit#(8) x); r <= r + x; return r; endmethod +endmodule + +// --------------------------------------------------------------------------- +// D5: number of (non-primitive) submodule instances (0,1,2,3) +interface Cnt; method Bit#(8) tot(); endinterface + +(* synthesize *) module mkLeaf (Acc); + Reg#(Bit#(8)) r <- mkReg(0); + method Action set(Bit#(8) x); r <= x; endmethod + method Bit#(8) get(); return r; endmethod +endmodule + +(* synthesize *) module mkD5_0 (Cnt); + Reg#(Bit#(8)) r <- mkReg(3); + method Bit#(8) tot(); return r; endmethod +endmodule +(* synthesize *) module mkD5_1 (Cnt); + Acc s0 <- mkLeaf; + rule t; s0.set(1); endrule + method Bit#(8) tot(); return s0.get(); endmethod +endmodule +(* synthesize *) module mkD5_2 (Cnt); + Acc s0 <- mkLeaf; Acc s1 <- mkLeaf; + rule t; s0.set(1); s1.set(2); endrule + method Bit#(8) tot(); return s0.get() + s1.get(); endmethod +endmodule +(* synthesize *) module mkD5_3 (Cnt); + Acc s0 <- mkLeaf; Acc s1 <- mkLeaf; Acc s2 <- mkLeaf; + rule t; s0.set(1); s1.set(2); s2.set(3); endrule + method Bit#(8) tot(); return s0.get() + s1.get() + s2.get(); endmethod +endmodule + +// --------------------------------------------------------------------------- +// D7: subinterface forwarding to a submodule (the cache shape) +interface Fwd; + interface Acc inner; +endinterface + +(* synthesize *) module mkD7_fwd (Fwd); + Acc s <- mkLeaf; + Reg#(Bit#(8)) n <- mkReg(0); + rule tick; n <= n + 1; endrule + interface Acc inner = s; +endmodule + +// --------------------------------------------------------------------------- +// D8: several distinct submodule instances, named so insertion order differs +// from name order (stresses state-instance / symbol-table ordering). +(* synthesize *) module mkD8_insts (Cnt); + Acc zz <- mkLeaf; Acc aa <- mkLeaf; Acc mm <- mkLeaf; + rule t; zz.set(1); aa.set(2); mm.set(3); endrule + method Bit#(8) tot(); return zz.get() + aa.get() + mm.get(); endmethod +endmodule + +// --------------------------------------------------------------------------- +// D9: kitchen sink -- many registers (declared out of name order), several +// rules (named out of order), and several methods of mixed kinds, to stress +// the member-def, state, rule and method orderings together. +interface Sink; + method Action poke(Bit#(8) x); + method Bit#(8) red(); + method ActionValue#(Bit#(8)) step(); +endinterface +(* synthesize *) module mkD9_sink (Sink); + Reg#(Bit#(8)) z <- mkReg(0); Reg#(Bit#(8)) a <- mkReg(0); + Reg#(Bit#(8)) m <- mkReg(0); Reg#(Bit#(8)) b <- mkReg(0); + Reg#(Bit#(8)) y <- mkReg(0); Reg#(Bit#(8)) c <- mkReg(0); + rule rz; z <= z + a; endrule + rule ra; a <= a + b; endrule + rule rm; m <= m + z + y; endrule + rule rb; b <= b + c; endrule + method Action poke(Bit#(8) x); c <= c + x; endmethod + method Bit#(8) red(); return z + a + m + b + y + c; endmethod + method ActionValue#(Bit#(8)) step(); y <= y + 1; return m; endmethod +endmodule + +endpackage diff --git a/testsuite/bsc.bluesim/block_codegen_sweep/SchedFixMeths.bs b/testsuite/bsc.bluesim/block_codegen_sweep/SchedFixMeths.bs new file mode 100644 index 000000000..53606f36b --- /dev/null +++ b/testsuite/bsc.bluesim/block_codegen_sweep/SchedFixMeths.bs @@ -0,0 +1,71 @@ +-- D6: many *wide* method return ports, named deliberately out of sorted order. +-- +-- This pressures the ordering of a module's method (enable / argument / +-- return) ports in the generated Bluesim C++. Those port lists come from a +-- map keyed by Id, whose order depends on interned-Id order and so can differ +-- between building the module on its own (-c) and as part of the +-- whole design. The ports must therefore be emitted in a context-independent +-- (name) order for the per-module C++ to be byte-identical either way. +-- +-- The return values are *wide* (more than 64 bits) on purpose: narrow defs are +-- moved onto the function stack (and ordered separately), whereas wide values +-- stay as class members whose declaration/initialization order is exactly the +-- port order under test. +-- +-- Written in Classic (.bs) syntax so the sweep also exercises that frontend. +package SchedFixMeths(Many(..), mkSchedFixMeths) where + +interface Many = + load :: Bit 96 -> Action + wz :: Bit 96 + wa :: Bit 96 + wm :: Bit 96 + wb :: Bit 96 + wy :: Bit 96 + wc :: Bit 96 + wx :: Bit 96 + wd :: Bit 96 + ww :: Bit 96 + we :: Bit 96 + wv :: Bit 96 + wf :: Bit 96 + wu :: Bit 96 + wg :: Bit 96 + wt :: Bit 96 + wh :: Bit 96 + ws :: Bit 96 + wi :: Bit 96 + wr :: Bit 96 + wj :: Bit 96 + wq :: Bit 96 + wk :: Bit 96 + +{-# verilog mkSchedFixMeths #-} +mkSchedFixMeths :: Module Many +mkSchedFixMeths = + module + r :: Reg (Bit 96) <- mkReg 0 + interface + load x = r := x + wz = r + 26 + wa = r + 1 + wm = r + 13 + wb = r + 2 + wy = r + 25 + wc = r + 3 + wx = r + 24 + wd = r + 4 + ww = r + 23 + we = r + 5 + wv = r + 22 + wf = r + 6 + wu = r + 21 + wg = r + 7 + wt = r + 20 + wh = r + 8 + ws = r + 19 + wi = r + 9 + wr = r + 18 + wj = r + 10 + wq = r + 17 + wk = r + 11 diff --git a/testsuite/bsc.bluesim/block_codegen_sweep/SchedFixTb.bsv b/testsuite/bsc.bluesim/block_codegen_sweep/SchedFixTb.bsv new file mode 100644 index 000000000..61767aad7 --- /dev/null +++ b/testsuite/bsc.bluesim/block_codegen_sweep/SchedFixTb.bsv @@ -0,0 +1,73 @@ +// Instantiates every SchedFix child so each gets a nested per-module C++, which +// the codegen-mode check compares against the standalone (-c) +// form. Driving is split across mutually-exclusive rules so no two conflicting +// methods of the same instance are called in one rule. +package SchedFixTb; + +import SchedFix::*; +import SchedFixMeths::*; + +(* synthesize *) +module sysSchedFixTb(); + Reg#(Bit#(8)) n <- mkReg(0); + + // D1 + Acc d1_0 <- mkD1_0; Acc d1_1 <- mkD1_1; Acc d1_2 <- mkD1_2; Acc d1_3 <- mkD1_3; + // D2 + Arg d2 <- mkD2_args; + // D3 + M1 d3_1 <- mkD3_1; M2 d3_2 <- mkD3_2; M3 d3_3 <- mkD3_3; + // D4 + KV d4v <- mkD4_val; KA d4a <- mkD4_act; KAV d4av <- mkD4_av; + // D5 + Cnt d5_0 <- mkD5_0; Cnt d5_1 <- mkD5_1; Cnt d5_2 <- mkD5_2; Cnt d5_3 <- mkD5_3; + // D7 + Fwd d7 <- mkD7_fwd; + // D6 + Many d6 <- mkSchedFixMeths; + // D8, D9 + Cnt d8 <- mkD8_insts; + Sink d9 <- mkD9_sink; + + Reg#(Bit#(8)) acc <- mkReg(0); + + rule drive (n < 8); + d1_0.set(n); d1_1.set(n); d1_2.set(n); d1_3.set(n); + // d2's four methods all write the same reg, so call only one per cycle + case (n[1:0]) + 0: d2.go0(); + 1: d2.go1(n); + 2: d2.go2(n, n); + default: d2.go3(n, n, n); + endcase + d4a.a(n); + let av <- d4av.av(n); + d7.inner.set(n); + d6.load(zeroExtend(n)); + d9.poke(n); + acc <= acc + av; + n <= n + 1; + endrule + + rule done (n == 8); + Bit#(8) s = d1_0.get() + d1_1.get() + d1_2.get() + d1_3.get() + + d2.v() + + d3_1.a() + d3_2.a() + d3_2.b() + d3_3.a() + d3_3.b() + d3_3.c() + + d4v.v() + + d5_0.tot() + d5_1.tot() + d5_2.tot() + d5_3.tot() + + d7.inner.get() + d8.tot() + d9.red() + acc + + // d6's many wide methods, truncated and summed. Calling them + // exercises every (wide) method return port, whose declaration + // and initialization order is the thing the port-order + // canonicalization keeps context-independent. + truncate(d6.wa() + d6.wb() + d6.wc() + d6.wd() + d6.we() + + d6.wf() + d6.wg() + d6.wh() + d6.wi() + d6.wj() + + d6.wk() + d6.wm() + d6.wq() + d6.wr() + d6.ws() + + d6.wt() + d6.wu() + d6.wv() + d6.ww() + d6.wx() + + d6.wy() + d6.wz()); + $display("sum=%0d", s); + $finish(0); + endrule +endmodule + +endpackage diff --git a/testsuite/bsc.bluesim/block_codegen_sweep/block_codegen_sweep.exp b/testsuite/bsc.bluesim/block_codegen_sweep/block_codegen_sweep.exp new file mode 100644 index 000000000..ba895687f --- /dev/null +++ b/testsuite/bsc.bluesim/block_codegen_sweep/block_codegen_sweep.exp @@ -0,0 +1,28 @@ +# +# Pressure -c codegen-mode byte-identity across the "access count" dimensions, +# stepping each 0 -> 1 -> 2 -> n: +# D1 mkD1_0..3 - number of internal rules reading a shared value +# D2 mkD2_args - number of method arguments (0..3) +# D3 mkD3_1..3 - number of methods in the interface +# D4 mkD4_* - method kind (value / action / actionvalue) +# D5 mkD5_0..3 - number of (non-primitive) submodule instances +# D6 mkSchedFixMeths - many method ports, named out of sorted order (Classic .bs) +# D7 mkD7_fwd - subinterface forwarding to a submodule (the cache shape) +# D8 mkD8_insts - several submodule instances (insertion order != name order) +# D9 mkD9_sink - many regs/rules/methods (declared out of order) together +# +# Each module is a submodule of sysSchedFixTb, so the testsuite's codegen-mode +# check (check_block_codegen_modules, invoked by the test_c_veri worker) +# regenerates each on its own with -c and confirms the per-module +# C++ is byte-identical to the version built as part of the design. +# + +test_c_veri_bsv_multi SchedFixTb sysSchedFixTb \ + { mkD1_0 mkD1_1 mkD1_2 mkD1_3 \ + mkD2_args \ + mkD3_1 mkD3_2 mkD3_3 \ + mkD4_val mkD4_act mkD4_av \ + mkD5_0 mkD5_1 mkD5_2 mkD5_3 \ + mkSchedFixMeths \ + mkD7_fwd mkLeaf \ + mkD8_insts mkD9_sink } diff --git a/testsuite/bsc.bluesim/block_codegen_sweep/sysSchedFixTb.out.expected b/testsuite/bsc.bluesim/block_codegen_sweep/sysSchedFixTb.out.expected new file mode 100644 index 000000000..6972fc156 --- /dev/null +++ b/testsuite/bsc.bluesim/block_codegen_sweep/sysSchedFixTb.out.expected @@ -0,0 +1 @@ +sum=20 diff --git a/testsuite/bsc.bluesim/parallel/Makefile b/testsuite/bsc.bluesim/parallel/Makefile index b746a6e03..bc27b7989 100644 --- a/testsuite/bsc.bluesim/parallel/Makefile +++ b/testsuite/bsc.bluesim/parallel/Makefile @@ -8,5 +8,5 @@ SUBDIRS = include $(CONFDIR)/clean.mk -DONTKEEPFILES += dir?with?many?spec?ial?char?acters +DONTKEEPFILES += dir?with?many?spec?ial?char?acters gcd_blockcg gcd_nested diff --git a/testsuite/bsc.bluesim/parallel/parallel.exp b/testsuite/bsc.bluesim/parallel/parallel.exp index fe0bfb53c..7d14786c1 100644 --- a/testsuite/bsc.bluesim/parallel/parallel.exp +++ b/testsuite/bsc.bluesim/parallel/parallel.exp @@ -17,10 +17,13 @@ compile_object_pass TbGCD.bsv mkTbGCD link_objects_pass {} mkTbGCD {-v -parallel-sim-link 2} # Store the output to a new name, since we are going to re-link later move mkTbGCD.bsc-ccomp-out mkTbGCD-1.bsc-ccomp-out -# Check that the object file for mkGCD was reused +# The previous link generated mkGCD in top form (it was that link's top); +# as a submodule here it must be regenerated in block form, not reused +# (generate shareable block-form objects with -c instead) find_regexp mkTbGCD-1.bsc-ccomp-out {exec\: make} -find_n_strings mkTbGCD-1.bsc-ccomp-out {reuse} 1 -find_n_strings mkTbGCD-1.bsc-ccomp-out {Bluesim object created:} 2 +find_n_strings mkTbGCD-1.bsc-ccomp-out {reuse} 0 +find_n_strings mkTbGCD-1.bsc-ccomp-out {Bluesim object created:} 3 +find_regexp mkTbGCD-1.bsc-ccomp-out {Bluesim object created\: mkGCD\.} find_regexp mkTbGCD-1.bsc-ccomp-out {Bluesim object created\: mkTbGCD\.} find_regexp mkTbGCD-1.bsc-ccomp-out {Bluesim object created\: model\_mkTbGCD\.} @@ -58,4 +61,30 @@ test_c_only_bsv_multi_options TbGCD mkTbGCD {} \ } # ------------------------- +# The C++ generated for the submodule mkGCD does not depend on whether it is +# built as part of its parent mkTbGCD or on its own with the -c codegen mode: +# the per-module .cxx/.h are byte-identical. That is what lets the object be +# generated and compiled once and shared across simulations (and reused by +# the Bluesim dependency analysis). Since the source is byte-identical, +# there is no need to compile, link, or simulate both ways. + +if { $ctest == 1 } { + +compile_object_pass GCD.bsv mkGCD +compile_object_pass TbGCD.bsv mkTbGCD + +# mkGCD on its own, via -c +mkdir gcd_blockcg +gen_modules_pass {mkGCD} {-simdir gcd_blockcg} + +# mkGCD as a submodule, generated as part of linking mkTbGCD +mkdir gcd_nested +link_objects_pass {} mkTbGCD {-simdir gcd_nested} + +compare_file gcd_blockcg/mkGCD.cxx gcd_nested/mkGCD.cxx +compare_file gcd_blockcg/mkGCD.h gcd_nested/mkGCD.h + +} + +# ------------------------- diff --git a/testsuite/bsc.bugs/bluespec_inc/b1390/Test.bsv.bsc-vcomp-out.expected b/testsuite/bsc.bugs/bluespec_inc/b1390/Test.bsv.bsc-vcomp-out.expected index 547930950..f38a886dc 100644 --- a/testsuite/bsc.bugs/bluespec_inc/b1390/Test.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.bugs/bluespec_inc/b1390/Test.bsv.bsc-vcomp-out.expected @@ -3,4 +3,5 @@ compiling Test.bsv code generation for mkTest starts Schedule dump file created: mkTest.sched Verilog file created: mkTest.v +Elaborated module file created: mkTest.ba All packages are up to date. diff --git a/testsuite/bsc.bugs/bluespec_inc/b1390/Test2.bsv.bsc-vcomp-out.expected b/testsuite/bsc.bugs/bluespec_inc/b1390/Test2.bsv.bsc-vcomp-out.expected index 7f06a65ba..d932e7fa8 100644 --- a/testsuite/bsc.bugs/bluespec_inc/b1390/Test2.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.bugs/bluespec_inc/b1390/Test2.bsv.bsc-vcomp-out.expected @@ -3,4 +3,5 @@ compiling Test2.bsv code generation for mkTest2 starts Schedule dump file created: mkTest2.sched Verilog file created: mkTest2.v +Elaborated module file created: mkTest2.ba All packages are up to date. diff --git a/testsuite/bsc.bugs/bluespec_inc/b1619/Bug1619A.bsv.bsc-sched-out.expected b/testsuite/bsc.bugs/bluespec_inc/b1619/Bug1619A.bsv.bsc-sched-out.expected index bc36d4091..d71858441 100644 --- a/testsuite/bsc.bugs/bluespec_inc/b1619/Bug1619A.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.bugs/bluespec_inc/b1619/Bug1619A.bsv.bsc-sched-out.expected @@ -48,4 +48,5 @@ Logical execution order: high_priority, normal, normal_1, normal_2 =========================================== Verilog file created: sysBug1619A.v +Elaborated module file created: sysBug1619A.ba All packages are up to date. diff --git a/testsuite/bsc.bugs/bluespec_inc/b1619/Bug1619B.bsv.bsc-sched-out.expected b/testsuite/bsc.bugs/bluespec_inc/b1619/Bug1619B.bsv.bsc-sched-out.expected index 934f87d4a..b8edd4e13 100644 --- a/testsuite/bsc.bugs/bluespec_inc/b1619/Bug1619B.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.bugs/bluespec_inc/b1619/Bug1619B.bsv.bsc-sched-out.expected @@ -60,4 +60,5 @@ Logical execution order: high_priority, normal, normal_1, normal_2 =========================================== Verilog file created: sysBug1619B.v +Elaborated module file created: sysBug1619B.ba All packages are up to date. diff --git a/testsuite/bsc.bugs/bluespec_inc/b1619/Bug1619C.bsv.bsc-sched-out.expected b/testsuite/bsc.bugs/bluespec_inc/b1619/Bug1619C.bsv.bsc-sched-out.expected index ef68addec..e7d389eba 100644 --- a/testsuite/bsc.bugs/bluespec_inc/b1619/Bug1619C.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.bugs/bluespec_inc/b1619/Bug1619C.bsv.bsc-sched-out.expected @@ -48,4 +48,5 @@ Logical execution order: normal, normal_1, low_priority, normal_2 =========================================== Verilog file created: sysBug1619C.v +Elaborated module file created: sysBug1619C.ba All packages are up to date. diff --git a/testsuite/bsc.bugs/bluespec_inc/b1690/MutEx.bsv.bsc-sched-out.expected b/testsuite/bsc.bugs/bluespec_inc/b1690/MutEx.bsv.bsc-sched-out.expected index f85c993cb..db3d13634 100644 --- a/testsuite/bsc.bugs/bluespec_inc/b1690/MutEx.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.bugs/bluespec_inc/b1690/MutEx.bsv.bsc-sched-out.expected @@ -43,4 +43,5 @@ Logical execution order: r1, r2, done ======================================= Verilog file created: mkMutEx.v +Elaborated module file created: mkMutEx.ba All packages are up to date. diff --git a/testsuite/bsc.bugs/bluespec_inc/b1690/MutExBig.bsv.bsc-sched-out.expected b/testsuite/bsc.bugs/bluespec_inc/b1690/MutExBig.bsv.bsc-sched-out.expected index 052ba206f..62658dd87 100644 --- a/testsuite/bsc.bugs/bluespec_inc/b1690/MutExBig.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.bugs/bluespec_inc/b1690/MutExBig.bsv.bsc-sched-out.expected @@ -100,4 +100,5 @@ Logical execution order: r1, r2, r3, r4, done, r1y, r2y, r3y, r4y, r5y =========================================== Verilog file created: sysMutExBig.v +Elaborated module file created: sysMutExBig.ba All packages are up to date. diff --git a/testsuite/bsc.bugs/bluespec_inc/b323/Test.bsv.bsc-sched-out.expected b/testsuite/bsc.bugs/bluespec_inc/b323/Test.bsv.bsc-sched-out.expected index 85ca335f5..da3061188 100644 --- a/testsuite/bsc.bugs/bluespec_inc/b323/Test.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.bugs/bluespec_inc/b323/Test.bsv.bsc-sched-out.expected @@ -39,4 +39,5 @@ Logical execution order: zero, grter_four, non_zero ===================================== Verilog file created: mkFoo.v +Elaborated module file created: mkFoo.ba All packages are up to date. diff --git a/testsuite/bsc.bugs/bluespec_inc/b518/MethodUrg.bsv.bsc-sched-out.expected b/testsuite/bsc.bugs/bluespec_inc/b518/MethodUrg.bsv.bsc-sched-out.expected index d6c9576a4..7de080fcc 100644 --- a/testsuite/bsc.bugs/bluespec_inc/b518/MethodUrg.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.bugs/bluespec_inc/b518/MethodUrg.bsv.bsc-sched-out.expected @@ -51,4 +51,5 @@ Logical execution order: highx, lowx ========================================= Verilog file created: mkTestUrg.v +Elaborated module file created: mkTestUrg.ba All packages are up to date. diff --git a/testsuite/bsc.codegen/rdy_en_pragmas/rdy_en_pragmas.exp b/testsuite/bsc.codegen/rdy_en_pragmas/rdy_en_pragmas.exp index f150ec9ea..095a4a09f 100644 --- a/testsuite/bsc.codegen/rdy_en_pragmas/rdy_en_pragmas.exp +++ b/testsuite/bsc.codegen/rdy_en_pragmas/rdy_en_pragmas.exp @@ -16,6 +16,10 @@ compile_verilog_pass TestEnableFail.bsv if { $vtest == 1 } { find_n_emsg TestEnableFail.bsv.bsc-vcomp-out Warning G0015 2 } +# the Verilog compile leaves up-to-date generic .ba files, which the -sim +# compile would reuse (skipping elaboration and its warnings); remove them +erase sysTestEnableFail.ba +erase mkSub.ba compile_object_pass TestEnableFail.bsv link_objects_pass {sysTestEnableFail.ba mkSub.ba} sysTestEnableFail if { $ctest == 1 } { diff --git a/testsuite/bsc.driver/depend/CrossElab.bsv b/testsuite/bsc.driver/depend/CrossElab.bsv new file mode 100644 index 000000000..c1f12a63d --- /dev/null +++ b/testsuite/bsc.driver/depend/CrossElab.bsv @@ -0,0 +1,10 @@ +// A module whose elaboration differs by backend (via genVerilog), so its +// .ba file records the backend it was elaborated for +(* synthesize *) +module sysCrossElab(); + Reg#(Bit#(8)) rg <- mkReg(genVerilog ? 1 : 0); + rule r; + $display("val %0d", rg); + $finish(0); + endrule +endmodule diff --git a/testsuite/bsc.driver/depend/VerilogInclude.bsv.bsc-vcomp-out.expected.1 b/testsuite/bsc.driver/depend/VerilogInclude.bsv.bsc-vcomp-out.expected.1 index a0016da52..9ef323da2 100644 --- a/testsuite/bsc.driver/depend/VerilogInclude.bsv.bsc-vcomp-out.expected.1 +++ b/testsuite/bsc.driver/depend/VerilogInclude.bsv.bsc-vcomp-out.expected.1 @@ -3,4 +3,5 @@ compiling VerilogInclude.bsv code generation for sysVerilogInclude starts Compilation message: "./defines", line 1, column 11: defines1 Verilog file created: sysVerilogInclude.v +Elaborated module file created: sysVerilogInclude.ba All packages are up to date. diff --git a/testsuite/bsc.driver/depend/VerilogInclude.bsv.bsc-vcomp-out.expected.2 b/testsuite/bsc.driver/depend/VerilogInclude.bsv.bsc-vcomp-out.expected.2 index a97c763e5..32d0200b5 100644 --- a/testsuite/bsc.driver/depend/VerilogInclude.bsv.bsc-vcomp-out.expected.2 +++ b/testsuite/bsc.driver/depend/VerilogInclude.bsv.bsc-vcomp-out.expected.2 @@ -3,4 +3,5 @@ compiling VerilogInclude.bsv code generation for sysVerilogInclude starts Compilation message: "./defines", line 1, column 11: defines2 Verilog file created: sysVerilogInclude.v +Elaborated module file created: sysVerilogInclude.ba All packages are up to date. diff --git a/testsuite/bsc.driver/depend/depend.exp b/testsuite/bsc.driver/depend/depend.exp index 0075a88a1..3024eb6af 100644 --- a/testsuite/bsc.driver/depend/depend.exp +++ b/testsuite/bsc.driver/depend/depend.exp @@ -55,6 +55,59 @@ compare_file $outfile } +# ----- +# Test that an up-to-date .ba elaborated for a different backend does not +# satisfy the generated-file check: after a Verilog compile of a +# backend-specific module (with -elab), a Bluesim compile with -u must +# re-elaborate rather than leave the Verilog-tagged .ba in place to fail +# the Bluesim link with a backend mismatch (S0042) + +if { $ctest == 1 && $vtest == 1 } { + +compile_verilog_pass CrossElab.bsv sysCrossElab {-elab} +find_regexp [make_bsc_vcomp_output_name CrossElab.bsv] \ + {Elaborated Verilog module file created: sysCrossElab\.ba} + +# recompiling for Bluesim must regenerate the .ba, not skip codegen +compile_object_pass CrossElab.bsv sysCrossElab +find_regexp [make_bsc_ccomp_output_name CrossElab.bsv] \ + {Elaborated Bluesim module file created: sysCrossElab\.ba} + +# and the Bluesim link succeeds +link_objects_pass {} sysCrossElab + +} + +# ----- +# With the Verilog backend, .ba files are now written by default +# (-elab is on, as it has always been for -sim); -no-elab suppresses them + +if { $vtest == 1 } { + +set outfile [make_bsc_vcomp_output_name VerilogElab.bsv] + +erase sysVerilogElab.ba +compile_verilog_pass VerilogElab.bsv {} {} +files_exist sysVerilogElab.ba + +erase sysVerilogElab.ba +# -no-elab must come after -verilog, since the backend flag turns -elab on; +# compile_verilog_pass puts user options first, so run bsc directly +set noelab_out [make_bsc_output_name VerilogElabNoElab] +if [ gen_basic_output {-no-show-timestamps -no-show-version -verilog -no-elab -u -g sysVerilogElab VerilogElab.bsv} $noelab_out ] { + pass "VerilogElab compiles with -verilog -no-elab" +} else { + fail "VerilogElab should compile with -verilog -no-elab" +} +find_regexp_fail $noelab_out {Elaborated} +if { [file exists [file join [absolute $srcdir] $subdir sysVerilogElab.ba]] } { + fail "sysVerilogElab.ba should not exist with -no-elab" +} else { + pass "sysVerilogElab.ba correctly absent with -no-elab" +} + +} + # ----- # Test that generated files associated with noinline functions are # included in the set of files which are checked to force recompilation diff --git a/testsuite/bsc.evaluator/dynamic/errors/ModArg_Clock.bsv.bsc-vcomp-out.expected b/testsuite/bsc.evaluator/dynamic/errors/ModArg_Clock.bsv.bsc-vcomp-out.expected index d18928d01..63a5197ef 100644 --- a/testsuite/bsc.evaluator/dynamic/errors/ModArg_Clock.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.evaluator/dynamic/errors/ModArg_Clock.bsv.bsc-vcomp-out.expected @@ -2,6 +2,7 @@ checking package dependencies compiling ModArg_Clock.bsv code generation for mkSub_ModArg_Clock starts Verilog file created: mkSub_ModArg_Clock.v +Elaborated module file created: mkSub_ModArg_Clock.ba code generation for sysModArg_Clock starts Error: "ModArg_Clock.bsv", line 17, column 8: (G0071) Input clock `clk_in' of submodule `s' is instantiated with a dynamic diff --git a/testsuite/bsc.evaluator/dynamic/errors/ModArg_Inout.bsv.bsc-vcomp-out.expected b/testsuite/bsc.evaluator/dynamic/errors/ModArg_Inout.bsv.bsc-vcomp-out.expected index a071bde9b..96d5a016d 100644 --- a/testsuite/bsc.evaluator/dynamic/errors/ModArg_Inout.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.evaluator/dynamic/errors/ModArg_Inout.bsv.bsc-vcomp-out.expected @@ -2,6 +2,7 @@ checking package dependencies compiling ModArg_Inout.bsv code generation for mkSub_ModArg_Inout starts Verilog file created: mkSub_ModArg_Inout.v +Elaborated module file created: mkSub_ModArg_Inout.ba code generation for sysModArg_Inout starts Error: "ModArg_Inout.bsv", line 11, column 25: (G0094) The expression for a inout could not be evaluated. Inouts must be determined diff --git a/testsuite/bsc.evaluator/dynamic/errors/ModArg_Param.bsv.bsc-vcomp-out.expected b/testsuite/bsc.evaluator/dynamic/errors/ModArg_Param.bsv.bsc-vcomp-out.expected index ca06c13e3..d0bfb5794 100644 --- a/testsuite/bsc.evaluator/dynamic/errors/ModArg_Param.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.evaluator/dynamic/errors/ModArg_Param.bsv.bsc-vcomp-out.expected @@ -2,6 +2,7 @@ checking package dependencies compiling ModArg_Param.bsv code generation for mkSub_ModArg_Param starts Verilog file created: mkSub_ModArg_Param.v +Elaborated module file created: mkSub_ModArg_Param.ba code generation for sysModArg_Param starts Error: "ModArg_Param.bsv", line 11, column 8: (G0053) Parameter `b' of submodule `s' is instantiated with a dynamic expression. diff --git a/testsuite/bsc.evaluator/dynamic/errors/ModArg_Reset.bsv.bsc-vcomp-out.expected b/testsuite/bsc.evaluator/dynamic/errors/ModArg_Reset.bsv.bsc-vcomp-out.expected index 08c82a84c..fbdca5ff3 100644 --- a/testsuite/bsc.evaluator/dynamic/errors/ModArg_Reset.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.evaluator/dynamic/errors/ModArg_Reset.bsv.bsc-vcomp-out.expected @@ -2,6 +2,7 @@ checking package dependencies compiling ModArg_Reset.bsv code generation for mkSub_ModArg_Reset starts Verilog file created: mkSub_ModArg_Reset.v +Elaborated module file created: mkSub_ModArg_Reset.ba code generation for sysModArg_Reset starts Error: "ModArg_Reset.bsv", line 21, column 8: (G0072) Input reset `rst_in' of submodule `s' is instantiated with a dynamic diff --git a/testsuite/bsc.evaluator/show-progress/BuildModule.bsv.bsc-vcomp-out.expected b/testsuite/bsc.evaluator/show-progress/BuildModule.bsv.bsc-vcomp-out.expected index f259a7bf8..097f7de48 100644 --- a/testsuite/bsc.evaluator/show-progress/BuildModule.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.evaluator/show-progress/BuildModule.bsv.bsc-vcomp-out.expected @@ -31,4 +31,5 @@ code generation for sysBuildModule starts [TIME] elab progress: Elaborating interface [TIME] elab progress: Finished elaborating module `sysBuildModule' Verilog file created: sysBuildModule.v +Elaborated module file created: sysBuildModule.ba All packages are up to date. diff --git a/testsuite/bsc.evaluator/show-progress/StaticAssert.bsv.bsc-vcomp-out.expected b/testsuite/bsc.evaluator/show-progress/StaticAssert.bsv.bsc-vcomp-out.expected index bd712556e..97f3e0a97 100644 --- a/testsuite/bsc.evaluator/show-progress/StaticAssert.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.evaluator/show-progress/StaticAssert.bsv.bsc-vcomp-out.expected @@ -15,4 +15,5 @@ code generation for sysStaticAssert starts [TIME] elab progress: Elaborating interface [TIME] elab progress: Finished elaborating module `sysStaticAssert' Verilog file created: sysStaticAssert.v +Elaborated module file created: sysStaticAssert.ba All packages are up to date. diff --git a/testsuite/bsc.evaluator/show-progress/Test1-hide.bsv.bsc-vcomp-out.expected b/testsuite/bsc.evaluator/show-progress/Test1-hide.bsv.bsc-vcomp-out.expected index 9a9875b55..0098e0956 100644 --- a/testsuite/bsc.evaluator/show-progress/Test1-hide.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.evaluator/show-progress/Test1-hide.bsv.bsc-vcomp-out.expected @@ -28,4 +28,5 @@ code generation for sysTest1 starts [TIME] elab progress: Elaborating interface [TIME] elab progress: Finished elaborating module `sysTest1' Verilog file created: sysTest1.v +Elaborated module file created: sysTest1.ba All packages are up to date. diff --git a/testsuite/bsc.evaluator/show-progress/Test1-show.bsv.bsc-vcomp-out.expected b/testsuite/bsc.evaluator/show-progress/Test1-show.bsv.bsc-vcomp-out.expected index ae4b3a470..2b6b14119 100644 --- a/testsuite/bsc.evaluator/show-progress/Test1-show.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.evaluator/show-progress/Test1-show.bsv.bsc-vcomp-out.expected @@ -46,4 +46,5 @@ code generation for sysTest1 starts [TIME] elab progress: Elaborating interface [TIME] elab progress: Finished elaborating module `sysTest1' Verilog file created: sysTest1.v +Elaborated module file created: sysTest1.ba All packages are up to date. diff --git a/testsuite/bsc.interra/MCD_library/NullCrossing/Nullcross.exp b/testsuite/bsc.interra/MCD_library/NullCrossing/Nullcross.exp index cb9fcb9c1..0bf348fcb 100644 --- a/testsuite/bsc.interra/MCD_library/NullCrossing/Nullcross.exp +++ b/testsuite/bsc.interra/MCD_library/NullCrossing/Nullcross.exp @@ -7,7 +7,26 @@ test_veri_only_bsv_multi Testbench_same_with_phase_diff mkTestbench_same_with_ph compile_verilog_fail Negative.bsv {mkDesign} # Bluesim does not support dynamic arguments yet +# (the Verilog builds above left up-to-date generic .ba files, which the +# -sim compiles would reuse, skipping elaboration and these errors; +# remove them so the compile-time errors are still exercised. mkDesign.ba +# must go too: the up-to-date check knows only pragma-marked modules, so a +# fresh mkDesign.ba alone keeps the package "up to date") +erase mkDesign.ba +erase mkTestbench_fast_to_slow.ba +erase mkTestbench_slow_to_fast.ba +erase mkTestbench_same_with_phase_diff.ba compile_object_fail_error Testbench_fast_to_slow.bsv G0058 1 mkTestbench_fast_to_slow compile_object_fail_error Testbench_slow_to_fast.bsv G0058 1 mkTestbench_slow_to_fast compile_object_fail_error Testbench_same_with_phase_diff.bsv G0058 1 mkTestbench_same_with_phase_diff +# With an up-to-date generic .ba (here from a -verilog compile), a -sim +# compile reuses it and succeeds; the Bluesim-unsupported errors then +# fire at the next step, when the .ba is used for linking (the link walks +# the whole design, so it reports the design's imported-BVI first, G0084) +if { $ctest == 1 } { +compile_verilog_pass Testbench_fast_to_slow.bsv mkTestbench_fast_to_slow +compile_object_pass Testbench_fast_to_slow.bsv mkTestbench_fast_to_slow +link_objects_fail_error {} mkTestbench_fast_to_slow G0084 1 +} + diff --git a/testsuite/bsc.interra/Path_Analysis/Input_Output_Path/Argument2Rdy.bsv.bsc-vcomp-out.expected b/testsuite/bsc.interra/Path_Analysis/Input_Output_Path/Argument2Rdy.bsv.bsc-vcomp-out.expected index fe2613da0..64aa67ac3 100644 --- a/testsuite/bsc.interra/Path_Analysis/Input_Output_Path/Argument2Rdy.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.interra/Path_Analysis/Input_Output_Path/Argument2Rdy.bsv.bsc-vcomp-out.expected @@ -8,4 +8,5 @@ Combinational paths from inputs to outputs: ----- Verilog file created: mkArgument2Rdy.v +Elaborated module file created: mkArgument2Rdy.ba All packages are up to date. diff --git a/testsuite/bsc.interra/Path_Analysis/Input_Output_Path/Argument2ReturnValue.bsv.bsc-vcomp-out.expected b/testsuite/bsc.interra/Path_Analysis/Input_Output_Path/Argument2ReturnValue.bsv.bsc-vcomp-out.expected index 472062dd4..00cf263d5 100644 --- a/testsuite/bsc.interra/Path_Analysis/Input_Output_Path/Argument2ReturnValue.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.interra/Path_Analysis/Input_Output_Path/Argument2ReturnValue.bsv.bsc-vcomp-out.expected @@ -8,4 +8,5 @@ Combinational paths from inputs to outputs: ----- Verilog file created: mkArgument2ReturnValue.v +Elaborated module file created: mkArgument2ReturnValue.ba All packages are up to date. diff --git a/testsuite/bsc.interra/Path_Analysis/Input_Output_Path/Argument2ReturnValue2.bsv.bsc-vcomp-out.expected b/testsuite/bsc.interra/Path_Analysis/Input_Output_Path/Argument2ReturnValue2.bsv.bsc-vcomp-out.expected index 29b470faa..91fae421a 100644 --- a/testsuite/bsc.interra/Path_Analysis/Input_Output_Path/Argument2ReturnValue2.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.interra/Path_Analysis/Input_Output_Path/Argument2ReturnValue2.bsv.bsc-vcomp-out.expected @@ -8,4 +8,5 @@ Combinational paths from inputs to outputs: ----- Verilog file created: mkArgument2ReturnValue2.v +Elaborated module file created: mkArgument2ReturnValue2.ba All packages are up to date. diff --git a/testsuite/bsc.interra/Path_Analysis/Input_Output_Path/Argument2ReturnValue3.bsv.bsc-vcomp-out.expected b/testsuite/bsc.interra/Path_Analysis/Input_Output_Path/Argument2ReturnValue3.bsv.bsc-vcomp-out.expected index c2abe15ec..5820e18af 100644 --- a/testsuite/bsc.interra/Path_Analysis/Input_Output_Path/Argument2ReturnValue3.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.interra/Path_Analysis/Input_Output_Path/Argument2ReturnValue3.bsv.bsc-vcomp-out.expected @@ -8,6 +8,7 @@ Combinational paths from inputs to outputs: ----- Verilog file created: mkArgument2ReturnValue3.v +Elaborated module file created: mkArgument2ReturnValue3.ba Warning: "Argument2ReturnValue3.bsv", line 7, column 8: (T0157) Package `FIFO' is imported but not used All packages are up to date. diff --git a/testsuite/bsc.interra/Path_Analysis/Input_Output_Path/En2Rdy5.bsv.bsc-vcomp-out.expected b/testsuite/bsc.interra/Path_Analysis/Input_Output_Path/En2Rdy5.bsv.bsc-vcomp-out.expected index 98265b6ff..e76d21b49 100644 --- a/testsuite/bsc.interra/Path_Analysis/Input_Output_Path/En2Rdy5.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.interra/Path_Analysis/Input_Output_Path/En2Rdy5.bsv.bsc-vcomp-out.expected @@ -8,4 +8,5 @@ Combinational paths from inputs to outputs: ----- Verilog file created: mkEn2Rdy5.v +Elaborated module file created: mkEn2Rdy5.ba All packages are up to date. diff --git a/testsuite/bsc.interra/Path_Analysis/Input_Output_Path/En2ReturnValue.bsv.bsc-vcomp-out.expected b/testsuite/bsc.interra/Path_Analysis/Input_Output_Path/En2ReturnValue.bsv.bsc-vcomp-out.expected index f86a08077..6f52c9794 100644 --- a/testsuite/bsc.interra/Path_Analysis/Input_Output_Path/En2ReturnValue.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.interra/Path_Analysis/Input_Output_Path/En2ReturnValue.bsv.bsc-vcomp-out.expected @@ -8,4 +8,5 @@ Combinational paths from inputs to outputs: ----- Verilog file created: mkEn2ReturnValue.v +Elaborated module file created: mkEn2ReturnValue.ba All packages are up to date. diff --git a/testsuite/bsc.interra/Path_Analysis/Input_Output_Path/MuxMethods1.bsv.bsc-vcomp-out.expected b/testsuite/bsc.interra/Path_Analysis/Input_Output_Path/MuxMethods1.bsv.bsc-vcomp-out.expected index b87222c6d..8d2f9bd9f 100644 --- a/testsuite/bsc.interra/Path_Analysis/Input_Output_Path/MuxMethods1.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.interra/Path_Analysis/Input_Output_Path/MuxMethods1.bsv.bsc-vcomp-out.expected @@ -9,4 +9,5 @@ Combinational paths from inputs to outputs: ----- Verilog file created: mkMuxMethods1.v +Elaborated module file created: mkMuxMethods1.ba All packages are up to date. diff --git a/testsuite/bsc.interra/Path_Analysis/Input_Output_Path/Parameter2Rdy.bsv.bsc-vcomp-out.expected b/testsuite/bsc.interra/Path_Analysis/Input_Output_Path/Parameter2Rdy.bsv.bsc-vcomp-out.expected index 5cc5b9cbc..b8b88fcfd 100644 --- a/testsuite/bsc.interra/Path_Analysis/Input_Output_Path/Parameter2Rdy.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.interra/Path_Analysis/Input_Output_Path/Parameter2Rdy.bsv.bsc-vcomp-out.expected @@ -8,6 +8,7 @@ Combinational paths from inputs to outputs: ----- Verilog file created: mkParameter2Rdy.v +Elaborated module file created: mkParameter2Rdy.ba Warning: "Parameter2Rdy.bsv", line 6, column 8: (T0157) Package `FIFO' is imported but not used All packages are up to date. diff --git a/testsuite/bsc.interra/Path_Analysis/Input_Output_Path/Parameter2ReturnValue.bsv.bsc-vcomp-out.expected b/testsuite/bsc.interra/Path_Analysis/Input_Output_Path/Parameter2ReturnValue.bsv.bsc-vcomp-out.expected index fc7358460..a7ed0cf9c 100644 --- a/testsuite/bsc.interra/Path_Analysis/Input_Output_Path/Parameter2ReturnValue.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.interra/Path_Analysis/Input_Output_Path/Parameter2ReturnValue.bsv.bsc-vcomp-out.expected @@ -8,6 +8,7 @@ Combinational paths from inputs to outputs: ----- Verilog file created: mkParameter2ReturnValue.v +Elaborated module file created: mkParameter2ReturnValue.ba Warning: "Parameter2ReturnValue.bsv", line 6, column 8: (T0157) Package `FIFO' is imported but not used All packages are up to date. diff --git a/testsuite/bsc.interra/bugs/bugID231/TestSyn.bs.bsc-vcomp-out.expected b/testsuite/bsc.interra/bugs/bugID231/TestSyn.bs.bsc-vcomp-out.expected index df00e9327..9d4375ae0 100644 --- a/testsuite/bsc.interra/bugs/bugID231/TestSyn.bs.bsc-vcomp-out.expected +++ b/testsuite/bsc.interra/bugs/bugID231/TestSyn.bs.bsc-vcomp-out.expected @@ -2,4 +2,5 @@ checking package dependencies compiling TestSyn.bs code generation for mkStack starts Verilog file created: mkStack.v +Elaborated module file created: mkStack.ba All packages are up to date. diff --git a/testsuite/bsc.interra/bugs/bugID265/Design_0.bsv.bsc-vcomp-out.expected b/testsuite/bsc.interra/bugs/bugID265/Design_0.bsv.bsc-vcomp-out.expected index df343ce67..22856c66d 100644 --- a/testsuite/bsc.interra/bugs/bugID265/Design_0.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.interra/bugs/bugID265/Design_0.bsv.bsc-vcomp-out.expected @@ -2,4 +2,5 @@ checking package dependencies compiling Design_0.bsv code generation for mkDesign_in starts Verilog file created: mkDesign_in.v +Elaborated module file created: mkDesign_in.ba All packages are up to date. diff --git a/testsuite/bsc.interra/bugs/bugID265/Design_1.bsv.bsc-vcomp-out.expected b/testsuite/bsc.interra/bugs/bugID265/Design_1.bsv.bsc-vcomp-out.expected index 6b4bc19ac..889050d3a 100644 --- a/testsuite/bsc.interra/bugs/bugID265/Design_1.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.interra/bugs/bugID265/Design_1.bsv.bsc-vcomp-out.expected @@ -2,4 +2,5 @@ checking package dependencies compiling Design_1.bsv code generation for mkDesign starts Verilog file created: mkDesign.v +Elaborated module file created: mkDesign.ba All packages are up to date. diff --git a/testsuite/bsc.interra/bugs/bugID363/Design.bsv.bsc-vcomp-out.expected b/testsuite/bsc.interra/bugs/bugID363/Design.bsv.bsc-vcomp-out.expected index c1c330e1c..faabfca78 100644 --- a/testsuite/bsc.interra/bugs/bugID363/Design.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.interra/bugs/bugID363/Design.bsv.bsc-vcomp-out.expected @@ -2,4 +2,5 @@ checking package dependencies compiling Design.bsv code generation for mkDesign starts Verilog file created: mkDesign.v +Elaborated module file created: mkDesign.ba All packages are up to date. diff --git a/testsuite/bsc.interra/bugs/bugID383/MkCompletionBuffer.bsv.bsc-vcomp-out.expected b/testsuite/bsc.interra/bugs/bugID383/MkCompletionBuffer.bsv.bsc-vcomp-out.expected index 8a11edea5..ea201b896 100644 --- a/testsuite/bsc.interra/bugs/bugID383/MkCompletionBuffer.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.interra/bugs/bugID383/MkCompletionBuffer.bsv.bsc-vcomp-out.expected @@ -2,4 +2,5 @@ checking package dependencies compiling MkCompletionBuffer.bsv code generation for mkDesign starts Verilog file created: mkDesign.v +Elaborated module file created: mkDesign.ba All packages are up to date. diff --git a/testsuite/bsc.interra/bugs/bugID413/Design.bsv.bsc-vcomp-out.expected b/testsuite/bsc.interra/bugs/bugID413/Design.bsv.bsc-vcomp-out.expected index c1c330e1c..faabfca78 100644 --- a/testsuite/bsc.interra/bugs/bugID413/Design.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.interra/bugs/bugID413/Design.bsv.bsc-vcomp-out.expected @@ -2,4 +2,5 @@ checking package dependencies compiling Design.bsv code generation for mkDesign starts Verilog file created: mkDesign.v +Elaborated module file created: mkDesign.ba All packages are up to date. diff --git a/testsuite/bsc.interra/bugs/bugID415/Alternate.bsv.bsc-vcomp-out.expected b/testsuite/bsc.interra/bugs/bugID415/Alternate.bsv.bsc-vcomp-out.expected index 190fd37ee..69f738209 100644 --- a/testsuite/bsc.interra/bugs/bugID415/Alternate.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.interra/bugs/bugID415/Alternate.bsv.bsc-vcomp-out.expected @@ -2,4 +2,5 @@ checking package dependencies compiling Alternate.bsv code generation for mkAlternate starts Verilog file created: mkAlternate.v +Elaborated module file created: mkAlternate.ba All packages are up to date. diff --git a/testsuite/bsc.interra/bugs/bugID415/Design.bsv.bsc-vcomp-out.expected b/testsuite/bsc.interra/bugs/bugID415/Design.bsv.bsc-vcomp-out.expected index c1c330e1c..faabfca78 100644 --- a/testsuite/bsc.interra/bugs/bugID415/Design.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.interra/bugs/bugID415/Design.bsv.bsc-vcomp-out.expected @@ -2,4 +2,5 @@ checking package dependencies compiling Design.bsv code generation for mkDesign starts Verilog file created: mkDesign.v +Elaborated module file created: mkDesign.ba All packages are up to date. diff --git a/testsuite/bsc.interra/messages/EArbitrate/ResourceTwoRules.bs.bsc-vcomp-out.expected b/testsuite/bsc.interra/messages/EArbitrate/ResourceTwoRules.bs.bsc-vcomp-out.expected index 3b27536e0..7236ad1f0 100644 --- a/testsuite/bsc.interra/messages/EArbitrate/ResourceTwoRules.bs.bsc-vcomp-out.expected +++ b/testsuite/bsc.interra/messages/EArbitrate/ResourceTwoRules.bs.bsc-vcomp-out.expected @@ -19,4 +19,5 @@ Warning: "ResourceTwoRules.bs", line 36, column 0: (G0010) Warning: "ResourceTwoRules.bs", line 40, column 27: (G0021) According to the generated schedule, rule `Contender_1' can never fire. Verilog file created: sysResourceTwoRules.v +Elaborated module file created: sysResourceTwoRules.ba All packages are up to date. diff --git a/testsuite/bsc.interra/messages/EGeneric/EGeneric.bs.bsc-vcomp-out.expected b/testsuite/bsc.interra/messages/EGeneric/EGeneric.bs.bsc-vcomp-out.expected index f7c83e3ef..4f88bc565 100755 --- a/testsuite/bsc.interra/messages/EGeneric/EGeneric.bs.bsc-vcomp-out.expected +++ b/testsuite/bsc.interra/messages/EGeneric/EGeneric.bs.bsc-vcomp-out.expected @@ -7,3 +7,4 @@ Error: "EGeneric.bs", line 29, column 10: (G0004) and x.write(...) For the complete expressions use the flag `-show-range-conflict'. +Elaborated error module file created: mkTest.ba diff --git a/testsuite/bsc.interra/messages/EHasImplicit/EHasImplicit2.bs.bsc-vcomp-out.expected b/testsuite/bsc.interra/messages/EHasImplicit/EHasImplicit2.bs.bsc-vcomp-out.expected index aa4a92bfa..672b2e0a8 100644 --- a/testsuite/bsc.interra/messages/EHasImplicit/EHasImplicit2.bs.bsc-vcomp-out.expected +++ b/testsuite/bsc.interra/messages/EHasImplicit/EHasImplicit2.bs.bsc-vcomp-out.expected @@ -2,6 +2,7 @@ checking package dependencies compiling EHasImplicit2.bs code generation for mkPort starts Verilog file created: mkPort.v +Elaborated module file created: mkPort.ba code generation for mkTop starts Error: "EHasImplicit2.bs", line 16, column 10: (G0081) Module arguments cannot have implicit conditions. The expression for diff --git a/testsuite/bsc.interra/messages/EResources/EResources.bs.bsc-vcomp-out.expected b/testsuite/bsc.interra/messages/EResources/EResources.bs.bsc-vcomp-out.expected index 6b022d6a2..a18390222 100755 --- a/testsuite/bsc.interra/messages/EResources/EResources.bs.bsc-vcomp-out.expected +++ b/testsuite/bsc.interra/messages/EResources/EResources.bs.bsc-vcomp-out.expected @@ -2,8 +2,10 @@ checking package dependencies compiling EResources.bs code generation for subtractor starts Verilog file created: subtractor.v +Elaborated module file created: subtractor.ba code generation for mkDifference starts Error: "EResources.bs", line 43, column 13: (G0002) `m.minus' needs more than 1 ports for the following uses: `m.minus x___d1 y___d2' at "EResources.bs", line 43, column 13 `m.minus y___d2 x___d1' at "EResources.bs", line 43, column 13 +Elaborated error module file created: mkDifference.ba diff --git a/testsuite/bsc.interra/messages/ERuleAssertion/ERuleAssertion.bs.bsc-vcomp-out.expected b/testsuite/bsc.interra/messages/ERuleAssertion/ERuleAssertion.bs.bsc-vcomp-out.expected index 9e2e7184e..9c6755bdf 100755 --- a/testsuite/bsc.interra/messages/ERuleAssertion/ERuleAssertion.bs.bsc-vcomp-out.expected +++ b/testsuite/bsc.interra/messages/ERuleAssertion/ERuleAssertion.bs.bsc-vcomp-out.expected @@ -17,3 +17,4 @@ Error: "ERuleAssertion.bs", line 43, column 10: (G0005) result -> [], RL_Swap -> [], RL_Subtract -> [RL_Swap]] +Elaborated error module file created: mkGCD.ba diff --git a/testsuite/bsc.interra/messages/WCycleDrop/WCycleDrop1.bs.bsc-vcomp-out.expected b/testsuite/bsc.interra/messages/WCycleDrop/WCycleDrop1.bs.bsc-vcomp-out.expected index 2caa44759..8198d4bc6 100755 --- a/testsuite/bsc.interra/messages/WCycleDrop/WCycleDrop1.bs.bsc-vcomp-out.expected +++ b/testsuite/bsc.interra/messages/WCycleDrop/WCycleDrop1.bs.bsc-vcomp-out.expected @@ -34,4 +34,5 @@ Warning: "WCycleDrop1.bs", line 30, column 0: (G0117) Warning: "WCycleDrop1.bs", line 54, column 22: (G0021) According to the generated schedule, rule `Two' can never fire. Verilog file created: mkWCycleDrop1.v +Elaborated module file created: mkWCycleDrop1.ba All packages are up to date. diff --git a/testsuite/bsc.interra/messages/WMissingRule/WMissingRule1.bs.bsc-vcomp-out.expected b/testsuite/bsc.interra/messages/WMissingRule/WMissingRule1.bs.bsc-vcomp-out.expected index cc26ecd81..b06d95c8a 100755 --- a/testsuite/bsc.interra/messages/WMissingRule/WMissingRule1.bs.bsc-vcomp-out.expected +++ b/testsuite/bsc.interra/messages/WMissingRule/WMissingRule1.bs.bsc-vcomp-out.expected @@ -44,4 +44,5 @@ Warning: "WMissingRule1.bs", line 58, column 22: (G0021) Warning: "WMissingRule1.bs", line 65, column 22: (G0021) According to the generated schedule, rule `Four' can never fire. Verilog file created: mkWMissingRule1.v +Elaborated module file created: mkWMissingRule1.ba All packages are up to date. diff --git a/testsuite/bsc.interra/messages/WUrgencyChoice/WUrgencyChoice1.bs.bsc-vcomp-out.expected b/testsuite/bsc.interra/messages/WUrgencyChoice/WUrgencyChoice1.bs.bsc-vcomp-out.expected index 13446320c..f080dfbad 100755 --- a/testsuite/bsc.interra/messages/WUrgencyChoice/WUrgencyChoice1.bs.bsc-vcomp-out.expected +++ b/testsuite/bsc.interra/messages/WUrgencyChoice/WUrgencyChoice1.bs.bsc-vcomp-out.expected @@ -34,4 +34,5 @@ Warning: "WUrgencyChoice1.bs", line 50, column 22: (G0021) Warning: "WUrgencyChoice1.bs", line 60, column 22: (G0021) According to the generated schedule, rule `Four' can never fire. Verilog file created: mkWUrgencyChoice1.v +Elaborated module file created: mkWUrgencyChoice1.ba All packages are up to date. diff --git a/testsuite/bsc.interra/messages/WUrgencyChoice/WUrgencyChoice2.bs.bsc-vcomp-out.expected b/testsuite/bsc.interra/messages/WUrgencyChoice/WUrgencyChoice2.bs.bsc-vcomp-out.expected index 265ab498a..35dbfef81 100755 --- a/testsuite/bsc.interra/messages/WUrgencyChoice/WUrgencyChoice2.bs.bsc-vcomp-out.expected +++ b/testsuite/bsc.interra/messages/WUrgencyChoice/WUrgencyChoice2.bs.bsc-vcomp-out.expected @@ -18,4 +18,5 @@ Warning: "WUrgencyChoice2.bs", line 23, column 0: (G0117) Warning: "WUrgencyChoice2.bs", line 39, column 17: (G0021) According to the generated schedule, rule `Two' can never fire. Verilog file created: mkWUrgencyChoice2.v +Elaborated module file created: mkWUrgencyChoice2.ba All packages are up to date. diff --git a/testsuite/bsc.lib/IsModule/FIFOContextTest.bsv.bsc-vcomp-out.expected b/testsuite/bsc.lib/IsModule/FIFOContextTest.bsv.bsc-vcomp-out.expected index 8a059d82b..466a142ce 100644 --- a/testsuite/bsc.lib/IsModule/FIFOContextTest.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.lib/IsModule/FIFOContextTest.bsv.bsc-vcomp-out.expected @@ -3,4 +3,5 @@ compiling FIFOContextTest.bsv code generation for mkFIFOContextTest starts Compilation message: "FIFOContextTest.bsv", line 34, column 42: Final state was: 7 Verilog file created: mkFIFOContextTest.v +Elaborated module file created: mkFIFOContextTest.ba All packages are up to date. diff --git a/testsuite/bsc.lib/IsModule/ModuleCollectClock.bsv.bsc-vcomp-out.expected b/testsuite/bsc.lib/IsModule/ModuleCollectClock.bsv.bsc-vcomp-out.expected index 24b02d604..eebc1fd7f 100644 --- a/testsuite/bsc.lib/IsModule/ModuleCollectClock.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.lib/IsModule/ModuleCollectClock.bsv.bsc-vcomp-out.expected @@ -3,4 +3,5 @@ compiling ModuleCollectClock.bsv code generation for mkTestWrapper starts Compilation message: "ModuleCollectClock.bsv", line 22, column 22: 5 Verilog file created: mkTestWrapper.v +Elaborated module file created: mkTestWrapper.ba All packages are up to date. diff --git a/testsuite/bsc.lib/IsModule/ModuleContextClock.bsv.bsc-vcomp-out.expected b/testsuite/bsc.lib/IsModule/ModuleContextClock.bsv.bsc-vcomp-out.expected index c4215d4e4..3ff941a9b 100644 --- a/testsuite/bsc.lib/IsModule/ModuleContextClock.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.lib/IsModule/ModuleContextClock.bsv.bsc-vcomp-out.expected @@ -3,4 +3,5 @@ compiling ModuleContextClock.bsv code generation for mkTestWrapper2 starts Compilation message: "ModuleContextClock.bsv", line 23, column 13: 1 Verilog file created: mkTestWrapper2.v +Elaborated module file created: mkTestWrapper2.ba All packages are up to date. diff --git a/testsuite/bsc.lib/rwire/BypassReg.bsv.bsc-sched-out.expected b/testsuite/bsc.lib/rwire/BypassReg.bsv.bsc-sched-out.expected index c065356dc..c4efc8174 100644 --- a/testsuite/bsc.lib/rwire/BypassReg.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.lib/rwire/BypassReg.bsv.bsc-sched-out.expected @@ -55,4 +55,5 @@ Logical execution order: _write, _read, the_r_propagate ============================================ Verilog file created: sysBypassReg.v +Elaborated module file created: sysBypassReg.ba All packages are up to date. diff --git a/testsuite/bsc.lib/rwire/ConfigReg2.bsv.bsc-sched-out.expected b/testsuite/bsc.lib/rwire/ConfigReg2.bsv.bsc-sched-out.expected index cab9657d0..6b9e4f80d 100644 --- a/testsuite/bsc.lib/rwire/ConfigReg2.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.lib/rwire/ConfigReg2.bsv.bsc-sched-out.expected @@ -52,4 +52,5 @@ Logical execution order: _write, _read, the_r_propagate ============================================ Verilog file created: sysConfigReg.v +Elaborated module file created: sysConfigReg.ba All packages are up to date. diff --git a/testsuite/bsc.mcd/MultErrors/MsgTest_ClockOfMultiClock.bsv.bsc-vcomp-out.expected b/testsuite/bsc.mcd/MultErrors/MsgTest_ClockOfMultiClock.bsv.bsc-vcomp-out.expected index a30806694..a5204037f 100644 --- a/testsuite/bsc.mcd/MultErrors/MsgTest_ClockOfMultiClock.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.mcd/MultErrors/MsgTest_ClockOfMultiClock.bsv.bsc-vcomp-out.expected @@ -18,4 +18,5 @@ Warning: "MsgTest_ClockOfMultiClock.bsv", line 24, column 8: (G0038) "MsgTest_ClockOfMultiClock.bsv", line 8, column 8. Compilation message: "MsgTest_ClockOfMultiClock.bsv", line 25, column 15: True Verilog file created: sysMsgTest_ClockOfMultiClock.v +Elaborated module file created: sysMsgTest_ClockOfMultiClock.ba All packages are up to date. diff --git a/testsuite/bsc.mcd/MultErrors/MsgTest_MultiReset.bsv.bsc-vcomp-out.expected b/testsuite/bsc.mcd/MultErrors/MsgTest_MultiReset.bsv.bsc-vcomp-out.expected index 177d08f41..cd8c1cc5e 100644 --- a/testsuite/bsc.mcd/MultErrors/MsgTest_MultiReset.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.mcd/MultErrors/MsgTest_MultiReset.bsv.bsc-vcomp-out.expected @@ -17,4 +17,5 @@ Warning: "MsgTest_MultiReset.bsv", line 19, column 9: (G0043) During elaboration of `sysMsgTest_MultiReset' at "MsgTest_MultiReset.bsv", line 8, column 8. Verilog file created: sysMsgTest_MultiReset.v +Elaborated module file created: sysMsgTest_MultiReset.ba All packages are up to date. diff --git a/testsuite/bsc.mcd/MultErrors/MsgTest_ResetOfMultiReset.bsv.bsc-vcomp-out.expected b/testsuite/bsc.mcd/MultErrors/MsgTest_ResetOfMultiReset.bsv.bsc-vcomp-out.expected index f8c412a8f..e5bbff926 100644 --- a/testsuite/bsc.mcd/MultErrors/MsgTest_ResetOfMultiReset.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.mcd/MultErrors/MsgTest_ResetOfMultiReset.bsv.bsc-vcomp-out.expected @@ -16,4 +16,5 @@ Warning: "MsgTest_ResetOfMultiReset.bsv", line 27, column 8: (G0044) "MsgTest_ResetOfMultiReset.bsv", line 8, column 8. Compilation message: "MsgTest_ResetOfMultiReset.bsv", line 28, column 15: True Verilog file created: sysMsgTest_MultiReset.v +Elaborated module file created: sysMsgTest_MultiReset.ba All packages are up to date. diff --git a/testsuite/bsc.mcd/NoClock/NoClock.exp b/testsuite/bsc.mcd/NoClock/NoClock.exp index 4684733b2..4be60175f 100644 --- a/testsuite/bsc.mcd/NoClock/NoClock.exp +++ b/testsuite/bsc.mcd/NoClock/NoClock.exp @@ -18,10 +18,16 @@ test_c_veri_bsv OutputNoClock # (and that neither impedes Verilog or Blueim compilation) compile_verilog_pass_warning FixupRule_NoDefaultClock.bsv G0023 +# the Verilog compile leaves an up-to-date generic .ba, which the -sim +# compile would reuse (skipping elaboration and its warning); remove it +erase sysFixupRule_NoDefaultClock.ba compile_object_pass_warning FixupRule_NoDefaultClock.bsv G0023 link_objects_pass {} sysFixupRule_NoDefaultClock compile_verilog_pass_warning FixupRule_NoClock.bsv G0023 +# the Verilog compile leaves an up-to-date generic .ba, which the -sim +# compile would reuse (skipping elaboration and its warning); remove it +erase sysFixupRule_NoClock.ba compile_object_pass_warning FixupRule_NoClock.bsv G0023 link_objects_pass {} sysFixupRule_NoClock diff --git a/testsuite/bsc.mcd/Reset/Boundary_Method_MissingReset.bsv.bsc-vcomp-out.expected b/testsuite/bsc.mcd/Reset/Boundary_Method_MissingReset.bsv.bsc-vcomp-out.expected index 9289da2c9..844c55a8f 100644 --- a/testsuite/bsc.mcd/Reset/Boundary_Method_MissingReset.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.mcd/Reset/Boundary_Method_MissingReset.bsv.bsc-vcomp-out.expected @@ -9,4 +9,5 @@ Warning: "Boundary_Method_MissingReset.bsv", line 8, column 8: (G0046) During elaboration of `sysBoundary_Method_MissingReset' at "Boundary_Method_MissingReset.bsv", line 8, column 8. Verilog file created: sysBoundary_Method_MissingReset.v +Elaborated module file created: sysBoundary_Method_MissingReset.ba All packages are up to date. diff --git a/testsuite/bsc.mcd/Reset/Boundary_Method_MultipleReset.bsv.bsc-vcomp-out.expected b/testsuite/bsc.mcd/Reset/Boundary_Method_MultipleReset.bsv.bsc-vcomp-out.expected index 2045aa38f..43917262e 100644 --- a/testsuite/bsc.mcd/Reset/Boundary_Method_MultipleReset.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.mcd/Reset/Boundary_Method_MultipleReset.bsv.bsc-vcomp-out.expected @@ -23,4 +23,5 @@ Warning: "Boundary_Method_MultipleReset.bsv", line 6, column 8: (G0127) During elaboration of `sysBoundary_Method_MultipleReset' at "Boundary_Method_MultipleReset.bsv", line 6, column 8. Verilog file created: sysBoundary_Method_MultipleReset.v +Elaborated module file created: sysBoundary_Method_MultipleReset.ba All packages are up to date. diff --git a/testsuite/bsc.mcd/Reset/Boundary_Method_MultipleReset_AllMissing.bsv.bsc-vcomp-out.expected b/testsuite/bsc.mcd/Reset/Boundary_Method_MultipleReset_AllMissing.bsv.bsc-vcomp-out.expected index 778f9b533..fa2f21e1d 100644 --- a/testsuite/bsc.mcd/Reset/Boundary_Method_MultipleReset_AllMissing.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.mcd/Reset/Boundary_Method_MultipleReset_AllMissing.bsv.bsc-vcomp-out.expected @@ -22,4 +22,5 @@ Warning: "Boundary_Method_MultipleReset_AllMissing.bsv", line 8, column 8: (G004 During elaboration of `sysBoundary_Method_MultipleReset_AllMissing' at "Boundary_Method_MultipleReset_AllMissing.bsv", line 8, column 8. Verilog file created: sysBoundary_Method_MultipleReset_AllMissing.v +Elaborated module file created: sysBoundary_Method_MultipleReset_AllMissing.ba All packages are up to date. diff --git a/testsuite/bsc.mcd/Reset/Boundary_Method_MultipleReset_SomeMissing.bsv.bsc-vcomp-out.expected b/testsuite/bsc.mcd/Reset/Boundary_Method_MultipleReset_SomeMissing.bsv.bsc-vcomp-out.expected index 6be76912a..dd8a1dd09 100644 --- a/testsuite/bsc.mcd/Reset/Boundary_Method_MultipleReset_SomeMissing.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.mcd/Reset/Boundary_Method_MultipleReset_SomeMissing.bsv.bsc-vcomp-out.expected @@ -23,4 +23,5 @@ Warning: "Boundary_Method_MultipleReset_SomeMissing.bsv", line 8, column 8: (G01 During elaboration of `sysBoundary_Method_MultipleReset' at "Boundary_Method_MultipleReset_SomeMissing.bsv", line 8, column 8. Verilog file created: sysBoundary_Method_MultipleReset.v +Elaborated module file created: sysBoundary_Method_MultipleReset.ba All packages are up to date. diff --git a/testsuite/bsc.mcd/Reset/MultipleResetsForRule.bsv.bsc-vcomp-out.expected b/testsuite/bsc.mcd/Reset/MultipleResetsForRule.bsv.bsc-vcomp-out.expected index edb56f1fa..3bcd6c2c0 100644 --- a/testsuite/bsc.mcd/Reset/MultipleResetsForRule.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.mcd/Reset/MultipleResetsForRule.bsv.bsc-vcomp-out.expected @@ -15,4 +15,5 @@ Warning: "MultipleResetsForRule.bsv", line 27, column 9: (G0043) During elaboration of `sysMultipleResetsForRule' at "MultipleResetsForRule.bsv", line 19, column 8. Verilog file created: sysMultipleResetsForRule.v +Elaborated Verilog module file created: sysMultipleResetsForRule.ba All packages are up to date. diff --git a/testsuite/bsc.misc/lambda_calculus/DynamicInstArg.bsv.bsc-vcomp-out.expected b/testsuite/bsc.misc/lambda_calculus/DynamicInstArg.bsv.bsc-vcomp-out.expected index 593c03c94..2518270fb 100644 --- a/testsuite/bsc.misc/lambda_calculus/DynamicInstArg.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.misc/lambda_calculus/DynamicInstArg.bsv.bsc-vcomp-out.expected @@ -2,8 +2,10 @@ checking package dependencies compiling DynamicInstArg.bsv code generation for mkDynamicInstArg_Sub starts Verilog file created: mkDynamicInstArg_Sub.v +Elaborated module file created: mkDynamicInstArg_Sub.ba code generation for sysDynamicInstArg starts Warning: "DynamicInstArg.bsv", line 12, column 10: (S0015) The lambda-calculus dump does not support dynamic module arguments: b Verilog file created: sysDynamicInstArg.v +Elaborated module file created: sysDynamicInstArg.ba All packages are up to date. diff --git a/testsuite/bsc.misc/sal/DynamicInstArg.bsv.bsc-vcomp-out.expected b/testsuite/bsc.misc/sal/DynamicInstArg.bsv.bsc-vcomp-out.expected index e527935ae..468c2c8c0 100644 --- a/testsuite/bsc.misc/sal/DynamicInstArg.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.misc/sal/DynamicInstArg.bsv.bsc-vcomp-out.expected @@ -2,8 +2,10 @@ checking package dependencies compiling DynamicInstArg.bsv code generation for mkDynamicInstArg_Sub starts Verilog file created: mkDynamicInstArg_Sub.v +Elaborated module file created: mkDynamicInstArg_Sub.ba code generation for sysDynamicInstArg starts Warning: "DynamicInstArg.bsv", line 12, column 10: (S0015) The SAL dump does not support dynamic module arguments: b Verilog file created: sysDynamicInstArg.v +Elaborated module file created: sysDynamicInstArg.ba All packages are up to date. diff --git a/testsuite/bsc.names/signal_names/FFunc.bsv.bsc-vcomp-out.expected b/testsuite/bsc.names/signal_names/FFunc.bsv.bsc-vcomp-out.expected index e66fdaeb1..9793e33c5 100644 --- a/testsuite/bsc.names/signal_names/FFunc.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.names/signal_names/FFunc.bsv.bsc-vcomp-out.expected @@ -42,4 +42,5 @@ clock domain = Just (0), resets = [] ----- Verilog file created: sysFFunc.v +Elaborated module file created: sysFFunc.ba All packages are up to date. diff --git a/testsuite/bsc.names/signal_names/LiteralNum_ENotation.bsv.bsc-vcomp-out.expected b/testsuite/bsc.names/signal_names/LiteralNum_ENotation.bsv.bsc-vcomp-out.expected index 6913949ce..f30de1db9 100644 --- a/testsuite/bsc.names/signal_names/LiteralNum_ENotation.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.names/signal_names/LiteralNum_ENotation.bsv.bsc-vcomp-out.expected @@ -82,4 +82,5 @@ clock domain = Just (0), resets = [0] ----- Verilog file created: sysLiteralNum_ENotation.v +Elaborated module file created: sysLiteralNum_ENotation.ba All packages are up to date. diff --git a/testsuite/bsc.names/signal_names/Method.bsv.bsc-vcomp-out.expected b/testsuite/bsc.names/signal_names/Method.bsv.bsc-vcomp-out.expected index 4d9324a41..c44a5e4f1 100644 --- a/testsuite/bsc.names/signal_names/Method.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.names/signal_names/Method.bsv.bsc-vcomp-out.expected @@ -68,4 +68,5 @@ clock domain = Just (0), resets = [0] ----- Verilog file created: sysMethod.v +Elaborated module file created: sysMethod.ba All packages are up to date. diff --git a/testsuite/bsc.names/signal_names/MethodActionValue.bsv.bsc-vcomp-out.expected b/testsuite/bsc.names/signal_names/MethodActionValue.bsv.bsc-vcomp-out.expected index 4b22211c9..8438d2457 100644 --- a/testsuite/bsc.names/signal_names/MethodActionValue.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.names/signal_names/MethodActionValue.bsv.bsc-vcomp-out.expected @@ -51,6 +51,7 @@ method (RDY_m, [])RDY_m clocked_by (default_clock) reset_by (no_reset); ----- Verilog file created: mkMethodActionValue_Sub.v +Elaborated module file created: mkMethodActionValue_Sub.ba code generation for sysMethodActionValue starts === ATS (MethodActionValue sysMethodActionValue): APackage sysMethodActionValue @@ -109,4 +110,5 @@ clock domain = Just (0), resets = [] ----- Verilog file created: sysMethodActionValue.v +Elaborated module file created: sysMethodActionValue.ba All packages are up to date. diff --git a/testsuite/bsc.names/signal_names/MethodRead.bsv.bsc-vcomp-out.expected b/testsuite/bsc.names/signal_names/MethodRead.bsv.bsc-vcomp-out.expected index c6f2f84a8..602457569 100644 --- a/testsuite/bsc.names/signal_names/MethodRead.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.names/signal_names/MethodRead.bsv.bsc-vcomp-out.expected @@ -58,4 +58,5 @@ clock domain = Just (0), resets = [] ----- Verilog file created: sysMethodRead.v +Elaborated module file created: sysMethodRead.ba All packages are up to date. diff --git a/testsuite/bsc.names/signal_names/NoInline.bsv.bsc-vcomp-out.expected b/testsuite/bsc.names/signal_names/NoInline.bsv.bsc-vcomp-out.expected index d0c8e5f88..478faf721 100644 --- a/testsuite/bsc.names/signal_names/NoInline.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.names/signal_names/NoInline.bsv.bsc-vcomp-out.expected @@ -40,6 +40,7 @@ clock domain = Just (0), resets = [] ----- Verilog file created: sysNoInline.v +Elaborated module file created: sysNoInline.ba code generation for module_fnNoInline starts === ATS (NoInline module_fnNoInline): APackage module_fnNoInline -- function @@ -85,4 +86,5 @@ method (RDY_fnNoInline, [])RDY_fnNoInline clocked_by (no_clock) reset_by (no_res ----- Verilog file created: module_fnNoInline.v +Elaborated module file created: module_fnNoInline.ba All packages are up to date. diff --git a/testsuite/bsc.names/signal_names/TaskValue.bsv.bsc-vcomp-out.expected b/testsuite/bsc.names/signal_names/TaskValue.bsv.bsc-vcomp-out.expected index dc109698b..ffcea2959 100644 --- a/testsuite/bsc.names/signal_names/TaskValue.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.names/signal_names/TaskValue.bsv.bsc-vcomp-out.expected @@ -43,4 +43,5 @@ clock domain = Just (0), resets = [] ----- Verilog file created: sysTaskValue.v +Elaborated module file created: sysTaskValue.ba All packages are up to date. diff --git a/testsuite/bsc.options/bsc.help.out.expected b/testsuite/bsc.options/bsc.help.out.expected index ffdc4ae8f..38736d2e8 100644 --- a/testsuite/bsc.options/bsc.help.out.expected +++ b/testsuite/bsc.options/bsc.help.out.expected @@ -21,12 +21,13 @@ Compiler flags: -Xv arg pass argument to the Verilog link process -aggressive-conditions construct implicit conditions aggressively -bdir dir output directory for .bo and .ba files +-c module generate code for ``module'' from its elaborated .ba file -check-assert test assertions with the Assert library -continue-after-errors aggressively continue compilation after an error has been detected -cpp preprocess the source with the C preprocessor -demote-errors list treat a list of errors as warnings (``:'' sep list of tags) -e module top-level module for simulation --elab generate a .ba file after elaboration and scheduling +-elab generate a .ba file after elaboration and scheduling (on by default with -sim, -verilog and -systemc; -no-elab suppresses) -fdir dir working directory for relative file paths during elaboration -g module generate code for ``module'' (requires -sim or -verilog) -help generate help message diff --git a/testsuite/bsc.options/bsc.print-flags-raw.out.expected b/testsuite/bsc.options/bsc.print-flags-raw.out.expected index 22a18c388..6fd3e86c9 100644 --- a/testsuite/bsc.options/bsc.print-flags-raw.out.expected +++ b/testsuite/bsc.options/bsc.print-flags-raw.out.expected @@ -11,6 +11,7 @@ Flags { cLibPath = [], cLibs = [], cdir = Nothing, + codegenNames = [], cpp = False, cppFlags = [], cxxFlags = [], @@ -28,7 +29,6 @@ Flags { fdir = Nothing, finalcleanup = 1, genABin = False, - genABinVerilog = False, genName = [], genSysC = False, ifLift = True, diff --git a/testsuite/bsc.options/messages/PromoteTest3.bsv.bsc-vcomp-out.expected b/testsuite/bsc.options/messages/PromoteTest3.bsv.bsc-vcomp-out.expected index 9653ebc64..78d7965cd 100644 --- a/testsuite/bsc.options/messages/PromoteTest3.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.options/messages/PromoteTest3.bsv.bsc-vcomp-out.expected @@ -20,4 +20,5 @@ Warning: "PromoteTest3.bsv", line 15, column 8: (G0117) rg1.write To silence this warning, use the `-no-warn-action-shadowing' flag. Verilog file created: sysWarnings.v +Elaborated module file created: sysWarnings.ba All packages are up to date. diff --git a/testsuite/bsc.options/messages/PromoteTest4.bsv.bsc-vcomp-out.expected b/testsuite/bsc.options/messages/PromoteTest4.bsv.bsc-vcomp-out.expected index b5ff92748..577b67968 100644 --- a/testsuite/bsc.options/messages/PromoteTest4.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.options/messages/PromoteTest4.bsv.bsc-vcomp-out.expected @@ -20,4 +20,5 @@ Warning: "PromoteTest4.bsv", line 15, column 8: (G0117) rg1.write To silence this warning, use the `-no-warn-action-shadowing' flag. Verilog file created: sysWarnings.v +Elaborated module file created: sysWarnings.ba All packages are up to date. diff --git a/testsuite/bsc.options/messages/SuppressTest1.bsv.bsc-vcomp-out.expected b/testsuite/bsc.options/messages/SuppressTest1.bsv.bsc-vcomp-out.expected index fd0a71acd..1efce17e2 100644 --- a/testsuite/bsc.options/messages/SuppressTest1.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.options/messages/SuppressTest1.bsv.bsc-vcomp-out.expected @@ -11,6 +11,7 @@ Warning: "SuppressTest1.bsv", line 15, column 8: (G0117) rg1.write To silence this warning, use the `-no-warn-action-shadowing' flag. Verilog file created: sysWarnings.v +Elaborated module file created: sysWarnings.ba All packages are up to date. Warning: Unknown position: (S0080) 2 warnings were suppressed. diff --git a/testsuite/bsc.options/messages/SuppressTest1Lower.bsv.bsc-vcomp-out.expected b/testsuite/bsc.options/messages/SuppressTest1Lower.bsv.bsc-vcomp-out.expected index 372a89fc3..1c4beea4e 100644 --- a/testsuite/bsc.options/messages/SuppressTest1Lower.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.options/messages/SuppressTest1Lower.bsv.bsc-vcomp-out.expected @@ -11,6 +11,7 @@ Warning: "SuppressTest1Lower.bsv", line 15, column 8: (G0117) rg1.write To silence this warning, use the `-no-warn-action-shadowing' flag. Verilog file created: sysWarnings.v +Elaborated module file created: sysWarnings.ba All packages are up to date. Warning: Unknown position: (S0080) 2 warnings were suppressed. diff --git a/testsuite/bsc.options/messages/SuppressTest2.bsv.bsc-vcomp-out.expected b/testsuite/bsc.options/messages/SuppressTest2.bsv.bsc-vcomp-out.expected index f5d064b79..3a2029e7b 100644 --- a/testsuite/bsc.options/messages/SuppressTest2.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.options/messages/SuppressTest2.bsv.bsc-vcomp-out.expected @@ -11,4 +11,5 @@ Warning: "SuppressTest2.bsv", line 15, column 8: (G0117) rg1.write To silence this warning, use the `-no-warn-action-shadowing' flag. Verilog file created: sysWarnings.v +Elaborated module file created: sysWarnings.ba All packages are up to date. diff --git a/testsuite/bsc.options/messages/SuppressTest3.bsv.bsc-vcomp-out.expected b/testsuite/bsc.options/messages/SuppressTest3.bsv.bsc-vcomp-out.expected index d83a4a63e..bb0448388 100644 --- a/testsuite/bsc.options/messages/SuppressTest3.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.options/messages/SuppressTest3.bsv.bsc-vcomp-out.expected @@ -2,4 +2,5 @@ checking package dependencies compiling SuppressTest3.bsv code generation for sysWarnings starts Verilog file created: sysWarnings.v +Elaborated module file created: sysWarnings.ba All packages are up to date. diff --git a/testsuite/bsc.options/messages/SuppressTest4.bsv.bsc-vcomp-out.expected b/testsuite/bsc.options/messages/SuppressTest4.bsv.bsc-vcomp-out.expected index d3b4e984a..bf32a1a81 100644 --- a/testsuite/bsc.options/messages/SuppressTest4.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.options/messages/SuppressTest4.bsv.bsc-vcomp-out.expected @@ -11,4 +11,5 @@ Warning: "SuppressTest4.bsv", line 15, column 8: (G0117) rg1.write To silence this warning, use the `-no-warn-action-shadowing' flag. Verilog file created: sysWarnings.v +Elaborated module file created: sysWarnings.ba All packages are up to date. diff --git a/testsuite/bsc.options/messages/Warnings.bsv.bsc-vcomp-out.expected b/testsuite/bsc.options/messages/Warnings.bsv.bsc-vcomp-out.expected index 1edd57c88..b853ecceb 100644 --- a/testsuite/bsc.options/messages/Warnings.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.options/messages/Warnings.bsv.bsc-vcomp-out.expected @@ -20,4 +20,5 @@ Warning: "Warnings.bsv", line 15, column 8: (G0117) rg1.write To silence this warning, use the `-no-warn-action-shadowing' flag. Verilog file created: sysWarnings.v +Elaborated module file created: sysWarnings.ba All packages are up to date. diff --git a/testsuite/bsc.preprocessor/include/IncludeAbsolute.bsv.bsc-vcomp-out.expected.pre-m4 b/testsuite/bsc.preprocessor/include/IncludeAbsolute.bsv.bsc-vcomp-out.expected.pre-m4 index d76fd24cf..0761a128d 100644 --- a/testsuite/bsc.preprocessor/include/IncludeAbsolute.bsv.bsc-vcomp-out.expected.pre-m4 +++ b/testsuite/bsc.preprocessor/include/IncludeAbsolute.bsv.bsc-vcomp-out.expected.pre-m4 @@ -3,4 +3,5 @@ compiling IncludeAbsolute.bsv code generation for sysIncludeAbsolute starts Compilation message: "CURDIR/subdir/defines2", line 1, column 11: subdir/defines2 Verilog file created: sysIncludeAbsolute.v +Elaborated module file created: sysIncludeAbsolute.ba All packages are up to date. diff --git a/testsuite/bsc.preprocessor/include/IncludeNoPath.bsv.bsc-vcomp-out.expected b/testsuite/bsc.preprocessor/include/IncludeNoPath.bsv.bsc-vcomp-out.expected index f902f7ed1..1b146cbb8 100644 --- a/testsuite/bsc.preprocessor/include/IncludeNoPath.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.preprocessor/include/IncludeNoPath.bsv.bsc-vcomp-out.expected @@ -3,4 +3,5 @@ compiling IncludeNoPath.bsv code generation for sysIncludeNoPath starts Compilation message: "./defines1", line 1, column 11: defines1 Verilog file created: sysIncludeNoPath.v +Elaborated module file created: sysIncludeNoPath.ba All packages are up to date. diff --git a/testsuite/bsc.preprocessor/include/IncludeSubdir.bsv.bsc-vcomp-out.expected b/testsuite/bsc.preprocessor/include/IncludeSubdir.bsv.bsc-vcomp-out.expected index 1af2b691e..9497753e9 100644 --- a/testsuite/bsc.preprocessor/include/IncludeSubdir.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.preprocessor/include/IncludeSubdir.bsv.bsc-vcomp-out.expected @@ -3,4 +3,5 @@ compiling IncludeSubdir.bsv code generation for sysIncludeSubdir starts Compilation message: "./subdir/defines2", line 1, column 11: subdir/defines2 Verilog file created: sysIncludeSubdir.v +Elaborated module file created: sysIncludeSubdir.ba All packages are up to date. diff --git a/testsuite/bsc.real/evaluator/AddSubInf.bsv.bsc-vcomp-out.expected b/testsuite/bsc.real/evaluator/AddSubInf.bsv.bsc-vcomp-out.expected index b62db187e..30d15aaf9 100644 --- a/testsuite/bsc.real/evaluator/AddSubInf.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.real/evaluator/AddSubInf.bsv.bsc-vcomp-out.expected @@ -6,4 +6,5 @@ Compilation message: "AddSubInf.bsv", line 17, column 28: -INF + -INF = -Infinit Compilation message: "AddSubInf.bsv", line 18, column 28: +INF - -INF = Infinity Compilation message: "AddSubInf.bsv", line 19, column 28: -INF - +INF = -Infinity Verilog file created: sysAddSubInf.v +Elaborated module file created: sysAddSubInf.ba All packages are up to date. diff --git a/testsuite/bsc.real/evaluator/Arith.bsv.bsc-vcomp-out.expected b/testsuite/bsc.real/evaluator/Arith.bsv.bsc-vcomp-out.expected index d91dae1f0..7ce015e71 100644 --- a/testsuite/bsc.real/evaluator/Arith.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.real/evaluator/Arith.bsv.bsc-vcomp-out.expected @@ -9,4 +9,5 @@ Compilation message: "Arith.bsv", line 19, column 24: 5.0 / 2 = 2.5 Compilation message: "Arith.bsv", line 20, column 25: abs -1.1 = 1.1 Compilation message: "Arith.bsv", line 21, column 28: signum -1.1 = -1.0 Verilog file created: sysArith.v +Elaborated module file created: sysArith.ba All packages are up to date. diff --git a/testsuite/bsc.real/evaluator/Bits.bsv.bsc-vcomp-out.expected b/testsuite/bsc.real/evaluator/Bits.bsv.bsc-vcomp-out.expected index 81e687b14..25ca25bec 100644 --- a/testsuite/bsc.real/evaluator/Bits.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.real/evaluator/Bits.bsv.bsc-vcomp-out.expected @@ -16,4 +16,5 @@ Compilation message: "Bits.bsv", line 100, column 19: r6 = -0.0 Compilation message: "Bits.bsv", line 101, column 19: r7 = 8.344026969402005e-309 Compilation message: "Bits.bsv", line 102, column 19: r8 = -4.172013484701003e-309 Verilog file created: sysBits.v +Elaborated module file created: sysBits.ba All packages are up to date. diff --git a/testsuite/bsc.real/evaluator/Constants.bsv.bsc-vcomp-out.expected b/testsuite/bsc.real/evaluator/Constants.bsv.bsc-vcomp-out.expected index 97b72fad4..a7427bf02 100644 --- a/testsuite/bsc.real/evaluator/Constants.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.real/evaluator/Constants.bsv.bsc-vcomp-out.expected @@ -3,4 +3,5 @@ compiling Constants.bsv code generation for sysConstants starts Compilation message: "Constants.bsv", line 11, column 19: pi = 3.141592653589793 Verilog file created: sysConstants.v +Elaborated module file created: sysConstants.ba All packages are up to date. diff --git a/testsuite/bsc.real/evaluator/Exps.bsv.bsc-vcomp-out.expected b/testsuite/bsc.real/evaluator/Exps.bsv.bsc-vcomp-out.expected index 661a52094..26e1ca7a3 100644 --- a/testsuite/bsc.real/evaluator/Exps.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.real/evaluator/Exps.bsv.bsc-vcomp-out.expected @@ -6,4 +6,5 @@ Compilation message: "Exps.bsv", line 12, column 25: pow(2,7) = 128.0 Compilation message: "Exps.bsv", line 13, column 25: pow(3,2) = 9.0 Compilation message: "Exps.bsv", line 14, column 26: pow(10,2) = 100.0 Verilog file created: sysExps.v +Elaborated module file created: sysExps.ba All packages are up to date. diff --git a/testsuite/bsc.real/evaluator/Introspect.bsv.bsc-vcomp-out.expected b/testsuite/bsc.real/evaluator/Introspect.bsv.bsc-vcomp-out.expected index 0ecbf847a..c484b9aad 100644 --- a/testsuite/bsc.real/evaluator/Introspect.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.real/evaluator/Introspect.bsv.bsc-vcomp-out.expected @@ -48,4 +48,5 @@ Compilation message: "Introspect.bsv", line 21, column 39: 6 Compilation message: "Introspect.bsv", line 21, column 39: 7 Compilation message: "Introspect.bsv", line 57, column 27: -y exponent: 12 Verilog file created: sysIntrospect.v +Elaborated module file created: sysIntrospect.ba All packages are up to date. diff --git a/testsuite/bsc.real/evaluator/IntrospectInfinite.bsv.bsc-vcomp-out.expected b/testsuite/bsc.real/evaluator/IntrospectInfinite.bsv.bsc-vcomp-out.expected index c44d60c6e..b0b1e5747 100644 --- a/testsuite/bsc.real/evaluator/IntrospectInfinite.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.real/evaluator/IntrospectInfinite.bsv.bsc-vcomp-out.expected @@ -44,4 +44,5 @@ Compilation message: "IntrospectInfinite.bsv", line 20, column 39: 1 Compilation message: "IntrospectInfinite.bsv", line 20, column 39: 6 Compilation message: "IntrospectInfinite.bsv", line 46, column 30: -INF exponent = 309 Verilog file created: sysIntrospectInfinite.v +Elaborated module file created: sysIntrospectInfinite.ba All packages are up to date. diff --git a/testsuite/bsc.real/evaluator/IsInfinite.bsv.bsc-vcomp-out.expected b/testsuite/bsc.real/evaluator/IsInfinite.bsv.bsc-vcomp-out.expected index 26c05b667..47090d462 100644 --- a/testsuite/bsc.real/evaluator/IsInfinite.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.real/evaluator/IsInfinite.bsv.bsc-vcomp-out.expected @@ -3,4 +3,5 @@ compiling IsInfinite.bsv code generation for sysIsInfinite starts Compilation message: "IsInfinite.bsv", line 12, column 29: isInfinite: Infinity Verilog file created: sysIsInfinite.v +Elaborated module file created: sysIsInfinite.ba All packages are up to date. diff --git a/testsuite/bsc.real/evaluator/IsNegativeZero.bsv.bsc-vcomp-out.expected b/testsuite/bsc.real/evaluator/IsNegativeZero.bsv.bsc-vcomp-out.expected index 7a8f9eb3e..5fc57b85e 100644 --- a/testsuite/bsc.real/evaluator/IsNegativeZero.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.real/evaluator/IsNegativeZero.bsv.bsc-vcomp-out.expected @@ -4,4 +4,5 @@ code generation for sysIsNegativeZero starts Compilation message: "IsNegativeZero.bsv", line 13, column 23: -0.0: -0.0 Compilation message: "IsNegativeZero.bsv", line 19, column 22: 0.0: 0.0 Verilog file created: sysIsNegativeZero.v +Elaborated module file created: sysIsNegativeZero.ba All packages are up to date. diff --git a/testsuite/bsc.real/evaluator/LiteralEqOrd.bsv.bsc-vcomp-out.expected b/testsuite/bsc.real/evaluator/LiteralEqOrd.bsv.bsc-vcomp-out.expected index c233424eb..5a91fd14c 100644 --- a/testsuite/bsc.real/evaluator/LiteralEqOrd.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.real/evaluator/LiteralEqOrd.bsv.bsc-vcomp-out.expected @@ -6,4 +6,5 @@ Compilation message: "LiteralEqOrd.bsv", line 20, column 11: w > x Compilation message: "LiteralEqOrd.bsv", line 23, column 11: w <= z Compilation message: "LiteralEqOrd.bsv", line 30, column 11: w > v Verilog file created: sysLiteralEqOrd.v +Elaborated module file created: sysLiteralEqOrd.ba All packages are up to date. diff --git a/testsuite/bsc.real/evaluator/Logs.bsv.bsc-vcomp-out.expected b/testsuite/bsc.real/evaluator/Logs.bsv.bsc-vcomp-out.expected index 527342093..7d6e37d44 100644 --- a/testsuite/bsc.real/evaluator/Logs.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.real/evaluator/Logs.bsv.bsc-vcomp-out.expected @@ -8,4 +8,5 @@ Compilation message: "Logs.bsv", line 16, column 22: 100.0 = 100.0 Compilation message: "Logs.bsv", line 17, column 29: log10(100.0) = 2.0 Compilation message: "Logs.bsv", line 18, column 28: logb(3,9.0) = 2.0 Verilog file created: sysLogs.v +Elaborated module file created: sysLogs.ba All packages are up to date. diff --git a/testsuite/bsc.real/evaluator/RoundInfinite.bsv.bsc-vcomp-out.expected b/testsuite/bsc.real/evaluator/RoundInfinite.bsv.bsc-vcomp-out.expected index 07ca317d9..3e7aa7452 100644 --- a/testsuite/bsc.real/evaluator/RoundInfinite.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.real/evaluator/RoundInfinite.bsv.bsc-vcomp-out.expected @@ -6,4 +6,5 @@ Compilation message: "RoundInfinite.bsv", line 16, column 18: x = 17976931348623 Compilation message: "RoundInfinite.bsv", line 17, column 18: y = 179769313486231590772930519078902473361797697894230657273430081157732675805500963132708477322407536021120113879871393357658789768814416622492847430639474124377767893424865485276302219601246094119453082952085005768838150682342462881473913110540827237163350510684586298239947245938479716304835356329624224137216 Compilation message: "RoundInfinite.bsv", line 18, column 18: z = 179769313486231590772930519078902473361797697894230657273430081157732675805500963132708477322407536021120113879871393357658789768814416622492847430639474124377767893424865485276302219601246094119453082952085005768838150682342462881473913110540827237163350510684586298239947245938479716304835356329624224137216 Verilog file created: sysRoundInfinite.v +Elaborated module file created: sysRoundInfinite.ba All packages are up to date. diff --git a/testsuite/bsc.real/evaluator/Rounds.bsv.bsc-vcomp-out.expected b/testsuite/bsc.real/evaluator/Rounds.bsv.bsc-vcomp-out.expected index 894ca9e18..99ff3491c 100644 --- a/testsuite/bsc.real/evaluator/Rounds.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.real/evaluator/Rounds.bsv.bsc-vcomp-out.expected @@ -26,4 +26,5 @@ Compilation message: "Rounds.bsv", line 73, column 27: ceil -1.7 = -1 Compilation message: "Rounds.bsv", line 74, column 27: floor -1.7 = -2 Compilation message: "Rounds.bsv", line 75, column 27: trunc -1.7 = -1 Verilog file created: sysRounds.v +Elaborated module file created: sysRounds.ba All packages are up to date. diff --git a/testsuite/bsc.real/evaluator/Sqrt.bsv.bsc-vcomp-out.expected b/testsuite/bsc.real/evaluator/Sqrt.bsv.bsc-vcomp-out.expected index 4ab6ba4f7..9b20d9b96 100644 --- a/testsuite/bsc.real/evaluator/Sqrt.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.real/evaluator/Sqrt.bsv.bsc-vcomp-out.expected @@ -5,4 +5,5 @@ Compilation message: "Sqrt.bsv", line 12, column 26: sqrt(0.0) = 0.0 Compilation message: "Sqrt.bsv", line 13, column 26: sqrt(4.0) = 2.0 Compilation message: "Sqrt.bsv", line 14, column 27: sqrt(10.0) = 3.1622776601683795 Verilog file created: sysSqrt.v +Elaborated module file created: sysSqrt.ba All packages are up to date. diff --git a/testsuite/bsc.real/evaluator/Zero.bsv.bsc-vcomp-out.expected b/testsuite/bsc.real/evaluator/Zero.bsv.bsc-vcomp-out.expected index 4d696b369..f4de8828b 100644 --- a/testsuite/bsc.real/evaluator/Zero.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.real/evaluator/Zero.bsv.bsc-vcomp-out.expected @@ -4,4 +4,5 @@ code generation for sysZero starts Compilation message: "Zero.bsv", line 12, column 32: 0.0 = (+, 0, 0) Compilation message: "Zero.bsv", line 18, column 32: -0.0 = (-, 0, 0) Verilog file created: sysZero.v +Elaborated module file created: sysZero.ba All packages are up to date. diff --git a/testsuite/bsc.real/parser/Classic.bs.bsc-vcomp-out.expected b/testsuite/bsc.real/parser/Classic.bs.bsc-vcomp-out.expected index 1aa63b66e..11c78a30e 100644 --- a/testsuite/bsc.real/parser/Classic.bs.bsc-vcomp-out.expected +++ b/testsuite/bsc.real/parser/Classic.bs.bsc-vcomp-out.expected @@ -6,4 +6,5 @@ Compilation message: "Classic.bs", line 19, column 38: 3e10 = 3.0e10 Compilation message: "Classic.bs", line 20, column 38: 2e-1 = 0.2 Compilation message: "Classic.bs", line 21, column 40: 2.5e+0 = 2.5 Verilog file created: sysClassic.v +Elaborated module file created: sysClassic.ba All packages are up to date. diff --git a/testsuite/bsc.real/parser/FractionalLeadingZeros.bsv.bsc-vcomp-out.expected b/testsuite/bsc.real/parser/FractionalLeadingZeros.bsv.bsc-vcomp-out.expected index 4a14dc85d..51ee3e3b2 100644 --- a/testsuite/bsc.real/parser/FractionalLeadingZeros.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.real/parser/FractionalLeadingZeros.bsv.bsc-vcomp-out.expected @@ -5,4 +5,5 @@ Compilation message: "FractionalLeadingZeros.bsv", line 10, column 21: 1.02 = 1. Compilation message: "FractionalLeadingZeros.bsv", line 11, column 22: 1.002 = 1.002 Compilation message: "FractionalLeadingZeros.bsv", line 12, column 30: 1.00000000002 = 1.00000000002 Verilog file created: sysFractionalLeadingZeros.v +Elaborated module file created: sysFractionalLeadingZeros.ba All packages are up to date. diff --git a/testsuite/bsc.real/parser/LargeReal.bsv.bsc-vcomp-out.expected b/testsuite/bsc.real/parser/LargeReal.bsv.bsc-vcomp-out.expected index 5ad984346..9c1f62f95 100644 --- a/testsuite/bsc.real/parser/LargeReal.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.real/parser/LargeReal.bsv.bsc-vcomp-out.expected @@ -6,4 +6,5 @@ Compilation message: "LargeReal.bsv", line 16, column 21: zero = 0.0 Compilation message: "LargeReal.bsv", line 17, column 21: inf2 = Infinity Compilation message: "LargeReal.bsv", line 18, column 22: zero2 = 0.0 Verilog file created: sysLargeReal.v +Elaborated module file created: sysLargeReal.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/AccessorConflicts.bs.bsc-sched-out.expected b/testsuite/bsc.scheduler/AccessorConflicts.bs.bsc-sched-out.expected index 2658e2c88..b21b31196 100644 --- a/testsuite/bsc.scheduler/AccessorConflicts.bs.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/AccessorConflicts.bs.bsc-sched-out.expected @@ -36,4 +36,5 @@ Logical execution order: g, s ==================================================== Verilog file created: sysAccessorConflicts.v +Elaborated module file created: sysAccessorConflicts.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/AccessorPredicates.bs.bsc-sched-out.expected b/testsuite/bsc.scheduler/AccessorPredicates.bs.bsc-sched-out.expected index f788195ed..ca3122349 100644 --- a/testsuite/bsc.scheduler/AccessorPredicates.bs.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/AccessorPredicates.bs.bsc-sched-out.expected @@ -35,4 +35,5 @@ Logical execution order: s, g ===================================================== Verilog file created: sysAccessorPredicates.v +Elaborated module file created: sysAccessorPredicates.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/BlockerEsposito.bs.bsc-sched-out.expected b/testsuite/bsc.scheduler/BlockerEsposito.bs.bsc-sched-out.expected index 19da2bc43..079f6776a 100644 --- a/testsuite/bsc.scheduler/BlockerEsposito.bs.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/BlockerEsposito.bs.bsc-sched-out.expected @@ -51,4 +51,5 @@ Warning: "BlockerEsposito.bs", line 19, column 21: (G0021) Warning: "BlockerEsposito.bs", line 20, column 21: (G0021) According to the generated schedule, rule `B' can never fire. Verilog file created: sysBlockerEsposito.v +Elaborated module file created: sysBlockerEsposito.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/BlockersEsposito.bs.bsc-sched-out.expected b/testsuite/bsc.scheduler/BlockersEsposito.bs.bsc-sched-out.expected index e99499af3..35b3dc3e8 100644 --- a/testsuite/bsc.scheduler/BlockersEsposito.bs.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/BlockersEsposito.bs.bsc-sched-out.expected @@ -139,4 +139,5 @@ Warning: "BlockersEsposito.bs", line 23, column 19: (G0021) Warning: "BlockersEsposito.bs", line 23, column 19: (G0021) According to the generated schedule, rule `Victim_6' can never fire. Verilog file created: sysBlockersEsposito.v +Elaborated module file created: sysBlockersEsposito.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/IgnoreRdy.bs.bsc-sched-out.expected b/testsuite/bsc.scheduler/IgnoreRdy.bs.bsc-sched-out.expected index 33e956cdf..7f265f472 100644 --- a/testsuite/bsc.scheduler/IgnoreRdy.bs.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/IgnoreRdy.bs.bsc-sched-out.expected @@ -47,6 +47,7 @@ Logical execution order: bar, glurph ===================================== Verilog file created: mkBar.v +Elaborated module file created: mkBar.ba code generation for sysIgnoreRdy starts === schedule (IgnoreRdy sysIgnoreRdy): parallel: [esposito: [foo -> [], RL_do_glurph -> []]] @@ -86,4 +87,5 @@ Logical execution order: foo, do_glurph ============================================ Verilog file created: sysIgnoreRdy.v +Elaborated module file created: sysIgnoreRdy.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/InterfaceOrderingParallel.bs.bsc-sched-out.expected b/testsuite/bsc.scheduler/InterfaceOrderingParallel.bs.bsc-sched-out.expected index 3a328ba47..7ad73ddb8 100644 --- a/testsuite/bsc.scheduler/InterfaceOrderingParallel.bs.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/InterfaceOrderingParallel.bs.bsc-sched-out.expected @@ -36,4 +36,5 @@ Logical execution order: act, write ============================================================ Verilog file created: sysInterfaceOrderingParallel.v +Elaborated module file created: sysInterfaceOrderingParallel.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/InterfaceOrderingResource.bs.bsc-sched-out.expected b/testsuite/bsc.scheduler/InterfaceOrderingResource.bs.bsc-sched-out.expected index 18977e082..9353ac2f0 100644 --- a/testsuite/bsc.scheduler/InterfaceOrderingResource.bs.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/InterfaceOrderingResource.bs.bsc-sched-out.expected @@ -40,4 +40,5 @@ Logical execution order: act, write ============================================================ Verilog file created: sysInterfaceOrderingResource.v +Elaborated module file created: sysInterfaceOrderingResource.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/InterfaceOrderingSequential.bs.bsc-sched-out.expected b/testsuite/bsc.scheduler/InterfaceOrderingSequential.bs.bsc-sched-out.expected index 1d8575f61..c4e804810 100644 --- a/testsuite/bsc.scheduler/InterfaceOrderingSequential.bs.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/InterfaceOrderingSequential.bs.bsc-sched-out.expected @@ -36,4 +36,5 @@ Logical execution order: write, act ============================================================== Verilog file created: sysInterfaceOrderingSequential.v +Elaborated module file created: sysInterfaceOrderingSequential.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/PredicateConflicts.bs.bsc-sched-out.expected b/testsuite/bsc.scheduler/PredicateConflicts.bs.bsc-sched-out.expected index 7ea9fcb1e..247b87cc1 100644 --- a/testsuite/bsc.scheduler/PredicateConflicts.bs.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/PredicateConflicts.bs.bsc-sched-out.expected @@ -41,4 +41,5 @@ Logical execution order: foo, bar ===================================================== Verilog file created: sysPredicateConflicts.v +Elaborated module file created: sysPredicateConflicts.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/Ring.bs.bsc-sched-out.expected b/testsuite/bsc.scheduler/Ring.bs.bsc-sched-out.expected index b97a36ea5..e0bb1a6e4 100644 --- a/testsuite/bsc.scheduler/Ring.bs.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/Ring.bs.bsc-sched-out.expected @@ -55,4 +55,5 @@ Logical execution order: r1gets3, r3gets2, r2gets1 Warning: "Ring.bs", line 22, column 12: (G0021) According to the generated schedule, rule `r1gets3' can never fire. Verilog file created: sysRing.v +Elaborated module file created: sysRing.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/RuleAssertionsEspositoFail.bs.bsc-sched-out.expected b/testsuite/bsc.scheduler/RuleAssertionsEspositoFail.bs.bsc-sched-out.expected index 430ea5619..5127763d4 100644 --- a/testsuite/bsc.scheduler/RuleAssertionsEspositoFail.bs.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/RuleAssertionsEspositoFail.bs.bsc-sched-out.expected @@ -35,3 +35,4 @@ Blocking rules: setF, setT Logical execution order: setT, setF, flip ============================================================= +Elaborated error module file created: sysRuleAssertionsEspositoFail.ba diff --git a/testsuite/bsc.scheduler/RuleAssertionsEspositoOK.bs.bsc-sched-out.expected b/testsuite/bsc.scheduler/RuleAssertionsEspositoOK.bs.bsc-sched-out.expected index b93c85f40..a62b001da 100644 --- a/testsuite/bsc.scheduler/RuleAssertionsEspositoOK.bs.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/RuleAssertionsEspositoOK.bs.bsc-sched-out.expected @@ -42,4 +42,5 @@ Warning: "RuleAssertionsEspositoOK.bs", line 17, column 15: (G0021) Warning: "RuleAssertionsEspositoOK.bs", line 20, column 15: (G0021) According to the generated schedule, rule `flip' can never fire. Verilog file created: sysRuleAssertionsEspositoOK.v +Elaborated module file created: sysRuleAssertionsEspositoOK.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/RuleMethodConflict.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/RuleMethodConflict.bsv.bsc-sched-out.expected index ec43e118d..c578580c7 100644 --- a/testsuite/bsc.scheduler/RuleMethodConflict.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/RuleMethodConflict.bsv.bsc-sched-out.expected @@ -49,4 +49,5 @@ Logical execution order: get, put Warning: "RuleMethodConflict.bsv", line 44, column 8: (G0021) According to the generated schedule, rule `put' can never fire. Verilog file created: sysRuleMethodConflict.v +Elaborated module file created: sysRuleMethodConflict.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/SplitIf.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/SplitIf.bsv.bsc-sched-out.expected index 08348949d..5dbe30483 100644 --- a/testsuite/bsc.scheduler/SplitIf.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/SplitIf.bsv.bsc-sched-out.expected @@ -57,6 +57,7 @@ Logical execution order: toggle2, xfer_T, xfer_F, toggle1 ============================================== Verilog file created: mkSplitIf_Test.v +Elaborated module file created: mkSplitIf_Test.ba code generation for sysSplitIf starts === schedule (SplitIf sysSplitIf): parallel: [esposito: [RL_toggleDir -> [], RL_r -> [], RL_incr -> [], RL_done -> []]] @@ -104,4 +105,5 @@ Logical execution order: r, toggleDir, done, incr ========================================== Verilog file created: sysSplitIf.v +Elaborated module file created: sysSplitIf.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/SplitIf2.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/SplitIf2.bsv.bsc-sched-out.expected index 51f702f9d..356ef3653 100644 --- a/testsuite/bsc.scheduler/SplitIf2.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/SplitIf2.bsv.bsc-sched-out.expected @@ -62,6 +62,7 @@ Logical execution order: toggle1, toggle2, xfer Warning: "SplitIf2.bsv", line 6, column 8: (G0022) According to the generated schedule, method `xfer' is never ready. Verilog file created: mkSplitIf2_Test.v +Elaborated module file created: mkSplitIf2_Test.ba code generation for sysSplitIf2 starts === schedule (SplitIf2 sysSplitIf2): parallel: [esposito: [RL_toggleDir -> [], RL_r -> [], RL_incr -> [], RL_done -> []]] @@ -109,4 +110,5 @@ Logical execution order: r, toggleDir, done, incr =========================================== Verilog file created: sysSplitIf2.v +Elaborated module file created: sysSplitIf2.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/SplitIfMeth.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/SplitIfMeth.bsv.bsc-sched-out.expected index 10afe74c4..0a661ffcc 100644 --- a/testsuite/bsc.scheduler/SplitIfMeth.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/SplitIfMeth.bsv.bsc-sched-out.expected @@ -45,4 +45,5 @@ Logical execution order: a1_T, a2, a1_F ============================================= Verilog file created: mkSplitIfMeth.v +Elaborated module file created: mkSplitIfMeth.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/ThreeRulesEsposito.bs.bsc-sched-out.expected b/testsuite/bsc.scheduler/ThreeRulesEsposito.bs.bsc-sched-out.expected index 9444d76cb..628ff54eb 100644 --- a/testsuite/bsc.scheduler/ThreeRulesEsposito.bs.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/ThreeRulesEsposito.bs.bsc-sched-out.expected @@ -42,4 +42,5 @@ Warning: "ThreeRulesEsposito.bs", line 18, column 15: (G0021) Warning: "ThreeRulesEsposito.bs", line 21, column 15: (G0021) According to the generated schedule, rule `flip' can never fire. Verilog file created: sysThreeRulesEsposito.v +Elaborated module file created: sysThreeRulesEsposito.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/TooManyBlockersEsposito.bs.bsc-sched-out.expected b/testsuite/bsc.scheduler/TooManyBlockersEsposito.bs.bsc-sched-out.expected index 044a5acbf..71f6d483e 100644 --- a/testsuite/bsc.scheduler/TooManyBlockersEsposito.bs.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/TooManyBlockersEsposito.bs.bsc-sched-out.expected @@ -283,4 +283,5 @@ Warning: "TooManyBlockersEsposito.bs", line 25, column 19: (G0021) Warning: "TooManyBlockersEsposito.bs", line 25, column 19: (G0021) According to the generated schedule, rule `Victim_15' can never fire. Verilog file created: sysTooManyBlockersEsposito.v +Elaborated module file created: sysTooManyBlockersEsposito.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/attribute_scope/InlinedMethodName.bsv.bsc-vcomp-out.expected b/testsuite/bsc.scheduler/attribute_scope/InlinedMethodName.bsv.bsc-vcomp-out.expected index 49418585d..c1553412d 100644 --- a/testsuite/bsc.scheduler/attribute_scope/InlinedMethodName.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.scheduler/attribute_scope/InlinedMethodName.bsv.bsc-vcomp-out.expected @@ -24,4 +24,5 @@ Warning: "InlinedMethodName.bsv", line 14, column 8: (G0010) Warning: "InlinedMethodName.bsv", line 32, column 9: (G0021) According to the generated schedule, rule `m_r' can never fire. Verilog file created: sysTopMethodNameTopModule1.v +Elaborated module file created: sysTopMethodNameTopModule1.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/attribute_scope/RuleHierarchyNonAlphanum2.bsv.bsc-vcomp-out.expected b/testsuite/bsc.scheduler/attribute_scope/RuleHierarchyNonAlphanum2.bsv.bsc-vcomp-out.expected index b11643e0f..f9146fbd2 100644 --- a/testsuite/bsc.scheduler/attribute_scope/RuleHierarchyNonAlphanum2.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.scheduler/attribute_scope/RuleHierarchyNonAlphanum2.bsv.bsc-vcomp-out.expected @@ -4,4 +4,5 @@ code generation for sysRuleHierarchyNonAlphanum2 starts Warning: "RuleHierarchyNonAlphanum2.bsv", line 14, column 9: (G0021) According to the generated schedule, rule `r2' can never fire. Verilog file created: sysRuleHierarchyNonAlphanum2.v +Elaborated module file created: sysRuleHierarchyNonAlphanum2.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/attribute_scope/RuleMethClash.bsv.bsc-vcomp-out.expected b/testsuite/bsc.scheduler/attribute_scope/RuleMethClash.bsv.bsc-vcomp-out.expected index e317529f5..fb85b1b79 100644 --- a/testsuite/bsc.scheduler/attribute_scope/RuleMethClash.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.scheduler/attribute_scope/RuleMethClash.bsv.bsc-vcomp-out.expected @@ -6,4 +6,5 @@ Warning: "RuleMethClash.bsv", line 6, column 8: (G0010) "incr" cannot fire before "incr": calls to rg.write vs. rg.read "incr" cannot fire before "incr": calls to rg.write vs. rg.read Verilog file created: sysRuleMethClash.v +Elaborated module file created: sysRuleMethClash.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/attribute_scope/RuleNameAcrossSubModule1.bsv.bsc-vcomp-out.expected b/testsuite/bsc.scheduler/attribute_scope/RuleNameAcrossSubModule1.bsv.bsc-vcomp-out.expected index 16e5ed115..23cddcee3 100644 --- a/testsuite/bsc.scheduler/attribute_scope/RuleNameAcrossSubModule1.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.scheduler/attribute_scope/RuleNameAcrossSubModule1.bsv.bsc-vcomp-out.expected @@ -4,4 +4,5 @@ code generation for sysRuleNameAcrossSubModule1 starts Warning: "RuleNameAcrossSubModule1.bsv", line 18, column 9: (G0021) According to the generated schedule, rule `s_r2' can never fire. Verilog file created: sysRuleNameAcrossSubModule1.v +Elaborated module file created: sysRuleNameAcrossSubModule1.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/attribute_scope/RuleNameAcrossSubModule2.bsv.bsc-vcomp-out.expected b/testsuite/bsc.scheduler/attribute_scope/RuleNameAcrossSubModule2.bsv.bsc-vcomp-out.expected index 5e1786e7c..6879fb94b 100644 --- a/testsuite/bsc.scheduler/attribute_scope/RuleNameAcrossSubModule2.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.scheduler/attribute_scope/RuleNameAcrossSubModule2.bsv.bsc-vcomp-out.expected @@ -4,4 +4,5 @@ code generation for sysRuleNameAcrossSubModule2 starts Warning: "RuleNameAcrossSubModule2.bsv", line 26, column 9: (G0021) According to the generated schedule, rule `m_b_r2' can never fire. Verilog file created: sysRuleNameAcrossSubModule2.v +Elaborated module file created: sysRuleNameAcrossSubModule2.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/attribute_scope/RuleNameAcrossTopModule.bsv.bsc-vcomp-out.expected b/testsuite/bsc.scheduler/attribute_scope/RuleNameAcrossTopModule.bsv.bsc-vcomp-out.expected index f554bd541..97ab899fb 100644 --- a/testsuite/bsc.scheduler/attribute_scope/RuleNameAcrossTopModule.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.scheduler/attribute_scope/RuleNameAcrossTopModule.bsv.bsc-vcomp-out.expected @@ -4,4 +4,5 @@ code generation for sysRuleNameAcrossTopModule starts Warning: "RuleNameAcrossTopModule.bsv", line 14, column 9: (G0021) According to the generated schedule, rule `r2' can never fire. Verilog file created: sysRuleNameAcrossTopModule.v +Elaborated module file created: sysRuleNameAcrossTopModule.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/attribute_scope/RuleNameInAddRules1.bsv.bsc-vcomp-out.expected b/testsuite/bsc.scheduler/attribute_scope/RuleNameInAddRules1.bsv.bsc-vcomp-out.expected index cc5cecc7e..ae9827ade 100644 --- a/testsuite/bsc.scheduler/attribute_scope/RuleNameInAddRules1.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.scheduler/attribute_scope/RuleNameInAddRules1.bsv.bsc-vcomp-out.expected @@ -4,4 +4,5 @@ code generation for sysRuleNameInAddRules1 starts Warning: "RuleNameInAddRules1.bsv", line 12, column 15: (G0021) According to the generated schedule, rule `r2' can never fire. Verilog file created: sysRuleNameInAddRules1.v +Elaborated module file created: sysRuleNameInAddRules1.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/attribute_scope/RuleNameInAddRulesClash.bsv.bsc-vcomp-out.expected b/testsuite/bsc.scheduler/attribute_scope/RuleNameInAddRulesClash.bsv.bsc-vcomp-out.expected index e484b99cf..ec3209fd2 100644 --- a/testsuite/bsc.scheduler/attribute_scope/RuleNameInAddRulesClash.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.scheduler/attribute_scope/RuleNameInAddRulesClash.bsv.bsc-vcomp-out.expected @@ -8,4 +8,5 @@ Warning: "RuleNameInAddRulesClash.bsv", line 2, column 8: (G0010) Warning: "RuleNameInAddRulesClash.bsv", line 17, column 15: (G0021) According to the generated schedule, rule `a_r2' can never fire. Verilog file created: sysRuleNameInAddRulesClash.v +Elaborated module file created: sysRuleNameInAddRulesClash.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/attribute_scope/RuleNameInForLoop1.bsv.bsc-vcomp-out.expected b/testsuite/bsc.scheduler/attribute_scope/RuleNameInForLoop1.bsv.bsc-vcomp-out.expected index a2e4d65d7..f7b90bb75 100644 --- a/testsuite/bsc.scheduler/attribute_scope/RuleNameInForLoop1.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.scheduler/attribute_scope/RuleNameInForLoop1.bsv.bsc-vcomp-out.expected @@ -10,4 +10,5 @@ Warning: "RuleNameInForLoop1.bsv", line 24, column 12: (G0021) Warning: "RuleNameInForLoop1.bsv", line 24, column 12: (G0021) According to the generated schedule, rule `r4_3' can never fire. Verilog file created: sysRuleNameInForLoop1.v +Elaborated module file created: sysRuleNameInForLoop1.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/attribute_scope/RuleNameInForLoop3.bsv.bsc-vcomp-out.expected b/testsuite/bsc.scheduler/attribute_scope/RuleNameInForLoop3.bsv.bsc-vcomp-out.expected index cf0564b63..abd22d4d8 100644 --- a/testsuite/bsc.scheduler/attribute_scope/RuleNameInForLoop3.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.scheduler/attribute_scope/RuleNameInForLoop3.bsv.bsc-vcomp-out.expected @@ -22,4 +22,5 @@ Warning: "RuleNameInForLoop3.bsv", line 30, column 12: (G0021) Warning: "RuleNameInForLoop3.bsv", line 30, column 12: (G0021) According to the generated schedule, rule `r4_3' can never fire. Verilog file created: sysRuleNameInForLoop3.v +Elaborated module file created: sysRuleNameInForLoop3.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/attribute_scope/RuleNameInFunction.bsv.bsc-vcomp-out.expected b/testsuite/bsc.scheduler/attribute_scope/RuleNameInFunction.bsv.bsc-vcomp-out.expected index b6d5ad6ca..5de1f7f57 100644 --- a/testsuite/bsc.scheduler/attribute_scope/RuleNameInFunction.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.scheduler/attribute_scope/RuleNameInFunction.bsv.bsc-vcomp-out.expected @@ -4,4 +4,5 @@ code generation for sysRuleNameInFunction starts Warning: "RuleNameInFunction.bsv", line 14, column 9: (G0021) According to the generated schedule, rule `r' can never fire. Verilog file created: sysRuleNameInFunction.v +Elaborated module file created: sysRuleNameInFunction.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/attribute_scope/RuleNameInParent.bsv.bsc-vcomp-out.expected b/testsuite/bsc.scheduler/attribute_scope/RuleNameInParent.bsv.bsc-vcomp-out.expected index 273581073..2daedb180 100644 --- a/testsuite/bsc.scheduler/attribute_scope/RuleNameInParent.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.scheduler/attribute_scope/RuleNameInParent.bsv.bsc-vcomp-out.expected @@ -4,4 +4,5 @@ code generation for sysRuleNameInParent starts Warning: "RuleNameInParent.bsv", line 14, column 9: (G0021) According to the generated schedule, rule `r' can never fire. Verilog file created: sysRuleNameInParent.v +Elaborated module file created: sysRuleNameInParent.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/attribute_scope/RuleNameInRJoin1.bsv.bsc-vcomp-out.expected b/testsuite/bsc.scheduler/attribute_scope/RuleNameInRJoin1.bsv.bsc-vcomp-out.expected index 4b791f1fc..97361a2dd 100644 --- a/testsuite/bsc.scheduler/attribute_scope/RuleNameInRJoin1.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.scheduler/attribute_scope/RuleNameInRJoin1.bsv.bsc-vcomp-out.expected @@ -4,4 +4,5 @@ code generation for sysRuleNameInRJoin1 starts Warning: "RuleNameInRJoin1.bsv", line 16, column 15: (G0021) According to the generated schedule, rule `r2' can never fire. Verilog file created: sysRuleNameInRJoin1.v +Elaborated module file created: sysRuleNameInRJoin1.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/attribute_scope/RuleNameNonAlphanum1.bsv.bsc-vcomp-out.expected b/testsuite/bsc.scheduler/attribute_scope/RuleNameNonAlphanum1.bsv.bsc-vcomp-out.expected index 9d91b0e8c..704ef7310 100644 --- a/testsuite/bsc.scheduler/attribute_scope/RuleNameNonAlphanum1.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.scheduler/attribute_scope/RuleNameNonAlphanum1.bsv.bsc-vcomp-out.expected @@ -4,4 +4,5 @@ code generation for sysRuleNameNonAlphanum1 starts Warning: "RuleNameNonAlphanum1.bsv", line 10, column 9: (G0021) According to the generated schedule, rule `r2' can never fire. Verilog file created: sysRuleNameNonAlphanum1.v +Elaborated module file created: sysRuleNameNonAlphanum1.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/attribute_scope/RuleNameNonAlphanumClash1.bsv.bsc-vcomp-out.expected b/testsuite/bsc.scheduler/attribute_scope/RuleNameNonAlphanumClash1.bsv.bsc-vcomp-out.expected index 380175669..39a5adcc7 100644 --- a/testsuite/bsc.scheduler/attribute_scope/RuleNameNonAlphanumClash1.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.scheduler/attribute_scope/RuleNameNonAlphanumClash1.bsv.bsc-vcomp-out.expected @@ -8,4 +8,5 @@ Warning: "RuleNameNonAlphanumClash1.bsv", line 2, column 8: (G0010) Warning: "RuleNameNonAlphanumClash1.bsv", line 9, column 9: (G0021) According to the generated schedule, rule `r1_1' can never fire. Verilog file created: sysRuleNameNonAlphanumClash1.v +Elaborated module file created: sysRuleNameNonAlphanumClash1.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/attribute_scope/RuleNameNonAlphanumClash2.bsv.bsc-vcomp-out.expected b/testsuite/bsc.scheduler/attribute_scope/RuleNameNonAlphanumClash2.bsv.bsc-vcomp-out.expected index aab46b518..d5810172f 100644 --- a/testsuite/bsc.scheduler/attribute_scope/RuleNameNonAlphanumClash2.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.scheduler/attribute_scope/RuleNameNonAlphanumClash2.bsv.bsc-vcomp-out.expected @@ -8,4 +8,5 @@ Warning: "RuleNameNonAlphanumClash2.bsv", line 2, column 8: (G0010) Warning: "RuleNameNonAlphanumClash2.bsv", line 16, column 9: (G0021) According to the generated schedule, rule `r2' can never fire. Verilog file created: sysRuleNameNonAlphanumClash2.v +Elaborated module file created: sysRuleNameNonAlphanumClash2.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/attribute_scope/RuleNameNonAlphanumClash3.bsv.bsc-vcomp-out.expected b/testsuite/bsc.scheduler/attribute_scope/RuleNameNonAlphanumClash3.bsv.bsc-vcomp-out.expected index 47482f625..eb4007d1e 100644 --- a/testsuite/bsc.scheduler/attribute_scope/RuleNameNonAlphanumClash3.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.scheduler/attribute_scope/RuleNameNonAlphanumClash3.bsv.bsc-vcomp-out.expected @@ -8,4 +8,5 @@ Warning: "RuleNameNonAlphanumClash3.bsv", line 2, column 8: (G0010) Warning: "RuleNameNonAlphanumClash3.bsv", line 16, column 9: (G0021) According to the generated schedule, rule `r2' can never fire. Verilog file created: sysRuleNameNonAlphanumClash3.v +Elaborated module file created: sysRuleNameNonAlphanumClash3.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/attribute_scope/RuleNameNonAlphanumClashLoop.bsv.bsc-vcomp-out.expected b/testsuite/bsc.scheduler/attribute_scope/RuleNameNonAlphanumClashLoop.bsv.bsc-vcomp-out.expected index 2498bf2ce..2946823f8 100644 --- a/testsuite/bsc.scheduler/attribute_scope/RuleNameNonAlphanumClashLoop.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.scheduler/attribute_scope/RuleNameNonAlphanumClashLoop.bsv.bsc-vcomp-out.expected @@ -14,4 +14,5 @@ Warning: "RuleNameNonAlphanumClashLoop.bsv", line 12, column 12: (G0021) Warning: "RuleNameNonAlphanumClashLoop.bsv", line 12, column 12: (G0021) According to the generated schedule, rule `r1_1_2' can never fire. Verilog file created: sysRuleNameNonAlphanumClashLoop.v +Elaborated module file created: sysRuleNameNonAlphanumClashLoop.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/attribute_scope/RuleNameWithSpace.bs.bsc-vcomp-out.expected b/testsuite/bsc.scheduler/attribute_scope/RuleNameWithSpace.bs.bsc-vcomp-out.expected index 517b028a8..3b69d04db 100644 --- a/testsuite/bsc.scheduler/attribute_scope/RuleNameWithSpace.bs.bsc-vcomp-out.expected +++ b/testsuite/bsc.scheduler/attribute_scope/RuleNameWithSpace.bs.bsc-vcomp-out.expected @@ -8,4 +8,5 @@ Warning: "RuleNameWithSpace.bs", line 5, column 0: (G0010) Warning: "RuleNameWithSpace.bs", line 13, column 8: (G0021) According to the generated schedule, rule `r2_with_space' can never fire. Verilog file created: sysRuleNameWithSpace.v +Elaborated module file created: sysRuleNameWithSpace.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/attribute_scope/SplitTopMethodName.bsv.bsc-vcomp-out.expected b/testsuite/bsc.scheduler/attribute_scope/SplitTopMethodName.bsv.bsc-vcomp-out.expected index f0a905071..c6a49c0ca 100644 --- a/testsuite/bsc.scheduler/attribute_scope/SplitTopMethodName.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.scheduler/attribute_scope/SplitTopMethodName.bsv.bsc-vcomp-out.expected @@ -2,4 +2,5 @@ checking package dependencies compiling SplitTopMethodName.bsv code generation for sysSplitTopMethodName starts Verilog file created: sysSplitTopMethodName.v +Elaborated module file created: sysSplitTopMethodName.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/attribute_scope/TopMethodNameSubModuleClash.bsv.bsc-vcomp-out.expected b/testsuite/bsc.scheduler/attribute_scope/TopMethodNameSubModuleClash.bsv.bsc-vcomp-out.expected index 254b6cf37..de1ae2ded 100644 --- a/testsuite/bsc.scheduler/attribute_scope/TopMethodNameSubModuleClash.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.scheduler/attribute_scope/TopMethodNameSubModuleClash.bsv.bsc-vcomp-out.expected @@ -26,4 +26,5 @@ Warning: "TopMethodNameSubModuleClash.bsv", line 14, column 8: (G0010) "m_r" cannot fire before "sub_mymethod2": calls to m_rg2.write vs. m_rg2.read Verilog file created: sysTopMethodNameSubModuleClash.v +Elaborated module file created: sysTopMethodNameSubModuleClash.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/attribute_scope/TopMethodNameTopModule1.bsv.bsc-vcomp-out.expected b/testsuite/bsc.scheduler/attribute_scope/TopMethodNameTopModule1.bsv.bsc-vcomp-out.expected index bb0bceb71..466b260d0 100644 --- a/testsuite/bsc.scheduler/attribute_scope/TopMethodNameTopModule1.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.scheduler/attribute_scope/TopMethodNameTopModule1.bsv.bsc-vcomp-out.expected @@ -2,4 +2,5 @@ checking package dependencies compiling TopMethodNameTopModule1.bsv code generation for sysTopMethodNameTopModule1 starts Verilog file created: sysTopMethodNameTopModule1.v +Elaborated module file created: sysTopMethodNameTopModule1.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/attribute_scope/TopMethodNameTopModule2.bsv.bsc-vcomp-out.expected b/testsuite/bsc.scheduler/attribute_scope/TopMethodNameTopModule2.bsv.bsc-vcomp-out.expected index 8943840b6..52826e03e 100644 --- a/testsuite/bsc.scheduler/attribute_scope/TopMethodNameTopModule2.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.scheduler/attribute_scope/TopMethodNameTopModule2.bsv.bsc-vcomp-out.expected @@ -6,4 +6,5 @@ Warning: "TopMethodNameTopModule2.bsv", line 14, column 8: (G0010) "mymethod1" cannot fire before "r": calls to rg1.write vs. rg1.read "r" cannot fire before "mymethod1": calls to rg1.write vs. rg1.read Verilog file created: sysTopMethodNameTopModule1.v +Elaborated module file created: sysTopMethodNameTopModule1.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/avmeth/AVArgUse_C.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/avmeth/AVArgUse_C.bsv.bsc-sched-out.expected index 5f1f97015..7518107e0 100644 --- a/testsuite/bsc.scheduler/avmeth/AVArgUse_C.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/avmeth/AVArgUse_C.bsv.bsc-sched-out.expected @@ -30,6 +30,7 @@ Logical execution order: m ============================================ Verilog file created: mkAVArgUse_C.v +Elaborated module file created: mkAVArgUse_C.ba code generation for sysAVArgUse_C starts Warning: "AVArgUse_C.bsv", line 19, column 8: (G0010) Rule "rA" was treated as more urgent than "rB". Conflicts: @@ -75,4 +76,5 @@ Logical execution order: rA, rB Warning: "AVArgUse_C.bsv", line 30, column 10: (G0021) According to the generated schedule, rule `rB' can never fire. Verilog file created: sysAVArgUse_C.v +Elaborated module file created: sysAVArgUse_C.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/avmeth/AVArgUse_SBR.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/avmeth/AVArgUse_SBR.bsv.bsc-sched-out.expected index f3e1b2f46..2b4ff871b 100644 --- a/testsuite/bsc.scheduler/avmeth/AVArgUse_SBR.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/avmeth/AVArgUse_SBR.bsv.bsc-sched-out.expected @@ -30,6 +30,7 @@ Logical execution order: m ============================================== Verilog file created: mkAVArgUse_SBR.v +Elaborated module file created: mkAVArgUse_SBR.ba code generation for sysAVArgUse_SBR starts Warning: "AVArgUse_SBR.bsv", line 22, column 8: (G0117) Rule `rA' shadows the effects of `rB' when they execute in the same clock @@ -71,4 +72,5 @@ Logical execution order: rB, rA =============================================== Verilog file created: sysAVArgUse_SBR.v +Elaborated module file created: sysAVArgUse_SBR.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/avmeth/ArgCondUse.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/avmeth/ArgCondUse.bsv.bsc-sched-out.expected index 483c27f4d..f517bb184 100644 --- a/testsuite/bsc.scheduler/avmeth/ArgCondUse.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/avmeth/ArgCondUse.bsv.bsc-sched-out.expected @@ -30,4 +30,5 @@ Logical execution order: m ============================================ Verilog file created: mkArgCondUse.v +Elaborated module file created: mkArgCondUse.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/avmeth/TestAVMethCF.bsv.bsc-vcomp-out.expected b/testsuite/bsc.scheduler/avmeth/TestAVMethCF.bsv.bsc-vcomp-out.expected index 5fb59a06c..024b0f256 100644 --- a/testsuite/bsc.scheduler/avmeth/TestAVMethCF.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.scheduler/avmeth/TestAVMethCF.bsv.bsc-vcomp-out.expected @@ -5,3 +5,4 @@ Error: "TestAVMethCF.bsv", line 15, column 8: (G0002) `dut.m' needs more than 1 ports for the following uses: `dut.m 1'd0' at "TestAVMethCF.bsv", line 15, column 8 `dut.m 1'd1' at "TestAVMethCF.bsv", line 15, column 8 +Elaborated error module file created: sysTestAVMethCF.ba diff --git a/testsuite/bsc.scheduler/avmeth/TestAVMethSBR.bsv.bsc-vcomp-out.expected b/testsuite/bsc.scheduler/avmeth/TestAVMethSBR.bsv.bsc-vcomp-out.expected index d7ef97cf0..8097f8bbc 100644 --- a/testsuite/bsc.scheduler/avmeth/TestAVMethSBR.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.scheduler/avmeth/TestAVMethSBR.bsv.bsc-vcomp-out.expected @@ -11,4 +11,5 @@ Warning: "TestAVMethSBR.bsv", line 14, column 8: (G0117) dut.m To silence this warning, use the `-no-warn-action-shadowing' flag. Verilog file created: sysTestAVMethSBR.v +Elaborated module file created: sysTestAVMethSBR.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/disjoint/GCD_t1.bs.bsc-sched-out.expected b/testsuite/bsc.scheduler/disjoint/GCD_t1.bs.bsc-sched-out.expected index ea28ea8ff..709575ba2 100644 --- a/testsuite/bsc.scheduler/disjoint/GCD_t1.bs.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/disjoint/GCD_t1.bs.bsc-sched-out.expected @@ -53,4 +53,5 @@ Logical execution order: init, gcd_flip, gcd_stop, gcd_sub ====================================== Verilog file created: sysGCD.v +Elaborated module file created: sysGCD.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/disjoint/SharedPortsFIFO.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/disjoint/SharedPortsFIFO.bsv.bsc-sched-out.expected index ae108bd42..10a78e527 100644 --- a/testsuite/bsc.scheduler/disjoint/SharedPortsFIFO.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/disjoint/SharedPortsFIFO.bsv.bsc-sched-out.expected @@ -38,4 +38,5 @@ Logical execution order: do_enq, do_otherwise ================================================== Verilog file created: sysSharedPortsFIFO.v +Elaborated module file created: sysSharedPortsFIFO.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/disjoint/SharedPortsRegFile.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/disjoint/SharedPortsRegFile.bsv.bsc-sched-out.expected index d53e8bee5..8e1e5e5cd 100644 --- a/testsuite/bsc.scheduler/disjoint/SharedPortsRegFile.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/disjoint/SharedPortsRegFile.bsv.bsc-sched-out.expected @@ -42,4 +42,5 @@ Logical execution order: do1, do2 ===================================================== Verilog file created: sysSharedPortsRegFile.v +Elaborated module file created: sysSharedPortsRegFile.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/dump/ExpandFalse.bsv.bsc-vcomp-out.expected b/testsuite/bsc.scheduler/dump/ExpandFalse.bsv.bsc-vcomp-out.expected index ef9ed3f12..c5e94c158 100644 --- a/testsuite/bsc.scheduler/dump/ExpandFalse.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.scheduler/dump/ExpandFalse.bsv.bsc-vcomp-out.expected @@ -2,4 +2,5 @@ checking package dependencies compiling ExpandFalse.bsv code generation for sysExpandFalse starts Verilog file created: sysExpandFalse.v +Elaborated module file created: sysExpandFalse.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/dump/RuleFalse.bsv.bsc-vcomp-out.expected b/testsuite/bsc.scheduler/dump/RuleFalse.bsv.bsc-vcomp-out.expected index 884c7c25e..421370265 100644 --- a/testsuite/bsc.scheduler/dump/RuleFalse.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.scheduler/dump/RuleFalse.bsv.bsc-vcomp-out.expected @@ -6,4 +6,5 @@ Warning: "RuleFalse.bsv", line 5, column 8: (G0023) Warning: "RuleFalse.bsv", line 9, column 8: (G0023) The condition for rule `tricky' is always false. Removing... Verilog file created: sysRuleFalse.v +Elaborated module file created: sysRuleFalse.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/dump/RuleNeverFires.bsv.bsc-vcomp-out.expected b/testsuite/bsc.scheduler/dump/RuleNeverFires.bsv.bsc-vcomp-out.expected index 655daf727..1e32dfb9f 100644 --- a/testsuite/bsc.scheduler/dump/RuleNeverFires.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.scheduler/dump/RuleNeverFires.bsv.bsc-vcomp-out.expected @@ -11,4 +11,5 @@ Warning: "RuleNeverFires.bsv", line 3, column 8: (G0010) Warning: "RuleNeverFires.bsv", line 11, column 8: (G0021) According to the generated schedule, rule `never_fires' can never fire. Verilog file created: sysRuleNeverFires.v +Elaborated module file created: sysRuleNeverFires.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/earliness/ActionShadowing.bsv.bsc-vcomp-out.expected b/testsuite/bsc.scheduler/earliness/ActionShadowing.bsv.bsc-vcomp-out.expected index afea4ccfa..dd2faabf4 100644 --- a/testsuite/bsc.scheduler/earliness/ActionShadowing.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.scheduler/earliness/ActionShadowing.bsv.bsc-vcomp-out.expected @@ -12,4 +12,5 @@ Warning: "ActionShadowing.bsv", line 4, column 8: (G0117) rg1.write To silence this warning, use the `-no-warn-action-shadowing' flag. Verilog file created: sysTest.v +Elaborated module file created: sysTest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/earliness/ExecutionOrderAttr_Method.bsv.bsc-vcomp-out.expected b/testsuite/bsc.scheduler/earliness/ExecutionOrderAttr_Method.bsv.bsc-vcomp-out.expected index 5e47d77f3..349eb1977 100644 --- a/testsuite/bsc.scheduler/earliness/ExecutionOrderAttr_Method.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.scheduler/earliness/ExecutionOrderAttr_Method.bsv.bsc-vcomp-out.expected @@ -7,4 +7,5 @@ Warning: "ExecutionOrderAttr_Method.bsv", line 7, column 8: (G0117) rg.write To silence this warning, use the `-no-warn-action-shadowing' flag. Verilog file created: sysExecutionOrderAttr_Method.v +Elaborated module file created: sysExecutionOrderAttr_Method.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/relax-schedule/Ex1.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/relax-schedule/Ex1.bsv.bsc-sched-out.expected index 97e939fc6..d859a9b4d 100644 --- a/testsuite/bsc.scheduler/relax-schedule/Ex1.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/relax-schedule/Ex1.bsv.bsc-sched-out.expected @@ -60,4 +60,5 @@ Logical execution order: a, b, c ===================================== Verilog file created: mkEx1.v +Elaborated module file created: mkEx1.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/relax-schedule/Ex2.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/relax-schedule/Ex2.bsv.bsc-sched-out.expected index e4d9c53ea..15458f6f3 100644 --- a/testsuite/bsc.scheduler/relax-schedule/Ex2.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/relax-schedule/Ex2.bsv.bsc-sched-out.expected @@ -49,4 +49,5 @@ Logical execution order: a, b, c ===================================== Verilog file created: mkEx2.v +Elaborated module file created: mkEx2.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/relax-schedule/Ex3.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/relax-schedule/Ex3.bsv.bsc-sched-out.expected index d6dd2cac3..569f74677 100644 --- a/testsuite/bsc.scheduler/relax-schedule/Ex3.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/relax-schedule/Ex3.bsv.bsc-sched-out.expected @@ -70,4 +70,5 @@ Logical execution order: a, b, c, d, e ===================================== Verilog file created: mkEx3.v +Elaborated module file created: mkEx3.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/relax-schedule/Ex4.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/relax-schedule/Ex4.bsv.bsc-sched-out.expected index 73113677d..08a7ceee0 100644 --- a/testsuite/bsc.scheduler/relax-schedule/Ex4.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/relax-schedule/Ex4.bsv.bsc-sched-out.expected @@ -79,4 +79,5 @@ Logical execution order: a, b1, b2, b3, b4, b5, c ===================================== Verilog file created: mkEx4.v +Elaborated module file created: mkEx4.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/relax-schedule/Ex5.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/relax-schedule/Ex5.bsv.bsc-sched-out.expected index c2201cc80..aea3602ed 100644 --- a/testsuite/bsc.scheduler/relax-schedule/Ex5.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/relax-schedule/Ex5.bsv.bsc-sched-out.expected @@ -66,4 +66,5 @@ Logical execution order: b, c, a ===================================== Verilog file created: mkEx5.v +Elaborated module file created: mkEx5.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/relax-schedule/GetUrgency.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/relax-schedule/GetUrgency.bsv.bsc-sched-out.expected index 884e11b02..0bac52d7b 100644 --- a/testsuite/bsc.scheduler/relax-schedule/GetUrgency.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/relax-schedule/GetUrgency.bsv.bsc-sched-out.expected @@ -85,4 +85,5 @@ Logical execution order: enq, ========================================= Verilog file created: mkGetTest.v +Elaborated module file created: mkGetTest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/relax-schedule/IBuffer2.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/relax-schedule/IBuffer2.bsv.bsc-sched-out.expected index d65f4f084..cbd4470e8 100644 --- a/testsuite/bsc.scheduler/relax-schedule/IBuffer2.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/relax-schedule/IBuffer2.bsv.bsc-sched-out.expected @@ -274,4 +274,5 @@ Logical execution order: handleIBufferRequest, ========================================= Verilog file created: mkIBuffer.v +Elaborated module file created: mkIBuffer.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/relax-schedule/PutUrgency.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/relax-schedule/PutUrgency.bsv.bsc-sched-out.expected index c924d9edb..56a765835 100644 --- a/testsuite/bsc.scheduler/relax-schedule/PutUrgency.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/relax-schedule/PutUrgency.bsv.bsc-sched-out.expected @@ -40,4 +40,5 @@ Logical execution order: display_output, put ========================================= Verilog file created: mkPutTest.v +Elaborated module file created: mkPutTest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/relax-schedule/PutUrgency2.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/relax-schedule/PutUrgency2.bsv.bsc-sched-out.expected index e8b2ab3b0..2aaab9204 100644 --- a/testsuite/bsc.scheduler/relax-schedule/PutUrgency2.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/relax-schedule/PutUrgency2.bsv.bsc-sched-out.expected @@ -42,4 +42,5 @@ Logical execution order: display_output, put ========================================== Verilog file created: mkPutTest2.v +Elaborated module file created: mkPutTest2.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/relax-schedule/SeqEx1.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/relax-schedule/SeqEx1.bsv.bsc-sched-out.expected index f618bb271..5f9de02b0 100644 --- a/testsuite/bsc.scheduler/relax-schedule/SeqEx1.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/relax-schedule/SeqEx1.bsv.bsc-sched-out.expected @@ -56,4 +56,5 @@ Logical execution order: b, c, d, a ======================================== Verilog file created: mkSeqEx1.v +Elaborated module file created: mkSeqEx1.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/relax-schedule/ValueMethodEx1.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/relax-schedule/ValueMethodEx1.bsv.bsc-sched-out.expected index 5bbc7962e..bcf37cf0d 100644 --- a/testsuite/bsc.scheduler/relax-schedule/ValueMethodEx1.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/relax-schedule/ValueMethodEx1.bsv.bsc-sched-out.expected @@ -50,6 +50,7 @@ Logical execution order: a, copy_it, b ======================================= Verilog file created: mkTloop.v +Elaborated module file created: mkTloop.ba code generation for sysTloop starts === schedule (ValueMethodEx1 sysTloop): parallel: [esposito: [RL_count -> [], RL_quit -> [], RL_poke -> [], RL_yell -> []]] @@ -96,4 +97,5 @@ Logical execution order: quit, poke, count, yell ======================================== Verilog file created: sysTloop.v +Elaborated module file created: sysTloop.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/relax-schedule/ValueMethodEx2.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/relax-schedule/ValueMethodEx2.bsv.bsc-sched-out.expected index 0140b8280..b2dd3c76e 100644 --- a/testsuite/bsc.scheduler/relax-schedule/ValueMethodEx2.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/relax-schedule/ValueMethodEx2.bsv.bsc-sched-out.expected @@ -50,6 +50,7 @@ Logical execution order: m1, r, m2 ==================================================== Verilog file created: mkValueMethodEx2Mod1.v +Elaborated module file created: mkValueMethodEx2Mod1.ba code generation for mkValueMethodEx2Mod2 starts === schedule (ValueMethodEx2 mkValueMethodEx2Mod2): parallel: [esposito: [m1 -> [], RL_r -> [], m2 -> []]] @@ -100,4 +101,5 @@ Logical execution order: m1, r, m2 ==================================================== Verilog file created: mkValueMethodEx2Mod2.v +Elaborated module file created: mkValueMethodEx2Mod2.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/resource/ResourceOneRuleCSE.bs.bsc-sched-out.expected b/testsuite/bsc.scheduler/resource/ResourceOneRuleCSE.bs.bsc-sched-out.expected index 924cbafae..32e197b0b 100644 --- a/testsuite/bsc.scheduler/resource/ResourceOneRuleCSE.bs.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/resource/ResourceOneRuleCSE.bs.bsc-sched-out.expected @@ -22,3 +22,4 @@ Predicate: True ===================================================== +Elaborated error module file created: sysResourceOneRuleCSE.ba diff --git a/testsuite/bsc.scheduler/resource/ResourceOneRuleCSE2.bs.bsc-sched-out.expected b/testsuite/bsc.scheduler/resource/ResourceOneRuleCSE2.bs.bsc-sched-out.expected index f19513185..b219b9521 100644 --- a/testsuite/bsc.scheduler/resource/ResourceOneRuleCSE2.bs.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/resource/ResourceOneRuleCSE2.bs.bsc-sched-out.expected @@ -22,3 +22,4 @@ Predicate: True ====================================================== +Elaborated error module file created: sysResourceOneRuleCSE2.ba diff --git a/testsuite/bsc.scheduler/resource/ResourceOneRuleCSEnoSC.bs.bsc-sched-out.expected b/testsuite/bsc.scheduler/resource/ResourceOneRuleCSEnoSC.bs.bsc-sched-out.expected index 19b029e3c..ef6e6d97b 100644 --- a/testsuite/bsc.scheduler/resource/ResourceOneRuleCSEnoSC.bs.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/resource/ResourceOneRuleCSEnoSC.bs.bsc-sched-out.expected @@ -22,3 +22,4 @@ Predicate: q.i_notFull ========================================================= +Elaborated error module file created: sysResourceOneRuleCSEnoSC.ba diff --git a/testsuite/bsc.scheduler/resource/ResourceOneRuleFail.bs.bsc-sched-out.expected b/testsuite/bsc.scheduler/resource/ResourceOneRuleFail.bs.bsc-sched-out.expected index 78a4b261c..9d88081bb 100644 --- a/testsuite/bsc.scheduler/resource/ResourceOneRuleFail.bs.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/resource/ResourceOneRuleFail.bs.bsc-sched-out.expected @@ -24,3 +24,4 @@ Predicate: True ====================================================== +Elaborated error module file created: sysResourceOneRuleFail.ba diff --git a/testsuite/bsc.scheduler/resource/ResourceOneRuleFailII.bs.bsc-sched-out.expected b/testsuite/bsc.scheduler/resource/ResourceOneRuleFailII.bs.bsc-sched-out.expected index 7112be58c..97114fbcd 100644 --- a/testsuite/bsc.scheduler/resource/ResourceOneRuleFailII.bs.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/resource/ResourceOneRuleFailII.bs.bsc-sched-out.expected @@ -24,3 +24,4 @@ Predicate: True ======================================================== +Elaborated error module file created: sysResourceOneRuleFailII.ba diff --git a/testsuite/bsc.scheduler/resource/ResourceOneRuleFailIII.bs.bsc-sched-out.expected b/testsuite/bsc.scheduler/resource/ResourceOneRuleFailIII.bs.bsc-sched-out.expected index a4e7bbcba..e4f40ff93 100644 --- a/testsuite/bsc.scheduler/resource/ResourceOneRuleFailIII.bs.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/resource/ResourceOneRuleFailIII.bs.bsc-sched-out.expected @@ -22,3 +22,4 @@ Predicate: True ========================================================= +Elaborated error module file created: sysResourceOneRuleFailIII.ba diff --git a/testsuite/bsc.scheduler/resource/ResourceOneRuleOK.bs.bsc-sched-out.expected b/testsuite/bsc.scheduler/resource/ResourceOneRuleOK.bs.bsc-sched-out.expected index 3c7e41916..8707d47b4 100644 --- a/testsuite/bsc.scheduler/resource/ResourceOneRuleOK.bs.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/resource/ResourceOneRuleOK.bs.bsc-sched-out.expected @@ -31,4 +31,5 @@ Logical execution order: Good ==================================================== Verilog file created: sysResourceOneRuleOK.v +Elaborated module file created: sysResourceOneRuleOK.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/resource/ResourceOneRuleSC.bs.bsc-sched-out.expected b/testsuite/bsc.scheduler/resource/ResourceOneRuleSC.bs.bsc-sched-out.expected index 853002b1b..76fd5bc07 100644 --- a/testsuite/bsc.scheduler/resource/ResourceOneRuleSC.bs.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/resource/ResourceOneRuleSC.bs.bsc-sched-out.expected @@ -22,3 +22,4 @@ Predicate: True ==================================================== +Elaborated error module file created: sysResourceOneRuleSC.ba diff --git a/testsuite/bsc.scheduler/resource/ResourcePredicates.bs.bsc-sched-out.expected b/testsuite/bsc.scheduler/resource/ResourcePredicates.bs.bsc-sched-out.expected index fcc72811b..37c2fc3fe 100644 --- a/testsuite/bsc.scheduler/resource/ResourcePredicates.bs.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/resource/ResourcePredicates.bs.bsc-sched-out.expected @@ -45,4 +45,5 @@ Logical execution order: A, B ===================================================== Verilog file created: sysResourcePredicates.v +Elaborated module file created: sysResourcePredicates.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/resource/ResourceTwoRules.bs.bsc-sched-out.expected b/testsuite/bsc.scheduler/resource/ResourceTwoRules.bs.bsc-sched-out.expected index 0ea6bbbed..462ebb7c3 100644 --- a/testsuite/bsc.scheduler/resource/ResourceTwoRules.bs.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/resource/ResourceTwoRules.bs.bsc-sched-out.expected @@ -88,4 +88,5 @@ Logical execution order: Contender, Warning: "ResourceTwoRules.bs", line 23, column 26: (G0021) According to the generated schedule, rule `Contender_1' can never fire. Verilog file created: sysResourceTwoRules.v +Elaborated module file created: sysResourceTwoRules.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/resource/ResourceTwoRulesCond.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/resource/ResourceTwoRulesCond.bsv.bsc-sched-out.expected index db5d3f24a..a8751740c 100644 --- a/testsuite/bsc.scheduler/resource/ResourceTwoRulesCond.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/resource/ResourceTwoRulesCond.bsv.bsc-sched-out.expected @@ -240,4 +240,5 @@ Warning: "ResourceTwoRulesCond.bsv", line 15, column 12: (G0021) Warning: "ResourceTwoRulesCond.bsv", line 15, column 12: (G0021) According to the generated schedule, rule `contend_3' can never fire. Verilog file created: sysResourceTwoRulesCond.v +Elaborated module file created: sysResourceTwoRulesCond.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sat/AddTest_sat-stp.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/AddTest_sat-stp.bsv.bsc-sched-out.expected index d7693241f..639c2570a 100644 --- a/testsuite/bsc.scheduler/sat/AddTest_sat-stp.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sat/AddTest_sat-stp.bsv.bsc-sched-out.expected @@ -52,4 +52,5 @@ Logical execution order: aa, ab, bb Warning: "AddTest_sat-stp.bsv", line 26, column 10: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysAddTest.v +Elaborated module file created: sysAddTest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sat/AddTest_sat-yices.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/AddTest_sat-yices.bsv.bsc-sched-out.expected index 5c1da6a34..4fda36014 100644 --- a/testsuite/bsc.scheduler/sat/AddTest_sat-yices.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sat/AddTest_sat-yices.bsv.bsc-sched-out.expected @@ -52,4 +52,5 @@ Logical execution order: aa, ab, bb Warning: "AddTest_sat-yices.bsv", line 26, column 10: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysAddTest.v +Elaborated module file created: sysAddTest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sat/ArraySelectImplCondTest_sat-stp.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/ArraySelectImplCondTest_sat-stp.bsv.bsc-sched-out.expected index 5f5ad1be9..cb7b476cc 100644 --- a/testsuite/bsc.scheduler/sat/ArraySelectImplCondTest_sat-stp.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sat/ArraySelectImplCondTest_sat-stp.bsv.bsc-sched-out.expected @@ -83,4 +83,5 @@ Logical execution order: aa, ab, bb Warning: "ArraySelectImplCondTest_sat-stp.bsv", line 58, column 10: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysArraySelectImplCondTest.v +Elaborated module file created: sysArraySelectImplCondTest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sat/ArraySelectImplCondTest_sat-yices.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/ArraySelectImplCondTest_sat-yices.bsv.bsc-sched-out.expected index 012345890..fec7ee90f 100644 --- a/testsuite/bsc.scheduler/sat/ArraySelectImplCondTest_sat-yices.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sat/ArraySelectImplCondTest_sat-yices.bsv.bsc-sched-out.expected @@ -83,4 +83,5 @@ Logical execution order: aa, ab, bb Warning: "ArraySelectImplCondTest_sat-yices.bsv", line 58, column 10: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysArraySelectImplCondTest.v +Elaborated module file created: sysArraySelectImplCondTest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sat/ArraySelectLongIndexTest_sat-stp.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/ArraySelectLongIndexTest_sat-stp.bsv.bsc-sched-out.expected index a1b0dcab5..61b648c06 100644 --- a/testsuite/bsc.scheduler/sat/ArraySelectLongIndexTest_sat-stp.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sat/ArraySelectLongIndexTest_sat-stp.bsv.bsc-sched-out.expected @@ -65,4 +65,5 @@ Logical execution order: aa, ab, bb Warning: "ArraySelectLongIndexTest_sat-stp.bsv", line 35, column 10: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysArraySelectLongIndexTest.v +Elaborated module file created: sysArraySelectLongIndexTest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sat/ArraySelectLongIndexTest_sat-yices.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/ArraySelectLongIndexTest_sat-yices.bsv.bsc-sched-out.expected index e59588838..182b4e842 100644 --- a/testsuite/bsc.scheduler/sat/ArraySelectLongIndexTest_sat-yices.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sat/ArraySelectLongIndexTest_sat-yices.bsv.bsc-sched-out.expected @@ -65,4 +65,5 @@ Logical execution order: aa, ab, bb Warning: "ArraySelectLongIndexTest_sat-yices.bsv", line 35, column 10: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysArraySelectLongIndexTest.v +Elaborated module file created: sysArraySelectLongIndexTest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sat/ArraySelectShortIndexTest_sat-stp.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/ArraySelectShortIndexTest_sat-stp.bsv.bsc-sched-out.expected index 494b851b6..d244c2230 100644 --- a/testsuite/bsc.scheduler/sat/ArraySelectShortIndexTest_sat-stp.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sat/ArraySelectShortIndexTest_sat-stp.bsv.bsc-sched-out.expected @@ -64,4 +64,5 @@ Logical execution order: aa, ab, bb Warning: "ArraySelectShortIndexTest_sat-stp.bsv", line 35, column 10: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysArraySelectShortIndexTest.v +Elaborated module file created: sysArraySelectShortIndexTest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sat/ArraySelectShortIndexTest_sat-yices.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/ArraySelectShortIndexTest_sat-yices.bsv.bsc-sched-out.expected index f988cac6a..a6f3500a0 100644 --- a/testsuite/bsc.scheduler/sat/ArraySelectShortIndexTest_sat-yices.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sat/ArraySelectShortIndexTest_sat-yices.bsv.bsc-sched-out.expected @@ -64,4 +64,5 @@ Logical execution order: aa, ab, bb Warning: "ArraySelectShortIndexTest_sat-yices.bsv", line 35, column 10: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysArraySelectShortIndexTest.v +Elaborated module file created: sysArraySelectShortIndexTest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sat/ArraySelectTest_sat-stp.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/ArraySelectTest_sat-stp.bsv.bsc-sched-out.expected index dc3054979..0e3092b31 100644 --- a/testsuite/bsc.scheduler/sat/ArraySelectTest_sat-stp.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sat/ArraySelectTest_sat-stp.bsv.bsc-sched-out.expected @@ -59,4 +59,5 @@ Logical execution order: aa, ab, bb Warning: "ArraySelectTest_sat-stp.bsv", line 32, column 10: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysArraySelectTest.v +Elaborated module file created: sysArraySelectTest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sat/ArraySelectTest_sat-yices.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/ArraySelectTest_sat-yices.bsv.bsc-sched-out.expected index 9d21f7efa..f7e84242d 100644 --- a/testsuite/bsc.scheduler/sat/ArraySelectTest_sat-yices.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sat/ArraySelectTest_sat-yices.bsv.bsc-sched-out.expected @@ -59,4 +59,5 @@ Logical execution order: aa, ab, bb Warning: "ArraySelectTest_sat-yices.bsv", line 32, column 10: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysArraySelectTest.v +Elaborated module file created: sysArraySelectTest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sat/BoolTest_sat-stp.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/BoolTest_sat-stp.bsv.bsc-sched-out.expected index 0b45f46ea..090efe0a9 100644 --- a/testsuite/bsc.scheduler/sat/BoolTest_sat-stp.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sat/BoolTest_sat-stp.bsv.bsc-sched-out.expected @@ -48,4 +48,5 @@ Logical execution order: aa, ab, bb Warning: "BoolTest_sat-stp.bsv", line 25, column 10: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysBoolTest.v +Elaborated module file created: sysBoolTest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sat/BoolTest_sat-yices.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/BoolTest_sat-yices.bsv.bsc-sched-out.expected index fafff9bb7..71bcd246a 100644 --- a/testsuite/bsc.scheduler/sat/BoolTest_sat-yices.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sat/BoolTest_sat-yices.bsv.bsc-sched-out.expected @@ -48,4 +48,5 @@ Logical execution order: aa, ab, bb Warning: "BoolTest_sat-yices.bsv", line 25, column 10: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysBoolTest.v +Elaborated module file created: sysBoolTest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sat/CaseTest_sat-stp.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/CaseTest_sat-stp.bsv.bsc-sched-out.expected index 457a4840a..e5acd1adf 100644 --- a/testsuite/bsc.scheduler/sat/CaseTest_sat-stp.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sat/CaseTest_sat-stp.bsv.bsc-sched-out.expected @@ -69,4 +69,5 @@ Logical execution order: aa, ab, bb Warning: "CaseTest_sat-stp.bsv", line 45, column 10: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysCaseTest.v +Elaborated module file created: sysCaseTest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sat/CaseTest_sat-yices.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/CaseTest_sat-yices.bsv.bsc-sched-out.expected index 4e8803008..4c9925475 100644 --- a/testsuite/bsc.scheduler/sat/CaseTest_sat-yices.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sat/CaseTest_sat-yices.bsv.bsc-sched-out.expected @@ -69,4 +69,5 @@ Logical execution order: aa, ab, bb Warning: "CaseTest_sat-yices.bsv", line 45, column 10: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysCaseTest.v +Elaborated module file created: sysCaseTest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sat/DivTest_sat-stp.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/DivTest_sat-stp.bsv.bsc-sched-out.expected index 5748c0932..4f68cc209 100644 --- a/testsuite/bsc.scheduler/sat/DivTest_sat-stp.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sat/DivTest_sat-stp.bsv.bsc-sched-out.expected @@ -90,4 +90,5 @@ Logical execution order: aa, ab, ac, ad, ae, af, bb Warning: "DivTest_sat-stp.bsv", line 40, column 10: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysDivTest.v +Elaborated module file created: sysDivTest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sat/DivTest_sat-yices.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/DivTest_sat-yices.bsv.bsc-sched-out.expected index 03c39fcd5..c934b6e8c 100644 --- a/testsuite/bsc.scheduler/sat/DivTest_sat-yices.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sat/DivTest_sat-yices.bsv.bsc-sched-out.expected @@ -90,4 +90,5 @@ Logical execution order: aa, ab, ac, ad, ae, af, bb Warning: "DivTest_sat-yices.bsv", line 40, column 10: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysDivTest.v +Elaborated module file created: sysDivTest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sat/IteTest_sat-stp.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/IteTest_sat-stp.bsv.bsc-sched-out.expected index f126d0694..f09b4b600 100644 --- a/testsuite/bsc.scheduler/sat/IteTest_sat-stp.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sat/IteTest_sat-stp.bsv.bsc-sched-out.expected @@ -56,4 +56,5 @@ Logical execution order: aa, ab, bb Warning: "IteTest_sat-stp.bsv", line 30, column 10: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysIteTest.v +Elaborated module file created: sysIteTest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sat/IteTest_sat-yices.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/IteTest_sat-yices.bsv.bsc-sched-out.expected index 154e90c08..a83c6f40f 100644 --- a/testsuite/bsc.scheduler/sat/IteTest_sat-yices.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sat/IteTest_sat-yices.bsv.bsc-sched-out.expected @@ -56,4 +56,5 @@ Logical execution order: aa, ab, bb Warning: "IteTest_sat-yices.bsv", line 30, column 10: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysIteTest.v +Elaborated module file created: sysIteTest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sat/LessThanSTest_sat-stp.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/LessThanSTest_sat-stp.bsv.bsc-sched-out.expected index 54ce478fe..ab83a38a1 100644 --- a/testsuite/bsc.scheduler/sat/LessThanSTest_sat-stp.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sat/LessThanSTest_sat-stp.bsv.bsc-sched-out.expected @@ -52,4 +52,5 @@ Logical execution order: aa, ab, bb Warning: "LessThanSTest_sat-stp.bsv", line 26, column 10: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysLessThanSTest.v +Elaborated module file created: sysLessThanSTest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sat/LessThanSTest_sat-yices.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/LessThanSTest_sat-yices.bsv.bsc-sched-out.expected index 7adbb2f07..35efc1ad8 100644 --- a/testsuite/bsc.scheduler/sat/LessThanSTest_sat-yices.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sat/LessThanSTest_sat-yices.bsv.bsc-sched-out.expected @@ -52,4 +52,5 @@ Logical execution order: aa, ab, bb Warning: "LessThanSTest_sat-yices.bsv", line 26, column 10: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysLessThanSTest.v +Elaborated module file created: sysLessThanSTest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sat/LessThanTest_sat-stp.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/LessThanTest_sat-stp.bsv.bsc-sched-out.expected index 49336ce39..1fc4d4758 100644 --- a/testsuite/bsc.scheduler/sat/LessThanTest_sat-stp.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sat/LessThanTest_sat-stp.bsv.bsc-sched-out.expected @@ -52,4 +52,5 @@ Logical execution order: aa, ab, bb Warning: "LessThanTest_sat-stp.bsv", line 26, column 10: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysLessThanTest.v +Elaborated module file created: sysLessThanTest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sat/LessThanTest_sat-yices.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/LessThanTest_sat-yices.bsv.bsc-sched-out.expected index 8862f3e1e..22f55f710 100644 --- a/testsuite/bsc.scheduler/sat/LessThanTest_sat-yices.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sat/LessThanTest_sat-yices.bsv.bsc-sched-out.expected @@ -52,4 +52,5 @@ Logical execution order: aa, ab, bb Warning: "LessThanTest_sat-yices.bsv", line 26, column 10: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysLessThanTest.v +Elaborated module file created: sysLessThanTest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sat/MultTest_sat-stp.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/MultTest_sat-stp.bsv.bsc-sched-out.expected index 381d3ada0..44560b64c 100644 --- a/testsuite/bsc.scheduler/sat/MultTest_sat-stp.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sat/MultTest_sat-stp.bsv.bsc-sched-out.expected @@ -53,4 +53,5 @@ Logical execution order: aa, ab, bb Warning: "MultTest_sat-stp.bsv", line 26, column 10: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysMultTest.v +Elaborated module file created: sysMultTest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sat/MultTest_sat-yices.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/MultTest_sat-yices.bsv.bsc-sched-out.expected index 0caba8c0a..b65714397 100644 --- a/testsuite/bsc.scheduler/sat/MultTest_sat-yices.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sat/MultTest_sat-yices.bsv.bsc-sched-out.expected @@ -53,4 +53,5 @@ Logical execution order: aa, ab, bb Warning: "MultTest_sat-yices.bsv", line 26, column 10: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysMultTest.v +Elaborated module file created: sysMultTest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sat/ParamBitsTest_sat-stp.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/ParamBitsTest_sat-stp.bsv.bsc-sched-out.expected index f1864e945..cc18c6bb2 100644 --- a/testsuite/bsc.scheduler/sat/ParamBitsTest_sat-stp.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sat/ParamBitsTest_sat-stp.bsv.bsc-sched-out.expected @@ -50,4 +50,5 @@ Logical execution order: aa, ab, bb Warning: "ParamBitsTest_sat-stp.bsv", line 19, column 9: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysParamBitsTest.v +Elaborated module file created: sysParamBitsTest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sat/ParamBitsTest_sat-yices.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/ParamBitsTest_sat-yices.bsv.bsc-sched-out.expected index 5a9b21379..8ae91987a 100644 --- a/testsuite/bsc.scheduler/sat/ParamBitsTest_sat-yices.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sat/ParamBitsTest_sat-yices.bsv.bsc-sched-out.expected @@ -50,4 +50,5 @@ Logical execution order: aa, ab, bb Warning: "ParamBitsTest_sat-yices.bsv", line 19, column 9: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysParamBitsTest.v +Elaborated module file created: sysParamBitsTest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sat/ParamBoolTest_sat-stp.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/ParamBoolTest_sat-stp.bsv.bsc-sched-out.expected index 8855d4f7c..ae2c2ef11 100644 --- a/testsuite/bsc.scheduler/sat/ParamBoolTest_sat-stp.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sat/ParamBoolTest_sat-stp.bsv.bsc-sched-out.expected @@ -50,4 +50,5 @@ Logical execution order: aa, ab, bb Warning: "ParamBoolTest_sat-stp.bsv", line 19, column 9: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysParamBoolTest.v +Elaborated module file created: sysParamBoolTest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sat/ParamBoolTest_sat-yices.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/ParamBoolTest_sat-yices.bsv.bsc-sched-out.expected index 193b152bb..7edfe5140 100644 --- a/testsuite/bsc.scheduler/sat/ParamBoolTest_sat-yices.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sat/ParamBoolTest_sat-yices.bsv.bsc-sched-out.expected @@ -50,4 +50,5 @@ Logical execution order: aa, ab, bb Warning: "ParamBoolTest_sat-yices.bsv", line 19, column 9: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysParamBoolTest.v +Elaborated module file created: sysParamBoolTest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sat/RemTest_sat-stp.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/RemTest_sat-stp.bsv.bsc-sched-out.expected index 492d99517..37960b536 100644 --- a/testsuite/bsc.scheduler/sat/RemTest_sat-stp.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sat/RemTest_sat-stp.bsv.bsc-sched-out.expected @@ -80,4 +80,5 @@ Logical execution order: aa, ab, ac, ad, ae, bb Warning: "RemTest_sat-stp.bsv", line 38, column 10: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysRemTest.v +Elaborated module file created: sysRemTest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sat/RemTest_sat-yices.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/RemTest_sat-yices.bsv.bsc-sched-out.expected index 1232ca54b..41678e4e1 100644 --- a/testsuite/bsc.scheduler/sat/RemTest_sat-yices.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sat/RemTest_sat-yices.bsv.bsc-sched-out.expected @@ -80,4 +80,5 @@ Logical execution order: aa, ab, ac, ad, ae, bb Warning: "RemTest_sat-yices.bsv", line 38, column 10: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysRemTest.v +Elaborated module file created: sysRemTest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sat/SextTest_sat-stp.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/SextTest_sat-stp.bsv.bsc-sched-out.expected index 9b4cc15f4..d255024f5 100644 --- a/testsuite/bsc.scheduler/sat/SextTest_sat-stp.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sat/SextTest_sat-stp.bsv.bsc-sched-out.expected @@ -52,4 +52,5 @@ Logical execution order: aa, ab, bb Warning: "SextTest_sat-stp.bsv", line 40, column 10: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysSextTest.v +Elaborated module file created: sysSextTest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sat/SextTest_sat-yices.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/SextTest_sat-yices.bsv.bsc-sched-out.expected index 553def21c..6240eeb7a 100644 --- a/testsuite/bsc.scheduler/sat/SextTest_sat-yices.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sat/SextTest_sat-yices.bsv.bsc-sched-out.expected @@ -52,4 +52,5 @@ Logical execution order: aa, ab, bb Warning: "SextTest_sat-yices.bsv", line 40, column 10: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysSextTest.v +Elaborated module file created: sysSextTest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sat/ShiftLTest_sat-stp.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/ShiftLTest_sat-stp.bsv.bsc-sched-out.expected index 1c40e379b..afe6625aa 100644 --- a/testsuite/bsc.scheduler/sat/ShiftLTest_sat-stp.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sat/ShiftLTest_sat-stp.bsv.bsc-sched-out.expected @@ -52,4 +52,5 @@ Logical execution order: aa, ab, bb Warning: "ShiftLTest_sat-stp.bsv", line 27, column 10: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysShiftRTest.v +Elaborated module file created: sysShiftRTest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sat/ShiftLTest_sat-yices.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/ShiftLTest_sat-yices.bsv.bsc-sched-out.expected index 657754514..158040ccd 100644 --- a/testsuite/bsc.scheduler/sat/ShiftLTest_sat-yices.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sat/ShiftLTest_sat-yices.bsv.bsc-sched-out.expected @@ -52,4 +52,5 @@ Logical execution order: aa, ab, bb Warning: "ShiftLTest_sat-yices.bsv", line 27, column 10: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysShiftRTest.v +Elaborated module file created: sysShiftRTest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sat/ShiftRATest2_sat-stp.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/ShiftRATest2_sat-stp.bsv.bsc-sched-out.expected index 7102859ad..9f45b47e9 100644 --- a/testsuite/bsc.scheduler/sat/ShiftRATest2_sat-stp.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sat/ShiftRATest2_sat-stp.bsv.bsc-sched-out.expected @@ -66,4 +66,5 @@ Logical execution order: aa, ab, bb Warning: "ShiftRATest2_sat-stp.bsv", line 29, column 10: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysShiftRATest.v +Elaborated module file created: sysShiftRATest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sat/ShiftRATest2_sat-yices.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/ShiftRATest2_sat-yices.bsv.bsc-sched-out.expected index cf2864f43..d00876ead 100644 --- a/testsuite/bsc.scheduler/sat/ShiftRATest2_sat-yices.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sat/ShiftRATest2_sat-yices.bsv.bsc-sched-out.expected @@ -66,4 +66,5 @@ Logical execution order: aa, ab, bb Warning: "ShiftRATest2_sat-yices.bsv", line 29, column 10: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysShiftRATest.v +Elaborated module file created: sysShiftRATest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sat/ShiftRATest_sat-stp.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/ShiftRATest_sat-stp.bsv.bsc-sched-out.expected index fdce1d13e..5781ba22b 100644 --- a/testsuite/bsc.scheduler/sat/ShiftRATest_sat-stp.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sat/ShiftRATest_sat-stp.bsv.bsc-sched-out.expected @@ -66,4 +66,5 @@ Logical execution order: aa, ab, bb Warning: "ShiftRATest_sat-stp.bsv", line 27, column 10: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysShiftRATest.v +Elaborated module file created: sysShiftRATest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sat/ShiftRATest_sat-yices.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/ShiftRATest_sat-yices.bsv.bsc-sched-out.expected index 65dc596b2..a7af238f4 100644 --- a/testsuite/bsc.scheduler/sat/ShiftRATest_sat-yices.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sat/ShiftRATest_sat-yices.bsv.bsc-sched-out.expected @@ -66,4 +66,5 @@ Logical execution order: aa, ab, bb Warning: "ShiftRATest_sat-yices.bsv", line 27, column 10: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysShiftRATest.v +Elaborated module file created: sysShiftRATest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sat/ShiftRTest_sat-stp.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/ShiftRTest_sat-stp.bsv.bsc-sched-out.expected index 61fcd933b..43bd6e10c 100644 --- a/testsuite/bsc.scheduler/sat/ShiftRTest_sat-stp.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sat/ShiftRTest_sat-stp.bsv.bsc-sched-out.expected @@ -52,4 +52,5 @@ Logical execution order: aa, ab, bb Warning: "ShiftRTest_sat-stp.bsv", line 27, column 10: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysShiftRTest.v +Elaborated module file created: sysShiftRTest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sat/ShiftRTest_sat-yices.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/ShiftRTest_sat-yices.bsv.bsc-sched-out.expected index 7f7681ceb..1df0c3740 100644 --- a/testsuite/bsc.scheduler/sat/ShiftRTest_sat-yices.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sat/ShiftRTest_sat-yices.bsv.bsc-sched-out.expected @@ -52,4 +52,5 @@ Logical execution order: aa, ab, bb Warning: "ShiftRTest_sat-yices.bsv", line 27, column 10: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysShiftRTest.v +Elaborated module file created: sysShiftRTest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sat/TruncateTest_sat-stp.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/TruncateTest_sat-stp.bsv.bsc-sched-out.expected index 2dbe03a13..4e79363ab 100644 --- a/testsuite/bsc.scheduler/sat/TruncateTest_sat-stp.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sat/TruncateTest_sat-stp.bsv.bsc-sched-out.expected @@ -51,4 +51,5 @@ Logical execution order: aa, ab, bb Warning: "TruncateTest_sat-stp.bsv", line 30, column 10: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysAddTest.v +Elaborated module file created: sysAddTest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sat/TruncateTest_sat-yices.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/TruncateTest_sat-yices.bsv.bsc-sched-out.expected index e5dfb0a64..c8263d36a 100644 --- a/testsuite/bsc.scheduler/sat/TruncateTest_sat-yices.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sat/TruncateTest_sat-yices.bsv.bsc-sched-out.expected @@ -51,4 +51,5 @@ Logical execution order: aa, ab, bb Warning: "TruncateTest_sat-yices.bsv", line 30, column 10: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysAddTest.v +Elaborated module file created: sysAddTest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sat/Word64Test_sat-stp.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/Word64Test_sat-stp.bsv.bsc-sched-out.expected index 639a11066..258a0a405 100644 --- a/testsuite/bsc.scheduler/sat/Word64Test_sat-stp.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sat/Word64Test_sat-stp.bsv.bsc-sched-out.expected @@ -47,4 +47,5 @@ Logical execution order: aa, ab, bb Warning: "Word64Test_sat-stp.bsv", line 22, column 10: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysWord64Test.v +Elaborated module file created: sysWord64Test.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sat/Word64Test_sat-yices.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/Word64Test_sat-yices.bsv.bsc-sched-out.expected index cda56dc2c..5ceed8323 100644 --- a/testsuite/bsc.scheduler/sat/Word64Test_sat-yices.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sat/Word64Test_sat-yices.bsv.bsc-sched-out.expected @@ -47,4 +47,5 @@ Logical execution order: aa, ab, bb Warning: "Word64Test_sat-yices.bsv", line 22, column 10: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysWord64Test.v +Elaborated module file created: sysWord64Test.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sat/ZextTest_sat-stp.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/ZextTest_sat-stp.bsv.bsc-sched-out.expected index a494e9f5e..9e2dbca97 100644 --- a/testsuite/bsc.scheduler/sat/ZextTest_sat-stp.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sat/ZextTest_sat-stp.bsv.bsc-sched-out.expected @@ -52,4 +52,5 @@ Logical execution order: aa, ab, bb Warning: "ZextTest_sat-stp.bsv", line 40, column 10: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysZextTest.v +Elaborated module file created: sysZextTest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sat/ZextTest_sat-yices.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sat/ZextTest_sat-yices.bsv.bsc-sched-out.expected index 56e8eebe5..33f14e66e 100644 --- a/testsuite/bsc.scheduler/sat/ZextTest_sat-yices.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sat/ZextTest_sat-yices.bsv.bsc-sched-out.expected @@ -52,4 +52,5 @@ Logical execution order: aa, ab, bb Warning: "ZextTest_sat-yices.bsv", line 40, column 10: (G0021) According to the generated schedule, rule `bb' can never fire. Verilog file created: sysZextTest.v +Elaborated module file created: sysZextTest.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/sbr/SBRCount.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/sbr/SBRCount.bsv.bsc-sched-out.expected index 88d52717d..85da9c8d7 100644 --- a/testsuite/bsc.scheduler/sbr/SBRCount.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/sbr/SBRCount.bsv.bsc-sched-out.expected @@ -60,4 +60,5 @@ Logical execution order: readCount, driveCounter, incCount ========================================== Verilog file created: mkSBRCount.v +Elaborated module file created: mkSBRCount.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/urgency/DUFunction1.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/urgency/DUFunction1.bsv.bsc-sched-out.expected index 04873723f..f1a7febca 100644 --- a/testsuite/bsc.scheduler/urgency/DUFunction1.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/urgency/DUFunction1.bsv.bsc-sched-out.expected @@ -142,4 +142,5 @@ Logical execution order: clearGo, ============================================== Verilog file created: sysDUFunction1.v +Elaborated module file created: sysDUFunction1.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/urgency/DUFunction2.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/urgency/DUFunction2.bsv.bsc-sched-out.expected index 8072a0b2a..a76275d29 100644 --- a/testsuite/bsc.scheduler/urgency/DUFunction2.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/urgency/DUFunction2.bsv.bsc-sched-out.expected @@ -162,4 +162,5 @@ Logical execution order: clearGo, ============================================== Verilog file created: sysDUFunction2.v +Elaborated module file created: sysDUFunction2.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/urgency/DUFunction3.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/urgency/DUFunction3.bsv.bsc-sched-out.expected index 84098fb0a..c8338408a 100644 --- a/testsuite/bsc.scheduler/urgency/DUFunction3.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/urgency/DUFunction3.bsv.bsc-sched-out.expected @@ -142,4 +142,5 @@ Logical execution order: clearGo, ============================================== Verilog file created: sysDUFunction3.v +Elaborated module file created: sysDUFunction3.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/urgency/DUFunction4.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/urgency/DUFunction4.bsv.bsc-sched-out.expected index 92bed1693..a60fc177c 100644 --- a/testsuite/bsc.scheduler/urgency/DUFunction4.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/urgency/DUFunction4.bsv.bsc-sched-out.expected @@ -169,4 +169,5 @@ Logical execution order: clearGo, ============================================== Verilog file created: sysDUFunction4.v +Elaborated module file created: sysDUFunction4.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/urgency/DUFunction6.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/urgency/DUFunction6.bsv.bsc-sched-out.expected index a30991b40..a3e267fcf 100644 --- a/testsuite/bsc.scheduler/urgency/DUFunction6.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/urgency/DUFunction6.bsv.bsc-sched-out.expected @@ -223,4 +223,5 @@ Logical execution order: clearGo, Warning: "DUFunction6.bsv", line 51, column 22: (G0021) According to the generated schedule, rule `x3_1' can never fire. Verilog file created: sysDUFunction6.v +Elaborated module file created: sysDUFunction6.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/urgency/DescendingUrgencyAttribute1.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/urgency/DescendingUrgencyAttribute1.bsv.bsc-sched-out.expected index 177997c82..7a66cfc85 100644 --- a/testsuite/bsc.scheduler/urgency/DescendingUrgencyAttribute1.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/urgency/DescendingUrgencyAttribute1.bsv.bsc-sched-out.expected @@ -37,4 +37,5 @@ Logical execution order: test_rule_1, test_rule_2 Warning: "DescendingUrgencyAttribute1.bsv", line 12, column 8: (G0021) According to the generated schedule, rule `test_rule_2' can never fire. Verilog file created: sysDescendingUrgencyAttribute1.v +Elaborated module file created: sysDescendingUrgencyAttribute1.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/urgency/DescendingUrgencyAttribute2.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/urgency/DescendingUrgencyAttribute2.bsv.bsc-sched-out.expected index f6c385fab..f8cb1e9f4 100644 --- a/testsuite/bsc.scheduler/urgency/DescendingUrgencyAttribute2.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/urgency/DescendingUrgencyAttribute2.bsv.bsc-sched-out.expected @@ -37,4 +37,5 @@ Logical execution order: test_rule_1, test_rule_2 Warning: "DescendingUrgencyAttribute2.bsv", line 8, column 8: (G0021) According to the generated schedule, rule `test_rule_1' can never fire. Verilog file created: sysDescendingUrgencyAttribute2.v +Elaborated module file created: sysDescendingUrgencyAttribute2.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/urgency/DescendingUrgencyAttributeForLoop.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/urgency/DescendingUrgencyAttributeForLoop.bsv.bsc-sched-out.expected index 24e72bf6a..5d058a0a7 100644 --- a/testsuite/bsc.scheduler/urgency/DescendingUrgencyAttributeForLoop.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/urgency/DescendingUrgencyAttributeForLoop.bsv.bsc-sched-out.expected @@ -59,4 +59,5 @@ Warning: "DescendingUrgencyAttributeForLoop.bsv", line 9, column 10: (G0021) Warning: "DescendingUrgencyAttributeForLoop.bsv", line 9, column 10: (G0021) According to the generated schedule, rule `test_rule_2_2' can never fire. Verilog file created: sysDescendingUrgencyAttributeForLoop.v +Elaborated module file created: sysDescendingUrgencyAttributeForLoop.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/urgency/DescendingUrgencyAttributeSplitIf.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/urgency/DescendingUrgencyAttributeSplitIf.bsv.bsc-sched-out.expected index d8442582c..95f91a08d 100644 --- a/testsuite/bsc.scheduler/urgency/DescendingUrgencyAttributeSplitIf.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/urgency/DescendingUrgencyAttributeSplitIf.bsv.bsc-sched-out.expected @@ -57,4 +57,5 @@ Logical execution order: test_rule_2_T_T, Warning: "DescendingUrgencyAttributeSplitIf.bsv", line 14, column 8: (G0021) According to the generated schedule, rule `test_rule_1' can never fire. Verilog file created: sysDescendingUrgencyAttributeSplitIf.v +Elaborated module file created: sysDescendingUrgencyAttributeSplitIf.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/urgency/DescendingUrgencyAttributeSubModule1.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/urgency/DescendingUrgencyAttributeSubModule1.bsv.bsc-sched-out.expected index 7f3e33572..1703bbc2a 100644 --- a/testsuite/bsc.scheduler/urgency/DescendingUrgencyAttributeSubModule1.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/urgency/DescendingUrgencyAttributeSubModule1.bsv.bsc-sched-out.expected @@ -37,4 +37,5 @@ Logical execution order: test_rule_1, m_test_rule_2 Warning: "DescendingUrgencyAttributeSubModule1.bsv", line 18, column 8: (G0021) According to the generated schedule, rule `m_test_rule_2' can never fire. Verilog file created: sysDescendingUrgencyAttributeSubModule1.v +Elaborated module file created: sysDescendingUrgencyAttributeSubModule1.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/urgency/IfcIfcWarning.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/urgency/IfcIfcWarning.bsv.bsc-sched-out.expected index c59b60a6e..65cdfacfb 100644 --- a/testsuite/bsc.scheduler/urgency/IfcIfcWarning.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/urgency/IfcIfcWarning.bsv.bsc-sched-out.expected @@ -42,4 +42,5 @@ Logical execution order: bar, baz ================================================ Verilog file created: sysIfcIfcWarning.v +Elaborated module file created: sysIfcIfcWarning.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/urgency/IfcRuleWarning.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/urgency/IfcRuleWarning.bsv.bsc-sched-out.expected index 7fd50ba94..bab12b6c3 100644 --- a/testsuite/bsc.scheduler/urgency/IfcRuleWarning.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/urgency/IfcRuleWarning.bsv.bsc-sched-out.expected @@ -40,4 +40,5 @@ Logical execution order: bar, baz ================================================= Verilog file created: sysIfcRuleWarning.v +Elaborated module file created: sysIfcRuleWarning.ba All packages are up to date. diff --git a/testsuite/bsc.scheduler/urgency/MinimalRuleWarnings.bsv.bsc-sched-out.expected b/testsuite/bsc.scheduler/urgency/MinimalRuleWarnings.bsv.bsc-sched-out.expected index 98e6b512b..1dd175965 100644 --- a/testsuite/bsc.scheduler/urgency/MinimalRuleWarnings.bsv.bsc-sched-out.expected +++ b/testsuite/bsc.scheduler/urgency/MinimalRuleWarnings.bsv.bsc-sched-out.expected @@ -69,4 +69,5 @@ Logical execution order: theRuleOne, theRuleTwo, theRuleThree, theRuleFour ====================================================== Verilog file created: sysMinimalRuleWarnings.v +Elaborated module file created: sysMinimalRuleWarnings.ba All packages are up to date. diff --git a/testsuite/bsc.typechecker/dontcare/DummyInRuleQual.bs.bsc-vcomp-out.expected b/testsuite/bsc.typechecker/dontcare/DummyInRuleQual.bs.bsc-vcomp-out.expected index fed6dd883..874168584 100644 --- a/testsuite/bsc.typechecker/dontcare/DummyInRuleQual.bs.bsc-vcomp-out.expected +++ b/testsuite/bsc.typechecker/dontcare/DummyInRuleQual.bs.bsc-vcomp-out.expected @@ -58,4 +58,5 @@ clock domain = Just (0), resets = [] ----- Verilog file created: sysDummyInRuleQual.v +Elaborated module file created: sysDummyInRuleQual.ba All packages are up to date. diff --git a/testsuite/bsc.typechecker/instances/MutuallyRecursiveInstances.bsv.bsc-vcomp-out.expected b/testsuite/bsc.typechecker/instances/MutuallyRecursiveInstances.bsv.bsc-vcomp-out.expected index ffe93ff2c..cb91b43f4 100644 --- a/testsuite/bsc.typechecker/instances/MutuallyRecursiveInstances.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.typechecker/instances/MutuallyRecursiveInstances.bsv.bsc-vcomp-out.expected @@ -4,4 +4,5 @@ code generation for sysMutuallyRecursiveInstances starts Compilation message: "MutuallyRecursiveInstances.bsv", line 39, column 18: is_odd(17) PASS Compilation message: "MutuallyRecursiveInstances.bsv", line 45, column 18: is_odd(42) PASS Verilog file created: sysMutuallyRecursiveInstances.v +Elaborated module file created: sysMutuallyRecursiveInstances.ba All packages are up to date. diff --git a/testsuite/bsc.verilog/gen_mode/GenMode.bsv b/testsuite/bsc.verilog/gen_mode/GenMode.bsv new file mode 100644 index 000000000..49fefa338 --- /dev/null +++ b/testsuite/bsc.verilog/gen_mode/GenMode.bsv @@ -0,0 +1,23 @@ +// Fixtures for the -verilog -c codegen mode (.ba -> .v) + +(* synthesize *) +module mkGenSub(Reg#(Bit#(8))); + Reg#(Bit#(8)) rg <- mkReg(0); + return rg; +endmodule + +(* synthesize *) +module mkGenTop(Empty); + Reg#(Bit#(8)) sub <- mkGenSub; + rule bump; + sub <= sub + 1; + endrule +endmodule + +// A module whose elaboration differs by backend (via genC), so its .ba +// records the backend it was elaborated for +(* synthesize *) +module mkGenC(Reg#(Bit#(8))); + Reg#(Bit#(8)) rg <- mkReg(genC ? 1 : 0); + return rg; +endmodule diff --git a/testsuite/bsc.verilog/gen_mode/GenModeTb.bsv b/testsuite/bsc.verilog/gen_mode/GenModeTb.bsv new file mode 100644 index 000000000..d3799c488 --- /dev/null +++ b/testsuite/bsc.verilog/gen_mode/GenModeTb.bsv @@ -0,0 +1,16 @@ +// Testbench: run a design whose submodule .v can be regenerated with -c +import GenMode::*; + +(* synthesize *) +module sysGenModeTb(Empty); + Reg#(Bit#(8)) sub <- mkGenSub; + Reg#(Bit#(4)) n <- mkReg(0); + rule bump; + sub <= sub + 2; + n <= n + 1; + if (n == 5) begin + $display("sub = %0d", sub); + $finish(0); + end + endrule +endmodule diff --git a/testsuite/bsc.verilog/gen_mode/Makefile b/testsuite/bsc.verilog/gen_mode/Makefile new file mode 100644 index 000000000..b953e8132 --- /dev/null +++ b/testsuite/bsc.verilog/gen_mode/Makefile @@ -0,0 +1,5 @@ +# for "make clean" to work everywhere + +CONFDIR = $(realpath ../..) + +include $(CONFDIR)/clean.mk diff --git a/testsuite/bsc.verilog/gen_mode/gen_mode.exp b/testsuite/bsc.verilog/gen_mode/gen_mode.exp new file mode 100644 index 000000000..30f3b6a7c --- /dev/null +++ b/testsuite/bsc.verilog/gen_mode/gen_mode.exp @@ -0,0 +1,90 @@ +# +# Tests for the -c codegen mode with the Verilog backend: +# "bsc -verilog -c M" generates M.v from M.ba, and only M.v (root-only). +# The output is byte-identical to the .v the -g compile produces from the +# same elaboration (the testsuite passes -no-show-timestamps +# -no-show-version, so generated headers are deterministic). +# + +# Check that none of the listed files exist +proc files_dont_exist { filenames } { + global subdir + + incr_stat "files_dont_exist" + + set foundfile "" + foreach filename $filenames { + set fullname [join [concat $subdir $filename] "/" ] + if {[file exists $fullname]} { + set foundfile $filename + break + } + } + + if {$foundfile == ""} { + pass "found none of the files: $filenames" + } else { + fail "file `$foundfile' should not exist" + } +} + +# run "bsc -verilog -c" for a module, expecting success +proc vgen_pass { module { options "" } } { + set output "$module.bsc-vgen-out" + set opts "-no-show-timestamps -no-show-version -verilog -c $module $options" + if [ gen_basic_output $opts $output ] { + pass "-verilog -c $module generates" + } else { + fail "-verilog -c $module should generate" + } +} + +# ------------------------- +# Elaborate a two-level design; -verilog writes .v and .ba for each module + +compile_verilog_pass GenMode.bsv mkGenSub +compile_verilog_pass GenMode.bsv mkGenTop + +# keep the -g output for comparison +copy mkGenSub.v mkGenSub-from-g.v +copy mkGenTop.v mkGenTop-from-g.v + +# ------------------------- +# Regenerate each module's .v from its .ba alone, into a separate +# directory; the result is byte-identical to the -g output, and root-only +# (no other module's files, no link artifacts) + +mkdir gendir +vgen_pass mkGenSub {-vdir gendir} +files_exist { gendir/mkGenSub.v } +files_dont_exist { gendir/mkGenTop.v gendir/mkGenSub.ba mkGenSub.cexe } +compare_file gendir/mkGenSub.v mkGenSub-from-g.v + +mkdir gendir2 +vgen_pass mkGenTop {-vdir gendir2} +files_exist { gendir2/mkGenTop.v } +files_dont_exist { gendir2/mkGenSub.v } +compare_file gendir2/mkGenTop.v mkGenTop-from-g.v + +# ------------------------- +# The regenerated .v is usable in a real design: rebuild the testbench's +# submodule .v with -c and simulate against it + +compile_verilog_pass GenModeTb.bsv sysGenModeTb +erase mkGenSub.v +vgen_pass mkGenSub +files_exist { mkGenSub.v } +if { $vtest == 1 } { + link_verilog_pass {sysGenModeTb.v mkGenSub.v} sysGenModeTb + sim_verilog sysGenModeTb + compare_file sysGenModeTb.out sysGenModeTb.out.expected +} + +# ------------------------- +# A .ba elaborated for the Bluesim backend is rejected by -verilog -c + +if { $ctest == 1 } { + compile_object_pass GenMode.bsv mkGenC + compile_no_source_fail_error "verilog_c_wrong_backend" \ + {-no-show-timestamps -no-show-version -verilog -c mkGenC} S0042 +} diff --git a/testsuite/bsc.verilog/gen_mode/sysGenModeTb.out.expected b/testsuite/bsc.verilog/gen_mode/sysGenModeTb.out.expected new file mode 100644 index 000000000..323459bf0 --- /dev/null +++ b/testsuite/bsc.verilog/gen_mode/sysGenModeTb.out.expected @@ -0,0 +1 @@ +sub = 10 diff --git a/testsuite/bsc.verilog/inout/inout.exp b/testsuite/bsc.verilog/inout/inout.exp index bae45596a..c33f67078 100644 --- a/testsuite/bsc.verilog/inout/inout.exp +++ b/testsuite/bsc.verilog/inout/inout.exp @@ -103,6 +103,10 @@ compile_verilog_fail_error InoutNonbitifiable.bsv T0043 # ========== # Check that Bluesim gives an error on designs with Inout +# (an earlier -verilog compile leaves an up-to-date generic .ba, which the +# -sim compile would reuse, skipping elaboration and these errors; remove +# it so the compile-time errors are still exercised) +erase sysArgToIfc.ba # This gives an error about the Inout Ifc compile_object_fail_error ArgToIfc.bsv G0097 # And about the Inout modarg @@ -110,6 +114,16 @@ if { $ctest == 1 } { find_n_error [make_bsc_ccomp_output_name ArgToIfc.bsv] G0098 1 } +# With an up-to-date generic .ba (here from a -verilog compile), a -sim +# compile reuses it and succeeds; the unsupported-Inout errors then fire +# at the next step, when the .ba is used for linking +if { $ctest == 1 } { + compile_verilog_pass ArgToIfc.bsv + compile_object_pass ArgToIfc.bsv + link_objects_fail_error {} sysArgToIfc G0097 1 + find_n_error [make_bsc_ccomp_output_name sysArgToIfc] G0098 1 +} + # ========== # Test Clock checking diff --git a/testsuite/bsc.verilog/portprops/InHigh.bsv.bsc-vcomp-out.expected b/testsuite/bsc.verilog/portprops/InHigh.bsv.bsc-vcomp-out.expected index c8b492dde..86a6d56f1 100644 --- a/testsuite/bsc.verilog/portprops/InHigh.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.verilog/portprops/InHigh.bsv.bsc-vcomp-out.expected @@ -11,6 +11,7 @@ RST_N I 1 unused ----- Verilog file created: mkSub.v +Elaborated module file created: mkSub.ba code generation for mkTop starts Warning: "InHigh.bsv", line 26, column 11: (G0015) Instance `s' requires the following method to be always enabled, but the @@ -31,6 +32,7 @@ EN_start I 1 inhigh ----- Verilog file created: mkTop.v +Elaborated module file created: mkTop.ba code generation for mkTest1 starts Warning: "InHigh.bsv", line 41, column 11: (G0015) Instance `t' requires the following method to be always enabled, but the @@ -47,6 +49,7 @@ RST_N I 1 reset ----- Verilog file created: mkTest1.v +Elaborated module file created: mkTest1.ba code generation for mkTest2 starts Warning: "InHigh.bsv", line 51, column 11: (G0015) Instance `t' requires the following method to be always enabled, but the @@ -63,4 +66,5 @@ RST_N I 1 reset ----- Verilog file created: mkTest2.v +Elaborated module file created: mkTest2.ba All packages are up to date. diff --git a/testsuite/bsc.verilog/portprops/InoutProps_ArgToIfc.bsv.bsc-vcomp-out.expected b/testsuite/bsc.verilog/portprops/InoutProps_ArgToIfc.bsv.bsc-vcomp-out.expected index f09d9c4e6..652fa55c7 100644 --- a/testsuite/bsc.verilog/portprops/InoutProps_ArgToIfc.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.verilog/portprops/InoutProps_ArgToIfc.bsv.bsc-vcomp-out.expected @@ -12,4 +12,5 @@ io_ifc IO 32 inout ----- Verilog file created: sysInoutProps_ArgToIfc.v +Elaborated module file created: sysInoutProps_ArgToIfc.ba All packages are up to date. diff --git a/testsuite/bsc.verilog/portprops/InoutProps_BVIArg.bsv.bsc-vcomp-out.expected b/testsuite/bsc.verilog/portprops/InoutProps_BVIArg.bsv.bsc-vcomp-out.expected index 5f1751122..c7493435e 100644 --- a/testsuite/bsc.verilog/portprops/InoutProps_BVIArg.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.verilog/portprops/InoutProps_BVIArg.bsv.bsc-vcomp-out.expected @@ -11,4 +11,5 @@ io_arg IO 32 inout ----- Verilog file created: sysInoutProps_BVIArg.v +Elaborated module file created: sysInoutProps_BVIArg.ba All packages are up to date. diff --git a/testsuite/bsc.verilog/portprops/InoutProps_BVIIfc.bsv.bsc-vcomp-out.expected b/testsuite/bsc.verilog/portprops/InoutProps_BVIIfc.bsv.bsc-vcomp-out.expected index a70083359..ee963327e 100644 --- a/testsuite/bsc.verilog/portprops/InoutProps_BVIIfc.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.verilog/portprops/InoutProps_BVIIfc.bsv.bsc-vcomp-out.expected @@ -11,4 +11,5 @@ io_ifc IO 32 inout ----- Verilog file created: sysInoutProps_BVIIfc.v +Elaborated module file created: sysInoutProps_BVIIfc.ba All packages are up to date. diff --git a/testsuite/bsc.verilog/portprops/InoutProps_UnusedArg.bsv.bsc-vcomp-out.expected b/testsuite/bsc.verilog/portprops/InoutProps_UnusedArg.bsv.bsc-vcomp-out.expected index f430f4040..e86a55efc 100644 --- a/testsuite/bsc.verilog/portprops/InoutProps_UnusedArg.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.verilog/portprops/InoutProps_UnusedArg.bsv.bsc-vcomp-out.expected @@ -11,4 +11,5 @@ io_arg IO 32 unused ----- Verilog file created: sysInoutProps_UnusedArg.v +Elaborated module file created: sysInoutProps_UnusedArg.ba All packages are up to date. diff --git a/testsuite/bsc.verilog/portprops/InoutProps_UnusedArgBVI.bsv.bsc-vcomp-out.expected b/testsuite/bsc.verilog/portprops/InoutProps_UnusedArgBVI.bsv.bsc-vcomp-out.expected index 195e029d9..345034157 100644 --- a/testsuite/bsc.verilog/portprops/InoutProps_UnusedArgBVI.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.verilog/portprops/InoutProps_UnusedArgBVI.bsv.bsc-vcomp-out.expected @@ -11,4 +11,5 @@ io_arg IO 32 inout ----- Verilog file created: sysInoutProps_UnusedArgBVI.v +Elaborated module file created: sysInoutProps_UnusedArgBVI.ba All packages are up to date. diff --git a/testsuite/bsc.verilog/portprops/InputArg_ConcatReg.bsv.bsc-vcomp-out.expected b/testsuite/bsc.verilog/portprops/InputArg_ConcatReg.bsv.bsc-vcomp-out.expected index 130c38e49..c72be88dd 100644 --- a/testsuite/bsc.verilog/portprops/InputArg_ConcatReg.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.verilog/portprops/InputArg_ConcatReg.bsv.bsc-vcomp-out.expected @@ -11,4 +11,5 @@ RST_N I 1 reset ----- Verilog file created: sysInputArg_ConcatReg.v +Elaborated module file created: sysInputArg_ConcatReg.ba All packages are up to date. diff --git a/testsuite/bsc.verilog/portprops/InputArg_ExtractRegAndUnused.bsv.bsc-vcomp-out.expected b/testsuite/bsc.verilog/portprops/InputArg_ExtractRegAndUnused.bsv.bsc-vcomp-out.expected index 3202de3c1..4d64af51a 100644 --- a/testsuite/bsc.verilog/portprops/InputArg_ExtractRegAndUnused.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.verilog/portprops/InputArg_ExtractRegAndUnused.bsv.bsc-vcomp-out.expected @@ -11,4 +11,5 @@ RST_N I 1 reset ----- Verilog file created: sysInputArg_ExtractRegAndUnused.v +Elaborated module file created: sysInputArg_ExtractRegAndUnused.ba All packages are up to date. diff --git a/testsuite/bsc.verilog/portprops/InputArg_OneReg.bsv.bsc-vcomp-out.expected b/testsuite/bsc.verilog/portprops/InputArg_OneReg.bsv.bsc-vcomp-out.expected index 0471ed583..f96d31736 100644 --- a/testsuite/bsc.verilog/portprops/InputArg_OneReg.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.verilog/portprops/InputArg_OneReg.bsv.bsc-vcomp-out.expected @@ -11,4 +11,5 @@ RST_N I 1 reset ----- Verilog file created: sysInputArg_OneReg.v +Elaborated module file created: sysInputArg_OneReg.ba All packages are up to date. diff --git a/testsuite/bsc.verilog/portprops/InputArg_OneRegOneLogicReg.bsv.bsc-vcomp-out.expected b/testsuite/bsc.verilog/portprops/InputArg_OneRegOneLogicReg.bsv.bsc-vcomp-out.expected index fe46c6170..1deef8331 100644 --- a/testsuite/bsc.verilog/portprops/InputArg_OneRegOneLogicReg.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.verilog/portprops/InputArg_OneRegOneLogicReg.bsv.bsc-vcomp-out.expected @@ -11,4 +11,5 @@ RST_N I 1 reset ----- Verilog file created: sysInputArg_OneReg.v +Elaborated module file created: sysInputArg_OneReg.ba All packages are up to date. diff --git a/testsuite/bsc.verilog/portprops/InputArg_OneRegOneUnused.bsv.bsc-vcomp-out.expected b/testsuite/bsc.verilog/portprops/InputArg_OneRegOneUnused.bsv.bsc-vcomp-out.expected index cffaa2657..2622d9233 100644 --- a/testsuite/bsc.verilog/portprops/InputArg_OneRegOneUnused.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.verilog/portprops/InputArg_OneRegOneUnused.bsv.bsc-vcomp-out.expected @@ -13,6 +13,7 @@ EN_m I 1 unused ----- Verilog file created: mkInputArg_OneRegOneUnused_Sub.v +Elaborated module file created: mkInputArg_OneRegOneUnused_Sub.ba code generation for sysInputArg_OneRegOneUnused starts === IOproperties (InputArg_OneRegOneUnused sysInputArg_OneRegOneUnused): Name I/O size props @@ -24,4 +25,5 @@ RST_N I 1 reset ----- Verilog file created: sysInputArg_OneRegOneUnused.v +Elaborated module file created: sysInputArg_OneRegOneUnused.ba All packages are up to date. diff --git a/testsuite/bsc.verilog/portprops/InputArg_TwoReg.bsv.bsc-vcomp-out.expected b/testsuite/bsc.verilog/portprops/InputArg_TwoReg.bsv.bsc-vcomp-out.expected index bb2d96363..ff244cf15 100644 --- a/testsuite/bsc.verilog/portprops/InputArg_TwoReg.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.verilog/portprops/InputArg_TwoReg.bsv.bsc-vcomp-out.expected @@ -11,4 +11,5 @@ RST_N I 1 reset ----- Verilog file created: sysInputArg_TwoReg.v +Elaborated module file created: sysInputArg_TwoReg.ba All packages are up to date. diff --git a/testsuite/bsc.verilog/portprops/InputArg_Unused.bsv.bsc-vcomp-out.expected b/testsuite/bsc.verilog/portprops/InputArg_Unused.bsv.bsc-vcomp-out.expected index f9dd5546a..4e51911dc 100644 --- a/testsuite/bsc.verilog/portprops/InputArg_Unused.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.verilog/portprops/InputArg_Unused.bsv.bsc-vcomp-out.expected @@ -11,4 +11,5 @@ RST_N I 1 unused ----- Verilog file created: sysInputArg_Unused.v +Elaborated module file created: sysInputArg_Unused.ba All packages are up to date. diff --git a/testsuite/bsc.verilog/portprops/InputGate_OnlyInMethodReady.bsv.bsc-vcomp-out.expected b/testsuite/bsc.verilog/portprops/InputGate_OnlyInMethodReady.bsv.bsc-vcomp-out.expected index 927a7c560..d84056a64 100644 --- a/testsuite/bsc.verilog/portprops/InputGate_OnlyInMethodReady.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.verilog/portprops/InputGate_OnlyInMethodReady.bsv.bsc-vcomp-out.expected @@ -14,4 +14,5 @@ EN_set I 1 ----- Verilog file created: sysInputGate_OnlyInMethodReady.v +Elaborated module file created: sysInputGate_OnlyInMethodReady.ba All packages are up to date. diff --git a/testsuite/bsc.verilog/portprops/MethodArg_OneReg.bsv.bsc-vcomp-out.expected b/testsuite/bsc.verilog/portprops/MethodArg_OneReg.bsv.bsc-vcomp-out.expected index a267c525d..73d89573a 100644 --- a/testsuite/bsc.verilog/portprops/MethodArg_OneReg.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.verilog/portprops/MethodArg_OneReg.bsv.bsc-vcomp-out.expected @@ -13,4 +13,5 @@ EN_m I 1 ----- Verilog file created: sysMethodArg_OneReg.v +Elaborated module file created: sysMethodArg_OneReg.ba All packages are up to date. diff --git a/testsuite/bsc.verilog/portprops/MethodValue_ConcatRegAndConst.bsv.bsc-vcomp-out.expected b/testsuite/bsc.verilog/portprops/MethodValue_ConcatRegAndConst.bsv.bsc-vcomp-out.expected index 0ac143817..ff9099a23 100644 --- a/testsuite/bsc.verilog/portprops/MethodValue_ConcatRegAndConst.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.verilog/portprops/MethodValue_ConcatRegAndConst.bsv.bsc-vcomp-out.expected @@ -12,4 +12,5 @@ RST_N I 1 reset ----- Verilog file created: sysMethodValue_ConcatRegAndConst.v +Elaborated module file created: sysMethodValue_ConcatRegAndConst.ba All packages are up to date. diff --git a/testsuite/bsc.verilog/portprops/MethodValue_ConcatRegAndLogic.bsv.bsc-vcomp-out.expected b/testsuite/bsc.verilog/portprops/MethodValue_ConcatRegAndLogic.bsv.bsc-vcomp-out.expected index d9b3c42c3..9ccb975f8 100644 --- a/testsuite/bsc.verilog/portprops/MethodValue_ConcatRegAndLogic.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.verilog/portprops/MethodValue_ConcatRegAndLogic.bsv.bsc-vcomp-out.expected @@ -12,4 +12,5 @@ RST_N I 1 reset ----- Verilog file created: sysMethodValue_ConcatRegAndLogic.v +Elaborated module file created: sysMethodValue_ConcatRegAndLogic.ba All packages are up to date. diff --git a/testsuite/bsc.verilog/portprops/MethodValue_ConcatTwoReg.bsv.bsc-vcomp-out.expected b/testsuite/bsc.verilog/portprops/MethodValue_ConcatTwoReg.bsv.bsc-vcomp-out.expected index d345ab8af..516097899 100644 --- a/testsuite/bsc.verilog/portprops/MethodValue_ConcatTwoReg.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.verilog/portprops/MethodValue_ConcatTwoReg.bsv.bsc-vcomp-out.expected @@ -12,4 +12,5 @@ RST_N I 1 reset ----- Verilog file created: sysMethodValue_ConcatTwoReg.v +Elaborated module file created: sysMethodValue_ConcatTwoReg.ba All packages are up to date. diff --git a/testsuite/bsc.verilog/portprops/MethodValue_Const.bsv.bsc-vcomp-out.expected b/testsuite/bsc.verilog/portprops/MethodValue_Const.bsv.bsc-vcomp-out.expected index 10ccd30e7..486eaa4c5 100644 --- a/testsuite/bsc.verilog/portprops/MethodValue_Const.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.verilog/portprops/MethodValue_Const.bsv.bsc-vcomp-out.expected @@ -12,4 +12,5 @@ RST_N I 1 unused ----- Verilog file created: sysMethodValue_Const.v +Elaborated module file created: sysMethodValue_Const.ba All packages are up to date. diff --git a/testsuite/bsc.verilog/portprops/MethodValue_ExtractReg.bsv.bsc-vcomp-out.expected b/testsuite/bsc.verilog/portprops/MethodValue_ExtractReg.bsv.bsc-vcomp-out.expected index 24def84cf..f759f7bdc 100644 --- a/testsuite/bsc.verilog/portprops/MethodValue_ExtractReg.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.verilog/portprops/MethodValue_ExtractReg.bsv.bsc-vcomp-out.expected @@ -12,4 +12,5 @@ RST_N I 1 reset ----- Verilog file created: sysMethodValue_ExtractReg.v +Elaborated module file created: sysMethodValue_ExtractReg.ba All packages are up to date. diff --git a/testsuite/bsc.verilog/portprops/MethodValue_Logic.bsv.bsc-vcomp-out.expected b/testsuite/bsc.verilog/portprops/MethodValue_Logic.bsv.bsc-vcomp-out.expected index c762479d4..8f1e8bd5c 100644 --- a/testsuite/bsc.verilog/portprops/MethodValue_Logic.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.verilog/portprops/MethodValue_Logic.bsv.bsc-vcomp-out.expected @@ -12,4 +12,5 @@ RST_N I 1 reset ----- Verilog file created: sysMethodValue_Logic.v +Elaborated module file created: sysMethodValue_Logic.ba All packages are up to date. diff --git a/testsuite/bsc.verilog/portprops/MethodValue_OneReg.bsv.bsc-vcomp-out.expected b/testsuite/bsc.verilog/portprops/MethodValue_OneReg.bsv.bsc-vcomp-out.expected index e5b87d4a3..f90fa0e41 100644 --- a/testsuite/bsc.verilog/portprops/MethodValue_OneReg.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.verilog/portprops/MethodValue_OneReg.bsv.bsc-vcomp-out.expected @@ -12,4 +12,5 @@ RST_N I 1 reset ----- Verilog file created: sysMethodValue_OneReg.v +Elaborated module file created: sysMethodValue_OneReg.ba All packages are up to date. diff --git a/testsuite/bsc.verilog/portprops/OutputClockAndReset.bsv.bsc-vcomp-out.expected b/testsuite/bsc.verilog/portprops/OutputClockAndReset.bsv.bsc-vcomp-out.expected index a51c3e350..d0ff1be79 100644 --- a/testsuite/bsc.verilog/portprops/OutputClockAndReset.bsv.bsc-vcomp-out.expected +++ b/testsuite/bsc.verilog/portprops/OutputClockAndReset.bsv.bsc-vcomp-out.expected @@ -13,4 +13,5 @@ RST_N I 1 reset ----- Verilog file created: sysOutputClockAndReset.v +Elaborated module file created: sysOutputClockAndReset.ba All packages are up to date. diff --git a/testsuite/config/unix.exp b/testsuite/config/unix.exp index a779ba7f8..af7ab3ce0 100644 --- a/testsuite/config/unix.exp +++ b/testsuite/config/unix.exp @@ -1230,6 +1230,30 @@ proc bsc_link_objects { objects toplevel { options "" } } { return [expr $status == 0] } +# -sim -c codegen (generate a module's code from its elaborated .ba file) +# returns true iff code generation succeeded for all modules +proc bsc_gen_modules { modules { options "" } } { + global bsc + global srcdir + global subdir + + bsc_initialize + + set here [absolute $srcdir] + cd [file join $here $subdir] + set ok 1 + foreach mod $modules { + set output [make_bsc_ccomp_output_name $mod] + set gen_options "-no-show-timestamps -no-show-version -sim -c $mod" + set cmd "$bsc $gen_options $options >& $output" + verbose "Executing: $cmd" 4 + set status [exec_with_log "bsc_gen_modules" $cmd 2] + if { $status != 0 } { set ok 0 } + } + cd $here + return $ok +} + # -verilog -u compile # returns true iff compilation succeeded proc bsc_compile_verilog { source { module "" } { options "" } } { @@ -1837,6 +1861,21 @@ proc link_objects_pass { objects toplevel {options ""}} { } } +# generate code for modules from their .ba files (-sim -c) +proc gen_modules_pass { modules {options ""}} { + global ctest + + if {$ctest == 1} { + incr_stat "gen_modules_pass" + + if [bsc_gen_modules $modules $options] then { + pass "`$modules' generate code" + } else { + fail "`$modules' should generate code" + } + } +} + # create a simulation executable using C outputs proc link_objects_fail { objects toplevel {options ""}} { global ctest @@ -2951,10 +2990,60 @@ proc test_c_veri_worker_int { top sysmod modules extension doC doV gen_options l erase $sysmod.c.vcd } + + # Each bsc-generated submodule's Bluesim C++ must be identical whether + # it is generated as part of this design or on its own with + # the -c codegen mode, so the object can be generated/compiled once and + # shared across simulations (and reused by the dependency analysis). + if { [llength $modules] > 0 } { + check_block_codegen_modules $modules $link_options + } } } +# For each bsc-generated submodule, regenerate its Bluesim C++ on its own with +# the -c codegen mode and confirm it is byte-identical to the version generated +# as part of building the enclosing design (which the caller has just built, so +# the per-module files are present in the test directory). Source-only: +# byte-identity makes compiling or simulating the -c output unnecessary. +proc check_block_codegen_modules { modules link_options } { + global srcdir + global subdir + # -show-timestamps embeds the wall-clock time, and -show-version the build + # version, into the generated files. Those legitimately differ between two + # separate bsc invocations, so byte-identity is not expected when they are + # requested; skip the check in that case. + if { [regexp -- {-show-(timestamps|version)} $link_options] } { + return + } + set here [absolute $srcdir] + foreach mod $modules { + # only handle bsc-generated modules: a bare module name or an explicit + # ".ba". Skip anything else in the module list (pre-built objects, + # C/C++ sources, etc.). + set ext [file extension $mod] + if { ($ext != "") && ($ext != ".ba") } { continue } + set modname [file rootname $mod] + set bcgdir "blockcg_$modname" + mkdir $bcgdir + # Use bsc_gen_modules directly (not gen_modules_pass) so that entries + # which cannot stand alone as a -c root -- e.g. an imported "BDPI" + # function rather than a synthesized submodule -- are silently + # skipped rather than reported as failures. (Elaboration-affecting + # options are already baked into the .ba that -c reads, so they need + # not be replayed here.) + if { [bsc_gen_modules [list $modname] "-simdir $bcgdir"] && \ + [file exists [file join $here $subdir $modname.cxx]] && \ + [file exists [file join $here $subdir $bcgdir $modname.cxx]] } { + compare_file $bcgdir/$modname.cxx $modname.cxx "check_block_codegen" + compare_file $bcgdir/$modname.h $modname.h "check_block_codegen" + } + # remove the scratch directory (so no per-test cleanup rule is needed) + file delete -force [file join $here $subdir $bcgdir] + } +} + proc check_verilog_output { output expected veribug } { global verilog_compiler