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    <div class="header-inner"><a class="wordmark" href="#top">Wei-Kuan Chiang</a><div class="header-actions"><button class="menu-toggle" type="button" aria-expanded="false" aria-controls="main-navigation" aria-label="Open navigation"><span></span><span></span><span></span></button><nav id="main-navigation" aria-label="Main navigation"><a href="#about">About</a><a href="#publications">Publications</a><a href="experience.html">Experience</a><a href="honors.html">Honors</a></nav><a class="cv-button" href="assets/Wei-Kuan-Chiang-CV.pdf" download>CV <span aria-hidden="true">↓</span></a><button class="theme-toggle" type="button" aria-label="Switch to dark mode" title="Switch color theme"><span aria-hidden="true"></span></button></div></div>
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      <img class="avatar" src="assets/profile.png" alt="Portrait of Wei-Kuan Chiang">
      <h1>Wei-Kuan Chiang</h1><p class="english-name">Researcher · Engineer</p>
      <p class="role">MSc Advanced Computer Science<br>The University of Manchester</p>
      <p class="location">Manchester, United Kingdom</p>
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        <a href="#publications"><b>Research areas</b><span>Machine Learning · ML Systems · AI Systems · Edge AI</span></a>
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      <div class="availability"><i></i><span>Open to research collaboration</span></div>
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    <div class="main-column">
      <section id="about" class="intro section-block">
        <p class="kicker">ABOUT ME</p>
        <h2>Stay curious.<br><em>Build with purpose.</em></h2>
        <p>I am Wei-Kuan Chiang, a Computer Science graduate from Yuan Ze University and an incoming MSc Advanced Computer Science student at <strong>The University of Manchester</strong>. My research focuses on <strong>memory reliability, RTL/FPGA design, edge AI, and intelligent systems</strong>. Through an NSTC undergraduate research project, I have worked across the full research pipeline—from test algorithms and hardware architecture to fault injection and on-device FPGA validation.</p>
        <p>I also develop real-time AI and software systems in industry, integrating speech interaction, visual perception, streaming, and model inference. These experiences shaped a simple principle behind my work: technology should not only succeed in a paper; it should be deployable, useful, and accountable in the real world.</p>
        <p>At Manchester, I plan to deepen my work in machine learning, software engineering, and distributed systems while continuing to turn research ideas into reliable deployed systems.</p>
        <div class="interests" aria-label="Research interests"><span>Machine Learning</span><span>ML Systems</span><span>Memory Reliability</span><span>RTL / FPGA</span><span>Edge AI</span><span>AI Systems</span></div>
      </section>

      <section id="news" class="section-block">
        <div class="section-title"><h2>News</h2><span>SELECTED UPDATES</span></div>
        <ul class="news-list">
          <li><time>2026.09</time><p>Beginning the <strong>MSc Advanced Computer Science</strong> programme at The University of Manchester.</p></li>
          <li><time>2026.01</time><p>Received the <strong>Yuan Ze University Academic Gold Award</strong> for outstanding academic and research performance.</p></li>
          <li><time>2025.10</time><p>Received the <strong>Outstanding Paper Award</strong> at TANET & NCS 2025.</p></li>
          <li><time>2025</time><p>Completed FPGA validation and PPA analysis for an NSTC project on an optimized March mSR+ memory BIST architecture.</p></li>
          <li><time>2025</time><p>Published research in <strong>IEEE Transactions on VLSI Systems</strong>.</p></li>
        </ul>
      </section>

      <section id="publications" class="section-block">
        <div class="section-title"><h2>Publications</h2><a href="https://scholar.google.com/citations?user=nb5-cyQAAAAJ" target="_blank" rel="noopener noreferrer">Google Scholar ↗</a></div>
        <article class="publication">
          <div class="pub-visual llm-rtl" aria-hidden="true"><span>RTL</span><i></i><b>LLM</b></div>
          <div class="pub-content"><p class="venue">MLMI · 2026</p><h3>Parameter-Efficient Fine-Tuning for Functional RTL Debugging with Large Language Models</h3><p class="authors"><strong>Wei-Kuan Chiang</strong> et al.</p></div>
        </article>
        <article class="publication featured-publication">
          <div class="pub-visual memory" aria-hidden="true"><div class="chip"><span></span><span></span><span></span><span></span><b>BIST</b></div></div>
          <div class="pub-content"><p class="venue">IEEE TVLSI · 2025</p><h3>Enhancing Memory BIST with an Optimized RTL-BIST IP Core: A Low-Power, High-Fault-Coverage Approach</h3><p class="authors">M. Y. Lin, <strong>W. K. Chiang</strong>, and C. H. Wang</p><p class="abstract">A low-power, high-fault-coverage RTL-BIST IP core designed to improve the efficiency and reliability of embedded memory testing.</p><div class="pub-links"><a href="https://doi.org/10.1109/TVLSI.2025.3581296" target="_blank" rel="noopener noreferrer">Paper</a><a href="https://ieeexplore.ieee.org/document/11053774" target="_blank" rel="noopener noreferrer">IEEE Xplore</a></div></div>
        </article>
        <article class="publication">
          <div class="pub-visual network" aria-hidden="true"><i></i><i></i><i></i><i></i><i></i></div>
          <div class="pub-content"><p class="venue">ICRAS · 2025</p><h3>Optimized Memory Reliability Solutions for AI-Driven Automation Systems</h3><p class="authors">Rung-Bin Lin, <strong>Wei-Kuan Chiang</strong>, Chin-Hung Wang, Po-Yu Chuang, Che-Chi Li, Chen-Pei Hsu, and Ming-Yi Lin</p><p class="abstract">A memory-reliability solution for AI-driven automation systems, integrating testing, fault analysis, and hardware validation.</p><div class="pub-links"><a href="https://doi.org/10.1109/ICRAS65818.2025.11108937" target="_blank" rel="noopener noreferrer">Paper</a><a href="https://ieeexplore.ieee.org/document/11108937" target="_blank" rel="noopener noreferrer">IEEE Xplore</a></div></div>
        </article>
        <article class="publication">
          <div class="pub-visual cnn" aria-hidden="true"><span></span><span></span><span></span><b>CNN</b></div>
          <div class="pub-content"><p class="venue">ITAOI · 2025</p><h3>Design and Application of FPGA-Accelerated Convolutional Neural Networks Based on the PYNQ-Z2 Platform</h3><p class="authors"><strong>Wei-Kuan Chiang</strong> et al.</p></div>
        </article>
        <article class="publication">
          <div class="pub-visual vision" aria-hidden="true"><span></span><b>YOLO</b><i></i></div>
          <div class="pub-content"><p class="venue">ITAOI · 2025</p><h3>Improving YOLO Efficiency in Edge Computing via Hardware Acceleration and Quantization Techniques</h3><p class="authors"><strong>Wei-Kuan Chiang</strong> et al.</p></div>
        </article>
        <article class="publication">
          <div class="pub-visual march" aria-hidden="true"><span>C−</span><i></i><i></i><i></i><i></i></div>
          <div class="pub-content"><p class="venue">TANET &amp; NCS · 2025</p><h3>Design of an SRAM and OTP Built-In Self-Test Architecture Based on the March C- Enhanced Algorithm</h3><p class="authors"><strong>Wei-Kuan Chiang</strong> et al.</p></div>
        </article>
        <article class="publication">
          <div class="pub-visual waveform" aria-hidden="true"><span></span></div>
          <div class="pub-content"><p class="venue">TANET & NCS · 2025 · OUTSTANDING PAPER AWARD</p><h3>Self-Repairing BISR Memory Architecture Integrating BIST and OTP</h3><p class="authors"><strong>Wei-Kuan Chiang</strong> et al.</p><p class="abstract">A hardware architecture that combines built-in self-test with OTP redundancy information for memory fault localization and self-repair.</p><div class="pub-links"><span>Award Paper</span></div></div>
        </article>
      </section>

      <section id="projects" class="section-block">
        <div class="section-title"><h2>Research &amp; Projects</h2><span>SELECTED GITHUB WORK</span></div>
        <p class="projects-intro">A focused selection of systems that best represents my work across interpretable machine learning, deployable AI, and human-centred software.</p>
        <div class="projects">
          <article class="project-featured"><div class="project-topline"><p class="project-index">01 · INTERPRETABLE ML</p><a href="https://github.com/mark2146/ecg-stress-analysis" target="_blank" rel="noopener noreferrer">GitHub ↗</a></div><h3>ECG Stress Analysis</h3><p>An end-to-end research pipeline for stress classification from WESAD ECG signals: sliding-window HRV extraction, subject-wise cross-validation, Random Forest modelling, SHAP explanations, and a local dashboard that turns model outputs into reviewable reports.</p><ul><li>Python</li><li>Scikit-learn</li><li>SHAP</li><li>Flask</li><li>Ollama</li></ul></article>
          <article><div class="project-topline"><p class="project-index">02 · DEPLOYED GENERATIVE AI</p><span>Private industry project</span></div><h3>AI Wine Cabinet</h3><p>A voice-first interactive AI installation combining retrieval, speech understanding, response generation, and coordinated multimedia playback for an in-person user experience.</p><ul><li>Generative AI</li><li>Retrieval</li><li>Speech AI</li><li>Interactive System</li></ul></article>
          <article><div class="project-topline"><p class="project-index">03 · HUMAN-CENTRED SYSTEM</p><a href="https://github.com/mark2146/pet_farm" target="_blank" rel="noopener noreferrer">GitHub ↗</a></div><h3>Pet Farm — Family Care Platform</h3><p>A gamified family-care application that turns daily check-ins, shared tasks, reflective prompts, and private photo memories into a collaborative virtual-farm experience.</p><ul><li>Flask</li><li>PostgreSQL</li><li>OAuth</li><li>Gamification</li><li>Privacy-aware Design</li></ul></article>
        </div>
      </section>

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