Intel APX Support

[ds5678]

E20260307 23:45:28.976652 28932 InstructionLifter.cpp:321] Could not locate variable or register R18B
E20260307 23:45:28.979655 28932 InstructionLifter.cpp:321] Could not locate variable or register R18B
E20260307 23:45:28.980881 28932 InstructionLifter.cpp:321] Could not locate variable or register R20B
E20260307 23:45:28.982267 28932 InstructionLifter.cpp:321] Could not locate variable or register R22
E20260307 23:46:19.024295 28932 InstructionLifter.cpp:321] Could not locate variable or register R25B
E20260307 23:46:20.086778 28932 InstructionLifter.cpp:321] Could not locate variable or register R26B
E20260307 23:46:20.498807 28932 InstructionLifter.cpp:321] Could not locate variable or register R17B

Intel APX (Advanced Performance Extensions) doubles the number of general-purpose registers (GPRs) in x86-64 from 16 to 32.

I'm willing to work on this, but might need some guidance.

[kyle-elliott-tob]

This would likely require an extension for the macro used to define a majority of the x86 instruction handlers, as it's not just an addition to the amount of GPRs but also the fact that certain instructions will no longer affect flags. If anyone (or you) is serious about tackling this, it would be best to be done in three stages.

1. Extend the x86 state with additional GPRs, wrapped in an additional define like the avx/avx512 extensions
2. Rework the macros for defining x86 instruction handlers to optionally suppress flag writes. This will be a large change, and will necessitate some thinking as to how to elegantly handle this, as duplicating handlers with and without flags would be ugly
3. Investigate the x86 ghidra integration (low priority as I think very few of the x86 consumers of remill utilize the pcode integration over the manually defined semantics)