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3157 lines (2742 loc) · 234 KB
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\ STM32F103xx Register Bitfield Definitions for Mecrisp-Stellaris Forth by Matthias Koch.
\ bitfield.xsl takes STM32Fxx.svd, config.xml and produces bitfield.fs
\ Written by Terry Porter "terry@tjporter.com.au" 2016 - 2018 and released under the GPL V2.
\ Replace 'bis!' (set bit) with 'bic!' to CLEAR bit, 'bit@' to test bit etc.
\ FSMC-BCR1 (read-write)
: FSMC-BCR1_CBURSTRW %1 19 lshift FSMC-BCR1 bis! ; \ FSMC-BCR1_CBURSTRW CBURSTRW
: FSMC-BCR1_ASYNCWAIT %1 15 lshift FSMC-BCR1 bis! ; \ FSMC-BCR1_ASYNCWAIT ASYNCWAIT
: FSMC-BCR1_EXTMOD %1 14 lshift FSMC-BCR1 bis! ; \ FSMC-BCR1_EXTMOD EXTMOD
: FSMC-BCR1_WAITEN %1 13 lshift FSMC-BCR1 bis! ; \ FSMC-BCR1_WAITEN WAITEN
: FSMC-BCR1_WREN %1 12 lshift FSMC-BCR1 bis! ; \ FSMC-BCR1_WREN WREN
: FSMC-BCR1_WAITCFG %1 11 lshift FSMC-BCR1 bis! ; \ FSMC-BCR1_WAITCFG WAITCFG
: FSMC-BCR1_WAITPOL %1 9 lshift FSMC-BCR1 bis! ; \ FSMC-BCR1_WAITPOL WAITPOL
: FSMC-BCR1_BURSTEN %1 8 lshift FSMC-BCR1 bis! ; \ FSMC-BCR1_BURSTEN BURSTEN
: FSMC-BCR1_FACCEN %1 6 lshift FSMC-BCR1 bis! ; \ FSMC-BCR1_FACCEN FACCEN
: FSMC-BCR1_MWID ( %XX -- ) 4 lshift FSMC-BCR1 bis! ; \ FSMC-BCR1_MWID MWID
: FSMC-BCR1_MTYP ( %XX -- ) 2 lshift FSMC-BCR1 bis! ; \ FSMC-BCR1_MTYP MTYP
: FSMC-BCR1_MUXEN %1 1 lshift FSMC-BCR1 bis! ; \ FSMC-BCR1_MUXEN MUXEN
: FSMC-BCR1_MBKEN %1 0 lshift FSMC-BCR1 bis! ; \ FSMC-BCR1_MBKEN MBKEN
\ FSMC-BTR1 (read-write)
: FSMC-BTR1_ACCMOD ( %XX -- ) 28 lshift FSMC-BTR1 bis! ; \ FSMC-BTR1_ACCMOD ACCMOD
: FSMC-BTR1_DATLAT ( %XXXX -- ) 24 lshift FSMC-BTR1 bis! ; \ FSMC-BTR1_DATLAT DATLAT
: FSMC-BTR1_CLKDIV ( %XXXX -- ) 20 lshift FSMC-BTR1 bis! ; \ FSMC-BTR1_CLKDIV CLKDIV
: FSMC-BTR1_BUSTURN ( %XXXX -- ) 16 lshift FSMC-BTR1 bis! ; \ FSMC-BTR1_BUSTURN BUSTURN
: FSMC-BTR1_DATAST ( %XXXXXXXX -- ) 8 lshift FSMC-BTR1 bis! ; \ FSMC-BTR1_DATAST DATAST
: FSMC-BTR1_ADDHLD ( %XXXX -- ) 4 lshift FSMC-BTR1 bis! ; \ FSMC-BTR1_ADDHLD ADDHLD
: FSMC-BTR1_ADDSET ( %XXXX -- ) 0 lshift FSMC-BTR1 bis! ; \ FSMC-BTR1_ADDSET ADDSET
\ FSMC-BCR2 (read-write)
: FSMC-BCR2_CBURSTRW %1 19 lshift FSMC-BCR2 bis! ; \ FSMC-BCR2_CBURSTRW CBURSTRW
: FSMC-BCR2_ASYNCWAIT %1 15 lshift FSMC-BCR2 bis! ; \ FSMC-BCR2_ASYNCWAIT ASYNCWAIT
: FSMC-BCR2_EXTMOD %1 14 lshift FSMC-BCR2 bis! ; \ FSMC-BCR2_EXTMOD EXTMOD
: FSMC-BCR2_WAITEN %1 13 lshift FSMC-BCR2 bis! ; \ FSMC-BCR2_WAITEN WAITEN
: FSMC-BCR2_WREN %1 12 lshift FSMC-BCR2 bis! ; \ FSMC-BCR2_WREN WREN
: FSMC-BCR2_WAITCFG %1 11 lshift FSMC-BCR2 bis! ; \ FSMC-BCR2_WAITCFG WAITCFG
: FSMC-BCR2_WRAPMOD %1 10 lshift FSMC-BCR2 bis! ; \ FSMC-BCR2_WRAPMOD WRAPMOD
: FSMC-BCR2_WAITPOL %1 9 lshift FSMC-BCR2 bis! ; \ FSMC-BCR2_WAITPOL WAITPOL
: FSMC-BCR2_BURSTEN %1 8 lshift FSMC-BCR2 bis! ; \ FSMC-BCR2_BURSTEN BURSTEN
: FSMC-BCR2_FACCEN %1 6 lshift FSMC-BCR2 bis! ; \ FSMC-BCR2_FACCEN FACCEN
: FSMC-BCR2_MWID ( %XX -- ) 4 lshift FSMC-BCR2 bis! ; \ FSMC-BCR2_MWID MWID
: FSMC-BCR2_MTYP ( %XX -- ) 2 lshift FSMC-BCR2 bis! ; \ FSMC-BCR2_MTYP MTYP
: FSMC-BCR2_MUXEN %1 1 lshift FSMC-BCR2 bis! ; \ FSMC-BCR2_MUXEN MUXEN
: FSMC-BCR2_MBKEN %1 0 lshift FSMC-BCR2 bis! ; \ FSMC-BCR2_MBKEN MBKEN
\ FSMC-BTR2 (read-write)
: FSMC-BTR2_ACCMOD ( %XX -- ) 28 lshift FSMC-BTR2 bis! ; \ FSMC-BTR2_ACCMOD ACCMOD
: FSMC-BTR2_DATLAT ( %XXXX -- ) 24 lshift FSMC-BTR2 bis! ; \ FSMC-BTR2_DATLAT DATLAT
: FSMC-BTR2_CLKDIV ( %XXXX -- ) 20 lshift FSMC-BTR2 bis! ; \ FSMC-BTR2_CLKDIV CLKDIV
: FSMC-BTR2_BUSTURN ( %XXXX -- ) 16 lshift FSMC-BTR2 bis! ; \ FSMC-BTR2_BUSTURN BUSTURN
: FSMC-BTR2_DATAST ( %XXXXXXXX -- ) 8 lshift FSMC-BTR2 bis! ; \ FSMC-BTR2_DATAST DATAST
: FSMC-BTR2_ADDHLD ( %XXXX -- ) 4 lshift FSMC-BTR2 bis! ; \ FSMC-BTR2_ADDHLD ADDHLD
: FSMC-BTR2_ADDSET ( %XXXX -- ) 0 lshift FSMC-BTR2 bis! ; \ FSMC-BTR2_ADDSET ADDSET
\ FSMC-BCR3 (read-write)
: FSMC-BCR3_CBURSTRW %1 19 lshift FSMC-BCR3 bis! ; \ FSMC-BCR3_CBURSTRW CBURSTRW
: FSMC-BCR3_ASYNCWAIT %1 15 lshift FSMC-BCR3 bis! ; \ FSMC-BCR3_ASYNCWAIT ASYNCWAIT
: FSMC-BCR3_EXTMOD %1 14 lshift FSMC-BCR3 bis! ; \ FSMC-BCR3_EXTMOD EXTMOD
: FSMC-BCR3_WAITEN %1 13 lshift FSMC-BCR3 bis! ; \ FSMC-BCR3_WAITEN WAITEN
: FSMC-BCR3_WREN %1 12 lshift FSMC-BCR3 bis! ; \ FSMC-BCR3_WREN WREN
: FSMC-BCR3_WAITCFG %1 11 lshift FSMC-BCR3 bis! ; \ FSMC-BCR3_WAITCFG WAITCFG
: FSMC-BCR3_WRAPMOD %1 10 lshift FSMC-BCR3 bis! ; \ FSMC-BCR3_WRAPMOD WRAPMOD
: FSMC-BCR3_WAITPOL %1 9 lshift FSMC-BCR3 bis! ; \ FSMC-BCR3_WAITPOL WAITPOL
: FSMC-BCR3_BURSTEN %1 8 lshift FSMC-BCR3 bis! ; \ FSMC-BCR3_BURSTEN BURSTEN
: FSMC-BCR3_FACCEN %1 6 lshift FSMC-BCR3 bis! ; \ FSMC-BCR3_FACCEN FACCEN
: FSMC-BCR3_MWID ( %XX -- ) 4 lshift FSMC-BCR3 bis! ; \ FSMC-BCR3_MWID MWID
: FSMC-BCR3_MTYP ( %XX -- ) 2 lshift FSMC-BCR3 bis! ; \ FSMC-BCR3_MTYP MTYP
: FSMC-BCR3_MUXEN %1 1 lshift FSMC-BCR3 bis! ; \ FSMC-BCR3_MUXEN MUXEN
: FSMC-BCR3_MBKEN %1 0 lshift FSMC-BCR3 bis! ; \ FSMC-BCR3_MBKEN MBKEN
\ FSMC-BTR3 (read-write)
: FSMC-BTR3_ACCMOD ( %XX -- ) 28 lshift FSMC-BTR3 bis! ; \ FSMC-BTR3_ACCMOD ACCMOD
: FSMC-BTR3_DATLAT ( %XXXX -- ) 24 lshift FSMC-BTR3 bis! ; \ FSMC-BTR3_DATLAT DATLAT
: FSMC-BTR3_CLKDIV ( %XXXX -- ) 20 lshift FSMC-BTR3 bis! ; \ FSMC-BTR3_CLKDIV CLKDIV
: FSMC-BTR3_BUSTURN ( %XXXX -- ) 16 lshift FSMC-BTR3 bis! ; \ FSMC-BTR3_BUSTURN BUSTURN
: FSMC-BTR3_DATAST ( %XXXXXXXX -- ) 8 lshift FSMC-BTR3 bis! ; \ FSMC-BTR3_DATAST DATAST
: FSMC-BTR3_ADDHLD ( %XXXX -- ) 4 lshift FSMC-BTR3 bis! ; \ FSMC-BTR3_ADDHLD ADDHLD
: FSMC-BTR3_ADDSET ( %XXXX -- ) 0 lshift FSMC-BTR3 bis! ; \ FSMC-BTR3_ADDSET ADDSET
\ FSMC-BCR4 (read-write)
: FSMC-BCR4_CBURSTRW %1 19 lshift FSMC-BCR4 bis! ; \ FSMC-BCR4_CBURSTRW CBURSTRW
: FSMC-BCR4_ASYNCWAIT %1 15 lshift FSMC-BCR4 bis! ; \ FSMC-BCR4_ASYNCWAIT ASYNCWAIT
: FSMC-BCR4_EXTMOD %1 14 lshift FSMC-BCR4 bis! ; \ FSMC-BCR4_EXTMOD EXTMOD
: FSMC-BCR4_WAITEN %1 13 lshift FSMC-BCR4 bis! ; \ FSMC-BCR4_WAITEN WAITEN
: FSMC-BCR4_WREN %1 12 lshift FSMC-BCR4 bis! ; \ FSMC-BCR4_WREN WREN
: FSMC-BCR4_WAITCFG %1 11 lshift FSMC-BCR4 bis! ; \ FSMC-BCR4_WAITCFG WAITCFG
: FSMC-BCR4_WRAPMOD %1 10 lshift FSMC-BCR4 bis! ; \ FSMC-BCR4_WRAPMOD WRAPMOD
: FSMC-BCR4_WAITPOL %1 9 lshift FSMC-BCR4 bis! ; \ FSMC-BCR4_WAITPOL WAITPOL
: FSMC-BCR4_BURSTEN %1 8 lshift FSMC-BCR4 bis! ; \ FSMC-BCR4_BURSTEN BURSTEN
: FSMC-BCR4_FACCEN %1 6 lshift FSMC-BCR4 bis! ; \ FSMC-BCR4_FACCEN FACCEN
: FSMC-BCR4_MWID ( %XX -- ) 4 lshift FSMC-BCR4 bis! ; \ FSMC-BCR4_MWID MWID
: FSMC-BCR4_MTYP ( %XX -- ) 2 lshift FSMC-BCR4 bis! ; \ FSMC-BCR4_MTYP MTYP
: FSMC-BCR4_MUXEN %1 1 lshift FSMC-BCR4 bis! ; \ FSMC-BCR4_MUXEN MUXEN
: FSMC-BCR4_MBKEN %1 0 lshift FSMC-BCR4 bis! ; \ FSMC-BCR4_MBKEN MBKEN
\ FSMC-BTR4 (read-write)
: FSMC-BTR4_ACCMOD ( %XX -- ) 28 lshift FSMC-BTR4 bis! ; \ FSMC-BTR4_ACCMOD ACCMOD
: FSMC-BTR4_DATLAT ( %XXXX -- ) 24 lshift FSMC-BTR4 bis! ; \ FSMC-BTR4_DATLAT DATLAT
: FSMC-BTR4_CLKDIV ( %XXXX -- ) 20 lshift FSMC-BTR4 bis! ; \ FSMC-BTR4_CLKDIV CLKDIV
: FSMC-BTR4_BUSTURN ( %XXXX -- ) 16 lshift FSMC-BTR4 bis! ; \ FSMC-BTR4_BUSTURN BUSTURN
: FSMC-BTR4_DATAST ( %XXXXXXXX -- ) 8 lshift FSMC-BTR4 bis! ; \ FSMC-BTR4_DATAST DATAST
: FSMC-BTR4_ADDHLD ( %XXXX -- ) 4 lshift FSMC-BTR4 bis! ; \ FSMC-BTR4_ADDHLD ADDHLD
: FSMC-BTR4_ADDSET ( %XXXX -- ) 0 lshift FSMC-BTR4 bis! ; \ FSMC-BTR4_ADDSET ADDSET
\ FSMC-PCR2 (read-write)
: FSMC-PCR2_ECCPS ( %XXX -- ) 17 lshift FSMC-PCR2 bis! ; \ FSMC-PCR2_ECCPS ECCPS
: FSMC-PCR2_TAR ( %XXXX -- ) 13 lshift FSMC-PCR2 bis! ; \ FSMC-PCR2_TAR TAR
: FSMC-PCR2_TCLR ( %XXXX -- ) 9 lshift FSMC-PCR2 bis! ; \ FSMC-PCR2_TCLR TCLR
: FSMC-PCR2_ECCEN %1 6 lshift FSMC-PCR2 bis! ; \ FSMC-PCR2_ECCEN ECCEN
: FSMC-PCR2_PWID ( %XX -- ) 4 lshift FSMC-PCR2 bis! ; \ FSMC-PCR2_PWID PWID
: FSMC-PCR2_PTYP %1 3 lshift FSMC-PCR2 bis! ; \ FSMC-PCR2_PTYP PTYP
: FSMC-PCR2_PBKEN %1 2 lshift FSMC-PCR2 bis! ; \ FSMC-PCR2_PBKEN PBKEN
: FSMC-PCR2_PWAITEN %1 1 lshift FSMC-PCR2 bis! ; \ FSMC-PCR2_PWAITEN PWAITEN
\ FSMC-SR2 ()
: FSMC-SR2_FEMPT %1 6 lshift FSMC-SR2 bis! ; \ FSMC-SR2_FEMPT FEMPT
: FSMC-SR2_IFEN %1 5 lshift FSMC-SR2 bis! ; \ FSMC-SR2_IFEN IFEN
: FSMC-SR2_ILEN %1 4 lshift FSMC-SR2 bis! ; \ FSMC-SR2_ILEN ILEN
: FSMC-SR2_IREN %1 3 lshift FSMC-SR2 bis! ; \ FSMC-SR2_IREN IREN
: FSMC-SR2_IFS %1 2 lshift FSMC-SR2 bis! ; \ FSMC-SR2_IFS IFS
: FSMC-SR2_ILS %1 1 lshift FSMC-SR2 bis! ; \ FSMC-SR2_ILS ILS
: FSMC-SR2_IRS %1 0 lshift FSMC-SR2 bis! ; \ FSMC-SR2_IRS IRS
\ FSMC-PMEM2 (read-write)
: FSMC-PMEM2_MEMHIZx ( %XXXXXXXX -- ) 24 lshift FSMC-PMEM2 bis! ; \ FSMC-PMEM2_MEMHIZx MEMHIZx
: FSMC-PMEM2_MEMHOLDx ( %XXXXXXXX -- ) 16 lshift FSMC-PMEM2 bis! ; \ FSMC-PMEM2_MEMHOLDx MEMHOLDx
: FSMC-PMEM2_MEMWAITx ( %XXXXXXXX -- ) 8 lshift FSMC-PMEM2 bis! ; \ FSMC-PMEM2_MEMWAITx MEMWAITx
: FSMC-PMEM2_MEMSETx ( %XXXXXXXX -- ) 0 lshift FSMC-PMEM2 bis! ; \ FSMC-PMEM2_MEMSETx MEMSETx
\ FSMC-PATT2 (read-write)
: FSMC-PATT2_ATTHIZx ( %XXXXXXXX -- ) 24 lshift FSMC-PATT2 bis! ; \ FSMC-PATT2_ATTHIZx Attribute memory x databus HiZ time
: FSMC-PATT2_ATTHOLDx ( %XXXXXXXX -- ) 16 lshift FSMC-PATT2 bis! ; \ FSMC-PATT2_ATTHOLDx Attribute memory x hold time
: FSMC-PATT2_ATTWAITx ( %XXXXXXXX -- ) 8 lshift FSMC-PATT2 bis! ; \ FSMC-PATT2_ATTWAITx Attribute memory x wait time
: FSMC-PATT2_ATTSETx ( %XXXXXXXX -- ) 0 lshift FSMC-PATT2 bis! ; \ FSMC-PATT2_ATTSETx Attribute memory x setup time
\ FSMC-ECCR2 (read-only)
: FSMC-ECCR2_ECCx ( %XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- ) 0 lshift FSMC-ECCR2 bis! ; \ FSMC-ECCR2_ECCx ECC result
\ FSMC-PCR3 (read-write)
: FSMC-PCR3_ECCPS ( %XXX -- ) 17 lshift FSMC-PCR3 bis! ; \ FSMC-PCR3_ECCPS ECCPS
: FSMC-PCR3_TAR ( %XXXX -- ) 13 lshift FSMC-PCR3 bis! ; \ FSMC-PCR3_TAR TAR
: FSMC-PCR3_TCLR ( %XXXX -- ) 9 lshift FSMC-PCR3 bis! ; \ FSMC-PCR3_TCLR TCLR
: FSMC-PCR3_ECCEN %1 6 lshift FSMC-PCR3 bis! ; \ FSMC-PCR3_ECCEN ECCEN
: FSMC-PCR3_PWID ( %XX -- ) 4 lshift FSMC-PCR3 bis! ; \ FSMC-PCR3_PWID PWID
: FSMC-PCR3_PTYP %1 3 lshift FSMC-PCR3 bis! ; \ FSMC-PCR3_PTYP PTYP
: FSMC-PCR3_PBKEN %1 2 lshift FSMC-PCR3 bis! ; \ FSMC-PCR3_PBKEN PBKEN
: FSMC-PCR3_PWAITEN %1 1 lshift FSMC-PCR3 bis! ; \ FSMC-PCR3_PWAITEN PWAITEN
\ FSMC-SR3 ()
: FSMC-SR3_FEMPT %1 6 lshift FSMC-SR3 bis! ; \ FSMC-SR3_FEMPT FEMPT
: FSMC-SR3_IFEN %1 5 lshift FSMC-SR3 bis! ; \ FSMC-SR3_IFEN IFEN
: FSMC-SR3_ILEN %1 4 lshift FSMC-SR3 bis! ; \ FSMC-SR3_ILEN ILEN
: FSMC-SR3_IREN %1 3 lshift FSMC-SR3 bis! ; \ FSMC-SR3_IREN IREN
: FSMC-SR3_IFS %1 2 lshift FSMC-SR3 bis! ; \ FSMC-SR3_IFS IFS
: FSMC-SR3_ILS %1 1 lshift FSMC-SR3 bis! ; \ FSMC-SR3_ILS ILS
: FSMC-SR3_IRS %1 0 lshift FSMC-SR3 bis! ; \ FSMC-SR3_IRS IRS
\ FSMC-PMEM3 (read-write)
: FSMC-PMEM3_MEMHIZx ( %XXXXXXXX -- ) 24 lshift FSMC-PMEM3 bis! ; \ FSMC-PMEM3_MEMHIZx MEMHIZx
: FSMC-PMEM3_MEMHOLDx ( %XXXXXXXX -- ) 16 lshift FSMC-PMEM3 bis! ; \ FSMC-PMEM3_MEMHOLDx MEMHOLDx
: FSMC-PMEM3_MEMWAITx ( %XXXXXXXX -- ) 8 lshift FSMC-PMEM3 bis! ; \ FSMC-PMEM3_MEMWAITx MEMWAITx
: FSMC-PMEM3_MEMSETx ( %XXXXXXXX -- ) 0 lshift FSMC-PMEM3 bis! ; \ FSMC-PMEM3_MEMSETx MEMSETx
\ FSMC-PATT3 (read-write)
: FSMC-PATT3_ATTHIZx ( %XXXXXXXX -- ) 24 lshift FSMC-PATT3 bis! ; \ FSMC-PATT3_ATTHIZx ATTHIZx
: FSMC-PATT3_ATTHOLDx ( %XXXXXXXX -- ) 16 lshift FSMC-PATT3 bis! ; \ FSMC-PATT3_ATTHOLDx ATTHOLDx
: FSMC-PATT3_ATTWAITx ( %XXXXXXXX -- ) 8 lshift FSMC-PATT3 bis! ; \ FSMC-PATT3_ATTWAITx ATTWAITx
: FSMC-PATT3_ATTSETx ( %XXXXXXXX -- ) 0 lshift FSMC-PATT3 bis! ; \ FSMC-PATT3_ATTSETx ATTSETx
\ FSMC-ECCR3 (read-only)
: FSMC-ECCR3_ECCx ( %XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -- ) 0 lshift FSMC-ECCR3 bis! ; \ FSMC-ECCR3_ECCx ECCx
\ FSMC-PCR4 (read-write)
: FSMC-PCR4_ECCPS ( %XXX -- ) 17 lshift FSMC-PCR4 bis! ; \ FSMC-PCR4_ECCPS ECCPS
: FSMC-PCR4_TAR ( %XXXX -- ) 13 lshift FSMC-PCR4 bis! ; \ FSMC-PCR4_TAR TAR
: FSMC-PCR4_TCLR ( %XXXX -- ) 9 lshift FSMC-PCR4 bis! ; \ FSMC-PCR4_TCLR TCLR
: FSMC-PCR4_ECCEN %1 6 lshift FSMC-PCR4 bis! ; \ FSMC-PCR4_ECCEN ECCEN
: FSMC-PCR4_PWID ( %XX -- ) 4 lshift FSMC-PCR4 bis! ; \ FSMC-PCR4_PWID PWID
: FSMC-PCR4_PTYP %1 3 lshift FSMC-PCR4 bis! ; \ FSMC-PCR4_PTYP PTYP
: FSMC-PCR4_PBKEN %1 2 lshift FSMC-PCR4 bis! ; \ FSMC-PCR4_PBKEN PBKEN
: FSMC-PCR4_PWAITEN %1 1 lshift FSMC-PCR4 bis! ; \ FSMC-PCR4_PWAITEN PWAITEN
\ FSMC-SR4 ()
: FSMC-SR4_FEMPT %1 6 lshift FSMC-SR4 bis! ; \ FSMC-SR4_FEMPT FEMPT
: FSMC-SR4_IFEN %1 5 lshift FSMC-SR4 bis! ; \ FSMC-SR4_IFEN IFEN
: FSMC-SR4_ILEN %1 4 lshift FSMC-SR4 bis! ; \ FSMC-SR4_ILEN ILEN
: FSMC-SR4_IREN %1 3 lshift FSMC-SR4 bis! ; \ FSMC-SR4_IREN IREN
: FSMC-SR4_IFS %1 2 lshift FSMC-SR4 bis! ; \ FSMC-SR4_IFS IFS
: FSMC-SR4_ILS %1 1 lshift FSMC-SR4 bis! ; \ FSMC-SR4_ILS ILS
: FSMC-SR4_IRS %1 0 lshift FSMC-SR4 bis! ; \ FSMC-SR4_IRS IRS
\ FSMC-PMEM4 (read-write)
: FSMC-PMEM4_MEMHIZx ( %XXXXXXXX -- ) 24 lshift FSMC-PMEM4 bis! ; \ FSMC-PMEM4_MEMHIZx MEMHIZx
: FSMC-PMEM4_MEMHOLDx ( %XXXXXXXX -- ) 16 lshift FSMC-PMEM4 bis! ; \ FSMC-PMEM4_MEMHOLDx MEMHOLDx
: FSMC-PMEM4_MEMWAITx ( %XXXXXXXX -- ) 8 lshift FSMC-PMEM4 bis! ; \ FSMC-PMEM4_MEMWAITx MEMWAITx
: FSMC-PMEM4_MEMSETx ( %XXXXXXXX -- ) 0 lshift FSMC-PMEM4 bis! ; \ FSMC-PMEM4_MEMSETx MEMSETx
\ FSMC-PATT4 (read-write)
: FSMC-PATT4_ATTHIZx ( %XXXXXXXX -- ) 24 lshift FSMC-PATT4 bis! ; \ FSMC-PATT4_ATTHIZx ATTHIZx
: FSMC-PATT4_ATTHOLDx ( %XXXXXXXX -- ) 16 lshift FSMC-PATT4 bis! ; \ FSMC-PATT4_ATTHOLDx ATTHOLDx
: FSMC-PATT4_ATTWAITx ( %XXXXXXXX -- ) 8 lshift FSMC-PATT4 bis! ; \ FSMC-PATT4_ATTWAITx ATTWAITx
: FSMC-PATT4_ATTSETx ( %XXXXXXXX -- ) 0 lshift FSMC-PATT4 bis! ; \ FSMC-PATT4_ATTSETx ATTSETx
\ FSMC-PIO4 (read-write)
: FSMC-PIO4_IOHIZx ( %XXXXXXXX -- ) 24 lshift FSMC-PIO4 bis! ; \ FSMC-PIO4_IOHIZx IOHIZx
: FSMC-PIO4_IOHOLDx ( %XXXXXXXX -- ) 16 lshift FSMC-PIO4 bis! ; \ FSMC-PIO4_IOHOLDx IOHOLDx
: FSMC-PIO4_IOWAITx ( %XXXXXXXX -- ) 8 lshift FSMC-PIO4 bis! ; \ FSMC-PIO4_IOWAITx IOWAITx
: FSMC-PIO4_IOSETx ( %XXXXXXXX -- ) 0 lshift FSMC-PIO4 bis! ; \ FSMC-PIO4_IOSETx IOSETx
\ FSMC-BWTR1 (read-write)
: FSMC-BWTR1_ACCMOD ( %XX -- ) 28 lshift FSMC-BWTR1 bis! ; \ FSMC-BWTR1_ACCMOD ACCMOD
: FSMC-BWTR1_DATLAT ( %XXXX -- ) 24 lshift FSMC-BWTR1 bis! ; \ FSMC-BWTR1_DATLAT DATLAT
: FSMC-BWTR1_CLKDIV ( %XXXX -- ) 20 lshift FSMC-BWTR1 bis! ; \ FSMC-BWTR1_CLKDIV CLKDIV
: FSMC-BWTR1_DATAST ( %XXXXXXXX -- ) 8 lshift FSMC-BWTR1 bis! ; \ FSMC-BWTR1_DATAST DATAST
: FSMC-BWTR1_ADDHLD ( %XXXX -- ) 4 lshift FSMC-BWTR1 bis! ; \ FSMC-BWTR1_ADDHLD ADDHLD
: FSMC-BWTR1_ADDSET ( %XXXX -- ) 0 lshift FSMC-BWTR1 bis! ; \ FSMC-BWTR1_ADDSET ADDSET
\ FSMC-BWTR2 (read-write)
: FSMC-BWTR2_ACCMOD ( %XX -- ) 28 lshift FSMC-BWTR2 bis! ; \ FSMC-BWTR2_ACCMOD ACCMOD
: FSMC-BWTR2_DATLAT ( %XXXX -- ) 24 lshift FSMC-BWTR2 bis! ; \ FSMC-BWTR2_DATLAT DATLAT
: FSMC-BWTR2_CLKDIV ( %XXXX -- ) 20 lshift FSMC-BWTR2 bis! ; \ FSMC-BWTR2_CLKDIV CLKDIV
: FSMC-BWTR2_DATAST ( %XXXXXXXX -- ) 8 lshift FSMC-BWTR2 bis! ; \ FSMC-BWTR2_DATAST DATAST
: FSMC-BWTR2_ADDHLD ( %XXXX -- ) 4 lshift FSMC-BWTR2 bis! ; \ FSMC-BWTR2_ADDHLD ADDHLD
: FSMC-BWTR2_ADDSET ( %XXXX -- ) 0 lshift FSMC-BWTR2 bis! ; \ FSMC-BWTR2_ADDSET ADDSET
\ FSMC-BWTR3 (read-write)
: FSMC-BWTR3_ACCMOD ( %XX -- ) 28 lshift FSMC-BWTR3 bis! ; \ FSMC-BWTR3_ACCMOD ACCMOD
: FSMC-BWTR3_DATLAT ( %XXXX -- ) 24 lshift FSMC-BWTR3 bis! ; \ FSMC-BWTR3_DATLAT DATLAT
: FSMC-BWTR3_CLKDIV ( %XXXX -- ) 20 lshift FSMC-BWTR3 bis! ; \ FSMC-BWTR3_CLKDIV CLKDIV
: FSMC-BWTR3_DATAST ( %XXXXXXXX -- ) 8 lshift FSMC-BWTR3 bis! ; \ FSMC-BWTR3_DATAST DATAST
: FSMC-BWTR3_ADDHLD ( %XXXX -- ) 4 lshift FSMC-BWTR3 bis! ; \ FSMC-BWTR3_ADDHLD ADDHLD
: FSMC-BWTR3_ADDSET ( %XXXX -- ) 0 lshift FSMC-BWTR3 bis! ; \ FSMC-BWTR3_ADDSET ADDSET
\ FSMC-BWTR4 (read-write)
: FSMC-BWTR4_ACCMOD ( %XX -- ) 28 lshift FSMC-BWTR4 bis! ; \ FSMC-BWTR4_ACCMOD ACCMOD
: FSMC-BWTR4_DATLAT ( %XXXX -- ) 24 lshift FSMC-BWTR4 bis! ; \ FSMC-BWTR4_DATLAT DATLAT
: FSMC-BWTR4_CLKDIV ( %XXXX -- ) 20 lshift FSMC-BWTR4 bis! ; \ FSMC-BWTR4_CLKDIV CLKDIV
: FSMC-BWTR4_DATAST ( %XXXXXXXX -- ) 8 lshift FSMC-BWTR4 bis! ; \ FSMC-BWTR4_DATAST DATAST
: FSMC-BWTR4_ADDHLD ( %XXXX -- ) 4 lshift FSMC-BWTR4 bis! ; \ FSMC-BWTR4_ADDHLD ADDHLD
: FSMC-BWTR4_ADDSET ( %XXXX -- ) 0 lshift FSMC-BWTR4 bis! ; \ FSMC-BWTR4_ADDSET ADDSET
\ PWR-CR (read-write)
: PWR-CR_LPDS %1 0 lshift PWR-CR bis! ; \ PWR-CR_LPDS Low Power Deep Sleep
: PWR-CR_PDDS %1 1 lshift PWR-CR bis! ; \ PWR-CR_PDDS Power Down Deep Sleep
: PWR-CR_CWUF %1 2 lshift PWR-CR bis! ; \ PWR-CR_CWUF Clear Wake-up Flag
: PWR-CR_CSBF %1 3 lshift PWR-CR bis! ; \ PWR-CR_CSBF Clear STANDBY Flag
: PWR-CR_PVDE %1 4 lshift PWR-CR bis! ; \ PWR-CR_PVDE Power Voltage Detector Enable
: PWR-CR_PLS ( %XXX -- ) 5 lshift PWR-CR bis! ; \ PWR-CR_PLS PVD Level Selection
: PWR-CR_DBP %1 8 lshift PWR-CR bis! ; \ PWR-CR_DBP Disable Backup Domain write protection
\ PWR-CSR ()
: PWR-CSR_WUF %1 0 lshift PWR-CSR bis! ; \ PWR-CSR_WUF Wake-Up Flag
: PWR-CSR_SBF %1 1 lshift PWR-CSR bis! ; \ PWR-CSR_SBF STANDBY Flag
: PWR-CSR_PVDO %1 2 lshift PWR-CSR bis! ; \ PWR-CSR_PVDO PVD Output
: PWR-CSR_EWUP %1 8 lshift PWR-CSR bis! ; \ PWR-CSR_EWUP Enable WKUP pin
\ RCC-CR ()
: RCC-CR_HSION %1 0 lshift RCC-CR bis! ; \ RCC-CR_HSION Internal High Speed clock enable
: RCC-CR_HSIRDY %1 1 lshift RCC-CR bis! ; \ RCC-CR_HSIRDY Internal High Speed clock ready flag
: RCC-CR_HSITRIM ( %XXXXX -- ) 3 lshift RCC-CR bis! ; \ RCC-CR_HSITRIM Internal High Speed clock trimming
: RCC-CR_HSICAL ( %XXXXXXXX -- ) 8 lshift RCC-CR bis! ; \ RCC-CR_HSICAL Internal High Speed clock Calibration
: RCC-CR_HSEON %1 16 lshift RCC-CR bis! ; \ RCC-CR_HSEON External High Speed clock enable
: RCC-CR_HSERDY %1 17 lshift RCC-CR bis! ; \ RCC-CR_HSERDY External High Speed clock ready flag
: RCC-CR_HSEBYP %1 18 lshift RCC-CR bis! ; \ RCC-CR_HSEBYP External High Speed clock Bypass
: RCC-CR_CSSON %1 19 lshift RCC-CR bis! ; \ RCC-CR_CSSON Clock Security System enable
: RCC-CR_PLLON %1 24 lshift RCC-CR bis! ; \ RCC-CR_PLLON PLL enable
: RCC-CR_PLLRDY %1 25 lshift RCC-CR bis! ; \ RCC-CR_PLLRDY PLL clock ready flag
\ RCC-CFGR ()
: RCC-CFGR_SW ( %XX -- ) 0 lshift RCC-CFGR bis! ; \ RCC-CFGR_SW System clock Switch
: RCC-CFGR_SWS ( %XX -- ) 2 lshift RCC-CFGR bis! ; \ RCC-CFGR_SWS System Clock Switch Status
: RCC-CFGR_HPRE ( %XXXX -- ) 4 lshift RCC-CFGR bis! ; \ RCC-CFGR_HPRE AHB prescaler
: RCC-CFGR_PPRE1 ( %XXX -- ) 8 lshift RCC-CFGR bis! ; \ RCC-CFGR_PPRE1 APB Low speed prescaler APB1
: RCC-CFGR_PPRE2 ( %XXX -- ) 11 lshift RCC-CFGR bis! ; \ RCC-CFGR_PPRE2 APB High speed prescaler APB2
: RCC-CFGR_ADCPRE ( %XX -- ) 14 lshift RCC-CFGR bis! ; \ RCC-CFGR_ADCPRE ADC prescaler
: RCC-CFGR_PLLSRC %1 16 lshift RCC-CFGR bis! ; \ RCC-CFGR_PLLSRC PLL entry clock source
: RCC-CFGR_PLLXTPRE %1 17 lshift RCC-CFGR bis! ; \ RCC-CFGR_PLLXTPRE HSE divider for PLL entry
: RCC-CFGR_PLLMUL ( %XXXX -- ) 18 lshift RCC-CFGR bis! ; \ RCC-CFGR_PLLMUL PLL Multiplication Factor
: RCC-CFGR_OTGFSPRE %1 22 lshift RCC-CFGR bis! ; \ RCC-CFGR_OTGFSPRE USB OTG FS prescaler
: RCC-CFGR_MCO ( %XXX -- ) 24 lshift RCC-CFGR bis! ; \ RCC-CFGR_MCO Microcontroller clock output
\ RCC-CIR ()
: RCC-CIR_LSIRDYF %1 0 lshift RCC-CIR bis! ; \ RCC-CIR_LSIRDYF LSI Ready Interrupt flag
: RCC-CIR_LSERDYF %1 1 lshift RCC-CIR bis! ; \ RCC-CIR_LSERDYF LSE Ready Interrupt flag
: RCC-CIR_HSIRDYF %1 2 lshift RCC-CIR bis! ; \ RCC-CIR_HSIRDYF HSI Ready Interrupt flag
: RCC-CIR_HSERDYF %1 3 lshift RCC-CIR bis! ; \ RCC-CIR_HSERDYF HSE Ready Interrupt flag
: RCC-CIR_PLLRDYF %1 4 lshift RCC-CIR bis! ; \ RCC-CIR_PLLRDYF PLL Ready Interrupt flag
: RCC-CIR_CSSF %1 7 lshift RCC-CIR bis! ; \ RCC-CIR_CSSF Clock Security System Interrupt flag
: RCC-CIR_LSIRDYIE %1 8 lshift RCC-CIR bis! ; \ RCC-CIR_LSIRDYIE LSI Ready Interrupt Enable
: RCC-CIR_LSERDYIE %1 9 lshift RCC-CIR bis! ; \ RCC-CIR_LSERDYIE LSE Ready Interrupt Enable
: RCC-CIR_HSIRDYIE %1 10 lshift RCC-CIR bis! ; \ RCC-CIR_HSIRDYIE HSI Ready Interrupt Enable
: RCC-CIR_HSERDYIE %1 11 lshift RCC-CIR bis! ; \ RCC-CIR_HSERDYIE HSE Ready Interrupt Enable
: RCC-CIR_PLLRDYIE %1 12 lshift RCC-CIR bis! ; \ RCC-CIR_PLLRDYIE PLL Ready Interrupt Enable
: RCC-CIR_LSIRDYC %1 16 lshift RCC-CIR bis! ; \ RCC-CIR_LSIRDYC LSI Ready Interrupt Clear
: RCC-CIR_LSERDYC %1 17 lshift RCC-CIR bis! ; \ RCC-CIR_LSERDYC LSE Ready Interrupt Clear
: RCC-CIR_HSIRDYC %1 18 lshift RCC-CIR bis! ; \ RCC-CIR_HSIRDYC HSI Ready Interrupt Clear
: RCC-CIR_HSERDYC %1 19 lshift RCC-CIR bis! ; \ RCC-CIR_HSERDYC HSE Ready Interrupt Clear
: RCC-CIR_PLLRDYC %1 20 lshift RCC-CIR bis! ; \ RCC-CIR_PLLRDYC PLL Ready Interrupt Clear
: RCC-CIR_CSSC %1 23 lshift RCC-CIR bis! ; \ RCC-CIR_CSSC Clock security system interrupt clear
\ RCC-APB2RSTR (read-write)
: RCC-APB2RSTR_AFIORST %1 0 lshift RCC-APB2RSTR bis! ; \ RCC-APB2RSTR_AFIORST Alternate function I/O reset
: RCC-APB2RSTR_IOPARST %1 2 lshift RCC-APB2RSTR bis! ; \ RCC-APB2RSTR_IOPARST IO port A reset
: RCC-APB2RSTR_IOPBRST %1 3 lshift RCC-APB2RSTR bis! ; \ RCC-APB2RSTR_IOPBRST IO port B reset
: RCC-APB2RSTR_IOPCRST %1 4 lshift RCC-APB2RSTR bis! ; \ RCC-APB2RSTR_IOPCRST IO port C reset
: RCC-APB2RSTR_IOPDRST %1 5 lshift RCC-APB2RSTR bis! ; \ RCC-APB2RSTR_IOPDRST IO port D reset
: RCC-APB2RSTR_IOPERST %1 6 lshift RCC-APB2RSTR bis! ; \ RCC-APB2RSTR_IOPERST IO port E reset
: RCC-APB2RSTR_IOPFRST %1 7 lshift RCC-APB2RSTR bis! ; \ RCC-APB2RSTR_IOPFRST IO port F reset
: RCC-APB2RSTR_IOPGRST %1 8 lshift RCC-APB2RSTR bis! ; \ RCC-APB2RSTR_IOPGRST IO port G reset
: RCC-APB2RSTR_ADC1RST %1 9 lshift RCC-APB2RSTR bis! ; \ RCC-APB2RSTR_ADC1RST ADC 1 interface reset
: RCC-APB2RSTR_ADC2RST %1 10 lshift RCC-APB2RSTR bis! ; \ RCC-APB2RSTR_ADC2RST ADC 2 interface reset
: RCC-APB2RSTR_TIM1RST %1 11 lshift RCC-APB2RSTR bis! ; \ RCC-APB2RSTR_TIM1RST TIM1 timer reset
: RCC-APB2RSTR_SPI1RST %1 12 lshift RCC-APB2RSTR bis! ; \ RCC-APB2RSTR_SPI1RST SPI 1 reset
: RCC-APB2RSTR_TIM8RST %1 13 lshift RCC-APB2RSTR bis! ; \ RCC-APB2RSTR_TIM8RST TIM8 timer reset
: RCC-APB2RSTR_USART1RST %1 14 lshift RCC-APB2RSTR bis! ; \ RCC-APB2RSTR_USART1RST USART1 reset
: RCC-APB2RSTR_ADC3RST %1 15 lshift RCC-APB2RSTR bis! ; \ RCC-APB2RSTR_ADC3RST ADC 3 interface reset
: RCC-APB2RSTR_TIM9RST %1 19 lshift RCC-APB2RSTR bis! ; \ RCC-APB2RSTR_TIM9RST TIM9 timer reset
: RCC-APB2RSTR_TIM10RST %1 20 lshift RCC-APB2RSTR bis! ; \ RCC-APB2RSTR_TIM10RST TIM10 timer reset
: RCC-APB2RSTR_TIM11RST %1 21 lshift RCC-APB2RSTR bis! ; \ RCC-APB2RSTR_TIM11RST TIM11 timer reset
\ RCC-APB1RSTR (read-write)
: RCC-APB1RSTR_TIM2RST %1 0 lshift RCC-APB1RSTR bis! ; \ RCC-APB1RSTR_TIM2RST Timer 2 reset
: RCC-APB1RSTR_TIM3RST %1 1 lshift RCC-APB1RSTR bis! ; \ RCC-APB1RSTR_TIM3RST Timer 3 reset
: RCC-APB1RSTR_TIM4RST %1 2 lshift RCC-APB1RSTR bis! ; \ RCC-APB1RSTR_TIM4RST Timer 4 reset
: RCC-APB1RSTR_TIM5RST %1 3 lshift RCC-APB1RSTR bis! ; \ RCC-APB1RSTR_TIM5RST Timer 5 reset
: RCC-APB1RSTR_TIM6RST %1 4 lshift RCC-APB1RSTR bis! ; \ RCC-APB1RSTR_TIM6RST Timer 6 reset
: RCC-APB1RSTR_TIM7RST %1 5 lshift RCC-APB1RSTR bis! ; \ RCC-APB1RSTR_TIM7RST Timer 7 reset
: RCC-APB1RSTR_TIM12RST %1 6 lshift RCC-APB1RSTR bis! ; \ RCC-APB1RSTR_TIM12RST Timer 12 reset
: RCC-APB1RSTR_TIM13RST %1 7 lshift RCC-APB1RSTR bis! ; \ RCC-APB1RSTR_TIM13RST Timer 13 reset
: RCC-APB1RSTR_TIM14RST %1 8 lshift RCC-APB1RSTR bis! ; \ RCC-APB1RSTR_TIM14RST Timer 14 reset
: RCC-APB1RSTR_WWDGRST %1 11 lshift RCC-APB1RSTR bis! ; \ RCC-APB1RSTR_WWDGRST Window watchdog reset
: RCC-APB1RSTR_SPI2RST %1 14 lshift RCC-APB1RSTR bis! ; \ RCC-APB1RSTR_SPI2RST SPI2 reset
: RCC-APB1RSTR_SPI3RST %1 15 lshift RCC-APB1RSTR bis! ; \ RCC-APB1RSTR_SPI3RST SPI3 reset
: RCC-APB1RSTR_USART2RST %1 17 lshift RCC-APB1RSTR bis! ; \ RCC-APB1RSTR_USART2RST USART 2 reset
: RCC-APB1RSTR_USART3RST %1 18 lshift RCC-APB1RSTR bis! ; \ RCC-APB1RSTR_USART3RST USART 3 reset
: RCC-APB1RSTR_UART4RST %1 19 lshift RCC-APB1RSTR bis! ; \ RCC-APB1RSTR_UART4RST UART 4 reset
: RCC-APB1RSTR_UART5RST %1 20 lshift RCC-APB1RSTR bis! ; \ RCC-APB1RSTR_UART5RST UART 5 reset
: RCC-APB1RSTR_I2C1RST %1 21 lshift RCC-APB1RSTR bis! ; \ RCC-APB1RSTR_I2C1RST I2C1 reset
: RCC-APB1RSTR_I2C2RST %1 22 lshift RCC-APB1RSTR bis! ; \ RCC-APB1RSTR_I2C2RST I2C2 reset
: RCC-APB1RSTR_USBRST %1 23 lshift RCC-APB1RSTR bis! ; \ RCC-APB1RSTR_USBRST USB reset
: RCC-APB1RSTR_CANRST %1 25 lshift RCC-APB1RSTR bis! ; \ RCC-APB1RSTR_CANRST CAN reset
: RCC-APB1RSTR_BKPRST %1 27 lshift RCC-APB1RSTR bis! ; \ RCC-APB1RSTR_BKPRST Backup interface reset
: RCC-APB1RSTR_PWRRST %1 28 lshift RCC-APB1RSTR bis! ; \ RCC-APB1RSTR_PWRRST Power interface reset
: RCC-APB1RSTR_DACRST %1 29 lshift RCC-APB1RSTR bis! ; \ RCC-APB1RSTR_DACRST DAC interface reset
\ RCC-AHBENR (read-write)
: RCC-AHBENR_DMA1EN %1 0 lshift RCC-AHBENR bis! ; \ RCC-AHBENR_DMA1EN DMA1 clock enable
: RCC-AHBENR_DMA2EN %1 1 lshift RCC-AHBENR bis! ; \ RCC-AHBENR_DMA2EN DMA2 clock enable
: RCC-AHBENR_SRAMEN %1 2 lshift RCC-AHBENR bis! ; \ RCC-AHBENR_SRAMEN SRAM interface clock enable
: RCC-AHBENR_FLITFEN %1 4 lshift RCC-AHBENR bis! ; \ RCC-AHBENR_FLITFEN FLITF clock enable
: RCC-AHBENR_CRCEN %1 6 lshift RCC-AHBENR bis! ; \ RCC-AHBENR_CRCEN CRC clock enable
: RCC-AHBENR_FSMCEN %1 8 lshift RCC-AHBENR bis! ; \ RCC-AHBENR_FSMCEN FSMC clock enable
: RCC-AHBENR_SDIOEN %1 10 lshift RCC-AHBENR bis! ; \ RCC-AHBENR_SDIOEN SDIO clock enable
\ RCC-APB2ENR (read-write)
: RCC-APB2ENR_AFIOEN %1 0 lshift RCC-APB2ENR bis! ; \ RCC-APB2ENR_AFIOEN Alternate function I/O clock enable
: RCC-APB2ENR_IOPAEN %1 2 lshift RCC-APB2ENR bis! ; \ RCC-APB2ENR_IOPAEN I/O port A clock enable
: RCC-APB2ENR_IOPBEN %1 3 lshift RCC-APB2ENR bis! ; \ RCC-APB2ENR_IOPBEN I/O port B clock enable
: RCC-APB2ENR_IOPCEN %1 4 lshift RCC-APB2ENR bis! ; \ RCC-APB2ENR_IOPCEN I/O port C clock enable
: RCC-APB2ENR_IOPDEN %1 5 lshift RCC-APB2ENR bis! ; \ RCC-APB2ENR_IOPDEN I/O port D clock enable
: RCC-APB2ENR_IOPEEN %1 6 lshift RCC-APB2ENR bis! ; \ RCC-APB2ENR_IOPEEN I/O port E clock enable
: RCC-APB2ENR_IOPFEN %1 7 lshift RCC-APB2ENR bis! ; \ RCC-APB2ENR_IOPFEN I/O port F clock enable
: RCC-APB2ENR_IOPGEN %1 8 lshift RCC-APB2ENR bis! ; \ RCC-APB2ENR_IOPGEN I/O port G clock enable
: RCC-APB2ENR_ADC1EN %1 9 lshift RCC-APB2ENR bis! ; \ RCC-APB2ENR_ADC1EN ADC 1 interface clock enable
: RCC-APB2ENR_ADC2EN %1 10 lshift RCC-APB2ENR bis! ; \ RCC-APB2ENR_ADC2EN ADC 2 interface clock enable
: RCC-APB2ENR_TIM1EN %1 11 lshift RCC-APB2ENR bis! ; \ RCC-APB2ENR_TIM1EN TIM1 Timer clock enable
: RCC-APB2ENR_SPI1EN %1 12 lshift RCC-APB2ENR bis! ; \ RCC-APB2ENR_SPI1EN SPI 1 clock enable
: RCC-APB2ENR_TIM8EN %1 13 lshift RCC-APB2ENR bis! ; \ RCC-APB2ENR_TIM8EN TIM8 Timer clock enable
: RCC-APB2ENR_USART1EN %1 14 lshift RCC-APB2ENR bis! ; \ RCC-APB2ENR_USART1EN USART1 clock enable
: RCC-APB2ENR_ADC3EN %1 15 lshift RCC-APB2ENR bis! ; \ RCC-APB2ENR_ADC3EN ADC3 interface clock enable
: RCC-APB2ENR_TIM9EN %1 19 lshift RCC-APB2ENR bis! ; \ RCC-APB2ENR_TIM9EN TIM9 Timer clock enable
: RCC-APB2ENR_TIM10EN %1 20 lshift RCC-APB2ENR bis! ; \ RCC-APB2ENR_TIM10EN TIM10 Timer clock enable
: RCC-APB2ENR_TIM11EN %1 21 lshift RCC-APB2ENR bis! ; \ RCC-APB2ENR_TIM11EN TIM11 Timer clock enable
\ RCC-APB1ENR (read-write)
: RCC-APB1ENR_TIM2EN %1 0 lshift RCC-APB1ENR bis! ; \ RCC-APB1ENR_TIM2EN Timer 2 clock enable
: RCC-APB1ENR_TIM3EN %1 1 lshift RCC-APB1ENR bis! ; \ RCC-APB1ENR_TIM3EN Timer 3 clock enable
: RCC-APB1ENR_TIM4EN %1 2 lshift RCC-APB1ENR bis! ; \ RCC-APB1ENR_TIM4EN Timer 4 clock enable
: RCC-APB1ENR_TIM5EN %1 3 lshift RCC-APB1ENR bis! ; \ RCC-APB1ENR_TIM5EN Timer 5 clock enable
: RCC-APB1ENR_TIM6EN %1 4 lshift RCC-APB1ENR bis! ; \ RCC-APB1ENR_TIM6EN Timer 6 clock enable
: RCC-APB1ENR_TIM7EN %1 5 lshift RCC-APB1ENR bis! ; \ RCC-APB1ENR_TIM7EN Timer 7 clock enable
: RCC-APB1ENR_TIM12EN %1 6 lshift RCC-APB1ENR bis! ; \ RCC-APB1ENR_TIM12EN Timer 12 clock enable
: RCC-APB1ENR_TIM13EN %1 7 lshift RCC-APB1ENR bis! ; \ RCC-APB1ENR_TIM13EN Timer 13 clock enable
: RCC-APB1ENR_TIM14EN %1 8 lshift RCC-APB1ENR bis! ; \ RCC-APB1ENR_TIM14EN Timer 14 clock enable
: RCC-APB1ENR_WWDGEN %1 11 lshift RCC-APB1ENR bis! ; \ RCC-APB1ENR_WWDGEN Window watchdog clock enable
: RCC-APB1ENR_SPI2EN %1 14 lshift RCC-APB1ENR bis! ; \ RCC-APB1ENR_SPI2EN SPI 2 clock enable
: RCC-APB1ENR_SPI3EN %1 15 lshift RCC-APB1ENR bis! ; \ RCC-APB1ENR_SPI3EN SPI 3 clock enable
: RCC-APB1ENR_USART2EN %1 17 lshift RCC-APB1ENR bis! ; \ RCC-APB1ENR_USART2EN USART 2 clock enable
: RCC-APB1ENR_USART3EN %1 18 lshift RCC-APB1ENR bis! ; \ RCC-APB1ENR_USART3EN USART 3 clock enable
: RCC-APB1ENR_UART4EN %1 19 lshift RCC-APB1ENR bis! ; \ RCC-APB1ENR_UART4EN UART 4 clock enable
: RCC-APB1ENR_UART5EN %1 20 lshift RCC-APB1ENR bis! ; \ RCC-APB1ENR_UART5EN UART 5 clock enable
: RCC-APB1ENR_I2C1EN %1 21 lshift RCC-APB1ENR bis! ; \ RCC-APB1ENR_I2C1EN I2C 1 clock enable
: RCC-APB1ENR_I2C2EN %1 22 lshift RCC-APB1ENR bis! ; \ RCC-APB1ENR_I2C2EN I2C 2 clock enable
: RCC-APB1ENR_USBEN %1 23 lshift RCC-APB1ENR bis! ; \ RCC-APB1ENR_USBEN USB clock enable
: RCC-APB1ENR_CANEN %1 25 lshift RCC-APB1ENR bis! ; \ RCC-APB1ENR_CANEN CAN clock enable
: RCC-APB1ENR_BKPEN %1 27 lshift RCC-APB1ENR bis! ; \ RCC-APB1ENR_BKPEN Backup interface clock enable
: RCC-APB1ENR_PWREN %1 28 lshift RCC-APB1ENR bis! ; \ RCC-APB1ENR_PWREN Power interface clock enable
: RCC-APB1ENR_DACEN %1 29 lshift RCC-APB1ENR bis! ; \ RCC-APB1ENR_DACEN DAC interface clock enable
\ RCC-BDCR ()
: RCC-BDCR_LSEON %1 0 lshift RCC-BDCR bis! ; \ RCC-BDCR_LSEON External Low Speed oscillator enable
: RCC-BDCR_LSERDY %1 1 lshift RCC-BDCR bis! ; \ RCC-BDCR_LSERDY External Low Speed oscillator ready
: RCC-BDCR_LSEBYP %1 2 lshift RCC-BDCR bis! ; \ RCC-BDCR_LSEBYP External Low Speed oscillator bypass
: RCC-BDCR_RTCSEL ( %XX -- ) 8 lshift RCC-BDCR bis! ; \ RCC-BDCR_RTCSEL RTC clock source selection
: RCC-BDCR_RTCEN %1 15 lshift RCC-BDCR bis! ; \ RCC-BDCR_RTCEN RTC clock enable
: RCC-BDCR_BDRST %1 16 lshift RCC-BDCR bis! ; \ RCC-BDCR_BDRST Backup domain software reset
\ RCC-CSR ()
: RCC-CSR_LSION %1 0 lshift RCC-CSR bis! ; \ RCC-CSR_LSION Internal low speed oscillator enable
: RCC-CSR_LSIRDY %1 1 lshift RCC-CSR bis! ; \ RCC-CSR_LSIRDY Internal low speed oscillator ready
: RCC-CSR_RMVF %1 24 lshift RCC-CSR bis! ; \ RCC-CSR_RMVF Remove reset flag
: RCC-CSR_PINRSTF %1 26 lshift RCC-CSR bis! ; \ RCC-CSR_PINRSTF PIN reset flag
: RCC-CSR_PORRSTF %1 27 lshift RCC-CSR bis! ; \ RCC-CSR_PORRSTF POR/PDR reset flag
: RCC-CSR_SFTRSTF %1 28 lshift RCC-CSR bis! ; \ RCC-CSR_SFTRSTF Software reset flag
: RCC-CSR_IWDGRSTF %1 29 lshift RCC-CSR bis! ; \ RCC-CSR_IWDGRSTF Independent watchdog reset flag
: RCC-CSR_WWDGRSTF %1 30 lshift RCC-CSR bis! ; \ RCC-CSR_WWDGRSTF Window watchdog reset flag
: RCC-CSR_LPWRRSTF %1 31 lshift RCC-CSR bis! ; \ RCC-CSR_LPWRRSTF Low-power reset flag
\ GPIOA-CRL (read-write)
: GPIOA-CRL_MODE0 ( %XX -- ) 0 lshift GPIOA-CRL bis! ; \ GPIOA-CRL_MODE0 Port n.0 mode bits
: GPIOA-CRL_CNF0 ( %XX -- ) 2 lshift GPIOA-CRL bis! ; \ GPIOA-CRL_CNF0 Port n.0 configuration bits
: GPIOA-CRL_MODE1 ( %XX -- ) 4 lshift GPIOA-CRL bis! ; \ GPIOA-CRL_MODE1 Port n.1 mode bits
: GPIOA-CRL_CNF1 ( %XX -- ) 6 lshift GPIOA-CRL bis! ; \ GPIOA-CRL_CNF1 Port n.1 configuration bits
: GPIOA-CRL_MODE2 ( %XX -- ) 8 lshift GPIOA-CRL bis! ; \ GPIOA-CRL_MODE2 Port n.2 mode bits
: GPIOA-CRL_CNF2 ( %XX -- ) 10 lshift GPIOA-CRL bis! ; \ GPIOA-CRL_CNF2 Port n.2 configuration bits
: GPIOA-CRL_MODE3 ( %XX -- ) 12 lshift GPIOA-CRL bis! ; \ GPIOA-CRL_MODE3 Port n.3 mode bits
: GPIOA-CRL_CNF3 ( %XX -- ) 14 lshift GPIOA-CRL bis! ; \ GPIOA-CRL_CNF3 Port n.3 configuration bits
: GPIOA-CRL_MODE4 ( %XX -- ) 16 lshift GPIOA-CRL bis! ; \ GPIOA-CRL_MODE4 Port n.4 mode bits
: GPIOA-CRL_CNF4 ( %XX -- ) 18 lshift GPIOA-CRL bis! ; \ GPIOA-CRL_CNF4 Port n.4 configuration bits
: GPIOA-CRL_MODE5 ( %XX -- ) 20 lshift GPIOA-CRL bis! ; \ GPIOA-CRL_MODE5 Port n.5 mode bits
: GPIOA-CRL_CNF5 ( %XX -- ) 22 lshift GPIOA-CRL bis! ; \ GPIOA-CRL_CNF5 Port n.5 configuration bits
: GPIOA-CRL_MODE6 ( %XX -- ) 24 lshift GPIOA-CRL bis! ; \ GPIOA-CRL_MODE6 Port n.6 mode bits
: GPIOA-CRL_CNF6 ( %XX -- ) 26 lshift GPIOA-CRL bis! ; \ GPIOA-CRL_CNF6 Port n.6 configuration bits
: GPIOA-CRL_MODE7 ( %XX -- ) 28 lshift GPIOA-CRL bis! ; \ GPIOA-CRL_MODE7 Port n.7 mode bits
: GPIOA-CRL_CNF7 ( %XX -- ) 30 lshift GPIOA-CRL bis! ; \ GPIOA-CRL_CNF7 Port n.7 configuration bits
\ GPIOA-CRH (read-write)
: GPIOA-CRH_MODE8 ( %XX -- ) 0 lshift GPIOA-CRH bis! ; \ GPIOA-CRH_MODE8 Port n.8 mode bits
: GPIOA-CRH_CNF8 ( %XX -- ) 2 lshift GPIOA-CRH bis! ; \ GPIOA-CRH_CNF8 Port n.8 configuration bits
: GPIOA-CRH_MODE9 ( %XX -- ) 4 lshift GPIOA-CRH bis! ; \ GPIOA-CRH_MODE9 Port n.9 mode bits
: GPIOA-CRH_CNF9 ( %XX -- ) 6 lshift GPIOA-CRH bis! ; \ GPIOA-CRH_CNF9 Port n.9 configuration bits
: GPIOA-CRH_MODE10 ( %XX -- ) 8 lshift GPIOA-CRH bis! ; \ GPIOA-CRH_MODE10 Port n.10 mode bits
: GPIOA-CRH_CNF10 ( %XX -- ) 10 lshift GPIOA-CRH bis! ; \ GPIOA-CRH_CNF10 Port n.10 configuration bits
: GPIOA-CRH_MODE11 ( %XX -- ) 12 lshift GPIOA-CRH bis! ; \ GPIOA-CRH_MODE11 Port n.11 mode bits
: GPIOA-CRH_CNF11 ( %XX -- ) 14 lshift GPIOA-CRH bis! ; \ GPIOA-CRH_CNF11 Port n.11 configuration bits
: GPIOA-CRH_MODE12 ( %XX -- ) 16 lshift GPIOA-CRH bis! ; \ GPIOA-CRH_MODE12 Port n.12 mode bits
: GPIOA-CRH_CNF12 ( %XX -- ) 18 lshift GPIOA-CRH bis! ; \ GPIOA-CRH_CNF12 Port n.12 configuration bits
: GPIOA-CRH_MODE13 ( %XX -- ) 20 lshift GPIOA-CRH bis! ; \ GPIOA-CRH_MODE13 Port n.13 mode bits
: GPIOA-CRH_CNF13 ( %XX -- ) 22 lshift GPIOA-CRH bis! ; \ GPIOA-CRH_CNF13 Port n.13 configuration bits
: GPIOA-CRH_MODE14 ( %XX -- ) 24 lshift GPIOA-CRH bis! ; \ GPIOA-CRH_MODE14 Port n.14 mode bits
: GPIOA-CRH_CNF14 ( %XX -- ) 26 lshift GPIOA-CRH bis! ; \ GPIOA-CRH_CNF14 Port n.14 configuration bits
: GPIOA-CRH_MODE15 ( %XX -- ) 28 lshift GPIOA-CRH bis! ; \ GPIOA-CRH_MODE15 Port n.15 mode bits
: GPIOA-CRH_CNF15 ( %XX -- ) 30 lshift GPIOA-CRH bis! ; \ GPIOA-CRH_CNF15 Port n.15 configuration bits
\ GPIOA-IDR (read-only)
: GPIOA-IDR_IDR0 %1 0 lshift GPIOA-IDR bis! ; \ GPIOA-IDR_IDR0 Port input data
: GPIOA-IDR_IDR1 %1 1 lshift GPIOA-IDR bis! ; \ GPIOA-IDR_IDR1 Port input data
: GPIOA-IDR_IDR2 %1 2 lshift GPIOA-IDR bis! ; \ GPIOA-IDR_IDR2 Port input data
: GPIOA-IDR_IDR3 %1 3 lshift GPIOA-IDR bis! ; \ GPIOA-IDR_IDR3 Port input data
: GPIOA-IDR_IDR4 %1 4 lshift GPIOA-IDR bis! ; \ GPIOA-IDR_IDR4 Port input data
: GPIOA-IDR_IDR5 %1 5 lshift GPIOA-IDR bis! ; \ GPIOA-IDR_IDR5 Port input data
: GPIOA-IDR_IDR6 %1 6 lshift GPIOA-IDR bis! ; \ GPIOA-IDR_IDR6 Port input data
: GPIOA-IDR_IDR7 %1 7 lshift GPIOA-IDR bis! ; \ GPIOA-IDR_IDR7 Port input data
: GPIOA-IDR_IDR8 %1 8 lshift GPIOA-IDR bis! ; \ GPIOA-IDR_IDR8 Port input data
: GPIOA-IDR_IDR9 %1 9 lshift GPIOA-IDR bis! ; \ GPIOA-IDR_IDR9 Port input data
: GPIOA-IDR_IDR10 %1 10 lshift GPIOA-IDR bis! ; \ GPIOA-IDR_IDR10 Port input data
: GPIOA-IDR_IDR11 %1 11 lshift GPIOA-IDR bis! ; \ GPIOA-IDR_IDR11 Port input data
: GPIOA-IDR_IDR12 %1 12 lshift GPIOA-IDR bis! ; \ GPIOA-IDR_IDR12 Port input data
: GPIOA-IDR_IDR13 %1 13 lshift GPIOA-IDR bis! ; \ GPIOA-IDR_IDR13 Port input data
: GPIOA-IDR_IDR14 %1 14 lshift GPIOA-IDR bis! ; \ GPIOA-IDR_IDR14 Port input data
: GPIOA-IDR_IDR15 %1 15 lshift GPIOA-IDR bis! ; \ GPIOA-IDR_IDR15 Port input data
\ GPIOA-ODR (read-write)
: GPIOA-ODR_ODR0 %1 0 lshift GPIOA-ODR bis! ; \ GPIOA-ODR_ODR0 Port output data
: GPIOA-ODR_ODR1 %1 1 lshift GPIOA-ODR bis! ; \ GPIOA-ODR_ODR1 Port output data
: GPIOA-ODR_ODR2 %1 2 lshift GPIOA-ODR bis! ; \ GPIOA-ODR_ODR2 Port output data
: GPIOA-ODR_ODR3 %1 3 lshift GPIOA-ODR bis! ; \ GPIOA-ODR_ODR3 Port output data
: GPIOA-ODR_ODR4 %1 4 lshift GPIOA-ODR bis! ; \ GPIOA-ODR_ODR4 Port output data
: GPIOA-ODR_ODR5 %1 5 lshift GPIOA-ODR bis! ; \ GPIOA-ODR_ODR5 Port output data
: GPIOA-ODR_ODR6 %1 6 lshift GPIOA-ODR bis! ; \ GPIOA-ODR_ODR6 Port output data
: GPIOA-ODR_ODR7 %1 7 lshift GPIOA-ODR bis! ; \ GPIOA-ODR_ODR7 Port output data
: GPIOA-ODR_ODR8 %1 8 lshift GPIOA-ODR bis! ; \ GPIOA-ODR_ODR8 Port output data
: GPIOA-ODR_ODR9 %1 9 lshift GPIOA-ODR bis! ; \ GPIOA-ODR_ODR9 Port output data
: GPIOA-ODR_ODR10 %1 10 lshift GPIOA-ODR bis! ; \ GPIOA-ODR_ODR10 Port output data
: GPIOA-ODR_ODR11 %1 11 lshift GPIOA-ODR bis! ; \ GPIOA-ODR_ODR11 Port output data
: GPIOA-ODR_ODR12 %1 12 lshift GPIOA-ODR bis! ; \ GPIOA-ODR_ODR12 Port output data
: GPIOA-ODR_ODR13 %1 13 lshift GPIOA-ODR bis! ; \ GPIOA-ODR_ODR13 Port output data
: GPIOA-ODR_ODR14 %1 14 lshift GPIOA-ODR bis! ; \ GPIOA-ODR_ODR14 Port output data
: GPIOA-ODR_ODR15 %1 15 lshift GPIOA-ODR bis! ; \ GPIOA-ODR_ODR15 Port output data
\ GPIOA-BSRR (write-only)
: GPIOA-BSRR_BS0 %1 0 lshift GPIOA-BSRR bis! ; \ GPIOA-BSRR_BS0 Set bit 0
: GPIOA-BSRR_BS1 %1 1 lshift GPIOA-BSRR bis! ; \ GPIOA-BSRR_BS1 Set bit 1
: GPIOA-BSRR_BS2 %1 2 lshift GPIOA-BSRR bis! ; \ GPIOA-BSRR_BS2 Set bit 1
: GPIOA-BSRR_BS3 %1 3 lshift GPIOA-BSRR bis! ; \ GPIOA-BSRR_BS3 Set bit 3
: GPIOA-BSRR_BS4 %1 4 lshift GPIOA-BSRR bis! ; \ GPIOA-BSRR_BS4 Set bit 4
: GPIOA-BSRR_BS5 %1 5 lshift GPIOA-BSRR bis! ; \ GPIOA-BSRR_BS5 Set bit 5
: GPIOA-BSRR_BS6 %1 6 lshift GPIOA-BSRR bis! ; \ GPIOA-BSRR_BS6 Set bit 6
: GPIOA-BSRR_BS7 %1 7 lshift GPIOA-BSRR bis! ; \ GPIOA-BSRR_BS7 Set bit 7
: GPIOA-BSRR_BS8 %1 8 lshift GPIOA-BSRR bis! ; \ GPIOA-BSRR_BS8 Set bit 8
: GPIOA-BSRR_BS9 %1 9 lshift GPIOA-BSRR bis! ; \ GPIOA-BSRR_BS9 Set bit 9
: GPIOA-BSRR_BS10 %1 10 lshift GPIOA-BSRR bis! ; \ GPIOA-BSRR_BS10 Set bit 10
: GPIOA-BSRR_BS11 %1 11 lshift GPIOA-BSRR bis! ; \ GPIOA-BSRR_BS11 Set bit 11
: GPIOA-BSRR_BS12 %1 12 lshift GPIOA-BSRR bis! ; \ GPIOA-BSRR_BS12 Set bit 12
: GPIOA-BSRR_BS13 %1 13 lshift GPIOA-BSRR bis! ; \ GPIOA-BSRR_BS13 Set bit 13
: GPIOA-BSRR_BS14 %1 14 lshift GPIOA-BSRR bis! ; \ GPIOA-BSRR_BS14 Set bit 14
: GPIOA-BSRR_BS15 %1 15 lshift GPIOA-BSRR bis! ; \ GPIOA-BSRR_BS15 Set bit 15
: GPIOA-BSRR_BR0 %1 16 lshift GPIOA-BSRR bis! ; \ GPIOA-BSRR_BR0 Reset bit 0
: GPIOA-BSRR_BR1 %1 17 lshift GPIOA-BSRR bis! ; \ GPIOA-BSRR_BR1 Reset bit 1
: GPIOA-BSRR_BR2 %1 18 lshift GPIOA-BSRR bis! ; \ GPIOA-BSRR_BR2 Reset bit 2
: GPIOA-BSRR_BR3 %1 19 lshift GPIOA-BSRR bis! ; \ GPIOA-BSRR_BR3 Reset bit 3
: GPIOA-BSRR_BR4 %1 20 lshift GPIOA-BSRR bis! ; \ GPIOA-BSRR_BR4 Reset bit 4
: GPIOA-BSRR_BR5 %1 21 lshift GPIOA-BSRR bis! ; \ GPIOA-BSRR_BR5 Reset bit 5
: GPIOA-BSRR_BR6 %1 22 lshift GPIOA-BSRR bis! ; \ GPIOA-BSRR_BR6 Reset bit 6
: GPIOA-BSRR_BR7 %1 23 lshift GPIOA-BSRR bis! ; \ GPIOA-BSRR_BR7 Reset bit 7
: GPIOA-BSRR_BR8 %1 24 lshift GPIOA-BSRR bis! ; \ GPIOA-BSRR_BR8 Reset bit 8
: GPIOA-BSRR_BR9 %1 25 lshift GPIOA-BSRR bis! ; \ GPIOA-BSRR_BR9 Reset bit 9
: GPIOA-BSRR_BR10 %1 26 lshift GPIOA-BSRR bis! ; \ GPIOA-BSRR_BR10 Reset bit 10
: GPIOA-BSRR_BR11 %1 27 lshift GPIOA-BSRR bis! ; \ GPIOA-BSRR_BR11 Reset bit 11
: GPIOA-BSRR_BR12 %1 28 lshift GPIOA-BSRR bis! ; \ GPIOA-BSRR_BR12 Reset bit 12
: GPIOA-BSRR_BR13 %1 29 lshift GPIOA-BSRR bis! ; \ GPIOA-BSRR_BR13 Reset bit 13
: GPIOA-BSRR_BR14 %1 30 lshift GPIOA-BSRR bis! ; \ GPIOA-BSRR_BR14 Reset bit 14
: GPIOA-BSRR_BR15 %1 31 lshift GPIOA-BSRR bis! ; \ GPIOA-BSRR_BR15 Reset bit 15
\ GPIOA-BRR (write-only)
: GPIOA-BRR_BR0 %1 0 lshift GPIOA-BRR bis! ; \ GPIOA-BRR_BR0 Reset bit 0
: GPIOA-BRR_BR1 %1 1 lshift GPIOA-BRR bis! ; \ GPIOA-BRR_BR1 Reset bit 1
: GPIOA-BRR_BR2 %1 2 lshift GPIOA-BRR bis! ; \ GPIOA-BRR_BR2 Reset bit 1
: GPIOA-BRR_BR3 %1 3 lshift GPIOA-BRR bis! ; \ GPIOA-BRR_BR3 Reset bit 3
: GPIOA-BRR_BR4 %1 4 lshift GPIOA-BRR bis! ; \ GPIOA-BRR_BR4 Reset bit 4
: GPIOA-BRR_BR5 %1 5 lshift GPIOA-BRR bis! ; \ GPIOA-BRR_BR5 Reset bit 5
: GPIOA-BRR_BR6 %1 6 lshift GPIOA-BRR bis! ; \ GPIOA-BRR_BR6 Reset bit 6
: GPIOA-BRR_BR7 %1 7 lshift GPIOA-BRR bis! ; \ GPIOA-BRR_BR7 Reset bit 7
: GPIOA-BRR_BR8 %1 8 lshift GPIOA-BRR bis! ; \ GPIOA-BRR_BR8 Reset bit 8
: GPIOA-BRR_BR9 %1 9 lshift GPIOA-BRR bis! ; \ GPIOA-BRR_BR9 Reset bit 9
: GPIOA-BRR_BR10 %1 10 lshift GPIOA-BRR bis! ; \ GPIOA-BRR_BR10 Reset bit 10
: GPIOA-BRR_BR11 %1 11 lshift GPIOA-BRR bis! ; \ GPIOA-BRR_BR11 Reset bit 11
: GPIOA-BRR_BR12 %1 12 lshift GPIOA-BRR bis! ; \ GPIOA-BRR_BR12 Reset bit 12
: GPIOA-BRR_BR13 %1 13 lshift GPIOA-BRR bis! ; \ GPIOA-BRR_BR13 Reset bit 13
: GPIOA-BRR_BR14 %1 14 lshift GPIOA-BRR bis! ; \ GPIOA-BRR_BR14 Reset bit 14
: GPIOA-BRR_BR15 %1 15 lshift GPIOA-BRR bis! ; \ GPIOA-BRR_BR15 Reset bit 15
\ GPIOA-LCKR (read-write)
: GPIOA-LCKR_LCK0 %1 0 lshift GPIOA-LCKR bis! ; \ GPIOA-LCKR_LCK0 Port A Lock bit 0
: GPIOA-LCKR_LCK1 %1 1 lshift GPIOA-LCKR bis! ; \ GPIOA-LCKR_LCK1 Port A Lock bit 1
: GPIOA-LCKR_LCK2 %1 2 lshift GPIOA-LCKR bis! ; \ GPIOA-LCKR_LCK2 Port A Lock bit 2
: GPIOA-LCKR_LCK3 %1 3 lshift GPIOA-LCKR bis! ; \ GPIOA-LCKR_LCK3 Port A Lock bit 3
: GPIOA-LCKR_LCK4 %1 4 lshift GPIOA-LCKR bis! ; \ GPIOA-LCKR_LCK4 Port A Lock bit 4
: GPIOA-LCKR_LCK5 %1 5 lshift GPIOA-LCKR bis! ; \ GPIOA-LCKR_LCK5 Port A Lock bit 5
: GPIOA-LCKR_LCK6 %1 6 lshift GPIOA-LCKR bis! ; \ GPIOA-LCKR_LCK6 Port A Lock bit 6
: GPIOA-LCKR_LCK7 %1 7 lshift GPIOA-LCKR bis! ; \ GPIOA-LCKR_LCK7 Port A Lock bit 7
: GPIOA-LCKR_LCK8 %1 8 lshift GPIOA-LCKR bis! ; \ GPIOA-LCKR_LCK8 Port A Lock bit 8
: GPIOA-LCKR_LCK9 %1 9 lshift GPIOA-LCKR bis! ; \ GPIOA-LCKR_LCK9 Port A Lock bit 9
: GPIOA-LCKR_LCK10 %1 10 lshift GPIOA-LCKR bis! ; \ GPIOA-LCKR_LCK10 Port A Lock bit 10
: GPIOA-LCKR_LCK11 %1 11 lshift GPIOA-LCKR bis! ; \ GPIOA-LCKR_LCK11 Port A Lock bit 11
: GPIOA-LCKR_LCK12 %1 12 lshift GPIOA-LCKR bis! ; \ GPIOA-LCKR_LCK12 Port A Lock bit 12
: GPIOA-LCKR_LCK13 %1 13 lshift GPIOA-LCKR bis! ; \ GPIOA-LCKR_LCK13 Port A Lock bit 13
: GPIOA-LCKR_LCK14 %1 14 lshift GPIOA-LCKR bis! ; \ GPIOA-LCKR_LCK14 Port A Lock bit 14
: GPIOA-LCKR_LCK15 %1 15 lshift GPIOA-LCKR bis! ; \ GPIOA-LCKR_LCK15 Port A Lock bit 15
: GPIOA-LCKR_LCKK %1 16 lshift GPIOA-LCKR bis! ; \ GPIOA-LCKR_LCKK Lock key
\ GPIOB-CRL (read-write)
: GPIOB-CRL_MODE0 ( %XX -- ) 0 lshift GPIOB-CRL bis! ; \ GPIOB-CRL_MODE0 Port n.0 mode bits
: GPIOB-CRL_CNF0 ( %XX -- ) 2 lshift GPIOB-CRL bis! ; \ GPIOB-CRL_CNF0 Port n.0 configuration bits
: GPIOB-CRL_MODE1 ( %XX -- ) 4 lshift GPIOB-CRL bis! ; \ GPIOB-CRL_MODE1 Port n.1 mode bits
: GPIOB-CRL_CNF1 ( %XX -- ) 6 lshift GPIOB-CRL bis! ; \ GPIOB-CRL_CNF1 Port n.1 configuration bits
: GPIOB-CRL_MODE2 ( %XX -- ) 8 lshift GPIOB-CRL bis! ; \ GPIOB-CRL_MODE2 Port n.2 mode bits
: GPIOB-CRL_CNF2 ( %XX -- ) 10 lshift GPIOB-CRL bis! ; \ GPIOB-CRL_CNF2 Port n.2 configuration bits
: GPIOB-CRL_MODE3 ( %XX -- ) 12 lshift GPIOB-CRL bis! ; \ GPIOB-CRL_MODE3 Port n.3 mode bits
: GPIOB-CRL_CNF3 ( %XX -- ) 14 lshift GPIOB-CRL bis! ; \ GPIOB-CRL_CNF3 Port n.3 configuration bits
: GPIOB-CRL_MODE4 ( %XX -- ) 16 lshift GPIOB-CRL bis! ; \ GPIOB-CRL_MODE4 Port n.4 mode bits
: GPIOB-CRL_CNF4 ( %XX -- ) 18 lshift GPIOB-CRL bis! ; \ GPIOB-CRL_CNF4 Port n.4 configuration bits
: GPIOB-CRL_MODE5 ( %XX -- ) 20 lshift GPIOB-CRL bis! ; \ GPIOB-CRL_MODE5 Port n.5 mode bits
: GPIOB-CRL_CNF5 ( %XX -- ) 22 lshift GPIOB-CRL bis! ; \ GPIOB-CRL_CNF5 Port n.5 configuration bits
: GPIOB-CRL_MODE6 ( %XX -- ) 24 lshift GPIOB-CRL bis! ; \ GPIOB-CRL_MODE6 Port n.6 mode bits
: GPIOB-CRL_CNF6 ( %XX -- ) 26 lshift GPIOB-CRL bis! ; \ GPIOB-CRL_CNF6 Port n.6 configuration bits
: GPIOB-CRL_MODE7 ( %XX -- ) 28 lshift GPIOB-CRL bis! ; \ GPIOB-CRL_MODE7 Port n.7 mode bits
: GPIOB-CRL_CNF7 ( %XX -- ) 30 lshift GPIOB-CRL bis! ; \ GPIOB-CRL_CNF7 Port n.7 configuration bits
\ GPIOB-CRH (read-write)
: GPIOB-CRH_MODE8 ( %XX -- ) 0 lshift GPIOB-CRH bis! ; \ GPIOB-CRH_MODE8 Port n.8 mode bits
: GPIOB-CRH_CNF8 ( %XX -- ) 2 lshift GPIOB-CRH bis! ; \ GPIOB-CRH_CNF8 Port n.8 configuration bits
: GPIOB-CRH_MODE9 ( %XX -- ) 4 lshift GPIOB-CRH bis! ; \ GPIOB-CRH_MODE9 Port n.9 mode bits
: GPIOB-CRH_CNF9 ( %XX -- ) 6 lshift GPIOB-CRH bis! ; \ GPIOB-CRH_CNF9 Port n.9 configuration bits
: GPIOB-CRH_MODE10 ( %XX -- ) 8 lshift GPIOB-CRH bis! ; \ GPIOB-CRH_MODE10 Port n.10 mode bits
: GPIOB-CRH_CNF10 ( %XX -- ) 10 lshift GPIOB-CRH bis! ; \ GPIOB-CRH_CNF10 Port n.10 configuration bits
: GPIOB-CRH_MODE11 ( %XX -- ) 12 lshift GPIOB-CRH bis! ; \ GPIOB-CRH_MODE11 Port n.11 mode bits
: GPIOB-CRH_CNF11 ( %XX -- ) 14 lshift GPIOB-CRH bis! ; \ GPIOB-CRH_CNF11 Port n.11 configuration bits
: GPIOB-CRH_MODE12 ( %XX -- ) 16 lshift GPIOB-CRH bis! ; \ GPIOB-CRH_MODE12 Port n.12 mode bits
: GPIOB-CRH_CNF12 ( %XX -- ) 18 lshift GPIOB-CRH bis! ; \ GPIOB-CRH_CNF12 Port n.12 configuration bits
: GPIOB-CRH_MODE13 ( %XX -- ) 20 lshift GPIOB-CRH bis! ; \ GPIOB-CRH_MODE13 Port n.13 mode bits
: GPIOB-CRH_CNF13 ( %XX -- ) 22 lshift GPIOB-CRH bis! ; \ GPIOB-CRH_CNF13 Port n.13 configuration bits
: GPIOB-CRH_MODE14 ( %XX -- ) 24 lshift GPIOB-CRH bis! ; \ GPIOB-CRH_MODE14 Port n.14 mode bits
: GPIOB-CRH_CNF14 ( %XX -- ) 26 lshift GPIOB-CRH bis! ; \ GPIOB-CRH_CNF14 Port n.14 configuration bits
: GPIOB-CRH_MODE15 ( %XX -- ) 28 lshift GPIOB-CRH bis! ; \ GPIOB-CRH_MODE15 Port n.15 mode bits
: GPIOB-CRH_CNF15 ( %XX -- ) 30 lshift GPIOB-CRH bis! ; \ GPIOB-CRH_CNF15 Port n.15 configuration bits
\ GPIOB-IDR (read-only)
: GPIOB-IDR_IDR0 %1 0 lshift GPIOB-IDR bis! ; \ GPIOB-IDR_IDR0 Port input data
: GPIOB-IDR_IDR1 %1 1 lshift GPIOB-IDR bis! ; \ GPIOB-IDR_IDR1 Port input data
: GPIOB-IDR_IDR2 %1 2 lshift GPIOB-IDR bis! ; \ GPIOB-IDR_IDR2 Port input data
: GPIOB-IDR_IDR3 %1 3 lshift GPIOB-IDR bis! ; \ GPIOB-IDR_IDR3 Port input data
: GPIOB-IDR_IDR4 %1 4 lshift GPIOB-IDR bis! ; \ GPIOB-IDR_IDR4 Port input data
: GPIOB-IDR_IDR5 %1 5 lshift GPIOB-IDR bis! ; \ GPIOB-IDR_IDR5 Port input data
: GPIOB-IDR_IDR6 %1 6 lshift GPIOB-IDR bis! ; \ GPIOB-IDR_IDR6 Port input data
: GPIOB-IDR_IDR7 %1 7 lshift GPIOB-IDR bis! ; \ GPIOB-IDR_IDR7 Port input data
: GPIOB-IDR_IDR8 %1 8 lshift GPIOB-IDR bis! ; \ GPIOB-IDR_IDR8 Port input data
: GPIOB-IDR_IDR9 %1 9 lshift GPIOB-IDR bis! ; \ GPIOB-IDR_IDR9 Port input data
: GPIOB-IDR_IDR10 %1 10 lshift GPIOB-IDR bis! ; \ GPIOB-IDR_IDR10 Port input data
: GPIOB-IDR_IDR11 %1 11 lshift GPIOB-IDR bis! ; \ GPIOB-IDR_IDR11 Port input data
: GPIOB-IDR_IDR12 %1 12 lshift GPIOB-IDR bis! ; \ GPIOB-IDR_IDR12 Port input data
: GPIOB-IDR_IDR13 %1 13 lshift GPIOB-IDR bis! ; \ GPIOB-IDR_IDR13 Port input data
: GPIOB-IDR_IDR14 %1 14 lshift GPIOB-IDR bis! ; \ GPIOB-IDR_IDR14 Port input data
: GPIOB-IDR_IDR15 %1 15 lshift GPIOB-IDR bis! ; \ GPIOB-IDR_IDR15 Port input data
\ GPIOB-ODR (read-write)
: GPIOB-ODR_ODR0 %1 0 lshift GPIOB-ODR bis! ; \ GPIOB-ODR_ODR0 Port output data
: GPIOB-ODR_ODR1 %1 1 lshift GPIOB-ODR bis! ; \ GPIOB-ODR_ODR1 Port output data
: GPIOB-ODR_ODR2 %1 2 lshift GPIOB-ODR bis! ; \ GPIOB-ODR_ODR2 Port output data
: GPIOB-ODR_ODR3 %1 3 lshift GPIOB-ODR bis! ; \ GPIOB-ODR_ODR3 Port output data
: GPIOB-ODR_ODR4 %1 4 lshift GPIOB-ODR bis! ; \ GPIOB-ODR_ODR4 Port output data
: GPIOB-ODR_ODR5 %1 5 lshift GPIOB-ODR bis! ; \ GPIOB-ODR_ODR5 Port output data
: GPIOB-ODR_ODR6 %1 6 lshift GPIOB-ODR bis! ; \ GPIOB-ODR_ODR6 Port output data
: GPIOB-ODR_ODR7 %1 7 lshift GPIOB-ODR bis! ; \ GPIOB-ODR_ODR7 Port output data
: GPIOB-ODR_ODR8 %1 8 lshift GPIOB-ODR bis! ; \ GPIOB-ODR_ODR8 Port output data
: GPIOB-ODR_ODR9 %1 9 lshift GPIOB-ODR bis! ; \ GPIOB-ODR_ODR9 Port output data
: GPIOB-ODR_ODR10 %1 10 lshift GPIOB-ODR bis! ; \ GPIOB-ODR_ODR10 Port output data
: GPIOB-ODR_ODR11 %1 11 lshift GPIOB-ODR bis! ; \ GPIOB-ODR_ODR11 Port output data
: GPIOB-ODR_ODR12 %1 12 lshift GPIOB-ODR bis! ; \ GPIOB-ODR_ODR12 Port output data
: GPIOB-ODR_ODR13 %1 13 lshift GPIOB-ODR bis! ; \ GPIOB-ODR_ODR13 Port output data
: GPIOB-ODR_ODR14 %1 14 lshift GPIOB-ODR bis! ; \ GPIOB-ODR_ODR14 Port output data
: GPIOB-ODR_ODR15 %1 15 lshift GPIOB-ODR bis! ; \ GPIOB-ODR_ODR15 Port output data
\ GPIOB-BSRR (write-only)
: GPIOB-BSRR_BS0 %1 0 lshift GPIOB-BSRR bis! ; \ GPIOB-BSRR_BS0 Set bit 0
: GPIOB-BSRR_BS1 %1 1 lshift GPIOB-BSRR bis! ; \ GPIOB-BSRR_BS1 Set bit 1
: GPIOB-BSRR_BS2 %1 2 lshift GPIOB-BSRR bis! ; \ GPIOB-BSRR_BS2 Set bit 1
: GPIOB-BSRR_BS3 %1 3 lshift GPIOB-BSRR bis! ; \ GPIOB-BSRR_BS3 Set bit 3
: GPIOB-BSRR_BS4 %1 4 lshift GPIOB-BSRR bis! ; \ GPIOB-BSRR_BS4 Set bit 4
: GPIOB-BSRR_BS5 %1 5 lshift GPIOB-BSRR bis! ; \ GPIOB-BSRR_BS5 Set bit 5
: GPIOB-BSRR_BS6 %1 6 lshift GPIOB-BSRR bis! ; \ GPIOB-BSRR_BS6 Set bit 6
: GPIOB-BSRR_BS7 %1 7 lshift GPIOB-BSRR bis! ; \ GPIOB-BSRR_BS7 Set bit 7
: GPIOB-BSRR_BS8 %1 8 lshift GPIOB-BSRR bis! ; \ GPIOB-BSRR_BS8 Set bit 8
: GPIOB-BSRR_BS9 %1 9 lshift GPIOB-BSRR bis! ; \ GPIOB-BSRR_BS9 Set bit 9
: GPIOB-BSRR_BS10 %1 10 lshift GPIOB-BSRR bis! ; \ GPIOB-BSRR_BS10 Set bit 10
: GPIOB-BSRR_BS11 %1 11 lshift GPIOB-BSRR bis! ; \ GPIOB-BSRR_BS11 Set bit 11
: GPIOB-BSRR_BS12 %1 12 lshift GPIOB-BSRR bis! ; \ GPIOB-BSRR_BS12 Set bit 12
: GPIOB-BSRR_BS13 %1 13 lshift GPIOB-BSRR bis! ; \ GPIOB-BSRR_BS13 Set bit 13
: GPIOB-BSRR_BS14 %1 14 lshift GPIOB-BSRR bis! ; \ GPIOB-BSRR_BS14 Set bit 14
: GPIOB-BSRR_BS15 %1 15 lshift GPIOB-BSRR bis! ; \ GPIOB-BSRR_BS15 Set bit 15
: GPIOB-BSRR_BR0 %1 16 lshift GPIOB-BSRR bis! ; \ GPIOB-BSRR_BR0 Reset bit 0
: GPIOB-BSRR_BR1 %1 17 lshift GPIOB-BSRR bis! ; \ GPIOB-BSRR_BR1 Reset bit 1
: GPIOB-BSRR_BR2 %1 18 lshift GPIOB-BSRR bis! ; \ GPIOB-BSRR_BR2 Reset bit 2
: GPIOB-BSRR_BR3 %1 19 lshift GPIOB-BSRR bis! ; \ GPIOB-BSRR_BR3 Reset bit 3
: GPIOB-BSRR_BR4 %1 20 lshift GPIOB-BSRR bis! ; \ GPIOB-BSRR_BR4 Reset bit 4
: GPIOB-BSRR_BR5 %1 21 lshift GPIOB-BSRR bis! ; \ GPIOB-BSRR_BR5 Reset bit 5
: GPIOB-BSRR_BR6 %1 22 lshift GPIOB-BSRR bis! ; \ GPIOB-BSRR_BR6 Reset bit 6
: GPIOB-BSRR_BR7 %1 23 lshift GPIOB-BSRR bis! ; \ GPIOB-BSRR_BR7 Reset bit 7
: GPIOB-BSRR_BR8 %1 24 lshift GPIOB-BSRR bis! ; \ GPIOB-BSRR_BR8 Reset bit 8
: GPIOB-BSRR_BR9 %1 25 lshift GPIOB-BSRR bis! ; \ GPIOB-BSRR_BR9 Reset bit 9
: GPIOB-BSRR_BR10 %1 26 lshift GPIOB-BSRR bis! ; \ GPIOB-BSRR_BR10 Reset bit 10
: GPIOB-BSRR_BR11 %1 27 lshift GPIOB-BSRR bis! ; \ GPIOB-BSRR_BR11 Reset bit 11
: GPIOB-BSRR_BR12 %1 28 lshift GPIOB-BSRR bis! ; \ GPIOB-BSRR_BR12 Reset bit 12
: GPIOB-BSRR_BR13 %1 29 lshift GPIOB-BSRR bis! ; \ GPIOB-BSRR_BR13 Reset bit 13
: GPIOB-BSRR_BR14 %1 30 lshift GPIOB-BSRR bis! ; \ GPIOB-BSRR_BR14 Reset bit 14
: GPIOB-BSRR_BR15 %1 31 lshift GPIOB-BSRR bis! ; \ GPIOB-BSRR_BR15 Reset bit 15
\ GPIOB-BRR (write-only)
: GPIOB-BRR_BR0 %1 0 lshift GPIOB-BRR bis! ; \ GPIOB-BRR_BR0 Reset bit 0
: GPIOB-BRR_BR1 %1 1 lshift GPIOB-BRR bis! ; \ GPIOB-BRR_BR1 Reset bit 1
: GPIOB-BRR_BR2 %1 2 lshift GPIOB-BRR bis! ; \ GPIOB-BRR_BR2 Reset bit 1
: GPIOB-BRR_BR3 %1 3 lshift GPIOB-BRR bis! ; \ GPIOB-BRR_BR3 Reset bit 3
: GPIOB-BRR_BR4 %1 4 lshift GPIOB-BRR bis! ; \ GPIOB-BRR_BR4 Reset bit 4
: GPIOB-BRR_BR5 %1 5 lshift GPIOB-BRR bis! ; \ GPIOB-BRR_BR5 Reset bit 5
: GPIOB-BRR_BR6 %1 6 lshift GPIOB-BRR bis! ; \ GPIOB-BRR_BR6 Reset bit 6
: GPIOB-BRR_BR7 %1 7 lshift GPIOB-BRR bis! ; \ GPIOB-BRR_BR7 Reset bit 7
: GPIOB-BRR_BR8 %1 8 lshift GPIOB-BRR bis! ; \ GPIOB-BRR_BR8 Reset bit 8
: GPIOB-BRR_BR9 %1 9 lshift GPIOB-BRR bis! ; \ GPIOB-BRR_BR9 Reset bit 9
: GPIOB-BRR_BR10 %1 10 lshift GPIOB-BRR bis! ; \ GPIOB-BRR_BR10 Reset bit 10
: GPIOB-BRR_BR11 %1 11 lshift GPIOB-BRR bis! ; \ GPIOB-BRR_BR11 Reset bit 11
: GPIOB-BRR_BR12 %1 12 lshift GPIOB-BRR bis! ; \ GPIOB-BRR_BR12 Reset bit 12
: GPIOB-BRR_BR13 %1 13 lshift GPIOB-BRR bis! ; \ GPIOB-BRR_BR13 Reset bit 13
: GPIOB-BRR_BR14 %1 14 lshift GPIOB-BRR bis! ; \ GPIOB-BRR_BR14 Reset bit 14
: GPIOB-BRR_BR15 %1 15 lshift GPIOB-BRR bis! ; \ GPIOB-BRR_BR15 Reset bit 15
\ GPIOB-LCKR (read-write)
: GPIOB-LCKR_LCK0 %1 0 lshift GPIOB-LCKR bis! ; \ GPIOB-LCKR_LCK0 Port A Lock bit 0
: GPIOB-LCKR_LCK1 %1 1 lshift GPIOB-LCKR bis! ; \ GPIOB-LCKR_LCK1 Port A Lock bit 1
: GPIOB-LCKR_LCK2 %1 2 lshift GPIOB-LCKR bis! ; \ GPIOB-LCKR_LCK2 Port A Lock bit 2
: GPIOB-LCKR_LCK3 %1 3 lshift GPIOB-LCKR bis! ; \ GPIOB-LCKR_LCK3 Port A Lock bit 3
: GPIOB-LCKR_LCK4 %1 4 lshift GPIOB-LCKR bis! ; \ GPIOB-LCKR_LCK4 Port A Lock bit 4
: GPIOB-LCKR_LCK5 %1 5 lshift GPIOB-LCKR bis! ; \ GPIOB-LCKR_LCK5 Port A Lock bit 5
: GPIOB-LCKR_LCK6 %1 6 lshift GPIOB-LCKR bis! ; \ GPIOB-LCKR_LCK6 Port A Lock bit 6
: GPIOB-LCKR_LCK7 %1 7 lshift GPIOB-LCKR bis! ; \ GPIOB-LCKR_LCK7 Port A Lock bit 7
: GPIOB-LCKR_LCK8 %1 8 lshift GPIOB-LCKR bis! ; \ GPIOB-LCKR_LCK8 Port A Lock bit 8
: GPIOB-LCKR_LCK9 %1 9 lshift GPIOB-LCKR bis! ; \ GPIOB-LCKR_LCK9 Port A Lock bit 9
: GPIOB-LCKR_LCK10 %1 10 lshift GPIOB-LCKR bis! ; \ GPIOB-LCKR_LCK10 Port A Lock bit 10
: GPIOB-LCKR_LCK11 %1 11 lshift GPIOB-LCKR bis! ; \ GPIOB-LCKR_LCK11 Port A Lock bit 11
: GPIOB-LCKR_LCK12 %1 12 lshift GPIOB-LCKR bis! ; \ GPIOB-LCKR_LCK12 Port A Lock bit 12
: GPIOB-LCKR_LCK13 %1 13 lshift GPIOB-LCKR bis! ; \ GPIOB-LCKR_LCK13 Port A Lock bit 13
: GPIOB-LCKR_LCK14 %1 14 lshift GPIOB-LCKR bis! ; \ GPIOB-LCKR_LCK14 Port A Lock bit 14
: GPIOB-LCKR_LCK15 %1 15 lshift GPIOB-LCKR bis! ; \ GPIOB-LCKR_LCK15 Port A Lock bit 15
: GPIOB-LCKR_LCKK %1 16 lshift GPIOB-LCKR bis! ; \ GPIOB-LCKR_LCKK Lock key
\ GPIOC-CRL (read-write)
: GPIOC-CRL_MODE0 ( %XX -- ) 0 lshift GPIOC-CRL bis! ; \ GPIOC-CRL_MODE0 Port n.0 mode bits
: GPIOC-CRL_CNF0 ( %XX -- ) 2 lshift GPIOC-CRL bis! ; \ GPIOC-CRL_CNF0 Port n.0 configuration bits
: GPIOC-CRL_MODE1 ( %XX -- ) 4 lshift GPIOC-CRL bis! ; \ GPIOC-CRL_MODE1 Port n.1 mode bits
: GPIOC-CRL_CNF1 ( %XX -- ) 6 lshift GPIOC-CRL bis! ; \ GPIOC-CRL_CNF1 Port n.1 configuration bits
: GPIOC-CRL_MODE2 ( %XX -- ) 8 lshift GPIOC-CRL bis! ; \ GPIOC-CRL_MODE2 Port n.2 mode bits
: GPIOC-CRL_CNF2 ( %XX -- ) 10 lshift GPIOC-CRL bis! ; \ GPIOC-CRL_CNF2 Port n.2 configuration bits
: GPIOC-CRL_MODE3 ( %XX -- ) 12 lshift GPIOC-CRL bis! ; \ GPIOC-CRL_MODE3 Port n.3 mode bits
: GPIOC-CRL_CNF3 ( %XX -- ) 14 lshift GPIOC-CRL bis! ; \ GPIOC-CRL_CNF3 Port n.3 configuration bits
: GPIOC-CRL_MODE4 ( %XX -- ) 16 lshift GPIOC-CRL bis! ; \ GPIOC-CRL_MODE4 Port n.4 mode bits
: GPIOC-CRL_CNF4 ( %XX -- ) 18 lshift GPIOC-CRL bis! ; \ GPIOC-CRL_CNF4 Port n.4 configuration bits
: GPIOC-CRL_MODE5 ( %XX -- ) 20 lshift GPIOC-CRL bis! ; \ GPIOC-CRL_MODE5 Port n.5 mode bits
: GPIOC-CRL_CNF5 ( %XX -- ) 22 lshift GPIOC-CRL bis! ; \ GPIOC-CRL_CNF5 Port n.5 configuration bits
: GPIOC-CRL_MODE6 ( %XX -- ) 24 lshift GPIOC-CRL bis! ; \ GPIOC-CRL_MODE6 Port n.6 mode bits
: GPIOC-CRL_CNF6 ( %XX -- ) 26 lshift GPIOC-CRL bis! ; \ GPIOC-CRL_CNF6 Port n.6 configuration bits
: GPIOC-CRL_MODE7 ( %XX -- ) 28 lshift GPIOC-CRL bis! ; \ GPIOC-CRL_MODE7 Port n.7 mode bits
: GPIOC-CRL_CNF7 ( %XX -- ) 30 lshift GPIOC-CRL bis! ; \ GPIOC-CRL_CNF7 Port n.7 configuration bits
\ GPIOC-CRH (read-write)
: GPIOC-CRH_MODE8 ( %XX -- ) 0 lshift GPIOC-CRH bis! ; \ GPIOC-CRH_MODE8 Port n.8 mode bits
: GPIOC-CRH_CNF8 ( %XX -- ) 2 lshift GPIOC-CRH bis! ; \ GPIOC-CRH_CNF8 Port n.8 configuration bits
: GPIOC-CRH_MODE9 ( %XX -- ) 4 lshift GPIOC-CRH bis! ; \ GPIOC-CRH_MODE9 Port n.9 mode bits
: GPIOC-CRH_CNF9 ( %XX -- ) 6 lshift GPIOC-CRH bis! ; \ GPIOC-CRH_CNF9 Port n.9 configuration bits
: GPIOC-CRH_MODE10 ( %XX -- ) 8 lshift GPIOC-CRH bis! ; \ GPIOC-CRH_MODE10 Port n.10 mode bits
: GPIOC-CRH_CNF10 ( %XX -- ) 10 lshift GPIOC-CRH bis! ; \ GPIOC-CRH_CNF10 Port n.10 configuration bits
: GPIOC-CRH_MODE11 ( %XX -- ) 12 lshift GPIOC-CRH bis! ; \ GPIOC-CRH_MODE11 Port n.11 mode bits
: GPIOC-CRH_CNF11 ( %XX -- ) 14 lshift GPIOC-CRH bis! ; \ GPIOC-CRH_CNF11 Port n.11 configuration bits
: GPIOC-CRH_MODE12 ( %XX -- ) 16 lshift GPIOC-CRH bis! ; \ GPIOC-CRH_MODE12 Port n.12 mode bits
: GPIOC-CRH_CNF12 ( %XX -- ) 18 lshift GPIOC-CRH bis! ; \ GPIOC-CRH_CNF12 Port n.12 configuration bits
: GPIOC-CRH_MODE13 ( %XX -- ) 20 lshift GPIOC-CRH bis! ; \ GPIOC-CRH_MODE13 Port n.13 mode bits
: GPIOC-CRH_CNF13 ( %XX -- ) 22 lshift GPIOC-CRH bis! ; \ GPIOC-CRH_CNF13 Port n.13 configuration bits
: GPIOC-CRH_MODE14 ( %XX -- ) 24 lshift GPIOC-CRH bis! ; \ GPIOC-CRH_MODE14 Port n.14 mode bits
: GPIOC-CRH_CNF14 ( %XX -- ) 26 lshift GPIOC-CRH bis! ; \ GPIOC-CRH_CNF14 Port n.14 configuration bits
: GPIOC-CRH_MODE15 ( %XX -- ) 28 lshift GPIOC-CRH bis! ; \ GPIOC-CRH_MODE15 Port n.15 mode bits
: GPIOC-CRH_CNF15 ( %XX -- ) 30 lshift GPIOC-CRH bis! ; \ GPIOC-CRH_CNF15 Port n.15 configuration bits
\ GPIOC-IDR (read-only)
: GPIOC-IDR_IDR0 %1 0 lshift GPIOC-IDR bis! ; \ GPIOC-IDR_IDR0 Port input data
: GPIOC-IDR_IDR1 %1 1 lshift GPIOC-IDR bis! ; \ GPIOC-IDR_IDR1 Port input data
: GPIOC-IDR_IDR2 %1 2 lshift GPIOC-IDR bis! ; \ GPIOC-IDR_IDR2 Port input data
: GPIOC-IDR_IDR3 %1 3 lshift GPIOC-IDR bis! ; \ GPIOC-IDR_IDR3 Port input data
: GPIOC-IDR_IDR4 %1 4 lshift GPIOC-IDR bis! ; \ GPIOC-IDR_IDR4 Port input data
: GPIOC-IDR_IDR5 %1 5 lshift GPIOC-IDR bis! ; \ GPIOC-IDR_IDR5 Port input data
: GPIOC-IDR_IDR6 %1 6 lshift GPIOC-IDR bis! ; \ GPIOC-IDR_IDR6 Port input data
: GPIOC-IDR_IDR7 %1 7 lshift GPIOC-IDR bis! ; \ GPIOC-IDR_IDR7 Port input data
: GPIOC-IDR_IDR8 %1 8 lshift GPIOC-IDR bis! ; \ GPIOC-IDR_IDR8 Port input data
: GPIOC-IDR_IDR9 %1 9 lshift GPIOC-IDR bis! ; \ GPIOC-IDR_IDR9 Port input data
: GPIOC-IDR_IDR10 %1 10 lshift GPIOC-IDR bis! ; \ GPIOC-IDR_IDR10 Port input data
: GPIOC-IDR_IDR11 %1 11 lshift GPIOC-IDR bis! ; \ GPIOC-IDR_IDR11 Port input data
: GPIOC-IDR_IDR12 %1 12 lshift GPIOC-IDR bis! ; \ GPIOC-IDR_IDR12 Port input data
: GPIOC-IDR_IDR13 %1 13 lshift GPIOC-IDR bis! ; \ GPIOC-IDR_IDR13 Port input data
: GPIOC-IDR_IDR14 %1 14 lshift GPIOC-IDR bis! ; \ GPIOC-IDR_IDR14 Port input data
: GPIOC-IDR_IDR15 %1 15 lshift GPIOC-IDR bis! ; \ GPIOC-IDR_IDR15 Port input data
\ GPIOC-ODR (read-write)
: GPIOC-ODR_ODR0 %1 0 lshift GPIOC-ODR bis! ; \ GPIOC-ODR_ODR0 Port output data
: GPIOC-ODR_ODR1 %1 1 lshift GPIOC-ODR bis! ; \ GPIOC-ODR_ODR1 Port output data
: GPIOC-ODR_ODR2 %1 2 lshift GPIOC-ODR bis! ; \ GPIOC-ODR_ODR2 Port output data
: GPIOC-ODR_ODR3 %1 3 lshift GPIOC-ODR bis! ; \ GPIOC-ODR_ODR3 Port output data
: GPIOC-ODR_ODR4 %1 4 lshift GPIOC-ODR bis! ; \ GPIOC-ODR_ODR4 Port output data
: GPIOC-ODR_ODR5 %1 5 lshift GPIOC-ODR bis! ; \ GPIOC-ODR_ODR5 Port output data
: GPIOC-ODR_ODR6 %1 6 lshift GPIOC-ODR bis! ; \ GPIOC-ODR_ODR6 Port output data
: GPIOC-ODR_ODR7 %1 7 lshift GPIOC-ODR bis! ; \ GPIOC-ODR_ODR7 Port output data
: GPIOC-ODR_ODR8 %1 8 lshift GPIOC-ODR bis! ; \ GPIOC-ODR_ODR8 Port output data
: GPIOC-ODR_ODR9 %1 9 lshift GPIOC-ODR bis! ; \ GPIOC-ODR_ODR9 Port output data
: GPIOC-ODR_ODR10 %1 10 lshift GPIOC-ODR bis! ; \ GPIOC-ODR_ODR10 Port output data
: GPIOC-ODR_ODR11 %1 11 lshift GPIOC-ODR bis! ; \ GPIOC-ODR_ODR11 Port output data
: GPIOC-ODR_ODR12 %1 12 lshift GPIOC-ODR bis! ; \ GPIOC-ODR_ODR12 Port output data
: GPIOC-ODR_ODR13 %1 13 lshift GPIOC-ODR bis! ; \ GPIOC-ODR_ODR13 Port output data
: GPIOC-ODR_ODR14 %1 14 lshift GPIOC-ODR bis! ; \ GPIOC-ODR_ODR14 Port output data
: GPIOC-ODR_ODR15 %1 15 lshift GPIOC-ODR bis! ; \ GPIOC-ODR_ODR15 Port output data
\ GPIOC-BSRR (write-only)
: GPIOC-BSRR_BS0 %1 0 lshift GPIOC-BSRR bis! ; \ GPIOC-BSRR_BS0 Set bit 0
: GPIOC-BSRR_BS1 %1 1 lshift GPIOC-BSRR bis! ; \ GPIOC-BSRR_BS1 Set bit 1
: GPIOC-BSRR_BS2 %1 2 lshift GPIOC-BSRR bis! ; \ GPIOC-BSRR_BS2 Set bit 1
: GPIOC-BSRR_BS3 %1 3 lshift GPIOC-BSRR bis! ; \ GPIOC-BSRR_BS3 Set bit 3
: GPIOC-BSRR_BS4 %1 4 lshift GPIOC-BSRR bis! ; \ GPIOC-BSRR_BS4 Set bit 4
: GPIOC-BSRR_BS5 %1 5 lshift GPIOC-BSRR bis! ; \ GPIOC-BSRR_BS5 Set bit 5
: GPIOC-BSRR_BS6 %1 6 lshift GPIOC-BSRR bis! ; \ GPIOC-BSRR_BS6 Set bit 6
: GPIOC-BSRR_BS7 %1 7 lshift GPIOC-BSRR bis! ; \ GPIOC-BSRR_BS7 Set bit 7
: GPIOC-BSRR_BS8 %1 8 lshift GPIOC-BSRR bis! ; \ GPIOC-BSRR_BS8 Set bit 8
: GPIOC-BSRR_BS9 %1 9 lshift GPIOC-BSRR bis! ; \ GPIOC-BSRR_BS9 Set bit 9
: GPIOC-BSRR_BS10 %1 10 lshift GPIOC-BSRR bis! ; \ GPIOC-BSRR_BS10 Set bit 10
: GPIOC-BSRR_BS11 %1 11 lshift GPIOC-BSRR bis! ; \ GPIOC-BSRR_BS11 Set bit 11
: GPIOC-BSRR_BS12 %1 12 lshift GPIOC-BSRR bis! ; \ GPIOC-BSRR_BS12 Set bit 12
: GPIOC-BSRR_BS13 %1 13 lshift GPIOC-BSRR bis! ; \ GPIOC-BSRR_BS13 Set bit 13
: GPIOC-BSRR_BS14 %1 14 lshift GPIOC-BSRR bis! ; \ GPIOC-BSRR_BS14 Set bit 14
: GPIOC-BSRR_BS15 %1 15 lshift GPIOC-BSRR bis! ; \ GPIOC-BSRR_BS15 Set bit 15
: GPIOC-BSRR_BR0 %1 16 lshift GPIOC-BSRR bis! ; \ GPIOC-BSRR_BR0 Reset bit 0
: GPIOC-BSRR_BR1 %1 17 lshift GPIOC-BSRR bis! ; \ GPIOC-BSRR_BR1 Reset bit 1
: GPIOC-BSRR_BR2 %1 18 lshift GPIOC-BSRR bis! ; \ GPIOC-BSRR_BR2 Reset bit 2
: GPIOC-BSRR_BR3 %1 19 lshift GPIOC-BSRR bis! ; \ GPIOC-BSRR_BR3 Reset bit 3
: GPIOC-BSRR_BR4 %1 20 lshift GPIOC-BSRR bis! ; \ GPIOC-BSRR_BR4 Reset bit 4
: GPIOC-BSRR_BR5 %1 21 lshift GPIOC-BSRR bis! ; \ GPIOC-BSRR_BR5 Reset bit 5
: GPIOC-BSRR_BR6 %1 22 lshift GPIOC-BSRR bis! ; \ GPIOC-BSRR_BR6 Reset bit 6
: GPIOC-BSRR_BR7 %1 23 lshift GPIOC-BSRR bis! ; \ GPIOC-BSRR_BR7 Reset bit 7
: GPIOC-BSRR_BR8 %1 24 lshift GPIOC-BSRR bis! ; \ GPIOC-BSRR_BR8 Reset bit 8
: GPIOC-BSRR_BR9 %1 25 lshift GPIOC-BSRR bis! ; \ GPIOC-BSRR_BR9 Reset bit 9
: GPIOC-BSRR_BR10 %1 26 lshift GPIOC-BSRR bis! ; \ GPIOC-BSRR_BR10 Reset bit 10
: GPIOC-BSRR_BR11 %1 27 lshift GPIOC-BSRR bis! ; \ GPIOC-BSRR_BR11 Reset bit 11
: GPIOC-BSRR_BR12 %1 28 lshift GPIOC-BSRR bis! ; \ GPIOC-BSRR_BR12 Reset bit 12
: GPIOC-BSRR_BR13 %1 29 lshift GPIOC-BSRR bis! ; \ GPIOC-BSRR_BR13 Reset bit 13
: GPIOC-BSRR_BR14 %1 30 lshift GPIOC-BSRR bis! ; \ GPIOC-BSRR_BR14 Reset bit 14
: GPIOC-BSRR_BR15 %1 31 lshift GPIOC-BSRR bis! ; \ GPIOC-BSRR_BR15 Reset bit 15
\ GPIOC-BRR (write-only)
: GPIOC-BRR_BR0 %1 0 lshift GPIOC-BRR bis! ; \ GPIOC-BRR_BR0 Reset bit 0
: GPIOC-BRR_BR1 %1 1 lshift GPIOC-BRR bis! ; \ GPIOC-BRR_BR1 Reset bit 1
: GPIOC-BRR_BR2 %1 2 lshift GPIOC-BRR bis! ; \ GPIOC-BRR_BR2 Reset bit 1
: GPIOC-BRR_BR3 %1 3 lshift GPIOC-BRR bis! ; \ GPIOC-BRR_BR3 Reset bit 3
: GPIOC-BRR_BR4 %1 4 lshift GPIOC-BRR bis! ; \ GPIOC-BRR_BR4 Reset bit 4
: GPIOC-BRR_BR5 %1 5 lshift GPIOC-BRR bis! ; \ GPIOC-BRR_BR5 Reset bit 5
: GPIOC-BRR_BR6 %1 6 lshift GPIOC-BRR bis! ; \ GPIOC-BRR_BR6 Reset bit 6
: GPIOC-BRR_BR7 %1 7 lshift GPIOC-BRR bis! ; \ GPIOC-BRR_BR7 Reset bit 7
: GPIOC-BRR_BR8 %1 8 lshift GPIOC-BRR bis! ; \ GPIOC-BRR_BR8 Reset bit 8
: GPIOC-BRR_BR9 %1 9 lshift GPIOC-BRR bis! ; \ GPIOC-BRR_BR9 Reset bit 9
: GPIOC-BRR_BR10 %1 10 lshift GPIOC-BRR bis! ; \ GPIOC-BRR_BR10 Reset bit 10
: GPIOC-BRR_BR11 %1 11 lshift GPIOC-BRR bis! ; \ GPIOC-BRR_BR11 Reset bit 11
: GPIOC-BRR_BR12 %1 12 lshift GPIOC-BRR bis! ; \ GPIOC-BRR_BR12 Reset bit 12
: GPIOC-BRR_BR13 %1 13 lshift GPIOC-BRR bis! ; \ GPIOC-BRR_BR13 Reset bit 13
: GPIOC-BRR_BR14 %1 14 lshift GPIOC-BRR bis! ; \ GPIOC-BRR_BR14 Reset bit 14
: GPIOC-BRR_BR15 %1 15 lshift GPIOC-BRR bis! ; \ GPIOC-BRR_BR15 Reset bit 15
\ GPIOC-LCKR (read-write)
: GPIOC-LCKR_LCK0 %1 0 lshift GPIOC-LCKR bis! ; \ GPIOC-LCKR_LCK0 Port A Lock bit 0
: GPIOC-LCKR_LCK1 %1 1 lshift GPIOC-LCKR bis! ; \ GPIOC-LCKR_LCK1 Port A Lock bit 1
: GPIOC-LCKR_LCK2 %1 2 lshift GPIOC-LCKR bis! ; \ GPIOC-LCKR_LCK2 Port A Lock bit 2
: GPIOC-LCKR_LCK3 %1 3 lshift GPIOC-LCKR bis! ; \ GPIOC-LCKR_LCK3 Port A Lock bit 3
: GPIOC-LCKR_LCK4 %1 4 lshift GPIOC-LCKR bis! ; \ GPIOC-LCKR_LCK4 Port A Lock bit 4
: GPIOC-LCKR_LCK5 %1 5 lshift GPIOC-LCKR bis! ; \ GPIOC-LCKR_LCK5 Port A Lock bit 5
: GPIOC-LCKR_LCK6 %1 6 lshift GPIOC-LCKR bis! ; \ GPIOC-LCKR_LCK6 Port A Lock bit 6
: GPIOC-LCKR_LCK7 %1 7 lshift GPIOC-LCKR bis! ; \ GPIOC-LCKR_LCK7 Port A Lock bit 7
: GPIOC-LCKR_LCK8 %1 8 lshift GPIOC-LCKR bis! ; \ GPIOC-LCKR_LCK8 Port A Lock bit 8
: GPIOC-LCKR_LCK9 %1 9 lshift GPIOC-LCKR bis! ; \ GPIOC-LCKR_LCK9 Port A Lock bit 9
: GPIOC-LCKR_LCK10 %1 10 lshift GPIOC-LCKR bis! ; \ GPIOC-LCKR_LCK10 Port A Lock bit 10
: GPIOC-LCKR_LCK11 %1 11 lshift GPIOC-LCKR bis! ; \ GPIOC-LCKR_LCK11 Port A Lock bit 11
: GPIOC-LCKR_LCK12 %1 12 lshift GPIOC-LCKR bis! ; \ GPIOC-LCKR_LCK12 Port A Lock bit 12
: GPIOC-LCKR_LCK13 %1 13 lshift GPIOC-LCKR bis! ; \ GPIOC-LCKR_LCK13 Port A Lock bit 13
: GPIOC-LCKR_LCK14 %1 14 lshift GPIOC-LCKR bis! ; \ GPIOC-LCKR_LCK14 Port A Lock bit 14
: GPIOC-LCKR_LCK15 %1 15 lshift GPIOC-LCKR bis! ; \ GPIOC-LCKR_LCK15 Port A Lock bit 15
: GPIOC-LCKR_LCKK %1 16 lshift GPIOC-LCKR bis! ; \ GPIOC-LCKR_LCKK Lock key
\ AFIO-EVCR (read-write)
: AFIO-EVCR_PIN ( %XXXX -- ) 0 lshift AFIO-EVCR bis! ; \ AFIO-EVCR_PIN Pin selection
: AFIO-EVCR_PORT ( %XXX -- ) 4 lshift AFIO-EVCR bis! ; \ AFIO-EVCR_PORT Port selection
: AFIO-EVCR_EVOE %1 7 lshift AFIO-EVCR bis! ; \ AFIO-EVCR_EVOE Event Output Enable
\ AFIO-MAPR ()
: AFIO-MAPR_SPI1_REMAP %1 0 lshift AFIO-MAPR bis! ; \ AFIO-MAPR_SPI1_REMAP SPI1 remapping
: AFIO-MAPR_I2C1_REMAP %1 1 lshift AFIO-MAPR bis! ; \ AFIO-MAPR_I2C1_REMAP I2C1 remapping
: AFIO-MAPR_USART1_REMAP %1 2 lshift AFIO-MAPR bis! ; \ AFIO-MAPR_USART1_REMAP USART1 remapping
: AFIO-MAPR_USART2_REMAP %1 3 lshift AFIO-MAPR bis! ; \ AFIO-MAPR_USART2_REMAP USART2 remapping
: AFIO-MAPR_USART3_REMAP ( %XX -- ) 4 lshift AFIO-MAPR bis! ; \ AFIO-MAPR_USART3_REMAP USART3 remapping
: AFIO-MAPR_TIM1_REMAP ( %XX -- ) 6 lshift AFIO-MAPR bis! ; \ AFIO-MAPR_TIM1_REMAP TIM1 remapping
: AFIO-MAPR_TIM2_REMAP ( %XX -- ) 8 lshift AFIO-MAPR bis! ; \ AFIO-MAPR_TIM2_REMAP TIM2 remapping
: AFIO-MAPR_TIM3_REMAP ( %XX -- ) 10 lshift AFIO-MAPR bis! ; \ AFIO-MAPR_TIM3_REMAP TIM3 remapping
: AFIO-MAPR_TIM4_REMAP %1 12 lshift AFIO-MAPR bis! ; \ AFIO-MAPR_TIM4_REMAP TIM4 remapping
: AFIO-MAPR_CAN_REMAP ( %XX -- ) 13 lshift AFIO-MAPR bis! ; \ AFIO-MAPR_CAN_REMAP CAN1 remapping
: AFIO-MAPR_PD01_REMAP %1 15 lshift AFIO-MAPR bis! ; \ AFIO-MAPR_PD01_REMAP Port D0/Port D1 mapping on OSCIN/OSCOUT
: AFIO-MAPR_TIM5CH4_IREMAP %1 16 lshift AFIO-MAPR bis! ; \ AFIO-MAPR_TIM5CH4_IREMAP Set and cleared by software
: AFIO-MAPR_ADC1_ETRGINJ_REMAP %1 17 lshift AFIO-MAPR bis! ; \ AFIO-MAPR_ADC1_ETRGINJ_REMAP ADC 1 External trigger injected conversion remapping
: AFIO-MAPR_ADC1_ETRGREG_REMAP %1 18 lshift AFIO-MAPR bis! ; \ AFIO-MAPR_ADC1_ETRGREG_REMAP ADC 1 external trigger regular conversion remapping
: AFIO-MAPR_ADC2_ETRGINJ_REMAP %1 19 lshift AFIO-MAPR bis! ; \ AFIO-MAPR_ADC2_ETRGINJ_REMAP ADC 2 external trigger injected conversion remapping
: AFIO-MAPR_ADC2_ETRGREG_REMAP %1 20 lshift AFIO-MAPR bis! ; \ AFIO-MAPR_ADC2_ETRGREG_REMAP ADC 2 external trigger regular conversion remapping
: AFIO-MAPR_SWJ_CFG ( %XXX -- ) 24 lshift AFIO-MAPR bis! ; \ AFIO-MAPR_SWJ_CFG Serial wire JTAG configuration
\ AFIO-EXTICR1 (read-write)
: AFIO-EXTICR1_EXTI0 ( %XXXX -- ) 0 lshift AFIO-EXTICR1 bis! ; \ AFIO-EXTICR1_EXTI0 EXTI0 configuration
: AFIO-EXTICR1_EXTI1 ( %XXXX -- ) 4 lshift AFIO-EXTICR1 bis! ; \ AFIO-EXTICR1_EXTI1 EXTI1 configuration
: AFIO-EXTICR1_EXTI2 ( %XXXX -- ) 8 lshift AFIO-EXTICR1 bis! ; \ AFIO-EXTICR1_EXTI2 EXTI2 configuration
: AFIO-EXTICR1_EXTI3 ( %XXXX -- ) 12 lshift AFIO-EXTICR1 bis! ; \ AFIO-EXTICR1_EXTI3 EXTI3 configuration
\ AFIO-EXTICR2 (read-write)
: AFIO-EXTICR2_EXTI4 ( %XXXX -- ) 0 lshift AFIO-EXTICR2 bis! ; \ AFIO-EXTICR2_EXTI4 EXTI4 configuration
: AFIO-EXTICR2_EXTI5 ( %XXXX -- ) 4 lshift AFIO-EXTICR2 bis! ; \ AFIO-EXTICR2_EXTI5 EXTI5 configuration
: AFIO-EXTICR2_EXTI6 ( %XXXX -- ) 8 lshift AFIO-EXTICR2 bis! ; \ AFIO-EXTICR2_EXTI6 EXTI6 configuration
: AFIO-EXTICR2_EXTI7 ( %XXXX -- ) 12 lshift AFIO-EXTICR2 bis! ; \ AFIO-EXTICR2_EXTI7 EXTI7 configuration
\ AFIO-EXTICR3 (read-write)
: AFIO-EXTICR3_EXTI8 ( %XXXX -- ) 0 lshift AFIO-EXTICR3 bis! ; \ AFIO-EXTICR3_EXTI8 EXTI8 configuration
: AFIO-EXTICR3_EXTI9 ( %XXXX -- ) 4 lshift AFIO-EXTICR3 bis! ; \ AFIO-EXTICR3_EXTI9 EXTI9 configuration
: AFIO-EXTICR3_EXTI10 ( %XXXX -- ) 8 lshift AFIO-EXTICR3 bis! ; \ AFIO-EXTICR3_EXTI10 EXTI10 configuration
: AFIO-EXTICR3_EXTI11 ( %XXXX -- ) 12 lshift AFIO-EXTICR3 bis! ; \ AFIO-EXTICR3_EXTI11 EXTI11 configuration
\ AFIO-EXTICR4 (read-write)
: AFIO-EXTICR4_EXTI12 ( %XXXX -- ) 0 lshift AFIO-EXTICR4 bis! ; \ AFIO-EXTICR4_EXTI12 EXTI12 configuration
: AFIO-EXTICR4_EXTI13 ( %XXXX -- ) 4 lshift AFIO-EXTICR4 bis! ; \ AFIO-EXTICR4_EXTI13 EXTI13 configuration
: AFIO-EXTICR4_EXTI14 ( %XXXX -- ) 8 lshift AFIO-EXTICR4 bis! ; \ AFIO-EXTICR4_EXTI14 EXTI14 configuration
: AFIO-EXTICR4_EXTI15 ( %XXXX -- ) 12 lshift AFIO-EXTICR4 bis! ; \ AFIO-EXTICR4_EXTI15 EXTI15 configuration
\ AFIO-MAPR2 (read-write)
: AFIO-MAPR2_TIM9_REMAP %1 5 lshift AFIO-MAPR2 bis! ; \ AFIO-MAPR2_TIM9_REMAP TIM9 remapping
: AFIO-MAPR2_TIM10_REMAP %1 6 lshift AFIO-MAPR2 bis! ; \ AFIO-MAPR2_TIM10_REMAP TIM10 remapping
: AFIO-MAPR2_TIM11_REMAP %1 7 lshift AFIO-MAPR2 bis! ; \ AFIO-MAPR2_TIM11_REMAP TIM11 remapping
: AFIO-MAPR2_TIM13_REMAP %1 8 lshift AFIO-MAPR2 bis! ; \ AFIO-MAPR2_TIM13_REMAP TIM13 remapping
: AFIO-MAPR2_TIM14_REMAP %1 9 lshift AFIO-MAPR2 bis! ; \ AFIO-MAPR2_TIM14_REMAP TIM14 remapping
: AFIO-MAPR2_FSMC_NADV %1 10 lshift AFIO-MAPR2 bis! ; \ AFIO-MAPR2_FSMC_NADV NADV connect/disconnect
\ EXTI-IMR (read-write)
: EXTI-IMR_MR0 %1 0 lshift EXTI-IMR bis! ; \ EXTI-IMR_MR0 Interrupt Mask on line 0
: EXTI-IMR_MR1 %1 1 lshift EXTI-IMR bis! ; \ EXTI-IMR_MR1 Interrupt Mask on line 1
: EXTI-IMR_MR2 %1 2 lshift EXTI-IMR bis! ; \ EXTI-IMR_MR2 Interrupt Mask on line 2
: EXTI-IMR_MR3 %1 3 lshift EXTI-IMR bis! ; \ EXTI-IMR_MR3 Interrupt Mask on line 3
: EXTI-IMR_MR4 %1 4 lshift EXTI-IMR bis! ; \ EXTI-IMR_MR4 Interrupt Mask on line 4
: EXTI-IMR_MR5 %1 5 lshift EXTI-IMR bis! ; \ EXTI-IMR_MR5 Interrupt Mask on line 5
: EXTI-IMR_MR6 %1 6 lshift EXTI-IMR bis! ; \ EXTI-IMR_MR6 Interrupt Mask on line 6
: EXTI-IMR_MR7 %1 7 lshift EXTI-IMR bis! ; \ EXTI-IMR_MR7 Interrupt Mask on line 7
: EXTI-IMR_MR8 %1 8 lshift EXTI-IMR bis! ; \ EXTI-IMR_MR8 Interrupt Mask on line 8
: EXTI-IMR_MR9 %1 9 lshift EXTI-IMR bis! ; \ EXTI-IMR_MR9 Interrupt Mask on line 9
: EXTI-IMR_MR10 %1 10 lshift EXTI-IMR bis! ; \ EXTI-IMR_MR10 Interrupt Mask on line 10
: EXTI-IMR_MR11 %1 11 lshift EXTI-IMR bis! ; \ EXTI-IMR_MR11 Interrupt Mask on line 11
: EXTI-IMR_MR12 %1 12 lshift EXTI-IMR bis! ; \ EXTI-IMR_MR12 Interrupt Mask on line 12
: EXTI-IMR_MR13 %1 13 lshift EXTI-IMR bis! ; \ EXTI-IMR_MR13 Interrupt Mask on line 13
: EXTI-IMR_MR14 %1 14 lshift EXTI-IMR bis! ; \ EXTI-IMR_MR14 Interrupt Mask on line 14
: EXTI-IMR_MR15 %1 15 lshift EXTI-IMR bis! ; \ EXTI-IMR_MR15 Interrupt Mask on line 15
: EXTI-IMR_MR16 %1 16 lshift EXTI-IMR bis! ; \ EXTI-IMR_MR16 Interrupt Mask on line 16
: EXTI-IMR_MR17 %1 17 lshift EXTI-IMR bis! ; \ EXTI-IMR_MR17 Interrupt Mask on line 17
: EXTI-IMR_MR18 %1 18 lshift EXTI-IMR bis! ; \ EXTI-IMR_MR18 Interrupt Mask on line 18
\ EXTI-EMR (read-write)
: EXTI-EMR_MR0 %1 0 lshift EXTI-EMR bis! ; \ EXTI-EMR_MR0 Event Mask on line 0
: EXTI-EMR_MR1 %1 1 lshift EXTI-EMR bis! ; \ EXTI-EMR_MR1 Event Mask on line 1
: EXTI-EMR_MR2 %1 2 lshift EXTI-EMR bis! ; \ EXTI-EMR_MR2 Event Mask on line 2
: EXTI-EMR_MR3 %1 3 lshift EXTI-EMR bis! ; \ EXTI-EMR_MR3 Event Mask on line 3
: EXTI-EMR_MR4 %1 4 lshift EXTI-EMR bis! ; \ EXTI-EMR_MR4 Event Mask on line 4
: EXTI-EMR_MR5 %1 5 lshift EXTI-EMR bis! ; \ EXTI-EMR_MR5 Event Mask on line 5
: EXTI-EMR_MR6 %1 6 lshift EXTI-EMR bis! ; \ EXTI-EMR_MR6 Event Mask on line 6
: EXTI-EMR_MR7 %1 7 lshift EXTI-EMR bis! ; \ EXTI-EMR_MR7 Event Mask on line 7
: EXTI-EMR_MR8 %1 8 lshift EXTI-EMR bis! ; \ EXTI-EMR_MR8 Event Mask on line 8
: EXTI-EMR_MR9 %1 9 lshift EXTI-EMR bis! ; \ EXTI-EMR_MR9 Event Mask on line 9
: EXTI-EMR_MR10 %1 10 lshift EXTI-EMR bis! ; \ EXTI-EMR_MR10 Event Mask on line 10
: EXTI-EMR_MR11 %1 11 lshift EXTI-EMR bis! ; \ EXTI-EMR_MR11 Event Mask on line 11
: EXTI-EMR_MR12 %1 12 lshift EXTI-EMR bis! ; \ EXTI-EMR_MR12 Event Mask on line 12
: EXTI-EMR_MR13 %1 13 lshift EXTI-EMR bis! ; \ EXTI-EMR_MR13 Event Mask on line 13
: EXTI-EMR_MR14 %1 14 lshift EXTI-EMR bis! ; \ EXTI-EMR_MR14 Event Mask on line 14
: EXTI-EMR_MR15 %1 15 lshift EXTI-EMR bis! ; \ EXTI-EMR_MR15 Event Mask on line 15
: EXTI-EMR_MR16 %1 16 lshift EXTI-EMR bis! ; \ EXTI-EMR_MR16 Event Mask on line 16
: EXTI-EMR_MR17 %1 17 lshift EXTI-EMR bis! ; \ EXTI-EMR_MR17 Event Mask on line 17
: EXTI-EMR_MR18 %1 18 lshift EXTI-EMR bis! ; \ EXTI-EMR_MR18 Event Mask on line 18
\ EXTI-RTSR (read-write)
: EXTI-RTSR_TR0 %1 0 lshift EXTI-RTSR bis! ; \ EXTI-RTSR_TR0 Rising trigger event configuration of line 0
: EXTI-RTSR_TR1 %1 1 lshift EXTI-RTSR bis! ; \ EXTI-RTSR_TR1 Rising trigger event configuration of line 1
: EXTI-RTSR_TR2 %1 2 lshift EXTI-RTSR bis! ; \ EXTI-RTSR_TR2 Rising trigger event configuration of line 2
: EXTI-RTSR_TR3 %1 3 lshift EXTI-RTSR bis! ; \ EXTI-RTSR_TR3 Rising trigger event configuration of line 3
: EXTI-RTSR_TR4 %1 4 lshift EXTI-RTSR bis! ; \ EXTI-RTSR_TR4 Rising trigger event configuration of line 4
: EXTI-RTSR_TR5 %1 5 lshift EXTI-RTSR bis! ; \ EXTI-RTSR_TR5 Rising trigger event configuration of line 5
: EXTI-RTSR_TR6 %1 6 lshift EXTI-RTSR bis! ; \ EXTI-RTSR_TR6 Rising trigger event configuration of line 6
: EXTI-RTSR_TR7 %1 7 lshift EXTI-RTSR bis! ; \ EXTI-RTSR_TR7 Rising trigger event configuration of line 7
: EXTI-RTSR_TR8 %1 8 lshift EXTI-RTSR bis! ; \ EXTI-RTSR_TR8 Rising trigger event configuration of line 8
: EXTI-RTSR_TR9 %1 9 lshift EXTI-RTSR bis! ; \ EXTI-RTSR_TR9 Rising trigger event configuration of line 9
: EXTI-RTSR_TR10 %1 10 lshift EXTI-RTSR bis! ; \ EXTI-RTSR_TR10 Rising trigger event configuration of line 10
: EXTI-RTSR_TR11 %1 11 lshift EXTI-RTSR bis! ; \ EXTI-RTSR_TR11 Rising trigger event configuration of line 11
: EXTI-RTSR_TR12 %1 12 lshift EXTI-RTSR bis! ; \ EXTI-RTSR_TR12 Rising trigger event configuration of line 12
: EXTI-RTSR_TR13 %1 13 lshift EXTI-RTSR bis! ; \ EXTI-RTSR_TR13 Rising trigger event configuration of line 13
: EXTI-RTSR_TR14 %1 14 lshift EXTI-RTSR bis! ; \ EXTI-RTSR_TR14 Rising trigger event configuration of line 14
: EXTI-RTSR_TR15 %1 15 lshift EXTI-RTSR bis! ; \ EXTI-RTSR_TR15 Rising trigger event configuration of line 15
: EXTI-RTSR_TR16 %1 16 lshift EXTI-RTSR bis! ; \ EXTI-RTSR_TR16 Rising trigger event configuration of line 16
: EXTI-RTSR_TR17 %1 17 lshift EXTI-RTSR bis! ; \ EXTI-RTSR_TR17 Rising trigger event configuration of line 17
: EXTI-RTSR_TR18 %1 18 lshift EXTI-RTSR bis! ; \ EXTI-RTSR_TR18 Rising trigger event configuration of line 18
\ EXTI-FTSR (read-write)
: EXTI-FTSR_TR0 %1 0 lshift EXTI-FTSR bis! ; \ EXTI-FTSR_TR0 Falling trigger event configuration of line 0
: EXTI-FTSR_TR1 %1 1 lshift EXTI-FTSR bis! ; \ EXTI-FTSR_TR1 Falling trigger event configuration of line 1
: EXTI-FTSR_TR2 %1 2 lshift EXTI-FTSR bis! ; \ EXTI-FTSR_TR2 Falling trigger event configuration of line 2
: EXTI-FTSR_TR3 %1 3 lshift EXTI-FTSR bis! ; \ EXTI-FTSR_TR3 Falling trigger event configuration of line 3
: EXTI-FTSR_TR4 %1 4 lshift EXTI-FTSR bis! ; \ EXTI-FTSR_TR4 Falling trigger event configuration of line 4
: EXTI-FTSR_TR5 %1 5 lshift EXTI-FTSR bis! ; \ EXTI-FTSR_TR5 Falling trigger event configuration of line 5
: EXTI-FTSR_TR6 %1 6 lshift EXTI-FTSR bis! ; \ EXTI-FTSR_TR6 Falling trigger event configuration of line 6
: EXTI-FTSR_TR7 %1 7 lshift EXTI-FTSR bis! ; \ EXTI-FTSR_TR7 Falling trigger event configuration of line 7
: EXTI-FTSR_TR8 %1 8 lshift EXTI-FTSR bis! ; \ EXTI-FTSR_TR8 Falling trigger event configuration of line 8
: EXTI-FTSR_TR9 %1 9 lshift EXTI-FTSR bis! ; \ EXTI-FTSR_TR9 Falling trigger event configuration of line 9
: EXTI-FTSR_TR10 %1 10 lshift EXTI-FTSR bis! ; \ EXTI-FTSR_TR10 Falling trigger event configuration of line 10
: EXTI-FTSR_TR11 %1 11 lshift EXTI-FTSR bis! ; \ EXTI-FTSR_TR11 Falling trigger event configuration of line 11
: EXTI-FTSR_TR12 %1 12 lshift EXTI-FTSR bis! ; \ EXTI-FTSR_TR12 Falling trigger event configuration of line 12
: EXTI-FTSR_TR13 %1 13 lshift EXTI-FTSR bis! ; \ EXTI-FTSR_TR13 Falling trigger event configuration of line 13
: EXTI-FTSR_TR14 %1 14 lshift EXTI-FTSR bis! ; \ EXTI-FTSR_TR14 Falling trigger event configuration of line 14
: EXTI-FTSR_TR15 %1 15 lshift EXTI-FTSR bis! ; \ EXTI-FTSR_TR15 Falling trigger event configuration of line 15
: EXTI-FTSR_TR16 %1 16 lshift EXTI-FTSR bis! ; \ EXTI-FTSR_TR16 Falling trigger event configuration of line 16
: EXTI-FTSR_TR17 %1 17 lshift EXTI-FTSR bis! ; \ EXTI-FTSR_TR17 Falling trigger event configuration of line 17
: EXTI-FTSR_TR18 %1 18 lshift EXTI-FTSR bis! ; \ EXTI-FTSR_TR18 Falling trigger event configuration of line 18
\ EXTI-SWIER (read-write)
: EXTI-SWIER_SWIER0 %1 0 lshift EXTI-SWIER bis! ; \ EXTI-SWIER_SWIER0 Software Interrupt on line 0
: EXTI-SWIER_SWIER1 %1 1 lshift EXTI-SWIER bis! ; \ EXTI-SWIER_SWIER1 Software Interrupt on line 1
: EXTI-SWIER_SWIER2 %1 2 lshift EXTI-SWIER bis! ; \ EXTI-SWIER_SWIER2 Software Interrupt on line 2
: EXTI-SWIER_SWIER3 %1 3 lshift EXTI-SWIER bis! ; \ EXTI-SWIER_SWIER3 Software Interrupt on line 3
: EXTI-SWIER_SWIER4 %1 4 lshift EXTI-SWIER bis! ; \ EXTI-SWIER_SWIER4 Software Interrupt on line 4
: EXTI-SWIER_SWIER5 %1 5 lshift EXTI-SWIER bis! ; \ EXTI-SWIER_SWIER5 Software Interrupt on line 5
: EXTI-SWIER_SWIER6 %1 6 lshift EXTI-SWIER bis! ; \ EXTI-SWIER_SWIER6 Software Interrupt on line 6
: EXTI-SWIER_SWIER7 %1 7 lshift EXTI-SWIER bis! ; \ EXTI-SWIER_SWIER7 Software Interrupt on line 7
: EXTI-SWIER_SWIER8 %1 8 lshift EXTI-SWIER bis! ; \ EXTI-SWIER_SWIER8 Software Interrupt on line 8
: EXTI-SWIER_SWIER9 %1 9 lshift EXTI-SWIER bis! ; \ EXTI-SWIER_SWIER9 Software Interrupt on line 9
: EXTI-SWIER_SWIER10 %1 10 lshift EXTI-SWIER bis! ; \ EXTI-SWIER_SWIER10 Software Interrupt on line 10