Timeline for BrevitasQuantizer Ryzen AI integration (sub-INT8 / 1-bit support)?

[bong-water-water-bong]

The Quantization for Ryzen AI usage guide documents two quantizer paths:

1. RyzenAIOnnxQuantizer — Vitis AI based, fully documented, INT8 PTQ for timm CNN models.
2. BrevitasQuantizer — wraps Xilinx Brevitas, recommended for "other" model types beyond timm CNNs. The doc currently says "Coming soon." (source)

I'm building a 1-bit / ternary inference engine for AMD Strix Halo. The GPU lane (ROCm/Vulkan llama.cpp) runs 1-bit (IQ1_S, TQ2_0) cleanly today. The NPU lane is currently UINT4-AWQ via FastFlowLM — no public ternary path exists for XDNA 2.

Brevitas is the natural home for sub-INT8 BitNet-style quantization targeting Ryzen AI, since it already supports N-bit (down to binary) in upstream. The integration through BrevitasQuantizer is the missing link.

Asks

1. Is there a target window for promoting the BrevitasQuantizer from "Coming soon" to documented + tested? Even a rough quarter would help downstream projects plan.
2. Are sub-INT8 / 1-bit weights on the agenda for the Ryzen AI Brevitas integration, or will the initial release focus on INT8 parity with the Vitis AI path?
3. Is there a working code branch / draft PR / staging example we could follow or pre-test against? Happy to file bugs against pre-release code.

The "ResNet only" perception of AMD's official Linux NPU support is real for now, and the Brevitas path is the visible bridge to richer quantization. Any clarity on its trajectory would be appreciated.

[bong-water-water-bong]

Quick follow-up for completeness — the full RyzenAI/* HF org as of 2026-04-28 is just three models:

Model	Date	Notes
RyzenAI/Qwen2.5-VL-3B-Instruct-per-grp-quant	2026-02-02	uint4 per-group, Quark recipe (PyTorch)
RyzenAI/Qwen3-VL-4B-Instruct-per-grp-quant	2026-02-27	uint4 per-group, Quark recipe (PyTorch)
RyzenAI/granite-4.0-1b-converted	2026-03-30	gated, "-converted" suffix

A couple of related questions that surfaced from this:

• The bundled run_*_quantization.py scripts in the per-grp-quant repos default to cuda or cpu and use quark.torch — is there a parallel public path for compiling these Quark-quantized artifacts down to AIE2P / VitisAI EP? Or are the per-grp-quant repos PyTorch-side reproducers only, and *-converted (gated) is the NPU-deployment artifact?
• How does AMD Quark relate to the BrevitasQuantizer "coming soon" line in the docs? Quark looks like the actively-shipping quantizer for LLM/VLM weights; Brevitas is positioned as the upcoming sub-INT8 / N-bit research path. Is that the intended division of labor, or is one absorbing the other?

Apologies if this is documented somewhere I missed.