This page records synthesis and routing for the production RTL boundary. The study uses an open-source ECP5 flow and automatically allocated I/O pins. It is an implementation study without a physical board.
Current measurements come from results/implementation.csv. implementation_table.md is generated from the same manifests.
rtl/trader_impl_top.sv contains the full byte-level trader and the nonpausable market ingress adapter. Both input channels, order output, recovery requests, kill input, boot epoch, and status byte remain dynamic.
The wide verification buses stay internal and unconnected. Yosys prunes their fanout before reporting resources. The routed design therefore measures the production interface instead of hundreds of debug pins.
The frozen matrix covers both parsers at FIFO depths 64 and 256:
p0-f64: buffered receiver, 64-entry ingress FIFOp0-f256: buffered receiver, 256-entry ingress FIFOp1-f64: streaming receiver, 64-entry ingress FIFOp1-f256: streaming receiver, 256-entry ingress FIFO
The target device is an ECP5 85k in package CABGA381, speed grade 6.
The current configurations use 6,014 to 9,024 LUT4 equivalents and 2,813 to 2,844 flip-flops. Each design uses four multipliers. The 256-entry variants infer one block RAM.
The streaming receiver is smaller in this matrix. At depth 64 it uses 6,354 LUT4 equivalents, compared with 8,863 for the buffered receiver. The streaming architecture replaces a 64-byte frame store and its variable indexing with a four-byte CRC delay and a two-entry event queue.
An early 50 MHz route reached 36.79 MHz and used 9,098 LUT4 equivalents. The critical path started at the candidate quantity register, crossed the 32-by-32-bit notional product, and continued through a 64-bit comparison chain.
The notional and position limits are small constants. Their comparisons were split at the highest used bit. A high bit decides the result immediately; otherwise the low bits are compared. The 32-by-32-bit product remained full width.
The same seed reached 42.25 MHz after the revision and used 8,816 LUT4 equivalents. tb_risk.constant_comparisons_hold_at_every_boundary checks powers of two around each split point, the limit values, and 10,000 seeded tuples. Mutation M11 checks accidental product narrowing.
The route still missed 50 MHz, so the comparison uses a common 25 MHz target. The historical pair is stored in results/implementation_history.json.
All four configurations were routed with seeds 1 through 5 at 25 MHz. All twenty attempts meet timing. Their reported maximum clock rates span 38.13 to 46.70 MHz.
The limiting path remains in the risk decision. The streaming CRC network does not become the critical path in these routes.
tools/measure_parser.py publishes one saved frame sequence to both parsers and measures accepted bytes.
| Receiver | Accepted bytes/clock | Inter-frame bubble, min / median / max |
|---|---|---|
| Buffered | 0.515 | 19 / 31 / 46 clocks |
| Streaming | 0.995 | 0 / 0 / 8 clocks |
The buffered receiver pauses while it checks CRC and fields. The streaming receiver validates at EOP and can begin the next frame immediately.
On the C35_overflow burst at depth 64, the buffered design reaches occupancy 64 and loses 464 beats across five overflow events. The streaming design reaches occupancy 1 and loses zero beats. The overflow case is marked inapplicable for PARSER=1, with the reason recorded.
The I/O pinout is automatic. No physical board, external setup and hold timing, or power measurement is included. The reported clock rates describe this device, toolchain, source, constraints, and route seeds.
make synth PARSER=0 INGRESS_DEPTH=64
make pnr PARSER=0 INGRESS_DEPTH=64 ROUTE_SEED=1 TARGET_MHZ=25
make synth PARSER=1 INGRESS_DEPTH=64
make pnr PARSER=1 INGRESS_DEPTH=64 ROUTE_SEED=1 TARGET_MHZ=25
make parse-reports
make measure-parser