Examples of FPGA slice specifications

[gussmith23]

I need examples of FPGA slice configurations!

[gussmith23]

From Luis: FPGA families share the same slice types, but contain different numbers of slices (different numbers of rows/columns). (At least for Xilinx!)

[gussmith23]

Given that I was looking up with the spec sheet for the Zynq on my Pynq board, I'll start with that:
https://www.xilinx.com/support/documentation/data_sheets/ds190-Zynq-7000-Overview.pdf

[gussmith23]

One question -- I'm talking about slices as if they're the smallest indivisible unit, but it might actually be CLBs (configurable logic blocks) which are the unit we should be referring to (at least in Xilinx).

[gussmith23]

Some key features of the CLB architecture include:
• True 6-input LUTs
• Memory capability within the LUT
• Register and shift register functionality
LUTs can be configured as either one 6-input LUT (64-bit ROMs) with one output, or as two 5-input LUTs (32-bit ROMs) with separate outputs but common addresses or logic inputs. Each LUT output can optionally be registered in a flip-flop. Four
such LUTs and their eight flip-flops as well as multiplexers and arithmetic carry logic form a slice, and two slices form a
configurable logic block (CLB). Four of the eight flip-flops per slice (one flip-flop per LUT) can optionally be configured as
latches.
Between 25–50% of all slices can also use their LUTs as distributed 64-bit RAM or as 32-bit shift registers (SRL32) or as two
SRL16s. Modern synthesis tools take advantage of these highly efficient logic, arithmetic, and memory features.

[gussmith23]

This isn't a very exact description.

[gussmith23]

https://www.xilinx.com/support/documentation/user_guides/ug474_7Series_CLB.pdf

[bkushigian]

One thing I'm noticing is that Yosys isn't outputting PFU (Lattice's variant of a CLB) info. Instead, it's outputting configurations for individual LUTs and MUXs. Does PnR take care of assigning LUTs to CLB/PFU type structures?

[gussmith23]

What actually is carry chain logic?