LogicArray

[eulere28]

Problem with logic array in DataMem File and RegisterFile.

Error: type 'Port' is not a subtype of type 'int'

DataMem: https://github.com/eulere28/single-cycle-cpu/blob/main/lib/DataMem.dart

Register: https://github.com/eulere28/single-cycle-cpu/blob/main/lib/RegisterFile.dart

[quekyj]

register.elements[w1] < wd1, this line is causing the issue. Your w1 should be of type int and not type Logic. You can think of this as array position. I am thinking that you probably want to make the module to accept int instead of logic for w1?