This would be a cool feature to have
//C style
bit_vector<68>("0xABCDEF01234567890");
bit_vector<8>("0b10110100");
//verilog style
bit_vector<68>("68'hABCDEF01234567890");
bit_vector<8>("8'b1011_0100");
//Note verilog allows '_' as a separator in literals that is ignored.
I dont have strong opinions on which style. Although the ability to have a separator for readability purposes is really nice
This would be a cool feature to have
I dont have strong opinions on which style. Although the ability to have a separator for readability purposes is really nice