From 599569375827789e97724a1c2310188fa5e82560 Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sat, 11 Jul 2026 15:07:54 -0400 Subject: [PATCH 01/55] Update generate_runt_configs.py to add Runt test suite for bi --- scripts/generate_runt_configs.py | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/scripts/generate_runt_configs.py b/scripts/generate_runt_configs.py index 480f9438..a319619a 100644 --- a/scripts/generate_runt_configs.py +++ b/scripts/generate_runt_configs.py @@ -91,7 +91,7 @@ def expect_name(case: dict, runner: str) -> str: def expect_dir(case: dict, runner: str) -> str: wave = case.get("wave") - base = Path(wave if runner == "monitor" and wave else case["path"]).parent + base = Path(wave if runner in ("monitor", "bi") and wave else case["path"]).parent return f"../../{base.as_posix()}/expects" @@ -194,6 +194,18 @@ def monitor_runt_command(case: dict) -> list[tuple[str, str]]: cmd = timeout_cmd(case["timeout_secs"], cmd) return [("", repo_root_command(cmd))] +# Same as `monitor_runt_command` above but for BI test cases +def bi_runt_command(case: dict) -> list[tuple[str, str]]: + cmd = [*binary_prefix("bi"), "--protocol", case["path"]] + if case["wave"]: + cmd += ["--wave", case["wave"]] + if case["instances"]: + cmd += ["--instances", *case["instances"]] + cmd += case["extra_args"] + if case["timeout_secs"] is not None: + cmd = timeout_cmd(case["timeout_secs"], cmd) + return [("", repo_root_command(cmd))] + def waveform_runt_command(case: dict) -> list[tuple[str, str]]: ast_cmd = [ @@ -261,6 +273,7 @@ def fail_runt_command(case: dict) -> list[tuple[str, str]]: "interp": interp_runt_command, "graph_interp": graph_interp_runt_command, "monitor": monitor_runt_command, + "bi": bi_runt_command, "waveform": waveform_runt_command, "fail": fail_runt_command, } @@ -388,6 +401,9 @@ def generate_runt_configs() -> None: suite_specs = { "interp": ("interp", tx), "monitor": ("monitor", mon), + # Note: bi uses the same cases as the monitor (i.e. MONITOR_CASES) + # as the monitor/bi share largely the same CLI args + "bi": ("bi", mon), "graph_interp": ("graph_interp", graph_interp_cases(tx)), "waveform": ("waveform", waveform_cases(tx)), "fail": ("fail", fail_cases(tx)), From 42c80d5146dae3341fedaae41a3d586567069b51 Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sat, 11 Jul 2026 15:08:03 -0400 Subject: [PATCH 02/55] Update Justfile to run bi tests --- justfile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/justfile b/justfile index db492b4a..b0742574 100644 --- a/justfile +++ b/justfile @@ -1,8 +1,9 @@ # Runs the Runt snapshot suites that together cover every test runt: - cargo build --offline --package protocols-interp --package protocols-monitor --package graph-interp + cargo build --offline --package protocols-interp --package protocols-monitor --package graph-interp --package bi runt --max-futures 1 runt/interp runt --max-futures 1 runt/monitor + runt --max-futures 1 runt/bi runt --max-futures 1 runt/graph_interp runt --max-futures 1 runt/waveform runt --max-futures 1 runt/fail From 15cb68a7b68a37454f5b92c57b065b8e190b8c9f Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sat, 11 Jul 2026 15:08:16 -0400 Subject: [PATCH 03/55] Add auto-generated Runt BI config --- runt/bi/runt.toml | 1549 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 1549 insertions(+) create mode 100644 runt/bi/runt.toml diff --git a/runt/bi/runt.toml b/runt/bi/runt.toml new file mode 100644 index 00000000..9e18a046 --- /dev/null +++ b/runt/bi/runt.toml @@ -0,0 +1,1549 @@ +ver = "0.4.1" + +[[tests]] +name = "bi.tests_adders_add_d1.add_d1_bi" +paths = [ + "../../tests/adders/add_d1.prot", +] +expect_dir = "../../tests/adders/expects" +expect_name = "add_d1.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/adders/add_d1.prot --wave tests/adders/add_d1.fst --instances add_d1:Adder 2>/dev/null" + +[[tests]] +name = "bi.tests_adders_add_d2.add_d2_bi" +paths = [ + "../../tests/adders/add_d2.prot", +] +expect_dir = "../../tests/adders/expects" +expect_name = "add_d2.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/adders/add_d2.prot --wave tests/adders/add_d2.fst --instances add_d2:Adder 2>/dev/null" + +[[tests]] +name = "bi.tests_adders_add_var_cyc.add_var_cyc_bi" +paths = [ + "../../tests/adders/add_var_cyc.prot", +] +expect_dir = "../../tests/adders/expects" +expect_name = "add_var_cyc.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/adders/add_var_cyc.prot --wave tests/adders/loop_with_assigns.fst --instances add_d1:Adder 2>/dev/null" + +[[tests]] +name = "bi.tests_adders_busy_wait.busy_wait_bi" +paths = [ + "../../tests/adders/busy_wait.prot", +] +expect_dir = "../../tests/adders/expects" +expect_name = "busy_wait.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/adders/busy_wait.prot --wave tests/adders/busy_wait.fst --instances add_d1:Adder 2>/dev/null" + +[[tests]] +name = "bi.tests_adders_loop_with_assigns.loop_with_assigns_bi" +paths = [ + "../../tests/adders/loop_with_assigns.prot", +] +expect_dir = "../../tests/adders/expects" +expect_name = "loop_with_assigns.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/adders/loop_with_assigns.prot --wave tests/adders/loop_with_assigns.fst --instances add_d1:Adder 2>/dev/null" + +[[tests]] +name = "bi.tests_adders_nested_busy_wait.nested_busy_wait_bi" +paths = [ + "../../tests/adders/nested_busy_wait.prot", +] +expect_dir = "../../tests/adders/expects" +expect_name = "nested_busy_wait.bi.expect" +cmd = "cd ../.. && python3 -c 'import os, signal, subprocess, sys\np = subprocess.Popen(sys.argv[2:], start_new_session=True)\ntry:\n sys.exit(p.wait(timeout=float(sys.argv[1])))\nexcept subprocess.TimeoutExpired:\n os.killpg(p.pid, signal.SIGKILL)\n sys.exit(124)\n' 5 target/debug/bi --protocol tests/adders/nested_busy_wait.prot --wave tests/adders/nested_busy_wait.fst --instances add_d1:Adder 2>/dev/null" + +[[tests]] +name = "bi.tests_alus_alu_d1_monitor.alu_d1_bi" +paths = [ + "../../tests/alus/alu_d1.monitor.prot", +] +expect_dir = "../../tests/alus/expects" +expect_name = "alu_d1.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/alus/alu_d1.monitor.prot --wave tests/alus/alu_d1.fst --instances alu_d1:ALU 2>/dev/null" + +[[tests]] +name = "bi.tests_alus_alu_d2_monitor.alu_d2_bi" +paths = [ + "../../tests/alus/alu_d2.monitor.prot", +] +expect_dir = "../../tests/alus/expects" +expect_name = "alu_d2.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/alus/alu_d2.monitor.prot --wave tests/alus/alu_d2.fst --instances alu_d2:ALU 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_classic_1_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/fifo_classic/expects" +expect_name = "test_fifo_classic_1.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_classic_2_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/fifo_classic/expects" +expect_name = "test_fifo_classic_2.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_classic_3_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/fifo_classic/expects" +expect_name = "test_fifo_classic_3.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_classic_4_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/fifo_classic/expects" +expect_name = "test_fifo_classic_4.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_classic_5_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/fifo_classic/expects" +expect_name = "test_fifo_classic_5.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_5.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_classic_6_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/fifo_classic/expects" +expect_name = "test_fifo_classic_6.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_6.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_classic_7_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/fifo_classic/expects" +expect_name = "test_fifo_classic_7.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_7.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_classic_8_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/fifo_classic/expects" +expect_name = "test_fifo_classic_8.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_constant_1_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/fifo_constant/expects" +expect_name = "test_fifo_constant_1.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_constant_2_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/fifo_constant/expects" +expect_name = "test_fifo_constant_2.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_constant_3_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/fifo_constant/expects" +expect_name = "test_fifo_constant_3.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_constant_4_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/fifo_constant/expects" +expect_name = "test_fifo_constant_4.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_constant_5_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/fifo_constant/expects" +expect_name = "test_fifo_constant_5.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_5.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_constant_6_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/fifo_constant/expects" +expect_name = "test_fifo_constant_6.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_6.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_constant_7_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/fifo_constant/expects" +expect_name = "test_fifo_constant_7.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_7.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_constant_8_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/fifo_constant/expects" +expect_name = "test_fifo_constant_8.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_16_0_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_classic/expects" +expect_name = "test_sram_classic_16_0.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_16_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_16_12_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_classic/expects" +expect_name = "test_sram_classic_16_12.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_16_12.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_16_4_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_classic/expects" +expect_name = "test_sram_classic_16_4.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_16_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_16_8_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_classic/expects" +expect_name = "test_sram_classic_16_8.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_16_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_1_0_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_classic/expects" +expect_name = "test_sram_classic_1_0.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_1_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_1_12_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_classic/expects" +expect_name = "test_sram_classic_1_12.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_1_12.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_1_4_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_classic/expects" +expect_name = "test_sram_classic_1_4.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_1_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_1_8_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_classic/expects" +expect_name = "test_sram_classic_1_8.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_1_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_2_0_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_classic/expects" +expect_name = "test_sram_classic_2_0.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_2_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_2_12_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_classic/expects" +expect_name = "test_sram_classic_2_12.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_2_12.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_2_4_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_classic/expects" +expect_name = "test_sram_classic_2_4.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_2_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_2_8_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_classic/expects" +expect_name = "test_sram_classic_2_8.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_2_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_4_0_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_classic/expects" +expect_name = "test_sram_classic_4_0.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_4_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_4_12_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_classic/expects" +expect_name = "test_sram_classic_4_12.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_4_12.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_4_4_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_classic/expects" +expect_name = "test_sram_classic_4_4.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_4_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_4_8_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_classic/expects" +expect_name = "test_sram_classic_4_8.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_4_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_8_0_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_classic/expects" +expect_name = "test_sram_classic_8_0.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_8_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_8_12_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_classic/expects" +expect_name = "test_sram_classic_8_12.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_8_12.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_8_4_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_classic/expects" +expect_name = "test_sram_classic_8_4.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_8_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_8_8_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_classic/expects" +expect_name = "test_sram_classic_8_8.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_8_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_0_0_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_16_0_0.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_0_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_0_1_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_16_0_1.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_0_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_0_2_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_16_0_2.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_0_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_0_3_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_16_0_3.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_0_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_12_0_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_16_12_0.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_12_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_12_1_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_16_12_1.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_12_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_12_2_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_16_12_2.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_12_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_12_3_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_16_12_3.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_12_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_4_0_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_16_4_0.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_4_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_4_1_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_16_4_1.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_4_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_4_2_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_16_4_2.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_4_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_4_3_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_16_4_3.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_4_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_8_0_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_16_8_0.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_8_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_8_1_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_16_8_1.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_8_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_8_2_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_16_8_2.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_8_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_8_3_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_16_8_3.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_8_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_0_0_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_1_0_0.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_0_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_0_1_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_1_0_1.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_0_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_0_2_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_1_0_2.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_0_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_0_3_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_1_0_3.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_0_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_12_0_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_1_12_0.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_12_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_12_1_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_1_12_1.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_12_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_12_2_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_1_12_2.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_12_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_12_3_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_1_12_3.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_12_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_4_0_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_1_4_0.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_4_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_4_1_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_1_4_1.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_4_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_4_2_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_1_4_2.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_4_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_4_3_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_1_4_3.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_4_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_8_0_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_1_8_0.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_8_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_8_1_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_1_8_1.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_8_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_8_2_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_1_8_2.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_8_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_8_3_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_1_8_3.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_8_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_0_0_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_2_0_0.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_0_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_0_1_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_2_0_1.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_0_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_0_2_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_2_0_2.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_0_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_0_3_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_2_0_3.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_0_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_12_0_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_2_12_0.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_12_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_12_1_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_2_12_1.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_12_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_12_2_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_2_12_2.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_12_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_12_3_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_2_12_3.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_12_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_4_0_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_2_4_0.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_4_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_4_1_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_2_4_1.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_4_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_4_2_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_2_4_2.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_4_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_4_3_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_2_4_3.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_4_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_8_0_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_2_8_0.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_8_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_8_1_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_2_8_1.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_8_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_8_2_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_2_8_2.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_8_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_8_3_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_2_8_3.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_8_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_0_0_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_4_0_0.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_0_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_0_1_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_4_0_1.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_0_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_0_2_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_4_0_2.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_0_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_0_3_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_4_0_3.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_0_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_12_0_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_4_12_0.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_12_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_12_1_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_4_12_1.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_12_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_12_2_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_4_12_2.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_12_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_12_3_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_4_12_3.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_12_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_4_0_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_4_4_0.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_4_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_4_1_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_4_4_1.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_4_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_4_2_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_4_4_2.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_4_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_4_3_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_4_4_3.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_4_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_8_0_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_4_8_0.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_8_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_8_1_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_4_8_1.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_8_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_8_2_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_4_8_2.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_8_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_8_3_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_4_8_3.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_8_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_0_0_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_8_0_0.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_0_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_0_1_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_8_0_1.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_0_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_0_2_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_8_0_2.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_0_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_0_3_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_8_0_3.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_0_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_12_0_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_8_12_0.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_12_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_12_1_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_8_12_1.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_12_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_12_2_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_8_12_2.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_12_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_12_3_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_8_12_3.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_12_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_4_0_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_8_4_0.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_4_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_4_1_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_8_4_1.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_4_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_4_2_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_8_4_2.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_4_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_4_3_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_8_4_3.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_4_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_8_0_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_8_8_0.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_8_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_8_1_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_8_8_1.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_8_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_8_2_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_8_8_2.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_8_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_8_3_bi" +paths = [ + "../../tests/antmicro/wishbone_subordinate.prot", +] +expect_dir = "../../tests/antmicro/sram_incrementing/expects" +expect_name = "test_sram_incrementing_8_8_3.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_8_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_brave_new_world_francis_bit_truncation_fft.bit_truncation_fft_bi" +paths = [ + "../../tests/brave_new_world_francis/bit_truncation_fft.prot", +] +expect_dir = "../../tests/brave_new_world_francis/expects" +expect_name = "bit_truncation_fft.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/brave_new_world_francis/bit_truncation_fft.prot --wave tests/brave_new_world_francis/bit_truncation_fft.fst --instances round11_rne_unsigned_fixed:BitTruncationFFT 2>/dev/null" + +[[tests]] +name = "bi.tests_brave_new_world_francis_bit_truncation_sha.bit_truncation_sha_bi" +paths = [ + "../../tests/brave_new_world_francis/bit_truncation_sha.prot", +] +expect_dir = "../../tests/brave_new_world_francis/expects" +expect_name = "bit_truncation_sha.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/brave_new_world_francis/bit_truncation_sha.prot --wave tests/brave_new_world_francis/bit_truncation_sha.fst --instances bit_truncation_sha_fixed:bit_truncation_sha 2>/dev/null" + +[[tests]] +name = "bi.tests_brave_new_world_francis_ftu_sha.ftu_sha_bi" +paths = [ + "../../tests/brave_new_world_francis/ftu_sha.prot", +] +expect_dir = "../../tests/brave_new_world_francis/expects" +expect_name = "ftu_sha.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/brave_new_world_francis/ftu_sha.prot --wave tests/brave_new_world_francis/ftu_sha.fst --instances fsm_update_fixed_gated:FailureToUpdateSHA 2>/dev/null" + +[[tests]] +name = "bi.tests_brave_new_world_francis_signal_async.signal_async_bi" +paths = [ + "../../tests/brave_new_world_francis/signal_async.prot", +] +expect_dir = "../../tests/brave_new_world_francis/expects" +expect_name = "signal_async.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/brave_new_world_francis/signal_async.prot --wave tests/brave_new_world_francis/signal_async.fst --instances signal_async_fix:SignalAsyncSpec 2>/dev/null" + +[[tests]] +name = "bi.tests_brave_new_world_francis_use_without_valid.use_without_valid_bi" +paths = [ + "../../tests/brave_new_world_francis/use_without_valid.prot", +] +expect_dir = "../../tests/brave_new_world_francis/expects" +expect_name = "use_without_valid.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/brave_new_world_francis/use_without_valid.prot --wave tests/brave_new_world_francis/use_without_valid.fst --instances use_without_valid_fix:UseWithoutValid 2>/dev/null" + +[[tests]] +name = "bi.tests_ethmac_ethmac_wishbone_manager.ethmac_wishbone_manager_bi" +paths = [ + "../../tests/ethmac/ethmac_wishbone_manager.prot", +] +expect_dir = "../../tests/ethmac/expects" +expect_name = "ethmac_wishbone_manager.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/ethmac/ethmac_wishbone_manager.prot --instances tb_ethernet:WBManager --sample-posedge tb_ethernet.wb_clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_ethmac_ethmac_wishbone_subordinate.ethmac_wishbone_subordinate_bi" +paths = [ + "../../tests/ethmac/ethmac_wishbone_subordinate.prot", +] +expect_dir = "../../tests/ethmac/expects" +expect_name = "ethmac_wishbone_subordinate.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/ethmac/ethmac_wishbone_subordinate.prot --instances tb_ethernet:WBSubordinate --sample-posedge tb_ethernet.wb_clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_fifo_fifo_monitor.fifo_bi" +paths = [ + "../../tests/fifo/fifo.monitor.prot", +] +expect_dir = "../../tests/fifo/expects" +expect_name = "fifo.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/fifo/fifo.monitor.prot --wave tests/fifo/fifo.fst --instances fifo_wrapper:Fifo 2>/dev/null" + +[[tests]] +name = "bi.tests_fifo_push_pop_identity.push_pop_identity_bi" +paths = [ + "../../tests/fifo/push_pop_identity.prot", +] +expect_dir = "../../tests/fifo/expects" +expect_name = "push_pop_identity.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/fifo/push_pop_identity.prot --wave tests/fifo/push_pop_identity.fst --instances fifo_wrapper:Fifo 2>/dev/null" + +[[tests]] +name = "bi.tests_fifo_push_pop_loop_empty.push_pop_loop_empty_bi" +paths = [ + "../../tests/fifo/push_pop_loop_empty.prot", +] +expect_dir = "../../tests/fifo/expects" +expect_name = "push_pop_loop_empty.bi.expect" +cmd = "cd ../.. && python3 -c 'import os, signal, subprocess, sys\np = subprocess.Popen(sys.argv[2:], start_new_session=True)\ntry:\n sys.exit(p.wait(timeout=float(sys.argv[1])))\nexcept subprocess.TimeoutExpired:\n os.killpg(p.pid, signal.SIGKILL)\n sys.exit(124)\n' 5 target/debug/bi --protocol tests/fifo/push_pop_loop_empty.prot --wave tests/fifo/push_pop_loop_empty.fst --instances fifo_wrapper:Fifo 2>/dev/null" + +[[tests]] +name = "bi.tests_fifo_push_pop_loop_not_empty.push_pop_loop_not_empty_bi" +paths = [ + "../../tests/fifo/push_pop_loop_not_empty.prot", +] +expect_dir = "../../tests/fifo/expects" +expect_name = "push_pop_loop_not_empty.bi.expect" +cmd = "cd ../.. && python3 -c 'import os, signal, subprocess, sys\np = subprocess.Popen(sys.argv[2:], start_new_session=True)\ntry:\n sys.exit(p.wait(timeout=float(sys.argv[1])))\nexcept subprocess.TimeoutExpired:\n os.killpg(p.pid, signal.SIGKILL)\n sys.exit(124)\n' 5 target/debug/bi --protocol tests/fifo/push_pop_loop_not_empty.prot --wave tests/fifo/push_pop_loop_not_empty.fst --instances fifo_wrapper:Fifo 2>/dev/null" + +[[tests]] +name = "bi.tests_fpga_debugging_axi_burst_s4_s4_buggy.s4_buggy_bi" +paths = [ + "../../tests/fpga-debugging/axi-burst-s4/s4_buggy.prot", +] +expect_dir = "../../tests/fpga-debugging/axi-burst-s4/expects" +expect_name = "s4_buggy.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axi-burst-s4/s4_buggy.prot --wave tests/fpga-debugging/axi-burst-s4/s4_buggy.vcd --instances TOP.test_l2_cache_wait_state.axi_bus:WriteSubordinate --sample-posedge TOP.test_l2_cache_wait_state.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_fpga_debugging_axi_burst_s4_s4_fixed.s4_fixed_bi" +paths = [ + "../../tests/fpga-debugging/axi-burst-s4/s4_fixed.prot", +] +expect_dir = "../../tests/fpga-debugging/axi-burst-s4/expects" +expect_name = "s4_fixed.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axi-burst-s4/s4_fixed.prot --wave tests/fpga-debugging/axi-burst-s4/s4_fixed.vcd --instances TOP.test_l2_cache_wait_state.axi_bus:WriteSubordinate --sample-posedge TOP.test_l2_cache_wait_state.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_fpga_debugging_axi_lite_s1_s1_buggy.s1_buggy_bi" +paths = [ + "../../tests/fpga-debugging/axi-lite-s1/s1_buggy.prot", +] +expect_dir = "../../tests/fpga-debugging/axi-lite-s1/expects" +expect_name = "s1_buggy.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axi-lite-s1/s1_buggy.prot --wave tests/fpga-debugging/axi-lite-s1/s1_buggy_workload2.vcd --instances TOP.testbench.UUT:WriteSubordinate TOP.testbench.UUT:ReadSubordinate --sample-posedge TOP.testbench.UUT.S_AXI_ACLK --show-waveform-time --time-unit ns --include-idle 2>/dev/null" + +[[tests]] +name = "bi.tests_fpga_debugging_axi_lite_s1_s1_buggy_workload_1.s1_buggy_workload_1_bi" +paths = [ + "../../tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot", +] +expect_dir = "../../tests/fpga-debugging/axi-lite-s1/expects" +expect_name = "s1_buggy_workload_1.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot --wave tests/fpga-debugging/axi-lite-s1/s1_buggy_workload1.vcd --instances TOP.testbench.UUT:WriteSubordinate TOP.testbench.UUT:ReadSubordinate --sample-posedge TOP.testbench.UUT.S_AXI_ACLK --show-waveform-time --time-unit ns --include-idle 2>/dev/null" + +[[tests]] +name = "bi.tests_fpga_debugging_axi_lite_s1_s1_fixed.s1_fixed_bi" +paths = [ + "../../tests/fpga-debugging/axi-lite-s1/s1_fixed.prot", +] +expect_dir = "../../tests/fpga-debugging/axi-lite-s1/expects" +expect_name = "s1_fixed.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axi-lite-s1/s1_fixed.prot --wave tests/fpga-debugging/axi-lite-s1/s1_fixed_workload2.vcd --instances TOP.testbench.UUT:WriteSubordinate TOP.testbench.UUT:ReadSubordinate --sample-posedge TOP.testbench.UUT.S_AXI_ACLK --show-waveform-time --time-unit ns --include-idle 2>/dev/null" + +[[tests]] +name = "bi.tests_fpga_debugging_axi_lite_s1_s1_fixed_workload_1.s1_fixed_workload_1_bi" +paths = [ + "../../tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot", +] +expect_dir = "../../tests/fpga-debugging/axi-lite-s1/expects" +expect_name = "s1_fixed_workload_1.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot --wave tests/fpga-debugging/axi-lite-s1/s1_fixed_workload1.vcd --instances TOP.testbench.UUT:WriteSubordinate TOP.testbench.UUT:ReadSubordinate --sample-posedge TOP.testbench.UUT.S_AXI_ACLK --show-waveform-time --time-unit ns --include-idle 2>/dev/null" + +[[tests]] +name = "bi.tests_fpga_debugging_axi_stream_s2_s2_buggy.s2_buggy_bi" +paths = [ + "../../tests/fpga-debugging/axi-stream-s2/s2_buggy.prot", +] +expect_dir = "../../tests/fpga-debugging/axi-stream-s2/expects" +expect_name = "s2_buggy.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axi-stream-s2/s2_buggy.prot --wave tests/fpga-debugging/axi-stream-s2/s2_buggy.fst --instances TOP.testbench.UUT.axi_stream_check:AXISManager --sample-posedge TOP.testbench.UUT.axi_stream_check.i_aclk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_fpga_debugging_axi_stream_s2_s2_fixed.s2_fixed_bi" +paths = [ + "../../tests/fpga-debugging/axi-stream-s2/s2_fixed.prot", +] +expect_dir = "../../tests/fpga-debugging/axi-stream-s2/expects" +expect_name = "s2_fixed.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axi-stream-s2/s2_fixed.prot --wave tests/fpga-debugging/axi-stream-s2/s2_fixed.fst --instances TOP.testbench.UUT.axi_stream_check:AXISManager --sample-posedge TOP.testbench.UUT.axi_stream_check.i_aclk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_fpga_debugging_axis_adapter_s3_s3_buggy.s3_buggy_bi" +paths = [ + "../../tests/fpga-debugging/axis-adapter-s3/s3_buggy.prot", +] +expect_dir = "../../tests/fpga-debugging/axis-adapter-s3/expects" +expect_name = "s3_buggy.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axis-adapter-s3/s3_buggy.prot --wave tests/fpga-debugging/axis-adapter-s3/s3_buggy.fst --instances TOP.test_axis_adapter_64_8.UUT:AXISManager --sample-posedge TOP.test_axis_adapter_64_8.UUT.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_fpga_debugging_axis_adapter_s3_s3_fixed.s3_fixed_bi" +paths = [ + "../../tests/fpga-debugging/axis-adapter-s3/s3_fixed.prot", +] +expect_dir = "../../tests/fpga-debugging/axis-adapter-s3/expects" +expect_name = "s3_fixed.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axis-adapter-s3/s3_fixed.prot --wave tests/fpga-debugging/axis-adapter-s3/s3_fixed.fst --instances TOP.test_axis_adapter_64_8.UUT:AXISManager --sample-posedge TOP.test_axis_adapter_64_8.UUT.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_fpga_debugging_axis_async_fifo_c4_c4_buggy.c4_buggy_bi" +paths = [ + "../../tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot", +] +expect_dir = "../../tests/fpga-debugging/axis-async-fifo-c4/expects" +expect_name = "c4_buggy.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot --wave tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.fst --instances TOP.test_axis_async_fifo.UUT.axis_reg_inst:Sender TOP.test_axis_async_fifo.UUT.axis_reg_inst:Receiver --sample-posedge TOP.test_axis_async_fifo.UUT.axis_reg_inst.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_fpga_debugging_axis_async_fifo_c4_c4_fixed.c4_fixed_bi" +paths = [ + "../../tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.prot", +] +expect_dir = "../../tests/fpga-debugging/axis-async-fifo-c4/expects" +expect_name = "c4_fixed.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.prot --wave tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.fst --instances TOP.test_axis_async_fifo.UUT.axis_reg_inst:Sender TOP.test_axis_async_fifo.UUT.axis_reg_inst:Receiver --sample-posedge TOP.test_axis_async_fifo.UUT.axis_reg_inst.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_fpga_debugging_axis_fifo_d11_d11_buggy.d11_buggy_bi" +paths = [ + "../../tests/fpga-debugging/axis-fifo-d11/d11_buggy.prot", +] +expect_dir = "../../tests/fpga-debugging/axis-fifo-d11/expects" +expect_name = "d11_buggy.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axis-fifo-d11/d11_buggy.prot --wave tests/fpga-debugging/axis-fifo-d11/d11_buggy.fst --instances TOP.test_axis_fifo:AxisFifo --sample-posedge TOP.test_axis_fifo.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_fpga_debugging_axis_fifo_d11_d11_fixed.d11_fixed_bi" +paths = [ + "../../tests/fpga-debugging/axis-fifo-d11/d11_fixed.prot", +] +expect_dir = "../../tests/fpga-debugging/axis-fifo-d11/expects" +expect_name = "d11_fixed.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axis-fifo-d11/d11_fixed.prot --wave tests/fpga-debugging/axis-fifo-d11/d11_fixed.fst --instances TOP.test_axis_fifo:AxisFifo --sample-posedge TOP.test_axis_fifo.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_fpga_debugging_axis_fifo_d12_d12_buggy.d12_buggy_bi" +paths = [ + "../../tests/fpga-debugging/axis-fifo-d12/d12_buggy.prot", +] +expect_dir = "../../tests/fpga-debugging/axis-fifo-d12/expects" +expect_name = "d12_buggy.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axis-fifo-d12/d12_buggy.prot --wave tests/fpga-debugging/axis-fifo-d12/d12_buggy.fst --instances TOP.test_axis_fifo:AxisFifo --sample-posedge TOP.test_axis_fifo.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_fpga_debugging_axis_fifo_d12_d12_fixed.d12_fixed_bi" +paths = [ + "../../tests/fpga-debugging/axis-fifo-d12/d12_fixed.prot", +] +expect_dir = "../../tests/fpga-debugging/axis-fifo-d12/expects" +expect_name = "d12_fixed.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axis-fifo-d12/d12_fixed.prot --wave tests/fpga-debugging/axis-fifo-d12/d12_fixed.fst --instances TOP.test_axis_fifo:AxisFifo --sample-posedge TOP.test_axis_fifo.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_fpga_debugging_axis_fifo_d4_d4_buggy.d4_buggy_bi" +paths = [ + "../../tests/fpga-debugging/axis-fifo-d4/d4_buggy.prot", +] +expect_dir = "../../tests/fpga-debugging/axis-fifo-d4/expects" +expect_name = "d4_buggy.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axis-fifo-d4/d4_buggy.prot --wave tests/fpga-debugging/axis-fifo-d4/d4_buggy.fst --instances TOP.axis_fifo_wrapper.axis_fifo_inst:AxisFifo --sample-posedge TOP.axis_fifo_wrapper.axis_fifo_inst.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_fpga_debugging_axis_fifo_d4_d4_fixed.d4_fixed_bi" +paths = [ + "../../tests/fpga-debugging/axis-fifo-d4/d4_fixed.prot", +] +expect_dir = "../../tests/fpga-debugging/axis-fifo-d4/expects" +expect_name = "d4_fixed.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axis-fifo-d4/d4_fixed.prot --wave tests/fpga-debugging/axis-fifo-d4/d4_fixed.fst --instances TOP.axis_fifo_wrapper.axis_fifo_inst:AxisFifo --sample-posedge TOP.axis_fifo_wrapper.axis_fifo_inst.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_identities_identity_d1.identity_d1_bi" +paths = [ + "../../tests/identities/identity_d1.prot", +] +expect_dir = "../../tests/identities/expects" +expect_name = "identity_d1.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/identities/identity_d1.prot --wave tests/identities/identity_d1.fst --instances identity_d1:Identity 2>/dev/null" + +[[tests]] +name = "bi.tests_multi_multi0.multi0_bi" +paths = [ + "../../tests/multi/multi0.prot", +] +expect_dir = "../../tests/multi/expects" +expect_name = "multi0.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/multi/multi0.prot --wave tests/multi/multi0.fst --instances multi0:multi0 2>/dev/null" + +[[tests]] +name = "bi.tests_multi_multi0keep.multi0keep_bi" +paths = [ + "../../tests/multi/multi0keep.prot", +] +expect_dir = "../../tests/multi/expects" +expect_name = "multi0keep.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/multi/multi0keep.prot --wave tests/multi/multi0keep.fst --instances multi0keep:multi0keep 2>/dev/null" + +[[tests]] +name = "bi.tests_multi_multi0keep2const.multi0keep2const_bi" +paths = [ + "../../tests/multi/multi0keep2const.prot", +] +expect_dir = "../../tests/multi/expects" +expect_name = "multi0keep2const.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/multi/multi0keep2const.prot --wave tests/multi/multi0keep2const.fst --instances multi0keep2const:multi0keep2const 2>/dev/null" + +[[tests]] +name = "bi.tests_multi_multi2const.multi2const_bi" +paths = [ + "../../tests/multi/multi2const.prot", +] +expect_dir = "../../tests/multi/expects" +expect_name = "multi2const.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/multi/multi2const.prot --wave tests/multi/multi2const.fst --instances multi2const:multi2const 2>/dev/null" + +[[tests]] +name = "bi.tests_multi_multi2multi.multi2multi_bi" +paths = [ + "../../tests/multi/multi2multi.prot", +] +expect_dir = "../../tests/multi/expects" +expect_name = "multi2multi.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/multi/multi2multi.prot --wave tests/multi/multi2multi.fst --instances multi2multi:multi2multi 2>/dev/null" + +[[tests]] +name = "bi.tests_multi_multi_data.multi_data_bi" +paths = [ + "../../tests/multi/multi_data.prot", +] +expect_dir = "../../tests/multi/expects" +expect_name = "multi_data.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/multi/multi_data.prot --wave tests/multi/multi_data.fst --instances multi_data:multi_data 2>/dev/null" + +[[tests]] +name = "bi.tests_multipliers_mult_d2.mult_d2_bi" +paths = [ + "../../tests/multipliers/mult_d2.prot", +] +expect_dir = "../../tests/multipliers/expects" +expect_name = "mult_d2.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/multipliers/mult_d2.prot --wave tests/multipliers/mult_d2.fst --instances mult_d2:Multiplier 2>/dev/null" + +[[tests]] +name = "bi.tests_picorv32_pcpi_mul_unsigned_mul.pcpi_mul_unsigned_mul_bi" +paths = [ + "../../tests/picorv32/pcpi_mul_unsigned_mul.prot", +] +expect_dir = "../../tests/picorv32/expects" +expect_name = "pcpi_mul_unsigned_mul.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/picorv32/pcpi_mul_unsigned_mul.prot --wave tests/picorv32/unsigned_mul.fst --instances picorv32_pcpi_mul:picorv32_pcpi_mul 2>/dev/null" + +[[tests]] +name = "bi.tests_serv_serv_regfile.serv_regfile_bi" +paths = [ + "../../tests/serv/serv_regfile.prot", +] +expect_dir = "../../tests/serv/expects" +expect_name = "serv_regfile.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/serv/serv_regfile.prot --wave tests/serv/serv_regfile.fst --instances serv_regfile:Regfile --display-hex 2>/dev/null" + +[[tests]] +name = "bi.tests_tinyaes128_aes128.aes128_bi" +paths = [ + "../../tests/tinyaes128/aes128.prot", +] +expect_dir = "../../tests/tinyaes128/expects" +expect_name = "aes128.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/tinyaes128/aes128.prot --wave tests/tinyaes128/aes128.fst --instances aes_128:TinyAES128 --display-hex 2>/dev/null" + +[[tests]] +name = "bi.tests_wal_advanced_axis.axis_bi" +paths = [ + "../../tests/wal/advanced/axis.prot", +] +expect_dir = "../../tests/wal/advanced/expects" +expect_name = "axis.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/wal/advanced/axis.prot --wave tests/wal/advanced/uart-axi.fst --instances uut_rx:AXIS --sample-posedge uut_rx.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_wal_advanced_axis_failing.axis_failing_bi" +paths = [ + "../../tests/wal/advanced/axis_failing.prot", +] +expect_dir = "../../tests/wal/advanced/expects" +expect_name = "axis_failing.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/wal/advanced/axis_failing.prot --wave tests/wal/advanced/uart-axi-minimal.fst --instances uut_rx:AXIS --sample-posedge uut_rx.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_wal_advanced_axis_minimal.axis_minimal_bi" +paths = [ + "../../tests/wal/advanced/axis_minimal.prot", +] +expect_dir = "../../tests/wal/advanced/expects" +expect_name = "axis_minimal.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/wal/advanced/axis_minimal.prot --wave tests/wal/advanced/uart-axi-minimal.fst --instances uut_rx:AXIS --sample-posedge uut_rx.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_wal_advanced_axis_truncated.axis_truncated_bi" +paths = [ + "../../tests/wal/advanced/axis_truncated.prot", +] +expect_dir = "../../tests/wal/advanced/expects" +expect_name = "axis_truncated.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/wal/advanced/axis_truncated.prot --wave tests/wal/advanced/uart-axi-truncated.fst --instances uut_rx:AXIS --sample-posedge uut_rx.clk --show-waveform-time --time-unit ns 2>/dev/null" + +[[tests]] +name = "bi.tests_wal_advanced_axis_truncated_include_idle.axis_truncated_include_idle_bi" +paths = [ + "../../tests/wal/advanced/axis_truncated_include_idle.prot", +] +expect_dir = "../../tests/wal/advanced/expects" +expect_name = "axis_truncated_include_idle.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/wal/advanced/axis_truncated_include_idle.prot --wave tests/wal/advanced/uart-axi-truncated.fst --instances uut_rx:AXIS --sample-posedge uut_rx.clk --show-waveform-time --time-unit ns --include-idle 2>/dev/null" + +[[tests]] +name = "bi.tests_wb_intercon_wb_arb.wb_arb_bi" +paths = [ + "../../tests/wb_intercon/wb_arb.prot", +] +expect_dir = "../../tests/wb_intercon/expects" +expect_name = "wb_arb.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/wb_intercon/wb_arb.prot --instances wb_intercon_tb.wb_arb_tb:WBSubordinate --sample-posedge wb_intercon_tb.wb_arb_tb.wb_clk --show-waveform-time --time-unit s 2>/dev/null" + +[[tests]] +name = "bi.tests_wb_intercon_wb_cdc.wb_cdc_bi" +paths = [ + "../../tests/wb_intercon/wb_cdc.prot", +] +expect_dir = "../../tests/wb_intercon/expects" +expect_name = "wb_cdc.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/wb_intercon/wb_cdc.prot --wave tests/wb_intercon/wb_cdc.fst --instances wb_intercon_tb.wb_cdc_tb.dut:WBSubordinate --sample-posedge wb_intercon_tb.wb_cdc_tb.dut.wbm_clk --show-waveform-time --time-unit s 2>/dev/null" + +[[tests]] +name = "bi.tests_wishbone_wishbone_monitor.wishbone_bi" +paths = [ + "../../tests/wishbone/wishbone.monitor.prot", +] +expect_dir = "../../tests/wishbone/expects" +expect_name = "wishbone.bi.expect" +cmd = "cd ../.. && target/debug/bi --protocol tests/wishbone/wishbone.monitor.prot --wave tests/wishbone/reqwalker.vcd --instances TOP.reqwalker:WBSubordinate --sample-posedge TOP.reqwalker.i_clk 2>/dev/null" From 8ea4731a9a8af01a456c3ef9f5344967649a075c Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sat, 11 Jul 2026 15:08:31 -0400 Subject: [PATCH 04/55] Add expected test output for BI test cases --- tests/adders/expects/add_d1.bi.expect | 5 + tests/adders/expects/add_d2.bi.expect | 5 + tests/adders/expects/add_var_cyc.bi.expect | 27 +++ tests/adders/expects/busy_wait.bi.expect | 2 + .../expects/loop_with_assigns.bi.expect | 2 + .../adders/expects/nested_busy_wait.bi.expect | 2 + tests/alus/expects/alu_d1.bi.expect | 8 + tests/alus/expects/alu_d2.bi.expect | 8 + .../expects/test_fifo_classic_1.bi.expect | 11 + .../expects/test_fifo_classic_2.bi.expect | 13 ++ .../expects/test_fifo_classic_3.bi.expect | 15 ++ .../expects/test_fifo_classic_4.bi.expect | 17 ++ .../expects/test_fifo_classic_5.bi.expect | 19 ++ .../expects/test_fifo_classic_6.bi.expect | 21 ++ .../expects/test_fifo_classic_7.bi.expect | 23 +++ .../expects/test_fifo_classic_8.bi.expect | 25 +++ .../expects/test_fifo_constant_1.bi.expect | 16 ++ .../expects/test_fifo_constant_2.bi.expect | 19 ++ .../expects/test_fifo_constant_3.bi.expect | 22 ++ .../expects/test_fifo_constant_4.bi.expect | 25 +++ .../expects/test_fifo_constant_5.bi.expect | 28 +++ .../expects/test_fifo_constant_6.bi.expect | 31 +++ .../expects/test_fifo_constant_7.bi.expect | 34 ++++ .../expects/test_fifo_constant_8.bi.expect | 37 ++++ .../expects/test_sram_classic_16_0.bi.expect | 41 ++++ .../expects/test_sram_classic_16_12.bi.expect | 41 ++++ .../expects/test_sram_classic_16_4.bi.expect | 41 ++++ .../expects/test_sram_classic_16_8.bi.expect | 41 ++++ .../expects/test_sram_classic_1_0.bi.expect | 11 + .../expects/test_sram_classic_1_12.bi.expect | 11 + .../expects/test_sram_classic_1_4.bi.expect | 11 + .../expects/test_sram_classic_1_8.bi.expect | 11 + .../expects/test_sram_classic_2_0.bi.expect | 13 ++ .../expects/test_sram_classic_2_12.bi.expect | 13 ++ .../expects/test_sram_classic_2_4.bi.expect | 13 ++ .../expects/test_sram_classic_2_8.bi.expect | 13 ++ .../expects/test_sram_classic_4_0.bi.expect | 17 ++ .../expects/test_sram_classic_4_12.bi.expect | 17 ++ .../expects/test_sram_classic_4_4.bi.expect | 17 ++ .../expects/test_sram_classic_4_8.bi.expect | 17 ++ .../expects/test_sram_classic_8_0.bi.expect | 25 +++ .../expects/test_sram_classic_8_12.bi.expect | 25 +++ .../expects/test_sram_classic_8_4.bi.expect | 25 +++ .../expects/test_sram_classic_8_8.bi.expect | 25 +++ .../test_sram_incrementing_16_0_0.bi.expect | 61 ++++++ .../test_sram_incrementing_16_0_1.bi.expect | 61 ++++++ .../test_sram_incrementing_16_0_2.bi.expect | 61 ++++++ .../test_sram_incrementing_16_0_3.bi.expect | 61 ++++++ .../test_sram_incrementing_16_12_0.bi.expect | 61 ++++++ .../test_sram_incrementing_16_12_1.bi.expect | 61 ++++++ .../test_sram_incrementing_16_12_2.bi.expect | 61 ++++++ .../test_sram_incrementing_16_12_3.bi.expect | 61 ++++++ .../test_sram_incrementing_16_4_0.bi.expect | 61 ++++++ .../test_sram_incrementing_16_4_1.bi.expect | 61 ++++++ .../test_sram_incrementing_16_4_2.bi.expect | 61 ++++++ .../test_sram_incrementing_16_4_3.bi.expect | 61 ++++++ .../test_sram_incrementing_16_8_0.bi.expect | 61 ++++++ .../test_sram_incrementing_16_8_1.bi.expect | 61 ++++++ .../test_sram_incrementing_16_8_2.bi.expect | 61 ++++++ .../test_sram_incrementing_16_8_3.bi.expect | 61 ++++++ .../test_sram_incrementing_1_0_0.bi.expect | 16 ++ .../test_sram_incrementing_1_0_1.bi.expect | 16 ++ .../test_sram_incrementing_1_0_2.bi.expect | 16 ++ .../test_sram_incrementing_1_0_3.bi.expect | 16 ++ .../test_sram_incrementing_1_12_0.bi.expect | 16 ++ .../test_sram_incrementing_1_12_1.bi.expect | 16 ++ .../test_sram_incrementing_1_12_2.bi.expect | 16 ++ .../test_sram_incrementing_1_12_3.bi.expect | 16 ++ .../test_sram_incrementing_1_4_0.bi.expect | 16 ++ .../test_sram_incrementing_1_4_1.bi.expect | 16 ++ .../test_sram_incrementing_1_4_2.bi.expect | 16 ++ .../test_sram_incrementing_1_4_3.bi.expect | 16 ++ .../test_sram_incrementing_1_8_0.bi.expect | 16 ++ .../test_sram_incrementing_1_8_1.bi.expect | 16 ++ .../test_sram_incrementing_1_8_2.bi.expect | 16 ++ .../test_sram_incrementing_1_8_3.bi.expect | 16 ++ .../test_sram_incrementing_2_0_0.bi.expect | 19 ++ .../test_sram_incrementing_2_0_1.bi.expect | 19 ++ .../test_sram_incrementing_2_0_2.bi.expect | 19 ++ .../test_sram_incrementing_2_0_3.bi.expect | 19 ++ .../test_sram_incrementing_2_12_0.bi.expect | 19 ++ .../test_sram_incrementing_2_12_1.bi.expect | 19 ++ .../test_sram_incrementing_2_12_2.bi.expect | 19 ++ .../test_sram_incrementing_2_12_3.bi.expect | 19 ++ .../test_sram_incrementing_2_4_0.bi.expect | 19 ++ .../test_sram_incrementing_2_4_1.bi.expect | 19 ++ .../test_sram_incrementing_2_4_2.bi.expect | 19 ++ .../test_sram_incrementing_2_4_3.bi.expect | 19 ++ .../test_sram_incrementing_2_8_0.bi.expect | 19 ++ .../test_sram_incrementing_2_8_1.bi.expect | 19 ++ .../test_sram_incrementing_2_8_2.bi.expect | 19 ++ .../test_sram_incrementing_2_8_3.bi.expect | 19 ++ .../test_sram_incrementing_4_0_0.bi.expect | 25 +++ .../test_sram_incrementing_4_0_1.bi.expect | 25 +++ .../test_sram_incrementing_4_0_2.bi.expect | 25 +++ .../test_sram_incrementing_4_0_3.bi.expect | 25 +++ .../test_sram_incrementing_4_12_0.bi.expect | 25 +++ .../test_sram_incrementing_4_12_1.bi.expect | 25 +++ .../test_sram_incrementing_4_12_2.bi.expect | 25 +++ .../test_sram_incrementing_4_12_3.bi.expect | 25 +++ .../test_sram_incrementing_4_4_0.bi.expect | 25 +++ .../test_sram_incrementing_4_4_1.bi.expect | 25 +++ .../test_sram_incrementing_4_4_2.bi.expect | 25 +++ .../test_sram_incrementing_4_4_3.bi.expect | 25 +++ .../test_sram_incrementing_4_8_0.bi.expect | 25 +++ .../test_sram_incrementing_4_8_1.bi.expect | 25 +++ .../test_sram_incrementing_4_8_2.bi.expect | 25 +++ .../test_sram_incrementing_4_8_3.bi.expect | 25 +++ .../test_sram_incrementing_8_0_0.bi.expect | 37 ++++ .../test_sram_incrementing_8_0_1.bi.expect | 37 ++++ .../test_sram_incrementing_8_0_2.bi.expect | 37 ++++ .../test_sram_incrementing_8_0_3.bi.expect | 37 ++++ .../test_sram_incrementing_8_12_0.bi.expect | 37 ++++ .../test_sram_incrementing_8_12_1.bi.expect | 37 ++++ .../test_sram_incrementing_8_12_2.bi.expect | 37 ++++ .../test_sram_incrementing_8_12_3.bi.expect | 37 ++++ .../test_sram_incrementing_8_4_0.bi.expect | 37 ++++ .../test_sram_incrementing_8_4_1.bi.expect | 37 ++++ .../test_sram_incrementing_8_4_2.bi.expect | 37 ++++ .../test_sram_incrementing_8_4_3.bi.expect | 37 ++++ .../test_sram_incrementing_8_8_0.bi.expect | 37 ++++ .../test_sram_incrementing_8_8_1.bi.expect | 37 ++++ .../test_sram_incrementing_8_8_2.bi.expect | 37 ++++ .../test_sram_incrementing_8_8_3.bi.expect | 37 ++++ .../expects/bit_truncation_fft.bi.expect | 4 + .../expects/bit_truncation_sha.bi.expect | 4 + .../expects/ftu_sha.bi.expect | 4 + .../expects/signal_async.bi.expect | 4 + .../expects/use_without_valid.bi.expect | 4 + .../expects/ethmac_wishbone_manager.bi.expect | 2 + .../ethmac_wishbone_subordinate.bi.expect | 2 + tests/fifo/expects/fifo.bi.expect | 10 + .../fifo/expects/push_pop_identity.bi.expect | 9 + .../expects/push_pop_loop_empty.bi.expect | 2 + .../expects/push_pop_loop_not_empty.bi.expect | 2 + .../axi-burst-s4/expects/s4_buggy.bi.expect | 5 + .../axi-burst-s4/expects/s4_fixed.bi.expect | 4 + .../axi-lite-s1/expects/s1_buggy.bi.expect | 16 ++ .../expects/s1_buggy_workload_1.bi.expect | 49 +++++ .../axi-lite-s1/expects/s1_fixed.bi.expect | 12 ++ .../expects/s1_fixed_workload_1.bi.expect | 41 ++++ tests/fpga-debugging/axi-lite-s1/s1_alt.prot | 189 ++++++++++++++++++ .../axi-stream-s2/expects/s2_buggy.bi.expect | 17 ++ .../axi-stream-s2/expects/s2_fixed.bi.expect | 40 ++++ .../expects/s3_buggy.bi.expect | 13 ++ .../expects/s3_fixed.bi.expect | 12 ++ .../expects/c4_buggy.bi.expect | 28 +++ .../expects/c4_fixed.bi.expect | 26 +++ .../axis-fifo-d11/expects/d11_buggy.bi.expect | 17 ++ .../axis-fifo-d11/expects/d11_fixed.bi.expect | 21 ++ .../axis-fifo-d12/expects/d12_buggy.bi.expect | 16 ++ .../axis-fifo-d12/expects/d12_fixed.bi.expect | 15 ++ .../axis-fifo-d4/expects/d4_buggy.bi.expect | 47 +++++ .../axis-fifo-d4/expects/d4_fixed.bi.expect | 48 +++++ .../identities/expects/identity_d1.bi.expect | 2 + tests/multi/expects/multi0.bi.expect | 4 + tests/multi/expects/multi0keep.bi.expect | 4 + .../multi/expects/multi0keep2const.bi.expect | 4 + tests/multi/expects/multi2const.bi.expect | 4 + tests/multi/expects/multi2multi.bi.expect | 4 + tests/multi/expects/multi_data.bi.expect | 4 + tests/multipliers/expects/mult_d2.bi.expect | 5 + .../expects/pcpi_mul_unsigned_mul.bi.expect | 8 + tests/serv/expects/serv_regfile.bi.expect | 2 + tests/tinyaes128/expects/aes128.bi.expect | 5 + tests/wal/advanced/expects/axis.bi.expect | 9 + .../advanced/expects/axis_failing.bi.expect | 5 + .../advanced/expects/axis_minimal.bi.expect | 5 + .../advanced/expects/axis_truncated.bi.expect | 5 + .../axis_truncated_include_idle.bi.expect | 5 + tests/wb_intercon/expects/wb_arb.bi.expect | 2 + tests/wb_intercon/expects/wb_cdc.bi.expect | 2 + tests/wishbone/expects/wishbone.bi.expect | 18 ++ 173 files changed, 4131 insertions(+) create mode 100644 tests/adders/expects/add_d1.bi.expect create mode 100644 tests/adders/expects/add_d2.bi.expect create mode 100644 tests/adders/expects/add_var_cyc.bi.expect create mode 100644 tests/adders/expects/busy_wait.bi.expect create mode 100644 tests/adders/expects/loop_with_assigns.bi.expect create mode 100644 tests/adders/expects/nested_busy_wait.bi.expect create mode 100644 tests/alus/expects/alu_d1.bi.expect create mode 100644 tests/alus/expects/alu_d2.bi.expect create mode 100644 tests/antmicro/fifo_classic/expects/test_fifo_classic_1.bi.expect create mode 100644 tests/antmicro/fifo_classic/expects/test_fifo_classic_2.bi.expect create mode 100644 tests/antmicro/fifo_classic/expects/test_fifo_classic_3.bi.expect create mode 100644 tests/antmicro/fifo_classic/expects/test_fifo_classic_4.bi.expect create mode 100644 tests/antmicro/fifo_classic/expects/test_fifo_classic_5.bi.expect create mode 100644 tests/antmicro/fifo_classic/expects/test_fifo_classic_6.bi.expect create mode 100644 tests/antmicro/fifo_classic/expects/test_fifo_classic_7.bi.expect create mode 100644 tests/antmicro/fifo_classic/expects/test_fifo_classic_8.bi.expect create mode 100644 tests/antmicro/fifo_constant/expects/test_fifo_constant_1.bi.expect create mode 100644 tests/antmicro/fifo_constant/expects/test_fifo_constant_2.bi.expect create mode 100644 tests/antmicro/fifo_constant/expects/test_fifo_constant_3.bi.expect create mode 100644 tests/antmicro/fifo_constant/expects/test_fifo_constant_4.bi.expect create mode 100644 tests/antmicro/fifo_constant/expects/test_fifo_constant_5.bi.expect create mode 100644 tests/antmicro/fifo_constant/expects/test_fifo_constant_6.bi.expect create mode 100644 tests/antmicro/fifo_constant/expects/test_fifo_constant_7.bi.expect create mode 100644 tests/antmicro/fifo_constant/expects/test_fifo_constant_8.bi.expect create mode 100644 tests/antmicro/sram_classic/expects/test_sram_classic_16_0.bi.expect create mode 100644 tests/antmicro/sram_classic/expects/test_sram_classic_16_12.bi.expect create mode 100644 tests/antmicro/sram_classic/expects/test_sram_classic_16_4.bi.expect create mode 100644 tests/antmicro/sram_classic/expects/test_sram_classic_16_8.bi.expect create mode 100644 tests/antmicro/sram_classic/expects/test_sram_classic_1_0.bi.expect create mode 100644 tests/antmicro/sram_classic/expects/test_sram_classic_1_12.bi.expect create mode 100644 tests/antmicro/sram_classic/expects/test_sram_classic_1_4.bi.expect create mode 100644 tests/antmicro/sram_classic/expects/test_sram_classic_1_8.bi.expect create mode 100644 tests/antmicro/sram_classic/expects/test_sram_classic_2_0.bi.expect create mode 100644 tests/antmicro/sram_classic/expects/test_sram_classic_2_12.bi.expect create mode 100644 tests/antmicro/sram_classic/expects/test_sram_classic_2_4.bi.expect create mode 100644 tests/antmicro/sram_classic/expects/test_sram_classic_2_8.bi.expect create mode 100644 tests/antmicro/sram_classic/expects/test_sram_classic_4_0.bi.expect create mode 100644 tests/antmicro/sram_classic/expects/test_sram_classic_4_12.bi.expect create mode 100644 tests/antmicro/sram_classic/expects/test_sram_classic_4_4.bi.expect create mode 100644 tests/antmicro/sram_classic/expects/test_sram_classic_4_8.bi.expect create mode 100644 tests/antmicro/sram_classic/expects/test_sram_classic_8_0.bi.expect create mode 100644 tests/antmicro/sram_classic/expects/test_sram_classic_8_12.bi.expect create mode 100644 tests/antmicro/sram_classic/expects/test_sram_classic_8_4.bi.expect create mode 100644 tests/antmicro/sram_classic/expects/test_sram_classic_8_8.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_0_0.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_0_1.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_0_2.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_0_3.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_12_0.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_12_1.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_12_2.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_12_3.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_4_0.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_4_1.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_4_2.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_4_3.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_8_0.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_8_1.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_8_2.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_8_3.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_0_0.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_0_1.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_0_2.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_0_3.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_12_0.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_12_1.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_12_2.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_12_3.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_4_0.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_4_1.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_4_2.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_4_3.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_8_0.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_8_1.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_8_2.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_8_3.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_0_0.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_0_1.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_0_2.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_0_3.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_12_0.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_12_1.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_12_2.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_12_3.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_4_0.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_4_1.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_4_2.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_4_3.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_8_0.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_8_1.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_8_2.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_8_3.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_0_0.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_0_1.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_0_2.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_0_3.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_12_0.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_12_1.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_12_2.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_12_3.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_4_0.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_4_1.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_4_2.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_4_3.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_8_0.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_8_1.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_8_2.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_8_3.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_0_0.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_0_1.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_0_2.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_0_3.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_12_0.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_12_1.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_12_2.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_12_3.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_4_0.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_4_1.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_4_2.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_4_3.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_8_0.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_8_1.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_8_2.bi.expect create mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_8_3.bi.expect create mode 100644 tests/brave_new_world_francis/expects/bit_truncation_fft.bi.expect create mode 100644 tests/brave_new_world_francis/expects/bit_truncation_sha.bi.expect create mode 100644 tests/brave_new_world_francis/expects/ftu_sha.bi.expect create mode 100644 tests/brave_new_world_francis/expects/signal_async.bi.expect create mode 100644 tests/brave_new_world_francis/expects/use_without_valid.bi.expect create mode 100644 tests/ethmac/expects/ethmac_wishbone_manager.bi.expect create mode 100644 tests/ethmac/expects/ethmac_wishbone_subordinate.bi.expect create mode 100644 tests/fifo/expects/fifo.bi.expect create mode 100644 tests/fifo/expects/push_pop_identity.bi.expect create mode 100644 tests/fifo/expects/push_pop_loop_empty.bi.expect create mode 100644 tests/fifo/expects/push_pop_loop_not_empty.bi.expect create mode 100644 tests/fpga-debugging/axi-burst-s4/expects/s4_buggy.bi.expect create mode 100644 tests/fpga-debugging/axi-burst-s4/expects/s4_fixed.bi.expect create mode 100644 tests/fpga-debugging/axi-lite-s1/expects/s1_buggy.bi.expect create mode 100644 tests/fpga-debugging/axi-lite-s1/expects/s1_buggy_workload_1.bi.expect create mode 100644 tests/fpga-debugging/axi-lite-s1/expects/s1_fixed.bi.expect create mode 100644 tests/fpga-debugging/axi-lite-s1/expects/s1_fixed_workload_1.bi.expect create mode 100644 tests/fpga-debugging/axi-lite-s1/s1_alt.prot create mode 100644 tests/fpga-debugging/axi-stream-s2/expects/s2_buggy.bi.expect create mode 100644 tests/fpga-debugging/axi-stream-s2/expects/s2_fixed.bi.expect create mode 100644 tests/fpga-debugging/axis-adapter-s3/expects/s3_buggy.bi.expect create mode 100644 tests/fpga-debugging/axis-adapter-s3/expects/s3_fixed.bi.expect create mode 100644 tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.bi.expect create mode 100644 tests/fpga-debugging/axis-async-fifo-c4/expects/c4_fixed.bi.expect create mode 100644 tests/fpga-debugging/axis-fifo-d11/expects/d11_buggy.bi.expect create mode 100644 tests/fpga-debugging/axis-fifo-d11/expects/d11_fixed.bi.expect create mode 100644 tests/fpga-debugging/axis-fifo-d12/expects/d12_buggy.bi.expect create mode 100644 tests/fpga-debugging/axis-fifo-d12/expects/d12_fixed.bi.expect create mode 100644 tests/fpga-debugging/axis-fifo-d4/expects/d4_buggy.bi.expect create mode 100644 tests/fpga-debugging/axis-fifo-d4/expects/d4_fixed.bi.expect create mode 100644 tests/identities/expects/identity_d1.bi.expect create mode 100644 tests/multi/expects/multi0.bi.expect create mode 100644 tests/multi/expects/multi0keep.bi.expect create mode 100644 tests/multi/expects/multi0keep2const.bi.expect create mode 100644 tests/multi/expects/multi2const.bi.expect create mode 100644 tests/multi/expects/multi2multi.bi.expect create mode 100644 tests/multi/expects/multi_data.bi.expect create mode 100644 tests/multipliers/expects/mult_d2.bi.expect create mode 100644 tests/picorv32/expects/pcpi_mul_unsigned_mul.bi.expect create mode 100644 tests/serv/expects/serv_regfile.bi.expect create mode 100644 tests/tinyaes128/expects/aes128.bi.expect create mode 100644 tests/wal/advanced/expects/axis.bi.expect create mode 100644 tests/wal/advanced/expects/axis_failing.bi.expect create mode 100644 tests/wal/advanced/expects/axis_minimal.bi.expect create mode 100644 tests/wal/advanced/expects/axis_truncated.bi.expect create mode 100644 tests/wal/advanced/expects/axis_truncated_include_idle.bi.expect create mode 100644 tests/wb_intercon/expects/wb_arb.bi.expect create mode 100644 tests/wb_intercon/expects/wb_cdc.bi.expect create mode 100644 tests/wishbone/expects/wishbone.bi.expect diff --git a/tests/adders/expects/add_d1.bi.expect b/tests/adders/expects/add_d1.bi.expect new file mode 100644 index 00000000..ff76d998 --- /dev/null +++ b/tests/adders/expects/add_d1.bi.expect @@ -0,0 +1,5 @@ +// trace 0 +trace { + add(1, 2, 3); + add(4, 5, 9); +} diff --git a/tests/adders/expects/add_d2.bi.expect b/tests/adders/expects/add_d2.bi.expect new file mode 100644 index 00000000..ff76d998 --- /dev/null +++ b/tests/adders/expects/add_d2.bi.expect @@ -0,0 +1,5 @@ +// trace 0 +trace { + add(1, 2, 3); + add(4, 5, 9); +} diff --git a/tests/adders/expects/add_var_cyc.bi.expect b/tests/adders/expects/add_var_cyc.bi.expect new file mode 100644 index 00000000..3d640dc7 --- /dev/null +++ b/tests/adders/expects/add_var_cyc.bi.expect @@ -0,0 +1,27 @@ +// trace 0 +trace { + loop_add(1, 2, 3, 1); + loop_add(1, 2, 3, 0); + loop_add(10, 20, 30, 0); +} + +// trace 1 +trace { + loop_add(1, 2, 3, 2); + loop_add(10, 20, 30, 0); +} + +// trace 2 +trace { + loop_add(1, 2, 3, 0); + loop_add(1, 2, 3, 0); + loop_add(1, 2, 3, 0); + loop_add(10, 20, 30, 0); +} + +// trace 3 +trace { + loop_add(1, 2, 3, 0); + loop_add(1, 2, 3, 1); + loop_add(10, 20, 30, 0); +} diff --git a/tests/adders/expects/busy_wait.bi.expect b/tests/adders/expects/busy_wait.bi.expect new file mode 100644 index 00000000..c9f68b19 --- /dev/null +++ b/tests/adders/expects/busy_wait.bi.expect @@ -0,0 +1,2 @@ +---CODE--- +101 diff --git a/tests/adders/expects/loop_with_assigns.bi.expect b/tests/adders/expects/loop_with_assigns.bi.expect new file mode 100644 index 00000000..c9f68b19 --- /dev/null +++ b/tests/adders/expects/loop_with_assigns.bi.expect @@ -0,0 +1,2 @@ +---CODE--- +101 diff --git a/tests/adders/expects/nested_busy_wait.bi.expect b/tests/adders/expects/nested_busy_wait.bi.expect new file mode 100644 index 00000000..c9f68b19 --- /dev/null +++ b/tests/adders/expects/nested_busy_wait.bi.expect @@ -0,0 +1,2 @@ +---CODE--- +101 diff --git a/tests/alus/expects/alu_d1.bi.expect b/tests/alus/expects/alu_d1.bi.expect new file mode 100644 index 00000000..16fa0842 --- /dev/null +++ b/tests/alus/expects/alu_d1.bi.expect @@ -0,0 +1,8 @@ +// trace 0 +trace { + add(1, 2, 3); + add(123, 245, 368); + sub(200, 200, 0); + and(100, 100, 100); + or(0, 230, 230); +} diff --git a/tests/alus/expects/alu_d2.bi.expect b/tests/alus/expects/alu_d2.bi.expect new file mode 100644 index 00000000..16fa0842 --- /dev/null +++ b/tests/alus/expects/alu_d2.bi.expect @@ -0,0 +1,8 @@ +// trace 0 +trace { + add(1, 2, 3); + add(123, 245, 368); + sub(200, 200, 0); + and(100, 100, 100); + or(0, 230, 230); +} diff --git a/tests/antmicro/fifo_classic/expects/test_fifo_classic_1.bi.expect b/tests/antmicro/fifo_classic/expects/test_fifo_classic_1.bi.expect new file mode 100644 index 00000000..ff0306dd --- /dev/null +++ b/tests/antmicro/fifo_classic/expects/test_fifo_classic_1.bi.expect @@ -0,0 +1,11 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 872415232, 3511065769, 0); // [time: 110ns -> 130ns] + reset(); // [time: 170.001ns -> 180.001ns] + reset(); // [time: 180.001ns -> 190.001ns] + reset(); // [time: 190.001ns -> 200.001ns] + write(15, 872415232, 2839611496, 0); // [time: 240.001ns -> 260.001ns] +} diff --git a/tests/antmicro/fifo_classic/expects/test_fifo_classic_2.bi.expect b/tests/antmicro/fifo_classic/expects/test_fifo_classic_2.bi.expect new file mode 100644 index 00000000..2fcf485a --- /dev/null +++ b/tests/antmicro/fifo_classic/expects/test_fifo_classic_2.bi.expect @@ -0,0 +1,13 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 872415232, 3511065769, 0); // [time: 130ns -> 150ns] + read(15, 872415232, 2839611496, 0); // [time: 150ns -> 170ns] + reset(); // [time: 210.001ns -> 220.001ns] + reset(); // [time: 220.001ns -> 230.001ns] + reset(); // [time: 230.001ns -> 240.001ns] + write(15, 872415232, 4255599317, 0); // [time: 280.001ns -> 300.001ns] + write(15, 872415232, 2978480611, 0); // [time: 300.001ns -> 320.001ns] +} diff --git a/tests/antmicro/fifo_classic/expects/test_fifo_classic_3.bi.expect b/tests/antmicro/fifo_classic/expects/test_fifo_classic_3.bi.expect new file mode 100644 index 00000000..f90eb06e --- /dev/null +++ b/tests/antmicro/fifo_classic/expects/test_fifo_classic_3.bi.expect @@ -0,0 +1,15 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 872415232, 3511065769, 0); // [time: 150ns -> 170ns] + read(15, 872415232, 2839611496, 0); // [time: 170ns -> 190ns] + read(15, 872415232, 4255599317, 0); // [time: 190ns -> 210ns] + reset(); // [time: 250.001ns -> 260.001ns] + reset(); // [time: 260.001ns -> 270.001ns] + reset(); // [time: 270.001ns -> 280.001ns] + write(15, 872415232, 2978480611, 0); // [time: 320.001ns -> 340.001ns] + write(15, 872415232, 2227458782, 0); // [time: 340.001ns -> 360.001ns] + write(15, 872415232, 2594436392, 0); // [time: 360.001ns -> 380.001ns] +} diff --git a/tests/antmicro/fifo_classic/expects/test_fifo_classic_4.bi.expect b/tests/antmicro/fifo_classic/expects/test_fifo_classic_4.bi.expect new file mode 100644 index 00000000..9dd58394 --- /dev/null +++ b/tests/antmicro/fifo_classic/expects/test_fifo_classic_4.bi.expect @@ -0,0 +1,17 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 872415232, 3511065769, 0); // [time: 170ns -> 190ns] + read(15, 872415232, 2839611496, 0); // [time: 190ns -> 210ns] + read(15, 872415232, 4255599317, 0); // [time: 210ns -> 230ns] + read(15, 872415232, 2978480611, 0); // [time: 230ns -> 250ns] + reset(); // [time: 290.001ns -> 300.001ns] + reset(); // [time: 300.001ns -> 310.001ns] + reset(); // [time: 310.001ns -> 320.001ns] + write(15, 872415232, 2227458782, 0); // [time: 360.001ns -> 380.001ns] + write(15, 872415232, 2594436392, 0); // [time: 380.001ns -> 400.001ns] + write(15, 872415232, 2879904594, 0); // [time: 400.001ns -> 420.001ns] + write(15, 872415232, 2502756630, 0); // [time: 420.001ns -> 440.001ns] +} diff --git a/tests/antmicro/fifo_classic/expects/test_fifo_classic_5.bi.expect b/tests/antmicro/fifo_classic/expects/test_fifo_classic_5.bi.expect new file mode 100644 index 00000000..906c59ca --- /dev/null +++ b/tests/antmicro/fifo_classic/expects/test_fifo_classic_5.bi.expect @@ -0,0 +1,19 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 872415232, 3511065769, 0); // [time: 190ns -> 210ns] + read(15, 872415232, 2839611496, 0); // [time: 210ns -> 230ns] + read(15, 872415232, 4255599317, 0); // [time: 230ns -> 250ns] + read(15, 872415232, 2978480611, 0); // [time: 250ns -> 270ns] + read(15, 872415232, 2227458782, 0); // [time: 270ns -> 290ns] + reset(); // [time: 330.001ns -> 340.001ns] + reset(); // [time: 340.001ns -> 350.001ns] + reset(); // [time: 350.001ns -> 360.001ns] + write(15, 872415232, 2594436392, 0); // [time: 400.001ns -> 420.001ns] + write(15, 872415232, 2879904594, 0); // [time: 420.001ns -> 440.001ns] + write(15, 872415232, 2502756630, 0); // [time: 440.001ns -> 460.001ns] + write(15, 872415232, 3888695605, 0); // [time: 460.001ns -> 480.001ns] + write(15, 872415232, 4181798306, 0); // [time: 480.001ns -> 500.001ns] +} diff --git a/tests/antmicro/fifo_classic/expects/test_fifo_classic_6.bi.expect b/tests/antmicro/fifo_classic/expects/test_fifo_classic_6.bi.expect new file mode 100644 index 00000000..fd22df44 --- /dev/null +++ b/tests/antmicro/fifo_classic/expects/test_fifo_classic_6.bi.expect @@ -0,0 +1,21 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 872415232, 2215956531, 0); // [time: 210ns -> 230ns] + read(15, 872415232, 2174594346, 0); // [time: 230ns -> 250ns] + read(15, 872415232, 3706263408, 0); // [time: 250ns -> 270ns] + read(15, 872415232, 3375769081, 0); // [time: 270ns -> 290ns] + read(15, 872415232, 3915557832, 0); // [time: 290ns -> 310ns] + read(15, 872415232, 2529678886, 0); // [time: 310ns -> 330ns] + reset(); // [time: 370.001ns -> 380.001ns] + reset(); // [time: 380.001ns -> 390.001ns] + reset(); // [time: 390.001ns -> 400.001ns] + write(15, 872415232, 2550371957, 0); // [time: 440.001ns -> 460.001ns] + write(15, 872415232, 2973140726, 0); // [time: 460.001ns -> 480.001ns] + write(15, 872415232, 3658948496, 0); // [time: 480.001ns -> 500.001ns] + write(15, 872415232, 4239119767, 0); // [time: 500.001ns -> 520.001ns] + write(15, 872415232, 2305440508, 0); // [time: 520.001ns -> 540.001ns] + write(15, 872415232, 2674771663, 0); // [time: 540.001ns -> 560.001ns] +} diff --git a/tests/antmicro/fifo_classic/expects/test_fifo_classic_7.bi.expect b/tests/antmicro/fifo_classic/expects/test_fifo_classic_7.bi.expect new file mode 100644 index 00000000..21ba8129 --- /dev/null +++ b/tests/antmicro/fifo_classic/expects/test_fifo_classic_7.bi.expect @@ -0,0 +1,23 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 872415232, 2215956531, 0); // [time: 230ns -> 250ns] + read(15, 872415232, 2174594346, 0); // [time: 250ns -> 270ns] + read(15, 872415232, 3706263408, 0); // [time: 270ns -> 290ns] + read(15, 872415232, 3375769081, 0); // [time: 290ns -> 310ns] + read(15, 872415232, 3915557832, 0); // [time: 310ns -> 330ns] + read(15, 872415232, 2529678886, 0); // [time: 330ns -> 350ns] + read(15, 872415232, 2550371957, 0); // [time: 350ns -> 370ns] + reset(); // [time: 410.001ns -> 420.001ns] + reset(); // [time: 420.001ns -> 430.001ns] + reset(); // [time: 430.001ns -> 440.001ns] + write(15, 872415232, 2973140726, 0); // [time: 480.001ns -> 500.001ns] + write(15, 872415232, 3658948496, 0); // [time: 500.001ns -> 520.001ns] + write(15, 872415232, 4239119767, 0); // [time: 520.001ns -> 540.001ns] + write(15, 872415232, 2305440508, 0); // [time: 540.001ns -> 560.001ns] + write(15, 872415232, 2674771663, 0); // [time: 560.001ns -> 580.001ns] + write(15, 872415232, 4005297405, 0); // [time: 580.001ns -> 600.001ns] + write(15, 872415232, 2923162757, 0); // [time: 600.001ns -> 620.001ns] +} diff --git a/tests/antmicro/fifo_classic/expects/test_fifo_classic_8.bi.expect b/tests/antmicro/fifo_classic/expects/test_fifo_classic_8.bi.expect new file mode 100644 index 00000000..64b96213 --- /dev/null +++ b/tests/antmicro/fifo_classic/expects/test_fifo_classic_8.bi.expect @@ -0,0 +1,25 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 872415232, 2215956531, 0); // [time: 250ns -> 270ns] + read(15, 872415232, 2174594346, 0); // [time: 270ns -> 290ns] + read(15, 872415232, 3706263408, 0); // [time: 290ns -> 310ns] + read(15, 872415232, 3375769081, 0); // [time: 310ns -> 330ns] + read(15, 872415232, 3915557832, 0); // [time: 330ns -> 350ns] + read(15, 872415232, 2529678886, 0); // [time: 350ns -> 370ns] + read(15, 872415232, 2550371957, 0); // [time: 370ns -> 390ns] + read(15, 872415232, 2973140726, 0); // [time: 390ns -> 410ns] + reset(); // [time: 450.001ns -> 460.001ns] + reset(); // [time: 460.001ns -> 470.001ns] + reset(); // [time: 470.001ns -> 480.001ns] + write(15, 872415232, 3658948496, 0); // [time: 520.001ns -> 540.001ns] + write(15, 872415232, 4239119767, 0); // [time: 540.001ns -> 560.001ns] + write(15, 872415232, 2305440508, 0); // [time: 560.001ns -> 580.001ns] + write(15, 872415232, 2674771663, 0); // [time: 580.001ns -> 600.001ns] + write(15, 872415232, 4005297405, 0); // [time: 600.001ns -> 620.001ns] + write(15, 872415232, 2923162757, 0); // [time: 620.001ns -> 640.001ns] + write(15, 872415232, 2212602639, 0); // [time: 640.001ns -> 660.001ns] + write(15, 872415232, 3940387843, 0); // [time: 660.001ns -> 680.001ns] +} diff --git a/tests/antmicro/fifo_constant/expects/test_fifo_constant_1.bi.expect b/tests/antmicro/fifo_constant/expects/test_fifo_constant_1.bi.expect new file mode 100644 index 00000000..e26f1c51 --- /dev/null +++ b/tests/antmicro/fifo_constant/expects/test_fifo_constant_1.bi.expect @@ -0,0 +1,16 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 872415232, 136945767, 0); // [time: 110ns -> 130ns] + reset(); // [time: 170.001ns -> 180.001ns] + reset(); // [time: 180.001ns -> 190.001ns] + reset(); // [time: 190.001ns -> 200.001ns] + write(15, 872415232, 54221397, 0); // [time: 240.001ns -> 260.001ns] + reset(); // [time: 320.002ns -> 330.002ns] + reset(); // [time: 330.002ns -> 340.002ns] + reset(); // [time: 340.002ns -> 350.002ns] + write(15, 872415232, 3117559521, 0); // [time: 410.002ns -> 430.002ns] + read(15, 872415232, 6, 0); // [time: 430.002ns -> 450.002ns] +} diff --git a/tests/antmicro/fifo_constant/expects/test_fifo_constant_2.bi.expect b/tests/antmicro/fifo_constant/expects/test_fifo_constant_2.bi.expect new file mode 100644 index 00000000..10aa066c --- /dev/null +++ b/tests/antmicro/fifo_constant/expects/test_fifo_constant_2.bi.expect @@ -0,0 +1,19 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 872415232, 136945767, 0); // [time: 130ns -> 150ns] + read(15, 872415232, 54221397, 0); // [time: 150ns -> 160ns] + reset(); // [time: 200.001ns -> 210.001ns] + reset(); // [time: 210.001ns -> 220.001ns] + reset(); // [time: 220.001ns -> 230.001ns] + write(15, 872415232, 3117559521, 0); // [time: 270.001ns -> 290.001ns] + write(15, 872415232, 2456570867, 0); // [time: 290.001ns -> 300.001ns] + reset(); // [time: 380.002ns -> 390.002ns] + reset(); // [time: 390.002ns -> 400.002ns] + reset(); // [time: 400.002ns -> 410.002ns] + write(15, 872415232, 3536148369, 0); // [time: 470.002ns -> 490.002ns] + write(15, 872415232, 764390477, 0); // [time: 490.002ns -> 500.002ns] + read(15, 872415232, 6, 0); // [time: 500.002ns -> 520.002ns] +} diff --git a/tests/antmicro/fifo_constant/expects/test_fifo_constant_3.bi.expect b/tests/antmicro/fifo_constant/expects/test_fifo_constant_3.bi.expect new file mode 100644 index 00000000..905246ba --- /dev/null +++ b/tests/antmicro/fifo_constant/expects/test_fifo_constant_3.bi.expect @@ -0,0 +1,22 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 872415232, 136945767, 0); // [time: 150ns -> 170ns] + read(15, 872415232, 54221397, 0); // [time: 170ns -> 180ns] + read(15, 872415232, 3117559521, 0); // [time: 180ns -> 190ns] + reset(); // [time: 230.001ns -> 240.001ns] + reset(); // [time: 240.001ns -> 250.001ns] + reset(); // [time: 250.001ns -> 260.001ns] + write(15, 872415232, 2456570867, 0); // [time: 300.001ns -> 320.001ns] + write(15, 872415232, 3536148369, 0); // [time: 320.001ns -> 330.001ns] + write(15, 872415232, 764390477, 0); // [time: 330.001ns -> 340.001ns] + reset(); // [time: 440.002ns -> 450.002ns] + reset(); // [time: 450.002ns -> 460.002ns] + reset(); // [time: 460.002ns -> 470.002ns] + write(15, 872415232, 805776619, 0); // [time: 530.002ns -> 550.002ns] + write(15, 872415232, 1651314158, 0); // [time: 550.002ns -> 560.002ns] + write(15, 872415232, 3022929697, 0); // [time: 560.002ns -> 570.002ns] + read(15, 872415232, 6, 0); // [time: 570.002ns -> 590.002ns] +} diff --git a/tests/antmicro/fifo_constant/expects/test_fifo_constant_4.bi.expect b/tests/antmicro/fifo_constant/expects/test_fifo_constant_4.bi.expect new file mode 100644 index 00000000..8bd13fef --- /dev/null +++ b/tests/antmicro/fifo_constant/expects/test_fifo_constant_4.bi.expect @@ -0,0 +1,25 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 872415232, 136945767, 0); // [time: 170ns -> 190ns] + read(15, 872415232, 54221397, 0); // [time: 190ns -> 200ns] + read(15, 872415232, 3117559521, 0); // [time: 200ns -> 210ns] + read(15, 872415232, 2456570867, 0); // [time: 210ns -> 220ns] + reset(); // [time: 260.001ns -> 270.001ns] + reset(); // [time: 270.001ns -> 280.001ns] + reset(); // [time: 280.001ns -> 290.001ns] + write(15, 872415232, 3536148369, 0); // [time: 330.001ns -> 350.001ns] + write(15, 872415232, 764390477, 0); // [time: 350.001ns -> 360.001ns] + write(15, 872415232, 805776619, 0); // [time: 360.001ns -> 370.001ns] + write(15, 872415232, 1651314158, 0); // [time: 370.001ns -> 380.001ns] + reset(); // [time: 500.002ns -> 510.002ns] + reset(); // [time: 510.002ns -> 520.002ns] + reset(); // [time: 520.002ns -> 530.002ns] + write(15, 872415232, 3022929697, 0); // [time: 590.002ns -> 610.002ns] + write(15, 872415232, 4183272239, 0); // [time: 610.002ns -> 620.002ns] + write(15, 872415232, 315913722, 0); // [time: 620.002ns -> 630.002ns] + write(15, 872415232, 1054576031, 0); // [time: 630.002ns -> 640.002ns] + read(15, 872415232, 6, 0); // [time: 640.002ns -> 660.002ns] +} diff --git a/tests/antmicro/fifo_constant/expects/test_fifo_constant_5.bi.expect b/tests/antmicro/fifo_constant/expects/test_fifo_constant_5.bi.expect new file mode 100644 index 00000000..dcf480c0 --- /dev/null +++ b/tests/antmicro/fifo_constant/expects/test_fifo_constant_5.bi.expect @@ -0,0 +1,28 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 872415232, 1363247548, 0); // [time: 190ns -> 210ns] + read(15, 872415232, 2498712983, 0); // [time: 210ns -> 220ns] + read(15, 872415232, 2031470411, 0); // [time: 220ns -> 230ns] + read(15, 872415232, 247232753, 0); // [time: 230ns -> 240ns] + read(15, 872415232, 236574178, 0); // [time: 240ns -> 250ns] + reset(); // [time: 290.001ns -> 300.001ns] + reset(); // [time: 300.001ns -> 310.001ns] + reset(); // [time: 310.001ns -> 320.001ns] + write(15, 872415232, 421022298, 0); // [time: 360.001ns -> 380.001ns] + write(15, 872415232, 2203084718, 0); // [time: 380.001ns -> 390.001ns] + write(15, 872415232, 2308882986, 0); // [time: 390.001ns -> 400.001ns] + write(15, 872415232, 4235095479, 0); // [time: 400.001ns -> 410.001ns] + write(15, 872415232, 1180440750, 0); // [time: 410.001ns -> 420.001ns] + reset(); // [time: 560.002ns -> 570.002ns] + reset(); // [time: 570.002ns -> 580.002ns] + reset(); // [time: 580.002ns -> 590.002ns] + write(15, 872415232, 2313964829, 0); // [time: 650.002ns -> 670.002ns] + write(15, 872415232, 2950684687, 0); // [time: 670.002ns -> 680.002ns] + write(15, 872415232, 1632464407, 0); // [time: 680.002ns -> 690.002ns] + write(15, 872415232, 531222031, 0); // [time: 690.002ns -> 700.002ns] + write(15, 872415232, 2086209707, 0); // [time: 700.002ns -> 710.002ns] + read(15, 872415232, 6, 0); // [time: 710.002ns -> 730.002ns] +} diff --git a/tests/antmicro/fifo_constant/expects/test_fifo_constant_6.bi.expect b/tests/antmicro/fifo_constant/expects/test_fifo_constant_6.bi.expect new file mode 100644 index 00000000..d6aea314 --- /dev/null +++ b/tests/antmicro/fifo_constant/expects/test_fifo_constant_6.bi.expect @@ -0,0 +1,31 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 872415232, 1363247548, 0); // [time: 210ns -> 230ns] + read(15, 872415232, 2498712983, 0); // [time: 230ns -> 240ns] + read(15, 872415232, 2031470411, 0); // [time: 240ns -> 250ns] + read(15, 872415232, 247232753, 0); // [time: 250ns -> 260ns] + read(15, 872415232, 236574178, 0); // [time: 260ns -> 270ns] + read(15, 872415232, 421022298, 0); // [time: 270ns -> 280ns] + reset(); // [time: 320.001ns -> 330.001ns] + reset(); // [time: 330.001ns -> 340.001ns] + reset(); // [time: 340.001ns -> 350.001ns] + write(15, 872415232, 2203084718, 0); // [time: 390.001ns -> 410.001ns] + write(15, 872415232, 2308882986, 0); // [time: 410.001ns -> 420.001ns] + write(15, 872415232, 4235095479, 0); // [time: 420.001ns -> 430.001ns] + write(15, 872415232, 1180440750, 0); // [time: 430.001ns -> 440.001ns] + write(15, 872415232, 2313964829, 0); // [time: 440.001ns -> 450.001ns] + write(15, 872415232, 2950684687, 0); // [time: 450.001ns -> 460.001ns] + reset(); // [time: 620.002ns -> 630.002ns] + reset(); // [time: 630.002ns -> 640.002ns] + reset(); // [time: 640.002ns -> 650.002ns] + write(15, 872415232, 1632464407, 0); // [time: 710.002ns -> 730.002ns] + write(15, 872415232, 531222031, 0); // [time: 730.002ns -> 740.002ns] + write(15, 872415232, 2086209707, 0); // [time: 740.002ns -> 750.002ns] + write(15, 872415232, 3905452749, 0); // [time: 750.002ns -> 760.002ns] + write(15, 872415232, 1047759017, 0); // [time: 760.002ns -> 770.002ns] + write(15, 872415232, 1028960831, 0); // [time: 770.002ns -> 780.002ns] + read(15, 872415232, 6, 0); // [time: 780.002ns -> 800.002ns] +} diff --git a/tests/antmicro/fifo_constant/expects/test_fifo_constant_7.bi.expect b/tests/antmicro/fifo_constant/expects/test_fifo_constant_7.bi.expect new file mode 100644 index 00000000..247b5a2f --- /dev/null +++ b/tests/antmicro/fifo_constant/expects/test_fifo_constant_7.bi.expect @@ -0,0 +1,34 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 872415232, 1363247548, 0); // [time: 230ns -> 250ns] + read(15, 872415232, 2498712983, 0); // [time: 250ns -> 260ns] + read(15, 872415232, 2031470411, 0); // [time: 260ns -> 270ns] + read(15, 872415232, 247232753, 0); // [time: 270ns -> 280ns] + read(15, 872415232, 236574178, 0); // [time: 280ns -> 290ns] + read(15, 872415232, 421022298, 0); // [time: 290ns -> 300ns] + read(15, 872415232, 2203084718, 0); // [time: 300ns -> 310ns] + reset(); // [time: 350.001ns -> 360.001ns] + reset(); // [time: 360.001ns -> 370.001ns] + reset(); // [time: 370.001ns -> 380.001ns] + write(15, 872415232, 2308882986, 0); // [time: 420.001ns -> 440.001ns] + write(15, 872415232, 4235095479, 0); // [time: 440.001ns -> 450.001ns] + write(15, 872415232, 1180440750, 0); // [time: 450.001ns -> 460.001ns] + write(15, 872415232, 2313964829, 0); // [time: 460.001ns -> 470.001ns] + write(15, 872415232, 2950684687, 0); // [time: 470.001ns -> 480.001ns] + write(15, 872415232, 1632464407, 0); // [time: 480.001ns -> 490.001ns] + write(15, 872415232, 531222031, 0); // [time: 490.001ns -> 500.001ns] + reset(); // [time: 680.002ns -> 690.002ns] + reset(); // [time: 690.002ns -> 700.002ns] + reset(); // [time: 700.002ns -> 710.002ns] + write(15, 872415232, 2086209707, 0); // [time: 770.002ns -> 790.002ns] + write(15, 872415232, 3905452749, 0); // [time: 790.002ns -> 800.002ns] + write(15, 872415232, 1047759017, 0); // [time: 800.002ns -> 810.002ns] + write(15, 872415232, 1028960831, 0); // [time: 810.002ns -> 820.002ns] + write(15, 872415232, 3233599833, 0); // [time: 820.002ns -> 830.002ns] + write(15, 872415232, 1516004143, 0); // [time: 830.002ns -> 840.002ns] + write(15, 872415232, 619658659, 0); // [time: 840.002ns -> 850.002ns] + read(15, 872415232, 6, 0); // [time: 850.002ns -> 870.002ns] +} diff --git a/tests/antmicro/fifo_constant/expects/test_fifo_constant_8.bi.expect b/tests/antmicro/fifo_constant/expects/test_fifo_constant_8.bi.expect new file mode 100644 index 00000000..951423ae --- /dev/null +++ b/tests/antmicro/fifo_constant/expects/test_fifo_constant_8.bi.expect @@ -0,0 +1,37 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 872415232, 1363247548, 0); // [time: 250ns -> 270ns] + read(15, 872415232, 2498712983, 0); // [time: 270ns -> 280ns] + read(15, 872415232, 2031470411, 0); // [time: 280ns -> 290ns] + read(15, 872415232, 247232753, 0); // [time: 290ns -> 300ns] + read(15, 872415232, 236574178, 0); // [time: 300ns -> 310ns] + read(15, 872415232, 421022298, 0); // [time: 310ns -> 320ns] + read(15, 872415232, 2203084718, 0); // [time: 320ns -> 330ns] + read(15, 872415232, 2308882986, 0); // [time: 330ns -> 340ns] + reset(); // [time: 380.001ns -> 390.001ns] + reset(); // [time: 390.001ns -> 400.001ns] + reset(); // [time: 400.001ns -> 410.001ns] + write(15, 872415232, 4235095479, 0); // [time: 450.001ns -> 470.001ns] + write(15, 872415232, 1180440750, 0); // [time: 470.001ns -> 480.001ns] + write(15, 872415232, 2313964829, 0); // [time: 480.001ns -> 490.001ns] + write(15, 872415232, 2950684687, 0); // [time: 490.001ns -> 500.001ns] + write(15, 872415232, 1632464407, 0); // [time: 500.001ns -> 510.001ns] + write(15, 872415232, 531222031, 0); // [time: 510.001ns -> 520.001ns] + write(15, 872415232, 2086209707, 0); // [time: 520.001ns -> 530.001ns] + write(15, 872415232, 3905452749, 0); // [time: 530.001ns -> 540.001ns] + reset(); // [time: 740.002ns -> 750.002ns] + reset(); // [time: 750.002ns -> 760.002ns] + reset(); // [time: 760.002ns -> 770.002ns] + write(15, 872415232, 1047759017, 0); // [time: 830.002ns -> 850.002ns] + write(15, 872415232, 1028960831, 0); // [time: 850.002ns -> 860.002ns] + write(15, 872415232, 3233599833, 0); // [time: 860.002ns -> 870.002ns] + write(15, 872415232, 1516004143, 0); // [time: 870.002ns -> 880.002ns] + write(15, 872415232, 619658659, 0); // [time: 880.002ns -> 890.002ns] + write(15, 872415232, 1481414104, 0); // [time: 890.002ns -> 900.002ns] + write(15, 872415232, 2537393056, 0); // [time: 900.002ns -> 910.002ns] + write(15, 872415232, 3649566230, 0); // [time: 910.002ns -> 920.002ns] + read(15, 872415232, 6, 0); // [time: 920.002ns -> 940.002ns] +} diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_16_0.bi.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_16_0.bi.expect new file mode 100644 index 00000000..2f13eb1d --- /dev/null +++ b/tests/antmicro/sram_classic/expects/test_sram_classic_16_0.bi.expect @@ -0,0 +1,41 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108864, 3946442578, 0); // [time: 410ns -> 430ns] + read(15, 67108865, 2796792514, 0); // [time: 430ns -> 450ns] + read(15, 67108866, 3312914512, 0); // [time: 450ns -> 470ns] + read(15, 67108867, 4292142820, 0); // [time: 470ns -> 490ns] + read(15, 67108868, 3525794570, 0); // [time: 490ns -> 510ns] + read(15, 67108869, 2961047623, 0); // [time: 510ns -> 530ns] + read(15, 67108870, 4249856274, 0); // [time: 530ns -> 550ns] + read(15, 67108871, 3405678304, 0); // [time: 550ns -> 570ns] + read(15, 67108872, 2415042617, 0); // [time: 570ns -> 590ns] + read(15, 67108873, 3311552087, 0); // [time: 590ns -> 610ns] + read(15, 67108874, 3211316809, 0); // [time: 610ns -> 630ns] + read(15, 67108875, 3236997651, 0); // [time: 630ns -> 650ns] + read(15, 67108876, 3369414426, 0); // [time: 650ns -> 670ns] + read(15, 67108877, 3866725828, 0); // [time: 670ns -> 690ns] + read(15, 67108878, 2882616058, 0); // [time: 690ns -> 710ns] + read(15, 67108879, 3738458232, 0); // [time: 710ns -> 730ns] + reset(); // [time: 770.001ns -> 780.001ns] + reset(); // [time: 780.001ns -> 790.001ns] + reset(); // [time: 790.001ns -> 800.001ns] + write(15, 67108864, 2558870979, 0); // [time: 840.001ns -> 860.001ns] + write(15, 67108865, 3310254824, 0); // [time: 860.001ns -> 880.001ns] + write(15, 67108866, 3635210891, 0); // [time: 880.001ns -> 900.001ns] + write(15, 67108867, 2844952514, 0); // [time: 900.001ns -> 920.001ns] + write(15, 67108868, 2293386100, 0); // [time: 920.001ns -> 940.001ns] + write(15, 67108869, 3615462605, 0); // [time: 940.001ns -> 960.001ns] + write(15, 67108870, 3569010089, 0); // [time: 960.001ns -> 980.001ns] + write(15, 67108871, 3520072258, 0); // [time: 980.001ns -> 1000.001ns] + write(15, 67108872, 3002516588, 0); // [time: 1000.001ns -> 1020.001ns] + write(15, 67108873, 3681389096, 0); // [time: 1020.001ns -> 1040.001ns] + write(15, 67108874, 2924663556, 0); // [time: 1040.001ns -> 1060.001ns] + write(15, 67108875, 3055297102, 0); // [time: 1060.001ns -> 1080.001ns] + write(15, 67108876, 4177639544, 0); // [time: 1080.001ns -> 1100.001ns] + write(15, 67108877, 3526172361, 0); // [time: 1100.001ns -> 1120.001ns] + write(15, 67108878, 2564412332, 0); // [time: 1120.001ns -> 1140.001ns] + write(15, 67108879, 4210875098, 0); // [time: 1140.001ns -> 1160.001ns] +} diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_16_12.bi.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_16_12.bi.expect new file mode 100644 index 00000000..318d95b0 --- /dev/null +++ b/tests/antmicro/sram_classic/expects/test_sram_classic_16_12.bi.expect @@ -0,0 +1,41 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108867, 3622568730, 0); // [time: 410ns -> 430ns] + read(15, 67108868, 3538707329, 0); // [time: 430ns -> 450ns] + read(15, 67108869, 3440721235, 0); // [time: 450ns -> 470ns] + read(15, 67108870, 3191204602, 0); // [time: 470ns -> 490ns] + read(15, 67108871, 4084986393, 0); // [time: 490ns -> 510ns] + read(15, 67108872, 3446247256, 0); // [time: 510ns -> 530ns] + read(15, 67108873, 3908428032, 0); // [time: 530ns -> 550ns] + read(15, 67108874, 2315046581, 0); // [time: 550ns -> 570ns] + read(15, 67108875, 2780682871, 0); // [time: 570ns -> 590ns] + read(15, 67108876, 3026674647, 0); // [time: 590ns -> 610ns] + read(15, 67108877, 2376933607, 0); // [time: 610ns -> 630ns] + read(15, 67108878, 2436105964, 0); // [time: 630ns -> 650ns] + read(15, 67108879, 3222378968, 0); // [time: 650ns -> 670ns] + read(15, 67108880, 3310323703, 0); // [time: 670ns -> 690ns] + read(15, 67108881, 2550879638, 0); // [time: 690ns -> 710ns] + read(15, 67108882, 3261802111, 0); // [time: 710ns -> 730ns] + reset(); // [time: 770.001ns -> 780.001ns] + reset(); // [time: 780.001ns -> 790.001ns] + reset(); // [time: 790.001ns -> 800.001ns] + write(15, 67108867, 2711682730, 0); // [time: 840.001ns -> 860.001ns] + write(15, 67108868, 4230444125, 0); // [time: 860.001ns -> 880.001ns] + write(15, 67108869, 2579425060, 0); // [time: 880.001ns -> 900.001ns] + write(15, 67108870, 2991027419, 0); // [time: 900.001ns -> 920.001ns] + write(15, 67108871, 2417255467, 0); // [time: 920.001ns -> 940.001ns] + write(15, 67108872, 4045742383, 0); // [time: 940.001ns -> 960.001ns] + write(15, 67108873, 2931778361, 0); // [time: 960.001ns -> 980.001ns] + write(15, 67108874, 3640821048, 0); // [time: 980.001ns -> 1000.001ns] + write(15, 67108875, 3663784812, 0); // [time: 1000.001ns -> 1020.001ns] + write(15, 67108876, 3627233541, 0); // [time: 1020.001ns -> 1040.001ns] + write(15, 67108877, 2459429013, 0); // [time: 1040.001ns -> 1060.001ns] + write(15, 67108878, 4213999775, 0); // [time: 1060.001ns -> 1080.001ns] + write(15, 67108879, 2215241682, 0); // [time: 1080.001ns -> 1100.001ns] + write(15, 67108880, 3801611658, 0); // [time: 1100.001ns -> 1120.001ns] + write(15, 67108881, 2471241936, 0); // [time: 1120.001ns -> 1140.001ns] + write(15, 67108882, 2691314341, 0); // [time: 1140.001ns -> 1160.001ns] +} diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_16_4.bi.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_16_4.bi.expect new file mode 100644 index 00000000..97bca31d --- /dev/null +++ b/tests/antmicro/sram_classic/expects/test_sram_classic_16_4.bi.expect @@ -0,0 +1,41 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108865, 3946442578, 0); // [time: 410ns -> 430ns] + read(15, 67108866, 2796792514, 0); // [time: 430ns -> 450ns] + read(15, 67108867, 3312914512, 0); // [time: 450ns -> 470ns] + read(15, 67108868, 4292142820, 0); // [time: 470ns -> 490ns] + read(15, 67108869, 3525794570, 0); // [time: 490ns -> 510ns] + read(15, 67108870, 2961047623, 0); // [time: 510ns -> 530ns] + read(15, 67108871, 4249856274, 0); // [time: 530ns -> 550ns] + read(15, 67108872, 3405678304, 0); // [time: 550ns -> 570ns] + read(15, 67108873, 2415042617, 0); // [time: 570ns -> 590ns] + read(15, 67108874, 3311552087, 0); // [time: 590ns -> 610ns] + read(15, 67108875, 3211316809, 0); // [time: 610ns -> 630ns] + read(15, 67108876, 3236997651, 0); // [time: 630ns -> 650ns] + read(15, 67108877, 3369414426, 0); // [time: 650ns -> 670ns] + read(15, 67108878, 3866725828, 0); // [time: 670ns -> 690ns] + read(15, 67108879, 2882616058, 0); // [time: 690ns -> 710ns] + read(15, 67108880, 3738458232, 0); // [time: 710ns -> 730ns] + reset(); // [time: 770.001ns -> 780.001ns] + reset(); // [time: 780.001ns -> 790.001ns] + reset(); // [time: 790.001ns -> 800.001ns] + write(15, 67108865, 2558870979, 0); // [time: 840.001ns -> 860.001ns] + write(15, 67108866, 3310254824, 0); // [time: 860.001ns -> 880.001ns] + write(15, 67108867, 3635210891, 0); // [time: 880.001ns -> 900.001ns] + write(15, 67108868, 2844952514, 0); // [time: 900.001ns -> 920.001ns] + write(15, 67108869, 2293386100, 0); // [time: 920.001ns -> 940.001ns] + write(15, 67108870, 3615462605, 0); // [time: 940.001ns -> 960.001ns] + write(15, 67108871, 3569010089, 0); // [time: 960.001ns -> 980.001ns] + write(15, 67108872, 3520072258, 0); // [time: 980.001ns -> 1000.001ns] + write(15, 67108873, 3002516588, 0); // [time: 1000.001ns -> 1020.001ns] + write(15, 67108874, 3681389096, 0); // [time: 1020.001ns -> 1040.001ns] + write(15, 67108875, 2924663556, 0); // [time: 1040.001ns -> 1060.001ns] + write(15, 67108876, 3055297102, 0); // [time: 1060.001ns -> 1080.001ns] + write(15, 67108877, 4177639544, 0); // [time: 1080.001ns -> 1100.001ns] + write(15, 67108878, 3526172361, 0); // [time: 1100.001ns -> 1120.001ns] + write(15, 67108879, 2564412332, 0); // [time: 1120.001ns -> 1140.001ns] + write(15, 67108880, 4210875098, 0); // [time: 1140.001ns -> 1160.001ns] +} diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_16_8.bi.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_16_8.bi.expect new file mode 100644 index 00000000..cb71ef95 --- /dev/null +++ b/tests/antmicro/sram_classic/expects/test_sram_classic_16_8.bi.expect @@ -0,0 +1,41 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108866, 3622568730, 0); // [time: 410ns -> 430ns] + read(15, 67108867, 3538707329, 0); // [time: 430ns -> 450ns] + read(15, 67108868, 3440721235, 0); // [time: 450ns -> 470ns] + read(15, 67108869, 3191204602, 0); // [time: 470ns -> 490ns] + read(15, 67108870, 4084986393, 0); // [time: 490ns -> 510ns] + read(15, 67108871, 3446247256, 0); // [time: 510ns -> 530ns] + read(15, 67108872, 3908428032, 0); // [time: 530ns -> 550ns] + read(15, 67108873, 2315046581, 0); // [time: 550ns -> 570ns] + read(15, 67108874, 2780682871, 0); // [time: 570ns -> 590ns] + read(15, 67108875, 3026674647, 0); // [time: 590ns -> 610ns] + read(15, 67108876, 2376933607, 0); // [time: 610ns -> 630ns] + read(15, 67108877, 2436105964, 0); // [time: 630ns -> 650ns] + read(15, 67108878, 3222378968, 0); // [time: 650ns -> 670ns] + read(15, 67108879, 3310323703, 0); // [time: 670ns -> 690ns] + read(15, 67108880, 2550879638, 0); // [time: 690ns -> 710ns] + read(15, 67108881, 3261802111, 0); // [time: 710ns -> 730ns] + reset(); // [time: 770.001ns -> 780.001ns] + reset(); // [time: 780.001ns -> 790.001ns] + reset(); // [time: 790.001ns -> 800.001ns] + write(15, 67108866, 2711682730, 0); // [time: 840.001ns -> 860.001ns] + write(15, 67108867, 4230444125, 0); // [time: 860.001ns -> 880.001ns] + write(15, 67108868, 2579425060, 0); // [time: 880.001ns -> 900.001ns] + write(15, 67108869, 2991027419, 0); // [time: 900.001ns -> 920.001ns] + write(15, 67108870, 2417255467, 0); // [time: 920.001ns -> 940.001ns] + write(15, 67108871, 4045742383, 0); // [time: 940.001ns -> 960.001ns] + write(15, 67108872, 2931778361, 0); // [time: 960.001ns -> 980.001ns] + write(15, 67108873, 3640821048, 0); // [time: 980.001ns -> 1000.001ns] + write(15, 67108874, 3663784812, 0); // [time: 1000.001ns -> 1020.001ns] + write(15, 67108875, 3627233541, 0); // [time: 1020.001ns -> 1040.001ns] + write(15, 67108876, 2459429013, 0); // [time: 1040.001ns -> 1060.001ns] + write(15, 67108877, 4213999775, 0); // [time: 1060.001ns -> 1080.001ns] + write(15, 67108878, 2215241682, 0); // [time: 1080.001ns -> 1100.001ns] + write(15, 67108879, 3801611658, 0); // [time: 1100.001ns -> 1120.001ns] + write(15, 67108880, 2471241936, 0); // [time: 1120.001ns -> 1140.001ns] + write(15, 67108881, 2691314341, 0); // [time: 1140.001ns -> 1160.001ns] +} diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_1_0.bi.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_1_0.bi.expect new file mode 100644 index 00000000..5eaf9412 --- /dev/null +++ b/tests/antmicro/sram_classic/expects/test_sram_classic_1_0.bi.expect @@ -0,0 +1,11 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108864, 2993300090, 0); // [time: 110ns -> 130ns] + reset(); // [time: 170.001ns -> 180.001ns] + reset(); // [time: 180.001ns -> 190.001ns] + reset(); // [time: 190.001ns -> 200.001ns] + write(15, 67108864, 3921107982, 0); // [time: 240.001ns -> 260.001ns] +} diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_1_12.bi.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_1_12.bi.expect new file mode 100644 index 00000000..d429b3d6 --- /dev/null +++ b/tests/antmicro/sram_classic/expects/test_sram_classic_1_12.bi.expect @@ -0,0 +1,11 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108867, 3946442578, 0); // [time: 110ns -> 130ns] + reset(); // [time: 170.001ns -> 180.001ns] + reset(); // [time: 180.001ns -> 190.001ns] + reset(); // [time: 190.001ns -> 200.001ns] + write(15, 67108867, 2796792514, 0); // [time: 240.001ns -> 260.001ns] +} diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_1_4.bi.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_1_4.bi.expect new file mode 100644 index 00000000..a626949a --- /dev/null +++ b/tests/antmicro/sram_classic/expects/test_sram_classic_1_4.bi.expect @@ -0,0 +1,11 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108865, 2993300090, 0); // [time: 110ns -> 130ns] + reset(); // [time: 170.001ns -> 180.001ns] + reset(); // [time: 180.001ns -> 190.001ns] + reset(); // [time: 190.001ns -> 200.001ns] + write(15, 67108865, 3921107982, 0); // [time: 240.001ns -> 260.001ns] +} diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_1_8.bi.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_1_8.bi.expect new file mode 100644 index 00000000..c1285b74 --- /dev/null +++ b/tests/antmicro/sram_classic/expects/test_sram_classic_1_8.bi.expect @@ -0,0 +1,11 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108866, 3946442578, 0); // [time: 110ns -> 130ns] + reset(); // [time: 170.001ns -> 180.001ns] + reset(); // [time: 180.001ns -> 190.001ns] + reset(); // [time: 190.001ns -> 200.001ns] + write(15, 67108866, 2796792514, 0); // [time: 240.001ns -> 260.001ns] +} diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_2_0.bi.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_2_0.bi.expect new file mode 100644 index 00000000..de5ee088 --- /dev/null +++ b/tests/antmicro/sram_classic/expects/test_sram_classic_2_0.bi.expect @@ -0,0 +1,13 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108864, 3622568730, 0); // [time: 130ns -> 150ns] + read(15, 67108865, 3538707329, 0); // [time: 150ns -> 170ns] + reset(); // [time: 210.001ns -> 220.001ns] + reset(); // [time: 220.001ns -> 230.001ns] + reset(); // [time: 230.001ns -> 240.001ns] + write(15, 67108864, 3440721235, 0); // [time: 280.001ns -> 300.001ns] + write(15, 67108865, 3191204602, 0); // [time: 300.001ns -> 320.001ns] +} diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_2_12.bi.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_2_12.bi.expect new file mode 100644 index 00000000..3871f1f8 --- /dev/null +++ b/tests/antmicro/sram_classic/expects/test_sram_classic_2_12.bi.expect @@ -0,0 +1,13 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108867, 2993300090, 0); // [time: 130ns -> 150ns] + read(15, 67108868, 3921107982, 0); // [time: 150ns -> 170ns] + reset(); // [time: 210.001ns -> 220.001ns] + reset(); // [time: 220.001ns -> 230.001ns] + reset(); // [time: 230.001ns -> 240.001ns] + write(15, 67108867, 2480359279, 0); // [time: 280.001ns -> 300.001ns] + write(15, 67108868, 3789792143, 0); // [time: 300.001ns -> 320.001ns] +} diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_2_4.bi.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_2_4.bi.expect new file mode 100644 index 00000000..1a5c670e --- /dev/null +++ b/tests/antmicro/sram_classic/expects/test_sram_classic_2_4.bi.expect @@ -0,0 +1,13 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108865, 3622568730, 0); // [time: 130ns -> 150ns] + read(15, 67108866, 3538707329, 0); // [time: 150ns -> 170ns] + reset(); // [time: 210.001ns -> 220.001ns] + reset(); // [time: 220.001ns -> 230.001ns] + reset(); // [time: 230.001ns -> 240.001ns] + write(15, 67108865, 3440721235, 0); // [time: 280.001ns -> 300.001ns] + write(15, 67108866, 3191204602, 0); // [time: 300.001ns -> 320.001ns] +} diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_2_8.bi.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_2_8.bi.expect new file mode 100644 index 00000000..17d7651a --- /dev/null +++ b/tests/antmicro/sram_classic/expects/test_sram_classic_2_8.bi.expect @@ -0,0 +1,13 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108866, 3250481594, 0); // [time: 130ns -> 150ns] + read(15, 67108867, 2390763695, 0); // [time: 150ns -> 170ns] + reset(); // [time: 210.001ns -> 220.001ns] + reset(); // [time: 220.001ns -> 230.001ns] + reset(); // [time: 230.001ns -> 240.001ns] + write(15, 67108866, 4197550477, 0); // [time: 280.001ns -> 300.001ns] + write(15, 67108867, 2445792994, 0); // [time: 300.001ns -> 320.001ns] +} diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_4_0.bi.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_4_0.bi.expect new file mode 100644 index 00000000..5ad819ac --- /dev/null +++ b/tests/antmicro/sram_classic/expects/test_sram_classic_4_0.bi.expect @@ -0,0 +1,17 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108864, 2993300090, 0); // [time: 170ns -> 190ns] + read(15, 67108865, 3921107982, 0); // [time: 190ns -> 210ns] + read(15, 67108866, 2480359279, 0); // [time: 210ns -> 230ns] + read(15, 67108867, 3789792143, 0); // [time: 230ns -> 250ns] + reset(); // [time: 290.001ns -> 300.001ns] + reset(); // [time: 300.001ns -> 310.001ns] + reset(); // [time: 310.001ns -> 320.001ns] + write(15, 67108864, 2250616272, 0); // [time: 360.001ns -> 380.001ns] + write(15, 67108865, 3654263702, 0); // [time: 380.001ns -> 400.001ns] + write(15, 67108866, 2773364137, 0); // [time: 400.001ns -> 420.001ns] + write(15, 67108867, 2521253772, 0); // [time: 420.001ns -> 440.001ns] +} diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_4_12.bi.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_4_12.bi.expect new file mode 100644 index 00000000..961f4bc4 --- /dev/null +++ b/tests/antmicro/sram_classic/expects/test_sram_classic_4_12.bi.expect @@ -0,0 +1,17 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108867, 3622568730, 0); // [time: 170ns -> 190ns] + read(15, 67108868, 3538707329, 0); // [time: 190ns -> 210ns] + read(15, 67108869, 3440721235, 0); // [time: 210ns -> 230ns] + read(15, 67108870, 3191204602, 0); // [time: 230ns -> 250ns] + reset(); // [time: 290.001ns -> 300.001ns] + reset(); // [time: 300.001ns -> 310.001ns] + reset(); // [time: 310.001ns -> 320.001ns] + write(15, 67108867, 4084986393, 0); // [time: 360.001ns -> 380.001ns] + write(15, 67108868, 3446247256, 0); // [time: 380.001ns -> 400.001ns] + write(15, 67108869, 3908428032, 0); // [time: 400.001ns -> 420.001ns] + write(15, 67108870, 2315046581, 0); // [time: 420.001ns -> 440.001ns] +} diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_4_4.bi.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_4_4.bi.expect new file mode 100644 index 00000000..e1428e90 --- /dev/null +++ b/tests/antmicro/sram_classic/expects/test_sram_classic_4_4.bi.expect @@ -0,0 +1,17 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108865, 3946442578, 0); // [time: 170ns -> 190ns] + read(15, 67108866, 2796792514, 0); // [time: 190ns -> 210ns] + read(15, 67108867, 3312914512, 0); // [time: 210ns -> 230ns] + read(15, 67108868, 4292142820, 0); // [time: 230ns -> 250ns] + reset(); // [time: 290.001ns -> 300.001ns] + reset(); // [time: 300.001ns -> 310.001ns] + reset(); // [time: 310.001ns -> 320.001ns] + write(15, 67108865, 3525794570, 0); // [time: 360.001ns -> 380.001ns] + write(15, 67108866, 2961047623, 0); // [time: 380.001ns -> 400.001ns] + write(15, 67108867, 4249856274, 0); // [time: 400.001ns -> 420.001ns] + write(15, 67108868, 3405678304, 0); // [time: 420.001ns -> 440.001ns] +} diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_4_8.bi.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_4_8.bi.expect new file mode 100644 index 00000000..01877415 --- /dev/null +++ b/tests/antmicro/sram_classic/expects/test_sram_classic_4_8.bi.expect @@ -0,0 +1,17 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108866, 3946442578, 0); // [time: 170ns -> 190ns] + read(15, 67108867, 2796792514, 0); // [time: 190ns -> 210ns] + read(15, 67108868, 3312914512, 0); // [time: 210ns -> 230ns] + read(15, 67108869, 4292142820, 0); // [time: 230ns -> 250ns] + reset(); // [time: 290.001ns -> 300.001ns] + reset(); // [time: 300.001ns -> 310.001ns] + reset(); // [time: 310.001ns -> 320.001ns] + write(15, 67108866, 3525794570, 0); // [time: 360.001ns -> 380.001ns] + write(15, 67108867, 2961047623, 0); // [time: 380.001ns -> 400.001ns] + write(15, 67108868, 4249856274, 0); // [time: 400.001ns -> 420.001ns] + write(15, 67108869, 3405678304, 0); // [time: 420.001ns -> 440.001ns] +} diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_8_0.bi.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_8_0.bi.expect new file mode 100644 index 00000000..36649517 --- /dev/null +++ b/tests/antmicro/sram_classic/expects/test_sram_classic_8_0.bi.expect @@ -0,0 +1,25 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108864, 3622568730, 0); // [time: 250ns -> 270ns] + read(15, 67108865, 3538707329, 0); // [time: 270ns -> 290ns] + read(15, 67108866, 3440721235, 0); // [time: 290ns -> 310ns] + read(15, 67108867, 3191204602, 0); // [time: 310ns -> 330ns] + read(15, 67108868, 4084986393, 0); // [time: 330ns -> 350ns] + read(15, 67108869, 3446247256, 0); // [time: 350ns -> 370ns] + read(15, 67108870, 3908428032, 0); // [time: 370ns -> 390ns] + read(15, 67108871, 2315046581, 0); // [time: 390ns -> 410ns] + reset(); // [time: 450.001ns -> 460.001ns] + reset(); // [time: 460.001ns -> 470.001ns] + reset(); // [time: 470.001ns -> 480.001ns] + write(15, 67108864, 2780682871, 0); // [time: 520.001ns -> 540.001ns] + write(15, 67108865, 3026674647, 0); // [time: 540.001ns -> 560.001ns] + write(15, 67108866, 2376933607, 0); // [time: 560.001ns -> 580.001ns] + write(15, 67108867, 2436105964, 0); // [time: 580.001ns -> 600.001ns] + write(15, 67108868, 3222378968, 0); // [time: 600.001ns -> 620.001ns] + write(15, 67108869, 3310323703, 0); // [time: 620.001ns -> 640.001ns] + write(15, 67108870, 2550879638, 0); // [time: 640.001ns -> 660.001ns] + write(15, 67108871, 3261802111, 0); // [time: 660.001ns -> 680.001ns] +} diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_8_12.bi.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_8_12.bi.expect new file mode 100644 index 00000000..b7f411ee --- /dev/null +++ b/tests/antmicro/sram_classic/expects/test_sram_classic_8_12.bi.expect @@ -0,0 +1,25 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108867, 2993300090, 0); // [time: 250ns -> 270ns] + read(15, 67108868, 3921107982, 0); // [time: 270ns -> 290ns] + read(15, 67108869, 2480359279, 0); // [time: 290ns -> 310ns] + read(15, 67108870, 3789792143, 0); // [time: 310ns -> 330ns] + read(15, 67108871, 2250616272, 0); // [time: 330ns -> 350ns] + read(15, 67108872, 3654263702, 0); // [time: 350ns -> 370ns] + read(15, 67108873, 2773364137, 0); // [time: 370ns -> 390ns] + read(15, 67108874, 2521253772, 0); // [time: 390ns -> 410ns] + reset(); // [time: 450.001ns -> 460.001ns] + reset(); // [time: 460.001ns -> 470.001ns] + reset(); // [time: 470.001ns -> 480.001ns] + write(15, 67108867, 2521411224, 0); // [time: 520.001ns -> 540.001ns] + write(15, 67108868, 2219799945, 0); // [time: 540.001ns -> 560.001ns] + write(15, 67108869, 3487354134, 0); // [time: 560.001ns -> 580.001ns] + write(15, 67108870, 2235755512, 0); // [time: 580.001ns -> 600.001ns] + write(15, 67108871, 2319980602, 0); // [time: 600.001ns -> 620.001ns] + write(15, 67108872, 2978178103, 0); // [time: 620.001ns -> 640.001ns] + write(15, 67108873, 2464653045, 0); // [time: 640.001ns -> 660.001ns] + write(15, 67108874, 2202449462, 0); // [time: 660.001ns -> 680.001ns] +} diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_8_4.bi.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_8_4.bi.expect new file mode 100644 index 00000000..9e2e1b4f --- /dev/null +++ b/tests/antmicro/sram_classic/expects/test_sram_classic_8_4.bi.expect @@ -0,0 +1,25 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108865, 3250481594, 0); // [time: 250ns -> 270ns] + read(15, 67108866, 2390763695, 0); // [time: 270ns -> 290ns] + read(15, 67108867, 4197550477, 0); // [time: 290ns -> 310ns] + read(15, 67108868, 2445792994, 0); // [time: 310ns -> 330ns] + read(15, 67108869, 3897454712, 0); // [time: 330ns -> 350ns] + read(15, 67108870, 3326339601, 0); // [time: 350ns -> 370ns] + read(15, 67108871, 3190747046, 0); // [time: 370ns -> 390ns] + read(15, 67108872, 2329522371, 0); // [time: 390ns -> 410ns] + reset(); // [time: 450.001ns -> 460.001ns] + reset(); // [time: 460.001ns -> 470.001ns] + reset(); // [time: 470.001ns -> 480.001ns] + write(15, 67108865, 2252821017, 0); // [time: 520.001ns -> 540.001ns] + write(15, 67108866, 2931126915, 0); // [time: 540.001ns -> 560.001ns] + write(15, 67108867, 2608883160, 0); // [time: 560.001ns -> 580.001ns] + write(15, 67108868, 4233362437, 0); // [time: 580.001ns -> 600.001ns] + write(15, 67108869, 2517580333, 0); // [time: 600.001ns -> 620.001ns] + write(15, 67108870, 2583768976, 0); // [time: 620.001ns -> 640.001ns] + write(15, 67108871, 2451763371, 0); // [time: 640.001ns -> 660.001ns] + write(15, 67108872, 2672364833, 0); // [time: 660.001ns -> 680.001ns] +} diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_8_8.bi.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_8_8.bi.expect new file mode 100644 index 00000000..1347d8fd --- /dev/null +++ b/tests/antmicro/sram_classic/expects/test_sram_classic_8_8.bi.expect @@ -0,0 +1,25 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108866, 2993300090, 0); // [time: 250ns -> 270ns] + read(15, 67108867, 3921107982, 0); // [time: 270ns -> 290ns] + read(15, 67108868, 2480359279, 0); // [time: 290ns -> 310ns] + read(15, 67108869, 3789792143, 0); // [time: 310ns -> 330ns] + read(15, 67108870, 2250616272, 0); // [time: 330ns -> 350ns] + read(15, 67108871, 3654263702, 0); // [time: 350ns -> 370ns] + read(15, 67108872, 2773364137, 0); // [time: 370ns -> 390ns] + read(15, 67108873, 2521253772, 0); // [time: 390ns -> 410ns] + reset(); // [time: 450.001ns -> 460.001ns] + reset(); // [time: 460.001ns -> 470.001ns] + reset(); // [time: 470.001ns -> 480.001ns] + write(15, 67108866, 2521411224, 0); // [time: 520.001ns -> 540.001ns] + write(15, 67108867, 2219799945, 0); // [time: 540.001ns -> 560.001ns] + write(15, 67108868, 3487354134, 0); // [time: 560.001ns -> 580.001ns] + write(15, 67108869, 2235755512, 0); // [time: 580.001ns -> 600.001ns] + write(15, 67108870, 2319980602, 0); // [time: 600.001ns -> 620.001ns] + write(15, 67108871, 2978178103, 0); // [time: 620.001ns -> 640.001ns] + write(15, 67108872, 2464653045, 0); // [time: 640.001ns -> 660.001ns] + write(15, 67108873, 2202449462, 0); // [time: 660.001ns -> 680.001ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_0_0.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_0_0.bi.expect new file mode 100644 index 00000000..d079ea48 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_0_0.bi.expect @@ -0,0 +1,61 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108864, 1016512136, 0); // [time: 410ns -> 430ns] + read(15, 67108865, 226204128, 0); // [time: 430ns -> 440ns] + read(15, 67108866, 2116565440, 0); // [time: 440ns -> 450ns] + read(15, 67108867, 2153688786, 0); // [time: 450ns -> 460ns] + read(15, 67108868, 1974223269, 0); // [time: 460ns -> 470ns] + read(15, 67108869, 1053640572, 0); // [time: 470ns -> 480ns] + read(15, 67108870, 2079860600, 0); // [time: 480ns -> 490ns] + read(15, 67108871, 3550045624, 0); // [time: 490ns -> 500ns] + read(15, 67108872, 1038322047, 0); // [time: 500ns -> 510ns] + read(15, 67108873, 1502718053, 0); // [time: 510ns -> 520ns] + read(15, 67108874, 1367070343, 0); // [time: 520ns -> 530ns] + read(15, 67108875, 3425882885, 0); // [time: 530ns -> 540ns] + read(15, 67108876, 1614916721, 0); // [time: 540ns -> 550ns] + read(15, 67108877, 3041346437, 0); // [time: 550ns -> 560ns] + read(15, 67108878, 3665993952, 0); // [time: 560ns -> 570ns] + read(15, 67108879, 3560581876, 0); // [time: 570ns -> 580ns] + reset(); // [time: 620.001ns -> 630.001ns] + reset(); // [time: 630.001ns -> 640.001ns] + reset(); // [time: 640.001ns -> 650.001ns] + write(15, 67108864, 3433786972, 0); // [time: 690.001ns -> 710.001ns] + write(15, 67108865, 3840560806, 0); // [time: 710.001ns -> 720.001ns] + write(15, 67108866, 3225552468, 0); // [time: 720.001ns -> 730.001ns] + write(15, 67108867, 3717810263, 0); // [time: 730.001ns -> 740.001ns] + write(15, 67108868, 3317657198, 0); // [time: 740.001ns -> 750.001ns] + write(15, 67108869, 1024069544, 0); // [time: 750.001ns -> 760.001ns] + write(15, 67108870, 1752245362, 0); // [time: 760.001ns -> 770.001ns] + write(15, 67108871, 1579776374, 0); // [time: 770.001ns -> 780.001ns] + write(15, 67108872, 904253205, 0); // [time: 780.001ns -> 790.001ns] + write(15, 67108873, 1728285430, 0); // [time: 790.001ns -> 800.001ns] + write(15, 67108874, 91066718, 0); // [time: 800.001ns -> 810.001ns] + write(15, 67108875, 1402442819, 0); // [time: 810.001ns -> 820.001ns] + write(15, 67108876, 4062122226, 0); // [time: 820.001ns -> 830.001ns] + write(15, 67108877, 1191921998, 0); // [time: 830.001ns -> 840.001ns] + write(15, 67108878, 1249541889, 0); // [time: 840.001ns -> 850.001ns] + write(15, 67108879, 2580891116, 0); // [time: 850.001ns -> 860.001ns] + reset(); // [time: 1540.002ns -> 1550.002ns] + reset(); // [time: 1550.002ns -> 1560.002ns] + reset(); // [time: 1560.002ns -> 1570.002ns] + write(15, 67108864, 1526706340, 0); // [time: 1610.002ns -> 1630.002ns] + write(15, 67108865, 1162262173, 0); // [time: 1630.002ns -> 1640.002ns] + write(15, 67108866, 3667501502, 0); // [time: 1640.002ns -> 1650.002ns] + write(15, 67108867, 617255735, 0); // [time: 1650.002ns -> 1660.002ns] + write(15, 67108868, 4077356414, 0); // [time: 1660.002ns -> 1670.002ns] + write(15, 67108869, 1593609662, 0); // [time: 1670.002ns -> 1680.002ns] + write(15, 67108870, 2148292499, 0); // [time: 1680.002ns -> 1690.002ns] + write(15, 67108871, 3403556849, 0); // [time: 1690.002ns -> 1700.002ns] + write(15, 67108872, 3331963440, 0); // [time: 1700.002ns -> 1710.002ns] + write(15, 67108873, 1493302995, 0); // [time: 1710.002ns -> 1720.002ns] + write(15, 67108874, 2710958922, 0); // [time: 1720.002ns -> 1730.002ns] + write(15, 67108875, 4029972623, 0); // [time: 1730.002ns -> 1740.002ns] + write(15, 67108876, 2845272388, 0); // [time: 1740.002ns -> 1750.002ns] + write(15, 67108877, 70166840, 0); // [time: 1750.002ns -> 1760.002ns] + write(15, 67108878, 1323291936, 0); // [time: 1760.002ns -> 1770.002ns] + write(15, 67108879, 916783944, 0); // [time: 1770.002ns -> 1780.002ns] + read(15, 67108864, 1526706340, 0); // [time: 1780.002ns -> 1800.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_0_1.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_0_1.bi.expect new file mode 100644 index 00000000..fcc2c6dc --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_0_1.bi.expect @@ -0,0 +1,61 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108864, 518534189, 0); // [time: 410ns -> 430ns] + read(15, 67108865, 844695266, 0); // [time: 430ns -> 440ns] + read(15, 67108866, 3937184150, 0); // [time: 440ns -> 450ns] + read(15, 67108867, 444246851, 0); // [time: 450ns -> 460ns] + read(15, 67108868, 3220682802, 0); // [time: 460ns -> 470ns] + read(15, 67108869, 2130811954, 0); // [time: 470ns -> 480ns] + read(15, 67108870, 2002127438, 0); // [time: 480ns -> 490ns] + read(15, 67108871, 493792053, 0); // [time: 490ns -> 500ns] + read(15, 67108872, 63714206, 0); // [time: 500ns -> 510ns] + read(15, 67108873, 2091823691, 0); // [time: 510ns -> 520ns] + read(15, 67108874, 3903276977, 0); // [time: 520ns -> 530ns] + read(15, 67108875, 1662756337, 0); // [time: 530ns -> 540ns] + read(15, 67108876, 4101310419, 0); // [time: 540ns -> 550ns] + read(15, 67108877, 903798156, 0); // [time: 550ns -> 560ns] + read(15, 67108878, 3840476340, 0); // [time: 560ns -> 570ns] + read(15, 67108879, 2244097975, 0); // [time: 570ns -> 580ns] + reset(); // [time: 620.001ns -> 630.001ns] + reset(); // [time: 630.001ns -> 640.001ns] + reset(); // [time: 640.001ns -> 650.001ns] + write(15, 67108864, 3956643922, 0); // [time: 690.001ns -> 710.001ns] + write(15, 67108865, 2115347845, 0); // [time: 710.001ns -> 720.001ns] + write(15, 67108866, 1775201107, 0); // [time: 720.001ns -> 730.001ns] + write(15, 67108867, 1046910518, 0); // [time: 730.001ns -> 740.001ns] + write(15, 67108868, 345998276, 0); // [time: 740.001ns -> 750.001ns] + write(15, 67108869, 2089777588, 0); // [time: 750.001ns -> 760.001ns] + write(15, 67108870, 3110941387, 0); // [time: 760.001ns -> 770.001ns] + write(15, 67108871, 3151493219, 0); // [time: 770.001ns -> 780.001ns] + write(15, 67108872, 1789821109, 0); // [time: 780.001ns -> 790.001ns] + write(15, 67108873, 976504712, 0); // [time: 790.001ns -> 800.001ns] + write(15, 67108874, 3716648277, 0); // [time: 800.001ns -> 810.001ns] + write(15, 67108875, 3764578858, 0); // [time: 810.001ns -> 820.001ns] + write(15, 67108876, 2575976733, 0); // [time: 820.001ns -> 830.001ns] + write(15, 67108877, 2758477517, 0); // [time: 830.001ns -> 840.001ns] + write(15, 67108878, 801284123, 0); // [time: 840.001ns -> 850.001ns] + write(15, 67108879, 1745171602, 0); // [time: 850.001ns -> 860.001ns] + reset(); // [time: 1540.002ns -> 1550.002ns] + reset(); // [time: 1550.002ns -> 1560.002ns] + reset(); // [time: 1560.002ns -> 1570.002ns] + write(15, 67108864, 2836493204, 0); // [time: 1610.002ns -> 1630.002ns] + write(15, 67108865, 3265525290, 0); // [time: 1630.002ns -> 1640.002ns] + write(15, 67108866, 2395253012, 0); // [time: 1640.002ns -> 1650.002ns] + write(15, 67108867, 3557189713, 0); // [time: 1650.002ns -> 1660.002ns] + write(15, 67108868, 764605320, 0); // [time: 1660.002ns -> 1670.002ns] + write(15, 67108869, 2679315363, 0); // [time: 1670.002ns -> 1680.002ns] + write(15, 67108870, 375184876, 0); // [time: 1680.002ns -> 1690.002ns] + write(15, 67108871, 4121117117, 0); // [time: 1690.002ns -> 1700.002ns] + write(15, 67108872, 1446110016, 0); // [time: 1700.002ns -> 1710.002ns] + write(15, 67108873, 3729875561, 0); // [time: 1710.002ns -> 1720.002ns] + write(15, 67108874, 2582294219, 0); // [time: 1720.002ns -> 1730.002ns] + write(15, 67108875, 409432939, 0); // [time: 1730.002ns -> 1740.002ns] + write(15, 67108876, 937977575, 0); // [time: 1740.002ns -> 1750.002ns] + write(15, 67108877, 1981138244, 0); // [time: 1750.002ns -> 1760.002ns] + write(15, 67108878, 2912031569, 0); // [time: 1760.002ns -> 1770.002ns] + write(15, 67108879, 896776296, 0); // [time: 1770.002ns -> 1780.002ns] + read(15, 67108864, 2836493204, 0); // [time: 1780.002ns -> 1800.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_0_2.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_0_2.bi.expect new file mode 100644 index 00000000..6f08eae7 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_0_2.bi.expect @@ -0,0 +1,61 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108864, 3495738447, 0); // [time: 410ns -> 430ns] + read(15, 67108865, 1478546475, 0); // [time: 430ns -> 440ns] + read(15, 67108866, 2041778918, 0); // [time: 440ns -> 450ns] + read(15, 67108867, 3032895213, 0); // [time: 450ns -> 460ns] + read(15, 67108868, 2020268309, 0); // [time: 460ns -> 470ns] + read(15, 67108869, 3122719830, 0); // [time: 470ns -> 480ns] + read(15, 67108870, 3806053567, 0); // [time: 480ns -> 490ns] + read(15, 67108871, 3858565026, 0); // [time: 490ns -> 500ns] + read(15, 67108872, 880624971, 0); // [time: 500ns -> 510ns] + read(15, 67108873, 2554056607, 0); // [time: 510ns -> 520ns] + read(15, 67108874, 1441832696, 0); // [time: 520ns -> 530ns] + read(15, 67108875, 479445740, 0); // [time: 530ns -> 540ns] + read(15, 67108876, 2229265910, 0); // [time: 540ns -> 550ns] + read(15, 67108877, 788973880, 0); // [time: 550ns -> 560ns] + read(15, 67108878, 3880977277, 0); // [time: 560ns -> 570ns] + read(15, 67108879, 4096708504, 0); // [time: 570ns -> 580ns] + reset(); // [time: 620.001ns -> 630.001ns] + reset(); // [time: 630.001ns -> 640.001ns] + reset(); // [time: 640.001ns -> 650.001ns] + write(15, 67108864, 2427636421, 0); // [time: 690.001ns -> 710.001ns] + write(15, 67108865, 3595099675, 0); // [time: 710.001ns -> 720.001ns] + write(15, 67108866, 2668681316, 0); // [time: 720.001ns -> 730.001ns] + write(15, 67108867, 1679837987, 0); // [time: 730.001ns -> 740.001ns] + write(15, 67108868, 924732013, 0); // [time: 740.001ns -> 750.001ns] + write(15, 67108869, 2192079403, 0); // [time: 750.001ns -> 760.001ns] + write(15, 67108870, 2042051660, 0); // [time: 760.001ns -> 770.001ns] + write(15, 67108871, 989927686, 0); // [time: 770.001ns -> 780.001ns] + write(15, 67108872, 3067406900, 0); // [time: 780.001ns -> 790.001ns] + write(15, 67108873, 1058215073, 0); // [time: 790.001ns -> 800.001ns] + write(15, 67108874, 365012335, 0); // [time: 800.001ns -> 810.001ns] + write(15, 67108875, 687295108, 0); // [time: 810.001ns -> 820.001ns] + write(15, 67108876, 2829218573, 0); // [time: 820.001ns -> 830.001ns] + write(15, 67108877, 1448409262, 0); // [time: 830.001ns -> 840.001ns] + write(15, 67108878, 400594486, 0); // [time: 840.001ns -> 850.001ns] + write(15, 67108879, 4177343116, 0); // [time: 850.001ns -> 860.001ns] + reset(); // [time: 1540.002ns -> 1550.002ns] + reset(); // [time: 1550.002ns -> 1560.002ns] + reset(); // [time: 1560.002ns -> 1570.002ns] + write(15, 67108864, 2304668716, 0); // [time: 1610.002ns -> 1630.002ns] + write(15, 67108865, 2610611482, 0); // [time: 1630.002ns -> 1640.002ns] + write(15, 67108866, 1468153982, 0); // [time: 1640.002ns -> 1650.002ns] + write(15, 67108867, 1169841342, 0); // [time: 1650.002ns -> 1660.002ns] + write(15, 67108868, 27036823, 0); // [time: 1660.002ns -> 1670.002ns] + write(15, 67108869, 73783758, 0); // [time: 1670.002ns -> 1680.002ns] + write(15, 67108870, 1621524717, 0); // [time: 1680.002ns -> 1690.002ns] + write(15, 67108871, 3905946412, 0); // [time: 1690.002ns -> 1700.002ns] + write(15, 67108872, 1563100034, 0); // [time: 1700.002ns -> 1710.002ns] + write(15, 67108873, 2069336907, 0); // [time: 1710.002ns -> 1720.002ns] + write(15, 67108874, 583373053, 0); // [time: 1720.002ns -> 1730.002ns] + write(15, 67108875, 3629920426, 0); // [time: 1730.002ns -> 1740.002ns] + write(15, 67108876, 2146122704, 0); // [time: 1740.002ns -> 1750.002ns] + write(15, 67108877, 2674258699, 0); // [time: 1750.002ns -> 1760.002ns] + write(15, 67108878, 1361676606, 0); // [time: 1760.002ns -> 1770.002ns] + write(15, 67108879, 2435452493, 0); // [time: 1770.002ns -> 1780.002ns] + read(15, 67108864, 2304668716, 0); // [time: 1780.002ns -> 1800.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_0_3.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_0_3.bi.expect new file mode 100644 index 00000000..d1d6d833 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_0_3.bi.expect @@ -0,0 +1,61 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108864, 1070372987, 0); // [time: 410ns -> 430ns] + read(15, 67108865, 2645947069, 0); // [time: 430ns -> 440ns] + read(15, 67108866, 736643984, 0); // [time: 440ns -> 450ns] + read(15, 67108867, 192007203, 0); // [time: 450ns -> 460ns] + read(15, 67108868, 1925400290, 0); // [time: 460ns -> 470ns] + read(15, 67108869, 1309609983, 0); // [time: 470ns -> 480ns] + read(15, 67108870, 58503546, 0); // [time: 480ns -> 490ns] + read(15, 67108871, 3861022989, 0); // [time: 490ns -> 500ns] + read(15, 67108872, 1725708128, 0); // [time: 500ns -> 510ns] + read(15, 67108873, 3760744365, 0); // [time: 510ns -> 520ns] + read(15, 67108874, 3803789590, 0); // [time: 520ns -> 530ns] + read(15, 67108875, 2647121574, 0); // [time: 530ns -> 540ns] + read(15, 67108876, 336117328, 0); // [time: 540ns -> 550ns] + read(15, 67108877, 3984726565, 0); // [time: 550ns -> 560ns] + read(15, 67108878, 104808193, 0); // [time: 560ns -> 570ns] + read(15, 67108879, 2315494688, 0); // [time: 570ns -> 580ns] + reset(); // [time: 620.001ns -> 630.001ns] + reset(); // [time: 630.001ns -> 640.001ns] + reset(); // [time: 640.001ns -> 650.001ns] + write(15, 67108864, 3997204021, 0); // [time: 690.001ns -> 710.001ns] + write(15, 67108865, 666660673, 0); // [time: 710.001ns -> 720.001ns] + write(15, 67108866, 3910223084, 0); // [time: 720.001ns -> 730.001ns] + write(15, 67108867, 1271405124, 0); // [time: 730.001ns -> 740.001ns] + write(15, 67108868, 4236388983, 0); // [time: 740.001ns -> 750.001ns] + write(15, 67108869, 1347016890, 0); // [time: 750.001ns -> 760.001ns] + write(15, 67108870, 1337396640, 0); // [time: 760.001ns -> 770.001ns] + write(15, 67108871, 3009712000, 0); // [time: 770.001ns -> 780.001ns] + write(15, 67108872, 2237248361, 0); // [time: 780.001ns -> 790.001ns] + write(15, 67108873, 592560133, 0); // [time: 790.001ns -> 800.001ns] + write(15, 67108874, 371018497, 0); // [time: 800.001ns -> 810.001ns] + write(15, 67108875, 763875626, 0); // [time: 810.001ns -> 820.001ns] + write(15, 67108876, 75174504, 0); // [time: 820.001ns -> 830.001ns] + write(15, 67108877, 2983449782, 0); // [time: 830.001ns -> 840.001ns] + write(15, 67108878, 2295155532, 0); // [time: 840.001ns -> 850.001ns] + write(15, 67108879, 1954643484, 0); // [time: 850.001ns -> 860.001ns] + reset(); // [time: 1540.002ns -> 1550.002ns] + reset(); // [time: 1550.002ns -> 1560.002ns] + reset(); // [time: 1560.002ns -> 1570.002ns] + write(15, 67108864, 409090773, 0); // [time: 1610.002ns -> 1630.002ns] + write(15, 67108865, 1348706589, 0); // [time: 1630.002ns -> 1640.002ns] + write(15, 67108866, 1967918440, 0); // [time: 1640.002ns -> 1650.002ns] + write(15, 67108867, 2636141882, 0); // [time: 1650.002ns -> 1660.002ns] + write(15, 67108868, 533777194, 0); // [time: 1660.002ns -> 1670.002ns] + write(15, 67108869, 2114809607, 0); // [time: 1670.002ns -> 1680.002ns] + write(15, 67108870, 309856382, 0); // [time: 1680.002ns -> 1690.002ns] + write(15, 67108871, 3466848916, 0); // [time: 1690.002ns -> 1700.002ns] + write(15, 67108872, 3043756153, 0); // [time: 1700.002ns -> 1710.002ns] + write(15, 67108873, 2927281001, 0); // [time: 1710.002ns -> 1720.002ns] + write(15, 67108874, 1913699666, 0); // [time: 1720.002ns -> 1730.002ns] + write(15, 67108875, 1847871828, 0); // [time: 1730.002ns -> 1740.002ns] + write(15, 67108876, 3984372107, 0); // [time: 1740.002ns -> 1750.002ns] + write(15, 67108877, 4239907193, 0); // [time: 1750.002ns -> 1760.002ns] + write(15, 67108878, 1427511912, 0); // [time: 1760.002ns -> 1770.002ns] + write(15, 67108879, 277973300, 0); // [time: 1770.002ns -> 1780.002ns] + read(15, 67108864, 409090773, 0); // [time: 1780.002ns -> 1800.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_12_0.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_12_0.bi.expect new file mode 100644 index 00000000..abbf3eb6 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_12_0.bi.expect @@ -0,0 +1,61 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108867, 1833423740, 0); // [time: 410ns -> 430ns] + read(15, 67108868, 4073618608, 0); // [time: 430ns -> 440ns] + read(15, 67108869, 3418745219, 0); // [time: 440ns -> 450ns] + read(15, 67108870, 3757272308, 0); // [time: 450ns -> 460ns] + read(15, 67108871, 1325530178, 0); // [time: 460ns -> 470ns] + read(15, 67108872, 1451722922, 0); // [time: 470ns -> 480ns] + read(15, 67108873, 1997677454, 0); // [time: 480ns -> 490ns] + read(15, 67108874, 986005841, 0); // [time: 490ns -> 500ns] + read(15, 67108875, 789975088, 0); // [time: 500ns -> 510ns] + read(15, 67108876, 3746918692, 0); // [time: 510ns -> 520ns] + read(15, 67108877, 410224063, 0); // [time: 520ns -> 530ns] + read(15, 67108878, 864118294, 0); // [time: 530ns -> 540ns] + read(15, 67108879, 908783806, 0); // [time: 540ns -> 550ns] + read(15, 67108880, 2735695332, 0); // [time: 550ns -> 560ns] + read(15, 67108881, 3991830963, 0); // [time: 560ns -> 570ns] + read(15, 67108882, 3613974492, 0); // [time: 570ns -> 580ns] + reset(); // [time: 620.001ns -> 630.001ns] + reset(); // [time: 630.001ns -> 640.001ns] + reset(); // [time: 640.001ns -> 650.001ns] + write(15, 67108867, 1515921225, 0); // [time: 690.001ns -> 710.001ns] + write(15, 67108868, 104974629, 0); // [time: 710.001ns -> 720.001ns] + write(15, 67108869, 966302149, 0); // [time: 720.001ns -> 730.001ns] + write(15, 67108870, 4157870389, 0); // [time: 730.001ns -> 740.001ns] + write(15, 67108871, 2924407148, 0); // [time: 740.001ns -> 750.001ns] + write(15, 67108872, 1538378206, 0); // [time: 750.001ns -> 760.001ns] + write(15, 67108873, 60846013, 0); // [time: 760.001ns -> 770.001ns] + write(15, 67108874, 3809194079, 0); // [time: 770.001ns -> 780.001ns] + write(15, 67108875, 4127502511, 0); // [time: 780.001ns -> 790.001ns] + write(15, 67108876, 4180959758, 0); // [time: 790.001ns -> 800.001ns] + write(15, 67108877, 700566626, 0); // [time: 800.001ns -> 810.001ns] + write(15, 67108878, 2700144653, 0); // [time: 810.001ns -> 820.001ns] + write(15, 67108879, 3999062826, 0); // [time: 820.001ns -> 830.001ns] + write(15, 67108880, 3986108609, 0); // [time: 830.001ns -> 840.001ns] + write(15, 67108881, 447162407, 0); // [time: 840.001ns -> 850.001ns] + write(15, 67108882, 3816483315, 0); // [time: 850.001ns -> 860.001ns] + reset(); // [time: 1540.002ns -> 1550.002ns] + reset(); // [time: 1550.002ns -> 1560.002ns] + reset(); // [time: 1560.002ns -> 1570.002ns] + write(15, 67108867, 1264302217, 0); // [time: 1610.002ns -> 1630.002ns] + write(15, 67108868, 420700447, 0); // [time: 1630.002ns -> 1640.002ns] + write(15, 67108869, 353328025, 0); // [time: 1640.002ns -> 1650.002ns] + write(15, 67108870, 2517418204, 0); // [time: 1650.002ns -> 1660.002ns] + write(15, 67108871, 1410989455, 0); // [time: 1660.002ns -> 1670.002ns] + write(15, 67108872, 2070630692, 0); // [time: 1670.002ns -> 1680.002ns] + write(15, 67108873, 1509701018, 0); // [time: 1680.002ns -> 1690.002ns] + write(15, 67108874, 2805925831, 0); // [time: 1690.002ns -> 1700.002ns] + write(15, 67108875, 1828261736, 0); // [time: 1700.002ns -> 1710.002ns] + write(15, 67108876, 865271992, 0); // [time: 1710.002ns -> 1720.002ns] + write(15, 67108877, 3589189654, 0); // [time: 1720.002ns -> 1730.002ns] + write(15, 67108878, 2111939367, 0); // [time: 1730.002ns -> 1740.002ns] + write(15, 67108879, 4179134294, 0); // [time: 1740.002ns -> 1750.002ns] + write(15, 67108880, 1634099931, 0); // [time: 1750.002ns -> 1760.002ns] + write(15, 67108881, 4072299277, 0); // [time: 1760.002ns -> 1770.002ns] + write(15, 67108882, 1017567246, 0); // [time: 1770.002ns -> 1780.002ns] + read(15, 67108867, 1264302217, 0); // [time: 1780.002ns -> 1800.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_12_1.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_12_1.bi.expect new file mode 100644 index 00000000..e1164b5a --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_12_1.bi.expect @@ -0,0 +1,61 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108867, 3580256271, 0); // [time: 410ns -> 430ns] + read(15, 67108864, 1489666683, 0); // [time: 430ns -> 440ns] + read(15, 67108865, 3677074643, 0); // [time: 440ns -> 450ns] + read(15, 67108866, 1878953054, 0); // [time: 450ns -> 460ns] + read(15, 67108871, 2965505115, 0); // [time: 460ns -> 470ns] + read(15, 67108868, 3259566096, 0); // [time: 470ns -> 480ns] + read(15, 67108869, 1262153110, 0); // [time: 480ns -> 490ns] + read(15, 67108870, 2451703670, 0); // [time: 490ns -> 500ns] + read(15, 67108875, 3104341711, 0); // [time: 500ns -> 510ns] + read(15, 67108872, 964066815, 0); // [time: 510ns -> 520ns] + read(15, 67108873, 3328791441, 0); // [time: 520ns -> 530ns] + read(15, 67108874, 3489570824, 0); // [time: 530ns -> 540ns] + read(15, 67108879, 4241788620, 0); // [time: 540ns -> 550ns] + read(15, 67108876, 3583058104, 0); // [time: 550ns -> 560ns] + read(15, 67108877, 1005667378, 0); // [time: 560ns -> 570ns] + read(15, 67108878, 209419171, 0); // [time: 570ns -> 580ns] + reset(); // [time: 620.001ns -> 630.001ns] + reset(); // [time: 630.001ns -> 640.001ns] + reset(); // [time: 640.001ns -> 650.001ns] + write(15, 67108867, 1000382631, 0); // [time: 690.001ns -> 710.001ns] + write(15, 67108864, 1285425234, 0); // [time: 710.001ns -> 720.001ns] + write(15, 67108865, 318606993, 0); // [time: 720.001ns -> 730.001ns] + write(15, 67108866, 2625467664, 0); // [time: 730.001ns -> 740.001ns] + write(15, 67108871, 229964357, 0); // [time: 740.001ns -> 750.001ns] + write(15, 67108868, 3036014706, 0); // [time: 750.001ns -> 760.001ns] + write(15, 67108869, 1528299378, 0); // [time: 760.001ns -> 770.001ns] + write(15, 67108870, 2182965409, 0); // [time: 770.001ns -> 780.001ns] + write(15, 67108875, 3673940705, 0); // [time: 780.001ns -> 790.001ns] + write(15, 67108872, 2347881481, 0); // [time: 790.001ns -> 800.001ns] + write(15, 67108873, 2145987888, 0); // [time: 800.001ns -> 810.001ns] + write(15, 67108874, 2056885632, 0); // [time: 810.001ns -> 820.001ns] + write(15, 67108879, 3873405704, 0); // [time: 820.001ns -> 830.001ns] + write(15, 67108876, 188298896, 0); // [time: 830.001ns -> 840.001ns] + write(15, 67108877, 3827439034, 0); // [time: 840.001ns -> 850.001ns] + write(15, 67108878, 2726944699, 0); // [time: 850.001ns -> 860.001ns] + reset(); // [time: 1540.002ns -> 1550.002ns] + reset(); // [time: 1550.002ns -> 1560.002ns] + reset(); // [time: 1560.002ns -> 1570.002ns] + write(15, 67108867, 3833002895, 0); // [time: 1610.002ns -> 1630.002ns] + write(15, 67108864, 1414948600, 0); // [time: 1630.002ns -> 1640.002ns] + write(15, 67108865, 1931556247, 0); // [time: 1640.002ns -> 1650.002ns] + write(15, 67108866, 2036215835, 0); // [time: 1650.002ns -> 1660.002ns] + write(15, 67108871, 2213185472, 0); // [time: 1660.002ns -> 1670.002ns] + write(15, 67108868, 2227456846, 0); // [time: 1670.002ns -> 1680.002ns] + write(15, 67108869, 2213473648, 0); // [time: 1680.002ns -> 1690.002ns] + write(15, 67108870, 1116257432, 0); // [time: 1690.002ns -> 1700.002ns] + write(15, 67108875, 609949692, 0); // [time: 1700.002ns -> 1710.002ns] + write(15, 67108872, 493401018, 0); // [time: 1710.002ns -> 1720.002ns] + write(15, 67108873, 1721387478, 0); // [time: 1720.002ns -> 1730.002ns] + write(15, 67108874, 1431279294, 0); // [time: 1730.002ns -> 1740.002ns] + write(15, 67108879, 716225428, 0); // [time: 1740.002ns -> 1750.002ns] + write(15, 67108876, 2446670843, 0); // [time: 1750.002ns -> 1760.002ns] + write(15, 67108877, 1494143953, 0); // [time: 1760.002ns -> 1770.002ns] + write(15, 67108878, 1325582129, 0); // [time: 1770.002ns -> 1780.002ns] + read(15, 67108867, 3833002895, 0); // [time: 1780.002ns -> 1800.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_12_2.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_12_2.bi.expect new file mode 100644 index 00000000..7fee1f29 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_12_2.bi.expect @@ -0,0 +1,61 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108867, 3495738447, 0); // [time: 410ns -> 430ns] + read(15, 67108868, 1478546475, 0); // [time: 430ns -> 440ns] + read(15, 67108869, 2041778918, 0); // [time: 440ns -> 450ns] + read(15, 67108870, 3032895213, 0); // [time: 450ns -> 460ns] + read(15, 67108871, 2020268309, 0); // [time: 460ns -> 470ns] + read(15, 67108864, 3122719830, 0); // [time: 470ns -> 480ns] + read(15, 67108865, 3806053567, 0); // [time: 480ns -> 490ns] + read(15, 67108866, 3858565026, 0); // [time: 490ns -> 500ns] + read(15, 67108875, 880624971, 0); // [time: 500ns -> 510ns] + read(15, 67108876, 2554056607, 0); // [time: 510ns -> 520ns] + read(15, 67108877, 1441832696, 0); // [time: 520ns -> 530ns] + read(15, 67108878, 479445740, 0); // [time: 530ns -> 540ns] + read(15, 67108879, 2229265910, 0); // [time: 540ns -> 550ns] + read(15, 67108872, 788973880, 0); // [time: 550ns -> 560ns] + read(15, 67108873, 3880977277, 0); // [time: 560ns -> 570ns] + read(15, 67108874, 4096708504, 0); // [time: 570ns -> 580ns] + reset(); // [time: 620.001ns -> 630.001ns] + reset(); // [time: 630.001ns -> 640.001ns] + reset(); // [time: 640.001ns -> 650.001ns] + write(15, 67108867, 2427636421, 0); // [time: 690.001ns -> 710.001ns] + write(15, 67108868, 3595099675, 0); // [time: 710.001ns -> 720.001ns] + write(15, 67108869, 2668681316, 0); // [time: 720.001ns -> 730.001ns] + write(15, 67108870, 1679837987, 0); // [time: 730.001ns -> 740.001ns] + write(15, 67108871, 924732013, 0); // [time: 740.001ns -> 750.001ns] + write(15, 67108864, 2192079403, 0); // [time: 750.001ns -> 760.001ns] + write(15, 67108865, 2042051660, 0); // [time: 760.001ns -> 770.001ns] + write(15, 67108866, 989927686, 0); // [time: 770.001ns -> 780.001ns] + write(15, 67108875, 3067406900, 0); // [time: 780.001ns -> 790.001ns] + write(15, 67108876, 1058215073, 0); // [time: 790.001ns -> 800.001ns] + write(15, 67108877, 365012335, 0); // [time: 800.001ns -> 810.001ns] + write(15, 67108878, 687295108, 0); // [time: 810.001ns -> 820.001ns] + write(15, 67108879, 2829218573, 0); // [time: 820.001ns -> 830.001ns] + write(15, 67108872, 1448409262, 0); // [time: 830.001ns -> 840.001ns] + write(15, 67108873, 400594486, 0); // [time: 840.001ns -> 850.001ns] + write(15, 67108874, 4177343116, 0); // [time: 850.001ns -> 860.001ns] + reset(); // [time: 1540.002ns -> 1550.002ns] + reset(); // [time: 1550.002ns -> 1560.002ns] + reset(); // [time: 1560.002ns -> 1570.002ns] + write(15, 67108867, 2304668716, 0); // [time: 1610.002ns -> 1630.002ns] + write(15, 67108868, 2610611482, 0); // [time: 1630.002ns -> 1640.002ns] + write(15, 67108869, 1468153982, 0); // [time: 1640.002ns -> 1650.002ns] + write(15, 67108870, 1169841342, 0); // [time: 1650.002ns -> 1660.002ns] + write(15, 67108871, 27036823, 0); // [time: 1660.002ns -> 1670.002ns] + write(15, 67108864, 73783758, 0); // [time: 1670.002ns -> 1680.002ns] + write(15, 67108865, 1621524717, 0); // [time: 1680.002ns -> 1690.002ns] + write(15, 67108866, 3905946412, 0); // [time: 1690.002ns -> 1700.002ns] + write(15, 67108875, 1563100034, 0); // [time: 1700.002ns -> 1710.002ns] + write(15, 67108876, 2069336907, 0); // [time: 1710.002ns -> 1720.002ns] + write(15, 67108877, 583373053, 0); // [time: 1720.002ns -> 1730.002ns] + write(15, 67108878, 3629920426, 0); // [time: 1730.002ns -> 1740.002ns] + write(15, 67108879, 2146122704, 0); // [time: 1740.002ns -> 1750.002ns] + write(15, 67108872, 2674258699, 0); // [time: 1750.002ns -> 1760.002ns] + write(15, 67108873, 1361676606, 0); // [time: 1760.002ns -> 1770.002ns] + write(15, 67108874, 2435452493, 0); // [time: 1770.002ns -> 1780.002ns] + read(15, 67108867, 2304668716, 0); // [time: 1780.002ns -> 1800.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_12_3.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_12_3.bi.expect new file mode 100644 index 00000000..b68e5c47 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_12_3.bi.expect @@ -0,0 +1,61 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108867, 2727164243, 0); // [time: 410ns -> 430ns] + read(15, 67108868, 1384255697, 0); // [time: 430ns -> 440ns] + read(15, 67108869, 4216231340, 0); // [time: 440ns -> 450ns] + read(15, 67108870, 1661993927, 0); // [time: 450ns -> 460ns] + read(15, 67108871, 159950269, 0); // [time: 460ns -> 470ns] + read(15, 67108872, 893905490, 0); // [time: 470ns -> 480ns] + read(15, 67108873, 1464841894, 0); // [time: 480ns -> 490ns] + read(15, 67108874, 710545966, 0); // [time: 490ns -> 500ns] + read(15, 67108875, 3482423916, 0); // [time: 500ns -> 510ns] + read(15, 67108876, 4068629318, 0); // [time: 510ns -> 520ns] + read(15, 67108877, 3266524719, 0); // [time: 520ns -> 530ns] + read(15, 67108878, 1808083576, 0); // [time: 530ns -> 540ns] + read(15, 67108879, 3562161795, 0); // [time: 540ns -> 550ns] + read(15, 67108864, 2984675510, 0); // [time: 550ns -> 560ns] + read(15, 67108865, 2475539812, 0); // [time: 560ns -> 570ns] + read(15, 67108866, 2138191023, 0); // [time: 570ns -> 580ns] + reset(); // [time: 620.001ns -> 630.001ns] + reset(); // [time: 630.001ns -> 640.001ns] + reset(); // [time: 640.001ns -> 650.001ns] + write(15, 67108867, 1599974119, 0); // [time: 690.001ns -> 710.001ns] + write(15, 67108868, 609858284, 0); // [time: 710.001ns -> 720.001ns] + write(15, 67108869, 1648881400, 0); // [time: 720.001ns -> 730.001ns] + write(15, 67108870, 572149112, 0); // [time: 730.001ns -> 740.001ns] + write(15, 67108871, 602124761, 0); // [time: 740.001ns -> 750.001ns] + write(15, 67108872, 3299652692, 0); // [time: 750.001ns -> 760.001ns] + write(15, 67108873, 1416165996, 0); // [time: 760.001ns -> 770.001ns] + write(15, 67108874, 1639735531, 0); // [time: 770.001ns -> 780.001ns] + write(15, 67108875, 941900856, 0); // [time: 780.001ns -> 790.001ns] + write(15, 67108876, 4103564658, 0); // [time: 790.001ns -> 800.001ns] + write(15, 67108877, 788749736, 0); // [time: 800.001ns -> 810.001ns] + write(15, 67108878, 1260615071, 0); // [time: 810.001ns -> 820.001ns] + write(15, 67108879, 2210117974, 0); // [time: 820.001ns -> 830.001ns] + write(15, 67108864, 2952803435, 0); // [time: 830.001ns -> 840.001ns] + write(15, 67108865, 441673600, 0); // [time: 840.001ns -> 850.001ns] + write(15, 67108866, 2137709866, 0); // [time: 850.001ns -> 860.001ns] + reset(); // [time: 1540.002ns -> 1550.002ns] + reset(); // [time: 1550.002ns -> 1560.002ns] + reset(); // [time: 1560.002ns -> 1570.002ns] + write(15, 67108867, 2898868374, 0); // [time: 1610.002ns -> 1630.002ns] + write(15, 67108868, 1922764675, 0); // [time: 1630.002ns -> 1640.002ns] + write(15, 67108869, 4256406750, 0); // [time: 1640.002ns -> 1650.002ns] + write(15, 67108870, 245447329, 0); // [time: 1650.002ns -> 1660.002ns] + write(15, 67108871, 3225897750, 0); // [time: 1660.002ns -> 1670.002ns] + write(15, 67108872, 1779082048, 0); // [time: 1670.002ns -> 1680.002ns] + write(15, 67108873, 1953003128, 0); // [time: 1680.002ns -> 1690.002ns] + write(15, 67108874, 4020445238, 0); // [time: 1690.002ns -> 1700.002ns] + write(15, 67108875, 2174587331, 0); // [time: 1700.002ns -> 1710.002ns] + write(15, 67108876, 1632125876, 0); // [time: 1710.002ns -> 1720.002ns] + write(15, 67108877, 340410721, 0); // [time: 1720.002ns -> 1730.002ns] + write(15, 67108878, 771941360, 0); // [time: 1730.002ns -> 1740.002ns] + write(15, 67108879, 2567244845, 0); // [time: 1740.002ns -> 1750.002ns] + write(15, 67108864, 899887853, 0); // [time: 1750.002ns -> 1760.002ns] + write(15, 67108865, 1674678715, 0); // [time: 1760.002ns -> 1770.002ns] + write(15, 67108866, 902429492, 0); // [time: 1770.002ns -> 1780.002ns] + read(15, 67108867, 2898868374, 0); // [time: 1780.002ns -> 1800.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_4_0.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_4_0.bi.expect new file mode 100644 index 00000000..a60d8398 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_4_0.bi.expect @@ -0,0 +1,61 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108865, 1016512136, 0); // [time: 410ns -> 430ns] + read(15, 67108866, 226204128, 0); // [time: 430ns -> 440ns] + read(15, 67108867, 2116565440, 0); // [time: 440ns -> 450ns] + read(15, 67108868, 2153688786, 0); // [time: 450ns -> 460ns] + read(15, 67108869, 1974223269, 0); // [time: 460ns -> 470ns] + read(15, 67108870, 1053640572, 0); // [time: 470ns -> 480ns] + read(15, 67108871, 2079860600, 0); // [time: 480ns -> 490ns] + read(15, 67108872, 3550045624, 0); // [time: 490ns -> 500ns] + read(15, 67108873, 1038322047, 0); // [time: 500ns -> 510ns] + read(15, 67108874, 1502718053, 0); // [time: 510ns -> 520ns] + read(15, 67108875, 1367070343, 0); // [time: 520ns -> 530ns] + read(15, 67108876, 3425882885, 0); // [time: 530ns -> 540ns] + read(15, 67108877, 1614916721, 0); // [time: 540ns -> 550ns] + read(15, 67108878, 3041346437, 0); // [time: 550ns -> 560ns] + read(15, 67108879, 3665993952, 0); // [time: 560ns -> 570ns] + read(15, 67108880, 3560581876, 0); // [time: 570ns -> 580ns] + reset(); // [time: 620.001ns -> 630.001ns] + reset(); // [time: 630.001ns -> 640.001ns] + reset(); // [time: 640.001ns -> 650.001ns] + write(15, 67108865, 3433786972, 0); // [time: 690.001ns -> 710.001ns] + write(15, 67108866, 3840560806, 0); // [time: 710.001ns -> 720.001ns] + write(15, 67108867, 3225552468, 0); // [time: 720.001ns -> 730.001ns] + write(15, 67108868, 3717810263, 0); // [time: 730.001ns -> 740.001ns] + write(15, 67108869, 3317657198, 0); // [time: 740.001ns -> 750.001ns] + write(15, 67108870, 1024069544, 0); // [time: 750.001ns -> 760.001ns] + write(15, 67108871, 1752245362, 0); // [time: 760.001ns -> 770.001ns] + write(15, 67108872, 1579776374, 0); // [time: 770.001ns -> 780.001ns] + write(15, 67108873, 904253205, 0); // [time: 780.001ns -> 790.001ns] + write(15, 67108874, 1728285430, 0); // [time: 790.001ns -> 800.001ns] + write(15, 67108875, 91066718, 0); // [time: 800.001ns -> 810.001ns] + write(15, 67108876, 1402442819, 0); // [time: 810.001ns -> 820.001ns] + write(15, 67108877, 4062122226, 0); // [time: 820.001ns -> 830.001ns] + write(15, 67108878, 1191921998, 0); // [time: 830.001ns -> 840.001ns] + write(15, 67108879, 1249541889, 0); // [time: 840.001ns -> 850.001ns] + write(15, 67108880, 2580891116, 0); // [time: 850.001ns -> 860.001ns] + reset(); // [time: 1540.002ns -> 1550.002ns] + reset(); // [time: 1550.002ns -> 1560.002ns] + reset(); // [time: 1560.002ns -> 1570.002ns] + write(15, 67108865, 1526706340, 0); // [time: 1610.002ns -> 1630.002ns] + write(15, 67108866, 1162262173, 0); // [time: 1630.002ns -> 1640.002ns] + write(15, 67108867, 3667501502, 0); // [time: 1640.002ns -> 1650.002ns] + write(15, 67108868, 617255735, 0); // [time: 1650.002ns -> 1660.002ns] + write(15, 67108869, 4077356414, 0); // [time: 1660.002ns -> 1670.002ns] + write(15, 67108870, 1593609662, 0); // [time: 1670.002ns -> 1680.002ns] + write(15, 67108871, 2148292499, 0); // [time: 1680.002ns -> 1690.002ns] + write(15, 67108872, 3403556849, 0); // [time: 1690.002ns -> 1700.002ns] + write(15, 67108873, 3331963440, 0); // [time: 1700.002ns -> 1710.002ns] + write(15, 67108874, 1493302995, 0); // [time: 1710.002ns -> 1720.002ns] + write(15, 67108875, 2710958922, 0); // [time: 1720.002ns -> 1730.002ns] + write(15, 67108876, 4029972623, 0); // [time: 1730.002ns -> 1740.002ns] + write(15, 67108877, 2845272388, 0); // [time: 1740.002ns -> 1750.002ns] + write(15, 67108878, 70166840, 0); // [time: 1750.002ns -> 1760.002ns] + write(15, 67108879, 1323291936, 0); // [time: 1760.002ns -> 1770.002ns] + write(15, 67108880, 916783944, 0); // [time: 1770.002ns -> 1780.002ns] + read(15, 67108865, 1526706340, 0); // [time: 1780.002ns -> 1800.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_4_1.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_4_1.bi.expect new file mode 100644 index 00000000..8662cb21 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_4_1.bi.expect @@ -0,0 +1,61 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108865, 2821946881, 0); // [time: 410ns -> 430ns] + read(15, 67108866, 4080087070, 0); // [time: 430ns -> 440ns] + read(15, 67108867, 2243193877, 0); // [time: 440ns -> 450ns] + read(15, 67108864, 2472849580, 0); // [time: 450ns -> 460ns] + read(15, 67108869, 3565370026, 0); // [time: 460ns -> 470ns] + read(15, 67108870, 890985600, 0); // [time: 470ns -> 480ns] + read(15, 67108871, 4179549189, 0); // [time: 480ns -> 490ns] + read(15, 67108868, 4158632492, 0); // [time: 490ns -> 500ns] + read(15, 67108873, 3744957516, 0); // [time: 500ns -> 510ns] + read(15, 67108874, 2300150418, 0); // [time: 510ns -> 520ns] + read(15, 67108875, 2081940992, 0); // [time: 520ns -> 530ns] + read(15, 67108872, 1697819148, 0); // [time: 530ns -> 540ns] + read(15, 67108877, 602241333, 0); // [time: 540ns -> 550ns] + read(15, 67108878, 2260552922, 0); // [time: 550ns -> 560ns] + read(15, 67108879, 4251564751, 0); // [time: 560ns -> 570ns] + read(15, 67108876, 3326548024, 0); // [time: 570ns -> 580ns] + reset(); // [time: 620.001ns -> 630.001ns] + reset(); // [time: 630.001ns -> 640.001ns] + reset(); // [time: 640.001ns -> 650.001ns] + write(15, 67108865, 1044044861, 0); // [time: 690.001ns -> 710.001ns] + write(15, 67108866, 4177314760, 0); // [time: 710.001ns -> 720.001ns] + write(15, 67108867, 4253662683, 0); // [time: 720.001ns -> 730.001ns] + write(15, 67108864, 3575602093, 0); // [time: 730.001ns -> 740.001ns] + write(15, 67108869, 667576938, 0); // [time: 740.001ns -> 750.001ns] + write(15, 67108870, 3110079964, 0); // [time: 750.001ns -> 760.001ns] + write(15, 67108871, 3758039968, 0); // [time: 760.001ns -> 770.001ns] + write(15, 67108868, 3566852678, 0); // [time: 770.001ns -> 780.001ns] + write(15, 67108873, 3124984337, 0); // [time: 780.001ns -> 790.001ns] + write(15, 67108874, 2124019892, 0); // [time: 790.001ns -> 800.001ns] + write(15, 67108875, 4257151913, 0); // [time: 800.001ns -> 810.001ns] + write(15, 67108872, 2010257240, 0); // [time: 810.001ns -> 820.001ns] + write(15, 67108877, 236076834, 0); // [time: 820.001ns -> 830.001ns] + write(15, 67108878, 1005361240, 0); // [time: 830.001ns -> 840.001ns] + write(15, 67108879, 3482961596, 0); // [time: 840.001ns -> 850.001ns] + write(15, 67108876, 416798935, 0); // [time: 850.001ns -> 860.001ns] + reset(); // [time: 1540.002ns -> 1550.002ns] + reset(); // [time: 1550.002ns -> 1560.002ns] + reset(); // [time: 1560.002ns -> 1570.002ns] + write(15, 67108865, 5665644, 0); // [time: 1610.002ns -> 1630.002ns] + write(15, 67108866, 2207028948, 0); // [time: 1630.002ns -> 1640.002ns] + write(15, 67108867, 3039596975, 0); // [time: 1640.002ns -> 1650.002ns] + write(15, 67108864, 2873077745, 0); // [time: 1650.002ns -> 1660.002ns] + write(15, 67108869, 4156333102, 0); // [time: 1660.002ns -> 1670.002ns] + write(15, 67108870, 2428683490, 0); // [time: 1670.002ns -> 1680.002ns] + write(15, 67108871, 2474641325, 0); // [time: 1680.002ns -> 1690.002ns] + write(15, 67108868, 2593936487, 0); // [time: 1690.002ns -> 1700.002ns] + write(15, 67108873, 2521039073, 0); // [time: 1700.002ns -> 1710.002ns] + write(15, 67108874, 3155595410, 0); // [time: 1710.002ns -> 1720.002ns] + write(15, 67108875, 2665880696, 0); // [time: 1720.002ns -> 1730.002ns] + write(15, 67108872, 1347764084, 0); // [time: 1730.002ns -> 1740.002ns] + write(15, 67108877, 3198898103, 0); // [time: 1740.002ns -> 1750.002ns] + write(15, 67108878, 1659773118, 0); // [time: 1750.002ns -> 1760.002ns] + write(15, 67108879, 2296543553, 0); // [time: 1760.002ns -> 1770.002ns] + write(15, 67108876, 1471659223, 0); // [time: 1770.002ns -> 1780.002ns] + read(15, 67108865, 5665644, 0); // [time: 1780.002ns -> 1800.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_4_2.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_4_2.bi.expect new file mode 100644 index 00000000..c01c5814 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_4_2.bi.expect @@ -0,0 +1,61 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108865, 3495738447, 0); // [time: 410ns -> 430ns] + read(15, 67108866, 1478546475, 0); // [time: 430ns -> 440ns] + read(15, 67108867, 2041778918, 0); // [time: 440ns -> 450ns] + read(15, 67108868, 3032895213, 0); // [time: 450ns -> 460ns] + read(15, 67108869, 2020268309, 0); // [time: 460ns -> 470ns] + read(15, 67108870, 3122719830, 0); // [time: 470ns -> 480ns] + read(15, 67108871, 3806053567, 0); // [time: 480ns -> 490ns] + read(15, 67108864, 3858565026, 0); // [time: 490ns -> 500ns] + read(15, 67108873, 880624971, 0); // [time: 500ns -> 510ns] + read(15, 67108874, 2554056607, 0); // [time: 510ns -> 520ns] + read(15, 67108875, 1441832696, 0); // [time: 520ns -> 530ns] + read(15, 67108876, 479445740, 0); // [time: 530ns -> 540ns] + read(15, 67108877, 2229265910, 0); // [time: 540ns -> 550ns] + read(15, 67108878, 788973880, 0); // [time: 550ns -> 560ns] + read(15, 67108879, 3880977277, 0); // [time: 560ns -> 570ns] + read(15, 67108872, 4096708504, 0); // [time: 570ns -> 580ns] + reset(); // [time: 620.001ns -> 630.001ns] + reset(); // [time: 630.001ns -> 640.001ns] + reset(); // [time: 640.001ns -> 650.001ns] + write(15, 67108865, 2427636421, 0); // [time: 690.001ns -> 710.001ns] + write(15, 67108866, 3595099675, 0); // [time: 710.001ns -> 720.001ns] + write(15, 67108867, 2668681316, 0); // [time: 720.001ns -> 730.001ns] + write(15, 67108868, 1679837987, 0); // [time: 730.001ns -> 740.001ns] + write(15, 67108869, 924732013, 0); // [time: 740.001ns -> 750.001ns] + write(15, 67108870, 2192079403, 0); // [time: 750.001ns -> 760.001ns] + write(15, 67108871, 2042051660, 0); // [time: 760.001ns -> 770.001ns] + write(15, 67108864, 989927686, 0); // [time: 770.001ns -> 780.001ns] + write(15, 67108873, 3067406900, 0); // [time: 780.001ns -> 790.001ns] + write(15, 67108874, 1058215073, 0); // [time: 790.001ns -> 800.001ns] + write(15, 67108875, 365012335, 0); // [time: 800.001ns -> 810.001ns] + write(15, 67108876, 687295108, 0); // [time: 810.001ns -> 820.001ns] + write(15, 67108877, 2829218573, 0); // [time: 820.001ns -> 830.001ns] + write(15, 67108878, 1448409262, 0); // [time: 830.001ns -> 840.001ns] + write(15, 67108879, 400594486, 0); // [time: 840.001ns -> 850.001ns] + write(15, 67108872, 4177343116, 0); // [time: 850.001ns -> 860.001ns] + reset(); // [time: 1540.002ns -> 1550.002ns] + reset(); // [time: 1550.002ns -> 1560.002ns] + reset(); // [time: 1560.002ns -> 1570.002ns] + write(15, 67108865, 2304668716, 0); // [time: 1610.002ns -> 1630.002ns] + write(15, 67108866, 2610611482, 0); // [time: 1630.002ns -> 1640.002ns] + write(15, 67108867, 1468153982, 0); // [time: 1640.002ns -> 1650.002ns] + write(15, 67108868, 1169841342, 0); // [time: 1650.002ns -> 1660.002ns] + write(15, 67108869, 27036823, 0); // [time: 1660.002ns -> 1670.002ns] + write(15, 67108870, 73783758, 0); // [time: 1670.002ns -> 1680.002ns] + write(15, 67108871, 1621524717, 0); // [time: 1680.002ns -> 1690.002ns] + write(15, 67108864, 3905946412, 0); // [time: 1690.002ns -> 1700.002ns] + write(15, 67108873, 1563100034, 0); // [time: 1700.002ns -> 1710.002ns] + write(15, 67108874, 2069336907, 0); // [time: 1710.002ns -> 1720.002ns] + write(15, 67108875, 583373053, 0); // [time: 1720.002ns -> 1730.002ns] + write(15, 67108876, 3629920426, 0); // [time: 1730.002ns -> 1740.002ns] + write(15, 67108877, 2146122704, 0); // [time: 1740.002ns -> 1750.002ns] + write(15, 67108878, 2674258699, 0); // [time: 1750.002ns -> 1760.002ns] + write(15, 67108879, 1361676606, 0); // [time: 1760.002ns -> 1770.002ns] + write(15, 67108872, 2435452493, 0); // [time: 1770.002ns -> 1780.002ns] + read(15, 67108865, 2304668716, 0); // [time: 1780.002ns -> 1800.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_4_3.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_4_3.bi.expect new file mode 100644 index 00000000..6190588c --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_4_3.bi.expect @@ -0,0 +1,61 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108865, 1070372987, 0); // [time: 410ns -> 430ns] + read(15, 67108866, 2645947069, 0); // [time: 430ns -> 440ns] + read(15, 67108867, 736643984, 0); // [time: 440ns -> 450ns] + read(15, 67108868, 192007203, 0); // [time: 450ns -> 460ns] + read(15, 67108869, 1925400290, 0); // [time: 460ns -> 470ns] + read(15, 67108870, 1309609983, 0); // [time: 470ns -> 480ns] + read(15, 67108871, 58503546, 0); // [time: 480ns -> 490ns] + read(15, 67108872, 3861022989, 0); // [time: 490ns -> 500ns] + read(15, 67108873, 1725708128, 0); // [time: 500ns -> 510ns] + read(15, 67108874, 3760744365, 0); // [time: 510ns -> 520ns] + read(15, 67108875, 3803789590, 0); // [time: 520ns -> 530ns] + read(15, 67108876, 2647121574, 0); // [time: 530ns -> 540ns] + read(15, 67108877, 336117328, 0); // [time: 540ns -> 550ns] + read(15, 67108878, 3984726565, 0); // [time: 550ns -> 560ns] + read(15, 67108879, 104808193, 0); // [time: 560ns -> 570ns] + read(15, 67108864, 2315494688, 0); // [time: 570ns -> 580ns] + reset(); // [time: 620.001ns -> 630.001ns] + reset(); // [time: 630.001ns -> 640.001ns] + reset(); // [time: 640.001ns -> 650.001ns] + write(15, 67108865, 3997204021, 0); // [time: 690.001ns -> 710.001ns] + write(15, 67108866, 666660673, 0); // [time: 710.001ns -> 720.001ns] + write(15, 67108867, 3910223084, 0); // [time: 720.001ns -> 730.001ns] + write(15, 67108868, 1271405124, 0); // [time: 730.001ns -> 740.001ns] + write(15, 67108869, 4236388983, 0); // [time: 740.001ns -> 750.001ns] + write(15, 67108870, 1347016890, 0); // [time: 750.001ns -> 760.001ns] + write(15, 67108871, 1337396640, 0); // [time: 760.001ns -> 770.001ns] + write(15, 67108872, 3009712000, 0); // [time: 770.001ns -> 780.001ns] + write(15, 67108873, 2237248361, 0); // [time: 780.001ns -> 790.001ns] + write(15, 67108874, 592560133, 0); // [time: 790.001ns -> 800.001ns] + write(15, 67108875, 371018497, 0); // [time: 800.001ns -> 810.001ns] + write(15, 67108876, 763875626, 0); // [time: 810.001ns -> 820.001ns] + write(15, 67108877, 75174504, 0); // [time: 820.001ns -> 830.001ns] + write(15, 67108878, 2983449782, 0); // [time: 830.001ns -> 840.001ns] + write(15, 67108879, 2295155532, 0); // [time: 840.001ns -> 850.001ns] + write(15, 67108864, 1954643484, 0); // [time: 850.001ns -> 860.001ns] + reset(); // [time: 1540.002ns -> 1550.002ns] + reset(); // [time: 1550.002ns -> 1560.002ns] + reset(); // [time: 1560.002ns -> 1570.002ns] + write(15, 67108865, 409090773, 0); // [time: 1610.002ns -> 1630.002ns] + write(15, 67108866, 1348706589, 0); // [time: 1630.002ns -> 1640.002ns] + write(15, 67108867, 1967918440, 0); // [time: 1640.002ns -> 1650.002ns] + write(15, 67108868, 2636141882, 0); // [time: 1650.002ns -> 1660.002ns] + write(15, 67108869, 533777194, 0); // [time: 1660.002ns -> 1670.002ns] + write(15, 67108870, 2114809607, 0); // [time: 1670.002ns -> 1680.002ns] + write(15, 67108871, 309856382, 0); // [time: 1680.002ns -> 1690.002ns] + write(15, 67108872, 3466848916, 0); // [time: 1690.002ns -> 1700.002ns] + write(15, 67108873, 3043756153, 0); // [time: 1700.002ns -> 1710.002ns] + write(15, 67108874, 2927281001, 0); // [time: 1710.002ns -> 1720.002ns] + write(15, 67108875, 1913699666, 0); // [time: 1720.002ns -> 1730.002ns] + write(15, 67108876, 1847871828, 0); // [time: 1730.002ns -> 1740.002ns] + write(15, 67108877, 3984372107, 0); // [time: 1740.002ns -> 1750.002ns] + write(15, 67108878, 4239907193, 0); // [time: 1750.002ns -> 1760.002ns] + write(15, 67108879, 1427511912, 0); // [time: 1760.002ns -> 1770.002ns] + write(15, 67108864, 277973300, 0); // [time: 1770.002ns -> 1780.002ns] + read(15, 67108865, 409090773, 0); // [time: 1780.002ns -> 1800.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_8_0.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_8_0.bi.expect new file mode 100644 index 00000000..a37855f8 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_8_0.bi.expect @@ -0,0 +1,61 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108866, 2205995893, 0); // [time: 410ns -> 430ns] + read(15, 67108867, 486560095, 0); // [time: 430ns -> 440ns] + read(15, 67108868, 4100133660, 0); // [time: 440ns -> 450ns] + read(15, 67108869, 596618694, 0); // [time: 450ns -> 460ns] + read(15, 67108870, 3499942130, 0); // [time: 460ns -> 470ns] + read(15, 67108871, 2357711907, 0); // [time: 470ns -> 480ns] + read(15, 67108872, 2086526797, 0); // [time: 480ns -> 490ns] + read(15, 67108873, 364077448, 0); // [time: 490ns -> 500ns] + read(15, 67108874, 210674739, 0); // [time: 500ns -> 510ns] + read(15, 67108875, 1567286535, 0); // [time: 510ns -> 520ns] + read(15, 67108876, 922799025, 0); // [time: 520ns -> 530ns] + read(15, 67108877, 4171757579, 0); // [time: 530ns -> 540ns] + read(15, 67108878, 740193371, 0); // [time: 540ns -> 550ns] + read(15, 67108879, 872570658, 0); // [time: 550ns -> 560ns] + read(15, 67108880, 608559447, 0); // [time: 560ns -> 570ns] + read(15, 67108881, 1049762371, 0); // [time: 570ns -> 580ns] + reset(); // [time: 620.001ns -> 630.001ns] + reset(); // [time: 630.001ns -> 640.001ns] + reset(); // [time: 640.001ns -> 650.001ns] + write(15, 67108866, 61321282, 0); // [time: 690.001ns -> 710.001ns] + write(15, 67108867, 3113679544, 0); // [time: 710.001ns -> 720.001ns] + write(15, 67108868, 2723657215, 0); // [time: 720.001ns -> 730.001ns] + write(15, 67108869, 3578979173, 0); // [time: 730.001ns -> 740.001ns] + write(15, 67108870, 1844094072, 0); // [time: 740.001ns -> 750.001ns] + write(15, 67108871, 985922533, 0); // [time: 750.001ns -> 760.001ns] + write(15, 67108872, 772047228, 0); // [time: 760.001ns -> 770.001ns] + write(15, 67108873, 2786594234, 0); // [time: 770.001ns -> 780.001ns] + write(15, 67108874, 3174400206, 0); // [time: 780.001ns -> 790.001ns] + write(15, 67108875, 4087288639, 0); // [time: 790.001ns -> 800.001ns] + write(15, 67108876, 1255295898, 0); // [time: 800.001ns -> 810.001ns] + write(15, 67108877, 1278490992, 0); // [time: 810.001ns -> 820.001ns] + write(15, 67108878, 3471724536, 0); // [time: 820.001ns -> 830.001ns] + write(15, 67108879, 382544438, 0); // [time: 830.001ns -> 840.001ns] + write(15, 67108880, 457743574, 0); // [time: 840.001ns -> 850.001ns] + write(15, 67108881, 2419868428, 0); // [time: 850.001ns -> 860.001ns] + reset(); // [time: 1540.002ns -> 1550.002ns] + reset(); // [time: 1550.002ns -> 1560.002ns] + reset(); // [time: 1560.002ns -> 1570.002ns] + write(15, 67108866, 3159959397, 0); // [time: 1610.002ns -> 1630.002ns] + write(15, 67108867, 2987258927, 0); // [time: 1630.002ns -> 1640.002ns] + write(15, 67108868, 3076374300, 0); // [time: 1640.002ns -> 1650.002ns] + write(15, 67108869, 2145515966, 0); // [time: 1650.002ns -> 1660.002ns] + write(15, 67108870, 363069260, 0); // [time: 1660.002ns -> 1670.002ns] + write(15, 67108871, 1291413511, 0); // [time: 1670.002ns -> 1680.002ns] + write(15, 67108872, 3582649965, 0); // [time: 1680.002ns -> 1690.002ns] + write(15, 67108873, 2885357400, 0); // [time: 1690.002ns -> 1700.002ns] + write(15, 67108874, 1499869988, 0); // [time: 1700.002ns -> 1710.002ns] + write(15, 67108875, 2213787236, 0); // [time: 1710.002ns -> 1720.002ns] + write(15, 67108876, 1663586395, 0); // [time: 1720.002ns -> 1730.002ns] + write(15, 67108877, 680862039, 0); // [time: 1730.002ns -> 1740.002ns] + write(15, 67108878, 4246962232, 0); // [time: 1740.002ns -> 1750.002ns] + write(15, 67108879, 2414397419, 0); // [time: 1750.002ns -> 1760.002ns] + write(15, 67108880, 2179858695, 0); // [time: 1760.002ns -> 1770.002ns] + write(15, 67108881, 3059261273, 0); // [time: 1770.002ns -> 1780.002ns] + read(15, 67108866, 3159959397, 0); // [time: 1780.002ns -> 1800.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_8_1.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_8_1.bi.expect new file mode 100644 index 00000000..2ae4e75f --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_8_1.bi.expect @@ -0,0 +1,61 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108866, 2821946881, 0); // [time: 410ns -> 430ns] + read(15, 67108867, 4080087070, 0); // [time: 430ns -> 440ns] + read(15, 67108864, 2243193877, 0); // [time: 440ns -> 450ns] + read(15, 67108865, 2472849580, 0); // [time: 450ns -> 460ns] + read(15, 67108870, 3565370026, 0); // [time: 460ns -> 470ns] + read(15, 67108871, 890985600, 0); // [time: 470ns -> 480ns] + read(15, 67108868, 4179549189, 0); // [time: 480ns -> 490ns] + read(15, 67108869, 4158632492, 0); // [time: 490ns -> 500ns] + read(15, 67108874, 3744957516, 0); // [time: 500ns -> 510ns] + read(15, 67108875, 2300150418, 0); // [time: 510ns -> 520ns] + read(15, 67108872, 2081940992, 0); // [time: 520ns -> 530ns] + read(15, 67108873, 1697819148, 0); // [time: 530ns -> 540ns] + read(15, 67108878, 602241333, 0); // [time: 540ns -> 550ns] + read(15, 67108879, 2260552922, 0); // [time: 550ns -> 560ns] + read(15, 67108876, 4251564751, 0); // [time: 560ns -> 570ns] + read(15, 67108877, 3326548024, 0); // [time: 570ns -> 580ns] + reset(); // [time: 620.001ns -> 630.001ns] + reset(); // [time: 630.001ns -> 640.001ns] + reset(); // [time: 640.001ns -> 650.001ns] + write(15, 67108866, 1044044861, 0); // [time: 690.001ns -> 710.001ns] + write(15, 67108867, 4177314760, 0); // [time: 710.001ns -> 720.001ns] + write(15, 67108864, 4253662683, 0); // [time: 720.001ns -> 730.001ns] + write(15, 67108865, 3575602093, 0); // [time: 730.001ns -> 740.001ns] + write(15, 67108870, 667576938, 0); // [time: 740.001ns -> 750.001ns] + write(15, 67108871, 3110079964, 0); // [time: 750.001ns -> 760.001ns] + write(15, 67108868, 3758039968, 0); // [time: 760.001ns -> 770.001ns] + write(15, 67108869, 3566852678, 0); // [time: 770.001ns -> 780.001ns] + write(15, 67108874, 3124984337, 0); // [time: 780.001ns -> 790.001ns] + write(15, 67108875, 2124019892, 0); // [time: 790.001ns -> 800.001ns] + write(15, 67108872, 4257151913, 0); // [time: 800.001ns -> 810.001ns] + write(15, 67108873, 2010257240, 0); // [time: 810.001ns -> 820.001ns] + write(15, 67108878, 236076834, 0); // [time: 820.001ns -> 830.001ns] + write(15, 67108879, 1005361240, 0); // [time: 830.001ns -> 840.001ns] + write(15, 67108876, 3482961596, 0); // [time: 840.001ns -> 850.001ns] + write(15, 67108877, 416798935, 0); // [time: 850.001ns -> 860.001ns] + reset(); // [time: 1540.002ns -> 1550.002ns] + reset(); // [time: 1550.002ns -> 1560.002ns] + reset(); // [time: 1560.002ns -> 1570.002ns] + write(15, 67108866, 5665644, 0); // [time: 1610.002ns -> 1630.002ns] + write(15, 67108867, 2207028948, 0); // [time: 1630.002ns -> 1640.002ns] + write(15, 67108864, 3039596975, 0); // [time: 1640.002ns -> 1650.002ns] + write(15, 67108865, 2873077745, 0); // [time: 1650.002ns -> 1660.002ns] + write(15, 67108870, 4156333102, 0); // [time: 1660.002ns -> 1670.002ns] + write(15, 67108871, 2428683490, 0); // [time: 1670.002ns -> 1680.002ns] + write(15, 67108868, 2474641325, 0); // [time: 1680.002ns -> 1690.002ns] + write(15, 67108869, 2593936487, 0); // [time: 1690.002ns -> 1700.002ns] + write(15, 67108874, 2521039073, 0); // [time: 1700.002ns -> 1710.002ns] + write(15, 67108875, 3155595410, 0); // [time: 1710.002ns -> 1720.002ns] + write(15, 67108872, 2665880696, 0); // [time: 1720.002ns -> 1730.002ns] + write(15, 67108873, 1347764084, 0); // [time: 1730.002ns -> 1740.002ns] + write(15, 67108878, 3198898103, 0); // [time: 1740.002ns -> 1750.002ns] + write(15, 67108879, 1659773118, 0); // [time: 1750.002ns -> 1760.002ns] + write(15, 67108876, 2296543553, 0); // [time: 1760.002ns -> 1770.002ns] + write(15, 67108877, 1471659223, 0); // [time: 1770.002ns -> 1780.002ns] + read(15, 67108866, 5665644, 0); // [time: 1780.002ns -> 1800.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_8_2.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_8_2.bi.expect new file mode 100644 index 00000000..fb8baf9c --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_8_2.bi.expect @@ -0,0 +1,61 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108866, 3495738447, 0); // [time: 410ns -> 430ns] + read(15, 67108867, 1478546475, 0); // [time: 430ns -> 440ns] + read(15, 67108868, 2041778918, 0); // [time: 440ns -> 450ns] + read(15, 67108869, 3032895213, 0); // [time: 450ns -> 460ns] + read(15, 67108870, 2020268309, 0); // [time: 460ns -> 470ns] + read(15, 67108871, 3122719830, 0); // [time: 470ns -> 480ns] + read(15, 67108864, 3806053567, 0); // [time: 480ns -> 490ns] + read(15, 67108865, 3858565026, 0); // [time: 490ns -> 500ns] + read(15, 67108874, 880624971, 0); // [time: 500ns -> 510ns] + read(15, 67108875, 2554056607, 0); // [time: 510ns -> 520ns] + read(15, 67108876, 1441832696, 0); // [time: 520ns -> 530ns] + read(15, 67108877, 479445740, 0); // [time: 530ns -> 540ns] + read(15, 67108878, 2229265910, 0); // [time: 540ns -> 550ns] + read(15, 67108879, 788973880, 0); // [time: 550ns -> 560ns] + read(15, 67108872, 3880977277, 0); // [time: 560ns -> 570ns] + read(15, 67108873, 4096708504, 0); // [time: 570ns -> 580ns] + reset(); // [time: 620.001ns -> 630.001ns] + reset(); // [time: 630.001ns -> 640.001ns] + reset(); // [time: 640.001ns -> 650.001ns] + write(15, 67108866, 2427636421, 0); // [time: 690.001ns -> 710.001ns] + write(15, 67108867, 3595099675, 0); // [time: 710.001ns -> 720.001ns] + write(15, 67108868, 2668681316, 0); // [time: 720.001ns -> 730.001ns] + write(15, 67108869, 1679837987, 0); // [time: 730.001ns -> 740.001ns] + write(15, 67108870, 924732013, 0); // [time: 740.001ns -> 750.001ns] + write(15, 67108871, 2192079403, 0); // [time: 750.001ns -> 760.001ns] + write(15, 67108864, 2042051660, 0); // [time: 760.001ns -> 770.001ns] + write(15, 67108865, 989927686, 0); // [time: 770.001ns -> 780.001ns] + write(15, 67108874, 3067406900, 0); // [time: 780.001ns -> 790.001ns] + write(15, 67108875, 1058215073, 0); // [time: 790.001ns -> 800.001ns] + write(15, 67108876, 365012335, 0); // [time: 800.001ns -> 810.001ns] + write(15, 67108877, 687295108, 0); // [time: 810.001ns -> 820.001ns] + write(15, 67108878, 2829218573, 0); // [time: 820.001ns -> 830.001ns] + write(15, 67108879, 1448409262, 0); // [time: 830.001ns -> 840.001ns] + write(15, 67108872, 400594486, 0); // [time: 840.001ns -> 850.001ns] + write(15, 67108873, 4177343116, 0); // [time: 850.001ns -> 860.001ns] + reset(); // [time: 1540.002ns -> 1550.002ns] + reset(); // [time: 1550.002ns -> 1560.002ns] + reset(); // [time: 1560.002ns -> 1570.002ns] + write(15, 67108866, 2304668716, 0); // [time: 1610.002ns -> 1630.002ns] + write(15, 67108867, 2610611482, 0); // [time: 1630.002ns -> 1640.002ns] + write(15, 67108868, 1468153982, 0); // [time: 1640.002ns -> 1650.002ns] + write(15, 67108869, 1169841342, 0); // [time: 1650.002ns -> 1660.002ns] + write(15, 67108870, 27036823, 0); // [time: 1660.002ns -> 1670.002ns] + write(15, 67108871, 73783758, 0); // [time: 1670.002ns -> 1680.002ns] + write(15, 67108864, 1621524717, 0); // [time: 1680.002ns -> 1690.002ns] + write(15, 67108865, 3905946412, 0); // [time: 1690.002ns -> 1700.002ns] + write(15, 67108874, 1563100034, 0); // [time: 1700.002ns -> 1710.002ns] + write(15, 67108875, 2069336907, 0); // [time: 1710.002ns -> 1720.002ns] + write(15, 67108876, 583373053, 0); // [time: 1720.002ns -> 1730.002ns] + write(15, 67108877, 3629920426, 0); // [time: 1730.002ns -> 1740.002ns] + write(15, 67108878, 2146122704, 0); // [time: 1740.002ns -> 1750.002ns] + write(15, 67108879, 2674258699, 0); // [time: 1750.002ns -> 1760.002ns] + write(15, 67108872, 1361676606, 0); // [time: 1760.002ns -> 1770.002ns] + write(15, 67108873, 2435452493, 0); // [time: 1770.002ns -> 1780.002ns] + read(15, 67108866, 2304668716, 0); // [time: 1780.002ns -> 1800.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_8_3.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_8_3.bi.expect new file mode 100644 index 00000000..6e117e35 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_8_3.bi.expect @@ -0,0 +1,61 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108866, 2727164243, 0); // [time: 410ns -> 430ns] + read(15, 67108867, 1384255697, 0); // [time: 430ns -> 440ns] + read(15, 67108868, 4216231340, 0); // [time: 440ns -> 450ns] + read(15, 67108869, 1661993927, 0); // [time: 450ns -> 460ns] + read(15, 67108870, 159950269, 0); // [time: 460ns -> 470ns] + read(15, 67108871, 893905490, 0); // [time: 470ns -> 480ns] + read(15, 67108872, 1464841894, 0); // [time: 480ns -> 490ns] + read(15, 67108873, 710545966, 0); // [time: 490ns -> 500ns] + read(15, 67108874, 3482423916, 0); // [time: 500ns -> 510ns] + read(15, 67108875, 4068629318, 0); // [time: 510ns -> 520ns] + read(15, 67108876, 3266524719, 0); // [time: 520ns -> 530ns] + read(15, 67108877, 1808083576, 0); // [time: 530ns -> 540ns] + read(15, 67108878, 3562161795, 0); // [time: 540ns -> 550ns] + read(15, 67108879, 2984675510, 0); // [time: 550ns -> 560ns] + read(15, 67108864, 2475539812, 0); // [time: 560ns -> 570ns] + read(15, 67108865, 2138191023, 0); // [time: 570ns -> 580ns] + reset(); // [time: 620.001ns -> 630.001ns] + reset(); // [time: 630.001ns -> 640.001ns] + reset(); // [time: 640.001ns -> 650.001ns] + write(15, 67108866, 1599974119, 0); // [time: 690.001ns -> 710.001ns] + write(15, 67108867, 609858284, 0); // [time: 710.001ns -> 720.001ns] + write(15, 67108868, 1648881400, 0); // [time: 720.001ns -> 730.001ns] + write(15, 67108869, 572149112, 0); // [time: 730.001ns -> 740.001ns] + write(15, 67108870, 602124761, 0); // [time: 740.001ns -> 750.001ns] + write(15, 67108871, 3299652692, 0); // [time: 750.001ns -> 760.001ns] + write(15, 67108872, 1416165996, 0); // [time: 760.001ns -> 770.001ns] + write(15, 67108873, 1639735531, 0); // [time: 770.001ns -> 780.001ns] + write(15, 67108874, 941900856, 0); // [time: 780.001ns -> 790.001ns] + write(15, 67108875, 4103564658, 0); // [time: 790.001ns -> 800.001ns] + write(15, 67108876, 788749736, 0); // [time: 800.001ns -> 810.001ns] + write(15, 67108877, 1260615071, 0); // [time: 810.001ns -> 820.001ns] + write(15, 67108878, 2210117974, 0); // [time: 820.001ns -> 830.001ns] + write(15, 67108879, 2952803435, 0); // [time: 830.001ns -> 840.001ns] + write(15, 67108864, 441673600, 0); // [time: 840.001ns -> 850.001ns] + write(15, 67108865, 2137709866, 0); // [time: 850.001ns -> 860.001ns] + reset(); // [time: 1540.002ns -> 1550.002ns] + reset(); // [time: 1550.002ns -> 1560.002ns] + reset(); // [time: 1560.002ns -> 1570.002ns] + write(15, 67108866, 2898868374, 0); // [time: 1610.002ns -> 1630.002ns] + write(15, 67108867, 1922764675, 0); // [time: 1630.002ns -> 1640.002ns] + write(15, 67108868, 4256406750, 0); // [time: 1640.002ns -> 1650.002ns] + write(15, 67108869, 245447329, 0); // [time: 1650.002ns -> 1660.002ns] + write(15, 67108870, 3225897750, 0); // [time: 1660.002ns -> 1670.002ns] + write(15, 67108871, 1779082048, 0); // [time: 1670.002ns -> 1680.002ns] + write(15, 67108872, 1953003128, 0); // [time: 1680.002ns -> 1690.002ns] + write(15, 67108873, 4020445238, 0); // [time: 1690.002ns -> 1700.002ns] + write(15, 67108874, 2174587331, 0); // [time: 1700.002ns -> 1710.002ns] + write(15, 67108875, 1632125876, 0); // [time: 1710.002ns -> 1720.002ns] + write(15, 67108876, 340410721, 0); // [time: 1720.002ns -> 1730.002ns] + write(15, 67108877, 771941360, 0); // [time: 1730.002ns -> 1740.002ns] + write(15, 67108878, 2567244845, 0); // [time: 1740.002ns -> 1750.002ns] + write(15, 67108879, 899887853, 0); // [time: 1750.002ns -> 1760.002ns] + write(15, 67108864, 1674678715, 0); // [time: 1760.002ns -> 1770.002ns] + write(15, 67108865, 902429492, 0); // [time: 1770.002ns -> 1780.002ns] + read(15, 67108866, 2898868374, 0); // [time: 1780.002ns -> 1800.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_0_0.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_0_0.bi.expect new file mode 100644 index 00000000..c3a38561 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_0_0.bi.expect @@ -0,0 +1,16 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108864, 2205995893, 0); // [time: 110ns -> 130ns] + reset(); // [time: 170.001ns -> 180.001ns] + reset(); // [time: 180.001ns -> 190.001ns] + reset(); // [time: 190.001ns -> 200.001ns] + write(15, 67108864, 486560095, 0); // [time: 240.001ns -> 260.001ns] + reset(); // [time: 340.002ns -> 350.002ns] + reset(); // [time: 350.002ns -> 360.002ns] + reset(); // [time: 360.002ns -> 370.002ns] + write(15, 67108864, 4100133660, 0); // [time: 410.002ns -> 430.002ns] + read(15, 67108864, 4100133660, 0); // [time: 430.002ns -> 450.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_0_1.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_0_1.bi.expect new file mode 100644 index 00000000..aebae401 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_0_1.bi.expect @@ -0,0 +1,16 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108864, 518534189, 0); // [time: 110ns -> 130ns] + reset(); // [time: 170.001ns -> 180.001ns] + reset(); // [time: 180.001ns -> 190.001ns] + reset(); // [time: 190.001ns -> 200.001ns] + write(15, 67108864, 844695266, 0); // [time: 240.001ns -> 260.001ns] + reset(); // [time: 340.002ns -> 350.002ns] + reset(); // [time: 350.002ns -> 360.002ns] + reset(); // [time: 360.002ns -> 370.002ns] + write(15, 67108864, 3937184150, 0); // [time: 410.002ns -> 430.002ns] + read(15, 67108864, 3937184150, 0); // [time: 430.002ns -> 450.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_0_2.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_0_2.bi.expect new file mode 100644 index 00000000..b01c57c0 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_0_2.bi.expect @@ -0,0 +1,16 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108864, 3580256271, 0); // [time: 110ns -> 130ns] + reset(); // [time: 170.001ns -> 180.001ns] + reset(); // [time: 180.001ns -> 190.001ns] + reset(); // [time: 190.001ns -> 200.001ns] + write(15, 67108864, 1489666683, 0); // [time: 240.001ns -> 260.001ns] + reset(); // [time: 340.002ns -> 350.002ns] + reset(); // [time: 350.002ns -> 360.002ns] + reset(); // [time: 360.002ns -> 370.002ns] + write(15, 67108864, 3677074643, 0); // [time: 410.002ns -> 430.002ns] + read(15, 67108864, 3677074643, 0); // [time: 430.002ns -> 450.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_0_3.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_0_3.bi.expect new file mode 100644 index 00000000..90e7d396 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_0_3.bi.expect @@ -0,0 +1,16 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108864, 1509562552, 0); // [time: 110ns -> 130ns] + reset(); // [time: 170.001ns -> 180.001ns] + reset(); // [time: 180.001ns -> 190.001ns] + reset(); // [time: 190.001ns -> 200.001ns] + write(15, 67108864, 2329347035, 0); // [time: 240.001ns -> 260.001ns] + reset(); // [time: 340.002ns -> 350.002ns] + reset(); // [time: 350.002ns -> 360.002ns] + reset(); // [time: 360.002ns -> 370.002ns] + write(15, 67108864, 3862381389, 0); // [time: 410.002ns -> 430.002ns] + read(15, 67108864, 3862381389, 0); // [time: 430.002ns -> 450.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_12_0.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_12_0.bi.expect new file mode 100644 index 00000000..f42edacc --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_12_0.bi.expect @@ -0,0 +1,16 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108867, 3597917862, 0); // [time: 110ns -> 130ns] + reset(); // [time: 170.001ns -> 180.001ns] + reset(); // [time: 180.001ns -> 190.001ns] + reset(); // [time: 190.001ns -> 200.001ns] + write(15, 67108867, 1298617733, 0); // [time: 240.001ns -> 260.001ns] + reset(); // [time: 340.002ns -> 350.002ns] + reset(); // [time: 350.002ns -> 360.002ns] + reset(); // [time: 360.002ns -> 370.002ns] + write(15, 67108867, 2330861729, 0); // [time: 410.002ns -> 430.002ns] + read(15, 67108867, 2330861729, 0); // [time: 430.002ns -> 450.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_12_1.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_12_1.bi.expect new file mode 100644 index 00000000..896dad1e --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_12_1.bi.expect @@ -0,0 +1,16 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108867, 2821946881, 0); // [time: 110ns -> 130ns] + reset(); // [time: 170.001ns -> 180.001ns] + reset(); // [time: 180.001ns -> 190.001ns] + reset(); // [time: 190.001ns -> 200.001ns] + write(15, 67108867, 4080087070, 0); // [time: 240.001ns -> 260.001ns] + reset(); // [time: 340.002ns -> 350.002ns] + reset(); // [time: 350.002ns -> 360.002ns] + reset(); // [time: 360.002ns -> 370.002ns] + write(15, 67108867, 2243193877, 0); // [time: 410.002ns -> 430.002ns] + read(15, 67108867, 2243193877, 0); // [time: 430.002ns -> 450.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_12_2.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_12_2.bi.expect new file mode 100644 index 00000000..247aef00 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_12_2.bi.expect @@ -0,0 +1,16 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108867, 869832817, 0); // [time: 110ns -> 130ns] + reset(); // [time: 170.001ns -> 180.001ns] + reset(); // [time: 180.001ns -> 190.001ns] + reset(); // [time: 190.001ns -> 200.001ns] + write(15, 67108867, 2976082601, 0); // [time: 240.001ns -> 260.001ns] + reset(); // [time: 340.002ns -> 350.002ns] + reset(); // [time: 350.002ns -> 360.002ns] + reset(); // [time: 360.002ns -> 370.002ns] + write(15, 67108867, 373695501, 0); // [time: 410.002ns -> 430.002ns] + read(15, 67108867, 373695501, 0); // [time: 430.002ns -> 450.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_12_3.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_12_3.bi.expect new file mode 100644 index 00000000..464cc88c --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_12_3.bi.expect @@ -0,0 +1,16 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108867, 1509562552, 0); // [time: 110ns -> 130ns] + reset(); // [time: 170.001ns -> 180.001ns] + reset(); // [time: 180.001ns -> 190.001ns] + reset(); // [time: 190.001ns -> 200.001ns] + write(15, 67108867, 2329347035, 0); // [time: 240.001ns -> 260.001ns] + reset(); // [time: 340.002ns -> 350.002ns] + reset(); // [time: 350.002ns -> 360.002ns] + reset(); // [time: 360.002ns -> 370.002ns] + write(15, 67108867, 3862381389, 0); // [time: 410.002ns -> 430.002ns] + read(15, 67108867, 3862381389, 0); // [time: 430.002ns -> 450.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_4_0.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_4_0.bi.expect new file mode 100644 index 00000000..2cd9a72f --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_4_0.bi.expect @@ -0,0 +1,16 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108865, 1691632885, 0); // [time: 110ns -> 130ns] + reset(); // [time: 170.001ns -> 180.001ns] + reset(); // [time: 180.001ns -> 190.001ns] + reset(); // [time: 190.001ns -> 200.001ns] + write(15, 67108865, 3547248670, 0); // [time: 240.001ns -> 260.001ns] + reset(); // [time: 340.002ns -> 350.002ns] + reset(); // [time: 350.002ns -> 360.002ns] + reset(); // [time: 360.002ns -> 370.002ns] + write(15, 67108865, 665751263, 0); // [time: 410.002ns -> 430.002ns] + read(15, 67108865, 665751263, 0); // [time: 430.002ns -> 450.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_4_1.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_4_1.bi.expect new file mode 100644 index 00000000..80edb357 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_4_1.bi.expect @@ -0,0 +1,16 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108865, 518534189, 0); // [time: 110ns -> 130ns] + reset(); // [time: 170.001ns -> 180.001ns] + reset(); // [time: 180.001ns -> 190.001ns] + reset(); // [time: 190.001ns -> 200.001ns] + write(15, 67108865, 844695266, 0); // [time: 240.001ns -> 260.001ns] + reset(); // [time: 340.002ns -> 350.002ns] + reset(); // [time: 350.002ns -> 360.002ns] + reset(); // [time: 360.002ns -> 370.002ns] + write(15, 67108865, 3937184150, 0); // [time: 410.002ns -> 430.002ns] + read(15, 67108865, 3937184150, 0); // [time: 430.002ns -> 450.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_4_2.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_4_2.bi.expect new file mode 100644 index 00000000..7cdb5ea7 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_4_2.bi.expect @@ -0,0 +1,16 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108865, 1016512136, 0); // [time: 110ns -> 130ns] + reset(); // [time: 170.001ns -> 180.001ns] + reset(); // [time: 180.001ns -> 190.001ns] + reset(); // [time: 190.001ns -> 200.001ns] + write(15, 67108865, 226204128, 0); // [time: 240.001ns -> 260.001ns] + reset(); // [time: 340.002ns -> 350.002ns] + reset(); // [time: 350.002ns -> 360.002ns] + reset(); // [time: 360.002ns -> 370.002ns] + write(15, 67108865, 2116565440, 0); // [time: 410.002ns -> 430.002ns] + read(15, 67108865, 2116565440, 0); // [time: 430.002ns -> 450.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_4_3.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_4_3.bi.expect new file mode 100644 index 00000000..67edd59f --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_4_3.bi.expect @@ -0,0 +1,16 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108865, 3495738447, 0); // [time: 110ns -> 130ns] + reset(); // [time: 170.001ns -> 180.001ns] + reset(); // [time: 180.001ns -> 190.001ns] + reset(); // [time: 190.001ns -> 200.001ns] + write(15, 67108865, 1478546475, 0); // [time: 240.001ns -> 260.001ns] + reset(); // [time: 340.002ns -> 350.002ns] + reset(); // [time: 350.002ns -> 360.002ns] + reset(); // [time: 360.002ns -> 370.002ns] + write(15, 67108865, 2041778918, 0); // [time: 410.002ns -> 430.002ns] + read(15, 67108865, 2041778918, 0); // [time: 430.002ns -> 450.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_8_0.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_8_0.bi.expect new file mode 100644 index 00000000..07c59046 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_8_0.bi.expect @@ -0,0 +1,16 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108866, 1691632885, 0); // [time: 110ns -> 130ns] + reset(); // [time: 170.001ns -> 180.001ns] + reset(); // [time: 180.001ns -> 190.001ns] + reset(); // [time: 190.001ns -> 200.001ns] + write(15, 67108866, 3547248670, 0); // [time: 240.001ns -> 260.001ns] + reset(); // [time: 340.002ns -> 350.002ns] + reset(); // [time: 350.002ns -> 360.002ns] + reset(); // [time: 360.002ns -> 370.002ns] + write(15, 67108866, 665751263, 0); // [time: 410.002ns -> 430.002ns] + read(15, 67108866, 665751263, 0); // [time: 430.002ns -> 450.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_8_1.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_8_1.bi.expect new file mode 100644 index 00000000..7414ac38 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_8_1.bi.expect @@ -0,0 +1,16 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108866, 2821946881, 0); // [time: 110ns -> 130ns] + reset(); // [time: 170.001ns -> 180.001ns] + reset(); // [time: 180.001ns -> 190.001ns] + reset(); // [time: 190.001ns -> 200.001ns] + write(15, 67108866, 4080087070, 0); // [time: 240.001ns -> 260.001ns] + reset(); // [time: 340.002ns -> 350.002ns] + reset(); // [time: 350.002ns -> 360.002ns] + reset(); // [time: 360.002ns -> 370.002ns] + write(15, 67108866, 2243193877, 0); // [time: 410.002ns -> 430.002ns] + read(15, 67108866, 2243193877, 0); // [time: 430.002ns -> 450.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_8_2.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_8_2.bi.expect new file mode 100644 index 00000000..020b204d --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_8_2.bi.expect @@ -0,0 +1,16 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108866, 1016512136, 0); // [time: 110ns -> 130ns] + reset(); // [time: 170.001ns -> 180.001ns] + reset(); // [time: 180.001ns -> 190.001ns] + reset(); // [time: 190.001ns -> 200.001ns] + write(15, 67108866, 226204128, 0); // [time: 240.001ns -> 260.001ns] + reset(); // [time: 340.002ns -> 350.002ns] + reset(); // [time: 350.002ns -> 360.002ns] + reset(); // [time: 360.002ns -> 370.002ns] + write(15, 67108866, 2116565440, 0); // [time: 410.002ns -> 430.002ns] + read(15, 67108866, 2116565440, 0); // [time: 430.002ns -> 450.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_8_3.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_8_3.bi.expect new file mode 100644 index 00000000..288751ac --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_8_3.bi.expect @@ -0,0 +1,16 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108866, 3495738447, 0); // [time: 110ns -> 130ns] + reset(); // [time: 170.001ns -> 180.001ns] + reset(); // [time: 180.001ns -> 190.001ns] + reset(); // [time: 190.001ns -> 200.001ns] + write(15, 67108866, 1478546475, 0); // [time: 240.001ns -> 260.001ns] + reset(); // [time: 340.002ns -> 350.002ns] + reset(); // [time: 350.002ns -> 360.002ns] + reset(); // [time: 360.002ns -> 370.002ns] + write(15, 67108866, 2041778918, 0); // [time: 410.002ns -> 430.002ns] + read(15, 67108866, 2041778918, 0); // [time: 430.002ns -> 450.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_0_0.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_0_0.bi.expect new file mode 100644 index 00000000..883ac1d5 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_0_0.bi.expect @@ -0,0 +1,19 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108864, 3597917862, 0); // [time: 130ns -> 150ns] + read(15, 67108865, 1298617733, 0); // [time: 150ns -> 160ns] + reset(); // [time: 200.001ns -> 210.001ns] + reset(); // [time: 210.001ns -> 220.001ns] + reset(); // [time: 220.001ns -> 230.001ns] + write(15, 67108864, 2330861729, 0); // [time: 270.001ns -> 290.001ns] + write(15, 67108865, 4289318346, 0); // [time: 290.001ns -> 300.001ns] + reset(); // [time: 420.002ns -> 430.002ns] + reset(); // [time: 430.002ns -> 440.002ns] + reset(); // [time: 440.002ns -> 450.002ns] + write(15, 67108864, 2756621846, 0); // [time: 490.002ns -> 510.002ns] + write(15, 67108865, 1627127952, 0); // [time: 510.002ns -> 520.002ns] + read(15, 67108864, 2756621846, 0); // [time: 520.002ns -> 540.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_0_1.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_0_1.bi.expect new file mode 100644 index 00000000..52f2a7ab --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_0_1.bi.expect @@ -0,0 +1,19 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108864, 3580256271, 0); // [time: 130ns -> 150ns] + read(15, 67108865, 1489666683, 0); // [time: 150ns -> 160ns] + reset(); // [time: 200.001ns -> 210.001ns] + reset(); // [time: 210.001ns -> 220.001ns] + reset(); // [time: 220.001ns -> 230.001ns] + write(15, 67108864, 3677074643, 0); // [time: 270.001ns -> 290.001ns] + write(15, 67108865, 1878953054, 0); // [time: 290.001ns -> 300.001ns] + reset(); // [time: 420.002ns -> 430.002ns] + reset(); // [time: 430.002ns -> 440.002ns] + reset(); // [time: 440.002ns -> 450.002ns] + write(15, 67108864, 2965505115, 0); // [time: 490.002ns -> 510.002ns] + write(15, 67108865, 3259566096, 0); // [time: 510.002ns -> 520.002ns] + read(15, 67108864, 2965505115, 0); // [time: 520.002ns -> 540.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_0_2.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_0_2.bi.expect new file mode 100644 index 00000000..c67de0c0 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_0_2.bi.expect @@ -0,0 +1,19 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108864, 869832817, 0); // [time: 130ns -> 150ns] + read(15, 67108865, 2976082601, 0); // [time: 150ns -> 160ns] + reset(); // [time: 200.001ns -> 210.001ns] + reset(); // [time: 210.001ns -> 220.001ns] + reset(); // [time: 220.001ns -> 230.001ns] + write(15, 67108864, 373695501, 0); // [time: 270.001ns -> 290.001ns] + write(15, 67108865, 2110838384, 0); // [time: 290.001ns -> 300.001ns] + reset(); // [time: 420.002ns -> 430.002ns] + reset(); // [time: 430.002ns -> 440.002ns] + reset(); // [time: 440.002ns -> 450.002ns] + write(15, 67108864, 3556455435, 0); // [time: 490.002ns -> 510.002ns] + write(15, 67108865, 1804567173, 0); // [time: 510.002ns -> 520.002ns] + read(15, 67108864, 3556455435, 0); // [time: 520.002ns -> 540.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_0_3.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_0_3.bi.expect new file mode 100644 index 00000000..9948b2bc --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_0_3.bi.expect @@ -0,0 +1,19 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108864, 3495738447, 0); // [time: 130ns -> 150ns] + read(15, 67108865, 1478546475, 0); // [time: 150ns -> 160ns] + reset(); // [time: 200.001ns -> 210.001ns] + reset(); // [time: 210.001ns -> 220.001ns] + reset(); // [time: 220.001ns -> 230.001ns] + write(15, 67108864, 2041778918, 0); // [time: 270.001ns -> 290.001ns] + write(15, 67108865, 3032895213, 0); // [time: 290.001ns -> 300.001ns] + reset(); // [time: 420.002ns -> 430.002ns] + reset(); // [time: 430.002ns -> 440.002ns] + reset(); // [time: 440.002ns -> 450.002ns] + write(15, 67108864, 2020268309, 0); // [time: 490.002ns -> 510.002ns] + write(15, 67108865, 3122719830, 0); // [time: 510.002ns -> 520.002ns] + read(15, 67108864, 2020268309, 0); // [time: 520.002ns -> 540.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_12_0.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_12_0.bi.expect new file mode 100644 index 00000000..bbe1f1e4 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_12_0.bi.expect @@ -0,0 +1,19 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108867, 2205995893, 0); // [time: 130ns -> 150ns] + read(15, 67108868, 486560095, 0); // [time: 150ns -> 160ns] + reset(); // [time: 200.001ns -> 210.001ns] + reset(); // [time: 210.001ns -> 220.001ns] + reset(); // [time: 220.001ns -> 230.001ns] + write(15, 67108867, 4100133660, 0); // [time: 270.001ns -> 290.001ns] + write(15, 67108868, 596618694, 0); // [time: 290.001ns -> 300.001ns] + reset(); // [time: 420.002ns -> 430.002ns] + reset(); // [time: 430.002ns -> 440.002ns] + reset(); // [time: 440.002ns -> 450.002ns] + write(15, 67108867, 3499942130, 0); // [time: 490.002ns -> 510.002ns] + write(15, 67108868, 2357711907, 0); // [time: 510.002ns -> 520.002ns] + read(15, 67108867, 3499942130, 0); // [time: 520.002ns -> 540.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_12_1.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_12_1.bi.expect new file mode 100644 index 00000000..7b49175b --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_12_1.bi.expect @@ -0,0 +1,19 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108867, 1833423740, 0); // [time: 130ns -> 150ns] + read(15, 67108864, 4073618608, 0); // [time: 150ns -> 160ns] + reset(); // [time: 200.001ns -> 210.001ns] + reset(); // [time: 210.001ns -> 220.001ns] + reset(); // [time: 220.001ns -> 230.001ns] + write(15, 67108867, 3418745219, 0); // [time: 270.001ns -> 290.001ns] + write(15, 67108864, 3757272308, 0); // [time: 290.001ns -> 300.001ns] + reset(); // [time: 420.002ns -> 430.002ns] + reset(); // [time: 430.002ns -> 440.002ns] + reset(); // [time: 440.002ns -> 450.002ns] + write(15, 67108867, 1325530178, 0); // [time: 490.002ns -> 510.002ns] + write(15, 67108864, 1451722922, 0); // [time: 510.002ns -> 520.002ns] + read(15, 67108867, 1325530178, 0); // [time: 520.002ns -> 540.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_12_2.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_12_2.bi.expect new file mode 100644 index 00000000..9971ed4a --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_12_2.bi.expect @@ -0,0 +1,19 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108867, 1016512136, 0); // [time: 130ns -> 150ns] + read(15, 67108868, 226204128, 0); // [time: 150ns -> 160ns] + reset(); // [time: 200.001ns -> 210.001ns] + reset(); // [time: 210.001ns -> 220.001ns] + reset(); // [time: 220.001ns -> 230.001ns] + write(15, 67108867, 2116565440, 0); // [time: 270.001ns -> 290.001ns] + write(15, 67108868, 2153688786, 0); // [time: 290.001ns -> 300.001ns] + reset(); // [time: 420.002ns -> 430.002ns] + reset(); // [time: 430.002ns -> 440.002ns] + reset(); // [time: 440.002ns -> 450.002ns] + write(15, 67108867, 1974223269, 0); // [time: 490.002ns -> 510.002ns] + write(15, 67108868, 1053640572, 0); // [time: 510.002ns -> 520.002ns] + read(15, 67108867, 1974223269, 0); // [time: 520.002ns -> 540.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_12_3.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_12_3.bi.expect new file mode 100644 index 00000000..11bf515e --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_12_3.bi.expect @@ -0,0 +1,19 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108867, 1509562552, 0); // [time: 130ns -> 150ns] + read(15, 67108868, 2329347035, 0); // [time: 150ns -> 160ns] + reset(); // [time: 200.001ns -> 210.001ns] + reset(); // [time: 210.001ns -> 220.001ns] + reset(); // [time: 220.001ns -> 230.001ns] + write(15, 67108867, 3862381389, 0); // [time: 270.001ns -> 290.001ns] + write(15, 67108868, 1142123500, 0); // [time: 290.001ns -> 300.001ns] + reset(); // [time: 420.002ns -> 430.002ns] + reset(); // [time: 430.002ns -> 440.002ns] + reset(); // [time: 440.002ns -> 450.002ns] + write(15, 67108867, 3598508010, 0); // [time: 490.002ns -> 510.002ns] + write(15, 67108868, 908644471, 0); // [time: 510.002ns -> 520.002ns] + read(15, 67108867, 3598508010, 0); // [time: 520.002ns -> 540.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_4_0.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_4_0.bi.expect new file mode 100644 index 00000000..5c52c496 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_4_0.bi.expect @@ -0,0 +1,19 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108865, 2950170166, 0); // [time: 130ns -> 150ns] + read(15, 67108866, 2782447364, 0); // [time: 150ns -> 160ns] + reset(); // [time: 200.001ns -> 210.001ns] + reset(); // [time: 210.001ns -> 220.001ns] + reset(); // [time: 220.001ns -> 230.001ns] + write(15, 67108865, 2586475175, 0); // [time: 270.001ns -> 290.001ns] + write(15, 67108866, 2087441910, 0); // [time: 290.001ns -> 300.001ns] + reset(); // [time: 420.002ns -> 430.002ns] + reset(); // [time: 430.002ns -> 440.002ns] + reset(); // [time: 440.002ns -> 450.002ns] + write(15, 67108865, 3875005491, 0); // [time: 490.002ns -> 510.002ns] + write(15, 67108866, 2597527218, 0); // [time: 510.002ns -> 520.002ns] + read(15, 67108865, 3875005491, 0); // [time: 520.002ns -> 540.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_4_1.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_4_1.bi.expect new file mode 100644 index 00000000..0ae4956e --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_4_1.bi.expect @@ -0,0 +1,19 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108865, 3580256271, 0); // [time: 130ns -> 150ns] + read(15, 67108866, 1489666683, 0); // [time: 150ns -> 160ns] + reset(); // [time: 200.001ns -> 210.001ns] + reset(); // [time: 210.001ns -> 220.001ns] + reset(); // [time: 220.001ns -> 230.001ns] + write(15, 67108865, 3677074643, 0); // [time: 270.001ns -> 290.001ns] + write(15, 67108866, 1878953054, 0); // [time: 290.001ns -> 300.001ns] + reset(); // [time: 420.002ns -> 430.002ns] + reset(); // [time: 430.002ns -> 440.002ns] + reset(); // [time: 440.002ns -> 450.002ns] + write(15, 67108865, 2965505115, 0); // [time: 490.002ns -> 510.002ns] + write(15, 67108866, 3259566096, 0); // [time: 510.002ns -> 520.002ns] + read(15, 67108865, 2965505115, 0); // [time: 520.002ns -> 540.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_4_2.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_4_2.bi.expect new file mode 100644 index 00000000..0ae4956e --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_4_2.bi.expect @@ -0,0 +1,19 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108865, 3580256271, 0); // [time: 130ns -> 150ns] + read(15, 67108866, 1489666683, 0); // [time: 150ns -> 160ns] + reset(); // [time: 200.001ns -> 210.001ns] + reset(); // [time: 210.001ns -> 220.001ns] + reset(); // [time: 220.001ns -> 230.001ns] + write(15, 67108865, 3677074643, 0); // [time: 270.001ns -> 290.001ns] + write(15, 67108866, 1878953054, 0); // [time: 290.001ns -> 300.001ns] + reset(); // [time: 420.002ns -> 430.002ns] + reset(); // [time: 430.002ns -> 440.002ns] + reset(); // [time: 440.002ns -> 450.002ns] + write(15, 67108865, 2965505115, 0); // [time: 490.002ns -> 510.002ns] + write(15, 67108866, 3259566096, 0); // [time: 510.002ns -> 520.002ns] + read(15, 67108865, 2965505115, 0); // [time: 520.002ns -> 540.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_4_3.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_4_3.bi.expect new file mode 100644 index 00000000..e2edd110 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_4_3.bi.expect @@ -0,0 +1,19 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108865, 3495738447, 0); // [time: 130ns -> 150ns] + read(15, 67108866, 1478546475, 0); // [time: 150ns -> 160ns] + reset(); // [time: 200.001ns -> 210.001ns] + reset(); // [time: 210.001ns -> 220.001ns] + reset(); // [time: 220.001ns -> 230.001ns] + write(15, 67108865, 2041778918, 0); // [time: 270.001ns -> 290.001ns] + write(15, 67108866, 3032895213, 0); // [time: 290.001ns -> 300.001ns] + reset(); // [time: 420.002ns -> 430.002ns] + reset(); // [time: 430.002ns -> 440.002ns] + reset(); // [time: 440.002ns -> 450.002ns] + write(15, 67108865, 2020268309, 0); // [time: 490.002ns -> 510.002ns] + write(15, 67108866, 3122719830, 0); // [time: 510.002ns -> 520.002ns] + read(15, 67108865, 2020268309, 0); // [time: 520.002ns -> 540.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_8_0.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_8_0.bi.expect new file mode 100644 index 00000000..d973d119 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_8_0.bi.expect @@ -0,0 +1,19 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108866, 2950170166, 0); // [time: 130ns -> 150ns] + read(15, 67108867, 2782447364, 0); // [time: 150ns -> 160ns] + reset(); // [time: 200.001ns -> 210.001ns] + reset(); // [time: 210.001ns -> 220.001ns] + reset(); // [time: 220.001ns -> 230.001ns] + write(15, 67108866, 2586475175, 0); // [time: 270.001ns -> 290.001ns] + write(15, 67108867, 2087441910, 0); // [time: 290.001ns -> 300.001ns] + reset(); // [time: 420.002ns -> 430.002ns] + reset(); // [time: 430.002ns -> 440.002ns] + reset(); // [time: 440.002ns -> 450.002ns] + write(15, 67108866, 3875005491, 0); // [time: 490.002ns -> 510.002ns] + write(15, 67108867, 2597527218, 0); // [time: 510.002ns -> 520.002ns] + read(15, 67108866, 3875005491, 0); // [time: 520.002ns -> 540.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_8_1.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_8_1.bi.expect new file mode 100644 index 00000000..b22b7107 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_8_1.bi.expect @@ -0,0 +1,19 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108866, 2205995893, 0); // [time: 130ns -> 150ns] + read(15, 67108867, 486560095, 0); // [time: 150ns -> 160ns] + reset(); // [time: 200.001ns -> 210.001ns] + reset(); // [time: 210.001ns -> 220.001ns] + reset(); // [time: 220.001ns -> 230.001ns] + write(15, 67108866, 4100133660, 0); // [time: 270.001ns -> 290.001ns] + write(15, 67108867, 596618694, 0); // [time: 290.001ns -> 300.001ns] + reset(); // [time: 420.002ns -> 430.002ns] + reset(); // [time: 430.002ns -> 440.002ns] + reset(); // [time: 440.002ns -> 450.002ns] + write(15, 67108866, 3499942130, 0); // [time: 490.002ns -> 510.002ns] + write(15, 67108867, 2357711907, 0); // [time: 510.002ns -> 520.002ns] + read(15, 67108866, 3499942130, 0); // [time: 520.002ns -> 540.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_8_2.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_8_2.bi.expect new file mode 100644 index 00000000..684182f5 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_8_2.bi.expect @@ -0,0 +1,19 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108866, 1016512136, 0); // [time: 130ns -> 150ns] + read(15, 67108867, 226204128, 0); // [time: 150ns -> 160ns] + reset(); // [time: 200.001ns -> 210.001ns] + reset(); // [time: 210.001ns -> 220.001ns] + reset(); // [time: 220.001ns -> 230.001ns] + write(15, 67108866, 2116565440, 0); // [time: 270.001ns -> 290.001ns] + write(15, 67108867, 2153688786, 0); // [time: 290.001ns -> 300.001ns] + reset(); // [time: 420.002ns -> 430.002ns] + reset(); // [time: 430.002ns -> 440.002ns] + reset(); // [time: 440.002ns -> 450.002ns] + write(15, 67108866, 1974223269, 0); // [time: 490.002ns -> 510.002ns] + write(15, 67108867, 1053640572, 0); // [time: 510.002ns -> 520.002ns] + read(15, 67108866, 1974223269, 0); // [time: 520.002ns -> 540.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_8_3.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_8_3.bi.expect new file mode 100644 index 00000000..2328e1f0 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_8_3.bi.expect @@ -0,0 +1,19 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108866, 1509562552, 0); // [time: 130ns -> 150ns] + read(15, 67108867, 2329347035, 0); // [time: 150ns -> 160ns] + reset(); // [time: 200.001ns -> 210.001ns] + reset(); // [time: 210.001ns -> 220.001ns] + reset(); // [time: 220.001ns -> 230.001ns] + write(15, 67108866, 3862381389, 0); // [time: 270.001ns -> 290.001ns] + write(15, 67108867, 1142123500, 0); // [time: 290.001ns -> 300.001ns] + reset(); // [time: 420.002ns -> 430.002ns] + reset(); // [time: 430.002ns -> 440.002ns] + reset(); // [time: 440.002ns -> 450.002ns] + write(15, 67108866, 3598508010, 0); // [time: 490.002ns -> 510.002ns] + write(15, 67108867, 908644471, 0); // [time: 510.002ns -> 520.002ns] + read(15, 67108866, 3598508010, 0); // [time: 520.002ns -> 540.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_0_0.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_0_0.bi.expect new file mode 100644 index 00000000..866952c5 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_0_0.bi.expect @@ -0,0 +1,25 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108864, 2205995893, 0); // [time: 170ns -> 190ns] + read(15, 67108865, 486560095, 0); // [time: 190ns -> 200ns] + read(15, 67108866, 4100133660, 0); // [time: 200ns -> 210ns] + read(15, 67108867, 596618694, 0); // [time: 210ns -> 220ns] + reset(); // [time: 260.001ns -> 270.001ns] + reset(); // [time: 270.001ns -> 280.001ns] + reset(); // [time: 280.001ns -> 290.001ns] + write(15, 67108864, 3499942130, 0); // [time: 330.001ns -> 350.001ns] + write(15, 67108865, 2357711907, 0); // [time: 350.001ns -> 360.001ns] + write(15, 67108866, 2086526797, 0); // [time: 360.001ns -> 370.001ns] + write(15, 67108867, 364077448, 0); // [time: 370.001ns -> 380.001ns] + reset(); // [time: 580.002ns -> 590.002ns] + reset(); // [time: 590.002ns -> 600.002ns] + reset(); // [time: 600.002ns -> 610.002ns] + write(15, 67108864, 210674739, 0); // [time: 650.002ns -> 670.002ns] + write(15, 67108865, 1567286535, 0); // [time: 670.002ns -> 680.002ns] + write(15, 67108866, 922799025, 0); // [time: 680.002ns -> 690.002ns] + write(15, 67108867, 4171757579, 0); // [time: 690.002ns -> 700.002ns] + read(15, 67108864, 210674739, 0); // [time: 700.002ns -> 720.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_0_1.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_0_1.bi.expect new file mode 100644 index 00000000..0c3bcb95 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_0_1.bi.expect @@ -0,0 +1,25 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108864, 1833423740, 0); // [time: 170ns -> 190ns] + read(15, 67108865, 4073618608, 0); // [time: 190ns -> 200ns] + read(15, 67108866, 3418745219, 0); // [time: 200ns -> 210ns] + read(15, 67108867, 3757272308, 0); // [time: 210ns -> 220ns] + reset(); // [time: 260.001ns -> 270.001ns] + reset(); // [time: 270.001ns -> 280.001ns] + reset(); // [time: 280.001ns -> 290.001ns] + write(15, 67108864, 1325530178, 0); // [time: 330.001ns -> 350.001ns] + write(15, 67108865, 1451722922, 0); // [time: 350.001ns -> 360.001ns] + write(15, 67108866, 1997677454, 0); // [time: 360.001ns -> 370.001ns] + write(15, 67108867, 986005841, 0); // [time: 370.001ns -> 380.001ns] + reset(); // [time: 580.002ns -> 590.002ns] + reset(); // [time: 590.002ns -> 600.002ns] + reset(); // [time: 600.002ns -> 610.002ns] + write(15, 67108864, 789975088, 0); // [time: 650.002ns -> 670.002ns] + write(15, 67108865, 3746918692, 0); // [time: 670.002ns -> 680.002ns] + write(15, 67108866, 410224063, 0); // [time: 680.002ns -> 690.002ns] + write(15, 67108867, 864118294, 0); // [time: 690.002ns -> 700.002ns] + read(15, 67108864, 789975088, 0); // [time: 700.002ns -> 720.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_0_2.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_0_2.bi.expect new file mode 100644 index 00000000..17c05629 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_0_2.bi.expect @@ -0,0 +1,25 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108864, 869832817, 0); // [time: 170ns -> 190ns] + read(15, 67108865, 2976082601, 0); // [time: 190ns -> 200ns] + read(15, 67108866, 373695501, 0); // [time: 200ns -> 210ns] + read(15, 67108867, 2110838384, 0); // [time: 210ns -> 220ns] + reset(); // [time: 260.001ns -> 270.001ns] + reset(); // [time: 270.001ns -> 280.001ns] + reset(); // [time: 280.001ns -> 290.001ns] + write(15, 67108864, 3556455435, 0); // [time: 330.001ns -> 350.001ns] + write(15, 67108865, 1804567173, 0); // [time: 350.001ns -> 360.001ns] + write(15, 67108866, 1187331577, 0); // [time: 360.001ns -> 370.001ns] + write(15, 67108867, 1293993917, 0); // [time: 370.001ns -> 380.001ns] + reset(); // [time: 580.002ns -> 590.002ns] + reset(); // [time: 590.002ns -> 600.002ns] + reset(); // [time: 600.002ns -> 610.002ns] + write(15, 67108864, 753581369, 0); // [time: 650.002ns -> 670.002ns] + write(15, 67108865, 2300246917, 0); // [time: 670.002ns -> 680.002ns] + write(15, 67108866, 3523846629, 0); // [time: 680.002ns -> 690.002ns] + write(15, 67108867, 3751494934, 0); // [time: 690.002ns -> 700.002ns] + read(15, 67108864, 753581369, 0); // [time: 700.002ns -> 720.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_0_3.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_0_3.bi.expect new file mode 100644 index 00000000..7251b862 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_0_3.bi.expect @@ -0,0 +1,25 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108864, 1509562552, 0); // [time: 170ns -> 190ns] + read(15, 67108865, 2329347035, 0); // [time: 190ns -> 200ns] + read(15, 67108866, 3862381389, 0); // [time: 200ns -> 210ns] + read(15, 67108867, 1142123500, 0); // [time: 210ns -> 220ns] + reset(); // [time: 260.001ns -> 270.001ns] + reset(); // [time: 270.001ns -> 280.001ns] + reset(); // [time: 280.001ns -> 290.001ns] + write(15, 67108864, 3598508010, 0); // [time: 330.001ns -> 350.001ns] + write(15, 67108865, 908644471, 0); // [time: 350.001ns -> 360.001ns] + write(15, 67108866, 870782326, 0); // [time: 360.001ns -> 370.001ns] + write(15, 67108867, 1788061457, 0); // [time: 370.001ns -> 380.001ns] + reset(); // [time: 580.002ns -> 590.002ns] + reset(); // [time: 590.002ns -> 600.002ns] + reset(); // [time: 600.002ns -> 610.002ns] + write(15, 67108864, 1483205141, 0); // [time: 650.002ns -> 670.002ns] + write(15, 67108865, 408872453, 0); // [time: 670.002ns -> 680.002ns] + write(15, 67108866, 2880683308, 0); // [time: 680.002ns -> 690.002ns] + write(15, 67108867, 1446265757, 0); // [time: 690.002ns -> 700.002ns] + read(15, 67108864, 1483205141, 0); // [time: 700.002ns -> 720.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_12_0.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_12_0.bi.expect new file mode 100644 index 00000000..74443970 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_12_0.bi.expect @@ -0,0 +1,25 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108867, 518534189, 0); // [time: 170ns -> 190ns] + read(15, 67108868, 844695266, 0); // [time: 190ns -> 200ns] + read(15, 67108869, 3937184150, 0); // [time: 200ns -> 210ns] + read(15, 67108870, 444246851, 0); // [time: 210ns -> 220ns] + reset(); // [time: 260.001ns -> 270.001ns] + reset(); // [time: 270.001ns -> 280.001ns] + reset(); // [time: 280.001ns -> 290.001ns] + write(15, 67108867, 3220682802, 0); // [time: 330.001ns -> 350.001ns] + write(15, 67108868, 2130811954, 0); // [time: 350.001ns -> 360.001ns] + write(15, 67108869, 2002127438, 0); // [time: 360.001ns -> 370.001ns] + write(15, 67108870, 493792053, 0); // [time: 370.001ns -> 380.001ns] + reset(); // [time: 580.002ns -> 590.002ns] + reset(); // [time: 590.002ns -> 600.002ns] + reset(); // [time: 600.002ns -> 610.002ns] + write(15, 67108867, 63714206, 0); // [time: 650.002ns -> 670.002ns] + write(15, 67108868, 2091823691, 0); // [time: 670.002ns -> 680.002ns] + write(15, 67108869, 3903276977, 0); // [time: 680.002ns -> 690.002ns] + write(15, 67108870, 1662756337, 0); // [time: 690.002ns -> 700.002ns] + read(15, 67108867, 63714206, 0); // [time: 700.002ns -> 720.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_12_1.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_12_1.bi.expect new file mode 100644 index 00000000..f3104619 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_12_1.bi.expect @@ -0,0 +1,25 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108867, 2821946881, 0); // [time: 170ns -> 190ns] + read(15, 67108864, 4080087070, 0); // [time: 190ns -> 200ns] + read(15, 67108865, 2243193877, 0); // [time: 200ns -> 210ns] + read(15, 67108866, 2472849580, 0); // [time: 210ns -> 220ns] + reset(); // [time: 260.001ns -> 270.001ns] + reset(); // [time: 270.001ns -> 280.001ns] + reset(); // [time: 280.001ns -> 290.001ns] + write(15, 67108867, 3565370026, 0); // [time: 330.001ns -> 350.001ns] + write(15, 67108864, 890985600, 0); // [time: 350.001ns -> 360.001ns] + write(15, 67108865, 4179549189, 0); // [time: 360.001ns -> 370.001ns] + write(15, 67108866, 4158632492, 0); // [time: 370.001ns -> 380.001ns] + reset(); // [time: 580.002ns -> 590.002ns] + reset(); // [time: 590.002ns -> 600.002ns] + reset(); // [time: 600.002ns -> 610.002ns] + write(15, 67108867, 3744957516, 0); // [time: 650.002ns -> 670.002ns] + write(15, 67108864, 2300150418, 0); // [time: 670.002ns -> 680.002ns] + write(15, 67108865, 2081940992, 0); // [time: 680.002ns -> 690.002ns] + write(15, 67108866, 1697819148, 0); // [time: 690.002ns -> 700.002ns] + read(15, 67108867, 3744957516, 0); // [time: 700.002ns -> 720.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_12_2.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_12_2.bi.expect new file mode 100644 index 00000000..96a45f4c --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_12_2.bi.expect @@ -0,0 +1,25 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108867, 1016512136, 0); // [time: 170ns -> 190ns] + read(15, 67108868, 226204128, 0); // [time: 190ns -> 200ns] + read(15, 67108869, 2116565440, 0); // [time: 200ns -> 210ns] + read(15, 67108870, 2153688786, 0); // [time: 210ns -> 220ns] + reset(); // [time: 260.001ns -> 270.001ns] + reset(); // [time: 270.001ns -> 280.001ns] + reset(); // [time: 280.001ns -> 290.001ns] + write(15, 67108867, 1974223269, 0); // [time: 330.001ns -> 350.001ns] + write(15, 67108868, 1053640572, 0); // [time: 350.001ns -> 360.001ns] + write(15, 67108869, 2079860600, 0); // [time: 360.001ns -> 370.001ns] + write(15, 67108870, 3550045624, 0); // [time: 370.001ns -> 380.001ns] + reset(); // [time: 580.002ns -> 590.002ns] + reset(); // [time: 590.002ns -> 600.002ns] + reset(); // [time: 600.002ns -> 610.002ns] + write(15, 67108867, 1038322047, 0); // [time: 650.002ns -> 670.002ns] + write(15, 67108868, 1502718053, 0); // [time: 670.002ns -> 680.002ns] + write(15, 67108869, 1367070343, 0); // [time: 680.002ns -> 690.002ns] + write(15, 67108870, 3425882885, 0); // [time: 690.002ns -> 700.002ns] + read(15, 67108867, 1038322047, 0); // [time: 700.002ns -> 720.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_12_3.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_12_3.bi.expect new file mode 100644 index 00000000..372b11fb --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_12_3.bi.expect @@ -0,0 +1,25 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108867, 1509562552, 0); // [time: 170ns -> 190ns] + read(15, 67108868, 2329347035, 0); // [time: 190ns -> 200ns] + read(15, 67108869, 3862381389, 0); // [time: 200ns -> 210ns] + read(15, 67108870, 1142123500, 0); // [time: 210ns -> 220ns] + reset(); // [time: 260.001ns -> 270.001ns] + reset(); // [time: 270.001ns -> 280.001ns] + reset(); // [time: 280.001ns -> 290.001ns] + write(15, 67108867, 3598508010, 0); // [time: 330.001ns -> 350.001ns] + write(15, 67108868, 908644471, 0); // [time: 350.001ns -> 360.001ns] + write(15, 67108869, 870782326, 0); // [time: 360.001ns -> 370.001ns] + write(15, 67108870, 1788061457, 0); // [time: 370.001ns -> 380.001ns] + reset(); // [time: 580.002ns -> 590.002ns] + reset(); // [time: 590.002ns -> 600.002ns] + reset(); // [time: 600.002ns -> 610.002ns] + write(15, 67108867, 1483205141, 0); // [time: 650.002ns -> 670.002ns] + write(15, 67108868, 408872453, 0); // [time: 670.002ns -> 680.002ns] + write(15, 67108869, 2880683308, 0); // [time: 680.002ns -> 690.002ns] + write(15, 67108870, 1446265757, 0); // [time: 690.002ns -> 700.002ns] + read(15, 67108867, 1483205141, 0); // [time: 700.002ns -> 720.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_4_0.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_4_0.bi.expect new file mode 100644 index 00000000..28cf4257 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_4_0.bi.expect @@ -0,0 +1,25 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108865, 1833423740, 0); // [time: 170ns -> 190ns] + read(15, 67108866, 4073618608, 0); // [time: 190ns -> 200ns] + read(15, 67108867, 3418745219, 0); // [time: 200ns -> 210ns] + read(15, 67108868, 3757272308, 0); // [time: 210ns -> 220ns] + reset(); // [time: 260.001ns -> 270.001ns] + reset(); // [time: 270.001ns -> 280.001ns] + reset(); // [time: 280.001ns -> 290.001ns] + write(15, 67108865, 1325530178, 0); // [time: 330.001ns -> 350.001ns] + write(15, 67108866, 1451722922, 0); // [time: 350.001ns -> 360.001ns] + write(15, 67108867, 1997677454, 0); // [time: 360.001ns -> 370.001ns] + write(15, 67108868, 986005841, 0); // [time: 370.001ns -> 380.001ns] + reset(); // [time: 580.002ns -> 590.002ns] + reset(); // [time: 590.002ns -> 600.002ns] + reset(); // [time: 600.002ns -> 610.002ns] + write(15, 67108865, 789975088, 0); // [time: 650.002ns -> 670.002ns] + write(15, 67108866, 3746918692, 0); // [time: 670.002ns -> 680.002ns] + write(15, 67108867, 410224063, 0); // [time: 680.002ns -> 690.002ns] + write(15, 67108868, 864118294, 0); // [time: 690.002ns -> 700.002ns] + read(15, 67108865, 789975088, 0); // [time: 700.002ns -> 720.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_4_1.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_4_1.bi.expect new file mode 100644 index 00000000..50109ac8 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_4_1.bi.expect @@ -0,0 +1,25 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108865, 518534189, 0); // [time: 170ns -> 190ns] + read(15, 67108866, 844695266, 0); // [time: 190ns -> 200ns] + read(15, 67108867, 3937184150, 0); // [time: 200ns -> 210ns] + read(15, 67108864, 444246851, 0); // [time: 210ns -> 220ns] + reset(); // [time: 260.001ns -> 270.001ns] + reset(); // [time: 270.001ns -> 280.001ns] + reset(); // [time: 280.001ns -> 290.001ns] + write(15, 67108865, 3220682802, 0); // [time: 330.001ns -> 350.001ns] + write(15, 67108866, 2130811954, 0); // [time: 350.001ns -> 360.001ns] + write(15, 67108867, 2002127438, 0); // [time: 360.001ns -> 370.001ns] + write(15, 67108864, 493792053, 0); // [time: 370.001ns -> 380.001ns] + reset(); // [time: 580.002ns -> 590.002ns] + reset(); // [time: 590.002ns -> 600.002ns] + reset(); // [time: 600.002ns -> 610.002ns] + write(15, 67108865, 63714206, 0); // [time: 650.002ns -> 670.002ns] + write(15, 67108866, 2091823691, 0); // [time: 670.002ns -> 680.002ns] + write(15, 67108867, 3903276977, 0); // [time: 680.002ns -> 690.002ns] + write(15, 67108864, 1662756337, 0); // [time: 690.002ns -> 700.002ns] + read(15, 67108865, 63714206, 0); // [time: 700.002ns -> 720.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_4_2.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_4_2.bi.expect new file mode 100644 index 00000000..110541f7 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_4_2.bi.expect @@ -0,0 +1,25 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108865, 869832817, 0); // [time: 170ns -> 190ns] + read(15, 67108866, 2976082601, 0); // [time: 190ns -> 200ns] + read(15, 67108867, 373695501, 0); // [time: 200ns -> 210ns] + read(15, 67108868, 2110838384, 0); // [time: 210ns -> 220ns] + reset(); // [time: 260.001ns -> 270.001ns] + reset(); // [time: 270.001ns -> 280.001ns] + reset(); // [time: 280.001ns -> 290.001ns] + write(15, 67108865, 3556455435, 0); // [time: 330.001ns -> 350.001ns] + write(15, 67108866, 1804567173, 0); // [time: 350.001ns -> 360.001ns] + write(15, 67108867, 1187331577, 0); // [time: 360.001ns -> 370.001ns] + write(15, 67108868, 1293993917, 0); // [time: 370.001ns -> 380.001ns] + reset(); // [time: 580.002ns -> 590.002ns] + reset(); // [time: 590.002ns -> 600.002ns] + reset(); // [time: 600.002ns -> 610.002ns] + write(15, 67108865, 753581369, 0); // [time: 650.002ns -> 670.002ns] + write(15, 67108866, 2300246917, 0); // [time: 670.002ns -> 680.002ns] + write(15, 67108867, 3523846629, 0); // [time: 680.002ns -> 690.002ns] + write(15, 67108868, 3751494934, 0); // [time: 690.002ns -> 700.002ns] + read(15, 67108865, 753581369, 0); // [time: 700.002ns -> 720.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_4_3.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_4_3.bi.expect new file mode 100644 index 00000000..c525398d --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_4_3.bi.expect @@ -0,0 +1,25 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108865, 1509562552, 0); // [time: 170ns -> 190ns] + read(15, 67108866, 2329347035, 0); // [time: 190ns -> 200ns] + read(15, 67108867, 3862381389, 0); // [time: 200ns -> 210ns] + read(15, 67108868, 1142123500, 0); // [time: 210ns -> 220ns] + reset(); // [time: 260.001ns -> 270.001ns] + reset(); // [time: 270.001ns -> 280.001ns] + reset(); // [time: 280.001ns -> 290.001ns] + write(15, 67108865, 3598508010, 0); // [time: 330.001ns -> 350.001ns] + write(15, 67108866, 908644471, 0); // [time: 350.001ns -> 360.001ns] + write(15, 67108867, 870782326, 0); // [time: 360.001ns -> 370.001ns] + write(15, 67108868, 1788061457, 0); // [time: 370.001ns -> 380.001ns] + reset(); // [time: 580.002ns -> 590.002ns] + reset(); // [time: 590.002ns -> 600.002ns] + reset(); // [time: 600.002ns -> 610.002ns] + write(15, 67108865, 1483205141, 0); // [time: 650.002ns -> 670.002ns] + write(15, 67108866, 408872453, 0); // [time: 670.002ns -> 680.002ns] + write(15, 67108867, 2880683308, 0); // [time: 680.002ns -> 690.002ns] + write(15, 67108868, 1446265757, 0); // [time: 690.002ns -> 700.002ns] + read(15, 67108865, 1483205141, 0); // [time: 700.002ns -> 720.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_8_0.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_8_0.bi.expect new file mode 100644 index 00000000..6d06914b --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_8_0.bi.expect @@ -0,0 +1,25 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108866, 1833423740, 0); // [time: 170ns -> 190ns] + read(15, 67108867, 4073618608, 0); // [time: 190ns -> 200ns] + read(15, 67108868, 3418745219, 0); // [time: 200ns -> 210ns] + read(15, 67108869, 3757272308, 0); // [time: 210ns -> 220ns] + reset(); // [time: 260.001ns -> 270.001ns] + reset(); // [time: 270.001ns -> 280.001ns] + reset(); // [time: 280.001ns -> 290.001ns] + write(15, 67108866, 1325530178, 0); // [time: 330.001ns -> 350.001ns] + write(15, 67108867, 1451722922, 0); // [time: 350.001ns -> 360.001ns] + write(15, 67108868, 1997677454, 0); // [time: 360.001ns -> 370.001ns] + write(15, 67108869, 986005841, 0); // [time: 370.001ns -> 380.001ns] + reset(); // [time: 580.002ns -> 590.002ns] + reset(); // [time: 590.002ns -> 600.002ns] + reset(); // [time: 600.002ns -> 610.002ns] + write(15, 67108866, 789975088, 0); // [time: 650.002ns -> 670.002ns] + write(15, 67108867, 3746918692, 0); // [time: 670.002ns -> 680.002ns] + write(15, 67108868, 410224063, 0); // [time: 680.002ns -> 690.002ns] + write(15, 67108869, 864118294, 0); // [time: 690.002ns -> 700.002ns] + read(15, 67108866, 789975088, 0); // [time: 700.002ns -> 720.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_8_1.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_8_1.bi.expect new file mode 100644 index 00000000..e58197ce --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_8_1.bi.expect @@ -0,0 +1,25 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108866, 518534189, 0); // [time: 170ns -> 190ns] + read(15, 67108867, 844695266, 0); // [time: 190ns -> 200ns] + read(15, 67108864, 3937184150, 0); // [time: 200ns -> 210ns] + read(15, 67108865, 444246851, 0); // [time: 210ns -> 220ns] + reset(); // [time: 260.001ns -> 270.001ns] + reset(); // [time: 270.001ns -> 280.001ns] + reset(); // [time: 280.001ns -> 290.001ns] + write(15, 67108866, 3220682802, 0); // [time: 330.001ns -> 350.001ns] + write(15, 67108867, 2130811954, 0); // [time: 350.001ns -> 360.001ns] + write(15, 67108864, 2002127438, 0); // [time: 360.001ns -> 370.001ns] + write(15, 67108865, 493792053, 0); // [time: 370.001ns -> 380.001ns] + reset(); // [time: 580.002ns -> 590.002ns] + reset(); // [time: 590.002ns -> 600.002ns] + reset(); // [time: 600.002ns -> 610.002ns] + write(15, 67108866, 63714206, 0); // [time: 650.002ns -> 670.002ns] + write(15, 67108867, 2091823691, 0); // [time: 670.002ns -> 680.002ns] + write(15, 67108864, 3903276977, 0); // [time: 680.002ns -> 690.002ns] + write(15, 67108865, 1662756337, 0); // [time: 690.002ns -> 700.002ns] + read(15, 67108866, 63714206, 0); // [time: 700.002ns -> 720.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_8_2.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_8_2.bi.expect new file mode 100644 index 00000000..9c8093c8 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_8_2.bi.expect @@ -0,0 +1,25 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108866, 1016512136, 0); // [time: 170ns -> 190ns] + read(15, 67108867, 226204128, 0); // [time: 190ns -> 200ns] + read(15, 67108868, 2116565440, 0); // [time: 200ns -> 210ns] + read(15, 67108869, 2153688786, 0); // [time: 210ns -> 220ns] + reset(); // [time: 260.001ns -> 270.001ns] + reset(); // [time: 270.001ns -> 280.001ns] + reset(); // [time: 280.001ns -> 290.001ns] + write(15, 67108866, 1974223269, 0); // [time: 330.001ns -> 350.001ns] + write(15, 67108867, 1053640572, 0); // [time: 350.001ns -> 360.001ns] + write(15, 67108868, 2079860600, 0); // [time: 360.001ns -> 370.001ns] + write(15, 67108869, 3550045624, 0); // [time: 370.001ns -> 380.001ns] + reset(); // [time: 580.002ns -> 590.002ns] + reset(); // [time: 590.002ns -> 600.002ns] + reset(); // [time: 600.002ns -> 610.002ns] + write(15, 67108866, 1038322047, 0); // [time: 650.002ns -> 670.002ns] + write(15, 67108867, 1502718053, 0); // [time: 670.002ns -> 680.002ns] + write(15, 67108868, 1367070343, 0); // [time: 680.002ns -> 690.002ns] + write(15, 67108869, 3425882885, 0); // [time: 690.002ns -> 700.002ns] + read(15, 67108866, 1038322047, 0); // [time: 700.002ns -> 720.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_8_3.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_8_3.bi.expect new file mode 100644 index 00000000..cc76cf64 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_8_3.bi.expect @@ -0,0 +1,25 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108866, 1070372987, 0); // [time: 170ns -> 190ns] + read(15, 67108867, 2645947069, 0); // [time: 190ns -> 200ns] + read(15, 67108868, 736643984, 0); // [time: 200ns -> 210ns] + read(15, 67108869, 192007203, 0); // [time: 210ns -> 220ns] + reset(); // [time: 260.001ns -> 270.001ns] + reset(); // [time: 270.001ns -> 280.001ns] + reset(); // [time: 280.001ns -> 290.001ns] + write(15, 67108866, 1925400290, 0); // [time: 330.001ns -> 350.001ns] + write(15, 67108867, 1309609983, 0); // [time: 350.001ns -> 360.001ns] + write(15, 67108868, 58503546, 0); // [time: 360.001ns -> 370.001ns] + write(15, 67108869, 3861022989, 0); // [time: 370.001ns -> 380.001ns] + reset(); // [time: 580.002ns -> 590.002ns] + reset(); // [time: 590.002ns -> 600.002ns] + reset(); // [time: 600.002ns -> 610.002ns] + write(15, 67108866, 1725708128, 0); // [time: 650.002ns -> 670.002ns] + write(15, 67108867, 3760744365, 0); // [time: 670.002ns -> 680.002ns] + write(15, 67108868, 3803789590, 0); // [time: 680.002ns -> 690.002ns] + write(15, 67108869, 2647121574, 0); // [time: 690.002ns -> 700.002ns] + read(15, 67108866, 1725708128, 0); // [time: 700.002ns -> 720.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_0_0.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_0_0.bi.expect new file mode 100644 index 00000000..66d2bc8e --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_0_0.bi.expect @@ -0,0 +1,37 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108864, 518534189, 0); // [time: 250ns -> 270ns] + read(15, 67108865, 844695266, 0); // [time: 270ns -> 280ns] + read(15, 67108866, 3937184150, 0); // [time: 280ns -> 290ns] + read(15, 67108867, 444246851, 0); // [time: 290ns -> 300ns] + read(15, 67108868, 3220682802, 0); // [time: 300ns -> 310ns] + read(15, 67108869, 2130811954, 0); // [time: 310ns -> 320ns] + read(15, 67108870, 2002127438, 0); // [time: 320ns -> 330ns] + read(15, 67108871, 493792053, 0); // [time: 330ns -> 340ns] + reset(); // [time: 380.001ns -> 390.001ns] + reset(); // [time: 390.001ns -> 400.001ns] + reset(); // [time: 400.001ns -> 410.001ns] + write(15, 67108864, 63714206, 0); // [time: 450.001ns -> 470.001ns] + write(15, 67108865, 2091823691, 0); // [time: 470.001ns -> 480.001ns] + write(15, 67108866, 3903276977, 0); // [time: 480.001ns -> 490.001ns] + write(15, 67108867, 1662756337, 0); // [time: 490.001ns -> 500.001ns] + write(15, 67108868, 4101310419, 0); // [time: 500.001ns -> 510.001ns] + write(15, 67108869, 903798156, 0); // [time: 510.001ns -> 520.001ns] + write(15, 67108870, 3840476340, 0); // [time: 520.001ns -> 530.001ns] + write(15, 67108871, 2244097975, 0); // [time: 530.001ns -> 540.001ns] + reset(); // [time: 900.002ns -> 910.002ns] + reset(); // [time: 910.002ns -> 920.002ns] + reset(); // [time: 920.002ns -> 930.002ns] + write(15, 67108864, 3956643922, 0); // [time: 970.002ns -> 990.002ns] + write(15, 67108865, 2115347845, 0); // [time: 990.002ns -> 1000.002ns] + write(15, 67108866, 1775201107, 0); // [time: 1000.002ns -> 1010.002ns] + write(15, 67108867, 1046910518, 0); // [time: 1010.002ns -> 1020.002ns] + write(15, 67108868, 345998276, 0); // [time: 1020.002ns -> 1030.002ns] + write(15, 67108869, 2089777588, 0); // [time: 1030.002ns -> 1040.002ns] + write(15, 67108870, 3110941387, 0); // [time: 1040.002ns -> 1050.002ns] + write(15, 67108871, 3151493219, 0); // [time: 1050.002ns -> 1060.002ns] + read(15, 67108864, 3956643922, 0); // [time: 1060.002ns -> 1080.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_0_1.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_0_1.bi.expect new file mode 100644 index 00000000..bc132178 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_0_1.bi.expect @@ -0,0 +1,37 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108864, 2821946881, 0); // [time: 250ns -> 270ns] + read(15, 67108865, 4080087070, 0); // [time: 270ns -> 280ns] + read(15, 67108866, 2243193877, 0); // [time: 280ns -> 290ns] + read(15, 67108867, 2472849580, 0); // [time: 290ns -> 300ns] + read(15, 67108868, 3565370026, 0); // [time: 300ns -> 310ns] + read(15, 67108869, 890985600, 0); // [time: 310ns -> 320ns] + read(15, 67108870, 4179549189, 0); // [time: 320ns -> 330ns] + read(15, 67108871, 4158632492, 0); // [time: 330ns -> 340ns] + reset(); // [time: 380.001ns -> 390.001ns] + reset(); // [time: 390.001ns -> 400.001ns] + reset(); // [time: 400.001ns -> 410.001ns] + write(15, 67108864, 3744957516, 0); // [time: 450.001ns -> 470.001ns] + write(15, 67108865, 2300150418, 0); // [time: 470.001ns -> 480.001ns] + write(15, 67108866, 2081940992, 0); // [time: 480.001ns -> 490.001ns] + write(15, 67108867, 1697819148, 0); // [time: 490.001ns -> 500.001ns] + write(15, 67108868, 602241333, 0); // [time: 500.001ns -> 510.001ns] + write(15, 67108869, 2260552922, 0); // [time: 510.001ns -> 520.001ns] + write(15, 67108870, 4251564751, 0); // [time: 520.001ns -> 530.001ns] + write(15, 67108871, 3326548024, 0); // [time: 530.001ns -> 540.001ns] + reset(); // [time: 900.002ns -> 910.002ns] + reset(); // [time: 910.002ns -> 920.002ns] + reset(); // [time: 920.002ns -> 930.002ns] + write(15, 67108864, 1044044861, 0); // [time: 970.002ns -> 990.002ns] + write(15, 67108865, 4177314760, 0); // [time: 990.002ns -> 1000.002ns] + write(15, 67108866, 4253662683, 0); // [time: 1000.002ns -> 1010.002ns] + write(15, 67108867, 3575602093, 0); // [time: 1010.002ns -> 1020.002ns] + write(15, 67108868, 667576938, 0); // [time: 1020.002ns -> 1030.002ns] + write(15, 67108869, 3110079964, 0); // [time: 1030.002ns -> 1040.002ns] + write(15, 67108870, 3758039968, 0); // [time: 1040.002ns -> 1050.002ns] + write(15, 67108871, 3566852678, 0); // [time: 1050.002ns -> 1060.002ns] + read(15, 67108864, 1044044861, 0); // [time: 1060.002ns -> 1080.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_0_2.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_0_2.bi.expect new file mode 100644 index 00000000..37006294 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_0_2.bi.expect @@ -0,0 +1,37 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108864, 869832817, 0); // [time: 250ns -> 270ns] + read(15, 67108865, 2976082601, 0); // [time: 270ns -> 280ns] + read(15, 67108866, 373695501, 0); // [time: 280ns -> 290ns] + read(15, 67108867, 2110838384, 0); // [time: 290ns -> 300ns] + read(15, 67108868, 3556455435, 0); // [time: 300ns -> 310ns] + read(15, 67108869, 1804567173, 0); // [time: 310ns -> 320ns] + read(15, 67108870, 1187331577, 0); // [time: 320ns -> 330ns] + read(15, 67108871, 1293993917, 0); // [time: 330ns -> 340ns] + reset(); // [time: 380.001ns -> 390.001ns] + reset(); // [time: 390.001ns -> 400.001ns] + reset(); // [time: 400.001ns -> 410.001ns] + write(15, 67108864, 753581369, 0); // [time: 450.001ns -> 470.001ns] + write(15, 67108865, 2300246917, 0); // [time: 470.001ns -> 480.001ns] + write(15, 67108866, 3523846629, 0); // [time: 480.001ns -> 490.001ns] + write(15, 67108867, 3751494934, 0); // [time: 490.001ns -> 500.001ns] + write(15, 67108868, 504397671, 0); // [time: 500.001ns -> 510.001ns] + write(15, 67108869, 3203321461, 0); // [time: 510.001ns -> 520.001ns] + write(15, 67108870, 3801714021, 0); // [time: 520.001ns -> 530.001ns] + write(15, 67108871, 654543662, 0); // [time: 530.001ns -> 540.001ns] + reset(); // [time: 900.002ns -> 910.002ns] + reset(); // [time: 910.002ns -> 920.002ns] + reset(); // [time: 920.002ns -> 930.002ns] + write(15, 67108864, 1829143953, 0); // [time: 970.002ns -> 990.002ns] + write(15, 67108865, 2746894674, 0); // [time: 990.002ns -> 1000.002ns] + write(15, 67108866, 3464933947, 0); // [time: 1000.002ns -> 1010.002ns] + write(15, 67108867, 3350075041, 0); // [time: 1010.002ns -> 1020.002ns] + write(15, 67108868, 1123364414, 0); // [time: 1020.002ns -> 1030.002ns] + write(15, 67108869, 3896266205, 0); // [time: 1030.002ns -> 1040.002ns] + write(15, 67108870, 3668919860, 0); // [time: 1040.002ns -> 1050.002ns] + write(15, 67108871, 177490457, 0); // [time: 1050.002ns -> 1060.002ns] + read(15, 67108864, 1829143953, 0); // [time: 1060.002ns -> 1080.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_0_3.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_0_3.bi.expect new file mode 100644 index 00000000..60d1cc31 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_0_3.bi.expect @@ -0,0 +1,37 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108864, 1070372987, 0); // [time: 250ns -> 270ns] + read(15, 67108865, 2645947069, 0); // [time: 270ns -> 280ns] + read(15, 67108866, 736643984, 0); // [time: 280ns -> 290ns] + read(15, 67108867, 192007203, 0); // [time: 290ns -> 300ns] + read(15, 67108868, 1925400290, 0); // [time: 300ns -> 310ns] + read(15, 67108869, 1309609983, 0); // [time: 310ns -> 320ns] + read(15, 67108870, 58503546, 0); // [time: 320ns -> 330ns] + read(15, 67108871, 3861022989, 0); // [time: 330ns -> 340ns] + reset(); // [time: 380.001ns -> 390.001ns] + reset(); // [time: 390.001ns -> 400.001ns] + reset(); // [time: 400.001ns -> 410.001ns] + write(15, 67108864, 1725708128, 0); // [time: 450.001ns -> 470.001ns] + write(15, 67108865, 3760744365, 0); // [time: 470.001ns -> 480.001ns] + write(15, 67108866, 3803789590, 0); // [time: 480.001ns -> 490.001ns] + write(15, 67108867, 2647121574, 0); // [time: 490.001ns -> 500.001ns] + write(15, 67108868, 336117328, 0); // [time: 500.001ns -> 510.001ns] + write(15, 67108869, 3984726565, 0); // [time: 510.001ns -> 520.001ns] + write(15, 67108870, 104808193, 0); // [time: 520.001ns -> 530.001ns] + write(15, 67108871, 2315494688, 0); // [time: 530.001ns -> 540.001ns] + reset(); // [time: 900.002ns -> 910.002ns] + reset(); // [time: 910.002ns -> 920.002ns] + reset(); // [time: 920.002ns -> 930.002ns] + write(15, 67108864, 3997204021, 0); // [time: 970.002ns -> 990.002ns] + write(15, 67108865, 666660673, 0); // [time: 990.002ns -> 1000.002ns] + write(15, 67108866, 3910223084, 0); // [time: 1000.002ns -> 1010.002ns] + write(15, 67108867, 1271405124, 0); // [time: 1010.002ns -> 1020.002ns] + write(15, 67108868, 4236388983, 0); // [time: 1020.002ns -> 1030.002ns] + write(15, 67108869, 1347016890, 0); // [time: 1030.002ns -> 1040.002ns] + write(15, 67108870, 1337396640, 0); // [time: 1040.002ns -> 1050.002ns] + write(15, 67108871, 3009712000, 0); // [time: 1050.002ns -> 1060.002ns] + read(15, 67108864, 3997204021, 0); // [time: 1060.002ns -> 1080.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_12_0.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_12_0.bi.expect new file mode 100644 index 00000000..d17bbe8a --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_12_0.bi.expect @@ -0,0 +1,37 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108867, 3580256271, 0); // [time: 250ns -> 270ns] + read(15, 67108868, 1489666683, 0); // [time: 270ns -> 280ns] + read(15, 67108869, 3677074643, 0); // [time: 280ns -> 290ns] + read(15, 67108870, 1878953054, 0); // [time: 290ns -> 300ns] + read(15, 67108871, 2965505115, 0); // [time: 300ns -> 310ns] + read(15, 67108872, 3259566096, 0); // [time: 310ns -> 320ns] + read(15, 67108873, 1262153110, 0); // [time: 320ns -> 330ns] + read(15, 67108874, 2451703670, 0); // [time: 330ns -> 340ns] + reset(); // [time: 380.001ns -> 390.001ns] + reset(); // [time: 390.001ns -> 400.001ns] + reset(); // [time: 400.001ns -> 410.001ns] + write(15, 67108867, 3104341711, 0); // [time: 450.001ns -> 470.001ns] + write(15, 67108868, 964066815, 0); // [time: 470.001ns -> 480.001ns] + write(15, 67108869, 3328791441, 0); // [time: 480.001ns -> 490.001ns] + write(15, 67108870, 3489570824, 0); // [time: 490.001ns -> 500.001ns] + write(15, 67108871, 4241788620, 0); // [time: 500.001ns -> 510.001ns] + write(15, 67108872, 3583058104, 0); // [time: 510.001ns -> 520.001ns] + write(15, 67108873, 1005667378, 0); // [time: 520.001ns -> 530.001ns] + write(15, 67108874, 209419171, 0); // [time: 530.001ns -> 540.001ns] + reset(); // [time: 900.002ns -> 910.002ns] + reset(); // [time: 910.002ns -> 920.002ns] + reset(); // [time: 920.002ns -> 930.002ns] + write(15, 67108867, 1000382631, 0); // [time: 970.002ns -> 990.002ns] + write(15, 67108868, 1285425234, 0); // [time: 990.002ns -> 1000.002ns] + write(15, 67108869, 318606993, 0); // [time: 1000.002ns -> 1010.002ns] + write(15, 67108870, 2625467664, 0); // [time: 1010.002ns -> 1020.002ns] + write(15, 67108871, 229964357, 0); // [time: 1020.002ns -> 1030.002ns] + write(15, 67108872, 3036014706, 0); // [time: 1030.002ns -> 1040.002ns] + write(15, 67108873, 1528299378, 0); // [time: 1040.002ns -> 1050.002ns] + write(15, 67108874, 2182965409, 0); // [time: 1050.002ns -> 1060.002ns] + read(15, 67108867, 1000382631, 0); // [time: 1060.002ns -> 1080.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_12_1.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_12_1.bi.expect new file mode 100644 index 00000000..f8f3065d --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_12_1.bi.expect @@ -0,0 +1,37 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108867, 518534189, 0); // [time: 250ns -> 270ns] + read(15, 67108864, 844695266, 0); // [time: 270ns -> 280ns] + read(15, 67108865, 3937184150, 0); // [time: 280ns -> 290ns] + read(15, 67108866, 444246851, 0); // [time: 290ns -> 300ns] + read(15, 67108871, 3220682802, 0); // [time: 300ns -> 310ns] + read(15, 67108868, 2130811954, 0); // [time: 310ns -> 320ns] + read(15, 67108869, 2002127438, 0); // [time: 320ns -> 330ns] + read(15, 67108870, 493792053, 0); // [time: 330ns -> 340ns] + reset(); // [time: 380.001ns -> 390.001ns] + reset(); // [time: 390.001ns -> 400.001ns] + reset(); // [time: 400.001ns -> 410.001ns] + write(15, 67108867, 63714206, 0); // [time: 450.001ns -> 470.001ns] + write(15, 67108864, 2091823691, 0); // [time: 470.001ns -> 480.001ns] + write(15, 67108865, 3903276977, 0); // [time: 480.001ns -> 490.001ns] + write(15, 67108866, 1662756337, 0); // [time: 490.001ns -> 500.001ns] + write(15, 67108871, 4101310419, 0); // [time: 500.001ns -> 510.001ns] + write(15, 67108868, 903798156, 0); // [time: 510.001ns -> 520.001ns] + write(15, 67108869, 3840476340, 0); // [time: 520.001ns -> 530.001ns] + write(15, 67108870, 2244097975, 0); // [time: 530.001ns -> 540.001ns] + reset(); // [time: 900.002ns -> 910.002ns] + reset(); // [time: 910.002ns -> 920.002ns] + reset(); // [time: 920.002ns -> 930.002ns] + write(15, 67108867, 3956643922, 0); // [time: 970.002ns -> 990.002ns] + write(15, 67108864, 2115347845, 0); // [time: 990.002ns -> 1000.002ns] + write(15, 67108865, 1775201107, 0); // [time: 1000.002ns -> 1010.002ns] + write(15, 67108866, 1046910518, 0); // [time: 1010.002ns -> 1020.002ns] + write(15, 67108871, 345998276, 0); // [time: 1020.002ns -> 1030.002ns] + write(15, 67108868, 2089777588, 0); // [time: 1030.002ns -> 1040.002ns] + write(15, 67108869, 3110941387, 0); // [time: 1040.002ns -> 1050.002ns] + write(15, 67108870, 3151493219, 0); // [time: 1050.002ns -> 1060.002ns] + read(15, 67108867, 3956643922, 0); // [time: 1060.002ns -> 1080.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_12_2.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_12_2.bi.expect new file mode 100644 index 00000000..441adf6a --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_12_2.bi.expect @@ -0,0 +1,37 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108867, 869832817, 0); // [time: 250ns -> 270ns] + read(15, 67108868, 2976082601, 0); // [time: 270ns -> 280ns] + read(15, 67108869, 373695501, 0); // [time: 280ns -> 290ns] + read(15, 67108870, 2110838384, 0); // [time: 290ns -> 300ns] + read(15, 67108871, 3556455435, 0); // [time: 300ns -> 310ns] + read(15, 67108864, 1804567173, 0); // [time: 310ns -> 320ns] + read(15, 67108865, 1187331577, 0); // [time: 320ns -> 330ns] + read(15, 67108866, 1293993917, 0); // [time: 330ns -> 340ns] + reset(); // [time: 380.001ns -> 390.001ns] + reset(); // [time: 390.001ns -> 400.001ns] + reset(); // [time: 400.001ns -> 410.001ns] + write(15, 67108867, 753581369, 0); // [time: 450.001ns -> 470.001ns] + write(15, 67108868, 2300246917, 0); // [time: 470.001ns -> 480.001ns] + write(15, 67108869, 3523846629, 0); // [time: 480.001ns -> 490.001ns] + write(15, 67108870, 3751494934, 0); // [time: 490.001ns -> 500.001ns] + write(15, 67108871, 504397671, 0); // [time: 500.001ns -> 510.001ns] + write(15, 67108864, 3203321461, 0); // [time: 510.001ns -> 520.001ns] + write(15, 67108865, 3801714021, 0); // [time: 520.001ns -> 530.001ns] + write(15, 67108866, 654543662, 0); // [time: 530.001ns -> 540.001ns] + reset(); // [time: 900.002ns -> 910.002ns] + reset(); // [time: 910.002ns -> 920.002ns] + reset(); // [time: 920.002ns -> 930.002ns] + write(15, 67108867, 1829143953, 0); // [time: 970.002ns -> 990.002ns] + write(15, 67108868, 2746894674, 0); // [time: 990.002ns -> 1000.002ns] + write(15, 67108869, 3464933947, 0); // [time: 1000.002ns -> 1010.002ns] + write(15, 67108870, 3350075041, 0); // [time: 1010.002ns -> 1020.002ns] + write(15, 67108871, 1123364414, 0); // [time: 1020.002ns -> 1030.002ns] + write(15, 67108864, 3896266205, 0); // [time: 1030.002ns -> 1040.002ns] + write(15, 67108865, 3668919860, 0); // [time: 1040.002ns -> 1050.002ns] + write(15, 67108866, 177490457, 0); // [time: 1050.002ns -> 1060.002ns] + read(15, 67108867, 1829143953, 0); // [time: 1060.002ns -> 1080.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_12_3.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_12_3.bi.expect new file mode 100644 index 00000000..1b811196 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_12_3.bi.expect @@ -0,0 +1,37 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108867, 1070372987, 0); // [time: 250ns -> 270ns] + read(15, 67108868, 2645947069, 0); // [time: 270ns -> 280ns] + read(15, 67108869, 736643984, 0); // [time: 280ns -> 290ns] + read(15, 67108870, 192007203, 0); // [time: 290ns -> 300ns] + read(15, 67108871, 1925400290, 0); // [time: 300ns -> 310ns] + read(15, 67108872, 1309609983, 0); // [time: 310ns -> 320ns] + read(15, 67108873, 58503546, 0); // [time: 320ns -> 330ns] + read(15, 67108874, 3861022989, 0); // [time: 330ns -> 340ns] + reset(); // [time: 380.001ns -> 390.001ns] + reset(); // [time: 390.001ns -> 400.001ns] + reset(); // [time: 400.001ns -> 410.001ns] + write(15, 67108867, 1725708128, 0); // [time: 450.001ns -> 470.001ns] + write(15, 67108868, 3760744365, 0); // [time: 470.001ns -> 480.001ns] + write(15, 67108869, 3803789590, 0); // [time: 480.001ns -> 490.001ns] + write(15, 67108870, 2647121574, 0); // [time: 490.001ns -> 500.001ns] + write(15, 67108871, 336117328, 0); // [time: 500.001ns -> 510.001ns] + write(15, 67108872, 3984726565, 0); // [time: 510.001ns -> 520.001ns] + write(15, 67108873, 104808193, 0); // [time: 520.001ns -> 530.001ns] + write(15, 67108874, 2315494688, 0); // [time: 530.001ns -> 540.001ns] + reset(); // [time: 900.002ns -> 910.002ns] + reset(); // [time: 910.002ns -> 920.002ns] + reset(); // [time: 920.002ns -> 930.002ns] + write(15, 67108867, 3997204021, 0); // [time: 970.002ns -> 990.002ns] + write(15, 67108868, 666660673, 0); // [time: 990.002ns -> 1000.002ns] + write(15, 67108869, 3910223084, 0); // [time: 1000.002ns -> 1010.002ns] + write(15, 67108870, 1271405124, 0); // [time: 1010.002ns -> 1020.002ns] + write(15, 67108871, 4236388983, 0); // [time: 1020.002ns -> 1030.002ns] + write(15, 67108872, 1347016890, 0); // [time: 1030.002ns -> 1040.002ns] + write(15, 67108873, 1337396640, 0); // [time: 1040.002ns -> 1050.002ns] + write(15, 67108874, 3009712000, 0); // [time: 1050.002ns -> 1060.002ns] + read(15, 67108867, 3997204021, 0); // [time: 1060.002ns -> 1080.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_4_0.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_4_0.bi.expect new file mode 100644 index 00000000..c48eeb96 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_4_0.bi.expect @@ -0,0 +1,37 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108865, 2821946881, 0); // [time: 250ns -> 270ns] + read(15, 67108866, 4080087070, 0); // [time: 270ns -> 280ns] + read(15, 67108867, 2243193877, 0); // [time: 280ns -> 290ns] + read(15, 67108868, 2472849580, 0); // [time: 290ns -> 300ns] + read(15, 67108869, 3565370026, 0); // [time: 300ns -> 310ns] + read(15, 67108870, 890985600, 0); // [time: 310ns -> 320ns] + read(15, 67108871, 4179549189, 0); // [time: 320ns -> 330ns] + read(15, 67108872, 4158632492, 0); // [time: 330ns -> 340ns] + reset(); // [time: 380.001ns -> 390.001ns] + reset(); // [time: 390.001ns -> 400.001ns] + reset(); // [time: 400.001ns -> 410.001ns] + write(15, 67108865, 3744957516, 0); // [time: 450.001ns -> 470.001ns] + write(15, 67108866, 2300150418, 0); // [time: 470.001ns -> 480.001ns] + write(15, 67108867, 2081940992, 0); // [time: 480.001ns -> 490.001ns] + write(15, 67108868, 1697819148, 0); // [time: 490.001ns -> 500.001ns] + write(15, 67108869, 602241333, 0); // [time: 500.001ns -> 510.001ns] + write(15, 67108870, 2260552922, 0); // [time: 510.001ns -> 520.001ns] + write(15, 67108871, 4251564751, 0); // [time: 520.001ns -> 530.001ns] + write(15, 67108872, 3326548024, 0); // [time: 530.001ns -> 540.001ns] + reset(); // [time: 900.002ns -> 910.002ns] + reset(); // [time: 910.002ns -> 920.002ns] + reset(); // [time: 920.002ns -> 930.002ns] + write(15, 67108865, 1044044861, 0); // [time: 970.002ns -> 990.002ns] + write(15, 67108866, 4177314760, 0); // [time: 990.002ns -> 1000.002ns] + write(15, 67108867, 4253662683, 0); // [time: 1000.002ns -> 1010.002ns] + write(15, 67108868, 3575602093, 0); // [time: 1010.002ns -> 1020.002ns] + write(15, 67108869, 667576938, 0); // [time: 1020.002ns -> 1030.002ns] + write(15, 67108870, 3110079964, 0); // [time: 1030.002ns -> 1040.002ns] + write(15, 67108871, 3758039968, 0); // [time: 1040.002ns -> 1050.002ns] + write(15, 67108872, 3566852678, 0); // [time: 1050.002ns -> 1060.002ns] + read(15, 67108865, 1044044861, 0); // [time: 1060.002ns -> 1080.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_4_1.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_4_1.bi.expect new file mode 100644 index 00000000..1bea919b --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_4_1.bi.expect @@ -0,0 +1,37 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108865, 2205995893, 0); // [time: 250ns -> 270ns] + read(15, 67108866, 486560095, 0); // [time: 270ns -> 280ns] + read(15, 67108867, 4100133660, 0); // [time: 280ns -> 290ns] + read(15, 67108864, 596618694, 0); // [time: 290ns -> 300ns] + read(15, 67108869, 3499942130, 0); // [time: 300ns -> 310ns] + read(15, 67108870, 2357711907, 0); // [time: 310ns -> 320ns] + read(15, 67108871, 2086526797, 0); // [time: 320ns -> 330ns] + read(15, 67108868, 364077448, 0); // [time: 330ns -> 340ns] + reset(); // [time: 380.001ns -> 390.001ns] + reset(); // [time: 390.001ns -> 400.001ns] + reset(); // [time: 400.001ns -> 410.001ns] + write(15, 67108865, 210674739, 0); // [time: 450.001ns -> 470.001ns] + write(15, 67108866, 1567286535, 0); // [time: 470.001ns -> 480.001ns] + write(15, 67108867, 922799025, 0); // [time: 480.001ns -> 490.001ns] + write(15, 67108864, 4171757579, 0); // [time: 490.001ns -> 500.001ns] + write(15, 67108869, 740193371, 0); // [time: 500.001ns -> 510.001ns] + write(15, 67108870, 872570658, 0); // [time: 510.001ns -> 520.001ns] + write(15, 67108871, 608559447, 0); // [time: 520.001ns -> 530.001ns] + write(15, 67108868, 1049762371, 0); // [time: 530.001ns -> 540.001ns] + reset(); // [time: 900.002ns -> 910.002ns] + reset(); // [time: 910.002ns -> 920.002ns] + reset(); // [time: 920.002ns -> 930.002ns] + write(15, 67108865, 61321282, 0); // [time: 970.002ns -> 990.002ns] + write(15, 67108866, 3113679544, 0); // [time: 990.002ns -> 1000.002ns] + write(15, 67108867, 2723657215, 0); // [time: 1000.002ns -> 1010.002ns] + write(15, 67108864, 3578979173, 0); // [time: 1010.002ns -> 1020.002ns] + write(15, 67108869, 1844094072, 0); // [time: 1020.002ns -> 1030.002ns] + write(15, 67108870, 985922533, 0); // [time: 1030.002ns -> 1040.002ns] + write(15, 67108871, 772047228, 0); // [time: 1040.002ns -> 1050.002ns] + write(15, 67108868, 2786594234, 0); // [time: 1050.002ns -> 1060.002ns] + read(15, 67108865, 61321282, 0); // [time: 1060.002ns -> 1080.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_4_2.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_4_2.bi.expect new file mode 100644 index 00000000..efb5de91 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_4_2.bi.expect @@ -0,0 +1,37 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108865, 869832817, 0); // [time: 250ns -> 270ns] + read(15, 67108866, 2976082601, 0); // [time: 270ns -> 280ns] + read(15, 67108867, 373695501, 0); // [time: 280ns -> 290ns] + read(15, 67108868, 2110838384, 0); // [time: 290ns -> 300ns] + read(15, 67108869, 3556455435, 0); // [time: 300ns -> 310ns] + read(15, 67108870, 1804567173, 0); // [time: 310ns -> 320ns] + read(15, 67108871, 1187331577, 0); // [time: 320ns -> 330ns] + read(15, 67108864, 1293993917, 0); // [time: 330ns -> 340ns] + reset(); // [time: 380.001ns -> 390.001ns] + reset(); // [time: 390.001ns -> 400.001ns] + reset(); // [time: 400.001ns -> 410.001ns] + write(15, 67108865, 753581369, 0); // [time: 450.001ns -> 470.001ns] + write(15, 67108866, 2300246917, 0); // [time: 470.001ns -> 480.001ns] + write(15, 67108867, 3523846629, 0); // [time: 480.001ns -> 490.001ns] + write(15, 67108868, 3751494934, 0); // [time: 490.001ns -> 500.001ns] + write(15, 67108869, 504397671, 0); // [time: 500.001ns -> 510.001ns] + write(15, 67108870, 3203321461, 0); // [time: 510.001ns -> 520.001ns] + write(15, 67108871, 3801714021, 0); // [time: 520.001ns -> 530.001ns] + write(15, 67108864, 654543662, 0); // [time: 530.001ns -> 540.001ns] + reset(); // [time: 900.002ns -> 910.002ns] + reset(); // [time: 910.002ns -> 920.002ns] + reset(); // [time: 920.002ns -> 930.002ns] + write(15, 67108865, 1829143953, 0); // [time: 970.002ns -> 990.002ns] + write(15, 67108866, 2746894674, 0); // [time: 990.002ns -> 1000.002ns] + write(15, 67108867, 3464933947, 0); // [time: 1000.002ns -> 1010.002ns] + write(15, 67108868, 3350075041, 0); // [time: 1010.002ns -> 1020.002ns] + write(15, 67108869, 1123364414, 0); // [time: 1020.002ns -> 1030.002ns] + write(15, 67108870, 3896266205, 0); // [time: 1030.002ns -> 1040.002ns] + write(15, 67108871, 3668919860, 0); // [time: 1040.002ns -> 1050.002ns] + write(15, 67108864, 177490457, 0); // [time: 1050.002ns -> 1060.002ns] + read(15, 67108865, 1829143953, 0); // [time: 1060.002ns -> 1080.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_4_3.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_4_3.bi.expect new file mode 100644 index 00000000..84c4435f --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_4_3.bi.expect @@ -0,0 +1,37 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108865, 1070372987, 0); // [time: 250ns -> 270ns] + read(15, 67108866, 2645947069, 0); // [time: 270ns -> 280ns] + read(15, 67108867, 736643984, 0); // [time: 280ns -> 290ns] + read(15, 67108868, 192007203, 0); // [time: 290ns -> 300ns] + read(15, 67108869, 1925400290, 0); // [time: 300ns -> 310ns] + read(15, 67108870, 1309609983, 0); // [time: 310ns -> 320ns] + read(15, 67108871, 58503546, 0); // [time: 320ns -> 330ns] + read(15, 67108872, 3861022989, 0); // [time: 330ns -> 340ns] + reset(); // [time: 380.001ns -> 390.001ns] + reset(); // [time: 390.001ns -> 400.001ns] + reset(); // [time: 400.001ns -> 410.001ns] + write(15, 67108865, 1725708128, 0); // [time: 450.001ns -> 470.001ns] + write(15, 67108866, 3760744365, 0); // [time: 470.001ns -> 480.001ns] + write(15, 67108867, 3803789590, 0); // [time: 480.001ns -> 490.001ns] + write(15, 67108868, 2647121574, 0); // [time: 490.001ns -> 500.001ns] + write(15, 67108869, 336117328, 0); // [time: 500.001ns -> 510.001ns] + write(15, 67108870, 3984726565, 0); // [time: 510.001ns -> 520.001ns] + write(15, 67108871, 104808193, 0); // [time: 520.001ns -> 530.001ns] + write(15, 67108872, 2315494688, 0); // [time: 530.001ns -> 540.001ns] + reset(); // [time: 900.002ns -> 910.002ns] + reset(); // [time: 910.002ns -> 920.002ns] + reset(); // [time: 920.002ns -> 930.002ns] + write(15, 67108865, 3997204021, 0); // [time: 970.002ns -> 990.002ns] + write(15, 67108866, 666660673, 0); // [time: 990.002ns -> 1000.002ns] + write(15, 67108867, 3910223084, 0); // [time: 1000.002ns -> 1010.002ns] + write(15, 67108868, 1271405124, 0); // [time: 1010.002ns -> 1020.002ns] + write(15, 67108869, 4236388983, 0); // [time: 1020.002ns -> 1030.002ns] + write(15, 67108870, 1347016890, 0); // [time: 1030.002ns -> 1040.002ns] + write(15, 67108871, 1337396640, 0); // [time: 1040.002ns -> 1050.002ns] + write(15, 67108872, 3009712000, 0); // [time: 1050.002ns -> 1060.002ns] + read(15, 67108865, 3997204021, 0); // [time: 1060.002ns -> 1080.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_8_0.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_8_0.bi.expect new file mode 100644 index 00000000..e937ca48 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_8_0.bi.expect @@ -0,0 +1,37 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108866, 2821946881, 0); // [time: 250ns -> 270ns] + read(15, 67108867, 4080087070, 0); // [time: 270ns -> 280ns] + read(15, 67108868, 2243193877, 0); // [time: 280ns -> 290ns] + read(15, 67108869, 2472849580, 0); // [time: 290ns -> 300ns] + read(15, 67108870, 3565370026, 0); // [time: 300ns -> 310ns] + read(15, 67108871, 890985600, 0); // [time: 310ns -> 320ns] + read(15, 67108872, 4179549189, 0); // [time: 320ns -> 330ns] + read(15, 67108873, 4158632492, 0); // [time: 330ns -> 340ns] + reset(); // [time: 380.001ns -> 390.001ns] + reset(); // [time: 390.001ns -> 400.001ns] + reset(); // [time: 400.001ns -> 410.001ns] + write(15, 67108866, 3744957516, 0); // [time: 450.001ns -> 470.001ns] + write(15, 67108867, 2300150418, 0); // [time: 470.001ns -> 480.001ns] + write(15, 67108868, 2081940992, 0); // [time: 480.001ns -> 490.001ns] + write(15, 67108869, 1697819148, 0); // [time: 490.001ns -> 500.001ns] + write(15, 67108870, 602241333, 0); // [time: 500.001ns -> 510.001ns] + write(15, 67108871, 2260552922, 0); // [time: 510.001ns -> 520.001ns] + write(15, 67108872, 4251564751, 0); // [time: 520.001ns -> 530.001ns] + write(15, 67108873, 3326548024, 0); // [time: 530.001ns -> 540.001ns] + reset(); // [time: 900.002ns -> 910.002ns] + reset(); // [time: 910.002ns -> 920.002ns] + reset(); // [time: 920.002ns -> 930.002ns] + write(15, 67108866, 1044044861, 0); // [time: 970.002ns -> 990.002ns] + write(15, 67108867, 4177314760, 0); // [time: 990.002ns -> 1000.002ns] + write(15, 67108868, 4253662683, 0); // [time: 1000.002ns -> 1010.002ns] + write(15, 67108869, 3575602093, 0); // [time: 1010.002ns -> 1020.002ns] + write(15, 67108870, 667576938, 0); // [time: 1020.002ns -> 1030.002ns] + write(15, 67108871, 3110079964, 0); // [time: 1030.002ns -> 1040.002ns] + write(15, 67108872, 3758039968, 0); // [time: 1040.002ns -> 1050.002ns] + write(15, 67108873, 3566852678, 0); // [time: 1050.002ns -> 1060.002ns] + read(15, 67108866, 1044044861, 0); // [time: 1060.002ns -> 1080.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_8_1.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_8_1.bi.expect new file mode 100644 index 00000000..2c1254d3 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_8_1.bi.expect @@ -0,0 +1,37 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108866, 1833423740, 0); // [time: 250ns -> 270ns] + read(15, 67108867, 4073618608, 0); // [time: 270ns -> 280ns] + read(15, 67108864, 3418745219, 0); // [time: 280ns -> 290ns] + read(15, 67108865, 3757272308, 0); // [time: 290ns -> 300ns] + read(15, 67108870, 1325530178, 0); // [time: 300ns -> 310ns] + read(15, 67108871, 1451722922, 0); // [time: 310ns -> 320ns] + read(15, 67108868, 1997677454, 0); // [time: 320ns -> 330ns] + read(15, 67108869, 986005841, 0); // [time: 330ns -> 340ns] + reset(); // [time: 380.001ns -> 390.001ns] + reset(); // [time: 390.001ns -> 400.001ns] + reset(); // [time: 400.001ns -> 410.001ns] + write(15, 67108866, 789975088, 0); // [time: 450.001ns -> 470.001ns] + write(15, 67108867, 3746918692, 0); // [time: 470.001ns -> 480.001ns] + write(15, 67108864, 410224063, 0); // [time: 480.001ns -> 490.001ns] + write(15, 67108865, 864118294, 0); // [time: 490.001ns -> 500.001ns] + write(15, 67108870, 908783806, 0); // [time: 500.001ns -> 510.001ns] + write(15, 67108871, 2735695332, 0); // [time: 510.001ns -> 520.001ns] + write(15, 67108868, 3991830963, 0); // [time: 520.001ns -> 530.001ns] + write(15, 67108869, 3613974492, 0); // [time: 530.001ns -> 540.001ns] + reset(); // [time: 900.002ns -> 910.002ns] + reset(); // [time: 910.002ns -> 920.002ns] + reset(); // [time: 920.002ns -> 930.002ns] + write(15, 67108866, 1515921225, 0); // [time: 970.002ns -> 990.002ns] + write(15, 67108867, 104974629, 0); // [time: 990.002ns -> 1000.002ns] + write(15, 67108864, 966302149, 0); // [time: 1000.002ns -> 1010.002ns] + write(15, 67108865, 4157870389, 0); // [time: 1010.002ns -> 1020.002ns] + write(15, 67108870, 2924407148, 0); // [time: 1020.002ns -> 1030.002ns] + write(15, 67108871, 1538378206, 0); // [time: 1030.002ns -> 1040.002ns] + write(15, 67108868, 60846013, 0); // [time: 1040.002ns -> 1050.002ns] + write(15, 67108869, 3809194079, 0); // [time: 1050.002ns -> 1060.002ns] + read(15, 67108866, 1515921225, 0); // [time: 1060.002ns -> 1080.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_8_2.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_8_2.bi.expect new file mode 100644 index 00000000..0e6c8c94 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_8_2.bi.expect @@ -0,0 +1,37 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108866, 869832817, 0); // [time: 250ns -> 270ns] + read(15, 67108867, 2976082601, 0); // [time: 270ns -> 280ns] + read(15, 67108868, 373695501, 0); // [time: 280ns -> 290ns] + read(15, 67108869, 2110838384, 0); // [time: 290ns -> 300ns] + read(15, 67108870, 3556455435, 0); // [time: 300ns -> 310ns] + read(15, 67108871, 1804567173, 0); // [time: 310ns -> 320ns] + read(15, 67108864, 1187331577, 0); // [time: 320ns -> 330ns] + read(15, 67108865, 1293993917, 0); // [time: 330ns -> 340ns] + reset(); // [time: 380.001ns -> 390.001ns] + reset(); // [time: 390.001ns -> 400.001ns] + reset(); // [time: 400.001ns -> 410.001ns] + write(15, 67108866, 753581369, 0); // [time: 450.001ns -> 470.001ns] + write(15, 67108867, 2300246917, 0); // [time: 470.001ns -> 480.001ns] + write(15, 67108868, 3523846629, 0); // [time: 480.001ns -> 490.001ns] + write(15, 67108869, 3751494934, 0); // [time: 490.001ns -> 500.001ns] + write(15, 67108870, 504397671, 0); // [time: 500.001ns -> 510.001ns] + write(15, 67108871, 3203321461, 0); // [time: 510.001ns -> 520.001ns] + write(15, 67108864, 3801714021, 0); // [time: 520.001ns -> 530.001ns] + write(15, 67108865, 654543662, 0); // [time: 530.001ns -> 540.001ns] + reset(); // [time: 900.002ns -> 910.002ns] + reset(); // [time: 910.002ns -> 920.002ns] + reset(); // [time: 920.002ns -> 930.002ns] + write(15, 67108866, 1829143953, 0); // [time: 970.002ns -> 990.002ns] + write(15, 67108867, 2746894674, 0); // [time: 990.002ns -> 1000.002ns] + write(15, 67108868, 3464933947, 0); // [time: 1000.002ns -> 1010.002ns] + write(15, 67108869, 3350075041, 0); // [time: 1010.002ns -> 1020.002ns] + write(15, 67108870, 1123364414, 0); // [time: 1020.002ns -> 1030.002ns] + write(15, 67108871, 3896266205, 0); // [time: 1030.002ns -> 1040.002ns] + write(15, 67108864, 3668919860, 0); // [time: 1040.002ns -> 1050.002ns] + write(15, 67108865, 177490457, 0); // [time: 1050.002ns -> 1060.002ns] + read(15, 67108866, 1829143953, 0); // [time: 1060.002ns -> 1080.002ns] +} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_8_3.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_8_3.bi.expect new file mode 100644 index 00000000..847ef6a7 --- /dev/null +++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_8_3.bi.expect @@ -0,0 +1,37 @@ +// trace 0 +trace { + reset(); // [time: 20ns -> 30ns] + reset(); // [time: 30ns -> 40ns] + reset(); // [time: 40ns -> 50ns] + read(15, 67108866, 1070372987, 0); // [time: 250ns -> 270ns] + read(15, 67108867, 2645947069, 0); // [time: 270ns -> 280ns] + read(15, 67108868, 736643984, 0); // [time: 280ns -> 290ns] + read(15, 67108869, 192007203, 0); // [time: 290ns -> 300ns] + read(15, 67108870, 1925400290, 0); // [time: 300ns -> 310ns] + read(15, 67108871, 1309609983, 0); // [time: 310ns -> 320ns] + read(15, 67108872, 58503546, 0); // [time: 320ns -> 330ns] + read(15, 67108873, 3861022989, 0); // [time: 330ns -> 340ns] + reset(); // [time: 380.001ns -> 390.001ns] + reset(); // [time: 390.001ns -> 400.001ns] + reset(); // [time: 400.001ns -> 410.001ns] + write(15, 67108866, 1725708128, 0); // [time: 450.001ns -> 470.001ns] + write(15, 67108867, 3760744365, 0); // [time: 470.001ns -> 480.001ns] + write(15, 67108868, 3803789590, 0); // [time: 480.001ns -> 490.001ns] + write(15, 67108869, 2647121574, 0); // [time: 490.001ns -> 500.001ns] + write(15, 67108870, 336117328, 0); // [time: 500.001ns -> 510.001ns] + write(15, 67108871, 3984726565, 0); // [time: 510.001ns -> 520.001ns] + write(15, 67108872, 104808193, 0); // [time: 520.001ns -> 530.001ns] + write(15, 67108873, 2315494688, 0); // [time: 530.001ns -> 540.001ns] + reset(); // [time: 900.002ns -> 910.002ns] + reset(); // [time: 910.002ns -> 920.002ns] + reset(); // [time: 920.002ns -> 930.002ns] + write(15, 67108866, 3997204021, 0); // [time: 970.002ns -> 990.002ns] + write(15, 67108867, 666660673, 0); // [time: 990.002ns -> 1000.002ns] + write(15, 67108868, 3910223084, 0); // [time: 1000.002ns -> 1010.002ns] + write(15, 67108869, 1271405124, 0); // [time: 1010.002ns -> 1020.002ns] + write(15, 67108870, 4236388983, 0); // [time: 1020.002ns -> 1030.002ns] + write(15, 67108871, 1347016890, 0); // [time: 1030.002ns -> 1040.002ns] + write(15, 67108872, 1337396640, 0); // [time: 1040.002ns -> 1050.002ns] + write(15, 67108873, 3009712000, 0); // [time: 1050.002ns -> 1060.002ns] + read(15, 67108866, 3997204021, 0); // [time: 1060.002ns -> 1080.002ns] +} diff --git a/tests/brave_new_world_francis/expects/bit_truncation_fft.bi.expect b/tests/brave_new_world_francis/expects/bit_truncation_fft.bi.expect new file mode 100644 index 00000000..2861938d --- /dev/null +++ b/tests/brave_new_world_francis/expects/bit_truncation_fft.bi.expect @@ -0,0 +1,4 @@ +// trace 0 +trace { + bit_truncation_fft(8386560, 2047); +} diff --git a/tests/brave_new_world_francis/expects/bit_truncation_sha.bi.expect b/tests/brave_new_world_francis/expects/bit_truncation_sha.bi.expect new file mode 100644 index 00000000..52f5d64f --- /dev/null +++ b/tests/brave_new_world_francis/expects/bit_truncation_sha.bi.expect @@ -0,0 +1,4 @@ +// trace 0 +trace { + bit_truncation_sha(4398046511104, 68719476736); +} diff --git a/tests/brave_new_world_francis/expects/ftu_sha.bi.expect b/tests/brave_new_world_francis/expects/ftu_sha.bi.expect new file mode 100644 index 00000000..bf9d06bc --- /dev/null +++ b/tests/brave_new_world_francis/expects/ftu_sha.bi.expect @@ -0,0 +1,4 @@ +// trace 0 +trace { + failure_to_update_sha(); +} diff --git a/tests/brave_new_world_francis/expects/signal_async.bi.expect b/tests/brave_new_world_francis/expects/signal_async.bi.expect new file mode 100644 index 00000000..ccd9f567 --- /dev/null +++ b/tests/brave_new_world_francis/expects/signal_async.bi.expect @@ -0,0 +1,4 @@ +// trace 0 +trace { + signal_async(6, 7); +} diff --git a/tests/brave_new_world_francis/expects/use_without_valid.bi.expect b/tests/brave_new_world_francis/expects/use_without_valid.bi.expect new file mode 100644 index 00000000..1b5733f2 --- /dev/null +++ b/tests/brave_new_world_francis/expects/use_without_valid.bi.expect @@ -0,0 +1,4 @@ +// trace 0 +trace { + use_without_valid(5, 5); +} diff --git a/tests/ethmac/expects/ethmac_wishbone_manager.bi.expect b/tests/ethmac/expects/ethmac_wishbone_manager.bi.expect new file mode 100644 index 00000000..57404ebb --- /dev/null +++ b/tests/ethmac/expects/ethmac_wishbone_manager.bi.expect @@ -0,0 +1,2 @@ +---CODE--- +2 diff --git a/tests/ethmac/expects/ethmac_wishbone_subordinate.bi.expect b/tests/ethmac/expects/ethmac_wishbone_subordinate.bi.expect new file mode 100644 index 00000000..57404ebb --- /dev/null +++ b/tests/ethmac/expects/ethmac_wishbone_subordinate.bi.expect @@ -0,0 +1,2 @@ +---CODE--- +2 diff --git a/tests/fifo/expects/fifo.bi.expect b/tests/fifo/expects/fifo.bi.expect new file mode 100644 index 00000000..9ecea916 --- /dev/null +++ b/tests/fifo/expects/fifo.bi.expect @@ -0,0 +1,10 @@ +// trace 0 +trace { + reset(); + push(3); + push(4); + idle(); + pop(3); + pop(4); + push(1995394993); +} diff --git a/tests/fifo/expects/push_pop_identity.bi.expect b/tests/fifo/expects/push_pop_identity.bi.expect new file mode 100644 index 00000000..7b7038ac --- /dev/null +++ b/tests/fifo/expects/push_pop_identity.bi.expect @@ -0,0 +1,9 @@ +// trace 0 +trace { + reset(); + push(2); + pop(2); + idle(); + push(3); + pop(3); +} diff --git a/tests/fifo/expects/push_pop_loop_empty.bi.expect b/tests/fifo/expects/push_pop_loop_empty.bi.expect new file mode 100644 index 00000000..c9f68b19 --- /dev/null +++ b/tests/fifo/expects/push_pop_loop_empty.bi.expect @@ -0,0 +1,2 @@ +---CODE--- +101 diff --git a/tests/fifo/expects/push_pop_loop_not_empty.bi.expect b/tests/fifo/expects/push_pop_loop_not_empty.bi.expect new file mode 100644 index 00000000..c9f68b19 --- /dev/null +++ b/tests/fifo/expects/push_pop_loop_not_empty.bi.expect @@ -0,0 +1,2 @@ +---CODE--- +101 diff --git a/tests/fpga-debugging/axi-burst-s4/expects/s4_buggy.bi.expect b/tests/fpga-debugging/axi-burst-s4/expects/s4_buggy.bi.expect new file mode 100644 index 00000000..207ca5c9 --- /dev/null +++ b/tests/fpga-debugging/axi-burst-s4/expects/s4_buggy.bi.expect @@ -0,0 +1,5 @@ +// trace 0 +trace { +} +---CODE--- +1 diff --git a/tests/fpga-debugging/axi-burst-s4/expects/s4_fixed.bi.expect b/tests/fpga-debugging/axi-burst-s4/expects/s4_fixed.bi.expect new file mode 100644 index 00000000..e92193ec --- /dev/null +++ b/tests/fpga-debugging/axi-burst-s4/expects/s4_fixed.bi.expect @@ -0,0 +1,4 @@ +// trace 0 +trace { + write_burst(1152, 3700821297, 15); // [time: 0.19ns -> 0.332ns] +} diff --git a/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy.bi.expect b/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy.bi.expect new file mode 100644 index 00000000..cf728602 --- /dev/null +++ b/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy.bi.expect @@ -0,0 +1,16 @@ +// trace 0 +trace { + idle(); // [time: 0ns -> 25ns] + write(64, 2147483648, 0, 0); // [time: 25ns -> 100ns] +} +// trace 0 +trace { + idle(); // [time: 0ns -> 25ns] +} + +// trace 1 +trace { + idle(); // [time: 0ns -> 25ns] +} +---CODE--- +1 diff --git a/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy_workload_1.bi.expect b/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy_workload_1.bi.expect new file mode 100644 index 00000000..c3233582 --- /dev/null +++ b/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy_workload_1.bi.expect @@ -0,0 +1,49 @@ +// trace 0 +trace { + idle(); // [time: 0ns -> 25ns] + write_stalled(64, 2147483648, 0); // [time: 25ns -> 75ns] + write_stalled(64, 2147483648, 0); // [time: 75ns -> 100ns] +} + +// trace 1 +trace { + write_stalled(64, 2147483648, 1); // [time: 0ns -> 75ns] + write_stalled(64, 2147483648, 0); // [time: 75ns -> 100ns] +} +// trace 0 +trace { + idle(); // [time: 0ns -> 25ns] + read_v1(64, 0); // [time: 25ns -> 100ns] +} + +// trace 1 +trace { + idle(); // [time: 0ns -> 25ns] + read_v1(64, 0); // [time: 25ns -> 100ns] +} + +// trace 2 +trace { + idle(); // [time: 0ns -> 25ns] + read_v1(64, 0); // [time: 25ns -> 100ns] +} + +// trace 3 +trace { + idle(); // [time: 0ns -> 25ns] + read_v2(64, 0, 0); // [time: 25ns -> 100ns] +} + +// trace 4 +trace { + idle(); // [time: 0ns -> 25ns] + read_v2(64, 0, 0); // [time: 25ns -> 100ns] +} + +// trace 5 +trace { + idle(); // [time: 0ns -> 25ns] + read_v2(64, 0, 0); // [time: 25ns -> 100ns] +} +---CODE--- +1 diff --git a/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed.bi.expect b/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed.bi.expect new file mode 100644 index 00000000..ecf4be3e --- /dev/null +++ b/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed.bi.expect @@ -0,0 +1,12 @@ +// trace 0 +trace { + idle(); // [time: 0ns -> 25ns] + write(64, 2147483648, 0, 0); // [time: 25ns -> 100ns] +} +// trace 0 +trace { + idle(); // [time: 0ns -> 25ns] + read_v2(68, 0, 1); // [time: 25ns -> 125ns] + idle(); // [time: 125ns -> 150ns] + idle(); // [time: 150ns -> 150ns] +} diff --git a/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed_workload_1.bi.expect b/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed_workload_1.bi.expect new file mode 100644 index 00000000..d0ba43e7 --- /dev/null +++ b/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed_workload_1.bi.expect @@ -0,0 +1,41 @@ +// trace 0 +trace { + idle(); // [time: 0ns -> 25ns] +} +// trace 0 +trace { + idle(); // [time: 0ns -> 25ns] + read_v1(64, 0); // [time: 25ns -> 100ns] +} + +// trace 1 +trace { + idle(); // [time: 0ns -> 25ns] + read_v1(64, 0); // [time: 25ns -> 100ns] +} + +// trace 2 +trace { + idle(); // [time: 0ns -> 25ns] + read_v1(64, 0); // [time: 25ns -> 100ns] +} + +// trace 3 +trace { + idle(); // [time: 0ns -> 25ns] + read_v2(64, 0, 0); // [time: 25ns -> 100ns] +} + +// trace 4 +trace { + idle(); // [time: 0ns -> 25ns] + read_v2(64, 0, 0); // [time: 25ns -> 100ns] +} + +// trace 5 +trace { + idle(); // [time: 0ns -> 25ns] + read_v2(64, 0, 0); // [time: 25ns -> 100ns] +} +---CODE--- +1 diff --git a/tests/fpga-debugging/axi-lite-s1/s1_alt.prot b/tests/fpga-debugging/axi-lite-s1/s1_alt.prot new file mode 100644 index 00000000..2c0b19d5 --- /dev/null +++ b/tests/fpga-debugging/axi-lite-s1/s1_alt.prot @@ -0,0 +1,189 @@ + +struct Subordinate { + // Active-low reset + in S_AXI_ARESETN: u1, + + // Write address channel + in S_AXI_AWVALID: u1, + in S_AXI_AWADDR: u7, + out S_AXI_AWREADY: u1, + + // Write data channel + in S_AXI_WVALID: u1, + in S_AXI_WDATA: u32, + out S_AXI_WREADY: u1, + + // Write response channel + in S_AXI_BREADY: u1, + out S_AXI_BVALID: u1, + out S_AXI_BRESP: u2, + + // Read address channel + in S_AXI_ARVALID: u1, + in S_AXI_ARADDR: u7, + out S_AXI_ARREADY: u1, + + // Read data channel + in S_AXI_RREADY: u1, + out S_AXI_RVALID: u1, + out S_AXI_RDATA: u32, +} + +prot reset() { + // Reset is active-low + DUT.S_AXI_ARESETN := 1'b0; + + // Set valid = 0 for the write data / write address / read address channels + DUT.S_AXI_AWVALID := 1'b0; + DUT.S_AXI_WVALID := 1'b0; + DUT.S_AXI_ARVALID := 1'b0; + + // Set ready = 0 for the write response / read data channels + DUT.S_AXI_BREADY := 1'b0; + DUT.S_AXI_RREADY := 1'b0; + + step(); +} + + +#[idle] +prot idle() { + // Reset is active-low, so we set reset = 1 here + // to indicate that the DUT is *not* reset during an `idle` transaction + DUT.S_AXI_ARESETN := 1'b1; + + // No requests on either address channel + DUT.S_AXI_AWVALID := 1'b0; + DUT.S_AXI_AWADDR := X; + DUT.S_AXI_WVALID := 1'b0; + DUT.S_AXI_WDATA := X; + DUT.S_AXI_ARVALID := 1'b0; + DUT.S_AXI_ARADDR := X; + + // No transfer on the read data channel. + // (Note: BREADY is deliberately left unconstrained: the workload + // testbenches keep BREADY high after their last write completes.) + DUT.S_AXI_RREADY := 1'b0; + + step(); +} + +// // Note: this is still WIP (this is simpler than the protocol we discussed +// // yesterday for ease of debugging for now) +// prot write(addr: u7, data: u32, resp: u2, n: uint) { +// repeat n iterations { +// DUT.S_AXI_AWVALID := 1'b0; +// step(); +// } +// DUT.S_AXI_AWVALID := 1'b1; +// DUT.S_AXI_AWADDR := addr; + +// DUT.S_AXI_WVALID := 1'b1; +// DUT.S_AXI_WDATA := data; + +// // technically this should be `while !AWREADY && !WREADY { step() }` +// // but our DSL doesn't have `&&`. Without loss of generality, +// // we wait for AWREADY to become 1 +// while !(DUT.S_AXI_AWREADY == 1'b1) { +// step(); +// } +// // Assuming AWREADY & WREADY become 1 together +// // (this is allowed in the AXI spec and the DUT exhibits this behavior) +// assert_eq(DUT.S_AXI_WREADY, 1'b1); + +// step(); + +// // Remove constraints on AWVALID and WVALID +// DUT.S_AXI_AWVALID := X; +// DUT.S_AXI_WVALID := X; + +// // Wait for BVALID to become 1 +// while !(DUT.S_AXI_BVALID == 1'b1) { +// step(); +// } +// // BVALID is now 1 +// // Wait for some no. of cycles before BREADY becomes 1 +// repeat n iterations { +// step(); +// // BVALID must remain stable after it becomes 1 +// assert_eq(DUT.S_AXI_BVALID, 1'b1); +// } +// DUT.S_AXI_BREADY := 1'b1; +// assert_eq(DUT.S_AXI_BRESP, resp); +// step(); +// } + +// RREADY is asserted before RVALID +// (This is allowed in section A2.3.2.2 of the AXI spec) +prot read_v1(addr: u7, data: u32) { + DUT.S_AXI_ARVALID := 1'b1; + DUT.S_AXI_ARADDR := addr; + + // Wait for ARREADY to become 1 + while !(DUT.S_AXI_ARREADY == 1'b1) { + step(); + } + // ARREADY is now 1 + + step(); + + assert_eq(DUT.S_AXI_ARREADY, 1'b0); + DUT.S_AXI_RREADY := 1'b1; + + // Wait for RVALID to become 1 + // AXI spec says that ARVALID & ARREADY must both be 1 + // before RVALID can be asserted (A2.3.2.2) + while !(DUT.S_AXI_RVALID == 1'b1) { + step(); + assert_eq(DUT.S_AXI_ARREADY, 1'b0); + } + assert_eq(DUT.S_AXI_RDATA, data); + step(); +} + +// RVALID is asserted before RREADY +// (This is allowed in section A2.3.2.2 of the AXI spec) +prot read_v2(addr: u7, data: u32, n: uint) { + DUT.S_AXI_ARVALID := 1'b1; + DUT.S_AXI_ARADDR := addr; + + // Wait for ARREADY to become 1 + while !(DUT.S_AXI_ARREADY == 1'b1) { + step(); + } + // ARREADY is now 1 + + step(); + + fork(); + + // Wait for RVALID to become 1 + // AXI spec says that ARVALID & ARREADY must both be 1 + // before RVALID can be asserted (A2.3.2.2) + while !(DUT.S_AXI_RVALID == 1'b1) { + step(); + } + // RVALID is now 1 + + // While we are waiting for RREADY to become 1, + // another read address request cannot arrive + // (i.e. ARREADY has to remain 0). That is, we have to acknowledge + // the read data before another read address request can arrive. + assert_eq(DUT.S_AXI_ARREADY, 1'b0); + + // Wait until RREADY becomes 1 + repeat n iterations { + DUT.S_AXI_RREADY := 1'b0; + // Check that RVALID remains stable + assert_eq(DUT.S_AXI_RVALID, 1'b1); + step(); + } + // Check that ARREADY remains 0 (i.e. no conflicting read address request) + assert_eq(DUT.S_AXI_ARREADY, 1'b0); + + // Perform data transfer on the read data channel + DUT.S_AXI_RREADY := 1'b1; + assert_eq(DUT.S_AXI_RDATA, data); + + step(); +} \ No newline at end of file diff --git a/tests/fpga-debugging/axi-stream-s2/expects/s2_buggy.bi.expect b/tests/fpga-debugging/axi-stream-s2/expects/s2_buggy.bi.expect new file mode 100644 index 00000000..a37a8103 --- /dev/null +++ b/tests/fpga-debugging/axi-stream-s2/expects/s2_buggy.bi.expect @@ -0,0 +1,17 @@ +// trace 0 +trace { + reset(); // [time: 0ns -> 12.5ns] + wait_for_data(); // [time: 337.5ns -> 362.5ns] + wait_for_data(); // [time: 387.5ns -> 412.5ns] + wait_for_data(); // [time: 512.5ns -> 537.5ns] + wait_for_data(); // [time: 537.5ns -> 562.5ns] + wait_for_data(); // [time: 612.5ns -> 637.5ns] + wait_for_data(); // [time: 787.5ns -> 812.5ns] + wait_for_data(); // [time: 837.5ns -> 862.5ns] + recv(1); // [time: 862.5ns -> 887.5ns] + recv(2); // [time: 887.5ns -> 912.5ns] + recv(3); // [time: 912.5ns -> 937.5ns] + recv(4); // [time: 937.5ns -> 962.5ns] + recv(5); // [time: 962.5ns -> 987.5ns] + recv(6); // [time: 987.5ns -> 1012.5ns] +} diff --git a/tests/fpga-debugging/axi-stream-s2/expects/s2_fixed.bi.expect b/tests/fpga-debugging/axi-stream-s2/expects/s2_fixed.bi.expect new file mode 100644 index 00000000..9e4f85a7 --- /dev/null +++ b/tests/fpga-debugging/axi-stream-s2/expects/s2_fixed.bi.expect @@ -0,0 +1,40 @@ +// trace 0 +trace { + reset(); // [time: 0ns -> 12.5ns] + wait_for_data(); // [time: 337.5ns -> 362.5ns] + wait_for_data(); // [time: 387.5ns -> 412.5ns] + wait_for_data(); // [time: 512.5ns -> 537.5ns] + wait_for_data(); // [time: 537.5ns -> 562.5ns] + wait_for_data(); // [time: 612.5ns -> 637.5ns] + wait_for_data(); // [time: 787.5ns -> 812.5ns] + wait_for_data(); // [time: 837.5ns -> 862.5ns] + recv(1); // [time: 862.5ns -> 887.5ns] + recv(2); // [time: 887.5ns -> 912.5ns] + recv(3); // [time: 912.5ns -> 937.5ns] + recv(4); // [time: 937.5ns -> 962.5ns] + recv(5); // [time: 962.5ns -> 987.5ns] + recv(6); // [time: 987.5ns -> 1012.5ns] + stall(7, 0); // [time: 1012.5ns -> 1062.5ns] + reset(); // [time: 1062.5ns -> 1087.5ns] + reset(); // [time: 1087.5ns -> 1087.5ns] +} + +// trace 1 +trace { + reset(); // [time: 0ns -> 12.5ns] + wait_for_data(); // [time: 337.5ns -> 362.5ns] + wait_for_data(); // [time: 387.5ns -> 412.5ns] + wait_for_data(); // [time: 512.5ns -> 537.5ns] + wait_for_data(); // [time: 537.5ns -> 562.5ns] + wait_for_data(); // [time: 612.5ns -> 637.5ns] + wait_for_data(); // [time: 787.5ns -> 812.5ns] + wait_for_data(); // [time: 837.5ns -> 862.5ns] + recv(1); // [time: 862.5ns -> 887.5ns] + recv(2); // [time: 887.5ns -> 912.5ns] + recv(3); // [time: 912.5ns -> 937.5ns] + recv(4); // [time: 937.5ns -> 962.5ns] + recv(5); // [time: 962.5ns -> 987.5ns] + recv(6); // [time: 987.5ns -> 1012.5ns] + reset(); // [time: 1062.5ns -> 1087.5ns] + reset(); // [time: 1087.5ns -> 1087.5ns] +} diff --git a/tests/fpga-debugging/axis-adapter-s3/expects/s3_buggy.bi.expect b/tests/fpga-debugging/axis-adapter-s3/expects/s3_buggy.bi.expect new file mode 100644 index 00000000..204d6b80 --- /dev/null +++ b/tests/fpga-debugging/axis-adapter-s3/expects/s3_buggy.bi.expect @@ -0,0 +1,13 @@ +// trace 0 +trace { + reset(); // [time: 0ns -> 25ns] + wait_for_data(); // [time: 25ns -> 50ns] + wait_for_data(); // [time: 50ns -> 75ns] + wait_for_data(); // [time: 75ns -> 100ns] + recv(205); // [time: 100ns -> 125ns] + recv(171); // [time: 125ns -> 150ns] + recv(205); // [time: 150ns -> 175ns] + recv(171); // [time: 175ns -> 200ns] + recv(205); // [time: 200ns -> 225ns] + recv_last(171); // [time: 225ns -> 225ns] +} diff --git a/tests/fpga-debugging/axis-adapter-s3/expects/s3_fixed.bi.expect b/tests/fpga-debugging/axis-adapter-s3/expects/s3_fixed.bi.expect new file mode 100644 index 00000000..5cbf6070 --- /dev/null +++ b/tests/fpga-debugging/axis-adapter-s3/expects/s3_fixed.bi.expect @@ -0,0 +1,12 @@ +// trace 0 +trace { + reset(); // [time: 0ns -> 25ns] + wait_for_data(); // [time: 25ns -> 50ns] + wait_for_data(); // [time: 50ns -> 75ns] + wait_for_data(); // [time: 75ns -> 100ns] + recv(205); // [time: 100ns -> 125ns] + recv(171); // [time: 125ns -> 150ns] + recv(205); // [time: 150ns -> 175ns] + recv(171); // [time: 175ns -> 200ns] + recv_last(205); // [time: 200ns -> 200ns] +} diff --git a/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.bi.expect b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.bi.expect new file mode 100644 index 00000000..c233b7bd --- /dev/null +++ b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.bi.expect @@ -0,0 +1,28 @@ +// trace 0 +trace { + reset(); // [time: 0ns -> 25ns] + idle(); // [time: 25ns -> 50ns] + push(1); // [time: 50ns -> 75ns] + push(2); // [time: 75ns -> 100ns] + push(3); // [time: 100ns -> 125ns] + push(4); // [time: 125ns -> 150ns] + push(5); // [time: 150ns -> 175ns] + push(6); // [time: 175ns -> 200ns] + push(7); // [time: 200ns -> 200ns] +} +// trace 0 +trace { + reset(); // [time: 0ns -> 25ns] +} + +// trace 1 +trace { + reset(); // [time: 0ns -> 25ns] +} + +// trace 2 +trace { + reset(); // [time: 0ns -> 25ns] +} +---CODE--- +1 diff --git a/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_fixed.bi.expect b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_fixed.bi.expect new file mode 100644 index 00000000..49910681 --- /dev/null +++ b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_fixed.bi.expect @@ -0,0 +1,26 @@ +// trace 0 +trace { + reset(); // [time: 0ns -> 25ns] + idle(); // [time: 25ns -> 50ns] + push(1); // [time: 50ns -> 75ns] + push(2); // [time: 75ns -> 100ns] + push(3); // [time: 100ns -> 150ns] + push(4); // [time: 150ns -> 175ns] + push(5); // [time: 175ns -> 200ns] + push(6); // [time: 200ns -> 225ns] + push(7); // [time: 225ns -> 250ns] + push(8); // [time: 250ns -> 250ns] +} +// trace 0 +trace { + reset(); // [time: 0ns -> 25ns] + idle(); // [time: 25ns -> 50ns] + idle(); // [time: 50ns -> 75ns] + idle(); // [time: 75ns -> 100ns] + pop(2); // [time: 100ns -> 150ns] + pop(3); // [time: 125ns -> 175ns] + pop(4); // [time: 150ns -> 200ns] + pop(5); // [time: 175ns -> 225ns] + pop(6); // [time: 200ns -> 250ns] + pop(7); // [time: 225ns -> 250ns] +} diff --git a/tests/fpga-debugging/axis-fifo-d11/expects/d11_buggy.bi.expect b/tests/fpga-debugging/axis-fifo-d11/expects/d11_buggy.bi.expect new file mode 100644 index 00000000..c0878918 --- /dev/null +++ b/tests/fpga-debugging/axis-fifo-d11/expects/d11_buggy.bi.expect @@ -0,0 +1,17 @@ +// trace 0 +trace { + reset(); // [time: 0ns -> 25ns] + push(1); // [time: 25ns -> 50ns] + push(1); // [time: 50ns -> 75ns] + push(2); // [time: 75ns -> 100ns] + push(4); // [time: 100ns -> 125ns] + push(5); // [time: 125ns -> 150ns] + push(6); // [time: 150ns -> 175ns] + push(6); // [time: 175ns -> 200ns] + push(6); // [time: 200ns -> 225ns] + push(6); // [time: 225ns -> 250ns] + push(6); // [time: 250ns -> 275ns] + push(6); // [time: 275ns -> 300ns] + reset(); // [time: 300ns -> 325ns] + push(6); // [time: 325ns -> 325ns] +} diff --git a/tests/fpga-debugging/axis-fifo-d11/expects/d11_fixed.bi.expect b/tests/fpga-debugging/axis-fifo-d11/expects/d11_fixed.bi.expect new file mode 100644 index 00000000..ccbf4bd8 --- /dev/null +++ b/tests/fpga-debugging/axis-fifo-d11/expects/d11_fixed.bi.expect @@ -0,0 +1,21 @@ +// trace 0 +trace { + reset(); // [time: 0ns -> 25ns] + push(1); // [time: 25ns -> 50ns] + push(1); // [time: 50ns -> 75ns] + push(2); // [time: 75ns -> 100ns] + push(4); // [time: 100ns -> 125ns] + push(5); // [time: 125ns -> 150ns] + push(6); // [time: 150ns -> 175ns] + push(6); // [time: 175ns -> 200ns] + push(6); // [time: 200ns -> 225ns] + push(6); // [time: 225ns -> 250ns] + push(6); // [time: 250ns -> 275ns] + push(6); // [time: 275ns -> 300ns] + reset(); // [time: 300ns -> 325ns] + push(6); // [time: 325ns -> 350ns] + push(6); // [time: 350ns -> 375ns] + push(7); // [time: 375ns -> 400ns] + push(7); // [time: 400ns -> 425ns] + push(7); // [time: 425ns -> 425ns] +} diff --git a/tests/fpga-debugging/axis-fifo-d12/expects/d12_buggy.bi.expect b/tests/fpga-debugging/axis-fifo-d12/expects/d12_buggy.bi.expect new file mode 100644 index 00000000..008e0943 --- /dev/null +++ b/tests/fpga-debugging/axis-fifo-d12/expects/d12_buggy.bi.expect @@ -0,0 +1,16 @@ +// trace 0 +trace { + reset(); // [time: 0ns -> 25ns] + push(1); // [time: 25ns -> 50ns] + push(1); // [time: 50ns -> 75ns] + push(2); // [time: 75ns -> 100ns] + push(3); // [time: 100ns -> 125ns] + push(4); // [time: 125ns -> 150ns] + push(5); // [time: 150ns -> 175ns] + push(6); // [time: 175ns -> 200ns] + pop(1); // [time: 200ns -> 250ns] + push_and_pop(6, 2); // [time: 225ns -> 275ns] + push_and_pop(6, 3); // [time: 250ns -> 300ns] + push_and_pop(7, 3); // [time: 275ns -> 325ns] + push_and_pop(7, 5); // [time: 300ns -> 350ns] +} diff --git a/tests/fpga-debugging/axis-fifo-d12/expects/d12_fixed.bi.expect b/tests/fpga-debugging/axis-fifo-d12/expects/d12_fixed.bi.expect new file mode 100644 index 00000000..4eeb0094 --- /dev/null +++ b/tests/fpga-debugging/axis-fifo-d12/expects/d12_fixed.bi.expect @@ -0,0 +1,15 @@ +// trace 0 +trace { + reset(); // [time: 0ns -> 25ns] + push(1); // [time: 25ns -> 50ns] + push(1); // [time: 50ns -> 75ns] + push(2); // [time: 75ns -> 100ns] + push(3); // [time: 100ns -> 125ns] + push(4); // [time: 125ns -> 150ns] + push(5); // [time: 150ns -> 175ns] + push(6); // [time: 175ns -> 200ns] + pop(1); // [time: 200ns -> 250ns] + push_and_pop(6, 2); // [time: 225ns -> 275ns] + push_and_pop(6, 3); // [time: 250ns -> 300ns] + push_and_pop(7, 3); // [time: 275ns -> 325ns] +} diff --git a/tests/fpga-debugging/axis-fifo-d4/expects/d4_buggy.bi.expect b/tests/fpga-debugging/axis-fifo-d4/expects/d4_buggy.bi.expect new file mode 100644 index 00000000..68cf837b --- /dev/null +++ b/tests/fpga-debugging/axis-fifo-d4/expects/d4_buggy.bi.expect @@ -0,0 +1,47 @@ +// trace 0 +trace { + reset(); // [time: 0ns -> 2.5ns] + reset(); // [time: 2.5ns -> 5ns] + reset(); // [time: 5ns -> 7.5ns] + reset(); // [time: 7.5ns -> 10ns] + reset(); // [time: 10ns -> 12.5ns] + reset(); // [time: 12.5ns -> 15ns] + reset(); // [time: 15ns -> 17.5ns] + reset(); // [time: 17.5ns -> 20ns] + reset(); // [time: 20ns -> 22.5ns] + reset(); // [time: 22.5ns -> 25ns] + push(0); // [time: 37.5ns -> 40ns] + push(1); // [time: 40ns -> 42.5ns] + push(2); // [time: 42.5ns -> 45ns] + push(3); // [time: 45ns -> 47.5ns] + push(4); // [time: 47.5ns -> 50ns] + push(5); // [time: 50ns -> 52.5ns] + push(6); // [time: 52.5ns -> 55ns] + push(7); // [time: 55ns -> 57.5ns] + push(8); // [time: 57.5ns -> 60ns] + push(9); // [time: 60ns -> 62.5ns] + push(233); // [time: 62.5ns -> 65ns] + push(0); // [time: 77.5ns -> 80ns] + push(1); // [time: 80ns -> 82.5ns] + push(2); // [time: 82.5ns -> 85ns] + push(3); // [time: 85ns -> 87.5ns] + push(4); // [time: 87.5ns -> 90ns] + push(5); // [time: 90ns -> 92.5ns] + push(6); // [time: 92.5ns -> 95ns] + push(7); // [time: 95ns -> 97.5ns] + push(8); // [time: 97.5ns -> 100ns] + push(9); // [time: 100ns -> 102.5ns] + push(233); // [time: 102.5ns -> 105ns] + push(0); // [time: 117.5ns -> 120ns] + push(1); // [time: 120ns -> 122.5ns] + push(2); // [time: 122.5ns -> 125ns] + push(3); // [time: 125ns -> 127.5ns] + push(4); // [time: 127.5ns -> 130ns] + push(5); // [time: 130ns -> 132.5ns] + push(6); // [time: 132.5ns -> 135ns] + push(7); // [time: 135ns -> 137.5ns] + push(8); // [time: 137.5ns -> 140ns] + push(9); // [time: 140ns -> 142.5ns] + push(233); // [time: 142.5ns -> 145ns] + push(0); // [time: 157.5ns -> 157.5ns] +} diff --git a/tests/fpga-debugging/axis-fifo-d4/expects/d4_fixed.bi.expect b/tests/fpga-debugging/axis-fifo-d4/expects/d4_fixed.bi.expect new file mode 100644 index 00000000..2eabcecc --- /dev/null +++ b/tests/fpga-debugging/axis-fifo-d4/expects/d4_fixed.bi.expect @@ -0,0 +1,48 @@ +// trace 0 +trace { + reset(); // [time: 0ns -> 2.5ns] + reset(); // [time: 2.5ns -> 5ns] + reset(); // [time: 5ns -> 7.5ns] + reset(); // [time: 7.5ns -> 10ns] + reset(); // [time: 10ns -> 12.5ns] + reset(); // [time: 12.5ns -> 15ns] + reset(); // [time: 15ns -> 17.5ns] + reset(); // [time: 17.5ns -> 20ns] + reset(); // [time: 20ns -> 22.5ns] + reset(); // [time: 22.5ns -> 25ns] + push(0); // [time: 37.5ns -> 40ns] + push(1); // [time: 40ns -> 42.5ns] + push(2); // [time: 42.5ns -> 45ns] + push(3); // [time: 45ns -> 47.5ns] + push(4); // [time: 47.5ns -> 50ns] + push(5); // [time: 50ns -> 52.5ns] + push(6); // [time: 52.5ns -> 55ns] + push(7); // [time: 55ns -> 57.5ns] + push(8); // [time: 57.5ns -> 60ns] + push(9); // [time: 60ns -> 62.5ns] + push(233); // [time: 62.5ns -> 65ns] + push(0); // [time: 77.5ns -> 80ns] + push(1); // [time: 80ns -> 82.5ns] + push(2); // [time: 82.5ns -> 85ns] + push(3); // [time: 85ns -> 87.5ns] + push(4); // [time: 87.5ns -> 90ns] + push(5); // [time: 90ns -> 92.5ns] + push(6); // [time: 92.5ns -> 95ns] + push(7); // [time: 95ns -> 97.5ns] + push(8); // [time: 97.5ns -> 100ns] + push(9); // [time: 100ns -> 102.5ns] + push(233); // [time: 102.5ns -> 105ns] + push(0); // [time: 117.5ns -> 120ns] + push(1); // [time: 120ns -> 122.5ns] + push(2); // [time: 122.5ns -> 125ns] + push(3); // [time: 125ns -> 127.5ns] + push(4); // [time: 127.5ns -> 130ns] + push(5); // [time: 130ns -> 132.5ns] + push(6); // [time: 132.5ns -> 135ns] + push(7); // [time: 135ns -> 137.5ns] + push(8); // [time: 137.5ns -> 140ns] + push(9); // [time: 140ns -> 142.5ns] + push(233); // [time: 142.5ns -> 145ns] +} +---CODE--- +1 diff --git a/tests/identities/expects/identity_d1.bi.expect b/tests/identities/expects/identity_d1.bi.expect new file mode 100644 index 00000000..c9f68b19 --- /dev/null +++ b/tests/identities/expects/identity_d1.bi.expect @@ -0,0 +1,2 @@ +---CODE--- +101 diff --git a/tests/multi/expects/multi0.bi.expect b/tests/multi/expects/multi0.bi.expect new file mode 100644 index 00000000..8219b9ab --- /dev/null +++ b/tests/multi/expects/multi0.bi.expect @@ -0,0 +1,4 @@ +// trace 0 +trace { + multi(10, 10); +} diff --git a/tests/multi/expects/multi0keep.bi.expect b/tests/multi/expects/multi0keep.bi.expect new file mode 100644 index 00000000..8219b9ab --- /dev/null +++ b/tests/multi/expects/multi0keep.bi.expect @@ -0,0 +1,4 @@ +// trace 0 +trace { + multi(10, 10); +} diff --git a/tests/multi/expects/multi0keep2const.bi.expect b/tests/multi/expects/multi0keep2const.bi.expect new file mode 100644 index 00000000..8219b9ab --- /dev/null +++ b/tests/multi/expects/multi0keep2const.bi.expect @@ -0,0 +1,4 @@ +// trace 0 +trace { + multi(10, 10); +} diff --git a/tests/multi/expects/multi2const.bi.expect b/tests/multi/expects/multi2const.bi.expect new file mode 100644 index 00000000..8219b9ab --- /dev/null +++ b/tests/multi/expects/multi2const.bi.expect @@ -0,0 +1,4 @@ +// trace 0 +trace { + multi(10, 10); +} diff --git a/tests/multi/expects/multi2multi.bi.expect b/tests/multi/expects/multi2multi.bi.expect new file mode 100644 index 00000000..8219b9ab --- /dev/null +++ b/tests/multi/expects/multi2multi.bi.expect @@ -0,0 +1,4 @@ +// trace 0 +trace { + multi(10, 10); +} diff --git a/tests/multi/expects/multi_data.bi.expect b/tests/multi/expects/multi_data.bi.expect new file mode 100644 index 00000000..8219b9ab --- /dev/null +++ b/tests/multi/expects/multi_data.bi.expect @@ -0,0 +1,4 @@ +// trace 0 +trace { + multi(10, 10); +} diff --git a/tests/multipliers/expects/mult_d2.bi.expect b/tests/multipliers/expects/mult_d2.bi.expect new file mode 100644 index 00000000..e81c6c28 --- /dev/null +++ b/tests/multipliers/expects/mult_d2.bi.expect @@ -0,0 +1,5 @@ +// trace 0 +trace { + mul(1, 2, 2); + mul(6, 8, 48); +} diff --git a/tests/picorv32/expects/pcpi_mul_unsigned_mul.bi.expect b/tests/picorv32/expects/pcpi_mul_unsigned_mul.bi.expect new file mode 100644 index 00000000..7b7bd936 --- /dev/null +++ b/tests/picorv32/expects/pcpi_mul_unsigned_mul.bi.expect @@ -0,0 +1,8 @@ +// trace 0 +trace { + pcpi_mul_reset(); + pcpi_mul(1, 1, 1, 33554483); + pcpi_mul(1, 100, 100, 33554483); + pcpi_mul(100, 1, 100, 33554483); + pcpi_mul(33554483, 200, 2415929304, 33554483); +} diff --git a/tests/serv/expects/serv_regfile.bi.expect b/tests/serv/expects/serv_regfile.bi.expect new file mode 100644 index 00000000..c9f68b19 --- /dev/null +++ b/tests/serv/expects/serv_regfile.bi.expect @@ -0,0 +1,2 @@ +---CODE--- +101 diff --git a/tests/tinyaes128/expects/aes128.bi.expect b/tests/tinyaes128/expects/aes128.bi.expect new file mode 100644 index 00000000..0153c201 --- /dev/null +++ b/tests/tinyaes128/expects/aes128.bi.expect @@ -0,0 +1,5 @@ +// trace 0 +trace { + aes128(0x000102030405060708090a0b0c0d0e0f, 0x00112233445566778899aabbccddeeff, 0x69c4e0d86a7b0430d8cdb78070b4c55a); + aes128(0x00000000000000000000000000000000, 0x00000000000000000000000000000000, 0x66e94bd4ef8a2c3b884cfa59ca342b2e); +} diff --git a/tests/wal/advanced/expects/axis.bi.expect b/tests/wal/advanced/expects/axis.bi.expect new file mode 100644 index 00000000..dc460c13 --- /dev/null +++ b/tests/wal/advanced/expects/axis.bi.expect @@ -0,0 +1,9 @@ +// trace 0 +trace { + send_data(0); // [time: 804ns -> 812ns] + send_data(1); // [time: 1508ns -> 1516ns] + send_data(2); // [time: 2212ns -> 2220ns] + send_data(3); // [time: 2916ns -> 2924ns] +} +---CODE--- +1 diff --git a/tests/wal/advanced/expects/axis_failing.bi.expect b/tests/wal/advanced/expects/axis_failing.bi.expect new file mode 100644 index 00000000..207ca5c9 --- /dev/null +++ b/tests/wal/advanced/expects/axis_failing.bi.expect @@ -0,0 +1,5 @@ +// trace 0 +trace { +} +---CODE--- +1 diff --git a/tests/wal/advanced/expects/axis_minimal.bi.expect b/tests/wal/advanced/expects/axis_minimal.bi.expect new file mode 100644 index 00000000..207ca5c9 --- /dev/null +++ b/tests/wal/advanced/expects/axis_minimal.bi.expect @@ -0,0 +1,5 @@ +// trace 0 +trace { +} +---CODE--- +1 diff --git a/tests/wal/advanced/expects/axis_truncated.bi.expect b/tests/wal/advanced/expects/axis_truncated.bi.expect new file mode 100644 index 00000000..207ca5c9 --- /dev/null +++ b/tests/wal/advanced/expects/axis_truncated.bi.expect @@ -0,0 +1,5 @@ +// trace 0 +trace { +} +---CODE--- +1 diff --git a/tests/wal/advanced/expects/axis_truncated_include_idle.bi.expect b/tests/wal/advanced/expects/axis_truncated_include_idle.bi.expect new file mode 100644 index 00000000..207ca5c9 --- /dev/null +++ b/tests/wal/advanced/expects/axis_truncated_include_idle.bi.expect @@ -0,0 +1,5 @@ +// trace 0 +trace { +} +---CODE--- +1 diff --git a/tests/wb_intercon/expects/wb_arb.bi.expect b/tests/wb_intercon/expects/wb_arb.bi.expect new file mode 100644 index 00000000..57404ebb --- /dev/null +++ b/tests/wb_intercon/expects/wb_arb.bi.expect @@ -0,0 +1,2 @@ +---CODE--- +2 diff --git a/tests/wb_intercon/expects/wb_cdc.bi.expect b/tests/wb_intercon/expects/wb_cdc.bi.expect new file mode 100644 index 00000000..c9f68b19 --- /dev/null +++ b/tests/wb_intercon/expects/wb_cdc.bi.expect @@ -0,0 +1,2 @@ +---CODE--- +101 diff --git a/tests/wishbone/expects/wishbone.bi.expect b/tests/wishbone/expects/wishbone.bi.expect new file mode 100644 index 00000000..734ce750 --- /dev/null +++ b/tests/wishbone/expects/wishbone.bi.expect @@ -0,0 +1,18 @@ +// trace 0 +trace { + read(0, 0); + write(0, 0); + read(0, 3); + read(0, 5); + read(0, 7); + read(0, 9); + read(0, 11); + read(0, 0); + write(0, 0); + read(0, 3); + read(0, 5); + read(0, 7); + read(0, 9); + read(0, 11); + read(0, 0); +} From c1cff14951b0132b30af09590b70459f79fad1dd Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sat, 11 Jul 2026 15:13:07 -0400 Subject: [PATCH 05/55] Formatting --- scripts/generate_runt_configs.py | 1 + 1 file changed, 1 insertion(+) diff --git a/scripts/generate_runt_configs.py b/scripts/generate_runt_configs.py index a319619a..ab2b409e 100644 --- a/scripts/generate_runt_configs.py +++ b/scripts/generate_runt_configs.py @@ -194,6 +194,7 @@ def monitor_runt_command(case: dict) -> list[tuple[str, str]]: cmd = timeout_cmd(case["timeout_secs"], cmd) return [("", repo_root_command(cmd))] + # Same as `monitor_runt_command` above but for BI test cases def bi_runt_command(case: dict) -> list[tuple[str, str]]: cmd = [*binary_prefix("bi"), "--protocol", case["path"]] From d4c855711b7779034b344db758d1e9e7e2beaf10 Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sat, 11 Jul 2026 15:16:52 -0400 Subject: [PATCH 06/55] Redirect stderr to stdout so that bi error messages appear in expected output files --- scripts/generate_runt_configs.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/scripts/generate_runt_configs.py b/scripts/generate_runt_configs.py index ab2b409e..3cf158af 100644 --- a/scripts/generate_runt_configs.py +++ b/scripts/generate_runt_configs.py @@ -205,7 +205,9 @@ def bi_runt_command(case: dict) -> list[tuple[str, str]]: cmd += case["extra_args"] if case["timeout_secs"] is not None: cmd = timeout_cmd(case["timeout_secs"], cmd) - return [("", repo_root_command(cmd))] + # We redirect stderr to stdout so that the expected output files + # contain error messages if BI fails + return [("", repo_root_command(cmd, stderr="stdout"))] def waveform_runt_command(case: dict) -> list[tuple[str, str]]: From d383c7b7d0aae8e41eb58af21fc75af8ef756127 Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sat, 11 Jul 2026 15:17:02 -0400 Subject: [PATCH 07/55] Update auto-generated BI Runt config --- runt/bi/runt.toml | 344 +++++++++++++++++++++++----------------------- 1 file changed, 172 insertions(+), 172 deletions(-) diff --git a/runt/bi/runt.toml b/runt/bi/runt.toml index 9e18a046..8ac7ae9d 100644 --- a/runt/bi/runt.toml +++ b/runt/bi/runt.toml @@ -7,7 +7,7 @@ paths = [ ] expect_dir = "../../tests/adders/expects" expect_name = "add_d1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/adders/add_d1.prot --wave tests/adders/add_d1.fst --instances add_d1:Adder 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/adders/add_d1.prot --wave tests/adders/add_d1.fst --instances add_d1:Adder 2>&1" [[tests]] name = "bi.tests_adders_add_d2.add_d2_bi" @@ -16,7 +16,7 @@ paths = [ ] expect_dir = "../../tests/adders/expects" expect_name = "add_d2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/adders/add_d2.prot --wave tests/adders/add_d2.fst --instances add_d2:Adder 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/adders/add_d2.prot --wave tests/adders/add_d2.fst --instances add_d2:Adder 2>&1" [[tests]] name = "bi.tests_adders_add_var_cyc.add_var_cyc_bi" @@ -25,7 +25,7 @@ paths = [ ] expect_dir = "../../tests/adders/expects" expect_name = "add_var_cyc.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/adders/add_var_cyc.prot --wave tests/adders/loop_with_assigns.fst --instances add_d1:Adder 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/adders/add_var_cyc.prot --wave tests/adders/loop_with_assigns.fst --instances add_d1:Adder 2>&1" [[tests]] name = "bi.tests_adders_busy_wait.busy_wait_bi" @@ -34,7 +34,7 @@ paths = [ ] expect_dir = "../../tests/adders/expects" expect_name = "busy_wait.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/adders/busy_wait.prot --wave tests/adders/busy_wait.fst --instances add_d1:Adder 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/adders/busy_wait.prot --wave tests/adders/busy_wait.fst --instances add_d1:Adder 2>&1" [[tests]] name = "bi.tests_adders_loop_with_assigns.loop_with_assigns_bi" @@ -43,7 +43,7 @@ paths = [ ] expect_dir = "../../tests/adders/expects" expect_name = "loop_with_assigns.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/adders/loop_with_assigns.prot --wave tests/adders/loop_with_assigns.fst --instances add_d1:Adder 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/adders/loop_with_assigns.prot --wave tests/adders/loop_with_assigns.fst --instances add_d1:Adder 2>&1" [[tests]] name = "bi.tests_adders_nested_busy_wait.nested_busy_wait_bi" @@ -52,7 +52,7 @@ paths = [ ] expect_dir = "../../tests/adders/expects" expect_name = "nested_busy_wait.bi.expect" -cmd = "cd ../.. && python3 -c 'import os, signal, subprocess, sys\np = subprocess.Popen(sys.argv[2:], start_new_session=True)\ntry:\n sys.exit(p.wait(timeout=float(sys.argv[1])))\nexcept subprocess.TimeoutExpired:\n os.killpg(p.pid, signal.SIGKILL)\n sys.exit(124)\n' 5 target/debug/bi --protocol tests/adders/nested_busy_wait.prot --wave tests/adders/nested_busy_wait.fst --instances add_d1:Adder 2>/dev/null" +cmd = "cd ../.. && python3 -c 'import os, signal, subprocess, sys\np = subprocess.Popen(sys.argv[2:], start_new_session=True)\ntry:\n sys.exit(p.wait(timeout=float(sys.argv[1])))\nexcept subprocess.TimeoutExpired:\n os.killpg(p.pid, signal.SIGKILL)\n sys.exit(124)\n' 5 target/debug/bi --protocol tests/adders/nested_busy_wait.prot --wave tests/adders/nested_busy_wait.fst --instances add_d1:Adder 2>&1" [[tests]] name = "bi.tests_alus_alu_d1_monitor.alu_d1_bi" @@ -61,7 +61,7 @@ paths = [ ] expect_dir = "../../tests/alus/expects" expect_name = "alu_d1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/alus/alu_d1.monitor.prot --wave tests/alus/alu_d1.fst --instances alu_d1:ALU 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/alus/alu_d1.monitor.prot --wave tests/alus/alu_d1.fst --instances alu_d1:ALU 2>&1" [[tests]] name = "bi.tests_alus_alu_d2_monitor.alu_d2_bi" @@ -70,7 +70,7 @@ paths = [ ] expect_dir = "../../tests/alus/expects" expect_name = "alu_d2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/alus/alu_d2.monitor.prot --wave tests/alus/alu_d2.fst --instances alu_d2:ALU 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/alus/alu_d2.monitor.prot --wave tests/alus/alu_d2.fst --instances alu_d2:ALU 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_classic_1_bi" @@ -79,7 +79,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/fifo_classic/expects" expect_name = "test_fifo_classic_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_classic_2_bi" @@ -88,7 +88,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/fifo_classic/expects" expect_name = "test_fifo_classic_2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_classic_3_bi" @@ -97,7 +97,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/fifo_classic/expects" expect_name = "test_fifo_classic_3.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_classic_4_bi" @@ -106,7 +106,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/fifo_classic/expects" expect_name = "test_fifo_classic_4.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_classic_5_bi" @@ -115,7 +115,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/fifo_classic/expects" expect_name = "test_fifo_classic_5.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_5.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_5.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_classic_6_bi" @@ -124,7 +124,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/fifo_classic/expects" expect_name = "test_fifo_classic_6.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_6.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_6.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_classic_7_bi" @@ -133,7 +133,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/fifo_classic/expects" expect_name = "test_fifo_classic_7.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_7.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_7.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_classic_8_bi" @@ -142,7 +142,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/fifo_classic/expects" expect_name = "test_fifo_classic_8.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_constant_1_bi" @@ -151,7 +151,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/fifo_constant/expects" expect_name = "test_fifo_constant_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_constant_2_bi" @@ -160,7 +160,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/fifo_constant/expects" expect_name = "test_fifo_constant_2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_constant_3_bi" @@ -169,7 +169,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/fifo_constant/expects" expect_name = "test_fifo_constant_3.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_constant_4_bi" @@ -178,7 +178,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/fifo_constant/expects" expect_name = "test_fifo_constant_4.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_constant_5_bi" @@ -187,7 +187,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/fifo_constant/expects" expect_name = "test_fifo_constant_5.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_5.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_5.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_constant_6_bi" @@ -196,7 +196,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/fifo_constant/expects" expect_name = "test_fifo_constant_6.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_6.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_6.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_constant_7_bi" @@ -205,7 +205,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/fifo_constant/expects" expect_name = "test_fifo_constant_7.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_7.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_7.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_constant_8_bi" @@ -214,7 +214,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/fifo_constant/expects" expect_name = "test_fifo_constant_8.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_16_0_bi" @@ -223,7 +223,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_classic/expects" expect_name = "test_sram_classic_16_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_16_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_16_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_16_12_bi" @@ -232,7 +232,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_classic/expects" expect_name = "test_sram_classic_16_12.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_16_12.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_16_12.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_16_4_bi" @@ -241,7 +241,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_classic/expects" expect_name = "test_sram_classic_16_4.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_16_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_16_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_16_8_bi" @@ -250,7 +250,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_classic/expects" expect_name = "test_sram_classic_16_8.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_16_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_16_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_1_0_bi" @@ -259,7 +259,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_classic/expects" expect_name = "test_sram_classic_1_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_1_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_1_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_1_12_bi" @@ -268,7 +268,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_classic/expects" expect_name = "test_sram_classic_1_12.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_1_12.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_1_12.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_1_4_bi" @@ -277,7 +277,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_classic/expects" expect_name = "test_sram_classic_1_4.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_1_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_1_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_1_8_bi" @@ -286,7 +286,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_classic/expects" expect_name = "test_sram_classic_1_8.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_1_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_1_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_2_0_bi" @@ -295,7 +295,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_classic/expects" expect_name = "test_sram_classic_2_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_2_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_2_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_2_12_bi" @@ -304,7 +304,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_classic/expects" expect_name = "test_sram_classic_2_12.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_2_12.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_2_12.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_2_4_bi" @@ -313,7 +313,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_classic/expects" expect_name = "test_sram_classic_2_4.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_2_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_2_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_2_8_bi" @@ -322,7 +322,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_classic/expects" expect_name = "test_sram_classic_2_8.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_2_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_2_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_4_0_bi" @@ -331,7 +331,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_classic/expects" expect_name = "test_sram_classic_4_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_4_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_4_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_4_12_bi" @@ -340,7 +340,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_classic/expects" expect_name = "test_sram_classic_4_12.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_4_12.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_4_12.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_4_4_bi" @@ -349,7 +349,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_classic/expects" expect_name = "test_sram_classic_4_4.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_4_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_4_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_4_8_bi" @@ -358,7 +358,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_classic/expects" expect_name = "test_sram_classic_4_8.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_4_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_4_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_8_0_bi" @@ -367,7 +367,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_classic/expects" expect_name = "test_sram_classic_8_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_8_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_8_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_8_12_bi" @@ -376,7 +376,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_classic/expects" expect_name = "test_sram_classic_8_12.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_8_12.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_8_12.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_8_4_bi" @@ -385,7 +385,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_classic/expects" expect_name = "test_sram_classic_8_4.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_8_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_8_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_8_8_bi" @@ -394,7 +394,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_classic/expects" expect_name = "test_sram_classic_8_8.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_8_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_8_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_0_0_bi" @@ -403,7 +403,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_16_0_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_0_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_0_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_0_1_bi" @@ -412,7 +412,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_16_0_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_0_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_0_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_0_2_bi" @@ -421,7 +421,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_16_0_2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_0_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_0_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_0_3_bi" @@ -430,7 +430,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_16_0_3.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_0_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_0_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_12_0_bi" @@ -439,7 +439,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_16_12_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_12_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_12_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_12_1_bi" @@ -448,7 +448,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_16_12_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_12_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_12_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_12_2_bi" @@ -457,7 +457,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_16_12_2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_12_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_12_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_12_3_bi" @@ -466,7 +466,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_16_12_3.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_12_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_12_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_4_0_bi" @@ -475,7 +475,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_16_4_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_4_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_4_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_4_1_bi" @@ -484,7 +484,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_16_4_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_4_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_4_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_4_2_bi" @@ -493,7 +493,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_16_4_2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_4_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_4_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_4_3_bi" @@ -502,7 +502,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_16_4_3.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_4_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_4_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_8_0_bi" @@ -511,7 +511,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_16_8_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_8_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_8_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_8_1_bi" @@ -520,7 +520,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_16_8_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_8_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_8_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_8_2_bi" @@ -529,7 +529,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_16_8_2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_8_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_8_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_8_3_bi" @@ -538,7 +538,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_16_8_3.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_8_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_8_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_0_0_bi" @@ -547,7 +547,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_1_0_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_0_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_0_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_0_1_bi" @@ -556,7 +556,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_1_0_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_0_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_0_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_0_2_bi" @@ -565,7 +565,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_1_0_2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_0_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_0_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_0_3_bi" @@ -574,7 +574,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_1_0_3.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_0_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_0_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_12_0_bi" @@ -583,7 +583,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_1_12_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_12_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_12_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_12_1_bi" @@ -592,7 +592,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_1_12_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_12_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_12_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_12_2_bi" @@ -601,7 +601,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_1_12_2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_12_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_12_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_12_3_bi" @@ -610,7 +610,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_1_12_3.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_12_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_12_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_4_0_bi" @@ -619,7 +619,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_1_4_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_4_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_4_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_4_1_bi" @@ -628,7 +628,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_1_4_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_4_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_4_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_4_2_bi" @@ -637,7 +637,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_1_4_2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_4_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_4_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_4_3_bi" @@ -646,7 +646,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_1_4_3.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_4_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_4_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_8_0_bi" @@ -655,7 +655,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_1_8_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_8_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_8_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_8_1_bi" @@ -664,7 +664,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_1_8_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_8_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_8_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_8_2_bi" @@ -673,7 +673,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_1_8_2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_8_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_8_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_8_3_bi" @@ -682,7 +682,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_1_8_3.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_8_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_8_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_0_0_bi" @@ -691,7 +691,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_2_0_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_0_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_0_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_0_1_bi" @@ -700,7 +700,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_2_0_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_0_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_0_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_0_2_bi" @@ -709,7 +709,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_2_0_2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_0_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_0_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_0_3_bi" @@ -718,7 +718,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_2_0_3.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_0_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_0_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_12_0_bi" @@ -727,7 +727,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_2_12_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_12_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_12_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_12_1_bi" @@ -736,7 +736,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_2_12_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_12_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_12_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_12_2_bi" @@ -745,7 +745,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_2_12_2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_12_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_12_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_12_3_bi" @@ -754,7 +754,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_2_12_3.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_12_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_12_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_4_0_bi" @@ -763,7 +763,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_2_4_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_4_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_4_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_4_1_bi" @@ -772,7 +772,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_2_4_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_4_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_4_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_4_2_bi" @@ -781,7 +781,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_2_4_2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_4_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_4_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_4_3_bi" @@ -790,7 +790,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_2_4_3.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_4_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_4_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_8_0_bi" @@ -799,7 +799,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_2_8_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_8_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_8_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_8_1_bi" @@ -808,7 +808,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_2_8_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_8_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_8_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_8_2_bi" @@ -817,7 +817,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_2_8_2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_8_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_8_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_8_3_bi" @@ -826,7 +826,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_2_8_3.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_8_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_8_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_0_0_bi" @@ -835,7 +835,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_4_0_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_0_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_0_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_0_1_bi" @@ -844,7 +844,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_4_0_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_0_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_0_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_0_2_bi" @@ -853,7 +853,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_4_0_2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_0_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_0_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_0_3_bi" @@ -862,7 +862,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_4_0_3.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_0_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_0_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_12_0_bi" @@ -871,7 +871,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_4_12_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_12_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_12_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_12_1_bi" @@ -880,7 +880,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_4_12_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_12_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_12_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_12_2_bi" @@ -889,7 +889,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_4_12_2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_12_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_12_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_12_3_bi" @@ -898,7 +898,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_4_12_3.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_12_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_12_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_4_0_bi" @@ -907,7 +907,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_4_4_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_4_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_4_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_4_1_bi" @@ -916,7 +916,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_4_4_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_4_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_4_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_4_2_bi" @@ -925,7 +925,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_4_4_2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_4_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_4_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_4_3_bi" @@ -934,7 +934,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_4_4_3.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_4_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_4_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_8_0_bi" @@ -943,7 +943,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_4_8_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_8_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_8_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_8_1_bi" @@ -952,7 +952,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_4_8_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_8_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_8_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_8_2_bi" @@ -961,7 +961,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_4_8_2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_8_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_8_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_8_3_bi" @@ -970,7 +970,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_4_8_3.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_8_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_8_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_0_0_bi" @@ -979,7 +979,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_8_0_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_0_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_0_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_0_1_bi" @@ -988,7 +988,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_8_0_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_0_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_0_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_0_2_bi" @@ -997,7 +997,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_8_0_2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_0_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_0_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_0_3_bi" @@ -1006,7 +1006,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_8_0_3.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_0_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_0_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_12_0_bi" @@ -1015,7 +1015,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_8_12_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_12_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_12_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_12_1_bi" @@ -1024,7 +1024,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_8_12_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_12_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_12_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_12_2_bi" @@ -1033,7 +1033,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_8_12_2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_12_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_12_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_12_3_bi" @@ -1042,7 +1042,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_8_12_3.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_12_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_12_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_4_0_bi" @@ -1051,7 +1051,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_8_4_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_4_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_4_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_4_1_bi" @@ -1060,7 +1060,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_8_4_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_4_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_4_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_4_2_bi" @@ -1069,7 +1069,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_8_4_2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_4_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_4_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_4_3_bi" @@ -1078,7 +1078,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_8_4_3.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_4_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_4_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_8_0_bi" @@ -1087,7 +1087,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_8_8_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_8_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_8_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_8_1_bi" @@ -1096,7 +1096,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_8_8_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_8_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_8_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_8_2_bi" @@ -1105,7 +1105,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_8_8_2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_8_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_8_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_8_3_bi" @@ -1114,7 +1114,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_8_8_3.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_8_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_8_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_brave_new_world_francis_bit_truncation_fft.bit_truncation_fft_bi" @@ -1123,7 +1123,7 @@ paths = [ ] expect_dir = "../../tests/brave_new_world_francis/expects" expect_name = "bit_truncation_fft.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/brave_new_world_francis/bit_truncation_fft.prot --wave tests/brave_new_world_francis/bit_truncation_fft.fst --instances round11_rne_unsigned_fixed:BitTruncationFFT 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/brave_new_world_francis/bit_truncation_fft.prot --wave tests/brave_new_world_francis/bit_truncation_fft.fst --instances round11_rne_unsigned_fixed:BitTruncationFFT 2>&1" [[tests]] name = "bi.tests_brave_new_world_francis_bit_truncation_sha.bit_truncation_sha_bi" @@ -1132,7 +1132,7 @@ paths = [ ] expect_dir = "../../tests/brave_new_world_francis/expects" expect_name = "bit_truncation_sha.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/brave_new_world_francis/bit_truncation_sha.prot --wave tests/brave_new_world_francis/bit_truncation_sha.fst --instances bit_truncation_sha_fixed:bit_truncation_sha 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/brave_new_world_francis/bit_truncation_sha.prot --wave tests/brave_new_world_francis/bit_truncation_sha.fst --instances bit_truncation_sha_fixed:bit_truncation_sha 2>&1" [[tests]] name = "bi.tests_brave_new_world_francis_ftu_sha.ftu_sha_bi" @@ -1141,7 +1141,7 @@ paths = [ ] expect_dir = "../../tests/brave_new_world_francis/expects" expect_name = "ftu_sha.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/brave_new_world_francis/ftu_sha.prot --wave tests/brave_new_world_francis/ftu_sha.fst --instances fsm_update_fixed_gated:FailureToUpdateSHA 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/brave_new_world_francis/ftu_sha.prot --wave tests/brave_new_world_francis/ftu_sha.fst --instances fsm_update_fixed_gated:FailureToUpdateSHA 2>&1" [[tests]] name = "bi.tests_brave_new_world_francis_signal_async.signal_async_bi" @@ -1150,7 +1150,7 @@ paths = [ ] expect_dir = "../../tests/brave_new_world_francis/expects" expect_name = "signal_async.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/brave_new_world_francis/signal_async.prot --wave tests/brave_new_world_francis/signal_async.fst --instances signal_async_fix:SignalAsyncSpec 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/brave_new_world_francis/signal_async.prot --wave tests/brave_new_world_francis/signal_async.fst --instances signal_async_fix:SignalAsyncSpec 2>&1" [[tests]] name = "bi.tests_brave_new_world_francis_use_without_valid.use_without_valid_bi" @@ -1159,7 +1159,7 @@ paths = [ ] expect_dir = "../../tests/brave_new_world_francis/expects" expect_name = "use_without_valid.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/brave_new_world_francis/use_without_valid.prot --wave tests/brave_new_world_francis/use_without_valid.fst --instances use_without_valid_fix:UseWithoutValid 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/brave_new_world_francis/use_without_valid.prot --wave tests/brave_new_world_francis/use_without_valid.fst --instances use_without_valid_fix:UseWithoutValid 2>&1" [[tests]] name = "bi.tests_ethmac_ethmac_wishbone_manager.ethmac_wishbone_manager_bi" @@ -1168,7 +1168,7 @@ paths = [ ] expect_dir = "../../tests/ethmac/expects" expect_name = "ethmac_wishbone_manager.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/ethmac/ethmac_wishbone_manager.prot --instances tb_ethernet:WBManager --sample-posedge tb_ethernet.wb_clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/ethmac/ethmac_wishbone_manager.prot --instances tb_ethernet:WBManager --sample-posedge tb_ethernet.wb_clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_ethmac_ethmac_wishbone_subordinate.ethmac_wishbone_subordinate_bi" @@ -1177,7 +1177,7 @@ paths = [ ] expect_dir = "../../tests/ethmac/expects" expect_name = "ethmac_wishbone_subordinate.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/ethmac/ethmac_wishbone_subordinate.prot --instances tb_ethernet:WBSubordinate --sample-posedge tb_ethernet.wb_clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/ethmac/ethmac_wishbone_subordinate.prot --instances tb_ethernet:WBSubordinate --sample-posedge tb_ethernet.wb_clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_fifo_fifo_monitor.fifo_bi" @@ -1186,7 +1186,7 @@ paths = [ ] expect_dir = "../../tests/fifo/expects" expect_name = "fifo.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/fifo/fifo.monitor.prot --wave tests/fifo/fifo.fst --instances fifo_wrapper:Fifo 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/fifo/fifo.monitor.prot --wave tests/fifo/fifo.fst --instances fifo_wrapper:Fifo 2>&1" [[tests]] name = "bi.tests_fifo_push_pop_identity.push_pop_identity_bi" @@ -1195,7 +1195,7 @@ paths = [ ] expect_dir = "../../tests/fifo/expects" expect_name = "push_pop_identity.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/fifo/push_pop_identity.prot --wave tests/fifo/push_pop_identity.fst --instances fifo_wrapper:Fifo 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/fifo/push_pop_identity.prot --wave tests/fifo/push_pop_identity.fst --instances fifo_wrapper:Fifo 2>&1" [[tests]] name = "bi.tests_fifo_push_pop_loop_empty.push_pop_loop_empty_bi" @@ -1204,7 +1204,7 @@ paths = [ ] expect_dir = "../../tests/fifo/expects" expect_name = "push_pop_loop_empty.bi.expect" -cmd = "cd ../.. && python3 -c 'import os, signal, subprocess, sys\np = subprocess.Popen(sys.argv[2:], start_new_session=True)\ntry:\n sys.exit(p.wait(timeout=float(sys.argv[1])))\nexcept subprocess.TimeoutExpired:\n os.killpg(p.pid, signal.SIGKILL)\n sys.exit(124)\n' 5 target/debug/bi --protocol tests/fifo/push_pop_loop_empty.prot --wave tests/fifo/push_pop_loop_empty.fst --instances fifo_wrapper:Fifo 2>/dev/null" +cmd = "cd ../.. && python3 -c 'import os, signal, subprocess, sys\np = subprocess.Popen(sys.argv[2:], start_new_session=True)\ntry:\n sys.exit(p.wait(timeout=float(sys.argv[1])))\nexcept subprocess.TimeoutExpired:\n os.killpg(p.pid, signal.SIGKILL)\n sys.exit(124)\n' 5 target/debug/bi --protocol tests/fifo/push_pop_loop_empty.prot --wave tests/fifo/push_pop_loop_empty.fst --instances fifo_wrapper:Fifo 2>&1" [[tests]] name = "bi.tests_fifo_push_pop_loop_not_empty.push_pop_loop_not_empty_bi" @@ -1213,7 +1213,7 @@ paths = [ ] expect_dir = "../../tests/fifo/expects" expect_name = "push_pop_loop_not_empty.bi.expect" -cmd = "cd ../.. && python3 -c 'import os, signal, subprocess, sys\np = subprocess.Popen(sys.argv[2:], start_new_session=True)\ntry:\n sys.exit(p.wait(timeout=float(sys.argv[1])))\nexcept subprocess.TimeoutExpired:\n os.killpg(p.pid, signal.SIGKILL)\n sys.exit(124)\n' 5 target/debug/bi --protocol tests/fifo/push_pop_loop_not_empty.prot --wave tests/fifo/push_pop_loop_not_empty.fst --instances fifo_wrapper:Fifo 2>/dev/null" +cmd = "cd ../.. && python3 -c 'import os, signal, subprocess, sys\np = subprocess.Popen(sys.argv[2:], start_new_session=True)\ntry:\n sys.exit(p.wait(timeout=float(sys.argv[1])))\nexcept subprocess.TimeoutExpired:\n os.killpg(p.pid, signal.SIGKILL)\n sys.exit(124)\n' 5 target/debug/bi --protocol tests/fifo/push_pop_loop_not_empty.prot --wave tests/fifo/push_pop_loop_not_empty.fst --instances fifo_wrapper:Fifo 2>&1" [[tests]] name = "bi.tests_fpga_debugging_axi_burst_s4_s4_buggy.s4_buggy_bi" @@ -1222,7 +1222,7 @@ paths = [ ] expect_dir = "../../tests/fpga-debugging/axi-burst-s4/expects" expect_name = "s4_buggy.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axi-burst-s4/s4_buggy.prot --wave tests/fpga-debugging/axi-burst-s4/s4_buggy.vcd --instances TOP.test_l2_cache_wait_state.axi_bus:WriteSubordinate --sample-posedge TOP.test_l2_cache_wait_state.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axi-burst-s4/s4_buggy.prot --wave tests/fpga-debugging/axi-burst-s4/s4_buggy.vcd --instances TOP.test_l2_cache_wait_state.axi_bus:WriteSubordinate --sample-posedge TOP.test_l2_cache_wait_state.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_fpga_debugging_axi_burst_s4_s4_fixed.s4_fixed_bi" @@ -1231,7 +1231,7 @@ paths = [ ] expect_dir = "../../tests/fpga-debugging/axi-burst-s4/expects" expect_name = "s4_fixed.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axi-burst-s4/s4_fixed.prot --wave tests/fpga-debugging/axi-burst-s4/s4_fixed.vcd --instances TOP.test_l2_cache_wait_state.axi_bus:WriteSubordinate --sample-posedge TOP.test_l2_cache_wait_state.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axi-burst-s4/s4_fixed.prot --wave tests/fpga-debugging/axi-burst-s4/s4_fixed.vcd --instances TOP.test_l2_cache_wait_state.axi_bus:WriteSubordinate --sample-posedge TOP.test_l2_cache_wait_state.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_fpga_debugging_axi_lite_s1_s1_buggy.s1_buggy_bi" @@ -1240,7 +1240,7 @@ paths = [ ] expect_dir = "../../tests/fpga-debugging/axi-lite-s1/expects" expect_name = "s1_buggy.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axi-lite-s1/s1_buggy.prot --wave tests/fpga-debugging/axi-lite-s1/s1_buggy_workload2.vcd --instances TOP.testbench.UUT:WriteSubordinate TOP.testbench.UUT:ReadSubordinate --sample-posedge TOP.testbench.UUT.S_AXI_ACLK --show-waveform-time --time-unit ns --include-idle 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axi-lite-s1/s1_buggy.prot --wave tests/fpga-debugging/axi-lite-s1/s1_buggy_workload2.vcd --instances TOP.testbench.UUT:WriteSubordinate TOP.testbench.UUT:ReadSubordinate --sample-posedge TOP.testbench.UUT.S_AXI_ACLK --show-waveform-time --time-unit ns --include-idle 2>&1" [[tests]] name = "bi.tests_fpga_debugging_axi_lite_s1_s1_buggy_workload_1.s1_buggy_workload_1_bi" @@ -1249,7 +1249,7 @@ paths = [ ] expect_dir = "../../tests/fpga-debugging/axi-lite-s1/expects" expect_name = "s1_buggy_workload_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot --wave tests/fpga-debugging/axi-lite-s1/s1_buggy_workload1.vcd --instances TOP.testbench.UUT:WriteSubordinate TOP.testbench.UUT:ReadSubordinate --sample-posedge TOP.testbench.UUT.S_AXI_ACLK --show-waveform-time --time-unit ns --include-idle 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot --wave tests/fpga-debugging/axi-lite-s1/s1_buggy_workload1.vcd --instances TOP.testbench.UUT:WriteSubordinate TOP.testbench.UUT:ReadSubordinate --sample-posedge TOP.testbench.UUT.S_AXI_ACLK --show-waveform-time --time-unit ns --include-idle 2>&1" [[tests]] name = "bi.tests_fpga_debugging_axi_lite_s1_s1_fixed.s1_fixed_bi" @@ -1258,7 +1258,7 @@ paths = [ ] expect_dir = "../../tests/fpga-debugging/axi-lite-s1/expects" expect_name = "s1_fixed.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axi-lite-s1/s1_fixed.prot --wave tests/fpga-debugging/axi-lite-s1/s1_fixed_workload2.vcd --instances TOP.testbench.UUT:WriteSubordinate TOP.testbench.UUT:ReadSubordinate --sample-posedge TOP.testbench.UUT.S_AXI_ACLK --show-waveform-time --time-unit ns --include-idle 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axi-lite-s1/s1_fixed.prot --wave tests/fpga-debugging/axi-lite-s1/s1_fixed_workload2.vcd --instances TOP.testbench.UUT:WriteSubordinate TOP.testbench.UUT:ReadSubordinate --sample-posedge TOP.testbench.UUT.S_AXI_ACLK --show-waveform-time --time-unit ns --include-idle 2>&1" [[tests]] name = "bi.tests_fpga_debugging_axi_lite_s1_s1_fixed_workload_1.s1_fixed_workload_1_bi" @@ -1267,7 +1267,7 @@ paths = [ ] expect_dir = "../../tests/fpga-debugging/axi-lite-s1/expects" expect_name = "s1_fixed_workload_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot --wave tests/fpga-debugging/axi-lite-s1/s1_fixed_workload1.vcd --instances TOP.testbench.UUT:WriteSubordinate TOP.testbench.UUT:ReadSubordinate --sample-posedge TOP.testbench.UUT.S_AXI_ACLK --show-waveform-time --time-unit ns --include-idle 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot --wave tests/fpga-debugging/axi-lite-s1/s1_fixed_workload1.vcd --instances TOP.testbench.UUT:WriteSubordinate TOP.testbench.UUT:ReadSubordinate --sample-posedge TOP.testbench.UUT.S_AXI_ACLK --show-waveform-time --time-unit ns --include-idle 2>&1" [[tests]] name = "bi.tests_fpga_debugging_axi_stream_s2_s2_buggy.s2_buggy_bi" @@ -1276,7 +1276,7 @@ paths = [ ] expect_dir = "../../tests/fpga-debugging/axi-stream-s2/expects" expect_name = "s2_buggy.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axi-stream-s2/s2_buggy.prot --wave tests/fpga-debugging/axi-stream-s2/s2_buggy.fst --instances TOP.testbench.UUT.axi_stream_check:AXISManager --sample-posedge TOP.testbench.UUT.axi_stream_check.i_aclk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axi-stream-s2/s2_buggy.prot --wave tests/fpga-debugging/axi-stream-s2/s2_buggy.fst --instances TOP.testbench.UUT.axi_stream_check:AXISManager --sample-posedge TOP.testbench.UUT.axi_stream_check.i_aclk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_fpga_debugging_axi_stream_s2_s2_fixed.s2_fixed_bi" @@ -1285,7 +1285,7 @@ paths = [ ] expect_dir = "../../tests/fpga-debugging/axi-stream-s2/expects" expect_name = "s2_fixed.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axi-stream-s2/s2_fixed.prot --wave tests/fpga-debugging/axi-stream-s2/s2_fixed.fst --instances TOP.testbench.UUT.axi_stream_check:AXISManager --sample-posedge TOP.testbench.UUT.axi_stream_check.i_aclk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axi-stream-s2/s2_fixed.prot --wave tests/fpga-debugging/axi-stream-s2/s2_fixed.fst --instances TOP.testbench.UUT.axi_stream_check:AXISManager --sample-posedge TOP.testbench.UUT.axi_stream_check.i_aclk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_fpga_debugging_axis_adapter_s3_s3_buggy.s3_buggy_bi" @@ -1294,7 +1294,7 @@ paths = [ ] expect_dir = "../../tests/fpga-debugging/axis-adapter-s3/expects" expect_name = "s3_buggy.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axis-adapter-s3/s3_buggy.prot --wave tests/fpga-debugging/axis-adapter-s3/s3_buggy.fst --instances TOP.test_axis_adapter_64_8.UUT:AXISManager --sample-posedge TOP.test_axis_adapter_64_8.UUT.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axis-adapter-s3/s3_buggy.prot --wave tests/fpga-debugging/axis-adapter-s3/s3_buggy.fst --instances TOP.test_axis_adapter_64_8.UUT:AXISManager --sample-posedge TOP.test_axis_adapter_64_8.UUT.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_fpga_debugging_axis_adapter_s3_s3_fixed.s3_fixed_bi" @@ -1303,7 +1303,7 @@ paths = [ ] expect_dir = "../../tests/fpga-debugging/axis-adapter-s3/expects" expect_name = "s3_fixed.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axis-adapter-s3/s3_fixed.prot --wave tests/fpga-debugging/axis-adapter-s3/s3_fixed.fst --instances TOP.test_axis_adapter_64_8.UUT:AXISManager --sample-posedge TOP.test_axis_adapter_64_8.UUT.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axis-adapter-s3/s3_fixed.prot --wave tests/fpga-debugging/axis-adapter-s3/s3_fixed.fst --instances TOP.test_axis_adapter_64_8.UUT:AXISManager --sample-posedge TOP.test_axis_adapter_64_8.UUT.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_fpga_debugging_axis_async_fifo_c4_c4_buggy.c4_buggy_bi" @@ -1312,7 +1312,7 @@ paths = [ ] expect_dir = "../../tests/fpga-debugging/axis-async-fifo-c4/expects" expect_name = "c4_buggy.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot --wave tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.fst --instances TOP.test_axis_async_fifo.UUT.axis_reg_inst:Sender TOP.test_axis_async_fifo.UUT.axis_reg_inst:Receiver --sample-posedge TOP.test_axis_async_fifo.UUT.axis_reg_inst.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot --wave tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.fst --instances TOP.test_axis_async_fifo.UUT.axis_reg_inst:Sender TOP.test_axis_async_fifo.UUT.axis_reg_inst:Receiver --sample-posedge TOP.test_axis_async_fifo.UUT.axis_reg_inst.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_fpga_debugging_axis_async_fifo_c4_c4_fixed.c4_fixed_bi" @@ -1321,7 +1321,7 @@ paths = [ ] expect_dir = "../../tests/fpga-debugging/axis-async-fifo-c4/expects" expect_name = "c4_fixed.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.prot --wave tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.fst --instances TOP.test_axis_async_fifo.UUT.axis_reg_inst:Sender TOP.test_axis_async_fifo.UUT.axis_reg_inst:Receiver --sample-posedge TOP.test_axis_async_fifo.UUT.axis_reg_inst.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.prot --wave tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.fst --instances TOP.test_axis_async_fifo.UUT.axis_reg_inst:Sender TOP.test_axis_async_fifo.UUT.axis_reg_inst:Receiver --sample-posedge TOP.test_axis_async_fifo.UUT.axis_reg_inst.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_fpga_debugging_axis_fifo_d11_d11_buggy.d11_buggy_bi" @@ -1330,7 +1330,7 @@ paths = [ ] expect_dir = "../../tests/fpga-debugging/axis-fifo-d11/expects" expect_name = "d11_buggy.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axis-fifo-d11/d11_buggy.prot --wave tests/fpga-debugging/axis-fifo-d11/d11_buggy.fst --instances TOP.test_axis_fifo:AxisFifo --sample-posedge TOP.test_axis_fifo.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axis-fifo-d11/d11_buggy.prot --wave tests/fpga-debugging/axis-fifo-d11/d11_buggy.fst --instances TOP.test_axis_fifo:AxisFifo --sample-posedge TOP.test_axis_fifo.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_fpga_debugging_axis_fifo_d11_d11_fixed.d11_fixed_bi" @@ -1339,7 +1339,7 @@ paths = [ ] expect_dir = "../../tests/fpga-debugging/axis-fifo-d11/expects" expect_name = "d11_fixed.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axis-fifo-d11/d11_fixed.prot --wave tests/fpga-debugging/axis-fifo-d11/d11_fixed.fst --instances TOP.test_axis_fifo:AxisFifo --sample-posedge TOP.test_axis_fifo.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axis-fifo-d11/d11_fixed.prot --wave tests/fpga-debugging/axis-fifo-d11/d11_fixed.fst --instances TOP.test_axis_fifo:AxisFifo --sample-posedge TOP.test_axis_fifo.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_fpga_debugging_axis_fifo_d12_d12_buggy.d12_buggy_bi" @@ -1348,7 +1348,7 @@ paths = [ ] expect_dir = "../../tests/fpga-debugging/axis-fifo-d12/expects" expect_name = "d12_buggy.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axis-fifo-d12/d12_buggy.prot --wave tests/fpga-debugging/axis-fifo-d12/d12_buggy.fst --instances TOP.test_axis_fifo:AxisFifo --sample-posedge TOP.test_axis_fifo.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axis-fifo-d12/d12_buggy.prot --wave tests/fpga-debugging/axis-fifo-d12/d12_buggy.fst --instances TOP.test_axis_fifo:AxisFifo --sample-posedge TOP.test_axis_fifo.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_fpga_debugging_axis_fifo_d12_d12_fixed.d12_fixed_bi" @@ -1357,7 +1357,7 @@ paths = [ ] expect_dir = "../../tests/fpga-debugging/axis-fifo-d12/expects" expect_name = "d12_fixed.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axis-fifo-d12/d12_fixed.prot --wave tests/fpga-debugging/axis-fifo-d12/d12_fixed.fst --instances TOP.test_axis_fifo:AxisFifo --sample-posedge TOP.test_axis_fifo.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axis-fifo-d12/d12_fixed.prot --wave tests/fpga-debugging/axis-fifo-d12/d12_fixed.fst --instances TOP.test_axis_fifo:AxisFifo --sample-posedge TOP.test_axis_fifo.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_fpga_debugging_axis_fifo_d4_d4_buggy.d4_buggy_bi" @@ -1366,7 +1366,7 @@ paths = [ ] expect_dir = "../../tests/fpga-debugging/axis-fifo-d4/expects" expect_name = "d4_buggy.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axis-fifo-d4/d4_buggy.prot --wave tests/fpga-debugging/axis-fifo-d4/d4_buggy.fst --instances TOP.axis_fifo_wrapper.axis_fifo_inst:AxisFifo --sample-posedge TOP.axis_fifo_wrapper.axis_fifo_inst.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axis-fifo-d4/d4_buggy.prot --wave tests/fpga-debugging/axis-fifo-d4/d4_buggy.fst --instances TOP.axis_fifo_wrapper.axis_fifo_inst:AxisFifo --sample-posedge TOP.axis_fifo_wrapper.axis_fifo_inst.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_fpga_debugging_axis_fifo_d4_d4_fixed.d4_fixed_bi" @@ -1375,7 +1375,7 @@ paths = [ ] expect_dir = "../../tests/fpga-debugging/axis-fifo-d4/expects" expect_name = "d4_fixed.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axis-fifo-d4/d4_fixed.prot --wave tests/fpga-debugging/axis-fifo-d4/d4_fixed.fst --instances TOP.axis_fifo_wrapper.axis_fifo_inst:AxisFifo --sample-posedge TOP.axis_fifo_wrapper.axis_fifo_inst.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axis-fifo-d4/d4_fixed.prot --wave tests/fpga-debugging/axis-fifo-d4/d4_fixed.fst --instances TOP.axis_fifo_wrapper.axis_fifo_inst:AxisFifo --sample-posedge TOP.axis_fifo_wrapper.axis_fifo_inst.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_identities_identity_d1.identity_d1_bi" @@ -1384,7 +1384,7 @@ paths = [ ] expect_dir = "../../tests/identities/expects" expect_name = "identity_d1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/identities/identity_d1.prot --wave tests/identities/identity_d1.fst --instances identity_d1:Identity 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/identities/identity_d1.prot --wave tests/identities/identity_d1.fst --instances identity_d1:Identity 2>&1" [[tests]] name = "bi.tests_multi_multi0.multi0_bi" @@ -1393,7 +1393,7 @@ paths = [ ] expect_dir = "../../tests/multi/expects" expect_name = "multi0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/multi/multi0.prot --wave tests/multi/multi0.fst --instances multi0:multi0 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/multi/multi0.prot --wave tests/multi/multi0.fst --instances multi0:multi0 2>&1" [[tests]] name = "bi.tests_multi_multi0keep.multi0keep_bi" @@ -1402,7 +1402,7 @@ paths = [ ] expect_dir = "../../tests/multi/expects" expect_name = "multi0keep.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/multi/multi0keep.prot --wave tests/multi/multi0keep.fst --instances multi0keep:multi0keep 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/multi/multi0keep.prot --wave tests/multi/multi0keep.fst --instances multi0keep:multi0keep 2>&1" [[tests]] name = "bi.tests_multi_multi0keep2const.multi0keep2const_bi" @@ -1411,7 +1411,7 @@ paths = [ ] expect_dir = "../../tests/multi/expects" expect_name = "multi0keep2const.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/multi/multi0keep2const.prot --wave tests/multi/multi0keep2const.fst --instances multi0keep2const:multi0keep2const 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/multi/multi0keep2const.prot --wave tests/multi/multi0keep2const.fst --instances multi0keep2const:multi0keep2const 2>&1" [[tests]] name = "bi.tests_multi_multi2const.multi2const_bi" @@ -1420,7 +1420,7 @@ paths = [ ] expect_dir = "../../tests/multi/expects" expect_name = "multi2const.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/multi/multi2const.prot --wave tests/multi/multi2const.fst --instances multi2const:multi2const 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/multi/multi2const.prot --wave tests/multi/multi2const.fst --instances multi2const:multi2const 2>&1" [[tests]] name = "bi.tests_multi_multi2multi.multi2multi_bi" @@ -1429,7 +1429,7 @@ paths = [ ] expect_dir = "../../tests/multi/expects" expect_name = "multi2multi.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/multi/multi2multi.prot --wave tests/multi/multi2multi.fst --instances multi2multi:multi2multi 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/multi/multi2multi.prot --wave tests/multi/multi2multi.fst --instances multi2multi:multi2multi 2>&1" [[tests]] name = "bi.tests_multi_multi_data.multi_data_bi" @@ -1438,7 +1438,7 @@ paths = [ ] expect_dir = "../../tests/multi/expects" expect_name = "multi_data.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/multi/multi_data.prot --wave tests/multi/multi_data.fst --instances multi_data:multi_data 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/multi/multi_data.prot --wave tests/multi/multi_data.fst --instances multi_data:multi_data 2>&1" [[tests]] name = "bi.tests_multipliers_mult_d2.mult_d2_bi" @@ -1447,7 +1447,7 @@ paths = [ ] expect_dir = "../../tests/multipliers/expects" expect_name = "mult_d2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/multipliers/mult_d2.prot --wave tests/multipliers/mult_d2.fst --instances mult_d2:Multiplier 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/multipliers/mult_d2.prot --wave tests/multipliers/mult_d2.fst --instances mult_d2:Multiplier 2>&1" [[tests]] name = "bi.tests_picorv32_pcpi_mul_unsigned_mul.pcpi_mul_unsigned_mul_bi" @@ -1456,7 +1456,7 @@ paths = [ ] expect_dir = "../../tests/picorv32/expects" expect_name = "pcpi_mul_unsigned_mul.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/picorv32/pcpi_mul_unsigned_mul.prot --wave tests/picorv32/unsigned_mul.fst --instances picorv32_pcpi_mul:picorv32_pcpi_mul 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/picorv32/pcpi_mul_unsigned_mul.prot --wave tests/picorv32/unsigned_mul.fst --instances picorv32_pcpi_mul:picorv32_pcpi_mul 2>&1" [[tests]] name = "bi.tests_serv_serv_regfile.serv_regfile_bi" @@ -1465,7 +1465,7 @@ paths = [ ] expect_dir = "../../tests/serv/expects" expect_name = "serv_regfile.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/serv/serv_regfile.prot --wave tests/serv/serv_regfile.fst --instances serv_regfile:Regfile --display-hex 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/serv/serv_regfile.prot --wave tests/serv/serv_regfile.fst --instances serv_regfile:Regfile --display-hex 2>&1" [[tests]] name = "bi.tests_tinyaes128_aes128.aes128_bi" @@ -1474,7 +1474,7 @@ paths = [ ] expect_dir = "../../tests/tinyaes128/expects" expect_name = "aes128.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/tinyaes128/aes128.prot --wave tests/tinyaes128/aes128.fst --instances aes_128:TinyAES128 --display-hex 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/tinyaes128/aes128.prot --wave tests/tinyaes128/aes128.fst --instances aes_128:TinyAES128 --display-hex 2>&1" [[tests]] name = "bi.tests_wal_advanced_axis.axis_bi" @@ -1483,7 +1483,7 @@ paths = [ ] expect_dir = "../../tests/wal/advanced/expects" expect_name = "axis.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/wal/advanced/axis.prot --wave tests/wal/advanced/uart-axi.fst --instances uut_rx:AXIS --sample-posedge uut_rx.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/wal/advanced/axis.prot --wave tests/wal/advanced/uart-axi.fst --instances uut_rx:AXIS --sample-posedge uut_rx.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_wal_advanced_axis_failing.axis_failing_bi" @@ -1492,7 +1492,7 @@ paths = [ ] expect_dir = "../../tests/wal/advanced/expects" expect_name = "axis_failing.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/wal/advanced/axis_failing.prot --wave tests/wal/advanced/uart-axi-minimal.fst --instances uut_rx:AXIS --sample-posedge uut_rx.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/wal/advanced/axis_failing.prot --wave tests/wal/advanced/uart-axi-minimal.fst --instances uut_rx:AXIS --sample-posedge uut_rx.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_wal_advanced_axis_minimal.axis_minimal_bi" @@ -1501,7 +1501,7 @@ paths = [ ] expect_dir = "../../tests/wal/advanced/expects" expect_name = "axis_minimal.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/wal/advanced/axis_minimal.prot --wave tests/wal/advanced/uart-axi-minimal.fst --instances uut_rx:AXIS --sample-posedge uut_rx.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/wal/advanced/axis_minimal.prot --wave tests/wal/advanced/uart-axi-minimal.fst --instances uut_rx:AXIS --sample-posedge uut_rx.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_wal_advanced_axis_truncated.axis_truncated_bi" @@ -1510,7 +1510,7 @@ paths = [ ] expect_dir = "../../tests/wal/advanced/expects" expect_name = "axis_truncated.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/wal/advanced/axis_truncated.prot --wave tests/wal/advanced/uart-axi-truncated.fst --instances uut_rx:AXIS --sample-posedge uut_rx.clk --show-waveform-time --time-unit ns 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/wal/advanced/axis_truncated.prot --wave tests/wal/advanced/uart-axi-truncated.fst --instances uut_rx:AXIS --sample-posedge uut_rx.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_wal_advanced_axis_truncated_include_idle.axis_truncated_include_idle_bi" @@ -1519,7 +1519,7 @@ paths = [ ] expect_dir = "../../tests/wal/advanced/expects" expect_name = "axis_truncated_include_idle.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/wal/advanced/axis_truncated_include_idle.prot --wave tests/wal/advanced/uart-axi-truncated.fst --instances uut_rx:AXIS --sample-posedge uut_rx.clk --show-waveform-time --time-unit ns --include-idle 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/wal/advanced/axis_truncated_include_idle.prot --wave tests/wal/advanced/uart-axi-truncated.fst --instances uut_rx:AXIS --sample-posedge uut_rx.clk --show-waveform-time --time-unit ns --include-idle 2>&1" [[tests]] name = "bi.tests_wb_intercon_wb_arb.wb_arb_bi" @@ -1528,7 +1528,7 @@ paths = [ ] expect_dir = "../../tests/wb_intercon/expects" expect_name = "wb_arb.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/wb_intercon/wb_arb.prot --instances wb_intercon_tb.wb_arb_tb:WBSubordinate --sample-posedge wb_intercon_tb.wb_arb_tb.wb_clk --show-waveform-time --time-unit s 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/wb_intercon/wb_arb.prot --instances wb_intercon_tb.wb_arb_tb:WBSubordinate --sample-posedge wb_intercon_tb.wb_arb_tb.wb_clk --show-waveform-time --time-unit s 2>&1" [[tests]] name = "bi.tests_wb_intercon_wb_cdc.wb_cdc_bi" @@ -1537,7 +1537,7 @@ paths = [ ] expect_dir = "../../tests/wb_intercon/expects" expect_name = "wb_cdc.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/wb_intercon/wb_cdc.prot --wave tests/wb_intercon/wb_cdc.fst --instances wb_intercon_tb.wb_cdc_tb.dut:WBSubordinate --sample-posedge wb_intercon_tb.wb_cdc_tb.dut.wbm_clk --show-waveform-time --time-unit s 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/wb_intercon/wb_cdc.prot --wave tests/wb_intercon/wb_cdc.fst --instances wb_intercon_tb.wb_cdc_tb.dut:WBSubordinate --sample-posedge wb_intercon_tb.wb_cdc_tb.dut.wbm_clk --show-waveform-time --time-unit s 2>&1" [[tests]] name = "bi.tests_wishbone_wishbone_monitor.wishbone_bi" @@ -1546,4 +1546,4 @@ paths = [ ] expect_dir = "../../tests/wishbone/expects" expect_name = "wishbone.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/wishbone/wishbone.monitor.prot --wave tests/wishbone/reqwalker.vcd --instances TOP.reqwalker:WBSubordinate --sample-posedge TOP.reqwalker.i_clk 2>/dev/null" +cmd = "cd ../.. && target/debug/bi --protocol tests/wishbone/wishbone.monitor.prot --wave tests/wishbone/reqwalker.vcd --instances TOP.reqwalker:WBSubordinate --sample-posedge TOP.reqwalker.i_clk 2>&1" From 1a6a54fb175f08d544eb3815a688a685d1a129e9 Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sat, 11 Jul 2026 15:25:47 -0400 Subject: [PATCH 08/55] Update some .expect files --- tests/adders/expects/busy_wait.bi.expect | 4 ++++ .../expects/loop_with_assigns.bi.expect | 4 ++++ .../adders/expects/nested_busy_wait.bi.expect | 4 ++++ .../expects/ethmac_wishbone_manager.bi.expect | 6 ++++++ .../ethmac_wishbone_subordinate.bi.expect | 6 ++++++ .../expects/push_pop_loop_empty.bi.expect | 4 ++++ .../expects/push_pop_loop_not_empty.bi.expect | 4 ++++ .../axi-burst-s4/expects/s4_buggy.bi.expect | 7 +++++++ .../axi-lite-s1/expects/s1_buggy.bi.expect | 13 +++++++++++++ .../expects/s1_buggy_workload_1.bi.expect | 13 +++++++++++++ .../expects/s1_fixed_workload_1.bi.expect | 13 +++++++++++++ .../expects/c4_buggy.bi.expect | 19 +++++++++++++++++++ .../axis-fifo-d4/expects/d4_fixed.bi.expect | 7 +++++++ .../identities/expects/identity_d1.bi.expect | 4 ++++ tests/serv/expects/serv_regfile.bi.expect | 6 ++++++ tests/wal/advanced/expects/axis.bi.expect | 7 +++++++ .../advanced/expects/axis_failing.bi.expect | 7 +++++++ .../advanced/expects/axis_minimal.bi.expect | 7 +++++++ .../advanced/expects/axis_truncated.bi.expect | 7 +++++++ .../axis_truncated_include_idle.bi.expect | 7 +++++++ tests/wb_intercon/expects/wb_arb.bi.expect | 6 ++++++ tests/wb_intercon/expects/wb_cdc.bi.expect | 6 ++++++ 22 files changed, 161 insertions(+) diff --git a/tests/adders/expects/busy_wait.bi.expect b/tests/adders/expects/busy_wait.bi.expect index c9f68b19..89c0b63f 100644 --- a/tests/adders/expects/busy_wait.bi.expect +++ b/tests/adders/expects/busy_wait.bi.expect @@ -1,2 +1,6 @@ + +thread 'main' (11279289) panicked at bi/src/bi.rs:628:21: +[add_busy_wait@00!] Cannot fork at step zero! +note: run with `RUST_BACKTRACE=1` environment variable to display a backtrace ---CODE--- 101 diff --git a/tests/adders/expects/loop_with_assigns.bi.expect b/tests/adders/expects/loop_with_assigns.bi.expect index c9f68b19..9731c459 100644 --- a/tests/adders/expects/loop_with_assigns.bi.expect +++ b/tests/adders/expects/loop_with_assigns.bi.expect @@ -1,2 +1,6 @@ + +thread 'main' (11279247) panicked at bi/src/bi.rs:628:21: +[loop_add@00!] Cannot fork at step zero! +note: run with `RUST_BACKTRACE=1` environment variable to display a backtrace ---CODE--- 101 diff --git a/tests/adders/expects/nested_busy_wait.bi.expect b/tests/adders/expects/nested_busy_wait.bi.expect index c9f68b19..9e40a38e 100644 --- a/tests/adders/expects/nested_busy_wait.bi.expect +++ b/tests/adders/expects/nested_busy_wait.bi.expect @@ -1,2 +1,6 @@ + +thread 'main' (11280027) panicked at bi/src/bi.rs:628:21: +[nested_busy_wait@00!] Cannot fork at step zero! +note: run with `RUST_BACKTRACE=1` environment variable to display a backtrace ---CODE--- 101 diff --git a/tests/ethmac/expects/ethmac_wishbone_manager.bi.expect b/tests/ethmac/expects/ethmac_wishbone_manager.bi.expect index 57404ebb..7a3afdf3 100644 --- a/tests/ethmac/expects/ethmac_wishbone_manager.bi.expect +++ b/tests/ethmac/expects/ethmac_wishbone_manager.bi.expect @@ -1,2 +1,8 @@ +error: the following required arguments were not provided: + --wave + +Usage: bi --protocol --wave --show-waveform-time --instances ... --sample-posedge --time-unit + +For more information, try '--help'. ---CODE--- 2 diff --git a/tests/ethmac/expects/ethmac_wishbone_subordinate.bi.expect b/tests/ethmac/expects/ethmac_wishbone_subordinate.bi.expect index 57404ebb..7a3afdf3 100644 --- a/tests/ethmac/expects/ethmac_wishbone_subordinate.bi.expect +++ b/tests/ethmac/expects/ethmac_wishbone_subordinate.bi.expect @@ -1,2 +1,8 @@ +error: the following required arguments were not provided: + --wave + +Usage: bi --protocol --wave --show-waveform-time --instances ... --sample-posedge --time-unit + +For more information, try '--help'. ---CODE--- 2 diff --git a/tests/fifo/expects/push_pop_loop_empty.bi.expect b/tests/fifo/expects/push_pop_loop_empty.bi.expect index c9f68b19..d7e93258 100644 --- a/tests/fifo/expects/push_pop_loop_empty.bi.expect +++ b/tests/fifo/expects/push_pop_loop_empty.bi.expect @@ -1,2 +1,6 @@ + +thread 'main' (11280531) panicked at bi/src/bi.rs:628:21: +[pop_n_times@00!] Cannot fork at step zero! +note: run with `RUST_BACKTRACE=1` environment variable to display a backtrace ---CODE--- 101 diff --git a/tests/fifo/expects/push_pop_loop_not_empty.bi.expect b/tests/fifo/expects/push_pop_loop_not_empty.bi.expect index c9f68b19..d4b3f3d1 100644 --- a/tests/fifo/expects/push_pop_loop_not_empty.bi.expect +++ b/tests/fifo/expects/push_pop_loop_not_empty.bi.expect @@ -1,2 +1,6 @@ + +thread 'main' (11280497) panicked at bi/src/bi.rs:628:21: +[pop_n_times@00!] Cannot fork at step zero! +note: run with `RUST_BACKTRACE=1` environment variable to display a backtrace ---CODE--- 101 diff --git a/tests/fpga-debugging/axi-burst-s4/expects/s4_buggy.bi.expect b/tests/fpga-debugging/axi-burst-s4/expects/s4_buggy.bi.expect index 207ca5c9..a587ff56 100644 --- a/tests/fpga-debugging/axi-burst-s4/expects/s4_buggy.bi.expect +++ b/tests/fpga-debugging/axi-burst-s4/expects/s4_buggy.bi.expect @@ -1,5 +1,12 @@ // trace 0 trace { } +error: [write_burst@95] executing step 67 of the transaction: 0 != 1 + ┌─ tests/fpga-debugging/axi-burst-s4/s4_buggy.prot:63:5 + │ +63 │ DUT.m_wlast := 1'b1; + │ ^^^^^^^^^^^^^^^^^^^^ [write_burst@95] executing step 67 of the transaction: 0 != 1 + +Error: "Monitor failed" ---CODE--- 1 diff --git a/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy.bi.expect b/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy.bi.expect index cf728602..fe49b2c9 100644 --- a/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy.bi.expect +++ b/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy.bi.expect @@ -7,10 +7,23 @@ trace { trace { idle(); // [time: 0ns -> 25ns] } +error: [read_v2@11?1!] executing step 3 of the transaction: 1 != 0 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy.prot:169:5 + │ +169 │ assert_eq(DUT.S_AXI_ARREADY, 1'b0); + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@11?1!] executing step 3 of the transaction: 1 != 0 + // trace 1 trace { idle(); // [time: 0ns -> 25ns] } +error: [read_v2@11?2?] executing step 3 of the transaction: 1 != 0 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy.prot:163:9 + │ +163 │ DUT.S_AXI_RREADY := 1'b0; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@11?2?] executing step 3 of the transaction: 1 != 0 + +Error: "Monitor failed" ---CODE--- 1 diff --git a/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy_workload_1.bi.expect b/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy_workload_1.bi.expect index c3233582..b5e51f71 100644 --- a/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy_workload_1.bi.expect +++ b/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy_workload_1.bi.expect @@ -15,6 +15,12 @@ trace { idle(); // [time: 0ns -> 25ns] read_v1(64, 0); // [time: 25ns -> 100ns] } +error: [read_v2@4] executing step 0 of the transaction: 0 != 1 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot:161:5 + │ +161 │ DUT.S_AXI_ARVALID := 1'b1; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@4] executing step 0 of the transaction: 0 != 1 + // trace 1 trace { @@ -27,6 +33,12 @@ trace { idle(); // [time: 0ns -> 25ns] read_v1(64, 0); // [time: 25ns -> 100ns] } +error: [idle@4] executing step 0 of the transaction: 1 != 0 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot:108:5 + │ +108 │ DUT.S_AXI_RREADY := 1'b0; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [idle@4] executing step 0 of the transaction: 1 != 0 + // trace 3 trace { @@ -45,5 +57,6 @@ trace { idle(); // [time: 0ns -> 25ns] read_v2(64, 0, 0); // [time: 25ns -> 100ns] } +Error: "Monitor failed" ---CODE--- 1 diff --git a/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed_workload_1.bi.expect b/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed_workload_1.bi.expect index d0ba43e7..5c9957cb 100644 --- a/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed_workload_1.bi.expect +++ b/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed_workload_1.bi.expect @@ -7,6 +7,12 @@ trace { idle(); // [time: 0ns -> 25ns] read_v1(64, 0); // [time: 25ns -> 100ns] } +error: [read_v2@4] executing step 0 of the transaction: 0 != 1 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot:161:5 + │ +161 │ DUT.S_AXI_ARVALID := 1'b1; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@4] executing step 0 of the transaction: 0 != 1 + // trace 1 trace { @@ -19,6 +25,12 @@ trace { idle(); // [time: 0ns -> 25ns] read_v1(64, 0); // [time: 25ns -> 100ns] } +error: [idle@4] executing step 0 of the transaction: 1 != 0 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot:108:5 + │ +108 │ DUT.S_AXI_RREADY := 1'b0; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [idle@4] executing step 0 of the transaction: 1 != 0 + // trace 3 trace { @@ -37,5 +49,6 @@ trace { idle(); // [time: 0ns -> 25ns] read_v2(64, 0, 0); // [time: 25ns -> 100ns] } +Error: "Monitor failed" ---CODE--- 1 diff --git a/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.bi.expect b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.bi.expect index c233b7bd..2b823d8c 100644 --- a/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.bi.expect +++ b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.bi.expect @@ -14,15 +14,34 @@ trace { trace { reset(); // [time: 0ns -> 25ns] } +error: [reset@1] executing step 0 of the transaction: 0 != 1 + ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot:115:5 + │ +115 │ DUT.rst := 1'b1; + │ ^^^^^^^^^^^^^^^^ [reset@1] executing step 0 of the transaction: 0 != 1 + // trace 1 trace { reset(); // [time: 0ns -> 25ns] } +error: [idle@1] executing step 0 of the transaction: 1 != 0 + ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot:97:5 + │ +97 │ DUT.m_axis_tready := 1'b0; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [idle@1] executing step 0 of the transaction: 1 != 0 + // trace 2 trace { reset(); // [time: 0ns -> 25ns] } +error: [pop@1] executing step 0 of the transaction: 0 != 1 + ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot:62:5 + │ +62 │ assert_eq(DUT.m_axis_tvalid, 1'b1); + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ [pop@1] executing step 0 of the transaction: 0 != 1 + +Error: "Monitor failed" ---CODE--- 1 diff --git a/tests/fpga-debugging/axis-fifo-d4/expects/d4_fixed.bi.expect b/tests/fpga-debugging/axis-fifo-d4/expects/d4_fixed.bi.expect index 2eabcecc..c1126f66 100644 --- a/tests/fpga-debugging/axis-fifo-d4/expects/d4_fixed.bi.expect +++ b/tests/fpga-debugging/axis-fifo-d4/expects/d4_fixed.bi.expect @@ -44,5 +44,12 @@ trace { push(9); // [time: 140ns -> 142.5ns] push(233); // [time: 142.5ns -> 145ns] } +error: [push@63] executing step 1 of the transaction: 01 != 00 + ┌─ tests/fpga-debugging/axis-fifo-d4/d4_fixed.prot:89:5 + │ +89 │ DUT.s_axis_tdata := data; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^ [push@63] executing step 1 of the transaction: 01 != 00 + +Error: "Monitor failed" ---CODE--- 1 diff --git a/tests/identities/expects/identity_d1.bi.expect b/tests/identities/expects/identity_d1.bi.expect index c9f68b19..23ce9225 100644 --- a/tests/identities/expects/identity_d1.bi.expect +++ b/tests/identities/expects/identity_d1.bi.expect @@ -1,2 +1,6 @@ + +thread 'main' (11280585) panicked at bi/src/bi.rs:739:29: +not yet implemented: we currently expect one side of an assert_eq to be a port! +note: run with `RUST_BACKTRACE=1` environment variable to display a backtrace ---CODE--- 101 diff --git a/tests/serv/expects/serv_regfile.bi.expect b/tests/serv/expects/serv_regfile.bi.expect index c9f68b19..605f9cb1 100644 --- a/tests/serv/expects/serv_regfile.bi.expect +++ b/tests/serv/expects/serv_regfile.bi.expect @@ -1,2 +1,8 @@ + +thread 'main' (11280470) panicked at bi/src/constraints.rs:120:9: +assertion `left == right` failed + left: 32 + right: 1 +note: run with `RUST_BACKTRACE=1` environment variable to display a backtrace ---CODE--- 101 diff --git a/tests/wal/advanced/expects/axis.bi.expect b/tests/wal/advanced/expects/axis.bi.expect index dc460c13..e23f591a 100644 --- a/tests/wal/advanced/expects/axis.bi.expect +++ b/tests/wal/advanced/expects/axis.bi.expect @@ -5,5 +5,12 @@ trace { send_data(2); // [time: 2212ns -> 2220ns] send_data(3); // [time: 2916ns -> 2924ns] } +error: [send_data@453] executing step 88 of the transaction: 05 != 04 + ┌─ tests/wal/advanced/axis.prot:10:5 + │ +10 │ D.m_axis_tdata := data; + │ ^^^^^^^^^^^^^^^^^^^^^^^ [send_data@453] executing step 88 of the transaction: 05 != 04 + +Error: "Monitor failed" ---CODE--- 1 diff --git a/tests/wal/advanced/expects/axis_failing.bi.expect b/tests/wal/advanced/expects/axis_failing.bi.expect index 207ca5c9..1f448f01 100644 --- a/tests/wal/advanced/expects/axis_failing.bi.expect +++ b/tests/wal/advanced/expects/axis_failing.bi.expect @@ -1,5 +1,12 @@ // trace 0 trace { } +error: [idle@0] executing step 0 of the transaction: 1 != 0 + ┌─ tests/wal/advanced/axis_failing.prot:11:5 + │ +11 │ D.m_axis_tvalid := 1'b0; + │ ^^^^^^^^^^^^^^^^^^^^^^^^ [idle@0] executing step 0 of the transaction: 1 != 0 + +Error: "Monitor failed" ---CODE--- 1 diff --git a/tests/wal/advanced/expects/axis_minimal.bi.expect b/tests/wal/advanced/expects/axis_minimal.bi.expect index 207ca5c9..e8a5c963 100644 --- a/tests/wal/advanced/expects/axis_minimal.bi.expect +++ b/tests/wal/advanced/expects/axis_minimal.bi.expect @@ -1,5 +1,12 @@ // trace 0 trace { } +error: [send_data@0] executing step 3 of the transaction: 0f != 14 + ┌─ tests/wal/advanced/axis_minimal.prot:10:5 + │ +10 │ D.m_axis_tdata := data; + │ ^^^^^^^^^^^^^^^^^^^^^^^ [send_data@0] executing step 3 of the transaction: 0f != 14 + +Error: "Monitor failed" ---CODE--- 1 diff --git a/tests/wal/advanced/expects/axis_truncated.bi.expect b/tests/wal/advanced/expects/axis_truncated.bi.expect index 207ca5c9..577148ad 100644 --- a/tests/wal/advanced/expects/axis_truncated.bi.expect +++ b/tests/wal/advanced/expects/axis_truncated.bi.expect @@ -1,5 +1,12 @@ // trace 0 trace { } +error: [send_data@0] executing step 88 of the transaction: 0f != 0e + ┌─ tests/wal/advanced/axis_truncated.prot:10:5 + │ +10 │ D.m_axis_tdata := data; + │ ^^^^^^^^^^^^^^^^^^^^^^^ [send_data@0] executing step 88 of the transaction: 0f != 0e + +Error: "Monitor failed" ---CODE--- 1 diff --git a/tests/wal/advanced/expects/axis_truncated_include_idle.bi.expect b/tests/wal/advanced/expects/axis_truncated_include_idle.bi.expect index 207ca5c9..dcebb83c 100644 --- a/tests/wal/advanced/expects/axis_truncated_include_idle.bi.expect +++ b/tests/wal/advanced/expects/axis_truncated_include_idle.bi.expect @@ -1,5 +1,12 @@ // trace 0 trace { } +error: [send_data@0] executing step 88 of the transaction: 0f != 0e + ┌─ tests/wal/advanced/axis_truncated_include_idle.prot:11:5 + │ +11 │ D.m_axis_tdata := data; + │ ^^^^^^^^^^^^^^^^^^^^^^^ [send_data@0] executing step 88 of the transaction: 0f != 0e + +Error: "Monitor failed" ---CODE--- 1 diff --git a/tests/wb_intercon/expects/wb_arb.bi.expect b/tests/wb_intercon/expects/wb_arb.bi.expect index 57404ebb..7a3afdf3 100644 --- a/tests/wb_intercon/expects/wb_arb.bi.expect +++ b/tests/wb_intercon/expects/wb_arb.bi.expect @@ -1,2 +1,8 @@ +error: the following required arguments were not provided: + --wave + +Usage: bi --protocol --wave --show-waveform-time --instances ... --sample-posedge --time-unit + +For more information, try '--help'. ---CODE--- 2 diff --git a/tests/wb_intercon/expects/wb_cdc.bi.expect b/tests/wb_intercon/expects/wb_cdc.bi.expect index c9f68b19..98d73982 100644 --- a/tests/wb_intercon/expects/wb_cdc.bi.expect +++ b/tests/wb_intercon/expects/wb_cdc.bi.expect @@ -1,2 +1,8 @@ + +thread 'main' (11280542) panicked at bi/src/main.rs:90:9: +assertion `left == right` failed: Only nano seconds are supported + left: "s" + right: "ns" +note: run with `RUST_BACKTRACE=1` environment variable to display a backtrace ---CODE--- 101 From 87e6d3c7c1fe751ba39285097b2a2b7655145515 Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sat, 11 Jul 2026 15:25:56 -0400 Subject: [PATCH 09/55] Add --color CLI arg to BI to suppress colors --- bi/src/main.rs | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/bi/src/main.rs b/bi/src/main.rs index 6ab49d37..3b97896f 100644 --- a/bi/src/main.rs +++ b/bi/src/main.rs @@ -75,6 +75,11 @@ struct Cli { #[arg(long)] max_traces: Option, + /// To suppress colors in error messages, pass in `--color never`. + /// Otherwise, by default, error messages are displayed with colors. + #[arg(long, value_name = "COLOR_CHOICE", default_value = "auto")] + color: ColorChoice, + /// If enabled, displays integer literals using hexadecimal notation #[arg(short, long, value_name = "DISPLAY_IN_HEX")] display_hex: bool, @@ -96,7 +101,7 @@ fn main() -> Result<(), Box> { // parse protocol file let show_warnings = false; let skip_static_step_fork_checks = false; - let mut d = DiagnosticHandler::new(ColorChoice::Auto, false, show_warnings, false); + let mut d = DiagnosticHandler::new(cli.color, false, show_warnings, false); let (st, modules) = frontend(&cli.protocol, &mut d, skip_static_step_fork_checks)?; // try to find instances that we care about From 2ed33f965af896ed2eb3c2ceb7fb4943a1d8164e Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sat, 11 Jul 2026 15:26:07 -0400 Subject: [PATCH 10/55] Pass --color never to BI when running Runt tests --- scripts/generate_runt_configs.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/scripts/generate_runt_configs.py b/scripts/generate_runt_configs.py index 3cf158af..d7c7df91 100644 --- a/scripts/generate_runt_configs.py +++ b/scripts/generate_runt_configs.py @@ -195,9 +195,11 @@ def monitor_runt_command(case: dict) -> list[tuple[str, str]]: return [("", repo_root_command(cmd))] -# Same as `monitor_runt_command` above but for BI test cases +# Same as `monitor_runt_command` above but for the BI test cases def bi_runt_command(case: dict) -> list[tuple[str, str]]: - cmd = [*binary_prefix("bi"), "--protocol", case["path"]] + # We pass in `--color never` to BI to suppress color in error messages + # (so that the .expect files only display plaintext) + cmd = [*binary_prefix("bi"), "--color", "never", "--protocol", case["path"]] if case["wave"]: cmd += ["--wave", case["wave"]] if case["instances"]: From f2e9e3b127971bcbb70a60a9d54fc78aaa786def Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sat, 11 Jul 2026 15:26:16 -0400 Subject: [PATCH 11/55] Update auto-generated Runt BI config --- runt/bi/runt.toml | 344 +++++++++++++++++++++++----------------------- 1 file changed, 172 insertions(+), 172 deletions(-) diff --git a/runt/bi/runt.toml b/runt/bi/runt.toml index 8ac7ae9d..c188ce6f 100644 --- a/runt/bi/runt.toml +++ b/runt/bi/runt.toml @@ -7,7 +7,7 @@ paths = [ ] expect_dir = "../../tests/adders/expects" expect_name = "add_d1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/adders/add_d1.prot --wave tests/adders/add_d1.fst --instances add_d1:Adder 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/adders/add_d1.prot --wave tests/adders/add_d1.fst --instances add_d1:Adder 2>&1" [[tests]] name = "bi.tests_adders_add_d2.add_d2_bi" @@ -16,7 +16,7 @@ paths = [ ] expect_dir = "../../tests/adders/expects" expect_name = "add_d2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/adders/add_d2.prot --wave tests/adders/add_d2.fst --instances add_d2:Adder 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/adders/add_d2.prot --wave tests/adders/add_d2.fst --instances add_d2:Adder 2>&1" [[tests]] name = "bi.tests_adders_add_var_cyc.add_var_cyc_bi" @@ -25,7 +25,7 @@ paths = [ ] expect_dir = "../../tests/adders/expects" expect_name = "add_var_cyc.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/adders/add_var_cyc.prot --wave tests/adders/loop_with_assigns.fst --instances add_d1:Adder 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/adders/add_var_cyc.prot --wave tests/adders/loop_with_assigns.fst --instances add_d1:Adder 2>&1" [[tests]] name = "bi.tests_adders_busy_wait.busy_wait_bi" @@ -34,7 +34,7 @@ paths = [ ] expect_dir = "../../tests/adders/expects" expect_name = "busy_wait.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/adders/busy_wait.prot --wave tests/adders/busy_wait.fst --instances add_d1:Adder 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/adders/busy_wait.prot --wave tests/adders/busy_wait.fst --instances add_d1:Adder 2>&1" [[tests]] name = "bi.tests_adders_loop_with_assigns.loop_with_assigns_bi" @@ -43,7 +43,7 @@ paths = [ ] expect_dir = "../../tests/adders/expects" expect_name = "loop_with_assigns.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/adders/loop_with_assigns.prot --wave tests/adders/loop_with_assigns.fst --instances add_d1:Adder 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/adders/loop_with_assigns.prot --wave tests/adders/loop_with_assigns.fst --instances add_d1:Adder 2>&1" [[tests]] name = "bi.tests_adders_nested_busy_wait.nested_busy_wait_bi" @@ -52,7 +52,7 @@ paths = [ ] expect_dir = "../../tests/adders/expects" expect_name = "nested_busy_wait.bi.expect" -cmd = "cd ../.. && python3 -c 'import os, signal, subprocess, sys\np = subprocess.Popen(sys.argv[2:], start_new_session=True)\ntry:\n sys.exit(p.wait(timeout=float(sys.argv[1])))\nexcept subprocess.TimeoutExpired:\n os.killpg(p.pid, signal.SIGKILL)\n sys.exit(124)\n' 5 target/debug/bi --protocol tests/adders/nested_busy_wait.prot --wave tests/adders/nested_busy_wait.fst --instances add_d1:Adder 2>&1" +cmd = "cd ../.. && python3 -c 'import os, signal, subprocess, sys\np = subprocess.Popen(sys.argv[2:], start_new_session=True)\ntry:\n sys.exit(p.wait(timeout=float(sys.argv[1])))\nexcept subprocess.TimeoutExpired:\n os.killpg(p.pid, signal.SIGKILL)\n sys.exit(124)\n' 5 target/debug/bi --color never --protocol tests/adders/nested_busy_wait.prot --wave tests/adders/nested_busy_wait.fst --instances add_d1:Adder 2>&1" [[tests]] name = "bi.tests_alus_alu_d1_monitor.alu_d1_bi" @@ -61,7 +61,7 @@ paths = [ ] expect_dir = "../../tests/alus/expects" expect_name = "alu_d1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/alus/alu_d1.monitor.prot --wave tests/alus/alu_d1.fst --instances alu_d1:ALU 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/alus/alu_d1.monitor.prot --wave tests/alus/alu_d1.fst --instances alu_d1:ALU 2>&1" [[tests]] name = "bi.tests_alus_alu_d2_monitor.alu_d2_bi" @@ -70,7 +70,7 @@ paths = [ ] expect_dir = "../../tests/alus/expects" expect_name = "alu_d2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/alus/alu_d2.monitor.prot --wave tests/alus/alu_d2.fst --instances alu_d2:ALU 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/alus/alu_d2.monitor.prot --wave tests/alus/alu_d2.fst --instances alu_d2:ALU 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_classic_1_bi" @@ -79,7 +79,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/fifo_classic/expects" expect_name = "test_fifo_classic_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_classic_2_bi" @@ -88,7 +88,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/fifo_classic/expects" expect_name = "test_fifo_classic_2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_classic_3_bi" @@ -97,7 +97,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/fifo_classic/expects" expect_name = "test_fifo_classic_3.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_classic_4_bi" @@ -106,7 +106,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/fifo_classic/expects" expect_name = "test_fifo_classic_4.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_classic_5_bi" @@ -115,7 +115,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/fifo_classic/expects" expect_name = "test_fifo_classic_5.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_5.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_5.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_classic_6_bi" @@ -124,7 +124,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/fifo_classic/expects" expect_name = "test_fifo_classic_6.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_6.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_6.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_classic_7_bi" @@ -133,7 +133,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/fifo_classic/expects" expect_name = "test_fifo_classic_7.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_7.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_7.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_classic_8_bi" @@ -142,7 +142,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/fifo_classic/expects" expect_name = "test_fifo_classic_8.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_constant_1_bi" @@ -151,7 +151,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/fifo_constant/expects" expect_name = "test_fifo_constant_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_constant_2_bi" @@ -160,7 +160,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/fifo_constant/expects" expect_name = "test_fifo_constant_2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_constant_3_bi" @@ -169,7 +169,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/fifo_constant/expects" expect_name = "test_fifo_constant_3.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_constant_4_bi" @@ -178,7 +178,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/fifo_constant/expects" expect_name = "test_fifo_constant_4.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_constant_5_bi" @@ -187,7 +187,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/fifo_constant/expects" expect_name = "test_fifo_constant_5.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_5.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_5.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_constant_6_bi" @@ -196,7 +196,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/fifo_constant/expects" expect_name = "test_fifo_constant_6.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_6.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_6.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_constant_7_bi" @@ -205,7 +205,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/fifo_constant/expects" expect_name = "test_fifo_constant_7.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_7.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_7.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_constant_8_bi" @@ -214,7 +214,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/fifo_constant/expects" expect_name = "test_fifo_constant_8.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_16_0_bi" @@ -223,7 +223,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_classic/expects" expect_name = "test_sram_classic_16_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_16_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_16_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_16_12_bi" @@ -232,7 +232,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_classic/expects" expect_name = "test_sram_classic_16_12.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_16_12.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_16_12.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_16_4_bi" @@ -241,7 +241,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_classic/expects" expect_name = "test_sram_classic_16_4.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_16_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_16_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_16_8_bi" @@ -250,7 +250,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_classic/expects" expect_name = "test_sram_classic_16_8.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_16_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_16_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_1_0_bi" @@ -259,7 +259,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_classic/expects" expect_name = "test_sram_classic_1_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_1_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_1_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_1_12_bi" @@ -268,7 +268,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_classic/expects" expect_name = "test_sram_classic_1_12.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_1_12.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_1_12.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_1_4_bi" @@ -277,7 +277,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_classic/expects" expect_name = "test_sram_classic_1_4.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_1_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_1_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_1_8_bi" @@ -286,7 +286,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_classic/expects" expect_name = "test_sram_classic_1_8.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_1_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_1_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_2_0_bi" @@ -295,7 +295,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_classic/expects" expect_name = "test_sram_classic_2_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_2_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_2_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_2_12_bi" @@ -304,7 +304,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_classic/expects" expect_name = "test_sram_classic_2_12.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_2_12.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_2_12.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_2_4_bi" @@ -313,7 +313,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_classic/expects" expect_name = "test_sram_classic_2_4.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_2_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_2_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_2_8_bi" @@ -322,7 +322,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_classic/expects" expect_name = "test_sram_classic_2_8.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_2_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_2_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_4_0_bi" @@ -331,7 +331,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_classic/expects" expect_name = "test_sram_classic_4_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_4_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_4_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_4_12_bi" @@ -340,7 +340,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_classic/expects" expect_name = "test_sram_classic_4_12.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_4_12.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_4_12.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_4_4_bi" @@ -349,7 +349,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_classic/expects" expect_name = "test_sram_classic_4_4.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_4_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_4_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_4_8_bi" @@ -358,7 +358,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_classic/expects" expect_name = "test_sram_classic_4_8.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_4_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_4_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_8_0_bi" @@ -367,7 +367,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_classic/expects" expect_name = "test_sram_classic_8_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_8_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_8_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_8_12_bi" @@ -376,7 +376,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_classic/expects" expect_name = "test_sram_classic_8_12.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_8_12.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_8_12.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_8_4_bi" @@ -385,7 +385,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_classic/expects" expect_name = "test_sram_classic_8_4.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_8_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_8_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_8_8_bi" @@ -394,7 +394,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_classic/expects" expect_name = "test_sram_classic_8_8.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_8_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_8_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_0_0_bi" @@ -403,7 +403,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_16_0_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_0_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_0_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_0_1_bi" @@ -412,7 +412,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_16_0_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_0_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_0_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_0_2_bi" @@ -421,7 +421,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_16_0_2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_0_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_0_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_0_3_bi" @@ -430,7 +430,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_16_0_3.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_0_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_0_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_12_0_bi" @@ -439,7 +439,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_16_12_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_12_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_12_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_12_1_bi" @@ -448,7 +448,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_16_12_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_12_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_12_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_12_2_bi" @@ -457,7 +457,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_16_12_2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_12_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_12_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_12_3_bi" @@ -466,7 +466,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_16_12_3.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_12_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_12_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_4_0_bi" @@ -475,7 +475,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_16_4_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_4_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_4_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_4_1_bi" @@ -484,7 +484,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_16_4_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_4_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_4_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_4_2_bi" @@ -493,7 +493,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_16_4_2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_4_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_4_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_4_3_bi" @@ -502,7 +502,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_16_4_3.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_4_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_4_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_8_0_bi" @@ -511,7 +511,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_16_8_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_8_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_8_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_8_1_bi" @@ -520,7 +520,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_16_8_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_8_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_8_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_8_2_bi" @@ -529,7 +529,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_16_8_2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_8_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_8_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_8_3_bi" @@ -538,7 +538,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_16_8_3.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_8_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_8_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_0_0_bi" @@ -547,7 +547,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_1_0_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_0_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_0_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_0_1_bi" @@ -556,7 +556,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_1_0_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_0_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_0_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_0_2_bi" @@ -565,7 +565,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_1_0_2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_0_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_0_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_0_3_bi" @@ -574,7 +574,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_1_0_3.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_0_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_0_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_12_0_bi" @@ -583,7 +583,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_1_12_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_12_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_12_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_12_1_bi" @@ -592,7 +592,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_1_12_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_12_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_12_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_12_2_bi" @@ -601,7 +601,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_1_12_2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_12_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_12_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_12_3_bi" @@ -610,7 +610,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_1_12_3.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_12_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_12_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_4_0_bi" @@ -619,7 +619,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_1_4_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_4_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_4_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_4_1_bi" @@ -628,7 +628,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_1_4_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_4_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_4_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_4_2_bi" @@ -637,7 +637,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_1_4_2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_4_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_4_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_4_3_bi" @@ -646,7 +646,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_1_4_3.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_4_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_4_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_8_0_bi" @@ -655,7 +655,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_1_8_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_8_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_8_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_8_1_bi" @@ -664,7 +664,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_1_8_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_8_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_8_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_8_2_bi" @@ -673,7 +673,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_1_8_2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_8_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_8_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_8_3_bi" @@ -682,7 +682,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_1_8_3.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_8_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_8_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_0_0_bi" @@ -691,7 +691,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_2_0_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_0_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_0_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_0_1_bi" @@ -700,7 +700,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_2_0_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_0_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_0_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_0_2_bi" @@ -709,7 +709,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_2_0_2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_0_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_0_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_0_3_bi" @@ -718,7 +718,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_2_0_3.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_0_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_0_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_12_0_bi" @@ -727,7 +727,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_2_12_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_12_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_12_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_12_1_bi" @@ -736,7 +736,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_2_12_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_12_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_12_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_12_2_bi" @@ -745,7 +745,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_2_12_2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_12_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_12_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_12_3_bi" @@ -754,7 +754,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_2_12_3.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_12_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_12_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_4_0_bi" @@ -763,7 +763,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_2_4_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_4_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_4_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_4_1_bi" @@ -772,7 +772,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_2_4_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_4_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_4_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_4_2_bi" @@ -781,7 +781,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_2_4_2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_4_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_4_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_4_3_bi" @@ -790,7 +790,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_2_4_3.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_4_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_4_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_8_0_bi" @@ -799,7 +799,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_2_8_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_8_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_8_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_8_1_bi" @@ -808,7 +808,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_2_8_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_8_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_8_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_8_2_bi" @@ -817,7 +817,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_2_8_2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_8_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_8_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_8_3_bi" @@ -826,7 +826,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_2_8_3.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_8_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_8_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_0_0_bi" @@ -835,7 +835,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_4_0_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_0_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_0_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_0_1_bi" @@ -844,7 +844,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_4_0_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_0_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_0_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_0_2_bi" @@ -853,7 +853,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_4_0_2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_0_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_0_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_0_3_bi" @@ -862,7 +862,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_4_0_3.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_0_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_0_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_12_0_bi" @@ -871,7 +871,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_4_12_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_12_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_12_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_12_1_bi" @@ -880,7 +880,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_4_12_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_12_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_12_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_12_2_bi" @@ -889,7 +889,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_4_12_2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_12_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_12_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_12_3_bi" @@ -898,7 +898,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_4_12_3.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_12_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_12_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_4_0_bi" @@ -907,7 +907,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_4_4_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_4_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_4_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_4_1_bi" @@ -916,7 +916,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_4_4_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_4_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_4_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_4_2_bi" @@ -925,7 +925,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_4_4_2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_4_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_4_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_4_3_bi" @@ -934,7 +934,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_4_4_3.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_4_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_4_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_8_0_bi" @@ -943,7 +943,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_4_8_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_8_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_8_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_8_1_bi" @@ -952,7 +952,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_4_8_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_8_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_8_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_8_2_bi" @@ -961,7 +961,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_4_8_2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_8_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_8_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_8_3_bi" @@ -970,7 +970,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_4_8_3.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_8_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_8_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_0_0_bi" @@ -979,7 +979,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_8_0_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_0_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_0_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_0_1_bi" @@ -988,7 +988,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_8_0_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_0_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_0_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_0_2_bi" @@ -997,7 +997,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_8_0_2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_0_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_0_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_0_3_bi" @@ -1006,7 +1006,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_8_0_3.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_0_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_0_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_12_0_bi" @@ -1015,7 +1015,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_8_12_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_12_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_12_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_12_1_bi" @@ -1024,7 +1024,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_8_12_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_12_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_12_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_12_2_bi" @@ -1033,7 +1033,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_8_12_2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_12_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_12_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_12_3_bi" @@ -1042,7 +1042,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_8_12_3.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_12_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_12_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_4_0_bi" @@ -1051,7 +1051,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_8_4_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_4_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_4_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_4_1_bi" @@ -1060,7 +1060,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_8_4_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_4_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_4_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_4_2_bi" @@ -1069,7 +1069,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_8_4_2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_4_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_4_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_4_3_bi" @@ -1078,7 +1078,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_8_4_3.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_4_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_4_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_8_0_bi" @@ -1087,7 +1087,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_8_8_0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_8_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_8_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_8_1_bi" @@ -1096,7 +1096,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_8_8_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_8_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_8_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_8_2_bi" @@ -1105,7 +1105,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_8_8_2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_8_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_8_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_8_3_bi" @@ -1114,7 +1114,7 @@ paths = [ ] expect_dir = "../../tests/antmicro/sram_incrementing/expects" expect_name = "test_sram_incrementing_8_8_3.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_8_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_8_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_brave_new_world_francis_bit_truncation_fft.bit_truncation_fft_bi" @@ -1123,7 +1123,7 @@ paths = [ ] expect_dir = "../../tests/brave_new_world_francis/expects" expect_name = "bit_truncation_fft.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/brave_new_world_francis/bit_truncation_fft.prot --wave tests/brave_new_world_francis/bit_truncation_fft.fst --instances round11_rne_unsigned_fixed:BitTruncationFFT 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/brave_new_world_francis/bit_truncation_fft.prot --wave tests/brave_new_world_francis/bit_truncation_fft.fst --instances round11_rne_unsigned_fixed:BitTruncationFFT 2>&1" [[tests]] name = "bi.tests_brave_new_world_francis_bit_truncation_sha.bit_truncation_sha_bi" @@ -1132,7 +1132,7 @@ paths = [ ] expect_dir = "../../tests/brave_new_world_francis/expects" expect_name = "bit_truncation_sha.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/brave_new_world_francis/bit_truncation_sha.prot --wave tests/brave_new_world_francis/bit_truncation_sha.fst --instances bit_truncation_sha_fixed:bit_truncation_sha 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/brave_new_world_francis/bit_truncation_sha.prot --wave tests/brave_new_world_francis/bit_truncation_sha.fst --instances bit_truncation_sha_fixed:bit_truncation_sha 2>&1" [[tests]] name = "bi.tests_brave_new_world_francis_ftu_sha.ftu_sha_bi" @@ -1141,7 +1141,7 @@ paths = [ ] expect_dir = "../../tests/brave_new_world_francis/expects" expect_name = "ftu_sha.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/brave_new_world_francis/ftu_sha.prot --wave tests/brave_new_world_francis/ftu_sha.fst --instances fsm_update_fixed_gated:FailureToUpdateSHA 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/brave_new_world_francis/ftu_sha.prot --wave tests/brave_new_world_francis/ftu_sha.fst --instances fsm_update_fixed_gated:FailureToUpdateSHA 2>&1" [[tests]] name = "bi.tests_brave_new_world_francis_signal_async.signal_async_bi" @@ -1150,7 +1150,7 @@ paths = [ ] expect_dir = "../../tests/brave_new_world_francis/expects" expect_name = "signal_async.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/brave_new_world_francis/signal_async.prot --wave tests/brave_new_world_francis/signal_async.fst --instances signal_async_fix:SignalAsyncSpec 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/brave_new_world_francis/signal_async.prot --wave tests/brave_new_world_francis/signal_async.fst --instances signal_async_fix:SignalAsyncSpec 2>&1" [[tests]] name = "bi.tests_brave_new_world_francis_use_without_valid.use_without_valid_bi" @@ -1159,7 +1159,7 @@ paths = [ ] expect_dir = "../../tests/brave_new_world_francis/expects" expect_name = "use_without_valid.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/brave_new_world_francis/use_without_valid.prot --wave tests/brave_new_world_francis/use_without_valid.fst --instances use_without_valid_fix:UseWithoutValid 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/brave_new_world_francis/use_without_valid.prot --wave tests/brave_new_world_francis/use_without_valid.fst --instances use_without_valid_fix:UseWithoutValid 2>&1" [[tests]] name = "bi.tests_ethmac_ethmac_wishbone_manager.ethmac_wishbone_manager_bi" @@ -1168,7 +1168,7 @@ paths = [ ] expect_dir = "../../tests/ethmac/expects" expect_name = "ethmac_wishbone_manager.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/ethmac/ethmac_wishbone_manager.prot --instances tb_ethernet:WBManager --sample-posedge tb_ethernet.wb_clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/ethmac/ethmac_wishbone_manager.prot --instances tb_ethernet:WBManager --sample-posedge tb_ethernet.wb_clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_ethmac_ethmac_wishbone_subordinate.ethmac_wishbone_subordinate_bi" @@ -1177,7 +1177,7 @@ paths = [ ] expect_dir = "../../tests/ethmac/expects" expect_name = "ethmac_wishbone_subordinate.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/ethmac/ethmac_wishbone_subordinate.prot --instances tb_ethernet:WBSubordinate --sample-posedge tb_ethernet.wb_clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/ethmac/ethmac_wishbone_subordinate.prot --instances tb_ethernet:WBSubordinate --sample-posedge tb_ethernet.wb_clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_fifo_fifo_monitor.fifo_bi" @@ -1186,7 +1186,7 @@ paths = [ ] expect_dir = "../../tests/fifo/expects" expect_name = "fifo.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/fifo/fifo.monitor.prot --wave tests/fifo/fifo.fst --instances fifo_wrapper:Fifo 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fifo/fifo.monitor.prot --wave tests/fifo/fifo.fst --instances fifo_wrapper:Fifo 2>&1" [[tests]] name = "bi.tests_fifo_push_pop_identity.push_pop_identity_bi" @@ -1195,7 +1195,7 @@ paths = [ ] expect_dir = "../../tests/fifo/expects" expect_name = "push_pop_identity.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/fifo/push_pop_identity.prot --wave tests/fifo/push_pop_identity.fst --instances fifo_wrapper:Fifo 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fifo/push_pop_identity.prot --wave tests/fifo/push_pop_identity.fst --instances fifo_wrapper:Fifo 2>&1" [[tests]] name = "bi.tests_fifo_push_pop_loop_empty.push_pop_loop_empty_bi" @@ -1204,7 +1204,7 @@ paths = [ ] expect_dir = "../../tests/fifo/expects" expect_name = "push_pop_loop_empty.bi.expect" -cmd = "cd ../.. && python3 -c 'import os, signal, subprocess, sys\np = subprocess.Popen(sys.argv[2:], start_new_session=True)\ntry:\n sys.exit(p.wait(timeout=float(sys.argv[1])))\nexcept subprocess.TimeoutExpired:\n os.killpg(p.pid, signal.SIGKILL)\n sys.exit(124)\n' 5 target/debug/bi --protocol tests/fifo/push_pop_loop_empty.prot --wave tests/fifo/push_pop_loop_empty.fst --instances fifo_wrapper:Fifo 2>&1" +cmd = "cd ../.. && python3 -c 'import os, signal, subprocess, sys\np = subprocess.Popen(sys.argv[2:], start_new_session=True)\ntry:\n sys.exit(p.wait(timeout=float(sys.argv[1])))\nexcept subprocess.TimeoutExpired:\n os.killpg(p.pid, signal.SIGKILL)\n sys.exit(124)\n' 5 target/debug/bi --color never --protocol tests/fifo/push_pop_loop_empty.prot --wave tests/fifo/push_pop_loop_empty.fst --instances fifo_wrapper:Fifo 2>&1" [[tests]] name = "bi.tests_fifo_push_pop_loop_not_empty.push_pop_loop_not_empty_bi" @@ -1213,7 +1213,7 @@ paths = [ ] expect_dir = "../../tests/fifo/expects" expect_name = "push_pop_loop_not_empty.bi.expect" -cmd = "cd ../.. && python3 -c 'import os, signal, subprocess, sys\np = subprocess.Popen(sys.argv[2:], start_new_session=True)\ntry:\n sys.exit(p.wait(timeout=float(sys.argv[1])))\nexcept subprocess.TimeoutExpired:\n os.killpg(p.pid, signal.SIGKILL)\n sys.exit(124)\n' 5 target/debug/bi --protocol tests/fifo/push_pop_loop_not_empty.prot --wave tests/fifo/push_pop_loop_not_empty.fst --instances fifo_wrapper:Fifo 2>&1" +cmd = "cd ../.. && python3 -c 'import os, signal, subprocess, sys\np = subprocess.Popen(sys.argv[2:], start_new_session=True)\ntry:\n sys.exit(p.wait(timeout=float(sys.argv[1])))\nexcept subprocess.TimeoutExpired:\n os.killpg(p.pid, signal.SIGKILL)\n sys.exit(124)\n' 5 target/debug/bi --color never --protocol tests/fifo/push_pop_loop_not_empty.prot --wave tests/fifo/push_pop_loop_not_empty.fst --instances fifo_wrapper:Fifo 2>&1" [[tests]] name = "bi.tests_fpga_debugging_axi_burst_s4_s4_buggy.s4_buggy_bi" @@ -1222,7 +1222,7 @@ paths = [ ] expect_dir = "../../tests/fpga-debugging/axi-burst-s4/expects" expect_name = "s4_buggy.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axi-burst-s4/s4_buggy.prot --wave tests/fpga-debugging/axi-burst-s4/s4_buggy.vcd --instances TOP.test_l2_cache_wait_state.axi_bus:WriteSubordinate --sample-posedge TOP.test_l2_cache_wait_state.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axi-burst-s4/s4_buggy.prot --wave tests/fpga-debugging/axi-burst-s4/s4_buggy.vcd --instances TOP.test_l2_cache_wait_state.axi_bus:WriteSubordinate --sample-posedge TOP.test_l2_cache_wait_state.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_fpga_debugging_axi_burst_s4_s4_fixed.s4_fixed_bi" @@ -1231,7 +1231,7 @@ paths = [ ] expect_dir = "../../tests/fpga-debugging/axi-burst-s4/expects" expect_name = "s4_fixed.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axi-burst-s4/s4_fixed.prot --wave tests/fpga-debugging/axi-burst-s4/s4_fixed.vcd --instances TOP.test_l2_cache_wait_state.axi_bus:WriteSubordinate --sample-posedge TOP.test_l2_cache_wait_state.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axi-burst-s4/s4_fixed.prot --wave tests/fpga-debugging/axi-burst-s4/s4_fixed.vcd --instances TOP.test_l2_cache_wait_state.axi_bus:WriteSubordinate --sample-posedge TOP.test_l2_cache_wait_state.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_fpga_debugging_axi_lite_s1_s1_buggy.s1_buggy_bi" @@ -1240,7 +1240,7 @@ paths = [ ] expect_dir = "../../tests/fpga-debugging/axi-lite-s1/expects" expect_name = "s1_buggy.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axi-lite-s1/s1_buggy.prot --wave tests/fpga-debugging/axi-lite-s1/s1_buggy_workload2.vcd --instances TOP.testbench.UUT:WriteSubordinate TOP.testbench.UUT:ReadSubordinate --sample-posedge TOP.testbench.UUT.S_AXI_ACLK --show-waveform-time --time-unit ns --include-idle 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axi-lite-s1/s1_buggy.prot --wave tests/fpga-debugging/axi-lite-s1/s1_buggy_workload2.vcd --instances TOP.testbench.UUT:WriteSubordinate TOP.testbench.UUT:ReadSubordinate --sample-posedge TOP.testbench.UUT.S_AXI_ACLK --show-waveform-time --time-unit ns --include-idle 2>&1" [[tests]] name = "bi.tests_fpga_debugging_axi_lite_s1_s1_buggy_workload_1.s1_buggy_workload_1_bi" @@ -1249,7 +1249,7 @@ paths = [ ] expect_dir = "../../tests/fpga-debugging/axi-lite-s1/expects" expect_name = "s1_buggy_workload_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot --wave tests/fpga-debugging/axi-lite-s1/s1_buggy_workload1.vcd --instances TOP.testbench.UUT:WriteSubordinate TOP.testbench.UUT:ReadSubordinate --sample-posedge TOP.testbench.UUT.S_AXI_ACLK --show-waveform-time --time-unit ns --include-idle 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot --wave tests/fpga-debugging/axi-lite-s1/s1_buggy_workload1.vcd --instances TOP.testbench.UUT:WriteSubordinate TOP.testbench.UUT:ReadSubordinate --sample-posedge TOP.testbench.UUT.S_AXI_ACLK --show-waveform-time --time-unit ns --include-idle 2>&1" [[tests]] name = "bi.tests_fpga_debugging_axi_lite_s1_s1_fixed.s1_fixed_bi" @@ -1258,7 +1258,7 @@ paths = [ ] expect_dir = "../../tests/fpga-debugging/axi-lite-s1/expects" expect_name = "s1_fixed.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axi-lite-s1/s1_fixed.prot --wave tests/fpga-debugging/axi-lite-s1/s1_fixed_workload2.vcd --instances TOP.testbench.UUT:WriteSubordinate TOP.testbench.UUT:ReadSubordinate --sample-posedge TOP.testbench.UUT.S_AXI_ACLK --show-waveform-time --time-unit ns --include-idle 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axi-lite-s1/s1_fixed.prot --wave tests/fpga-debugging/axi-lite-s1/s1_fixed_workload2.vcd --instances TOP.testbench.UUT:WriteSubordinate TOP.testbench.UUT:ReadSubordinate --sample-posedge TOP.testbench.UUT.S_AXI_ACLK --show-waveform-time --time-unit ns --include-idle 2>&1" [[tests]] name = "bi.tests_fpga_debugging_axi_lite_s1_s1_fixed_workload_1.s1_fixed_workload_1_bi" @@ -1267,7 +1267,7 @@ paths = [ ] expect_dir = "../../tests/fpga-debugging/axi-lite-s1/expects" expect_name = "s1_fixed_workload_1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot --wave tests/fpga-debugging/axi-lite-s1/s1_fixed_workload1.vcd --instances TOP.testbench.UUT:WriteSubordinate TOP.testbench.UUT:ReadSubordinate --sample-posedge TOP.testbench.UUT.S_AXI_ACLK --show-waveform-time --time-unit ns --include-idle 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot --wave tests/fpga-debugging/axi-lite-s1/s1_fixed_workload1.vcd --instances TOP.testbench.UUT:WriteSubordinate TOP.testbench.UUT:ReadSubordinate --sample-posedge TOP.testbench.UUT.S_AXI_ACLK --show-waveform-time --time-unit ns --include-idle 2>&1" [[tests]] name = "bi.tests_fpga_debugging_axi_stream_s2_s2_buggy.s2_buggy_bi" @@ -1276,7 +1276,7 @@ paths = [ ] expect_dir = "../../tests/fpga-debugging/axi-stream-s2/expects" expect_name = "s2_buggy.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axi-stream-s2/s2_buggy.prot --wave tests/fpga-debugging/axi-stream-s2/s2_buggy.fst --instances TOP.testbench.UUT.axi_stream_check:AXISManager --sample-posedge TOP.testbench.UUT.axi_stream_check.i_aclk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axi-stream-s2/s2_buggy.prot --wave tests/fpga-debugging/axi-stream-s2/s2_buggy.fst --instances TOP.testbench.UUT.axi_stream_check:AXISManager --sample-posedge TOP.testbench.UUT.axi_stream_check.i_aclk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_fpga_debugging_axi_stream_s2_s2_fixed.s2_fixed_bi" @@ -1285,7 +1285,7 @@ paths = [ ] expect_dir = "../../tests/fpga-debugging/axi-stream-s2/expects" expect_name = "s2_fixed.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axi-stream-s2/s2_fixed.prot --wave tests/fpga-debugging/axi-stream-s2/s2_fixed.fst --instances TOP.testbench.UUT.axi_stream_check:AXISManager --sample-posedge TOP.testbench.UUT.axi_stream_check.i_aclk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axi-stream-s2/s2_fixed.prot --wave tests/fpga-debugging/axi-stream-s2/s2_fixed.fst --instances TOP.testbench.UUT.axi_stream_check:AXISManager --sample-posedge TOP.testbench.UUT.axi_stream_check.i_aclk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_fpga_debugging_axis_adapter_s3_s3_buggy.s3_buggy_bi" @@ -1294,7 +1294,7 @@ paths = [ ] expect_dir = "../../tests/fpga-debugging/axis-adapter-s3/expects" expect_name = "s3_buggy.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axis-adapter-s3/s3_buggy.prot --wave tests/fpga-debugging/axis-adapter-s3/s3_buggy.fst --instances TOP.test_axis_adapter_64_8.UUT:AXISManager --sample-posedge TOP.test_axis_adapter_64_8.UUT.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axis-adapter-s3/s3_buggy.prot --wave tests/fpga-debugging/axis-adapter-s3/s3_buggy.fst --instances TOP.test_axis_adapter_64_8.UUT:AXISManager --sample-posedge TOP.test_axis_adapter_64_8.UUT.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_fpga_debugging_axis_adapter_s3_s3_fixed.s3_fixed_bi" @@ -1303,7 +1303,7 @@ paths = [ ] expect_dir = "../../tests/fpga-debugging/axis-adapter-s3/expects" expect_name = "s3_fixed.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axis-adapter-s3/s3_fixed.prot --wave tests/fpga-debugging/axis-adapter-s3/s3_fixed.fst --instances TOP.test_axis_adapter_64_8.UUT:AXISManager --sample-posedge TOP.test_axis_adapter_64_8.UUT.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axis-adapter-s3/s3_fixed.prot --wave tests/fpga-debugging/axis-adapter-s3/s3_fixed.fst --instances TOP.test_axis_adapter_64_8.UUT:AXISManager --sample-posedge TOP.test_axis_adapter_64_8.UUT.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_fpga_debugging_axis_async_fifo_c4_c4_buggy.c4_buggy_bi" @@ -1312,7 +1312,7 @@ paths = [ ] expect_dir = "../../tests/fpga-debugging/axis-async-fifo-c4/expects" expect_name = "c4_buggy.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot --wave tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.fst --instances TOP.test_axis_async_fifo.UUT.axis_reg_inst:Sender TOP.test_axis_async_fifo.UUT.axis_reg_inst:Receiver --sample-posedge TOP.test_axis_async_fifo.UUT.axis_reg_inst.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot --wave tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.fst --instances TOP.test_axis_async_fifo.UUT.axis_reg_inst:Sender TOP.test_axis_async_fifo.UUT.axis_reg_inst:Receiver --sample-posedge TOP.test_axis_async_fifo.UUT.axis_reg_inst.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_fpga_debugging_axis_async_fifo_c4_c4_fixed.c4_fixed_bi" @@ -1321,7 +1321,7 @@ paths = [ ] expect_dir = "../../tests/fpga-debugging/axis-async-fifo-c4/expects" expect_name = "c4_fixed.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.prot --wave tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.fst --instances TOP.test_axis_async_fifo.UUT.axis_reg_inst:Sender TOP.test_axis_async_fifo.UUT.axis_reg_inst:Receiver --sample-posedge TOP.test_axis_async_fifo.UUT.axis_reg_inst.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.prot --wave tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.fst --instances TOP.test_axis_async_fifo.UUT.axis_reg_inst:Sender TOP.test_axis_async_fifo.UUT.axis_reg_inst:Receiver --sample-posedge TOP.test_axis_async_fifo.UUT.axis_reg_inst.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_fpga_debugging_axis_fifo_d11_d11_buggy.d11_buggy_bi" @@ -1330,7 +1330,7 @@ paths = [ ] expect_dir = "../../tests/fpga-debugging/axis-fifo-d11/expects" expect_name = "d11_buggy.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axis-fifo-d11/d11_buggy.prot --wave tests/fpga-debugging/axis-fifo-d11/d11_buggy.fst --instances TOP.test_axis_fifo:AxisFifo --sample-posedge TOP.test_axis_fifo.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axis-fifo-d11/d11_buggy.prot --wave tests/fpga-debugging/axis-fifo-d11/d11_buggy.fst --instances TOP.test_axis_fifo:AxisFifo --sample-posedge TOP.test_axis_fifo.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_fpga_debugging_axis_fifo_d11_d11_fixed.d11_fixed_bi" @@ -1339,7 +1339,7 @@ paths = [ ] expect_dir = "../../tests/fpga-debugging/axis-fifo-d11/expects" expect_name = "d11_fixed.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axis-fifo-d11/d11_fixed.prot --wave tests/fpga-debugging/axis-fifo-d11/d11_fixed.fst --instances TOP.test_axis_fifo:AxisFifo --sample-posedge TOP.test_axis_fifo.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axis-fifo-d11/d11_fixed.prot --wave tests/fpga-debugging/axis-fifo-d11/d11_fixed.fst --instances TOP.test_axis_fifo:AxisFifo --sample-posedge TOP.test_axis_fifo.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_fpga_debugging_axis_fifo_d12_d12_buggy.d12_buggy_bi" @@ -1348,7 +1348,7 @@ paths = [ ] expect_dir = "../../tests/fpga-debugging/axis-fifo-d12/expects" expect_name = "d12_buggy.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axis-fifo-d12/d12_buggy.prot --wave tests/fpga-debugging/axis-fifo-d12/d12_buggy.fst --instances TOP.test_axis_fifo:AxisFifo --sample-posedge TOP.test_axis_fifo.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axis-fifo-d12/d12_buggy.prot --wave tests/fpga-debugging/axis-fifo-d12/d12_buggy.fst --instances TOP.test_axis_fifo:AxisFifo --sample-posedge TOP.test_axis_fifo.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_fpga_debugging_axis_fifo_d12_d12_fixed.d12_fixed_bi" @@ -1357,7 +1357,7 @@ paths = [ ] expect_dir = "../../tests/fpga-debugging/axis-fifo-d12/expects" expect_name = "d12_fixed.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axis-fifo-d12/d12_fixed.prot --wave tests/fpga-debugging/axis-fifo-d12/d12_fixed.fst --instances TOP.test_axis_fifo:AxisFifo --sample-posedge TOP.test_axis_fifo.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axis-fifo-d12/d12_fixed.prot --wave tests/fpga-debugging/axis-fifo-d12/d12_fixed.fst --instances TOP.test_axis_fifo:AxisFifo --sample-posedge TOP.test_axis_fifo.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_fpga_debugging_axis_fifo_d4_d4_buggy.d4_buggy_bi" @@ -1366,7 +1366,7 @@ paths = [ ] expect_dir = "../../tests/fpga-debugging/axis-fifo-d4/expects" expect_name = "d4_buggy.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axis-fifo-d4/d4_buggy.prot --wave tests/fpga-debugging/axis-fifo-d4/d4_buggy.fst --instances TOP.axis_fifo_wrapper.axis_fifo_inst:AxisFifo --sample-posedge TOP.axis_fifo_wrapper.axis_fifo_inst.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axis-fifo-d4/d4_buggy.prot --wave tests/fpga-debugging/axis-fifo-d4/d4_buggy.fst --instances TOP.axis_fifo_wrapper.axis_fifo_inst:AxisFifo --sample-posedge TOP.axis_fifo_wrapper.axis_fifo_inst.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_fpga_debugging_axis_fifo_d4_d4_fixed.d4_fixed_bi" @@ -1375,7 +1375,7 @@ paths = [ ] expect_dir = "../../tests/fpga-debugging/axis-fifo-d4/expects" expect_name = "d4_fixed.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/fpga-debugging/axis-fifo-d4/d4_fixed.prot --wave tests/fpga-debugging/axis-fifo-d4/d4_fixed.fst --instances TOP.axis_fifo_wrapper.axis_fifo_inst:AxisFifo --sample-posedge TOP.axis_fifo_wrapper.axis_fifo_inst.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axis-fifo-d4/d4_fixed.prot --wave tests/fpga-debugging/axis-fifo-d4/d4_fixed.fst --instances TOP.axis_fifo_wrapper.axis_fifo_inst:AxisFifo --sample-posedge TOP.axis_fifo_wrapper.axis_fifo_inst.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_identities_identity_d1.identity_d1_bi" @@ -1384,7 +1384,7 @@ paths = [ ] expect_dir = "../../tests/identities/expects" expect_name = "identity_d1.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/identities/identity_d1.prot --wave tests/identities/identity_d1.fst --instances identity_d1:Identity 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/identities/identity_d1.prot --wave tests/identities/identity_d1.fst --instances identity_d1:Identity 2>&1" [[tests]] name = "bi.tests_multi_multi0.multi0_bi" @@ -1393,7 +1393,7 @@ paths = [ ] expect_dir = "../../tests/multi/expects" expect_name = "multi0.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/multi/multi0.prot --wave tests/multi/multi0.fst --instances multi0:multi0 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/multi/multi0.prot --wave tests/multi/multi0.fst --instances multi0:multi0 2>&1" [[tests]] name = "bi.tests_multi_multi0keep.multi0keep_bi" @@ -1402,7 +1402,7 @@ paths = [ ] expect_dir = "../../tests/multi/expects" expect_name = "multi0keep.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/multi/multi0keep.prot --wave tests/multi/multi0keep.fst --instances multi0keep:multi0keep 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/multi/multi0keep.prot --wave tests/multi/multi0keep.fst --instances multi0keep:multi0keep 2>&1" [[tests]] name = "bi.tests_multi_multi0keep2const.multi0keep2const_bi" @@ -1411,7 +1411,7 @@ paths = [ ] expect_dir = "../../tests/multi/expects" expect_name = "multi0keep2const.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/multi/multi0keep2const.prot --wave tests/multi/multi0keep2const.fst --instances multi0keep2const:multi0keep2const 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/multi/multi0keep2const.prot --wave tests/multi/multi0keep2const.fst --instances multi0keep2const:multi0keep2const 2>&1" [[tests]] name = "bi.tests_multi_multi2const.multi2const_bi" @@ -1420,7 +1420,7 @@ paths = [ ] expect_dir = "../../tests/multi/expects" expect_name = "multi2const.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/multi/multi2const.prot --wave tests/multi/multi2const.fst --instances multi2const:multi2const 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/multi/multi2const.prot --wave tests/multi/multi2const.fst --instances multi2const:multi2const 2>&1" [[tests]] name = "bi.tests_multi_multi2multi.multi2multi_bi" @@ -1429,7 +1429,7 @@ paths = [ ] expect_dir = "../../tests/multi/expects" expect_name = "multi2multi.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/multi/multi2multi.prot --wave tests/multi/multi2multi.fst --instances multi2multi:multi2multi 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/multi/multi2multi.prot --wave tests/multi/multi2multi.fst --instances multi2multi:multi2multi 2>&1" [[tests]] name = "bi.tests_multi_multi_data.multi_data_bi" @@ -1438,7 +1438,7 @@ paths = [ ] expect_dir = "../../tests/multi/expects" expect_name = "multi_data.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/multi/multi_data.prot --wave tests/multi/multi_data.fst --instances multi_data:multi_data 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/multi/multi_data.prot --wave tests/multi/multi_data.fst --instances multi_data:multi_data 2>&1" [[tests]] name = "bi.tests_multipliers_mult_d2.mult_d2_bi" @@ -1447,7 +1447,7 @@ paths = [ ] expect_dir = "../../tests/multipliers/expects" expect_name = "mult_d2.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/multipliers/mult_d2.prot --wave tests/multipliers/mult_d2.fst --instances mult_d2:Multiplier 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/multipliers/mult_d2.prot --wave tests/multipliers/mult_d2.fst --instances mult_d2:Multiplier 2>&1" [[tests]] name = "bi.tests_picorv32_pcpi_mul_unsigned_mul.pcpi_mul_unsigned_mul_bi" @@ -1456,7 +1456,7 @@ paths = [ ] expect_dir = "../../tests/picorv32/expects" expect_name = "pcpi_mul_unsigned_mul.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/picorv32/pcpi_mul_unsigned_mul.prot --wave tests/picorv32/unsigned_mul.fst --instances picorv32_pcpi_mul:picorv32_pcpi_mul 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/picorv32/pcpi_mul_unsigned_mul.prot --wave tests/picorv32/unsigned_mul.fst --instances picorv32_pcpi_mul:picorv32_pcpi_mul 2>&1" [[tests]] name = "bi.tests_serv_serv_regfile.serv_regfile_bi" @@ -1465,7 +1465,7 @@ paths = [ ] expect_dir = "../../tests/serv/expects" expect_name = "serv_regfile.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/serv/serv_regfile.prot --wave tests/serv/serv_regfile.fst --instances serv_regfile:Regfile --display-hex 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/serv/serv_regfile.prot --wave tests/serv/serv_regfile.fst --instances serv_regfile:Regfile --display-hex 2>&1" [[tests]] name = "bi.tests_tinyaes128_aes128.aes128_bi" @@ -1474,7 +1474,7 @@ paths = [ ] expect_dir = "../../tests/tinyaes128/expects" expect_name = "aes128.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/tinyaes128/aes128.prot --wave tests/tinyaes128/aes128.fst --instances aes_128:TinyAES128 --display-hex 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/tinyaes128/aes128.prot --wave tests/tinyaes128/aes128.fst --instances aes_128:TinyAES128 --display-hex 2>&1" [[tests]] name = "bi.tests_wal_advanced_axis.axis_bi" @@ -1483,7 +1483,7 @@ paths = [ ] expect_dir = "../../tests/wal/advanced/expects" expect_name = "axis.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/wal/advanced/axis.prot --wave tests/wal/advanced/uart-axi.fst --instances uut_rx:AXIS --sample-posedge uut_rx.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/wal/advanced/axis.prot --wave tests/wal/advanced/uart-axi.fst --instances uut_rx:AXIS --sample-posedge uut_rx.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_wal_advanced_axis_failing.axis_failing_bi" @@ -1492,7 +1492,7 @@ paths = [ ] expect_dir = "../../tests/wal/advanced/expects" expect_name = "axis_failing.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/wal/advanced/axis_failing.prot --wave tests/wal/advanced/uart-axi-minimal.fst --instances uut_rx:AXIS --sample-posedge uut_rx.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/wal/advanced/axis_failing.prot --wave tests/wal/advanced/uart-axi-minimal.fst --instances uut_rx:AXIS --sample-posedge uut_rx.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_wal_advanced_axis_minimal.axis_minimal_bi" @@ -1501,7 +1501,7 @@ paths = [ ] expect_dir = "../../tests/wal/advanced/expects" expect_name = "axis_minimal.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/wal/advanced/axis_minimal.prot --wave tests/wal/advanced/uart-axi-minimal.fst --instances uut_rx:AXIS --sample-posedge uut_rx.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/wal/advanced/axis_minimal.prot --wave tests/wal/advanced/uart-axi-minimal.fst --instances uut_rx:AXIS --sample-posedge uut_rx.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_wal_advanced_axis_truncated.axis_truncated_bi" @@ -1510,7 +1510,7 @@ paths = [ ] expect_dir = "../../tests/wal/advanced/expects" expect_name = "axis_truncated.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/wal/advanced/axis_truncated.prot --wave tests/wal/advanced/uart-axi-truncated.fst --instances uut_rx:AXIS --sample-posedge uut_rx.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/wal/advanced/axis_truncated.prot --wave tests/wal/advanced/uart-axi-truncated.fst --instances uut_rx:AXIS --sample-posedge uut_rx.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] name = "bi.tests_wal_advanced_axis_truncated_include_idle.axis_truncated_include_idle_bi" @@ -1519,7 +1519,7 @@ paths = [ ] expect_dir = "../../tests/wal/advanced/expects" expect_name = "axis_truncated_include_idle.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/wal/advanced/axis_truncated_include_idle.prot --wave tests/wal/advanced/uart-axi-truncated.fst --instances uut_rx:AXIS --sample-posedge uut_rx.clk --show-waveform-time --time-unit ns --include-idle 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/wal/advanced/axis_truncated_include_idle.prot --wave tests/wal/advanced/uart-axi-truncated.fst --instances uut_rx:AXIS --sample-posedge uut_rx.clk --show-waveform-time --time-unit ns --include-idle 2>&1" [[tests]] name = "bi.tests_wb_intercon_wb_arb.wb_arb_bi" @@ -1528,7 +1528,7 @@ paths = [ ] expect_dir = "../../tests/wb_intercon/expects" expect_name = "wb_arb.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/wb_intercon/wb_arb.prot --instances wb_intercon_tb.wb_arb_tb:WBSubordinate --sample-posedge wb_intercon_tb.wb_arb_tb.wb_clk --show-waveform-time --time-unit s 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/wb_intercon/wb_arb.prot --instances wb_intercon_tb.wb_arb_tb:WBSubordinate --sample-posedge wb_intercon_tb.wb_arb_tb.wb_clk --show-waveform-time --time-unit s 2>&1" [[tests]] name = "bi.tests_wb_intercon_wb_cdc.wb_cdc_bi" @@ -1537,7 +1537,7 @@ paths = [ ] expect_dir = "../../tests/wb_intercon/expects" expect_name = "wb_cdc.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/wb_intercon/wb_cdc.prot --wave tests/wb_intercon/wb_cdc.fst --instances wb_intercon_tb.wb_cdc_tb.dut:WBSubordinate --sample-posedge wb_intercon_tb.wb_cdc_tb.dut.wbm_clk --show-waveform-time --time-unit s 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/wb_intercon/wb_cdc.prot --wave tests/wb_intercon/wb_cdc.fst --instances wb_intercon_tb.wb_cdc_tb.dut:WBSubordinate --sample-posedge wb_intercon_tb.wb_cdc_tb.dut.wbm_clk --show-waveform-time --time-unit s 2>&1" [[tests]] name = "bi.tests_wishbone_wishbone_monitor.wishbone_bi" @@ -1546,4 +1546,4 @@ paths = [ ] expect_dir = "../../tests/wishbone/expects" expect_name = "wishbone.bi.expect" -cmd = "cd ../.. && target/debug/bi --protocol tests/wishbone/wishbone.monitor.prot --wave tests/wishbone/reqwalker.vcd --instances TOP.reqwalker:WBSubordinate --sample-posedge TOP.reqwalker.i_clk 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/wishbone/wishbone.monitor.prot --wave tests/wishbone/reqwalker.vcd --instances TOP.reqwalker:WBSubordinate --sample-posedge TOP.reqwalker.i_clk 2>&1" From cf631025834e4476320f16a61d604862d18c6819 Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sat, 11 Jul 2026 15:26:28 -0400 Subject: [PATCH 12/55] Update .expect files --- tests/adders/expects/busy_wait.bi.expect | 2 +- .../expects/loop_with_assigns.bi.expect | 2 +- .../adders/expects/nested_busy_wait.bi.expect | 2 +- .../expects/ethmac_wishbone_manager.bi.expect | 2 +- .../ethmac_wishbone_subordinate.bi.expect | 2 +- .../expects/push_pop_loop_empty.bi.expect | 2 +- .../expects/push_pop_loop_not_empty.bi.expect | 2 +- .../axi-burst-s4/expects/s4_buggy.bi.expect | 10 +++---- .../axi-lite-s1/expects/s1_buggy.bi.expect | 20 ++++++------- .../expects/s1_buggy_workload_1.bi.expect | 20 ++++++------- .../expects/s1_fixed_workload_1.bi.expect | 20 ++++++------- .../expects/c4_buggy.bi.expect | 30 +++++++++---------- .../axis-fifo-d4/expects/d4_fixed.bi.expect | 10 +++---- .../identities/expects/identity_d1.bi.expect | 2 +- tests/serv/expects/serv_regfile.bi.expect | 2 +- tests/wal/advanced/expects/axis.bi.expect | 10 +++---- .../advanced/expects/axis_failing.bi.expect | 10 +++---- .../advanced/expects/axis_minimal.bi.expect | 10 +++---- .../advanced/expects/axis_truncated.bi.expect | 10 +++---- .../axis_truncated_include_idle.bi.expect | 10 +++---- tests/wb_intercon/expects/wb_arb.bi.expect | 2 +- tests/wb_intercon/expects/wb_cdc.bi.expect | 2 +- 22 files changed, 91 insertions(+), 91 deletions(-) diff --git a/tests/adders/expects/busy_wait.bi.expect b/tests/adders/expects/busy_wait.bi.expect index 89c0b63f..5ed3292e 100644 --- a/tests/adders/expects/busy_wait.bi.expect +++ b/tests/adders/expects/busy_wait.bi.expect @@ -1,5 +1,5 @@ -thread 'main' (11279289) panicked at bi/src/bi.rs:628:21: +thread 'main' (11301631) panicked at bi/src/bi.rs:628:21: [add_busy_wait@00!] Cannot fork at step zero! note: run with `RUST_BACKTRACE=1` environment variable to display a backtrace ---CODE--- diff --git a/tests/adders/expects/loop_with_assigns.bi.expect b/tests/adders/expects/loop_with_assigns.bi.expect index 9731c459..d3c5196e 100644 --- a/tests/adders/expects/loop_with_assigns.bi.expect +++ b/tests/adders/expects/loop_with_assigns.bi.expect @@ -1,5 +1,5 @@ -thread 'main' (11279247) panicked at bi/src/bi.rs:628:21: +thread 'main' (11301764) panicked at bi/src/bi.rs:628:21: [loop_add@00!] Cannot fork at step zero! note: run with `RUST_BACKTRACE=1` environment variable to display a backtrace ---CODE--- diff --git a/tests/adders/expects/nested_busy_wait.bi.expect b/tests/adders/expects/nested_busy_wait.bi.expect index 9e40a38e..386c2750 100644 --- a/tests/adders/expects/nested_busy_wait.bi.expect +++ b/tests/adders/expects/nested_busy_wait.bi.expect @@ -1,5 +1,5 @@ -thread 'main' (11280027) panicked at bi/src/bi.rs:628:21: +thread 'main' (11301712) panicked at bi/src/bi.rs:628:21: [nested_busy_wait@00!] Cannot fork at step zero! note: run with `RUST_BACKTRACE=1` environment variable to display a backtrace ---CODE--- diff --git a/tests/ethmac/expects/ethmac_wishbone_manager.bi.expect b/tests/ethmac/expects/ethmac_wishbone_manager.bi.expect index 7a3afdf3..102c1bf9 100644 --- a/tests/ethmac/expects/ethmac_wishbone_manager.bi.expect +++ b/tests/ethmac/expects/ethmac_wishbone_manager.bi.expect @@ -1,7 +1,7 @@ error: the following required arguments were not provided: --wave -Usage: bi --protocol --wave --show-waveform-time --instances ... --sample-posedge --time-unit +Usage: bi --wave --show-waveform-time --color --protocol --instances ... --sample-posedge --time-unit For more information, try '--help'. ---CODE--- diff --git a/tests/ethmac/expects/ethmac_wishbone_subordinate.bi.expect b/tests/ethmac/expects/ethmac_wishbone_subordinate.bi.expect index 7a3afdf3..102c1bf9 100644 --- a/tests/ethmac/expects/ethmac_wishbone_subordinate.bi.expect +++ b/tests/ethmac/expects/ethmac_wishbone_subordinate.bi.expect @@ -1,7 +1,7 @@ error: the following required arguments were not provided: --wave -Usage: bi --protocol --wave --show-waveform-time --instances ... --sample-posedge --time-unit +Usage: bi --wave --show-waveform-time --color --protocol --instances ... --sample-posedge --time-unit For more information, try '--help'. ---CODE--- diff --git a/tests/fifo/expects/push_pop_loop_empty.bi.expect b/tests/fifo/expects/push_pop_loop_empty.bi.expect index d7e93258..629d3ff7 100644 --- a/tests/fifo/expects/push_pop_loop_empty.bi.expect +++ b/tests/fifo/expects/push_pop_loop_empty.bi.expect @@ -1,5 +1,5 @@ -thread 'main' (11280531) panicked at bi/src/bi.rs:628:21: +thread 'main' (11302832) panicked at bi/src/bi.rs:628:21: [pop_n_times@00!] Cannot fork at step zero! note: run with `RUST_BACKTRACE=1` environment variable to display a backtrace ---CODE--- diff --git a/tests/fifo/expects/push_pop_loop_not_empty.bi.expect b/tests/fifo/expects/push_pop_loop_not_empty.bi.expect index d4b3f3d1..303e34cf 100644 --- a/tests/fifo/expects/push_pop_loop_not_empty.bi.expect +++ b/tests/fifo/expects/push_pop_loop_not_empty.bi.expect @@ -1,5 +1,5 @@ -thread 'main' (11280497) panicked at bi/src/bi.rs:628:21: +thread 'main' (11302773) panicked at bi/src/bi.rs:628:21: [pop_n_times@00!] Cannot fork at step zero! note: run with `RUST_BACKTRACE=1` environment variable to display a backtrace ---CODE--- diff --git a/tests/fpga-debugging/axi-burst-s4/expects/s4_buggy.bi.expect b/tests/fpga-debugging/axi-burst-s4/expects/s4_buggy.bi.expect index a587ff56..b3c96b02 100644 --- a/tests/fpga-debugging/axi-burst-s4/expects/s4_buggy.bi.expect +++ b/tests/fpga-debugging/axi-burst-s4/expects/s4_buggy.bi.expect @@ -1,11 +1,11 @@ // trace 0 trace { } -error: [write_burst@95] executing step 67 of the transaction: 0 != 1 - ┌─ tests/fpga-debugging/axi-burst-s4/s4_buggy.prot:63:5 - │ -63 │ DUT.m_wlast := 1'b1; - │ ^^^^^^^^^^^^^^^^^^^^ [write_burst@95] executing step 67 of the transaction: 0 != 1 +error: [write_burst@95] executing step 67 of the transaction: 0 != 1 + ┌─ tests/fpga-debugging/axi-burst-s4/s4_buggy.prot:63:5 + │ +63 │ DUT.m_wlast := 1'b1; + │ ^^^^^^^^^^^^^^^^^^^^ [write_burst@95] executing step 67 of the transaction: 0 != 1 Error: "Monitor failed" ---CODE--- diff --git a/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy.bi.expect b/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy.bi.expect index fe49b2c9..523bbb01 100644 --- a/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy.bi.expect +++ b/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy.bi.expect @@ -7,22 +7,22 @@ trace { trace { idle(); // [time: 0ns -> 25ns] } -error: [read_v2@11?1!] executing step 3 of the transaction: 1 != 0 - ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy.prot:169:5 - │ -169 │ assert_eq(DUT.S_AXI_ARREADY, 1'b0); - │ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@11?1!] executing step 3 of the transaction: 1 != 0 +error: [read_v2@11?1!] executing step 3 of the transaction: 1 != 0 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy.prot:169:5 + │ +169 │ assert_eq(DUT.S_AXI_ARREADY, 1'b0); + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@11?1!] executing step 3 of the transaction: 1 != 0 // trace 1 trace { idle(); // [time: 0ns -> 25ns] } -error: [read_v2@11?2?] executing step 3 of the transaction: 1 != 0 - ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy.prot:163:9 - │ -163 │ DUT.S_AXI_RREADY := 1'b0; - │ ^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@11?2?] executing step 3 of the transaction: 1 != 0 +error: [read_v2@11?2?] executing step 3 of the transaction: 1 != 0 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy.prot:163:9 + │ +163 │ DUT.S_AXI_RREADY := 1'b0; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@11?2?] executing step 3 of the transaction: 1 != 0 Error: "Monitor failed" ---CODE--- diff --git a/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy_workload_1.bi.expect b/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy_workload_1.bi.expect index b5e51f71..58ee712c 100644 --- a/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy_workload_1.bi.expect +++ b/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy_workload_1.bi.expect @@ -15,11 +15,11 @@ trace { idle(); // [time: 0ns -> 25ns] read_v1(64, 0); // [time: 25ns -> 100ns] } -error: [read_v2@4] executing step 0 of the transaction: 0 != 1 - ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot:161:5 - │ -161 │ DUT.S_AXI_ARVALID := 1'b1; - │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@4] executing step 0 of the transaction: 0 != 1 +error: [read_v2@4] executing step 0 of the transaction: 0 != 1 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot:161:5 + │ +161 │ DUT.S_AXI_ARVALID := 1'b1; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@4] executing step 0 of the transaction: 0 != 1 // trace 1 @@ -33,11 +33,11 @@ trace { idle(); // [time: 0ns -> 25ns] read_v1(64, 0); // [time: 25ns -> 100ns] } -error: [idle@4] executing step 0 of the transaction: 1 != 0 - ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot:108:5 - │ -108 │ DUT.S_AXI_RREADY := 1'b0; - │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [idle@4] executing step 0 of the transaction: 1 != 0 +error: [idle@4] executing step 0 of the transaction: 1 != 0 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot:108:5 + │ +108 │ DUT.S_AXI_RREADY := 1'b0; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [idle@4] executing step 0 of the transaction: 1 != 0 // trace 3 diff --git a/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed_workload_1.bi.expect b/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed_workload_1.bi.expect index 5c9957cb..5d803553 100644 --- a/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed_workload_1.bi.expect +++ b/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed_workload_1.bi.expect @@ -7,11 +7,11 @@ trace { idle(); // [time: 0ns -> 25ns] read_v1(64, 0); // [time: 25ns -> 100ns] } -error: [read_v2@4] executing step 0 of the transaction: 0 != 1 - ┌─ tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot:161:5 - │ -161 │ DUT.S_AXI_ARVALID := 1'b1; - │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@4] executing step 0 of the transaction: 0 != 1 +error: [read_v2@4] executing step 0 of the transaction: 0 != 1 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot:161:5 + │ +161 │ DUT.S_AXI_ARVALID := 1'b1; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@4] executing step 0 of the transaction: 0 != 1 // trace 1 @@ -25,11 +25,11 @@ trace { idle(); // [time: 0ns -> 25ns] read_v1(64, 0); // [time: 25ns -> 100ns] } -error: [idle@4] executing step 0 of the transaction: 1 != 0 - ┌─ tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot:108:5 - │ -108 │ DUT.S_AXI_RREADY := 1'b0; - │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [idle@4] executing step 0 of the transaction: 1 != 0 +error: [idle@4] executing step 0 of the transaction: 1 != 0 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot:108:5 + │ +108 │ DUT.S_AXI_RREADY := 1'b0; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [idle@4] executing step 0 of the transaction: 1 != 0 // trace 3 diff --git a/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.bi.expect b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.bi.expect index 2b823d8c..3e619433 100644 --- a/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.bi.expect +++ b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.bi.expect @@ -14,33 +14,33 @@ trace { trace { reset(); // [time: 0ns -> 25ns] } -error: [reset@1] executing step 0 of the transaction: 0 != 1 - ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot:115:5 - │ -115 │ DUT.rst := 1'b1; - │ ^^^^^^^^^^^^^^^^ [reset@1] executing step 0 of the transaction: 0 != 1 +error: [reset@1] executing step 0 of the transaction: 0 != 1 + ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot:115:5 + │ +115 │ DUT.rst := 1'b1; + │ ^^^^^^^^^^^^^^^^ [reset@1] executing step 0 of the transaction: 0 != 1 // trace 1 trace { reset(); // [time: 0ns -> 25ns] } -error: [idle@1] executing step 0 of the transaction: 1 != 0 - ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot:97:5 - │ -97 │ DUT.m_axis_tready := 1'b0; - │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [idle@1] executing step 0 of the transaction: 1 != 0 +error: [idle@1] executing step 0 of the transaction: 1 != 0 + ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot:97:5 + │ +97 │ DUT.m_axis_tready := 1'b0; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [idle@1] executing step 0 of the transaction: 1 != 0 // trace 2 trace { reset(); // [time: 0ns -> 25ns] } -error: [pop@1] executing step 0 of the transaction: 0 != 1 - ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot:62:5 - │ -62 │ assert_eq(DUT.m_axis_tvalid, 1'b1); - │ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ [pop@1] executing step 0 of the transaction: 0 != 1 +error: [pop@1] executing step 0 of the transaction: 0 != 1 + ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot:62:5 + │ +62 │ assert_eq(DUT.m_axis_tvalid, 1'b1); + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ [pop@1] executing step 0 of the transaction: 0 != 1 Error: "Monitor failed" ---CODE--- diff --git a/tests/fpga-debugging/axis-fifo-d4/expects/d4_fixed.bi.expect b/tests/fpga-debugging/axis-fifo-d4/expects/d4_fixed.bi.expect index c1126f66..f831c600 100644 --- a/tests/fpga-debugging/axis-fifo-d4/expects/d4_fixed.bi.expect +++ b/tests/fpga-debugging/axis-fifo-d4/expects/d4_fixed.bi.expect @@ -44,11 +44,11 @@ trace { push(9); // [time: 140ns -> 142.5ns] push(233); // [time: 142.5ns -> 145ns] } -error: [push@63] executing step 1 of the transaction: 01 != 00 - ┌─ tests/fpga-debugging/axis-fifo-d4/d4_fixed.prot:89:5 - │ -89 │ DUT.s_axis_tdata := data; - │ ^^^^^^^^^^^^^^^^^^^^^^^^^ [push@63] executing step 1 of the transaction: 01 != 00 +error: [push@63] executing step 1 of the transaction: 01 != 00 + ┌─ tests/fpga-debugging/axis-fifo-d4/d4_fixed.prot:89:5 + │ +89 │ DUT.s_axis_tdata := data; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^ [push@63] executing step 1 of the transaction: 01 != 00 Error: "Monitor failed" ---CODE--- diff --git a/tests/identities/expects/identity_d1.bi.expect b/tests/identities/expects/identity_d1.bi.expect index 23ce9225..87a6f650 100644 --- a/tests/identities/expects/identity_d1.bi.expect +++ b/tests/identities/expects/identity_d1.bi.expect @@ -1,5 +1,5 @@ -thread 'main' (11280585) panicked at bi/src/bi.rs:739:29: +thread 'main' (11302885) panicked at bi/src/bi.rs:739:29: not yet implemented: we currently expect one side of an assert_eq to be a port! note: run with `RUST_BACKTRACE=1` environment variable to display a backtrace ---CODE--- diff --git a/tests/serv/expects/serv_regfile.bi.expect b/tests/serv/expects/serv_regfile.bi.expect index 605f9cb1..b7cd8904 100644 --- a/tests/serv/expects/serv_regfile.bi.expect +++ b/tests/serv/expects/serv_regfile.bi.expect @@ -1,5 +1,5 @@ -thread 'main' (11280470) panicked at bi/src/constraints.rs:120:9: +thread 'main' (11303043) panicked at bi/src/constraints.rs:120:9: assertion `left == right` failed left: 32 right: 1 diff --git a/tests/wal/advanced/expects/axis.bi.expect b/tests/wal/advanced/expects/axis.bi.expect index e23f591a..4a0b2a39 100644 --- a/tests/wal/advanced/expects/axis.bi.expect +++ b/tests/wal/advanced/expects/axis.bi.expect @@ -5,11 +5,11 @@ trace { send_data(2); // [time: 2212ns -> 2220ns] send_data(3); // [time: 2916ns -> 2924ns] } -error: [send_data@453] executing step 88 of the transaction: 05 != 04 - ┌─ tests/wal/advanced/axis.prot:10:5 - │ -10 │ D.m_axis_tdata := data; - │ ^^^^^^^^^^^^^^^^^^^^^^^ [send_data@453] executing step 88 of the transaction: 05 != 04 +error: [send_data@453] executing step 88 of the transaction: 05 != 04 + ┌─ tests/wal/advanced/axis.prot:10:5 + │ +10 │ D.m_axis_tdata := data; + │ ^^^^^^^^^^^^^^^^^^^^^^^ [send_data@453] executing step 88 of the transaction: 05 != 04 Error: "Monitor failed" ---CODE--- diff --git a/tests/wal/advanced/expects/axis_failing.bi.expect b/tests/wal/advanced/expects/axis_failing.bi.expect index 1f448f01..313a163a 100644 --- a/tests/wal/advanced/expects/axis_failing.bi.expect +++ b/tests/wal/advanced/expects/axis_failing.bi.expect @@ -1,11 +1,11 @@ // trace 0 trace { } -error: [idle@0] executing step 0 of the transaction: 1 != 0 - ┌─ tests/wal/advanced/axis_failing.prot:11:5 - │ -11 │ D.m_axis_tvalid := 1'b0; - │ ^^^^^^^^^^^^^^^^^^^^^^^^ [idle@0] executing step 0 of the transaction: 1 != 0 +error: [idle@0] executing step 0 of the transaction: 1 != 0 + ┌─ tests/wal/advanced/axis_failing.prot:11:5 + │ +11 │ D.m_axis_tvalid := 1'b0; + │ ^^^^^^^^^^^^^^^^^^^^^^^^ [idle@0] executing step 0 of the transaction: 1 != 0 Error: "Monitor failed" ---CODE--- diff --git a/tests/wal/advanced/expects/axis_minimal.bi.expect b/tests/wal/advanced/expects/axis_minimal.bi.expect index e8a5c963..8570d0a2 100644 --- a/tests/wal/advanced/expects/axis_minimal.bi.expect +++ b/tests/wal/advanced/expects/axis_minimal.bi.expect @@ -1,11 +1,11 @@ // trace 0 trace { } -error: [send_data@0] executing step 3 of the transaction: 0f != 14 - ┌─ tests/wal/advanced/axis_minimal.prot:10:5 - │ -10 │ D.m_axis_tdata := data; - │ ^^^^^^^^^^^^^^^^^^^^^^^ [send_data@0] executing step 3 of the transaction: 0f != 14 +error: [send_data@0] executing step 3 of the transaction: 0f != 14 + ┌─ tests/wal/advanced/axis_minimal.prot:10:5 + │ +10 │ D.m_axis_tdata := data; + │ ^^^^^^^^^^^^^^^^^^^^^^^ [send_data@0] executing step 3 of the transaction: 0f != 14 Error: "Monitor failed" ---CODE--- diff --git a/tests/wal/advanced/expects/axis_truncated.bi.expect b/tests/wal/advanced/expects/axis_truncated.bi.expect index 577148ad..e11c9fe8 100644 --- a/tests/wal/advanced/expects/axis_truncated.bi.expect +++ b/tests/wal/advanced/expects/axis_truncated.bi.expect @@ -1,11 +1,11 @@ // trace 0 trace { } -error: [send_data@0] executing step 88 of the transaction: 0f != 0e - ┌─ tests/wal/advanced/axis_truncated.prot:10:5 - │ -10 │ D.m_axis_tdata := data; - │ ^^^^^^^^^^^^^^^^^^^^^^^ [send_data@0] executing step 88 of the transaction: 0f != 0e +error: [send_data@0] executing step 88 of the transaction: 0f != 0e + ┌─ tests/wal/advanced/axis_truncated.prot:10:5 + │ +10 │ D.m_axis_tdata := data; + │ ^^^^^^^^^^^^^^^^^^^^^^^ [send_data@0] executing step 88 of the transaction: 0f != 0e Error: "Monitor failed" ---CODE--- diff --git a/tests/wal/advanced/expects/axis_truncated_include_idle.bi.expect b/tests/wal/advanced/expects/axis_truncated_include_idle.bi.expect index dcebb83c..a9f16426 100644 --- a/tests/wal/advanced/expects/axis_truncated_include_idle.bi.expect +++ b/tests/wal/advanced/expects/axis_truncated_include_idle.bi.expect @@ -1,11 +1,11 @@ // trace 0 trace { } -error: [send_data@0] executing step 88 of the transaction: 0f != 0e - ┌─ tests/wal/advanced/axis_truncated_include_idle.prot:11:5 - │ -11 │ D.m_axis_tdata := data; - │ ^^^^^^^^^^^^^^^^^^^^^^^ [send_data@0] executing step 88 of the transaction: 0f != 0e +error: [send_data@0] executing step 88 of the transaction: 0f != 0e + ┌─ tests/wal/advanced/axis_truncated_include_idle.prot:11:5 + │ +11 │ D.m_axis_tdata := data; + │ ^^^^^^^^^^^^^^^^^^^^^^^ [send_data@0] executing step 88 of the transaction: 0f != 0e Error: "Monitor failed" ---CODE--- diff --git a/tests/wb_intercon/expects/wb_arb.bi.expect b/tests/wb_intercon/expects/wb_arb.bi.expect index 7a3afdf3..102c1bf9 100644 --- a/tests/wb_intercon/expects/wb_arb.bi.expect +++ b/tests/wb_intercon/expects/wb_arb.bi.expect @@ -1,7 +1,7 @@ error: the following required arguments were not provided: --wave -Usage: bi --protocol --wave --show-waveform-time --instances ... --sample-posedge --time-unit +Usage: bi --wave --show-waveform-time --color --protocol --instances ... --sample-posedge --time-unit For more information, try '--help'. ---CODE--- diff --git a/tests/wb_intercon/expects/wb_cdc.bi.expect b/tests/wb_intercon/expects/wb_cdc.bi.expect index 98d73982..0e151222 100644 --- a/tests/wb_intercon/expects/wb_cdc.bi.expect +++ b/tests/wb_intercon/expects/wb_cdc.bi.expect @@ -1,5 +1,5 @@ -thread 'main' (11280542) panicked at bi/src/main.rs:90:9: +thread 'main' (11303056) panicked at bi/src/main.rs:98:9: assertion `left == right` failed: Only nano seconds are supported left: "s" right: "ns" From f4fc3478870ccc3ae76b6d36ccee52e0945981bb Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sat, 11 Jul 2026 15:34:58 -0400 Subject: [PATCH 13/55] Register custom panic hook to suppress extraneous information from panic error messages --- bi/src/main.rs | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/bi/src/main.rs b/bi/src/main.rs index 3b97896f..4bf540fc 100644 --- a/bi/src/main.rs +++ b/bi/src/main.rs @@ -91,6 +91,14 @@ struct Cli { #[allow(unused_variables)] fn main() -> Result<(), Box> { + // By default, a Rust panic error messages prints the OS's thread ID + // (e.g. `"thread 'main' ()`), but this changes every time we run this executable. + // To prevent the TID from appearing in error messages that appear in the expected + // output files for Runt, we register a custom panic hook that only prints + // the error message & source code location associated with the panic + // (via the `Display` trait for the `PanicHookInfo` type). + std::panic::set_hook(Box::new(|info| eprintln!("{}", info))); + // Parse CLI args let cli = Cli::parse(); From 9efd6a45e94f7424ec9c009e6460ac98d5a6e630 Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sat, 11 Jul 2026 15:35:03 -0400 Subject: [PATCH 14/55] Update .expect file output --- tests/adders/expects/busy_wait.bi.expect | 4 +--- tests/adders/expects/loop_with_assigns.bi.expect | 4 +--- tests/adders/expects/nested_busy_wait.bi.expect | 4 +--- tests/fifo/expects/push_pop_loop_empty.bi.expect | 4 +--- tests/fifo/expects/push_pop_loop_not_empty.bi.expect | 4 +--- tests/identities/expects/identity_d1.bi.expect | 4 +--- tests/serv/expects/serv_regfile.bi.expect | 4 +--- tests/wb_intercon/expects/wb_cdc.bi.expect | 4 +--- 8 files changed, 8 insertions(+), 24 deletions(-) diff --git a/tests/adders/expects/busy_wait.bi.expect b/tests/adders/expects/busy_wait.bi.expect index 5ed3292e..89398f87 100644 --- a/tests/adders/expects/busy_wait.bi.expect +++ b/tests/adders/expects/busy_wait.bi.expect @@ -1,6 +1,4 @@ - -thread 'main' (11301631) panicked at bi/src/bi.rs:628:21: +panicked at bi/src/bi.rs:628:21: [add_busy_wait@00!] Cannot fork at step zero! -note: run with `RUST_BACKTRACE=1` environment variable to display a backtrace ---CODE--- 101 diff --git a/tests/adders/expects/loop_with_assigns.bi.expect b/tests/adders/expects/loop_with_assigns.bi.expect index d3c5196e..bb042478 100644 --- a/tests/adders/expects/loop_with_assigns.bi.expect +++ b/tests/adders/expects/loop_with_assigns.bi.expect @@ -1,6 +1,4 @@ - -thread 'main' (11301764) panicked at bi/src/bi.rs:628:21: +panicked at bi/src/bi.rs:628:21: [loop_add@00!] Cannot fork at step zero! -note: run with `RUST_BACKTRACE=1` environment variable to display a backtrace ---CODE--- 101 diff --git a/tests/adders/expects/nested_busy_wait.bi.expect b/tests/adders/expects/nested_busy_wait.bi.expect index 386c2750..cd84b0ad 100644 --- a/tests/adders/expects/nested_busy_wait.bi.expect +++ b/tests/adders/expects/nested_busy_wait.bi.expect @@ -1,6 +1,4 @@ - -thread 'main' (11301712) panicked at bi/src/bi.rs:628:21: +panicked at bi/src/bi.rs:628:21: [nested_busy_wait@00!] Cannot fork at step zero! -note: run with `RUST_BACKTRACE=1` environment variable to display a backtrace ---CODE--- 101 diff --git a/tests/fifo/expects/push_pop_loop_empty.bi.expect b/tests/fifo/expects/push_pop_loop_empty.bi.expect index 629d3ff7..52c71229 100644 --- a/tests/fifo/expects/push_pop_loop_empty.bi.expect +++ b/tests/fifo/expects/push_pop_loop_empty.bi.expect @@ -1,6 +1,4 @@ - -thread 'main' (11302832) panicked at bi/src/bi.rs:628:21: +panicked at bi/src/bi.rs:628:21: [pop_n_times@00!] Cannot fork at step zero! -note: run with `RUST_BACKTRACE=1` environment variable to display a backtrace ---CODE--- 101 diff --git a/tests/fifo/expects/push_pop_loop_not_empty.bi.expect b/tests/fifo/expects/push_pop_loop_not_empty.bi.expect index 303e34cf..52c71229 100644 --- a/tests/fifo/expects/push_pop_loop_not_empty.bi.expect +++ b/tests/fifo/expects/push_pop_loop_not_empty.bi.expect @@ -1,6 +1,4 @@ - -thread 'main' (11302773) panicked at bi/src/bi.rs:628:21: +panicked at bi/src/bi.rs:628:21: [pop_n_times@00!] Cannot fork at step zero! -note: run with `RUST_BACKTRACE=1` environment variable to display a backtrace ---CODE--- 101 diff --git a/tests/identities/expects/identity_d1.bi.expect b/tests/identities/expects/identity_d1.bi.expect index 87a6f650..4b88a61a 100644 --- a/tests/identities/expects/identity_d1.bi.expect +++ b/tests/identities/expects/identity_d1.bi.expect @@ -1,6 +1,4 @@ - -thread 'main' (11302885) panicked at bi/src/bi.rs:739:29: +panicked at bi/src/bi.rs:739:29: not yet implemented: we currently expect one side of an assert_eq to be a port! -note: run with `RUST_BACKTRACE=1` environment variable to display a backtrace ---CODE--- 101 diff --git a/tests/serv/expects/serv_regfile.bi.expect b/tests/serv/expects/serv_regfile.bi.expect index b7cd8904..a5b7ee4e 100644 --- a/tests/serv/expects/serv_regfile.bi.expect +++ b/tests/serv/expects/serv_regfile.bi.expect @@ -1,8 +1,6 @@ - -thread 'main' (11303043) panicked at bi/src/constraints.rs:120:9: +panicked at bi/src/constraints.rs:120:9: assertion `left == right` failed left: 32 right: 1 -note: run with `RUST_BACKTRACE=1` environment variable to display a backtrace ---CODE--- 101 diff --git a/tests/wb_intercon/expects/wb_cdc.bi.expect b/tests/wb_intercon/expects/wb_cdc.bi.expect index 0e151222..8e5b9c2f 100644 --- a/tests/wb_intercon/expects/wb_cdc.bi.expect +++ b/tests/wb_intercon/expects/wb_cdc.bi.expect @@ -1,8 +1,6 @@ - -thread 'main' (11303056) panicked at bi/src/main.rs:98:9: +panicked at bi/src/main.rs:106:9: assertion `left == right` failed: Only nano seconds are supported left: "s" right: "ns" -note: run with `RUST_BACKTRACE=1` environment variable to display a backtrace ---CODE--- 101 From a1881e755a4c1395473af023b54dd3861dd78497 Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sat, 11 Jul 2026 15:35:18 -0400 Subject: [PATCH 15/55] Formatting --- bi/src/main.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/bi/src/main.rs b/bi/src/main.rs index 4bf540fc..88fd2b7a 100644 --- a/bi/src/main.rs +++ b/bi/src/main.rs @@ -92,9 +92,9 @@ struct Cli { #[allow(unused_variables)] fn main() -> Result<(), Box> { // By default, a Rust panic error messages prints the OS's thread ID - // (e.g. `"thread 'main' ()`), but this changes every time we run this executable. + // (e.g. `"thread 'main' ()`), but this changes every time we run this executable. // To prevent the TID from appearing in error messages that appear in the expected - // output files for Runt, we register a custom panic hook that only prints + // output files for Runt, we register a custom panic hook that only prints // the error message & source code location associated with the panic // (via the `Display` trait for the `PanicHookInfo` type). std::panic::set_hook(Box::new(|info| eprintln!("{}", info))); From 78ae7bb9947384d28f3b0ad0dd9a51584ac72a86 Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sat, 11 Jul 2026 15:36:11 -0400 Subject: [PATCH 16/55] Add BI tests to CI --- .github/workflows/test.yml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index 368b971f..a2f4bffa 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -36,6 +36,8 @@ jobs: run: runt runt/graph_interp - name: Run Runt tests for monitor run: runt runt/monitor + - name: Run Runt tests for bi + run: runt runt/bi - name: Run Runt tests for waveform run: runt runt/waveform - name: Run Runt tests for fail From f40648e566ff9b127211208b178b35133b3598e7 Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sat, 18 Jul 2026 11:16:51 -0400 Subject: [PATCH 17/55] Remove monitor code + test cases --- .cargo/config.toml | 1 - .github/workflows/test.yml | 27 +- Cargo.toml | 2 +- benchmark_results/baseline_results.csv | 33 - benchmark_results/benchmark_results.csv | 33 - justfile | 3 +- monitor/.gitignore | 2 - monitor/Cargo.toml | 23 - monitor/src/designs.rs | 45 - monitor/src/global_context.rs | 65 - monitor/src/global_scheduler.rs | 515 ------ monitor/src/interpreter.rs | 1197 ------------- monitor/src/macros.rs | 52 - monitor/src/main.rs | 227 --- monitor/src/queue.rs | 116 -- monitor/src/scheduler.rs | 1113 ------------ monitor/src/signal_trace.rs | 407 ----- monitor/src/thread.rs | 145 -- monitor/src/types.rs | 220 --- protocols/src/errors.rs | 4 +- pyproject.toml | 7 +- runt/monitor/runt.toml | 1549 ----------------- scripts/benchmark_monitor.py | 176 -- scripts/check_performance_regression.py | 118 -- scripts/generate_runt_configs.py | 30 +- scripts/plot_benchmark_results.py | 53 - scripts/test_catalog.py | 5 +- tests/adders/expects/add_d1.monitor.expect | 5 - tests/adders/expects/add_d2.monitor.expect | 5 - .../adders/expects/add_var_cyc.monitor.expect | 27 - tests/adders/expects/busy_wait.monitor.expect | 12 - .../expects/loop_with_assigns.monitor.expect | 31 - .../expects/nested_busy_wait.monitor.expect | 2 - tests/alus/expects/alu_d1.monitor.expect | 8 - tests/alus/expects/alu_d2.monitor.expect | 8 - .../test_fifo_classic_1.monitor.expect | 11 - .../test_fifo_classic_2.monitor.expect | 13 - .../test_fifo_classic_3.monitor.expect | 15 - .../test_fifo_classic_4.monitor.expect | 17 - .../test_fifo_classic_5.monitor.expect | 19 - .../test_fifo_classic_6.monitor.expect | 21 - .../test_fifo_classic_7.monitor.expect | 23 - .../test_fifo_classic_8.monitor.expect | 25 - .../test_fifo_constant_1.monitor.expect | 16 - .../test_fifo_constant_2.monitor.expect | 19 - .../test_fifo_constant_3.monitor.expect | 22 - .../test_fifo_constant_4.monitor.expect | 25 - .../test_fifo_constant_5.monitor.expect | 28 - .../test_fifo_constant_6.monitor.expect | 31 - .../test_fifo_constant_7.monitor.expect | 34 - .../test_fifo_constant_8.monitor.expect | 37 - .../test_sram_classic_16_0.monitor.expect | 41 - .../test_sram_classic_16_12.monitor.expect | 41 - .../test_sram_classic_16_4.monitor.expect | 41 - .../test_sram_classic_16_8.monitor.expect | 41 - .../test_sram_classic_1_0.monitor.expect | 11 - .../test_sram_classic_1_12.monitor.expect | 11 - .../test_sram_classic_1_4.monitor.expect | 11 - .../test_sram_classic_1_8.monitor.expect | 11 - .../test_sram_classic_2_0.monitor.expect | 13 - .../test_sram_classic_2_12.monitor.expect | 13 - .../test_sram_classic_2_4.monitor.expect | 13 - .../test_sram_classic_2_8.monitor.expect | 13 - .../test_sram_classic_4_0.monitor.expect | 17 - .../test_sram_classic_4_12.monitor.expect | 17 - .../test_sram_classic_4_4.monitor.expect | 17 - .../test_sram_classic_4_8.monitor.expect | 17 - .../test_sram_classic_8_0.monitor.expect | 25 - .../test_sram_classic_8_12.monitor.expect | 25 - .../test_sram_classic_8_4.monitor.expect | 25 - .../test_sram_classic_8_8.monitor.expect | 25 - ...st_sram_incrementing_16_0_0.monitor.expect | 61 - ...st_sram_incrementing_16_0_1.monitor.expect | 61 - ...st_sram_incrementing_16_0_2.monitor.expect | 61 - ...st_sram_incrementing_16_0_3.monitor.expect | 61 - ...t_sram_incrementing_16_12_0.monitor.expect | 61 - ...t_sram_incrementing_16_12_1.monitor.expect | 61 - ...t_sram_incrementing_16_12_2.monitor.expect | 61 - ...t_sram_incrementing_16_12_3.monitor.expect | 61 - ...st_sram_incrementing_16_4_0.monitor.expect | 61 - ...st_sram_incrementing_16_4_1.monitor.expect | 61 - ...st_sram_incrementing_16_4_2.monitor.expect | 61 - ...st_sram_incrementing_16_4_3.monitor.expect | 61 - ...st_sram_incrementing_16_8_0.monitor.expect | 61 - ...st_sram_incrementing_16_8_1.monitor.expect | 61 - ...st_sram_incrementing_16_8_2.monitor.expect | 61 - ...st_sram_incrementing_16_8_3.monitor.expect | 61 - ...est_sram_incrementing_1_0_0.monitor.expect | 16 - ...est_sram_incrementing_1_0_1.monitor.expect | 16 - ...est_sram_incrementing_1_0_2.monitor.expect | 16 - ...est_sram_incrementing_1_0_3.monitor.expect | 16 - ...st_sram_incrementing_1_12_0.monitor.expect | 16 - ...st_sram_incrementing_1_12_1.monitor.expect | 16 - ...st_sram_incrementing_1_12_2.monitor.expect | 16 - ...st_sram_incrementing_1_12_3.monitor.expect | 16 - ...est_sram_incrementing_1_4_0.monitor.expect | 16 - ...est_sram_incrementing_1_4_1.monitor.expect | 16 - ...est_sram_incrementing_1_4_2.monitor.expect | 16 - ...est_sram_incrementing_1_4_3.monitor.expect | 16 - ...est_sram_incrementing_1_8_0.monitor.expect | 16 - ...est_sram_incrementing_1_8_1.monitor.expect | 16 - ...est_sram_incrementing_1_8_2.monitor.expect | 16 - ...est_sram_incrementing_1_8_3.monitor.expect | 16 - ...est_sram_incrementing_2_0_0.monitor.expect | 19 - ...est_sram_incrementing_2_0_1.monitor.expect | 19 - ...est_sram_incrementing_2_0_2.monitor.expect | 19 - ...est_sram_incrementing_2_0_3.monitor.expect | 19 - ...st_sram_incrementing_2_12_0.monitor.expect | 19 - ...st_sram_incrementing_2_12_1.monitor.expect | 19 - ...st_sram_incrementing_2_12_2.monitor.expect | 19 - ...st_sram_incrementing_2_12_3.monitor.expect | 19 - ...est_sram_incrementing_2_4_0.monitor.expect | 19 - ...est_sram_incrementing_2_4_1.monitor.expect | 19 - ...est_sram_incrementing_2_4_2.monitor.expect | 19 - ...est_sram_incrementing_2_4_3.monitor.expect | 19 - ...est_sram_incrementing_2_8_0.monitor.expect | 19 - ...est_sram_incrementing_2_8_1.monitor.expect | 19 - ...est_sram_incrementing_2_8_2.monitor.expect | 19 - ...est_sram_incrementing_2_8_3.monitor.expect | 19 - ...est_sram_incrementing_4_0_0.monitor.expect | 25 - ...est_sram_incrementing_4_0_1.monitor.expect | 25 - ...est_sram_incrementing_4_0_2.monitor.expect | 25 - ...est_sram_incrementing_4_0_3.monitor.expect | 25 - ...st_sram_incrementing_4_12_0.monitor.expect | 25 - ...st_sram_incrementing_4_12_1.monitor.expect | 25 - ...st_sram_incrementing_4_12_2.monitor.expect | 25 - ...st_sram_incrementing_4_12_3.monitor.expect | 25 - ...est_sram_incrementing_4_4_0.monitor.expect | 25 - ...est_sram_incrementing_4_4_1.monitor.expect | 25 - ...est_sram_incrementing_4_4_2.monitor.expect | 25 - ...est_sram_incrementing_4_4_3.monitor.expect | 25 - ...est_sram_incrementing_4_8_0.monitor.expect | 25 - ...est_sram_incrementing_4_8_1.monitor.expect | 25 - ...est_sram_incrementing_4_8_2.monitor.expect | 25 - ...est_sram_incrementing_4_8_3.monitor.expect | 25 - ...est_sram_incrementing_8_0_0.monitor.expect | 37 - ...est_sram_incrementing_8_0_1.monitor.expect | 37 - ...est_sram_incrementing_8_0_2.monitor.expect | 37 - ...est_sram_incrementing_8_0_3.monitor.expect | 37 - ...st_sram_incrementing_8_12_0.monitor.expect | 37 - ...st_sram_incrementing_8_12_1.monitor.expect | 37 - ...st_sram_incrementing_8_12_2.monitor.expect | 37 - ...st_sram_incrementing_8_12_3.monitor.expect | 37 - ...est_sram_incrementing_8_4_0.monitor.expect | 37 - ...est_sram_incrementing_8_4_1.monitor.expect | 37 - ...est_sram_incrementing_8_4_2.monitor.expect | 37 - ...est_sram_incrementing_8_4_3.monitor.expect | 37 - ...est_sram_incrementing_8_8_0.monitor.expect | 37 - ...est_sram_incrementing_8_8_1.monitor.expect | 37 - ...est_sram_incrementing_8_8_2.monitor.expect | 37 - ...est_sram_incrementing_8_8_3.monitor.expect | 37 - .../expects/bit_truncation_fft.monitor.expect | 4 - .../expects/bit_truncation_sha.monitor.expect | 4 - .../expects/ftu_sha.monitor.expect | 4 - .../expects/signal_async.monitor.expect | 4 - .../expects/use_without_valid.monitor.expect | 4 - .../ethmac_wishbone_manager.monitor.expect | 2 - ...ethmac_wishbone_subordinate.monitor.expect | 2 - tests/fifo/expects/fifo.monitor.expect | 9 - .../expects/push_pop_identity.monitor.expect | 9 - .../push_pop_loop_empty.monitor.expect | 2 - .../push_pop_loop_not_empty.monitor.expect | 2 - .../expects/s4_buggy.monitor.expect | 2 - .../expects/s4_fixed.monitor.expect | 4 - .../expects/s1_buggy.monitor.expect | 2 - .../s1_buggy_workload_1.monitor.expect | 2 - .../expects/s1_fixed.monitor.expect | 8 - .../s1_fixed_workload_1.monitor.expect | 2 - .../expects/s2_buggy.monitor.expect | 18 - .../expects/s2_fixed.monitor.expect | 40 - .../expects/s3_buggy.monitor.expect | 13 - .../expects/s3_fixed.monitor.expect | 12 - .../expects/c4_buggy.monitor.expect | 2 - .../expects/c4_fixed.monitor.expect | 23 - .../expects/d11_buggy.monitor.expect | 17 - .../expects/d11_fixed.monitor.expect | 21 - .../expects/d12_buggy.monitor.expect | 16 - .../expects/d12_fixed.monitor.expect | 15 - .../expects/d4_buggy.monitor.expect | 47 - .../expects/d4_fixed.monitor.expect | 2 - .../expects/identity_d1.monitor.expect | 4 - tests/multi/expects/multi0.monitor.expect | 4 - tests/multi/expects/multi0keep.monitor.expect | 4 - .../expects/multi0keep2const.monitor.expect | 4 - .../multi/expects/multi2const.monitor.expect | 4 - .../multi/expects/multi2multi.monitor.expect | 4 - tests/multi/expects/multi_data.monitor.expect | 4 - .../expects/mult_d2.monitor.expect | 5 - .../pcpi_mul_unsigned_mul.monitor.expect | 8 - .../serv/expects/serv_regfile.monitor.expect | 5 - .../tinyaes128/expects/aes128.monitor.expect | 5 - .../wal/advanced/expects/axis.monitor.expect | 2 - .../expects/axis_failing.monitor.expect | 2 - .../expects/axis_minimal.monitor.expect | 2 - .../expects/axis_truncated.monitor.expect | 2 - ...axis_truncated_include_idle.monitor.expect | 2 - .../wb_intercon/expects/wb_arb.monitor.expect | 2 - .../wb_intercon/expects/wb_cdc.monitor.expect | 125 -- .../wishbone/expects/wishbone.monitor.expect | 18 - uv.lock | 442 ----- well-formedness.md | 1 - 201 files changed, 16 insertions(+), 10503 deletions(-) delete mode 100644 benchmark_results/baseline_results.csv delete mode 100644 benchmark_results/benchmark_results.csv delete mode 100644 monitor/.gitignore delete mode 100644 monitor/Cargo.toml delete mode 100644 monitor/src/designs.rs delete mode 100644 monitor/src/global_context.rs delete mode 100644 monitor/src/global_scheduler.rs delete mode 100644 monitor/src/interpreter.rs delete mode 100644 monitor/src/macros.rs delete mode 100644 monitor/src/main.rs delete mode 100644 monitor/src/queue.rs delete mode 100644 monitor/src/scheduler.rs delete mode 100644 monitor/src/signal_trace.rs delete mode 100644 monitor/src/thread.rs delete mode 100644 monitor/src/types.rs delete mode 100644 runt/monitor/runt.toml delete mode 100644 scripts/benchmark_monitor.py delete mode 100644 scripts/check_performance_regression.py delete mode 100644 scripts/plot_benchmark_results.py delete mode 100644 tests/adders/expects/add_d1.monitor.expect delete mode 100644 tests/adders/expects/add_d2.monitor.expect delete mode 100644 tests/adders/expects/add_var_cyc.monitor.expect delete mode 100644 tests/adders/expects/busy_wait.monitor.expect delete mode 100644 tests/adders/expects/loop_with_assigns.monitor.expect delete mode 100644 tests/adders/expects/nested_busy_wait.monitor.expect delete mode 100644 tests/alus/expects/alu_d1.monitor.expect delete mode 100644 tests/alus/expects/alu_d2.monitor.expect delete mode 100644 tests/antmicro/fifo_classic/expects/test_fifo_classic_1.monitor.expect delete mode 100644 tests/antmicro/fifo_classic/expects/test_fifo_classic_2.monitor.expect delete mode 100644 tests/antmicro/fifo_classic/expects/test_fifo_classic_3.monitor.expect delete mode 100644 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delete mode 100644 tests/antmicro/sram_classic/expects/test_sram_classic_8_8.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_0_0.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_0_1.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_0_2.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_0_3.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_12_0.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_12_1.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_12_2.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_12_3.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_4_0.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_4_1.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_4_2.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_4_3.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_8_0.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_8_1.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_8_2.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_8_3.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_0_0.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_0_1.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_0_2.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_0_3.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_12_0.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_12_1.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_12_2.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_12_3.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_4_0.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_4_1.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_4_2.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_4_3.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_8_0.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_8_1.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_8_2.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_8_3.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_0_0.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_0_1.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_0_2.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_0_3.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_12_0.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_12_1.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_12_2.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_12_3.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_4_0.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_4_1.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_4_2.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_4_3.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_8_0.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_8_1.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_8_2.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_8_3.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_0_0.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_0_1.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_0_2.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_0_3.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_12_0.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_12_1.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_12_2.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_12_3.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_4_0.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_4_1.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_4_2.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_4_3.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_8_0.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_8_1.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_8_2.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_8_3.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_0_0.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_0_1.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_0_2.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_0_3.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_12_0.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_12_1.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_12_2.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_12_3.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_4_0.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_4_1.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_4_2.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_4_3.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_8_0.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_8_1.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_8_2.monitor.expect delete mode 100644 tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_8_3.monitor.expect delete mode 100644 tests/brave_new_world_francis/expects/bit_truncation_fft.monitor.expect delete mode 100644 tests/brave_new_world_francis/expects/bit_truncation_sha.monitor.expect delete mode 100644 tests/brave_new_world_francis/expects/ftu_sha.monitor.expect delete mode 100644 tests/brave_new_world_francis/expects/signal_async.monitor.expect delete mode 100644 tests/brave_new_world_francis/expects/use_without_valid.monitor.expect delete mode 100644 tests/ethmac/expects/ethmac_wishbone_manager.monitor.expect delete mode 100644 tests/ethmac/expects/ethmac_wishbone_subordinate.monitor.expect delete mode 100644 tests/fifo/expects/fifo.monitor.expect delete mode 100644 tests/fifo/expects/push_pop_identity.monitor.expect delete mode 100644 tests/fifo/expects/push_pop_loop_empty.monitor.expect delete mode 100644 tests/fifo/expects/push_pop_loop_not_empty.monitor.expect delete mode 100644 tests/fpga-debugging/axi-burst-s4/expects/s4_buggy.monitor.expect delete mode 100644 tests/fpga-debugging/axi-burst-s4/expects/s4_fixed.monitor.expect delete mode 100644 tests/fpga-debugging/axi-lite-s1/expects/s1_buggy.monitor.expect delete mode 100644 tests/fpga-debugging/axi-lite-s1/expects/s1_buggy_workload_1.monitor.expect delete mode 100644 tests/fpga-debugging/axi-lite-s1/expects/s1_fixed.monitor.expect delete mode 100644 tests/fpga-debugging/axi-lite-s1/expects/s1_fixed_workload_1.monitor.expect delete mode 100644 tests/fpga-debugging/axi-stream-s2/expects/s2_buggy.monitor.expect delete mode 100644 tests/fpga-debugging/axi-stream-s2/expects/s2_fixed.monitor.expect delete mode 100644 tests/fpga-debugging/axis-adapter-s3/expects/s3_buggy.monitor.expect delete mode 100644 tests/fpga-debugging/axis-adapter-s3/expects/s3_fixed.monitor.expect delete mode 100644 tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.monitor.expect delete mode 100644 tests/fpga-debugging/axis-async-fifo-c4/expects/c4_fixed.monitor.expect delete mode 100644 tests/fpga-debugging/axis-fifo-d11/expects/d11_buggy.monitor.expect delete mode 100644 tests/fpga-debugging/axis-fifo-d11/expects/d11_fixed.monitor.expect delete mode 100644 tests/fpga-debugging/axis-fifo-d12/expects/d12_buggy.monitor.expect delete mode 100644 tests/fpga-debugging/axis-fifo-d12/expects/d12_fixed.monitor.expect delete mode 100644 tests/fpga-debugging/axis-fifo-d4/expects/d4_buggy.monitor.expect delete mode 100644 tests/fpga-debugging/axis-fifo-d4/expects/d4_fixed.monitor.expect delete mode 100644 tests/identities/expects/identity_d1.monitor.expect delete mode 100644 tests/multi/expects/multi0.monitor.expect delete mode 100644 tests/multi/expects/multi0keep.monitor.expect delete mode 100644 tests/multi/expects/multi0keep2const.monitor.expect delete mode 100644 tests/multi/expects/multi2const.monitor.expect delete mode 100644 tests/multi/expects/multi2multi.monitor.expect delete mode 100644 tests/multi/expects/multi_data.monitor.expect delete mode 100644 tests/multipliers/expects/mult_d2.monitor.expect delete mode 100644 tests/picorv32/expects/pcpi_mul_unsigned_mul.monitor.expect delete mode 100644 tests/serv/expects/serv_regfile.monitor.expect delete mode 100644 tests/tinyaes128/expects/aes128.monitor.expect delete mode 100644 tests/wal/advanced/expects/axis.monitor.expect delete mode 100644 tests/wal/advanced/expects/axis_failing.monitor.expect delete mode 100644 tests/wal/advanced/expects/axis_minimal.monitor.expect delete mode 100644 tests/wal/advanced/expects/axis_truncated.monitor.expect delete mode 100644 tests/wal/advanced/expects/axis_truncated_include_idle.monitor.expect delete mode 100644 tests/wb_intercon/expects/wb_arb.monitor.expect delete mode 100644 tests/wb_intercon/expects/wb_cdc.monitor.expect delete mode 100644 tests/wishbone/expects/wishbone.monitor.expect diff --git a/.cargo/config.toml b/.cargo/config.toml index 5bd4d4dc..1f2fe3e0 100644 --- a/.cargo/config.toml +++ b/.cargo/config.toml @@ -1,5 +1,4 @@ [alias] interp = "run --quiet --offline --package protocols-interp --" -monitor = "run --quiet --offline --package protocols-monitor --" bi = "run --quiet --package bi --" parse = "run --quiet --package protocols-cli -- -p" diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml index a2f4bffa..2c8549ae 100644 --- a/.github/workflows/test.yml +++ b/.github/workflows/test.yml @@ -34,8 +34,6 @@ jobs: run: runt runt/interp - name: Run Runt tests for graph-interpreter run: runt runt/graph_interp - - name: Run Runt tests for monitor - run: runt runt/monitor - name: Run Runt tests for bi run: runt runt/bi - name: Run Runt tests for waveform @@ -122,30 +120,7 @@ jobs: - name: Use ruff (via uv) to format Python files # We pass in `--preview-features format` to suppress # uv's warning messages about the formatter being experimental - run: uv format --check --preview-features format - - # benchmark: - # name: Performance Benchmarks - # runs-on: ubuntu-24.04 - # timeout-minutes: 30 - - # steps: - # - uses: actions/checkout@v4 - # with: - # fetch-depth: 0 # Fetch all history to access baseline - # - uses: ./.github/actions/setup-test-environment - # with: - # github_token: ${{ secrets.GITHUB_TOKEN }} - # - name: Install hyperfine - # run: | - # wget https://github.com/sharkdp/hyperfine/releases/download/v1.19.0/hyperfine_1.19.0_amd64.deb - # sudo dpkg -i hyperfine_1.19.0_amd64.deb - # - name: Build monitor (release) - # run: cargo build --release --package protocols-monitor - # - name: Run benchmarks - # run: uv run scripts/benchmark_monitor.py - # - name: Check for performance regressions - # run: uv run scripts/check_performance_regression.py + run: uv format --check --preview-features format verilog: diff --git a/Cargo.toml b/Cargo.toml index 4378bc26..efa1c733 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -1,6 +1,6 @@ [workspace] resolver = "3" -members = ["bi", "interp", "monitor", "protocols", "cli", "graph-interp"] +members = ["bi", "interp", "protocols", "cli", "graph-interp"] [workspace.package] diff --git a/benchmark_results/baseline_results.csv b/benchmark_results/baseline_results.csv deleted file mode 100644 index 25be40eb..00000000 --- a/benchmark_results/baseline_results.csv +++ /dev/null @@ -1,33 +0,0 @@ -file_path,test_name,num_steps,mean_per_step,stddev_per_step,min_per_step,max_per_step,steps_per_sec -monitor/tests/adders/add_d1.prot,add_d1,3,0.14875793053333333,0.006126195618268868,0.14195191666666668,0.15829109733333332,6.722330677865422 -monitor/tests/adders/add_d2.prot,add_d2,4,0.125136713575,0.01663598806858157,0.106305302,0.16327435425,7.991259890333107 -monitor/tests/alus/alu_d1.prot,alu_d1,6,0.08479561528333333,0.005089783504966598,0.076473361,0.091997868,11.793062608940714 -monitor/tests/alus/alu_d2.prot,alu_d2,7,0.06671416008571429,0.007254742149509938,0.05790981542857143,0.07599626185714285,14.989321588028702 -monitor/tests/brave_new_world_francis/bit_truncation_fft.prot,bit_truncation_fft,2,0.23601104785,0.024351858125364254,0.2008711665,0.2725409165,4.237089785032282 -monitor/tests/brave_new_world_francis/bit_truncation_sha.prot,bit_truncation_sha,2,0.22485540205000004,0.00970975540080263,0.2101191665,0.23957350000000002,4.447302537021702 -monitor/tests/brave_new_world_francis/ftu_sha.prot,ftu_sha,5,0.09479387414,0.010730857047385248,0.0812029082,0.1213028666,10.549204883462314 -monitor/tests/brave_new_world_francis/signal_async.prot,signal_async,4,0.11973648750000002,0.012270775808615969,0.10090861475,0.14023241675,8.351673085449411 -monitor/tests/brave_new_world_francis/use_without_valid.prot,use_without_valid,4,0.12223532915000002,0.019030568599586885,0.10200301025000001,0.16993876025000001,8.180940869990694 -monitor/tests/fifo/fifo.prot,fifo,7,0.07471902735714285,0.011858567918203744,0.05776523214285715,0.09260451185714287,13.38347185945273 -monitor/tests/fifo/push_pop_identity.prot,push_pop_identity,7,0.07313965772857142,0.007124680249118542,0.06392642271428571,0.08703029171428571,13.672473061209828 -monitor/tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot,c4_buggy,9,0.0571827926,0.0019631679881851097,0.054599301,0.05960237966666667,17.487778307630258 -monitor/tests/fpga-debugging/axis-fifo-d11/d11_buggy.prot,d11_buggy,14,0.03801793809285715,0.006364803708749545,0.026163267857142857,0.05120847321428572,26.30337283304381 -monitor/tests/fpga-debugging/axis-fifo-d11/d11_fixed.prot,d11_fixed,18,0.028343897683333334,0.002302835770616193,0.024919523166666666,0.03205006711111111,35.28096280801973 -monitor/tests/fpga-debugging/axis-fifo-d12/d12_buggy.prot,d12_buggy,15,0.03173991666666667,0.0031241106612165124,0.0272520944,0.035241525,31.50606885651348 -monitor/tests/fpga-debugging/axis-fifo-d12/d12_fixed.prot,d12_fixed,16,0.027547558606250005,0.00170299246537205,0.025870976562500002,0.031336036500000004,36.30085752038729 -monitor/tests/fpga-debugging/axis-fifo-d4/d4_buggy.prot,d4_buggy,64,0.007444867057812501,0.0006232076179890596,0.00662125,0.008239565109375001,134.32073296065363 -monitor/tests/fpga-debugging/axis-fifo-d4/d4_fixed.prot,d4_fixed,74,0.006796869031081082,0.0005187925012940971,0.006017109243243243,0.007463505635135136,147.1265659860661 -monitor/tests/identities/identity_d1.prot,identity_d1,2,0.22811124780000003,0.01845019705435232,0.19928956250000002,0.25774939550000003,4.383825916715712 -monitor/tests/multi/multi0.prot,multi0,2,0.2633629458,0.033184983499937606,0.21690383300000002,0.311940125,3.7970413679964232 -monitor/tests/multi/multi0keep.prot,multi0keep,2,0.25359159585,0.05337954584344636,0.21414804150000002,0.39135025,3.9433483457847007 -monitor/tests/multi/multi0keep2const.prot,multi0keep2const,5,0.09422256754,0.0068852966639202234,0.08476453340000001,0.10302559180000001,10.61316865065764 -monitor/tests/multi/multi2const.prot,multi2const,5,0.08806364578,0.00866290978210808,0.0732284084,0.10405595000000001,11.355423581919299 -monitor/tests/multi/multi2multi.prot,multi2multi,2,0.22786470005000004,0.021745575730084246,0.19717664550000003,0.266391875,4.38856918066103 -monitor/tests/multi/multi_data.prot,multi_data,4,0.11820262190000001,0.010799799240563734,0.1012197395,0.1353747395,8.460049226708396 -monitor/tests/multipliers/mult_d2.prot,mult_d2,4,0.13533660727500002,0.011569700297392268,0.11749706250000001,0.15447808325,7.388983809591364 -monitor/tests/picorv32/pcpi_mul_unsigned_mul.prot,pcpi_mul_unsigned_mul,150,0.003487208360666666,0.00020565603513011122,0.0031455255533333333,0.0037856022200000003,286.76233151976766 -monitor/tests/serv/serv_regfile.prot,serv_regfile,71,0.00756163045915493,0.0007525393297573979,0.006874832169014085,0.009002170774647888,132.24661075433693 -monitor/tests/tinyaes128/aes128.prot,aes128,23,0.022402877539130433,0.003273676371797421,0.01868655252173913,0.030728077913043484,44.63712298803268 -monitor/tests/wal/advanced/axis.prot,axis,1874,0.00047715058916755597,7.326208750458896e-05,0.00040384765208110996,0.0005918900522945571,2095.77442153978 -monitor/tests/wal/advanced/axis_minimal.prot,axis_minimal,179,0.0026242541435754193,0.0003474431563772878,0.0022224466927374302,0.0032717008826815643,381.0606539188115 -monitor/tests/wal/advanced/axis_truncated.prot,axis_truncated,541,0.0009323496532347504,6.009876184702381e-05,0.0008184909112754159,0.0009964992310536045,1072.5589874255215 diff --git a/benchmark_results/benchmark_results.csv b/benchmark_results/benchmark_results.csv deleted file mode 100644 index 4d41903f..00000000 --- a/benchmark_results/benchmark_results.csv +++ /dev/null @@ -1,33 +0,0 @@ -file_path,test_name,num_steps,mean_per_step,stddev_per_step,min_per_step,max_per_step,steps_per_sec -monitor/tests/adders/add_d1.prot,add_d1,3,0.14875793053333333,0.006126195618268868,0.14195191666666668,0.15829109733333332,6.722330677865422 -monitor/tests/adders/add_d2.prot,add_d2,4,0.125136713575,0.01663598806858157,0.106305302,0.16327435425,7.991259890333107 -monitor/tests/alus/alu_d1.prot,alu_d1,6,0.08479561528333333,0.005089783504966598,0.076473361,0.091997868,11.793062608940714 -monitor/tests/alus/alu_d2.prot,alu_d2,7,0.06671416008571429,0.007254742149509938,0.05790981542857143,0.07599626185714285,14.989321588028702 -monitor/tests/brave_new_world_francis/bit_truncation_fft.prot,bit_truncation_fft,2,0.23601104785,0.024351858125364254,0.2008711665,0.2725409165,4.237089785032282 -monitor/tests/brave_new_world_francis/bit_truncation_sha.prot,bit_truncation_sha,2,0.22485540205000004,0.00970975540080263,0.2101191665,0.23957350000000002,4.447302537021702 -monitor/tests/brave_new_world_francis/ftu_sha.prot,ftu_sha,5,0.09479387414,0.010730857047385248,0.0812029082,0.1213028666,10.549204883462314 -monitor/tests/brave_new_world_francis/signal_async.prot,signal_async,4,0.11973648750000002,0.012270775808615969,0.10090861475,0.14023241675,8.351673085449411 -monitor/tests/brave_new_world_francis/use_without_valid.prot,use_without_valid,4,0.12223532915000002,0.019030568599586885,0.10200301025000001,0.16993876025000001,8.180940869990694 -monitor/tests/fifo/fifo.prot,fifo,7,0.07471902735714285,0.011858567918203744,0.05776523214285715,0.09260451185714287,13.38347185945273 -monitor/tests/fifo/push_pop_identity.prot,push_pop_identity,7,0.07313965772857142,0.007124680249118542,0.06392642271428571,0.08703029171428571,13.672473061209828 -monitor/tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot,c4_buggy,9,0.0571827926,0.0019631679881851097,0.054599301,0.05960237966666667,17.487778307630258 -monitor/tests/fpga-debugging/axis-fifo-d11/d11_buggy.prot,d11_buggy,14,0.03801793809285715,0.006364803708749545,0.026163267857142857,0.05120847321428572,26.30337283304381 -monitor/tests/fpga-debugging/axis-fifo-d11/d11_fixed.prot,d11_fixed,18,0.028343897683333334,0.002302835770616193,0.024919523166666666,0.03205006711111111,35.28096280801973 -monitor/tests/fpga-debugging/axis-fifo-d12/d12_buggy.prot,d12_buggy,15,0.03173991666666667,0.0031241106612165124,0.0272520944,0.035241525,31.50606885651348 -monitor/tests/fpga-debugging/axis-fifo-d12/d12_fixed.prot,d12_fixed,16,0.027547558606250005,0.00170299246537205,0.025870976562500002,0.031336036500000004,36.30085752038729 -monitor/tests/fpga-debugging/axis-fifo-d4/d4_buggy.prot,d4_buggy,64,0.007444867057812501,0.0006232076179890596,0.00662125,0.008239565109375001,134.32073296065363 -monitor/tests/fpga-debugging/axis-fifo-d4/d4_fixed.prot,d4_fixed,74,0.006796869031081082,0.0005187925012940971,0.006017109243243243,0.007463505635135136,147.1265659860661 -monitor/tests/identities/identity_d1.prot,identity_d1,2,0.22811124780000003,0.01845019705435232,0.19928956250000002,0.25774939550000003,4.383825916715712 -monitor/tests/multi/multi0.prot,multi0,2,0.2633629458,0.033184983499937606,0.21690383300000002,0.311940125,3.7970413679964232 -monitor/tests/multi/multi0keep.prot,multi0keep,2,0.25359159585,0.05337954584344636,0.21414804150000002,0.39135025,3.9433483457847007 -monitor/tests/multi/multi0keep2const.prot,multi0keep2const,5,0.09422256754,0.0068852966639202234,0.08476453340000001,0.10302559180000001,10.61316865065764 -monitor/tests/multi/multi2const.prot,multi2const,5,0.08806364578,0.00866290978210808,0.0732284084,0.10405595000000001,11.355423581919299 -monitor/tests/multi/multi2multi.prot,multi2multi,2,0.22786470005000004,0.021745575730084246,0.19717664550000003,0.266391875,4.38856918066103 -monitor/tests/multi/multi_data.prot,multi_data,4,0.11820262190000001,0.010799799240563734,0.1012197395,0.1353747395,8.460049226708396 -monitor/tests/multipliers/mult_d2.prot,mult_d2,4,0.13533660727500002,0.011569700297392268,0.11749706250000001,0.15447808325,7.388983809591364 -monitor/tests/picorv32/pcpi_mul_unsigned_mul.prot,pcpi_mul_unsigned_mul,150,0.003487208360666666,0.00020565603513011122,0.0031455255533333333,0.0037856022200000003,286.76233151976766 -monitor/tests/serv/serv_regfile.prot,serv_regfile,71,0.00756163045915493,0.0007525393297573979,0.006874832169014085,0.009002170774647888,132.24661075433693 -monitor/tests/tinyaes128/aes128.prot,aes128,23,0.022402877539130433,0.003273676371797421,0.01868655252173913,0.030728077913043484,44.63712298803268 -monitor/tests/wal/advanced/axis.prot,axis,1874,0.00047715058916755597,7.326208750458896e-05,0.00040384765208110996,0.0005918900522945571,2095.77442153978 -monitor/tests/wal/advanced/axis_minimal.prot,axis_minimal,179,0.0026242541435754193,0.0003474431563772878,0.0022224466927374302,0.0032717008826815643,381.0606539188115 -monitor/tests/wal/advanced/axis_truncated.prot,axis_truncated,541,0.0009323496532347504,6.009876184702381e-05,0.0008184909112754159,0.0009964992310536045,1072.5589874255215 diff --git a/justfile b/justfile index b0742574..ec43f4f5 100644 --- a/justfile +++ b/justfile @@ -1,8 +1,7 @@ # Runs the Runt snapshot suites that together cover every test runt: - cargo build --offline --package protocols-interp --package protocols-monitor --package graph-interp --package bi + cargo build --offline --package protocols-interp --package graph-interp --package bi runt --max-futures 1 runt/interp - runt --max-futures 1 runt/monitor runt --max-futures 1 runt/bi runt --max-futures 1 runt/graph_interp runt --max-futures 1 runt/waveform diff --git a/monitor/.gitignore b/monitor/.gitignore deleted file mode 100644 index bde1bbf8..00000000 --- a/monitor/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -.vscode/ -tests/*.txt diff --git a/monitor/Cargo.toml b/monitor/Cargo.toml deleted file mode 100644 index 233acb68..00000000 --- a/monitor/Cargo.toml +++ /dev/null @@ -1,23 +0,0 @@ -[package] -name = "protocols-monitor" -version = "0.1.0" -description = "analyze signal traces to extract transactions" -edition.workspace = true -rust-version.workspace = true -repository.workspace = true -license.workspace = true - -[dependencies] -protocols.workspace = true -clap = { version = "4.5.45", features = ["derive"] } -clap-verbosity-flag = "3.0.4" -env_logger = "0.11.8" -baa.workspace = true -patronus.workspace = true -wellen = "0.19.0" -log = "0.4.27" -stdext = "0.3" -rustc-hash.workspace = true -anyhow = "1.0.100" -# There are dependency issues if we use rand v0.10, so we pin rand to 0.9 for now -rand = "0.9" diff --git a/monitor/src/designs.rs b/monitor/src/designs.rs deleted file mode 100644 index e3d7811e..00000000 --- a/monitor/src/designs.rs +++ /dev/null @@ -1,45 +0,0 @@ -// Copyright 2025-26 Cornell University -// released under MIT License -// author: Kevin Laeufer -// author: Ernest Ng - -use protocols::frontend::Module; - -/// Concatenates all the names of `struct`s (`Design`s) into one single string -pub fn collects_module_names(duts: &[Module]) -> String { - let mut dut_names: Vec = duts.iter().map(|d| d.name.clone()).collect(); - dut_names.sort(); - dut_names.join(", ") -} - -pub struct Instance { - pub name: String, - #[allow(dead_code)] - module: String, - pub module_id: usize, -} - -/// Takes the contents of the `-i` CLI flag and tries to find -pub fn parse_instance(duts: &[Module], arg: &str) -> Instance { - let parts: Vec<&str> = arg.split(':').collect(); - match parts.as_slice() { - // `module` is the name of the design - // (In Verilog, "modules" are like interfaces and you have "instances" - // (concrete instantiations, aka implementations) of the module) - [inst, module] => { - if let Some(module_id) = duts.iter().position(|d| &d.name == module) { - Instance { - name: inst.to_string(), - module: module.to_string(), - module_id, - } - } else { - panic!( - "Unknown design {module} for instance {inst}. Did you mean {}?", - collects_module_names(duts) - ); - } - } - _ => panic!("unexpected instance argument: {arg}"), - } -} diff --git a/monitor/src/global_context.rs b/monitor/src/global_context.rs deleted file mode 100644 index 8a634e81..00000000 --- a/monitor/src/global_context.rs +++ /dev/null @@ -1,65 +0,0 @@ -// Copyright 2025 Cornell University -// released under MIT License -// author: Ernest Ng - -use crate::Cli; - -/// The `GlobalContext` stores fields which are common to all scheduler groups -/// (regardless of which `struct` they belong to), such as CLI configuration -/// flags. -/// Note: The `WaveSignalTrace` is owned by `GlobalScheduler` and passed -/// as needed. -#[derive(Clone)] -pub struct GlobalContext { - /// The name of the waveform file supplied by the user - /// (Only used for error-reporting purposes) - pub waveform_file: String, - - /// Indicates whether to print integer literals - /// using hexadecimal (if `false`, we default to using decimal). - pub display_hex: bool, - - /// Indicates whether to display the start & end waveform time for each - /// inferred transaction - pub show_waveform_time: bool, - - /// Indicates whether to print the no. of logical steps (i.e. clock cycles) - /// taken by the monitor - pub print_num_steps: bool, - - /// Indicates if there are multiple (more than 1) structs in the source file - pub multiple_structs: bool, - - /// Indicates whether to print out thread IDs for each inferred transaction - pub show_thread_ids: bool, - - /// Indicates whether to print out `idle` transactions (regardless of - /// whether they've been annotated with `#[idle]`) - pub include_idle: bool, - - /// If `Some(n)`, the monitor stops after processing `n` clock cycles. - /// Useful for quickly testing a protocol against the beginning of a - /// large waveform without waiting for the full trace to be processed. - pub max_steps: Option, -} - -impl GlobalContext { - /// Creates a new `GlobalContext` with - /// the configuration flags as specified by the user via the `Cli`. - /// The `display_hex` field indicates whether to print integer literals - /// in hexadecimal (if `false`, we default to using decimal). - /// Note: this function is meant to be called from `main.rs` only - /// upon monitor initialization. - pub fn new(cli: &Cli, multiple_structs: bool) -> Self { - Self { - waveform_file: cli.wave.clone(), - display_hex: cli.display_hex, - show_waveform_time: cli.show_waveform_time, - print_num_steps: cli.print_num_steps, - multiple_structs, - show_thread_ids: cli.show_thread_ids, - include_idle: cli.include_idle, - max_steps: cli.max_steps, - } - } -} diff --git a/monitor/src/global_scheduler.rs b/monitor/src/global_scheduler.rs deleted file mode 100644 index 86a1ef44..00000000 --- a/monitor/src/global_scheduler.rs +++ /dev/null @@ -1,515 +0,0 @@ -// Copyright 2025 Cornell University -// released under MIT License -// author: Ernest Ng - -use std::collections::VecDeque; - -use rustc_hash::FxHashSet; - -use crate::global_context::GlobalContext; -use crate::scheduler::Scheduler; -use crate::signal_trace::{SignalTrace, StepResult, WaveSignalTrace}; -use crate::thread::Thread; -use crate::types::{ - AugmentedProtocolApplication, AugmentedTrace, CycleResult, SchedulerError, SchedulerGroup, - Trace, -}; - -pub struct GlobalScheduler { - /// A `Vec` of `SchedulerGroup`s, where each `SchedulerGroup` is a - /// collection of all schedulers for the same `struct` in our DSL. - /// Note that `SchedulerGroup` is defined as a type alias: - /// ``` - /// type SchedulerGroup = VecDeque - /// ``` - /// where each element in the `VecDeque` on the RHS is a scheduler clone - /// that is exploring a candidate transaction trace - pub scheduler_groups: Vec, - - /// The waveform supplied by the user (shared across all schedulers) - trace: WaveSignalTrace, -} - -/// Processes one clock cycle for all schedulers within the same scheduler group. -/// (See `types.rs` for the definition of a *scheduler group*) -/// Returns a `SchedulerGroup` of all schedulers that have been processed -/// for the current clock cycle. -/// The `other_groups` argument is only for error reporting purposes (printing -/// out the traces inferred by other scheduler groups, i.e. schedulers for -/// other `structs`) if the current scheduler group fails. -fn process_group_cycles( - scheduler_group: SchedulerGroup, - trace: &WaveSignalTrace, - ctx: &GlobalContext, - other_groups: &[&SchedulerGroup], -) -> anyhow::Result { - info!("Entered process_group_cycles function"); - - // We have to define this up here since we end up mutating `scheduler_group` - // later in this function - let group_was_non_empty = !scheduler_group.is_empty(); - - // BFS queue of schedulers (each scheduler represents the continuation - // of a possible protocol trace) - let mut last_failed_scheduler: Option = None; - let mut schedulers_to_process: SchedulerGroup = scheduler_group; - let mut processed_schedulers: SchedulerGroup = SchedulerGroup::new(); - - while let Some(mut scheduler) = schedulers_to_process.pop_front() { - match scheduler.process_current_queue(trace, ctx) { - Ok(CycleResult::Done) => { - processed_schedulers.push_back(scheduler); - } - Ok(CycleResult::Fork { parent }) => { - info!("Entered CycleResult::Fork branch"); - // When there is an explicit/implicit fork, - // we need to iterate over all possible candidate protocols - // and for each candidate protocol, spawn a scheduler that runs it - for transaction in &scheduler.possible_transactions { - let mut cloned_scheduler = scheduler.clone(); - - // If there was an explicit fork, we have to add the - // parent thread to the cloned scheduler's `current` queue. - if let Some(ref thread) = *parent { - cloned_scheduler.current.push_back(thread.clone()); - } - - // Create a new thread for the candidate protocol - let new_thread = Thread::new( - cloned_scheduler.struct_name.clone(), - transaction.clone(), - scheduler.symbol_table.clone(), - transaction.next_stmt_mapping(), - cloned_scheduler.num_threads, - cloned_scheduler.cycle_count, - trace.time_step(), - ); - cloned_scheduler.num_threads += 1; - cloned_scheduler.current.push_back(new_thread); - - // Continue processing the cloned scheduler - schedulers_to_process.push_back(cloned_scheduler); - } - } - Ok(CycleResult::RepeatLoopFork { - exited_thread, - speculative_thread, - }) => { - // For forks that arise due to `repeat` loops, - // create 2 schedulers that each execute a different thread: - // - One which executes the `exited_thread`, i.e. the thread - // which exits the loop with the `LoopArg` set to - // `Known(n)` for some `n >= 0` - // - One which executes the `speculative_thread`, i.e. - // the thread which speculatively executes the loop body - // for another iteration, with the `LoopArg` - // set to `Speculative(n + 1)` - - let mut scheduler_with_exited_thread = scheduler.clone(); - scheduler_with_exited_thread - .current - .push_back(*exited_thread); - schedulers_to_process.push_back(scheduler_with_exited_thread); - - let mut scheduler_with_speculative_thread = scheduler.clone(); - scheduler_with_speculative_thread - .current - .push_back(*speculative_thread); - schedulers_to_process.push_back(scheduler_with_speculative_thread); - } - Err(SchedulerError::NoTransactionsMatch { - struct_name, - error_context, - }) => { - info!("Entered NoTransactionsMatch branch"); - // This individual scheduler failed, so we discard it - // (Other schedulers in the scheduler group may still succeed) - info!( - "Error in scheduler for {}: {:#}", - struct_name, error_context - ); - last_failed_scheduler = Some(scheduler); - } - Err(SchedulerError::Other(err)) => { - info!("Entered OtherSchedulerError branch"); - // This individual scheduler failed; discard it. - info!("Scheduler error for `{}`: {:#}", scheduler.struct_name, err); - last_failed_scheduler = Some(scheduler); - } - } - } - - info!("Exited while-loop in process_group_cycles"); - - // If all schedulers that were processed can't make any more progress - // (i.e. both their `current` & `next` queues are empty, indicating - // there are no more threads to run in the current cycle nor the next cycle), - // and at least one scheduler failed in this cycle, then no scheduler in this - // group can produce a trace that is consistent with the waveform, - // so we emit an error. - let all_schedulers_done = processed_schedulers - .iter() - .all(|scheduler| scheduler.current.is_empty() && scheduler.next.is_empty()); - - info!("all_schedulers_done = {}", all_schedulers_done); - - if group_was_non_empty && all_schedulers_done { - info!("Entered if-statement at end of process_group_cycles"); - - info!( - "last_failed_scheduler.is_some() = {}", - last_failed_scheduler.is_some() - ); - - if let Some(failed_scheduler) = &last_failed_scheduler { - info!( - "All schedulers in the scheduler group for struct `{}` have been processed, - (all of them have no more threads to execute in the current/next cycle), - and there was at least one scheduler that failed, so emitting a global monitor failure", - failed_scheduler.struct_name - ); - eprintln!( - "All schedulers failed: No transactions match the waveform for DUT `{}`", - failed_scheduler.struct_name - ); - eprintln!( - "Trace inferred so far by failed scheduler:\n{}", - failed_scheduler - .output_buffer - .iter() - .map(|augmented_prot_app| { - let start_time = trace.format_time(augmented_prot_app.start_time_step); - let end_time = trace.format_time(augmented_prot_app.end_time_step); - format!( - "\t{}; // [time: {} -> {}]", - augmented_prot_app.protocol_application, start_time, end_time - ) - }) - .collect::>() - .join("\n") - ); - // Print the traces inferred by the other scheduler groups - // (for debugging purposes) - for other_group in other_groups { - if let Some(other_scheduler) = other_group.front() { - eprintln!( - "Trace inferred so far by scheduler for `{}`:\n{}", - other_scheduler.struct_name, - other_scheduler - .output_buffer - .iter() - .map(|augmented_prot_app| { - let start_time = - trace.format_time(augmented_prot_app.start_time_step); - let end_time = trace.format_time(augmented_prot_app.end_time_step); - format!( - "\t{}; // [time: {} -> {}]", - augmented_prot_app.protocol_application, start_time, end_time - ) - }) - .collect::>() - .join("\n") - ); - } - } - failed_scheduler.emit_error(trace, ctx)?; - } - } - - Ok(processed_schedulers) -} - -/// For a single scheduler group, collects all unique maximal traces -/// (deduplicated on canonical `ProtocolApplication` sequence, excluding idle, -/// with strict-prefix traces filtered out). -/// Returns the list of maximal `AugmentedProtocolApplication` traces for this group. -fn collect_maximal_traces(scheduler_group: &SchedulerGroup) -> Vec { - // Collect all unique traces, deduplicating on the canonical - // `ProtocolApplication` sequence (ignoring timing and thread IDs) - let mut all_entries: Vec = vec![]; - let mut seen_traces: FxHashSet = FxHashSet::default(); - - for scheduler in scheduler_group { - // Sort `AugmentedProtocolApplication`s by increasing cycle no. - let mut sorted_output_entries = scheduler.output_buffer.clone(); - sorted_output_entries.sort_by_key(|prot| prot.end_cycle_count); - - // Build canonical trace for dedup, excluding idle entries - let trace: Trace = sorted_output_entries - .iter() - .filter(|prot| !prot.is_idle) - .map(|prot| prot.protocol_application.clone()) - .collect(); - - // Only append `sorted_output_entries` to `all_entries` - // if it the corresponding `trace` wasn't previously in `seen_traces` - if seen_traces.insert(trace) { - all_entries.push(sorted_output_entries); - } - } - - // Filter out traces that are strict prefixes of other traces. - // These are partial traces from schedulers where a child thread failed - // but the parent thread completed successfully, - // resulting in a shorter trace. - let all_traces: Vec = all_entries - .iter() - .map(|augmented_trace| { - augmented_trace - .iter() - .filter(|prot| !prot.is_idle) - .map(|prot| prot.protocol_application.clone()) - .collect() - }) - .collect(); - - // Filter out traces which are strict prefixes of other traces. - // Call the remaining traces *maximal traces*. - let mut maximal_traces: Vec = all_entries - .into_iter() - .enumerate() - .filter(|(i, _)| { - !all_traces.iter().any(|other| { - other.len() > all_traces[*i].len() && other.starts_with(all_traces[*i].as_slice()) - }) - }) - .map(|(_, entries)| entries) - .collect(); - - // Keep only traces that reach the latest non-idle end cycle. - // This discards shorter maximal traces that do not cover as much - // of the waveform as competing candidates. - let max_end_cycle = maximal_traces - .iter() - .map(|trace| trace.max_non_idle_end_cycle()) - .max() - .unwrap_or(0); - maximal_traces.retain(|trace| trace.max_non_idle_end_cycle() == max_end_cycle); - - maximal_traces -} - -impl GlobalScheduler { - /// Pretty-prints a `trace { ... }` block to stdout - fn print_trace_block(trace_index: usize, lines: &[String]) { - println!("// trace {}", trace_index); - println!("trace {{"); - for line in lines { - println!(" {}", line); - } - println!("}}"); - } - - /// Creates an new `GlobalScheduler`. - /// Note: all the `Scheduler`s are expected to be initialized beforehand. - pub fn new(schedulers: Vec, trace: WaveSignalTrace) -> Self { - let scheduler_groups: Vec = schedulers - .into_iter() - .map(|s| VecDeque::from(vec![s])) - .collect(); - Self { - scheduler_groups, - trace, - } - } - - /// Prints all unique protocol traces across all scheduler groups. - /// (Recall that a scheduler group is just all schedulers corresponding - /// to the same `struct` in our DSL, where each scheduler is responsible - /// for exploring a possible candidate protocol trace.) - /// For multi-struct protocols, each struct's scheduler group is processed - /// independently during BFS, then the maximal (longest) trace from each - /// group is interleaved by cycle count at display time. - pub fn print_all_traces(&self, ctx: &GlobalContext) { - // Collect the maximal traces per scheduler group. - // The inner `Vec` represents the traces for all the schedulers - // for the same struct, while the outer `Vec` iterates over all - // possible `struct`s in the user-supplied `.prot` file. - let mut scheduler_group_traces: Vec> = self - .scheduler_groups - .iter() - .map(collect_maximal_traces) - .collect(); - - if scheduler_group_traces.is_empty() { - return; - } - - // Closure for deduplicating traces based on whether - // protocols have been annotated with `#[idle]` and if - // the monitor is in `include_idle` mode - let filter_key = - |prot_app: &AugmentedProtocolApplication| ctx.include_idle || !prot_app.is_idle; - - // For single-struct: show all unique traces directly - if scheduler_group_traces.len() == 1 { - // We call `swap_remove` to take ownership of - // `scheduler_group_traces[0]` without cloning. - // Since we only enter this branch when there's 1 element in - // `scheduler_group_traces`, calling `swap_remove` is OK - // (doesn't break functionality). - let traces: Vec = scheduler_group_traces.swap_remove(0); - for (i, trace) in traces.into_iter().enumerate() { - let lines: Vec = trace - .into_iter() - .filter(filter_key) - .map(|entry| self.format_augmented_protocol_application(&entry, ctx)) - .collect(); - if i > 0 { - println!(); - } - Self::print_trace_block(i, &lines); - } - return; - } - - // If we have multiple structs, pick the longest trace from each scheduler - // group. Interleave traces from each struct based on the cycle count in order. - let mut merged = AugmentedTrace::default(); - for group in scheduler_group_traces.into_iter() { - if let Some(longest) = group - .into_iter() - .max_by_key(|t| t.iter().filter(|&x| filter_key(x)).count()) - { - merged.extend(longest.clone()); - } - } - merged.sort_by_key(|entry| entry.end_cycle_count); - - // Format for stdout - let lines: Vec = merged - .into_iter() - .filter(filter_key) - .map(|entry| self.format_augmented_protocol_application(&entry, ctx)) - .collect(); - Self::print_trace_block(0, &lines); - } - - /// Formats an `AugmentedProtocolApplication` into a display string - fn format_augmented_protocol_application( - &self, - entry: &AugmentedProtocolApplication, - ctx: &GlobalContext, - ) -> String { - match (ctx.show_waveform_time, ctx.show_thread_ids) { - (true, true) | (true, false) => { - let start_time = self.trace.format_time(entry.start_time_step); - let end_time = self.trace.format_time(entry.end_time_step); - if ctx.show_thread_ids { - format!( - "{}; // [time: {} -> {}] (thread {})", - entry.protocol_application, start_time, end_time, entry.thread_id - ) - } else { - format!( - "{}; // [time: {} -> {}]", - entry.protocol_application, start_time, end_time - ) - } - } - (false, true) => format!( - "{}; // (thread {})", - entry.protocol_application, entry.thread_id - ), - (false, false) => format!("{};", entry.protocol_application), - } - } - - /// Runs all the schedulers in a round-robin fashion - pub fn run(&mut self, ctx: &GlobalContext) -> anyhow::Result<()> { - if self.scheduler_groups.is_empty() { - return Ok(()); - } - - let mut trace_ended = false; - let mut steps_taken: u32 = 0; - - loop { - for i in 0..self.scheduler_groups.len() { - // Begin cycle for each scheduler in this scheduler group - for scheduler in self.scheduler_groups[i].iter_mut() { - scheduler.begin_cycle(&self.trace); - } - - // Process each scheduler group and handle forks - let schedulers = std::mem::take(&mut self.scheduler_groups[i]); - let other_groups: Vec<&SchedulerGroup> = self - .scheduler_groups - .iter() - .enumerate() - .filter(|(j, _)| *j != i) - .map(|(_, g)| g) - .collect(); - let result = process_group_cycles(schedulers, &self.trace, ctx, &other_groups)?; - self.scheduler_groups[i] = result; - } - - // If we've reached the end of the trace, - // print the final state of each individual scheduler, - // then exit the loop - if trace_ended { - for scheduler_group in self.scheduler_groups.iter_mut() { - // Remove schedulers in the group - // whose candidate traces finish earlier - // than the maximum end-cycle observed across this group. - // (These are premature schedules that don't cover the entirety - // of the waveform) - let group_max_end_cycle = scheduler_group - .iter() - .map(|scheduler| scheduler.max_non_idle_end_cycle()) - .max() - .unwrap_or(0); - - scheduler_group.retain(|scheduler| { - let max_end_cycle = scheduler.max_non_idle_end_cycle(); - max_end_cycle == group_max_end_cycle - }); - - if let Some(scheduler) = scheduler_group.front() { - scheduler.print_step_count(ctx); - } - } - break; - } - - // Stop early if --max-steps was specified and we've hit the limit - steps_taken += 1; - if let Some(max) = ctx.max_steps - && steps_taken >= max - { - info!("GlobalScheduler: Reached --max-steps limit of {max}, stopping early"); - break; - } - - // Advance the trace (only once for all schedulers) - let step_result = self.trace.step(); - - // Advance all schedulers to their next cycle - for scheduler_group in self.scheduler_groups.iter_mut() { - for scheduler in scheduler_group.iter_mut() { - scheduler.advance_to_next_cycle(ctx, &self.trace); - } - } - - // Check if trace ended (if it finished, then we exit out the loop) - if let StepResult::Done = step_result { - info!("GlobalScheduler: No steps remaining in signal trace"); - // Mark all schedulers as having trace ended - for scheduler_group in self.scheduler_groups.iter_mut() { - for scheduler in scheduler_group.iter_mut() { - scheduler.mark_trace_ended(); - } - } - trace_ended = true; - } - } - - // No more threads to run in each of the schedulers - info!("Monitor finished!"); - - // Print all collected traces - self.print_all_traces(ctx); - - Ok(()) - } -} diff --git a/monitor/src/interpreter.rs b/monitor/src/interpreter.rs deleted file mode 100644 index 34b7a1e8..00000000 --- a/monitor/src/interpreter.rs +++ /dev/null @@ -1,1197 +0,0 @@ -use std::collections::hash_map::Entry; - -use baa::{BitVecMutOps, BitVecOps, BitVecValue}; -use protocols::errors::{ - AssertionError, EvaluationError, ExecutionError, ExecutionResult, SymbolError, -}; -use protocols::frontend::ast::{BinOp, Expr, ExprId, Protocol, Stmt, StmtId, UnaryOp}; -use protocols::frontend::serialize::{ - serialize_args_mapping, serialize_bitvec, serialize_expr, serialize_stmt, -}; -use protocols::frontend::symbol::{SymbolId, SymbolTable}; -use protocols::interpreter::ExprValue; -use protocols::scheduler::NextStmtMap; -use rustc_hash::FxHashMap; - -use crate::global_context::GlobalContext; -use crate::signal_trace::{PortKey, SignalTrace, WaveSignalTrace}; -use crate::thread::Thread; -use crate::types::{LoopArgState, ProtocolApplication}; - -#[allow(dead_code)] -#[derive(Clone)] -pub struct Interpreter { - pub transaction: Protocol, - pub symbol_table: SymbolTable, - pub next_stmt_map: NextStmtMap, - - /// Maps protocol arguments (input/output parameters) to their values - pub args_mapping: FxHashMap, - - /// Tracks which bits of a `SymbolId` are known - pub known_bits: FxHashMap, - - /// Tracks the state of arguments for `repeat` loops - pub loop_args: FxHashMap, - - /// Constraints on DUT input port values that must hold after stepping. - /// These are established by assignments like `D.m_axis_tvalid := 1'b1` - /// or assignments like `DUT.a := a`, - /// and checked after each `step()` to ensure the constraint still holds. - pub constraints: FxHashMap, - - /// The current cycle count in the trace - /// (This field is only used to make error messages more informative) - pub trace_cycle_count: u32, - - /// The `instance_id` of the DUT (which determines which `struct` - /// in our DSL for which we are inferring transactions). - /// This field is useful when we have a `.prot` file with multiple - /// `struct`s. - pub instance_id: u32, -} - -/// internal adapter to deal with the fact that the monitor does support sequence types and -/// all values are bit-vectors -pub(crate) fn serialize_monitor_args_mapping( - args_mapping: &FxHashMap, - symbol_table: &SymbolTable, - display_hex: bool, -) -> String { - let normalized_args = args_mapping - .iter() - .map(|(k, v)| (*k, v.clone().into())) - .collect(); - serialize_args_mapping(&normalized_args, symbol_table, display_hex) -} - -impl Interpreter { - /// Attempts to builds a `ProtocolApplication` from the current interpreter state. - /// `struct_name` is left as `None` — the caller (Scheduler) is responsible - /// for setting it, since the Interpreter doesn't know the struct name. - /// If this return function returns `None` (e.g. because an argument - /// wasn't present in `args_mapping`), the caller - /// (`Scheduler::run_thread_till_next_step`) treats the corresponding thread - /// as having failed. - pub fn to_protocol_application( - &self, - struct_name: Option, - ctx: &GlobalContext, - trace: &WaveSignalTrace, - ) -> Option { - let mut serialized_args = vec![]; - for arg in &self.transaction.args { - let symbol_id = arg.symbol(); - if let Some(value) = self.args_mapping.get(&symbol_id) { - serialized_args.push(serialize_bitvec(value, ctx.display_hex)); - } else { - let name = self.symbol_table[symbol_id].full_name(&self.symbol_table); - let time_str = if ctx.show_waveform_time { - trace.format_time(trace.time_step()) - } else { - format!("cycle {}", self.trace_cycle_count) - }; - info!( - "Transaction `{}`, {}: Unable to find value for {} ({}) in args_mapping, which is {{ {} }}", - self.transaction.name, - time_str, - name, - symbol_id, - serialize_monitor_args_mapping( - &self.args_mapping, - &self.symbol_table, - ctx.display_hex - ) - ); - return None; - } - } - Some(ProtocolApplication { - struct_name, - protocol_name: self.transaction.name.clone(), - serialized_args, - }) - } - - /// Performs a context switch in the `Interpreter` by setting its - /// `Transaction`, `SymbolTable`, `args_mapping`, `known_bits`, and `constraints` - /// to the specified arguments - pub fn context_switch(&mut self, thread: &Thread) { - self.transaction = thread.transaction.clone(); - self.symbol_table = thread.symbol_table.clone(); - self.next_stmt_map = thread.next_stmt_map.clone(); - self.args_mapping = thread.args_mapping.clone(); - self.known_bits = thread.known_bits.clone(); - self.constraints = thread.constraints.clone(); - self.loop_args = thread.loop_args_state.clone(); - } - - /// Pretty-prints a `Statement` identified by its `StmtId` - /// with respect to the current `SymbolTable` associated with this `Evaluator` - pub fn format_stmt(&self, stmt_id: &StmtId) -> String { - self.transaction.format_stmt(stmt_id, &self.symbol_table) - } - - /// Pretty-prints a `Expr` identified by its `ExprID` - /// with respect to the current `SymbolTable` associated with this `Evaluator` - pub fn format_expr(&self, expr_id: &ExprId) -> String { - self.transaction.format_expr(expr_id, &self.symbol_table) - } - - /// Creates a new Interpreter for a given `Transaction` - pub fn new( - transaction: Protocol, - symbol_table: SymbolTable, - trace: &WaveSignalTrace, - trace_cycle_count: u32, - instance_id: u32, - ) -> Self { - let mut args_mapping = FxHashMap::default(); - let mut known_bits = FxHashMap::default(); - - for port_key in trace.port_map.keys() { - // We assume that there is only one `Instance` at the moment - let PortKey { - instance_id, - pin_id, - } = port_key; - - // Fetch the current value of the `pin_id` - // (along with the name of the corresponding `Field`) - let current_value = trace.get(*instance_id, *pin_id).unwrap_or_else(|err| { - panic!( - "Unable to get value for pin {pin_id} in signal trace, {:?}", - err - ) - }); - let bitwidth = current_value.width(); - args_mapping.insert(*pin_id, current_value); - - // Insert a bitstring of all `1`s into `known_bits`, - // with length equal to the bit-width of `current_value` - known_bits.insert(*pin_id, BitVecValue::ones(bitwidth)); - } - - Self { - transaction: transaction.clone(), - symbol_table, - next_stmt_map: transaction.next_stmt_mapping(), - args_mapping, - known_bits, - constraints: FxHashMap::default(), - trace_cycle_count, - loop_args: FxHashMap::default(), - instance_id, - } - } - - /// Evaluates an `Expr` identified by its `ExprId`, returning an `ExprValue` - fn evaluate_expr( - &mut self, - expr_id: &ExprId, - ctx: &GlobalContext, - trace: &WaveSignalTrace, - ) -> ExecutionResult { - let transaction = self.transaction.clone(); - let expr = &transaction[expr_id]; - match expr { - Expr::Const(bit_vec) => Ok(ExprValue::Concrete(bit_vec.clone())), - Expr::Sym(sym_id) => { - let name = self.symbol_table[sym_id].full_name(&self.symbol_table); - - // First check if the symbol is in args_mapping - // (the symbol corresponds to a parameter to the transaction) - if let Some(value) = self.args_mapping.get(sym_id) { - Ok(ExprValue::Concrete(value.clone())) - } - // Otherwise, try to fetch the value from the trace - else if let Ok(value) = trace.get(self.instance_id, *sym_id) { - if ctx.show_waveform_time { - info!( - "Trace @ time {}: `{}` has value {}", - trace.format_time(trace.time_step()), - name, - serialize_bitvec(&value, ctx.display_hex) - ); - } else { - info!( - "Trace @ cycle {}: `{}` has value {}", - self.trace_cycle_count, - name, - serialize_bitvec(&value, ctx.display_hex) - ); - } - - // TODO: what is this code actually supposed to do? - // // Check if the symbol we're referring to - // // is the DUT pin corresponding to an output parameter - // - // // Concretely, we check if the identifier begins with - // // the name of the DUT (e.g. check if "DUT.s" begins with "DUT.") - // let dut_prefix = format!("{}.", self.symbol_table[self.dut_symbol_id].name()); - // if name.starts_with(&dut_prefix) { - // let pin_name = &name[dut_prefix.len()..]; - // - // // Find if there's an output parameter with this name - // // that hasn't been added to the `args_mapping` yet - // for arg in &self.transaction.args { - // let param_name = self.symbol_table[arg.symbol()].name(); - // if param_name == pin_name - // && !self.args_mapping.contains_key(&arg.symbol()) - // { - // // If yes, we read the value for the corresponding - // // DUT pin from the trace, and update the args_mapping - // // so that ` |-> ` - // info!( - // "Capturing output parameter {} = {}", - // param_name, - // serialize_bitvec(&value, ctx.display_hex) - // ); - // self.args_mapping.insert(arg.symbol(), value.clone()); - // - // break; - // } - // } - // } - Ok(ExprValue::Concrete(value)) - } else { - info!( - "args_mapping: \n{}", - serialize_monitor_args_mapping( - &self.args_mapping, - &self.symbol_table, - ctx.display_hex - ) - ); - - Err(ExecutionError::symbol_not_found( - *sym_id, - name.to_string(), - "args_mapping or trace".to_string(), - *expr_id, - )) - } - } - Expr::DontCare => Ok(ExprValue::DontCare), - Expr::Binary(bin_op, lhs_id, rhs_id) => { - let lhs_val = self.evaluate_expr(lhs_id, ctx, trace)?; - let rhs_val = self.evaluate_expr(rhs_id, ctx, trace)?; - match bin_op { - BinOp::Equal => match (&lhs_val, &rhs_val) { - (ExprValue::DontCare, _) | (_, ExprValue::DontCare) => { - Err(ExecutionError::dont_care_operation( - "equality".to_string(), - "binary expression".to_string(), - *expr_id, - )) - } - (ExprValue::Concrete(lhs), ExprValue::Concrete(rhs)) => { - if lhs.width() != rhs.width() { - Err(ExecutionError::arithmetic_error( - "Equal".to_string(), - format!( - "Width mismatch in EQUAL operation: lhs width = {}, rhs width = {}", - lhs.width(), - rhs.width() - ), - *expr_id, - )) - } else if lhs == rhs { - Ok(ExprValue::Concrete(BitVecValue::new_true())) - } else { - Ok(ExprValue::Concrete(BitVecValue::new_false())) - } - } - }, - BinOp::Concat => match (&lhs_val, &rhs_val) { - (ExprValue::DontCare, _) | (_, ExprValue::DontCare) => { - Err(ExecutionError::dont_care_operation( - "CONCAT".to_string(), - "binary expression".to_string(), - *expr_id, - )) - } - (ExprValue::Concrete(lhs), ExprValue::Concrete(rhs)) => { - if lhs.width() != rhs.width() { - Err(ExecutionError::arithmetic_error( - "Concat".to_string(), - format!( - "Width mismatch in CONCAT operation: lhs width = {}, rhs width = {}", - lhs.width(), - rhs.width() - ), - *expr_id, - )) - } else { - Ok(ExprValue::Concrete(lhs.concat(rhs))) - } - } - }, - BinOp::Add => todo!("add support for `add`"), - BinOp::And => todo!("and support for `and`"), - } - } - Expr::Unary(unary_op, expr_id) => { - let expr_val = self.evaluate_expr(expr_id, ctx, trace)?; - match expr_val { - ExprValue::Concrete(bvv) => match unary_op { - UnaryOp::Not => Ok(ExprValue::Concrete(bvv.not())), - }, - ExprValue::DontCare => Err(ExecutionError::dont_care_operation( - "unary operation".to_string(), - "unary expression".to_string(), - *expr_id, - )), - } - } - Expr::Slice(sliced_expr_id, msb, lsb) => { - let sliced_expr = &self.transaction[sliced_expr_id]; - - // Before evaluating the slice, we first need to - // check whether all bits in the slice are currently known - // (i.e. are set to 1 in `self.known_bits`) - // Note: we only do this for the function's (output) parameters - // (i.e. if `sliced_symbol_id` has *no* parent in the `SymbolTable`) - // We don't do this for DUT (output) ports, since if they are - // mentioned in `assert_eq`, we can just read them from the trace - if let Expr::Sym(sliced_symbol_id) = sliced_expr { - if self.symbol_table[sliced_symbol_id].parent().is_none() { - let symbol_name = self.symbol_table[sliced_symbol_id].name(); - - // Check whether `[msb:lsb]` are all 1s in the - // known-bits map - if let Some(known_bits) = self.known_bits.get(sliced_symbol_id) { - let all_bits_known_in_slice = - (*lsb..=*msb).all(|idx| known_bits.is_bit_set(idx)); - if !all_bits_known_in_slice { - // Some bits in the slice are not known yet, - // so we report an error - return Err(ExecutionError::symbol_not_found( - *sliced_symbol_id, - symbol_name.to_string(), - format!( - "known_bits (some bits in slice {}[{}:{}] are not yet known)", - symbol_name, msb, lsb - ), - *sliced_expr_id, - )); - } - } else { - // Report an error since we are trying to slice - // a `symbol_id` where the provenance of the bits - // is unknown (i.e. it is absent from `self.known_bits`) - return Err(ExecutionError::symbol_not_found( - *sliced_symbol_id, - symbol_name.to_string(), - "known_bits".to_string(), - *sliced_expr_id, - )); - } - } - } else { - return Err(ExecutionError::illegal_slice(*sliced_expr_id, *msb, *lsb)); - } - - let expr_val = self.evaluate_expr(sliced_expr_id, ctx, trace)?; - match expr_val { - ExprValue::Concrete(bvv) => { - let width = bvv.width(); - // Check whether `msb` & `lsb` are in bounds - if *msb < width && *lsb <= *msb { - Ok(ExprValue::Concrete(bvv.slice(*msb, *lsb))) - } else { - Err(ExecutionError::invalid_slice( - *sliced_expr_id, - *msb, - *lsb, - width, - )) - } - } - ExprValue::DontCare => Err(ExecutionError::dont_care_operation( - "slice".to_string(), - "slice expression".to_string(), - *sliced_expr_id, - )), - } - } - Expr::IsLastIteration => todo!("add support for is_last() expression"), - Expr::IterCount(_) => todo!("add support for iter_count() expression"), - } - } - - /// Helper function to map an output parameter of a function (`out_param_symbol`) - /// to the trace value for `trace_symbol`. This function checks - /// if `trace_symbol` exists in the trace and `out_param_symbol` is - /// currently *not* in the `args_mapping`. If so, it - /// adds a mapping from `out_param_symbol` to the trace value. - /// - /// Other arguments: - /// - `out_param_name` & `trace_symbol_name` - /// are the full (string) names corresponding to the two symbols - /// respectively. - /// - `trace_symbol_expr_id` is the `ExprId` of `trace_symbol` (this is - /// only used to enable more precise error message locations) - fn map_output_param_to_trace( - &mut self, - out_param_symbol: SymbolId, - trace_symbol: SymbolId, - trace_symbol_expr_id: ExprId, - ctx: &GlobalContext, - trace: &WaveSignalTrace, - ) -> ExecutionResult<()> { - if let Ok(value) = trace.get(self.instance_id, trace_symbol) { - // Only modify the args_mapping if `out_param_symbol` - // is currently *not* present - // (Clippy suggested checking if the `Entry` is `Vacant` - // instead of using `contains_key` + `insert`) - if let Entry::Vacant(e) = self.args_mapping.entry(out_param_symbol) { - e.insert(value.clone()); - let out_param_name = self - .symbol_table - .full_name_from_symbol_id(&out_param_symbol); - info!( - "Extended args_mapping with {} |-> {}", - out_param_name, - serialize_bitvec(&value, ctx.display_hex) - ); - repeat_info!( - "Output param {} = {} (read from trace at cycle {})", - out_param_name, - serialize_bitvec(&value, ctx.display_hex), - self.trace_cycle_count - ); - Ok(()) - } else { - // If `out_param_symbol` is already in the `args_mapping`, - // we do nothing (we don't want to overwrite existing - // key-value bindings) - Ok(()) - } - } else { - info!( - "args_mapping: \n{}", - serialize_monitor_args_mapping( - &self.args_mapping, - &self.symbol_table, - ctx.display_hex - ) - ); - - let trace_symbol_name = self.symbol_table.full_name_from_symbol_id(&trace_symbol); - Err(ExecutionError::symbol_not_found( - trace_symbol, - trace_symbol_name, - "trace".to_string(), - trace_symbol_expr_id, - )) - } - } - - /// Evaluates a `Statement` identified by its `StmtId`, - /// returning the `StmtId` of the next statement to evaluate (if one exists) - pub fn evaluate_stmt( - &mut self, - stmt_id: &StmtId, - ctx: &GlobalContext, - trace: &WaveSignalTrace, - ) -> ExecutionResult> { - let transaction = self.transaction.clone(); - let stmt = &transaction[stmt_id]; - info!( - "Examining statement `{}` ({})", - serialize_stmt(&self.transaction, &self.symbol_table, stmt_id), - stmt_id - ); - match stmt { - Stmt::Assign(symbol_id, expr_id) => { - self.evaluate_assign(symbol_id, expr_id, ctx, trace)?; - Ok(self.next_stmt_map[stmt_id]) - } - Stmt::IfElse(cond_expr_id, then_stmt_id, else_stmt_id) => { - self.evaluate_if(cond_expr_id, then_stmt_id, else_stmt_id, ctx, trace) - } - Stmt::While(loop_guard_id, do_block_id) => { - self.evaluate_while(loop_guard_id, stmt_id, do_block_id, ctx, trace) - } - Stmt::RepeatLoop(_, _) => { - // Repeat loops are intercepted in `run_thread_till_next_step` - // in `scheduler.rs`, so this case is unreachable - unreachable!("Repeat loops handled in `scheduler.rs` already") - } - Stmt::ForInLoop(_, _, _) => todo!("add support for for-in loops"), - Stmt::Step | Stmt::Fork => { - // The scheduler handles `step`s and `fork`s. - // Here, we simply return the next statement to run - Ok(self.next_stmt_map[stmt_id]) - } - Stmt::AssertEq(expr_id1, expr_id2) => { - self.evaluate_assert_eq(stmt_id, expr_id1, expr_id2, ctx, trace) - } - Stmt::Block(stmt_ids) => { - if stmt_ids.is_empty() { - Ok(None) - } else { - Ok(Some(stmt_ids[0])) - } - } - } - } - - /// Evaluates an `assert_eq` statement identified by `stmt_id`, - /// where `expr_id1` & `expr_id2` refer to the two arguments (expressions) - /// supplied to `assert_eq` - fn evaluate_assert_eq( - &mut self, - stmt_id: &StmtId, - expr_id1: &ExprId, - expr_id2: &ExprId, - ctx: &GlobalContext, - trace: &WaveSignalTrace, - ) -> ExecutionResult> { - let e1 = &self.transaction[expr_id1]; - let e2 = &self.transaction[expr_id2]; - match (e1, e2) { - // If the two args to `assert_eq`s are both identifiers, - // one of them is an output param of the transaction, - // & the other is a DUT output port - (Expr::Sym(symbol_id1), Expr::Sym(symbol_id2)) => { - // We deference the two `SymbolId`s in order to - // avoid borrow-checker issues here - let symbol_id1 = *symbol_id1; - let symbol_id2 = *symbol_id2; - - let name1 = self.symbol_table.full_name_from_symbol_id(&symbol_id1); - let name2 = self.symbol_table.full_name_from_symbol_id(&symbol_id2); - - let params: Vec<_> = self.transaction.args.iter().map(|a| a.symbol()).collect(); - for param_symbol in params { - if param_symbol == symbol_id1 { - info!("{} is an output param of the transaction", name1); - self.map_output_param_to_trace( - symbol_id1, symbol_id2, *expr_id2, ctx, trace, - )?; - } else if param_symbol == symbol_id2 { - info!("{} is an output param of the transaction", name2); - self.map_output_param_to_trace( - symbol_id2, symbol_id1, *expr_id1, ctx, trace, - )?; - } - } - Ok(self.next_stmt_map[stmt_id]) - } - (_, _) => { - // Handle other exprs that are supplied to `assert_eq` - // e.g. bit-slices - - let eval_result1 = self.evaluate_expr(expr_id1, ctx, trace); - let eval_result2 = self.evaluate_expr(expr_id2, ctx, trace); - - match (eval_result1.clone(), eval_result2.clone()) { - ( - Ok(ExprValue::Concrete(value1)), - Err(ExecutionError::Symbol(SymbolError::NotFound { .. })), - ) => { - self.infer_value_from_assertion(expr_id2, expr_id1, &value1, ctx)?; - Ok(self.next_stmt_map[stmt_id]) - } - ( - Err(ExecutionError::Symbol(SymbolError::NotFound { .. })), - Ok(ExprValue::Concrete(value2)), - ) => { - self.infer_value_from_assertion(expr_id1, expr_id2, &value2, ctx)?; - Ok(self.next_stmt_map[stmt_id]) - } - // Check whether the two arguments to the assertion are equal - (Ok(ExprValue::Concrete(value1)), Ok(ExprValue::Concrete(value2))) => { - if value1 != value2 { - info!( - "Assertion `{}` failed: {} != {}", - self.format_stmt(stmt_id), - serialize_bitvec(&value1, ctx.display_hex), - serialize_bitvec(&value2, ctx.display_hex), - ); - Err(ExecutionError::Assertion(AssertionError::EqualityFailed { - expr1_id: *expr_id1, - expr2_id: *expr_id2, - value1, - value2, - })) - } else { - info!("Assertion `{}` passed", self.format_stmt(stmt_id),); - Ok(self.next_stmt_map[stmt_id]) - } - } - - // For other cases, we skip the assertion for now - (Ok(_), Ok(_)) => { - info!( - "Skipping assertion `{}` ({})", - self.format_stmt(stmt_id), - stmt_id - ); - Ok(self.next_stmt_map[stmt_id]) - } - _ => { - if eval_result1.is_err() { - info!("{} is ???", self.format_expr(expr_id1)) - } - if eval_result2.is_err() { - info!("{} is ???", self.format_expr(expr_id2)) - } - info!( - "Skipping assertion `{}` ({})", - self.format_stmt(stmt_id), - stmt_id - ); - Ok(self.next_stmt_map[stmt_id]) - } - } - } - } - } - - /// Infers the value of an unknown expression from an assertion, - /// and inserts a binding for it into the `args_mapping`. - /// - `unknown_expr_id` is the expr whose value we're inferring - /// - `known_expr_id` is the (known) expr with value `known_value` - fn infer_value_from_assertion( - &mut self, - unknown_expr_id: &ExprId, - known_expr_id: &ExprId, - known_value: &BitVecValue, - ctx: &GlobalContext, - ) -> ExecutionResult<()> { - let unknown_expr = &self.transaction[unknown_expr_id]; - - match unknown_expr { - Expr::Slice(sliced_expr_id, msb, lsb) => { - let sliced_expr = &self.transaction[sliced_expr_id]; - match sliced_expr { - Expr::Sym(sliced_symbol_id) => { - let symbol_name = - self.symbol_table[sliced_symbol_id].full_name(&self.symbol_table); - info!( - "Inferring value for `{}[{}:{}]` from assertion with `{}`", - symbol_name, - msb, - lsb, - self.format_expr(known_expr_id) - ); - - // Get the expected width from the symbol's type - let expected_width = self.symbol_table[sliced_symbol_id].tpe().bitwidth(); - - // If `sliced_symbol_id` isn't in either of - // `args_mapping` or `known_bits`, map it to the - // bit-vector of all zeroes - self.args_mapping - .entry(*sliced_symbol_id) - .or_insert_with(|| BitVecValue::zero(expected_width)); - self.known_bits - .entry(*sliced_symbol_id) - .or_insert_with(|| BitVecValue::zero(expected_width)); - - // Get the current value and known_bits - let mut current_value = self.args_mapping[sliced_symbol_id].clone(); - let mut known_bits = self.known_bits[sliced_symbol_id].clone(); - - // Update bits `[msb:lsb]` w/ the known value - for i in 0..=(msb - lsb) { - let bit_pos = lsb + i; - if known_value.is_bit_set(i) { - current_value.set_bit(bit_pos); - } else { - current_value.clear_bit(bit_pos); - } - // Mark this bit as known - known_bits.set_bit(bit_pos); - } - - // Update `args_mapping` and `known_bits` to point - // to the updated values & known bits - self.args_mapping - .insert(*sliced_symbol_id, current_value.clone()); - self.known_bits - .insert(*sliced_symbol_id, known_bits.clone()); - - info!( - "Updated args_mapping: {} |-> {} (0b{})", - symbol_name, - serialize_bitvec(¤t_value, ctx.display_hex), - current_value.to_bit_str() - ); - info!( - "Updated known_bits: {} |-> {}", - symbol_name, - known_bits.to_bit_str() - ); - - Ok(()) - } - _ => Ok(()), - } - } - Expr::Sym(symbol_id) => { - // Fetch all the parameters of the function - let params: Vec<_> = self.transaction.args.iter().map(|a| a.symbol()).collect(); - - let param_strs = params - .iter() - .map(|symbol_id| self.symbol_table[symbol_id].name().to_string()) - .collect::>() - .join(", "); - info!("out_params = {}", param_strs); - - // If `symbol_id` is an output parameter that is currently - // absent from `args_mapping`, insert the binding - // `symbol_id |-> known_value` into `args_mapping`, - // and update `known_bits` to be all ones - if params.contains(symbol_id) { - let symbol_name = self.symbol_table[symbol_id].full_name(&self.symbol_table); - - info!("Identified {} as an output parameter", symbol_name); - - if let Entry::Vacant(e) = self.args_mapping.entry(*symbol_id) { - e.insert(known_value.clone()); - let width = known_value.width(); - self.known_bits.insert(*symbol_id, BitVecValue::ones(width)); - info!( - "Extended args_mapping with {} |-> {}", - symbol_name, - serialize_bitvec(known_value, ctx.display_hex) - ); - } - } - Ok(()) - } - _ => Ok(()), - } - } - - /// Evaluates an `if`-statement, returning the `StmtId` of the next - /// statement to evaluate (if one exists) - fn evaluate_if( - &mut self, - cond_expr_id: &ExprId, - then_stmt_id: &StmtId, - else_stmt_id: &StmtId, - ctx: &GlobalContext, - trace: &WaveSignalTrace, - ) -> ExecutionResult> { - let res = self.evaluate_expr(cond_expr_id, ctx, trace)?; - match res { - ExprValue::DontCare => Err(ExecutionError::invalid_condition( - "if".to_string(), - *cond_expr_id, - )), - ExprValue::Concrete(bvv) => { - if bvv.is_zero() { - Ok(Some(*else_stmt_id)) - } else { - Ok(Some(*then_stmt_id)) - } - } - } - } - /// When the monitor encounters an assignment of the form `lhs_symbol_id := rhs_expr_id`, - /// e.g. `DUT.a := a` (where `stmt_id` is the `StmtId` of the assignment): - /// 1. It first tries to evaluate `rhs_expr_id` to a value. - /// 2. If `rhs_expr_id` successfully evaluates to a value, we know the corresponding - /// `expr` is a value. - /// - We compare this constant value with the value of `lhs_symbol_id` (the LHS) - /// (the DUT pin) from the trace. - /// - If the values are different, we emit a `ValueDisagreesWithTrace` error - /// 3. If `rhs_expr_id` can't be evaluated to a value (e.g. it fails with a `SymbolNotFound` error), - /// this is either because `rhs_expr_id` is an unsupported expr pattern (indicated w/ `todo!(...)`) - /// or `rhs_expr_id` corresponds to a `Symbol` that is currently not in `args_mapping`. - /// - For the latter, we check if the expr is a symbol. - /// - If it is a symbol `s`, update `args_mapping` to be `args_mapping[s |-> read_trace(lhs_symbol_id)]`, - /// i.e. make the symbol `s` point to the trace value for `lhs_symbol_id` - /// in the resultant `args_mapping`. - /// - For any other expr pattern, we do `todo!(...)` - fn evaluate_assign( - &mut self, - lhs_symbol_id: &SymbolId, - rhs_expr_id: &ExprId, - ctx: &GlobalContext, - trace: &WaveSignalTrace, - ) -> ExecutionResult<()> { - let lhs_name = self.symbol_table.full_name_from_symbol_id(lhs_symbol_id); - match self.evaluate_expr(rhs_expr_id, ctx, trace) { - Ok(ExprValue::Concrete(rhs_value)) => { - let rhs_expr = &self.transaction[rhs_expr_id]; - match rhs_expr { - Expr::Const(_) | Expr::Sym(_) => { - // We only print out the following log for the case - // where a variable evaluates to a value, since the - // constant case is trivial - if let Expr::Sym(_) = rhs_expr { - info!( - "`{}` evaluates to Concrete Value `{}`", - serialize_expr(&self.transaction, &self.symbol_table, rhs_expr_id), - serialize_bitvec(&rhs_value, ctx.display_hex) - ); - } - - // If the `rhs` is a constant or an identifier, - // we compare it with the trace's value for the LHS - if let Ok(trace_value) = trace.get(self.instance_id, *lhs_symbol_id) { - // If they're different, we report an error - if rhs_value != trace_value { - Err(ExecutionError::value_disagrees_with_trace( - *rhs_expr_id, - rhs_value, - trace_value, - *lhs_symbol_id, // Use LHS symbol for error reporting - lhs_name.to_string(), - self.trace_cycle_count, - )) - } else { - // Update the `known_bits` mapping for the RHS - // with all 1s (since the RHS is an input parameter - // whose value we are learning) - if let Expr::Sym(rhs_symbol_id) = rhs_expr { - let width = trace_value.width(); - self.known_bits - .insert(*rhs_symbol_id, BitVecValue::ones(width)); - } - - // If LHS is a DUT input port (has a parent) and RHS is a constant, - // add this as a constraint that must hold after stepping - if let Expr::Const(_) = rhs_expr - && self.symbol_table[*lhs_symbol_id].parent().is_some() - { - info!( - "Adding constraint: {} must equal {}", - lhs_name, - serialize_bitvec(&rhs_value, ctx.display_hex) - ); - self.constraints.insert(*lhs_symbol_id, rhs_value.clone()); - } - - Ok(()) - } - } else { - info!( - "Unable to find value for `{}` in trace at cycle {:?}", - lhs_name, self.trace_cycle_count - ); - Err(ExecutionError::symbol_not_found( - *lhs_symbol_id, - lhs_name.to_string(), - "trace".to_string(), - *rhs_expr_id, - )) - } - } - Expr::Slice(sliced_expr_id, msb, lsb) => { - // In this case, we are taking a bitslice - // of an identifier that we've previously seen before - // (i.e. the identifier exists as a key - // in the `args_mapping`) - - let sliced_expr = &self.transaction[sliced_expr_id]; - match sliced_expr { - Expr::Sym(sliced_symbol_id) => { - let symbol_name = &self.symbol_table[sliced_symbol_id].name(); - info!( - "`{}`[{}:{}] evaluates to Concrete Value `{}`", - symbol_name, - msb, - lsb, - serialize_bitvec(&rhs_value, ctx.display_hex) - ); - - // Compare `rhs_value` (the value that - // `slice_expr[msb:lsb]` evaluates to) - // with the actual trace value - // (Note that we don't need to perform any - // further bit-slicing here, since we've - // already evaluated `slice_expr[msb:lsb]` - - if let Ok(trace_value) = trace.get(self.instance_id, *lhs_symbol_id) - { - // If they're different, we report an error - if rhs_value != trace_value { - Err(ExecutionError::value_disagrees_with_trace( - *rhs_expr_id, - rhs_value, - trace_value, - *lhs_symbol_id, // Use LHS symbol for error reporting - lhs_name.to_string(), - self.trace_cycle_count, - )) - } else { - // The value matches the trace data, - // so all we have to do is update - // `known_bits` for `sliced_symbol_id` - // by setting bits `[msb:lsb]` to 1 - let known_mask = self - .known_bits - .get_mut(sliced_symbol_id) - .unwrap_or_else(|| { - panic!( - "Missing entry in `known_bits` for {}", - symbol_name - ) - }); - for idx in *lsb..=*msb { - known_mask.set_bit(idx); - } - Ok(()) - } - } else { - info!( - "Unable to find value for `{}` in trace at cycle {:?}", - lhs_name, self.trace_cycle_count - ); - Err(ExecutionError::symbol_not_found( - *lhs_symbol_id, - lhs_name.to_string(), - "trace".to_string(), - *rhs_expr_id, - )) - } - } - _ => { - // Illegal bit-slice operation - // (this will already have been caught by the type-checker) - Err(ExecutionError::illegal_slice(*rhs_expr_id, *msb, *lsb)) - } - } - } - _ => todo!( - "Unhandled expr pattern {} which evaluates to {}", - serialize_expr(&self.transaction, &self.symbol_table, rhs_expr_id), - serialize_bitvec(&rhs_value, ctx.display_hex) - ), - } - } - Ok(ExprValue::DontCare) => { - // If the LHS is a DUT (input) port (e.g. `DUT.a`) and we - // encountered a DontCare assignment `DUT.a := X`, - // remove any constraints for it and any parameter bindings - if self.symbol_table[*lhs_symbol_id].parent().is_some() { - self.constraints.remove(lhs_symbol_id); - - info!( - "Cleared bindings for {} in `constraints` due to DontCare assignment", - self.symbol_table[*lhs_symbol_id].full_name(&self.symbol_table) - ); - } - Ok(()) - } - Err(ExecutionError::Symbol(SymbolError::NotFound { .. })) => { - let rhs_expr = &self.transaction[rhs_expr_id]; - match rhs_expr { - Expr::Sym(rhs_symbol_id) => { - let symbol_name = - self.symbol_table[rhs_symbol_id].full_name(&self.symbol_table); - info!( - "RHS of assignment is a symbol `{}` ({}) that is not in the args_mapping, adding it...", - symbol_name, rhs_symbol_id - ); - if let Ok(trace_value) = trace.get(self.instance_id, *lhs_symbol_id) { - self.args_mapping - .insert(*rhs_symbol_id, trace_value.clone()); - info!( - "Updated args_mapping to map {} |-> {}", - symbol_name, - serialize_bitvec(&trace_value, ctx.display_hex) - ); - - // All the bits are known, so we insert a bit-string of - // all 1s into the `known_bits` map - // From type-checking, we know that the bitwidth of the - // LHS & RHS must be the same (otherwise the type-checker - // would have rejected the program) - let width = trace_value.width(); - self.known_bits - .insert(*rhs_symbol_id, BitVecValue::ones(width)); - info!("Updated known_bits to map {} |-> 111...1", symbol_name); - - // Add a constraint saying that `DUT input port := current trace value` - // (This is checked after future `step()`s) - self.constraints.insert(*lhs_symbol_id, trace_value.clone()); - info!( - "Added constraint: {} == {}", - lhs_name, - serialize_bitvec(&trace_value, ctx.display_hex) - ); - - Ok(()) - } else { - Err(ExecutionError::symbol_not_found( - *lhs_symbol_id, - symbol_name, - "trace".to_string(), - *rhs_expr_id, - )) - } - } - // The case below corresponds to a bit-slice - // where the identifier being sliced hasn't been - // encountered before (i.e. is not in the args_mapping) - Expr::Slice(sliced_expr_id, msb, lsb) => { - let sliced_expr = &self.transaction[sliced_expr_id]; - match sliced_expr { - Expr::Sym(sliced_symbol_id) => { - let symbol_name = self.symbol_table[sliced_symbol_id] - .full_name(&self.symbol_table); - info!( - "RHS of assignment is a bit-slice on an identifier `{}[{}:{}]` where `{}` is not in the args_mapping (adding it now...)", - symbol_name, msb, lsb, symbol_name - ); - - // Look up the trace value corresponding - // to the LHS - if let Ok(trace_value) = trace.get(self.instance_id, *lhs_symbol_id) - { - // Look up the width of `sliced_symbol_id` - // based on its type in the `SymbolTable`. - // Call this the `expected_width` - // (the width is dictated by the type) - let expected_width = - self.symbol_table[sliced_symbol_id].tpe().bitwidth(); - info!("{} has type u{}", symbol_name, expected_width); - - // If `sliced_symbol_id` isn't currently - // in either of `args_mapping` & `known_bits`, - // map it to the bit-vector of all zeroes - self.args_mapping - .entry(*sliced_symbol_id) - .or_insert_with(|| BitVecValue::zero(expected_width)); - self.known_bits - .entry(*sliced_symbol_id) - .or_insert_with(|| BitVecValue::zero(expected_width)); - - // We have to clone these values in order - // to satisfy the borrower checker - let mut current_value = - self.args_mapping[sliced_symbol_id].clone(); - let mut current_known_bits = - self.known_bits[sliced_symbol_id].clone(); - - // Update bits `[msb:lsb]` w/ the trace value - for i in 0..=(msb - lsb) { - let bit_pos = lsb + i; - if trace_value.is_bit_set(i) { - current_value.set_bit(bit_pos); - } else { - current_value.clear_bit(bit_pos); - } - // Mark this bit as known - current_known_bits.set_bit(bit_pos); - } - - // Update `args_mapping` and `known_bits` - self.args_mapping - .insert(*sliced_symbol_id, current_value.clone()); - self.known_bits - .insert(*sliced_symbol_id, current_known_bits.clone()); - - info!( - "Updated args_mapping to map {} |-> {} (0b{})", - symbol_name, - serialize_bitvec(¤t_value, ctx.display_hex), - current_value.to_bit_str() - ); - - info!( - "Updated known_bits to map {} |-> {}", - symbol_name, - current_known_bits.to_bit_str() - ); - - Ok(()) - } else { - Err(ExecutionError::symbol_not_found( - *lhs_symbol_id, - symbol_name, - "trace".to_string(), - *sliced_expr_id, - )) - } - } - _ => { - // Illegal bit-slice operation - // (this will already have been caught by the type-checker) - Err(ExecutionError::illegal_slice(*sliced_expr_id, *msb, *lsb)) - } - } - } - _ => { - todo!( - "Unhandled expr pattern {} which results in SymbolNotFound error", - serialize_expr(&self.transaction, &self.symbol_table, rhs_expr_id), - ) - } - } - } - Err(ExecutionError::Evaluation(EvaluationError::InvalidSlice { - expr_id, - start, - end, - width, - })) => { - panic!( - "Evaluation Error: Invalid slice {}[{}:{}] (actual width is {})", - serialize_expr(&self.transaction, &self.symbol_table, &expr_id), - start, - end, - width - ) - } - Err(e) => todo!("Unhandled error {}", e), - } - } - - /// Evaluates a `while`-loop with guard `loop_guard_id` and - /// loop-body `do_block_id`. Note that the argument `while_id` - /// is the `StmtId` for the `while`-loop itself. - fn evaluate_while( - &mut self, - loop_guard_id: &ExprId, - while_id: &StmtId, - do_block_id: &StmtId, - ctx: &GlobalContext, - trace: &WaveSignalTrace, - ) -> ExecutionResult> { - let res = self.evaluate_expr(loop_guard_id, ctx, trace)?; - match res { - ExprValue::DontCare => Err(ExecutionError::invalid_condition( - "while".to_string(), - *loop_guard_id, - )), - ExprValue::Concrete(bvv) => { - if bvv.is_true() { - // Proceed to the next iteration of the loop - Ok(Some(*do_block_id)) - } else { - let next_stmt_str = match self.next_stmt_map[while_id] { - Some(next_stmt_id) => { - format!( - "{} ({})", - serialize_stmt( - &self.transaction, - &self.symbol_table, - &next_stmt_id - ), - next_stmt_id - ) - } - None => "No next stmt".to_string(), - }; - info!( - "Loop guard `{}` evaluated to false, exiting loop, next stmt: `{}`", - serialize_expr(&self.transaction, &self.symbol_table, loop_guard_id), - next_stmt_str, - ); - // Exit the loop, executing the statement that follows it immediately - Ok(self.next_stmt_map[while_id]) - } - } - } - } -} diff --git a/monitor/src/macros.rs b/monitor/src/macros.rs deleted file mode 100644 index 6297f022..00000000 --- a/monitor/src/macros.rs +++ /dev/null @@ -1,52 +0,0 @@ -/// Takes the output of `stdext::debug_name!` (in the `debug_name` argument) -/// and extracts the file name, line number and function name where -/// the log was called, returning a formatted string of -/// the form `file_name:line (function_name)`. -pub fn compact_debug_prefix(debug_name: &str) -> String { - // `stdext::debug_name!` returns strings in the form - // " at `, so we have to split on "at" - let mut debug_parts = debug_name.split(" at "); - let loc = debug_parts.next().unwrap_or("?:0"); - let fn_path = debug_parts.next().unwrap_or("?"); - let mut loc_parts = loc.rsplitn(2, ':'); - let line = loc_parts.next().unwrap_or("0"); - // `stdext::debug_name!` gives us the full filepath - // we just need the stem of the filepath (the file name) - let file_path = loc_parts.next().unwrap_or(loc); - let file = std::path::Path::new(file_path) - .file_name() - .and_then(|f| f.to_str()) - .unwrap_or(file_path); - let fn_name = fn_path.rsplit("::").next().unwrap_or(fn_path); - format!("{}:{} ({})", file, line, fn_name) -} - -/// A wrapper around the `log::info!` macro, which includes the function name, -/// file name and line number in which the log was called -/// (obtained via `stdext::debug_name!`) -macro_rules! info { - ($($arg:tt)*) => {{ - let location = crate::macros::compact_debug_prefix(&stdext::debug_name!()); - log::info!( - target: "info", - "{}: {}", - location, - format_args!($($arg)*) - ) - }} -} - -/// Like `info!`, but prefixes the target with `"repeat::"` so logs can be filtered -/// independently of other logs. Use this macro when logging events -/// related to `repeat` loops. -macro_rules! repeat_info { - ($($arg:tt)*) => {{ - let location = crate::macros::compact_debug_prefix(&stdext::debug_name!()); - log::info!( - target: "repeat", - "{}: {}", - location, - format_args!($($arg)*) - ) - }} -} diff --git a/monitor/src/main.rs b/monitor/src/main.rs deleted file mode 100644 index 0d2d72c0..00000000 --- a/monitor/src/main.rs +++ /dev/null @@ -1,227 +0,0 @@ -// Copyright 2025 Cornell University -// released under MIT License -// author: Ernest Ng -// author: Kevin Laeufer - -#[macro_use] -mod macros; -mod designs; -mod global_context; -mod global_scheduler; -mod interpreter; -mod queue; -mod scheduler; -mod signal_trace; -mod thread; -mod types; - -use std::io::Write; - -use anyhow::{Context, anyhow}; -use clap::{ColorChoice, Parser}; -use clap_verbosity_flag::{Verbosity, WarnLevel}; -use log::LevelFilter; -use protocols::frontend; -use protocols::frontend::diagnostic::DiagnosticHandler; - -use crate::designs::*; -use crate::global_context::GlobalContext; -use crate::global_scheduler::GlobalScheduler; -use crate::scheduler::Scheduler; -use crate::signal_trace::WaveSignalTrace; - -// From the top-level directory, run: -// $ cargo run --package protocols-monitor -- -p tests/adders/adder_d1/add_d1.prot -w trace.fst -i add_d1:Adder - -/// Args for the monitor CLI -#[derive(Parser, Debug)] -#[command(version, about, long_about = None, disable_version_flag = true)] -struct Cli { - #[arg( - short, - long, - value_name = "PROTOCOLS_FILE", - help = "One or several protocol files." - )] - protocol: Vec, - - /// Path to a waveform trace (.fst, .vcd, .ghw) file - #[arg(short, long, value_name = "WAVE_FILE")] - wave: String, - - /// A mapping of DUT struct in the protocol file to an instance in the signal trace. - /// Multiple arguments can be passed if they're seperated by whitespace. - /// Format is: `${instance_name}:${dut_struct_name}` - #[arg(short, long, value_delimiter = ' ', num_args = 1..)] - instances: Vec, - - /// Users can specify `-v` or `--verbose` to toggle logging - #[command(flatten)] - verbosity: Verbosity, - - /// To suppress colors in error messages, pass in `--color never` - /// Otherwise, by default, error messages are displayed w/ ANSI colors - #[arg(long, value_name = "COLOR_CHOICE", default_value = "auto")] - color: ColorChoice, - - /// If enabled, displays integer literals using hexadecimal notation - #[arg(short, long, value_name = "DISPLAY_IN_HEX")] - display_hex: bool, - - /// Optional argument which specifies the name of the - /// signal to sample on a rising edge (posedge). If enabled, this - /// flag acts as the "clock" signal for the monitor. - /// Note: the full path to the signal should be passed as this argument, - /// e.g. `uut_rx.clk`, where `uut_rx` is an instance in the signal trace. - #[arg(long, value_name = "SIGNAL_TO_SAMPLE_ON_RISING_EDGE")] - sample_posedge: Option, - - /// If enabled, displays the start & end waveform time for each inferred transaction - #[arg(long, value_name = "SHOW_START_END_WAVEFORM_TIME_FOR_EACH_TRANSACTION")] - show_waveform_time: bool, - - /// If enabled, displays the thread ID corresponding to each inferred transaction - #[arg(long, value_name = "SHOW_THREAD_IDS")] - show_thread_ids: bool, - - /// Time unit to use when displaying waveform times (e.g. "ns", "s"). Defaults to "ns". - #[arg(long, value_name = "TIME_UNIT", requires = "show_waveform_time")] - time_unit: Option, - - /// Optional flag: if enabled, prints the no. of (logical) steps - /// (i.e. clock cycles) taken by the montior - #[arg(long, value_name = "PRINT_NUM_STEPS_TAKEN")] - print_num_steps: bool, - - /// Optional flag: if enabled, always prints out idle transcations - /// regardless of whether the protocol has been annotated with `#[idle]` - #[arg(long, value_name = "ALWAYS_PRINT_IDLE_TRANSACTIONS")] - include_idle: bool, - - /// If this CLI flag is specified, - /// the monitor stops after processing after a certain no. of clock cycles. - /// (This should only be used when test the monitor over a large waveform - /// where we only want to see the monitor's output on a prefix of the waveform.) - #[arg(long, value_name = "MAX_STEPS")] - max_steps: Option, - - /// Skips the static checks for step/fork errors. - #[arg(long)] - skip_static_step_fork_checks: bool, -} - -fn main() -> anyhow::Result<()> { - // Parse CLI args - let cli = Cli::parse(); - - // Set up logger to use the log-level specified via the `-v` flag. - // For concision, we disable timestamps and the module paths in the log. - let mut logger = env_logger::Builder::new(); - - // Configure output format of logger. - // For `info!` / `repeat_info!` logs, call-site context is included - // directly by the macros via `debug_name!`. - // When -v is passed, show only repeat-loop logs (target="repeat"). - // All other info-level logs are hidden to reduce noise. - if cli.verbosity.log_level_filter() >= LevelFilter::Info { - logger.filter(None, LevelFilter::Info); - } else { - logger.filter_level(cli.verbosity.log_level_filter()); - } - - logger.format(move |buf, record| { - let target = record.target(); - if target == "repeat" || target == "info" { - writeln!(buf, "{}", record.args()) - } else { - writeln!(buf, "({}): {}", target, record.args()) - } - }); - - if cli.color == ColorChoice::Never { - logger.write_style(env_logger::WriteStyle::Never); - } - - logger.init(); - - // Print warning messages only if `--verbose` is enabled - // (the --verbose flag triggers `LevelFilter::Info`) - let emit_warnings = cli.verbosity.log_level_filter() == LevelFilter::Info; - - // Note: for the monitor, error message locations in `.prot` files are suppressed - // in the `DiagnosticHandlers` for now - let mut protocols_handler = - DiagnosticHandler::new(cli.color, false, emit_warnings, cli.display_hex); - - // Parse protocols file - let (st, modules) = frontend( - &cli.protocol, - &mut protocols_handler, - cli.skip_static_step_fork_checks, - )?; - - // Try to find instances that we care about - if cli.instances.is_empty() { - println!("Available DUTs are: {}", collects_module_names(&modules)); - println!("No instances specified. Nothing to monitor. Exiting..."); - return Ok(()); - } - - let instances: Vec = cli - .instances - .iter() - .map(|arg| parse_instance(&modules, arg)) - .collect(); - - // parse waveform - let trace = WaveSignalTrace::open( - &cli.wave, - &modules, - &instances, - cli.sample_posedge.clone(), - cli.time_unit.clone(), - ) - .with_context(|| format!("failed to read waveform file {}", cli.wave))?; - - // Check if we have multiple structs/designs - let multiple_structs = instances.len() > 1; - - // Multi-struct mode: create a GlobalScheduler with one scheduler per design - let mut schedulers = vec![]; - - // We use the index of `design` in `dut_designs` as our `instance_id` - for (instance_id, inst) in instances.iter().enumerate() { - // Filter transactions that belong to this design - let module = &modules[inst.module_id]; - - if module.protos.is_empty() { - continue; // Skip designs with no transactions - } - - // Create a scheduler for this design, using the design name as the struct name - let scheduler = Scheduler::initialize( - &st, - &module.protos, - &trace, - module.name.clone(), - instance_id as u32, - ); - - schedulers.push(scheduler); - } - - // Create a `GlobalScheduler` whose `schedulers` field - // contains all the initialized schedulers - let mut global_scheduler = GlobalScheduler::new(schedulers, trace); - - // Create a GlobalContext that is shared across all schedulers - // (regardless of which `struct` they belong to) - let ctx = GlobalContext::new(&cli, multiple_structs); - - if let Err(error_msg) = global_scheduler.run(&ctx) { - eprintln!("{error_msg}"); - return Err(anyhow!("Monitor failed")); - } - - Ok(()) -} diff --git a/monitor/src/queue.rs b/monitor/src/queue.rs deleted file mode 100644 index aeb0ba9b..00000000 --- a/monitor/src/queue.rs +++ /dev/null @@ -1,116 +0,0 @@ -// Copyright 2026 Cornell University -// released under MIT License -// author: Ernest Ng - -/*! This file defines a `Queue` data structure, representing a ready - * queue of threads. This type is used in the monitor scheduler. - */ - -use std::collections::VecDeque; - -use protocols::frontend::serialize::serialize_stmt; - -use crate::global_context::GlobalContext; -use crate::signal_trace::WaveSignalTrace; -use crate::thread::Thread; - -/// `Queue` is just a type alias for `VecDeque`. -/// We use a `VecDeque` instead of `Vec`, since `VecDeque::pop_back` produces -/// elements in a FIFO order (which is what we want), -/// whereas `Vec::pop` returns elements in LIFO order -pub type Queue = VecDeque; - -/// Formats a queue's contents into a pretty-printed string -/// Note: we can't implement the `Display` trait for `Queue` since -/// `Queue` is just a type alias -#[allow(dead_code)] -pub fn format_queue( - queue: &Queue, - ctx: &GlobalContext, - trace: &WaveSignalTrace, - struct_name: &str, -) -> String { - if !queue.is_empty() { - let formatted_queue = queue - .iter() - .map(|thread| format_thread(thread, ctx, trace, struct_name)) - .collect::>() - .join("\n\t"); - format!("\n\t{}", formatted_queue) - } else { - "".to_string() - } -} - -/// Formats a single thread with context-aware timing information -#[allow(dead_code)] -pub fn format_thread( - thread: &Thread, - ctx: &GlobalContext, - trace: &WaveSignalTrace, - struct_name: &str, -) -> String { - let start_info = if ctx.show_waveform_time { - format!("Start time: {}", trace.format_time(thread.start_time_step)) - } else { - format!("Start cycle: {}", thread.start_cycle) - }; - - let transaction_name = if ctx.multiple_structs { - format!("{}::{}", struct_name, thread.transaction.name) - } else { - thread.transaction.name.clone() - }; - - format!( - "THREAD {}: {{ {}, Transaction: `{}`, Current stmt: `{}` ({}) }}", - thread.global_thread_id(ctx), - start_info, - transaction_name, - serialize_stmt( - &thread.transaction, - &thread.symbol_table, - &thread.current_stmt_id - ), - thread.current_stmt_id - ) -} - -/// Formats a queue's contents into a *compact* pretty-printed string -/// (i.e. no new-lines, only displays the thread_id and transaction name -/// for each thread) -pub fn format_queue_compact(queue: &Queue, ctx: &GlobalContext) -> String { - if !queue.is_empty() { - queue - .iter() - .map(|thread| { - format!( - "Thread {} (`{}`)", - thread.global_thread_id(ctx), - thread.transaction.name - ) - }) - .collect::>() - .join(", ") - } else { - "".to_string() - } -} - -/// Extracts all elements in the `Queue` where all the threads have the -/// same `start_cycle`, preserving their order -pub fn threads_with_start_time(queue: &Queue, start_cycle: u32) -> Queue { - queue - .clone() - .into_iter() - .filter(|thread| thread.start_cycle == start_cycle) - .collect() -} - -/// Finds all the unique start cycles of all the threads in the same queue -pub fn unique_start_cycles(queue: &Queue) -> Vec { - let mut start_cycles: Vec = queue.iter().map(|thread| thread.start_cycle).collect(); - start_cycles.sort(); - start_cycles.dedup(); - start_cycles -} diff --git a/monitor/src/scheduler.rs b/monitor/src/scheduler.rs deleted file mode 100644 index ea8b258f..00000000 --- a/monitor/src/scheduler.rs +++ /dev/null @@ -1,1113 +0,0 @@ -use anyhow::anyhow; -use baa::{BitVecOps, BitVecValue}; -use protocols::errors::{EvaluationError, ExecutionError}; -use protocols::frontend::ast::{Expr, Protocol, Stmt, StmtId}; -use protocols::frontend::serialize::serialize_bitvec; -use protocols::frontend::symbol::{SymbolId, SymbolTable}; -use rustc_hash::FxHashSet; - -use crate::global_context::GlobalContext; -use crate::interpreter::{Interpreter, serialize_monitor_args_mapping}; -use crate::queue::*; -use crate::signal_trace::{SignalTrace, WaveSignalTrace}; -use crate::thread::Thread; -use crate::types::{ - AugmentedProtocolApplication, AugmentedTrace, CycleResult, LoopArgState, SchedulerError, - ThreadResult, -}; - -/// Scheduler for handling the multiple threads in the monitor -#[derive(Clone)] -pub struct Scheduler { - /// Queue storing threads that are ready (to be run during the current step) - pub current: Queue, - - /// Queue of suspended threads (to be run during the next step) - pub next: Queue, - - /// Threads that have finished successfully - pub finished: Queue, - - /// Threads that failed - pub failed: Queue, - - /// The current scheduling cycle - pub cycle_count: u32, - - /// The no. of threads that have been created so far. - /// (This variable is used to create unique `thread_id`s for `Thread`s.) - pub num_threads: u32, - - /// The associated interpreter for Protocols programs - interpreter: Interpreter, - - /// Flag indicating whether the trace has ended - trace_ended: bool, - - /// Tracks which start cycles have already called fork() in the current cycle - /// (Used to prevent duplicate thread spawning when multiple threads from the - /// same start cycle finish simultaneously) - forked_start_cycles: FxHashSet, - - /// Tracks which thread (if any) has finished in the current cycle - /// Only one thread per struct should finish per cycle - finished_thread: Option<(u32, u32, String)>, // (start_cycle, thread_id, transaction_name) - - /// All possible transactions - /// (This is used when forking new threads) - pub possible_transactions: Vec, - - /// The global symbol table. - pub symbol_table: SymbolTable, - - /// The name of the struct this scheduler is monitoring - /// (Used for prefixing transaction names in multi-struct scenarios) - /// Note: if there is just one single struct, this string is empty - pub struct_name: String, - - /// The instance ID of the DUT instance this scheduler is monitoring. - /// Used to look up the correct signals in the waveform trace. - pub instance_id: u32, - - /// Output buffer, where each element is an `OutputEntry` - /// (defined in `types.rs`). - pub output_buffer: AugmentedTrace, -} - -impl Scheduler { - // Helper function that prefixes a transaction's name with the name of a struct - // if the source file contains multiple struct - pub fn format_transaction_name(&self, ctx: &GlobalContext, transaction_name: String) -> String { - if ctx.multiple_structs { - format!("{}::{}", self.struct_name, transaction_name) - } else { - transaction_name - } - } - - /// Prints the internal state of the scheduler - /// (i.e. the contents of all 4 queues + current scheduling cycle) - #[allow(dead_code)] - pub fn print_scheduler_state(&self, trace: &WaveSignalTrace, ctx: &GlobalContext) { - let time_step = trace.time_step(); - let header = if ctx.show_waveform_time { - format!("SCHEDULER STATE, TIME {}:", trace.format_time(time_step)) - } else { - format!("SCHEDULER STATE, CYCLE {}:", self.cycle_count) - }; - info!( - "{}\n{}\n{}\n{}\n{}", - header, - format_args!( - "Current: {}", - format_queue(&self.current, ctx, trace, &self.struct_name) - ), - format_args!( - "Next: {}", - format_queue(&self.next, ctx, trace, &self.struct_name) - ), - format_args!( - "Failed: {}", - format_queue(&self.failed, ctx, trace, &self.struct_name) - ), - format_args!( - "Finished: {}", - format_queue(&self.finished, ctx, trace, &self.struct_name) - ) - ); - } - - /// Initializes a `Scheduler` with one scheduled thread for each `(Transcation, SymbolTable)` - /// pair in the argument `transactions`. - /// The `instance_id` indicates the `struct` for which the scheduler is exploring - /// transaction traces (this is useful in `.prot` files when multiple - /// `struct`s are defined). - pub fn initialize( - st: &SymbolTable, - protos: &[Protocol], - trace: &WaveSignalTrace, - struct_name: String, - instance_id: u32, - ) -> Self { - let cycle_count = 0; - let mut thread_id = 0; - let mut current_threads = Queue::new(); - // Create a new thread for each transaction, then push it to the - // end of the `current` queue - for proto in protos { - let thread = Thread::new( - struct_name.clone(), - proto.clone(), - st.clone(), - proto.next_stmt_mapping(), - thread_id, - cycle_count, - trace.time_step(), - ); - current_threads.push_back(thread); - thread_id += 1; - } - // Technically, initializing the `interpreter` here is unnecessary - // since when we pop a thread from the `current` queue, we perform - // a context switch and run the `interpreter` on the transaction/symbol_table - // corresponding to the thread. However, we do this here nonetheless - // since we need to initialize all fields in `Scheduler` struct. - let initial_thread = ¤t_threads[0]; - let initial_transaction = initial_thread.transaction.clone(); - let initial_symbol_table = initial_thread.symbol_table.clone(); - let interpreter = Interpreter::new( - initial_transaction, - initial_symbol_table, - trace, - cycle_count, - instance_id, - ); - Self { - current: current_threads, - next: Queue::new(), - finished: Queue::new(), - failed: Queue::new(), - interpreter, - cycle_count, - num_threads: thread_id, - trace_ended: false, - forked_start_cycles: FxHashSet::default(), - finished_thread: None, - possible_transactions: protos.to_vec(), - symbol_table: st.clone(), - struct_name, - instance_id, - output_buffer: AugmentedTrace::default(), - } - } - - /// Call this function exactly once at the beginning of each cycle - /// (**Don't** call this on a cloned `Scheduler` that is created from a `fork`) - #[allow(unused_variables)] - pub fn begin_cycle(&mut self, trace: &WaveSignalTrace) { - // Clear auxiliary fields at the beginning of each cycle - // to track which start cycles fork/finish in THIS cycle - self.forked_start_cycles.clear(); - self.finished_thread = None; - // self.print_scheduler_state(trace, ctx); - } - - /// Runs the scheduler in the current cycle by repeating the following steps. - /// 1. While the `current` queue is non-empty, - /// pop a thread from the `current` queue and runs it till the next `step` - /// and exmaine its `ThreadResult`. - /// - If it `fork`ed either implicitly or explicitly, return early by - /// signalling to the caller the appropriate `CycleResult` - /// - Otherwise, continue. - /// 2. When the `current` queue is empty, it sets `current` to `next` - /// (marking all suspended threads as ready for execution), - /// then advances the trace to the next step. - /// Notes: - /// - This function is used by `GlobalScheduler::process_group_cycles` - /// to coordinate execution between multiple schedulers. - /// - When a `fork` creates a `Scheduler` clone, call this function - /// on the clone - pub fn process_current_queue( - &mut self, - trace: &WaveSignalTrace, - ctx: &GlobalContext, - ) -> Result { - // info!( - // "Inside `Scheduler::process_current_queue` for {} scheduler", - // self.struct_name - // ); - - // Process each thread. Note that - // this function returns early when a thread `fork`s, with the - // new forked-off threads propagated to the caller - // (`GlobalScheduler::process_group_cycles`) - while let Some(thread) = self.current.pop_front() { - match self.run_thread_till_next_step(thread, trace, ctx)? { - ThreadResult::Completed => continue, - ThreadResult::ExplicitFork { parent } => { - return Ok(CycleResult::Fork { - parent: Box::new(Some(*parent)), - }); - } - ThreadResult::ImplicitFork => { - return Ok(CycleResult::Fork { - parent: Box::new(None), - }); - } - ThreadResult::RepeatLoopFork { - exited_thread, - speculative_thread, - } => { - return Ok(CycleResult::RepeatLoopFork { - exited_thread, - speculative_thread, - }); - } - } - } - - // At this point, all threads have been executed till their next `step` - // and are synchronized (i.e. `current` is empty) - - // Check constraints for all threads in the `next` queue. - // These threads have called `step()` and have more work to do. - // Threads that finished (i.e. they executed the `step()` statement at - // the end of a function) are not in `next`, so they won't be checked. - let mut failed_constraint_checks = Vec::new(); - - for thread in self.next.iter_mut() { - // If any constraints failed, figure out the right time-step/cycle - // to display in the logs - let time_str = if ctx.show_waveform_time { - trace.format_time(trace.time_step()) - } else { - format!("cycle {}", self.interpreter.trace_cycle_count) - }; - - // Check that all constraints in the `constraints` map still hold - // against the current trace values. This is called after each `step()` - // to ensure that assignments like `D.m_axis_tvalid := 1'b1` continue - // to hold after stepping to a new cycle. - for (symbol_id, expected_value) in &thread.constraints { - let symbol_name = thread.symbol_table.full_name_from_symbol_id(symbol_id); - - match trace.get(self.instance_id, *symbol_id) { - Ok(trace_value) => { - if trace_value != *expected_value { - info!( - "Constraint FAILED for thread {} (`{}`) at {}: {} = {} (trace) != {} (expected)", - thread.global_thread_id(ctx), - thread.transaction.name, - time_str, - symbol_name, - serialize_bitvec(&trace_value, ctx.display_hex), - serialize_bitvec(expected_value, ctx.display_hex) - ); - failed_constraint_checks.push(thread.clone()); - } else { - info!( - "Constraint OK for thread {} (`{}`) at {}: {} = {}", - thread.global_thread_id(ctx), - thread.transaction.name, - time_str, - symbol_name, - serialize_bitvec(expected_value, ctx.display_hex) - ); - } - } - Err(_) => { - info!( - "Unable to verify constraint for {} at cycle {:?} - symbol not found in trace", - symbol_name, self.interpreter.trace_cycle_count - ); - // If we can't read the symbol from the trace, treat it as a constraint violation - // (The constraint can't hold if the signal doesn't exist in the trace) - failed_constraint_checks.push(thread.clone()); - } - } - } - } - - // Remove threads that failed constraint checks from `next` and add to `failed` - for failed_thread in failed_constraint_checks { - info!( - "Moving thread {} (`{}`) to `failed` as it failed a constraint check", - failed_thread.global_thread_id(ctx), - failed_thread.transaction.name - ); - self.next.retain(|t| t.thread_id != failed_thread.thread_id); - self.failed.push_back(failed_thread); - } - - // Check that threads in the `finished` and `failed` queues - // behave as expected - self.validate_finished_and_failed_threads(trace, ctx)?; - - Ok(CycleResult::Done) - } - - /// Validates that threads in the `finished` and `failed` queues - /// behave as expected - pub fn validate_finished_and_failed_threads( - &mut self, - trace: &WaveSignalTrace, - ctx: &GlobalContext, - ) -> Result<(), SchedulerError> { - // Find the unique start cycles of all threads in the `finished` queue - let finished_threads_start_cycles = unique_start_cycles(&self.finished); - - // Out of all threads that started in the same cycle & finished in the most recent step... - for start_cycle in finished_threads_start_cycles { - // ...there should only be at most one of them in `finished` - let finished = threads_with_start_time(&self.finished, start_cycle); - if finished.len() > 1 { - let start_time = if ctx.show_waveform_time { - trace.format_time(finished[0].start_time_step) - } else { - format!("cycle {}", start_cycle) - }; - let end_time_step = trace.time_step(); - let end_time = if ctx.show_waveform_time { - trace.format_time(end_time_step) - } else { - format!("cycle {}", self.cycle_count) - }; - - return Err(SchedulerError::Other(anyhow!( - "Scheduler for `{}`: Expected the no. of threads for that started at {} & ended at {} to be at most 1, but instead there were {} ({:?})", - self.struct_name, - start_time, - end_time, - finished.len(), - finished - .iter() - .map(|t| t.transaction.name.clone()) - .collect::>() - ))); - } - let finished_thread = &finished[0]; - - // ...and there shouldn't be any other threads in `next` - let next = threads_with_start_time(&self.next, start_cycle); - if !next.is_empty() { - let start_time_str = if ctx.show_waveform_time { - trace.format_time(finished_thread.start_time_step) - } else { - format!("cycle {}", finished_thread.start_cycle) - }; - let error_context = anyhow!( - "Thread {} (`{}`) finished but there are other threads with the same start time ({}) in the `next` queue, namely {:?}", - finished_thread.global_thread_id(ctx), - finished_thread.transaction.name, - start_time_str, - next.iter() - .map(|t| t.transaction.name.clone()) - .collect::>() - ); - - return Err(SchedulerError::NoTransactionsMatch { - struct_name: self.struct_name.clone(), - error_context, - }); - } - } - - // Next, find the unique start cycles of all threads in `failed` - let failed_threads_start_cycles = unique_start_cycles(&self.failed); - - // Out of all threads that started in the same cycle & failed in the most recent step... - for start_cycle in failed_threads_start_cycles { - // ...if `failed` is non-empty, but `next` and `finished` are non-empty, - // then we should emit an error - // (The expected behavior is that all but one threads that started in - // the same cycle should fail, but here we have the case where - // *all* the threads that started in the same cycle failed) - let failed = threads_with_start_time(&self.failed, start_cycle); - let finished = threads_with_start_time(&self.finished, start_cycle); - let paused = threads_with_start_time(&self.next, start_cycle); - - // We also need to check whether the `next` queue contains - // any threads (regardless of their start time) before emitting - // an error. A thread `t` that started in an EARLIER cycle - // might be paused at an intermediate `step()` (i.e. `t` is in `next`), - // while all threads from the CURRENT `start_cycle` have failed. - // In this case, we still need to try to run `t` since it may - // succeed, even though all threads from the current cycle failed. - // (Example: `picorv32/unsigned_mul.prot`) - // We also check that no threads finished successfully this cycle - // (regardless of their start cycle) before throwing the error -- - // this allows us to handle implicitly forked threads that - // are spawned at the end of fork-free protocols (when they - // reach the final `step()` statement). - if failed.len() > 1 - && finished.is_empty() - && paused.is_empty() - && self.next.is_empty() - && self.finished_thread.is_none() - { - let error_context = anyhow!( - "Out of all threads that started in cycle {}, all but one are expected to fail, but all {} of them failed", - start_cycle, - failed.len() - ); - - return Err(SchedulerError::NoTransactionsMatch { - struct_name: self.struct_name.clone(), - error_context, - }); - } - } - - // Print all the threads that finished & failed during the most recent step - if !self.failed.is_empty() { - if ctx.show_waveform_time { - let time_str = trace.format_time(trace.time_step()); - info!( - "Threads that failed at time {}: {}", - time_str, - format_queue_compact(&self.failed, ctx) - ); - } else { - info!( - "Threads that failed in cycle {}: {}", - self.cycle_count, - format_queue_compact(&self.failed, ctx) - ); - } - - // If there are a non-zero no. of failed threads, - // and there are no threads that finished succesfully / - // no threads waiting to be run / no threads that are currently still running, - // then we know that *all* threads have failed. In which case, we emit - // an error message indicating that no transactions match the given waveform. - let no_transactions_match = - self.current.is_empty() && self.next.is_empty() && self.finished.is_empty(); - - if no_transactions_match { - return Err(SchedulerError::NoTransactionsMatch { - struct_name: self.struct_name.clone(), - error_context: anyhow!("All threads failed for {}", self.struct_name), - }); - } else { - self.failed.clear(); - } - } - - if !self.finished.is_empty() { - if ctx.show_waveform_time { - let time_str = trace.format_time(trace.time_step()); - info!( - "Threads that finished at time {}: {}", - time_str, - format_queue_compact(&self.finished, ctx) - ); - } else { - info!( - "Threads that finished in cycle {}: {}", - self.cycle_count, - format_queue_compact(&self.finished, ctx) - ); - } - self.finished.clear(); - } - - Ok(()) - } - - /// Helper function to print the number of steps taken - pub fn print_step_count(&self, ctx: &GlobalContext) { - if ctx.print_num_steps { - eprintln!( - "No. of steps taken by {} scheduler: {}", - self.struct_name, self.cycle_count - ); - } - } - - /// Advances to the next cycle by moving next queue to current and incrementing cycle count - /// (This function should only be called after `trace.step()` has been called in `GlobalScheduler`) - pub fn advance_to_next_cycle(&mut self, ctx: &GlobalContext, trace: &WaveSignalTrace) { - // If next queue is empty and we're in multi-struct mode, - // spawn new threads for this cycle. - // This is necessary in multi-struct mode where schedulers need to continuously - // try to discover transactions even if all previous threads failed - if self.next.is_empty() && ctx.multiple_structs { - info!( - "Next queue is empty for `{}` scheduler, spawning new threads for cycle {}", - self.struct_name, self.cycle_count - ); - for transaction in &self.possible_transactions { - let new_thread = Thread::new( - self.struct_name.clone(), - transaction.clone(), - self.symbol_table.clone(), - transaction.next_stmt_mapping(), - self.num_threads, - self.cycle_count, - trace.time_step(), - ); - self.num_threads += 1; - info!( - "Adding new thread {} (`{}`) to `next` queue", - new_thread.global_thread_id(ctx), - self.format_transaction_name(ctx, new_thread.transaction.name.clone()) - ); - self.next.push_back(new_thread); - } - } - - // Mark all suspended threads as ready for execution - // by setting `current` to `next`, and setting `next = []` - // (the latter is done via `std::mem::take`) - self.current = std::mem::take(&mut self.next); - self.cycle_count += 1; - self.interpreter.trace_cycle_count += 1; - - // if ctx.show_waveform_time { - // let time_str = trace.format_time(trace.time_step()); - // info!("Advancing to time {}, setting current = next", time_str); - // } else { - // info!( - // "Advancing to cycle {}, setting current = next", - // self.cycle_count - // ); - // } - } - - /// Marks the trace as having ended - /// (This function is used by the `GlobalScheduler` when we reach - /// the end of the trace) - pub fn mark_trace_ended(&mut self) { - self.trace_ended = true; - } - - /// Helper function that emits an error (and terminates the monitor with - /// non-zero exit code). The caller should only call this function - /// when it is determined that no transactions match the provided waveform. - pub fn emit_error(&self, trace: &WaveSignalTrace, ctx: &GlobalContext) -> anyhow::Result<()> { - self.print_step_count(ctx); - let time_str = if ctx.show_waveform_time { - trace.format_time(trace.time_step()) - } else { - format!("cycle {}", self.interpreter.trace_cycle_count) - }; - - let error_msg = anyhow!( - "Failure at {}: No transactions match the waveform in `{}`.\nPossible transactions: [{}]", - time_str, - ctx.waveform_file, - self.possible_transactions - .iter() - .map(|tr| tr.name.clone()) - .collect::>() - .join(", ") - ); - Err(error_msg) - } - - /// Helper function which handles `repeat` loops by forking two threads: - /// - One which exits the loop with the `LoopArg` set to `Known(n)` - /// - One which speculatively executes the loop body for another iteration, - /// with the `LoopArg` set to `Speculative(n + 1)` - /// - /// The arguments to this function are: - /// - The `SymbolId` / `StmtId`s of the `LoopArg`, loop body and the - /// entire loop statement itself - /// - The `current_thread` (which will speculatively execute the loop body - /// for another iteration) - /// - The value `n` that has been currently "guessed" for the `LoopArg` - /// - /// This function returns a `ThreadResult::RepeatLoopFork` containing the - /// two threads. - fn handle_repeat_loops( - &mut self, - loop_arg_symbol_id: SymbolId, - loop_body_id: StmtId, - loop_stmt_id: StmtId, - mut current_thread: Thread, - n: u64, - ) -> ThreadResult { - repeat_info!( - "Thread {} (`{}`): RepeatLoop fork at cycle {} — spawning exited_thread (Thread {}, Known({})) and speculative_thread (Thread {}, Speculative({}))", - current_thread.thread_id, - current_thread.transaction.name, - self.cycle_count, - self.num_threads, - n, - current_thread.thread_id, - n + 1 - ); - // Create a new thread `exited_thread` that is identical - // to the current thread, but it exits the loop - // with the `LoopArg` set to `Known(n)` - let mut exited_thread = current_thread.clone(); - exited_thread.thread_id = self.num_threads; - self.num_threads += 1; - exited_thread - .loop_args_state - .insert(loop_arg_symbol_id, LoopArgState::Known(n)); - - // Also add the `loop_arg` to the `exited_thread`'s - // `args_mapping` and `known_bits` map. - // (The `loop_arg` is an input - // parameter, so other statements in the protocol - // can still refer to it) - let loop_arg_bitwidth = 64; // TODO: simplify this code since we will just treat uint as 64-bit - exited_thread.args_mapping.insert( - loop_arg_symbol_id, - BitVecValue::from_u64(n, loop_arg_bitwidth), - ); - exited_thread - .known_bits - .insert(loop_arg_symbol_id, BitVecValue::ones(loop_arg_bitwidth)); - - repeat_info!( - "Exited thread ({}, `{}`) has args_mapping {}\n", - exited_thread.thread_id, - exited_thread.transaction.name, - serialize_monitor_args_mapping( - &exited_thread.args_mapping, - &exited_thread.symbol_table, - false - ) - ); - - // The exited_thread needs to execute the first statement - // that immediately follow the loop - exited_thread.current_stmt_id = self.interpreter.next_stmt_map[&loop_stmt_id].expect( - "Repeat loops can't be the last statement in a protocol since protocols always end with `step`" - ); - - // Update the current thread's `loop_args` map so that - // the `LoopArg` is now `Speculative(n + 1)` - current_thread.loop_args_state.insert( - loop_arg_symbol_id, - LoopArgState::Speculative(n + 1, loop_stmt_id), - ); - - // The current thread executes the - // loop body for another iteration speculatively - current_thread.current_stmt_id = loop_body_id; - - // Let the global scheduler deal with both threads - // (The current thread is called the `speculative_thread`, - // since it speculatively executes the loop body again - // with the `LoopArg` set to `Speculative(n + 1)`) - ThreadResult::RepeatLoopFork { - exited_thread: Box::new(exited_thread), - speculative_thread: Box::new(current_thread), - } - } - - /// Keeps running a `thread` until: - /// - It reaches the next `step()` or `fork()` statement - /// - It completes succesfully - /// - An error was encountered during execution - pub fn run_thread_till_next_step( - &mut self, - mut thread: Thread, - trace: &WaveSignalTrace, - ctx: &GlobalContext, - ) -> Result { - // info!( - // "Running thread {} (transaction `{}`) till next `step()`...", - // thread.global_thread_id(ctx), - // self.format_transaction_name(ctx, thread.transaction.name.clone()) - // ); - - // Perform a context switch (use the argument thread's `Transaction` - // & associated `SymbolTable` / `NextStmtMap`) - self.interpreter.context_switch(&thread); - - let mut current_stmt_id = thread.current_stmt_id; - - loop { - // Intercept repeat loops before evaluating statements - if let Stmt::RepeatLoop(loop_arg_expr_id, loop_body_id) = - thread.transaction[current_stmt_id] - { - let loop_stmt_id = current_stmt_id; - let loop_arg_symbol_id = match thread.transaction[loop_arg_expr_id] { - Expr::Sym(symbol_id) => symbol_id, - Expr::Const(_) => { - todo!("Maybe allow constants to appear as arguments to repeat loops??") - } - _ => { - unreachable!("Arguments to repeat loops are always SymbolIDs") - } - }; - - // Suppose we already know how many iterations a `repeat` loop - // must take. If so, we execute it deterministically. - // This situation occurs if there are multiple `repeat` loops - // in a protocol that use the same `LoopArg`, e.g. - // `repeat n iterations { ... }; ...; repeat n iterations { ... }` - if let Some(num_remaining_iters) = - thread.repeat_loops_remaining_iters.get_mut(&loop_stmt_id) - { - *num_remaining_iters -= 1; - if *num_remaining_iters == 0 { - repeat_info!( - "Thread {}: repeat_loops_remaining_iters hit 0, exiting loop", - thread.thread_id - ); - thread.repeat_loops_remaining_iters.remove(&loop_stmt_id); - current_stmt_id = self.interpreter.next_stmt_map[&loop_stmt_id].expect( - "Repeat loops can't be the last statement in a protocol since protocols always end with `step()`" - ); - } else { - repeat_info!( - "Thread {}: repeat_loops_remaining_iters = {}, re-entering loop body", - thread.thread_id, - *num_remaining_iters - ); - current_stmt_id = loop_body_id; - } - continue; - } - - // Handle case where the loop argument is already in the thread's - // `args_mapping` (e.g. a value for it has already been - // inferred, via a previous assignment) - if !thread.loop_args_state.contains_key(&loop_arg_symbol_id) - && let Some(loop_arg) = thread.args_mapping.get(&loop_arg_symbol_id) - { - let n = loop_arg.to_u64().unwrap_or_else(|| { - panic!("Unable to convert {} to u64", loop_arg.to_bit_str()) - }); - thread - .loop_args_state - .insert(loop_arg_symbol_id, LoopArgState::Known(n)); - } - - // Now we need to handle the case when the value of a `LoopArg` - // is unknown - match thread.loop_args_state.get(&loop_arg_symbol_id).cloned() { - None => { - // First time seeing loop arg, it is `Unknown` - // (i.e. absent from the thread's `loop_args_state` map), - // so pass in `n = 0` to the `handle_repeat_loops` - // helper function - repeat_info!( - "Thread {}: First encounter of repeat loop (loop_arg `{}`), calling handle_repeat_loops(n=0)", - thread.thread_id, - thread.symbol_table[loop_arg_symbol_id].name() - ); - return Ok(self.handle_repeat_loops( - loop_arg_symbol_id, - loop_body_id, - loop_stmt_id, - thread, - 0, - )); - } - Some(LoopArgState::Speculative(n, stored_loop_stmt_id)) => { - // We disallow nested `repeat` loops that use the - // same loop argument, i.e. we forbid - // `repeat n iterations { repeat n iterations { ... } ... }` - if loop_stmt_id != stored_loop_stmt_id { - panic!( - "Nested `repeat` loops that use the same loop argument `{}` are forbidden", - thread.symbol_table[loop_arg_symbol_id].name() - ) - } - - repeat_info!( - "Thread {}: Speculative({}), calling handle_repeat_loops(n={})", - thread.thread_id, - n, - n - ); - // Fork two threads: - // one with `Known(n)`, one with `Speculative(n + 1)` - return Ok(self.handle_repeat_loops( - loop_arg_symbol_id, - loop_body_id, - loop_stmt_id, - thread, - n, - )); - } - Some(LoopArgState::Known(n)) => { - // Value of `n` has been resolved from a prior loop - // (either with the same `StmtId` or a different `StmtId`) - if n == 0 { - repeat_info!( - "Thread {}: Known(0) — skipping loop body entirely (0 iterations, no step() called inside loop)", - thread.thread_id - ); - // Exit the loop since the `LoopArg` is already known, - // proceed to the next immediate statement - // (evaluated in the next iteration - // of the outer `loop` in this function) - current_stmt_id = self.interpreter.next_stmt_map[&loop_stmt_id].expect( - "Repeat loops can't be the last statement in a protocol since protocols always end with `step()`" - ); - } else { - repeat_info!( - "Thread {}: Known({}) — executing {} iteration(s) of loop body", - thread.thread_id, - n, - n - ); - // Insert it into the thread's `repeat_loops_remaining_iters` - // map, which tracks how many iterations need to be executed - // for this loop - thread.repeat_loops_remaining_iters.insert(loop_stmt_id, n); - current_stmt_id = loop_body_id; - } - continue; - } - } - } - match self.interpreter.evaluate_stmt(¤t_stmt_id, ctx, trace) { - Ok(Some(next_stmt_id)) => { - // Update thread-local maps - // to be the resultant maps in the interpreter - thread.args_mapping = self.interpreter.args_mapping.clone(); - thread.known_bits = self.interpreter.known_bits.clone(); - thread.constraints = self.interpreter.constraints.clone(); - - // Check whether the next statement is `Step` or `Fork` - // This determines if we need to move threads to/from different queues - match thread.transaction[next_stmt_id] { - Stmt::Step => { - // If the current statement itself is a `fork()`, - // it means this thread started directly at the fork - // (e.g. `exited_thread` from `handle_repeat_loops`, i.e. - // the thread that exits the `repeat_loop` - // with `loop_arg = Known(n)` set to some `n`). - // We need to handle the fork (by returning `ExplicitFork` early) - // before moving the current thread - // to the `next` queue, but only if no other threads from the same - // start cycle have already forked this cycle (to avoid duplicates) - if matches!(thread.transaction[current_stmt_id], Stmt::Fork) { - thread.has_forked = true; - let already_forked = - self.forked_start_cycles.contains(&thread.start_cycle); - if !already_forked { - self.forked_start_cycles.insert(thread.start_cycle); - thread.current_stmt_id = next_stmt_id; - return Ok(ThreadResult::ExplicitFork { - parent: Box::new(thread), - }); - } - // If another thread from the same start cycle, - // has already forked in this cycle, - // we just fall through to the normal Step logic below - } - - // if the thread is moving to the `next` queue, - // its `current_stmt_id` is updated to be `next_stmt_id` - thread.current_stmt_id = next_stmt_id; - self.next.push_back(thread); - // self.print_scheduler_state(trace, ctx); - return Ok(ThreadResult::Completed); - } - Stmt::Fork => { - thread.has_forked = true; - - // Check if another thread from the same start cycle has already forked - // in the current cycle for this scheduler. - // If so, skip the fork to avoid creating duplicate threads. - let already_forked = - self.forked_start_cycles.contains(&thread.start_cycle); - - if already_forked { - // info!( - // "Thread {} called `fork()`, but another thread from the same start cycle (cycle {}) already forked in this cycle. Skipping fork to avoid duplicates.", - // thread.global_thread_id(ctx), - // thread.start_cycle - // ); - // Continue from the fork statement onwards - current_stmt_id = next_stmt_id; - } else { - // Here, instead of creating a new thread for - // each possible protocol, we indicate to the - // caller that the current thread forked - - // Indicate that the thread's `start_cycle` - // called `fork` in the current cycle - self.forked_start_cycles.insert(thread.start_cycle); - - // Advance to next statement - thread.current_stmt_id = next_stmt_id; - - // Save the parent thread's state before we exit this function - thread.args_mapping = self.interpreter.args_mapping.clone(); - thread.known_bits = self.interpreter.known_bits.clone(); - thread.constraints = self.interpreter.constraints.clone(); - - // Indicate to the caller that this thread forked - return Ok(ThreadResult::ExplicitFork { - parent: Box::new(thread), - }); - } - } - _ => { - // Default case: update `current_stmt_id` - // to point to `next_stmt_id` - current_stmt_id = next_stmt_id; - } - } - } - Ok(None) => { - // Check if another thread has already finished in this cycle. - // Invariant: Only one thread per struct can finish per cycle - if let Some((first_start_cycle, first_thread_id, first_transaction_name)) = - &self.finished_thread - { - info!( - "Thread {} (`{}`) would have finished, but another thread (thread {} `{}` from start_cycle {}) already finished in this cycle. Marking as failed.", - thread.global_thread_id(ctx), - self.format_transaction_name(ctx, thread.transaction.name.clone()), - first_thread_id, - self.format_transaction_name(ctx, first_transaction_name.to_string()), - first_start_cycle - ); - self.failed.push_back(thread); - // self.print_scheduler_state(trace, ctx); - return Ok(ThreadResult::Completed); - } - - repeat_info!( - "Thread {} (`{}`) finished successfully at time {}, adding to `finished` queue", - thread.global_thread_id(ctx), - self.format_transaction_name(ctx, thread.transaction.name.clone()), - trace.format_time(trace.time_step()) - ); - - // Record this thread as having finished in this cycle - self.finished_thread = Some(( - thread.start_cycle, - thread.thread_id, - thread.transaction.name.clone(), - )); - - // Use the actual time-step from the waveform as the `end_time_step` - let end_time_step = trace.time_step(); - - // Construct a `ProtocolApplication` object - // from the current interpreter state - // (i.e. an entry in the monitor's output trace) - let struct_name = if ctx.multiple_structs { - Some(self.struct_name.clone()) - } else { - None - }; - let is_idle = self.interpreter.transaction.is_idle; - - let prot_app_opt = - self.interpreter - .to_protocol_application(struct_name, ctx, trace); - - if prot_app_opt.is_none() { - info!( - "Unable to construct protocol application for thread {} (`{}`), marking thread as failed", - thread.global_thread_id(ctx), - self.format_transaction_name(ctx, thread.transaction.name.clone()) - ); - self.failed.push_back(thread.clone()); - // self.print_scheduler_state(trace, ctx); - return Ok(ThreadResult::Completed); - } - - if is_idle { - info!( - "Transaction `{}` is marked as idle", - self.interpreter.transaction.name - ); - } - - repeat_info!( - "Thread {}: Pushing {} to output buffer", - thread.thread_id, - prot_app_opt - .clone() - .expect("Expected Some(ProtocolApplication)") - ); - - repeat_info!("next queue: {}", format_queue_compact(&self.next, ctx)); - - // Add the output entry + metadata to the scheduler's - // output buffer - self.output_buffer.push(AugmentedProtocolApplication { - end_cycle_count: self.cycle_count, - protocol_application: prot_app_opt - .expect("Expected Some(ProtocolApplication)"), - start_time_step: thread.start_time_step, - end_time_step, - thread_id: thread.global_thread_id(ctx), - is_idle, - }); - self.finished.push_back(thread.clone()); - - // Implicit fork: if this thread hasn't forked yet, - // indicate to the caller that an implicit fork - // needs to be performed. - // This handles the case where a protocol just ends in - // `step()` without having previously called `fork()` - if !thread.has_forked { - info!( - "Thread {} finished without explicit fork, performing implicit fork", - thread.global_thread_id(ctx) - ); - self.forked_start_cycles.insert(thread.start_cycle); - return Ok(ThreadResult::ImplicitFork); - } else { - return Ok(ThreadResult::Completed); - } - } - Err(err) => { - info!( - "Thread {} (`{}`) encountered `{}`, adding to `failed` queue", - thread.global_thread_id(ctx), - self.format_transaction_name(ctx, thread.transaction.name.clone()), - self.serialize_monitor_error(err, trace, ctx) - ); - self.failed.push_back(thread); - // self.print_scheduler_state(trace, ctx); - return Ok(ThreadResult::Completed); - } - } - } - } - - /// Helper function: out of all the protocols that were executed - /// successfully by the same scheduler - /// (i.e. are in the scheduler's `output_buffer`), this function - /// finds the maximum end-time (clock cycle) when a non-idle protocol finished - pub fn max_non_idle_end_cycle(&self) -> u32 { - self.output_buffer - .iter() - .filter(|e| !e.is_idle) - .map(|e| e.end_cycle_count) - .max() - .unwrap_or(0) - } - - /// Pretty-prints an error message for the monitor - /// (ExprIds/StmtIds are rendered with respect - /// to a `Transaction` and `SymbolTable` in which they reside). - /// Remarks: - /// - At the moment, this function only adds extra information for - /// the `ValueDisagreesWithTrace` error message (this was used for debugging - /// the monitor). Otherwise, it falls-back on the error's `Display` instance. - /// - We put this function here and not in `serialize.rs` of the - /// `protocols` crate, since it depends on some monitor-speciifc functionality - /// (e.g. whether to display the time of the error in time units or - /// in no. of cycles). - pub fn serialize_monitor_error( - &self, - err: ExecutionError, - trace: &WaveSignalTrace, - ctx: &GlobalContext, - ) -> String { - match err { - ExecutionError::Evaluation(EvaluationError::ValueDisagreesWithTrace { - expr_id: _, - value, - trace_value, - symbol_id, - symbol_name, - cycle_count, - }) => { - let time_str = if ctx.show_waveform_time { - trace.format_time(trace.time_step()) - } else { - format!("cycle {}", cycle_count) - }; - - format!( - "At {}: we expected {} ({}) to have value {}, but the trace value {} is different", - time_str, - symbol_name, - symbol_id, - serialize_bitvec(&value, false), - serialize_bitvec(&trace_value, false), - ) - } - _ => format!("{err}"), - } - } -} diff --git a/monitor/src/signal_trace.rs b/monitor/src/signal_trace.rs deleted file mode 100644 index ed2b2e03..00000000 --- a/monitor/src/signal_trace.rs +++ /dev/null @@ -1,407 +0,0 @@ -// Copyright 2025-26 Cornell University -// released under MIT License -// author: Kevin Laeufer -// author: Ernest Ng - -use crate::designs::Instance; -use anyhow::Context; -use baa::BitVecValue; -use protocols::frontend::Module; -use protocols::frontend::symbol::SymbolId; -use rand::SeedableRng; -use rustc_hash::FxHashMap; -use wellen::{Hierarchy, SignalEncoding, SignalRef}; - -/// The result of advancing the clock cycle by one step -#[derive(Debug)] -pub enum StepResult { - /// advance time by one step and there are values available for this step - Ok, - /// no more values available - Done, -} - -/// Provides a trace of signals that we can analyze. -pub trait SignalTrace { - /// Advance to the next time step - /// (This should map 1:1 to a `step` in the Protocol) - fn step(&mut self) -> StepResult; - - /// Returns value of a design input / output at the current step. - /// Returns `Err` if the `pin` doesn't exist in the port map - /// for the given instance. - fn get(&self, instance_id: u32, pin: SymbolId) -> anyhow::Result; -} - -/// The `WaveSamplingMode` determines how signals from a waveform are sampled -#[derive(Debug)] -#[allow(dead_code)] -pub enum WaveSamplingMode { - /// Sample on the rising edge of the signal, specified by its - /// signal identifier (a `SignalRef`) - RisingEdge(SignalRef), - /// Sample on the falling edge of the signal, specified by its - /// signal identifier (a `SignalRef`) - FallingEdge(SignalRef), - /// Interpret every time step as a new clock step. This generally only works - /// for waveforms produced by the Patronus simulator. - Direct, -} - -/// Waveform dump based implementation of a signal trace. -#[derive(Debug)] -#[allow(dead_code)] -pub struct WaveSignalTrace { - wave: wellen::simple::Waveform, - pub port_map: FxHashMap, - - /// The sampling mode to be used on the waveform - sampling_mode: WaveSamplingMode, - - /// The current (logical) `step()` in the Protocols specification - logical_step: u32, - - /// The actual clock time-step in the waveform - time_step: u32, - - /// An (optional) reference to the signal to treat as the clock signal - /// (to be sampled on every rising clockedge) - /// Note that this field is only `Some` if the user passes an argument - /// to the optional `--sample_posedge` CLI argument - clock_signal: Option, - - /// The time unit to use when formatting time values. - /// Note: we only support "ns" and "s" at the moment for simplicity. - time_unit: String, -} - -/// A `PortKey` is just a pair consisting of an `instance_id` and a `symbol_id` for a pin -#[derive(Debug, Copy, Clone, Hash, Eq, PartialEq)] -pub struct PortKey { - pub instance_id: u32, - pub pin_id: SymbolId, -} - -impl WaveSignalTrace { - /// Returns the actual clock time-step index in the waveform - pub fn time_step(&self) -> u32 { - self.time_step - } - - /// Returns the actual time value (in the waveform's time units) for a given time_step index - pub fn time_value(&self, time_step: u32) -> u64 { - self.wave.time_table()[time_step as usize] - } - - /// Formats a time value from the waveform using the configured time unit - pub fn format_time(&self, time_step: u32) -> String { - let time_value = self.time_value(time_step); - - // Convert raw time value to nanoseconds using the waveform's timescale. - const FS_PER_NS: f64 = 1_000_000.0; - let time_ns = if let Some(timescale) = self.wave.hierarchy().timescale() { - let fs_per_unit: f64 = match timescale.unit { - wellen::TimescaleUnit::FemtoSeconds => 1.0, - wellen::TimescaleUnit::PicoSeconds => 1_000.0, - wellen::TimescaleUnit::NanoSeconds => 1_000_000.0, - wellen::TimescaleUnit::MicroSeconds => 1_000_000_000.0, - wellen::TimescaleUnit::MilliSeconds => 1_000_000_000_000.0, - wellen::TimescaleUnit::Seconds => 1_000_000_000_000_000.0, - _ => 1.0, - }; - (time_value as f64) * (timescale.factor as f64) * fs_per_unit / FS_PER_NS - } else { - time_value as f64 - }; - - // Convert from ns to s if needed - let (time_out, unit_str) = match self.time_unit.as_str() { - "s" => (time_ns / 1_000_000_000.0, "s"), - _ => (time_ns, "ns"), - }; - - if (time_out - time_out.round()).abs() < 1e-10 { - format!("{}{}", time_out as u64, unit_str) - } else { - let formatted = format!("{:.3}", time_out); - let trimmed = formatted.trim_end_matches('0').trim_end_matches('.'); - format!("{}{}", trimmed, unit_str) - } - } - - /// Opens a waveform at the specified `filename` with the given - /// `Design`s and `Instance`s. The CLI arg `sample_posedge` is passed - /// as an argument to determine the `WaveSamplingMode` (whether it is - /// `Direct` or `RisingEdge`). - pub fn open( - filename: &impl AsRef, - modules: &[Module], - instances: &[Instance], - sample_posedge: Option, - time_unit: Option, - ) -> Result { - let mut wave = wellen::simple::read(filename)?; - - // find instances in the waveform hierarchy - let (port_map, clock_signal) = - find_instances(wave.hierarchy(), modules, instances, sample_posedge); - - // Determine the sampling mode based on the vavlue received - // for `clock_signal`. Note: we only support `Direct` & `RisingEdge` - // for now (`FallingEdge` is currently unsupported). - let sampling_mode = if let Some(signal_ref) = clock_signal { - WaveSamplingMode::RisingEdge(signal_ref) - } else { - WaveSamplingMode::Direct - }; - - // load all relavant signal references into memory - let mut signals: Vec = port_map.values().cloned().collect(); - // Add clock signal if present - if let Some(clk_sig) = clock_signal { - signals.push(clk_sig); - } - signals.sort(); - signals.dedup(); - wave.load_signals(&signals); - - Ok(Self { - wave, - port_map, - sampling_mode, - - // At the beginning, zero `step()` calls have happened, - // so `logical_step` is initialized to 0 - logical_step: 0, - - // The waveform begins with `TimeIdx = 0` - time_step: 0, - - clock_signal, - - time_unit: time_unit.unwrap_or_else(|| "ns".to_string()), - }) - } - - /// Helper function that returns the string representation of a - /// `SignalValue` associated with a particular `SignalRef` - /// at a given `time_step` - fn get_value(&self, signal_ref: SignalRef, time_step: u32) -> String { - // Get the clock signal - let signal = self - .wave - .get_signal(signal_ref) - .unwrap_or_else(|| panic!("Unable to get signal for SignalRef {:?}", signal_ref)); - let offset = signal - .get_offset(time_step) - .unwrap_or_else(|| panic!("Unable to get offset for time_step {}", time_step)); - // Get the last value in the time step (this is to deal with delta cycles) - let value = signal.get_value_at(&offset, offset.elements - 1); - value - .to_bit_string() - .unwrap_or_else(|| panic!("Unable to convert {value} to bit-string")) - } -} - -/// Checks instances and returns a pair consisting of the (port map, optional clock signal) -/// (the latter is only `Some` if `sample_posedge` corresponds to a valid signal) -fn find_instances( - hierachy: &Hierarchy, - modules: &[Module], - instances: &[Instance], - sample_posedge: Option, -) -> (FxHashMap, Option) { - let mut port_map = FxHashMap::default(); - - let mut clock_signal: Option = None; - - for (inst_id, inst) in instances.iter().enumerate() { - // fetch the design from the hashmap (the design tells us what pins to expect) - let module = &modules[inst.module_id]; - - let inst_name_parts: Vec<&str> = inst.name.split('.').collect(); - if let Some(instance_scope) = hierachy.lookup_scope(&inst_name_parts) { - let instance_scope = &hierachy[instance_scope]; - - // for every pin designed in our struct, we have to find the correct - // variable that corresponds to it - for (field_idx, field) in module.pins.iter().enumerate() { - // find a variable that has a matching name - if let Some(var) = instance_scope - .vars(hierachy) - .find(|v| hierachy[*v].name(hierachy) == field.name()) - { - let waveform_bits = hierachy[var].length().expect("not a bit vector"); - - // Set up `sample_posedge` to - // refer to the clock signal (if one is specified) - if let Some(ref signal_name) = sample_posedge { - let clock_signal_parts: Vec<&str> = signal_name.split('.').collect(); - - // The clock signal should be in the same scope as the instance - // So we look it up directly in the instance_scope - match clock_signal_parts.last() { - Some(var_name) => { - if let Some(var) = instance_scope - .vars(hierachy) - .find(|v| hierachy[*v].name(hierachy) == *var_name) - { - let signal_ref = hierachy[var].signal_ref(); - clock_signal = Some(signal_ref); - } else { - // If not found in instance scope, use `lookup_var` - // (We exclude the final element from `clock_signal_parts`, - // since that is equal to `var_name`) - match hierachy.lookup_var( - &clock_signal_parts[..clock_signal_parts.len() - 1], - var_name, - ) { - Some(var_ref) => { - let signal_ref = hierachy[var_ref].signal_ref(); - clock_signal = Some(signal_ref); - } - None => { - panic!("Unable to find signal {var_name} in waveform") - } - } - } - } - None => panic!("Malformed signal {signal_name}"), - } - } - - // Check that bit widths match - assert_eq!( - waveform_bits, - field.bitwidth(), - "The bit-width of the waveform value is {}, which doesn't match expected width of {}, which is {}", - waveform_bits, - field.name(), - field.bitwidth() - ); - - // store a mapping from any SymbolId that refers to this pin - let value = hierachy[var].signal_ref(); - for syms in module.proto_pin_map.iter() { - let key = PortKey { - instance_id: inst_id as u32, - pin_id: syms[field_idx], - }; - port_map.insert(key, value); - } - } else { - // unable to find a variable whose name matches a pin - let available_vars: Vec<&str> = instance_scope - .vars(hierachy) - .map(|v| hierachy[v].name(hierachy)) - .collect(); - panic!( - "Failed to find pin {}. Available pins in waveform for instance {} are {}", - field.name(), - inst.name, - available_vars.join(",\n") - ); - } - } - } else { - panic!( - "Failed to find instance {}. First scope: {:#?}", - inst.name, - hierachy.first_scope().unwrap().full_name(hierachy) - ); - } - } - (port_map, clock_signal) -} - -impl SignalTrace for WaveSignalTrace { - /// Advance to the next time step - /// (This should map 1:1 to a `step` in the Protocol) - fn step(&mut self) -> StepResult { - // The no. of times we can call `step` is 1 less than the - // total no. of cycles available in the signal trace - let total_steps = (self.wave.time_table().len() - 1) as u32; - match self.sampling_mode { - // A `Direct` sampling mode means a `logical_step` maps 1:1 - // to a `time_step` in the waveform - WaveSamplingMode::Direct => { - // If we haven't reached the end of the waveform yet - // (i.e. if `self.logical_step < total_steps`) - // increment the `logical_step` & `time_step` together - if self.logical_step < total_steps { - self.logical_step += 1; - self.time_step += 1; - } - if self.logical_step == total_steps { - StepResult::Done - } else { - StepResult::Ok - } - } - // Sample on the next rising edge of `clock_signal_ref` - WaveSamplingMode::RisingEdge(clock_signal_ref) => { - // First, increment the logical step - self.logical_step += 1; - - let old_time = self.format_time(self.time_step); - - // Next, as long as the time-step is in bounds... - while self.time_step < total_steps { - // ...first fetch the current signal value before incrementing - let prev_value = self.get_value(clock_signal_ref, self.time_step); - - // Then, increment the `time_step`, and check whether - // the prevous value is 0 while the new value is 1 - // If yes, we have encountered a rising clock-edge - // and have found the new `time_step` for the waveform - self.time_step += 1; - let new_value = self.get_value(clock_signal_ref, self.time_step); - if prev_value == "0" && new_value == "1" { - let new_time = self.format_time(self.time_step); - info!("Advanced clock time from {old_time} -> {new_time}"); - - return StepResult::Ok; - } - } - // If we reach this point, we cannot increment the `time_step` - // any further, so we return `Done` to indicate that - // we've reached the end of the waveform - StepResult::Done - } - WaveSamplingMode::FallingEdge(_) => { - todo!("Handle WaveSamplingMode::FallingEdge when stepping WaveSignalTrace") - } - } - } - - /// Returns value of a design input / output at the current (logical) step. - /// Returns `Err` if the `pin` doesn't exist in the port map - /// for the given instance. - fn get(&self, instance_id: u32, pin: SymbolId) -> anyhow::Result { - let key = PortKey { - instance_id, - pin_id: pin, - }; - // Get the Wellen `SignalRef` (akin to `SignalId`) - let signal_ref = self - .port_map - .get(&key) - .with_context(|| format!("Key {:?} doesn't exist in port map", key))?; - - // Obtain the `SignalValue` at the current `time_step` - // (represented as a bit-string) - let bit_str = self.get_value(*signal_ref, self.time_step); - - Ok(BitVecValue::from_bit_str(&bit_str).unwrap_or_else(|_| { - // If the bit-string can't be converted into a BitVecValue - // (e.g. because the waveform contains "x"), generate - // a random value of the appropriate bit-width. - let bitwidth = match self.wave.hierarchy().get_signal_tpe(*signal_ref) { - Some(SignalEncoding::BitVector(width)) => width.get(), - _ => panic!("Expected a bit-vector signal for key {:?}", key), - }; - let mut rng = rand::rngs::SmallRng::seed_from_u64(0); - BitVecValue::random(&mut rng, bitwidth) - })) - } -} diff --git a/monitor/src/thread.rs b/monitor/src/thread.rs deleted file mode 100644 index b7cb219f..00000000 --- a/monitor/src/thread.rs +++ /dev/null @@ -1,145 +0,0 @@ -// Copyright 2025 Cornell University -// released under MIT License -// author: Ernest Ng - -use baa::BitVecValue; -use protocols::frontend::ast::{Protocol, StmtId}; -use protocols::frontend::serialize::serialize_stmt; -use protocols::frontend::symbol::{SymbolId, SymbolTable}; -use protocols::scheduler::NextStmtMap; -use rustc_hash::FxHashMap; - -use crate::global_context::GlobalContext; -use crate::types::LoopArgState; - -/// The local context associated with an individual thread, -/// storing information such as: -// - Which transaction are we currently running? -// - Where in the transaction are we currently at? (the `StmtId`) -// - A mutable map mapping variable names to their values (`args_mapping`) -#[derive(Debug, Clone)] -pub struct Thread { - /// Name of the scheduler/struct this thread belongs to - /// (Used to create globally unique thread identifiers in multi-struct mode) - pub scheduler_name: String, - - // The thread's ID (unique within this scheduler) - pub thread_id: u32, - - /// The logical scheduling cycle in which the thread was started - /// (This corresponds to the `logical_step` field in `WaveSignalTrace`, - /// i.e. the no. of logical `step()` calls encountered in the program - /// before this thread started) - pub start_cycle: u32, - - /// The actual clock time-step in the waveform - /// at which the thread began. (This corresponds to the `time_step` - /// field in `WaveSignalTrace`.) - pub start_time_step: u32, - - /// The `Transaction` that this `Thread` is running - pub transaction: Protocol, - - /// The `SymbolTable` associated with the `Transaction` - pub symbol_table: SymbolTable, - - /// The `NextStmtMap` associated with the `Transaction` - pub next_stmt_map: NextStmtMap, - - /// Map storing the inferred values for the input and output arguments - pub args_mapping: FxHashMap, - - /// Maps each `SymbolId` to a bit-string, - /// where the `i`-th bit is 1 if it is known & 0 otherwise - pub known_bits: FxHashMap, - - /// Constraints on DUT input port values that must hold after stepping - pub constraints: FxHashMap, - - /// The current statement in the `Transaction`, identified by its `StmtId` - pub current_stmt_id: StmtId, - - /// Maps arguments of `repeat` loops to their current "guessed" state - /// (either `Speculative` or `Known` -- see docs for the `LoopArgState` type) - pub loop_args_state: FxHashMap, - - /// Once the state of a `LoopArg` has been determined, we need to track - /// how many iterations remain to be executed -- this is most useful - /// if we have two loops that use the same `LoopArg`, e.g. - /// `repeat n iterations { ... }; ...; repeat n iterations { ...}`. - /// This map is populated lazily when we encounter each `repeat` loop - /// (see `Scheduler::run_thread_till_next_step`). - /// The `StmtId` key is the statement of the `repeat` loop. - pub repeat_loops_remaining_iters: FxHashMap, - - /// Determines if the thread has called `fork()` yet. Initialized to `false`. - /// Since well-formedness dicates that a protocol can only contain - /// at most one `fork()`, once this flag is set to `true`, - /// it remains `true` for the rest of the thread's execution. - pub has_forked: bool, -} - -/// Pretty-prints a `Thread` -impl std::fmt::Display for Thread { - fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { - write!( - f, - "THREAD {}: {{ Start cycle: {}, Transaction: `{}`, Current stmt: `{}` ({}) }}", - self.thread_id, - self.start_cycle, - self.transaction.name, - serialize_stmt(&self.transaction, &self.symbol_table, &self.current_stmt_id), - self.current_stmt_id - ) - } -} - -impl Thread { - /// Creates a new `Thread` given the following: - /// - a `scheduler_name` (the name of the corresponding struct) - /// - a `Transaction` - /// - a `SymbolTable` - /// - a `GlobalContext` - /// - a `thread_id` - /// - a `start_cycle` / `start_time_step` - /// This method also sets up the `args_mapping` - /// accordingly based on the pins' values at the beginning of the signal trace. - pub fn new( - scheduler_name: String, - transaction: Protocol, - symbol_table: SymbolTable, - next_stmt_map: NextStmtMap, - thread_id: u32, - start_cycle: u32, - start_time_step: u32, - ) -> Self { - Self { - scheduler_name, - thread_id, - transaction: transaction.clone(), - next_stmt_map, - args_mapping: FxHashMap::default(), - known_bits: FxHashMap::default(), - constraints: FxHashMap::default(), - symbol_table, - current_stmt_id: transaction.body, - start_cycle, - start_time_step, - has_forked: false, - loop_args_state: FxHashMap::default(), - repeat_loops_remaining_iters: FxHashMap::default(), - } - } - - /// Returns an ID for the thread that is unique across all schedulers. - /// If there are multiple structs, this function prefixes the thread ID with - /// the struct name (same as the scheduler name). Otherwise, - /// this functio just returns the regular thread ID. - pub fn global_thread_id(&self, ctx: &GlobalContext) -> String { - if ctx.multiple_structs { - format!("{}::{}", self.scheduler_name, self.thread_id) - } else { - format!("{}", self.thread_id) - } - } -} diff --git a/monitor/src/types.rs b/monitor/src/types.rs deleted file mode 100644 index d6757fab..00000000 --- a/monitor/src/types.rs +++ /dev/null @@ -1,220 +0,0 @@ -// Copyright 2026 Cornell University -// released under MIT License -// author: Ernest Ng - -/*! Miscellaneous type definitions for the monitor live in this file - */ - -use std::collections::VecDeque; -use std::fmt; -use std::ops::{Deref, DerefMut}; - -use protocols::frontend::ast::StmtId; - -use crate::scheduler::Scheduler; -use crate::thread::Thread; - -/// Represents a protocol application like `add(1, 2, 3)` which appears -/// in the protocol trace produced by the monitor. -/// (We can't use the name `Transaction` for this type as it is already -/// used elsewhere in the codebase.) -#[derive(Clone, Debug, PartialEq, Eq, Hash)] -pub struct ProtocolApplication { - pub struct_name: Option, - pub protocol_name: String, - pub serialized_args: Vec, // already serialized -} - -impl fmt::Display for ProtocolApplication { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - if let Some(ref s) = self.struct_name { - write!(f, "{}::", s)?; - } - write!( - f, - "{}({})", - self.protocol_name, - self.serialized_args.join(", ") - ) - } -} - -/// A `Trace` is just an ordered sequence of `ProtocolApplication`s, e.g. -/// `add(1, 2, 3); add(4, 5, 9), ...]` -pub type Trace = Vec; - -/// An `AugmentedProtocolApplication` represents a singular `ProtocolApplication` -/// (an entry in the the transaction trace produced by the monitor, e.g. `add(1, 2, 3)`) -/// augmented with extra metadata (cycle count, start/end time, thread ID) -#[derive(Clone, Debug)] -pub struct AugmentedProtocolApplication { - /// The scheduling cycle in which the protocol finished - pub end_cycle_count: u32, - - /// A concrete protocol with concrete argument values - pub protocol_application: ProtocolApplication, - - /// The time-step at which the protocol began - pub start_time_step: u32, - - /// The time-step at which the protocol ended - pub end_time_step: u32, - - /// The ID of the thread that executed this protocol - pub thread_id: String, - - /// Whether this transaction was marked `#[idle]` in the protocol file. - /// Idle entries are excluded from the dedup key but still displayed. - pub is_idle: bool, -} - -/// An `AugmentedTrace` is just a wrapper over a vector of -/// `AugmentedProtocolApplication`s (intuitively, a trace is just an -/// ordered sequence of protocols). -/// We define `AugmentedTrace` as a tuple struct so that we can define -/// methods over this type. -#[derive(Clone, Debug, Default)] -pub struct AugmentedTrace(pub Vec); - -/// Allows us to call `iter()` directly on the `AugmentedTrace` type -impl Deref for AugmentedTrace { - type Target = Vec; - - fn deref(&self) -> &Self::Target { - &self.0 - } -} - -/// Allows us to use mutable `Vec` methods directly on the `AugmentedTrace` type -impl DerefMut for AugmentedTrace { - fn deref_mut(&mut self) -> &mut Self::Target { - &mut self.0 - } -} - -/// Allows us to call `into_iter()` directly on the `AugmentedTrace` type -/// (without needing to access the internal `Vec`) -impl IntoIterator for AugmentedTrace { - type Item = AugmentedProtocolApplication; - type IntoIter = std::vec::IntoIter; - - fn into_iter(self) -> Self::IntoIter { - self.0.into_iter() - } -} - -impl AugmentedTrace { - /// Helper function: takes a trace and computes the latest clock cycle - /// during which a non-idle protocol finished successfully. - pub fn max_non_idle_end_cycle(&self) -> u32 { - self.iter() - .filter(|entry| !entry.is_idle) - .map(|entry| entry.end_cycle_count) - .max() - .unwrap_or(0) - } -} - -/// Conceptually, a `SchedulerGroup` is the collection of -/// all schedulers corresponding to the same `struct` in our DSL, -/// where each scheduler represents a different possible protocol trace. -/// Practically, a `SchedulerGroup` is implemented as a queue (`VecDeque`) -/// of `Scheduler`s so that we can `push`/`pop` individual `Schedulers` -/// into/from this queue. -pub type SchedulerGroup = VecDeque; - -/// Error types that can occur during scheduler execution -#[derive(Debug)] -pub enum SchedulerError { - NoTransactionsMatch { - struct_name: String, - error_context: anyhow::Error, - }, - /// Other errors (e.g., internal errors, validation failures) - Other(anyhow::Error), -} - -impl From for SchedulerError { - fn from(err: anyhow::Error) -> Self { - SchedulerError::Other(err) - } -} - -/// The result of an individual `Thread` is one of four options: -/// - it `Completed` (was moved to one of the `next/finished/failed` queues) -/// - it forked explicitly (by calling `fork()`) (`ExplicitFork`) -/// - it forked implicitly at the end of a protocol (`ImplicitFork`) -/// - it forked after encountering a `repeat` loop (`RepeatLoopFork`) -#[derive(Debug)] -pub enum ThreadResult { - /// Thread completed (moved to next/finished/failed queue) - Completed, - - /// Thread encountered `fork`. The parent `Thread` is stored as an argument - /// to this constructor, with the `parent` `Thread`'s state updated to - /// it's post-`fork` state. - /// Note: We have to wrap the `Thread` in `Box`, otherwise - /// Clippy complains that there is a large size difference between different - /// constructors of this enum. - ExplicitFork { parent: Box }, - - /// Thread is already in the `finished` queue and forked implicitly - /// (e.g. this thread is a protocol which ends with `step` without - /// ever calling `fork`). The caller of a function which returns - /// this constructor is responsible for spawning new protocol - ImplicitFork, - - /// A fork that arises when learning the value of arguments to `repeat` loops - RepeatLoopFork { - /// The thread that exited the loop with the loop argument - /// set to `Known(n)` for some `n >= 0` - exited_thread: Box, - - /// The thread that remains in the loop and executed the loop body again, - /// with the loop argument set to `Speculative(n + 1)` - speculative_thread: Box, - }, -} - -/// The result of the *Scheduler* at the end of a cycle -#[derive(Debug)] -pub enum CycleResult { - Done, - Fork { - /// The thread that called fork - /// (Some for an explicit fork, None for implicit). - /// Note: We have to wrap the `Thread` in `Box`, otherwise - /// Clippy complains that there is a large size difference between different - /// constructors of this enum. - parent: Box>, - }, - /// A fork that arises when learning the value of arguments to `repeat` loops - RepeatLoopFork { - /// The thread that exited the loop with the loop argument - /// set to `Known(n)` for some `n >= 0` - exited_thread: Box, - - /// The thread that remains in the loop and executed the loop body again, - /// with the loop argument set to `Speculative(n + 1)` - speculative_thread: Box, - }, -} - -/// The possible states for an argument to a `repeat` loop. -/// We maintain the following invariants: -/// - `Speculative(n, loopID) `only becomes `Known(n)` after the corresponding -/// scheduler has executed the body of the loop at `loopID` exactly `n` -/// times (note that `n` can be 0). -/// - Once a `LoopArg` becomes Known, we proceed to the next statement -/// that immediately follows the loop (we don't enter the loop body). -/// - Moreover, once a `LoopArg` remains `Known`, it remains `Known` thereafter. -#[allow(dead_code)] -#[derive(Debug, Clone)] -pub enum LoopArgState { - /// `Speculative(n, loopID)` means the associated thread has already - /// *speculatively* executed the loop at `loopID` for `n` iterations. - /// (The `StmtId` is there to disambiguate between different loop statements, - /// since different loops can use the same loop argument `n`.) - Speculative(u64, StmtId), - Known(u64), -} diff --git a/protocols/src/errors.rs b/protocols/src/errors.rs index 0602967d..8b4ab6f2 100644 --- a/protocols/src/errors.rs +++ b/protocols/src/errors.rs @@ -75,7 +75,7 @@ pub enum EvaluationError { start: u32, end: u32, }, - /// (For monitor only) When the value of an expression on the RHS + /// (Trace comparison) When the value of an expression on the RHS /// of an assignment disagreess with the actual observed trace value ValueDisagreesWithTrace { expr_id: ExprId, @@ -85,7 +85,7 @@ pub enum EvaluationError { symbol_name: String, cycle_count: u32, }, - /// (For monitor only) When a constraint established by an assignment + /// (Trace comparison) When a constraint established by an assignment /// no longer holds after stepping to a new cycle ConstraintViolation { symbol_id: SymbolId, diff --git a/pyproject.toml b/pyproject.toml index 8a74c79c..83fd56f5 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -1,13 +1,10 @@ [project] name = "protocols" version = "0.1.0" -description = "Scripts for benchmarking the performance of the Protocols monitor" +description = "Scripts for generating the Protocols test catalog and Runt configs" readme = "README.md" requires-python = ">=3.12" -dependencies = [ - "matplotlib>=3.10.8", - "tqdm>=4.67.1", -] +dependencies = [] [dependency-groups] dev = [ diff --git a/runt/monitor/runt.toml b/runt/monitor/runt.toml deleted file mode 100644 index aee94652..00000000 --- a/runt/monitor/runt.toml +++ /dev/null @@ -1,1549 +0,0 @@ -ver = "0.4.1" - -[[tests]] -name = "monitor.tests_adders_add_d1.add_d1_monitor" -paths = [ - "../../tests/adders/add_d1.prot", -] -expect_dir = "../../tests/adders/expects" -expect_name = "add_d1.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/adders/add_d1.prot --wave tests/adders/add_d1.fst --instances add_d1:Adder 2>/dev/null" - -[[tests]] -name = "monitor.tests_adders_add_d2.add_d2_monitor" -paths = [ - "../../tests/adders/add_d2.prot", -] -expect_dir = "../../tests/adders/expects" -expect_name = "add_d2.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/adders/add_d2.prot --wave tests/adders/add_d2.fst --instances add_d2:Adder 2>/dev/null" - -[[tests]] -name = "monitor.tests_adders_add_var_cyc.add_var_cyc_monitor" -paths = [ - "../../tests/adders/add_var_cyc.prot", -] -expect_dir = "../../tests/adders/expects" -expect_name = "add_var_cyc.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/adders/add_var_cyc.prot --wave tests/adders/loop_with_assigns.fst --instances add_d1:Adder 2>/dev/null" - -[[tests]] -name = "monitor.tests_adders_busy_wait.busy_wait_monitor" -paths = [ - "../../tests/adders/busy_wait.prot", -] -expect_dir = "../../tests/adders/expects" -expect_name = "busy_wait.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/adders/busy_wait.prot --wave tests/adders/busy_wait.fst --instances add_d1:Adder 2>/dev/null" - -[[tests]] -name = "monitor.tests_adders_loop_with_assigns.loop_with_assigns_monitor" -paths = [ - "../../tests/adders/loop_with_assigns.prot", -] -expect_dir = "../../tests/adders/expects" -expect_name = "loop_with_assigns.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/adders/loop_with_assigns.prot --wave tests/adders/loop_with_assigns.fst --instances add_d1:Adder 2>/dev/null" - -[[tests]] -name = "monitor.tests_adders_nested_busy_wait.nested_busy_wait_monitor" -paths = [ - "../../tests/adders/nested_busy_wait.prot", -] -expect_dir = "../../tests/adders/expects" -expect_name = "nested_busy_wait.monitor.expect" -cmd = "cd ../.. && python3 -c 'import os, signal, subprocess, sys\np = subprocess.Popen(sys.argv[2:], start_new_session=True)\ntry:\n sys.exit(p.wait(timeout=float(sys.argv[1])))\nexcept subprocess.TimeoutExpired:\n os.killpg(p.pid, signal.SIGKILL)\n sys.exit(124)\n' 5 target/debug/protocols-monitor --protocol tests/adders/nested_busy_wait.prot --wave tests/adders/nested_busy_wait.fst --instances add_d1:Adder 2>/dev/null" - -[[tests]] -name = "monitor.tests_alus_alu_d1_monitor.alu_d1_monitor" -paths = [ - "../../tests/alus/alu_d1.monitor.prot", -] -expect_dir = "../../tests/alus/expects" -expect_name = "alu_d1.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/alus/alu_d1.monitor.prot --wave tests/alus/alu_d1.fst --instances alu_d1:ALU 2>/dev/null" - -[[tests]] -name = "monitor.tests_alus_alu_d2_monitor.alu_d2_monitor" -paths = [ - "../../tests/alus/alu_d2.monitor.prot", -] -expect_dir = "../../tests/alus/expects" -expect_name = "alu_d2.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/alus/alu_d2.monitor.prot --wave tests/alus/alu_d2.fst --instances alu_d2:ALU 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_fifo_classic_1_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/fifo_classic/expects" -expect_name = "test_fifo_classic_1.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_fifo_classic_2_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/fifo_classic/expects" -expect_name = "test_fifo_classic_2.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_fifo_classic_3_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/fifo_classic/expects" -expect_name = "test_fifo_classic_3.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_fifo_classic_4_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/fifo_classic/expects" -expect_name = "test_fifo_classic_4.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_fifo_classic_5_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/fifo_classic/expects" -expect_name = "test_fifo_classic_5.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_5.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_fifo_classic_6_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/fifo_classic/expects" -expect_name = "test_fifo_classic_6.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_6.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_fifo_classic_7_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/fifo_classic/expects" -expect_name = "test_fifo_classic_7.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_7.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_fifo_classic_8_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/fifo_classic/expects" -expect_name = "test_fifo_classic_8.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_fifo_constant_1_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/fifo_constant/expects" -expect_name = "test_fifo_constant_1.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_fifo_constant_2_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/fifo_constant/expects" -expect_name = "test_fifo_constant_2.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_fifo_constant_3_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/fifo_constant/expects" -expect_name = "test_fifo_constant_3.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_fifo_constant_4_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/fifo_constant/expects" -expect_name = "test_fifo_constant_4.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_fifo_constant_5_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/fifo_constant/expects" -expect_name = "test_fifo_constant_5.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_5.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_fifo_constant_6_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/fifo_constant/expects" -expect_name = "test_fifo_constant_6.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_6.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_fifo_constant_7_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/fifo_constant/expects" -expect_name = "test_fifo_constant_7.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_7.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_fifo_constant_8_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/fifo_constant/expects" -expect_name = "test_fifo_constant_8.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_classic_16_0_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_classic/expects" -expect_name = "test_sram_classic_16_0.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_16_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_classic_16_12_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_classic/expects" -expect_name = "test_sram_classic_16_12.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_16_12.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_classic_16_4_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_classic/expects" -expect_name = "test_sram_classic_16_4.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_16_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_classic_16_8_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_classic/expects" -expect_name = "test_sram_classic_16_8.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_16_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_classic_1_0_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_classic/expects" -expect_name = "test_sram_classic_1_0.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_1_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_classic_1_12_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_classic/expects" -expect_name = "test_sram_classic_1_12.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_1_12.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_classic_1_4_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_classic/expects" -expect_name = "test_sram_classic_1_4.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_1_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_classic_1_8_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_classic/expects" -expect_name = "test_sram_classic_1_8.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_1_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_classic_2_0_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_classic/expects" -expect_name = "test_sram_classic_2_0.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_2_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_classic_2_12_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_classic/expects" -expect_name = "test_sram_classic_2_12.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_2_12.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_classic_2_4_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_classic/expects" -expect_name = "test_sram_classic_2_4.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_2_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_classic_2_8_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_classic/expects" -expect_name = "test_sram_classic_2_8.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_2_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_classic_4_0_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_classic/expects" -expect_name = "test_sram_classic_4_0.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_4_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_classic_4_12_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_classic/expects" -expect_name = "test_sram_classic_4_12.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_4_12.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_classic_4_4_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_classic/expects" -expect_name = "test_sram_classic_4_4.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_4_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_classic_4_8_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_classic/expects" -expect_name = "test_sram_classic_4_8.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_4_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_classic_8_0_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_classic/expects" -expect_name = "test_sram_classic_8_0.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_8_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_classic_8_12_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_classic/expects" -expect_name = "test_sram_classic_8_12.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_8_12.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_classic_8_4_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_classic/expects" -expect_name = "test_sram_classic_8_4.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_8_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_classic_8_8_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_classic/expects" -expect_name = "test_sram_classic_8_8.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_8_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_0_0_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_16_0_0.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_0_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_0_1_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_16_0_1.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_0_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_0_2_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_16_0_2.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_0_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_0_3_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_16_0_3.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_0_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_12_0_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_16_12_0.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_12_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_12_1_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_16_12_1.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_12_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_12_2_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_16_12_2.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_12_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_12_3_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_16_12_3.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_12_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_4_0_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_16_4_0.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_4_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_4_1_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_16_4_1.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_4_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_4_2_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_16_4_2.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_4_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_4_3_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_16_4_3.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_4_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_8_0_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_16_8_0.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_8_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_8_1_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_16_8_1.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_8_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_8_2_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_16_8_2.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_8_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_8_3_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_16_8_3.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_8_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_0_0_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_1_0_0.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_0_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_0_1_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_1_0_1.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_0_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_0_2_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_1_0_2.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_0_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_0_3_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_1_0_3.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_0_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_12_0_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_1_12_0.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_12_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_12_1_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_1_12_1.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_12_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_12_2_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_1_12_2.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_12_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_12_3_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_1_12_3.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_12_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_4_0_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_1_4_0.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_4_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_4_1_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_1_4_1.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_4_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_4_2_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_1_4_2.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_4_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_4_3_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_1_4_3.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_4_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_8_0_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_1_8_0.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_8_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_8_1_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_1_8_1.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_8_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_8_2_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_1_8_2.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_8_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_8_3_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_1_8_3.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_8_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_0_0_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_2_0_0.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_0_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_0_1_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_2_0_1.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_0_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_0_2_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_2_0_2.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_0_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_0_3_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_2_0_3.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_0_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_12_0_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_2_12_0.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_12_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_12_1_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_2_12_1.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_12_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_12_2_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_2_12_2.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_12_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_12_3_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_2_12_3.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_12_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_4_0_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_2_4_0.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_4_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_4_1_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_2_4_1.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_4_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_4_2_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_2_4_2.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_4_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_4_3_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_2_4_3.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_4_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_8_0_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_2_8_0.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_8_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_8_1_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_2_8_1.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_8_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_8_2_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_2_8_2.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_8_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_8_3_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_2_8_3.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_8_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_0_0_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_4_0_0.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_0_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_0_1_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_4_0_1.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_0_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_0_2_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_4_0_2.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_0_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_0_3_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_4_0_3.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_0_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_12_0_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_4_12_0.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_12_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_12_1_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_4_12_1.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_12_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_12_2_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_4_12_2.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_12_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_12_3_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_4_12_3.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_12_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_4_0_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_4_4_0.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_4_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_4_1_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_4_4_1.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_4_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_4_2_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_4_4_2.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_4_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_4_3_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_4_4_3.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_4_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_8_0_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_4_8_0.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_8_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_8_1_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_4_8_1.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_8_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_8_2_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_4_8_2.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_8_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_8_3_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_4_8_3.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_8_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_0_0_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_8_0_0.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_0_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_0_1_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_8_0_1.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_0_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_0_2_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_8_0_2.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_0_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_0_3_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_8_0_3.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_0_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_12_0_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_8_12_0.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_12_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_12_1_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_8_12_1.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_12_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_12_2_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_8_12_2.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_12_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_12_3_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_8_12_3.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_12_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_4_0_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_8_4_0.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_4_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_4_1_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_8_4_1.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_4_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_4_2_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_8_4_2.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_4_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_4_3_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_8_4_3.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_4_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_8_0_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_8_8_0.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_8_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_8_1_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_8_8_1.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_8_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_8_2_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_8_8_2.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_8_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_8_3_monitor" -paths = [ - "../../tests/antmicro/wishbone_subordinate.prot", -] -expect_dir = "../../tests/antmicro/sram_incrementing/expects" -expect_name = "test_sram_incrementing_8_8_3.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_8_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_brave_new_world_francis_bit_truncation_fft.bit_truncation_fft_monitor" -paths = [ - "../../tests/brave_new_world_francis/bit_truncation_fft.prot", -] -expect_dir = "../../tests/brave_new_world_francis/expects" -expect_name = "bit_truncation_fft.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/brave_new_world_francis/bit_truncation_fft.prot --wave tests/brave_new_world_francis/bit_truncation_fft.fst --instances round11_rne_unsigned_fixed:BitTruncationFFT 2>/dev/null" - -[[tests]] -name = "monitor.tests_brave_new_world_francis_bit_truncation_sha.bit_truncation_sha_monitor" -paths = [ - "../../tests/brave_new_world_francis/bit_truncation_sha.prot", -] -expect_dir = "../../tests/brave_new_world_francis/expects" -expect_name = "bit_truncation_sha.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/brave_new_world_francis/bit_truncation_sha.prot --wave tests/brave_new_world_francis/bit_truncation_sha.fst --instances bit_truncation_sha_fixed:bit_truncation_sha 2>/dev/null" - -[[tests]] -name = "monitor.tests_brave_new_world_francis_ftu_sha.ftu_sha_monitor" -paths = [ - "../../tests/brave_new_world_francis/ftu_sha.prot", -] -expect_dir = "../../tests/brave_new_world_francis/expects" -expect_name = "ftu_sha.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/brave_new_world_francis/ftu_sha.prot --wave tests/brave_new_world_francis/ftu_sha.fst --instances fsm_update_fixed_gated:FailureToUpdateSHA 2>/dev/null" - -[[tests]] -name = "monitor.tests_brave_new_world_francis_signal_async.signal_async_monitor" -paths = [ - "../../tests/brave_new_world_francis/signal_async.prot", -] -expect_dir = "../../tests/brave_new_world_francis/expects" -expect_name = "signal_async.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/brave_new_world_francis/signal_async.prot --wave tests/brave_new_world_francis/signal_async.fst --instances signal_async_fix:SignalAsyncSpec 2>/dev/null" - -[[tests]] -name = "monitor.tests_brave_new_world_francis_use_without_valid.use_without_valid_monitor" -paths = [ - "../../tests/brave_new_world_francis/use_without_valid.prot", -] -expect_dir = "../../tests/brave_new_world_francis/expects" -expect_name = "use_without_valid.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/brave_new_world_francis/use_without_valid.prot --wave tests/brave_new_world_francis/use_without_valid.fst --instances use_without_valid_fix:UseWithoutValid 2>/dev/null" - -[[tests]] -name = "monitor.tests_ethmac_ethmac_wishbone_manager.ethmac_wishbone_manager_monitor" -paths = [ - "../../tests/ethmac/ethmac_wishbone_manager.prot", -] -expect_dir = "../../tests/ethmac/expects" -expect_name = "ethmac_wishbone_manager.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/ethmac/ethmac_wishbone_manager.prot --instances tb_ethernet:WBManager --sample-posedge tb_ethernet.wb_clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_ethmac_ethmac_wishbone_subordinate.ethmac_wishbone_subordinate_monitor" -paths = [ - "../../tests/ethmac/ethmac_wishbone_subordinate.prot", -] -expect_dir = "../../tests/ethmac/expects" -expect_name = "ethmac_wishbone_subordinate.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/ethmac/ethmac_wishbone_subordinate.prot --instances tb_ethernet:WBSubordinate --sample-posedge tb_ethernet.wb_clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_fifo_fifo_monitor.fifo_monitor" -paths = [ - "../../tests/fifo/fifo.monitor.prot", -] -expect_dir = "../../tests/fifo/expects" -expect_name = "fifo.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/fifo/fifo.monitor.prot --wave tests/fifo/fifo.fst --instances fifo_wrapper:Fifo 2>/dev/null" - -[[tests]] -name = "monitor.tests_fifo_push_pop_identity.push_pop_identity_monitor" -paths = [ - "../../tests/fifo/push_pop_identity.prot", -] -expect_dir = "../../tests/fifo/expects" -expect_name = "push_pop_identity.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/fifo/push_pop_identity.prot --wave tests/fifo/push_pop_identity.fst --instances fifo_wrapper:Fifo 2>/dev/null" - -[[tests]] -name = "monitor.tests_fifo_push_pop_loop_empty.push_pop_loop_empty_monitor" -paths = [ - "../../tests/fifo/push_pop_loop_empty.prot", -] -expect_dir = "../../tests/fifo/expects" -expect_name = "push_pop_loop_empty.monitor.expect" -cmd = "cd ../.. && python3 -c 'import os, signal, subprocess, sys\np = subprocess.Popen(sys.argv[2:], start_new_session=True)\ntry:\n sys.exit(p.wait(timeout=float(sys.argv[1])))\nexcept subprocess.TimeoutExpired:\n os.killpg(p.pid, signal.SIGKILL)\n sys.exit(124)\n' 5 target/debug/protocols-monitor --protocol tests/fifo/push_pop_loop_empty.prot --wave tests/fifo/push_pop_loop_empty.fst --instances fifo_wrapper:Fifo 2>/dev/null" - -[[tests]] -name = "monitor.tests_fifo_push_pop_loop_not_empty.push_pop_loop_not_empty_monitor" -paths = [ - "../../tests/fifo/push_pop_loop_not_empty.prot", -] -expect_dir = "../../tests/fifo/expects" -expect_name = "push_pop_loop_not_empty.monitor.expect" -cmd = "cd ../.. && python3 -c 'import os, signal, subprocess, sys\np = subprocess.Popen(sys.argv[2:], start_new_session=True)\ntry:\n sys.exit(p.wait(timeout=float(sys.argv[1])))\nexcept subprocess.TimeoutExpired:\n os.killpg(p.pid, signal.SIGKILL)\n sys.exit(124)\n' 5 target/debug/protocols-monitor --protocol tests/fifo/push_pop_loop_not_empty.prot --wave tests/fifo/push_pop_loop_not_empty.fst --instances fifo_wrapper:Fifo 2>/dev/null" - -[[tests]] -name = "monitor.tests_fpga_debugging_axi_burst_s4_s4_buggy.s4_buggy_monitor" -paths = [ - "../../tests/fpga-debugging/axi-burst-s4/s4_buggy.prot", -] -expect_dir = "../../tests/fpga-debugging/axi-burst-s4/expects" -expect_name = "s4_buggy.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/fpga-debugging/axi-burst-s4/s4_buggy.prot --wave tests/fpga-debugging/axi-burst-s4/s4_buggy.vcd --instances TOP.test_l2_cache_wait_state.axi_bus:WriteSubordinate --sample-posedge TOP.test_l2_cache_wait_state.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_fpga_debugging_axi_burst_s4_s4_fixed.s4_fixed_monitor" -paths = [ - "../../tests/fpga-debugging/axi-burst-s4/s4_fixed.prot", -] -expect_dir = "../../tests/fpga-debugging/axi-burst-s4/expects" -expect_name = "s4_fixed.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/fpga-debugging/axi-burst-s4/s4_fixed.prot --wave tests/fpga-debugging/axi-burst-s4/s4_fixed.vcd --instances TOP.test_l2_cache_wait_state.axi_bus:WriteSubordinate --sample-posedge TOP.test_l2_cache_wait_state.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_fpga_debugging_axi_lite_s1_s1_buggy.s1_buggy_monitor" -paths = [ - "../../tests/fpga-debugging/axi-lite-s1/s1_buggy.prot", -] -expect_dir = "../../tests/fpga-debugging/axi-lite-s1/expects" -expect_name = "s1_buggy.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/fpga-debugging/axi-lite-s1/s1_buggy.prot --wave tests/fpga-debugging/axi-lite-s1/s1_buggy_workload2.vcd --instances TOP.testbench.UUT:WriteSubordinate TOP.testbench.UUT:ReadSubordinate --sample-posedge TOP.testbench.UUT.S_AXI_ACLK --show-waveform-time --time-unit ns --include-idle 2>/dev/null" - -[[tests]] -name = "monitor.tests_fpga_debugging_axi_lite_s1_s1_buggy_workload_1.s1_buggy_workload_1_monitor" -paths = [ - "../../tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot", -] -expect_dir = "../../tests/fpga-debugging/axi-lite-s1/expects" -expect_name = "s1_buggy_workload_1.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot --wave tests/fpga-debugging/axi-lite-s1/s1_buggy_workload1.vcd --instances TOP.testbench.UUT:WriteSubordinate TOP.testbench.UUT:ReadSubordinate --sample-posedge TOP.testbench.UUT.S_AXI_ACLK --show-waveform-time --time-unit ns --include-idle 2>/dev/null" - -[[tests]] -name = "monitor.tests_fpga_debugging_axi_lite_s1_s1_fixed.s1_fixed_monitor" -paths = [ - "../../tests/fpga-debugging/axi-lite-s1/s1_fixed.prot", -] -expect_dir = "../../tests/fpga-debugging/axi-lite-s1/expects" -expect_name = "s1_fixed.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/fpga-debugging/axi-lite-s1/s1_fixed.prot --wave tests/fpga-debugging/axi-lite-s1/s1_fixed_workload2.vcd --instances TOP.testbench.UUT:WriteSubordinate TOP.testbench.UUT:ReadSubordinate --sample-posedge TOP.testbench.UUT.S_AXI_ACLK --show-waveform-time --time-unit ns --include-idle 2>/dev/null" - -[[tests]] -name = "monitor.tests_fpga_debugging_axi_lite_s1_s1_fixed_workload_1.s1_fixed_workload_1_monitor" -paths = [ - "../../tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot", -] -expect_dir = "../../tests/fpga-debugging/axi-lite-s1/expects" -expect_name = "s1_fixed_workload_1.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot --wave tests/fpga-debugging/axi-lite-s1/s1_fixed_workload1.vcd --instances TOP.testbench.UUT:WriteSubordinate TOP.testbench.UUT:ReadSubordinate --sample-posedge TOP.testbench.UUT.S_AXI_ACLK --show-waveform-time --time-unit ns --include-idle 2>/dev/null" - -[[tests]] -name = "monitor.tests_fpga_debugging_axi_stream_s2_s2_buggy.s2_buggy_monitor" -paths = [ - "../../tests/fpga-debugging/axi-stream-s2/s2_buggy.prot", -] -expect_dir = "../../tests/fpga-debugging/axi-stream-s2/expects" -expect_name = "s2_buggy.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/fpga-debugging/axi-stream-s2/s2_buggy.prot --wave tests/fpga-debugging/axi-stream-s2/s2_buggy.fst --instances TOP.testbench.UUT.axi_stream_check:AXISManager --sample-posedge TOP.testbench.UUT.axi_stream_check.i_aclk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_fpga_debugging_axi_stream_s2_s2_fixed.s2_fixed_monitor" -paths = [ - "../../tests/fpga-debugging/axi-stream-s2/s2_fixed.prot", -] -expect_dir = "../../tests/fpga-debugging/axi-stream-s2/expects" -expect_name = "s2_fixed.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/fpga-debugging/axi-stream-s2/s2_fixed.prot --wave tests/fpga-debugging/axi-stream-s2/s2_fixed.fst --instances TOP.testbench.UUT.axi_stream_check:AXISManager --sample-posedge TOP.testbench.UUT.axi_stream_check.i_aclk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_fpga_debugging_axis_adapter_s3_s3_buggy.s3_buggy_monitor" -paths = [ - "../../tests/fpga-debugging/axis-adapter-s3/s3_buggy.prot", -] -expect_dir = "../../tests/fpga-debugging/axis-adapter-s3/expects" -expect_name = "s3_buggy.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/fpga-debugging/axis-adapter-s3/s3_buggy.prot --wave tests/fpga-debugging/axis-adapter-s3/s3_buggy.fst --instances TOP.test_axis_adapter_64_8.UUT:AXISManager --sample-posedge TOP.test_axis_adapter_64_8.UUT.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_fpga_debugging_axis_adapter_s3_s3_fixed.s3_fixed_monitor" -paths = [ - "../../tests/fpga-debugging/axis-adapter-s3/s3_fixed.prot", -] -expect_dir = "../../tests/fpga-debugging/axis-adapter-s3/expects" -expect_name = "s3_fixed.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/fpga-debugging/axis-adapter-s3/s3_fixed.prot --wave tests/fpga-debugging/axis-adapter-s3/s3_fixed.fst --instances TOP.test_axis_adapter_64_8.UUT:AXISManager --sample-posedge TOP.test_axis_adapter_64_8.UUT.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_fpga_debugging_axis_async_fifo_c4_c4_buggy.c4_buggy_monitor" -paths = [ - "../../tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot", -] -expect_dir = "../../tests/fpga-debugging/axis-async-fifo-c4/expects" -expect_name = "c4_buggy.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot --wave tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.fst --instances TOP.test_axis_async_fifo.UUT.axis_reg_inst:Sender TOP.test_axis_async_fifo.UUT.axis_reg_inst:Receiver --sample-posedge TOP.test_axis_async_fifo.UUT.axis_reg_inst.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_fpga_debugging_axis_async_fifo_c4_c4_fixed.c4_fixed_monitor" -paths = [ - "../../tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.prot", -] -expect_dir = "../../tests/fpga-debugging/axis-async-fifo-c4/expects" -expect_name = "c4_fixed.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.prot --wave tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.fst --instances TOP.test_axis_async_fifo.UUT.axis_reg_inst:Sender TOP.test_axis_async_fifo.UUT.axis_reg_inst:Receiver --sample-posedge TOP.test_axis_async_fifo.UUT.axis_reg_inst.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_fpga_debugging_axis_fifo_d11_d11_buggy.d11_buggy_monitor" -paths = [ - "../../tests/fpga-debugging/axis-fifo-d11/d11_buggy.prot", -] -expect_dir = "../../tests/fpga-debugging/axis-fifo-d11/expects" -expect_name = "d11_buggy.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/fpga-debugging/axis-fifo-d11/d11_buggy.prot --wave tests/fpga-debugging/axis-fifo-d11/d11_buggy.fst --instances TOP.test_axis_fifo:AxisFifo --sample-posedge TOP.test_axis_fifo.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_fpga_debugging_axis_fifo_d11_d11_fixed.d11_fixed_monitor" -paths = [ - "../../tests/fpga-debugging/axis-fifo-d11/d11_fixed.prot", -] -expect_dir = "../../tests/fpga-debugging/axis-fifo-d11/expects" -expect_name = "d11_fixed.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/fpga-debugging/axis-fifo-d11/d11_fixed.prot --wave tests/fpga-debugging/axis-fifo-d11/d11_fixed.fst --instances TOP.test_axis_fifo:AxisFifo --sample-posedge TOP.test_axis_fifo.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_fpga_debugging_axis_fifo_d12_d12_buggy.d12_buggy_monitor" -paths = [ - "../../tests/fpga-debugging/axis-fifo-d12/d12_buggy.prot", -] -expect_dir = "../../tests/fpga-debugging/axis-fifo-d12/expects" -expect_name = "d12_buggy.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/fpga-debugging/axis-fifo-d12/d12_buggy.prot --wave tests/fpga-debugging/axis-fifo-d12/d12_buggy.fst --instances TOP.test_axis_fifo:AxisFifo --sample-posedge TOP.test_axis_fifo.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_fpga_debugging_axis_fifo_d12_d12_fixed.d12_fixed_monitor" -paths = [ - "../../tests/fpga-debugging/axis-fifo-d12/d12_fixed.prot", -] -expect_dir = "../../tests/fpga-debugging/axis-fifo-d12/expects" -expect_name = "d12_fixed.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/fpga-debugging/axis-fifo-d12/d12_fixed.prot --wave tests/fpga-debugging/axis-fifo-d12/d12_fixed.fst --instances TOP.test_axis_fifo:AxisFifo --sample-posedge TOP.test_axis_fifo.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_fpga_debugging_axis_fifo_d4_d4_buggy.d4_buggy_monitor" -paths = [ - "../../tests/fpga-debugging/axis-fifo-d4/d4_buggy.prot", -] -expect_dir = "../../tests/fpga-debugging/axis-fifo-d4/expects" -expect_name = "d4_buggy.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/fpga-debugging/axis-fifo-d4/d4_buggy.prot --wave tests/fpga-debugging/axis-fifo-d4/d4_buggy.fst --instances TOP.axis_fifo_wrapper.axis_fifo_inst:AxisFifo --sample-posedge TOP.axis_fifo_wrapper.axis_fifo_inst.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_fpga_debugging_axis_fifo_d4_d4_fixed.d4_fixed_monitor" -paths = [ - "../../tests/fpga-debugging/axis-fifo-d4/d4_fixed.prot", -] -expect_dir = "../../tests/fpga-debugging/axis-fifo-d4/expects" -expect_name = "d4_fixed.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/fpga-debugging/axis-fifo-d4/d4_fixed.prot --wave tests/fpga-debugging/axis-fifo-d4/d4_fixed.fst --instances TOP.axis_fifo_wrapper.axis_fifo_inst:AxisFifo --sample-posedge TOP.axis_fifo_wrapper.axis_fifo_inst.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_identities_identity_d1.identity_d1_monitor" -paths = [ - "../../tests/identities/identity_d1.prot", -] -expect_dir = "../../tests/identities/expects" -expect_name = "identity_d1.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/identities/identity_d1.prot --wave tests/identities/identity_d1.fst --instances identity_d1:Identity 2>/dev/null" - -[[tests]] -name = "monitor.tests_multi_multi0.multi0_monitor" -paths = [ - "../../tests/multi/multi0.prot", -] -expect_dir = "../../tests/multi/expects" -expect_name = "multi0.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/multi/multi0.prot --wave tests/multi/multi0.fst --instances multi0:multi0 2>/dev/null" - -[[tests]] -name = "monitor.tests_multi_multi0keep.multi0keep_monitor" -paths = [ - "../../tests/multi/multi0keep.prot", -] -expect_dir = "../../tests/multi/expects" -expect_name = "multi0keep.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/multi/multi0keep.prot --wave tests/multi/multi0keep.fst --instances multi0keep:multi0keep 2>/dev/null" - -[[tests]] -name = "monitor.tests_multi_multi0keep2const.multi0keep2const_monitor" -paths = [ - "../../tests/multi/multi0keep2const.prot", -] -expect_dir = "../../tests/multi/expects" -expect_name = "multi0keep2const.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/multi/multi0keep2const.prot --wave tests/multi/multi0keep2const.fst --instances multi0keep2const:multi0keep2const 2>/dev/null" - -[[tests]] -name = "monitor.tests_multi_multi2const.multi2const_monitor" -paths = [ - "../../tests/multi/multi2const.prot", -] -expect_dir = "../../tests/multi/expects" -expect_name = "multi2const.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/multi/multi2const.prot --wave tests/multi/multi2const.fst --instances multi2const:multi2const 2>/dev/null" - -[[tests]] -name = "monitor.tests_multi_multi2multi.multi2multi_monitor" -paths = [ - "../../tests/multi/multi2multi.prot", -] -expect_dir = "../../tests/multi/expects" -expect_name = "multi2multi.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/multi/multi2multi.prot --wave tests/multi/multi2multi.fst --instances multi2multi:multi2multi 2>/dev/null" - -[[tests]] -name = "monitor.tests_multi_multi_data.multi_data_monitor" -paths = [ - "../../tests/multi/multi_data.prot", -] -expect_dir = "../../tests/multi/expects" -expect_name = "multi_data.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/multi/multi_data.prot --wave tests/multi/multi_data.fst --instances multi_data:multi_data 2>/dev/null" - -[[tests]] -name = "monitor.tests_multipliers_mult_d2.mult_d2_monitor" -paths = [ - "../../tests/multipliers/mult_d2.prot", -] -expect_dir = "../../tests/multipliers/expects" -expect_name = "mult_d2.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/multipliers/mult_d2.prot --wave tests/multipliers/mult_d2.fst --instances mult_d2:Multiplier 2>/dev/null" - -[[tests]] -name = "monitor.tests_picorv32_pcpi_mul_unsigned_mul.pcpi_mul_unsigned_mul_monitor" -paths = [ - "../../tests/picorv32/pcpi_mul_unsigned_mul.prot", -] -expect_dir = "../../tests/picorv32/expects" -expect_name = "pcpi_mul_unsigned_mul.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/picorv32/pcpi_mul_unsigned_mul.prot --wave tests/picorv32/unsigned_mul.fst --instances picorv32_pcpi_mul:picorv32_pcpi_mul 2>/dev/null" - -[[tests]] -name = "monitor.tests_serv_serv_regfile.serv_regfile_monitor" -paths = [ - "../../tests/serv/serv_regfile.prot", -] -expect_dir = "../../tests/serv/expects" -expect_name = "serv_regfile.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/serv/serv_regfile.prot --wave tests/serv/serv_regfile.fst --instances serv_regfile:Regfile --display-hex 2>/dev/null" - -[[tests]] -name = "monitor.tests_tinyaes128_aes128.aes128_monitor" -paths = [ - "../../tests/tinyaes128/aes128.prot", -] -expect_dir = "../../tests/tinyaes128/expects" -expect_name = "aes128.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/tinyaes128/aes128.prot --wave tests/tinyaes128/aes128.fst --instances aes_128:TinyAES128 --display-hex 2>/dev/null" - -[[tests]] -name = "monitor.tests_wal_advanced_axis.axis_monitor" -paths = [ - "../../tests/wal/advanced/axis.prot", -] -expect_dir = "../../tests/wal/advanced/expects" -expect_name = "axis.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/wal/advanced/axis.prot --wave tests/wal/advanced/uart-axi.fst --instances uut_rx:AXIS --sample-posedge uut_rx.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_wal_advanced_axis_failing.axis_failing_monitor" -paths = [ - "../../tests/wal/advanced/axis_failing.prot", -] -expect_dir = "../../tests/wal/advanced/expects" -expect_name = "axis_failing.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/wal/advanced/axis_failing.prot --wave tests/wal/advanced/uart-axi-minimal.fst --instances uut_rx:AXIS --sample-posedge uut_rx.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_wal_advanced_axis_minimal.axis_minimal_monitor" -paths = [ - "../../tests/wal/advanced/axis_minimal.prot", -] -expect_dir = "../../tests/wal/advanced/expects" -expect_name = "axis_minimal.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/wal/advanced/axis_minimal.prot --wave tests/wal/advanced/uart-axi-minimal.fst --instances uut_rx:AXIS --sample-posedge uut_rx.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_wal_advanced_axis_truncated.axis_truncated_monitor" -paths = [ - "../../tests/wal/advanced/axis_truncated.prot", -] -expect_dir = "../../tests/wal/advanced/expects" -expect_name = "axis_truncated.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/wal/advanced/axis_truncated.prot --wave tests/wal/advanced/uart-axi-truncated.fst --instances uut_rx:AXIS --sample-posedge uut_rx.clk --show-waveform-time --time-unit ns 2>/dev/null" - -[[tests]] -name = "monitor.tests_wal_advanced_axis_truncated_include_idle.axis_truncated_include_idle_monitor" -paths = [ - "../../tests/wal/advanced/axis_truncated_include_idle.prot", -] -expect_dir = "../../tests/wal/advanced/expects" -expect_name = "axis_truncated_include_idle.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/wal/advanced/axis_truncated_include_idle.prot --wave tests/wal/advanced/uart-axi-truncated.fst --instances uut_rx:AXIS --sample-posedge uut_rx.clk --show-waveform-time --time-unit ns --include-idle 2>/dev/null" - -[[tests]] -name = "monitor.tests_wb_intercon_wb_arb.wb_arb_monitor" -paths = [ - "../../tests/wb_intercon/wb_arb.prot", -] -expect_dir = "../../tests/wb_intercon/expects" -expect_name = "wb_arb.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/wb_intercon/wb_arb.prot --instances wb_intercon_tb.wb_arb_tb:WBSubordinate --max-steps 1000 --sample-posedge wb_intercon_tb.wb_arb_tb.wb_clk --show-waveform-time --time-unit s 2>/dev/null" - -[[tests]] -name = "monitor.tests_wb_intercon_wb_cdc.wb_cdc_monitor" -paths = [ - "../../tests/wb_intercon/wb_cdc.prot", -] -expect_dir = "../../tests/wb_intercon/expects" -expect_name = "wb_cdc.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/wb_intercon/wb_cdc.prot --wave tests/wb_intercon/wb_cdc.fst --instances wb_intercon_tb.wb_cdc_tb.dut:WBSubordinate --max-steps 1000 --sample-posedge wb_intercon_tb.wb_cdc_tb.dut.wbm_clk --show-waveform-time --time-unit s 2>/dev/null" - -[[tests]] -name = "monitor.tests_wishbone_wishbone_monitor.wishbone_monitor" -paths = [ - "../../tests/wishbone/wishbone.monitor.prot", -] -expect_dir = "../../tests/wishbone/expects" -expect_name = "wishbone.monitor.expect" -cmd = "cd ../.. && target/debug/protocols-monitor --protocol tests/wishbone/wishbone.monitor.prot --wave tests/wishbone/reqwalker.vcd --instances TOP.reqwalker:WBSubordinate --sample-posedge TOP.reqwalker.i_clk 2>/dev/null" diff --git a/scripts/benchmark_monitor.py b/scripts/benchmark_monitor.py deleted file mode 100644 index 9b90fd72..00000000 --- a/scripts/benchmark_monitor.py +++ /dev/null @@ -1,176 +0,0 @@ -#!/usr/bin/env python3 -""" -Benchmarks the monitor on a range of test files using Hyperfine -(measuring CPU wall-clock time, averaged over 10 runs) and -creates a CSV with the results. -""" - -# Note: before running this script, first run -# `cargo build --release --package protocols-monitor` - -import csv -import json -import os -import re -import subprocess -import sys -from pathlib import Path - -from tqdm import tqdm - -sys.path.insert(0, str(Path(__file__).resolve().parent)) -import test_catalog # noqa: E402 - -OUTPUT_CSV = "benchmark_results/benchmark_results.csv" - - -def main(): - cases = sorted( - ( - { - "id": case_id, - "path": c["protocol"], - "wave": c.get("wave"), - "instances": c.get("instances", ()), - "extra_args": c.get("extra_args", ()), - } - for case_id, c in test_catalog.MONITOR_CASES.items() - ), - key=lambda case: (case["path"], case["id"]), - ) - - if not cases: - print("No monitor cases found in scripts/test_catalog.py") - return - - rows = [] - - for case in tqdm(cases, desc="Benchmarking", unit="case"): - # By default, Hyperfine executes the monitor for at least 10 - # times on each test file - cmd = [ - "hyperfine", - # Disable shell startup to avoid noise in measurements - "--shell=none", - "--export-json", - "tmp_hyperfine.json", - # Five warmup runs to run benchmarks on warm cache & avoid - # outliers between runs - "--warmup", - "5", - # Suppress hyperfine output (results are checked separately) - "--style", - "none", - # Ignore non-zero exit codes (some tests are expected to fail) - "--ignore-failure", - # Run the monitor directly on the catalog case. - " ".join(monitor_command(case)), - ] - - # Suppress monitor output to avoid measurement overhead - subprocess.run( - cmd, check=True, stdout=subprocess.DEVNULL, stderr=subprocess.DEVNULL - ) - - # Load hyperfine JSON - with open("tmp_hyperfine.json") as f: - data = json.load(f) - - result = data["results"][0] - mean_time = result["mean"] - stddev = result["stddev"] - min_time = result["min"] - max_time = result["max"] - - # Read the number of steps from the .prof file - prof_file = profile_path(case) - if not os.path.exists(prof_file): - # Skip tests without .prof files (e.g., tests expected to fail) - continue - - # Parse lines beginning with "No. of steps taken..." and extract the integer - # Example: "No. of steps taken by AxisFifo scheduler: 74" -> 74 - num_steps = None - pattern = re.compile(r"^No\. of steps taken.*:\s*(\d+)") - - with open(prof_file) as f: - for line in f: - match = pattern.match(line) - if match: - num_steps = int(match.group(1)) - break # Use the first matching line - - if num_steps is None: - # Skip if no step count found - continue - - # Normalize times by number of steps - mean_time_per_step = mean_time / num_steps - stddev_per_step = stddev / num_steps - min_time_per_step = min_time / num_steps - max_time_per_step = max_time / num_steps - - # Compute throughput (steps per second) - steps_per_sec = 1.0 / mean_time_per_step - - base = os.path.basename(case["path"]) - if base.endswith(".prot"): - base = base[:-5] # strip .prot - - rows.append( - [ - case["path"], - base, - num_steps, - mean_time_per_step, - stddev_per_step, - min_time_per_step, - max_time_per_step, - steps_per_sec, - ] - ) - - # ---- Write CSV ---- - os.makedirs(os.path.dirname(OUTPUT_CSV), exist_ok=True) - with open(OUTPUT_CSV, "w", newline="") as f: - writer = csv.writer(f) - writer.writerow( - [ - "file_path", - "test_name", - "num_steps", - "mean_per_step", - "stddev_per_step", - "min_per_step", - "max_per_step", - "steps_per_sec", - ] - ) - writer.writerows(rows) - - print(f"\nWrote results to {OUTPUT_CSV}") - - -def monitor_command(case): - cmd = ["cargo", "monitor", "--protocol", case["path"]] - if case["wave"]: - cmd += ["--wave", case["wave"]] - if case["instances"]: - cmd += ["--instances", *case["instances"]] - cmd += case["extra_args"] - return cmd - - -def profile_path(case): - candidates = [Path(case["path"]).with_suffix(".prof")] - wave = case.get("wave") - if isinstance(wave, str): - candidates.append(Path(wave).with_suffix(".prof")) - for candidate in candidates: - if candidate.exists(): - return str(candidate) - return str(candidates[0]) - - -if __name__ == "__main__": - main() diff --git a/scripts/check_performance_regression.py b/scripts/check_performance_regression.py deleted file mode 100644 index abeaaeec..00000000 --- a/scripts/check_performance_regression.py +++ /dev/null @@ -1,118 +0,0 @@ -#!/usr/bin/env python3 -""" -Check for performance regressions in the monitor -by comparing current benchmark results with a baseline (the existing CSV -in the `benchmark_results` sub-directory). -""" - -import csv -import sys -import os - -BASELINE_CSV = "benchmark_results/baseline_results.csv" -CURRENT_CSV = "benchmark_results/benchmark_results.csv" -REGRESSION_THRESHOLD = 0.10 # 10% slower is considered a regression - - -def load_results(csv_path): - """Load benchmark results from CSV into a dict keyed by test_name.""" - results = {} - with open(csv_path) as f: - reader = csv.DictReader(f) - for row in reader: - test_name = row["test_name"] - results[test_name] = { - "mean_per_step": float(row["mean_per_step"]), - "stddev_per_step": float(row["stddev_per_step"]), - "min_per_step": float(row["min_per_step"]), - "max_per_step": float(row["max_per_step"]), - "steps_per_sec": float(row["steps_per_sec"]), - } - return results - - -def main(): - if not os.path.exists(BASELINE_CSV): - print(f"No baseline found at {BASELINE_CSV}") - print("Creating baseline from current results...") - # Copy current results as baseline - os.makedirs(os.path.dirname(BASELINE_CSV), exist_ok=True) - with open(CURRENT_CSV) as src, open(BASELINE_CSV, "w") as dst: - dst.write(src.read()) - print(f"Baseline saved to {BASELINE_CSV}") - return 0 - - baseline = load_results(BASELINE_CSV) - current = load_results(CURRENT_CSV) - - regressions = [] - improvements = [] - - print("\n=== Performance Comparison ===\n") - - for test_name in sorted(current.keys()): - if test_name not in baseline: - steps_per_sec = current[test_name]["steps_per_sec"] - print(f"NEW: {test_name}: {steps_per_sec:.2f} steps/sec") - continue - - # Read pre-computed throughput (steps per second) - baseline_throughput = baseline[test_name]["steps_per_sec"] - current_throughput = current[test_name]["steps_per_sec"] - - # Calculate percentage change (positive = improvement, negative = regression) - pct_change = ( - (current_throughput - baseline_throughput) / baseline_throughput - ) * 100 - - status = "=" - if pct_change < -REGRESSION_THRESHOLD * 100: - # Throughput decreased by more than threshold = regression - status = "REGRESSION" - regressions.append( - (test_name, baseline_throughput, current_throughput, pct_change) - ) - elif pct_change > REGRESSION_THRESHOLD * 100: - # Throughput increased by more than threshold = improvement - status = "IMPROVEMENT" - improvements.append( - (test_name, baseline_throughput, current_throughput, pct_change) - ) - - print( - f"{status:12} {test_name:30} {baseline_throughput:7.2f} -> {current_throughput:7.2f} steps/sec ({pct_change:+6.2f}%)" - ) - - print() - - if regressions: - print(f"\nFound {len(regressions)} performance regression(s):") - for ( - test_name, - baseline_throughput, - current_throughput, - pct_change, - ) in regressions: - print( - f" - {test_name}: {baseline_throughput:.2f} -> {current_throughput:.2f} steps/sec ({pct_change:+.2f}%)" - ) - return 1 - - if improvements: - print(f"\nFound {len(improvements)} performance improvement(s):") - for ( - test_name, - baseline_throughput, - current_throughput, - pct_change, - ) in improvements: - print( - f" - {test_name}: {baseline_throughput:.2f} -> {current_throughput:.2f} steps/sec ({pct_change:+.2f}%)" - ) - - print("\nNo performance regressions detected!") - return 0 - - -if __name__ == "__main__": - sys.exit(main()) diff --git a/scripts/generate_runt_configs.py b/scripts/generate_runt_configs.py index d7c7df91..41930bf6 100644 --- a/scripts/generate_runt_configs.py +++ b/scripts/generate_runt_configs.py @@ -91,7 +91,7 @@ def expect_name(case: dict, runner: str) -> str: def expect_dir(case: dict, runner: str) -> str: wave = case.get("wave") - base = Path(wave if runner in ("monitor", "bi") and wave else case["path"]).parent + base = Path(wave if runner == "bi" and wave else case["path"]).parent return f"../../{base.as_posix()}/expects" @@ -105,7 +105,7 @@ def binary_prefix(binary: str) -> list[str]: def repo_root_command(cmd: list[str], stderr: str = "discard") -> str: # Each runt test runs exactly one path, so we bake it straight into the # command. Runt captures stdout; interp snapshots intentionally include - # diagnostics, while monitor/graph snapshots historically discard stderr. + # diagnostics, while graph snapshots historically discard stderr. if stderr == "stdout": tail = " 2>&1" elif stderr == "discard": @@ -119,7 +119,7 @@ def repo_root_command(cmd: list[str], stderr: str = "discard") -> str: def timeout_cmd(timeout_secs: int, cmd: list[str]) -> list[str]: # Runt doesn't support expected timeouts, so we have to have this wrapper - # on the interp/monitor commands + # on the interp/bi commands # Run in a new process group and kill the whole group (cargo's child binary # included) on expiry, exiting 124 to match coreutils. script = ( @@ -181,21 +181,6 @@ def graph_interp_runt_command(case: dict) -> list[tuple[str, str]]: return [(suffix, repo_root_command(cmd + flags)) for suffix, flags in flag_sets] -def monitor_runt_command(case: dict) -> list[tuple[str, str]]: - cmd = [*binary_prefix("protocols-monitor"), "--protocol", case["path"]] - if case["wave"]: - cmd += ["--wave", case["wave"]] - if case["instances"]: - cmd += ["--instances", *case["instances"]] - if case["max_steps"] is not None: - cmd += ["--max-steps", str(case["max_steps"])] - cmd += case["extra_args"] - if case["timeout_secs"] is not None: - cmd = timeout_cmd(case["timeout_secs"], cmd) - return [("", repo_root_command(cmd))] - - -# Same as `monitor_runt_command` above but for the BI test cases def bi_runt_command(case: dict) -> list[tuple[str, str]]: # We pass in `--color never` to BI to suppress color in error messages # (so that the .expect files only display plaintext) @@ -277,7 +262,6 @@ def fail_runt_command(case: dict) -> list[tuple[str, str]]: RUNT_BUILDERS = { "interp": interp_runt_command, "graph_interp": graph_interp_runt_command, - "monitor": monitor_runt_command, "bi": bi_runt_command, "waveform": waveform_runt_command, "fail": fail_runt_command, @@ -401,13 +385,11 @@ def write_runt_toml(output_dir: Path, suites) -> None: def generate_runt_configs() -> None: tx = load_tx_cases() mon = load_monitor_cases() - # Each suite maps a name to (runner, cases). interp + monitor + graph_interp - # together cover every test. + # Each suite maps a name to (runner, cases). interp + graph_interp + # together cover every tx test. suite_specs = { "interp": ("interp", tx), - "monitor": ("monitor", mon), - # Note: bi uses the same cases as the monitor (i.e. MONITOR_CASES) - # as the monitor/bi share largely the same CLI args + # The bi suite runs over the wave-based cases (MONITOR_CASES). "bi": ("bi", mon), "graph_interp": ("graph_interp", graph_interp_cases(tx)), "waveform": ("waveform", waveform_cases(tx)), diff --git a/scripts/plot_benchmark_results.py b/scripts/plot_benchmark_results.py deleted file mode 100644 index 65e99094..00000000 --- a/scripts/plot_benchmark_results.py +++ /dev/null @@ -1,53 +0,0 @@ -#!/usr/bin/env python3 -""" -Plots the data in `INPUT_CSV` as a scatter plot, saving it in `OUTPUT_PNG` -""" - -import csv -import math -import matplotlib.pyplot as plt - -INPUT_CSV = "benchmark_results/benchmark_results.csv" -OUTPUT_PNG = "benchmark_results/benchmark_plot.png" - - -def main(): - names = [] - steps_per_sec = [] - - with open(INPUT_CSV) as f: - reader = csv.DictReader(f) - for row in reader: - names.append(row["test_name"]) - # Read pre-computed throughput (steps per second) - steps_per_sec.append(float(row["steps_per_sec"])) - - # Determine min/max values on the y-axis, round them to nearest multiple of 10 - min_steps_per_sec = min(steps_per_sec) - max_steps_per_sec = max(steps_per_sec) - ymin = math.floor(min_steps_per_sec / 10.0) * 10.0 - ymax = math.ceil(max_steps_per_sec / 10.0) * 10.0 - - # Create ticks for every 200 units on the y-axis - yticks = list(range(int(ymin), int(ymax) + 1, 200)) - - plt.figure(figsize=(12, 8)) - plt.scatter(names, steps_per_sec) - - plt.title("Monitor throughput on benchmarks (higher is better)") - plt.xlabel("Test File") - plt.ylabel("Mean no. of Steps (clock cycles) per second") - plt.xticks(rotation=45, ha="right") - plt.yticks(yticks) - - plt.grid(zorder=1, linestyle="--", alpha=0.6) - plt.tight_layout() - plt.savefig(OUTPUT_PNG) - - print(f"Saved plot to {OUTPUT_PNG}") - - plt.close() - - -if __name__ == "__main__": - main() diff --git a/scripts/test_catalog.py b/scripts/test_catalog.py index ff56b960..507e2cc9 100644 --- a/scripts/test_catalog.py +++ b/scripts/test_catalog.py @@ -1,7 +1,8 @@ # Checked-in test catalog. Hand-maintained source of truth. -# Consumed by scripts/generate_runt_configs.py and scripts/benchmark_monitor.py. +# Consumed by scripts/generate_runt_configs.py. # -# TX_CASES are keyed by their .tx path. MONITOR_CASES are keyed by a unique id +# TX_CASES are keyed by their .tx path. MONITOR_CASES (the wave-based cases that +# drive the bi suite) are keyed by a unique id TX_CASES = { "examples/picorv32/unsigned_mul.tx": { diff --git a/tests/adders/expects/add_d1.monitor.expect b/tests/adders/expects/add_d1.monitor.expect deleted file mode 100644 index ff76d998..00000000 --- a/tests/adders/expects/add_d1.monitor.expect +++ /dev/null @@ -1,5 +0,0 @@ -// trace 0 -trace { - add(1, 2, 3); - add(4, 5, 9); -} diff --git a/tests/adders/expects/add_d2.monitor.expect b/tests/adders/expects/add_d2.monitor.expect deleted file mode 100644 index ff76d998..00000000 --- a/tests/adders/expects/add_d2.monitor.expect +++ /dev/null @@ -1,5 +0,0 @@ -// trace 0 -trace { - add(1, 2, 3); - add(4, 5, 9); -} diff --git a/tests/adders/expects/add_var_cyc.monitor.expect b/tests/adders/expects/add_var_cyc.monitor.expect deleted file mode 100644 index 1f54e4cf..00000000 --- a/tests/adders/expects/add_var_cyc.monitor.expect +++ /dev/null @@ -1,27 +0,0 @@ -// trace 0 -trace { - loop_add(1, 2, 3, 2); - loop_add(10, 20, 30, 0); -} - -// trace 1 -trace { - loop_add(1, 2, 3, 0); - loop_add(1, 2, 3, 1); - loop_add(10, 20, 30, 0); -} - -// trace 2 -trace { - loop_add(1, 2, 3, 1); - loop_add(1, 2, 3, 0); - loop_add(10, 20, 30, 0); -} - -// trace 3 -trace { - loop_add(1, 2, 3, 0); - loop_add(1, 2, 3, 0); - loop_add(1, 2, 3, 0); - loop_add(10, 20, 30, 0); -} diff --git a/tests/adders/expects/busy_wait.monitor.expect b/tests/adders/expects/busy_wait.monitor.expect deleted file mode 100644 index dd10c482..00000000 --- a/tests/adders/expects/busy_wait.monitor.expect +++ /dev/null @@ -1,12 +0,0 @@ -// trace 0 -trace { - add_busy_wait(1, 2, 1, 3); - add_busy_wait(4, 5, 2, 9); -} - -// trace 1 -trace { - add_busy_wait(1, 2, 1, 3); - add_busy_wait(4, 5, 1, 9); - add_busy_wait(4, 5, 1, 9); -} diff --git a/tests/adders/expects/loop_with_assigns.monitor.expect b/tests/adders/expects/loop_with_assigns.monitor.expect deleted file mode 100644 index 95bdea3c..00000000 --- a/tests/adders/expects/loop_with_assigns.monitor.expect +++ /dev/null @@ -1,31 +0,0 @@ -// trace 0 -trace { - loop_add(1, 2, 3, 3); - loop_add(10, 20, 1, 30); - loop_add(198490043, 4254467669, 1, 30); -} - -// trace 1 -trace { - loop_add(1, 2, 1, 3); - loop_add(1, 2, 2, 3); - loop_add(10, 20, 1, 30); - loop_add(198490043, 4254467669, 1, 30); -} - -// trace 2 -trace { - loop_add(1, 2, 2, 3); - loop_add(1, 2, 1, 3); - loop_add(10, 20, 1, 30); - loop_add(198490043, 4254467669, 1, 30); -} - -// trace 3 -trace { - loop_add(1, 2, 1, 3); - loop_add(1, 2, 1, 3); - loop_add(1, 2, 1, 3); - loop_add(10, 20, 1, 30); - loop_add(198490043, 4254467669, 1, 30); -} diff --git a/tests/adders/expects/nested_busy_wait.monitor.expect b/tests/adders/expects/nested_busy_wait.monitor.expect deleted file mode 100644 index 5b85e011..00000000 --- a/tests/adders/expects/nested_busy_wait.monitor.expect +++ /dev/null @@ -1,2 +0,0 @@ ----CODE--- -124 diff --git a/tests/alus/expects/alu_d1.monitor.expect b/tests/alus/expects/alu_d1.monitor.expect deleted file mode 100644 index 16fa0842..00000000 --- a/tests/alus/expects/alu_d1.monitor.expect +++ /dev/null @@ -1,8 +0,0 @@ -// trace 0 -trace { - add(1, 2, 3); - add(123, 245, 368); - sub(200, 200, 0); - and(100, 100, 100); - or(0, 230, 230); -} diff --git a/tests/alus/expects/alu_d2.monitor.expect b/tests/alus/expects/alu_d2.monitor.expect deleted file mode 100644 index 16fa0842..00000000 --- a/tests/alus/expects/alu_d2.monitor.expect +++ /dev/null @@ -1,8 +0,0 @@ -// trace 0 -trace { - add(1, 2, 3); - add(123, 245, 368); - sub(200, 200, 0); - and(100, 100, 100); - or(0, 230, 230); -} diff --git a/tests/antmicro/fifo_classic/expects/test_fifo_classic_1.monitor.expect b/tests/antmicro/fifo_classic/expects/test_fifo_classic_1.monitor.expect deleted file mode 100644 index ff0306dd..00000000 --- a/tests/antmicro/fifo_classic/expects/test_fifo_classic_1.monitor.expect +++ /dev/null @@ -1,11 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 872415232, 3511065769, 0); // [time: 110ns -> 130ns] - reset(); // [time: 170.001ns -> 180.001ns] - reset(); // [time: 180.001ns -> 190.001ns] - reset(); // [time: 190.001ns -> 200.001ns] - write(15, 872415232, 2839611496, 0); // [time: 240.001ns -> 260.001ns] -} diff --git a/tests/antmicro/fifo_classic/expects/test_fifo_classic_2.monitor.expect b/tests/antmicro/fifo_classic/expects/test_fifo_classic_2.monitor.expect deleted file mode 100644 index 2fcf485a..00000000 --- a/tests/antmicro/fifo_classic/expects/test_fifo_classic_2.monitor.expect +++ /dev/null @@ -1,13 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 872415232, 3511065769, 0); // [time: 130ns -> 150ns] - read(15, 872415232, 2839611496, 0); // [time: 150ns -> 170ns] - reset(); // [time: 210.001ns -> 220.001ns] - reset(); // [time: 220.001ns -> 230.001ns] - reset(); // [time: 230.001ns -> 240.001ns] - write(15, 872415232, 4255599317, 0); // [time: 280.001ns -> 300.001ns] - write(15, 872415232, 2978480611, 0); // [time: 300.001ns -> 320.001ns] -} diff --git a/tests/antmicro/fifo_classic/expects/test_fifo_classic_3.monitor.expect b/tests/antmicro/fifo_classic/expects/test_fifo_classic_3.monitor.expect deleted file mode 100644 index f90eb06e..00000000 --- a/tests/antmicro/fifo_classic/expects/test_fifo_classic_3.monitor.expect +++ /dev/null @@ -1,15 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 872415232, 3511065769, 0); // [time: 150ns -> 170ns] - read(15, 872415232, 2839611496, 0); // [time: 170ns -> 190ns] - read(15, 872415232, 4255599317, 0); // [time: 190ns -> 210ns] - reset(); // [time: 250.001ns -> 260.001ns] - reset(); // [time: 260.001ns -> 270.001ns] - reset(); // [time: 270.001ns -> 280.001ns] - write(15, 872415232, 2978480611, 0); // [time: 320.001ns -> 340.001ns] - write(15, 872415232, 2227458782, 0); // [time: 340.001ns -> 360.001ns] - write(15, 872415232, 2594436392, 0); // [time: 360.001ns -> 380.001ns] -} diff --git a/tests/antmicro/fifo_classic/expects/test_fifo_classic_4.monitor.expect b/tests/antmicro/fifo_classic/expects/test_fifo_classic_4.monitor.expect deleted file mode 100644 index 9dd58394..00000000 --- a/tests/antmicro/fifo_classic/expects/test_fifo_classic_4.monitor.expect +++ /dev/null @@ -1,17 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 872415232, 3511065769, 0); // [time: 170ns -> 190ns] - read(15, 872415232, 2839611496, 0); // [time: 190ns -> 210ns] - read(15, 872415232, 4255599317, 0); // [time: 210ns -> 230ns] - read(15, 872415232, 2978480611, 0); // [time: 230ns -> 250ns] - reset(); // [time: 290.001ns -> 300.001ns] - reset(); // [time: 300.001ns -> 310.001ns] - reset(); // [time: 310.001ns -> 320.001ns] - write(15, 872415232, 2227458782, 0); // [time: 360.001ns -> 380.001ns] - write(15, 872415232, 2594436392, 0); // [time: 380.001ns -> 400.001ns] - write(15, 872415232, 2879904594, 0); // [time: 400.001ns -> 420.001ns] - write(15, 872415232, 2502756630, 0); // [time: 420.001ns -> 440.001ns] -} diff --git a/tests/antmicro/fifo_classic/expects/test_fifo_classic_5.monitor.expect b/tests/antmicro/fifo_classic/expects/test_fifo_classic_5.monitor.expect deleted file mode 100644 index 906c59ca..00000000 --- a/tests/antmicro/fifo_classic/expects/test_fifo_classic_5.monitor.expect +++ /dev/null @@ -1,19 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 872415232, 3511065769, 0); // [time: 190ns -> 210ns] - read(15, 872415232, 2839611496, 0); // [time: 210ns -> 230ns] - read(15, 872415232, 4255599317, 0); // [time: 230ns -> 250ns] - read(15, 872415232, 2978480611, 0); // [time: 250ns -> 270ns] - read(15, 872415232, 2227458782, 0); // [time: 270ns -> 290ns] - reset(); // [time: 330.001ns -> 340.001ns] - reset(); // [time: 340.001ns -> 350.001ns] - reset(); // [time: 350.001ns -> 360.001ns] - write(15, 872415232, 2594436392, 0); // [time: 400.001ns -> 420.001ns] - write(15, 872415232, 2879904594, 0); // [time: 420.001ns -> 440.001ns] - write(15, 872415232, 2502756630, 0); // [time: 440.001ns -> 460.001ns] - write(15, 872415232, 3888695605, 0); // [time: 460.001ns -> 480.001ns] - write(15, 872415232, 4181798306, 0); // [time: 480.001ns -> 500.001ns] -} diff --git a/tests/antmicro/fifo_classic/expects/test_fifo_classic_6.monitor.expect b/tests/antmicro/fifo_classic/expects/test_fifo_classic_6.monitor.expect deleted file mode 100644 index fd22df44..00000000 --- a/tests/antmicro/fifo_classic/expects/test_fifo_classic_6.monitor.expect +++ /dev/null @@ -1,21 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 872415232, 2215956531, 0); // [time: 210ns -> 230ns] - read(15, 872415232, 2174594346, 0); // [time: 230ns -> 250ns] - read(15, 872415232, 3706263408, 0); // [time: 250ns -> 270ns] - read(15, 872415232, 3375769081, 0); // [time: 270ns -> 290ns] - read(15, 872415232, 3915557832, 0); // [time: 290ns -> 310ns] - read(15, 872415232, 2529678886, 0); // [time: 310ns -> 330ns] - reset(); // [time: 370.001ns -> 380.001ns] - reset(); // [time: 380.001ns -> 390.001ns] - reset(); // [time: 390.001ns -> 400.001ns] - write(15, 872415232, 2550371957, 0); // [time: 440.001ns -> 460.001ns] - write(15, 872415232, 2973140726, 0); // [time: 460.001ns -> 480.001ns] - write(15, 872415232, 3658948496, 0); // [time: 480.001ns -> 500.001ns] - write(15, 872415232, 4239119767, 0); // [time: 500.001ns -> 520.001ns] - write(15, 872415232, 2305440508, 0); // [time: 520.001ns -> 540.001ns] - write(15, 872415232, 2674771663, 0); // [time: 540.001ns -> 560.001ns] -} diff --git a/tests/antmicro/fifo_classic/expects/test_fifo_classic_7.monitor.expect b/tests/antmicro/fifo_classic/expects/test_fifo_classic_7.monitor.expect deleted file mode 100644 index 21ba8129..00000000 --- a/tests/antmicro/fifo_classic/expects/test_fifo_classic_7.monitor.expect +++ /dev/null @@ -1,23 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 872415232, 2215956531, 0); // [time: 230ns -> 250ns] - read(15, 872415232, 2174594346, 0); // [time: 250ns -> 270ns] - read(15, 872415232, 3706263408, 0); // [time: 270ns -> 290ns] - read(15, 872415232, 3375769081, 0); // [time: 290ns -> 310ns] - read(15, 872415232, 3915557832, 0); // [time: 310ns -> 330ns] - read(15, 872415232, 2529678886, 0); // [time: 330ns -> 350ns] - read(15, 872415232, 2550371957, 0); // [time: 350ns -> 370ns] - reset(); // [time: 410.001ns -> 420.001ns] - reset(); // [time: 420.001ns -> 430.001ns] - reset(); // [time: 430.001ns -> 440.001ns] - write(15, 872415232, 2973140726, 0); // [time: 480.001ns -> 500.001ns] - write(15, 872415232, 3658948496, 0); // [time: 500.001ns -> 520.001ns] - write(15, 872415232, 4239119767, 0); // [time: 520.001ns -> 540.001ns] - write(15, 872415232, 2305440508, 0); // [time: 540.001ns -> 560.001ns] - write(15, 872415232, 2674771663, 0); // [time: 560.001ns -> 580.001ns] - write(15, 872415232, 4005297405, 0); // [time: 580.001ns -> 600.001ns] - write(15, 872415232, 2923162757, 0); // [time: 600.001ns -> 620.001ns] -} diff --git a/tests/antmicro/fifo_classic/expects/test_fifo_classic_8.monitor.expect b/tests/antmicro/fifo_classic/expects/test_fifo_classic_8.monitor.expect deleted file mode 100644 index 64b96213..00000000 --- a/tests/antmicro/fifo_classic/expects/test_fifo_classic_8.monitor.expect +++ /dev/null @@ -1,25 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 872415232, 2215956531, 0); // [time: 250ns -> 270ns] - read(15, 872415232, 2174594346, 0); // [time: 270ns -> 290ns] - read(15, 872415232, 3706263408, 0); // [time: 290ns -> 310ns] - read(15, 872415232, 3375769081, 0); // [time: 310ns -> 330ns] - read(15, 872415232, 3915557832, 0); // [time: 330ns -> 350ns] - read(15, 872415232, 2529678886, 0); // [time: 350ns -> 370ns] - read(15, 872415232, 2550371957, 0); // [time: 370ns -> 390ns] - read(15, 872415232, 2973140726, 0); // [time: 390ns -> 410ns] - reset(); // [time: 450.001ns -> 460.001ns] - reset(); // [time: 460.001ns -> 470.001ns] - reset(); // [time: 470.001ns -> 480.001ns] - write(15, 872415232, 3658948496, 0); // [time: 520.001ns -> 540.001ns] - write(15, 872415232, 4239119767, 0); // [time: 540.001ns -> 560.001ns] - write(15, 872415232, 2305440508, 0); // [time: 560.001ns -> 580.001ns] - write(15, 872415232, 2674771663, 0); // [time: 580.001ns -> 600.001ns] - write(15, 872415232, 4005297405, 0); // [time: 600.001ns -> 620.001ns] - write(15, 872415232, 2923162757, 0); // [time: 620.001ns -> 640.001ns] - write(15, 872415232, 2212602639, 0); // [time: 640.001ns -> 660.001ns] - write(15, 872415232, 3940387843, 0); // [time: 660.001ns -> 680.001ns] -} diff --git a/tests/antmicro/fifo_constant/expects/test_fifo_constant_1.monitor.expect b/tests/antmicro/fifo_constant/expects/test_fifo_constant_1.monitor.expect deleted file mode 100644 index e26f1c51..00000000 --- a/tests/antmicro/fifo_constant/expects/test_fifo_constant_1.monitor.expect +++ /dev/null @@ -1,16 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 872415232, 136945767, 0); // [time: 110ns -> 130ns] - reset(); // [time: 170.001ns -> 180.001ns] - reset(); // [time: 180.001ns -> 190.001ns] - reset(); // [time: 190.001ns -> 200.001ns] - write(15, 872415232, 54221397, 0); // [time: 240.001ns -> 260.001ns] - reset(); // [time: 320.002ns -> 330.002ns] - reset(); // [time: 330.002ns -> 340.002ns] - reset(); // [time: 340.002ns -> 350.002ns] - write(15, 872415232, 3117559521, 0); // [time: 410.002ns -> 430.002ns] - read(15, 872415232, 6, 0); // [time: 430.002ns -> 450.002ns] -} diff --git a/tests/antmicro/fifo_constant/expects/test_fifo_constant_2.monitor.expect b/tests/antmicro/fifo_constant/expects/test_fifo_constant_2.monitor.expect deleted file mode 100644 index 10aa066c..00000000 --- a/tests/antmicro/fifo_constant/expects/test_fifo_constant_2.monitor.expect +++ /dev/null @@ -1,19 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 872415232, 136945767, 0); // [time: 130ns -> 150ns] - read(15, 872415232, 54221397, 0); // [time: 150ns -> 160ns] - reset(); // [time: 200.001ns -> 210.001ns] - reset(); // [time: 210.001ns -> 220.001ns] - reset(); // [time: 220.001ns -> 230.001ns] - write(15, 872415232, 3117559521, 0); // [time: 270.001ns -> 290.001ns] - write(15, 872415232, 2456570867, 0); // [time: 290.001ns -> 300.001ns] - reset(); // [time: 380.002ns -> 390.002ns] - reset(); // [time: 390.002ns -> 400.002ns] - reset(); // [time: 400.002ns -> 410.002ns] - write(15, 872415232, 3536148369, 0); // [time: 470.002ns -> 490.002ns] - write(15, 872415232, 764390477, 0); // [time: 490.002ns -> 500.002ns] - read(15, 872415232, 6, 0); // [time: 500.002ns -> 520.002ns] -} diff --git a/tests/antmicro/fifo_constant/expects/test_fifo_constant_3.monitor.expect b/tests/antmicro/fifo_constant/expects/test_fifo_constant_3.monitor.expect deleted file mode 100644 index 905246ba..00000000 --- a/tests/antmicro/fifo_constant/expects/test_fifo_constant_3.monitor.expect +++ /dev/null @@ -1,22 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 872415232, 136945767, 0); // [time: 150ns -> 170ns] - read(15, 872415232, 54221397, 0); // [time: 170ns -> 180ns] - read(15, 872415232, 3117559521, 0); // [time: 180ns -> 190ns] - reset(); // [time: 230.001ns -> 240.001ns] - reset(); // [time: 240.001ns -> 250.001ns] - reset(); // [time: 250.001ns -> 260.001ns] - write(15, 872415232, 2456570867, 0); // [time: 300.001ns -> 320.001ns] - write(15, 872415232, 3536148369, 0); // [time: 320.001ns -> 330.001ns] - write(15, 872415232, 764390477, 0); // [time: 330.001ns -> 340.001ns] - reset(); // [time: 440.002ns -> 450.002ns] - reset(); // [time: 450.002ns -> 460.002ns] - reset(); // [time: 460.002ns -> 470.002ns] - write(15, 872415232, 805776619, 0); // [time: 530.002ns -> 550.002ns] - write(15, 872415232, 1651314158, 0); // [time: 550.002ns -> 560.002ns] - write(15, 872415232, 3022929697, 0); // [time: 560.002ns -> 570.002ns] - read(15, 872415232, 6, 0); // [time: 570.002ns -> 590.002ns] -} diff --git a/tests/antmicro/fifo_constant/expects/test_fifo_constant_4.monitor.expect b/tests/antmicro/fifo_constant/expects/test_fifo_constant_4.monitor.expect deleted file mode 100644 index 8bd13fef..00000000 --- a/tests/antmicro/fifo_constant/expects/test_fifo_constant_4.monitor.expect +++ /dev/null @@ -1,25 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 872415232, 136945767, 0); // [time: 170ns -> 190ns] - read(15, 872415232, 54221397, 0); // [time: 190ns -> 200ns] - read(15, 872415232, 3117559521, 0); // [time: 200ns -> 210ns] - read(15, 872415232, 2456570867, 0); // [time: 210ns -> 220ns] - reset(); // [time: 260.001ns -> 270.001ns] - reset(); // [time: 270.001ns -> 280.001ns] - reset(); // [time: 280.001ns -> 290.001ns] - write(15, 872415232, 3536148369, 0); // [time: 330.001ns -> 350.001ns] - write(15, 872415232, 764390477, 0); // [time: 350.001ns -> 360.001ns] - write(15, 872415232, 805776619, 0); // [time: 360.001ns -> 370.001ns] - write(15, 872415232, 1651314158, 0); // [time: 370.001ns -> 380.001ns] - reset(); // [time: 500.002ns -> 510.002ns] - reset(); // [time: 510.002ns -> 520.002ns] - reset(); // [time: 520.002ns -> 530.002ns] - write(15, 872415232, 3022929697, 0); // [time: 590.002ns -> 610.002ns] - write(15, 872415232, 4183272239, 0); // [time: 610.002ns -> 620.002ns] - write(15, 872415232, 315913722, 0); // [time: 620.002ns -> 630.002ns] - write(15, 872415232, 1054576031, 0); // [time: 630.002ns -> 640.002ns] - read(15, 872415232, 6, 0); // [time: 640.002ns -> 660.002ns] -} diff --git a/tests/antmicro/fifo_constant/expects/test_fifo_constant_5.monitor.expect b/tests/antmicro/fifo_constant/expects/test_fifo_constant_5.monitor.expect deleted file mode 100644 index dcf480c0..00000000 --- a/tests/antmicro/fifo_constant/expects/test_fifo_constant_5.monitor.expect +++ /dev/null @@ -1,28 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 872415232, 1363247548, 0); // [time: 190ns -> 210ns] - read(15, 872415232, 2498712983, 0); // [time: 210ns -> 220ns] - read(15, 872415232, 2031470411, 0); // [time: 220ns -> 230ns] - read(15, 872415232, 247232753, 0); // [time: 230ns -> 240ns] - read(15, 872415232, 236574178, 0); // [time: 240ns -> 250ns] - reset(); // [time: 290.001ns -> 300.001ns] - reset(); // [time: 300.001ns -> 310.001ns] - reset(); // [time: 310.001ns -> 320.001ns] - write(15, 872415232, 421022298, 0); // [time: 360.001ns -> 380.001ns] - write(15, 872415232, 2203084718, 0); // [time: 380.001ns -> 390.001ns] - write(15, 872415232, 2308882986, 0); // [time: 390.001ns -> 400.001ns] - write(15, 872415232, 4235095479, 0); // [time: 400.001ns -> 410.001ns] - write(15, 872415232, 1180440750, 0); // [time: 410.001ns -> 420.001ns] - reset(); // [time: 560.002ns -> 570.002ns] - reset(); // [time: 570.002ns -> 580.002ns] - reset(); // [time: 580.002ns -> 590.002ns] - write(15, 872415232, 2313964829, 0); // [time: 650.002ns -> 670.002ns] - write(15, 872415232, 2950684687, 0); // [time: 670.002ns -> 680.002ns] - write(15, 872415232, 1632464407, 0); // [time: 680.002ns -> 690.002ns] - write(15, 872415232, 531222031, 0); // [time: 690.002ns -> 700.002ns] - write(15, 872415232, 2086209707, 0); // [time: 700.002ns -> 710.002ns] - read(15, 872415232, 6, 0); // [time: 710.002ns -> 730.002ns] -} diff --git a/tests/antmicro/fifo_constant/expects/test_fifo_constant_6.monitor.expect b/tests/antmicro/fifo_constant/expects/test_fifo_constant_6.monitor.expect deleted file mode 100644 index d6aea314..00000000 --- a/tests/antmicro/fifo_constant/expects/test_fifo_constant_6.monitor.expect +++ /dev/null @@ -1,31 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 872415232, 1363247548, 0); // [time: 210ns -> 230ns] - read(15, 872415232, 2498712983, 0); // [time: 230ns -> 240ns] - read(15, 872415232, 2031470411, 0); // [time: 240ns -> 250ns] - read(15, 872415232, 247232753, 0); // [time: 250ns -> 260ns] - read(15, 872415232, 236574178, 0); // [time: 260ns -> 270ns] - read(15, 872415232, 421022298, 0); // [time: 270ns -> 280ns] - reset(); // [time: 320.001ns -> 330.001ns] - reset(); // [time: 330.001ns -> 340.001ns] - reset(); // [time: 340.001ns -> 350.001ns] - write(15, 872415232, 2203084718, 0); // [time: 390.001ns -> 410.001ns] - write(15, 872415232, 2308882986, 0); // [time: 410.001ns -> 420.001ns] - write(15, 872415232, 4235095479, 0); // [time: 420.001ns -> 430.001ns] - write(15, 872415232, 1180440750, 0); // [time: 430.001ns -> 440.001ns] - write(15, 872415232, 2313964829, 0); // [time: 440.001ns -> 450.001ns] - write(15, 872415232, 2950684687, 0); // [time: 450.001ns -> 460.001ns] - reset(); // [time: 620.002ns -> 630.002ns] - reset(); // [time: 630.002ns -> 640.002ns] - reset(); // [time: 640.002ns -> 650.002ns] - write(15, 872415232, 1632464407, 0); // [time: 710.002ns -> 730.002ns] - write(15, 872415232, 531222031, 0); // [time: 730.002ns -> 740.002ns] - write(15, 872415232, 2086209707, 0); // [time: 740.002ns -> 750.002ns] - write(15, 872415232, 3905452749, 0); // [time: 750.002ns -> 760.002ns] - write(15, 872415232, 1047759017, 0); // [time: 760.002ns -> 770.002ns] - write(15, 872415232, 1028960831, 0); // [time: 770.002ns -> 780.002ns] - read(15, 872415232, 6, 0); // [time: 780.002ns -> 800.002ns] -} diff --git a/tests/antmicro/fifo_constant/expects/test_fifo_constant_7.monitor.expect b/tests/antmicro/fifo_constant/expects/test_fifo_constant_7.monitor.expect deleted file mode 100644 index 247b5a2f..00000000 --- a/tests/antmicro/fifo_constant/expects/test_fifo_constant_7.monitor.expect +++ /dev/null @@ -1,34 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 872415232, 1363247548, 0); // [time: 230ns -> 250ns] - read(15, 872415232, 2498712983, 0); // [time: 250ns -> 260ns] - read(15, 872415232, 2031470411, 0); // [time: 260ns -> 270ns] - read(15, 872415232, 247232753, 0); // [time: 270ns -> 280ns] - read(15, 872415232, 236574178, 0); // [time: 280ns -> 290ns] - read(15, 872415232, 421022298, 0); // [time: 290ns -> 300ns] - read(15, 872415232, 2203084718, 0); // [time: 300ns -> 310ns] - reset(); // [time: 350.001ns -> 360.001ns] - reset(); // [time: 360.001ns -> 370.001ns] - reset(); // [time: 370.001ns -> 380.001ns] - write(15, 872415232, 2308882986, 0); // [time: 420.001ns -> 440.001ns] - write(15, 872415232, 4235095479, 0); // [time: 440.001ns -> 450.001ns] - write(15, 872415232, 1180440750, 0); // [time: 450.001ns -> 460.001ns] - write(15, 872415232, 2313964829, 0); // [time: 460.001ns -> 470.001ns] - write(15, 872415232, 2950684687, 0); // [time: 470.001ns -> 480.001ns] - write(15, 872415232, 1632464407, 0); // [time: 480.001ns -> 490.001ns] - write(15, 872415232, 531222031, 0); // [time: 490.001ns -> 500.001ns] - reset(); // [time: 680.002ns -> 690.002ns] - reset(); // [time: 690.002ns -> 700.002ns] - reset(); // [time: 700.002ns -> 710.002ns] - write(15, 872415232, 2086209707, 0); // [time: 770.002ns -> 790.002ns] - write(15, 872415232, 3905452749, 0); // [time: 790.002ns -> 800.002ns] - write(15, 872415232, 1047759017, 0); // [time: 800.002ns -> 810.002ns] - write(15, 872415232, 1028960831, 0); // [time: 810.002ns -> 820.002ns] - write(15, 872415232, 3233599833, 0); // [time: 820.002ns -> 830.002ns] - write(15, 872415232, 1516004143, 0); // [time: 830.002ns -> 840.002ns] - write(15, 872415232, 619658659, 0); // [time: 840.002ns -> 850.002ns] - read(15, 872415232, 6, 0); // [time: 850.002ns -> 870.002ns] -} diff --git a/tests/antmicro/fifo_constant/expects/test_fifo_constant_8.monitor.expect b/tests/antmicro/fifo_constant/expects/test_fifo_constant_8.monitor.expect deleted file mode 100644 index 951423ae..00000000 --- a/tests/antmicro/fifo_constant/expects/test_fifo_constant_8.monitor.expect +++ /dev/null @@ -1,37 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 872415232, 1363247548, 0); // [time: 250ns -> 270ns] - read(15, 872415232, 2498712983, 0); // [time: 270ns -> 280ns] - read(15, 872415232, 2031470411, 0); // [time: 280ns -> 290ns] - read(15, 872415232, 247232753, 0); // [time: 290ns -> 300ns] - read(15, 872415232, 236574178, 0); // [time: 300ns -> 310ns] - read(15, 872415232, 421022298, 0); // [time: 310ns -> 320ns] - read(15, 872415232, 2203084718, 0); // [time: 320ns -> 330ns] - read(15, 872415232, 2308882986, 0); // [time: 330ns -> 340ns] - reset(); // [time: 380.001ns -> 390.001ns] - reset(); // [time: 390.001ns -> 400.001ns] - reset(); // [time: 400.001ns -> 410.001ns] - write(15, 872415232, 4235095479, 0); // [time: 450.001ns -> 470.001ns] - write(15, 872415232, 1180440750, 0); // [time: 470.001ns -> 480.001ns] - write(15, 872415232, 2313964829, 0); // [time: 480.001ns -> 490.001ns] - write(15, 872415232, 2950684687, 0); // [time: 490.001ns -> 500.001ns] - write(15, 872415232, 1632464407, 0); // [time: 500.001ns -> 510.001ns] - write(15, 872415232, 531222031, 0); // [time: 510.001ns -> 520.001ns] - write(15, 872415232, 2086209707, 0); // [time: 520.001ns -> 530.001ns] - write(15, 872415232, 3905452749, 0); // [time: 530.001ns -> 540.001ns] - reset(); // [time: 740.002ns -> 750.002ns] - reset(); // [time: 750.002ns -> 760.002ns] - reset(); // [time: 760.002ns -> 770.002ns] - write(15, 872415232, 1047759017, 0); // [time: 830.002ns -> 850.002ns] - write(15, 872415232, 1028960831, 0); // [time: 850.002ns -> 860.002ns] - write(15, 872415232, 3233599833, 0); // [time: 860.002ns -> 870.002ns] - write(15, 872415232, 1516004143, 0); // [time: 870.002ns -> 880.002ns] - write(15, 872415232, 619658659, 0); // [time: 880.002ns -> 890.002ns] - write(15, 872415232, 1481414104, 0); // [time: 890.002ns -> 900.002ns] - write(15, 872415232, 2537393056, 0); // [time: 900.002ns -> 910.002ns] - write(15, 872415232, 3649566230, 0); // [time: 910.002ns -> 920.002ns] - read(15, 872415232, 6, 0); // [time: 920.002ns -> 940.002ns] -} diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_16_0.monitor.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_16_0.monitor.expect deleted file mode 100644 index 2f13eb1d..00000000 --- a/tests/antmicro/sram_classic/expects/test_sram_classic_16_0.monitor.expect +++ /dev/null @@ -1,41 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108864, 3946442578, 0); // [time: 410ns -> 430ns] - read(15, 67108865, 2796792514, 0); // [time: 430ns -> 450ns] - read(15, 67108866, 3312914512, 0); // [time: 450ns -> 470ns] - read(15, 67108867, 4292142820, 0); // [time: 470ns -> 490ns] - read(15, 67108868, 3525794570, 0); // [time: 490ns -> 510ns] - read(15, 67108869, 2961047623, 0); // [time: 510ns -> 530ns] - read(15, 67108870, 4249856274, 0); // [time: 530ns -> 550ns] - read(15, 67108871, 3405678304, 0); // [time: 550ns -> 570ns] - read(15, 67108872, 2415042617, 0); // [time: 570ns -> 590ns] - read(15, 67108873, 3311552087, 0); // [time: 590ns -> 610ns] - read(15, 67108874, 3211316809, 0); // [time: 610ns -> 630ns] - read(15, 67108875, 3236997651, 0); // [time: 630ns -> 650ns] - read(15, 67108876, 3369414426, 0); // [time: 650ns -> 670ns] - read(15, 67108877, 3866725828, 0); // [time: 670ns -> 690ns] - read(15, 67108878, 2882616058, 0); // [time: 690ns -> 710ns] - read(15, 67108879, 3738458232, 0); // [time: 710ns -> 730ns] - reset(); // [time: 770.001ns -> 780.001ns] - reset(); // [time: 780.001ns -> 790.001ns] - reset(); // [time: 790.001ns -> 800.001ns] - write(15, 67108864, 2558870979, 0); // [time: 840.001ns -> 860.001ns] - write(15, 67108865, 3310254824, 0); // [time: 860.001ns -> 880.001ns] - write(15, 67108866, 3635210891, 0); // [time: 880.001ns -> 900.001ns] - write(15, 67108867, 2844952514, 0); // [time: 900.001ns -> 920.001ns] - write(15, 67108868, 2293386100, 0); // [time: 920.001ns -> 940.001ns] - write(15, 67108869, 3615462605, 0); // [time: 940.001ns -> 960.001ns] - write(15, 67108870, 3569010089, 0); // [time: 960.001ns -> 980.001ns] - write(15, 67108871, 3520072258, 0); // [time: 980.001ns -> 1000.001ns] - write(15, 67108872, 3002516588, 0); // [time: 1000.001ns -> 1020.001ns] - write(15, 67108873, 3681389096, 0); // [time: 1020.001ns -> 1040.001ns] - write(15, 67108874, 2924663556, 0); // [time: 1040.001ns -> 1060.001ns] - write(15, 67108875, 3055297102, 0); // [time: 1060.001ns -> 1080.001ns] - write(15, 67108876, 4177639544, 0); // [time: 1080.001ns -> 1100.001ns] - write(15, 67108877, 3526172361, 0); // [time: 1100.001ns -> 1120.001ns] - write(15, 67108878, 2564412332, 0); // [time: 1120.001ns -> 1140.001ns] - write(15, 67108879, 4210875098, 0); // [time: 1140.001ns -> 1160.001ns] -} diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_16_12.monitor.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_16_12.monitor.expect deleted file mode 100644 index 318d95b0..00000000 --- a/tests/antmicro/sram_classic/expects/test_sram_classic_16_12.monitor.expect +++ /dev/null @@ -1,41 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108867, 3622568730, 0); // [time: 410ns -> 430ns] - read(15, 67108868, 3538707329, 0); // [time: 430ns -> 450ns] - read(15, 67108869, 3440721235, 0); // [time: 450ns -> 470ns] - read(15, 67108870, 3191204602, 0); // [time: 470ns -> 490ns] - read(15, 67108871, 4084986393, 0); // [time: 490ns -> 510ns] - read(15, 67108872, 3446247256, 0); // [time: 510ns -> 530ns] - read(15, 67108873, 3908428032, 0); // [time: 530ns -> 550ns] - read(15, 67108874, 2315046581, 0); // [time: 550ns -> 570ns] - read(15, 67108875, 2780682871, 0); // [time: 570ns -> 590ns] - read(15, 67108876, 3026674647, 0); // [time: 590ns -> 610ns] - read(15, 67108877, 2376933607, 0); // [time: 610ns -> 630ns] - read(15, 67108878, 2436105964, 0); // [time: 630ns -> 650ns] - read(15, 67108879, 3222378968, 0); // [time: 650ns -> 670ns] - read(15, 67108880, 3310323703, 0); // [time: 670ns -> 690ns] - read(15, 67108881, 2550879638, 0); // [time: 690ns -> 710ns] - read(15, 67108882, 3261802111, 0); // [time: 710ns -> 730ns] - reset(); // [time: 770.001ns -> 780.001ns] - reset(); // [time: 780.001ns -> 790.001ns] - reset(); // [time: 790.001ns -> 800.001ns] - write(15, 67108867, 2711682730, 0); // [time: 840.001ns -> 860.001ns] - write(15, 67108868, 4230444125, 0); // [time: 860.001ns -> 880.001ns] - write(15, 67108869, 2579425060, 0); // [time: 880.001ns -> 900.001ns] - write(15, 67108870, 2991027419, 0); // [time: 900.001ns -> 920.001ns] - write(15, 67108871, 2417255467, 0); // [time: 920.001ns -> 940.001ns] - write(15, 67108872, 4045742383, 0); // [time: 940.001ns -> 960.001ns] - write(15, 67108873, 2931778361, 0); // [time: 960.001ns -> 980.001ns] - write(15, 67108874, 3640821048, 0); // [time: 980.001ns -> 1000.001ns] - write(15, 67108875, 3663784812, 0); // [time: 1000.001ns -> 1020.001ns] - write(15, 67108876, 3627233541, 0); // [time: 1020.001ns -> 1040.001ns] - write(15, 67108877, 2459429013, 0); // [time: 1040.001ns -> 1060.001ns] - write(15, 67108878, 4213999775, 0); // [time: 1060.001ns -> 1080.001ns] - write(15, 67108879, 2215241682, 0); // [time: 1080.001ns -> 1100.001ns] - write(15, 67108880, 3801611658, 0); // [time: 1100.001ns -> 1120.001ns] - write(15, 67108881, 2471241936, 0); // [time: 1120.001ns -> 1140.001ns] - write(15, 67108882, 2691314341, 0); // [time: 1140.001ns -> 1160.001ns] -} diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_16_4.monitor.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_16_4.monitor.expect deleted file mode 100644 index 97bca31d..00000000 --- a/tests/antmicro/sram_classic/expects/test_sram_classic_16_4.monitor.expect +++ /dev/null @@ -1,41 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108865, 3946442578, 0); // [time: 410ns -> 430ns] - read(15, 67108866, 2796792514, 0); // [time: 430ns -> 450ns] - read(15, 67108867, 3312914512, 0); // [time: 450ns -> 470ns] - read(15, 67108868, 4292142820, 0); // [time: 470ns -> 490ns] - read(15, 67108869, 3525794570, 0); // [time: 490ns -> 510ns] - read(15, 67108870, 2961047623, 0); // [time: 510ns -> 530ns] - read(15, 67108871, 4249856274, 0); // [time: 530ns -> 550ns] - read(15, 67108872, 3405678304, 0); // [time: 550ns -> 570ns] - read(15, 67108873, 2415042617, 0); // [time: 570ns -> 590ns] - read(15, 67108874, 3311552087, 0); // [time: 590ns -> 610ns] - read(15, 67108875, 3211316809, 0); // [time: 610ns -> 630ns] - read(15, 67108876, 3236997651, 0); // [time: 630ns -> 650ns] - read(15, 67108877, 3369414426, 0); // [time: 650ns -> 670ns] - read(15, 67108878, 3866725828, 0); // [time: 670ns -> 690ns] - read(15, 67108879, 2882616058, 0); // [time: 690ns -> 710ns] - read(15, 67108880, 3738458232, 0); // [time: 710ns -> 730ns] - reset(); // [time: 770.001ns -> 780.001ns] - reset(); // [time: 780.001ns -> 790.001ns] - reset(); // [time: 790.001ns -> 800.001ns] - write(15, 67108865, 2558870979, 0); // [time: 840.001ns -> 860.001ns] - write(15, 67108866, 3310254824, 0); // [time: 860.001ns -> 880.001ns] - write(15, 67108867, 3635210891, 0); // [time: 880.001ns -> 900.001ns] - write(15, 67108868, 2844952514, 0); // [time: 900.001ns -> 920.001ns] - write(15, 67108869, 2293386100, 0); // [time: 920.001ns -> 940.001ns] - write(15, 67108870, 3615462605, 0); // [time: 940.001ns -> 960.001ns] - write(15, 67108871, 3569010089, 0); // [time: 960.001ns -> 980.001ns] - write(15, 67108872, 3520072258, 0); // [time: 980.001ns -> 1000.001ns] - write(15, 67108873, 3002516588, 0); // [time: 1000.001ns -> 1020.001ns] - write(15, 67108874, 3681389096, 0); // [time: 1020.001ns -> 1040.001ns] - write(15, 67108875, 2924663556, 0); // [time: 1040.001ns -> 1060.001ns] - write(15, 67108876, 3055297102, 0); // [time: 1060.001ns -> 1080.001ns] - write(15, 67108877, 4177639544, 0); // [time: 1080.001ns -> 1100.001ns] - write(15, 67108878, 3526172361, 0); // [time: 1100.001ns -> 1120.001ns] - write(15, 67108879, 2564412332, 0); // [time: 1120.001ns -> 1140.001ns] - write(15, 67108880, 4210875098, 0); // [time: 1140.001ns -> 1160.001ns] -} diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_16_8.monitor.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_16_8.monitor.expect deleted file mode 100644 index cb71ef95..00000000 --- a/tests/antmicro/sram_classic/expects/test_sram_classic_16_8.monitor.expect +++ /dev/null @@ -1,41 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108866, 3622568730, 0); // [time: 410ns -> 430ns] - read(15, 67108867, 3538707329, 0); // [time: 430ns -> 450ns] - read(15, 67108868, 3440721235, 0); // [time: 450ns -> 470ns] - read(15, 67108869, 3191204602, 0); // [time: 470ns -> 490ns] - read(15, 67108870, 4084986393, 0); // [time: 490ns -> 510ns] - read(15, 67108871, 3446247256, 0); // [time: 510ns -> 530ns] - read(15, 67108872, 3908428032, 0); // [time: 530ns -> 550ns] - read(15, 67108873, 2315046581, 0); // [time: 550ns -> 570ns] - read(15, 67108874, 2780682871, 0); // [time: 570ns -> 590ns] - read(15, 67108875, 3026674647, 0); // [time: 590ns -> 610ns] - read(15, 67108876, 2376933607, 0); // [time: 610ns -> 630ns] - read(15, 67108877, 2436105964, 0); // [time: 630ns -> 650ns] - read(15, 67108878, 3222378968, 0); // [time: 650ns -> 670ns] - read(15, 67108879, 3310323703, 0); // [time: 670ns -> 690ns] - read(15, 67108880, 2550879638, 0); // [time: 690ns -> 710ns] - read(15, 67108881, 3261802111, 0); // [time: 710ns -> 730ns] - reset(); // [time: 770.001ns -> 780.001ns] - reset(); // [time: 780.001ns -> 790.001ns] - reset(); // [time: 790.001ns -> 800.001ns] - write(15, 67108866, 2711682730, 0); // [time: 840.001ns -> 860.001ns] - write(15, 67108867, 4230444125, 0); // [time: 860.001ns -> 880.001ns] - write(15, 67108868, 2579425060, 0); // [time: 880.001ns -> 900.001ns] - write(15, 67108869, 2991027419, 0); // [time: 900.001ns -> 920.001ns] - write(15, 67108870, 2417255467, 0); // [time: 920.001ns -> 940.001ns] - write(15, 67108871, 4045742383, 0); // [time: 940.001ns -> 960.001ns] - write(15, 67108872, 2931778361, 0); // [time: 960.001ns -> 980.001ns] - write(15, 67108873, 3640821048, 0); // [time: 980.001ns -> 1000.001ns] - write(15, 67108874, 3663784812, 0); // [time: 1000.001ns -> 1020.001ns] - write(15, 67108875, 3627233541, 0); // [time: 1020.001ns -> 1040.001ns] - write(15, 67108876, 2459429013, 0); // [time: 1040.001ns -> 1060.001ns] - write(15, 67108877, 4213999775, 0); // [time: 1060.001ns -> 1080.001ns] - write(15, 67108878, 2215241682, 0); // [time: 1080.001ns -> 1100.001ns] - write(15, 67108879, 3801611658, 0); // [time: 1100.001ns -> 1120.001ns] - write(15, 67108880, 2471241936, 0); // [time: 1120.001ns -> 1140.001ns] - write(15, 67108881, 2691314341, 0); // [time: 1140.001ns -> 1160.001ns] -} diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_1_0.monitor.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_1_0.monitor.expect deleted file mode 100644 index 5eaf9412..00000000 --- a/tests/antmicro/sram_classic/expects/test_sram_classic_1_0.monitor.expect +++ /dev/null @@ -1,11 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108864, 2993300090, 0); // [time: 110ns -> 130ns] - reset(); // [time: 170.001ns -> 180.001ns] - reset(); // [time: 180.001ns -> 190.001ns] - reset(); // [time: 190.001ns -> 200.001ns] - write(15, 67108864, 3921107982, 0); // [time: 240.001ns -> 260.001ns] -} diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_1_12.monitor.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_1_12.monitor.expect deleted file mode 100644 index d429b3d6..00000000 --- a/tests/antmicro/sram_classic/expects/test_sram_classic_1_12.monitor.expect +++ /dev/null @@ -1,11 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108867, 3946442578, 0); // [time: 110ns -> 130ns] - reset(); // [time: 170.001ns -> 180.001ns] - reset(); // [time: 180.001ns -> 190.001ns] - reset(); // [time: 190.001ns -> 200.001ns] - write(15, 67108867, 2796792514, 0); // [time: 240.001ns -> 260.001ns] -} diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_1_4.monitor.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_1_4.monitor.expect deleted file mode 100644 index a626949a..00000000 --- a/tests/antmicro/sram_classic/expects/test_sram_classic_1_4.monitor.expect +++ /dev/null @@ -1,11 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108865, 2993300090, 0); // [time: 110ns -> 130ns] - reset(); // [time: 170.001ns -> 180.001ns] - reset(); // [time: 180.001ns -> 190.001ns] - reset(); // [time: 190.001ns -> 200.001ns] - write(15, 67108865, 3921107982, 0); // [time: 240.001ns -> 260.001ns] -} diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_1_8.monitor.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_1_8.monitor.expect deleted file mode 100644 index c1285b74..00000000 --- a/tests/antmicro/sram_classic/expects/test_sram_classic_1_8.monitor.expect +++ /dev/null @@ -1,11 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108866, 3946442578, 0); // [time: 110ns -> 130ns] - reset(); // [time: 170.001ns -> 180.001ns] - reset(); // [time: 180.001ns -> 190.001ns] - reset(); // [time: 190.001ns -> 200.001ns] - write(15, 67108866, 2796792514, 0); // [time: 240.001ns -> 260.001ns] -} diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_2_0.monitor.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_2_0.monitor.expect deleted file mode 100644 index de5ee088..00000000 --- a/tests/antmicro/sram_classic/expects/test_sram_classic_2_0.monitor.expect +++ /dev/null @@ -1,13 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108864, 3622568730, 0); // [time: 130ns -> 150ns] - read(15, 67108865, 3538707329, 0); // [time: 150ns -> 170ns] - reset(); // [time: 210.001ns -> 220.001ns] - reset(); // [time: 220.001ns -> 230.001ns] - reset(); // [time: 230.001ns -> 240.001ns] - write(15, 67108864, 3440721235, 0); // [time: 280.001ns -> 300.001ns] - write(15, 67108865, 3191204602, 0); // [time: 300.001ns -> 320.001ns] -} diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_2_12.monitor.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_2_12.monitor.expect deleted file mode 100644 index 3871f1f8..00000000 --- a/tests/antmicro/sram_classic/expects/test_sram_classic_2_12.monitor.expect +++ /dev/null @@ -1,13 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108867, 2993300090, 0); // [time: 130ns -> 150ns] - read(15, 67108868, 3921107982, 0); // [time: 150ns -> 170ns] - reset(); // [time: 210.001ns -> 220.001ns] - reset(); // [time: 220.001ns -> 230.001ns] - reset(); // [time: 230.001ns -> 240.001ns] - write(15, 67108867, 2480359279, 0); // [time: 280.001ns -> 300.001ns] - write(15, 67108868, 3789792143, 0); // [time: 300.001ns -> 320.001ns] -} diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_2_4.monitor.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_2_4.monitor.expect deleted file mode 100644 index 1a5c670e..00000000 --- a/tests/antmicro/sram_classic/expects/test_sram_classic_2_4.monitor.expect +++ /dev/null @@ -1,13 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108865, 3622568730, 0); // [time: 130ns -> 150ns] - read(15, 67108866, 3538707329, 0); // [time: 150ns -> 170ns] - reset(); // [time: 210.001ns -> 220.001ns] - reset(); // [time: 220.001ns -> 230.001ns] - reset(); // [time: 230.001ns -> 240.001ns] - write(15, 67108865, 3440721235, 0); // [time: 280.001ns -> 300.001ns] - write(15, 67108866, 3191204602, 0); // [time: 300.001ns -> 320.001ns] -} diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_2_8.monitor.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_2_8.monitor.expect deleted file mode 100644 index 17d7651a..00000000 --- a/tests/antmicro/sram_classic/expects/test_sram_classic_2_8.monitor.expect +++ /dev/null @@ -1,13 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108866, 3250481594, 0); // [time: 130ns -> 150ns] - read(15, 67108867, 2390763695, 0); // [time: 150ns -> 170ns] - reset(); // [time: 210.001ns -> 220.001ns] - reset(); // [time: 220.001ns -> 230.001ns] - reset(); // [time: 230.001ns -> 240.001ns] - write(15, 67108866, 4197550477, 0); // [time: 280.001ns -> 300.001ns] - write(15, 67108867, 2445792994, 0); // [time: 300.001ns -> 320.001ns] -} diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_4_0.monitor.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_4_0.monitor.expect deleted file mode 100644 index 5ad819ac..00000000 --- a/tests/antmicro/sram_classic/expects/test_sram_classic_4_0.monitor.expect +++ /dev/null @@ -1,17 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108864, 2993300090, 0); // [time: 170ns -> 190ns] - read(15, 67108865, 3921107982, 0); // [time: 190ns -> 210ns] - read(15, 67108866, 2480359279, 0); // [time: 210ns -> 230ns] - read(15, 67108867, 3789792143, 0); // [time: 230ns -> 250ns] - reset(); // [time: 290.001ns -> 300.001ns] - reset(); // [time: 300.001ns -> 310.001ns] - reset(); // [time: 310.001ns -> 320.001ns] - write(15, 67108864, 2250616272, 0); // [time: 360.001ns -> 380.001ns] - write(15, 67108865, 3654263702, 0); // [time: 380.001ns -> 400.001ns] - write(15, 67108866, 2773364137, 0); // [time: 400.001ns -> 420.001ns] - write(15, 67108867, 2521253772, 0); // [time: 420.001ns -> 440.001ns] -} diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_4_12.monitor.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_4_12.monitor.expect deleted file mode 100644 index 961f4bc4..00000000 --- a/tests/antmicro/sram_classic/expects/test_sram_classic_4_12.monitor.expect +++ /dev/null @@ -1,17 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108867, 3622568730, 0); // [time: 170ns -> 190ns] - read(15, 67108868, 3538707329, 0); // [time: 190ns -> 210ns] - read(15, 67108869, 3440721235, 0); // [time: 210ns -> 230ns] - read(15, 67108870, 3191204602, 0); // [time: 230ns -> 250ns] - reset(); // [time: 290.001ns -> 300.001ns] - reset(); // [time: 300.001ns -> 310.001ns] - reset(); // [time: 310.001ns -> 320.001ns] - write(15, 67108867, 4084986393, 0); // [time: 360.001ns -> 380.001ns] - write(15, 67108868, 3446247256, 0); // [time: 380.001ns -> 400.001ns] - write(15, 67108869, 3908428032, 0); // [time: 400.001ns -> 420.001ns] - write(15, 67108870, 2315046581, 0); // [time: 420.001ns -> 440.001ns] -} diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_4_4.monitor.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_4_4.monitor.expect deleted file mode 100644 index e1428e90..00000000 --- a/tests/antmicro/sram_classic/expects/test_sram_classic_4_4.monitor.expect +++ /dev/null @@ -1,17 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108865, 3946442578, 0); // [time: 170ns -> 190ns] - read(15, 67108866, 2796792514, 0); // [time: 190ns -> 210ns] - read(15, 67108867, 3312914512, 0); // [time: 210ns -> 230ns] - read(15, 67108868, 4292142820, 0); // [time: 230ns -> 250ns] - reset(); // [time: 290.001ns -> 300.001ns] - reset(); // [time: 300.001ns -> 310.001ns] - reset(); // [time: 310.001ns -> 320.001ns] - write(15, 67108865, 3525794570, 0); // [time: 360.001ns -> 380.001ns] - write(15, 67108866, 2961047623, 0); // [time: 380.001ns -> 400.001ns] - write(15, 67108867, 4249856274, 0); // [time: 400.001ns -> 420.001ns] - write(15, 67108868, 3405678304, 0); // [time: 420.001ns -> 440.001ns] -} diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_4_8.monitor.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_4_8.monitor.expect deleted file mode 100644 index 01877415..00000000 --- a/tests/antmicro/sram_classic/expects/test_sram_classic_4_8.monitor.expect +++ /dev/null @@ -1,17 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108866, 3946442578, 0); // [time: 170ns -> 190ns] - read(15, 67108867, 2796792514, 0); // [time: 190ns -> 210ns] - read(15, 67108868, 3312914512, 0); // [time: 210ns -> 230ns] - read(15, 67108869, 4292142820, 0); // [time: 230ns -> 250ns] - reset(); // [time: 290.001ns -> 300.001ns] - reset(); // [time: 300.001ns -> 310.001ns] - reset(); // [time: 310.001ns -> 320.001ns] - write(15, 67108866, 3525794570, 0); // [time: 360.001ns -> 380.001ns] - write(15, 67108867, 2961047623, 0); // [time: 380.001ns -> 400.001ns] - write(15, 67108868, 4249856274, 0); // [time: 400.001ns -> 420.001ns] - write(15, 67108869, 3405678304, 0); // [time: 420.001ns -> 440.001ns] -} diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_8_0.monitor.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_8_0.monitor.expect deleted file mode 100644 index 36649517..00000000 --- a/tests/antmicro/sram_classic/expects/test_sram_classic_8_0.monitor.expect +++ /dev/null @@ -1,25 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108864, 3622568730, 0); // [time: 250ns -> 270ns] - read(15, 67108865, 3538707329, 0); // [time: 270ns -> 290ns] - read(15, 67108866, 3440721235, 0); // [time: 290ns -> 310ns] - read(15, 67108867, 3191204602, 0); // [time: 310ns -> 330ns] - read(15, 67108868, 4084986393, 0); // [time: 330ns -> 350ns] - read(15, 67108869, 3446247256, 0); // [time: 350ns -> 370ns] - read(15, 67108870, 3908428032, 0); // [time: 370ns -> 390ns] - read(15, 67108871, 2315046581, 0); // [time: 390ns -> 410ns] - reset(); // [time: 450.001ns -> 460.001ns] - reset(); // [time: 460.001ns -> 470.001ns] - reset(); // [time: 470.001ns -> 480.001ns] - write(15, 67108864, 2780682871, 0); // [time: 520.001ns -> 540.001ns] - write(15, 67108865, 3026674647, 0); // [time: 540.001ns -> 560.001ns] - write(15, 67108866, 2376933607, 0); // [time: 560.001ns -> 580.001ns] - write(15, 67108867, 2436105964, 0); // [time: 580.001ns -> 600.001ns] - write(15, 67108868, 3222378968, 0); // [time: 600.001ns -> 620.001ns] - write(15, 67108869, 3310323703, 0); // [time: 620.001ns -> 640.001ns] - write(15, 67108870, 2550879638, 0); // [time: 640.001ns -> 660.001ns] - write(15, 67108871, 3261802111, 0); // [time: 660.001ns -> 680.001ns] -} diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_8_12.monitor.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_8_12.monitor.expect deleted file mode 100644 index b7f411ee..00000000 --- a/tests/antmicro/sram_classic/expects/test_sram_classic_8_12.monitor.expect +++ /dev/null @@ -1,25 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108867, 2993300090, 0); // [time: 250ns -> 270ns] - read(15, 67108868, 3921107982, 0); // [time: 270ns -> 290ns] - read(15, 67108869, 2480359279, 0); // [time: 290ns -> 310ns] - read(15, 67108870, 3789792143, 0); // [time: 310ns -> 330ns] - read(15, 67108871, 2250616272, 0); // [time: 330ns -> 350ns] - read(15, 67108872, 3654263702, 0); // [time: 350ns -> 370ns] - read(15, 67108873, 2773364137, 0); // [time: 370ns -> 390ns] - read(15, 67108874, 2521253772, 0); // [time: 390ns -> 410ns] - reset(); // [time: 450.001ns -> 460.001ns] - reset(); // [time: 460.001ns -> 470.001ns] - reset(); // [time: 470.001ns -> 480.001ns] - write(15, 67108867, 2521411224, 0); // [time: 520.001ns -> 540.001ns] - write(15, 67108868, 2219799945, 0); // [time: 540.001ns -> 560.001ns] - write(15, 67108869, 3487354134, 0); // [time: 560.001ns -> 580.001ns] - write(15, 67108870, 2235755512, 0); // [time: 580.001ns -> 600.001ns] - write(15, 67108871, 2319980602, 0); // [time: 600.001ns -> 620.001ns] - write(15, 67108872, 2978178103, 0); // [time: 620.001ns -> 640.001ns] - write(15, 67108873, 2464653045, 0); // [time: 640.001ns -> 660.001ns] - write(15, 67108874, 2202449462, 0); // [time: 660.001ns -> 680.001ns] -} diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_8_4.monitor.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_8_4.monitor.expect deleted file mode 100644 index 9e2e1b4f..00000000 --- a/tests/antmicro/sram_classic/expects/test_sram_classic_8_4.monitor.expect +++ /dev/null @@ -1,25 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108865, 3250481594, 0); // [time: 250ns -> 270ns] - read(15, 67108866, 2390763695, 0); // [time: 270ns -> 290ns] - read(15, 67108867, 4197550477, 0); // [time: 290ns -> 310ns] - read(15, 67108868, 2445792994, 0); // [time: 310ns -> 330ns] - read(15, 67108869, 3897454712, 0); // [time: 330ns -> 350ns] - read(15, 67108870, 3326339601, 0); // [time: 350ns -> 370ns] - read(15, 67108871, 3190747046, 0); // [time: 370ns -> 390ns] - read(15, 67108872, 2329522371, 0); // [time: 390ns -> 410ns] - reset(); // [time: 450.001ns -> 460.001ns] - reset(); // [time: 460.001ns -> 470.001ns] - reset(); // [time: 470.001ns -> 480.001ns] - write(15, 67108865, 2252821017, 0); // [time: 520.001ns -> 540.001ns] - write(15, 67108866, 2931126915, 0); // [time: 540.001ns -> 560.001ns] - write(15, 67108867, 2608883160, 0); // [time: 560.001ns -> 580.001ns] - write(15, 67108868, 4233362437, 0); // [time: 580.001ns -> 600.001ns] - write(15, 67108869, 2517580333, 0); // [time: 600.001ns -> 620.001ns] - write(15, 67108870, 2583768976, 0); // [time: 620.001ns -> 640.001ns] - write(15, 67108871, 2451763371, 0); // [time: 640.001ns -> 660.001ns] - write(15, 67108872, 2672364833, 0); // [time: 660.001ns -> 680.001ns] -} diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_8_8.monitor.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_8_8.monitor.expect deleted file mode 100644 index 1347d8fd..00000000 --- a/tests/antmicro/sram_classic/expects/test_sram_classic_8_8.monitor.expect +++ /dev/null @@ -1,25 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108866, 2993300090, 0); // [time: 250ns -> 270ns] - read(15, 67108867, 3921107982, 0); // [time: 270ns -> 290ns] - read(15, 67108868, 2480359279, 0); // [time: 290ns -> 310ns] - read(15, 67108869, 3789792143, 0); // [time: 310ns -> 330ns] - read(15, 67108870, 2250616272, 0); // [time: 330ns -> 350ns] - read(15, 67108871, 3654263702, 0); // [time: 350ns -> 370ns] - read(15, 67108872, 2773364137, 0); // [time: 370ns -> 390ns] - read(15, 67108873, 2521253772, 0); // [time: 390ns -> 410ns] - reset(); // [time: 450.001ns -> 460.001ns] - reset(); // [time: 460.001ns -> 470.001ns] - reset(); // [time: 470.001ns -> 480.001ns] - write(15, 67108866, 2521411224, 0); // [time: 520.001ns -> 540.001ns] - write(15, 67108867, 2219799945, 0); // [time: 540.001ns -> 560.001ns] - write(15, 67108868, 3487354134, 0); // [time: 560.001ns -> 580.001ns] - write(15, 67108869, 2235755512, 0); // [time: 580.001ns -> 600.001ns] - write(15, 67108870, 2319980602, 0); // [time: 600.001ns -> 620.001ns] - write(15, 67108871, 2978178103, 0); // [time: 620.001ns -> 640.001ns] - write(15, 67108872, 2464653045, 0); // [time: 640.001ns -> 660.001ns] - write(15, 67108873, 2202449462, 0); // [time: 660.001ns -> 680.001ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_0_0.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_0_0.monitor.expect deleted file mode 100644 index d079ea48..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_0_0.monitor.expect +++ /dev/null @@ -1,61 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108864, 1016512136, 0); // [time: 410ns -> 430ns] - read(15, 67108865, 226204128, 0); // [time: 430ns -> 440ns] - read(15, 67108866, 2116565440, 0); // [time: 440ns -> 450ns] - read(15, 67108867, 2153688786, 0); // [time: 450ns -> 460ns] - read(15, 67108868, 1974223269, 0); // [time: 460ns -> 470ns] - read(15, 67108869, 1053640572, 0); // [time: 470ns -> 480ns] - read(15, 67108870, 2079860600, 0); // [time: 480ns -> 490ns] - read(15, 67108871, 3550045624, 0); // [time: 490ns -> 500ns] - read(15, 67108872, 1038322047, 0); // [time: 500ns -> 510ns] - read(15, 67108873, 1502718053, 0); // [time: 510ns -> 520ns] - read(15, 67108874, 1367070343, 0); // [time: 520ns -> 530ns] - read(15, 67108875, 3425882885, 0); // [time: 530ns -> 540ns] - read(15, 67108876, 1614916721, 0); // [time: 540ns -> 550ns] - read(15, 67108877, 3041346437, 0); // [time: 550ns -> 560ns] - read(15, 67108878, 3665993952, 0); // [time: 560ns -> 570ns] - read(15, 67108879, 3560581876, 0); // [time: 570ns -> 580ns] - reset(); // [time: 620.001ns -> 630.001ns] - reset(); // [time: 630.001ns -> 640.001ns] - reset(); // [time: 640.001ns -> 650.001ns] - write(15, 67108864, 3433786972, 0); // [time: 690.001ns -> 710.001ns] - write(15, 67108865, 3840560806, 0); // [time: 710.001ns -> 720.001ns] - write(15, 67108866, 3225552468, 0); // [time: 720.001ns -> 730.001ns] - write(15, 67108867, 3717810263, 0); // [time: 730.001ns -> 740.001ns] - write(15, 67108868, 3317657198, 0); // [time: 740.001ns -> 750.001ns] - write(15, 67108869, 1024069544, 0); // [time: 750.001ns -> 760.001ns] - write(15, 67108870, 1752245362, 0); // [time: 760.001ns -> 770.001ns] - write(15, 67108871, 1579776374, 0); // [time: 770.001ns -> 780.001ns] - write(15, 67108872, 904253205, 0); // [time: 780.001ns -> 790.001ns] - write(15, 67108873, 1728285430, 0); // [time: 790.001ns -> 800.001ns] - write(15, 67108874, 91066718, 0); // [time: 800.001ns -> 810.001ns] - write(15, 67108875, 1402442819, 0); // [time: 810.001ns -> 820.001ns] - write(15, 67108876, 4062122226, 0); // [time: 820.001ns -> 830.001ns] - write(15, 67108877, 1191921998, 0); // [time: 830.001ns -> 840.001ns] - write(15, 67108878, 1249541889, 0); // [time: 840.001ns -> 850.001ns] - write(15, 67108879, 2580891116, 0); // [time: 850.001ns -> 860.001ns] - reset(); // [time: 1540.002ns -> 1550.002ns] - reset(); // [time: 1550.002ns -> 1560.002ns] - reset(); // [time: 1560.002ns -> 1570.002ns] - write(15, 67108864, 1526706340, 0); // [time: 1610.002ns -> 1630.002ns] - write(15, 67108865, 1162262173, 0); // [time: 1630.002ns -> 1640.002ns] - write(15, 67108866, 3667501502, 0); // [time: 1640.002ns -> 1650.002ns] - write(15, 67108867, 617255735, 0); // [time: 1650.002ns -> 1660.002ns] - write(15, 67108868, 4077356414, 0); // [time: 1660.002ns -> 1670.002ns] - write(15, 67108869, 1593609662, 0); // [time: 1670.002ns -> 1680.002ns] - write(15, 67108870, 2148292499, 0); // [time: 1680.002ns -> 1690.002ns] - write(15, 67108871, 3403556849, 0); // [time: 1690.002ns -> 1700.002ns] - write(15, 67108872, 3331963440, 0); // [time: 1700.002ns -> 1710.002ns] - write(15, 67108873, 1493302995, 0); // [time: 1710.002ns -> 1720.002ns] - write(15, 67108874, 2710958922, 0); // [time: 1720.002ns -> 1730.002ns] - write(15, 67108875, 4029972623, 0); // [time: 1730.002ns -> 1740.002ns] - write(15, 67108876, 2845272388, 0); // [time: 1740.002ns -> 1750.002ns] - write(15, 67108877, 70166840, 0); // [time: 1750.002ns -> 1760.002ns] - write(15, 67108878, 1323291936, 0); // [time: 1760.002ns -> 1770.002ns] - write(15, 67108879, 916783944, 0); // [time: 1770.002ns -> 1780.002ns] - read(15, 67108864, 1526706340, 0); // [time: 1780.002ns -> 1800.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_0_1.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_0_1.monitor.expect deleted file mode 100644 index fcc2c6dc..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_0_1.monitor.expect +++ /dev/null @@ -1,61 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108864, 518534189, 0); // [time: 410ns -> 430ns] - read(15, 67108865, 844695266, 0); // [time: 430ns -> 440ns] - read(15, 67108866, 3937184150, 0); // [time: 440ns -> 450ns] - read(15, 67108867, 444246851, 0); // [time: 450ns -> 460ns] - read(15, 67108868, 3220682802, 0); // [time: 460ns -> 470ns] - read(15, 67108869, 2130811954, 0); // [time: 470ns -> 480ns] - read(15, 67108870, 2002127438, 0); // [time: 480ns -> 490ns] - read(15, 67108871, 493792053, 0); // [time: 490ns -> 500ns] - read(15, 67108872, 63714206, 0); // [time: 500ns -> 510ns] - read(15, 67108873, 2091823691, 0); // [time: 510ns -> 520ns] - read(15, 67108874, 3903276977, 0); // [time: 520ns -> 530ns] - read(15, 67108875, 1662756337, 0); // [time: 530ns -> 540ns] - read(15, 67108876, 4101310419, 0); // [time: 540ns -> 550ns] - read(15, 67108877, 903798156, 0); // [time: 550ns -> 560ns] - read(15, 67108878, 3840476340, 0); // [time: 560ns -> 570ns] - read(15, 67108879, 2244097975, 0); // [time: 570ns -> 580ns] - reset(); // [time: 620.001ns -> 630.001ns] - reset(); // [time: 630.001ns -> 640.001ns] - reset(); // [time: 640.001ns -> 650.001ns] - write(15, 67108864, 3956643922, 0); // [time: 690.001ns -> 710.001ns] - write(15, 67108865, 2115347845, 0); // [time: 710.001ns -> 720.001ns] - write(15, 67108866, 1775201107, 0); // [time: 720.001ns -> 730.001ns] - write(15, 67108867, 1046910518, 0); // [time: 730.001ns -> 740.001ns] - write(15, 67108868, 345998276, 0); // [time: 740.001ns -> 750.001ns] - write(15, 67108869, 2089777588, 0); // [time: 750.001ns -> 760.001ns] - write(15, 67108870, 3110941387, 0); // [time: 760.001ns -> 770.001ns] - write(15, 67108871, 3151493219, 0); // [time: 770.001ns -> 780.001ns] - write(15, 67108872, 1789821109, 0); // [time: 780.001ns -> 790.001ns] - write(15, 67108873, 976504712, 0); // [time: 790.001ns -> 800.001ns] - write(15, 67108874, 3716648277, 0); // [time: 800.001ns -> 810.001ns] - write(15, 67108875, 3764578858, 0); // [time: 810.001ns -> 820.001ns] - write(15, 67108876, 2575976733, 0); // [time: 820.001ns -> 830.001ns] - write(15, 67108877, 2758477517, 0); // [time: 830.001ns -> 840.001ns] - write(15, 67108878, 801284123, 0); // [time: 840.001ns -> 850.001ns] - write(15, 67108879, 1745171602, 0); // [time: 850.001ns -> 860.001ns] - reset(); // [time: 1540.002ns -> 1550.002ns] - reset(); // [time: 1550.002ns -> 1560.002ns] - reset(); // [time: 1560.002ns -> 1570.002ns] - write(15, 67108864, 2836493204, 0); // [time: 1610.002ns -> 1630.002ns] - write(15, 67108865, 3265525290, 0); // [time: 1630.002ns -> 1640.002ns] - write(15, 67108866, 2395253012, 0); // [time: 1640.002ns -> 1650.002ns] - write(15, 67108867, 3557189713, 0); // [time: 1650.002ns -> 1660.002ns] - write(15, 67108868, 764605320, 0); // [time: 1660.002ns -> 1670.002ns] - write(15, 67108869, 2679315363, 0); // [time: 1670.002ns -> 1680.002ns] - write(15, 67108870, 375184876, 0); // [time: 1680.002ns -> 1690.002ns] - write(15, 67108871, 4121117117, 0); // [time: 1690.002ns -> 1700.002ns] - write(15, 67108872, 1446110016, 0); // [time: 1700.002ns -> 1710.002ns] - write(15, 67108873, 3729875561, 0); // [time: 1710.002ns -> 1720.002ns] - write(15, 67108874, 2582294219, 0); // [time: 1720.002ns -> 1730.002ns] - write(15, 67108875, 409432939, 0); // [time: 1730.002ns -> 1740.002ns] - write(15, 67108876, 937977575, 0); // [time: 1740.002ns -> 1750.002ns] - write(15, 67108877, 1981138244, 0); // [time: 1750.002ns -> 1760.002ns] - write(15, 67108878, 2912031569, 0); // [time: 1760.002ns -> 1770.002ns] - write(15, 67108879, 896776296, 0); // [time: 1770.002ns -> 1780.002ns] - read(15, 67108864, 2836493204, 0); // [time: 1780.002ns -> 1800.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_0_2.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_0_2.monitor.expect deleted file mode 100644 index 6f08eae7..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_0_2.monitor.expect +++ /dev/null @@ -1,61 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108864, 3495738447, 0); // [time: 410ns -> 430ns] - read(15, 67108865, 1478546475, 0); // [time: 430ns -> 440ns] - read(15, 67108866, 2041778918, 0); // [time: 440ns -> 450ns] - read(15, 67108867, 3032895213, 0); // [time: 450ns -> 460ns] - read(15, 67108868, 2020268309, 0); // [time: 460ns -> 470ns] - read(15, 67108869, 3122719830, 0); // [time: 470ns -> 480ns] - read(15, 67108870, 3806053567, 0); // [time: 480ns -> 490ns] - read(15, 67108871, 3858565026, 0); // [time: 490ns -> 500ns] - read(15, 67108872, 880624971, 0); // [time: 500ns -> 510ns] - read(15, 67108873, 2554056607, 0); // [time: 510ns -> 520ns] - read(15, 67108874, 1441832696, 0); // [time: 520ns -> 530ns] - read(15, 67108875, 479445740, 0); // [time: 530ns -> 540ns] - read(15, 67108876, 2229265910, 0); // [time: 540ns -> 550ns] - read(15, 67108877, 788973880, 0); // [time: 550ns -> 560ns] - read(15, 67108878, 3880977277, 0); // [time: 560ns -> 570ns] - read(15, 67108879, 4096708504, 0); // [time: 570ns -> 580ns] - reset(); // [time: 620.001ns -> 630.001ns] - reset(); // [time: 630.001ns -> 640.001ns] - reset(); // [time: 640.001ns -> 650.001ns] - write(15, 67108864, 2427636421, 0); // [time: 690.001ns -> 710.001ns] - write(15, 67108865, 3595099675, 0); // [time: 710.001ns -> 720.001ns] - write(15, 67108866, 2668681316, 0); // [time: 720.001ns -> 730.001ns] - write(15, 67108867, 1679837987, 0); // [time: 730.001ns -> 740.001ns] - write(15, 67108868, 924732013, 0); // [time: 740.001ns -> 750.001ns] - write(15, 67108869, 2192079403, 0); // [time: 750.001ns -> 760.001ns] - write(15, 67108870, 2042051660, 0); // [time: 760.001ns -> 770.001ns] - write(15, 67108871, 989927686, 0); // [time: 770.001ns -> 780.001ns] - write(15, 67108872, 3067406900, 0); // [time: 780.001ns -> 790.001ns] - write(15, 67108873, 1058215073, 0); // [time: 790.001ns -> 800.001ns] - write(15, 67108874, 365012335, 0); // [time: 800.001ns -> 810.001ns] - write(15, 67108875, 687295108, 0); // [time: 810.001ns -> 820.001ns] - write(15, 67108876, 2829218573, 0); // [time: 820.001ns -> 830.001ns] - write(15, 67108877, 1448409262, 0); // [time: 830.001ns -> 840.001ns] - write(15, 67108878, 400594486, 0); // [time: 840.001ns -> 850.001ns] - write(15, 67108879, 4177343116, 0); // [time: 850.001ns -> 860.001ns] - reset(); // [time: 1540.002ns -> 1550.002ns] - reset(); // [time: 1550.002ns -> 1560.002ns] - reset(); // [time: 1560.002ns -> 1570.002ns] - write(15, 67108864, 2304668716, 0); // [time: 1610.002ns -> 1630.002ns] - write(15, 67108865, 2610611482, 0); // [time: 1630.002ns -> 1640.002ns] - write(15, 67108866, 1468153982, 0); // [time: 1640.002ns -> 1650.002ns] - write(15, 67108867, 1169841342, 0); // [time: 1650.002ns -> 1660.002ns] - write(15, 67108868, 27036823, 0); // [time: 1660.002ns -> 1670.002ns] - write(15, 67108869, 73783758, 0); // [time: 1670.002ns -> 1680.002ns] - write(15, 67108870, 1621524717, 0); // [time: 1680.002ns -> 1690.002ns] - write(15, 67108871, 3905946412, 0); // [time: 1690.002ns -> 1700.002ns] - write(15, 67108872, 1563100034, 0); // [time: 1700.002ns -> 1710.002ns] - write(15, 67108873, 2069336907, 0); // [time: 1710.002ns -> 1720.002ns] - write(15, 67108874, 583373053, 0); // [time: 1720.002ns -> 1730.002ns] - write(15, 67108875, 3629920426, 0); // [time: 1730.002ns -> 1740.002ns] - write(15, 67108876, 2146122704, 0); // [time: 1740.002ns -> 1750.002ns] - write(15, 67108877, 2674258699, 0); // [time: 1750.002ns -> 1760.002ns] - write(15, 67108878, 1361676606, 0); // [time: 1760.002ns -> 1770.002ns] - write(15, 67108879, 2435452493, 0); // [time: 1770.002ns -> 1780.002ns] - read(15, 67108864, 2304668716, 0); // [time: 1780.002ns -> 1800.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_0_3.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_0_3.monitor.expect deleted file mode 100644 index d1d6d833..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_0_3.monitor.expect +++ /dev/null @@ -1,61 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108864, 1070372987, 0); // [time: 410ns -> 430ns] - read(15, 67108865, 2645947069, 0); // [time: 430ns -> 440ns] - read(15, 67108866, 736643984, 0); // [time: 440ns -> 450ns] - read(15, 67108867, 192007203, 0); // [time: 450ns -> 460ns] - read(15, 67108868, 1925400290, 0); // [time: 460ns -> 470ns] - read(15, 67108869, 1309609983, 0); // [time: 470ns -> 480ns] - read(15, 67108870, 58503546, 0); // [time: 480ns -> 490ns] - read(15, 67108871, 3861022989, 0); // [time: 490ns -> 500ns] - read(15, 67108872, 1725708128, 0); // [time: 500ns -> 510ns] - read(15, 67108873, 3760744365, 0); // [time: 510ns -> 520ns] - read(15, 67108874, 3803789590, 0); // [time: 520ns -> 530ns] - read(15, 67108875, 2647121574, 0); // [time: 530ns -> 540ns] - read(15, 67108876, 336117328, 0); // [time: 540ns -> 550ns] - read(15, 67108877, 3984726565, 0); // [time: 550ns -> 560ns] - read(15, 67108878, 104808193, 0); // [time: 560ns -> 570ns] - read(15, 67108879, 2315494688, 0); // [time: 570ns -> 580ns] - reset(); // [time: 620.001ns -> 630.001ns] - reset(); // [time: 630.001ns -> 640.001ns] - reset(); // [time: 640.001ns -> 650.001ns] - write(15, 67108864, 3997204021, 0); // [time: 690.001ns -> 710.001ns] - write(15, 67108865, 666660673, 0); // [time: 710.001ns -> 720.001ns] - write(15, 67108866, 3910223084, 0); // [time: 720.001ns -> 730.001ns] - write(15, 67108867, 1271405124, 0); // [time: 730.001ns -> 740.001ns] - write(15, 67108868, 4236388983, 0); // [time: 740.001ns -> 750.001ns] - write(15, 67108869, 1347016890, 0); // [time: 750.001ns -> 760.001ns] - write(15, 67108870, 1337396640, 0); // [time: 760.001ns -> 770.001ns] - write(15, 67108871, 3009712000, 0); // [time: 770.001ns -> 780.001ns] - write(15, 67108872, 2237248361, 0); // [time: 780.001ns -> 790.001ns] - write(15, 67108873, 592560133, 0); // [time: 790.001ns -> 800.001ns] - write(15, 67108874, 371018497, 0); // [time: 800.001ns -> 810.001ns] - write(15, 67108875, 763875626, 0); // [time: 810.001ns -> 820.001ns] - write(15, 67108876, 75174504, 0); // [time: 820.001ns -> 830.001ns] - write(15, 67108877, 2983449782, 0); // [time: 830.001ns -> 840.001ns] - write(15, 67108878, 2295155532, 0); // [time: 840.001ns -> 850.001ns] - write(15, 67108879, 1954643484, 0); // [time: 850.001ns -> 860.001ns] - reset(); // [time: 1540.002ns -> 1550.002ns] - reset(); // [time: 1550.002ns -> 1560.002ns] - reset(); // [time: 1560.002ns -> 1570.002ns] - write(15, 67108864, 409090773, 0); // [time: 1610.002ns -> 1630.002ns] - write(15, 67108865, 1348706589, 0); // [time: 1630.002ns -> 1640.002ns] - write(15, 67108866, 1967918440, 0); // [time: 1640.002ns -> 1650.002ns] - write(15, 67108867, 2636141882, 0); // [time: 1650.002ns -> 1660.002ns] - write(15, 67108868, 533777194, 0); // [time: 1660.002ns -> 1670.002ns] - write(15, 67108869, 2114809607, 0); // [time: 1670.002ns -> 1680.002ns] - write(15, 67108870, 309856382, 0); // [time: 1680.002ns -> 1690.002ns] - write(15, 67108871, 3466848916, 0); // [time: 1690.002ns -> 1700.002ns] - write(15, 67108872, 3043756153, 0); // [time: 1700.002ns -> 1710.002ns] - write(15, 67108873, 2927281001, 0); // [time: 1710.002ns -> 1720.002ns] - write(15, 67108874, 1913699666, 0); // [time: 1720.002ns -> 1730.002ns] - write(15, 67108875, 1847871828, 0); // [time: 1730.002ns -> 1740.002ns] - write(15, 67108876, 3984372107, 0); // [time: 1740.002ns -> 1750.002ns] - write(15, 67108877, 4239907193, 0); // [time: 1750.002ns -> 1760.002ns] - write(15, 67108878, 1427511912, 0); // [time: 1760.002ns -> 1770.002ns] - write(15, 67108879, 277973300, 0); // [time: 1770.002ns -> 1780.002ns] - read(15, 67108864, 409090773, 0); // [time: 1780.002ns -> 1800.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_12_0.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_12_0.monitor.expect deleted file mode 100644 index abbf3eb6..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_12_0.monitor.expect +++ /dev/null @@ -1,61 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108867, 1833423740, 0); // [time: 410ns -> 430ns] - read(15, 67108868, 4073618608, 0); // [time: 430ns -> 440ns] - read(15, 67108869, 3418745219, 0); // [time: 440ns -> 450ns] - read(15, 67108870, 3757272308, 0); // [time: 450ns -> 460ns] - read(15, 67108871, 1325530178, 0); // [time: 460ns -> 470ns] - read(15, 67108872, 1451722922, 0); // [time: 470ns -> 480ns] - read(15, 67108873, 1997677454, 0); // [time: 480ns -> 490ns] - read(15, 67108874, 986005841, 0); // [time: 490ns -> 500ns] - read(15, 67108875, 789975088, 0); // [time: 500ns -> 510ns] - read(15, 67108876, 3746918692, 0); // [time: 510ns -> 520ns] - read(15, 67108877, 410224063, 0); // [time: 520ns -> 530ns] - read(15, 67108878, 864118294, 0); // [time: 530ns -> 540ns] - read(15, 67108879, 908783806, 0); // [time: 540ns -> 550ns] - read(15, 67108880, 2735695332, 0); // [time: 550ns -> 560ns] - read(15, 67108881, 3991830963, 0); // [time: 560ns -> 570ns] - read(15, 67108882, 3613974492, 0); // [time: 570ns -> 580ns] - reset(); // [time: 620.001ns -> 630.001ns] - reset(); // [time: 630.001ns -> 640.001ns] - reset(); // [time: 640.001ns -> 650.001ns] - write(15, 67108867, 1515921225, 0); // [time: 690.001ns -> 710.001ns] - write(15, 67108868, 104974629, 0); // [time: 710.001ns -> 720.001ns] - write(15, 67108869, 966302149, 0); // [time: 720.001ns -> 730.001ns] - write(15, 67108870, 4157870389, 0); // [time: 730.001ns -> 740.001ns] - write(15, 67108871, 2924407148, 0); // [time: 740.001ns -> 750.001ns] - write(15, 67108872, 1538378206, 0); // [time: 750.001ns -> 760.001ns] - write(15, 67108873, 60846013, 0); // [time: 760.001ns -> 770.001ns] - write(15, 67108874, 3809194079, 0); // [time: 770.001ns -> 780.001ns] - write(15, 67108875, 4127502511, 0); // [time: 780.001ns -> 790.001ns] - write(15, 67108876, 4180959758, 0); // [time: 790.001ns -> 800.001ns] - write(15, 67108877, 700566626, 0); // [time: 800.001ns -> 810.001ns] - write(15, 67108878, 2700144653, 0); // [time: 810.001ns -> 820.001ns] - write(15, 67108879, 3999062826, 0); // [time: 820.001ns -> 830.001ns] - write(15, 67108880, 3986108609, 0); // [time: 830.001ns -> 840.001ns] - write(15, 67108881, 447162407, 0); // [time: 840.001ns -> 850.001ns] - write(15, 67108882, 3816483315, 0); // [time: 850.001ns -> 860.001ns] - reset(); // [time: 1540.002ns -> 1550.002ns] - reset(); // [time: 1550.002ns -> 1560.002ns] - reset(); // [time: 1560.002ns -> 1570.002ns] - write(15, 67108867, 1264302217, 0); // [time: 1610.002ns -> 1630.002ns] - write(15, 67108868, 420700447, 0); // [time: 1630.002ns -> 1640.002ns] - write(15, 67108869, 353328025, 0); // [time: 1640.002ns -> 1650.002ns] - write(15, 67108870, 2517418204, 0); // [time: 1650.002ns -> 1660.002ns] - write(15, 67108871, 1410989455, 0); // [time: 1660.002ns -> 1670.002ns] - write(15, 67108872, 2070630692, 0); // [time: 1670.002ns -> 1680.002ns] - write(15, 67108873, 1509701018, 0); // [time: 1680.002ns -> 1690.002ns] - write(15, 67108874, 2805925831, 0); // [time: 1690.002ns -> 1700.002ns] - write(15, 67108875, 1828261736, 0); // [time: 1700.002ns -> 1710.002ns] - write(15, 67108876, 865271992, 0); // [time: 1710.002ns -> 1720.002ns] - write(15, 67108877, 3589189654, 0); // [time: 1720.002ns -> 1730.002ns] - write(15, 67108878, 2111939367, 0); // [time: 1730.002ns -> 1740.002ns] - write(15, 67108879, 4179134294, 0); // [time: 1740.002ns -> 1750.002ns] - write(15, 67108880, 1634099931, 0); // [time: 1750.002ns -> 1760.002ns] - write(15, 67108881, 4072299277, 0); // [time: 1760.002ns -> 1770.002ns] - write(15, 67108882, 1017567246, 0); // [time: 1770.002ns -> 1780.002ns] - read(15, 67108867, 1264302217, 0); // [time: 1780.002ns -> 1800.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_12_1.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_12_1.monitor.expect deleted file mode 100644 index e1164b5a..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_12_1.monitor.expect +++ /dev/null @@ -1,61 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108867, 3580256271, 0); // [time: 410ns -> 430ns] - read(15, 67108864, 1489666683, 0); // [time: 430ns -> 440ns] - read(15, 67108865, 3677074643, 0); // [time: 440ns -> 450ns] - read(15, 67108866, 1878953054, 0); // [time: 450ns -> 460ns] - read(15, 67108871, 2965505115, 0); // [time: 460ns -> 470ns] - read(15, 67108868, 3259566096, 0); // [time: 470ns -> 480ns] - read(15, 67108869, 1262153110, 0); // [time: 480ns -> 490ns] - read(15, 67108870, 2451703670, 0); // [time: 490ns -> 500ns] - read(15, 67108875, 3104341711, 0); // [time: 500ns -> 510ns] - read(15, 67108872, 964066815, 0); // [time: 510ns -> 520ns] - read(15, 67108873, 3328791441, 0); // [time: 520ns -> 530ns] - read(15, 67108874, 3489570824, 0); // [time: 530ns -> 540ns] - read(15, 67108879, 4241788620, 0); // [time: 540ns -> 550ns] - read(15, 67108876, 3583058104, 0); // [time: 550ns -> 560ns] - read(15, 67108877, 1005667378, 0); // [time: 560ns -> 570ns] - read(15, 67108878, 209419171, 0); // [time: 570ns -> 580ns] - reset(); // [time: 620.001ns -> 630.001ns] - reset(); // [time: 630.001ns -> 640.001ns] - reset(); // [time: 640.001ns -> 650.001ns] - write(15, 67108867, 1000382631, 0); // [time: 690.001ns -> 710.001ns] - write(15, 67108864, 1285425234, 0); // [time: 710.001ns -> 720.001ns] - write(15, 67108865, 318606993, 0); // [time: 720.001ns -> 730.001ns] - write(15, 67108866, 2625467664, 0); // [time: 730.001ns -> 740.001ns] - write(15, 67108871, 229964357, 0); // [time: 740.001ns -> 750.001ns] - write(15, 67108868, 3036014706, 0); // [time: 750.001ns -> 760.001ns] - write(15, 67108869, 1528299378, 0); // [time: 760.001ns -> 770.001ns] - write(15, 67108870, 2182965409, 0); // [time: 770.001ns -> 780.001ns] - write(15, 67108875, 3673940705, 0); // [time: 780.001ns -> 790.001ns] - write(15, 67108872, 2347881481, 0); // [time: 790.001ns -> 800.001ns] - write(15, 67108873, 2145987888, 0); // [time: 800.001ns -> 810.001ns] - write(15, 67108874, 2056885632, 0); // [time: 810.001ns -> 820.001ns] - write(15, 67108879, 3873405704, 0); // [time: 820.001ns -> 830.001ns] - write(15, 67108876, 188298896, 0); // [time: 830.001ns -> 840.001ns] - write(15, 67108877, 3827439034, 0); // [time: 840.001ns -> 850.001ns] - write(15, 67108878, 2726944699, 0); // [time: 850.001ns -> 860.001ns] - reset(); // [time: 1540.002ns -> 1550.002ns] - reset(); // [time: 1550.002ns -> 1560.002ns] - reset(); // [time: 1560.002ns -> 1570.002ns] - write(15, 67108867, 3833002895, 0); // [time: 1610.002ns -> 1630.002ns] - write(15, 67108864, 1414948600, 0); // [time: 1630.002ns -> 1640.002ns] - write(15, 67108865, 1931556247, 0); // [time: 1640.002ns -> 1650.002ns] - write(15, 67108866, 2036215835, 0); // [time: 1650.002ns -> 1660.002ns] - write(15, 67108871, 2213185472, 0); // [time: 1660.002ns -> 1670.002ns] - write(15, 67108868, 2227456846, 0); // [time: 1670.002ns -> 1680.002ns] - write(15, 67108869, 2213473648, 0); // [time: 1680.002ns -> 1690.002ns] - write(15, 67108870, 1116257432, 0); // [time: 1690.002ns -> 1700.002ns] - write(15, 67108875, 609949692, 0); // [time: 1700.002ns -> 1710.002ns] - write(15, 67108872, 493401018, 0); // [time: 1710.002ns -> 1720.002ns] - write(15, 67108873, 1721387478, 0); // [time: 1720.002ns -> 1730.002ns] - write(15, 67108874, 1431279294, 0); // [time: 1730.002ns -> 1740.002ns] - write(15, 67108879, 716225428, 0); // [time: 1740.002ns -> 1750.002ns] - write(15, 67108876, 2446670843, 0); // [time: 1750.002ns -> 1760.002ns] - write(15, 67108877, 1494143953, 0); // [time: 1760.002ns -> 1770.002ns] - write(15, 67108878, 1325582129, 0); // [time: 1770.002ns -> 1780.002ns] - read(15, 67108867, 3833002895, 0); // [time: 1780.002ns -> 1800.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_12_2.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_12_2.monitor.expect deleted file mode 100644 index 7fee1f29..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_12_2.monitor.expect +++ /dev/null @@ -1,61 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108867, 3495738447, 0); // [time: 410ns -> 430ns] - read(15, 67108868, 1478546475, 0); // [time: 430ns -> 440ns] - read(15, 67108869, 2041778918, 0); // [time: 440ns -> 450ns] - read(15, 67108870, 3032895213, 0); // [time: 450ns -> 460ns] - read(15, 67108871, 2020268309, 0); // [time: 460ns -> 470ns] - read(15, 67108864, 3122719830, 0); // [time: 470ns -> 480ns] - read(15, 67108865, 3806053567, 0); // [time: 480ns -> 490ns] - read(15, 67108866, 3858565026, 0); // [time: 490ns -> 500ns] - read(15, 67108875, 880624971, 0); // [time: 500ns -> 510ns] - read(15, 67108876, 2554056607, 0); // [time: 510ns -> 520ns] - read(15, 67108877, 1441832696, 0); // [time: 520ns -> 530ns] - read(15, 67108878, 479445740, 0); // [time: 530ns -> 540ns] - read(15, 67108879, 2229265910, 0); // [time: 540ns -> 550ns] - read(15, 67108872, 788973880, 0); // [time: 550ns -> 560ns] - read(15, 67108873, 3880977277, 0); // [time: 560ns -> 570ns] - read(15, 67108874, 4096708504, 0); // [time: 570ns -> 580ns] - reset(); // [time: 620.001ns -> 630.001ns] - reset(); // [time: 630.001ns -> 640.001ns] - reset(); // [time: 640.001ns -> 650.001ns] - write(15, 67108867, 2427636421, 0); // [time: 690.001ns -> 710.001ns] - write(15, 67108868, 3595099675, 0); // [time: 710.001ns -> 720.001ns] - write(15, 67108869, 2668681316, 0); // [time: 720.001ns -> 730.001ns] - write(15, 67108870, 1679837987, 0); // [time: 730.001ns -> 740.001ns] - write(15, 67108871, 924732013, 0); // [time: 740.001ns -> 750.001ns] - write(15, 67108864, 2192079403, 0); // [time: 750.001ns -> 760.001ns] - write(15, 67108865, 2042051660, 0); // [time: 760.001ns -> 770.001ns] - write(15, 67108866, 989927686, 0); // [time: 770.001ns -> 780.001ns] - write(15, 67108875, 3067406900, 0); // [time: 780.001ns -> 790.001ns] - write(15, 67108876, 1058215073, 0); // [time: 790.001ns -> 800.001ns] - write(15, 67108877, 365012335, 0); // [time: 800.001ns -> 810.001ns] - write(15, 67108878, 687295108, 0); // [time: 810.001ns -> 820.001ns] - write(15, 67108879, 2829218573, 0); // [time: 820.001ns -> 830.001ns] - write(15, 67108872, 1448409262, 0); // [time: 830.001ns -> 840.001ns] - write(15, 67108873, 400594486, 0); // [time: 840.001ns -> 850.001ns] - write(15, 67108874, 4177343116, 0); // [time: 850.001ns -> 860.001ns] - reset(); // [time: 1540.002ns -> 1550.002ns] - reset(); // [time: 1550.002ns -> 1560.002ns] - reset(); // [time: 1560.002ns -> 1570.002ns] - write(15, 67108867, 2304668716, 0); // [time: 1610.002ns -> 1630.002ns] - write(15, 67108868, 2610611482, 0); // [time: 1630.002ns -> 1640.002ns] - write(15, 67108869, 1468153982, 0); // [time: 1640.002ns -> 1650.002ns] - write(15, 67108870, 1169841342, 0); // [time: 1650.002ns -> 1660.002ns] - write(15, 67108871, 27036823, 0); // [time: 1660.002ns -> 1670.002ns] - write(15, 67108864, 73783758, 0); // [time: 1670.002ns -> 1680.002ns] - write(15, 67108865, 1621524717, 0); // [time: 1680.002ns -> 1690.002ns] - write(15, 67108866, 3905946412, 0); // [time: 1690.002ns -> 1700.002ns] - write(15, 67108875, 1563100034, 0); // [time: 1700.002ns -> 1710.002ns] - write(15, 67108876, 2069336907, 0); // [time: 1710.002ns -> 1720.002ns] - write(15, 67108877, 583373053, 0); // [time: 1720.002ns -> 1730.002ns] - write(15, 67108878, 3629920426, 0); // [time: 1730.002ns -> 1740.002ns] - write(15, 67108879, 2146122704, 0); // [time: 1740.002ns -> 1750.002ns] - write(15, 67108872, 2674258699, 0); // [time: 1750.002ns -> 1760.002ns] - write(15, 67108873, 1361676606, 0); // [time: 1760.002ns -> 1770.002ns] - write(15, 67108874, 2435452493, 0); // [time: 1770.002ns -> 1780.002ns] - read(15, 67108867, 2304668716, 0); // [time: 1780.002ns -> 1800.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_12_3.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_12_3.monitor.expect deleted file mode 100644 index b68e5c47..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_12_3.monitor.expect +++ /dev/null @@ -1,61 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108867, 2727164243, 0); // [time: 410ns -> 430ns] - read(15, 67108868, 1384255697, 0); // [time: 430ns -> 440ns] - read(15, 67108869, 4216231340, 0); // [time: 440ns -> 450ns] - read(15, 67108870, 1661993927, 0); // [time: 450ns -> 460ns] - read(15, 67108871, 159950269, 0); // [time: 460ns -> 470ns] - read(15, 67108872, 893905490, 0); // [time: 470ns -> 480ns] - read(15, 67108873, 1464841894, 0); // [time: 480ns -> 490ns] - read(15, 67108874, 710545966, 0); // [time: 490ns -> 500ns] - read(15, 67108875, 3482423916, 0); // [time: 500ns -> 510ns] - read(15, 67108876, 4068629318, 0); // [time: 510ns -> 520ns] - read(15, 67108877, 3266524719, 0); // [time: 520ns -> 530ns] - read(15, 67108878, 1808083576, 0); // [time: 530ns -> 540ns] - read(15, 67108879, 3562161795, 0); // [time: 540ns -> 550ns] - read(15, 67108864, 2984675510, 0); // [time: 550ns -> 560ns] - read(15, 67108865, 2475539812, 0); // [time: 560ns -> 570ns] - read(15, 67108866, 2138191023, 0); // [time: 570ns -> 580ns] - reset(); // [time: 620.001ns -> 630.001ns] - reset(); // [time: 630.001ns -> 640.001ns] - reset(); // [time: 640.001ns -> 650.001ns] - write(15, 67108867, 1599974119, 0); // [time: 690.001ns -> 710.001ns] - write(15, 67108868, 609858284, 0); // [time: 710.001ns -> 720.001ns] - write(15, 67108869, 1648881400, 0); // [time: 720.001ns -> 730.001ns] - write(15, 67108870, 572149112, 0); // [time: 730.001ns -> 740.001ns] - write(15, 67108871, 602124761, 0); // [time: 740.001ns -> 750.001ns] - write(15, 67108872, 3299652692, 0); // [time: 750.001ns -> 760.001ns] - write(15, 67108873, 1416165996, 0); // [time: 760.001ns -> 770.001ns] - write(15, 67108874, 1639735531, 0); // [time: 770.001ns -> 780.001ns] - write(15, 67108875, 941900856, 0); // [time: 780.001ns -> 790.001ns] - write(15, 67108876, 4103564658, 0); // [time: 790.001ns -> 800.001ns] - write(15, 67108877, 788749736, 0); // [time: 800.001ns -> 810.001ns] - write(15, 67108878, 1260615071, 0); // [time: 810.001ns -> 820.001ns] - write(15, 67108879, 2210117974, 0); // [time: 820.001ns -> 830.001ns] - write(15, 67108864, 2952803435, 0); // [time: 830.001ns -> 840.001ns] - write(15, 67108865, 441673600, 0); // [time: 840.001ns -> 850.001ns] - write(15, 67108866, 2137709866, 0); // [time: 850.001ns -> 860.001ns] - reset(); // [time: 1540.002ns -> 1550.002ns] - reset(); // [time: 1550.002ns -> 1560.002ns] - reset(); // [time: 1560.002ns -> 1570.002ns] - write(15, 67108867, 2898868374, 0); // [time: 1610.002ns -> 1630.002ns] - write(15, 67108868, 1922764675, 0); // [time: 1630.002ns -> 1640.002ns] - write(15, 67108869, 4256406750, 0); // [time: 1640.002ns -> 1650.002ns] - write(15, 67108870, 245447329, 0); // [time: 1650.002ns -> 1660.002ns] - write(15, 67108871, 3225897750, 0); // [time: 1660.002ns -> 1670.002ns] - write(15, 67108872, 1779082048, 0); // [time: 1670.002ns -> 1680.002ns] - write(15, 67108873, 1953003128, 0); // [time: 1680.002ns -> 1690.002ns] - write(15, 67108874, 4020445238, 0); // [time: 1690.002ns -> 1700.002ns] - write(15, 67108875, 2174587331, 0); // [time: 1700.002ns -> 1710.002ns] - write(15, 67108876, 1632125876, 0); // [time: 1710.002ns -> 1720.002ns] - write(15, 67108877, 340410721, 0); // [time: 1720.002ns -> 1730.002ns] - write(15, 67108878, 771941360, 0); // [time: 1730.002ns -> 1740.002ns] - write(15, 67108879, 2567244845, 0); // [time: 1740.002ns -> 1750.002ns] - write(15, 67108864, 899887853, 0); // [time: 1750.002ns -> 1760.002ns] - write(15, 67108865, 1674678715, 0); // [time: 1760.002ns -> 1770.002ns] - write(15, 67108866, 902429492, 0); // [time: 1770.002ns -> 1780.002ns] - read(15, 67108867, 2898868374, 0); // [time: 1780.002ns -> 1800.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_4_0.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_4_0.monitor.expect deleted file mode 100644 index a60d8398..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_4_0.monitor.expect +++ /dev/null @@ -1,61 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108865, 1016512136, 0); // [time: 410ns -> 430ns] - read(15, 67108866, 226204128, 0); // [time: 430ns -> 440ns] - read(15, 67108867, 2116565440, 0); // [time: 440ns -> 450ns] - read(15, 67108868, 2153688786, 0); // [time: 450ns -> 460ns] - read(15, 67108869, 1974223269, 0); // [time: 460ns -> 470ns] - read(15, 67108870, 1053640572, 0); // [time: 470ns -> 480ns] - read(15, 67108871, 2079860600, 0); // [time: 480ns -> 490ns] - read(15, 67108872, 3550045624, 0); // [time: 490ns -> 500ns] - read(15, 67108873, 1038322047, 0); // [time: 500ns -> 510ns] - read(15, 67108874, 1502718053, 0); // [time: 510ns -> 520ns] - read(15, 67108875, 1367070343, 0); // [time: 520ns -> 530ns] - read(15, 67108876, 3425882885, 0); // [time: 530ns -> 540ns] - read(15, 67108877, 1614916721, 0); // [time: 540ns -> 550ns] - read(15, 67108878, 3041346437, 0); // [time: 550ns -> 560ns] - read(15, 67108879, 3665993952, 0); // [time: 560ns -> 570ns] - read(15, 67108880, 3560581876, 0); // [time: 570ns -> 580ns] - reset(); // [time: 620.001ns -> 630.001ns] - reset(); // [time: 630.001ns -> 640.001ns] - reset(); // [time: 640.001ns -> 650.001ns] - write(15, 67108865, 3433786972, 0); // [time: 690.001ns -> 710.001ns] - write(15, 67108866, 3840560806, 0); // [time: 710.001ns -> 720.001ns] - write(15, 67108867, 3225552468, 0); // [time: 720.001ns -> 730.001ns] - write(15, 67108868, 3717810263, 0); // [time: 730.001ns -> 740.001ns] - write(15, 67108869, 3317657198, 0); // [time: 740.001ns -> 750.001ns] - write(15, 67108870, 1024069544, 0); // [time: 750.001ns -> 760.001ns] - write(15, 67108871, 1752245362, 0); // [time: 760.001ns -> 770.001ns] - write(15, 67108872, 1579776374, 0); // [time: 770.001ns -> 780.001ns] - write(15, 67108873, 904253205, 0); // [time: 780.001ns -> 790.001ns] - write(15, 67108874, 1728285430, 0); // [time: 790.001ns -> 800.001ns] - write(15, 67108875, 91066718, 0); // [time: 800.001ns -> 810.001ns] - write(15, 67108876, 1402442819, 0); // [time: 810.001ns -> 820.001ns] - write(15, 67108877, 4062122226, 0); // [time: 820.001ns -> 830.001ns] - write(15, 67108878, 1191921998, 0); // [time: 830.001ns -> 840.001ns] - write(15, 67108879, 1249541889, 0); // [time: 840.001ns -> 850.001ns] - write(15, 67108880, 2580891116, 0); // [time: 850.001ns -> 860.001ns] - reset(); // [time: 1540.002ns -> 1550.002ns] - reset(); // [time: 1550.002ns -> 1560.002ns] - reset(); // [time: 1560.002ns -> 1570.002ns] - write(15, 67108865, 1526706340, 0); // [time: 1610.002ns -> 1630.002ns] - write(15, 67108866, 1162262173, 0); // [time: 1630.002ns -> 1640.002ns] - write(15, 67108867, 3667501502, 0); // [time: 1640.002ns -> 1650.002ns] - write(15, 67108868, 617255735, 0); // [time: 1650.002ns -> 1660.002ns] - write(15, 67108869, 4077356414, 0); // [time: 1660.002ns -> 1670.002ns] - write(15, 67108870, 1593609662, 0); // [time: 1670.002ns -> 1680.002ns] - write(15, 67108871, 2148292499, 0); // [time: 1680.002ns -> 1690.002ns] - write(15, 67108872, 3403556849, 0); // [time: 1690.002ns -> 1700.002ns] - write(15, 67108873, 3331963440, 0); // [time: 1700.002ns -> 1710.002ns] - write(15, 67108874, 1493302995, 0); // [time: 1710.002ns -> 1720.002ns] - write(15, 67108875, 2710958922, 0); // [time: 1720.002ns -> 1730.002ns] - write(15, 67108876, 4029972623, 0); // [time: 1730.002ns -> 1740.002ns] - write(15, 67108877, 2845272388, 0); // [time: 1740.002ns -> 1750.002ns] - write(15, 67108878, 70166840, 0); // [time: 1750.002ns -> 1760.002ns] - write(15, 67108879, 1323291936, 0); // [time: 1760.002ns -> 1770.002ns] - write(15, 67108880, 916783944, 0); // [time: 1770.002ns -> 1780.002ns] - read(15, 67108865, 1526706340, 0); // [time: 1780.002ns -> 1800.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_4_1.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_4_1.monitor.expect deleted file mode 100644 index 8662cb21..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_4_1.monitor.expect +++ /dev/null @@ -1,61 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108865, 2821946881, 0); // [time: 410ns -> 430ns] - read(15, 67108866, 4080087070, 0); // [time: 430ns -> 440ns] - read(15, 67108867, 2243193877, 0); // [time: 440ns -> 450ns] - read(15, 67108864, 2472849580, 0); // [time: 450ns -> 460ns] - read(15, 67108869, 3565370026, 0); // [time: 460ns -> 470ns] - read(15, 67108870, 890985600, 0); // [time: 470ns -> 480ns] - read(15, 67108871, 4179549189, 0); // [time: 480ns -> 490ns] - read(15, 67108868, 4158632492, 0); // [time: 490ns -> 500ns] - read(15, 67108873, 3744957516, 0); // [time: 500ns -> 510ns] - read(15, 67108874, 2300150418, 0); // [time: 510ns -> 520ns] - read(15, 67108875, 2081940992, 0); // [time: 520ns -> 530ns] - read(15, 67108872, 1697819148, 0); // [time: 530ns -> 540ns] - read(15, 67108877, 602241333, 0); // [time: 540ns -> 550ns] - read(15, 67108878, 2260552922, 0); // [time: 550ns -> 560ns] - read(15, 67108879, 4251564751, 0); // [time: 560ns -> 570ns] - read(15, 67108876, 3326548024, 0); // [time: 570ns -> 580ns] - reset(); // [time: 620.001ns -> 630.001ns] - reset(); // [time: 630.001ns -> 640.001ns] - reset(); // [time: 640.001ns -> 650.001ns] - write(15, 67108865, 1044044861, 0); // [time: 690.001ns -> 710.001ns] - write(15, 67108866, 4177314760, 0); // [time: 710.001ns -> 720.001ns] - write(15, 67108867, 4253662683, 0); // [time: 720.001ns -> 730.001ns] - write(15, 67108864, 3575602093, 0); // [time: 730.001ns -> 740.001ns] - write(15, 67108869, 667576938, 0); // [time: 740.001ns -> 750.001ns] - write(15, 67108870, 3110079964, 0); // [time: 750.001ns -> 760.001ns] - write(15, 67108871, 3758039968, 0); // [time: 760.001ns -> 770.001ns] - write(15, 67108868, 3566852678, 0); // [time: 770.001ns -> 780.001ns] - write(15, 67108873, 3124984337, 0); // [time: 780.001ns -> 790.001ns] - write(15, 67108874, 2124019892, 0); // [time: 790.001ns -> 800.001ns] - write(15, 67108875, 4257151913, 0); // [time: 800.001ns -> 810.001ns] - write(15, 67108872, 2010257240, 0); // [time: 810.001ns -> 820.001ns] - write(15, 67108877, 236076834, 0); // [time: 820.001ns -> 830.001ns] - write(15, 67108878, 1005361240, 0); // [time: 830.001ns -> 840.001ns] - write(15, 67108879, 3482961596, 0); // [time: 840.001ns -> 850.001ns] - write(15, 67108876, 416798935, 0); // [time: 850.001ns -> 860.001ns] - reset(); // [time: 1540.002ns -> 1550.002ns] - reset(); // [time: 1550.002ns -> 1560.002ns] - reset(); // [time: 1560.002ns -> 1570.002ns] - write(15, 67108865, 5665644, 0); // [time: 1610.002ns -> 1630.002ns] - write(15, 67108866, 2207028948, 0); // [time: 1630.002ns -> 1640.002ns] - write(15, 67108867, 3039596975, 0); // [time: 1640.002ns -> 1650.002ns] - write(15, 67108864, 2873077745, 0); // [time: 1650.002ns -> 1660.002ns] - write(15, 67108869, 4156333102, 0); // [time: 1660.002ns -> 1670.002ns] - write(15, 67108870, 2428683490, 0); // [time: 1670.002ns -> 1680.002ns] - write(15, 67108871, 2474641325, 0); // [time: 1680.002ns -> 1690.002ns] - write(15, 67108868, 2593936487, 0); // [time: 1690.002ns -> 1700.002ns] - write(15, 67108873, 2521039073, 0); // [time: 1700.002ns -> 1710.002ns] - write(15, 67108874, 3155595410, 0); // [time: 1710.002ns -> 1720.002ns] - write(15, 67108875, 2665880696, 0); // [time: 1720.002ns -> 1730.002ns] - write(15, 67108872, 1347764084, 0); // [time: 1730.002ns -> 1740.002ns] - write(15, 67108877, 3198898103, 0); // [time: 1740.002ns -> 1750.002ns] - write(15, 67108878, 1659773118, 0); // [time: 1750.002ns -> 1760.002ns] - write(15, 67108879, 2296543553, 0); // [time: 1760.002ns -> 1770.002ns] - write(15, 67108876, 1471659223, 0); // [time: 1770.002ns -> 1780.002ns] - read(15, 67108865, 5665644, 0); // [time: 1780.002ns -> 1800.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_4_2.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_4_2.monitor.expect deleted file mode 100644 index c01c5814..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_4_2.monitor.expect +++ /dev/null @@ -1,61 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108865, 3495738447, 0); // [time: 410ns -> 430ns] - read(15, 67108866, 1478546475, 0); // [time: 430ns -> 440ns] - read(15, 67108867, 2041778918, 0); // [time: 440ns -> 450ns] - read(15, 67108868, 3032895213, 0); // [time: 450ns -> 460ns] - read(15, 67108869, 2020268309, 0); // [time: 460ns -> 470ns] - read(15, 67108870, 3122719830, 0); // [time: 470ns -> 480ns] - read(15, 67108871, 3806053567, 0); // [time: 480ns -> 490ns] - read(15, 67108864, 3858565026, 0); // [time: 490ns -> 500ns] - read(15, 67108873, 880624971, 0); // [time: 500ns -> 510ns] - read(15, 67108874, 2554056607, 0); // [time: 510ns -> 520ns] - read(15, 67108875, 1441832696, 0); // [time: 520ns -> 530ns] - read(15, 67108876, 479445740, 0); // [time: 530ns -> 540ns] - read(15, 67108877, 2229265910, 0); // [time: 540ns -> 550ns] - read(15, 67108878, 788973880, 0); // [time: 550ns -> 560ns] - read(15, 67108879, 3880977277, 0); // [time: 560ns -> 570ns] - read(15, 67108872, 4096708504, 0); // [time: 570ns -> 580ns] - reset(); // [time: 620.001ns -> 630.001ns] - reset(); // [time: 630.001ns -> 640.001ns] - reset(); // [time: 640.001ns -> 650.001ns] - write(15, 67108865, 2427636421, 0); // [time: 690.001ns -> 710.001ns] - write(15, 67108866, 3595099675, 0); // [time: 710.001ns -> 720.001ns] - write(15, 67108867, 2668681316, 0); // [time: 720.001ns -> 730.001ns] - write(15, 67108868, 1679837987, 0); // [time: 730.001ns -> 740.001ns] - write(15, 67108869, 924732013, 0); // [time: 740.001ns -> 750.001ns] - write(15, 67108870, 2192079403, 0); // [time: 750.001ns -> 760.001ns] - write(15, 67108871, 2042051660, 0); // [time: 760.001ns -> 770.001ns] - write(15, 67108864, 989927686, 0); // [time: 770.001ns -> 780.001ns] - write(15, 67108873, 3067406900, 0); // [time: 780.001ns -> 790.001ns] - write(15, 67108874, 1058215073, 0); // [time: 790.001ns -> 800.001ns] - write(15, 67108875, 365012335, 0); // [time: 800.001ns -> 810.001ns] - write(15, 67108876, 687295108, 0); // [time: 810.001ns -> 820.001ns] - write(15, 67108877, 2829218573, 0); // [time: 820.001ns -> 830.001ns] - write(15, 67108878, 1448409262, 0); // [time: 830.001ns -> 840.001ns] - write(15, 67108879, 400594486, 0); // [time: 840.001ns -> 850.001ns] - write(15, 67108872, 4177343116, 0); // [time: 850.001ns -> 860.001ns] - reset(); // [time: 1540.002ns -> 1550.002ns] - reset(); // [time: 1550.002ns -> 1560.002ns] - reset(); // [time: 1560.002ns -> 1570.002ns] - write(15, 67108865, 2304668716, 0); // [time: 1610.002ns -> 1630.002ns] - write(15, 67108866, 2610611482, 0); // [time: 1630.002ns -> 1640.002ns] - write(15, 67108867, 1468153982, 0); // [time: 1640.002ns -> 1650.002ns] - write(15, 67108868, 1169841342, 0); // [time: 1650.002ns -> 1660.002ns] - write(15, 67108869, 27036823, 0); // [time: 1660.002ns -> 1670.002ns] - write(15, 67108870, 73783758, 0); // [time: 1670.002ns -> 1680.002ns] - write(15, 67108871, 1621524717, 0); // [time: 1680.002ns -> 1690.002ns] - write(15, 67108864, 3905946412, 0); // [time: 1690.002ns -> 1700.002ns] - write(15, 67108873, 1563100034, 0); // [time: 1700.002ns -> 1710.002ns] - write(15, 67108874, 2069336907, 0); // [time: 1710.002ns -> 1720.002ns] - write(15, 67108875, 583373053, 0); // [time: 1720.002ns -> 1730.002ns] - write(15, 67108876, 3629920426, 0); // [time: 1730.002ns -> 1740.002ns] - write(15, 67108877, 2146122704, 0); // [time: 1740.002ns -> 1750.002ns] - write(15, 67108878, 2674258699, 0); // [time: 1750.002ns -> 1760.002ns] - write(15, 67108879, 1361676606, 0); // [time: 1760.002ns -> 1770.002ns] - write(15, 67108872, 2435452493, 0); // [time: 1770.002ns -> 1780.002ns] - read(15, 67108865, 2304668716, 0); // [time: 1780.002ns -> 1800.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_4_3.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_4_3.monitor.expect deleted file mode 100644 index 6190588c..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_4_3.monitor.expect +++ /dev/null @@ -1,61 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108865, 1070372987, 0); // [time: 410ns -> 430ns] - read(15, 67108866, 2645947069, 0); // [time: 430ns -> 440ns] - read(15, 67108867, 736643984, 0); // [time: 440ns -> 450ns] - read(15, 67108868, 192007203, 0); // [time: 450ns -> 460ns] - read(15, 67108869, 1925400290, 0); // [time: 460ns -> 470ns] - read(15, 67108870, 1309609983, 0); // [time: 470ns -> 480ns] - read(15, 67108871, 58503546, 0); // [time: 480ns -> 490ns] - read(15, 67108872, 3861022989, 0); // [time: 490ns -> 500ns] - read(15, 67108873, 1725708128, 0); // [time: 500ns -> 510ns] - read(15, 67108874, 3760744365, 0); // [time: 510ns -> 520ns] - read(15, 67108875, 3803789590, 0); // [time: 520ns -> 530ns] - read(15, 67108876, 2647121574, 0); // [time: 530ns -> 540ns] - read(15, 67108877, 336117328, 0); // [time: 540ns -> 550ns] - read(15, 67108878, 3984726565, 0); // [time: 550ns -> 560ns] - read(15, 67108879, 104808193, 0); // [time: 560ns -> 570ns] - read(15, 67108864, 2315494688, 0); // [time: 570ns -> 580ns] - reset(); // [time: 620.001ns -> 630.001ns] - reset(); // [time: 630.001ns -> 640.001ns] - reset(); // [time: 640.001ns -> 650.001ns] - write(15, 67108865, 3997204021, 0); // [time: 690.001ns -> 710.001ns] - write(15, 67108866, 666660673, 0); // [time: 710.001ns -> 720.001ns] - write(15, 67108867, 3910223084, 0); // [time: 720.001ns -> 730.001ns] - write(15, 67108868, 1271405124, 0); // [time: 730.001ns -> 740.001ns] - write(15, 67108869, 4236388983, 0); // [time: 740.001ns -> 750.001ns] - write(15, 67108870, 1347016890, 0); // [time: 750.001ns -> 760.001ns] - write(15, 67108871, 1337396640, 0); // [time: 760.001ns -> 770.001ns] - write(15, 67108872, 3009712000, 0); // [time: 770.001ns -> 780.001ns] - write(15, 67108873, 2237248361, 0); // [time: 780.001ns -> 790.001ns] - write(15, 67108874, 592560133, 0); // [time: 790.001ns -> 800.001ns] - write(15, 67108875, 371018497, 0); // [time: 800.001ns -> 810.001ns] - write(15, 67108876, 763875626, 0); // [time: 810.001ns -> 820.001ns] - write(15, 67108877, 75174504, 0); // [time: 820.001ns -> 830.001ns] - write(15, 67108878, 2983449782, 0); // [time: 830.001ns -> 840.001ns] - write(15, 67108879, 2295155532, 0); // [time: 840.001ns -> 850.001ns] - write(15, 67108864, 1954643484, 0); // [time: 850.001ns -> 860.001ns] - reset(); // [time: 1540.002ns -> 1550.002ns] - reset(); // [time: 1550.002ns -> 1560.002ns] - reset(); // [time: 1560.002ns -> 1570.002ns] - write(15, 67108865, 409090773, 0); // [time: 1610.002ns -> 1630.002ns] - write(15, 67108866, 1348706589, 0); // [time: 1630.002ns -> 1640.002ns] - write(15, 67108867, 1967918440, 0); // [time: 1640.002ns -> 1650.002ns] - write(15, 67108868, 2636141882, 0); // [time: 1650.002ns -> 1660.002ns] - write(15, 67108869, 533777194, 0); // [time: 1660.002ns -> 1670.002ns] - write(15, 67108870, 2114809607, 0); // [time: 1670.002ns -> 1680.002ns] - write(15, 67108871, 309856382, 0); // [time: 1680.002ns -> 1690.002ns] - write(15, 67108872, 3466848916, 0); // [time: 1690.002ns -> 1700.002ns] - write(15, 67108873, 3043756153, 0); // [time: 1700.002ns -> 1710.002ns] - write(15, 67108874, 2927281001, 0); // [time: 1710.002ns -> 1720.002ns] - write(15, 67108875, 1913699666, 0); // [time: 1720.002ns -> 1730.002ns] - write(15, 67108876, 1847871828, 0); // [time: 1730.002ns -> 1740.002ns] - write(15, 67108877, 3984372107, 0); // [time: 1740.002ns -> 1750.002ns] - write(15, 67108878, 4239907193, 0); // [time: 1750.002ns -> 1760.002ns] - write(15, 67108879, 1427511912, 0); // [time: 1760.002ns -> 1770.002ns] - write(15, 67108864, 277973300, 0); // [time: 1770.002ns -> 1780.002ns] - read(15, 67108865, 409090773, 0); // [time: 1780.002ns -> 1800.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_8_0.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_8_0.monitor.expect deleted file mode 100644 index a37855f8..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_8_0.monitor.expect +++ /dev/null @@ -1,61 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108866, 2205995893, 0); // [time: 410ns -> 430ns] - read(15, 67108867, 486560095, 0); // [time: 430ns -> 440ns] - read(15, 67108868, 4100133660, 0); // [time: 440ns -> 450ns] - read(15, 67108869, 596618694, 0); // [time: 450ns -> 460ns] - read(15, 67108870, 3499942130, 0); // [time: 460ns -> 470ns] - read(15, 67108871, 2357711907, 0); // [time: 470ns -> 480ns] - read(15, 67108872, 2086526797, 0); // [time: 480ns -> 490ns] - read(15, 67108873, 364077448, 0); // [time: 490ns -> 500ns] - read(15, 67108874, 210674739, 0); // [time: 500ns -> 510ns] - read(15, 67108875, 1567286535, 0); // [time: 510ns -> 520ns] - read(15, 67108876, 922799025, 0); // [time: 520ns -> 530ns] - read(15, 67108877, 4171757579, 0); // [time: 530ns -> 540ns] - read(15, 67108878, 740193371, 0); // [time: 540ns -> 550ns] - read(15, 67108879, 872570658, 0); // [time: 550ns -> 560ns] - read(15, 67108880, 608559447, 0); // [time: 560ns -> 570ns] - read(15, 67108881, 1049762371, 0); // [time: 570ns -> 580ns] - reset(); // [time: 620.001ns -> 630.001ns] - reset(); // [time: 630.001ns -> 640.001ns] - reset(); // [time: 640.001ns -> 650.001ns] - write(15, 67108866, 61321282, 0); // [time: 690.001ns -> 710.001ns] - write(15, 67108867, 3113679544, 0); // [time: 710.001ns -> 720.001ns] - write(15, 67108868, 2723657215, 0); // [time: 720.001ns -> 730.001ns] - write(15, 67108869, 3578979173, 0); // [time: 730.001ns -> 740.001ns] - write(15, 67108870, 1844094072, 0); // [time: 740.001ns -> 750.001ns] - write(15, 67108871, 985922533, 0); // [time: 750.001ns -> 760.001ns] - write(15, 67108872, 772047228, 0); // [time: 760.001ns -> 770.001ns] - write(15, 67108873, 2786594234, 0); // [time: 770.001ns -> 780.001ns] - write(15, 67108874, 3174400206, 0); // [time: 780.001ns -> 790.001ns] - write(15, 67108875, 4087288639, 0); // [time: 790.001ns -> 800.001ns] - write(15, 67108876, 1255295898, 0); // [time: 800.001ns -> 810.001ns] - write(15, 67108877, 1278490992, 0); // [time: 810.001ns -> 820.001ns] - write(15, 67108878, 3471724536, 0); // [time: 820.001ns -> 830.001ns] - write(15, 67108879, 382544438, 0); // [time: 830.001ns -> 840.001ns] - write(15, 67108880, 457743574, 0); // [time: 840.001ns -> 850.001ns] - write(15, 67108881, 2419868428, 0); // [time: 850.001ns -> 860.001ns] - reset(); // [time: 1540.002ns -> 1550.002ns] - reset(); // [time: 1550.002ns -> 1560.002ns] - reset(); // [time: 1560.002ns -> 1570.002ns] - write(15, 67108866, 3159959397, 0); // [time: 1610.002ns -> 1630.002ns] - write(15, 67108867, 2987258927, 0); // [time: 1630.002ns -> 1640.002ns] - write(15, 67108868, 3076374300, 0); // [time: 1640.002ns -> 1650.002ns] - write(15, 67108869, 2145515966, 0); // [time: 1650.002ns -> 1660.002ns] - write(15, 67108870, 363069260, 0); // [time: 1660.002ns -> 1670.002ns] - write(15, 67108871, 1291413511, 0); // [time: 1670.002ns -> 1680.002ns] - write(15, 67108872, 3582649965, 0); // [time: 1680.002ns -> 1690.002ns] - write(15, 67108873, 2885357400, 0); // [time: 1690.002ns -> 1700.002ns] - write(15, 67108874, 1499869988, 0); // [time: 1700.002ns -> 1710.002ns] - write(15, 67108875, 2213787236, 0); // [time: 1710.002ns -> 1720.002ns] - write(15, 67108876, 1663586395, 0); // [time: 1720.002ns -> 1730.002ns] - write(15, 67108877, 680862039, 0); // [time: 1730.002ns -> 1740.002ns] - write(15, 67108878, 4246962232, 0); // [time: 1740.002ns -> 1750.002ns] - write(15, 67108879, 2414397419, 0); // [time: 1750.002ns -> 1760.002ns] - write(15, 67108880, 2179858695, 0); // [time: 1760.002ns -> 1770.002ns] - write(15, 67108881, 3059261273, 0); // [time: 1770.002ns -> 1780.002ns] - read(15, 67108866, 3159959397, 0); // [time: 1780.002ns -> 1800.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_8_1.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_8_1.monitor.expect deleted file mode 100644 index 2ae4e75f..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_8_1.monitor.expect +++ /dev/null @@ -1,61 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108866, 2821946881, 0); // [time: 410ns -> 430ns] - read(15, 67108867, 4080087070, 0); // [time: 430ns -> 440ns] - read(15, 67108864, 2243193877, 0); // [time: 440ns -> 450ns] - read(15, 67108865, 2472849580, 0); // [time: 450ns -> 460ns] - read(15, 67108870, 3565370026, 0); // [time: 460ns -> 470ns] - read(15, 67108871, 890985600, 0); // [time: 470ns -> 480ns] - read(15, 67108868, 4179549189, 0); // [time: 480ns -> 490ns] - read(15, 67108869, 4158632492, 0); // [time: 490ns -> 500ns] - read(15, 67108874, 3744957516, 0); // [time: 500ns -> 510ns] - read(15, 67108875, 2300150418, 0); // [time: 510ns -> 520ns] - read(15, 67108872, 2081940992, 0); // [time: 520ns -> 530ns] - read(15, 67108873, 1697819148, 0); // [time: 530ns -> 540ns] - read(15, 67108878, 602241333, 0); // [time: 540ns -> 550ns] - read(15, 67108879, 2260552922, 0); // [time: 550ns -> 560ns] - read(15, 67108876, 4251564751, 0); // [time: 560ns -> 570ns] - read(15, 67108877, 3326548024, 0); // [time: 570ns -> 580ns] - reset(); // [time: 620.001ns -> 630.001ns] - reset(); // [time: 630.001ns -> 640.001ns] - reset(); // [time: 640.001ns -> 650.001ns] - write(15, 67108866, 1044044861, 0); // [time: 690.001ns -> 710.001ns] - write(15, 67108867, 4177314760, 0); // [time: 710.001ns -> 720.001ns] - write(15, 67108864, 4253662683, 0); // [time: 720.001ns -> 730.001ns] - write(15, 67108865, 3575602093, 0); // [time: 730.001ns -> 740.001ns] - write(15, 67108870, 667576938, 0); // [time: 740.001ns -> 750.001ns] - write(15, 67108871, 3110079964, 0); // [time: 750.001ns -> 760.001ns] - write(15, 67108868, 3758039968, 0); // [time: 760.001ns -> 770.001ns] - write(15, 67108869, 3566852678, 0); // [time: 770.001ns -> 780.001ns] - write(15, 67108874, 3124984337, 0); // [time: 780.001ns -> 790.001ns] - write(15, 67108875, 2124019892, 0); // [time: 790.001ns -> 800.001ns] - write(15, 67108872, 4257151913, 0); // [time: 800.001ns -> 810.001ns] - write(15, 67108873, 2010257240, 0); // [time: 810.001ns -> 820.001ns] - write(15, 67108878, 236076834, 0); // [time: 820.001ns -> 830.001ns] - write(15, 67108879, 1005361240, 0); // [time: 830.001ns -> 840.001ns] - write(15, 67108876, 3482961596, 0); // [time: 840.001ns -> 850.001ns] - write(15, 67108877, 416798935, 0); // [time: 850.001ns -> 860.001ns] - reset(); // [time: 1540.002ns -> 1550.002ns] - reset(); // [time: 1550.002ns -> 1560.002ns] - reset(); // [time: 1560.002ns -> 1570.002ns] - write(15, 67108866, 5665644, 0); // [time: 1610.002ns -> 1630.002ns] - write(15, 67108867, 2207028948, 0); // [time: 1630.002ns -> 1640.002ns] - write(15, 67108864, 3039596975, 0); // [time: 1640.002ns -> 1650.002ns] - write(15, 67108865, 2873077745, 0); // [time: 1650.002ns -> 1660.002ns] - write(15, 67108870, 4156333102, 0); // [time: 1660.002ns -> 1670.002ns] - write(15, 67108871, 2428683490, 0); // [time: 1670.002ns -> 1680.002ns] - write(15, 67108868, 2474641325, 0); // [time: 1680.002ns -> 1690.002ns] - write(15, 67108869, 2593936487, 0); // [time: 1690.002ns -> 1700.002ns] - write(15, 67108874, 2521039073, 0); // [time: 1700.002ns -> 1710.002ns] - write(15, 67108875, 3155595410, 0); // [time: 1710.002ns -> 1720.002ns] - write(15, 67108872, 2665880696, 0); // [time: 1720.002ns -> 1730.002ns] - write(15, 67108873, 1347764084, 0); // [time: 1730.002ns -> 1740.002ns] - write(15, 67108878, 3198898103, 0); // [time: 1740.002ns -> 1750.002ns] - write(15, 67108879, 1659773118, 0); // [time: 1750.002ns -> 1760.002ns] - write(15, 67108876, 2296543553, 0); // [time: 1760.002ns -> 1770.002ns] - write(15, 67108877, 1471659223, 0); // [time: 1770.002ns -> 1780.002ns] - read(15, 67108866, 5665644, 0); // [time: 1780.002ns -> 1800.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_8_2.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_8_2.monitor.expect deleted file mode 100644 index fb8baf9c..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_8_2.monitor.expect +++ /dev/null @@ -1,61 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108866, 3495738447, 0); // [time: 410ns -> 430ns] - read(15, 67108867, 1478546475, 0); // [time: 430ns -> 440ns] - read(15, 67108868, 2041778918, 0); // [time: 440ns -> 450ns] - read(15, 67108869, 3032895213, 0); // [time: 450ns -> 460ns] - read(15, 67108870, 2020268309, 0); // [time: 460ns -> 470ns] - read(15, 67108871, 3122719830, 0); // [time: 470ns -> 480ns] - read(15, 67108864, 3806053567, 0); // [time: 480ns -> 490ns] - read(15, 67108865, 3858565026, 0); // [time: 490ns -> 500ns] - read(15, 67108874, 880624971, 0); // [time: 500ns -> 510ns] - read(15, 67108875, 2554056607, 0); // [time: 510ns -> 520ns] - read(15, 67108876, 1441832696, 0); // [time: 520ns -> 530ns] - read(15, 67108877, 479445740, 0); // [time: 530ns -> 540ns] - read(15, 67108878, 2229265910, 0); // [time: 540ns -> 550ns] - read(15, 67108879, 788973880, 0); // [time: 550ns -> 560ns] - read(15, 67108872, 3880977277, 0); // [time: 560ns -> 570ns] - read(15, 67108873, 4096708504, 0); // [time: 570ns -> 580ns] - reset(); // [time: 620.001ns -> 630.001ns] - reset(); // [time: 630.001ns -> 640.001ns] - reset(); // [time: 640.001ns -> 650.001ns] - write(15, 67108866, 2427636421, 0); // [time: 690.001ns -> 710.001ns] - write(15, 67108867, 3595099675, 0); // [time: 710.001ns -> 720.001ns] - write(15, 67108868, 2668681316, 0); // [time: 720.001ns -> 730.001ns] - write(15, 67108869, 1679837987, 0); // [time: 730.001ns -> 740.001ns] - write(15, 67108870, 924732013, 0); // [time: 740.001ns -> 750.001ns] - write(15, 67108871, 2192079403, 0); // [time: 750.001ns -> 760.001ns] - write(15, 67108864, 2042051660, 0); // [time: 760.001ns -> 770.001ns] - write(15, 67108865, 989927686, 0); // [time: 770.001ns -> 780.001ns] - write(15, 67108874, 3067406900, 0); // [time: 780.001ns -> 790.001ns] - write(15, 67108875, 1058215073, 0); // [time: 790.001ns -> 800.001ns] - write(15, 67108876, 365012335, 0); // [time: 800.001ns -> 810.001ns] - write(15, 67108877, 687295108, 0); // [time: 810.001ns -> 820.001ns] - write(15, 67108878, 2829218573, 0); // [time: 820.001ns -> 830.001ns] - write(15, 67108879, 1448409262, 0); // [time: 830.001ns -> 840.001ns] - write(15, 67108872, 400594486, 0); // [time: 840.001ns -> 850.001ns] - write(15, 67108873, 4177343116, 0); // [time: 850.001ns -> 860.001ns] - reset(); // [time: 1540.002ns -> 1550.002ns] - reset(); // [time: 1550.002ns -> 1560.002ns] - reset(); // [time: 1560.002ns -> 1570.002ns] - write(15, 67108866, 2304668716, 0); // [time: 1610.002ns -> 1630.002ns] - write(15, 67108867, 2610611482, 0); // [time: 1630.002ns -> 1640.002ns] - write(15, 67108868, 1468153982, 0); // [time: 1640.002ns -> 1650.002ns] - write(15, 67108869, 1169841342, 0); // [time: 1650.002ns -> 1660.002ns] - write(15, 67108870, 27036823, 0); // [time: 1660.002ns -> 1670.002ns] - write(15, 67108871, 73783758, 0); // [time: 1670.002ns -> 1680.002ns] - write(15, 67108864, 1621524717, 0); // [time: 1680.002ns -> 1690.002ns] - write(15, 67108865, 3905946412, 0); // [time: 1690.002ns -> 1700.002ns] - write(15, 67108874, 1563100034, 0); // [time: 1700.002ns -> 1710.002ns] - write(15, 67108875, 2069336907, 0); // [time: 1710.002ns -> 1720.002ns] - write(15, 67108876, 583373053, 0); // [time: 1720.002ns -> 1730.002ns] - write(15, 67108877, 3629920426, 0); // [time: 1730.002ns -> 1740.002ns] - write(15, 67108878, 2146122704, 0); // [time: 1740.002ns -> 1750.002ns] - write(15, 67108879, 2674258699, 0); // [time: 1750.002ns -> 1760.002ns] - write(15, 67108872, 1361676606, 0); // [time: 1760.002ns -> 1770.002ns] - write(15, 67108873, 2435452493, 0); // [time: 1770.002ns -> 1780.002ns] - read(15, 67108866, 2304668716, 0); // [time: 1780.002ns -> 1800.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_8_3.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_8_3.monitor.expect deleted file mode 100644 index 6e117e35..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_8_3.monitor.expect +++ /dev/null @@ -1,61 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108866, 2727164243, 0); // [time: 410ns -> 430ns] - read(15, 67108867, 1384255697, 0); // [time: 430ns -> 440ns] - read(15, 67108868, 4216231340, 0); // [time: 440ns -> 450ns] - read(15, 67108869, 1661993927, 0); // [time: 450ns -> 460ns] - read(15, 67108870, 159950269, 0); // [time: 460ns -> 470ns] - read(15, 67108871, 893905490, 0); // [time: 470ns -> 480ns] - read(15, 67108872, 1464841894, 0); // [time: 480ns -> 490ns] - read(15, 67108873, 710545966, 0); // [time: 490ns -> 500ns] - read(15, 67108874, 3482423916, 0); // [time: 500ns -> 510ns] - read(15, 67108875, 4068629318, 0); // [time: 510ns -> 520ns] - read(15, 67108876, 3266524719, 0); // [time: 520ns -> 530ns] - read(15, 67108877, 1808083576, 0); // [time: 530ns -> 540ns] - read(15, 67108878, 3562161795, 0); // [time: 540ns -> 550ns] - read(15, 67108879, 2984675510, 0); // [time: 550ns -> 560ns] - read(15, 67108864, 2475539812, 0); // [time: 560ns -> 570ns] - read(15, 67108865, 2138191023, 0); // [time: 570ns -> 580ns] - reset(); // [time: 620.001ns -> 630.001ns] - reset(); // [time: 630.001ns -> 640.001ns] - reset(); // [time: 640.001ns -> 650.001ns] - write(15, 67108866, 1599974119, 0); // [time: 690.001ns -> 710.001ns] - write(15, 67108867, 609858284, 0); // [time: 710.001ns -> 720.001ns] - write(15, 67108868, 1648881400, 0); // [time: 720.001ns -> 730.001ns] - write(15, 67108869, 572149112, 0); // [time: 730.001ns -> 740.001ns] - write(15, 67108870, 602124761, 0); // [time: 740.001ns -> 750.001ns] - write(15, 67108871, 3299652692, 0); // [time: 750.001ns -> 760.001ns] - write(15, 67108872, 1416165996, 0); // [time: 760.001ns -> 770.001ns] - write(15, 67108873, 1639735531, 0); // [time: 770.001ns -> 780.001ns] - write(15, 67108874, 941900856, 0); // [time: 780.001ns -> 790.001ns] - write(15, 67108875, 4103564658, 0); // [time: 790.001ns -> 800.001ns] - write(15, 67108876, 788749736, 0); // [time: 800.001ns -> 810.001ns] - write(15, 67108877, 1260615071, 0); // [time: 810.001ns -> 820.001ns] - write(15, 67108878, 2210117974, 0); // [time: 820.001ns -> 830.001ns] - write(15, 67108879, 2952803435, 0); // [time: 830.001ns -> 840.001ns] - write(15, 67108864, 441673600, 0); // [time: 840.001ns -> 850.001ns] - write(15, 67108865, 2137709866, 0); // [time: 850.001ns -> 860.001ns] - reset(); // [time: 1540.002ns -> 1550.002ns] - reset(); // [time: 1550.002ns -> 1560.002ns] - reset(); // [time: 1560.002ns -> 1570.002ns] - write(15, 67108866, 2898868374, 0); // [time: 1610.002ns -> 1630.002ns] - write(15, 67108867, 1922764675, 0); // [time: 1630.002ns -> 1640.002ns] - write(15, 67108868, 4256406750, 0); // [time: 1640.002ns -> 1650.002ns] - write(15, 67108869, 245447329, 0); // [time: 1650.002ns -> 1660.002ns] - write(15, 67108870, 3225897750, 0); // [time: 1660.002ns -> 1670.002ns] - write(15, 67108871, 1779082048, 0); // [time: 1670.002ns -> 1680.002ns] - write(15, 67108872, 1953003128, 0); // [time: 1680.002ns -> 1690.002ns] - write(15, 67108873, 4020445238, 0); // [time: 1690.002ns -> 1700.002ns] - write(15, 67108874, 2174587331, 0); // [time: 1700.002ns -> 1710.002ns] - write(15, 67108875, 1632125876, 0); // [time: 1710.002ns -> 1720.002ns] - write(15, 67108876, 340410721, 0); // [time: 1720.002ns -> 1730.002ns] - write(15, 67108877, 771941360, 0); // [time: 1730.002ns -> 1740.002ns] - write(15, 67108878, 2567244845, 0); // [time: 1740.002ns -> 1750.002ns] - write(15, 67108879, 899887853, 0); // [time: 1750.002ns -> 1760.002ns] - write(15, 67108864, 1674678715, 0); // [time: 1760.002ns -> 1770.002ns] - write(15, 67108865, 902429492, 0); // [time: 1770.002ns -> 1780.002ns] - read(15, 67108866, 2898868374, 0); // [time: 1780.002ns -> 1800.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_0_0.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_0_0.monitor.expect deleted file mode 100644 index c3a38561..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_0_0.monitor.expect +++ /dev/null @@ -1,16 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108864, 2205995893, 0); // [time: 110ns -> 130ns] - reset(); // [time: 170.001ns -> 180.001ns] - reset(); // [time: 180.001ns -> 190.001ns] - reset(); // [time: 190.001ns -> 200.001ns] - write(15, 67108864, 486560095, 0); // [time: 240.001ns -> 260.001ns] - reset(); // [time: 340.002ns -> 350.002ns] - reset(); // [time: 350.002ns -> 360.002ns] - reset(); // [time: 360.002ns -> 370.002ns] - write(15, 67108864, 4100133660, 0); // [time: 410.002ns -> 430.002ns] - read(15, 67108864, 4100133660, 0); // [time: 430.002ns -> 450.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_0_1.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_0_1.monitor.expect deleted file mode 100644 index aebae401..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_0_1.monitor.expect +++ /dev/null @@ -1,16 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108864, 518534189, 0); // [time: 110ns -> 130ns] - reset(); // [time: 170.001ns -> 180.001ns] - reset(); // [time: 180.001ns -> 190.001ns] - reset(); // [time: 190.001ns -> 200.001ns] - write(15, 67108864, 844695266, 0); // [time: 240.001ns -> 260.001ns] - reset(); // [time: 340.002ns -> 350.002ns] - reset(); // [time: 350.002ns -> 360.002ns] - reset(); // [time: 360.002ns -> 370.002ns] - write(15, 67108864, 3937184150, 0); // [time: 410.002ns -> 430.002ns] - read(15, 67108864, 3937184150, 0); // [time: 430.002ns -> 450.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_0_2.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_0_2.monitor.expect deleted file mode 100644 index b01c57c0..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_0_2.monitor.expect +++ /dev/null @@ -1,16 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108864, 3580256271, 0); // [time: 110ns -> 130ns] - reset(); // [time: 170.001ns -> 180.001ns] - reset(); // [time: 180.001ns -> 190.001ns] - reset(); // [time: 190.001ns -> 200.001ns] - write(15, 67108864, 1489666683, 0); // [time: 240.001ns -> 260.001ns] - reset(); // [time: 340.002ns -> 350.002ns] - reset(); // [time: 350.002ns -> 360.002ns] - reset(); // [time: 360.002ns -> 370.002ns] - write(15, 67108864, 3677074643, 0); // [time: 410.002ns -> 430.002ns] - read(15, 67108864, 3677074643, 0); // [time: 430.002ns -> 450.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_0_3.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_0_3.monitor.expect deleted file mode 100644 index 90e7d396..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_0_3.monitor.expect +++ /dev/null @@ -1,16 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108864, 1509562552, 0); // [time: 110ns -> 130ns] - reset(); // [time: 170.001ns -> 180.001ns] - reset(); // [time: 180.001ns -> 190.001ns] - reset(); // [time: 190.001ns -> 200.001ns] - write(15, 67108864, 2329347035, 0); // [time: 240.001ns -> 260.001ns] - reset(); // [time: 340.002ns -> 350.002ns] - reset(); // [time: 350.002ns -> 360.002ns] - reset(); // [time: 360.002ns -> 370.002ns] - write(15, 67108864, 3862381389, 0); // [time: 410.002ns -> 430.002ns] - read(15, 67108864, 3862381389, 0); // [time: 430.002ns -> 450.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_12_0.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_12_0.monitor.expect deleted file mode 100644 index f42edacc..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_12_0.monitor.expect +++ /dev/null @@ -1,16 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108867, 3597917862, 0); // [time: 110ns -> 130ns] - reset(); // [time: 170.001ns -> 180.001ns] - reset(); // [time: 180.001ns -> 190.001ns] - reset(); // [time: 190.001ns -> 200.001ns] - write(15, 67108867, 1298617733, 0); // [time: 240.001ns -> 260.001ns] - reset(); // [time: 340.002ns -> 350.002ns] - reset(); // [time: 350.002ns -> 360.002ns] - reset(); // [time: 360.002ns -> 370.002ns] - write(15, 67108867, 2330861729, 0); // [time: 410.002ns -> 430.002ns] - read(15, 67108867, 2330861729, 0); // [time: 430.002ns -> 450.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_12_1.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_12_1.monitor.expect deleted file mode 100644 index 896dad1e..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_12_1.monitor.expect +++ /dev/null @@ -1,16 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108867, 2821946881, 0); // [time: 110ns -> 130ns] - reset(); // [time: 170.001ns -> 180.001ns] - reset(); // [time: 180.001ns -> 190.001ns] - reset(); // [time: 190.001ns -> 200.001ns] - write(15, 67108867, 4080087070, 0); // [time: 240.001ns -> 260.001ns] - reset(); // [time: 340.002ns -> 350.002ns] - reset(); // [time: 350.002ns -> 360.002ns] - reset(); // [time: 360.002ns -> 370.002ns] - write(15, 67108867, 2243193877, 0); // [time: 410.002ns -> 430.002ns] - read(15, 67108867, 2243193877, 0); // [time: 430.002ns -> 450.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_12_2.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_12_2.monitor.expect deleted file mode 100644 index 247aef00..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_12_2.monitor.expect +++ /dev/null @@ -1,16 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108867, 869832817, 0); // [time: 110ns -> 130ns] - reset(); // [time: 170.001ns -> 180.001ns] - reset(); // [time: 180.001ns -> 190.001ns] - reset(); // [time: 190.001ns -> 200.001ns] - write(15, 67108867, 2976082601, 0); // [time: 240.001ns -> 260.001ns] - reset(); // [time: 340.002ns -> 350.002ns] - reset(); // [time: 350.002ns -> 360.002ns] - reset(); // [time: 360.002ns -> 370.002ns] - write(15, 67108867, 373695501, 0); // [time: 410.002ns -> 430.002ns] - read(15, 67108867, 373695501, 0); // [time: 430.002ns -> 450.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_12_3.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_12_3.monitor.expect deleted file mode 100644 index 464cc88c..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_12_3.monitor.expect +++ /dev/null @@ -1,16 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108867, 1509562552, 0); // [time: 110ns -> 130ns] - reset(); // [time: 170.001ns -> 180.001ns] - reset(); // [time: 180.001ns -> 190.001ns] - reset(); // [time: 190.001ns -> 200.001ns] - write(15, 67108867, 2329347035, 0); // [time: 240.001ns -> 260.001ns] - reset(); // [time: 340.002ns -> 350.002ns] - reset(); // [time: 350.002ns -> 360.002ns] - reset(); // [time: 360.002ns -> 370.002ns] - write(15, 67108867, 3862381389, 0); // [time: 410.002ns -> 430.002ns] - read(15, 67108867, 3862381389, 0); // [time: 430.002ns -> 450.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_4_0.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_4_0.monitor.expect deleted file mode 100644 index 2cd9a72f..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_4_0.monitor.expect +++ /dev/null @@ -1,16 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108865, 1691632885, 0); // [time: 110ns -> 130ns] - reset(); // [time: 170.001ns -> 180.001ns] - reset(); // [time: 180.001ns -> 190.001ns] - reset(); // [time: 190.001ns -> 200.001ns] - write(15, 67108865, 3547248670, 0); // [time: 240.001ns -> 260.001ns] - reset(); // [time: 340.002ns -> 350.002ns] - reset(); // [time: 350.002ns -> 360.002ns] - reset(); // [time: 360.002ns -> 370.002ns] - write(15, 67108865, 665751263, 0); // [time: 410.002ns -> 430.002ns] - read(15, 67108865, 665751263, 0); // [time: 430.002ns -> 450.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_4_1.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_4_1.monitor.expect deleted file mode 100644 index 80edb357..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_4_1.monitor.expect +++ /dev/null @@ -1,16 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108865, 518534189, 0); // [time: 110ns -> 130ns] - reset(); // [time: 170.001ns -> 180.001ns] - reset(); // [time: 180.001ns -> 190.001ns] - reset(); // [time: 190.001ns -> 200.001ns] - write(15, 67108865, 844695266, 0); // [time: 240.001ns -> 260.001ns] - reset(); // [time: 340.002ns -> 350.002ns] - reset(); // [time: 350.002ns -> 360.002ns] - reset(); // [time: 360.002ns -> 370.002ns] - write(15, 67108865, 3937184150, 0); // [time: 410.002ns -> 430.002ns] - read(15, 67108865, 3937184150, 0); // [time: 430.002ns -> 450.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_4_2.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_4_2.monitor.expect deleted file mode 100644 index 7cdb5ea7..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_4_2.monitor.expect +++ /dev/null @@ -1,16 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108865, 1016512136, 0); // [time: 110ns -> 130ns] - reset(); // [time: 170.001ns -> 180.001ns] - reset(); // [time: 180.001ns -> 190.001ns] - reset(); // [time: 190.001ns -> 200.001ns] - write(15, 67108865, 226204128, 0); // [time: 240.001ns -> 260.001ns] - reset(); // [time: 340.002ns -> 350.002ns] - reset(); // [time: 350.002ns -> 360.002ns] - reset(); // [time: 360.002ns -> 370.002ns] - write(15, 67108865, 2116565440, 0); // [time: 410.002ns -> 430.002ns] - read(15, 67108865, 2116565440, 0); // [time: 430.002ns -> 450.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_4_3.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_4_3.monitor.expect deleted file mode 100644 index 67edd59f..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_4_3.monitor.expect +++ /dev/null @@ -1,16 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108865, 3495738447, 0); // [time: 110ns -> 130ns] - reset(); // [time: 170.001ns -> 180.001ns] - reset(); // [time: 180.001ns -> 190.001ns] - reset(); // [time: 190.001ns -> 200.001ns] - write(15, 67108865, 1478546475, 0); // [time: 240.001ns -> 260.001ns] - reset(); // [time: 340.002ns -> 350.002ns] - reset(); // [time: 350.002ns -> 360.002ns] - reset(); // [time: 360.002ns -> 370.002ns] - write(15, 67108865, 2041778918, 0); // [time: 410.002ns -> 430.002ns] - read(15, 67108865, 2041778918, 0); // [time: 430.002ns -> 450.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_8_0.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_8_0.monitor.expect deleted file mode 100644 index 07c59046..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_8_0.monitor.expect +++ /dev/null @@ -1,16 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108866, 1691632885, 0); // [time: 110ns -> 130ns] - reset(); // [time: 170.001ns -> 180.001ns] - reset(); // [time: 180.001ns -> 190.001ns] - reset(); // [time: 190.001ns -> 200.001ns] - write(15, 67108866, 3547248670, 0); // [time: 240.001ns -> 260.001ns] - reset(); // [time: 340.002ns -> 350.002ns] - reset(); // [time: 350.002ns -> 360.002ns] - reset(); // [time: 360.002ns -> 370.002ns] - write(15, 67108866, 665751263, 0); // [time: 410.002ns -> 430.002ns] - read(15, 67108866, 665751263, 0); // [time: 430.002ns -> 450.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_8_1.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_8_1.monitor.expect deleted file mode 100644 index 7414ac38..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_8_1.monitor.expect +++ /dev/null @@ -1,16 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108866, 2821946881, 0); // [time: 110ns -> 130ns] - reset(); // [time: 170.001ns -> 180.001ns] - reset(); // [time: 180.001ns -> 190.001ns] - reset(); // [time: 190.001ns -> 200.001ns] - write(15, 67108866, 4080087070, 0); // [time: 240.001ns -> 260.001ns] - reset(); // [time: 340.002ns -> 350.002ns] - reset(); // [time: 350.002ns -> 360.002ns] - reset(); // [time: 360.002ns -> 370.002ns] - write(15, 67108866, 2243193877, 0); // [time: 410.002ns -> 430.002ns] - read(15, 67108866, 2243193877, 0); // [time: 430.002ns -> 450.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_8_2.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_8_2.monitor.expect deleted file mode 100644 index 020b204d..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_8_2.monitor.expect +++ /dev/null @@ -1,16 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108866, 1016512136, 0); // [time: 110ns -> 130ns] - reset(); // [time: 170.001ns -> 180.001ns] - reset(); // [time: 180.001ns -> 190.001ns] - reset(); // [time: 190.001ns -> 200.001ns] - write(15, 67108866, 226204128, 0); // [time: 240.001ns -> 260.001ns] - reset(); // [time: 340.002ns -> 350.002ns] - reset(); // [time: 350.002ns -> 360.002ns] - reset(); // [time: 360.002ns -> 370.002ns] - write(15, 67108866, 2116565440, 0); // [time: 410.002ns -> 430.002ns] - read(15, 67108866, 2116565440, 0); // [time: 430.002ns -> 450.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_8_3.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_8_3.monitor.expect deleted file mode 100644 index 288751ac..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_8_3.monitor.expect +++ /dev/null @@ -1,16 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108866, 3495738447, 0); // [time: 110ns -> 130ns] - reset(); // [time: 170.001ns -> 180.001ns] - reset(); // [time: 180.001ns -> 190.001ns] - reset(); // [time: 190.001ns -> 200.001ns] - write(15, 67108866, 1478546475, 0); // [time: 240.001ns -> 260.001ns] - reset(); // [time: 340.002ns -> 350.002ns] - reset(); // [time: 350.002ns -> 360.002ns] - reset(); // [time: 360.002ns -> 370.002ns] - write(15, 67108866, 2041778918, 0); // [time: 410.002ns -> 430.002ns] - read(15, 67108866, 2041778918, 0); // [time: 430.002ns -> 450.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_0_0.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_0_0.monitor.expect deleted file mode 100644 index 883ac1d5..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_0_0.monitor.expect +++ /dev/null @@ -1,19 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108864, 3597917862, 0); // [time: 130ns -> 150ns] - read(15, 67108865, 1298617733, 0); // [time: 150ns -> 160ns] - reset(); // [time: 200.001ns -> 210.001ns] - reset(); // [time: 210.001ns -> 220.001ns] - reset(); // [time: 220.001ns -> 230.001ns] - write(15, 67108864, 2330861729, 0); // [time: 270.001ns -> 290.001ns] - write(15, 67108865, 4289318346, 0); // [time: 290.001ns -> 300.001ns] - reset(); // [time: 420.002ns -> 430.002ns] - reset(); // [time: 430.002ns -> 440.002ns] - reset(); // [time: 440.002ns -> 450.002ns] - write(15, 67108864, 2756621846, 0); // [time: 490.002ns -> 510.002ns] - write(15, 67108865, 1627127952, 0); // [time: 510.002ns -> 520.002ns] - read(15, 67108864, 2756621846, 0); // [time: 520.002ns -> 540.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_0_1.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_0_1.monitor.expect deleted file mode 100644 index 52f2a7ab..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_0_1.monitor.expect +++ /dev/null @@ -1,19 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108864, 3580256271, 0); // [time: 130ns -> 150ns] - read(15, 67108865, 1489666683, 0); // [time: 150ns -> 160ns] - reset(); // [time: 200.001ns -> 210.001ns] - reset(); // [time: 210.001ns -> 220.001ns] - reset(); // [time: 220.001ns -> 230.001ns] - write(15, 67108864, 3677074643, 0); // [time: 270.001ns -> 290.001ns] - write(15, 67108865, 1878953054, 0); // [time: 290.001ns -> 300.001ns] - reset(); // [time: 420.002ns -> 430.002ns] - reset(); // [time: 430.002ns -> 440.002ns] - reset(); // [time: 440.002ns -> 450.002ns] - write(15, 67108864, 2965505115, 0); // [time: 490.002ns -> 510.002ns] - write(15, 67108865, 3259566096, 0); // [time: 510.002ns -> 520.002ns] - read(15, 67108864, 2965505115, 0); // [time: 520.002ns -> 540.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_0_2.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_0_2.monitor.expect deleted file mode 100644 index c67de0c0..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_0_2.monitor.expect +++ /dev/null @@ -1,19 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108864, 869832817, 0); // [time: 130ns -> 150ns] - read(15, 67108865, 2976082601, 0); // [time: 150ns -> 160ns] - reset(); // [time: 200.001ns -> 210.001ns] - reset(); // [time: 210.001ns -> 220.001ns] - reset(); // [time: 220.001ns -> 230.001ns] - write(15, 67108864, 373695501, 0); // [time: 270.001ns -> 290.001ns] - write(15, 67108865, 2110838384, 0); // [time: 290.001ns -> 300.001ns] - reset(); // [time: 420.002ns -> 430.002ns] - reset(); // [time: 430.002ns -> 440.002ns] - reset(); // [time: 440.002ns -> 450.002ns] - write(15, 67108864, 3556455435, 0); // [time: 490.002ns -> 510.002ns] - write(15, 67108865, 1804567173, 0); // [time: 510.002ns -> 520.002ns] - read(15, 67108864, 3556455435, 0); // [time: 520.002ns -> 540.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_0_3.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_0_3.monitor.expect deleted file mode 100644 index 9948b2bc..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_0_3.monitor.expect +++ /dev/null @@ -1,19 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108864, 3495738447, 0); // [time: 130ns -> 150ns] - read(15, 67108865, 1478546475, 0); // [time: 150ns -> 160ns] - reset(); // [time: 200.001ns -> 210.001ns] - reset(); // [time: 210.001ns -> 220.001ns] - reset(); // [time: 220.001ns -> 230.001ns] - write(15, 67108864, 2041778918, 0); // [time: 270.001ns -> 290.001ns] - write(15, 67108865, 3032895213, 0); // [time: 290.001ns -> 300.001ns] - reset(); // [time: 420.002ns -> 430.002ns] - reset(); // [time: 430.002ns -> 440.002ns] - reset(); // [time: 440.002ns -> 450.002ns] - write(15, 67108864, 2020268309, 0); // [time: 490.002ns -> 510.002ns] - write(15, 67108865, 3122719830, 0); // [time: 510.002ns -> 520.002ns] - read(15, 67108864, 2020268309, 0); // [time: 520.002ns -> 540.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_12_0.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_12_0.monitor.expect deleted file mode 100644 index bbe1f1e4..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_12_0.monitor.expect +++ /dev/null @@ -1,19 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108867, 2205995893, 0); // [time: 130ns -> 150ns] - read(15, 67108868, 486560095, 0); // [time: 150ns -> 160ns] - reset(); // [time: 200.001ns -> 210.001ns] - reset(); // [time: 210.001ns -> 220.001ns] - reset(); // [time: 220.001ns -> 230.001ns] - write(15, 67108867, 4100133660, 0); // [time: 270.001ns -> 290.001ns] - write(15, 67108868, 596618694, 0); // [time: 290.001ns -> 300.001ns] - reset(); // [time: 420.002ns -> 430.002ns] - reset(); // [time: 430.002ns -> 440.002ns] - reset(); // [time: 440.002ns -> 450.002ns] - write(15, 67108867, 3499942130, 0); // [time: 490.002ns -> 510.002ns] - write(15, 67108868, 2357711907, 0); // [time: 510.002ns -> 520.002ns] - read(15, 67108867, 3499942130, 0); // [time: 520.002ns -> 540.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_12_1.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_12_1.monitor.expect deleted file mode 100644 index 7b49175b..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_12_1.monitor.expect +++ /dev/null @@ -1,19 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108867, 1833423740, 0); // [time: 130ns -> 150ns] - read(15, 67108864, 4073618608, 0); // [time: 150ns -> 160ns] - reset(); // [time: 200.001ns -> 210.001ns] - reset(); // [time: 210.001ns -> 220.001ns] - reset(); // [time: 220.001ns -> 230.001ns] - write(15, 67108867, 3418745219, 0); // [time: 270.001ns -> 290.001ns] - write(15, 67108864, 3757272308, 0); // [time: 290.001ns -> 300.001ns] - reset(); // [time: 420.002ns -> 430.002ns] - reset(); // [time: 430.002ns -> 440.002ns] - reset(); // [time: 440.002ns -> 450.002ns] - write(15, 67108867, 1325530178, 0); // [time: 490.002ns -> 510.002ns] - write(15, 67108864, 1451722922, 0); // [time: 510.002ns -> 520.002ns] - read(15, 67108867, 1325530178, 0); // [time: 520.002ns -> 540.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_12_2.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_12_2.monitor.expect deleted file mode 100644 index 9971ed4a..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_12_2.monitor.expect +++ /dev/null @@ -1,19 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108867, 1016512136, 0); // [time: 130ns -> 150ns] - read(15, 67108868, 226204128, 0); // [time: 150ns -> 160ns] - reset(); // [time: 200.001ns -> 210.001ns] - reset(); // [time: 210.001ns -> 220.001ns] - reset(); // [time: 220.001ns -> 230.001ns] - write(15, 67108867, 2116565440, 0); // [time: 270.001ns -> 290.001ns] - write(15, 67108868, 2153688786, 0); // [time: 290.001ns -> 300.001ns] - reset(); // [time: 420.002ns -> 430.002ns] - reset(); // [time: 430.002ns -> 440.002ns] - reset(); // [time: 440.002ns -> 450.002ns] - write(15, 67108867, 1974223269, 0); // [time: 490.002ns -> 510.002ns] - write(15, 67108868, 1053640572, 0); // [time: 510.002ns -> 520.002ns] - read(15, 67108867, 1974223269, 0); // [time: 520.002ns -> 540.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_12_3.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_12_3.monitor.expect deleted file mode 100644 index 11bf515e..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_12_3.monitor.expect +++ /dev/null @@ -1,19 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108867, 1509562552, 0); // [time: 130ns -> 150ns] - read(15, 67108868, 2329347035, 0); // [time: 150ns -> 160ns] - reset(); // [time: 200.001ns -> 210.001ns] - reset(); // [time: 210.001ns -> 220.001ns] - reset(); // [time: 220.001ns -> 230.001ns] - write(15, 67108867, 3862381389, 0); // [time: 270.001ns -> 290.001ns] - write(15, 67108868, 1142123500, 0); // [time: 290.001ns -> 300.001ns] - reset(); // [time: 420.002ns -> 430.002ns] - reset(); // [time: 430.002ns -> 440.002ns] - reset(); // [time: 440.002ns -> 450.002ns] - write(15, 67108867, 3598508010, 0); // [time: 490.002ns -> 510.002ns] - write(15, 67108868, 908644471, 0); // [time: 510.002ns -> 520.002ns] - read(15, 67108867, 3598508010, 0); // [time: 520.002ns -> 540.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_4_0.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_4_0.monitor.expect deleted file mode 100644 index 5c52c496..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_4_0.monitor.expect +++ /dev/null @@ -1,19 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108865, 2950170166, 0); // [time: 130ns -> 150ns] - read(15, 67108866, 2782447364, 0); // [time: 150ns -> 160ns] - reset(); // [time: 200.001ns -> 210.001ns] - reset(); // [time: 210.001ns -> 220.001ns] - reset(); // [time: 220.001ns -> 230.001ns] - write(15, 67108865, 2586475175, 0); // [time: 270.001ns -> 290.001ns] - write(15, 67108866, 2087441910, 0); // [time: 290.001ns -> 300.001ns] - reset(); // [time: 420.002ns -> 430.002ns] - reset(); // [time: 430.002ns -> 440.002ns] - reset(); // [time: 440.002ns -> 450.002ns] - write(15, 67108865, 3875005491, 0); // [time: 490.002ns -> 510.002ns] - write(15, 67108866, 2597527218, 0); // [time: 510.002ns -> 520.002ns] - read(15, 67108865, 3875005491, 0); // [time: 520.002ns -> 540.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_4_1.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_4_1.monitor.expect deleted file mode 100644 index 0ae4956e..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_4_1.monitor.expect +++ /dev/null @@ -1,19 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108865, 3580256271, 0); // [time: 130ns -> 150ns] - read(15, 67108866, 1489666683, 0); // [time: 150ns -> 160ns] - reset(); // [time: 200.001ns -> 210.001ns] - reset(); // [time: 210.001ns -> 220.001ns] - reset(); // [time: 220.001ns -> 230.001ns] - write(15, 67108865, 3677074643, 0); // [time: 270.001ns -> 290.001ns] - write(15, 67108866, 1878953054, 0); // [time: 290.001ns -> 300.001ns] - reset(); // [time: 420.002ns -> 430.002ns] - reset(); // [time: 430.002ns -> 440.002ns] - reset(); // [time: 440.002ns -> 450.002ns] - write(15, 67108865, 2965505115, 0); // [time: 490.002ns -> 510.002ns] - write(15, 67108866, 3259566096, 0); // [time: 510.002ns -> 520.002ns] - read(15, 67108865, 2965505115, 0); // [time: 520.002ns -> 540.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_4_2.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_4_2.monitor.expect deleted file mode 100644 index 0ae4956e..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_4_2.monitor.expect +++ /dev/null @@ -1,19 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108865, 3580256271, 0); // [time: 130ns -> 150ns] - read(15, 67108866, 1489666683, 0); // [time: 150ns -> 160ns] - reset(); // [time: 200.001ns -> 210.001ns] - reset(); // [time: 210.001ns -> 220.001ns] - reset(); // [time: 220.001ns -> 230.001ns] - write(15, 67108865, 3677074643, 0); // [time: 270.001ns -> 290.001ns] - write(15, 67108866, 1878953054, 0); // [time: 290.001ns -> 300.001ns] - reset(); // [time: 420.002ns -> 430.002ns] - reset(); // [time: 430.002ns -> 440.002ns] - reset(); // [time: 440.002ns -> 450.002ns] - write(15, 67108865, 2965505115, 0); // [time: 490.002ns -> 510.002ns] - write(15, 67108866, 3259566096, 0); // [time: 510.002ns -> 520.002ns] - read(15, 67108865, 2965505115, 0); // [time: 520.002ns -> 540.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_4_3.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_4_3.monitor.expect deleted file mode 100644 index e2edd110..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_4_3.monitor.expect +++ /dev/null @@ -1,19 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108865, 3495738447, 0); // [time: 130ns -> 150ns] - read(15, 67108866, 1478546475, 0); // [time: 150ns -> 160ns] - reset(); // [time: 200.001ns -> 210.001ns] - reset(); // [time: 210.001ns -> 220.001ns] - reset(); // [time: 220.001ns -> 230.001ns] - write(15, 67108865, 2041778918, 0); // [time: 270.001ns -> 290.001ns] - write(15, 67108866, 3032895213, 0); // [time: 290.001ns -> 300.001ns] - reset(); // [time: 420.002ns -> 430.002ns] - reset(); // [time: 430.002ns -> 440.002ns] - reset(); // [time: 440.002ns -> 450.002ns] - write(15, 67108865, 2020268309, 0); // [time: 490.002ns -> 510.002ns] - write(15, 67108866, 3122719830, 0); // [time: 510.002ns -> 520.002ns] - read(15, 67108865, 2020268309, 0); // [time: 520.002ns -> 540.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_8_0.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_8_0.monitor.expect deleted file mode 100644 index d973d119..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_8_0.monitor.expect +++ /dev/null @@ -1,19 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108866, 2950170166, 0); // [time: 130ns -> 150ns] - read(15, 67108867, 2782447364, 0); // [time: 150ns -> 160ns] - reset(); // [time: 200.001ns -> 210.001ns] - reset(); // [time: 210.001ns -> 220.001ns] - reset(); // [time: 220.001ns -> 230.001ns] - write(15, 67108866, 2586475175, 0); // [time: 270.001ns -> 290.001ns] - write(15, 67108867, 2087441910, 0); // [time: 290.001ns -> 300.001ns] - reset(); // [time: 420.002ns -> 430.002ns] - reset(); // [time: 430.002ns -> 440.002ns] - reset(); // [time: 440.002ns -> 450.002ns] - write(15, 67108866, 3875005491, 0); // [time: 490.002ns -> 510.002ns] - write(15, 67108867, 2597527218, 0); // [time: 510.002ns -> 520.002ns] - read(15, 67108866, 3875005491, 0); // [time: 520.002ns -> 540.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_8_1.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_8_1.monitor.expect deleted file mode 100644 index b22b7107..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_8_1.monitor.expect +++ /dev/null @@ -1,19 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108866, 2205995893, 0); // [time: 130ns -> 150ns] - read(15, 67108867, 486560095, 0); // [time: 150ns -> 160ns] - reset(); // [time: 200.001ns -> 210.001ns] - reset(); // [time: 210.001ns -> 220.001ns] - reset(); // [time: 220.001ns -> 230.001ns] - write(15, 67108866, 4100133660, 0); // [time: 270.001ns -> 290.001ns] - write(15, 67108867, 596618694, 0); // [time: 290.001ns -> 300.001ns] - reset(); // [time: 420.002ns -> 430.002ns] - reset(); // [time: 430.002ns -> 440.002ns] - reset(); // [time: 440.002ns -> 450.002ns] - write(15, 67108866, 3499942130, 0); // [time: 490.002ns -> 510.002ns] - write(15, 67108867, 2357711907, 0); // [time: 510.002ns -> 520.002ns] - read(15, 67108866, 3499942130, 0); // [time: 520.002ns -> 540.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_8_2.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_8_2.monitor.expect deleted file mode 100644 index 684182f5..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_8_2.monitor.expect +++ /dev/null @@ -1,19 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108866, 1016512136, 0); // [time: 130ns -> 150ns] - read(15, 67108867, 226204128, 0); // [time: 150ns -> 160ns] - reset(); // [time: 200.001ns -> 210.001ns] - reset(); // [time: 210.001ns -> 220.001ns] - reset(); // [time: 220.001ns -> 230.001ns] - write(15, 67108866, 2116565440, 0); // [time: 270.001ns -> 290.001ns] - write(15, 67108867, 2153688786, 0); // [time: 290.001ns -> 300.001ns] - reset(); // [time: 420.002ns -> 430.002ns] - reset(); // [time: 430.002ns -> 440.002ns] - reset(); // [time: 440.002ns -> 450.002ns] - write(15, 67108866, 1974223269, 0); // [time: 490.002ns -> 510.002ns] - write(15, 67108867, 1053640572, 0); // [time: 510.002ns -> 520.002ns] - read(15, 67108866, 1974223269, 0); // [time: 520.002ns -> 540.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_8_3.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_8_3.monitor.expect deleted file mode 100644 index 2328e1f0..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_8_3.monitor.expect +++ /dev/null @@ -1,19 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108866, 1509562552, 0); // [time: 130ns -> 150ns] - read(15, 67108867, 2329347035, 0); // [time: 150ns -> 160ns] - reset(); // [time: 200.001ns -> 210.001ns] - reset(); // [time: 210.001ns -> 220.001ns] - reset(); // [time: 220.001ns -> 230.001ns] - write(15, 67108866, 3862381389, 0); // [time: 270.001ns -> 290.001ns] - write(15, 67108867, 1142123500, 0); // [time: 290.001ns -> 300.001ns] - reset(); // [time: 420.002ns -> 430.002ns] - reset(); // [time: 430.002ns -> 440.002ns] - reset(); // [time: 440.002ns -> 450.002ns] - write(15, 67108866, 3598508010, 0); // [time: 490.002ns -> 510.002ns] - write(15, 67108867, 908644471, 0); // [time: 510.002ns -> 520.002ns] - read(15, 67108866, 3598508010, 0); // [time: 520.002ns -> 540.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_0_0.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_0_0.monitor.expect deleted file mode 100644 index 866952c5..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_0_0.monitor.expect +++ /dev/null @@ -1,25 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108864, 2205995893, 0); // [time: 170ns -> 190ns] - read(15, 67108865, 486560095, 0); // [time: 190ns -> 200ns] - read(15, 67108866, 4100133660, 0); // [time: 200ns -> 210ns] - read(15, 67108867, 596618694, 0); // [time: 210ns -> 220ns] - reset(); // [time: 260.001ns -> 270.001ns] - reset(); // [time: 270.001ns -> 280.001ns] - reset(); // [time: 280.001ns -> 290.001ns] - write(15, 67108864, 3499942130, 0); // [time: 330.001ns -> 350.001ns] - write(15, 67108865, 2357711907, 0); // [time: 350.001ns -> 360.001ns] - write(15, 67108866, 2086526797, 0); // [time: 360.001ns -> 370.001ns] - write(15, 67108867, 364077448, 0); // [time: 370.001ns -> 380.001ns] - reset(); // [time: 580.002ns -> 590.002ns] - reset(); // [time: 590.002ns -> 600.002ns] - reset(); // [time: 600.002ns -> 610.002ns] - write(15, 67108864, 210674739, 0); // [time: 650.002ns -> 670.002ns] - write(15, 67108865, 1567286535, 0); // [time: 670.002ns -> 680.002ns] - write(15, 67108866, 922799025, 0); // [time: 680.002ns -> 690.002ns] - write(15, 67108867, 4171757579, 0); // [time: 690.002ns -> 700.002ns] - read(15, 67108864, 210674739, 0); // [time: 700.002ns -> 720.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_0_1.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_0_1.monitor.expect deleted file mode 100644 index 0c3bcb95..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_0_1.monitor.expect +++ /dev/null @@ -1,25 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108864, 1833423740, 0); // [time: 170ns -> 190ns] - read(15, 67108865, 4073618608, 0); // [time: 190ns -> 200ns] - read(15, 67108866, 3418745219, 0); // [time: 200ns -> 210ns] - read(15, 67108867, 3757272308, 0); // [time: 210ns -> 220ns] - reset(); // [time: 260.001ns -> 270.001ns] - reset(); // [time: 270.001ns -> 280.001ns] - reset(); // [time: 280.001ns -> 290.001ns] - write(15, 67108864, 1325530178, 0); // [time: 330.001ns -> 350.001ns] - write(15, 67108865, 1451722922, 0); // [time: 350.001ns -> 360.001ns] - write(15, 67108866, 1997677454, 0); // [time: 360.001ns -> 370.001ns] - write(15, 67108867, 986005841, 0); // [time: 370.001ns -> 380.001ns] - reset(); // [time: 580.002ns -> 590.002ns] - reset(); // [time: 590.002ns -> 600.002ns] - reset(); // [time: 600.002ns -> 610.002ns] - write(15, 67108864, 789975088, 0); // [time: 650.002ns -> 670.002ns] - write(15, 67108865, 3746918692, 0); // [time: 670.002ns -> 680.002ns] - write(15, 67108866, 410224063, 0); // [time: 680.002ns -> 690.002ns] - write(15, 67108867, 864118294, 0); // [time: 690.002ns -> 700.002ns] - read(15, 67108864, 789975088, 0); // [time: 700.002ns -> 720.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_0_2.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_0_2.monitor.expect deleted file mode 100644 index 17c05629..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_0_2.monitor.expect +++ /dev/null @@ -1,25 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108864, 869832817, 0); // [time: 170ns -> 190ns] - read(15, 67108865, 2976082601, 0); // [time: 190ns -> 200ns] - read(15, 67108866, 373695501, 0); // [time: 200ns -> 210ns] - read(15, 67108867, 2110838384, 0); // [time: 210ns -> 220ns] - reset(); // [time: 260.001ns -> 270.001ns] - reset(); // [time: 270.001ns -> 280.001ns] - reset(); // [time: 280.001ns -> 290.001ns] - write(15, 67108864, 3556455435, 0); // [time: 330.001ns -> 350.001ns] - write(15, 67108865, 1804567173, 0); // [time: 350.001ns -> 360.001ns] - write(15, 67108866, 1187331577, 0); // [time: 360.001ns -> 370.001ns] - write(15, 67108867, 1293993917, 0); // [time: 370.001ns -> 380.001ns] - reset(); // [time: 580.002ns -> 590.002ns] - reset(); // [time: 590.002ns -> 600.002ns] - reset(); // [time: 600.002ns -> 610.002ns] - write(15, 67108864, 753581369, 0); // [time: 650.002ns -> 670.002ns] - write(15, 67108865, 2300246917, 0); // [time: 670.002ns -> 680.002ns] - write(15, 67108866, 3523846629, 0); // [time: 680.002ns -> 690.002ns] - write(15, 67108867, 3751494934, 0); // [time: 690.002ns -> 700.002ns] - read(15, 67108864, 753581369, 0); // [time: 700.002ns -> 720.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_0_3.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_0_3.monitor.expect deleted file mode 100644 index 7251b862..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_0_3.monitor.expect +++ /dev/null @@ -1,25 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108864, 1509562552, 0); // [time: 170ns -> 190ns] - read(15, 67108865, 2329347035, 0); // [time: 190ns -> 200ns] - read(15, 67108866, 3862381389, 0); // [time: 200ns -> 210ns] - read(15, 67108867, 1142123500, 0); // [time: 210ns -> 220ns] - reset(); // [time: 260.001ns -> 270.001ns] - reset(); // [time: 270.001ns -> 280.001ns] - reset(); // [time: 280.001ns -> 290.001ns] - write(15, 67108864, 3598508010, 0); // [time: 330.001ns -> 350.001ns] - write(15, 67108865, 908644471, 0); // [time: 350.001ns -> 360.001ns] - write(15, 67108866, 870782326, 0); // [time: 360.001ns -> 370.001ns] - write(15, 67108867, 1788061457, 0); // [time: 370.001ns -> 380.001ns] - reset(); // [time: 580.002ns -> 590.002ns] - reset(); // [time: 590.002ns -> 600.002ns] - reset(); // [time: 600.002ns -> 610.002ns] - write(15, 67108864, 1483205141, 0); // [time: 650.002ns -> 670.002ns] - write(15, 67108865, 408872453, 0); // [time: 670.002ns -> 680.002ns] - write(15, 67108866, 2880683308, 0); // [time: 680.002ns -> 690.002ns] - write(15, 67108867, 1446265757, 0); // [time: 690.002ns -> 700.002ns] - read(15, 67108864, 1483205141, 0); // [time: 700.002ns -> 720.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_12_0.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_12_0.monitor.expect deleted file mode 100644 index 74443970..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_12_0.monitor.expect +++ /dev/null @@ -1,25 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108867, 518534189, 0); // [time: 170ns -> 190ns] - read(15, 67108868, 844695266, 0); // [time: 190ns -> 200ns] - read(15, 67108869, 3937184150, 0); // [time: 200ns -> 210ns] - read(15, 67108870, 444246851, 0); // [time: 210ns -> 220ns] - reset(); // [time: 260.001ns -> 270.001ns] - reset(); // [time: 270.001ns -> 280.001ns] - reset(); // [time: 280.001ns -> 290.001ns] - write(15, 67108867, 3220682802, 0); // [time: 330.001ns -> 350.001ns] - write(15, 67108868, 2130811954, 0); // [time: 350.001ns -> 360.001ns] - write(15, 67108869, 2002127438, 0); // [time: 360.001ns -> 370.001ns] - write(15, 67108870, 493792053, 0); // [time: 370.001ns -> 380.001ns] - reset(); // [time: 580.002ns -> 590.002ns] - reset(); // [time: 590.002ns -> 600.002ns] - reset(); // [time: 600.002ns -> 610.002ns] - write(15, 67108867, 63714206, 0); // [time: 650.002ns -> 670.002ns] - write(15, 67108868, 2091823691, 0); // [time: 670.002ns -> 680.002ns] - write(15, 67108869, 3903276977, 0); // [time: 680.002ns -> 690.002ns] - write(15, 67108870, 1662756337, 0); // [time: 690.002ns -> 700.002ns] - read(15, 67108867, 63714206, 0); // [time: 700.002ns -> 720.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_12_1.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_12_1.monitor.expect deleted file mode 100644 index f3104619..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_12_1.monitor.expect +++ /dev/null @@ -1,25 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108867, 2821946881, 0); // [time: 170ns -> 190ns] - read(15, 67108864, 4080087070, 0); // [time: 190ns -> 200ns] - read(15, 67108865, 2243193877, 0); // [time: 200ns -> 210ns] - read(15, 67108866, 2472849580, 0); // [time: 210ns -> 220ns] - reset(); // [time: 260.001ns -> 270.001ns] - reset(); // [time: 270.001ns -> 280.001ns] - reset(); // [time: 280.001ns -> 290.001ns] - write(15, 67108867, 3565370026, 0); // [time: 330.001ns -> 350.001ns] - write(15, 67108864, 890985600, 0); // [time: 350.001ns -> 360.001ns] - write(15, 67108865, 4179549189, 0); // [time: 360.001ns -> 370.001ns] - write(15, 67108866, 4158632492, 0); // [time: 370.001ns -> 380.001ns] - reset(); // [time: 580.002ns -> 590.002ns] - reset(); // [time: 590.002ns -> 600.002ns] - reset(); // [time: 600.002ns -> 610.002ns] - write(15, 67108867, 3744957516, 0); // [time: 650.002ns -> 670.002ns] - write(15, 67108864, 2300150418, 0); // [time: 670.002ns -> 680.002ns] - write(15, 67108865, 2081940992, 0); // [time: 680.002ns -> 690.002ns] - write(15, 67108866, 1697819148, 0); // [time: 690.002ns -> 700.002ns] - read(15, 67108867, 3744957516, 0); // [time: 700.002ns -> 720.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_12_2.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_12_2.monitor.expect deleted file mode 100644 index 96a45f4c..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_12_2.monitor.expect +++ /dev/null @@ -1,25 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108867, 1016512136, 0); // [time: 170ns -> 190ns] - read(15, 67108868, 226204128, 0); // [time: 190ns -> 200ns] - read(15, 67108869, 2116565440, 0); // [time: 200ns -> 210ns] - read(15, 67108870, 2153688786, 0); // [time: 210ns -> 220ns] - reset(); // [time: 260.001ns -> 270.001ns] - reset(); // [time: 270.001ns -> 280.001ns] - reset(); // [time: 280.001ns -> 290.001ns] - write(15, 67108867, 1974223269, 0); // [time: 330.001ns -> 350.001ns] - write(15, 67108868, 1053640572, 0); // [time: 350.001ns -> 360.001ns] - write(15, 67108869, 2079860600, 0); // [time: 360.001ns -> 370.001ns] - write(15, 67108870, 3550045624, 0); // [time: 370.001ns -> 380.001ns] - reset(); // [time: 580.002ns -> 590.002ns] - reset(); // [time: 590.002ns -> 600.002ns] - reset(); // [time: 600.002ns -> 610.002ns] - write(15, 67108867, 1038322047, 0); // [time: 650.002ns -> 670.002ns] - write(15, 67108868, 1502718053, 0); // [time: 670.002ns -> 680.002ns] - write(15, 67108869, 1367070343, 0); // [time: 680.002ns -> 690.002ns] - write(15, 67108870, 3425882885, 0); // [time: 690.002ns -> 700.002ns] - read(15, 67108867, 1038322047, 0); // [time: 700.002ns -> 720.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_12_3.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_12_3.monitor.expect deleted file mode 100644 index 372b11fb..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_12_3.monitor.expect +++ /dev/null @@ -1,25 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108867, 1509562552, 0); // [time: 170ns -> 190ns] - read(15, 67108868, 2329347035, 0); // [time: 190ns -> 200ns] - read(15, 67108869, 3862381389, 0); // [time: 200ns -> 210ns] - read(15, 67108870, 1142123500, 0); // [time: 210ns -> 220ns] - reset(); // [time: 260.001ns -> 270.001ns] - reset(); // [time: 270.001ns -> 280.001ns] - reset(); // [time: 280.001ns -> 290.001ns] - write(15, 67108867, 3598508010, 0); // [time: 330.001ns -> 350.001ns] - write(15, 67108868, 908644471, 0); // [time: 350.001ns -> 360.001ns] - write(15, 67108869, 870782326, 0); // [time: 360.001ns -> 370.001ns] - write(15, 67108870, 1788061457, 0); // [time: 370.001ns -> 380.001ns] - reset(); // [time: 580.002ns -> 590.002ns] - reset(); // [time: 590.002ns -> 600.002ns] - reset(); // [time: 600.002ns -> 610.002ns] - write(15, 67108867, 1483205141, 0); // [time: 650.002ns -> 670.002ns] - write(15, 67108868, 408872453, 0); // [time: 670.002ns -> 680.002ns] - write(15, 67108869, 2880683308, 0); // [time: 680.002ns -> 690.002ns] - write(15, 67108870, 1446265757, 0); // [time: 690.002ns -> 700.002ns] - read(15, 67108867, 1483205141, 0); // [time: 700.002ns -> 720.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_4_0.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_4_0.monitor.expect deleted file mode 100644 index 28cf4257..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_4_0.monitor.expect +++ /dev/null @@ -1,25 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108865, 1833423740, 0); // [time: 170ns -> 190ns] - read(15, 67108866, 4073618608, 0); // [time: 190ns -> 200ns] - read(15, 67108867, 3418745219, 0); // [time: 200ns -> 210ns] - read(15, 67108868, 3757272308, 0); // [time: 210ns -> 220ns] - reset(); // [time: 260.001ns -> 270.001ns] - reset(); // [time: 270.001ns -> 280.001ns] - reset(); // [time: 280.001ns -> 290.001ns] - write(15, 67108865, 1325530178, 0); // [time: 330.001ns -> 350.001ns] - write(15, 67108866, 1451722922, 0); // [time: 350.001ns -> 360.001ns] - write(15, 67108867, 1997677454, 0); // [time: 360.001ns -> 370.001ns] - write(15, 67108868, 986005841, 0); // [time: 370.001ns -> 380.001ns] - reset(); // [time: 580.002ns -> 590.002ns] - reset(); // [time: 590.002ns -> 600.002ns] - reset(); // [time: 600.002ns -> 610.002ns] - write(15, 67108865, 789975088, 0); // [time: 650.002ns -> 670.002ns] - write(15, 67108866, 3746918692, 0); // [time: 670.002ns -> 680.002ns] - write(15, 67108867, 410224063, 0); // [time: 680.002ns -> 690.002ns] - write(15, 67108868, 864118294, 0); // [time: 690.002ns -> 700.002ns] - read(15, 67108865, 789975088, 0); // [time: 700.002ns -> 720.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_4_1.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_4_1.monitor.expect deleted file mode 100644 index 50109ac8..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_4_1.monitor.expect +++ /dev/null @@ -1,25 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108865, 518534189, 0); // [time: 170ns -> 190ns] - read(15, 67108866, 844695266, 0); // [time: 190ns -> 200ns] - read(15, 67108867, 3937184150, 0); // [time: 200ns -> 210ns] - read(15, 67108864, 444246851, 0); // [time: 210ns -> 220ns] - reset(); // [time: 260.001ns -> 270.001ns] - reset(); // [time: 270.001ns -> 280.001ns] - reset(); // [time: 280.001ns -> 290.001ns] - write(15, 67108865, 3220682802, 0); // [time: 330.001ns -> 350.001ns] - write(15, 67108866, 2130811954, 0); // [time: 350.001ns -> 360.001ns] - write(15, 67108867, 2002127438, 0); // [time: 360.001ns -> 370.001ns] - write(15, 67108864, 493792053, 0); // [time: 370.001ns -> 380.001ns] - reset(); // [time: 580.002ns -> 590.002ns] - reset(); // [time: 590.002ns -> 600.002ns] - reset(); // [time: 600.002ns -> 610.002ns] - write(15, 67108865, 63714206, 0); // [time: 650.002ns -> 670.002ns] - write(15, 67108866, 2091823691, 0); // [time: 670.002ns -> 680.002ns] - write(15, 67108867, 3903276977, 0); // [time: 680.002ns -> 690.002ns] - write(15, 67108864, 1662756337, 0); // [time: 690.002ns -> 700.002ns] - read(15, 67108865, 63714206, 0); // [time: 700.002ns -> 720.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_4_2.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_4_2.monitor.expect deleted file mode 100644 index 110541f7..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_4_2.monitor.expect +++ /dev/null @@ -1,25 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108865, 869832817, 0); // [time: 170ns -> 190ns] - read(15, 67108866, 2976082601, 0); // [time: 190ns -> 200ns] - read(15, 67108867, 373695501, 0); // [time: 200ns -> 210ns] - read(15, 67108868, 2110838384, 0); // [time: 210ns -> 220ns] - reset(); // [time: 260.001ns -> 270.001ns] - reset(); // [time: 270.001ns -> 280.001ns] - reset(); // [time: 280.001ns -> 290.001ns] - write(15, 67108865, 3556455435, 0); // [time: 330.001ns -> 350.001ns] - write(15, 67108866, 1804567173, 0); // [time: 350.001ns -> 360.001ns] - write(15, 67108867, 1187331577, 0); // [time: 360.001ns -> 370.001ns] - write(15, 67108868, 1293993917, 0); // [time: 370.001ns -> 380.001ns] - reset(); // [time: 580.002ns -> 590.002ns] - reset(); // [time: 590.002ns -> 600.002ns] - reset(); // [time: 600.002ns -> 610.002ns] - write(15, 67108865, 753581369, 0); // [time: 650.002ns -> 670.002ns] - write(15, 67108866, 2300246917, 0); // [time: 670.002ns -> 680.002ns] - write(15, 67108867, 3523846629, 0); // [time: 680.002ns -> 690.002ns] - write(15, 67108868, 3751494934, 0); // [time: 690.002ns -> 700.002ns] - read(15, 67108865, 753581369, 0); // [time: 700.002ns -> 720.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_4_3.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_4_3.monitor.expect deleted file mode 100644 index c525398d..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_4_3.monitor.expect +++ /dev/null @@ -1,25 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108865, 1509562552, 0); // [time: 170ns -> 190ns] - read(15, 67108866, 2329347035, 0); // [time: 190ns -> 200ns] - read(15, 67108867, 3862381389, 0); // [time: 200ns -> 210ns] - read(15, 67108868, 1142123500, 0); // [time: 210ns -> 220ns] - reset(); // [time: 260.001ns -> 270.001ns] - reset(); // [time: 270.001ns -> 280.001ns] - reset(); // [time: 280.001ns -> 290.001ns] - write(15, 67108865, 3598508010, 0); // [time: 330.001ns -> 350.001ns] - write(15, 67108866, 908644471, 0); // [time: 350.001ns -> 360.001ns] - write(15, 67108867, 870782326, 0); // [time: 360.001ns -> 370.001ns] - write(15, 67108868, 1788061457, 0); // [time: 370.001ns -> 380.001ns] - reset(); // [time: 580.002ns -> 590.002ns] - reset(); // [time: 590.002ns -> 600.002ns] - reset(); // [time: 600.002ns -> 610.002ns] - write(15, 67108865, 1483205141, 0); // [time: 650.002ns -> 670.002ns] - write(15, 67108866, 408872453, 0); // [time: 670.002ns -> 680.002ns] - write(15, 67108867, 2880683308, 0); // [time: 680.002ns -> 690.002ns] - write(15, 67108868, 1446265757, 0); // [time: 690.002ns -> 700.002ns] - read(15, 67108865, 1483205141, 0); // [time: 700.002ns -> 720.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_8_0.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_8_0.monitor.expect deleted file mode 100644 index 6d06914b..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_8_0.monitor.expect +++ /dev/null @@ -1,25 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108866, 1833423740, 0); // [time: 170ns -> 190ns] - read(15, 67108867, 4073618608, 0); // [time: 190ns -> 200ns] - read(15, 67108868, 3418745219, 0); // [time: 200ns -> 210ns] - read(15, 67108869, 3757272308, 0); // [time: 210ns -> 220ns] - reset(); // [time: 260.001ns -> 270.001ns] - reset(); // [time: 270.001ns -> 280.001ns] - reset(); // [time: 280.001ns -> 290.001ns] - write(15, 67108866, 1325530178, 0); // [time: 330.001ns -> 350.001ns] - write(15, 67108867, 1451722922, 0); // [time: 350.001ns -> 360.001ns] - write(15, 67108868, 1997677454, 0); // [time: 360.001ns -> 370.001ns] - write(15, 67108869, 986005841, 0); // [time: 370.001ns -> 380.001ns] - reset(); // [time: 580.002ns -> 590.002ns] - reset(); // [time: 590.002ns -> 600.002ns] - reset(); // [time: 600.002ns -> 610.002ns] - write(15, 67108866, 789975088, 0); // [time: 650.002ns -> 670.002ns] - write(15, 67108867, 3746918692, 0); // [time: 670.002ns -> 680.002ns] - write(15, 67108868, 410224063, 0); // [time: 680.002ns -> 690.002ns] - write(15, 67108869, 864118294, 0); // [time: 690.002ns -> 700.002ns] - read(15, 67108866, 789975088, 0); // [time: 700.002ns -> 720.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_8_1.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_8_1.monitor.expect deleted file mode 100644 index e58197ce..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_8_1.monitor.expect +++ /dev/null @@ -1,25 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108866, 518534189, 0); // [time: 170ns -> 190ns] - read(15, 67108867, 844695266, 0); // [time: 190ns -> 200ns] - read(15, 67108864, 3937184150, 0); // [time: 200ns -> 210ns] - read(15, 67108865, 444246851, 0); // [time: 210ns -> 220ns] - reset(); // [time: 260.001ns -> 270.001ns] - reset(); // [time: 270.001ns -> 280.001ns] - reset(); // [time: 280.001ns -> 290.001ns] - write(15, 67108866, 3220682802, 0); // [time: 330.001ns -> 350.001ns] - write(15, 67108867, 2130811954, 0); // [time: 350.001ns -> 360.001ns] - write(15, 67108864, 2002127438, 0); // [time: 360.001ns -> 370.001ns] - write(15, 67108865, 493792053, 0); // [time: 370.001ns -> 380.001ns] - reset(); // [time: 580.002ns -> 590.002ns] - reset(); // [time: 590.002ns -> 600.002ns] - reset(); // [time: 600.002ns -> 610.002ns] - write(15, 67108866, 63714206, 0); // [time: 650.002ns -> 670.002ns] - write(15, 67108867, 2091823691, 0); // [time: 670.002ns -> 680.002ns] - write(15, 67108864, 3903276977, 0); // [time: 680.002ns -> 690.002ns] - write(15, 67108865, 1662756337, 0); // [time: 690.002ns -> 700.002ns] - read(15, 67108866, 63714206, 0); // [time: 700.002ns -> 720.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_8_2.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_8_2.monitor.expect deleted file mode 100644 index 9c8093c8..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_8_2.monitor.expect +++ /dev/null @@ -1,25 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108866, 1016512136, 0); // [time: 170ns -> 190ns] - read(15, 67108867, 226204128, 0); // [time: 190ns -> 200ns] - read(15, 67108868, 2116565440, 0); // [time: 200ns -> 210ns] - read(15, 67108869, 2153688786, 0); // [time: 210ns -> 220ns] - reset(); // [time: 260.001ns -> 270.001ns] - reset(); // [time: 270.001ns -> 280.001ns] - reset(); // [time: 280.001ns -> 290.001ns] - write(15, 67108866, 1974223269, 0); // [time: 330.001ns -> 350.001ns] - write(15, 67108867, 1053640572, 0); // [time: 350.001ns -> 360.001ns] - write(15, 67108868, 2079860600, 0); // [time: 360.001ns -> 370.001ns] - write(15, 67108869, 3550045624, 0); // [time: 370.001ns -> 380.001ns] - reset(); // [time: 580.002ns -> 590.002ns] - reset(); // [time: 590.002ns -> 600.002ns] - reset(); // [time: 600.002ns -> 610.002ns] - write(15, 67108866, 1038322047, 0); // [time: 650.002ns -> 670.002ns] - write(15, 67108867, 1502718053, 0); // [time: 670.002ns -> 680.002ns] - write(15, 67108868, 1367070343, 0); // [time: 680.002ns -> 690.002ns] - write(15, 67108869, 3425882885, 0); // [time: 690.002ns -> 700.002ns] - read(15, 67108866, 1038322047, 0); // [time: 700.002ns -> 720.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_8_3.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_8_3.monitor.expect deleted file mode 100644 index cc76cf64..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_8_3.monitor.expect +++ /dev/null @@ -1,25 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108866, 1070372987, 0); // [time: 170ns -> 190ns] - read(15, 67108867, 2645947069, 0); // [time: 190ns -> 200ns] - read(15, 67108868, 736643984, 0); // [time: 200ns -> 210ns] - read(15, 67108869, 192007203, 0); // [time: 210ns -> 220ns] - reset(); // [time: 260.001ns -> 270.001ns] - reset(); // [time: 270.001ns -> 280.001ns] - reset(); // [time: 280.001ns -> 290.001ns] - write(15, 67108866, 1925400290, 0); // [time: 330.001ns -> 350.001ns] - write(15, 67108867, 1309609983, 0); // [time: 350.001ns -> 360.001ns] - write(15, 67108868, 58503546, 0); // [time: 360.001ns -> 370.001ns] - write(15, 67108869, 3861022989, 0); // [time: 370.001ns -> 380.001ns] - reset(); // [time: 580.002ns -> 590.002ns] - reset(); // [time: 590.002ns -> 600.002ns] - reset(); // [time: 600.002ns -> 610.002ns] - write(15, 67108866, 1725708128, 0); // [time: 650.002ns -> 670.002ns] - write(15, 67108867, 3760744365, 0); // [time: 670.002ns -> 680.002ns] - write(15, 67108868, 3803789590, 0); // [time: 680.002ns -> 690.002ns] - write(15, 67108869, 2647121574, 0); // [time: 690.002ns -> 700.002ns] - read(15, 67108866, 1725708128, 0); // [time: 700.002ns -> 720.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_0_0.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_0_0.monitor.expect deleted file mode 100644 index 66d2bc8e..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_0_0.monitor.expect +++ /dev/null @@ -1,37 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108864, 518534189, 0); // [time: 250ns -> 270ns] - read(15, 67108865, 844695266, 0); // [time: 270ns -> 280ns] - read(15, 67108866, 3937184150, 0); // [time: 280ns -> 290ns] - read(15, 67108867, 444246851, 0); // [time: 290ns -> 300ns] - read(15, 67108868, 3220682802, 0); // [time: 300ns -> 310ns] - read(15, 67108869, 2130811954, 0); // [time: 310ns -> 320ns] - read(15, 67108870, 2002127438, 0); // [time: 320ns -> 330ns] - read(15, 67108871, 493792053, 0); // [time: 330ns -> 340ns] - reset(); // [time: 380.001ns -> 390.001ns] - reset(); // [time: 390.001ns -> 400.001ns] - reset(); // [time: 400.001ns -> 410.001ns] - write(15, 67108864, 63714206, 0); // [time: 450.001ns -> 470.001ns] - write(15, 67108865, 2091823691, 0); // [time: 470.001ns -> 480.001ns] - write(15, 67108866, 3903276977, 0); // [time: 480.001ns -> 490.001ns] - write(15, 67108867, 1662756337, 0); // [time: 490.001ns -> 500.001ns] - write(15, 67108868, 4101310419, 0); // [time: 500.001ns -> 510.001ns] - write(15, 67108869, 903798156, 0); // [time: 510.001ns -> 520.001ns] - write(15, 67108870, 3840476340, 0); // [time: 520.001ns -> 530.001ns] - write(15, 67108871, 2244097975, 0); // [time: 530.001ns -> 540.001ns] - reset(); // [time: 900.002ns -> 910.002ns] - reset(); // [time: 910.002ns -> 920.002ns] - reset(); // [time: 920.002ns -> 930.002ns] - write(15, 67108864, 3956643922, 0); // [time: 970.002ns -> 990.002ns] - write(15, 67108865, 2115347845, 0); // [time: 990.002ns -> 1000.002ns] - write(15, 67108866, 1775201107, 0); // [time: 1000.002ns -> 1010.002ns] - write(15, 67108867, 1046910518, 0); // [time: 1010.002ns -> 1020.002ns] - write(15, 67108868, 345998276, 0); // [time: 1020.002ns -> 1030.002ns] - write(15, 67108869, 2089777588, 0); // [time: 1030.002ns -> 1040.002ns] - write(15, 67108870, 3110941387, 0); // [time: 1040.002ns -> 1050.002ns] - write(15, 67108871, 3151493219, 0); // [time: 1050.002ns -> 1060.002ns] - read(15, 67108864, 3956643922, 0); // [time: 1060.002ns -> 1080.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_0_1.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_0_1.monitor.expect deleted file mode 100644 index bc132178..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_0_1.monitor.expect +++ /dev/null @@ -1,37 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108864, 2821946881, 0); // [time: 250ns -> 270ns] - read(15, 67108865, 4080087070, 0); // [time: 270ns -> 280ns] - read(15, 67108866, 2243193877, 0); // [time: 280ns -> 290ns] - read(15, 67108867, 2472849580, 0); // [time: 290ns -> 300ns] - read(15, 67108868, 3565370026, 0); // [time: 300ns -> 310ns] - read(15, 67108869, 890985600, 0); // [time: 310ns -> 320ns] - read(15, 67108870, 4179549189, 0); // [time: 320ns -> 330ns] - read(15, 67108871, 4158632492, 0); // [time: 330ns -> 340ns] - reset(); // [time: 380.001ns -> 390.001ns] - reset(); // [time: 390.001ns -> 400.001ns] - reset(); // [time: 400.001ns -> 410.001ns] - write(15, 67108864, 3744957516, 0); // [time: 450.001ns -> 470.001ns] - write(15, 67108865, 2300150418, 0); // [time: 470.001ns -> 480.001ns] - write(15, 67108866, 2081940992, 0); // [time: 480.001ns -> 490.001ns] - write(15, 67108867, 1697819148, 0); // [time: 490.001ns -> 500.001ns] - write(15, 67108868, 602241333, 0); // [time: 500.001ns -> 510.001ns] - write(15, 67108869, 2260552922, 0); // [time: 510.001ns -> 520.001ns] - write(15, 67108870, 4251564751, 0); // [time: 520.001ns -> 530.001ns] - write(15, 67108871, 3326548024, 0); // [time: 530.001ns -> 540.001ns] - reset(); // [time: 900.002ns -> 910.002ns] - reset(); // [time: 910.002ns -> 920.002ns] - reset(); // [time: 920.002ns -> 930.002ns] - write(15, 67108864, 1044044861, 0); // [time: 970.002ns -> 990.002ns] - write(15, 67108865, 4177314760, 0); // [time: 990.002ns -> 1000.002ns] - write(15, 67108866, 4253662683, 0); // [time: 1000.002ns -> 1010.002ns] - write(15, 67108867, 3575602093, 0); // [time: 1010.002ns -> 1020.002ns] - write(15, 67108868, 667576938, 0); // [time: 1020.002ns -> 1030.002ns] - write(15, 67108869, 3110079964, 0); // [time: 1030.002ns -> 1040.002ns] - write(15, 67108870, 3758039968, 0); // [time: 1040.002ns -> 1050.002ns] - write(15, 67108871, 3566852678, 0); // [time: 1050.002ns -> 1060.002ns] - read(15, 67108864, 1044044861, 0); // [time: 1060.002ns -> 1080.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_0_2.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_0_2.monitor.expect deleted file mode 100644 index 37006294..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_0_2.monitor.expect +++ /dev/null @@ -1,37 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108864, 869832817, 0); // [time: 250ns -> 270ns] - read(15, 67108865, 2976082601, 0); // [time: 270ns -> 280ns] - read(15, 67108866, 373695501, 0); // [time: 280ns -> 290ns] - read(15, 67108867, 2110838384, 0); // [time: 290ns -> 300ns] - read(15, 67108868, 3556455435, 0); // [time: 300ns -> 310ns] - read(15, 67108869, 1804567173, 0); // [time: 310ns -> 320ns] - read(15, 67108870, 1187331577, 0); // [time: 320ns -> 330ns] - read(15, 67108871, 1293993917, 0); // [time: 330ns -> 340ns] - reset(); // [time: 380.001ns -> 390.001ns] - reset(); // [time: 390.001ns -> 400.001ns] - reset(); // [time: 400.001ns -> 410.001ns] - write(15, 67108864, 753581369, 0); // [time: 450.001ns -> 470.001ns] - write(15, 67108865, 2300246917, 0); // [time: 470.001ns -> 480.001ns] - write(15, 67108866, 3523846629, 0); // [time: 480.001ns -> 490.001ns] - write(15, 67108867, 3751494934, 0); // [time: 490.001ns -> 500.001ns] - write(15, 67108868, 504397671, 0); // [time: 500.001ns -> 510.001ns] - write(15, 67108869, 3203321461, 0); // [time: 510.001ns -> 520.001ns] - write(15, 67108870, 3801714021, 0); // [time: 520.001ns -> 530.001ns] - write(15, 67108871, 654543662, 0); // [time: 530.001ns -> 540.001ns] - reset(); // [time: 900.002ns -> 910.002ns] - reset(); // [time: 910.002ns -> 920.002ns] - reset(); // [time: 920.002ns -> 930.002ns] - write(15, 67108864, 1829143953, 0); // [time: 970.002ns -> 990.002ns] - write(15, 67108865, 2746894674, 0); // [time: 990.002ns -> 1000.002ns] - write(15, 67108866, 3464933947, 0); // [time: 1000.002ns -> 1010.002ns] - write(15, 67108867, 3350075041, 0); // [time: 1010.002ns -> 1020.002ns] - write(15, 67108868, 1123364414, 0); // [time: 1020.002ns -> 1030.002ns] - write(15, 67108869, 3896266205, 0); // [time: 1030.002ns -> 1040.002ns] - write(15, 67108870, 3668919860, 0); // [time: 1040.002ns -> 1050.002ns] - write(15, 67108871, 177490457, 0); // [time: 1050.002ns -> 1060.002ns] - read(15, 67108864, 1829143953, 0); // [time: 1060.002ns -> 1080.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_0_3.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_0_3.monitor.expect deleted file mode 100644 index 60d1cc31..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_0_3.monitor.expect +++ /dev/null @@ -1,37 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108864, 1070372987, 0); // [time: 250ns -> 270ns] - read(15, 67108865, 2645947069, 0); // [time: 270ns -> 280ns] - read(15, 67108866, 736643984, 0); // [time: 280ns -> 290ns] - read(15, 67108867, 192007203, 0); // [time: 290ns -> 300ns] - read(15, 67108868, 1925400290, 0); // [time: 300ns -> 310ns] - read(15, 67108869, 1309609983, 0); // [time: 310ns -> 320ns] - read(15, 67108870, 58503546, 0); // [time: 320ns -> 330ns] - read(15, 67108871, 3861022989, 0); // [time: 330ns -> 340ns] - reset(); // [time: 380.001ns -> 390.001ns] - reset(); // [time: 390.001ns -> 400.001ns] - reset(); // [time: 400.001ns -> 410.001ns] - write(15, 67108864, 1725708128, 0); // [time: 450.001ns -> 470.001ns] - write(15, 67108865, 3760744365, 0); // [time: 470.001ns -> 480.001ns] - write(15, 67108866, 3803789590, 0); // [time: 480.001ns -> 490.001ns] - write(15, 67108867, 2647121574, 0); // [time: 490.001ns -> 500.001ns] - write(15, 67108868, 336117328, 0); // [time: 500.001ns -> 510.001ns] - write(15, 67108869, 3984726565, 0); // [time: 510.001ns -> 520.001ns] - write(15, 67108870, 104808193, 0); // [time: 520.001ns -> 530.001ns] - write(15, 67108871, 2315494688, 0); // [time: 530.001ns -> 540.001ns] - reset(); // [time: 900.002ns -> 910.002ns] - reset(); // [time: 910.002ns -> 920.002ns] - reset(); // [time: 920.002ns -> 930.002ns] - write(15, 67108864, 3997204021, 0); // [time: 970.002ns -> 990.002ns] - write(15, 67108865, 666660673, 0); // [time: 990.002ns -> 1000.002ns] - write(15, 67108866, 3910223084, 0); // [time: 1000.002ns -> 1010.002ns] - write(15, 67108867, 1271405124, 0); // [time: 1010.002ns -> 1020.002ns] - write(15, 67108868, 4236388983, 0); // [time: 1020.002ns -> 1030.002ns] - write(15, 67108869, 1347016890, 0); // [time: 1030.002ns -> 1040.002ns] - write(15, 67108870, 1337396640, 0); // [time: 1040.002ns -> 1050.002ns] - write(15, 67108871, 3009712000, 0); // [time: 1050.002ns -> 1060.002ns] - read(15, 67108864, 3997204021, 0); // [time: 1060.002ns -> 1080.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_12_0.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_12_0.monitor.expect deleted file mode 100644 index d17bbe8a..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_12_0.monitor.expect +++ /dev/null @@ -1,37 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108867, 3580256271, 0); // [time: 250ns -> 270ns] - read(15, 67108868, 1489666683, 0); // [time: 270ns -> 280ns] - read(15, 67108869, 3677074643, 0); // [time: 280ns -> 290ns] - read(15, 67108870, 1878953054, 0); // [time: 290ns -> 300ns] - read(15, 67108871, 2965505115, 0); // [time: 300ns -> 310ns] - read(15, 67108872, 3259566096, 0); // [time: 310ns -> 320ns] - read(15, 67108873, 1262153110, 0); // [time: 320ns -> 330ns] - read(15, 67108874, 2451703670, 0); // [time: 330ns -> 340ns] - reset(); // [time: 380.001ns -> 390.001ns] - reset(); // [time: 390.001ns -> 400.001ns] - reset(); // [time: 400.001ns -> 410.001ns] - write(15, 67108867, 3104341711, 0); // [time: 450.001ns -> 470.001ns] - write(15, 67108868, 964066815, 0); // [time: 470.001ns -> 480.001ns] - write(15, 67108869, 3328791441, 0); // [time: 480.001ns -> 490.001ns] - write(15, 67108870, 3489570824, 0); // [time: 490.001ns -> 500.001ns] - write(15, 67108871, 4241788620, 0); // [time: 500.001ns -> 510.001ns] - write(15, 67108872, 3583058104, 0); // [time: 510.001ns -> 520.001ns] - write(15, 67108873, 1005667378, 0); // [time: 520.001ns -> 530.001ns] - write(15, 67108874, 209419171, 0); // [time: 530.001ns -> 540.001ns] - reset(); // [time: 900.002ns -> 910.002ns] - reset(); // [time: 910.002ns -> 920.002ns] - reset(); // [time: 920.002ns -> 930.002ns] - write(15, 67108867, 1000382631, 0); // [time: 970.002ns -> 990.002ns] - write(15, 67108868, 1285425234, 0); // [time: 990.002ns -> 1000.002ns] - write(15, 67108869, 318606993, 0); // [time: 1000.002ns -> 1010.002ns] - write(15, 67108870, 2625467664, 0); // [time: 1010.002ns -> 1020.002ns] - write(15, 67108871, 229964357, 0); // [time: 1020.002ns -> 1030.002ns] - write(15, 67108872, 3036014706, 0); // [time: 1030.002ns -> 1040.002ns] - write(15, 67108873, 1528299378, 0); // [time: 1040.002ns -> 1050.002ns] - write(15, 67108874, 2182965409, 0); // [time: 1050.002ns -> 1060.002ns] - read(15, 67108867, 1000382631, 0); // [time: 1060.002ns -> 1080.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_12_1.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_12_1.monitor.expect deleted file mode 100644 index f8f3065d..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_12_1.monitor.expect +++ /dev/null @@ -1,37 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108867, 518534189, 0); // [time: 250ns -> 270ns] - read(15, 67108864, 844695266, 0); // [time: 270ns -> 280ns] - read(15, 67108865, 3937184150, 0); // [time: 280ns -> 290ns] - read(15, 67108866, 444246851, 0); // [time: 290ns -> 300ns] - read(15, 67108871, 3220682802, 0); // [time: 300ns -> 310ns] - read(15, 67108868, 2130811954, 0); // [time: 310ns -> 320ns] - read(15, 67108869, 2002127438, 0); // [time: 320ns -> 330ns] - read(15, 67108870, 493792053, 0); // [time: 330ns -> 340ns] - reset(); // [time: 380.001ns -> 390.001ns] - reset(); // [time: 390.001ns -> 400.001ns] - reset(); // [time: 400.001ns -> 410.001ns] - write(15, 67108867, 63714206, 0); // [time: 450.001ns -> 470.001ns] - write(15, 67108864, 2091823691, 0); // [time: 470.001ns -> 480.001ns] - write(15, 67108865, 3903276977, 0); // [time: 480.001ns -> 490.001ns] - write(15, 67108866, 1662756337, 0); // [time: 490.001ns -> 500.001ns] - write(15, 67108871, 4101310419, 0); // [time: 500.001ns -> 510.001ns] - write(15, 67108868, 903798156, 0); // [time: 510.001ns -> 520.001ns] - write(15, 67108869, 3840476340, 0); // [time: 520.001ns -> 530.001ns] - write(15, 67108870, 2244097975, 0); // [time: 530.001ns -> 540.001ns] - reset(); // [time: 900.002ns -> 910.002ns] - reset(); // [time: 910.002ns -> 920.002ns] - reset(); // [time: 920.002ns -> 930.002ns] - write(15, 67108867, 3956643922, 0); // [time: 970.002ns -> 990.002ns] - write(15, 67108864, 2115347845, 0); // [time: 990.002ns -> 1000.002ns] - write(15, 67108865, 1775201107, 0); // [time: 1000.002ns -> 1010.002ns] - write(15, 67108866, 1046910518, 0); // [time: 1010.002ns -> 1020.002ns] - write(15, 67108871, 345998276, 0); // [time: 1020.002ns -> 1030.002ns] - write(15, 67108868, 2089777588, 0); // [time: 1030.002ns -> 1040.002ns] - write(15, 67108869, 3110941387, 0); // [time: 1040.002ns -> 1050.002ns] - write(15, 67108870, 3151493219, 0); // [time: 1050.002ns -> 1060.002ns] - read(15, 67108867, 3956643922, 0); // [time: 1060.002ns -> 1080.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_12_2.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_12_2.monitor.expect deleted file mode 100644 index 441adf6a..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_12_2.monitor.expect +++ /dev/null @@ -1,37 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108867, 869832817, 0); // [time: 250ns -> 270ns] - read(15, 67108868, 2976082601, 0); // [time: 270ns -> 280ns] - read(15, 67108869, 373695501, 0); // [time: 280ns -> 290ns] - read(15, 67108870, 2110838384, 0); // [time: 290ns -> 300ns] - read(15, 67108871, 3556455435, 0); // [time: 300ns -> 310ns] - read(15, 67108864, 1804567173, 0); // [time: 310ns -> 320ns] - read(15, 67108865, 1187331577, 0); // [time: 320ns -> 330ns] - read(15, 67108866, 1293993917, 0); // [time: 330ns -> 340ns] - reset(); // [time: 380.001ns -> 390.001ns] - reset(); // [time: 390.001ns -> 400.001ns] - reset(); // [time: 400.001ns -> 410.001ns] - write(15, 67108867, 753581369, 0); // [time: 450.001ns -> 470.001ns] - write(15, 67108868, 2300246917, 0); // [time: 470.001ns -> 480.001ns] - write(15, 67108869, 3523846629, 0); // [time: 480.001ns -> 490.001ns] - write(15, 67108870, 3751494934, 0); // [time: 490.001ns -> 500.001ns] - write(15, 67108871, 504397671, 0); // [time: 500.001ns -> 510.001ns] - write(15, 67108864, 3203321461, 0); // [time: 510.001ns -> 520.001ns] - write(15, 67108865, 3801714021, 0); // [time: 520.001ns -> 530.001ns] - write(15, 67108866, 654543662, 0); // [time: 530.001ns -> 540.001ns] - reset(); // [time: 900.002ns -> 910.002ns] - reset(); // [time: 910.002ns -> 920.002ns] - reset(); // [time: 920.002ns -> 930.002ns] - write(15, 67108867, 1829143953, 0); // [time: 970.002ns -> 990.002ns] - write(15, 67108868, 2746894674, 0); // [time: 990.002ns -> 1000.002ns] - write(15, 67108869, 3464933947, 0); // [time: 1000.002ns -> 1010.002ns] - write(15, 67108870, 3350075041, 0); // [time: 1010.002ns -> 1020.002ns] - write(15, 67108871, 1123364414, 0); // [time: 1020.002ns -> 1030.002ns] - write(15, 67108864, 3896266205, 0); // [time: 1030.002ns -> 1040.002ns] - write(15, 67108865, 3668919860, 0); // [time: 1040.002ns -> 1050.002ns] - write(15, 67108866, 177490457, 0); // [time: 1050.002ns -> 1060.002ns] - read(15, 67108867, 1829143953, 0); // [time: 1060.002ns -> 1080.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_12_3.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_12_3.monitor.expect deleted file mode 100644 index 1b811196..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_12_3.monitor.expect +++ /dev/null @@ -1,37 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108867, 1070372987, 0); // [time: 250ns -> 270ns] - read(15, 67108868, 2645947069, 0); // [time: 270ns -> 280ns] - read(15, 67108869, 736643984, 0); // [time: 280ns -> 290ns] - read(15, 67108870, 192007203, 0); // [time: 290ns -> 300ns] - read(15, 67108871, 1925400290, 0); // [time: 300ns -> 310ns] - read(15, 67108872, 1309609983, 0); // [time: 310ns -> 320ns] - read(15, 67108873, 58503546, 0); // [time: 320ns -> 330ns] - read(15, 67108874, 3861022989, 0); // [time: 330ns -> 340ns] - reset(); // [time: 380.001ns -> 390.001ns] - reset(); // [time: 390.001ns -> 400.001ns] - reset(); // [time: 400.001ns -> 410.001ns] - write(15, 67108867, 1725708128, 0); // [time: 450.001ns -> 470.001ns] - write(15, 67108868, 3760744365, 0); // [time: 470.001ns -> 480.001ns] - write(15, 67108869, 3803789590, 0); // [time: 480.001ns -> 490.001ns] - write(15, 67108870, 2647121574, 0); // [time: 490.001ns -> 500.001ns] - write(15, 67108871, 336117328, 0); // [time: 500.001ns -> 510.001ns] - write(15, 67108872, 3984726565, 0); // [time: 510.001ns -> 520.001ns] - write(15, 67108873, 104808193, 0); // [time: 520.001ns -> 530.001ns] - write(15, 67108874, 2315494688, 0); // [time: 530.001ns -> 540.001ns] - reset(); // [time: 900.002ns -> 910.002ns] - reset(); // [time: 910.002ns -> 920.002ns] - reset(); // [time: 920.002ns -> 930.002ns] - write(15, 67108867, 3997204021, 0); // [time: 970.002ns -> 990.002ns] - write(15, 67108868, 666660673, 0); // [time: 990.002ns -> 1000.002ns] - write(15, 67108869, 3910223084, 0); // [time: 1000.002ns -> 1010.002ns] - write(15, 67108870, 1271405124, 0); // [time: 1010.002ns -> 1020.002ns] - write(15, 67108871, 4236388983, 0); // [time: 1020.002ns -> 1030.002ns] - write(15, 67108872, 1347016890, 0); // [time: 1030.002ns -> 1040.002ns] - write(15, 67108873, 1337396640, 0); // [time: 1040.002ns -> 1050.002ns] - write(15, 67108874, 3009712000, 0); // [time: 1050.002ns -> 1060.002ns] - read(15, 67108867, 3997204021, 0); // [time: 1060.002ns -> 1080.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_4_0.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_4_0.monitor.expect deleted file mode 100644 index c48eeb96..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_4_0.monitor.expect +++ /dev/null @@ -1,37 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108865, 2821946881, 0); // [time: 250ns -> 270ns] - read(15, 67108866, 4080087070, 0); // [time: 270ns -> 280ns] - read(15, 67108867, 2243193877, 0); // [time: 280ns -> 290ns] - read(15, 67108868, 2472849580, 0); // [time: 290ns -> 300ns] - read(15, 67108869, 3565370026, 0); // [time: 300ns -> 310ns] - read(15, 67108870, 890985600, 0); // [time: 310ns -> 320ns] - read(15, 67108871, 4179549189, 0); // [time: 320ns -> 330ns] - read(15, 67108872, 4158632492, 0); // [time: 330ns -> 340ns] - reset(); // [time: 380.001ns -> 390.001ns] - reset(); // [time: 390.001ns -> 400.001ns] - reset(); // [time: 400.001ns -> 410.001ns] - write(15, 67108865, 3744957516, 0); // [time: 450.001ns -> 470.001ns] - write(15, 67108866, 2300150418, 0); // [time: 470.001ns -> 480.001ns] - write(15, 67108867, 2081940992, 0); // [time: 480.001ns -> 490.001ns] - write(15, 67108868, 1697819148, 0); // [time: 490.001ns -> 500.001ns] - write(15, 67108869, 602241333, 0); // [time: 500.001ns -> 510.001ns] - write(15, 67108870, 2260552922, 0); // [time: 510.001ns -> 520.001ns] - write(15, 67108871, 4251564751, 0); // [time: 520.001ns -> 530.001ns] - write(15, 67108872, 3326548024, 0); // [time: 530.001ns -> 540.001ns] - reset(); // [time: 900.002ns -> 910.002ns] - reset(); // [time: 910.002ns -> 920.002ns] - reset(); // [time: 920.002ns -> 930.002ns] - write(15, 67108865, 1044044861, 0); // [time: 970.002ns -> 990.002ns] - write(15, 67108866, 4177314760, 0); // [time: 990.002ns -> 1000.002ns] - write(15, 67108867, 4253662683, 0); // [time: 1000.002ns -> 1010.002ns] - write(15, 67108868, 3575602093, 0); // [time: 1010.002ns -> 1020.002ns] - write(15, 67108869, 667576938, 0); // [time: 1020.002ns -> 1030.002ns] - write(15, 67108870, 3110079964, 0); // [time: 1030.002ns -> 1040.002ns] - write(15, 67108871, 3758039968, 0); // [time: 1040.002ns -> 1050.002ns] - write(15, 67108872, 3566852678, 0); // [time: 1050.002ns -> 1060.002ns] - read(15, 67108865, 1044044861, 0); // [time: 1060.002ns -> 1080.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_4_1.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_4_1.monitor.expect deleted file mode 100644 index 1bea919b..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_4_1.monitor.expect +++ /dev/null @@ -1,37 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108865, 2205995893, 0); // [time: 250ns -> 270ns] - read(15, 67108866, 486560095, 0); // [time: 270ns -> 280ns] - read(15, 67108867, 4100133660, 0); // [time: 280ns -> 290ns] - read(15, 67108864, 596618694, 0); // [time: 290ns -> 300ns] - read(15, 67108869, 3499942130, 0); // [time: 300ns -> 310ns] - read(15, 67108870, 2357711907, 0); // [time: 310ns -> 320ns] - read(15, 67108871, 2086526797, 0); // [time: 320ns -> 330ns] - read(15, 67108868, 364077448, 0); // [time: 330ns -> 340ns] - reset(); // [time: 380.001ns -> 390.001ns] - reset(); // [time: 390.001ns -> 400.001ns] - reset(); // [time: 400.001ns -> 410.001ns] - write(15, 67108865, 210674739, 0); // [time: 450.001ns -> 470.001ns] - write(15, 67108866, 1567286535, 0); // [time: 470.001ns -> 480.001ns] - write(15, 67108867, 922799025, 0); // [time: 480.001ns -> 490.001ns] - write(15, 67108864, 4171757579, 0); // [time: 490.001ns -> 500.001ns] - write(15, 67108869, 740193371, 0); // [time: 500.001ns -> 510.001ns] - write(15, 67108870, 872570658, 0); // [time: 510.001ns -> 520.001ns] - write(15, 67108871, 608559447, 0); // [time: 520.001ns -> 530.001ns] - write(15, 67108868, 1049762371, 0); // [time: 530.001ns -> 540.001ns] - reset(); // [time: 900.002ns -> 910.002ns] - reset(); // [time: 910.002ns -> 920.002ns] - reset(); // [time: 920.002ns -> 930.002ns] - write(15, 67108865, 61321282, 0); // [time: 970.002ns -> 990.002ns] - write(15, 67108866, 3113679544, 0); // [time: 990.002ns -> 1000.002ns] - write(15, 67108867, 2723657215, 0); // [time: 1000.002ns -> 1010.002ns] - write(15, 67108864, 3578979173, 0); // [time: 1010.002ns -> 1020.002ns] - write(15, 67108869, 1844094072, 0); // [time: 1020.002ns -> 1030.002ns] - write(15, 67108870, 985922533, 0); // [time: 1030.002ns -> 1040.002ns] - write(15, 67108871, 772047228, 0); // [time: 1040.002ns -> 1050.002ns] - write(15, 67108868, 2786594234, 0); // [time: 1050.002ns -> 1060.002ns] - read(15, 67108865, 61321282, 0); // [time: 1060.002ns -> 1080.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_4_2.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_4_2.monitor.expect deleted file mode 100644 index efb5de91..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_4_2.monitor.expect +++ /dev/null @@ -1,37 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108865, 869832817, 0); // [time: 250ns -> 270ns] - read(15, 67108866, 2976082601, 0); // [time: 270ns -> 280ns] - read(15, 67108867, 373695501, 0); // [time: 280ns -> 290ns] - read(15, 67108868, 2110838384, 0); // [time: 290ns -> 300ns] - read(15, 67108869, 3556455435, 0); // [time: 300ns -> 310ns] - read(15, 67108870, 1804567173, 0); // [time: 310ns -> 320ns] - read(15, 67108871, 1187331577, 0); // [time: 320ns -> 330ns] - read(15, 67108864, 1293993917, 0); // [time: 330ns -> 340ns] - reset(); // [time: 380.001ns -> 390.001ns] - reset(); // [time: 390.001ns -> 400.001ns] - reset(); // [time: 400.001ns -> 410.001ns] - write(15, 67108865, 753581369, 0); // [time: 450.001ns -> 470.001ns] - write(15, 67108866, 2300246917, 0); // [time: 470.001ns -> 480.001ns] - write(15, 67108867, 3523846629, 0); // [time: 480.001ns -> 490.001ns] - write(15, 67108868, 3751494934, 0); // [time: 490.001ns -> 500.001ns] - write(15, 67108869, 504397671, 0); // [time: 500.001ns -> 510.001ns] - write(15, 67108870, 3203321461, 0); // [time: 510.001ns -> 520.001ns] - write(15, 67108871, 3801714021, 0); // [time: 520.001ns -> 530.001ns] - write(15, 67108864, 654543662, 0); // [time: 530.001ns -> 540.001ns] - reset(); // [time: 900.002ns -> 910.002ns] - reset(); // [time: 910.002ns -> 920.002ns] - reset(); // [time: 920.002ns -> 930.002ns] - write(15, 67108865, 1829143953, 0); // [time: 970.002ns -> 990.002ns] - write(15, 67108866, 2746894674, 0); // [time: 990.002ns -> 1000.002ns] - write(15, 67108867, 3464933947, 0); // [time: 1000.002ns -> 1010.002ns] - write(15, 67108868, 3350075041, 0); // [time: 1010.002ns -> 1020.002ns] - write(15, 67108869, 1123364414, 0); // [time: 1020.002ns -> 1030.002ns] - write(15, 67108870, 3896266205, 0); // [time: 1030.002ns -> 1040.002ns] - write(15, 67108871, 3668919860, 0); // [time: 1040.002ns -> 1050.002ns] - write(15, 67108864, 177490457, 0); // [time: 1050.002ns -> 1060.002ns] - read(15, 67108865, 1829143953, 0); // [time: 1060.002ns -> 1080.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_4_3.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_4_3.monitor.expect deleted file mode 100644 index 84c4435f..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_4_3.monitor.expect +++ /dev/null @@ -1,37 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108865, 1070372987, 0); // [time: 250ns -> 270ns] - read(15, 67108866, 2645947069, 0); // [time: 270ns -> 280ns] - read(15, 67108867, 736643984, 0); // [time: 280ns -> 290ns] - read(15, 67108868, 192007203, 0); // [time: 290ns -> 300ns] - read(15, 67108869, 1925400290, 0); // [time: 300ns -> 310ns] - read(15, 67108870, 1309609983, 0); // [time: 310ns -> 320ns] - read(15, 67108871, 58503546, 0); // [time: 320ns -> 330ns] - read(15, 67108872, 3861022989, 0); // [time: 330ns -> 340ns] - reset(); // [time: 380.001ns -> 390.001ns] - reset(); // [time: 390.001ns -> 400.001ns] - reset(); // [time: 400.001ns -> 410.001ns] - write(15, 67108865, 1725708128, 0); // [time: 450.001ns -> 470.001ns] - write(15, 67108866, 3760744365, 0); // [time: 470.001ns -> 480.001ns] - write(15, 67108867, 3803789590, 0); // [time: 480.001ns -> 490.001ns] - write(15, 67108868, 2647121574, 0); // [time: 490.001ns -> 500.001ns] - write(15, 67108869, 336117328, 0); // [time: 500.001ns -> 510.001ns] - write(15, 67108870, 3984726565, 0); // [time: 510.001ns -> 520.001ns] - write(15, 67108871, 104808193, 0); // [time: 520.001ns -> 530.001ns] - write(15, 67108872, 2315494688, 0); // [time: 530.001ns -> 540.001ns] - reset(); // [time: 900.002ns -> 910.002ns] - reset(); // [time: 910.002ns -> 920.002ns] - reset(); // [time: 920.002ns -> 930.002ns] - write(15, 67108865, 3997204021, 0); // [time: 970.002ns -> 990.002ns] - write(15, 67108866, 666660673, 0); // [time: 990.002ns -> 1000.002ns] - write(15, 67108867, 3910223084, 0); // [time: 1000.002ns -> 1010.002ns] - write(15, 67108868, 1271405124, 0); // [time: 1010.002ns -> 1020.002ns] - write(15, 67108869, 4236388983, 0); // [time: 1020.002ns -> 1030.002ns] - write(15, 67108870, 1347016890, 0); // [time: 1030.002ns -> 1040.002ns] - write(15, 67108871, 1337396640, 0); // [time: 1040.002ns -> 1050.002ns] - write(15, 67108872, 3009712000, 0); // [time: 1050.002ns -> 1060.002ns] - read(15, 67108865, 3997204021, 0); // [time: 1060.002ns -> 1080.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_8_0.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_8_0.monitor.expect deleted file mode 100644 index e937ca48..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_8_0.monitor.expect +++ /dev/null @@ -1,37 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108866, 2821946881, 0); // [time: 250ns -> 270ns] - read(15, 67108867, 4080087070, 0); // [time: 270ns -> 280ns] - read(15, 67108868, 2243193877, 0); // [time: 280ns -> 290ns] - read(15, 67108869, 2472849580, 0); // [time: 290ns -> 300ns] - read(15, 67108870, 3565370026, 0); // [time: 300ns -> 310ns] - read(15, 67108871, 890985600, 0); // [time: 310ns -> 320ns] - read(15, 67108872, 4179549189, 0); // [time: 320ns -> 330ns] - read(15, 67108873, 4158632492, 0); // [time: 330ns -> 340ns] - reset(); // [time: 380.001ns -> 390.001ns] - reset(); // [time: 390.001ns -> 400.001ns] - reset(); // [time: 400.001ns -> 410.001ns] - write(15, 67108866, 3744957516, 0); // [time: 450.001ns -> 470.001ns] - write(15, 67108867, 2300150418, 0); // [time: 470.001ns -> 480.001ns] - write(15, 67108868, 2081940992, 0); // [time: 480.001ns -> 490.001ns] - write(15, 67108869, 1697819148, 0); // [time: 490.001ns -> 500.001ns] - write(15, 67108870, 602241333, 0); // [time: 500.001ns -> 510.001ns] - write(15, 67108871, 2260552922, 0); // [time: 510.001ns -> 520.001ns] - write(15, 67108872, 4251564751, 0); // [time: 520.001ns -> 530.001ns] - write(15, 67108873, 3326548024, 0); // [time: 530.001ns -> 540.001ns] - reset(); // [time: 900.002ns -> 910.002ns] - reset(); // [time: 910.002ns -> 920.002ns] - reset(); // [time: 920.002ns -> 930.002ns] - write(15, 67108866, 1044044861, 0); // [time: 970.002ns -> 990.002ns] - write(15, 67108867, 4177314760, 0); // [time: 990.002ns -> 1000.002ns] - write(15, 67108868, 4253662683, 0); // [time: 1000.002ns -> 1010.002ns] - write(15, 67108869, 3575602093, 0); // [time: 1010.002ns -> 1020.002ns] - write(15, 67108870, 667576938, 0); // [time: 1020.002ns -> 1030.002ns] - write(15, 67108871, 3110079964, 0); // [time: 1030.002ns -> 1040.002ns] - write(15, 67108872, 3758039968, 0); // [time: 1040.002ns -> 1050.002ns] - write(15, 67108873, 3566852678, 0); // [time: 1050.002ns -> 1060.002ns] - read(15, 67108866, 1044044861, 0); // [time: 1060.002ns -> 1080.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_8_1.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_8_1.monitor.expect deleted file mode 100644 index 2c1254d3..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_8_1.monitor.expect +++ /dev/null @@ -1,37 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108866, 1833423740, 0); // [time: 250ns -> 270ns] - read(15, 67108867, 4073618608, 0); // [time: 270ns -> 280ns] - read(15, 67108864, 3418745219, 0); // [time: 280ns -> 290ns] - read(15, 67108865, 3757272308, 0); // [time: 290ns -> 300ns] - read(15, 67108870, 1325530178, 0); // [time: 300ns -> 310ns] - read(15, 67108871, 1451722922, 0); // [time: 310ns -> 320ns] - read(15, 67108868, 1997677454, 0); // [time: 320ns -> 330ns] - read(15, 67108869, 986005841, 0); // [time: 330ns -> 340ns] - reset(); // [time: 380.001ns -> 390.001ns] - reset(); // [time: 390.001ns -> 400.001ns] - reset(); // [time: 400.001ns -> 410.001ns] - write(15, 67108866, 789975088, 0); // [time: 450.001ns -> 470.001ns] - write(15, 67108867, 3746918692, 0); // [time: 470.001ns -> 480.001ns] - write(15, 67108864, 410224063, 0); // [time: 480.001ns -> 490.001ns] - write(15, 67108865, 864118294, 0); // [time: 490.001ns -> 500.001ns] - write(15, 67108870, 908783806, 0); // [time: 500.001ns -> 510.001ns] - write(15, 67108871, 2735695332, 0); // [time: 510.001ns -> 520.001ns] - write(15, 67108868, 3991830963, 0); // [time: 520.001ns -> 530.001ns] - write(15, 67108869, 3613974492, 0); // [time: 530.001ns -> 540.001ns] - reset(); // [time: 900.002ns -> 910.002ns] - reset(); // [time: 910.002ns -> 920.002ns] - reset(); // [time: 920.002ns -> 930.002ns] - write(15, 67108866, 1515921225, 0); // [time: 970.002ns -> 990.002ns] - write(15, 67108867, 104974629, 0); // [time: 990.002ns -> 1000.002ns] - write(15, 67108864, 966302149, 0); // [time: 1000.002ns -> 1010.002ns] - write(15, 67108865, 4157870389, 0); // [time: 1010.002ns -> 1020.002ns] - write(15, 67108870, 2924407148, 0); // [time: 1020.002ns -> 1030.002ns] - write(15, 67108871, 1538378206, 0); // [time: 1030.002ns -> 1040.002ns] - write(15, 67108868, 60846013, 0); // [time: 1040.002ns -> 1050.002ns] - write(15, 67108869, 3809194079, 0); // [time: 1050.002ns -> 1060.002ns] - read(15, 67108866, 1515921225, 0); // [time: 1060.002ns -> 1080.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_8_2.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_8_2.monitor.expect deleted file mode 100644 index 0e6c8c94..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_8_2.monitor.expect +++ /dev/null @@ -1,37 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108866, 869832817, 0); // [time: 250ns -> 270ns] - read(15, 67108867, 2976082601, 0); // [time: 270ns -> 280ns] - read(15, 67108868, 373695501, 0); // [time: 280ns -> 290ns] - read(15, 67108869, 2110838384, 0); // [time: 290ns -> 300ns] - read(15, 67108870, 3556455435, 0); // [time: 300ns -> 310ns] - read(15, 67108871, 1804567173, 0); // [time: 310ns -> 320ns] - read(15, 67108864, 1187331577, 0); // [time: 320ns -> 330ns] - read(15, 67108865, 1293993917, 0); // [time: 330ns -> 340ns] - reset(); // [time: 380.001ns -> 390.001ns] - reset(); // [time: 390.001ns -> 400.001ns] - reset(); // [time: 400.001ns -> 410.001ns] - write(15, 67108866, 753581369, 0); // [time: 450.001ns -> 470.001ns] - write(15, 67108867, 2300246917, 0); // [time: 470.001ns -> 480.001ns] - write(15, 67108868, 3523846629, 0); // [time: 480.001ns -> 490.001ns] - write(15, 67108869, 3751494934, 0); // [time: 490.001ns -> 500.001ns] - write(15, 67108870, 504397671, 0); // [time: 500.001ns -> 510.001ns] - write(15, 67108871, 3203321461, 0); // [time: 510.001ns -> 520.001ns] - write(15, 67108864, 3801714021, 0); // [time: 520.001ns -> 530.001ns] - write(15, 67108865, 654543662, 0); // [time: 530.001ns -> 540.001ns] - reset(); // [time: 900.002ns -> 910.002ns] - reset(); // [time: 910.002ns -> 920.002ns] - reset(); // [time: 920.002ns -> 930.002ns] - write(15, 67108866, 1829143953, 0); // [time: 970.002ns -> 990.002ns] - write(15, 67108867, 2746894674, 0); // [time: 990.002ns -> 1000.002ns] - write(15, 67108868, 3464933947, 0); // [time: 1000.002ns -> 1010.002ns] - write(15, 67108869, 3350075041, 0); // [time: 1010.002ns -> 1020.002ns] - write(15, 67108870, 1123364414, 0); // [time: 1020.002ns -> 1030.002ns] - write(15, 67108871, 3896266205, 0); // [time: 1030.002ns -> 1040.002ns] - write(15, 67108864, 3668919860, 0); // [time: 1040.002ns -> 1050.002ns] - write(15, 67108865, 177490457, 0); // [time: 1050.002ns -> 1060.002ns] - read(15, 67108866, 1829143953, 0); // [time: 1060.002ns -> 1080.002ns] -} diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_8_3.monitor.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_8_3.monitor.expect deleted file mode 100644 index 847ef6a7..00000000 --- a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_8_3.monitor.expect +++ /dev/null @@ -1,37 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 20ns -> 30ns] - reset(); // [time: 30ns -> 40ns] - reset(); // [time: 40ns -> 50ns] - read(15, 67108866, 1070372987, 0); // [time: 250ns -> 270ns] - read(15, 67108867, 2645947069, 0); // [time: 270ns -> 280ns] - read(15, 67108868, 736643984, 0); // [time: 280ns -> 290ns] - read(15, 67108869, 192007203, 0); // [time: 290ns -> 300ns] - read(15, 67108870, 1925400290, 0); // [time: 300ns -> 310ns] - read(15, 67108871, 1309609983, 0); // [time: 310ns -> 320ns] - read(15, 67108872, 58503546, 0); // [time: 320ns -> 330ns] - read(15, 67108873, 3861022989, 0); // [time: 330ns -> 340ns] - reset(); // [time: 380.001ns -> 390.001ns] - reset(); // [time: 390.001ns -> 400.001ns] - reset(); // [time: 400.001ns -> 410.001ns] - write(15, 67108866, 1725708128, 0); // [time: 450.001ns -> 470.001ns] - write(15, 67108867, 3760744365, 0); // [time: 470.001ns -> 480.001ns] - write(15, 67108868, 3803789590, 0); // [time: 480.001ns -> 490.001ns] - write(15, 67108869, 2647121574, 0); // [time: 490.001ns -> 500.001ns] - write(15, 67108870, 336117328, 0); // [time: 500.001ns -> 510.001ns] - write(15, 67108871, 3984726565, 0); // [time: 510.001ns -> 520.001ns] - write(15, 67108872, 104808193, 0); // [time: 520.001ns -> 530.001ns] - write(15, 67108873, 2315494688, 0); // [time: 530.001ns -> 540.001ns] - reset(); // [time: 900.002ns -> 910.002ns] - reset(); // [time: 910.002ns -> 920.002ns] - reset(); // [time: 920.002ns -> 930.002ns] - write(15, 67108866, 3997204021, 0); // [time: 970.002ns -> 990.002ns] - write(15, 67108867, 666660673, 0); // [time: 990.002ns -> 1000.002ns] - write(15, 67108868, 3910223084, 0); // [time: 1000.002ns -> 1010.002ns] - write(15, 67108869, 1271405124, 0); // [time: 1010.002ns -> 1020.002ns] - write(15, 67108870, 4236388983, 0); // [time: 1020.002ns -> 1030.002ns] - write(15, 67108871, 1347016890, 0); // [time: 1030.002ns -> 1040.002ns] - write(15, 67108872, 1337396640, 0); // [time: 1040.002ns -> 1050.002ns] - write(15, 67108873, 3009712000, 0); // [time: 1050.002ns -> 1060.002ns] - read(15, 67108866, 3997204021, 0); // [time: 1060.002ns -> 1080.002ns] -} diff --git a/tests/brave_new_world_francis/expects/bit_truncation_fft.monitor.expect b/tests/brave_new_world_francis/expects/bit_truncation_fft.monitor.expect deleted file mode 100644 index 2861938d..00000000 --- a/tests/brave_new_world_francis/expects/bit_truncation_fft.monitor.expect +++ /dev/null @@ -1,4 +0,0 @@ -// trace 0 -trace { - bit_truncation_fft(8386560, 2047); -} diff --git a/tests/brave_new_world_francis/expects/bit_truncation_sha.monitor.expect b/tests/brave_new_world_francis/expects/bit_truncation_sha.monitor.expect deleted file mode 100644 index 52f5d64f..00000000 --- a/tests/brave_new_world_francis/expects/bit_truncation_sha.monitor.expect +++ /dev/null @@ -1,4 +0,0 @@ -// trace 0 -trace { - bit_truncation_sha(4398046511104, 68719476736); -} diff --git a/tests/brave_new_world_francis/expects/ftu_sha.monitor.expect b/tests/brave_new_world_francis/expects/ftu_sha.monitor.expect deleted file mode 100644 index bf9d06bc..00000000 --- a/tests/brave_new_world_francis/expects/ftu_sha.monitor.expect +++ /dev/null @@ -1,4 +0,0 @@ -// trace 0 -trace { - failure_to_update_sha(); -} diff --git a/tests/brave_new_world_francis/expects/signal_async.monitor.expect b/tests/brave_new_world_francis/expects/signal_async.monitor.expect deleted file mode 100644 index ccd9f567..00000000 --- a/tests/brave_new_world_francis/expects/signal_async.monitor.expect +++ /dev/null @@ -1,4 +0,0 @@ -// trace 0 -trace { - signal_async(6, 7); -} diff --git a/tests/brave_new_world_francis/expects/use_without_valid.monitor.expect b/tests/brave_new_world_francis/expects/use_without_valid.monitor.expect deleted file mode 100644 index 1b5733f2..00000000 --- a/tests/brave_new_world_francis/expects/use_without_valid.monitor.expect +++ /dev/null @@ -1,4 +0,0 @@ -// trace 0 -trace { - use_without_valid(5, 5); -} diff --git a/tests/ethmac/expects/ethmac_wishbone_manager.monitor.expect b/tests/ethmac/expects/ethmac_wishbone_manager.monitor.expect deleted file mode 100644 index 57404ebb..00000000 --- a/tests/ethmac/expects/ethmac_wishbone_manager.monitor.expect +++ /dev/null @@ -1,2 +0,0 @@ ----CODE--- -2 diff --git a/tests/ethmac/expects/ethmac_wishbone_subordinate.monitor.expect b/tests/ethmac/expects/ethmac_wishbone_subordinate.monitor.expect deleted file mode 100644 index 57404ebb..00000000 --- a/tests/ethmac/expects/ethmac_wishbone_subordinate.monitor.expect +++ /dev/null @@ -1,2 +0,0 @@ ----CODE--- -2 diff --git a/tests/fifo/expects/fifo.monitor.expect b/tests/fifo/expects/fifo.monitor.expect deleted file mode 100644 index 8d3f2a95..00000000 --- a/tests/fifo/expects/fifo.monitor.expect +++ /dev/null @@ -1,9 +0,0 @@ -// trace 0 -trace { - reset(); - push(3); - push(4); - idle(); - pop(3); - pop(4); -} diff --git a/tests/fifo/expects/push_pop_identity.monitor.expect b/tests/fifo/expects/push_pop_identity.monitor.expect deleted file mode 100644 index 7b7038ac..00000000 --- a/tests/fifo/expects/push_pop_identity.monitor.expect +++ /dev/null @@ -1,9 +0,0 @@ -// trace 0 -trace { - reset(); - push(2); - pop(2); - idle(); - push(3); - pop(3); -} diff --git a/tests/fifo/expects/push_pop_loop_empty.monitor.expect b/tests/fifo/expects/push_pop_loop_empty.monitor.expect deleted file mode 100644 index 5b85e011..00000000 --- a/tests/fifo/expects/push_pop_loop_empty.monitor.expect +++ /dev/null @@ -1,2 +0,0 @@ ----CODE--- -124 diff --git a/tests/fifo/expects/push_pop_loop_not_empty.monitor.expect b/tests/fifo/expects/push_pop_loop_not_empty.monitor.expect deleted file mode 100644 index 5b85e011..00000000 --- a/tests/fifo/expects/push_pop_loop_not_empty.monitor.expect +++ /dev/null @@ -1,2 +0,0 @@ ----CODE--- -124 diff --git a/tests/fpga-debugging/axi-burst-s4/expects/s4_buggy.monitor.expect b/tests/fpga-debugging/axi-burst-s4/expects/s4_buggy.monitor.expect deleted file mode 100644 index 6503598b..00000000 --- a/tests/fpga-debugging/axi-burst-s4/expects/s4_buggy.monitor.expect +++ /dev/null @@ -1,2 +0,0 @@ ----CODE--- -1 diff --git a/tests/fpga-debugging/axi-burst-s4/expects/s4_fixed.monitor.expect b/tests/fpga-debugging/axi-burst-s4/expects/s4_fixed.monitor.expect deleted file mode 100644 index e92193ec..00000000 --- a/tests/fpga-debugging/axi-burst-s4/expects/s4_fixed.monitor.expect +++ /dev/null @@ -1,4 +0,0 @@ -// trace 0 -trace { - write_burst(1152, 3700821297, 15); // [time: 0.19ns -> 0.332ns] -} diff --git a/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy.monitor.expect b/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy.monitor.expect deleted file mode 100644 index 6503598b..00000000 --- a/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy.monitor.expect +++ /dev/null @@ -1,2 +0,0 @@ ----CODE--- -1 diff --git a/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy_workload_1.monitor.expect b/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy_workload_1.monitor.expect deleted file mode 100644 index 6503598b..00000000 --- a/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy_workload_1.monitor.expect +++ /dev/null @@ -1,2 +0,0 @@ ----CODE--- -1 diff --git a/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed.monitor.expect b/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed.monitor.expect deleted file mode 100644 index aabbc981..00000000 --- a/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed.monitor.expect +++ /dev/null @@ -1,8 +0,0 @@ -// trace 0 -trace { - WriteSubordinate::idle(); // [time: 0ns -> 25ns] - ReadSubordinate::idle(); // [time: 0ns -> 25ns] - WriteSubordinate::write(64, 2147483648, 0, 0); // [time: 25ns -> 100ns] - ReadSubordinate::read_v2(68, 0, 1); // [time: 50ns -> 125ns] - ReadSubordinate::idle(); // [time: 125ns -> 150ns] -} diff --git a/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed_workload_1.monitor.expect b/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed_workload_1.monitor.expect deleted file mode 100644 index 6503598b..00000000 --- a/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed_workload_1.monitor.expect +++ /dev/null @@ -1,2 +0,0 @@ ----CODE--- -1 diff --git a/tests/fpga-debugging/axi-stream-s2/expects/s2_buggy.monitor.expect b/tests/fpga-debugging/axi-stream-s2/expects/s2_buggy.monitor.expect deleted file mode 100644 index 343c9ed9..00000000 --- a/tests/fpga-debugging/axi-stream-s2/expects/s2_buggy.monitor.expect +++ /dev/null @@ -1,18 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 0ns -> 12.5ns] - wait_for_data(); // [time: 337.5ns -> 362.5ns] - wait_for_data(); // [time: 387.5ns -> 412.5ns] - wait_for_data(); // [time: 512.5ns -> 537.5ns] - wait_for_data(); // [time: 537.5ns -> 562.5ns] - wait_for_data(); // [time: 612.5ns -> 637.5ns] - wait_for_data(); // [time: 787.5ns -> 812.5ns] - wait_for_data(); // [time: 837.5ns -> 862.5ns] - recv(1); // [time: 862.5ns -> 887.5ns] - recv(2); // [time: 887.5ns -> 912.5ns] - recv(3); // [time: 912.5ns -> 937.5ns] - recv(4); // [time: 937.5ns -> 962.5ns] - recv(5); // [time: 962.5ns -> 987.5ns] - recv(6); // [time: 987.5ns -> 1012.5ns] - stall(7, 0); // [time: 1012.5ns -> 1050ns] -} diff --git a/tests/fpga-debugging/axi-stream-s2/expects/s2_fixed.monitor.expect b/tests/fpga-debugging/axi-stream-s2/expects/s2_fixed.monitor.expect deleted file mode 100644 index 190a394f..00000000 --- a/tests/fpga-debugging/axi-stream-s2/expects/s2_fixed.monitor.expect +++ /dev/null @@ -1,40 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 0ns -> 12.5ns] - wait_for_data(); // [time: 337.5ns -> 362.5ns] - wait_for_data(); // [time: 387.5ns -> 412.5ns] - wait_for_data(); // [time: 512.5ns -> 537.5ns] - wait_for_data(); // [time: 537.5ns -> 562.5ns] - wait_for_data(); // [time: 612.5ns -> 637.5ns] - wait_for_data(); // [time: 787.5ns -> 812.5ns] - wait_for_data(); // [time: 837.5ns -> 862.5ns] - recv(1); // [time: 862.5ns -> 887.5ns] - recv(2); // [time: 887.5ns -> 912.5ns] - recv(3); // [time: 912.5ns -> 937.5ns] - recv(4); // [time: 937.5ns -> 962.5ns] - recv(5); // [time: 962.5ns -> 987.5ns] - recv(6); // [time: 987.5ns -> 1012.5ns] - stall(7, 0); // [time: 1012.5ns -> 1062.5ns] - reset(); // [time: 1062.5ns -> 1087.5ns] - reset(); // [time: 1087.5ns -> 1100ns] -} - -// trace 1 -trace { - reset(); // [time: 0ns -> 12.5ns] - wait_for_data(); // [time: 337.5ns -> 362.5ns] - wait_for_data(); // [time: 387.5ns -> 412.5ns] - wait_for_data(); // [time: 512.5ns -> 537.5ns] - wait_for_data(); // [time: 537.5ns -> 562.5ns] - wait_for_data(); // [time: 612.5ns -> 637.5ns] - wait_for_data(); // [time: 787.5ns -> 812.5ns] - wait_for_data(); // [time: 837.5ns -> 862.5ns] - recv(1); // [time: 862.5ns -> 887.5ns] - recv(2); // [time: 887.5ns -> 912.5ns] - recv(3); // [time: 912.5ns -> 937.5ns] - recv(4); // [time: 937.5ns -> 962.5ns] - recv(5); // [time: 962.5ns -> 987.5ns] - recv(6); // [time: 987.5ns -> 1012.5ns] - reset(); // [time: 1062.5ns -> 1087.5ns] - reset(); // [time: 1087.5ns -> 1100ns] -} diff --git a/tests/fpga-debugging/axis-adapter-s3/expects/s3_buggy.monitor.expect b/tests/fpga-debugging/axis-adapter-s3/expects/s3_buggy.monitor.expect deleted file mode 100644 index fc233887..00000000 --- a/tests/fpga-debugging/axis-adapter-s3/expects/s3_buggy.monitor.expect +++ /dev/null @@ -1,13 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 0ns -> 25ns] - wait_for_data(); // [time: 25ns -> 50ns] - wait_for_data(); // [time: 50ns -> 75ns] - wait_for_data(); // [time: 75ns -> 100ns] - recv(205); // [time: 100ns -> 125ns] - recv(171); // [time: 125ns -> 150ns] - recv(205); // [time: 150ns -> 175ns] - recv(171); // [time: 175ns -> 200ns] - recv(205); // [time: 200ns -> 225ns] - recv_last(171); // [time: 225ns -> 237.5ns] -} diff --git a/tests/fpga-debugging/axis-adapter-s3/expects/s3_fixed.monitor.expect b/tests/fpga-debugging/axis-adapter-s3/expects/s3_fixed.monitor.expect deleted file mode 100644 index 989b7303..00000000 --- a/tests/fpga-debugging/axis-adapter-s3/expects/s3_fixed.monitor.expect +++ /dev/null @@ -1,12 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 0ns -> 25ns] - wait_for_data(); // [time: 25ns -> 50ns] - wait_for_data(); // [time: 50ns -> 75ns] - wait_for_data(); // [time: 75ns -> 100ns] - recv(205); // [time: 100ns -> 125ns] - recv(171); // [time: 125ns -> 150ns] - recv(205); // [time: 150ns -> 175ns] - recv(171); // [time: 175ns -> 200ns] - recv_last(205); // [time: 200ns -> 212.5ns] -} diff --git a/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.monitor.expect b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.monitor.expect deleted file mode 100644 index 6503598b..00000000 --- a/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.monitor.expect +++ /dev/null @@ -1,2 +0,0 @@ ----CODE--- -1 diff --git a/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_fixed.monitor.expect b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_fixed.monitor.expect deleted file mode 100644 index 421b780e..00000000 --- a/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_fixed.monitor.expect +++ /dev/null @@ -1,23 +0,0 @@ -// trace 0 -trace { - Sender::reset(); // [time: 0ns -> 25ns] - Receiver::reset(); // [time: 0ns -> 25ns] - Sender::idle(); // [time: 25ns -> 50ns] - Receiver::idle(); // [time: 25ns -> 50ns] - Sender::push(1); // [time: 50ns -> 75ns] - Receiver::idle(); // [time: 50ns -> 75ns] - Sender::push(2); // [time: 75ns -> 100ns] - Receiver::idle(); // [time: 75ns -> 100ns] - Sender::push(3); // [time: 100ns -> 150ns] - Receiver::pop(2); // [time: 100ns -> 150ns] - Sender::push(4); // [time: 150ns -> 175ns] - Receiver::pop(3); // [time: 125ns -> 175ns] - Sender::push(5); // [time: 175ns -> 200ns] - Receiver::pop(4); // [time: 150ns -> 200ns] - Sender::push(6); // [time: 200ns -> 225ns] - Receiver::pop(5); // [time: 175ns -> 225ns] - Sender::push(7); // [time: 225ns -> 250ns] - Receiver::pop(6); // [time: 200ns -> 250ns] - Sender::push(8); // [time: 250ns -> 262.5ns] - Receiver::pop(7); // [time: 225ns -> 262.5ns] -} diff --git a/tests/fpga-debugging/axis-fifo-d11/expects/d11_buggy.monitor.expect b/tests/fpga-debugging/axis-fifo-d11/expects/d11_buggy.monitor.expect deleted file mode 100644 index 7f01204e..00000000 --- a/tests/fpga-debugging/axis-fifo-d11/expects/d11_buggy.monitor.expect +++ /dev/null @@ -1,17 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 0ns -> 25ns] - push(1); // [time: 25ns -> 50ns] - push(1); // [time: 50ns -> 75ns] - push(2); // [time: 75ns -> 100ns] - push(4); // [time: 100ns -> 125ns] - push(5); // [time: 125ns -> 150ns] - push(6); // [time: 150ns -> 175ns] - push(6); // [time: 175ns -> 200ns] - push(6); // [time: 200ns -> 225ns] - push(6); // [time: 225ns -> 250ns] - push(6); // [time: 250ns -> 275ns] - push(6); // [time: 275ns -> 300ns] - reset(); // [time: 300ns -> 325ns] - push(6); // [time: 325ns -> 337.5ns] -} diff --git a/tests/fpga-debugging/axis-fifo-d11/expects/d11_fixed.monitor.expect b/tests/fpga-debugging/axis-fifo-d11/expects/d11_fixed.monitor.expect deleted file mode 100644 index 91c4edb1..00000000 --- a/tests/fpga-debugging/axis-fifo-d11/expects/d11_fixed.monitor.expect +++ /dev/null @@ -1,21 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 0ns -> 25ns] - push(1); // [time: 25ns -> 50ns] - push(1); // [time: 50ns -> 75ns] - push(2); // [time: 75ns -> 100ns] - push(4); // [time: 100ns -> 125ns] - push(5); // [time: 125ns -> 150ns] - push(6); // [time: 150ns -> 175ns] - push(6); // [time: 175ns -> 200ns] - push(6); // [time: 200ns -> 225ns] - push(6); // [time: 225ns -> 250ns] - push(6); // [time: 250ns -> 275ns] - push(6); // [time: 275ns -> 300ns] - reset(); // [time: 300ns -> 325ns] - push(6); // [time: 325ns -> 350ns] - push(6); // [time: 350ns -> 375ns] - push(7); // [time: 375ns -> 400ns] - push(7); // [time: 400ns -> 425ns] - push(7); // [time: 425ns -> 437.5ns] -} diff --git a/tests/fpga-debugging/axis-fifo-d12/expects/d12_buggy.monitor.expect b/tests/fpga-debugging/axis-fifo-d12/expects/d12_buggy.monitor.expect deleted file mode 100644 index 6a0936b1..00000000 --- a/tests/fpga-debugging/axis-fifo-d12/expects/d12_buggy.monitor.expect +++ /dev/null @@ -1,16 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 0ns -> 25ns] - push(1); // [time: 25ns -> 50ns] - push(1); // [time: 50ns -> 75ns] - push(2); // [time: 75ns -> 100ns] - push(3); // [time: 100ns -> 125ns] - push(4); // [time: 125ns -> 150ns] - push(5); // [time: 150ns -> 175ns] - push(6); // [time: 175ns -> 200ns] - pop(1); // [time: 200ns -> 250ns] - push_and_pop(6, 2); // [time: 225ns -> 275ns] - push_and_pop(6, 3); // [time: 250ns -> 300ns] - push_and_pop(7, 3); // [time: 275ns -> 325ns] - push_and_pop(7, 5); // [time: 300ns -> 362.5ns] -} diff --git a/tests/fpga-debugging/axis-fifo-d12/expects/d12_fixed.monitor.expect b/tests/fpga-debugging/axis-fifo-d12/expects/d12_fixed.monitor.expect deleted file mode 100644 index 4eeb0094..00000000 --- a/tests/fpga-debugging/axis-fifo-d12/expects/d12_fixed.monitor.expect +++ /dev/null @@ -1,15 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 0ns -> 25ns] - push(1); // [time: 25ns -> 50ns] - push(1); // [time: 50ns -> 75ns] - push(2); // [time: 75ns -> 100ns] - push(3); // [time: 100ns -> 125ns] - push(4); // [time: 125ns -> 150ns] - push(5); // [time: 150ns -> 175ns] - push(6); // [time: 175ns -> 200ns] - pop(1); // [time: 200ns -> 250ns] - push_and_pop(6, 2); // [time: 225ns -> 275ns] - push_and_pop(6, 3); // [time: 250ns -> 300ns] - push_and_pop(7, 3); // [time: 275ns -> 325ns] -} diff --git a/tests/fpga-debugging/axis-fifo-d4/expects/d4_buggy.monitor.expect b/tests/fpga-debugging/axis-fifo-d4/expects/d4_buggy.monitor.expect deleted file mode 100644 index 168cdc90..00000000 --- a/tests/fpga-debugging/axis-fifo-d4/expects/d4_buggy.monitor.expect +++ /dev/null @@ -1,47 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 0ns -> 2.5ns] - reset(); // [time: 2.5ns -> 5ns] - reset(); // [time: 5ns -> 7.5ns] - reset(); // [time: 7.5ns -> 10ns] - reset(); // [time: 10ns -> 12.5ns] - reset(); // [time: 12.5ns -> 15ns] - reset(); // [time: 15ns -> 17.5ns] - reset(); // [time: 17.5ns -> 20ns] - reset(); // [time: 20ns -> 22.5ns] - reset(); // [time: 22.5ns -> 25ns] - push(0); // [time: 37.5ns -> 40ns] - push(1); // [time: 40ns -> 42.5ns] - push(2); // [time: 42.5ns -> 45ns] - push(3); // [time: 45ns -> 47.5ns] - push(4); // [time: 47.5ns -> 50ns] - push(5); // [time: 50ns -> 52.5ns] - push(6); // [time: 52.5ns -> 55ns] - push(7); // [time: 55ns -> 57.5ns] - push(8); // [time: 57.5ns -> 60ns] - push(9); // [time: 60ns -> 62.5ns] - push(233); // [time: 62.5ns -> 65ns] - push(0); // [time: 77.5ns -> 80ns] - push(1); // [time: 80ns -> 82.5ns] - push(2); // [time: 82.5ns -> 85ns] - push(3); // [time: 85ns -> 87.5ns] - push(4); // [time: 87.5ns -> 90ns] - push(5); // [time: 90ns -> 92.5ns] - push(6); // [time: 92.5ns -> 95ns] - push(7); // [time: 95ns -> 97.5ns] - push(8); // [time: 97.5ns -> 100ns] - push(9); // [time: 100ns -> 102.5ns] - push(233); // [time: 102.5ns -> 105ns] - push(0); // [time: 117.5ns -> 120ns] - push(1); // [time: 120ns -> 122.5ns] - push(2); // [time: 122.5ns -> 125ns] - push(3); // [time: 125ns -> 127.5ns] - push(4); // [time: 127.5ns -> 130ns] - push(5); // [time: 130ns -> 132.5ns] - push(6); // [time: 132.5ns -> 135ns] - push(7); // [time: 135ns -> 137.5ns] - push(8); // [time: 137.5ns -> 140ns] - push(9); // [time: 140ns -> 142.5ns] - push(233); // [time: 142.5ns -> 145ns] - push(0); // [time: 157.5ns -> 158.75ns] -} diff --git a/tests/fpga-debugging/axis-fifo-d4/expects/d4_fixed.monitor.expect b/tests/fpga-debugging/axis-fifo-d4/expects/d4_fixed.monitor.expect deleted file mode 100644 index 6503598b..00000000 --- a/tests/fpga-debugging/axis-fifo-d4/expects/d4_fixed.monitor.expect +++ /dev/null @@ -1,2 +0,0 @@ ----CODE--- -1 diff --git a/tests/identities/expects/identity_d1.monitor.expect b/tests/identities/expects/identity_d1.monitor.expect deleted file mode 100644 index c47a0da0..00000000 --- a/tests/identities/expects/identity_d1.monitor.expect +++ /dev/null @@ -1,4 +0,0 @@ -// trace 0 -trace { - slicing_ok(1, 0); -} diff --git a/tests/multi/expects/multi0.monitor.expect b/tests/multi/expects/multi0.monitor.expect deleted file mode 100644 index 8219b9ab..00000000 --- a/tests/multi/expects/multi0.monitor.expect +++ /dev/null @@ -1,4 +0,0 @@ -// trace 0 -trace { - multi(10, 10); -} diff --git a/tests/multi/expects/multi0keep.monitor.expect b/tests/multi/expects/multi0keep.monitor.expect deleted file mode 100644 index 8219b9ab..00000000 --- a/tests/multi/expects/multi0keep.monitor.expect +++ /dev/null @@ -1,4 +0,0 @@ -// trace 0 -trace { - multi(10, 10); -} diff --git a/tests/multi/expects/multi0keep2const.monitor.expect b/tests/multi/expects/multi0keep2const.monitor.expect deleted file mode 100644 index 8219b9ab..00000000 --- a/tests/multi/expects/multi0keep2const.monitor.expect +++ /dev/null @@ -1,4 +0,0 @@ -// trace 0 -trace { - multi(10, 10); -} diff --git a/tests/multi/expects/multi2const.monitor.expect b/tests/multi/expects/multi2const.monitor.expect deleted file mode 100644 index 8219b9ab..00000000 --- a/tests/multi/expects/multi2const.monitor.expect +++ /dev/null @@ -1,4 +0,0 @@ -// trace 0 -trace { - multi(10, 10); -} diff --git a/tests/multi/expects/multi2multi.monitor.expect b/tests/multi/expects/multi2multi.monitor.expect deleted file mode 100644 index 8219b9ab..00000000 --- a/tests/multi/expects/multi2multi.monitor.expect +++ /dev/null @@ -1,4 +0,0 @@ -// trace 0 -trace { - multi(10, 10); -} diff --git a/tests/multi/expects/multi_data.monitor.expect b/tests/multi/expects/multi_data.monitor.expect deleted file mode 100644 index 8219b9ab..00000000 --- a/tests/multi/expects/multi_data.monitor.expect +++ /dev/null @@ -1,4 +0,0 @@ -// trace 0 -trace { - multi(10, 10); -} diff --git a/tests/multipliers/expects/mult_d2.monitor.expect b/tests/multipliers/expects/mult_d2.monitor.expect deleted file mode 100644 index e81c6c28..00000000 --- a/tests/multipliers/expects/mult_d2.monitor.expect +++ /dev/null @@ -1,5 +0,0 @@ -// trace 0 -trace { - mul(1, 2, 2); - mul(6, 8, 48); -} diff --git a/tests/picorv32/expects/pcpi_mul_unsigned_mul.monitor.expect b/tests/picorv32/expects/pcpi_mul_unsigned_mul.monitor.expect deleted file mode 100644 index 7b7bd936..00000000 --- a/tests/picorv32/expects/pcpi_mul_unsigned_mul.monitor.expect +++ /dev/null @@ -1,8 +0,0 @@ -// trace 0 -trace { - pcpi_mul_reset(); - pcpi_mul(1, 1, 1, 33554483); - pcpi_mul(1, 100, 100, 33554483); - pcpi_mul(100, 1, 100, 33554483); - pcpi_mul(33554483, 200, 2415929304, 33554483); -} diff --git a/tests/serv/expects/serv_regfile.monitor.expect b/tests/serv/expects/serv_regfile.monitor.expect deleted file mode 100644 index 92f93316..00000000 --- a/tests/serv/expects/serv_regfile.monitor.expect +++ /dev/null @@ -1,5 +0,0 @@ -// trace 0 -trace { - read_write(0x00, 0x00000000, 0x00000000, 0x00, 0x1, 0x05, 0xdeadbeef); - read_write(0x05, 0xdeadbeef, 0x00000000, 0x00, 0x0, 0x00, 0x00000000); -} diff --git a/tests/tinyaes128/expects/aes128.monitor.expect b/tests/tinyaes128/expects/aes128.monitor.expect deleted file mode 100644 index 0153c201..00000000 --- a/tests/tinyaes128/expects/aes128.monitor.expect +++ /dev/null @@ -1,5 +0,0 @@ -// trace 0 -trace { - aes128(0x000102030405060708090a0b0c0d0e0f, 0x00112233445566778899aabbccddeeff, 0x69c4e0d86a7b0430d8cdb78070b4c55a); - aes128(0x00000000000000000000000000000000, 0x00000000000000000000000000000000, 0x66e94bd4ef8a2c3b884cfa59ca342b2e); -} diff --git a/tests/wal/advanced/expects/axis.monitor.expect b/tests/wal/advanced/expects/axis.monitor.expect deleted file mode 100644 index 6503598b..00000000 --- a/tests/wal/advanced/expects/axis.monitor.expect +++ /dev/null @@ -1,2 +0,0 @@ ----CODE--- -1 diff --git a/tests/wal/advanced/expects/axis_failing.monitor.expect b/tests/wal/advanced/expects/axis_failing.monitor.expect deleted file mode 100644 index 6503598b..00000000 --- a/tests/wal/advanced/expects/axis_failing.monitor.expect +++ /dev/null @@ -1,2 +0,0 @@ ----CODE--- -1 diff --git a/tests/wal/advanced/expects/axis_minimal.monitor.expect b/tests/wal/advanced/expects/axis_minimal.monitor.expect deleted file mode 100644 index 6503598b..00000000 --- a/tests/wal/advanced/expects/axis_minimal.monitor.expect +++ /dev/null @@ -1,2 +0,0 @@ ----CODE--- -1 diff --git a/tests/wal/advanced/expects/axis_truncated.monitor.expect b/tests/wal/advanced/expects/axis_truncated.monitor.expect deleted file mode 100644 index 6503598b..00000000 --- a/tests/wal/advanced/expects/axis_truncated.monitor.expect +++ /dev/null @@ -1,2 +0,0 @@ ----CODE--- -1 diff --git a/tests/wal/advanced/expects/axis_truncated_include_idle.monitor.expect b/tests/wal/advanced/expects/axis_truncated_include_idle.monitor.expect deleted file mode 100644 index 6503598b..00000000 --- a/tests/wal/advanced/expects/axis_truncated_include_idle.monitor.expect +++ /dev/null @@ -1,2 +0,0 @@ ----CODE--- -1 diff --git a/tests/wb_intercon/expects/wb_arb.monitor.expect b/tests/wb_intercon/expects/wb_arb.monitor.expect deleted file mode 100644 index 57404ebb..00000000 --- a/tests/wb_intercon/expects/wb_arb.monitor.expect +++ /dev/null @@ -1,2 +0,0 @@ ----CODE--- -2 diff --git a/tests/wb_intercon/expects/wb_cdc.monitor.expect b/tests/wb_intercon/expects/wb_cdc.monitor.expect deleted file mode 100644 index 672093d3..00000000 --- a/tests/wb_intercon/expects/wb_cdc.monitor.expect +++ /dev/null @@ -1,125 +0,0 @@ -// trace 0 -trace { - reset(); // [time: 157140570s -> 157140580s] - write(15, 40, 2297678865, 0); // [time: 157140580s -> 157140650s] - write(15, 44, 3604862125, 0); // [time: 157140650s -> 157140730s] - write(15, 48, 648269133, 0); // [time: 157140730s -> 157140800s] - write(15, 52, 223519002, 0); // [time: 157140800s -> 157140880s] - write(15, 56, 2069755382, 0); // [time: 157140880s -> 157140950s] - write(15, 60, 2191335941, 0); // [time: 157140950s -> 157141030s] - write(15, 64, 3011745895, 0); // [time: 157141030s -> 157141100s] - write(15, 68, 90880778, 0); // [time: 157141100s -> 157141180s] - write(15, 72, 2066225142, 0); // [time: 157141180s -> 157141250s] - write(15, 76, 3164103289, 0); // [time: 157141250s -> 157141330s] - write(15, 80, 594197318, 0); // [time: 157141330s -> 157141400s] - write(15, 84, 2156596737, 0); // [time: 157141400s -> 157141480s] - write(15, 88, 186359062, 0); // [time: 157141480s -> 157141550s] - write(15, 92, 3868659405, 0); // [time: 157141550s -> 157141630s] - write(15, 96, 1617133504, 0); // [time: 157141630s -> 157141700s] - write(15, 100, 3134092405, 0); // [time: 157141700s -> 157141780s] - write(15, 104, 2246488587, 0); // [time: 157141780s -> 157141850s] - write(15, 108, 2723046980, 0); // [time: 157141850s -> 157141930s] - write(15, 112, 1486549937, 0); // [time: 157141930s -> 157142000s] - write(15, 116, 3286469255, 0); // [time: 157142000s -> 157142080s] - write(15, 120, 4098377448, 0); // [time: 157142080s -> 157142150s] - write(15, 124, 2392678941, 0); // [time: 157142150s -> 157142230s] - write(15, 128, 2473386534, 0); // [time: 157142230s -> 157142300s] - write(15, 132, 1973988843, 0); // [time: 157142300s -> 157142380s] - write(15, 136, 1945895911, 0); // [time: 157142380s -> 157142450s] - write(15, 140, 2928197725, 0); // [time: 157142450s -> 157142530s] - write(15, 144, 1966069738, 0); // [time: 157142530s -> 157142600s] - write(15, 148, 445118261, 0); // [time: 157142600s -> 157142680s] - write(15, 152, 459691318, 0); // [time: 157142680s -> 157142750s] - write(15, 156, 1979121643, 0); // [time: 157142750s -> 157142830s] - write(15, 160, 4257292027, 0); // [time: 157142830s -> 157142900s] - write(15, 164, 529745215, 0); // [time: 157142900s -> 157142980s] - read(15, 40, 2297678865, 0); // [time: 157143060s -> 157143140s] - read(15, 44, 3604862125, 0); // [time: 157143140s -> 157143220s] - read(15, 48, 648269133, 0); // [time: 157143220s -> 157143290s] - read(15, 52, 223519002, 0); // [time: 157143290s -> 157143370s] - read(15, 56, 2069755382, 0); // [time: 157143370s -> 157143460s] - read(15, 60, 2191335941, 0); // [time: 157143460s -> 157143550s] - read(15, 64, 3011745895, 0); // [time: 157143550s -> 157143620s] - read(15, 68, 90880778, 0); // [time: 157143620s -> 157143700s] - read(15, 72, 2066225142, 0); // [time: 157143700s -> 157143790s] - read(15, 76, 3164103289, 0); // [time: 157143790s -> 157143880s] - read(15, 80, 594197318, 0); // [time: 157143880s -> 157143970s] - read(15, 84, 2156596737, 0); // [time: 157143970s -> 157144060s] - read(15, 88, 186359062, 0); // [time: 157144060s -> 157144160s] - read(15, 92, 3868659405, 0); // [time: 157144160s -> 157144250s] - read(15, 96, 1617133504, 0); // [time: 157144250s -> 157144350s] - read(15, 100, 3134092405, 0); // [time: 157144350s -> 157144430s] - read(15, 104, 2246488587, 0); // [time: 157144430s -> 157144510s] - read(15, 108, 2723046980, 0); // [time: 157144510s -> 157144590s] - read(15, 112, 1486549937, 0); // [time: 157144590s -> 157144690s] - read(15, 116, 3286469255, 0); // [time: 157144690s -> 157144770s] - read(15, 120, 4098377448, 0); // [time: 157144770s -> 157144840s] - read(15, 124, 2392678941, 0); // [time: 157144840s -> 157144930s] - read(15, 128, 2473386534, 0); // [time: 157144930s -> 157145030s] - read(15, 132, 1973988843, 0); // [time: 157145030s -> 157145120s] - read(15, 136, 1945895911, 0); // [time: 157145120s -> 157145210s] - read(15, 140, 2928197725, 0); // [time: 157145210s -> 157145290s] - read(15, 144, 1966069738, 0); // [time: 157145290s -> 157145380s] - read(15, 148, 445118261, 0); // [time: 157145380s -> 157145460s] - read(15, 152, 459691318, 0); // [time: 157145460s -> 157145530s] - read(15, 156, 1979121643, 0); // [time: 157145530s -> 157145600s] - read(15, 160, 4257292027, 0); // [time: 157145600s -> 157145680s] - read(15, 164, 529745215, 0); // [time: 157145680s -> 157145770s] - write(15, 144, 100689676, 0); // [time: 157145850s -> 157145920s] - write(15, 144, 942429552, 0); // [time: 157145920s -> 157145990s] - write(15, 144, 2379269659, 0); // [time: 157145990s -> 157146070s] - write(15, 144, 3999281884, 0); // [time: 157146070s -> 157146140s] - write(15, 144, 4119078123, 0); // [time: 157146140s -> 157146220s] - write(15, 144, 1946599400, 0); // [time: 157146220s -> 157146290s] - write(15, 144, 4276983549, 0); // [time: 157146290s -> 157146370s] - write(15, 144, 3399752341, 0); // [time: 157146370s -> 157146440s] - write(15, 144, 3017292903, 0); // [time: 157146440s -> 157146520s] - write(15, 144, 972684659, 0); // [time: 157146520s -> 157146590s] - write(15, 144, 441524532, 0); // [time: 157146590s -> 157146670s] - write(15, 144, 1334844831, 0); // [time: 157146670s -> 157146740s] - write(15, 144, 565975363, 0); // [time: 157146740s -> 157146820s] - write(15, 144, 2815133775, 0); // [time: 157146820s -> 157146890s] - write(15, 140, 980134772, 0); // [time: 157146970s -> 157147040s] - write(15, 140, 3907850449, 0); // [time: 157147040s -> 157147120s] - write(15, 140, 2654200892, 0); // [time: 157147120s -> 157147190s] - write(15, 140, 906927468, 0); // [time: 157147190s -> 157147270s] - write(15, 140, 2737849414, 0); // [time: 157147270s -> 157147340s] - write(15, 140, 1677170119, 0); // [time: 157147340s -> 157147420s] - write(15, 140, 850693989, 0); // [time: 157147420s -> 157147490s] - write(15, 140, 1398815142, 0); // [time: 157147490s -> 157147570s] - write(15, 140, 3709909178, 0); // [time: 157147570s -> 157147640s] - write(15, 140, 1945896423, 0); // [time: 157147640s -> 157147720s] - write(15, 140, 2953822816, 0); // [time: 157147720s -> 157147790s] - write(15, 140, 2304971794, 0); // [time: 157147790s -> 157147870s] - write(15, 140, 521770302, 0); // [time: 157147870s -> 157147940s] - write(15, 140, 3333586061, 0); // [time: 157147940s -> 157148020s] - read(15, 44, 3604862125, 0); // [time: 157148100s -> 157148180s] - read(15, 92, 3868659405, 0); // [time: 157148260s -> 157148350s] - write(15, 124, 2820663376, 0); // [time: 157148430s -> 157148500s] - write(15, 64, 662417230, 0); // [time: 157148500s -> 157148570s] - write(15, 68, 2464031269, 0); // [time: 157148570s -> 157148650s] - write(15, 72, 73062664, 0); // [time: 157148650s -> 157148720s] - write(15, 76, 4029952224, 0); // [time: 157148720s -> 157148800s] - write(15, 80, 793527134, 0); // [time: 157148800s -> 157148870s] - write(15, 84, 6582016, 0); // [time: 157148870s -> 157148950s] - write(15, 88, 3617108655, 0); // [time: 157148950s -> 157149020s] - write(15, 92, 406619440, 0); // [time: 157149020s -> 157149100s] - write(15, 96, 4277193981, 0); // [time: 157149100s -> 157149170s] - write(15, 100, 736184151, 0); // [time: 157149170s -> 157149250s] - write(15, 104, 3641666226, 0); // [time: 157149250s -> 157149320s] - write(15, 108, 45454085, 0); // [time: 157149320s -> 157149400s] - write(15, 112, 4110092521, 0); // [time: 157149400s -> 157149470s] - write(15, 116, 4069799141, 0); // [time: 157149470s -> 157149550s] - write(15, 120, 4206762229, 0); // [time: 157149550s -> 157149620s] - write(15, 124, 2304033810, 0); // [time: 157149620s -> 157149700s] - write(15, 64, 170815764, 0); // [time: 157149700s -> 157149770s] - write(15, 68, 4065560292, 0); // [time: 157149770s -> 157149850s] - write(15, 128, 3474693278, 0); // [time: 157149930s -> 157150000s] - write(15, 128, 3665053876, 0); // [time: 157150000s -> 157150070s] - write(15, 128, 486294841, 0); // [time: 157150070s -> 157150150s] - write(15, 128, 1205356431, 0); // [time: 157150150s -> 157150220s] - write(15, 128, 3354562191, 0); // [time: 157150220s -> 157150300s] - write(15, 128, 4215211766, 0); // [time: 157150300s -> 157150370s] - write(15, 128, 1790934485, 0); // [time: 157150370s -> 157150450s] - write(15, 128, 2949267551, 0); // [time: 157150450s -> 157150520s] -} diff --git a/tests/wishbone/expects/wishbone.monitor.expect b/tests/wishbone/expects/wishbone.monitor.expect deleted file mode 100644 index 734ce750..00000000 --- a/tests/wishbone/expects/wishbone.monitor.expect +++ /dev/null @@ -1,18 +0,0 @@ -// trace 0 -trace { - read(0, 0); - write(0, 0); - read(0, 3); - read(0, 5); - read(0, 7); - read(0, 9); - read(0, 11); - read(0, 0); - write(0, 0); - read(0, 3); - read(0, 5); - read(0, 7); - read(0, 9); - read(0, 11); - read(0, 0); -} diff --git a/uv.lock b/uv.lock index 204847f7..f1f647a9 100644 --- a/uv.lock +++ b/uv.lock @@ -2,406 +2,10 @@ version = 1 revision = 3 requires-python = ">=3.12" -[[package]] -name = "colorama" -version = "0.4.6" -source = { registry = "https://pypi.org/simple" } -sdist = { url = "https://files.pythonhosted.org/packages/d8/53/6f443c9a4a8358a93a6792e2acffb9d9d5cb0a5cfd8802644b7b1c9a02e4/colorama-0.4.6.tar.gz", hash = "sha256:08695f5cb7ed6e0531a20572697297273c47b8cae5a63ffc6d6ed5c201be6e44", size = 27697, upload-time = "2022-10-25T02:36:22.414Z" } -wheels = [ - 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We also check that assignments, assertions and conditionals (`if` and `while`) abide by the grammars discussed below. These grammars are designed in order to make it tractable to reconstruct transactions from a waveform and `.prot` file -(which is what the monitor does) ### Grammar for assignments - In assignments `LHS := RHS`, `LHS` & `RHS` must conform to the following grammar: From b5c4fe70c0f6209a20d396fbcbc9a1f00a9858b7 Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sat, 18 Jul 2026 11:22:09 -0400 Subject: [PATCH 18/55] Update scripts for generating runt catalog --- scripts/generate_runt_configs.py | 17 ++++++----------- scripts/test_catalog.py | 7 +++---- 2 files changed, 9 insertions(+), 15 deletions(-) diff --git a/scripts/generate_runt_configs.py b/scripts/generate_runt_configs.py index 41930bf6..6b67d6f7 100644 --- a/scripts/generate_runt_configs.py +++ b/scripts/generate_runt_configs.py @@ -43,18 +43,16 @@ def load_tx_cases() -> list[dict]: return out -def load_monitor_cases() -> list[dict]: - """Same idea as load_tx_cases but for the monitor cases""" +def load_bi_cases() -> list[dict]: + """Same idea as load_tx_cases but for the bi cases""" out = [] - for case_id, c in test_catalog.MONITOR_CASES.items(): + for case_id, c in test_catalog.BI_CASES.items(): out.append( { "id": case_id, "path": c["protocol"], "wave": c.get("wave"), "instances": c.get("instances", ()), - "max_steps": c.get("max_steps"), - "timeout_secs": c.get("timeout_secs"), "extra_args": c.get("extra_args", ()), "expected": c["expect"], } @@ -190,8 +188,6 @@ def bi_runt_command(case: dict) -> list[tuple[str, str]]: if case["instances"]: cmd += ["--instances", *case["instances"]] cmd += case["extra_args"] - if case["timeout_secs"] is not None: - cmd = timeout_cmd(case["timeout_secs"], cmd) # We redirect stderr to stdout so that the expected output files # contain error messages if BI fails return [("", repo_root_command(cmd, stderr="stdout"))] @@ -384,13 +380,12 @@ def write_runt_toml(output_dir: Path, suites) -> None: def generate_runt_configs() -> None: tx = load_tx_cases() - mon = load_monitor_cases() + bi = load_bi_cases() # Each suite maps a name to (runner, cases). interp + graph_interp - # together cover every tx test. + # together cover every test. suite_specs = { "interp": ("interp", tx), - # The bi suite runs over the wave-based cases (MONITOR_CASES). - "bi": ("bi", mon), + "bi": ("bi", bi), "graph_interp": ("graph_interp", graph_interp_cases(tx)), "waveform": ("waveform", waveform_cases(tx)), "fail": ("fail", fail_cases(tx)), diff --git a/scripts/test_catalog.py b/scripts/test_catalog.py index 507e2cc9..ea93d722 100644 --- a/scripts/test_catalog.py +++ b/scripts/test_catalog.py @@ -1,8 +1,7 @@ # Checked-in test catalog. Hand-maintained source of truth. # Consumed by scripts/generate_runt_configs.py. # -# TX_CASES are keyed by their .tx path. MONITOR_CASES (the wave-based cases that -# drive the bi suite) are keyed by a unique id +# TX_CASES are keyed by their .tx path. BI_CASES are keyed by a unique id TX_CASES = { "examples/picorv32/unsigned_mul.tx": { @@ -502,7 +501,7 @@ }, } -MONITOR_CASES = { +BI_CASES = { "tests.adders.add_d1": { "protocol": "tests/adders/add_d1.prot", "wave": "tests/adders/add_d1.fst", @@ -1094,7 +1093,7 @@ def _antmicro_case(stem): } -MONITOR_CASES.update( +BI_CASES.update( { f"tests.antmicro.{stem.replace('/', '.')}": _antmicro_case(stem) for stem in ANTMICRO_TRACE_STEMS From 224ef81d787e4d1ecb397bf08150a902932e0d36 Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sat, 18 Jul 2026 11:26:44 -0400 Subject: [PATCH 19/55] update readme to refer to BI instead of monitor --- README.md | 58 +++++++++++++++++++++++++------------------------------ 1 file changed, 26 insertions(+), 32 deletions(-) diff --git a/README.md b/README.md index f3dab58a..989fcad1 100644 --- a/README.md +++ b/README.md @@ -11,9 +11,9 @@ A protocol is described using an `prot` definition containing a sequence of stat This repository contains: - An *interpreter* for the DSL -- A *monitor* tool, which given a specification of a hardware module's communication behavior (written in our DSL) +- A *backwards interpreter* (BI) tool, which given a specification of a hardware module's communication behavior (written in our DSL) and a `.fst` waveform file, infers a transaction-level trace that is consistent with the waveform data -- Common infrastructure shared between the interpreter & the monitor, such as a parser, type-checker and pretty-printer for our DSL +- Common infrastructure shared between the interpreter & the BI, such as a parser, type-checker and pretty-printer for our DSL These tools are all implemented in Rust, with some auxiliary benchmarking scripts written in Python. ## Installation + Build Instructions @@ -29,17 +29,7 @@ Note: the instructions below assume a macOS environment. - (Optional) Run `brew install hyperfine` to install [Hyperfine](https://github.com/sharkdp/hyperfine), a command-line benchmarking tool - Run `brew install just` to install [Just](https://github.com/casey/just), a command runner - Run `cargo install --git https://github.com/Nikil-Shyamsunder/runt.git` to install our fork of [Runt](https://github.com/rachitnigam/runt), a command-line tool we use for snapshot tests. Runt compares the output of our tools to expected outputs stored in dedicated files. - -**Dependencies for benchmarking the monitor**: - Run `uv sync` to install the Python dependencies specified in `pyproject.toml` -- Then, from the top-level directory, run the following scripts (note that they take ~3 minutes to run): -```bash -$ uv run scripts/benchmark_monitor.py -$ uv run scripts/plot_benchmark_results.py -``` -- This produces a CSV and a scatter plot measuring the performance of the monitor in - `benchmark_results/benchmark_results.csv` and `benchmark_results/benchmark_plot.png` respectively - - Some of the benchmarks correspond to real-world bugs taken from the [artifact for *Debugging in the Brave New World of Reconfigurable Hardware* (Ma et al. ASPLOS '22)](https://github.com/efeslab/asplos22-hardware-debugging-artifact) -- these can be found in the `tests/fpga-debugging` sub-directory (more details in the `README` of the sub-directories corresponding to each bug) @@ -49,43 +39,47 @@ $ uv run scripts/plot_benchmark_results.py **Building the source code**: - Run `cargo build` to build the Rust code - Run `just test` to execute all unit tests (`cargo test`) + snapshot tests (via Runt) - - To only run the subset of tests for the monitor, run `just monitor` - To generate HTML documentation, run `just doc` (this opens Cargo-generated docs in your browser) -## Monitor CLI -The CLI for the monitor can be used as follows: +## Backwards Interpreter CLI +The CLI for the BI can be used as follows: ```bash -$ cargo monitor --help +$ cargo bi --help +analyze signal traces to extract transactions -Usage: protocols-monitor [OPTIONS] --protocol --wave +Usage: bi [OPTIONS] --wave Options: -p, --protocol - Path to a Protocol (.prot) file + One or several protocol files. -w, --wave Path to a waveform trace (.fst, .vcd, .ghw) file -i, --instances ... - A mapping of DUT struct in the protocol file to an instance in the signal trace. Multiple arguments can be passed if they're seperated by whitespace. Format is: `${instance_name}:${dut_struct_name}` + A mapping of DUT struct in the protocol file to an instance in the signal trace. Can be used multiple times. Format is: `${instance_name}:${dut_struct_name} -v, --verbose... Increase logging verbosity -q, --quiet... Decrease logging verbosity - --color - To suppress colors in error messages, pass in `--color never` Otherwise, by default, error messages are displayed w/ ANSI colors [default: auto] [possible values: auto, always, never] - -d, --display-hex - If enabled, displays integer literals using hexadecimal notation --sample-posedge Optional argument which specifies the name of the signal to sample on a rising edge (posedge). If enabled, this flag acts as the "clock" signal for the monitor. Note: the full path to the signal should be passed as this argument, e.g. `uut_rx.clk`, where `uut_rx` is an instance in the signal trace - --show-waveform-time - If enabled, displays the start & end waveform time for each inferred transaction - --show-thread-ids - If enabled, displays the thread ID corresponding to each inferred transaction - --time-unit - Specifies the time unit for displaying waveform times. Can only be used with --show-waveform-time. Valid options: fs, ps, ns, us, ms, s, auto Default is 'auto' which selects the unit based on the maximum time in the waveform - --print-num-steps - Optional flag: if enabled, prints the no. of (logical) steps (i.e. clock cycles) taken by the montior --include-idle Optional flag: if enabled, always prints out idle transcations regardless of whether the protocol has been annotated with `#[idle]` + --show-steps + If enabled, displays the start & end step for each inferred transaction + --include-in-progress + This flag will make the bi append any in-progress transactions to the trace + --show-waveform-time + + --time-unit + + --max-traces + Limit the number of traces written to stdout + --color + To suppress colors in error messages, pass in `--color never`. Otherwise, by default, error messages are displayed with colors [default: auto] [possible values: auto, always, never] + -d, --display-hex + If enabled, displays integer literals using hexadecimal notation + -r, --rename ... + Rename pins of the DUT. &{field name in the struct} = ${verilog name} -h, --help Print help ``` @@ -93,7 +87,7 @@ Options: Example usage: ```bash $ cd tests -$ cargo monitor -p adders/add_d1.prot --wave adders/add_d1.fst --instances add_d1:Adder +$ cargo bi -p adders/add_d1.prot --wave adders/add_d1.fst --instances add_d1:Adder ``` ## Interpreter CLI From 975ee639dd5a57b8df26c28c409f3f31158892f0 Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sat, 18 Jul 2026 11:34:31 -0400 Subject: [PATCH 20/55] Change .monitor.prot test cases to bi.prot --- scripts/test_catalog.py | 16 ++++++++-------- .../alus/{alu_d1.monitor.prot => alu_d1.bi.prot} | 0 .../alus/{alu_d2.monitor.prot => alu_d2.bi.prot} | 0 tests/fifo/{fifo.monitor.prot => fifo.bi.prot} | 0 .../{wishbone.monitor.prot => wishbone.bi.prot} | 0 5 files changed, 8 insertions(+), 8 deletions(-) rename tests/alus/{alu_d1.monitor.prot => alu_d1.bi.prot} (100%) rename tests/alus/{alu_d2.monitor.prot => alu_d2.bi.prot} (100%) rename tests/fifo/{fifo.monitor.prot => fifo.bi.prot} (100%) rename tests/wishbone/{wishbone.monitor.prot => wishbone.bi.prot} (100%) diff --git a/scripts/test_catalog.py b/scripts/test_catalog.py index ea93d722..004e5309 100644 --- a/scripts/test_catalog.py +++ b/scripts/test_catalog.py @@ -539,14 +539,14 @@ "expect": None, "timeout_secs": 5, }, - "tests.alus.alu_d1.monitor": { - "protocol": "tests/alus/alu_d1.monitor.prot", + "tests.alus.alu_d1.bi": { + "protocol": "tests/alus/alu_d1.bi.prot", "wave": "tests/alus/alu_d1.fst", "instances": ("alu_d1:ALU",), "expect": "pass", }, - "tests.alus.alu_d2.monitor": { - "protocol": "tests/alus/alu_d2.monitor.prot", + "tests.alus.alu_d2.bi": { + "protocol": "tests/alus/alu_d2.bi.prot", "wave": "tests/alus/alu_d2.fst", "instances": ("alu_d2:ALU",), "expect": "pass", @@ -605,8 +605,8 @@ "ns", ), }, - "tests.fifo.fifo.monitor": { - "protocol": "tests/fifo/fifo.monitor.prot", + "tests.fifo.fifo.bi": { + "protocol": "tests/fifo/fifo.bi.prot", "wave": "tests/fifo/fifo.fst", "instances": ("fifo_wrapper:Fifo",), "expect": "pass", @@ -1048,8 +1048,8 @@ "s", ), }, - "tests.wishbone.wishbone.monitor": { - "protocol": "tests/wishbone/wishbone.monitor.prot", + "tests.wishbone.wishbone.bi": { + "protocol": "tests/wishbone/wishbone.bi.prot", "wave": "tests/wishbone/reqwalker.vcd", "instances": ("TOP.reqwalker:WBSubordinate",), "expect": "pass", diff --git a/tests/alus/alu_d1.monitor.prot b/tests/alus/alu_d1.bi.prot similarity index 100% rename from tests/alus/alu_d1.monitor.prot rename to tests/alus/alu_d1.bi.prot diff --git a/tests/alus/alu_d2.monitor.prot b/tests/alus/alu_d2.bi.prot similarity index 100% rename from tests/alus/alu_d2.monitor.prot rename to tests/alus/alu_d2.bi.prot diff --git a/tests/fifo/fifo.monitor.prot b/tests/fifo/fifo.bi.prot similarity index 100% rename from tests/fifo/fifo.monitor.prot rename to tests/fifo/fifo.bi.prot diff --git a/tests/wishbone/wishbone.monitor.prot b/tests/wishbone/wishbone.bi.prot similarity index 100% rename from tests/wishbone/wishbone.monitor.prot rename to tests/wishbone/wishbone.bi.prot From b0924d152cab9b46e392c17ca9511af6361cb4eb Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sat, 18 Jul 2026 11:34:50 -0400 Subject: [PATCH 21/55] Update case_stem function to refer to .bi suffix instead of .monitor --- scripts/generate_runt_configs.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/scripts/generate_runt_configs.py b/scripts/generate_runt_configs.py index 6b67d6f7..c2df419f 100644 --- a/scripts/generate_runt_configs.py +++ b/scripts/generate_runt_configs.py @@ -71,13 +71,13 @@ def replace_non_alphanumerics(value: object) -> str: def case_stem(case: dict) -> str: - # antmicro monitor cases share one .prot but differ by wave, so name them by - # the wave; otherwise use the test file's stem (dropping a .monitor suffix). + # antmicro cases share one .prot but differ by wave, so name them by + # the wave; otherwise use the test file's stem (dropping a .bi suffix). wave = case.get("wave") if wave and case["path"].startswith("tests/antmicro/"): return Path(wave).stem stem = Path(case["path"]).stem - return stem.removesuffix(".monitor") + return stem.removesuffix(".bi") def expect_name(case: dict, runner: str) -> str: From ec880b30b723001061ad23e560c611478c2422bd Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sat, 18 Jul 2026 11:34:55 -0400 Subject: [PATCH 22/55] Regenerate Runt config --- runt/bi/runt.toml | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/runt/bi/runt.toml b/runt/bi/runt.toml index c188ce6f..2427fd8a 100644 --- a/runt/bi/runt.toml +++ b/runt/bi/runt.toml @@ -52,25 +52,25 @@ paths = [ ] expect_dir = "../../tests/adders/expects" expect_name = "nested_busy_wait.bi.expect" -cmd = "cd ../.. && python3 -c 'import os, signal, subprocess, sys\np = subprocess.Popen(sys.argv[2:], start_new_session=True)\ntry:\n sys.exit(p.wait(timeout=float(sys.argv[1])))\nexcept subprocess.TimeoutExpired:\n os.killpg(p.pid, signal.SIGKILL)\n sys.exit(124)\n' 5 target/debug/bi --color never --protocol tests/adders/nested_busy_wait.prot --wave tests/adders/nested_busy_wait.fst --instances add_d1:Adder 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/adders/nested_busy_wait.prot --wave tests/adders/nested_busy_wait.fst --instances add_d1:Adder 2>&1" [[tests]] -name = "bi.tests_alus_alu_d1_monitor.alu_d1_bi" +name = "bi.tests_alus_alu_d1_bi.alu_d1_bi" paths = [ - "../../tests/alus/alu_d1.monitor.prot", + "../../tests/alus/alu_d1.bi.prot", ] expect_dir = "../../tests/alus/expects" expect_name = "alu_d1.bi.expect" -cmd = "cd ../.. && target/debug/bi --color never --protocol tests/alus/alu_d1.monitor.prot --wave tests/alus/alu_d1.fst --instances alu_d1:ALU 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/alus/alu_d1.bi.prot --wave tests/alus/alu_d1.fst --instances alu_d1:ALU 2>&1" [[tests]] -name = "bi.tests_alus_alu_d2_monitor.alu_d2_bi" +name = "bi.tests_alus_alu_d2_bi.alu_d2_bi" paths = [ - "../../tests/alus/alu_d2.monitor.prot", + "../../tests/alus/alu_d2.bi.prot", ] expect_dir = "../../tests/alus/expects" expect_name = "alu_d2.bi.expect" -cmd = "cd ../.. && target/debug/bi --color never --protocol tests/alus/alu_d2.monitor.prot --wave tests/alus/alu_d2.fst --instances alu_d2:ALU 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/alus/alu_d2.bi.prot --wave tests/alus/alu_d2.fst --instances alu_d2:ALU 2>&1" [[tests]] name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_classic_1_bi" @@ -1180,13 +1180,13 @@ expect_name = "ethmac_wishbone_subordinate.bi.expect" cmd = "cd ../.. && target/debug/bi --color never --protocol tests/ethmac/ethmac_wishbone_subordinate.prot --instances tb_ethernet:WBSubordinate --sample-posedge tb_ethernet.wb_clk --show-waveform-time --time-unit ns 2>&1" [[tests]] -name = "bi.tests_fifo_fifo_monitor.fifo_bi" +name = "bi.tests_fifo_fifo_bi.fifo_bi" paths = [ - "../../tests/fifo/fifo.monitor.prot", + "../../tests/fifo/fifo.bi.prot", ] expect_dir = "../../tests/fifo/expects" expect_name = "fifo.bi.expect" -cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fifo/fifo.monitor.prot --wave tests/fifo/fifo.fst --instances fifo_wrapper:Fifo 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fifo/fifo.bi.prot --wave tests/fifo/fifo.fst --instances fifo_wrapper:Fifo 2>&1" [[tests]] name = "bi.tests_fifo_push_pop_identity.push_pop_identity_bi" @@ -1204,7 +1204,7 @@ paths = [ ] expect_dir = "../../tests/fifo/expects" expect_name = "push_pop_loop_empty.bi.expect" -cmd = "cd ../.. && python3 -c 'import os, signal, subprocess, sys\np = subprocess.Popen(sys.argv[2:], start_new_session=True)\ntry:\n sys.exit(p.wait(timeout=float(sys.argv[1])))\nexcept subprocess.TimeoutExpired:\n os.killpg(p.pid, signal.SIGKILL)\n sys.exit(124)\n' 5 target/debug/bi --color never --protocol tests/fifo/push_pop_loop_empty.prot --wave tests/fifo/push_pop_loop_empty.fst --instances fifo_wrapper:Fifo 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fifo/push_pop_loop_empty.prot --wave tests/fifo/push_pop_loop_empty.fst --instances fifo_wrapper:Fifo 2>&1" [[tests]] name = "bi.tests_fifo_push_pop_loop_not_empty.push_pop_loop_not_empty_bi" @@ -1213,7 +1213,7 @@ paths = [ ] expect_dir = "../../tests/fifo/expects" expect_name = "push_pop_loop_not_empty.bi.expect" -cmd = "cd ../.. && python3 -c 'import os, signal, subprocess, sys\np = subprocess.Popen(sys.argv[2:], start_new_session=True)\ntry:\n sys.exit(p.wait(timeout=float(sys.argv[1])))\nexcept subprocess.TimeoutExpired:\n os.killpg(p.pid, signal.SIGKILL)\n sys.exit(124)\n' 5 target/debug/bi --color never --protocol tests/fifo/push_pop_loop_not_empty.prot --wave tests/fifo/push_pop_loop_not_empty.fst --instances fifo_wrapper:Fifo 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fifo/push_pop_loop_not_empty.prot --wave tests/fifo/push_pop_loop_not_empty.fst --instances fifo_wrapper:Fifo 2>&1" [[tests]] name = "bi.tests_fpga_debugging_axi_burst_s4_s4_buggy.s4_buggy_bi" @@ -1540,10 +1540,10 @@ expect_name = "wb_cdc.bi.expect" cmd = "cd ../.. && target/debug/bi --color never --protocol tests/wb_intercon/wb_cdc.prot --wave tests/wb_intercon/wb_cdc.fst --instances wb_intercon_tb.wb_cdc_tb.dut:WBSubordinate --sample-posedge wb_intercon_tb.wb_cdc_tb.dut.wbm_clk --show-waveform-time --time-unit s 2>&1" [[tests]] -name = "bi.tests_wishbone_wishbone_monitor.wishbone_bi" +name = "bi.tests_wishbone_wishbone_bi.wishbone_bi" paths = [ - "../../tests/wishbone/wishbone.monitor.prot", + "../../tests/wishbone/wishbone.bi.prot", ] expect_dir = "../../tests/wishbone/expects" expect_name = "wishbone.bi.expect" -cmd = "cd ../.. && target/debug/bi --color never --protocol tests/wishbone/wishbone.monitor.prot --wave tests/wishbone/reqwalker.vcd --instances TOP.reqwalker:WBSubordinate --sample-posedge TOP.reqwalker.i_clk 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/wishbone/wishbone.bi.prot --wave tests/wishbone/reqwalker.vcd --instances TOP.reqwalker:WBSubordinate --sample-posedge TOP.reqwalker.i_clk 2>&1" From c9f6f89608aadcbc30c223fd2016d2ca30eb72e6 Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sat, 18 Jul 2026 11:37:09 -0400 Subject: [PATCH 23/55] update some outdated comments --- protocols/src/errors.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/protocols/src/errors.rs b/protocols/src/errors.rs index 7d1dc8a5..d2e0b057 100644 --- a/protocols/src/errors.rs +++ b/protocols/src/errors.rs @@ -75,7 +75,7 @@ pub enum EvaluationError { start: u32, end: u32, }, - /// (Trace comparison) When the value of an expression on the RHS + /// (For bi only) When the value of an expression on the RHS /// of an assignment disagreess with the actual observed trace value ValueDisagreesWithTrace { expr_id: ExprId, @@ -85,7 +85,7 @@ pub enum EvaluationError { symbol_name: String, cycle_count: u32, }, - /// (Trace comparison) When a constraint established by an assignment + /// (For bi only) When a constraint established by an assignment /// no longer holds after stepping to a new cycle ConstraintViolation { symbol_id: SymbolId, From 6b8765cf61b1fa895b3ceed6c431bfe9c69841c8 Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sat, 18 Jul 2026 11:57:02 -0400 Subject: [PATCH 24/55] Add new FailureKind enum to BI --- bi/src/bi.rs | 5 +++-- bi/src/proto_trace.rs | 28 +++++++++++++++++++++++++++- 2 files changed, 30 insertions(+), 3 deletions(-) diff --git a/bi/src/bi.rs b/bi/src/bi.rs index dd3bad40..a8eae6db 100644 --- a/bi/src/bi.rs +++ b/bi/src/bi.rs @@ -828,8 +828,9 @@ impl Thread { proto_id: ti.proto_id, thread_name: self.name.clone(), stmt, - a, - b, + a: a.clone(), + b: b.clone(), + kind: FailureKind::SignalValueMismatch { lhs: a, rhs: b } }) } } diff --git a/bi/src/proto_trace.rs b/bi/src/proto_trace.rs index ca93b1c1..728ea96d 100644 --- a/bi/src/proto_trace.rs +++ b/bi/src/proto_trace.rs @@ -4,7 +4,7 @@ //! # Protocol Traces and Error Reporting -use baa::BitVecValue; +use baa::{BitVecOps, BitVecValue}; use protocols::Value; use protocols::frontend::ast::StmtId; @@ -152,4 +152,30 @@ pub struct Failure { pub stmt: StmtId, pub a: BitVecValue, pub b: BitVecValue, + pub kind: FailureKind } + +#[derive(Debug, Clone, PartialEq)] +pub enum FailureKind { + /// When the value of a signal in the waveform differs from what we expect + /// (i.e. a constraint is violated) + SignalValueMismatch { lhs: BitVecValue, rhs: BitVecValue }, + /// A `fork` was reached before any `step`s have been called + ForkBeforeStep, +} + +impl Failure { + /// Error message portion of the failure (appears in diagnostics) + pub fn message(&self) -> String { + match &self.kind { + FailureKind::SignalValueMismatch { lhs, rhs } => format!( + "[{}] executing step {} of the transaction: {} != {}", + self.thread_name, self.thread_local_step, + lhs.to_hex_str(), rhs.to_hex_str(), + ), + FailureKind::ForkBeforeStep => format!( + "[{}] cannot fork at step zero", self.thread_name, + ), + } + } +} \ No newline at end of file From 0f4cfe4b6bde6716f5a163c5231852930a3e4a76 Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sat, 18 Jul 2026 12:01:48 -0400 Subject: [PATCH 25/55] Error-handling for BI when fork is called before step --- bi/src/bi.rs | 24 ++++++++++++++++-------- bi/src/main.rs | 10 +--------- bi/src/proto_trace.rs | 20 ++++++++++---------- 3 files changed, 27 insertions(+), 27 deletions(-) diff --git a/bi/src/bi.rs b/bi/src/bi.rs index a8eae6db..69eca2fb 100644 --- a/bi/src/bi.rs +++ b/bi/src/bi.rs @@ -632,11 +632,21 @@ impl Thread { } } Stmt::Fork => { - assert!(self.step > 0, "[{}] Cannot fork at step zero!", self.name); - self.has_forked = true; - self.next_stmt = ti.next_stmt[&stmt]; - self.effectful_stmt_in_step = true; - Fork + if self.step > 0 { + self.has_forked = true; + self.next_stmt = ti.next_stmt[&stmt]; + self.effectful_stmt_in_step = true; + Fork + } else { + self.failures.push(Failure { + thread_local_step: self.step, + proto_id: ti.proto_id, + thread_name: self.name.clone(), + stmt, + kind: FailureKind::ForkBeforeStep, + }); + Failed + } } Stmt::While(cond, body) => { let cond_value = self @@ -828,9 +838,7 @@ impl Thread { proto_id: ti.proto_id, thread_name: self.name.clone(), stmt, - a: a.clone(), - b: b.clone(), - kind: FailureKind::SignalValueMismatch { lhs: a, rhs: b } + kind: FailureKind::SignalValueMismatch { lhs: a, rhs: b }, }) } } diff --git a/bi/src/main.rs b/bi/src/main.rs index 6b878a59..db59353b 100644 --- a/bi/src/main.rs +++ b/bi/src/main.rs @@ -11,7 +11,6 @@ mod signal_trace; use crate::bi::*; use crate::proto_trace::*; use crate::signal_trace::*; -use baa::BitVecOps; use clap::{ColorChoice, Parser}; use clap_verbosity_flag::{Verbosity, WarnLevel}; use protocols::frontend; @@ -197,14 +196,7 @@ fn main() { for fail in fails { let proto = &protos[fail.proto_id]; - let msg = format!( - "[{}] executing step {} of the transaction: {} != {}", - fail.thread_name, - fail.thread_local_step, - fail.a.to_hex_str(), - fail.b.to_hex_str() - ); - d.emit_diagnostic_stmt(proto, &fail.stmt, &msg, Level::Error); + d.emit_diagnostic_stmt(proto, &fail.stmt, &fail.message(), Level::Error); } } } else { diff --git a/bi/src/proto_trace.rs b/bi/src/proto_trace.rs index 728ea96d..09be2c27 100644 --- a/bi/src/proto_trace.rs +++ b/bi/src/proto_trace.rs @@ -150,14 +150,12 @@ pub struct Failure { pub proto_id: usize, pub thread_name: String, pub stmt: StmtId, - pub a: BitVecValue, - pub b: BitVecValue, - pub kind: FailureKind + pub kind: FailureKind, } #[derive(Debug, Clone, PartialEq)] pub enum FailureKind { - /// When the value of a signal in the waveform differs from what we expect + /// When the value of a signal in the waveform differs from what we expect /// (i.e. a constraint is violated) SignalValueMismatch { lhs: BitVecValue, rhs: BitVecValue }, /// A `fork` was reached before any `step`s have been called @@ -170,12 +168,14 @@ impl Failure { match &self.kind { FailureKind::SignalValueMismatch { lhs, rhs } => format!( "[{}] executing step {} of the transaction: {} != {}", - self.thread_name, self.thread_local_step, - lhs.to_hex_str(), rhs.to_hex_str(), - ), - FailureKind::ForkBeforeStep => format!( - "[{}] cannot fork at step zero", self.thread_name, + self.thread_name, + self.thread_local_step, + lhs.to_hex_str(), + rhs.to_hex_str(), ), + FailureKind::ForkBeforeStep => { + format!("[{}] cannot fork at step zero", self.thread_name,) + } } } -} \ No newline at end of file +} From 146de939308d6820137f34dfe6baa2eeeb15fc0a Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sat, 18 Jul 2026 12:28:44 -0400 Subject: [PATCH 26/55] Update expect files for tests that previously panicked due to the 'fork before step' failure --- tests/adders/expects/busy_wait.bi.expect | 16 +- .../expects/loop_with_assigns.bi.expect | 31 +- .../adders/expects/nested_busy_wait.bi.expect | 248 +++++- .../expects/push_pop_loop_empty.bi.expect | 707 +++++++++++++++++- .../expects/push_pop_loop_not_empty.bi.expect | 79 +- 5 files changed, 1061 insertions(+), 20 deletions(-) diff --git a/tests/adders/expects/busy_wait.bi.expect b/tests/adders/expects/busy_wait.bi.expect index 89398f87..dd10c482 100644 --- a/tests/adders/expects/busy_wait.bi.expect +++ b/tests/adders/expects/busy_wait.bi.expect @@ -1,4 +1,12 @@ -panicked at bi/src/bi.rs:628:21: -[add_busy_wait@00!] Cannot fork at step zero! ----CODE--- -101 +// trace 0 +trace { + add_busy_wait(1, 2, 1, 3); + add_busy_wait(4, 5, 2, 9); +} + +// trace 1 +trace { + add_busy_wait(1, 2, 1, 3); + add_busy_wait(4, 5, 1, 9); + add_busy_wait(4, 5, 1, 9); +} diff --git a/tests/adders/expects/loop_with_assigns.bi.expect b/tests/adders/expects/loop_with_assigns.bi.expect index bb042478..42427fc9 100644 --- a/tests/adders/expects/loop_with_assigns.bi.expect +++ b/tests/adders/expects/loop_with_assigns.bi.expect @@ -1,4 +1,27 @@ -panicked at bi/src/bi.rs:628:21: -[loop_add@00!] Cannot fork at step zero! ----CODE--- -101 +// trace 0 +trace { + loop_add(1, 2, 2, 3); + loop_add(1, 2, 1, 3); + loop_add(10, 20, 1, 30); +} + +// trace 1 +trace { + loop_add(1, 2, 3, 3); + loop_add(10, 20, 1, 30); +} + +// trace 2 +trace { + loop_add(1, 2, 1, 3); + loop_add(1, 2, 1, 3); + loop_add(1, 2, 1, 3); + loop_add(10, 20, 1, 30); +} + +// trace 3 +trace { + loop_add(1, 2, 1, 3); + loop_add(1, 2, 2, 3); + loop_add(10, 20, 1, 30); +} diff --git a/tests/adders/expects/nested_busy_wait.bi.expect b/tests/adders/expects/nested_busy_wait.bi.expect index cd84b0ad..bcab7ed1 100644 --- a/tests/adders/expects/nested_busy_wait.bi.expect +++ b/tests/adders/expects/nested_busy_wait.bi.expect @@ -1,4 +1,244 @@ -panicked at bi/src/bi.rs:628:21: -[nested_busy_wait@00!] Cannot fork at step zero! ----CODE--- -101 +// trace 0 +trace { + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(10, 20, 2, 0, 30); + nested_busy_wait(10, 20, 2, 0, 30); + nested_busy_wait(10, 20, 2, 0, 30); + nested_busy_wait(10, 20, 2, 0, 30); +} + +// trace 1 +trace { + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(10, 20, 2, 0, 30); + nested_busy_wait(10, 20, 2, 0, 30); + nested_busy_wait(10, 20, 2, 0, 30); + nested_busy_wait(10, 20, 1, 0, 30); + nested_busy_wait(10, 20, 1, 0, 30); +} + +// trace 2 +trace { + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(10, 20, 2, 0, 30); + nested_busy_wait(10, 20, 2, 0, 30); + nested_busy_wait(10, 20, 2, 0, 30); + nested_busy_wait(10, 20, 1, 1, 30); +} + +// trace 3 +trace { + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(10, 20, 2, 0, 30); + nested_busy_wait(10, 20, 2, 0, 30); + nested_busy_wait(10, 20, 4, 0, 30); +} + +// trace 4 +trace { + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(10, 20, 2, 0, 30); + nested_busy_wait(10, 20, 2, 0, 30); + nested_busy_wait(10, 20, 3, 0, 30); + nested_busy_wait(10, 20, 1, 0, 30); +} + +// trace 5 +trace { + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(10, 20, 2, 0, 30); + nested_busy_wait(10, 20, 2, 0, 30); + nested_busy_wait(10, 20, 1, 0, 30); + nested_busy_wait(10, 20, 1, 1, 30); + nested_busy_wait(10, 20, 1, 0, 30); +} + +// trace 6 +trace { + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(10, 20, 2, 0, 30); + nested_busy_wait(10, 20, 2, 0, 30); + nested_busy_wait(10, 20, 1, 0, 30); + nested_busy_wait(10, 20, 1, 2, 30); +} + +// trace 7 +trace { + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(10, 20, 2, 0, 30); + nested_busy_wait(10, 20, 2, 0, 30); + nested_busy_wait(10, 20, 1, 0, 30); + nested_busy_wait(10, 20, 1, 0, 30); + nested_busy_wait(10, 20, 2, 0, 30); +} + +// trace 8 +trace { + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(10, 20, 2, 0, 30); + nested_busy_wait(10, 20, 2, 0, 30); + nested_busy_wait(10, 20, 1, 0, 30); + nested_busy_wait(10, 20, 1, 0, 30); + nested_busy_wait(10, 20, 1, 0, 30); + nested_busy_wait(10, 20, 1, 0, 30); +} + +// trace 9 +trace { + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(10, 20, 2, 0, 30); + nested_busy_wait(10, 20, 2, 0, 30); + nested_busy_wait(10, 20, 1, 0, 30); + nested_busy_wait(10, 20, 1, 0, 30); + nested_busy_wait(10, 20, 1, 1, 30); +} + +// trace 10 +trace { + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(10, 20, 2, 0, 30); + nested_busy_wait(10, 20, 2, 0, 30); + nested_busy_wait(10, 20, 1, 0, 30); + nested_busy_wait(10, 20, 3, 0, 30); +} + +// trace 11 +trace { + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(10, 20, 2, 0, 30); + nested_busy_wait(10, 20, 2, 0, 30); + nested_busy_wait(10, 20, 1, 0, 30); + nested_busy_wait(10, 20, 2, 0, 30); + nested_busy_wait(10, 20, 1, 0, 30); +} + +// trace 12 +trace { + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(10, 20, 2, 0, 30); + nested_busy_wait(10, 20, 2, 0, 30); + nested_busy_wait(10, 20, 1, 2, 30); + nested_busy_wait(10, 20, 1, 0, 30); +} + +// trace 13 +trace { + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(10, 20, 2, 0, 30); + nested_busy_wait(10, 20, 2, 0, 30); + nested_busy_wait(10, 20, 1, 3, 30); +} + +// trace 14 +trace { + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(10, 20, 2, 0, 30); + nested_busy_wait(10, 20, 2, 0, 30); + nested_busy_wait(10, 20, 1, 1, 30); + nested_busy_wait(10, 20, 2, 0, 30); +} + +// trace 15 +trace { + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(10, 20, 2, 0, 30); + nested_busy_wait(10, 20, 2, 0, 30); + nested_busy_wait(10, 20, 1, 1, 30); + nested_busy_wait(10, 20, 1, 0, 30); + nested_busy_wait(10, 20, 1, 0, 30); +} + +// trace 16 +trace { + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(10, 20, 2, 0, 30); + nested_busy_wait(10, 20, 2, 0, 30); + nested_busy_wait(10, 20, 1, 1, 30); + nested_busy_wait(10, 20, 1, 1, 30); +} + +// trace 17 +trace { + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(10, 20, 2, 0, 30); + nested_busy_wait(10, 20, 2, 0, 30); + nested_busy_wait(10, 20, 2, 1, 30); +} + +// trace 18 +trace { + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(10, 20, 2, 0, 30); + nested_busy_wait(10, 20, 4, 0, 30); + nested_busy_wait(10, 20, 2, 0, 30); +} + +// trace 19 +trace { + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(1, 2, 2, 0, 3); + nested_busy_wait(10, 20, 2, 0, 30); + nested_busy_wait(10, 20, 4, 0, 30); + nested_busy_wait(10, 20, 1, 0, 30); + nested_busy_wait(10, 20, 1, 0, 30); +} +Displayed 20/423801 traces. diff --git a/tests/fifo/expects/push_pop_loop_empty.bi.expect b/tests/fifo/expects/push_pop_loop_empty.bi.expect index 52c71229..248a01e1 100644 --- a/tests/fifo/expects/push_pop_loop_empty.bi.expect +++ b/tests/fifo/expects/push_pop_loop_empty.bi.expect @@ -1,4 +1,703 @@ -panicked at bi/src/bi.rs:628:21: -[pop_n_times@00!] Cannot fork at step zero! ----CODE--- -101 +// trace 0 +trace { + reset(); + push_n_times(42, 2); + push_n_times(42, 2); + pop_n_times(42, 2); + pop_n_times(42, 2); + check_empty(); +} + +// trace 1 +trace { + reset(); + push_n_times(42, 2); + push_n_times(42, 2); + pop_n_times(42, 2); + pop_n_times(42, 1); + pop_n_times(42, 1); + check_empty(); +} + +// trace 2 +trace { + reset(); + push_n_times(42, 2); + push_n_times(42, 2); + pop_n_times(42, 4); + check_empty(); +} + +// trace 3 +trace { + reset(); + push_n_times(42, 2); + push_n_times(42, 2); + pop_n_times(42, 3); + pop_n_times(42, 1); + check_empty(); +} + +// trace 4 +trace { + reset(); + push_n_times(42, 2); + push_n_times(42, 2); + pop_n_times(42, 1); + pop_n_times(42, 1); + pop_n_times(42, 2); + check_empty(); +} + +// trace 5 +trace { + reset(); + push_n_times(42, 2); + push_n_times(42, 2); + pop_n_times(42, 1); + pop_n_times(42, 1); + pop_n_times(42, 1); + pop_n_times(42, 1); + check_empty(); +} + +// trace 6 +trace { + reset(); + push_n_times(42, 2); + push_n_times(42, 2); + pop_n_times(42, 1); + pop_n_times(42, 3); + check_empty(); +} + +// trace 7 +trace { + reset(); + push_n_times(42, 2); + push_n_times(42, 2); + pop_n_times(42, 1); + pop_n_times(42, 2); + pop_n_times(42, 1); + check_empty(); +} + +// trace 8 +trace { + reset(); + push_n_times(42, 2); + push_n_times(42, 1); + push_n_times(42, 1); + pop_n_times(42, 2); + pop_n_times(42, 2); + check_empty(); +} + +// trace 9 +trace { + reset(); + push_n_times(42, 2); + push_n_times(42, 1); + push_n_times(42, 1); + pop_n_times(42, 2); + pop_n_times(42, 1); + pop_n_times(42, 1); + check_empty(); +} + +// trace 10 +trace { + reset(); + push_n_times(42, 2); + push_n_times(42, 1); + push_n_times(42, 1); + pop_n_times(42, 4); + check_empty(); +} + +// trace 11 +trace { + reset(); + push_n_times(42, 2); + push_n_times(42, 1); + push_n_times(42, 1); + pop_n_times(42, 3); + pop_n_times(42, 1); + check_empty(); +} + +// trace 12 +trace { + reset(); + push_n_times(42, 2); + push_n_times(42, 1); + push_n_times(42, 1); + pop_n_times(42, 1); + pop_n_times(42, 1); + pop_n_times(42, 2); + check_empty(); +} + +// trace 13 +trace { + reset(); + push_n_times(42, 2); + push_n_times(42, 1); + push_n_times(42, 1); + pop_n_times(42, 1); + pop_n_times(42, 1); + pop_n_times(42, 1); + pop_n_times(42, 1); + check_empty(); +} + +// trace 14 +trace { + reset(); + push_n_times(42, 2); + push_n_times(42, 1); + push_n_times(42, 1); + pop_n_times(42, 1); + pop_n_times(42, 3); + check_empty(); +} + +// trace 15 +trace { + reset(); + push_n_times(42, 2); + push_n_times(42, 1); + push_n_times(42, 1); + pop_n_times(42, 1); + pop_n_times(42, 2); + pop_n_times(42, 1); + check_empty(); +} + +// trace 16 +trace { + reset(); + push_n_times(42, 4); + pop_n_times(42, 2); + pop_n_times(42, 2); + check_empty(); +} + +// trace 17 +trace { + reset(); + push_n_times(42, 4); + pop_n_times(42, 2); + pop_n_times(42, 1); + pop_n_times(42, 1); + check_empty(); +} + +// trace 18 +trace { + reset(); + push_n_times(42, 4); + pop_n_times(42, 4); + check_empty(); +} + +// trace 19 +trace { + reset(); + push_n_times(42, 4); + pop_n_times(42, 3); + pop_n_times(42, 1); + check_empty(); +} + +// trace 20 +trace { + reset(); + push_n_times(42, 4); + pop_n_times(42, 1); + pop_n_times(42, 1); + pop_n_times(42, 2); + check_empty(); +} + +// trace 21 +trace { + reset(); + push_n_times(42, 4); + pop_n_times(42, 1); + pop_n_times(42, 1); + pop_n_times(42, 1); + pop_n_times(42, 1); + check_empty(); +} + +// trace 22 +trace { + reset(); + push_n_times(42, 4); + pop_n_times(42, 1); + pop_n_times(42, 3); + check_empty(); +} + +// trace 23 +trace { + reset(); + push_n_times(42, 4); + pop_n_times(42, 1); + pop_n_times(42, 2); + pop_n_times(42, 1); + check_empty(); +} + +// trace 24 +trace { + reset(); + push_n_times(42, 3); + push_n_times(42, 1); + pop_n_times(42, 2); + pop_n_times(42, 2); + check_empty(); +} + +// trace 25 +trace { + reset(); + push_n_times(42, 3); + push_n_times(42, 1); + pop_n_times(42, 2); + pop_n_times(42, 1); + pop_n_times(42, 1); + check_empty(); +} + +// trace 26 +trace { + reset(); + push_n_times(42, 3); + push_n_times(42, 1); + pop_n_times(42, 4); + check_empty(); +} + +// trace 27 +trace { + reset(); + push_n_times(42, 3); + push_n_times(42, 1); + pop_n_times(42, 3); + pop_n_times(42, 1); + check_empty(); +} + +// trace 28 +trace { + reset(); + push_n_times(42, 3); + push_n_times(42, 1); + pop_n_times(42, 1); + pop_n_times(42, 1); + pop_n_times(42, 2); + check_empty(); +} + +// trace 29 +trace { + reset(); + push_n_times(42, 3); + push_n_times(42, 1); + pop_n_times(42, 1); + pop_n_times(42, 1); + pop_n_times(42, 1); + pop_n_times(42, 1); + check_empty(); +} + +// trace 30 +trace { + reset(); + push_n_times(42, 3); + push_n_times(42, 1); + pop_n_times(42, 1); + pop_n_times(42, 3); + check_empty(); +} + +// trace 31 +trace { + reset(); + push_n_times(42, 3); + push_n_times(42, 1); + pop_n_times(42, 1); + pop_n_times(42, 2); + pop_n_times(42, 1); + check_empty(); +} + +// trace 32 +trace { + reset(); + push_n_times(42, 1); + push_n_times(42, 1); + push_n_times(42, 2); + pop_n_times(42, 2); + pop_n_times(42, 2); + check_empty(); +} + +// trace 33 +trace { + reset(); + push_n_times(42, 1); + push_n_times(42, 1); + push_n_times(42, 2); + pop_n_times(42, 2); + pop_n_times(42, 1); + pop_n_times(42, 1); + check_empty(); +} + +// trace 34 +trace { + reset(); + push_n_times(42, 1); + push_n_times(42, 1); + push_n_times(42, 2); + pop_n_times(42, 4); + check_empty(); +} + +// trace 35 +trace { + reset(); + push_n_times(42, 1); + push_n_times(42, 1); + push_n_times(42, 2); + pop_n_times(42, 3); + pop_n_times(42, 1); + check_empty(); +} + +// trace 36 +trace { + reset(); + push_n_times(42, 1); + push_n_times(42, 1); + push_n_times(42, 2); + pop_n_times(42, 1); + pop_n_times(42, 1); + pop_n_times(42, 2); + check_empty(); +} + +// trace 37 +trace { + reset(); + push_n_times(42, 1); + push_n_times(42, 1); + push_n_times(42, 2); + pop_n_times(42, 1); + pop_n_times(42, 1); + pop_n_times(42, 1); + pop_n_times(42, 1); + check_empty(); +} + +// trace 38 +trace { + reset(); + push_n_times(42, 1); + push_n_times(42, 1); + push_n_times(42, 2); + pop_n_times(42, 1); + pop_n_times(42, 3); + check_empty(); +} + +// trace 39 +trace { + reset(); + push_n_times(42, 1); + push_n_times(42, 1); + push_n_times(42, 2); + pop_n_times(42, 1); + pop_n_times(42, 2); + pop_n_times(42, 1); + check_empty(); +} + +// trace 40 +trace { + reset(); + push_n_times(42, 1); + push_n_times(42, 1); + push_n_times(42, 1); + push_n_times(42, 1); + pop_n_times(42, 2); + pop_n_times(42, 2); + check_empty(); +} + +// trace 41 +trace { + reset(); + push_n_times(42, 1); + push_n_times(42, 1); + push_n_times(42, 1); + push_n_times(42, 1); + pop_n_times(42, 2); + pop_n_times(42, 1); + pop_n_times(42, 1); + check_empty(); +} + +// trace 42 +trace { + reset(); + push_n_times(42, 1); + push_n_times(42, 1); + push_n_times(42, 1); + push_n_times(42, 1); + pop_n_times(42, 4); + check_empty(); +} + +// trace 43 +trace { + reset(); + push_n_times(42, 1); + push_n_times(42, 1); + push_n_times(42, 1); + push_n_times(42, 1); + pop_n_times(42, 3); + pop_n_times(42, 1); + check_empty(); +} + +// trace 44 +trace { + reset(); + push_n_times(42, 1); + push_n_times(42, 1); + push_n_times(42, 1); + push_n_times(42, 1); + pop_n_times(42, 1); + pop_n_times(42, 1); + pop_n_times(42, 2); + check_empty(); +} + +// trace 45 +trace { + reset(); + push_n_times(42, 1); + push_n_times(42, 1); + push_n_times(42, 1); + push_n_times(42, 1); + pop_n_times(42, 1); + pop_n_times(42, 1); + pop_n_times(42, 1); + pop_n_times(42, 1); + check_empty(); +} + +// trace 46 +trace { + reset(); + push_n_times(42, 1); + push_n_times(42, 1); + push_n_times(42, 1); + push_n_times(42, 1); + pop_n_times(42, 1); + pop_n_times(42, 3); + check_empty(); +} + +// trace 47 +trace { + reset(); + push_n_times(42, 1); + push_n_times(42, 1); + push_n_times(42, 1); + push_n_times(42, 1); + pop_n_times(42, 1); + pop_n_times(42, 2); + pop_n_times(42, 1); + check_empty(); +} + +// trace 48 +trace { + reset(); + push_n_times(42, 1); + push_n_times(42, 3); + pop_n_times(42, 2); + pop_n_times(42, 2); + check_empty(); +} + +// trace 49 +trace { + reset(); + push_n_times(42, 1); + push_n_times(42, 3); + pop_n_times(42, 2); + pop_n_times(42, 1); + pop_n_times(42, 1); + check_empty(); +} + +// trace 50 +trace { + reset(); + push_n_times(42, 1); + push_n_times(42, 3); + pop_n_times(42, 4); + check_empty(); +} + +// trace 51 +trace { + reset(); + push_n_times(42, 1); + push_n_times(42, 3); + pop_n_times(42, 3); + pop_n_times(42, 1); + check_empty(); +} + +// trace 52 +trace { + reset(); + push_n_times(42, 1); + push_n_times(42, 3); + pop_n_times(42, 1); + pop_n_times(42, 1); + pop_n_times(42, 2); + check_empty(); +} + +// trace 53 +trace { + reset(); + push_n_times(42, 1); + push_n_times(42, 3); + pop_n_times(42, 1); + pop_n_times(42, 1); + pop_n_times(42, 1); + pop_n_times(42, 1); + check_empty(); +} + +// trace 54 +trace { + reset(); + push_n_times(42, 1); + push_n_times(42, 3); + pop_n_times(42, 1); + pop_n_times(42, 3); + check_empty(); +} + +// trace 55 +trace { + reset(); + push_n_times(42, 1); + push_n_times(42, 3); + pop_n_times(42, 1); + pop_n_times(42, 2); + pop_n_times(42, 1); + check_empty(); +} + +// trace 56 +trace { + reset(); + push_n_times(42, 1); + push_n_times(42, 2); + push_n_times(42, 1); + pop_n_times(42, 2); + pop_n_times(42, 2); + check_empty(); +} + +// trace 57 +trace { + reset(); + push_n_times(42, 1); + push_n_times(42, 2); + push_n_times(42, 1); + pop_n_times(42, 2); + pop_n_times(42, 1); + pop_n_times(42, 1); + check_empty(); +} + +// trace 58 +trace { + reset(); + push_n_times(42, 1); + push_n_times(42, 2); + push_n_times(42, 1); + pop_n_times(42, 4); + check_empty(); +} + +// trace 59 +trace { + reset(); + push_n_times(42, 1); + push_n_times(42, 2); + push_n_times(42, 1); + pop_n_times(42, 3); + pop_n_times(42, 1); + check_empty(); +} + +// trace 60 +trace { + reset(); + push_n_times(42, 1); + push_n_times(42, 2); + push_n_times(42, 1); + pop_n_times(42, 1); + pop_n_times(42, 1); + pop_n_times(42, 2); + check_empty(); +} + +// trace 61 +trace { + reset(); + push_n_times(42, 1); + push_n_times(42, 2); + push_n_times(42, 1); + pop_n_times(42, 1); + pop_n_times(42, 1); + pop_n_times(42, 1); + pop_n_times(42, 1); + check_empty(); +} + +// trace 62 +trace { + reset(); + push_n_times(42, 1); + push_n_times(42, 2); + push_n_times(42, 1); + pop_n_times(42, 1); + pop_n_times(42, 3); + check_empty(); +} + +// trace 63 +trace { + reset(); + push_n_times(42, 1); + push_n_times(42, 2); + push_n_times(42, 1); + pop_n_times(42, 1); + pop_n_times(42, 2); + pop_n_times(42, 1); + check_empty(); +} diff --git a/tests/fifo/expects/push_pop_loop_not_empty.bi.expect b/tests/fifo/expects/push_pop_loop_not_empty.bi.expect index 52c71229..a20f3b61 100644 --- a/tests/fifo/expects/push_pop_loop_not_empty.bi.expect +++ b/tests/fifo/expects/push_pop_loop_not_empty.bi.expect @@ -1,4 +1,75 @@ -panicked at bi/src/bi.rs:628:21: -[pop_n_times@00!] Cannot fork at step zero! ----CODE--- -101 +// trace 0 +trace { + reset(); + push_n_times(7, 1); + push_n_times(7, 2); + pop_n_times(7, 2); + check_not_empty(); +} + +// trace 1 +trace { + reset(); + push_n_times(7, 1); + push_n_times(7, 2); + pop_n_times(7, 1); + pop_n_times(7, 1); + check_not_empty(); +} + +// trace 2 +trace { + reset(); + push_n_times(7, 1); + push_n_times(7, 1); + push_n_times(7, 1); + pop_n_times(7, 2); + check_not_empty(); +} + +// trace 3 +trace { + reset(); + push_n_times(7, 1); + push_n_times(7, 1); + push_n_times(7, 1); + pop_n_times(7, 1); + pop_n_times(7, 1); + check_not_empty(); +} + +// trace 4 +trace { + reset(); + push_n_times(7, 3); + pop_n_times(7, 2); + check_not_empty(); +} + +// trace 5 +trace { + reset(); + push_n_times(7, 3); + pop_n_times(7, 1); + pop_n_times(7, 1); + check_not_empty(); +} + +// trace 6 +trace { + reset(); + push_n_times(7, 2); + push_n_times(7, 1); + pop_n_times(7, 2); + check_not_empty(); +} + +// trace 7 +trace { + reset(); + push_n_times(7, 2); + push_n_times(7, 1); + pop_n_times(7, 1); + pop_n_times(7, 1); + check_not_empty(); +} From 3e355fd0bac6ff74007b08bc8cf2358637a7b706 Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sat, 18 Jul 2026 12:28:45 -0400 Subject: [PATCH 27/55] Add --max-traces argument to the nested_busy_wait test case to avoid too many traces from showing up --- runt/bi/runt.toml | 2 +- scripts/test_catalog.py | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/runt/bi/runt.toml b/runt/bi/runt.toml index 2427fd8a..62917ee0 100644 --- a/runt/bi/runt.toml +++ b/runt/bi/runt.toml @@ -52,7 +52,7 @@ paths = [ ] expect_dir = "../../tests/adders/expects" expect_name = "nested_busy_wait.bi.expect" -cmd = "cd ../.. && target/debug/bi --color never --protocol tests/adders/nested_busy_wait.prot --wave tests/adders/nested_busy_wait.fst --instances add_d1:Adder 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/adders/nested_busy_wait.prot --wave tests/adders/nested_busy_wait.fst --instances add_d1:Adder --max-traces 20 2>&1" [[tests]] name = "bi.tests_alus_alu_d1_bi.alu_d1_bi" diff --git a/scripts/test_catalog.py b/scripts/test_catalog.py index 004e5309..24aab7ff 100644 --- a/scripts/test_catalog.py +++ b/scripts/test_catalog.py @@ -538,6 +538,10 @@ "instances": ("add_d1:Adder",), "expect": None, "timeout_secs": 5, + "extra_args": ( + "--max-traces", + "20", + ), }, "tests.alus.alu_d1.bi": { "protocol": "tests/alus/alu_d1.bi.prot", @@ -623,6 +627,7 @@ "instances": ("fifo_wrapper:Fifo",), "expect": None, "timeout_secs": 5, + "extra_args": ("--max-traces", "20"), }, "tests.fifo.push_pop_loop_not_empty": { "protocol": "tests/fifo/push_pop_loop_not_empty.prot", From 571657db8c91994313109dd191ad000c51c9a1c0 Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sat, 18 Jul 2026 15:32:50 -0400 Subject: [PATCH 28/55] Add --max-traces to push_pop_loop_empty test, update Runt expected output --- runt/bi/runt.toml | 2 +- scripts/test_catalog.py | 1 - .../expects/push_pop_loop_empty.bi.expect | 493 +----------------- .../axi-burst-s4/expects/s4_buggy.bi.expect | 11 +- .../axi-lite-s1/expects/s1_buggy.bi.expect | 21 +- .../expects/s1_buggy_workload_1.bi.expect | 45 +- .../expects/s1_fixed_workload_1.bi.expect | 45 +- .../expects/c4_buggy.bi.expect | 31 +- .../axis-fifo-d4/expects/d4_fixed.bi.expect | 11 +- .../identities/expects/identity_d1.bi.expect | 8 +- tests/serv/expects/serv_regfile.bi.expect | 11 +- tests/wal/advanced/expects/axis.bi.expect | 11 +- .../advanced/expects/axis_failing.bi.expect | 11 +- .../advanced/expects/axis_minimal.bi.expect | 11 +- .../advanced/expects/axis_truncated.bi.expect | 11 +- .../axis_truncated_include_idle.bi.expect | 11 +- tests/wb_intercon/expects/wb_cdc.bi.expect | 4 +- 17 files changed, 142 insertions(+), 596 deletions(-) diff --git a/runt/bi/runt.toml b/runt/bi/runt.toml index 62917ee0..999cbe05 100644 --- a/runt/bi/runt.toml +++ b/runt/bi/runt.toml @@ -1204,7 +1204,7 @@ paths = [ ] expect_dir = "../../tests/fifo/expects" expect_name = "push_pop_loop_empty.bi.expect" -cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fifo/push_pop_loop_empty.prot --wave tests/fifo/push_pop_loop_empty.fst --instances fifo_wrapper:Fifo 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fifo/push_pop_loop_empty.prot --wave tests/fifo/push_pop_loop_empty.fst --instances fifo_wrapper:Fifo --max-traces 20 2>&1" [[tests]] name = "bi.tests_fifo_push_pop_loop_not_empty.push_pop_loop_not_empty_bi" diff --git a/scripts/test_catalog.py b/scripts/test_catalog.py index 24aab7ff..daef74d3 100644 --- a/scripts/test_catalog.py +++ b/scripts/test_catalog.py @@ -626,7 +626,6 @@ "wave": "tests/fifo/push_pop_loop_empty.fst", "instances": ("fifo_wrapper:Fifo",), "expect": None, - "timeout_secs": 5, "extra_args": ("--max-traces", "20"), }, "tests.fifo.push_pop_loop_not_empty": { diff --git a/tests/fifo/expects/push_pop_loop_empty.bi.expect b/tests/fifo/expects/push_pop_loop_empty.bi.expect index 248a01e1..eb5f72bb 100644 --- a/tests/fifo/expects/push_pop_loop_empty.bi.expect +++ b/tests/fifo/expects/push_pop_loop_empty.bi.expect @@ -209,495 +209,4 @@ trace { pop_n_times(42, 1); check_empty(); } - -// trace 20 -trace { - reset(); - push_n_times(42, 4); - pop_n_times(42, 1); - pop_n_times(42, 1); - pop_n_times(42, 2); - check_empty(); -} - -// trace 21 -trace { - reset(); - push_n_times(42, 4); - pop_n_times(42, 1); - pop_n_times(42, 1); - pop_n_times(42, 1); - pop_n_times(42, 1); - check_empty(); -} - -// trace 22 -trace { - reset(); - push_n_times(42, 4); - pop_n_times(42, 1); - pop_n_times(42, 3); - check_empty(); -} - -// trace 23 -trace { - reset(); - push_n_times(42, 4); - pop_n_times(42, 1); - pop_n_times(42, 2); - pop_n_times(42, 1); - check_empty(); -} - -// trace 24 -trace { - reset(); - push_n_times(42, 3); - push_n_times(42, 1); - pop_n_times(42, 2); - pop_n_times(42, 2); - check_empty(); -} - -// trace 25 -trace { - reset(); - push_n_times(42, 3); - push_n_times(42, 1); - pop_n_times(42, 2); - pop_n_times(42, 1); - pop_n_times(42, 1); - check_empty(); -} - -// trace 26 -trace { - reset(); - push_n_times(42, 3); - push_n_times(42, 1); - pop_n_times(42, 4); - check_empty(); -} - -// trace 27 -trace { - reset(); - push_n_times(42, 3); - push_n_times(42, 1); - pop_n_times(42, 3); - pop_n_times(42, 1); - check_empty(); -} - -// trace 28 -trace { - reset(); - push_n_times(42, 3); - push_n_times(42, 1); - pop_n_times(42, 1); - pop_n_times(42, 1); - pop_n_times(42, 2); - check_empty(); -} - -// trace 29 -trace { - reset(); - push_n_times(42, 3); - push_n_times(42, 1); - pop_n_times(42, 1); - pop_n_times(42, 1); - pop_n_times(42, 1); - pop_n_times(42, 1); - check_empty(); -} - -// trace 30 -trace { - reset(); - push_n_times(42, 3); - push_n_times(42, 1); - pop_n_times(42, 1); - pop_n_times(42, 3); - check_empty(); -} - -// trace 31 -trace { - reset(); - push_n_times(42, 3); - push_n_times(42, 1); - pop_n_times(42, 1); - pop_n_times(42, 2); - pop_n_times(42, 1); - check_empty(); -} - -// trace 32 -trace { - reset(); - push_n_times(42, 1); - push_n_times(42, 1); - push_n_times(42, 2); - pop_n_times(42, 2); - pop_n_times(42, 2); - check_empty(); -} - -// trace 33 -trace { - reset(); - push_n_times(42, 1); - push_n_times(42, 1); - push_n_times(42, 2); - pop_n_times(42, 2); - pop_n_times(42, 1); - pop_n_times(42, 1); - check_empty(); -} - -// trace 34 -trace { - reset(); - push_n_times(42, 1); - push_n_times(42, 1); - push_n_times(42, 2); - pop_n_times(42, 4); - check_empty(); -} - -// trace 35 -trace { - reset(); - push_n_times(42, 1); - push_n_times(42, 1); - push_n_times(42, 2); - pop_n_times(42, 3); - pop_n_times(42, 1); - check_empty(); -} - -// trace 36 -trace { - reset(); - push_n_times(42, 1); - push_n_times(42, 1); - push_n_times(42, 2); - pop_n_times(42, 1); - pop_n_times(42, 1); - pop_n_times(42, 2); - check_empty(); -} - -// trace 37 -trace { - reset(); - push_n_times(42, 1); - push_n_times(42, 1); - push_n_times(42, 2); - pop_n_times(42, 1); - pop_n_times(42, 1); - pop_n_times(42, 1); - pop_n_times(42, 1); - check_empty(); -} - -// trace 38 -trace { - reset(); - push_n_times(42, 1); - push_n_times(42, 1); - push_n_times(42, 2); - pop_n_times(42, 1); - pop_n_times(42, 3); - check_empty(); -} - -// trace 39 -trace { - reset(); - push_n_times(42, 1); - push_n_times(42, 1); - push_n_times(42, 2); - pop_n_times(42, 1); - pop_n_times(42, 2); - pop_n_times(42, 1); - check_empty(); -} - -// trace 40 -trace { - reset(); - push_n_times(42, 1); - push_n_times(42, 1); - push_n_times(42, 1); - push_n_times(42, 1); - pop_n_times(42, 2); - pop_n_times(42, 2); - check_empty(); -} - -// trace 41 -trace { - reset(); - push_n_times(42, 1); - push_n_times(42, 1); - push_n_times(42, 1); - push_n_times(42, 1); - pop_n_times(42, 2); - pop_n_times(42, 1); - pop_n_times(42, 1); - check_empty(); -} - -// trace 42 -trace { - reset(); - push_n_times(42, 1); - push_n_times(42, 1); - push_n_times(42, 1); - push_n_times(42, 1); - pop_n_times(42, 4); - check_empty(); -} - -// trace 43 -trace { - reset(); - push_n_times(42, 1); - push_n_times(42, 1); - push_n_times(42, 1); - push_n_times(42, 1); - pop_n_times(42, 3); - pop_n_times(42, 1); - check_empty(); -} - -// trace 44 -trace { - reset(); - push_n_times(42, 1); - push_n_times(42, 1); - push_n_times(42, 1); - push_n_times(42, 1); - pop_n_times(42, 1); - pop_n_times(42, 1); - pop_n_times(42, 2); - check_empty(); -} - -// trace 45 -trace { - reset(); - push_n_times(42, 1); - push_n_times(42, 1); - push_n_times(42, 1); - push_n_times(42, 1); - pop_n_times(42, 1); - pop_n_times(42, 1); - pop_n_times(42, 1); - pop_n_times(42, 1); - check_empty(); -} - -// trace 46 -trace { - reset(); - push_n_times(42, 1); - push_n_times(42, 1); - push_n_times(42, 1); - push_n_times(42, 1); - pop_n_times(42, 1); - pop_n_times(42, 3); - check_empty(); -} - -// trace 47 -trace { - reset(); - push_n_times(42, 1); - push_n_times(42, 1); - push_n_times(42, 1); - push_n_times(42, 1); - pop_n_times(42, 1); - pop_n_times(42, 2); - pop_n_times(42, 1); - check_empty(); -} - -// trace 48 -trace { - reset(); - push_n_times(42, 1); - push_n_times(42, 3); - pop_n_times(42, 2); - pop_n_times(42, 2); - check_empty(); -} - -// trace 49 -trace { - reset(); - push_n_times(42, 1); - push_n_times(42, 3); - pop_n_times(42, 2); - pop_n_times(42, 1); - pop_n_times(42, 1); - check_empty(); -} - -// trace 50 -trace { - reset(); - push_n_times(42, 1); - push_n_times(42, 3); - pop_n_times(42, 4); - check_empty(); -} - -// trace 51 -trace { - reset(); - push_n_times(42, 1); - push_n_times(42, 3); - pop_n_times(42, 3); - pop_n_times(42, 1); - check_empty(); -} - -// trace 52 -trace { - reset(); - push_n_times(42, 1); - push_n_times(42, 3); - pop_n_times(42, 1); - pop_n_times(42, 1); - pop_n_times(42, 2); - check_empty(); -} - -// trace 53 -trace { - reset(); - push_n_times(42, 1); - push_n_times(42, 3); - pop_n_times(42, 1); - pop_n_times(42, 1); - pop_n_times(42, 1); - pop_n_times(42, 1); - check_empty(); -} - -// trace 54 -trace { - reset(); - push_n_times(42, 1); - push_n_times(42, 3); - pop_n_times(42, 1); - pop_n_times(42, 3); - check_empty(); -} - -// trace 55 -trace { - reset(); - push_n_times(42, 1); - push_n_times(42, 3); - pop_n_times(42, 1); - pop_n_times(42, 2); - pop_n_times(42, 1); - check_empty(); -} - -// trace 56 -trace { - reset(); - push_n_times(42, 1); - push_n_times(42, 2); - push_n_times(42, 1); - pop_n_times(42, 2); - pop_n_times(42, 2); - check_empty(); -} - -// trace 57 -trace { - reset(); - push_n_times(42, 1); - push_n_times(42, 2); - push_n_times(42, 1); - pop_n_times(42, 2); - pop_n_times(42, 1); - pop_n_times(42, 1); - check_empty(); -} - -// trace 58 -trace { - reset(); - push_n_times(42, 1); - push_n_times(42, 2); - push_n_times(42, 1); - pop_n_times(42, 4); - check_empty(); -} - -// trace 59 -trace { - reset(); - push_n_times(42, 1); - push_n_times(42, 2); - push_n_times(42, 1); - pop_n_times(42, 3); - pop_n_times(42, 1); - check_empty(); -} - -// trace 60 -trace { - reset(); - push_n_times(42, 1); - push_n_times(42, 2); - push_n_times(42, 1); - pop_n_times(42, 1); - pop_n_times(42, 1); - pop_n_times(42, 2); - check_empty(); -} - -// trace 61 -trace { - reset(); - push_n_times(42, 1); - push_n_times(42, 2); - push_n_times(42, 1); - pop_n_times(42, 1); - pop_n_times(42, 1); - pop_n_times(42, 1); - pop_n_times(42, 1); - check_empty(); -} - -// trace 62 -trace { - reset(); - push_n_times(42, 1); - push_n_times(42, 2); - push_n_times(42, 1); - pop_n_times(42, 1); - pop_n_times(42, 3); - check_empty(); -} - -// trace 63 -trace { - reset(); - push_n_times(42, 1); - push_n_times(42, 2); - push_n_times(42, 1); - pop_n_times(42, 1); - pop_n_times(42, 2); - pop_n_times(42, 1); - check_empty(); -} +Displayed 20/64 traces. diff --git a/tests/fpga-debugging/axi-burst-s4/expects/s4_buggy.bi.expect b/tests/fpga-debugging/axi-burst-s4/expects/s4_buggy.bi.expect index b3c96b02..f9d89335 100644 --- a/tests/fpga-debugging/axi-burst-s4/expects/s4_buggy.bi.expect +++ b/tests/fpga-debugging/axi-burst-s4/expects/s4_buggy.bi.expect @@ -1,12 +1,11 @@ // trace 0 trace { } -error: [write_burst@95] executing step 67 of the transaction: 0 != 1 - ┌─ tests/fpga-debugging/axi-burst-s4/s4_buggy.prot:63:5 - │ -63 │ DUT.m_wlast := 1'b1; - │ ^^^^^^^^^^^^^^^^^^^^ [write_burst@95] executing step 67 of the transaction: 0 != 1 +error: [write_burst@95] executing step 67 of the transaction: 0 != 1 + ┌─ tests/fpga-debugging/axi-burst-s4/s4_buggy.prot:63:5 + │ +63 │ DUT.m_wlast := 1'b1; + │ ^^^^^^^^^^^^^^^^^^^^ [write_burst@95] executing step 67 of the transaction: 0 != 1 -Error: "Monitor failed" ---CODE--- 1 diff --git a/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy.bi.expect b/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy.bi.expect index 523bbb01..9d2dd36b 100644 --- a/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy.bi.expect +++ b/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy.bi.expect @@ -7,23 +7,22 @@ trace { trace { idle(); // [time: 0ns -> 25ns] } -error: [read_v2@11?1!] executing step 3 of the transaction: 1 != 0 - ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy.prot:169:5 - │ -169 │ assert_eq(DUT.S_AXI_ARREADY, 1'b0); - │ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@11?1!] executing step 3 of the transaction: 1 != 0 +error: [read_v2@11?1!] executing step 3 of the transaction: 1 != 0 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy.prot:169:5 + │ +169 │ assert_eq(DUT.S_AXI_ARREADY, 1'b0); + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@11?1!] executing step 3 of the transaction: 1 != 0 // trace 1 trace { idle(); // [time: 0ns -> 25ns] } -error: [read_v2@11?2?] executing step 3 of the transaction: 1 != 0 - ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy.prot:163:9 - │ -163 │ DUT.S_AXI_RREADY := 1'b0; - │ ^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@11?2?] executing step 3 of the transaction: 1 != 0 +error: [read_v2@11?2?] executing step 3 of the transaction: 1 != 0 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy.prot:163:9 + │ +163 │ DUT.S_AXI_RREADY := 1'b0; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@11?2?] executing step 3 of the transaction: 1 != 0 -Error: "Monitor failed" ---CODE--- 1 diff --git a/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy_workload_1.bi.expect b/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy_workload_1.bi.expect index 58ee712c..772fe72d 100644 --- a/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy_workload_1.bi.expect +++ b/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy_workload_1.bi.expect @@ -15,11 +15,11 @@ trace { idle(); // [time: 0ns -> 25ns] read_v1(64, 0); // [time: 25ns -> 100ns] } -error: [read_v2@4] executing step 0 of the transaction: 0 != 1 - ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot:161:5 - │ -161 │ DUT.S_AXI_ARVALID := 1'b1; - │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@4] executing step 0 of the transaction: 0 != 1 +error: [read_v2@4] executing step 0 of the transaction: 0 != 1 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot:161:5 + │ +161 │ DUT.S_AXI_ARVALID := 1'b1; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@4] executing step 0 of the transaction: 0 != 1 // trace 1 @@ -27,17 +27,23 @@ trace { idle(); // [time: 0ns -> 25ns] read_v1(64, 0); // [time: 25ns -> 100ns] } +error: [read_v1@4] executing step 0 of the transaction: 0 != 1 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot:124:5 + │ +124 │ DUT.S_AXI_ARVALID := 1'b1; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v1@4] executing step 0 of the transaction: 0 != 1 + // trace 2 trace { idle(); // [time: 0ns -> 25ns] read_v1(64, 0); // [time: 25ns -> 100ns] } -error: [idle@4] executing step 0 of the transaction: 1 != 0 - ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot:108:5 - │ -108 │ DUT.S_AXI_RREADY := 1'b0; - │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [idle@4] executing step 0 of the transaction: 1 != 0 +error: [idle@4] executing step 0 of the transaction: 1 != 0 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot:108:5 + │ +108 │ DUT.S_AXI_RREADY := 1'b0; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [idle@4] executing step 0 of the transaction: 1 != 0 // trace 3 @@ -45,18 +51,35 @@ trace { idle(); // [time: 0ns -> 25ns] read_v2(64, 0, 0); // [time: 25ns -> 100ns] } +error: [read_v2@4] executing step 0 of the transaction: 0 != 1 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot:161:5 + │ +161 │ DUT.S_AXI_ARVALID := 1'b1; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@4] executing step 0 of the transaction: 0 != 1 + // trace 4 trace { idle(); // [time: 0ns -> 25ns] read_v2(64, 0, 0); // [time: 25ns -> 100ns] } +error: [read_v1@4] executing step 0 of the transaction: 0 != 1 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot:124:5 + │ +124 │ DUT.S_AXI_ARVALID := 1'b1; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v1@4] executing step 0 of the transaction: 0 != 1 + // trace 5 trace { idle(); // [time: 0ns -> 25ns] read_v2(64, 0, 0); // [time: 25ns -> 100ns] } -Error: "Monitor failed" +error: [idle@4] executing step 0 of the transaction: 1 != 0 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot:108:5 + │ +108 │ DUT.S_AXI_RREADY := 1'b0; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [idle@4] executing step 0 of the transaction: 1 != 0 + ---CODE--- 1 diff --git a/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed_workload_1.bi.expect b/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed_workload_1.bi.expect index 5d803553..da9923a9 100644 --- a/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed_workload_1.bi.expect +++ b/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed_workload_1.bi.expect @@ -7,11 +7,11 @@ trace { idle(); // [time: 0ns -> 25ns] read_v1(64, 0); // [time: 25ns -> 100ns] } -error: [read_v2@4] executing step 0 of the transaction: 0 != 1 - ┌─ tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot:161:5 - │ -161 │ DUT.S_AXI_ARVALID := 1'b1; - │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@4] executing step 0 of the transaction: 0 != 1 +error: [read_v2@4] executing step 0 of the transaction: 0 != 1 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot:161:5 + │ +161 │ DUT.S_AXI_ARVALID := 1'b1; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@4] executing step 0 of the transaction: 0 != 1 // trace 1 @@ -19,17 +19,23 @@ trace { idle(); // [time: 0ns -> 25ns] read_v1(64, 0); // [time: 25ns -> 100ns] } +error: [read_v1@4] executing step 0 of the transaction: 0 != 1 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot:124:5 + │ +124 │ DUT.S_AXI_ARVALID := 1'b1; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v1@4] executing step 0 of the transaction: 0 != 1 + // trace 2 trace { idle(); // [time: 0ns -> 25ns] read_v1(64, 0); // [time: 25ns -> 100ns] } -error: [idle@4] executing step 0 of the transaction: 1 != 0 - ┌─ tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot:108:5 - │ -108 │ DUT.S_AXI_RREADY := 1'b0; - │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [idle@4] executing step 0 of the transaction: 1 != 0 +error: [idle@4] executing step 0 of the transaction: 1 != 0 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot:108:5 + │ +108 │ DUT.S_AXI_RREADY := 1'b0; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [idle@4] executing step 0 of the transaction: 1 != 0 // trace 3 @@ -37,18 +43,35 @@ trace { idle(); // [time: 0ns -> 25ns] read_v2(64, 0, 0); // [time: 25ns -> 100ns] } +error: [read_v2@4] executing step 0 of the transaction: 0 != 1 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot:161:5 + │ +161 │ DUT.S_AXI_ARVALID := 1'b1; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@4] executing step 0 of the transaction: 0 != 1 + // trace 4 trace { idle(); // [time: 0ns -> 25ns] read_v2(64, 0, 0); // [time: 25ns -> 100ns] } +error: [read_v1@4] executing step 0 of the transaction: 0 != 1 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot:124:5 + │ +124 │ DUT.S_AXI_ARVALID := 1'b1; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v1@4] executing step 0 of the transaction: 0 != 1 + // trace 5 trace { idle(); // [time: 0ns -> 25ns] read_v2(64, 0, 0); // [time: 25ns -> 100ns] } -Error: "Monitor failed" +error: [idle@4] executing step 0 of the transaction: 1 != 0 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot:108:5 + │ +108 │ DUT.S_AXI_RREADY := 1'b0; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [idle@4] executing step 0 of the transaction: 1 != 0 + ---CODE--- 1 diff --git a/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.bi.expect b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.bi.expect index 3e619433..0e48f520 100644 --- a/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.bi.expect +++ b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.bi.expect @@ -14,34 +14,33 @@ trace { trace { reset(); // [time: 0ns -> 25ns] } -error: [reset@1] executing step 0 of the transaction: 0 != 1 - ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot:115:5 - │ -115 │ DUT.rst := 1'b1; - │ ^^^^^^^^^^^^^^^^ [reset@1] executing step 0 of the transaction: 0 != 1 +error: [reset@1] executing step 0 of the transaction: 0 != 1 + ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot:115:5 + │ +115 │ DUT.rst := 1'b1; + │ ^^^^^^^^^^^^^^^^ [reset@1] executing step 0 of the transaction: 0 != 1 // trace 1 trace { reset(); // [time: 0ns -> 25ns] } -error: [idle@1] executing step 0 of the transaction: 1 != 0 - ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot:97:5 - │ -97 │ DUT.m_axis_tready := 1'b0; - │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [idle@1] executing step 0 of the transaction: 1 != 0 +error: [idle@1] executing step 0 of the transaction: 1 != 0 + ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot:97:5 + │ +97 │ DUT.m_axis_tready := 1'b0; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [idle@1] executing step 0 of the transaction: 1 != 0 // trace 2 trace { reset(); // [time: 0ns -> 25ns] } -error: [pop@1] executing step 0 of the transaction: 0 != 1 - ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot:62:5 - │ -62 │ assert_eq(DUT.m_axis_tvalid, 1'b1); - │ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ [pop@1] executing step 0 of the transaction: 0 != 1 +error: [pop@1] executing step 0 of the transaction: 0 != 1 + ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot:62:5 + │ +62 │ assert_eq(DUT.m_axis_tvalid, 1'b1); + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ [pop@1] executing step 0 of the transaction: 0 != 1 -Error: "Monitor failed" ---CODE--- 1 diff --git a/tests/fpga-debugging/axis-fifo-d4/expects/d4_fixed.bi.expect b/tests/fpga-debugging/axis-fifo-d4/expects/d4_fixed.bi.expect index f831c600..26e27800 100644 --- a/tests/fpga-debugging/axis-fifo-d4/expects/d4_fixed.bi.expect +++ b/tests/fpga-debugging/axis-fifo-d4/expects/d4_fixed.bi.expect @@ -44,12 +44,11 @@ trace { push(9); // [time: 140ns -> 142.5ns] push(233); // [time: 142.5ns -> 145ns] } -error: [push@63] executing step 1 of the transaction: 01 != 00 - ┌─ tests/fpga-debugging/axis-fifo-d4/d4_fixed.prot:89:5 - │ -89 │ DUT.s_axis_tdata := data; - │ ^^^^^^^^^^^^^^^^^^^^^^^^^ [push@63] executing step 1 of the transaction: 01 != 00 +error: [push@63] executing step 1 of the transaction: 01 != 00 + ┌─ tests/fpga-debugging/axis-fifo-d4/d4_fixed.prot:89:5 + │ +89 │ DUT.s_axis_tdata := data; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^ [push@63] executing step 1 of the transaction: 01 != 00 -Error: "Monitor failed" ---CODE--- 1 diff --git a/tests/identities/expects/identity_d1.bi.expect b/tests/identities/expects/identity_d1.bi.expect index 4b88a61a..86f06504 100644 --- a/tests/identities/expects/identity_d1.bi.expect +++ b/tests/identities/expects/identity_d1.bi.expect @@ -1,4 +1,4 @@ -panicked at bi/src/bi.rs:739:29: -not yet implemented: we currently expect one side of an assert_eq to be a port! ----CODE--- -101 +// trace 0 +trace { + slicing_ok(1, X); +} diff --git a/tests/serv/expects/serv_regfile.bi.expect b/tests/serv/expects/serv_regfile.bi.expect index a5b7ee4e..92f93316 100644 --- a/tests/serv/expects/serv_regfile.bi.expect +++ b/tests/serv/expects/serv_regfile.bi.expect @@ -1,6 +1,5 @@ -panicked at bi/src/constraints.rs:120:9: -assertion `left == right` failed - left: 32 - right: 1 ----CODE--- -101 +// trace 0 +trace { + read_write(0x00, 0x00000000, 0x00000000, 0x00, 0x1, 0x05, 0xdeadbeef); + read_write(0x05, 0xdeadbeef, 0x00000000, 0x00, 0x0, 0x00, 0x00000000); +} diff --git a/tests/wal/advanced/expects/axis.bi.expect b/tests/wal/advanced/expects/axis.bi.expect index 4a0b2a39..5892adbe 100644 --- a/tests/wal/advanced/expects/axis.bi.expect +++ b/tests/wal/advanced/expects/axis.bi.expect @@ -5,12 +5,11 @@ trace { send_data(2); // [time: 2212ns -> 2220ns] send_data(3); // [time: 2916ns -> 2924ns] } -error: [send_data@453] executing step 88 of the transaction: 05 != 04 - ┌─ tests/wal/advanced/axis.prot:10:5 - │ -10 │ D.m_axis_tdata := data; - │ ^^^^^^^^^^^^^^^^^^^^^^^ [send_data@453] executing step 88 of the transaction: 05 != 04 +error: [send_data@453] executing step 88 of the transaction: 05 != 04 + ┌─ tests/wal/advanced/axis.prot:10:5 + │ +10 │ D.m_axis_tdata := data; + │ ^^^^^^^^^^^^^^^^^^^^^^^ [send_data@453] executing step 88 of the transaction: 05 != 04 -Error: "Monitor failed" ---CODE--- 1 diff --git a/tests/wal/advanced/expects/axis_failing.bi.expect b/tests/wal/advanced/expects/axis_failing.bi.expect index 313a163a..9fae4547 100644 --- a/tests/wal/advanced/expects/axis_failing.bi.expect +++ b/tests/wal/advanced/expects/axis_failing.bi.expect @@ -1,12 +1,11 @@ // trace 0 trace { } -error: [idle@0] executing step 0 of the transaction: 1 != 0 - ┌─ tests/wal/advanced/axis_failing.prot:11:5 - │ -11 │ D.m_axis_tvalid := 1'b0; - │ ^^^^^^^^^^^^^^^^^^^^^^^^ [idle@0] executing step 0 of the transaction: 1 != 0 +error: [idle@0] executing step 0 of the transaction: 1 != 0 + ┌─ tests/wal/advanced/axis_failing.prot:11:5 + │ +11 │ D.m_axis_tvalid := 1'b0; + │ ^^^^^^^^^^^^^^^^^^^^^^^^ [idle@0] executing step 0 of the transaction: 1 != 0 -Error: "Monitor failed" ---CODE--- 1 diff --git a/tests/wal/advanced/expects/axis_minimal.bi.expect b/tests/wal/advanced/expects/axis_minimal.bi.expect index 8570d0a2..2523a8a7 100644 --- a/tests/wal/advanced/expects/axis_minimal.bi.expect +++ b/tests/wal/advanced/expects/axis_minimal.bi.expect @@ -1,12 +1,11 @@ // trace 0 trace { } -error: [send_data@0] executing step 3 of the transaction: 0f != 14 - ┌─ tests/wal/advanced/axis_minimal.prot:10:5 - │ -10 │ D.m_axis_tdata := data; - │ ^^^^^^^^^^^^^^^^^^^^^^^ [send_data@0] executing step 3 of the transaction: 0f != 14 +error: [send_data@0] executing step 3 of the transaction: 0f != 14 + ┌─ tests/wal/advanced/axis_minimal.prot:10:5 + │ +10 │ D.m_axis_tdata := data; + │ ^^^^^^^^^^^^^^^^^^^^^^^ [send_data@0] executing step 3 of the transaction: 0f != 14 -Error: "Monitor failed" ---CODE--- 1 diff --git a/tests/wal/advanced/expects/axis_truncated.bi.expect b/tests/wal/advanced/expects/axis_truncated.bi.expect index e11c9fe8..79980854 100644 --- a/tests/wal/advanced/expects/axis_truncated.bi.expect +++ b/tests/wal/advanced/expects/axis_truncated.bi.expect @@ -1,12 +1,11 @@ // trace 0 trace { } -error: [send_data@0] executing step 88 of the transaction: 0f != 0e - ┌─ tests/wal/advanced/axis_truncated.prot:10:5 - │ -10 │ D.m_axis_tdata := data; - │ ^^^^^^^^^^^^^^^^^^^^^^^ [send_data@0] executing step 88 of the transaction: 0f != 0e +error: [send_data@0] executing step 88 of the transaction: 0f != 0e + ┌─ tests/wal/advanced/axis_truncated.prot:10:5 + │ +10 │ D.m_axis_tdata := data; + │ ^^^^^^^^^^^^^^^^^^^^^^^ [send_data@0] executing step 88 of the transaction: 0f != 0e -Error: "Monitor failed" ---CODE--- 1 diff --git a/tests/wal/advanced/expects/axis_truncated_include_idle.bi.expect b/tests/wal/advanced/expects/axis_truncated_include_idle.bi.expect index a9f16426..142e3ed2 100644 --- a/tests/wal/advanced/expects/axis_truncated_include_idle.bi.expect +++ b/tests/wal/advanced/expects/axis_truncated_include_idle.bi.expect @@ -1,12 +1,11 @@ // trace 0 trace { } -error: [send_data@0] executing step 88 of the transaction: 0f != 0e - ┌─ tests/wal/advanced/axis_truncated_include_idle.prot:11:5 - │ -11 │ D.m_axis_tdata := data; - │ ^^^^^^^^^^^^^^^^^^^^^^^ [send_data@0] executing step 88 of the transaction: 0f != 0e +error: [send_data@0] executing step 88 of the transaction: 0f != 0e + ┌─ tests/wal/advanced/axis_truncated_include_idle.prot:11:5 + │ +11 │ D.m_axis_tdata := data; + │ ^^^^^^^^^^^^^^^^^^^^^^^ [send_data@0] executing step 88 of the transaction: 0f != 0e -Error: "Monitor failed" ---CODE--- 1 diff --git a/tests/wb_intercon/expects/wb_cdc.bi.expect b/tests/wb_intercon/expects/wb_cdc.bi.expect index 8e5b9c2f..c3f3adc3 100644 --- a/tests/wb_intercon/expects/wb_cdc.bi.expect +++ b/tests/wb_intercon/expects/wb_cdc.bi.expect @@ -1,6 +1,8 @@ -panicked at bi/src/main.rs:106:9: + +thread 'main' (2101252) panicked at bi/src/main.rs:117:9: assertion `left == right` failed: Only nano seconds are supported left: "s" right: "ns" +note: run with `RUST_BACKTRACE=1` environment variable to display a backtrace ---CODE--- 101 From b3c5f40e57094c442cba11952ceeb4a7eed171a5 Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sat, 18 Jul 2026 15:37:17 -0400 Subject: [PATCH 29/55] Propagate --color CLI flag to diagnostic handler --- bi/src/main.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bi/src/main.rs b/bi/src/main.rs index db59353b..e2944e2d 100644 --- a/bi/src/main.rs +++ b/bi/src/main.rs @@ -120,7 +120,7 @@ fn main() { // parse protocol file let show_warnings = false; let skip_static_step_fork_checks = false; - let mut d = DiagnosticHandler::new(ColorChoice::Auto, false, show_warnings, false); + let mut d = DiagnosticHandler::new(cli.color, false, show_warnings, false); let (st, modules) = frontend(&cli.protocol, &mut d, skip_static_step_fork_checks).unwrap(); let posedge_clock = get_clock(&modules, cli.sample_posedge); From 7cb79839ddccac6865bf93b557ffe1b73650b338 Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sat, 18 Jul 2026 15:43:26 -0400 Subject: [PATCH 30/55] Update Runt expect files (error messages no longer contain color) --- .../axi-burst-s4/expects/s4_buggy.bi.expect | 10 ++-- .../axi-lite-s1/expects/s1_buggy.bi.expect | 20 +++---- .../expects/s1_buggy_workload_1.bi.expect | 60 +++++++++---------- .../expects/s1_fixed_workload_1.bi.expect | 60 +++++++++---------- .../expects/c4_buggy.bi.expect | 30 +++++----- .../axis-fifo-d4/expects/d4_fixed.bi.expect | 10 ++-- tests/wal/advanced/expects/axis.bi.expect | 10 ++-- .../advanced/expects/axis_failing.bi.expect | 10 ++-- .../advanced/expects/axis_minimal.bi.expect | 10 ++-- .../advanced/expects/axis_truncated.bi.expect | 10 ++-- .../axis_truncated_include_idle.bi.expect | 10 ++-- 11 files changed, 120 insertions(+), 120 deletions(-) diff --git a/tests/fpga-debugging/axi-burst-s4/expects/s4_buggy.bi.expect b/tests/fpga-debugging/axi-burst-s4/expects/s4_buggy.bi.expect index f9d89335..67a3c6de 100644 --- a/tests/fpga-debugging/axi-burst-s4/expects/s4_buggy.bi.expect +++ b/tests/fpga-debugging/axi-burst-s4/expects/s4_buggy.bi.expect @@ -1,11 +1,11 @@ // trace 0 trace { } -error: [write_burst@95] executing step 67 of the transaction: 0 != 1 - ┌─ tests/fpga-debugging/axi-burst-s4/s4_buggy.prot:63:5 - │ -63 │ DUT.m_wlast := 1'b1; - │ ^^^^^^^^^^^^^^^^^^^^ [write_burst@95] executing step 67 of the transaction: 0 != 1 +error: [write_burst@95] executing step 67 of the transaction: 0 != 1 + ┌─ tests/fpga-debugging/axi-burst-s4/s4_buggy.prot:63:5 + │ +63 │ DUT.m_wlast := 1'b1; + │ ^^^^^^^^^^^^^^^^^^^^ [write_burst@95] executing step 67 of the transaction: 0 != 1 ---CODE--- 1 diff --git a/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy.bi.expect b/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy.bi.expect index 9d2dd36b..3b9d8bbd 100644 --- a/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy.bi.expect +++ b/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy.bi.expect @@ -7,22 +7,22 @@ trace { trace { idle(); // [time: 0ns -> 25ns] } -error: [read_v2@11?1!] executing step 3 of the transaction: 1 != 0 - ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy.prot:169:5 - │ -169 │ assert_eq(DUT.S_AXI_ARREADY, 1'b0); - │ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@11?1!] executing step 3 of the transaction: 1 != 0 +error: [read_v2@11?1!] executing step 3 of the transaction: 1 != 0 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy.prot:169:5 + │ +169 │ assert_eq(DUT.S_AXI_ARREADY, 1'b0); + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@11?1!] executing step 3 of the transaction: 1 != 0 // trace 1 trace { idle(); // [time: 0ns -> 25ns] } -error: [read_v2@11?2?] executing step 3 of the transaction: 1 != 0 - ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy.prot:163:9 - │ -163 │ DUT.S_AXI_RREADY := 1'b0; - │ ^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@11?2?] executing step 3 of the transaction: 1 != 0 +error: [read_v2@11?2?] executing step 3 of the transaction: 1 != 0 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy.prot:163:9 + │ +163 │ DUT.S_AXI_RREADY := 1'b0; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@11?2?] executing step 3 of the transaction: 1 != 0 ---CODE--- 1 diff --git a/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy_workload_1.bi.expect b/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy_workload_1.bi.expect index 772fe72d..f3ec1c05 100644 --- a/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy_workload_1.bi.expect +++ b/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy_workload_1.bi.expect @@ -15,11 +15,11 @@ trace { idle(); // [time: 0ns -> 25ns] read_v1(64, 0); // [time: 25ns -> 100ns] } -error: [read_v2@4] executing step 0 of the transaction: 0 != 1 - ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot:161:5 - │ -161 │ DUT.S_AXI_ARVALID := 1'b1; - │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@4] executing step 0 of the transaction: 0 != 1 +error: [read_v2@4] executing step 0 of the transaction: 0 != 1 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot:161:5 + │ +161 │ DUT.S_AXI_ARVALID := 1'b1; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@4] executing step 0 of the transaction: 0 != 1 // trace 1 @@ -27,11 +27,11 @@ trace { idle(); // [time: 0ns -> 25ns] read_v1(64, 0); // [time: 25ns -> 100ns] } -error: [read_v1@4] executing step 0 of the transaction: 0 != 1 - ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot:124:5 - │ -124 │ DUT.S_AXI_ARVALID := 1'b1; - │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v1@4] executing step 0 of the transaction: 0 != 1 +error: [read_v1@4] executing step 0 of the transaction: 0 != 1 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot:124:5 + │ +124 │ DUT.S_AXI_ARVALID := 1'b1; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v1@4] executing step 0 of the transaction: 0 != 1 // trace 2 @@ -39,11 +39,11 @@ trace { idle(); // [time: 0ns -> 25ns] read_v1(64, 0); // [time: 25ns -> 100ns] } -error: [idle@4] executing step 0 of the transaction: 1 != 0 - ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot:108:5 - │ -108 │ DUT.S_AXI_RREADY := 1'b0; - │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [idle@4] executing step 0 of the transaction: 1 != 0 +error: [idle@4] executing step 0 of the transaction: 1 != 0 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot:108:5 + │ +108 │ DUT.S_AXI_RREADY := 1'b0; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [idle@4] executing step 0 of the transaction: 1 != 0 // trace 3 @@ -51,11 +51,11 @@ trace { idle(); // [time: 0ns -> 25ns] read_v2(64, 0, 0); // [time: 25ns -> 100ns] } -error: [read_v2@4] executing step 0 of the transaction: 0 != 1 - ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot:161:5 - │ -161 │ DUT.S_AXI_ARVALID := 1'b1; - │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@4] executing step 0 of the transaction: 0 != 1 +error: [read_v2@4] executing step 0 of the transaction: 0 != 1 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot:161:5 + │ +161 │ DUT.S_AXI_ARVALID := 1'b1; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@4] executing step 0 of the transaction: 0 != 1 // trace 4 @@ -63,11 +63,11 @@ trace { idle(); // [time: 0ns -> 25ns] read_v2(64, 0, 0); // [time: 25ns -> 100ns] } -error: [read_v1@4] executing step 0 of the transaction: 0 != 1 - ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot:124:5 - │ -124 │ DUT.S_AXI_ARVALID := 1'b1; - │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v1@4] executing step 0 of the transaction: 0 != 1 +error: [read_v1@4] executing step 0 of the transaction: 0 != 1 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot:124:5 + │ +124 │ DUT.S_AXI_ARVALID := 1'b1; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v1@4] executing step 0 of the transaction: 0 != 1 // trace 5 @@ -75,11 +75,11 @@ trace { idle(); // [time: 0ns -> 25ns] read_v2(64, 0, 0); // [time: 25ns -> 100ns] } -error: [idle@4] executing step 0 of the transaction: 1 != 0 - ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot:108:5 - │ -108 │ DUT.S_AXI_RREADY := 1'b0; - │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [idle@4] executing step 0 of the transaction: 1 != 0 +error: [idle@4] executing step 0 of the transaction: 1 != 0 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot:108:5 + │ +108 │ DUT.S_AXI_RREADY := 1'b0; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [idle@4] executing step 0 of the transaction: 1 != 0 ---CODE--- 1 diff --git a/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed_workload_1.bi.expect b/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed_workload_1.bi.expect index da9923a9..5b0357ce 100644 --- a/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed_workload_1.bi.expect +++ b/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed_workload_1.bi.expect @@ -7,11 +7,11 @@ trace { idle(); // [time: 0ns -> 25ns] read_v1(64, 0); // [time: 25ns -> 100ns] } -error: [read_v2@4] executing step 0 of the transaction: 0 != 1 - ┌─ tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot:161:5 - │ -161 │ DUT.S_AXI_ARVALID := 1'b1; - │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@4] executing step 0 of the transaction: 0 != 1 +error: [read_v2@4] executing step 0 of the transaction: 0 != 1 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot:161:5 + │ +161 │ DUT.S_AXI_ARVALID := 1'b1; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@4] executing step 0 of the transaction: 0 != 1 // trace 1 @@ -19,11 +19,11 @@ trace { idle(); // [time: 0ns -> 25ns] read_v1(64, 0); // [time: 25ns -> 100ns] } -error: [read_v1@4] executing step 0 of the transaction: 0 != 1 - ┌─ tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot:124:5 - │ -124 │ DUT.S_AXI_ARVALID := 1'b1; - │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v1@4] executing step 0 of the transaction: 0 != 1 +error: [read_v1@4] executing step 0 of the transaction: 0 != 1 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot:124:5 + │ +124 │ DUT.S_AXI_ARVALID := 1'b1; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v1@4] executing step 0 of the transaction: 0 != 1 // trace 2 @@ -31,11 +31,11 @@ trace { idle(); // [time: 0ns -> 25ns] read_v1(64, 0); // [time: 25ns -> 100ns] } -error: [idle@4] executing step 0 of the transaction: 1 != 0 - ┌─ tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot:108:5 - │ -108 │ DUT.S_AXI_RREADY := 1'b0; - │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [idle@4] executing step 0 of the transaction: 1 != 0 +error: [idle@4] executing step 0 of the transaction: 1 != 0 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot:108:5 + │ +108 │ DUT.S_AXI_RREADY := 1'b0; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [idle@4] executing step 0 of the transaction: 1 != 0 // trace 3 @@ -43,11 +43,11 @@ trace { idle(); // [time: 0ns -> 25ns] read_v2(64, 0, 0); // [time: 25ns -> 100ns] } -error: [read_v2@4] executing step 0 of the transaction: 0 != 1 - ┌─ tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot:161:5 - │ -161 │ DUT.S_AXI_ARVALID := 1'b1; - │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@4] executing step 0 of the transaction: 0 != 1 +error: [read_v2@4] executing step 0 of the transaction: 0 != 1 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot:161:5 + │ +161 │ DUT.S_AXI_ARVALID := 1'b1; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@4] executing step 0 of the transaction: 0 != 1 // trace 4 @@ -55,11 +55,11 @@ trace { idle(); // [time: 0ns -> 25ns] read_v2(64, 0, 0); // [time: 25ns -> 100ns] } -error: [read_v1@4] executing step 0 of the transaction: 0 != 1 - ┌─ tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot:124:5 - │ -124 │ DUT.S_AXI_ARVALID := 1'b1; - │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v1@4] executing step 0 of the transaction: 0 != 1 +error: [read_v1@4] executing step 0 of the transaction: 0 != 1 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot:124:5 + │ +124 │ DUT.S_AXI_ARVALID := 1'b1; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v1@4] executing step 0 of the transaction: 0 != 1 // trace 5 @@ -67,11 +67,11 @@ trace { idle(); // [time: 0ns -> 25ns] read_v2(64, 0, 0); // [time: 25ns -> 100ns] } -error: [idle@4] executing step 0 of the transaction: 1 != 0 - ┌─ tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot:108:5 - │ -108 │ DUT.S_AXI_RREADY := 1'b0; - │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [idle@4] executing step 0 of the transaction: 1 != 0 +error: [idle@4] executing step 0 of the transaction: 1 != 0 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot:108:5 + │ +108 │ DUT.S_AXI_RREADY := 1'b0; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [idle@4] executing step 0 of the transaction: 1 != 0 ---CODE--- 1 diff --git a/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.bi.expect b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.bi.expect index 0e48f520..801003cc 100644 --- a/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.bi.expect +++ b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.bi.expect @@ -14,33 +14,33 @@ trace { trace { reset(); // [time: 0ns -> 25ns] } -error: [reset@1] executing step 0 of the transaction: 0 != 1 - ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot:115:5 - │ -115 │ DUT.rst := 1'b1; - │ ^^^^^^^^^^^^^^^^ [reset@1] executing step 0 of the transaction: 0 != 1 +error: [reset@1] executing step 0 of the transaction: 0 != 1 + ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot:115:5 + │ +115 │ DUT.rst := 1'b1; + │ ^^^^^^^^^^^^^^^^ [reset@1] executing step 0 of the transaction: 0 != 1 // trace 1 trace { reset(); // [time: 0ns -> 25ns] } -error: [idle@1] executing step 0 of the transaction: 1 != 0 - ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot:97:5 - │ -97 │ DUT.m_axis_tready := 1'b0; - │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [idle@1] executing step 0 of the transaction: 1 != 0 +error: [idle@1] executing step 0 of the transaction: 1 != 0 + ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot:97:5 + │ +97 │ DUT.m_axis_tready := 1'b0; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [idle@1] executing step 0 of the transaction: 1 != 0 // trace 2 trace { reset(); // [time: 0ns -> 25ns] } -error: [pop@1] executing step 0 of the transaction: 0 != 1 - ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot:62:5 - │ -62 │ assert_eq(DUT.m_axis_tvalid, 1'b1); - │ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ [pop@1] executing step 0 of the transaction: 0 != 1 +error: [pop@1] executing step 0 of the transaction: 0 != 1 + ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot:62:5 + │ +62 │ assert_eq(DUT.m_axis_tvalid, 1'b1); + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ [pop@1] executing step 0 of the transaction: 0 != 1 ---CODE--- 1 diff --git a/tests/fpga-debugging/axis-fifo-d4/expects/d4_fixed.bi.expect b/tests/fpga-debugging/axis-fifo-d4/expects/d4_fixed.bi.expect index 26e27800..48aafb42 100644 --- a/tests/fpga-debugging/axis-fifo-d4/expects/d4_fixed.bi.expect +++ b/tests/fpga-debugging/axis-fifo-d4/expects/d4_fixed.bi.expect @@ -44,11 +44,11 @@ trace { push(9); // [time: 140ns -> 142.5ns] push(233); // [time: 142.5ns -> 145ns] } -error: [push@63] executing step 1 of the transaction: 01 != 00 - ┌─ tests/fpga-debugging/axis-fifo-d4/d4_fixed.prot:89:5 - │ -89 │ DUT.s_axis_tdata := data; - │ ^^^^^^^^^^^^^^^^^^^^^^^^^ [push@63] executing step 1 of the transaction: 01 != 00 +error: [push@63] executing step 1 of the transaction: 01 != 00 + ┌─ tests/fpga-debugging/axis-fifo-d4/d4_fixed.prot:89:5 + │ +89 │ DUT.s_axis_tdata := data; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^ [push@63] executing step 1 of the transaction: 01 != 00 ---CODE--- 1 diff --git a/tests/wal/advanced/expects/axis.bi.expect b/tests/wal/advanced/expects/axis.bi.expect index 5892adbe..56066dee 100644 --- a/tests/wal/advanced/expects/axis.bi.expect +++ b/tests/wal/advanced/expects/axis.bi.expect @@ -5,11 +5,11 @@ trace { send_data(2); // [time: 2212ns -> 2220ns] send_data(3); // [time: 2916ns -> 2924ns] } -error: [send_data@453] executing step 88 of the transaction: 05 != 04 - ┌─ tests/wal/advanced/axis.prot:10:5 - │ -10 │ D.m_axis_tdata := data; - │ ^^^^^^^^^^^^^^^^^^^^^^^ [send_data@453] executing step 88 of the transaction: 05 != 04 +error: [send_data@453] executing step 88 of the transaction: 05 != 04 + ┌─ tests/wal/advanced/axis.prot:10:5 + │ +10 │ D.m_axis_tdata := data; + │ ^^^^^^^^^^^^^^^^^^^^^^^ [send_data@453] executing step 88 of the transaction: 05 != 04 ---CODE--- 1 diff --git a/tests/wal/advanced/expects/axis_failing.bi.expect b/tests/wal/advanced/expects/axis_failing.bi.expect index 9fae4547..ce009b0d 100644 --- a/tests/wal/advanced/expects/axis_failing.bi.expect +++ b/tests/wal/advanced/expects/axis_failing.bi.expect @@ -1,11 +1,11 @@ // trace 0 trace { } -error: [idle@0] executing step 0 of the transaction: 1 != 0 - ┌─ tests/wal/advanced/axis_failing.prot:11:5 - │ -11 │ D.m_axis_tvalid := 1'b0; - │ ^^^^^^^^^^^^^^^^^^^^^^^^ [idle@0] executing step 0 of the transaction: 1 != 0 +error: [idle@0] executing step 0 of the transaction: 1 != 0 + ┌─ tests/wal/advanced/axis_failing.prot:11:5 + │ +11 │ D.m_axis_tvalid := 1'b0; + │ ^^^^^^^^^^^^^^^^^^^^^^^^ [idle@0] executing step 0 of the transaction: 1 != 0 ---CODE--- 1 diff --git a/tests/wal/advanced/expects/axis_minimal.bi.expect b/tests/wal/advanced/expects/axis_minimal.bi.expect index 2523a8a7..5564118e 100644 --- a/tests/wal/advanced/expects/axis_minimal.bi.expect +++ b/tests/wal/advanced/expects/axis_minimal.bi.expect @@ -1,11 +1,11 @@ // trace 0 trace { } -error: [send_data@0] executing step 3 of the transaction: 0f != 14 - ┌─ tests/wal/advanced/axis_minimal.prot:10:5 - │ -10 │ D.m_axis_tdata := data; - │ ^^^^^^^^^^^^^^^^^^^^^^^ [send_data@0] executing step 3 of the transaction: 0f != 14 +error: [send_data@0] executing step 3 of the transaction: 0f != 14 + ┌─ tests/wal/advanced/axis_minimal.prot:10:5 + │ +10 │ D.m_axis_tdata := data; + │ ^^^^^^^^^^^^^^^^^^^^^^^ [send_data@0] executing step 3 of the transaction: 0f != 14 ---CODE--- 1 diff --git a/tests/wal/advanced/expects/axis_truncated.bi.expect b/tests/wal/advanced/expects/axis_truncated.bi.expect index 79980854..cef1509b 100644 --- a/tests/wal/advanced/expects/axis_truncated.bi.expect +++ b/tests/wal/advanced/expects/axis_truncated.bi.expect @@ -1,11 +1,11 @@ // trace 0 trace { } -error: [send_data@0] executing step 88 of the transaction: 0f != 0e - ┌─ tests/wal/advanced/axis_truncated.prot:10:5 - │ -10 │ D.m_axis_tdata := data; - │ ^^^^^^^^^^^^^^^^^^^^^^^ [send_data@0] executing step 88 of the transaction: 0f != 0e +error: [send_data@0] executing step 88 of the transaction: 0f != 0e + ┌─ tests/wal/advanced/axis_truncated.prot:10:5 + │ +10 │ D.m_axis_tdata := data; + │ ^^^^^^^^^^^^^^^^^^^^^^^ [send_data@0] executing step 88 of the transaction: 0f != 0e ---CODE--- 1 diff --git a/tests/wal/advanced/expects/axis_truncated_include_idle.bi.expect b/tests/wal/advanced/expects/axis_truncated_include_idle.bi.expect index 142e3ed2..728b03c9 100644 --- a/tests/wal/advanced/expects/axis_truncated_include_idle.bi.expect +++ b/tests/wal/advanced/expects/axis_truncated_include_idle.bi.expect @@ -1,11 +1,11 @@ // trace 0 trace { } -error: [send_data@0] executing step 88 of the transaction: 0f != 0e - ┌─ tests/wal/advanced/axis_truncated_include_idle.prot:11:5 - │ -11 │ D.m_axis_tdata := data; - │ ^^^^^^^^^^^^^^^^^^^^^^^ [send_data@0] executing step 88 of the transaction: 0f != 0e +error: [send_data@0] executing step 88 of the transaction: 0f != 0e + ┌─ tests/wal/advanced/axis_truncated_include_idle.prot:11:5 + │ +11 │ D.m_axis_tdata := data; + │ ^^^^^^^^^^^^^^^^^^^^^^^ [send_data@0] executing step 88 of the transaction: 0f != 0e ---CODE--- 1 From 3fd7b018c8b25b9d1c1f18bb1c685c5ea3f258cd Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sat, 18 Jul 2026 15:51:24 -0400 Subject: [PATCH 31/55] Fix remaining failing test case involving a panic due to unsupported time unit --- bi/src/main.rs | 11 ++++++++--- bi/src/signal_trace.rs | 3 +++ tests/wb_intercon/expects/wb_cdc.bi.expect | 9 +-------- 3 files changed, 12 insertions(+), 11 deletions(-) diff --git a/bi/src/main.rs b/bi/src/main.rs index e2944e2d..56f9f1c6 100644 --- a/bi/src/main.rs +++ b/bi/src/main.rs @@ -113,9 +113,14 @@ fn main() { // Parse CLI args let cli = Cli::parse(); - if let Some(tu) = cli.time_unit { - assert_eq!(tu, "ns", "Only nano seconds are supported"); - } + if let Some(tu) = cli.time_unit + && tu != "ns" { + eprintln!( + "Only nano seconds are supported (received time unit {}). Exiting...", + tu + ); + return; + } // parse protocol file let show_warnings = false; diff --git a/bi/src/signal_trace.rs b/bi/src/signal_trace.rs index c4d078a1..d409eea5 100644 --- a/bi/src/signal_trace.rs +++ b/bi/src/signal_trace.rs @@ -373,6 +373,9 @@ impl StepToTime { TimescaleUnit::FemtoSeconds => format!("{}ns", time as f64 / 1000.0 / 1000.0), TimescaleUnit::PicoSeconds => format!("{}ns", time as f64 / 1000.0), TimescaleUnit::NanoSeconds => format!("{}ns", time), + TimescaleUnit::MicroSeconds => format!("{}ns", time as f64 * 1000.0), + TimescaleUnit::MilliSeconds => format!("{}ns", time as f64 * 1000.0 * 1000.0), + TimescaleUnit::Seconds => format!("{}ns", time as f64 * 1000.0 * 1000.0 * 1000.0), other => todo!("support {other:?}"), } } else { diff --git a/tests/wb_intercon/expects/wb_cdc.bi.expect b/tests/wb_intercon/expects/wb_cdc.bi.expect index c3f3adc3..a102bb76 100644 --- a/tests/wb_intercon/expects/wb_cdc.bi.expect +++ b/tests/wb_intercon/expects/wb_cdc.bi.expect @@ -1,8 +1 @@ - -thread 'main' (2101252) panicked at bi/src/main.rs:117:9: -assertion `left == right` failed: Only nano seconds are supported - left: "s" - right: "ns" -note: run with `RUST_BACKTRACE=1` environment variable to display a backtrace ----CODE--- -101 +Only nano seconds are supported (received time unit s). Exiting... From d259beeda64f8506e3af30f64e2290ff3c4ffafb Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sat, 18 Jul 2026 15:52:23 -0400 Subject: [PATCH 32/55] formatting --- bi/src/main.rs | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/bi/src/main.rs b/bi/src/main.rs index 56f9f1c6..62a27b61 100644 --- a/bi/src/main.rs +++ b/bi/src/main.rs @@ -114,13 +114,14 @@ fn main() { let cli = Cli::parse(); if let Some(tu) = cli.time_unit - && tu != "ns" { - eprintln!( - "Only nano seconds are supported (received time unit {}). Exiting...", - tu - ); - return; - } + && tu != "ns" + { + eprintln!( + "Only nano seconds are supported (received time unit {}). Exiting...", + tu + ); + return; + } // parse protocol file let show_warnings = false; From bfd70aa33d41e3c0718bf76d52eaf0cf198f4121 Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sat, 18 Jul 2026 16:18:59 -0400 Subject: [PATCH 33/55] Add one extra comment --- bi/src/proto_trace.rs | 3 +++ 1 file changed, 3 insertions(+) diff --git a/bi/src/proto_trace.rs b/bi/src/proto_trace.rs index 09be2c27..48e1d4bf 100644 --- a/bi/src/proto_trace.rs +++ b/bi/src/proto_trace.rs @@ -150,9 +150,12 @@ pub struct Failure { pub proto_id: usize, pub thread_name: String, pub stmt: StmtId, + /// The specific kind of failure pub kind: FailureKind, } +/// The specific reason why the BI failed +/// (e.g. a constraint was violated, or a `fork` was encountered before a `step`, etc.) #[derive(Debug, Clone, PartialEq)] pub enum FailureKind { /// When the value of a signal in the waveform differs from what we expect From 06559fcd4f29e312595b4bde11b5d25fe9b79910 Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sun, 19 Jul 2026 13:05:06 -0400 Subject: [PATCH 34/55] Add syntax highlighting to .bi.expect files --- .../axis-async-fifo-c4/{c4_fixed.prot => c4.prot} | 0 tools/protocols-textmate/package.json | 3 ++- 2 files changed, 2 insertions(+), 1 deletion(-) rename tests/fpga-debugging/axis-async-fifo-c4/{c4_fixed.prot => c4.prot} (100%) diff --git a/tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.prot b/tests/fpga-debugging/axis-async-fifo-c4/c4.prot similarity index 100% rename from tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.prot rename to tests/fpga-debugging/axis-async-fifo-c4/c4.prot diff --git a/tools/protocols-textmate/package.json b/tools/protocols-textmate/package.json index 90bf9cdc..9613781a 100644 --- a/tools/protocols-textmate/package.json +++ b/tools/protocols-textmate/package.json @@ -34,7 +34,8 @@ "transactions" ], "extensions": [ - ".tx" + ".tx", + ".bi.expect" ], "configuration": "./transactions-configuration.json" } From 6bd6ff99faec17ae50dc53c31311bfed67540017 Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sun, 19 Jul 2026 13:05:31 -0400 Subject: [PATCH 35/55] Update Runt config to handle sharing the same .prot file for Brave New World test cases + excluding from graph interpreter --- runt/bi/runt.toml | 12 +++++------ runt/interp/runt.toml | 18 +++++++++++++++++ scripts/generate_runt_configs.py | 29 ++++++++++++++++++++++++--- scripts/test_catalog.py | 34 ++++++++++++++++++++++---------- 4 files changed, 74 insertions(+), 19 deletions(-) diff --git a/runt/bi/runt.toml b/runt/bi/runt.toml index 999cbe05..567638f1 100644 --- a/runt/bi/runt.toml +++ b/runt/bi/runt.toml @@ -1306,22 +1306,22 @@ expect_name = "s3_fixed.bi.expect" cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axis-adapter-s3/s3_fixed.prot --wave tests/fpga-debugging/axis-adapter-s3/s3_fixed.fst --instances TOP.test_axis_adapter_64_8.UUT:AXISManager --sample-posedge TOP.test_axis_adapter_64_8.UUT.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] -name = "bi.tests_fpga_debugging_axis_async_fifo_c4_c4_buggy.c4_buggy_bi" +name = "bi.tests_fpga_debugging_axis_async_fifo_c4_c4.c4_buggy_bi" paths = [ - "../../tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot", + "../../tests/fpga-debugging/axis-async-fifo-c4/c4.prot", ] expect_dir = "../../tests/fpga-debugging/axis-async-fifo-c4/expects" expect_name = "c4_buggy.bi.expect" -cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot --wave tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.fst --instances TOP.test_axis_async_fifo.UUT.axis_reg_inst:Sender TOP.test_axis_async_fifo.UUT.axis_reg_inst:Receiver --sample-posedge TOP.test_axis_async_fifo.UUT.axis_reg_inst.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axis-async-fifo-c4/c4.prot --wave tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.fst --instances TOP.test_axis_async_fifo.UUT.axis_reg_inst:AsyncFifo --sample-posedge TOP.test_axis_async_fifo.UUT.axis_reg_inst.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] -name = "bi.tests_fpga_debugging_axis_async_fifo_c4_c4_fixed.c4_fixed_bi" +name = "bi.tests_fpga_debugging_axis_async_fifo_c4_c4.c4_fixed_bi" paths = [ - "../../tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.prot", + "../../tests/fpga-debugging/axis-async-fifo-c4/c4.prot", ] expect_dir = "../../tests/fpga-debugging/axis-async-fifo-c4/expects" expect_name = "c4_fixed.bi.expect" -cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.prot --wave tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.fst --instances TOP.test_axis_async_fifo.UUT.axis_reg_inst:Sender TOP.test_axis_async_fifo.UUT.axis_reg_inst:Receiver --sample-posedge TOP.test_axis_async_fifo.UUT.axis_reg_inst.clk --show-waveform-time --time-unit ns 2>&1" +cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axis-async-fifo-c4/c4.prot --wave tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.fst --instances TOP.test_axis_async_fifo.UUT.axis_reg_inst:AsyncFifo --sample-posedge TOP.test_axis_async_fifo.UUT.axis_reg_inst.clk --show-waveform-time --time-unit ns --max-traces 20 2>&1" [[tests]] name = "bi.tests_fpga_debugging_axis_fifo_d11_d11_buggy.d11_buggy_bi" diff --git a/runt/interp/runt.toml b/runt/interp/runt.toml index 23b631a7..0e57ecaa 100644 --- a/runt/interp/runt.toml +++ b/runt/interp/runt.toml @@ -495,6 +495,24 @@ expect_dir = "../../tests/fifo/expects" expect_name = "push_pop_loop_not_empty.interp.expect" cmd = "cd ../.. && target/debug/protocols-interp --color never --transactions tests/fifo/push_pop_loop_not_empty.tx --verilog tests/fifo/bsg_mem_1rw_sync.v tests/fifo/bsg_mem_1rw_sync_synth.v tests/fifo/bsg_circular_ptr.v tests/fifo/bsg_fifo_1rw_large.v tests/fifo/fifo_wrapper.v --protocol tests/fifo/fifo_bounded_loop.prot --module fifo_wrapper 2>&1" +[[tests]] +name = "interp.tests_fpga_debugging_axis_async_fifo_c4_c4_buggy.c4_buggy_interp" +paths = [ + "../../tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.tx", +] +expect_dir = "../../tests/fpga-debugging/axis-async-fifo-c4/expects" +expect_name = "c4_buggy.interp.expect" +cmd = "cd ../.. && target/debug/protocols-interp --color never --transactions tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.tx --verilog tests/fpga-debugging/axis-async-fifo-c4/c4_dut.v tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.v --protocol tests/fpga-debugging/axis-async-fifo-c4/c4.prot --module c4_dut 2>&1" + +[[tests]] +name = "interp.tests_fpga_debugging_axis_async_fifo_c4_c4_fixed.c4_fixed_interp" +paths = [ + "../../tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.tx", +] +expect_dir = "../../tests/fpga-debugging/axis-async-fifo-c4/expects" +expect_name = "c4_fixed.interp.expect" +cmd = "cd ../.. && target/debug/protocols-interp --color never --transactions tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.tx --verilog tests/fpga-debugging/axis-async-fifo-c4/c4_dut.v tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.v --protocol tests/fpga-debugging/axis-async-fifo-c4/c4.prot --module c4_dut 2>&1" + [[tests]] name = "interp.tests_identities_dual_identity_d0_dual_identity_d0_combdep.dual_identity_d0_combdep_interp" paths = [ diff --git a/scripts/generate_runt_configs.py b/scripts/generate_runt_configs.py index c2df419f..b91ec3bf 100644 --- a/scripts/generate_runt_configs.py +++ b/scripts/generate_runt_configs.py @@ -70,11 +70,23 @@ def replace_non_alphanumerics(value: object) -> str: return re.sub(r"[^A-Za-z0-9]+", "_", text).strip("_") or "default" +def shared_bi_prot_files() -> frozenset[str]: + # Set of `.prot` files which are used by more than one BI test case + # (e.g. Antmicro and the Brave New World test cases for fixed/buggy wvaeforms + # that share a single .prot file) + from collections import Counter + + counts = Counter(test_case["protocol"] for test_case in test_catalog.BI_CASES.values()) + return frozenset(file for (file, num_cases) in counts.items() if num_cases > 1) + + def case_stem(case: dict) -> str: - # antmicro cases share one .prot but differ by wave, so name them by - # the wave; otherwise use the test file's stem (dropping a .bi suffix). + # Antmicro & Brave New World test cases for the BI share the same `.prot` + # file but have multiple waveforms, so we use the waveform files' + # names to identify a particular test, otherwise we use the `.prot` file's stem + # to identify a test wave = case.get("wave") - if wave and case["path"].startswith("tests/antmicro/"): + if wave and case["path"] in shared_bi_prot_files(): return Path(wave).stem stem = Path(case["path"]).stem return stem.removesuffix(".bi") @@ -297,6 +309,15 @@ def protocol_constructs(protocol_path: str) -> frozenset[str]: return frozenset(used) +# `.tx` files that are kept only for the AST interpreter +# and excluded from the graph interpreter for now +# (otherwise `.tx` files are shared between the AST & graph interpreters) +EXCLUDED_GRAPH_INTERPRETER_TEST_CASES = { + "tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.tx", + "tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.tx", +} + + def graph_interp_cases(cases: list[dict]) -> list[dict]: """Passing tx cases whose protocol uses no for-in or repeat loop.""" # Loop constructs the graph interpreter cannot handle (AST construct names). @@ -306,6 +327,7 @@ def graph_interp_cases(cases: list[dict]) -> list[dict]: c for c in cases if c["expected"] == "pass" + and c["path"] not in EXCLUDED_GRAPH_INTERPRETER_TEST_CASES and not graph_interp_unsupported & protocol_constructs(c["protocol_path"]) ] return sorted(selected, key=lambda c: c["path"]) @@ -338,6 +360,7 @@ def fail_cases(cases: list[dict]) -> list[dict]: c for c in cases if c["expected"] in runtime_failures + and c["path"] not in EXCLUDED_GRAPH_INTERPRETER_TEST_CASES and not graph_interp_unsupported & protocol_constructs(c["protocol_path"]) ] return sorted(selected, key=lambda c: c["path"]) diff --git a/scripts/test_catalog.py b/scripts/test_catalog.py index daef74d3..f746dac9 100644 --- a/scripts/test_catalog.py +++ b/scripts/test_catalog.py @@ -349,6 +349,24 @@ "top": "fifo_wrapper", "expect": "pass", }, + "tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.tx": { + "protocol": "tests/fpga-debugging/axis-async-fifo-c4/c4.prot", + "verilog": ( + "tests/fpga-debugging/axis-async-fifo-c4/c4_dut.v", + "tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.v", + ), + "top": "c4_dut", + "expect": "assertion_mismatch", + }, + "tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.tx": { + "protocol": "tests/fpga-debugging/axis-async-fifo-c4/c4.prot", + "verilog": ( + "tests/fpga-debugging/axis-async-fifo-c4/c4_dut.v", + "tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.v", + ), + "top": "c4_dut", + "expect": "pass", + }, "tests/identities/dual_identity_d0/dual_identity_d0_combdep.tx": { "protocol": "tests/identities/dual_identity_d0/dual_identity_d0.prot", "verilog": ("tests/identities/dual_identity_d0/dual_identity_d0.v",), @@ -782,12 +800,9 @@ ), }, "tests.fpga-debugging.axis-async-fifo-c4.c4_buggy": { - "protocol": "tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot", + "protocol": "tests/fpga-debugging/axis-async-fifo-c4/c4.prot", "wave": "tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.fst", - "instances": ( - "TOP.test_axis_async_fifo.UUT.axis_reg_inst:Sender", - "TOP.test_axis_async_fifo.UUT.axis_reg_inst:Receiver", - ), + "instances": ("TOP.test_axis_async_fifo.UUT.axis_reg_inst:AsyncFifo",), "expect": None, "extra_args": ( "--sample-posedge", @@ -798,12 +813,9 @@ ), }, "tests.fpga-debugging.axis-async-fifo-c4.c4_fixed": { - "protocol": "tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.prot", + "protocol": "tests/fpga-debugging/axis-async-fifo-c4/c4.prot", "wave": "tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.fst", - "instances": ( - "TOP.test_axis_async_fifo.UUT.axis_reg_inst:Sender", - "TOP.test_axis_async_fifo.UUT.axis_reg_inst:Receiver", - ), + "instances": ("TOP.test_axis_async_fifo.UUT.axis_reg_inst:AsyncFifo",), "expect": "pass", "extra_args": ( "--sample-posedge", @@ -811,6 +823,8 @@ "--show-waveform-time", "--time-unit", "ns", + "--max-traces", + "20" ), }, "tests.fpga-debugging.axis-fifo-d11.d11_buggy": { From 027ab107428068f7fdb9102747523b35338562b9 Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sun, 19 Jul 2026 13:05:51 -0400 Subject: [PATCH 36/55] Add extra Verilog file to handle port renaming --- .../axis-async-fifo-c4/c4_dut.v | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 tests/fpga-debugging/axis-async-fifo-c4/c4_dut.v diff --git a/tests/fpga-debugging/axis-async-fifo-c4/c4_dut.v b/tests/fpga-debugging/axis-async-fifo-c4/c4_dut.v new file mode 100644 index 00000000..44e7642a --- /dev/null +++ b/tests/fpga-debugging/axis-async-fifo-c4/c4_dut.v @@ -0,0 +1,47 @@ +// This file is used to rename ports so that the interpreter can drive the design. +// The signals in waveforms used by the BI (obtained directly from the Brave New World artifact) +// uses names such as `axis_reg_inst.s_axis_tdata`, but the Verilog DUT (in `c4_buggy.v` / `c4_fixed.v`) +// uses names such as `input_axis_tdata`, so this file renames them. + +`timescale 1ns / 1ps + +module c4_dut ( + input wire clk, + input wire rst, + + // AXI-Stream input (write / push) side + input wire [7:0] s_axis_tdata, + input wire s_axis_tvalid, + output wire s_axis_tready, + + // AXI-Stream output (read / pop) side + input wire m_axis_tready, + output wire m_axis_tvalid, + output wire [7:0] m_axis_tdata +); + +axis_async_fifo #( + .ADDR_WIDTH(5), + .DATA_WIDTH(8) +) +fifo ( + .async_rst(rst), + + // AXI input + .input_clk(clk), + .input_axis_tdata(s_axis_tdata), + .input_axis_tvalid(s_axis_tvalid), + .input_axis_tready(s_axis_tready), + .input_axis_tlast(1'b0), + .input_axis_tuser(1'b0), + + // AXI output + .output_clk(clk), + .output_axis_tdata(m_axis_tdata), + .output_axis_tvalid(m_axis_tvalid), + .output_axis_tready(m_axis_tready), + .output_axis_tlast(), + .output_axis_tuser() +); + +endmodule From 7e04069363a7b07ebda1c39d605dd95fea25eaaa Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sun, 19 Jul 2026 13:06:41 -0400 Subject: [PATCH 37/55] Combine c4_buggy/c4_fixed.prot into one file --- .../fpga-debugging/axis-async-fifo-c4/c4.prot | 54 +--- .../axis-async-fifo-c4/c4_buggy.prot | 121 ------- .../expects/c4_buggy.bi.expect | 39 ++- .../expects/c4_fixed.bi.expect | 296 +++++++++++++++++- 4 files changed, 314 insertions(+), 196 deletions(-) delete mode 100644 tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot diff --git a/tests/fpga-debugging/axis-async-fifo-c4/c4.prot b/tests/fpga-debugging/axis-async-fifo-c4/c4.prot index 7a59c42e..24961d6d 100644 --- a/tests/fpga-debugging/axis-async-fifo-c4/c4.prot +++ b/tests/fpga-debugging/axis-async-fifo-c4/c4.prot @@ -1,5 +1,4 @@ -// Only `Sender` supports `push` -struct Sender { +struct AsyncFifo { // Active-high reset signal // Note: AXI-Stream says reset should be active-low, // but this DUT uses active-high instead @@ -11,14 +10,6 @@ struct Sender { in s_axis_tdata: u8, in s_axis_tvalid: u1, out s_axis_tready: u1, -} - -// Only `Receiver` supports `pop` -struct Receiver { - // Active-high reset signal - // Note: AXI-Stream says reset should be active-low, - // but this DUT uses active-high instead - in rst: u1, // The Receiver receives a READY signal from the environment // (environment is ready to read data that is popped from the FIFO) @@ -30,7 +21,7 @@ struct Receiver { // PUSH: Write data to FIFO via AXI-Stream receiver interface // Performs data transfer when s_axis_tvalid and s_axis_tready are both 1 -prot push(data: u8) { +prot push(data: u8) { DUT.rst := 1'b0; // Update the data field and set receiver's valid bit to 1 to indicate @@ -47,8 +38,8 @@ prot push(data: u8) { step(); } -// POP: Read data from FIFO via AXI-Stream sender interface -prot pop(data: u8) { +// POP: Read data from FIFO (the `data` argument is the data that is popped) +prot pop(data: u8) { DUT.rst := 1'b0; DUT.m_axis_tready := 1'b1; @@ -61,63 +52,38 @@ prot pop(data: u8) { // without waiting for it to become 1. assert_eq(DUT.m_axis_tvalid, 1'b1); - // One cycle for the transfer to complete - step(); - - // Capture output data assert_eq(DUT.m_axis_tdata, data); - // Release inputs after transaction (i.e. release all constraints) - DUT.m_axis_tready := X; - DUT.rst := X; - - fork(); + // One cycle for the transfer to complete step(); } // IDLE: No transaction occurs on the monitored interface -// For Sender: no push transaction (no data being written to FIFO) -// For Receiver: no pop transaction (no data being read from FIFO) -prot idle() { +prot idle() { DUT.rst := 1'b0; - // Ensure no push handshake by setting valid = 0 - // (Push handshake requires s_axis_tvalid && s_axis_tready) + // Ensure no pushes from the sender by setting valid = 0 DUT.s_axis_tvalid := 1'b0; // Data is DontCare when valid = 0 DUT.s_axis_tdata := X; - step(); -} - -prot idle() { - DUT.rst := 1'b0; - - // Ensure no pop handshake by setting ready = 0 - // (Pop handshake requires m_axis_tvalid && m_axis_tready) + // Ensure no pops from the receiver by setting ready = 0 DUT.m_axis_tready := 1'b0; step(); } // RESET: Assert reset signal to initialize FIFO -prot reset() { +prot reset() { DUT.rst := 1'b1; // Valid must be low when reset is asserted (AXI-Stream spec section 2.8.2) DUT.s_axis_tvalid := 1'b0; - step(); -} - -// We have to also define `reset` for the `Receiver` `DUT` since different -// structs are now treated separately in the new monitor implementation -prot reset() { - DUT.rst := 1'b1; - // Valid must be low when reset is asserted (AXI-Stream spec section 2.8.2) assert_eq(DUT.m_axis_tvalid, 1'b0); step(); } + diff --git a/tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot b/tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot deleted file mode 100644 index f8d0a03c..00000000 --- a/tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot +++ /dev/null @@ -1,121 +0,0 @@ -// Only `Sender` supports `push` -struct Sender { - // Active-high reset signal - // Note: AXI-Stream says reset should be active-low, - // but this DUT uses active-high instead - in rst: u1, - - // The Sender recieves VALID and DATA signals from the environment - // (data to be written, i.e. pushed to the FIFO), - // and outputs a READY signal, indicating that the FIFO can accept new data - in s_axis_tdata: u8, - in s_axis_tvalid: u1, - out s_axis_tready: u1, -} - -// Only `Receiver` supports `pop` -struct Receiver { - // Active-high reset signal - // Note: AXI-Stream says reset should be active-low, - // but this DUT uses active-high instead - in rst: u1, - - // The Receiver receives a READY signal from the environment - // (environment is ready to read data that is popped from the FIFO) - // and outputs a VALID signal + the data being popped - in m_axis_tready: u1, - out m_axis_tvalid: u1, - out m_axis_tdata: u8, -} - -// PUSH: Write data to FIFO via AXI-Stream receiver interface -// Performs data transfer when s_axis_tvalid and s_axis_tready are both 1 -prot push(data: u8) { - DUT.rst := 1'b0; - - // Update the data field and set receiver's valid bit to 1 to indicate - // that data transfer can occur - DUT.s_axis_tdata := data; - DUT.s_axis_tvalid := 1'b1; - - // Wait for FIFO to be ready to accept data - while (!(DUT.s_axis_tready == 1'b1)) { - step(); - } - - // One cycle for the transfer to complete - step(); -} - -// POP: Read data from FIFO via AXI-Stream sender interface -prot pop(data: u8) { - DUT.rst := 1'b0; - DUT.m_axis_tready := 1'b1; - - // Valid needs to be 1 in order for data exchange to occur - // Note: we don't use a while-loop here to wait for `m_axis_tvalid` to become 1, - // since when `m_axis_tready = 1 && m_axis_tvalid = 0`, that means the environment is ready - // to read the popped data but the DUT has no valid data on its output ports. - // This situation should not be described in a `pop` transaction, - // so we just assert that `m_axis_tvalid` must be 1 during a `pop` transaction - // without waiting for it to become 1. - assert_eq(DUT.m_axis_tvalid, 1'b1); - - // One cycle for the transfer to complete - step(); - - assert_eq(DUT.m_axis_tdata, data); - - // Release inputs after transaction (i.e. release all constraints) - DUT.m_axis_tready := X; - DUT.rst := X; - - fork(); - step(); -} - -// IDLE: No transaction occurs on the monitored interface -// For Sender: no push transaction (no data being written to FIFO) -// For Receiver: no pop transaction (no data being read from FIFO) -prot idle() { - DUT.rst := 1'b0; - - // Ensure no push handshake by setting valid = 0 - // (Push handshake requires s_axis_tvalid && s_axis_tready) - DUT.s_axis_tvalid := 1'b0; - - // Data is DontCare when valid = 0 - DUT.s_axis_tdata := X; - - step(); -} - -prot idle() { - DUT.rst := 1'b0; - - // Ensure no pop handshake by setting ready = 0 - DUT.m_axis_tready := 1'b0; - - step(); -} - -// RESET: Assert reset signal to initialize FIFO -prot reset() { - DUT.rst := 1'b1; - - // Valid must be low when reset is asserted (AXI-Stream spec section 2.8.2) - DUT.s_axis_tvalid := 1'b0; - - step(); -} - -// We have to also define `reset` for the `Receiver` `DUT` since different -// structs are now treated separately in the new monitor implementation -prot reset() { - DUT.rst := 1'b1; - - // Valid must be low when reset is asserted (AXI-Stream spec section 2.8.2) - assert_eq(DUT.m_axis_tvalid, 1'b0); - - step(); -} diff --git a/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.bi.expect b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.bi.expect index 801003cc..583da898 100644 --- a/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.bi.expect +++ b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.bi.expect @@ -1,24 +1,12 @@ // trace 0 -trace { - reset(); // [time: 0ns -> 25ns] - idle(); // [time: 25ns -> 50ns] - push(1); // [time: 50ns -> 75ns] - push(2); // [time: 75ns -> 100ns] - push(3); // [time: 100ns -> 125ns] - push(4); // [time: 125ns -> 150ns] - push(5); // [time: 150ns -> 175ns] - push(6); // [time: 175ns -> 200ns] - push(7); // [time: 200ns -> 200ns] -} -// trace 0 trace { reset(); // [time: 0ns -> 25ns] } error: [reset@1] executing step 0 of the transaction: 0 != 1 - ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot:115:5 - │ -115 │ DUT.rst := 1'b1; - │ ^^^^^^^^^^^^^^^^ [reset@1] executing step 0 of the transaction: 0 != 1 + ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4.prot:79:5 + │ +79 │ DUT.rst := 1'b1; + │ ^^^^^^^^^^^^^^^^ [reset@1] executing step 0 of the transaction: 0 != 1 // trace 1 @@ -26,9 +14,9 @@ trace { reset(); // [time: 0ns -> 25ns] } error: [idle@1] executing step 0 of the transaction: 1 != 0 - ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot:97:5 + ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4.prot:72:5 │ -97 │ DUT.m_axis_tready := 1'b0; +72 │ DUT.m_axis_tready := 1'b0; │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [idle@1] executing step 0 of the transaction: 1 != 0 @@ -37,10 +25,21 @@ trace { reset(); // [time: 0ns -> 25ns] } error: [pop@1] executing step 0 of the transaction: 0 != 1 - ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot:62:5 + ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4.prot:53:5 │ -62 │ assert_eq(DUT.m_axis_tvalid, 1'b1); +53 │ assert_eq(DUT.m_axis_tvalid, 1'b1); │ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ [pop@1] executing step 0 of the transaction: 0 != 1 + +// trace 3 +trace { + reset(); // [time: 0ns -> 25ns] +} +error: [push@1] executing step 0 of the transaction: 0 != 1 + ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4.prot:30:5 + │ +30 │ DUT.s_axis_tvalid := 1'b1; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [push@1] executing step 0 of the transaction: 0 != 1 + ---CODE--- 1 diff --git a/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_fixed.bi.expect b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_fixed.bi.expect index 49910681..e943304d 100644 --- a/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_fixed.bi.expect +++ b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_fixed.bi.expect @@ -4,23 +4,297 @@ trace { idle(); // [time: 25ns -> 50ns] push(1); // [time: 50ns -> 75ns] push(2); // [time: 75ns -> 100ns] - push(3); // [time: 100ns -> 150ns] - push(4); // [time: 150ns -> 175ns] + pop(1); // [time: 100ns -> 125ns] + push(3); // [time: 125ns -> 150ns] + pop(3); // [time: 150ns -> 175ns] + push(5); // [time: 175ns -> 200ns] + pop(5); // [time: 200ns -> 225ns] + push(7); // [time: 225ns -> 250ns] + pop(7); // [time: 250ns -> 250ns] +} + +// trace 1 +trace { + reset(); // [time: 0ns -> 25ns] + idle(); // [time: 25ns -> 50ns] + push(1); // [time: 50ns -> 75ns] + push(2); // [time: 75ns -> 100ns] + pop(1); // [time: 100ns -> 125ns] + push(3); // [time: 125ns -> 150ns] + pop(3); // [time: 150ns -> 175ns] + push(5); // [time: 175ns -> 200ns] + pop(5); // [time: 200ns -> 225ns] + push(7); // [time: 225ns -> 250ns] + push(8); // [time: 250ns -> 250ns] +} + +// trace 2 +trace { + reset(); // [time: 0ns -> 25ns] + idle(); // [time: 25ns -> 50ns] + push(1); // [time: 50ns -> 75ns] + push(2); // [time: 75ns -> 100ns] + pop(1); // [time: 100ns -> 125ns] + push(3); // [time: 125ns -> 150ns] + pop(3); // [time: 150ns -> 175ns] + push(5); // [time: 175ns -> 200ns] + pop(5); // [time: 200ns -> 225ns] + pop(6); // [time: 225ns -> 250ns] + pop(7); // [time: 250ns -> 250ns] +} + +// trace 3 +trace { + reset(); // [time: 0ns -> 25ns] + idle(); // [time: 25ns -> 50ns] + push(1); // [time: 50ns -> 75ns] + push(2); // [time: 75ns -> 100ns] + pop(1); // [time: 100ns -> 125ns] + push(3); // [time: 125ns -> 150ns] + pop(3); // [time: 150ns -> 175ns] + push(5); // [time: 175ns -> 200ns] + pop(5); // [time: 200ns -> 225ns] + pop(6); // [time: 225ns -> 250ns] + push(8); // [time: 250ns -> 250ns] +} + +// trace 4 +trace { + reset(); // [time: 0ns -> 25ns] + idle(); // [time: 25ns -> 50ns] + push(1); // [time: 50ns -> 75ns] + push(2); // [time: 75ns -> 100ns] + pop(1); // [time: 100ns -> 125ns] + push(3); // [time: 125ns -> 150ns] + pop(3); // [time: 150ns -> 175ns] + push(5); // [time: 175ns -> 200ns] + push(6); // [time: 200ns -> 225ns] + push(7); // [time: 225ns -> 250ns] + pop(7); // [time: 250ns -> 250ns] +} + +// trace 5 +trace { + reset(); // [time: 0ns -> 25ns] + idle(); // [time: 25ns -> 50ns] + push(1); // [time: 50ns -> 75ns] + push(2); // [time: 75ns -> 100ns] + pop(1); // [time: 100ns -> 125ns] + push(3); // [time: 125ns -> 150ns] + pop(3); // [time: 150ns -> 175ns] push(5); // [time: 175ns -> 200ns] push(6); // [time: 200ns -> 225ns] push(7); // [time: 225ns -> 250ns] push(8); // [time: 250ns -> 250ns] } -// trace 0 + +// trace 6 +trace { + reset(); // [time: 0ns -> 25ns] + idle(); // [time: 25ns -> 50ns] + push(1); // [time: 50ns -> 75ns] + push(2); // [time: 75ns -> 100ns] + pop(1); // [time: 100ns -> 125ns] + push(3); // [time: 125ns -> 150ns] + pop(3); // [time: 150ns -> 175ns] + push(5); // [time: 175ns -> 200ns] + push(6); // [time: 200ns -> 225ns] + pop(6); // [time: 225ns -> 250ns] + pop(7); // [time: 250ns -> 250ns] +} + +// trace 7 +trace { + reset(); // [time: 0ns -> 25ns] + idle(); // [time: 25ns -> 50ns] + push(1); // [time: 50ns -> 75ns] + push(2); // [time: 75ns -> 100ns] + pop(1); // [time: 100ns -> 125ns] + push(3); // [time: 125ns -> 150ns] + pop(3); // [time: 150ns -> 175ns] + push(5); // [time: 175ns -> 200ns] + push(6); // [time: 200ns -> 225ns] + pop(6); // [time: 225ns -> 250ns] + push(8); // [time: 250ns -> 250ns] +} + +// trace 8 +trace { + reset(); // [time: 0ns -> 25ns] + idle(); // [time: 25ns -> 50ns] + push(1); // [time: 50ns -> 75ns] + push(2); // [time: 75ns -> 100ns] + pop(1); // [time: 100ns -> 125ns] + push(3); // [time: 125ns -> 150ns] + pop(3); // [time: 150ns -> 175ns] + pop(4); // [time: 175ns -> 200ns] + pop(5); // [time: 200ns -> 225ns] + push(7); // [time: 225ns -> 250ns] + pop(7); // [time: 250ns -> 250ns] +} + +// trace 9 +trace { + reset(); // [time: 0ns -> 25ns] + idle(); // [time: 25ns -> 50ns] + push(1); // [time: 50ns -> 75ns] + push(2); // [time: 75ns -> 100ns] + pop(1); // [time: 100ns -> 125ns] + push(3); // [time: 125ns -> 150ns] + pop(3); // [time: 150ns -> 175ns] + pop(4); // [time: 175ns -> 200ns] + pop(5); // [time: 200ns -> 225ns] + push(7); // [time: 225ns -> 250ns] + push(8); // [time: 250ns -> 250ns] +} + +// trace 10 +trace { + reset(); // [time: 0ns -> 25ns] + idle(); // [time: 25ns -> 50ns] + push(1); // [time: 50ns -> 75ns] + push(2); // [time: 75ns -> 100ns] + pop(1); // [time: 100ns -> 125ns] + push(3); // [time: 125ns -> 150ns] + pop(3); // [time: 150ns -> 175ns] + pop(4); // [time: 175ns -> 200ns] + pop(5); // [time: 200ns -> 225ns] + pop(6); // [time: 225ns -> 250ns] + pop(7); // [time: 250ns -> 250ns] +} + +// trace 11 +trace { + reset(); // [time: 0ns -> 25ns] + idle(); // [time: 25ns -> 50ns] + push(1); // [time: 50ns -> 75ns] + push(2); // [time: 75ns -> 100ns] + pop(1); // [time: 100ns -> 125ns] + push(3); // [time: 125ns -> 150ns] + pop(3); // [time: 150ns -> 175ns] + pop(4); // [time: 175ns -> 200ns] + pop(5); // [time: 200ns -> 225ns] + pop(6); // [time: 225ns -> 250ns] + push(8); // [time: 250ns -> 250ns] +} + +// trace 12 +trace { + reset(); // [time: 0ns -> 25ns] + idle(); // [time: 25ns -> 50ns] + push(1); // [time: 50ns -> 75ns] + push(2); // [time: 75ns -> 100ns] + pop(1); // [time: 100ns -> 125ns] + push(3); // [time: 125ns -> 150ns] + pop(3); // [time: 150ns -> 175ns] + pop(4); // [time: 175ns -> 200ns] + push(6); // [time: 200ns -> 225ns] + push(7); // [time: 225ns -> 250ns] + pop(7); // [time: 250ns -> 250ns] +} + +// trace 13 +trace { + reset(); // [time: 0ns -> 25ns] + idle(); // [time: 25ns -> 50ns] + push(1); // [time: 50ns -> 75ns] + push(2); // [time: 75ns -> 100ns] + pop(1); // [time: 100ns -> 125ns] + push(3); // [time: 125ns -> 150ns] + pop(3); // [time: 150ns -> 175ns] + pop(4); // [time: 175ns -> 200ns] + push(6); // [time: 200ns -> 225ns] + push(7); // [time: 225ns -> 250ns] + push(8); // [time: 250ns -> 250ns] +} + +// trace 14 +trace { + reset(); // [time: 0ns -> 25ns] + idle(); // [time: 25ns -> 50ns] + push(1); // [time: 50ns -> 75ns] + push(2); // [time: 75ns -> 100ns] + pop(1); // [time: 100ns -> 125ns] + push(3); // [time: 125ns -> 150ns] + pop(3); // [time: 150ns -> 175ns] + pop(4); // [time: 175ns -> 200ns] + push(6); // [time: 200ns -> 225ns] + pop(6); // [time: 225ns -> 250ns] + pop(7); // [time: 250ns -> 250ns] +} + +// trace 15 +trace { + reset(); // [time: 0ns -> 25ns] + idle(); // [time: 25ns -> 50ns] + push(1); // [time: 50ns -> 75ns] + push(2); // [time: 75ns -> 100ns] + pop(1); // [time: 100ns -> 125ns] + push(3); // [time: 125ns -> 150ns] + pop(3); // [time: 150ns -> 175ns] + pop(4); // [time: 175ns -> 200ns] + push(6); // [time: 200ns -> 225ns] + pop(6); // [time: 225ns -> 250ns] + push(8); // [time: 250ns -> 250ns] +} + +// trace 16 +trace { + reset(); // [time: 0ns -> 25ns] + idle(); // [time: 25ns -> 50ns] + push(1); // [time: 50ns -> 75ns] + push(2); // [time: 75ns -> 100ns] + pop(1); // [time: 100ns -> 125ns] + push(3); // [time: 125ns -> 150ns] + push(4); // [time: 150ns -> 175ns] + push(5); // [time: 175ns -> 200ns] + pop(5); // [time: 200ns -> 225ns] + push(7); // [time: 225ns -> 250ns] + pop(7); // [time: 250ns -> 250ns] +} + +// trace 17 +trace { + reset(); // [time: 0ns -> 25ns] + idle(); // [time: 25ns -> 50ns] + push(1); // [time: 50ns -> 75ns] + push(2); // [time: 75ns -> 100ns] + pop(1); // [time: 100ns -> 125ns] + push(3); // [time: 125ns -> 150ns] + push(4); // [time: 150ns -> 175ns] + push(5); // [time: 175ns -> 200ns] + pop(5); // [time: 200ns -> 225ns] + push(7); // [time: 225ns -> 250ns] + push(8); // [time: 250ns -> 250ns] +} + +// trace 18 trace { reset(); // [time: 0ns -> 25ns] idle(); // [time: 25ns -> 50ns] - idle(); // [time: 50ns -> 75ns] - idle(); // [time: 75ns -> 100ns] - pop(2); // [time: 100ns -> 150ns] - pop(3); // [time: 125ns -> 175ns] - pop(4); // [time: 150ns -> 200ns] - pop(5); // [time: 175ns -> 225ns] - pop(6); // [time: 200ns -> 250ns] - pop(7); // [time: 225ns -> 250ns] + push(1); // [time: 50ns -> 75ns] + push(2); // [time: 75ns -> 100ns] + pop(1); // [time: 100ns -> 125ns] + push(3); // [time: 125ns -> 150ns] + push(4); // [time: 150ns -> 175ns] + push(5); // [time: 175ns -> 200ns] + pop(5); // [time: 200ns -> 225ns] + pop(6); // [time: 225ns -> 250ns] + pop(7); // [time: 250ns -> 250ns] +} + +// trace 19 +trace { + reset(); // [time: 0ns -> 25ns] + idle(); // [time: 25ns -> 50ns] + push(1); // [time: 50ns -> 75ns] + push(2); // [time: 75ns -> 100ns] + pop(1); // [time: 100ns -> 125ns] + push(3); // [time: 125ns -> 150ns] + push(4); // [time: 150ns -> 175ns] + push(5); // [time: 175ns -> 200ns] + pop(5); // [time: 200ns -> 225ns] + pop(6); // [time: 225ns -> 250ns] + push(8); // [time: 250ns -> 250ns] } +Displayed 20/96 traces. From d7ee8ebac0b9c62208b783b772675453a791de36 Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sun, 19 Jul 2026 13:07:00 -0400 Subject: [PATCH 38/55] Add .tx files for interpreter --- tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.tx | 11 +++++++++++ tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.tx | 11 +++++++++++ .../axis-async-fifo-c4/expects/c4_buggy.interp.expect | 9 +++++++++ .../axis-async-fifo-c4/expects/c4_fixed.interp.expect | 1 + 4 files changed, 32 insertions(+) create mode 100644 tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.tx create mode 100644 tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.tx create mode 100644 tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.interp.expect create mode 100644 tests/fpga-debugging/axis-async-fifo-c4/expects/c4_fixed.interp.expect diff --git a/tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.tx b/tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.tx new file mode 100644 index 00000000..cbef167e --- /dev/null +++ b/tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.tx @@ -0,0 +1,11 @@ +trace { + reset(); + idle(); + push(1); + push(2); + push(3); + idle(); + idle(); + pop(1); + pop(2); +} diff --git a/tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.tx b/tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.tx new file mode 100644 index 00000000..010dca97 --- /dev/null +++ b/tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.tx @@ -0,0 +1,11 @@ +trace { + reset(); + idle(); + push(1); + push(2); + push(3); + idle(); + idle(); + pop(1); + pop(2); +} \ No newline at end of file diff --git a/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.interp.expect b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.interp.expect new file mode 100644 index 00000000..9a4c59d6 --- /dev/null +++ b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.interp.expect @@ -0,0 +1,9 @@ +error: The two expressions did not evaluate to the same value (in transaction `pop(1)`) + ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4.prot:53:15 + │ +53 │ assert_eq(DUT.m_axis_tvalid, 1'b1); + │ ^^^^^^^^^^^^^^^^^^^^^^^ LHS Value: 0, RHS Value: 1 + +Trace 0 execution failed. +---CODE--- +101 diff --git a/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_fixed.interp.expect b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_fixed.interp.expect new file mode 100644 index 00000000..f5f6cb49 --- /dev/null +++ b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_fixed.interp.expect @@ -0,0 +1 @@ +Trace 0 executed successfully! From 56dad4f6215fd35a22ce6f5a18231ec86dc7782a Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sun, 19 Jul 2026 13:13:49 -0400 Subject: [PATCH 39/55] Fix type error in Python scripts --- scripts/generate_runt_configs.py | 12 +++++++----- scripts/test_catalog.py | 2 +- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/scripts/generate_runt_configs.py b/scripts/generate_runt_configs.py index b91ec3bf..a7fda617 100644 --- a/scripts/generate_runt_configs.py +++ b/scripts/generate_runt_configs.py @@ -16,6 +16,7 @@ import subprocess from functools import lru_cache from pathlib import Path +from collections import Counter import test_catalog @@ -71,12 +72,13 @@ def replace_non_alphanumerics(value: object) -> str: def shared_bi_prot_files() -> frozenset[str]: - # Set of `.prot` files which are used by more than one BI test case + # Set of `.prot` files which are used by more than one BI test case # (e.g. Antmicro and the Brave New World test cases for fixed/buggy wvaeforms # that share a single .prot file) - from collections import Counter - counts = Counter(test_case["protocol"] for test_case in test_catalog.BI_CASES.values()) + counts = Counter( + str(test_case["protocol"]) for test_case in test_catalog.BI_CASES.values() + ) return frozenset(file for (file, num_cases) in counts.items() if num_cases > 1) @@ -309,8 +311,8 @@ def protocol_constructs(protocol_path: str) -> frozenset[str]: return frozenset(used) -# `.tx` files that are kept only for the AST interpreter -# and excluded from the graph interpreter for now +# `.tx` files that are kept only for the AST interpreter +# and excluded from the graph interpreter for now # (otherwise `.tx` files are shared between the AST & graph interpreters) EXCLUDED_GRAPH_INTERPRETER_TEST_CASES = { "tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.tx", diff --git a/scripts/test_catalog.py b/scripts/test_catalog.py index f746dac9..a9c0fdc8 100644 --- a/scripts/test_catalog.py +++ b/scripts/test_catalog.py @@ -824,7 +824,7 @@ "--time-unit", "ns", "--max-traces", - "20" + "20", ), }, "tests.fpga-debugging.axis-fifo-d11.d11_buggy": { From 81bc369b29d030fd2e387fe807be8fa482fe8302 Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sun, 19 Jul 2026 13:18:49 -0400 Subject: [PATCH 40/55] Update c4.prot --- .../fpga-debugging/axis-async-fifo-c4/c4.prot | 34 ++++++++----------- 1 file changed, 15 insertions(+), 19 deletions(-) diff --git a/tests/fpga-debugging/axis-async-fifo-c4/c4.prot b/tests/fpga-debugging/axis-async-fifo-c4/c4.prot index 24961d6d..606308cb 100644 --- a/tests/fpga-debugging/axis-async-fifo-c4/c4.prot +++ b/tests/fpga-debugging/axis-async-fifo-c4/c4.prot @@ -4,28 +4,27 @@ struct AsyncFifo { // but this DUT uses active-high instead in rst: u1, - // The Sender recieves VALID and DATA signals from the environment + // The Sender recieves valid and data signals from the environment // (data to be written, i.e. pushed to the FIFO), - // and outputs a READY signal, indicating that the FIFO can accept new data + // and outputs a ready signal, indicating that the FIFO can accept new data in s_axis_tdata: u8, in s_axis_tvalid: u1, out s_axis_tready: u1, - // The Receiver receives a READY signal from the environment + // The Receiver receives a ready signal from the environment // (environment is ready to read data that is popped from the FIFO) - // and outputs a VALID signal + the data being popped + // and outputs a valid signal + the data being popped. in m_axis_tready: u1, out m_axis_tvalid: u1, out m_axis_tdata: u8, } -// PUSH: Write data to FIFO via AXI-Stream receiver interface -// Performs data transfer when s_axis_tvalid and s_axis_tready are both 1 +// Write data to FIFO +// Push happens when s_axis_tvalid and s_axis_tready are both 1 prot push(data: u8) { DUT.rst := 1'b0; - // Update the data field and set receiver's valid bit to 1 to indicate - // that data transfer can occur + // Update the data field and set valid to 1 DUT.s_axis_tdata := data; DUT.s_axis_tvalid := 1'b1; @@ -34,11 +33,10 @@ prot push(data: u8) { step(); } - // One cycle for the transfer to complete step(); } -// POP: Read data from FIFO (the `data` argument is the data that is popped) +// Read data from FIFO (the `data` argument is the data that is popped) prot pop(data: u8) { DUT.rst := 1'b0; DUT.m_axis_tready := 1'b1; @@ -52,36 +50,34 @@ prot pop(data: u8) { // without waiting for it to become 1. assert_eq(DUT.m_axis_tvalid, 1'b1); + // Check that the data on DUT's output port is the data we expect to be popped assert_eq(DUT.m_axis_tdata, data); - // One cycle for the transfer to complete step(); } -// IDLE: No transaction occurs on the monitored interface +// No transaction occurs prot idle() { DUT.rst := 1'b0; - // Ensure no pushes from the sender by setting valid = 0 + // Ensure no pushes from the sender by setting the subordinate's valid = 0 DUT.s_axis_tvalid := 1'b0; - // Data is DontCare when valid = 0 + // Data is DontCare when subordinate's valid = 0 DUT.s_axis_tdata := X; - // Ensure no pops from the receiver by setting ready = 0 + // Ensure no pops on the receiver side by setting manager's ready = 0 DUT.m_axis_tready := 1'b0; step(); } -// RESET: Assert reset signal to initialize FIFO +// Asserts reset signal prot reset() { DUT.rst := 1'b1; - // Valid must be low when reset is asserted (AXI-Stream spec section 2.8.2) + // Valid must be low when reset is asserted (AXI-Stream spec section 2.7.2) DUT.s_axis_tvalid := 1'b0; - - // Valid must be low when reset is asserted (AXI-Stream spec section 2.8.2) assert_eq(DUT.m_axis_tvalid, 1'b0); step(); From 7ebd372c81b8e68a9dee06174b53057a68829456 Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sun, 19 Jul 2026 13:26:16 -0400 Subject: [PATCH 41/55] Update c4.prot --- tests/fpga-debugging/axis-async-fifo-c4/c4.prot | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/tests/fpga-debugging/axis-async-fifo-c4/c4.prot b/tests/fpga-debugging/axis-async-fifo-c4/c4.prot index 606308cb..4cde74ed 100644 --- a/tests/fpga-debugging/axis-async-fifo-c4/c4.prot +++ b/tests/fpga-debugging/axis-async-fifo-c4/c4.prot @@ -4,15 +4,21 @@ struct AsyncFifo { // but this DUT uses active-high instead in rst: u1, - // The Sender recieves valid and data signals from the environment - // (data to be written, i.e. pushed to the FIFO), - // and outputs a ready signal, indicating that the FIFO can accept new data + // Signals related to pushes. + // These signals are named in the DUT with the `s_axis` prefix, + // since they are for the subordinate (receiving data). + // The subordinate receives valid and data signals from the environment + // (data to be pushed to the FIFO), + // and outputs a ready signal to the environment. in s_axis_tdata: u8, in s_axis_tvalid: u1, out s_axis_tready: u1, - // The Receiver receives a ready signal from the environment - // (environment is ready to read data that is popped from the FIFO) + // Signals related to pops. + // These signals are named in the DUT with the `m_axis` prefix, + // since they are for the manager (producing data). + // The manager receives a ready signal from the environment + // (indicating that the environment is ready to read data that is popped from the FIFO) // and outputs a valid signal + the data being popped. in m_axis_tready: u1, out m_axis_tvalid: u1, From 8d2041b2ec59562b3813eda5af6bb2f70381d61a Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sun, 19 Jul 2026 13:26:55 -0400 Subject: [PATCH 42/55] Update expect test output --- .../axis-async-fifo-c4/expects/c4_buggy.interp.expect | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.interp.expect b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.interp.expect index 9a4c59d6..9731d952 100644 --- a/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.interp.expect +++ b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.interp.expect @@ -1,7 +1,7 @@ error: The two expressions did not evaluate to the same value (in transaction `pop(1)`) - ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4.prot:53:15 + ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4.prot:57:15 │ -53 │ assert_eq(DUT.m_axis_tvalid, 1'b1); +57 │ assert_eq(DUT.m_axis_tvalid, 1'b1); │ ^^^^^^^^^^^^^^^^^^^^^^^ LHS Value: 0, RHS Value: 1 Trace 0 execution failed. From 483685e27afe80dd571e67d66763470237d75e34 Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sun, 19 Jul 2026 13:59:57 -0400 Subject: [PATCH 43/55] update expect test output --- .../expects/c4_buggy.bi.expect | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.bi.expect b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.bi.expect index 583da898..25cdd3ae 100644 --- a/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.bi.expect +++ b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.bi.expect @@ -3,9 +3,9 @@ trace { reset(); // [time: 0ns -> 25ns] } error: [reset@1] executing step 0 of the transaction: 0 != 1 - ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4.prot:79:5 + ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4.prot:83:5 │ -79 │ DUT.rst := 1'b1; +83 │ DUT.rst := 1'b1; │ ^^^^^^^^^^^^^^^^ [reset@1] executing step 0 of the transaction: 0 != 1 @@ -14,9 +14,9 @@ trace { reset(); // [time: 0ns -> 25ns] } error: [idle@1] executing step 0 of the transaction: 1 != 0 - ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4.prot:72:5 + ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4.prot:76:5 │ -72 │ DUT.m_axis_tready := 1'b0; +76 │ DUT.m_axis_tready := 1'b0; │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [idle@1] executing step 0 of the transaction: 1 != 0 @@ -25,9 +25,9 @@ trace { reset(); // [time: 0ns -> 25ns] } error: [pop@1] executing step 0 of the transaction: 0 != 1 - ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4.prot:53:5 + ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4.prot:57:5 │ -53 │ assert_eq(DUT.m_axis_tvalid, 1'b1); +57 │ assert_eq(DUT.m_axis_tvalid, 1'b1); │ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ [pop@1] executing step 0 of the transaction: 0 != 1 @@ -36,9 +36,9 @@ trace { reset(); // [time: 0ns -> 25ns] } error: [push@1] executing step 0 of the transaction: 0 != 1 - ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4.prot:30:5 + ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4.prot:35:5 │ -30 │ DUT.s_axis_tvalid := 1'b1; +35 │ DUT.s_axis_tvalid := 1'b1; │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [push@1] executing step 0 of the transaction: 0 != 1 ---CODE--- From 37b8e6e0cca408ef2b11f7054f39d1c98cb909de Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sun, 19 Jul 2026 14:33:20 -0400 Subject: [PATCH 44/55] Update DUT files + waveform screenshot --- .../axis-async-fifo-c4/c4_buggy.v | 8 +---- .../axis-async-fifo-c4/c4_buggy_waveform.png | Bin 67399 -> 64796 bytes .../axis-async-fifo-c4/c4_fixed.v | 32 +----------------- 3 files changed, 2 insertions(+), 38 deletions(-) diff --git a/tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.v b/tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.v index eaab568f..3ec649ea 100644 --- a/tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.v +++ b/tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.v @@ -121,13 +121,7 @@ assign {output_axis_tlast, output_axis_tuser, output_axis_tdata} = data_out_reg; // - However, the write pointer `input_rst_sync3` (used in line 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zx6&aba*J@mFv$$nPyVz);UxinvrFR7h+#$Wp4T?x7r)3RnM0pXUdWhd{`mWD{LXo* zKc)dVi5@F+iXlVT!Gt@Ze@f*>NKNz9uS;aI2Oa*^5yiZh5~~WgDLv*MnN0lZe}@$J z*VM>}>OP3drhiXcna+}`O0mQ3-v8B5Nb92zm3OOlypYiY1JmWTFHcOxH}A~A)3v$X zh=eT^&1=3!LZ38;OweTAf9UXaJoG;iuD0vy7I+~*HyxTt=#wM^NiCuE1AHd%jsD+% zeb4f55@AZ3%>TOF{vSU@2Y%|muLZ8+f3Mg7-bC;Jdr$o5ar*B)@!xym|94&e@COsS X?!E~TQ7HT$@JCis@nwm)vETmyr$_*a From b2e53f300ca8e83a5ff0a4d8e003b46926780f81 Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sun, 19 Jul 2026 14:57:20 -0400 Subject: [PATCH 46/55] Update Runt config script --- runt/fail/runt.toml | 18 +++++++++++++ runt/graph_interp/runt.toml | 27 +++++++++++++++++++ runt/waveform/runt.toml | 27 +++++++++++++++++++ scripts/generate_runt_configs.py | 11 -------- .../expects/c4_fixed.graph_interp.expect | 1 + 5 files changed, 73 insertions(+), 11 deletions(-) create mode 100644 tests/fpga-debugging/axis-async-fifo-c4/expects/c4_fixed.graph_interp.expect diff --git a/runt/fail/runt.toml b/runt/fail/runt.toml index 7c86432d..f3e88462 100644 --- a/runt/fail/runt.toml +++ b/runt/fail/runt.toml @@ -324,6 +324,24 @@ expect_dir = "../../tests/fifo/expects" expect_name = "push_pop_conflict.fail.expect" cmd = "cd ../.. && target/debug/graph-interp --transactions tests/fifo/push_pop_conflict.tx --transition-system --verilog tests/fifo/bsg_mem_1rw_sync.v tests/fifo/bsg_mem_1rw_sync_synth.v tests/fifo/bsg_circular_ptr.v tests/fifo/bsg_fifo_1rw_large.v tests/fifo/fifo_wrapper.v --protocol tests/fifo/fifo.prot --module fifo_wrapper 2>/dev/null" +[[tests]] +name = "fail.tests_fpga_debugging_axis_async_fifo_c4_c4_buggy.c4_buggy_fail.graph" +paths = [ + "../../tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.tx", +] +expect_dir = "../../tests/fpga-debugging/axis-async-fifo-c4/expects" +expect_name = "c4_buggy.fail.expect" +cmd = "cd ../.. && target/debug/graph-interp --transactions tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.tx --respect-forks --determinize --brief-graph-errors --verilog tests/fpga-debugging/axis-async-fifo-c4/c4_dut.v tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.v --protocol tests/fpga-debugging/axis-async-fifo-c4/c4.prot --module c4_dut 2>/dev/null" + +[[tests]] +name = "fail.tests_fpga_debugging_axis_async_fifo_c4_c4_buggy.c4_buggy_fail.ts" +paths = [ + "../../tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.tx", +] +expect_dir = "../../tests/fpga-debugging/axis-async-fifo-c4/expects" +expect_name = "c4_buggy.fail.expect" +cmd = "cd ../.. && target/debug/graph-interp --transactions tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.tx --transition-system --verilog tests/fpga-debugging/axis-async-fifo-c4/c4_dut.v tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.v --protocol tests/fpga-debugging/axis-async-fifo-c4/c4.prot --module c4_dut 2>/dev/null" + [[tests]] name = "fail.tests_identities_identity_d1_explicit_fork.explicit_fork_fail.graph" paths = [ diff --git a/runt/graph_interp/runt.toml b/runt/graph_interp/runt.toml index 45563474..373c5075 100644 --- a/runt/graph_interp/runt.toml +++ b/runt/graph_interp/runt.toml @@ -531,6 +531,33 @@ expect_dir = "../../tests/fifo/expects" expect_name = "push_pop_identity_ok.graph_interp.expect" cmd = "cd ../.. && target/debug/graph-interp --transactions tests/fifo/push_pop_identity_ok.tx --verilog tests/fifo/bsg_mem_1rw_sync.v tests/fifo/bsg_mem_1rw_sync_synth.v tests/fifo/bsg_circular_ptr.v tests/fifo/bsg_fifo_1rw_large.v tests/fifo/fifo_wrapper.v --protocol tests/fifo/fifo.prot --module fifo_wrapper --respect-forks --determinize 2>/dev/null" +[[tests]] +name = "graph_interp.tests_fpga_debugging_axis_async_fifo_c4_c4_fixed.c4_fixed_graph_interp" +paths = [ + "../../tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.tx", +] +expect_dir = "../../tests/fpga-debugging/axis-async-fifo-c4/expects" +expect_name = "c4_fixed.graph_interp.expect" +cmd = "cd ../.. && target/debug/graph-interp --transactions tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.tx --verilog tests/fpga-debugging/axis-async-fifo-c4/c4_dut.v tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.v --protocol tests/fpga-debugging/axis-async-fifo-c4/c4.prot --module c4_dut 2>/dev/null" + +[[tests]] +name = "graph_interp.tests_fpga_debugging_axis_async_fifo_c4_c4_fixed.c4_fixed_graph_interp.contract_edges" +paths = [ + "../../tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.tx", +] +expect_dir = "../../tests/fpga-debugging/axis-async-fifo-c4/expects" +expect_name = "c4_fixed.graph_interp.expect" +cmd = "cd ../.. && target/debug/graph-interp --transactions tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.tx --verilog tests/fpga-debugging/axis-async-fifo-c4/c4_dut.v tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.v --protocol tests/fpga-debugging/axis-async-fifo-c4/c4.prot --module c4_dut --contract-edges 2>/dev/null" + +[[tests]] +name = "graph_interp.tests_fpga_debugging_axis_async_fifo_c4_c4_fixed.c4_fixed_graph_interp.respect_forks" +paths = [ + "../../tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.tx", +] +expect_dir = "../../tests/fpga-debugging/axis-async-fifo-c4/expects" +expect_name = "c4_fixed.graph_interp.expect" +cmd = "cd ../.. && target/debug/graph-interp --transactions tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.tx --verilog tests/fpga-debugging/axis-async-fifo-c4/c4_dut.v tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.v --protocol tests/fpga-debugging/axis-async-fifo-c4/c4.prot --module c4_dut --respect-forks --determinize 2>/dev/null" + [[tests]] name = "graph_interp.tests_identities_identity_d0_passthrough_combdep.passthrough_combdep_graph_interp" paths = [ diff --git a/runt/waveform/runt.toml b/runt/waveform/runt.toml index c18c9309..32c34273 100644 --- a/runt/waveform/runt.toml +++ b/runt/waveform/runt.toml @@ -513,6 +513,33 @@ expect_dir = "../../tests/fifo/expects" expect_name = "push_pop_identity_ok.waveform.expect" cmd = "cd ../.. && target/debug/graph-interp --transactions tests/fifo/push_pop_identity_ok.tx --transition-system --ascii-waveform --verilog tests/fifo/bsg_mem_1rw_sync.v tests/fifo/bsg_mem_1rw_sync_synth.v tests/fifo/bsg_circular_ptr.v tests/fifo/bsg_fifo_1rw_large.v tests/fifo/fifo_wrapper.v --protocol tests/fifo/fifo.prot --module fifo_wrapper 2>/dev/null" +[[tests]] +name = "waveform.tests_fpga_debugging_axis_async_fifo_c4_c4_fixed.c4_fixed_waveform.ast" +paths = [ + "../../tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.tx", +] +expect_dir = "../../tests/fpga-debugging/axis-async-fifo-c4/expects" +expect_name = "c4_fixed.waveform.expect" +cmd = "cd ../.. && target/debug/protocols-interp --color never --transactions tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.tx --ascii-waveform --verilog tests/fpga-debugging/axis-async-fifo-c4/c4_dut.v tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.v --protocol tests/fpga-debugging/axis-async-fifo-c4/c4.prot --module c4_dut 2>/dev/null" + +[[tests]] +name = "waveform.tests_fpga_debugging_axis_async_fifo_c4_c4_fixed.c4_fixed_waveform.graph" +paths = [ + "../../tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.tx", +] +expect_dir = "../../tests/fpga-debugging/axis-async-fifo-c4/expects" +expect_name = "c4_fixed.waveform.expect" +cmd = "cd ../.. && target/debug/graph-interp --transactions tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.tx --respect-forks --determinize --ascii-waveform --verilog tests/fpga-debugging/axis-async-fifo-c4/c4_dut.v tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.v --protocol tests/fpga-debugging/axis-async-fifo-c4/c4.prot --module c4_dut 2>/dev/null" + +[[tests]] +name = "waveform.tests_fpga_debugging_axis_async_fifo_c4_c4_fixed.c4_fixed_waveform.ts" +paths = [ + "../../tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.tx", +] +expect_dir = "../../tests/fpga-debugging/axis-async-fifo-c4/expects" +expect_name = "c4_fixed.waveform.expect" +cmd = "cd ../.. && target/debug/graph-interp --transactions tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.tx --transition-system --ascii-waveform --verilog tests/fpga-debugging/axis-async-fifo-c4/c4_dut.v tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.v --protocol tests/fpga-debugging/axis-async-fifo-c4/c4.prot --module c4_dut 2>/dev/null" + [[tests]] name = "waveform.tests_identities_identity_d0_passthrough_combdep.passthrough_combdep_waveform.ast" paths = [ diff --git a/scripts/generate_runt_configs.py b/scripts/generate_runt_configs.py index a7fda617..8bcba52d 100644 --- a/scripts/generate_runt_configs.py +++ b/scripts/generate_runt_configs.py @@ -311,15 +311,6 @@ def protocol_constructs(protocol_path: str) -> frozenset[str]: return frozenset(used) -# `.tx` files that are kept only for the AST interpreter -# and excluded from the graph interpreter for now -# (otherwise `.tx` files are shared between the AST & graph interpreters) -EXCLUDED_GRAPH_INTERPRETER_TEST_CASES = { - "tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.tx", - "tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.tx", -} - - def graph_interp_cases(cases: list[dict]) -> list[dict]: """Passing tx cases whose protocol uses no for-in or repeat loop.""" # Loop constructs the graph interpreter cannot handle (AST construct names). @@ -329,7 +320,6 @@ def graph_interp_cases(cases: list[dict]) -> list[dict]: c for c in cases if c["expected"] == "pass" - and c["path"] not in EXCLUDED_GRAPH_INTERPRETER_TEST_CASES and not graph_interp_unsupported & protocol_constructs(c["protocol_path"]) ] return sorted(selected, key=lambda c: c["path"]) @@ -362,7 +352,6 @@ def fail_cases(cases: list[dict]) -> list[dict]: c for c in cases if c["expected"] in runtime_failures - and c["path"] not in EXCLUDED_GRAPH_INTERPRETER_TEST_CASES and not graph_interp_unsupported & protocol_constructs(c["protocol_path"]) ] return sorted(selected, key=lambda c: c["path"]) diff --git a/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_fixed.graph_interp.expect b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_fixed.graph_interp.expect new file mode 100644 index 00000000..f5f6cb49 --- /dev/null +++ b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_fixed.graph_interp.expect @@ -0,0 +1 @@ +Trace 0 executed successfully! From ce64dda2953d94bd9d822cc62663ddfc8ba1ab7f Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sun, 19 Jul 2026 15:03:08 -0400 Subject: [PATCH 47/55] Add a missing waveform.expect file --- .../axis-async-fifo-c4/expects/c4_fixed.waveform.expect | 8 ++++++++ 1 file changed, 8 insertions(+) create mode 100644 tests/fpga-debugging/axis-async-fifo-c4/expects/c4_fixed.waveform.expect diff --git a/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_fixed.waveform.expect b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_fixed.waveform.expect new file mode 100644 index 00000000..b8d4a3cc --- /dev/null +++ b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_fixed.waveform.expect @@ -0,0 +1,8 @@ +Trace 0 executed successfully! +m_axis_tready x 0 x x x x x 0 0 1 1 +s_axis_tvalid 0 0 1 1 1 1 1 0 0 x x +s_axis_tdata[7:0] x x 1 1 1 2 3 x x x x +rst 1 0 0 0 0 0 0 0 0 0 0 +m_axis_tdata[7:0] 0 0 0 0 0 0 0 0 1 1 2 +m_axis_tvalid 0 0 0 0 0 0 0 0 1 1 1 +s_axis_tready 0 0 0 0 1 1 1 1 1 1 1 From 10ccca5d401af8c05b012c5249c7a766022e3411 Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sun, 19 Jul 2026 17:25:57 -0400 Subject: [PATCH 48/55] Add missing Runt expect file --- .../axis-async-fifo-c4/expects/c4_buggy.fail.expect | 1 + 1 file changed, 1 insertion(+) create mode 100644 tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.fail.expect diff --git a/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.fail.expect b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.fail.expect new file mode 100644 index 00000000..677fced5 --- /dev/null +++ b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.fail.expect @@ -0,0 +1 @@ +Assertion failure in cycle 7. From 81e02fbd8f9003a67b344cee3baacc6accc458ed Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sun, 19 Jul 2026 20:44:58 -0400 Subject: [PATCH 49/55] Clean up .tx files --- tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.tx | 1 - tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.tx | 1 - 2 files changed, 2 deletions(-) diff --git a/tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.tx b/tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.tx index cbef167e..32ad4ac6 100644 --- a/tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.tx +++ b/tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.tx @@ -5,7 +5,6 @@ trace { push(2); push(3); idle(); - idle(); pop(1); pop(2); } diff --git a/tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.tx b/tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.tx index 010dca97..e56724b5 100644 --- a/tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.tx +++ b/tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.tx @@ -5,7 +5,6 @@ trace { push(2); push(3); idle(); - idle(); pop(1); pop(2); } \ No newline at end of file From 9830177759906b4a71c60bd5827cbedf87b30d2d Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Sun, 19 Jul 2026 20:49:15 -0400 Subject: [PATCH 50/55] Update Runt expect tests --- .../expects/c4_buggy.fail.expect | 2 +- .../expects/c4_fixed.waveform.expect | 14 +++++++------- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.fail.expect b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.fail.expect index 677fced5..19b70357 100644 --- a/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.fail.expect +++ b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.fail.expect @@ -1 +1 @@ -Assertion failure in cycle 7. +Assertion failure in cycle 6. diff --git a/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_fixed.waveform.expect b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_fixed.waveform.expect index b8d4a3cc..7b09eb0c 100644 --- a/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_fixed.waveform.expect +++ b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_fixed.waveform.expect @@ -1,8 +1,8 @@ Trace 0 executed successfully! -m_axis_tready x 0 x x x x x 0 0 1 1 -s_axis_tvalid 0 0 1 1 1 1 1 0 0 x x -s_axis_tdata[7:0] x x 1 1 1 2 3 x x x x -rst 1 0 0 0 0 0 0 0 0 0 0 -m_axis_tdata[7:0] 0 0 0 0 0 0 0 0 1 1 2 -m_axis_tvalid 0 0 0 0 0 0 0 0 1 1 1 -s_axis_tready 0 0 0 0 1 1 1 1 1 1 1 +m_axis_tready x 0 x x x x x 0 1 1 +s_axis_tvalid 0 0 1 1 1 1 1 0 x x +s_axis_tdata[7:0] x x 1 1 1 2 3 x x x +rst 1 0 0 0 0 0 0 0 0 0 +m_axis_tdata[7:0] 0 0 0 0 0 0 0 0 1 2 +m_axis_tvalid 0 0 0 0 0 0 0 0 1 1 +s_axis_tready 0 0 0 0 1 1 1 1 1 1 From 23db86656ae5e6329ba7dee08a80b0464746919f Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Wed, 22 Jul 2026 17:49:59 -0400 Subject: [PATCH 51/55] Regenerate Runt config after resolving merge conflict in script --- runt/bi/runt.toml | 16 ++++++++-------- scripts/generate_runt_configs.py | 18 +----------------- 2 files changed, 9 insertions(+), 25 deletions(-) diff --git a/runt/bi/runt.toml b/runt/bi/runt.toml index 294e3720..83187897 100644 --- a/runt/bi/runt.toml +++ b/runt/bi/runt.toml @@ -2233,39 +2233,39 @@ expect_name = "s4_fixed.bi.expect" cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axi-burst-s4/s4_fixed.prot --wave tests/fpga-debugging/axi-burst-s4/s4_fixed.vcd --instances TOP.test_l2_cache_wait_state.axi_bus:WriteSubordinate --sample-posedge TOP.test_l2_cache_wait_state.clk --show-waveform-time --time-unit ns 2>&1" [[tests]] -name = "bi.tests_fpga_debugging_axi_lite_s1_s1_buggy.s1_buggy_bi" +name = "bi.tests_fpga_debugging_axi_lite_s1_s1_buggy.s1_buggy_workload2_bi" paths = [ "../../tests/fpga-debugging/axi-lite-s1/s1_buggy.prot", ] expect_dir = "../../tests/fpga-debugging/axi-lite-s1/expects" -expect_name = "s1_buggy.bi.expect" +expect_name = "s1_buggy_workload2.bi.expect" cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axi-lite-s1/s1_buggy.prot --wave tests/fpga-debugging/axi-lite-s1/s1_buggy_workload2.vcd --instances TOP.testbench.UUT:WriteSubordinate TOP.testbench.UUT:ReadSubordinate --sample-posedge TOP.testbench.UUT.S_AXI_ACLK --show-waveform-time --time-unit ns --include-idle 2>&1" [[tests]] -name = "bi.tests_fpga_debugging_axi_lite_s1_s1_buggy_workload_1.s1_buggy_workload_1_bi" +name = "bi.tests_fpga_debugging_axi_lite_s1_s1_buggy_workload_1.s1_buggy_workload1_bi" paths = [ "../../tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot", ] expect_dir = "../../tests/fpga-debugging/axi-lite-s1/expects" -expect_name = "s1_buggy_workload_1.bi.expect" +expect_name = "s1_buggy_workload1.bi.expect" cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot --wave tests/fpga-debugging/axi-lite-s1/s1_buggy_workload1.vcd --instances TOP.testbench.UUT:WriteSubordinate TOP.testbench.UUT:ReadSubordinate --sample-posedge TOP.testbench.UUT.S_AXI_ACLK --show-waveform-time --time-unit ns --include-idle 2>&1" [[tests]] -name = "bi.tests_fpga_debugging_axi_lite_s1_s1_fixed.s1_fixed_bi" +name = "bi.tests_fpga_debugging_axi_lite_s1_s1_fixed.s1_fixed_workload2_bi" paths = [ "../../tests/fpga-debugging/axi-lite-s1/s1_fixed.prot", ] expect_dir = "../../tests/fpga-debugging/axi-lite-s1/expects" -expect_name = "s1_fixed.bi.expect" +expect_name = "s1_fixed_workload2.bi.expect" cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axi-lite-s1/s1_fixed.prot --wave tests/fpga-debugging/axi-lite-s1/s1_fixed_workload2.vcd --instances TOP.testbench.UUT:WriteSubordinate TOP.testbench.UUT:ReadSubordinate --sample-posedge TOP.testbench.UUT.S_AXI_ACLK --show-waveform-time --time-unit ns --include-idle 2>&1" [[tests]] -name = "bi.tests_fpga_debugging_axi_lite_s1_s1_fixed_workload_1.s1_fixed_workload_1_bi" +name = "bi.tests_fpga_debugging_axi_lite_s1_s1_fixed_workload_1.s1_fixed_workload1_bi" paths = [ "../../tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot", ] expect_dir = "../../tests/fpga-debugging/axi-lite-s1/expects" -expect_name = "s1_fixed_workload_1.bi.expect" +expect_name = "s1_fixed_workload1.bi.expect" cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot --wave tests/fpga-debugging/axi-lite-s1/s1_fixed_workload1.vcd --instances TOP.testbench.UUT:WriteSubordinate TOP.testbench.UUT:ReadSubordinate --sample-posedge TOP.testbench.UUT.S_AXI_ACLK --show-waveform-time --time-unit ns --include-idle 2>&1" [[tests]] diff --git a/scripts/generate_runt_configs.py b/scripts/generate_runt_configs.py index f6601d3e..7aee54f9 100644 --- a/scripts/generate_runt_configs.py +++ b/scripts/generate_runt_configs.py @@ -16,7 +16,6 @@ import subprocess from functools import lru_cache from pathlib import Path -from collections import Counter import test_catalog @@ -74,28 +73,13 @@ def replace_non_alphanumerics(value: object) -> str: return re.sub(r"[^A-Za-z0-9]+", "_", text).strip("_") or "default" -def shared_bi_prot_files() -> frozenset[str]: - # Set of `.prot` files which are used by more than one BI test case - # (e.g. Antmicro and the Brave New World test cases for fixed/buggy wvaeforms - # that share a single .prot file) - - counts = Counter() - for test_case in test_catalog.BI_CASES.values(): - if "protocol" in test_case: - counts[str(test_case["protocol"])] += 1 - else: - for p in test_case["protocols"]: - counts[str(p)] += 1 - return frozenset(file for (file, num_cases) in counts.items() if num_cases > 1) - - def case_stem(case: dict) -> str: # Antmicro & Brave New World test cases for the BI share the same `.prot` # file but have multiple waveforms, so we use the waveform files' # names to identify a particular test, otherwise we use the `.prot` file's stem # to identify a test wave = case.get("wave") - if wave and any(p in shared_bi_prot_files() for p in case["paths"]): + if wave and ("antmicro" in wave or "fpga-debugging" in wave): return Path(wave).stem stem = Path(case["paths"][0]).stem return stem.removesuffix(".bi") From 9f66496ad3820fd3962016ffbfda87a2f8c0faec Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Wed, 22 Jul 2026 17:50:15 -0400 Subject: [PATCH 52/55] Add missing Runt expect files so that CI passes (these are for a different BNW test case) --- .../expects/s1_buggy_workload1.bi.expect | 85 +++++++++++++++++++ .../expects/s1_buggy_workload2.bi.expect | 28 ++++++ .../expects/s1_fixed_workload1.bi.expect | 77 +++++++++++++++++ .../expects/s1_fixed_workload2.bi.expect | 12 +++ 4 files changed, 202 insertions(+) create mode 100644 tests/fpga-debugging/axi-lite-s1/expects/s1_buggy_workload1.bi.expect create mode 100644 tests/fpga-debugging/axi-lite-s1/expects/s1_buggy_workload2.bi.expect create mode 100644 tests/fpga-debugging/axi-lite-s1/expects/s1_fixed_workload1.bi.expect create mode 100644 tests/fpga-debugging/axi-lite-s1/expects/s1_fixed_workload2.bi.expect diff --git a/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy_workload1.bi.expect b/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy_workload1.bi.expect new file mode 100644 index 00000000..f3ec1c05 --- /dev/null +++ b/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy_workload1.bi.expect @@ -0,0 +1,85 @@ +// trace 0 +trace { + idle(); // [time: 0ns -> 25ns] + write_stalled(64, 2147483648, 0); // [time: 25ns -> 75ns] + write_stalled(64, 2147483648, 0); // [time: 75ns -> 100ns] +} + +// trace 1 +trace { + write_stalled(64, 2147483648, 1); // [time: 0ns -> 75ns] + write_stalled(64, 2147483648, 0); // [time: 75ns -> 100ns] +} +// trace 0 +trace { + idle(); // [time: 0ns -> 25ns] + read_v1(64, 0); // [time: 25ns -> 100ns] +} +error: [read_v2@4] executing step 0 of the transaction: 0 != 1 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot:161:5 + │ +161 │ DUT.S_AXI_ARVALID := 1'b1; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@4] executing step 0 of the transaction: 0 != 1 + + +// trace 1 +trace { + idle(); // [time: 0ns -> 25ns] + read_v1(64, 0); // [time: 25ns -> 100ns] +} +error: [read_v1@4] executing step 0 of the transaction: 0 != 1 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot:124:5 + │ +124 │ DUT.S_AXI_ARVALID := 1'b1; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v1@4] executing step 0 of the transaction: 0 != 1 + + +// trace 2 +trace { + idle(); // [time: 0ns -> 25ns] + read_v1(64, 0); // [time: 25ns -> 100ns] +} +error: [idle@4] executing step 0 of the transaction: 1 != 0 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot:108:5 + │ +108 │ DUT.S_AXI_RREADY := 1'b0; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [idle@4] executing step 0 of the transaction: 1 != 0 + + +// trace 3 +trace { + idle(); // [time: 0ns -> 25ns] + read_v2(64, 0, 0); // [time: 25ns -> 100ns] +} +error: [read_v2@4] executing step 0 of the transaction: 0 != 1 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot:161:5 + │ +161 │ DUT.S_AXI_ARVALID := 1'b1; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@4] executing step 0 of the transaction: 0 != 1 + + +// trace 4 +trace { + idle(); // [time: 0ns -> 25ns] + read_v2(64, 0, 0); // [time: 25ns -> 100ns] +} +error: [read_v1@4] executing step 0 of the transaction: 0 != 1 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot:124:5 + │ +124 │ DUT.S_AXI_ARVALID := 1'b1; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v1@4] executing step 0 of the transaction: 0 != 1 + + +// trace 5 +trace { + idle(); // [time: 0ns -> 25ns] + read_v2(64, 0, 0); // [time: 25ns -> 100ns] +} +error: [idle@4] executing step 0 of the transaction: 1 != 0 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot:108:5 + │ +108 │ DUT.S_AXI_RREADY := 1'b0; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [idle@4] executing step 0 of the transaction: 1 != 0 + +---CODE--- +1 diff --git a/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy_workload2.bi.expect b/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy_workload2.bi.expect new file mode 100644 index 00000000..3b9d8bbd --- /dev/null +++ b/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy_workload2.bi.expect @@ -0,0 +1,28 @@ +// trace 0 +trace { + idle(); // [time: 0ns -> 25ns] + write(64, 2147483648, 0, 0); // [time: 25ns -> 100ns] +} +// trace 0 +trace { + idle(); // [time: 0ns -> 25ns] +} +error: [read_v2@11?1!] executing step 3 of the transaction: 1 != 0 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy.prot:169:5 + │ +169 │ assert_eq(DUT.S_AXI_ARREADY, 1'b0); + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@11?1!] executing step 3 of the transaction: 1 != 0 + + +// trace 1 +trace { + idle(); // [time: 0ns -> 25ns] +} +error: [read_v2@11?2?] executing step 3 of the transaction: 1 != 0 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy.prot:163:9 + │ +163 │ DUT.S_AXI_RREADY := 1'b0; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@11?2?] executing step 3 of the transaction: 1 != 0 + +---CODE--- +1 diff --git a/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed_workload1.bi.expect b/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed_workload1.bi.expect new file mode 100644 index 00000000..5b0357ce --- /dev/null +++ b/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed_workload1.bi.expect @@ -0,0 +1,77 @@ +// trace 0 +trace { + idle(); // [time: 0ns -> 25ns] +} +// trace 0 +trace { + idle(); // [time: 0ns -> 25ns] + read_v1(64, 0); // [time: 25ns -> 100ns] +} +error: [read_v2@4] executing step 0 of the transaction: 0 != 1 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot:161:5 + │ +161 │ DUT.S_AXI_ARVALID := 1'b1; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@4] executing step 0 of the transaction: 0 != 1 + + +// trace 1 +trace { + idle(); // [time: 0ns -> 25ns] + read_v1(64, 0); // [time: 25ns -> 100ns] +} +error: [read_v1@4] executing step 0 of the transaction: 0 != 1 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot:124:5 + │ +124 │ DUT.S_AXI_ARVALID := 1'b1; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v1@4] executing step 0 of the transaction: 0 != 1 + + +// trace 2 +trace { + idle(); // [time: 0ns -> 25ns] + read_v1(64, 0); // [time: 25ns -> 100ns] +} +error: [idle@4] executing step 0 of the transaction: 1 != 0 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot:108:5 + │ +108 │ DUT.S_AXI_RREADY := 1'b0; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [idle@4] executing step 0 of the transaction: 1 != 0 + + +// trace 3 +trace { + idle(); // [time: 0ns -> 25ns] + read_v2(64, 0, 0); // [time: 25ns -> 100ns] +} +error: [read_v2@4] executing step 0 of the transaction: 0 != 1 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot:161:5 + │ +161 │ DUT.S_AXI_ARVALID := 1'b1; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@4] executing step 0 of the transaction: 0 != 1 + + +// trace 4 +trace { + idle(); // [time: 0ns -> 25ns] + read_v2(64, 0, 0); // [time: 25ns -> 100ns] +} +error: [read_v1@4] executing step 0 of the transaction: 0 != 1 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot:124:5 + │ +124 │ DUT.S_AXI_ARVALID := 1'b1; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v1@4] executing step 0 of the transaction: 0 != 1 + + +// trace 5 +trace { + idle(); // [time: 0ns -> 25ns] + read_v2(64, 0, 0); // [time: 25ns -> 100ns] +} +error: [idle@4] executing step 0 of the transaction: 1 != 0 + ┌─ tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot:108:5 + │ +108 │ DUT.S_AXI_RREADY := 1'b0; + │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [idle@4] executing step 0 of the transaction: 1 != 0 + +---CODE--- +1 diff --git a/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed_workload2.bi.expect b/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed_workload2.bi.expect new file mode 100644 index 00000000..ecf4be3e --- /dev/null +++ b/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed_workload2.bi.expect @@ -0,0 +1,12 @@ +// trace 0 +trace { + idle(); // [time: 0ns -> 25ns] + write(64, 2147483648, 0, 0); // [time: 25ns -> 100ns] +} +// trace 0 +trace { + idle(); // [time: 0ns -> 25ns] + read_v2(68, 0, 1); // [time: 25ns -> 125ns] + idle(); // [time: 125ns -> 150ns] + idle(); // [time: 150ns -> 150ns] +} From 01a3508f54499ab62a4a3874d89f6f55df45de08 Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Wed, 22 Jul 2026 17:55:56 -0400 Subject: [PATCH 53/55] Fix merge conflict in Rust code --- bi/src/bi.rs | 13 ++++--------- bi/src/main.rs | 10 +++++++++- bi/src/proto_trace.rs | 35 +++-------------------------------- 3 files changed, 16 insertions(+), 42 deletions(-) diff --git a/bi/src/bi.rs b/bi/src/bi.rs index 69eca2fb..918e8d4d 100644 --- a/bi/src/bi.rs +++ b/bi/src/bi.rs @@ -638,14 +638,8 @@ impl Thread { self.effectful_stmt_in_step = true; Fork } else { - self.failures.push(Failure { - thread_local_step: self.step, - proto_id: ti.proto_id, - thread_name: self.name.clone(), - stmt, - kind: FailureKind::ForkBeforeStep, - }); - Failed + eprintln!("[{}] Cannot fork at step zero!", self.name); + std::process::exit(1); } } Stmt::While(cond, body) => { @@ -838,7 +832,8 @@ impl Thread { proto_id: ti.proto_id, thread_name: self.name.clone(), stmt, - kind: FailureKind::SignalValueMismatch { lhs: a, rhs: b }, + a, + b, }) } } diff --git a/bi/src/main.rs b/bi/src/main.rs index 62a27b61..1bffb6a3 100644 --- a/bi/src/main.rs +++ b/bi/src/main.rs @@ -11,6 +11,7 @@ mod signal_trace; use crate::bi::*; use crate::proto_trace::*; use crate::signal_trace::*; +use baa::BitVecOps; use clap::{ColorChoice, Parser}; use clap_verbosity_flag::{Verbosity, WarnLevel}; use protocols::frontend; @@ -202,7 +203,14 @@ fn main() { for fail in fails { let proto = &protos[fail.proto_id]; - d.emit_diagnostic_stmt(proto, &fail.stmt, &fail.message(), Level::Error); + let msg = format!( + "[{}] executing step {} of the transaction: {} != {}", + fail.thread_name, + fail.thread_local_step, + fail.a.to_hex_str(), + fail.b.to_hex_str() + ); + d.emit_diagnostic_stmt(proto, &fail.stmt, &msg, Level::Error); } } } else { diff --git a/bi/src/proto_trace.rs b/bi/src/proto_trace.rs index 48e1d4bf..ca93b1c1 100644 --- a/bi/src/proto_trace.rs +++ b/bi/src/proto_trace.rs @@ -4,7 +4,7 @@ //! # Protocol Traces and Error Reporting -use baa::{BitVecOps, BitVecValue}; +use baa::BitVecValue; use protocols::Value; use protocols::frontend::ast::StmtId; @@ -150,35 +150,6 @@ pub struct Failure { pub proto_id: usize, pub thread_name: String, pub stmt: StmtId, - /// The specific kind of failure - pub kind: FailureKind, -} - -/// The specific reason why the BI failed -/// (e.g. a constraint was violated, or a `fork` was encountered before a `step`, etc.) -#[derive(Debug, Clone, PartialEq)] -pub enum FailureKind { - /// When the value of a signal in the waveform differs from what we expect - /// (i.e. a constraint is violated) - SignalValueMismatch { lhs: BitVecValue, rhs: BitVecValue }, - /// A `fork` was reached before any `step`s have been called - ForkBeforeStep, -} - -impl Failure { - /// Error message portion of the failure (appears in diagnostics) - pub fn message(&self) -> String { - match &self.kind { - FailureKind::SignalValueMismatch { lhs, rhs } => format!( - "[{}] executing step {} of the transaction: {} != {}", - self.thread_name, - self.thread_local_step, - lhs.to_hex_str(), - rhs.to_hex_str(), - ), - FailureKind::ForkBeforeStep => { - format!("[{}] cannot fork at step zero", self.thread_name,) - } - } - } + pub a: BitVecValue, + pub b: BitVecValue, } From a223654927bc0f9bce39afcfb9549f4053bb3f22 Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Wed, 22 Jul 2026 17:59:48 -0400 Subject: [PATCH 54/55] Remove .expect files corresponding to .prot files that have been deleted --- .../adders/expects/nested_busy_wait.bi.expect | 244 ------------------ .../expects/push_pop_loop_empty.bi.expect | 212 --------------- .../expects/push_pop_loop_not_empty.bi.expect | 75 ------ 3 files changed, 531 deletions(-) delete mode 100644 tests/adders/expects/nested_busy_wait.bi.expect delete mode 100644 tests/fifo/expects/push_pop_loop_empty.bi.expect delete mode 100644 tests/fifo/expects/push_pop_loop_not_empty.bi.expect diff --git a/tests/adders/expects/nested_busy_wait.bi.expect b/tests/adders/expects/nested_busy_wait.bi.expect deleted file mode 100644 index bcab7ed1..00000000 --- a/tests/adders/expects/nested_busy_wait.bi.expect +++ /dev/null @@ -1,244 +0,0 @@ -// trace 0 -trace { - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(10, 20, 2, 0, 30); - nested_busy_wait(10, 20, 2, 0, 30); - nested_busy_wait(10, 20, 2, 0, 30); - nested_busy_wait(10, 20, 2, 0, 30); -} - -// trace 1 -trace { - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(10, 20, 2, 0, 30); - nested_busy_wait(10, 20, 2, 0, 30); - nested_busy_wait(10, 20, 2, 0, 30); - nested_busy_wait(10, 20, 1, 0, 30); - nested_busy_wait(10, 20, 1, 0, 30); -} - -// trace 2 -trace { - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(10, 20, 2, 0, 30); - nested_busy_wait(10, 20, 2, 0, 30); - nested_busy_wait(10, 20, 2, 0, 30); - nested_busy_wait(10, 20, 1, 1, 30); -} - -// trace 3 -trace { - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(10, 20, 2, 0, 30); - nested_busy_wait(10, 20, 2, 0, 30); - nested_busy_wait(10, 20, 4, 0, 30); -} - -// trace 4 -trace { - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(10, 20, 2, 0, 30); - nested_busy_wait(10, 20, 2, 0, 30); - nested_busy_wait(10, 20, 3, 0, 30); - nested_busy_wait(10, 20, 1, 0, 30); -} - -// trace 5 -trace { - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(10, 20, 2, 0, 30); - nested_busy_wait(10, 20, 2, 0, 30); - nested_busy_wait(10, 20, 1, 0, 30); - nested_busy_wait(10, 20, 1, 1, 30); - nested_busy_wait(10, 20, 1, 0, 30); -} - -// trace 6 -trace { - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(10, 20, 2, 0, 30); - nested_busy_wait(10, 20, 2, 0, 30); - nested_busy_wait(10, 20, 1, 0, 30); - nested_busy_wait(10, 20, 1, 2, 30); -} - -// trace 7 -trace { - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(10, 20, 2, 0, 30); - nested_busy_wait(10, 20, 2, 0, 30); - nested_busy_wait(10, 20, 1, 0, 30); - nested_busy_wait(10, 20, 1, 0, 30); - nested_busy_wait(10, 20, 2, 0, 30); -} - -// trace 8 -trace { - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(10, 20, 2, 0, 30); - nested_busy_wait(10, 20, 2, 0, 30); - nested_busy_wait(10, 20, 1, 0, 30); - nested_busy_wait(10, 20, 1, 0, 30); - nested_busy_wait(10, 20, 1, 0, 30); - nested_busy_wait(10, 20, 1, 0, 30); -} - -// trace 9 -trace { - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(10, 20, 2, 0, 30); - nested_busy_wait(10, 20, 2, 0, 30); - nested_busy_wait(10, 20, 1, 0, 30); - nested_busy_wait(10, 20, 1, 0, 30); - nested_busy_wait(10, 20, 1, 1, 30); -} - -// trace 10 -trace { - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(10, 20, 2, 0, 30); - nested_busy_wait(10, 20, 2, 0, 30); - nested_busy_wait(10, 20, 1, 0, 30); - nested_busy_wait(10, 20, 3, 0, 30); -} - -// trace 11 -trace { - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(10, 20, 2, 0, 30); - nested_busy_wait(10, 20, 2, 0, 30); - nested_busy_wait(10, 20, 1, 0, 30); - nested_busy_wait(10, 20, 2, 0, 30); - nested_busy_wait(10, 20, 1, 0, 30); -} - -// trace 12 -trace { - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(10, 20, 2, 0, 30); - nested_busy_wait(10, 20, 2, 0, 30); - nested_busy_wait(10, 20, 1, 2, 30); - nested_busy_wait(10, 20, 1, 0, 30); -} - -// trace 13 -trace { - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(10, 20, 2, 0, 30); - nested_busy_wait(10, 20, 2, 0, 30); - nested_busy_wait(10, 20, 1, 3, 30); -} - -// trace 14 -trace { - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(10, 20, 2, 0, 30); - nested_busy_wait(10, 20, 2, 0, 30); - nested_busy_wait(10, 20, 1, 1, 30); - nested_busy_wait(10, 20, 2, 0, 30); -} - -// trace 15 -trace { - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(10, 20, 2, 0, 30); - nested_busy_wait(10, 20, 2, 0, 30); - nested_busy_wait(10, 20, 1, 1, 30); - nested_busy_wait(10, 20, 1, 0, 30); - nested_busy_wait(10, 20, 1, 0, 30); -} - -// trace 16 -trace { - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(10, 20, 2, 0, 30); - nested_busy_wait(10, 20, 2, 0, 30); - nested_busy_wait(10, 20, 1, 1, 30); - nested_busy_wait(10, 20, 1, 1, 30); -} - -// trace 17 -trace { - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(10, 20, 2, 0, 30); - nested_busy_wait(10, 20, 2, 0, 30); - nested_busy_wait(10, 20, 2, 1, 30); -} - -// trace 18 -trace { - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(10, 20, 2, 0, 30); - nested_busy_wait(10, 20, 4, 0, 30); - nested_busy_wait(10, 20, 2, 0, 30); -} - -// trace 19 -trace { - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(1, 2, 2, 0, 3); - nested_busy_wait(10, 20, 2, 0, 30); - nested_busy_wait(10, 20, 4, 0, 30); - nested_busy_wait(10, 20, 1, 0, 30); - nested_busy_wait(10, 20, 1, 0, 30); -} -Displayed 20/423801 traces. diff --git a/tests/fifo/expects/push_pop_loop_empty.bi.expect b/tests/fifo/expects/push_pop_loop_empty.bi.expect deleted file mode 100644 index eb5f72bb..00000000 --- a/tests/fifo/expects/push_pop_loop_empty.bi.expect +++ /dev/null @@ -1,212 +0,0 @@ -// trace 0 -trace { - reset(); - push_n_times(42, 2); - push_n_times(42, 2); - pop_n_times(42, 2); - pop_n_times(42, 2); - check_empty(); -} - -// trace 1 -trace { - reset(); - push_n_times(42, 2); - push_n_times(42, 2); - pop_n_times(42, 2); - pop_n_times(42, 1); - pop_n_times(42, 1); - check_empty(); -} - -// trace 2 -trace { - reset(); - push_n_times(42, 2); - push_n_times(42, 2); - pop_n_times(42, 4); - check_empty(); -} - -// trace 3 -trace { - reset(); - push_n_times(42, 2); - push_n_times(42, 2); - pop_n_times(42, 3); - pop_n_times(42, 1); - check_empty(); -} - -// trace 4 -trace { - reset(); - push_n_times(42, 2); - push_n_times(42, 2); - pop_n_times(42, 1); - pop_n_times(42, 1); - pop_n_times(42, 2); - check_empty(); -} - -// trace 5 -trace { - reset(); - push_n_times(42, 2); - push_n_times(42, 2); - pop_n_times(42, 1); - pop_n_times(42, 1); - pop_n_times(42, 1); - pop_n_times(42, 1); - check_empty(); -} - -// trace 6 -trace { - reset(); - push_n_times(42, 2); - push_n_times(42, 2); - pop_n_times(42, 1); - pop_n_times(42, 3); - check_empty(); -} - -// trace 7 -trace { - reset(); - push_n_times(42, 2); - push_n_times(42, 2); - pop_n_times(42, 1); - pop_n_times(42, 2); - pop_n_times(42, 1); - check_empty(); -} - -// trace 8 -trace { - reset(); - push_n_times(42, 2); - push_n_times(42, 1); - push_n_times(42, 1); - pop_n_times(42, 2); - pop_n_times(42, 2); - check_empty(); -} - -// trace 9 -trace { - reset(); - push_n_times(42, 2); - push_n_times(42, 1); - push_n_times(42, 1); - pop_n_times(42, 2); - pop_n_times(42, 1); - pop_n_times(42, 1); - check_empty(); -} - -// trace 10 -trace { - reset(); - push_n_times(42, 2); - push_n_times(42, 1); - push_n_times(42, 1); - pop_n_times(42, 4); - check_empty(); -} - -// trace 11 -trace { - reset(); - push_n_times(42, 2); - push_n_times(42, 1); - push_n_times(42, 1); - pop_n_times(42, 3); - pop_n_times(42, 1); - check_empty(); -} - -// trace 12 -trace { - reset(); - push_n_times(42, 2); - push_n_times(42, 1); - push_n_times(42, 1); - pop_n_times(42, 1); - pop_n_times(42, 1); - pop_n_times(42, 2); - check_empty(); -} - -// trace 13 -trace { - reset(); - push_n_times(42, 2); - push_n_times(42, 1); - push_n_times(42, 1); - pop_n_times(42, 1); - pop_n_times(42, 1); - pop_n_times(42, 1); - pop_n_times(42, 1); - check_empty(); -} - -// trace 14 -trace { - reset(); - push_n_times(42, 2); - push_n_times(42, 1); - push_n_times(42, 1); - pop_n_times(42, 1); - pop_n_times(42, 3); - check_empty(); -} - -// trace 15 -trace { - reset(); - push_n_times(42, 2); - push_n_times(42, 1); - push_n_times(42, 1); - pop_n_times(42, 1); - pop_n_times(42, 2); - pop_n_times(42, 1); - check_empty(); -} - -// trace 16 -trace { - reset(); - push_n_times(42, 4); - pop_n_times(42, 2); - pop_n_times(42, 2); - check_empty(); -} - -// trace 17 -trace { - reset(); - push_n_times(42, 4); - pop_n_times(42, 2); - pop_n_times(42, 1); - pop_n_times(42, 1); - check_empty(); -} - -// trace 18 -trace { - reset(); - push_n_times(42, 4); - pop_n_times(42, 4); - check_empty(); -} - -// trace 19 -trace { - reset(); - push_n_times(42, 4); - pop_n_times(42, 3); - pop_n_times(42, 1); - check_empty(); -} -Displayed 20/64 traces. diff --git a/tests/fifo/expects/push_pop_loop_not_empty.bi.expect b/tests/fifo/expects/push_pop_loop_not_empty.bi.expect deleted file mode 100644 index a20f3b61..00000000 --- a/tests/fifo/expects/push_pop_loop_not_empty.bi.expect +++ /dev/null @@ -1,75 +0,0 @@ -// trace 0 -trace { - reset(); - push_n_times(7, 1); - push_n_times(7, 2); - pop_n_times(7, 2); - check_not_empty(); -} - -// trace 1 -trace { - reset(); - push_n_times(7, 1); - push_n_times(7, 2); - pop_n_times(7, 1); - pop_n_times(7, 1); - check_not_empty(); -} - -// trace 2 -trace { - reset(); - push_n_times(7, 1); - push_n_times(7, 1); - push_n_times(7, 1); - pop_n_times(7, 2); - check_not_empty(); -} - -// trace 3 -trace { - reset(); - push_n_times(7, 1); - push_n_times(7, 1); - push_n_times(7, 1); - pop_n_times(7, 1); - pop_n_times(7, 1); - check_not_empty(); -} - -// trace 4 -trace { - reset(); - push_n_times(7, 3); - pop_n_times(7, 2); - check_not_empty(); -} - -// trace 5 -trace { - reset(); - push_n_times(7, 3); - pop_n_times(7, 1); - pop_n_times(7, 1); - check_not_empty(); -} - -// trace 6 -trace { - reset(); - push_n_times(7, 2); - push_n_times(7, 1); - pop_n_times(7, 2); - check_not_empty(); -} - -// trace 7 -trace { - reset(); - push_n_times(7, 2); - push_n_times(7, 1); - pop_n_times(7, 1); - pop_n_times(7, 1); - check_not_empty(); -} From 462dccff6a2e8231f382c40242ad2f0de89eb0a2 Mon Sep 17 00:00:00 2001 From: Ernest Ng Date: Thu, 23 Jul 2026 10:09:43 -0400 Subject: [PATCH 55/55] git mv s1 .expect files --- .../axi-lite-s1/expects/s1_buggy.bi.expect | 28 ------ .../expects/s1_buggy_workload_1.bi.expect | 85 ------------------- .../axi-lite-s1/expects/s1_fixed.bi.expect | 12 --- .../expects/s1_fixed_workload_1.bi.expect | 77 ----------------- 4 files changed, 202 deletions(-) delete mode 100644 tests/fpga-debugging/axi-lite-s1/expects/s1_buggy.bi.expect delete mode 100644 tests/fpga-debugging/axi-lite-s1/expects/s1_buggy_workload_1.bi.expect delete mode 100644 tests/fpga-debugging/axi-lite-s1/expects/s1_fixed.bi.expect delete mode 100644 tests/fpga-debugging/axi-lite-s1/expects/s1_fixed_workload_1.bi.expect diff --git a/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy.bi.expect b/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy.bi.expect deleted file mode 100644 index 3b9d8bbd..00000000 --- a/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy.bi.expect +++ /dev/null @@ -1,28 +0,0 @@ -// trace 0 -trace { - idle(); // [time: 0ns -> 25ns] - write(64, 2147483648, 0, 0); // [time: 25ns -> 100ns] -} -// trace 0 -trace { - idle(); // [time: 0ns -> 25ns] -} -error: [read_v2@11?1!] executing step 3 of the transaction: 1 != 0 - ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy.prot:169:5 - │ -169 │ assert_eq(DUT.S_AXI_ARREADY, 1'b0); - │ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@11?1!] executing step 3 of the transaction: 1 != 0 - - -// trace 1 -trace { - idle(); // [time: 0ns -> 25ns] -} -error: [read_v2@11?2?] executing step 3 of the transaction: 1 != 0 - ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy.prot:163:9 - │ -163 │ DUT.S_AXI_RREADY := 1'b0; - │ ^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@11?2?] executing step 3 of the transaction: 1 != 0 - ----CODE--- -1 diff --git a/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy_workload_1.bi.expect b/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy_workload_1.bi.expect deleted file mode 100644 index f3ec1c05..00000000 --- a/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy_workload_1.bi.expect +++ /dev/null @@ -1,85 +0,0 @@ -// trace 0 -trace { - idle(); // [time: 0ns -> 25ns] - write_stalled(64, 2147483648, 0); // [time: 25ns -> 75ns] - write_stalled(64, 2147483648, 0); // [time: 75ns -> 100ns] -} - -// trace 1 -trace { - write_stalled(64, 2147483648, 1); // [time: 0ns -> 75ns] - write_stalled(64, 2147483648, 0); // [time: 75ns -> 100ns] -} -// trace 0 -trace { - idle(); // [time: 0ns -> 25ns] - read_v1(64, 0); // [time: 25ns -> 100ns] -} -error: [read_v2@4] executing step 0 of the transaction: 0 != 1 - ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot:161:5 - │ -161 │ DUT.S_AXI_ARVALID := 1'b1; - │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@4] executing step 0 of the transaction: 0 != 1 - - -// trace 1 -trace { - idle(); // [time: 0ns -> 25ns] - read_v1(64, 0); // [time: 25ns -> 100ns] -} -error: [read_v1@4] executing step 0 of the transaction: 0 != 1 - ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot:124:5 - │ -124 │ DUT.S_AXI_ARVALID := 1'b1; - │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v1@4] executing step 0 of the transaction: 0 != 1 - - -// trace 2 -trace { - idle(); // [time: 0ns -> 25ns] - read_v1(64, 0); // [time: 25ns -> 100ns] -} -error: [idle@4] executing step 0 of the transaction: 1 != 0 - ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot:108:5 - │ -108 │ DUT.S_AXI_RREADY := 1'b0; - │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [idle@4] executing step 0 of the transaction: 1 != 0 - - -// trace 3 -trace { - idle(); // [time: 0ns -> 25ns] - read_v2(64, 0, 0); // [time: 25ns -> 100ns] -} -error: [read_v2@4] executing step 0 of the transaction: 0 != 1 - ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot:161:5 - │ -161 │ DUT.S_AXI_ARVALID := 1'b1; - │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@4] executing step 0 of the transaction: 0 != 1 - - -// trace 4 -trace { - idle(); // [time: 0ns -> 25ns] - read_v2(64, 0, 0); // [time: 25ns -> 100ns] -} -error: [read_v1@4] executing step 0 of the transaction: 0 != 1 - ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot:124:5 - │ -124 │ DUT.S_AXI_ARVALID := 1'b1; - │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v1@4] executing step 0 of the transaction: 0 != 1 - - -// trace 5 -trace { - idle(); // [time: 0ns -> 25ns] - read_v2(64, 0, 0); // [time: 25ns -> 100ns] -} -error: [idle@4] executing step 0 of the transaction: 1 != 0 - ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot:108:5 - │ -108 │ DUT.S_AXI_RREADY := 1'b0; - │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [idle@4] executing step 0 of the transaction: 1 != 0 - ----CODE--- -1 diff --git a/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed.bi.expect b/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed.bi.expect deleted file mode 100644 index ecf4be3e..00000000 --- a/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed.bi.expect +++ /dev/null @@ -1,12 +0,0 @@ -// trace 0 -trace { - idle(); // [time: 0ns -> 25ns] - write(64, 2147483648, 0, 0); // [time: 25ns -> 100ns] -} -// trace 0 -trace { - idle(); // [time: 0ns -> 25ns] - read_v2(68, 0, 1); // [time: 25ns -> 125ns] - idle(); // [time: 125ns -> 150ns] - idle(); // [time: 150ns -> 150ns] -} diff --git a/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed_workload_1.bi.expect b/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed_workload_1.bi.expect deleted file mode 100644 index 5b0357ce..00000000 --- a/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed_workload_1.bi.expect +++ /dev/null @@ -1,77 +0,0 @@ -// trace 0 -trace { - idle(); // [time: 0ns -> 25ns] -} -// trace 0 -trace { - idle(); // [time: 0ns -> 25ns] - read_v1(64, 0); // [time: 25ns -> 100ns] -} -error: [read_v2@4] executing step 0 of the transaction: 0 != 1 - ┌─ tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot:161:5 - │ -161 │ DUT.S_AXI_ARVALID := 1'b1; - │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@4] executing step 0 of the transaction: 0 != 1 - - -// trace 1 -trace { - idle(); // [time: 0ns -> 25ns] - read_v1(64, 0); // [time: 25ns -> 100ns] -} -error: [read_v1@4] executing step 0 of the transaction: 0 != 1 - ┌─ tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot:124:5 - │ -124 │ DUT.S_AXI_ARVALID := 1'b1; - │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v1@4] executing step 0 of the transaction: 0 != 1 - - -// trace 2 -trace { - idle(); // [time: 0ns -> 25ns] - read_v1(64, 0); // [time: 25ns -> 100ns] -} -error: [idle@4] executing step 0 of the transaction: 1 != 0 - ┌─ tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot:108:5 - │ -108 │ DUT.S_AXI_RREADY := 1'b0; - │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [idle@4] executing step 0 of the transaction: 1 != 0 - - -// trace 3 -trace { - idle(); // [time: 0ns -> 25ns] - read_v2(64, 0, 0); // [time: 25ns -> 100ns] -} -error: [read_v2@4] executing step 0 of the transaction: 0 != 1 - ┌─ tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot:161:5 - │ -161 │ DUT.S_AXI_ARVALID := 1'b1; - │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@4] executing step 0 of the transaction: 0 != 1 - - -// trace 4 -trace { - idle(); // [time: 0ns -> 25ns] - read_v2(64, 0, 0); // [time: 25ns -> 100ns] -} -error: [read_v1@4] executing step 0 of the transaction: 0 != 1 - ┌─ tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot:124:5 - │ -124 │ DUT.S_AXI_ARVALID := 1'b1; - │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v1@4] executing step 0 of the transaction: 0 != 1 - - -// trace 5 -trace { - idle(); // [time: 0ns -> 25ns] - read_v2(64, 0, 0); // [time: 25ns -> 100ns] -} -error: [idle@4] executing step 0 of the transaction: 1 != 0 - ┌─ tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot:108:5 - │ -108 │ DUT.S_AXI_RREADY := 1'b0; - │ ^^^^^^^^^^^^^^^^^^^^^^^^^^ [idle@4] executing step 0 of the transaction: 1 != 0 - ----CODE--- -1