diff --git a/runt/bi/runt.toml b/runt/bi/runt.toml
index 620156fa..83187897 100644
--- a/runt/bi/runt.toml
+++ b/runt/bi/runt.toml
@@ -2233,39 +2233,39 @@ expect_name = "s4_fixed.bi.expect"
 cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axi-burst-s4/s4_fixed.prot --wave tests/fpga-debugging/axi-burst-s4/s4_fixed.vcd --instances TOP.test_l2_cache_wait_state.axi_bus:WriteSubordinate --sample-posedge TOP.test_l2_cache_wait_state.clk --show-waveform-time --time-unit ns 2>&1"
 
 [[tests]]
-name = "bi.tests_fpga_debugging_axi_lite_s1_s1_buggy.s1_buggy_bi"
+name = "bi.tests_fpga_debugging_axi_lite_s1_s1_buggy.s1_buggy_workload2_bi"
 paths = [
   "../../tests/fpga-debugging/axi-lite-s1/s1_buggy.prot",
 ]
 expect_dir = "../../tests/fpga-debugging/axi-lite-s1/expects"
-expect_name = "s1_buggy.bi.expect"
+expect_name = "s1_buggy_workload2.bi.expect"
 cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axi-lite-s1/s1_buggy.prot --wave tests/fpga-debugging/axi-lite-s1/s1_buggy_workload2.vcd --instances TOP.testbench.UUT:WriteSubordinate TOP.testbench.UUT:ReadSubordinate --sample-posedge TOP.testbench.UUT.S_AXI_ACLK --show-waveform-time --time-unit ns --include-idle 2>&1"
 
 [[tests]]
-name = "bi.tests_fpga_debugging_axi_lite_s1_s1_buggy_workload_1.s1_buggy_workload_1_bi"
+name = "bi.tests_fpga_debugging_axi_lite_s1_s1_buggy_workload_1.s1_buggy_workload1_bi"
 paths = [
   "../../tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot",
 ]
 expect_dir = "../../tests/fpga-debugging/axi-lite-s1/expects"
-expect_name = "s1_buggy_workload_1.bi.expect"
+expect_name = "s1_buggy_workload1.bi.expect"
 cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot --wave tests/fpga-debugging/axi-lite-s1/s1_buggy_workload1.vcd --instances TOP.testbench.UUT:WriteSubordinate TOP.testbench.UUT:ReadSubordinate --sample-posedge TOP.testbench.UUT.S_AXI_ACLK --show-waveform-time --time-unit ns --include-idle 2>&1"
 
 [[tests]]
-name = "bi.tests_fpga_debugging_axi_lite_s1_s1_fixed.s1_fixed_bi"
+name = "bi.tests_fpga_debugging_axi_lite_s1_s1_fixed.s1_fixed_workload2_bi"
 paths = [
   "../../tests/fpga-debugging/axi-lite-s1/s1_fixed.prot",
 ]
 expect_dir = "../../tests/fpga-debugging/axi-lite-s1/expects"
-expect_name = "s1_fixed.bi.expect"
+expect_name = "s1_fixed_workload2.bi.expect"
 cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axi-lite-s1/s1_fixed.prot --wave tests/fpga-debugging/axi-lite-s1/s1_fixed_workload2.vcd --instances TOP.testbench.UUT:WriteSubordinate TOP.testbench.UUT:ReadSubordinate --sample-posedge TOP.testbench.UUT.S_AXI_ACLK --show-waveform-time --time-unit ns --include-idle 2>&1"
 
 [[tests]]
-name = "bi.tests_fpga_debugging_axi_lite_s1_s1_fixed_workload_1.s1_fixed_workload_1_bi"
+name = "bi.tests_fpga_debugging_axi_lite_s1_s1_fixed_workload_1.s1_fixed_workload1_bi"
 paths = [
   "../../tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot",
 ]
 expect_dir = "../../tests/fpga-debugging/axi-lite-s1/expects"
-expect_name = "s1_fixed_workload_1.bi.expect"
+expect_name = "s1_fixed_workload1.bi.expect"
 cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot --wave tests/fpga-debugging/axi-lite-s1/s1_fixed_workload1.vcd --instances TOP.testbench.UUT:WriteSubordinate TOP.testbench.UUT:ReadSubordinate --sample-posedge TOP.testbench.UUT.S_AXI_ACLK --show-waveform-time --time-unit ns --include-idle 2>&1"
 
 [[tests]]
@@ -2305,22 +2305,22 @@ expect_name = "s3_fixed.bi.expect"
 cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axis-adapter-s3/s3_fixed.prot --wave tests/fpga-debugging/axis-adapter-s3/s3_fixed.fst --instances TOP.test_axis_adapter_64_8.UUT:AXISManager --sample-posedge TOP.test_axis_adapter_64_8.UUT.clk --show-waveform-time --time-unit ns 2>&1"
 
 [[tests]]
-name = "bi.tests_fpga_debugging_axis_async_fifo_c4_c4_buggy.c4_buggy_bi"
+name = "bi.tests_fpga_debugging_axis_async_fifo_c4_c4.c4_buggy_bi"
 paths = [
-  "../../tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot",
+  "../../tests/fpga-debugging/axis-async-fifo-c4/c4.prot",
 ]
 expect_dir = "../../tests/fpga-debugging/axis-async-fifo-c4/expects"
 expect_name = "c4_buggy.bi.expect"
-cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot --wave tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.fst --instances TOP.test_axis_async_fifo.UUT.axis_reg_inst:Sender TOP.test_axis_async_fifo.UUT.axis_reg_inst:Receiver --sample-posedge TOP.test_axis_async_fifo.UUT.axis_reg_inst.clk --show-waveform-time --time-unit ns 2>&1"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axis-async-fifo-c4/c4.prot --wave tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.fst --instances TOP.test_axis_async_fifo.UUT.axis_reg_inst:AsyncFifo --sample-posedge TOP.test_axis_async_fifo.UUT.axis_reg_inst.clk --show-waveform-time --time-unit ns 2>&1"
 
 [[tests]]
-name = "bi.tests_fpga_debugging_axis_async_fifo_c4_c4_fixed.c4_fixed_bi"
+name = "bi.tests_fpga_debugging_axis_async_fifo_c4_c4.c4_fixed_bi"
 paths = [
-  "../../tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.prot",
+  "../../tests/fpga-debugging/axis-async-fifo-c4/c4.prot",
 ]
 expect_dir = "../../tests/fpga-debugging/axis-async-fifo-c4/expects"
 expect_name = "c4_fixed.bi.expect"
-cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.prot --wave tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.fst --instances TOP.test_axis_async_fifo.UUT.axis_reg_inst:Sender TOP.test_axis_async_fifo.UUT.axis_reg_inst:Receiver --sample-posedge TOP.test_axis_async_fifo.UUT.axis_reg_inst.clk --show-waveform-time --time-unit ns 2>&1"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axis-async-fifo-c4/c4.prot --wave tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.fst --instances TOP.test_axis_async_fifo.UUT.axis_reg_inst:AsyncFifo --sample-posedge TOP.test_axis_async_fifo.UUT.axis_reg_inst.clk --show-waveform-time --time-unit ns --max-traces 20 2>&1"
 
 [[tests]]
 name = "bi.tests_fpga_debugging_axis_fifo_d11_d11_buggy.d11_buggy_bi"
diff --git a/runt/fail/runt.toml b/runt/fail/runt.toml
index 7c86432d..f3e88462 100644
--- a/runt/fail/runt.toml
+++ b/runt/fail/runt.toml
@@ -324,6 +324,24 @@ expect_dir = "../../tests/fifo/expects"
 expect_name = "push_pop_conflict.fail.expect"
 cmd = "cd ../.. && target/debug/graph-interp --transactions tests/fifo/push_pop_conflict.tx --transition-system --verilog tests/fifo/bsg_mem_1rw_sync.v tests/fifo/bsg_mem_1rw_sync_synth.v tests/fifo/bsg_circular_ptr.v tests/fifo/bsg_fifo_1rw_large.v tests/fifo/fifo_wrapper.v --protocol tests/fifo/fifo.prot --module fifo_wrapper 2>/dev/null"
 
+[[tests]]
+name = "fail.tests_fpga_debugging_axis_async_fifo_c4_c4_buggy.c4_buggy_fail.graph"
+paths = [
+  "../../tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.tx",
+]
+expect_dir = "../../tests/fpga-debugging/axis-async-fifo-c4/expects"
+expect_name = "c4_buggy.fail.expect"
+cmd = "cd ../.. && target/debug/graph-interp --transactions tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.tx --respect-forks --determinize --brief-graph-errors --verilog tests/fpga-debugging/axis-async-fifo-c4/c4_dut.v tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.v --protocol tests/fpga-debugging/axis-async-fifo-c4/c4.prot --module c4_dut 2>/dev/null"
+
+[[tests]]
+name = "fail.tests_fpga_debugging_axis_async_fifo_c4_c4_buggy.c4_buggy_fail.ts"
+paths = [
+  "../../tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.tx",
+]
+expect_dir = "../../tests/fpga-debugging/axis-async-fifo-c4/expects"
+expect_name = "c4_buggy.fail.expect"
+cmd = "cd ../.. && target/debug/graph-interp --transactions tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.tx --transition-system --verilog tests/fpga-debugging/axis-async-fifo-c4/c4_dut.v tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.v --protocol tests/fpga-debugging/axis-async-fifo-c4/c4.prot --module c4_dut 2>/dev/null"
+
 [[tests]]
 name = "fail.tests_identities_identity_d1_explicit_fork.explicit_fork_fail.graph"
 paths = [
diff --git a/runt/graph_interp/runt.toml b/runt/graph_interp/runt.toml
index 45563474..373c5075 100644
--- a/runt/graph_interp/runt.toml
+++ b/runt/graph_interp/runt.toml
@@ -531,6 +531,33 @@ expect_dir = "../../tests/fifo/expects"
 expect_name = "push_pop_identity_ok.graph_interp.expect"
 cmd = "cd ../.. && target/debug/graph-interp --transactions tests/fifo/push_pop_identity_ok.tx --verilog tests/fifo/bsg_mem_1rw_sync.v tests/fifo/bsg_mem_1rw_sync_synth.v tests/fifo/bsg_circular_ptr.v tests/fifo/bsg_fifo_1rw_large.v tests/fifo/fifo_wrapper.v --protocol tests/fifo/fifo.prot --module fifo_wrapper --respect-forks --determinize 2>/dev/null"
 
+[[tests]]
+name = "graph_interp.tests_fpga_debugging_axis_async_fifo_c4_c4_fixed.c4_fixed_graph_interp"
+paths = [
+  "../../tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.tx",
+]
+expect_dir = "../../tests/fpga-debugging/axis-async-fifo-c4/expects"
+expect_name = "c4_fixed.graph_interp.expect"
+cmd = "cd ../.. && target/debug/graph-interp --transactions tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.tx --verilog tests/fpga-debugging/axis-async-fifo-c4/c4_dut.v tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.v --protocol tests/fpga-debugging/axis-async-fifo-c4/c4.prot --module c4_dut 2>/dev/null"
+
+[[tests]]
+name = "graph_interp.tests_fpga_debugging_axis_async_fifo_c4_c4_fixed.c4_fixed_graph_interp.contract_edges"
+paths = [
+  "../../tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.tx",
+]
+expect_dir = "../../tests/fpga-debugging/axis-async-fifo-c4/expects"
+expect_name = "c4_fixed.graph_interp.expect"
+cmd = "cd ../.. && target/debug/graph-interp --transactions tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.tx --verilog tests/fpga-debugging/axis-async-fifo-c4/c4_dut.v tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.v --protocol tests/fpga-debugging/axis-async-fifo-c4/c4.prot --module c4_dut --contract-edges 2>/dev/null"
+
+[[tests]]
+name = "graph_interp.tests_fpga_debugging_axis_async_fifo_c4_c4_fixed.c4_fixed_graph_interp.respect_forks"
+paths = [
+  "../../tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.tx",
+]
+expect_dir = "../../tests/fpga-debugging/axis-async-fifo-c4/expects"
+expect_name = "c4_fixed.graph_interp.expect"
+cmd = "cd ../.. && target/debug/graph-interp --transactions tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.tx --verilog tests/fpga-debugging/axis-async-fifo-c4/c4_dut.v tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.v --protocol tests/fpga-debugging/axis-async-fifo-c4/c4.prot --module c4_dut --respect-forks --determinize 2>/dev/null"
+
 [[tests]]
 name = "graph_interp.tests_identities_identity_d0_passthrough_combdep.passthrough_combdep_graph_interp"
 paths = [
diff --git a/runt/interp/runt.toml b/runt/interp/runt.toml
index 5c652982..a06c977b 100644
--- a/runt/interp/runt.toml
+++ b/runt/interp/runt.toml
@@ -441,6 +441,24 @@ expect_dir = "../../tests/fifo/expects"
 expect_name = "push_pop_identity_ok.interp.expect"
 cmd = "cd ../.. && target/debug/protocols-interp --color never --transactions tests/fifo/push_pop_identity_ok.tx --verilog tests/fifo/bsg_mem_1rw_sync.v tests/fifo/bsg_mem_1rw_sync_synth.v tests/fifo/bsg_circular_ptr.v tests/fifo/bsg_fifo_1rw_large.v tests/fifo/fifo_wrapper.v --protocol tests/fifo/fifo.prot --module fifo_wrapper 2>&1"
 
+[[tests]]
+name = "interp.tests_fpga_debugging_axis_async_fifo_c4_c4_buggy.c4_buggy_interp"
+paths = [
+  "../../tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.tx",
+]
+expect_dir = "../../tests/fpga-debugging/axis-async-fifo-c4/expects"
+expect_name = "c4_buggy.interp.expect"
+cmd = "cd ../.. && target/debug/protocols-interp --color never --transactions tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.tx --verilog tests/fpga-debugging/axis-async-fifo-c4/c4_dut.v tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.v --protocol tests/fpga-debugging/axis-async-fifo-c4/c4.prot --module c4_dut 2>&1"
+
+[[tests]]
+name = "interp.tests_fpga_debugging_axis_async_fifo_c4_c4_fixed.c4_fixed_interp"
+paths = [
+  "../../tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.tx",
+]
+expect_dir = "../../tests/fpga-debugging/axis-async-fifo-c4/expects"
+expect_name = "c4_fixed.interp.expect"
+cmd = "cd ../.. && target/debug/protocols-interp --color never --transactions tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.tx --verilog tests/fpga-debugging/axis-async-fifo-c4/c4_dut.v tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.v --protocol tests/fpga-debugging/axis-async-fifo-c4/c4.prot --module c4_dut 2>&1"
+
 [[tests]]
 name = "interp.tests_identities_dual_identity_d0_dual_identity_d0_combdep.dual_identity_d0_combdep_interp"
 paths = [
diff --git a/runt/waveform/runt.toml b/runt/waveform/runt.toml
index c18c9309..32c34273 100644
--- a/runt/waveform/runt.toml
+++ b/runt/waveform/runt.toml
@@ -513,6 +513,33 @@ expect_dir = "../../tests/fifo/expects"
 expect_name = "push_pop_identity_ok.waveform.expect"
 cmd = "cd ../.. && target/debug/graph-interp --transactions tests/fifo/push_pop_identity_ok.tx --transition-system --ascii-waveform --verilog tests/fifo/bsg_mem_1rw_sync.v tests/fifo/bsg_mem_1rw_sync_synth.v tests/fifo/bsg_circular_ptr.v tests/fifo/bsg_fifo_1rw_large.v tests/fifo/fifo_wrapper.v --protocol tests/fifo/fifo.prot --module fifo_wrapper 2>/dev/null"
 
+[[tests]]
+name = "waveform.tests_fpga_debugging_axis_async_fifo_c4_c4_fixed.c4_fixed_waveform.ast"
+paths = [
+  "../../tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.tx",
+]
+expect_dir = "../../tests/fpga-debugging/axis-async-fifo-c4/expects"
+expect_name = "c4_fixed.waveform.expect"
+cmd = "cd ../.. && target/debug/protocols-interp --color never --transactions tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.tx --ascii-waveform --verilog tests/fpga-debugging/axis-async-fifo-c4/c4_dut.v tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.v --protocol tests/fpga-debugging/axis-async-fifo-c4/c4.prot --module c4_dut 2>/dev/null"
+
+[[tests]]
+name = "waveform.tests_fpga_debugging_axis_async_fifo_c4_c4_fixed.c4_fixed_waveform.graph"
+paths = [
+  "../../tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.tx",
+]
+expect_dir = "../../tests/fpga-debugging/axis-async-fifo-c4/expects"
+expect_name = "c4_fixed.waveform.expect"
+cmd = "cd ../.. && target/debug/graph-interp --transactions tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.tx --respect-forks --determinize --ascii-waveform --verilog tests/fpga-debugging/axis-async-fifo-c4/c4_dut.v tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.v --protocol tests/fpga-debugging/axis-async-fifo-c4/c4.prot --module c4_dut 2>/dev/null"
+
+[[tests]]
+name = "waveform.tests_fpga_debugging_axis_async_fifo_c4_c4_fixed.c4_fixed_waveform.ts"
+paths = [
+  "../../tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.tx",
+]
+expect_dir = "../../tests/fpga-debugging/axis-async-fifo-c4/expects"
+expect_name = "c4_fixed.waveform.expect"
+cmd = "cd ../.. && target/debug/graph-interp --transactions tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.tx --transition-system --ascii-waveform --verilog tests/fpga-debugging/axis-async-fifo-c4/c4_dut.v tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.v --protocol tests/fpga-debugging/axis-async-fifo-c4/c4.prot --module c4_dut 2>/dev/null"
+
 [[tests]]
 name = "waveform.tests_identities_identity_d0_passthrough_combdep.passthrough_combdep_waveform.ast"
 paths = [
diff --git a/scripts/generate_runt_configs.py b/scripts/generate_runt_configs.py
index 1802450b..7aee54f9 100644
--- a/scripts/generate_runt_configs.py
+++ b/scripts/generate_runt_configs.py
@@ -74,10 +74,12 @@ def replace_non_alphanumerics(value: object) -> str:
 
 
 def case_stem(case: dict) -> str:
-    # antmicro cases share one .prot but differ by wave, so name them by
-    # the wave; otherwise use the test file's stem (dropping a .bi suffix).
+    # Antmicro & Brave New World test cases for the BI share the same `.prot`
+    # file but have multiple waveforms, so we use the waveform files'
+    # names to identify a particular test, otherwise we use the `.prot` file's stem
+    # to identify a test
     wave = case.get("wave")
-    if wave and "antmicro" in wave:
+    if wave and ("antmicro" in wave or "fpga-debugging" in wave):
         return Path(wave).stem
     stem = Path(case["paths"][0]).stem
     return stem.removesuffix(".bi")
diff --git a/scripts/test_catalog.py b/scripts/test_catalog.py
index 8b5255d1..600d2dca 100644
--- a/scripts/test_catalog.py
+++ b/scripts/test_catalog.py
@@ -305,6 +305,24 @@
         "top": "fifo_wrapper",
         "expect": "pass",
     },
+    "tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.tx": {
+        "protocol": "tests/fpga-debugging/axis-async-fifo-c4/c4.prot",
+        "verilog": (
+            "tests/fpga-debugging/axis-async-fifo-c4/c4_dut.v",
+            "tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.v",
+        ),
+        "top": "c4_dut",
+        "expect": "assertion_mismatch",
+    },
+    "tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.tx": {
+        "protocol": "tests/fpga-debugging/axis-async-fifo-c4/c4.prot",
+        "verilog": (
+            "tests/fpga-debugging/axis-async-fifo-c4/c4_dut.v",
+            "tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.v",
+        ),
+        "top": "c4_dut",
+        "expect": "pass",
+    },
     "tests/identities/dual_identity_d0/dual_identity_d0_combdep.tx": {
         "protocol": "tests/identities/dual_identity_d0/dual_identity_d0.prot",
         "verilog": ("tests/identities/dual_identity_d0/dual_identity_d0.v",),
@@ -701,12 +719,9 @@
         ),
     },
     "tests.fpga-debugging.axis-async-fifo-c4.c4_buggy": {
-        "protocol": "tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot",
+        "protocol": "tests/fpga-debugging/axis-async-fifo-c4/c4.prot",
         "wave": "tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.fst",
-        "instances": (
-            "TOP.test_axis_async_fifo.UUT.axis_reg_inst:Sender",
-            "TOP.test_axis_async_fifo.UUT.axis_reg_inst:Receiver",
-        ),
+        "instances": ("TOP.test_axis_async_fifo.UUT.axis_reg_inst:AsyncFifo",),
         "expect": None,
         "extra_args": (
             "--sample-posedge",
@@ -717,12 +732,9 @@
         ),
     },
     "tests.fpga-debugging.axis-async-fifo-c4.c4_fixed": {
-        "protocol": "tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.prot",
+        "protocol": "tests/fpga-debugging/axis-async-fifo-c4/c4.prot",
         "wave": "tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.fst",
-        "instances": (
-            "TOP.test_axis_async_fifo.UUT.axis_reg_inst:Sender",
-            "TOP.test_axis_async_fifo.UUT.axis_reg_inst:Receiver",
-        ),
+        "instances": ("TOP.test_axis_async_fifo.UUT.axis_reg_inst:AsyncFifo",),
         "expect": "pass",
         "extra_args": (
             "--sample-posedge",
@@ -730,6 +742,8 @@
             "--show-waveform-time",
             "--time-unit",
             "ns",
+            "--max-traces",
+            "20",
         ),
     },
     "tests.fpga-debugging.axis-fifo-d11.d11_buggy": {
diff --git a/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy_workload_1.bi.expect b/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy_workload1.bi.expect
similarity index 100%
rename from tests/fpga-debugging/axi-lite-s1/expects/s1_buggy_workload_1.bi.expect
rename to tests/fpga-debugging/axi-lite-s1/expects/s1_buggy_workload1.bi.expect
diff --git a/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy.bi.expect b/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy_workload2.bi.expect
similarity index 100%
rename from tests/fpga-debugging/axi-lite-s1/expects/s1_buggy.bi.expect
rename to tests/fpga-debugging/axi-lite-s1/expects/s1_buggy_workload2.bi.expect
diff --git a/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed_workload_1.bi.expect b/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed_workload1.bi.expect
similarity index 100%
rename from tests/fpga-debugging/axi-lite-s1/expects/s1_fixed_workload_1.bi.expect
rename to tests/fpga-debugging/axi-lite-s1/expects/s1_fixed_workload1.bi.expect
diff --git a/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed.bi.expect b/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed_workload2.bi.expect
similarity index 100%
rename from tests/fpga-debugging/axi-lite-s1/expects/s1_fixed.bi.expect
rename to tests/fpga-debugging/axi-lite-s1/expects/s1_fixed_workload2.bi.expect
diff --git a/tests/fpga-debugging/axis-async-fifo-c4/c4.prot b/tests/fpga-debugging/axis-async-fifo-c4/c4.prot
new file mode 100644
index 00000000..4cde74ed
--- /dev/null
+++ b/tests/fpga-debugging/axis-async-fifo-c4/c4.prot
@@ -0,0 +1,91 @@
+struct AsyncFifo {
+    // Active-high reset signal
+    // Note: AXI-Stream says reset should be active-low,
+    // but this DUT uses active-high instead
+    in rst: u1,
+
+    // Signals related to pushes.
+    // These signals are named in the DUT with the `s_axis` prefix,
+    // since they are for the subordinate (receiving data).
+    // The subordinate receives valid and data signals from the environment
+    // (data to be pushed to the FIFO),
+    // and outputs a ready signal to the environment.
+    in s_axis_tdata: u8,
+    in s_axis_tvalid: u1,
+    out s_axis_tready: u1,
+
+    // Signals related to pops. 
+    // These signals are named in the DUT with the `m_axis` prefix,
+    // since they are for the manager (producing data).
+    // The manager receives a ready signal from the environment
+    // (indicating that the environment is ready to read data that is popped from the FIFO)
+    // and outputs a valid signal + the data being popped.
+    in m_axis_tready: u1,
+    out m_axis_tvalid: u1,
+    out m_axis_tdata: u8,
+}
+
+// Write data to FIFO
+// Push happens when s_axis_tvalid and s_axis_tready are both 1
+prot push<DUT: AsyncFifo>(data: u8) {
+    DUT.rst := 1'b0;
+
+    // Update the data field and set valid to 1
+    DUT.s_axis_tdata := data;
+    DUT.s_axis_tvalid := 1'b1;
+
+    // Wait for FIFO to be ready to accept data
+    while (!(DUT.s_axis_tready == 1'b1)) {
+        step();
+    }
+
+    step();
+}
+
+// Read data from FIFO (the `data` argument is the data that is popped)
+prot pop<DUT: AsyncFifo>(data: u8) {
+    DUT.rst := 1'b0;
+    DUT.m_axis_tready := 1'b1;
+
+    // Valid needs to be 1 in order for data exchange to occur
+    // Note: we don't use a while-loop here to wait for `m_axis_tvalid` to become 1,
+    // since when `m_axis_tready = 1 && m_axis_tvalid = 0`, that means the environment is ready
+    // to read the popped data but the DUT has no valid data on its output ports.
+    // This situation should not be described in a `pop` transaction,
+    // so we just assert that `m_axis_tvalid` must be 1 during a `pop` transaction
+    // without waiting for it to become 1.
+    assert_eq(DUT.m_axis_tvalid, 1'b1);
+
+    // Check that the data on DUT's output port is the data we expect to be popped
+    assert_eq(DUT.m_axis_tdata, data);
+
+    step();
+}
+
+// No transaction occurs
+prot idle<DUT: AsyncFifo>() {
+    DUT.rst := 1'b0;
+
+    // Ensure no pushes from the sender by setting the subordinate's valid = 0
+    DUT.s_axis_tvalid := 1'b0;
+
+    // Data is DontCare when subordinate's valid = 0
+    DUT.s_axis_tdata := X;
+
+    // Ensure no pops on the receiver side by setting manager's ready = 0
+    DUT.m_axis_tready := 1'b0;
+
+    step();
+}
+
+// Asserts reset signal
+prot reset<DUT: AsyncFifo>() {
+    DUT.rst := 1'b1;
+
+    // Valid must be low when reset is asserted (AXI-Stream spec section 2.7.2)
+    DUT.s_axis_tvalid := 1'b0;
+    assert_eq(DUT.m_axis_tvalid, 1'b0);
+
+    step();
+}
+
diff --git a/tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot b/tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot
deleted file mode 100644
index f8d0a03c..00000000
--- a/tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot
+++ /dev/null
@@ -1,121 +0,0 @@
-// Only `Sender` supports `push`
-struct Sender {
-    // Active-high reset signal
-    // Note: AXI-Stream says reset should be active-low,
-    // but this DUT uses active-high instead
-    in rst: u1,
-
-    // The Sender recieves VALID and DATA signals from the environment
-    // (data to be written, i.e. pushed to the FIFO),
-    // and outputs a READY signal, indicating that the FIFO can accept new data
-    in s_axis_tdata: u8,
-    in s_axis_tvalid: u1,
-    out s_axis_tready: u1,
-}
-
-// Only `Receiver` supports `pop`
-struct Receiver {
-    // Active-high reset signal
-    // Note: AXI-Stream says reset should be active-low,
-    // but this DUT uses active-high instead
-    in rst: u1,
-
-    // The Receiver receives a READY signal from the environment
-    // (environment is ready to read data that is popped from the FIFO)
-    // and outputs a VALID signal + the data being popped
-    in m_axis_tready: u1,
-    out m_axis_tvalid: u1,
-    out m_axis_tdata: u8,
-}
-
-// PUSH: Write data to FIFO via AXI-Stream receiver interface
-// Performs data transfer when s_axis_tvalid and s_axis_tready are both 1
-prot push<DUT: Sender>(data: u8) {
-    DUT.rst := 1'b0;
-
-    // Update the data field and set receiver's valid bit to 1 to indicate
-    // that data transfer can occur
-    DUT.s_axis_tdata := data;
-    DUT.s_axis_tvalid := 1'b1;
-
-    // Wait for FIFO to be ready to accept data
-    while (!(DUT.s_axis_tready == 1'b1)) {
-        step();
-    }
-
-    // One cycle for the transfer to complete
-    step();
-}
-
-// POP: Read data from FIFO via AXI-Stream sender interface
-prot pop<DUT: Receiver>(data: u8) {
-    DUT.rst := 1'b0;
-    DUT.m_axis_tready := 1'b1;
-
-    // Valid needs to be 1 in order for data exchange to occur
-    // Note: we don't use a while-loop here to wait for `m_axis_tvalid` to become 1,
-    // since when `m_axis_tready = 1 && m_axis_tvalid = 0`, that means the environment is ready
-    // to read the popped data but the DUT has no valid data on its output ports.
-    // This situation should not be described in a `pop` transaction,
-    // so we just assert that `m_axis_tvalid` must be 1 during a `pop` transaction
-    // without waiting for it to become 1.
-    assert_eq(DUT.m_axis_tvalid, 1'b1);
-
-    // One cycle for the transfer to complete
-    step();
-
-    assert_eq(DUT.m_axis_tdata, data);
-
-    // Release inputs after transaction (i.e. release all constraints)
-    DUT.m_axis_tready := X;
-    DUT.rst := X;
-
-    fork();
-    step();
-}
-
-// IDLE: No transaction occurs on the monitored interface
-// For Sender: no push transaction (no data being written to FIFO)
-// For Receiver: no pop transaction (no data being read from FIFO)
-prot idle<DUT: Sender>() {
-    DUT.rst := 1'b0;
-
-    // Ensure no push handshake by setting valid = 0
-    // (Push handshake requires s_axis_tvalid && s_axis_tready)
-    DUT.s_axis_tvalid := 1'b0;
-
-    // Data is DontCare when valid = 0
-    DUT.s_axis_tdata := X;
-
-    step();
-}
-
-prot idle<DUT: Receiver>() {
-    DUT.rst := 1'b0;
-
-    // Ensure no pop handshake by setting ready = 0
-    DUT.m_axis_tready := 1'b0;
-
-    step();
-}
-
-// RESET: Assert reset signal to initialize FIFO
-prot reset<DUT: Sender>() {
-    DUT.rst := 1'b1;
-
-    // Valid must be low when reset is asserted (AXI-Stream spec section 2.8.2)
-    DUT.s_axis_tvalid := 1'b0;
-
-    step();
-}
-
-// We have to also define `reset` for the `Receiver` `DUT` since different
-// structs are now treated separately in the new monitor implementation
-prot reset<DUT: Receiver>() {
-    DUT.rst := 1'b1;
-
-    // Valid must be low when reset is asserted (AXI-Stream spec section 2.8.2)
-    assert_eq(DUT.m_axis_tvalid, 1'b0);
-
-    step();
-}
diff --git a/tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.tx b/tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.tx
new file mode 100644
index 00000000..32ad4ac6
--- /dev/null
+++ b/tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.tx
@@ -0,0 +1,10 @@
+trace {
+    reset();
+    idle();
+    push(1);
+    push(2);
+    push(3);
+    idle();
+    pop(1);
+    pop(2);
+}
diff --git a/tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.v b/tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.v
index eaab568f..3ec649ea 100644
--- a/tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.v
+++ b/tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.v
@@ -121,13 +121,7 @@ assign {output_axis_tlast, output_axis_tuser, output_axis_tdata} = data_out_reg;
 // - However, the write pointer `input_rst_sync3` (used in line 162 in `if (input_rst_sync3) ...`)
 //   hasn't been initialized yet.
 // As a consequence, data can be written to uninitialized FIFO state during the reset.
-//
-// Inferred transaction-level trace by the monitor (`c4_buggy.out`):
-//   Time 0-25ns:   reset() - async_rst is 1
-//   Time 25-50ns:  idle() - input_rst_sync3 still high (reset being synced)
-//   Time 50-100ns: push_and_pop(2,2) - Data is accepted too early (bug)
-//                  At 50ns, input_rst_sync3 may still be 1, but tready = 1 allows for writes
-//                  This violates the invariant that no data should be accepted during reset sync
+
 assign input_axis_tready = ~full;
 assign output_axis_tvalid = output_axis_tvalid_reg;
 
diff --git a/tests/fpga-debugging/axis-async-fifo-c4/c4_buggy_waveform.png b/tests/fpga-debugging/axis-async-fifo-c4/c4_buggy_waveform.png
index f27781fb..99083166 100644
Binary files a/tests/fpga-debugging/axis-async-fifo-c4/c4_buggy_waveform.png and b/tests/fpga-debugging/axis-async-fifo-c4/c4_buggy_waveform.png differ
diff --git a/tests/fpga-debugging/axis-async-fifo-c4/c4_dut.v b/tests/fpga-debugging/axis-async-fifo-c4/c4_dut.v
new file mode 100644
index 00000000..44e7642a
--- /dev/null
+++ b/tests/fpga-debugging/axis-async-fifo-c4/c4_dut.v
@@ -0,0 +1,47 @@
+// This file is used to rename ports so that the interpreter can drive the design.
+// The signals in waveforms used by the BI (obtained directly from the Brave New World artifact) 
+// uses names such as `axis_reg_inst.s_axis_tdata`, but the Verilog DUT (in `c4_buggy.v` / `c4_fixed.v`)
+// uses names such as `input_axis_tdata`, so this file renames them.
+
+`timescale 1ns / 1ps
+
+module c4_dut (
+    input  wire       clk,
+    input  wire       rst,
+
+    // AXI-Stream input (write / push) side
+    input  wire [7:0] s_axis_tdata,
+    input  wire       s_axis_tvalid,
+    output wire       s_axis_tready,
+
+    // AXI-Stream output (read / pop) side
+    input  wire       m_axis_tready,
+    output wire       m_axis_tvalid,
+    output wire [7:0] m_axis_tdata
+);
+
+axis_async_fifo #(
+    .ADDR_WIDTH(5),
+    .DATA_WIDTH(8)
+)
+fifo (
+    .async_rst(rst),
+
+    // AXI input
+    .input_clk(clk),
+    .input_axis_tdata(s_axis_tdata),
+    .input_axis_tvalid(s_axis_tvalid),
+    .input_axis_tready(s_axis_tready),
+    .input_axis_tlast(1'b0),
+    .input_axis_tuser(1'b0),
+
+    // AXI output
+    .output_clk(clk),
+    .output_axis_tdata(m_axis_tdata),
+    .output_axis_tvalid(m_axis_tvalid),
+    .output_axis_tready(m_axis_tready),
+    .output_axis_tlast(),
+    .output_axis_tuser()
+);
+
+endmodule
diff --git a/tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.prot b/tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.prot
deleted file mode 100644
index 7a59c42e..00000000
--- a/tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.prot
+++ /dev/null
@@ -1,123 +0,0 @@
-// Only `Sender` supports `push`
-struct Sender {
-    // Active-high reset signal
-    // Note: AXI-Stream says reset should be active-low,
-    // but this DUT uses active-high instead
-    in rst: u1,
-
-    // The Sender recieves VALID and DATA signals from the environment
-    // (data to be written, i.e. pushed to the FIFO),
-    // and outputs a READY signal, indicating that the FIFO can accept new data
-    in s_axis_tdata: u8,
-    in s_axis_tvalid: u1,
-    out s_axis_tready: u1,
-}
-
-// Only `Receiver` supports `pop`
-struct Receiver {
-    // Active-high reset signal
-    // Note: AXI-Stream says reset should be active-low,
-    // but this DUT uses active-high instead
-    in rst: u1,
-
-    // The Receiver receives a READY signal from the environment
-    // (environment is ready to read data that is popped from the FIFO)
-    // and outputs a VALID signal + the data being popped
-    in m_axis_tready: u1,
-    out m_axis_tvalid: u1,
-    out m_axis_tdata: u8,
-}
-
-// PUSH: Write data to FIFO via AXI-Stream receiver interface
-// Performs data transfer when s_axis_tvalid and s_axis_tready are both 1
-prot push<DUT: Sender>(data: u8) {
-    DUT.rst := 1'b0;
-
-    // Update the data field and set receiver's valid bit to 1 to indicate
-    // that data transfer can occur
-    DUT.s_axis_tdata := data;
-    DUT.s_axis_tvalid := 1'b1;
-
-    // Wait for FIFO to be ready to accept data
-    while (!(DUT.s_axis_tready == 1'b1)) {
-        step();
-    }
-
-    // One cycle for the transfer to complete
-    step();
-}
-
-// POP: Read data from FIFO via AXI-Stream sender interface
-prot pop<DUT: Receiver>(data: u8) {
-    DUT.rst := 1'b0;
-    DUT.m_axis_tready := 1'b1;
-
-    // Valid needs to be 1 in order for data exchange to occur
-    // Note: we don't use a while-loop here to wait for `m_axis_tvalid` to become 1,
-    // since when `m_axis_tready = 1 && m_axis_tvalid = 0`, that means the environment is ready
-    // to read the popped data but the DUT has no valid data on its output ports.
-    // This situation should not be described in a `pop` transaction,
-    // so we just assert that `m_axis_tvalid` must be 1 during a `pop` transaction
-    // without waiting for it to become 1.
-    assert_eq(DUT.m_axis_tvalid, 1'b1);
-
-    // One cycle for the transfer to complete
-    step();
-
-    // Capture output data
-    assert_eq(DUT.m_axis_tdata, data);
-
-    // Release inputs after transaction (i.e. release all constraints)
-    DUT.m_axis_tready := X;
-    DUT.rst := X;
-
-    fork();
-    step();
-}
-
-// IDLE: No transaction occurs on the monitored interface
-// For Sender: no push transaction (no data being written to FIFO)
-// For Receiver: no pop transaction (no data being read from FIFO)
-prot idle<DUT: Sender>() {
-    DUT.rst := 1'b0;
-
-    // Ensure no push handshake by setting valid = 0
-    // (Push handshake requires s_axis_tvalid && s_axis_tready)
-    DUT.s_axis_tvalid := 1'b0;
-
-    // Data is DontCare when valid = 0
-    DUT.s_axis_tdata := X;
-
-    step();
-}
-
-prot idle<DUT: Receiver>() {
-    DUT.rst := 1'b0;
-
-    // Ensure no pop handshake by setting ready = 0
-    // (Pop handshake requires m_axis_tvalid && m_axis_tready)
-    DUT.m_axis_tready := 1'b0;
-
-    step();
-}
-
-// RESET: Assert reset signal to initialize FIFO
-prot reset<DUT: Sender>() {
-    DUT.rst := 1'b1;
-
-    // Valid must be low when reset is asserted (AXI-Stream spec section 2.8.2)
-    DUT.s_axis_tvalid := 1'b0;
-
-    step();
-}
-
-// We have to also define `reset` for the `Receiver` `DUT` since different
-// structs are now treated separately in the new monitor implementation
-prot reset<DUT: Receiver>() {
-    DUT.rst := 1'b1;
-
-    // Valid must be low when reset is asserted (AXI-Stream spec section 2.8.2)
-    assert_eq(DUT.m_axis_tvalid, 1'b0);
-
-    step();
-}
diff --git a/tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.tx b/tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.tx
new file mode 100644
index 00000000..e56724b5
--- /dev/null
+++ b/tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.tx
@@ -0,0 +1,10 @@
+trace {
+    reset();
+    idle();
+    push(1);
+    push(2);
+    push(3);
+    idle();
+    pop(1);
+    pop(2);
+}
\ No newline at end of file
diff --git a/tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.v b/tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.v
index 7d293a48..a5772ed4 100644
--- a/tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.v
+++ b/tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.v
@@ -104,36 +104,6 @@ wire read = (output_axis_tready | ~output_axis_tvalid_reg) & ~empty;
 
 assign {output_axis_tlast, output_axis_tuser, output_axis_tdata} = data_out_reg;
 
-// Fix: Reset-Data Synchronization
-// `input_axis_tready` is now dependent ~input_rst_sync3, preventing data acceptance during reset
-//
-// The reset synchronization code in lines 139-149 creates a 3-cycle delay:
-//   Cycle 0: async_rst deasserts, but input_rst_sync1/2/3 are all still 1
-//   Cycle 1: input_rst_sync1 becomes 0, but input_rst_sync2/3 are still 1
-//   Cycle 2: input_rst_sync2 becomes 0, but input_rst_sync3 is still 1
-//   Cycle 3: input_rst_sync3 becomes 0 (reset complete)
-//
-// The fix in the line below ensures that data is only accepted after the reset completes:
-// ```verilog
-// input_axis_tready = ~full & ~input_rst_sync3
-// ```
-// - During cycles 0-2: input_rst_sync3 = 1, so tready = 0 (blocks all writes)
-// - Starting cycle 3: input_rst_sync3 = 0, so tready depends only on ~full
-// - `write = input_axis_tvalid & ~full` (line 102) can only be 1 after reset sync completes
-// - The write pointer `wr_ptr_next` is guaranteed to be properly initialized before any writes
-//
-// Correct behavior: No data acceptance until FIFO is fully initialized
-//
-// Inferred transaction-level trace by the monitor (`c4_fixed.out`):
-//   Time 0-25ns:    reset() - async_rst is 1
-//   Time 25-50ns:   idle() - input_rst_sync3 still 1, tready = 0 (this is OK)
-//   Time 50-75ns:   push(1) - First write after reset sync completes
-//                   Data pushed to FIFO but not yet readable on the output side
-//   Time 100-150ns: push_and_pop(3,3) - Normal operation begins
-//                   Both push and pop can now complete (output side also synced)
-//
-// By making `tready` dependent on `~input_rst_sync3`, the FIFO correctly 
-// rejects writes during the reset synchronization period, as desired.
 assign input_axis_tready = ~full  & ~input_rst_sync3;
 assign output_axis_tvalid = output_axis_tvalid_reg;
 
@@ -221,4 +191,4 @@ always @(posedge output_clk) begin
     end
 end
 
-endmodule
+endmodule
\ No newline at end of file
diff --git a/tests/fpga-debugging/axis-async-fifo-c4/c4_fixed_waveform.png b/tests/fpga-debugging/axis-async-fifo-c4/c4_fixed_waveform.png
index 224b9d9b..e0e5d760 100644
Binary files a/tests/fpga-debugging/axis-async-fifo-c4/c4_fixed_waveform.png and b/tests/fpga-debugging/axis-async-fifo-c4/c4_fixed_waveform.png differ
diff --git a/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.bi.expect b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.bi.expect
index 801003cc..25cdd3ae 100644
--- a/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.bi.expect
+++ b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.bi.expect
@@ -1,24 +1,12 @@
 // trace 0
-trace {
-    reset();  // [time: 0ns -> 25ns]
-    idle();  // [time: 25ns -> 50ns]
-    push(1);  // [time: 50ns -> 75ns]
-    push(2);  // [time: 75ns -> 100ns]
-    push(3);  // [time: 100ns -> 125ns]
-    push(4);  // [time: 125ns -> 150ns]
-    push(5);  // [time: 150ns -> 175ns]
-    push(6);  // [time: 175ns -> 200ns]
-    push(7);  // [time: 200ns -> 200ns]
-}
-// trace 0
 trace {
     reset();  // [time: 0ns -> 25ns]
 }
 error: [reset@1] executing step 0 of the transaction: 0 != 1
-    ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot:115:5
-    │
-115 │     DUT.rst := 1'b1;
-    │     ^^^^^^^^^^^^^^^^ [reset@1] executing step 0 of the transaction: 0 != 1
+   ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4.prot:83:5
+   │
+83 │     DUT.rst := 1'b1;
+   │     ^^^^^^^^^^^^^^^^ [reset@1] executing step 0 of the transaction: 0 != 1
 
 
 // trace 1
@@ -26,9 +14,9 @@ trace {
     reset();  // [time: 0ns -> 25ns]
 }
 error: [idle@1] executing step 0 of the transaction: 1 != 0
-   ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot:97:5
+   ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4.prot:76:5
    │
-97 │     DUT.m_axis_tready := 1'b0;
+76 │     DUT.m_axis_tready := 1'b0;
    │     ^^^^^^^^^^^^^^^^^^^^^^^^^^ [idle@1] executing step 0 of the transaction: 1 != 0
 
 
@@ -37,10 +25,21 @@ trace {
     reset();  // [time: 0ns -> 25ns]
 }
 error: [pop@1] executing step 0 of the transaction: 0 != 1
-   ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot:62:5
+   ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4.prot:57:5
    │
-62 │     assert_eq(DUT.m_axis_tvalid, 1'b1);
+57 │     assert_eq(DUT.m_axis_tvalid, 1'b1);
    │     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ [pop@1] executing step 0 of the transaction: 0 != 1
 
+
+// trace 3
+trace {
+    reset();  // [time: 0ns -> 25ns]
+}
+error: [push@1] executing step 0 of the transaction: 0 != 1
+   ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4.prot:35:5
+   │
+35 │     DUT.s_axis_tvalid := 1'b1;
+   │     ^^^^^^^^^^^^^^^^^^^^^^^^^^ [push@1] executing step 0 of the transaction: 0 != 1
+
 ---CODE---
 1
diff --git a/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.fail.expect b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.fail.expect
new file mode 100644
index 00000000..19b70357
--- /dev/null
+++ b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.fail.expect
@@ -0,0 +1 @@
+Assertion failure in cycle 6.
diff --git a/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.interp.expect b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.interp.expect
new file mode 100644
index 00000000..9731d952
--- /dev/null
+++ b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.interp.expect
@@ -0,0 +1,9 @@
+error: The two expressions did not evaluate to the same value (in transaction `pop(1)`)
+   ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4.prot:57:15
+   │
+57 │     assert_eq(DUT.m_axis_tvalid, 1'b1);
+   │               ^^^^^^^^^^^^^^^^^^^^^^^ LHS Value: 0, RHS Value: 1
+
+Trace 0 execution failed.
+---CODE---
+101
diff --git a/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_fixed.bi.expect b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_fixed.bi.expect
index 49910681..e943304d 100644
--- a/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_fixed.bi.expect
+++ b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_fixed.bi.expect
@@ -4,23 +4,297 @@ trace {
     idle();  // [time: 25ns -> 50ns]
     push(1);  // [time: 50ns -> 75ns]
     push(2);  // [time: 75ns -> 100ns]
-    push(3);  // [time: 100ns -> 150ns]
-    push(4);  // [time: 150ns -> 175ns]
+    pop(1);  // [time: 100ns -> 125ns]
+    push(3);  // [time: 125ns -> 150ns]
+    pop(3);  // [time: 150ns -> 175ns]
+    push(5);  // [time: 175ns -> 200ns]
+    pop(5);  // [time: 200ns -> 225ns]
+    push(7);  // [time: 225ns -> 250ns]
+    pop(7);  // [time: 250ns -> 250ns]
+}
+
+// trace 1
+trace {
+    reset();  // [time: 0ns -> 25ns]
+    idle();  // [time: 25ns -> 50ns]
+    push(1);  // [time: 50ns -> 75ns]
+    push(2);  // [time: 75ns -> 100ns]
+    pop(1);  // [time: 100ns -> 125ns]
+    push(3);  // [time: 125ns -> 150ns]
+    pop(3);  // [time: 150ns -> 175ns]
+    push(5);  // [time: 175ns -> 200ns]
+    pop(5);  // [time: 200ns -> 225ns]
+    push(7);  // [time: 225ns -> 250ns]
+    push(8);  // [time: 250ns -> 250ns]
+}
+
+// trace 2
+trace {
+    reset();  // [time: 0ns -> 25ns]
+    idle();  // [time: 25ns -> 50ns]
+    push(1);  // [time: 50ns -> 75ns]
+    push(2);  // [time: 75ns -> 100ns]
+    pop(1);  // [time: 100ns -> 125ns]
+    push(3);  // [time: 125ns -> 150ns]
+    pop(3);  // [time: 150ns -> 175ns]
+    push(5);  // [time: 175ns -> 200ns]
+    pop(5);  // [time: 200ns -> 225ns]
+    pop(6);  // [time: 225ns -> 250ns]
+    pop(7);  // [time: 250ns -> 250ns]
+}
+
+// trace 3
+trace {
+    reset();  // [time: 0ns -> 25ns]
+    idle();  // [time: 25ns -> 50ns]
+    push(1);  // [time: 50ns -> 75ns]
+    push(2);  // [time: 75ns -> 100ns]
+    pop(1);  // [time: 100ns -> 125ns]
+    push(3);  // [time: 125ns -> 150ns]
+    pop(3);  // [time: 150ns -> 175ns]
+    push(5);  // [time: 175ns -> 200ns]
+    pop(5);  // [time: 200ns -> 225ns]
+    pop(6);  // [time: 225ns -> 250ns]
+    push(8);  // [time: 250ns -> 250ns]
+}
+
+// trace 4
+trace {
+    reset();  // [time: 0ns -> 25ns]
+    idle();  // [time: 25ns -> 50ns]
+    push(1);  // [time: 50ns -> 75ns]
+    push(2);  // [time: 75ns -> 100ns]
+    pop(1);  // [time: 100ns -> 125ns]
+    push(3);  // [time: 125ns -> 150ns]
+    pop(3);  // [time: 150ns -> 175ns]
+    push(5);  // [time: 175ns -> 200ns]
+    push(6);  // [time: 200ns -> 225ns]
+    push(7);  // [time: 225ns -> 250ns]
+    pop(7);  // [time: 250ns -> 250ns]
+}
+
+// trace 5
+trace {
+    reset();  // [time: 0ns -> 25ns]
+    idle();  // [time: 25ns -> 50ns]
+    push(1);  // [time: 50ns -> 75ns]
+    push(2);  // [time: 75ns -> 100ns]
+    pop(1);  // [time: 100ns -> 125ns]
+    push(3);  // [time: 125ns -> 150ns]
+    pop(3);  // [time: 150ns -> 175ns]
     push(5);  // [time: 175ns -> 200ns]
     push(6);  // [time: 200ns -> 225ns]
     push(7);  // [time: 225ns -> 250ns]
     push(8);  // [time: 250ns -> 250ns]
 }
-// trace 0
+
+// trace 6
+trace {
+    reset();  // [time: 0ns -> 25ns]
+    idle();  // [time: 25ns -> 50ns]
+    push(1);  // [time: 50ns -> 75ns]
+    push(2);  // [time: 75ns -> 100ns]
+    pop(1);  // [time: 100ns -> 125ns]
+    push(3);  // [time: 125ns -> 150ns]
+    pop(3);  // [time: 150ns -> 175ns]
+    push(5);  // [time: 175ns -> 200ns]
+    push(6);  // [time: 200ns -> 225ns]
+    pop(6);  // [time: 225ns -> 250ns]
+    pop(7);  // [time: 250ns -> 250ns]
+}
+
+// trace 7
+trace {
+    reset();  // [time: 0ns -> 25ns]
+    idle();  // [time: 25ns -> 50ns]
+    push(1);  // [time: 50ns -> 75ns]
+    push(2);  // [time: 75ns -> 100ns]
+    pop(1);  // [time: 100ns -> 125ns]
+    push(3);  // [time: 125ns -> 150ns]
+    pop(3);  // [time: 150ns -> 175ns]
+    push(5);  // [time: 175ns -> 200ns]
+    push(6);  // [time: 200ns -> 225ns]
+    pop(6);  // [time: 225ns -> 250ns]
+    push(8);  // [time: 250ns -> 250ns]
+}
+
+// trace 8
+trace {
+    reset();  // [time: 0ns -> 25ns]
+    idle();  // [time: 25ns -> 50ns]
+    push(1);  // [time: 50ns -> 75ns]
+    push(2);  // [time: 75ns -> 100ns]
+    pop(1);  // [time: 100ns -> 125ns]
+    push(3);  // [time: 125ns -> 150ns]
+    pop(3);  // [time: 150ns -> 175ns]
+    pop(4);  // [time: 175ns -> 200ns]
+    pop(5);  // [time: 200ns -> 225ns]
+    push(7);  // [time: 225ns -> 250ns]
+    pop(7);  // [time: 250ns -> 250ns]
+}
+
+// trace 9
+trace {
+    reset();  // [time: 0ns -> 25ns]
+    idle();  // [time: 25ns -> 50ns]
+    push(1);  // [time: 50ns -> 75ns]
+    push(2);  // [time: 75ns -> 100ns]
+    pop(1);  // [time: 100ns -> 125ns]
+    push(3);  // [time: 125ns -> 150ns]
+    pop(3);  // [time: 150ns -> 175ns]
+    pop(4);  // [time: 175ns -> 200ns]
+    pop(5);  // [time: 200ns -> 225ns]
+    push(7);  // [time: 225ns -> 250ns]
+    push(8);  // [time: 250ns -> 250ns]
+}
+
+// trace 10
+trace {
+    reset();  // [time: 0ns -> 25ns]
+    idle();  // [time: 25ns -> 50ns]
+    push(1);  // [time: 50ns -> 75ns]
+    push(2);  // [time: 75ns -> 100ns]
+    pop(1);  // [time: 100ns -> 125ns]
+    push(3);  // [time: 125ns -> 150ns]
+    pop(3);  // [time: 150ns -> 175ns]
+    pop(4);  // [time: 175ns -> 200ns]
+    pop(5);  // [time: 200ns -> 225ns]
+    pop(6);  // [time: 225ns -> 250ns]
+    pop(7);  // [time: 250ns -> 250ns]
+}
+
+// trace 11
+trace {
+    reset();  // [time: 0ns -> 25ns]
+    idle();  // [time: 25ns -> 50ns]
+    push(1);  // [time: 50ns -> 75ns]
+    push(2);  // [time: 75ns -> 100ns]
+    pop(1);  // [time: 100ns -> 125ns]
+    push(3);  // [time: 125ns -> 150ns]
+    pop(3);  // [time: 150ns -> 175ns]
+    pop(4);  // [time: 175ns -> 200ns]
+    pop(5);  // [time: 200ns -> 225ns]
+    pop(6);  // [time: 225ns -> 250ns]
+    push(8);  // [time: 250ns -> 250ns]
+}
+
+// trace 12
+trace {
+    reset();  // [time: 0ns -> 25ns]
+    idle();  // [time: 25ns -> 50ns]
+    push(1);  // [time: 50ns -> 75ns]
+    push(2);  // [time: 75ns -> 100ns]
+    pop(1);  // [time: 100ns -> 125ns]
+    push(3);  // [time: 125ns -> 150ns]
+    pop(3);  // [time: 150ns -> 175ns]
+    pop(4);  // [time: 175ns -> 200ns]
+    push(6);  // [time: 200ns -> 225ns]
+    push(7);  // [time: 225ns -> 250ns]
+    pop(7);  // [time: 250ns -> 250ns]
+}
+
+// trace 13
+trace {
+    reset();  // [time: 0ns -> 25ns]
+    idle();  // [time: 25ns -> 50ns]
+    push(1);  // [time: 50ns -> 75ns]
+    push(2);  // [time: 75ns -> 100ns]
+    pop(1);  // [time: 100ns -> 125ns]
+    push(3);  // [time: 125ns -> 150ns]
+    pop(3);  // [time: 150ns -> 175ns]
+    pop(4);  // [time: 175ns -> 200ns]
+    push(6);  // [time: 200ns -> 225ns]
+    push(7);  // [time: 225ns -> 250ns]
+    push(8);  // [time: 250ns -> 250ns]
+}
+
+// trace 14
+trace {
+    reset();  // [time: 0ns -> 25ns]
+    idle();  // [time: 25ns -> 50ns]
+    push(1);  // [time: 50ns -> 75ns]
+    push(2);  // [time: 75ns -> 100ns]
+    pop(1);  // [time: 100ns -> 125ns]
+    push(3);  // [time: 125ns -> 150ns]
+    pop(3);  // [time: 150ns -> 175ns]
+    pop(4);  // [time: 175ns -> 200ns]
+    push(6);  // [time: 200ns -> 225ns]
+    pop(6);  // [time: 225ns -> 250ns]
+    pop(7);  // [time: 250ns -> 250ns]
+}
+
+// trace 15
+trace {
+    reset();  // [time: 0ns -> 25ns]
+    idle();  // [time: 25ns -> 50ns]
+    push(1);  // [time: 50ns -> 75ns]
+    push(2);  // [time: 75ns -> 100ns]
+    pop(1);  // [time: 100ns -> 125ns]
+    push(3);  // [time: 125ns -> 150ns]
+    pop(3);  // [time: 150ns -> 175ns]
+    pop(4);  // [time: 175ns -> 200ns]
+    push(6);  // [time: 200ns -> 225ns]
+    pop(6);  // [time: 225ns -> 250ns]
+    push(8);  // [time: 250ns -> 250ns]
+}
+
+// trace 16
+trace {
+    reset();  // [time: 0ns -> 25ns]
+    idle();  // [time: 25ns -> 50ns]
+    push(1);  // [time: 50ns -> 75ns]
+    push(2);  // [time: 75ns -> 100ns]
+    pop(1);  // [time: 100ns -> 125ns]
+    push(3);  // [time: 125ns -> 150ns]
+    push(4);  // [time: 150ns -> 175ns]
+    push(5);  // [time: 175ns -> 200ns]
+    pop(5);  // [time: 200ns -> 225ns]
+    push(7);  // [time: 225ns -> 250ns]
+    pop(7);  // [time: 250ns -> 250ns]
+}
+
+// trace 17
+trace {
+    reset();  // [time: 0ns -> 25ns]
+    idle();  // [time: 25ns -> 50ns]
+    push(1);  // [time: 50ns -> 75ns]
+    push(2);  // [time: 75ns -> 100ns]
+    pop(1);  // [time: 100ns -> 125ns]
+    push(3);  // [time: 125ns -> 150ns]
+    push(4);  // [time: 150ns -> 175ns]
+    push(5);  // [time: 175ns -> 200ns]
+    pop(5);  // [time: 200ns -> 225ns]
+    push(7);  // [time: 225ns -> 250ns]
+    push(8);  // [time: 250ns -> 250ns]
+}
+
+// trace 18
 trace {
     reset();  // [time: 0ns -> 25ns]
     idle();  // [time: 25ns -> 50ns]
-    idle();  // [time: 50ns -> 75ns]
-    idle();  // [time: 75ns -> 100ns]
-    pop(2);  // [time: 100ns -> 150ns]
-    pop(3);  // [time: 125ns -> 175ns]
-    pop(4);  // [time: 150ns -> 200ns]
-    pop(5);  // [time: 175ns -> 225ns]
-    pop(6);  // [time: 200ns -> 250ns]
-    pop(7);  // [time: 225ns -> 250ns]
+    push(1);  // [time: 50ns -> 75ns]
+    push(2);  // [time: 75ns -> 100ns]
+    pop(1);  // [time: 100ns -> 125ns]
+    push(3);  // [time: 125ns -> 150ns]
+    push(4);  // [time: 150ns -> 175ns]
+    push(5);  // [time: 175ns -> 200ns]
+    pop(5);  // [time: 200ns -> 225ns]
+    pop(6);  // [time: 225ns -> 250ns]
+    pop(7);  // [time: 250ns -> 250ns]
+}
+
+// trace 19
+trace {
+    reset();  // [time: 0ns -> 25ns]
+    idle();  // [time: 25ns -> 50ns]
+    push(1);  // [time: 50ns -> 75ns]
+    push(2);  // [time: 75ns -> 100ns]
+    pop(1);  // [time: 100ns -> 125ns]
+    push(3);  // [time: 125ns -> 150ns]
+    push(4);  // [time: 150ns -> 175ns]
+    push(5);  // [time: 175ns -> 200ns]
+    pop(5);  // [time: 200ns -> 225ns]
+    pop(6);  // [time: 225ns -> 250ns]
+    push(8);  // [time: 250ns -> 250ns]
 }
+Displayed 20/96 traces.
diff --git a/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_fixed.graph_interp.expect b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_fixed.graph_interp.expect
new file mode 100644
index 00000000..f5f6cb49
--- /dev/null
+++ b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_fixed.graph_interp.expect
@@ -0,0 +1 @@
+Trace 0 executed successfully!
diff --git a/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_fixed.interp.expect b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_fixed.interp.expect
new file mode 100644
index 00000000..f5f6cb49
--- /dev/null
+++ b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_fixed.interp.expect
@@ -0,0 +1 @@
+Trace 0 executed successfully!
diff --git a/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_fixed.waveform.expect b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_fixed.waveform.expect
new file mode 100644
index 00000000..7b09eb0c
--- /dev/null
+++ b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_fixed.waveform.expect
@@ -0,0 +1,8 @@
+Trace 0 executed successfully!
+m_axis_tready     x 0 x x x x x 0 1 1
+s_axis_tvalid     0 0 1 1 1 1 1 0 x x
+s_axis_tdata[7:0] x x 1 1 1 2 3 x x x
+rst               1 0 0 0 0 0 0 0 0 0
+m_axis_tdata[7:0] 0 0 0 0 0 0 0 0 1 2
+m_axis_tvalid     0 0 0 0 0 0 0 0 1 1
+s_axis_tready     0 0 0 0 1 1 1 1 1 1
diff --git a/tools/protocols-textmate/package.json b/tools/protocols-textmate/package.json
index 90bf9cdc..9613781a 100644
--- a/tools/protocols-textmate/package.json
+++ b/tools/protocols-textmate/package.json
@@ -34,7 +34,8 @@
           "transactions"
         ],
         "extensions": [
-          ".tx"
+          ".tx",
+          ".bi.expect"
         ],
         "configuration": "./transactions-configuration.json"
       }