diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml
index 368b971f..a2f4bffa 100644
--- a/.github/workflows/test.yml
+++ b/.github/workflows/test.yml
@@ -36,6 +36,8 @@ jobs:
       run: runt runt/graph_interp
     - name: Run Runt tests for monitor
       run: runt runt/monitor
+    - name: Run Runt tests for bi
+      run: runt runt/bi
     - name: Run Runt tests for waveform
       run: runt runt/waveform
     - name: Run Runt tests for fail
diff --git a/bi/src/main.rs b/bi/src/main.rs
index 6ab49d37..88fd2b7a 100644
--- a/bi/src/main.rs
+++ b/bi/src/main.rs
@@ -75,6 +75,11 @@ struct Cli {
     #[arg(long)]
     max_traces: Option<u32>,
 
+    /// To suppress colors in error messages, pass in `--color never`.
+    /// Otherwise, by default, error messages are displayed with colors.
+    #[arg(long, value_name = "COLOR_CHOICE", default_value = "auto")]
+    color: ColorChoice,
+
     /// If enabled, displays integer literals using hexadecimal notation
     #[arg(short, long, value_name = "DISPLAY_IN_HEX")]
     display_hex: bool,
@@ -86,6 +91,14 @@ struct Cli {
 
 #[allow(unused_variables)]
 fn main() -> Result<(), Box<dyn std::error::Error>> {
+    // By default, a Rust panic error messages prints the OS's thread ID
+    // (e.g. `"thread 'main' (<tid>)`), but this changes every time we run this executable.
+    // To prevent the TID from appearing in error messages that appear in the expected
+    // output files for Runt, we register a custom panic hook that only prints
+    // the error message & source code location associated with the panic
+    // (via the `Display` trait for the `PanicHookInfo` type).
+    std::panic::set_hook(Box::new(|info| eprintln!("{}", info)));
+
     // Parse CLI args
     let cli = Cli::parse();
 
@@ -96,7 +109,7 @@ fn main() -> Result<(), Box<dyn std::error::Error>> {
     // parse protocol file
     let show_warnings = false;
     let skip_static_step_fork_checks = false;
-    let mut d = DiagnosticHandler::new(ColorChoice::Auto, false, show_warnings, false);
+    let mut d = DiagnosticHandler::new(cli.color, false, show_warnings, false);
     let (st, modules) = frontend(&cli.protocol, &mut d, skip_static_step_fork_checks)?;
 
     // try to find instances that we care about
diff --git a/justfile b/justfile
index db492b4a..b0742574 100644
--- a/justfile
+++ b/justfile
@@ -1,8 +1,9 @@
 # Runs the Runt snapshot suites that together cover every test
 runt:
-  cargo build --offline --package protocols-interp --package protocols-monitor --package graph-interp
+  cargo build --offline --package protocols-interp --package protocols-monitor --package graph-interp --package bi
   runt --max-futures 1 runt/interp
   runt --max-futures 1 runt/monitor
+  runt --max-futures 1 runt/bi
   runt --max-futures 1 runt/graph_interp
   runt --max-futures 1 runt/waveform
   runt --max-futures 1 runt/fail
diff --git a/runt/bi/runt.toml b/runt/bi/runt.toml
new file mode 100644
index 00000000..c188ce6f
--- /dev/null
+++ b/runt/bi/runt.toml
@@ -0,0 +1,1549 @@
+ver = "0.4.1"
+
+[[tests]]
+name = "bi.tests_adders_add_d1.add_d1_bi"
+paths = [
+  "../../tests/adders/add_d1.prot",
+]
+expect_dir = "../../tests/adders/expects"
+expect_name = "add_d1.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/adders/add_d1.prot --wave tests/adders/add_d1.fst --instances add_d1:Adder 2>&1"
+
+[[tests]]
+name = "bi.tests_adders_add_d2.add_d2_bi"
+paths = [
+  "../../tests/adders/add_d2.prot",
+]
+expect_dir = "../../tests/adders/expects"
+expect_name = "add_d2.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/adders/add_d2.prot --wave tests/adders/add_d2.fst --instances add_d2:Adder 2>&1"
+
+[[tests]]
+name = "bi.tests_adders_add_var_cyc.add_var_cyc_bi"
+paths = [
+  "../../tests/adders/add_var_cyc.prot",
+]
+expect_dir = "../../tests/adders/expects"
+expect_name = "add_var_cyc.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/adders/add_var_cyc.prot --wave tests/adders/loop_with_assigns.fst --instances add_d1:Adder 2>&1"
+
+[[tests]]
+name = "bi.tests_adders_busy_wait.busy_wait_bi"
+paths = [
+  "../../tests/adders/busy_wait.prot",
+]
+expect_dir = "../../tests/adders/expects"
+expect_name = "busy_wait.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/adders/busy_wait.prot --wave tests/adders/busy_wait.fst --instances add_d1:Adder 2>&1"
+
+[[tests]]
+name = "bi.tests_adders_loop_with_assigns.loop_with_assigns_bi"
+paths = [
+  "../../tests/adders/loop_with_assigns.prot",
+]
+expect_dir = "../../tests/adders/expects"
+expect_name = "loop_with_assigns.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/adders/loop_with_assigns.prot --wave tests/adders/loop_with_assigns.fst --instances add_d1:Adder 2>&1"
+
+[[tests]]
+name = "bi.tests_adders_nested_busy_wait.nested_busy_wait_bi"
+paths = [
+  "../../tests/adders/nested_busy_wait.prot",
+]
+expect_dir = "../../tests/adders/expects"
+expect_name = "nested_busy_wait.bi.expect"
+cmd = "cd ../.. && python3 -c 'import os, signal, subprocess, sys\np = subprocess.Popen(sys.argv[2:], start_new_session=True)\ntry:\n    sys.exit(p.wait(timeout=float(sys.argv[1])))\nexcept subprocess.TimeoutExpired:\n    os.killpg(p.pid, signal.SIGKILL)\n    sys.exit(124)\n' 5 target/debug/bi --color never --protocol tests/adders/nested_busy_wait.prot --wave tests/adders/nested_busy_wait.fst --instances add_d1:Adder 2>&1"
+
+[[tests]]
+name = "bi.tests_alus_alu_d1_monitor.alu_d1_bi"
+paths = [
+  "../../tests/alus/alu_d1.monitor.prot",
+]
+expect_dir = "../../tests/alus/expects"
+expect_name = "alu_d1.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/alus/alu_d1.monitor.prot --wave tests/alus/alu_d1.fst --instances alu_d1:ALU 2>&1"
+
+[[tests]]
+name = "bi.tests_alus_alu_d2_monitor.alu_d2_bi"
+paths = [
+  "../../tests/alus/alu_d2.monitor.prot",
+]
+expect_dir = "../../tests/alus/expects"
+expect_name = "alu_d2.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/alus/alu_d2.monitor.prot --wave tests/alus/alu_d2.fst --instances alu_d2:ALU 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_classic_1_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/fifo_classic/expects"
+expect_name = "test_fifo_classic_1.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_classic_2_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/fifo_classic/expects"
+expect_name = "test_fifo_classic_2.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_classic_3_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/fifo_classic/expects"
+expect_name = "test_fifo_classic_3.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_classic_4_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/fifo_classic/expects"
+expect_name = "test_fifo_classic_4.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_classic_5_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/fifo_classic/expects"
+expect_name = "test_fifo_classic_5.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_5.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_classic_6_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/fifo_classic/expects"
+expect_name = "test_fifo_classic_6.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_6.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_classic_7_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/fifo_classic/expects"
+expect_name = "test_fifo_classic_7.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_7.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_classic_8_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/fifo_classic/expects"
+expect_name = "test_fifo_classic_8.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_classic/test_fifo_classic_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_constant_1_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/fifo_constant/expects"
+expect_name = "test_fifo_constant_1.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_constant_2_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/fifo_constant/expects"
+expect_name = "test_fifo_constant_2.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_constant_3_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/fifo_constant/expects"
+expect_name = "test_fifo_constant_3.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_constant_4_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/fifo_constant/expects"
+expect_name = "test_fifo_constant_4.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_constant_5_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/fifo_constant/expects"
+expect_name = "test_fifo_constant_5.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_5.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_constant_6_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/fifo_constant/expects"
+expect_name = "test_fifo_constant_6.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_6.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_constant_7_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/fifo_constant/expects"
+expect_name = "test_fifo_constant_7.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_7.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_fifo_constant_8_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/fifo_constant/expects"
+expect_name = "test_fifo_constant_8.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/fifo_constant/test_fifo_constant_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_16_0_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_classic/expects"
+expect_name = "test_sram_classic_16_0.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_16_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_16_12_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_classic/expects"
+expect_name = "test_sram_classic_16_12.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_16_12.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_16_4_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_classic/expects"
+expect_name = "test_sram_classic_16_4.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_16_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_16_8_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_classic/expects"
+expect_name = "test_sram_classic_16_8.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_16_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_1_0_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_classic/expects"
+expect_name = "test_sram_classic_1_0.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_1_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_1_12_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_classic/expects"
+expect_name = "test_sram_classic_1_12.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_1_12.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_1_4_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_classic/expects"
+expect_name = "test_sram_classic_1_4.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_1_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_1_8_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_classic/expects"
+expect_name = "test_sram_classic_1_8.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_1_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_2_0_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_classic/expects"
+expect_name = "test_sram_classic_2_0.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_2_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_2_12_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_classic/expects"
+expect_name = "test_sram_classic_2_12.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_2_12.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_2_4_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_classic/expects"
+expect_name = "test_sram_classic_2_4.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_2_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_2_8_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_classic/expects"
+expect_name = "test_sram_classic_2_8.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_2_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_4_0_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_classic/expects"
+expect_name = "test_sram_classic_4_0.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_4_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_4_12_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_classic/expects"
+expect_name = "test_sram_classic_4_12.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_4_12.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_4_4_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_classic/expects"
+expect_name = "test_sram_classic_4_4.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_4_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_4_8_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_classic/expects"
+expect_name = "test_sram_classic_4_8.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_4_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_8_0_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_classic/expects"
+expect_name = "test_sram_classic_8_0.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_8_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_8_12_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_classic/expects"
+expect_name = "test_sram_classic_8_12.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_8_12.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_8_4_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_classic/expects"
+expect_name = "test_sram_classic_8_4.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_8_4.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_classic_8_8_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_classic/expects"
+expect_name = "test_sram_classic_8_8.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_classic/test_sram_classic_8_8.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_0_0_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_16_0_0.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_0_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_0_1_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_16_0_1.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_0_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_0_2_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_16_0_2.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_0_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_0_3_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_16_0_3.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_0_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_12_0_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_16_12_0.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_12_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_12_1_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_16_12_1.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_12_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_12_2_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_16_12_2.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_12_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_12_3_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_16_12_3.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_12_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_4_0_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_16_4_0.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_4_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_4_1_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_16_4_1.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_4_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_4_2_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_16_4_2.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_4_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_4_3_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_16_4_3.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_4_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_8_0_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_16_8_0.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_8_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_8_1_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_16_8_1.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_8_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_8_2_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_16_8_2.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_8_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_16_8_3_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_16_8_3.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_16_8_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_0_0_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_1_0_0.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_0_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_0_1_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_1_0_1.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_0_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_0_2_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_1_0_2.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_0_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_0_3_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_1_0_3.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_0_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_12_0_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_1_12_0.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_12_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_12_1_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_1_12_1.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_12_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_12_2_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_1_12_2.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_12_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_12_3_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_1_12_3.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_12_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_4_0_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_1_4_0.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_4_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_4_1_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_1_4_1.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_4_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_4_2_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_1_4_2.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_4_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_4_3_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_1_4_3.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_4_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_8_0_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_1_8_0.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_8_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_8_1_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_1_8_1.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_8_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_8_2_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_1_8_2.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_8_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_1_8_3_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_1_8_3.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_1_8_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_0_0_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_2_0_0.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_0_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_0_1_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_2_0_1.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_0_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_0_2_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_2_0_2.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_0_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_0_3_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_2_0_3.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_0_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_12_0_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_2_12_0.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_12_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_12_1_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_2_12_1.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_12_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_12_2_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_2_12_2.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_12_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_12_3_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_2_12_3.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_12_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_4_0_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_2_4_0.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_4_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_4_1_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_2_4_1.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_4_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_4_2_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_2_4_2.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_4_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_4_3_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_2_4_3.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_4_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_8_0_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_2_8_0.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_8_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_8_1_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_2_8_1.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_8_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_8_2_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_2_8_2.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_8_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_2_8_3_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_2_8_3.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_2_8_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_0_0_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_4_0_0.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_0_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_0_1_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_4_0_1.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_0_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_0_2_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_4_0_2.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_0_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_0_3_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_4_0_3.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_0_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_12_0_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_4_12_0.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_12_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_12_1_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_4_12_1.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_12_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_12_2_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_4_12_2.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_12_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_12_3_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_4_12_3.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_12_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_4_0_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_4_4_0.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_4_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_4_1_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_4_4_1.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_4_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_4_2_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_4_4_2.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_4_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_4_3_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_4_4_3.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_4_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_8_0_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_4_8_0.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_8_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_8_1_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_4_8_1.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_8_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_8_2_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_4_8_2.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_8_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_4_8_3_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_4_8_3.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_4_8_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_0_0_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_8_0_0.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_0_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_0_1_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_8_0_1.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_0_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_0_2_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_8_0_2.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_0_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_0_3_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_8_0_3.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_0_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_12_0_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_8_12_0.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_12_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_12_1_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_8_12_1.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_12_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_12_2_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_8_12_2.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_12_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_12_3_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_8_12_3.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_12_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_4_0_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_8_4_0.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_4_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_4_1_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_8_4_1.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_4_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_4_2_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_8_4_2.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_4_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_4_3_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_8_4_3.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_4_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_8_0_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_8_8_0.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_8_0.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_8_1_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_8_8_1.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_8_1.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_8_2_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_8_8_2.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_8_2.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_antmicro_wishbone_subordinate.test_sram_incrementing_8_8_3_bi"
+paths = [
+  "../../tests/antmicro/wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/antmicro/sram_incrementing/expects"
+expect_name = "test_sram_incrementing_8_8_3.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/antmicro/wishbone_subordinate.prot --wave tests/antmicro/sram_incrementing/test_sram_incrementing_8_8_3.fst --instances tb.dut:WBSubordinate --sample-posedge tb.dut.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_brave_new_world_francis_bit_truncation_fft.bit_truncation_fft_bi"
+paths = [
+  "../../tests/brave_new_world_francis/bit_truncation_fft.prot",
+]
+expect_dir = "../../tests/brave_new_world_francis/expects"
+expect_name = "bit_truncation_fft.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/brave_new_world_francis/bit_truncation_fft.prot --wave tests/brave_new_world_francis/bit_truncation_fft.fst --instances round11_rne_unsigned_fixed:BitTruncationFFT 2>&1"
+
+[[tests]]
+name = "bi.tests_brave_new_world_francis_bit_truncation_sha.bit_truncation_sha_bi"
+paths = [
+  "../../tests/brave_new_world_francis/bit_truncation_sha.prot",
+]
+expect_dir = "../../tests/brave_new_world_francis/expects"
+expect_name = "bit_truncation_sha.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/brave_new_world_francis/bit_truncation_sha.prot --wave tests/brave_new_world_francis/bit_truncation_sha.fst --instances bit_truncation_sha_fixed:bit_truncation_sha 2>&1"
+
+[[tests]]
+name = "bi.tests_brave_new_world_francis_ftu_sha.ftu_sha_bi"
+paths = [
+  "../../tests/brave_new_world_francis/ftu_sha.prot",
+]
+expect_dir = "../../tests/brave_new_world_francis/expects"
+expect_name = "ftu_sha.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/brave_new_world_francis/ftu_sha.prot --wave tests/brave_new_world_francis/ftu_sha.fst --instances fsm_update_fixed_gated:FailureToUpdateSHA 2>&1"
+
+[[tests]]
+name = "bi.tests_brave_new_world_francis_signal_async.signal_async_bi"
+paths = [
+  "../../tests/brave_new_world_francis/signal_async.prot",
+]
+expect_dir = "../../tests/brave_new_world_francis/expects"
+expect_name = "signal_async.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/brave_new_world_francis/signal_async.prot --wave tests/brave_new_world_francis/signal_async.fst --instances signal_async_fix:SignalAsyncSpec 2>&1"
+
+[[tests]]
+name = "bi.tests_brave_new_world_francis_use_without_valid.use_without_valid_bi"
+paths = [
+  "../../tests/brave_new_world_francis/use_without_valid.prot",
+]
+expect_dir = "../../tests/brave_new_world_francis/expects"
+expect_name = "use_without_valid.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/brave_new_world_francis/use_without_valid.prot --wave tests/brave_new_world_francis/use_without_valid.fst --instances use_without_valid_fix:UseWithoutValid 2>&1"
+
+[[tests]]
+name = "bi.tests_ethmac_ethmac_wishbone_manager.ethmac_wishbone_manager_bi"
+paths = [
+  "../../tests/ethmac/ethmac_wishbone_manager.prot",
+]
+expect_dir = "../../tests/ethmac/expects"
+expect_name = "ethmac_wishbone_manager.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/ethmac/ethmac_wishbone_manager.prot --instances tb_ethernet:WBManager --sample-posedge tb_ethernet.wb_clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_ethmac_ethmac_wishbone_subordinate.ethmac_wishbone_subordinate_bi"
+paths = [
+  "../../tests/ethmac/ethmac_wishbone_subordinate.prot",
+]
+expect_dir = "../../tests/ethmac/expects"
+expect_name = "ethmac_wishbone_subordinate.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/ethmac/ethmac_wishbone_subordinate.prot --instances tb_ethernet:WBSubordinate --sample-posedge tb_ethernet.wb_clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_fifo_fifo_monitor.fifo_bi"
+paths = [
+  "../../tests/fifo/fifo.monitor.prot",
+]
+expect_dir = "../../tests/fifo/expects"
+expect_name = "fifo.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fifo/fifo.monitor.prot --wave tests/fifo/fifo.fst --instances fifo_wrapper:Fifo 2>&1"
+
+[[tests]]
+name = "bi.tests_fifo_push_pop_identity.push_pop_identity_bi"
+paths = [
+  "../../tests/fifo/push_pop_identity.prot",
+]
+expect_dir = "../../tests/fifo/expects"
+expect_name = "push_pop_identity.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fifo/push_pop_identity.prot --wave tests/fifo/push_pop_identity.fst --instances fifo_wrapper:Fifo 2>&1"
+
+[[tests]]
+name = "bi.tests_fifo_push_pop_loop_empty.push_pop_loop_empty_bi"
+paths = [
+  "../../tests/fifo/push_pop_loop_empty.prot",
+]
+expect_dir = "../../tests/fifo/expects"
+expect_name = "push_pop_loop_empty.bi.expect"
+cmd = "cd ../.. && python3 -c 'import os, signal, subprocess, sys\np = subprocess.Popen(sys.argv[2:], start_new_session=True)\ntry:\n    sys.exit(p.wait(timeout=float(sys.argv[1])))\nexcept subprocess.TimeoutExpired:\n    os.killpg(p.pid, signal.SIGKILL)\n    sys.exit(124)\n' 5 target/debug/bi --color never --protocol tests/fifo/push_pop_loop_empty.prot --wave tests/fifo/push_pop_loop_empty.fst --instances fifo_wrapper:Fifo 2>&1"
+
+[[tests]]
+name = "bi.tests_fifo_push_pop_loop_not_empty.push_pop_loop_not_empty_bi"
+paths = [
+  "../../tests/fifo/push_pop_loop_not_empty.prot",
+]
+expect_dir = "../../tests/fifo/expects"
+expect_name = "push_pop_loop_not_empty.bi.expect"
+cmd = "cd ../.. && python3 -c 'import os, signal, subprocess, sys\np = subprocess.Popen(sys.argv[2:], start_new_session=True)\ntry:\n    sys.exit(p.wait(timeout=float(sys.argv[1])))\nexcept subprocess.TimeoutExpired:\n    os.killpg(p.pid, signal.SIGKILL)\n    sys.exit(124)\n' 5 target/debug/bi --color never --protocol tests/fifo/push_pop_loop_not_empty.prot --wave tests/fifo/push_pop_loop_not_empty.fst --instances fifo_wrapper:Fifo 2>&1"
+
+[[tests]]
+name = "bi.tests_fpga_debugging_axi_burst_s4_s4_buggy.s4_buggy_bi"
+paths = [
+  "../../tests/fpga-debugging/axi-burst-s4/s4_buggy.prot",
+]
+expect_dir = "../../tests/fpga-debugging/axi-burst-s4/expects"
+expect_name = "s4_buggy.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axi-burst-s4/s4_buggy.prot --wave tests/fpga-debugging/axi-burst-s4/s4_buggy.vcd --instances TOP.test_l2_cache_wait_state.axi_bus:WriteSubordinate --sample-posedge TOP.test_l2_cache_wait_state.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_fpga_debugging_axi_burst_s4_s4_fixed.s4_fixed_bi"
+paths = [
+  "../../tests/fpga-debugging/axi-burst-s4/s4_fixed.prot",
+]
+expect_dir = "../../tests/fpga-debugging/axi-burst-s4/expects"
+expect_name = "s4_fixed.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axi-burst-s4/s4_fixed.prot --wave tests/fpga-debugging/axi-burst-s4/s4_fixed.vcd --instances TOP.test_l2_cache_wait_state.axi_bus:WriteSubordinate --sample-posedge TOP.test_l2_cache_wait_state.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_fpga_debugging_axi_lite_s1_s1_buggy.s1_buggy_bi"
+paths = [
+  "../../tests/fpga-debugging/axi-lite-s1/s1_buggy.prot",
+]
+expect_dir = "../../tests/fpga-debugging/axi-lite-s1/expects"
+expect_name = "s1_buggy.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axi-lite-s1/s1_buggy.prot --wave tests/fpga-debugging/axi-lite-s1/s1_buggy_workload2.vcd --instances TOP.testbench.UUT:WriteSubordinate TOP.testbench.UUT:ReadSubordinate --sample-posedge TOP.testbench.UUT.S_AXI_ACLK --show-waveform-time --time-unit ns --include-idle 2>&1"
+
+[[tests]]
+name = "bi.tests_fpga_debugging_axi_lite_s1_s1_buggy_workload_1.s1_buggy_workload_1_bi"
+paths = [
+  "../../tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot",
+]
+expect_dir = "../../tests/fpga-debugging/axi-lite-s1/expects"
+expect_name = "s1_buggy_workload_1.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot --wave tests/fpga-debugging/axi-lite-s1/s1_buggy_workload1.vcd --instances TOP.testbench.UUT:WriteSubordinate TOP.testbench.UUT:ReadSubordinate --sample-posedge TOP.testbench.UUT.S_AXI_ACLK --show-waveform-time --time-unit ns --include-idle 2>&1"
+
+[[tests]]
+name = "bi.tests_fpga_debugging_axi_lite_s1_s1_fixed.s1_fixed_bi"
+paths = [
+  "../../tests/fpga-debugging/axi-lite-s1/s1_fixed.prot",
+]
+expect_dir = "../../tests/fpga-debugging/axi-lite-s1/expects"
+expect_name = "s1_fixed.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axi-lite-s1/s1_fixed.prot --wave tests/fpga-debugging/axi-lite-s1/s1_fixed_workload2.vcd --instances TOP.testbench.UUT:WriteSubordinate TOP.testbench.UUT:ReadSubordinate --sample-posedge TOP.testbench.UUT.S_AXI_ACLK --show-waveform-time --time-unit ns --include-idle 2>&1"
+
+[[tests]]
+name = "bi.tests_fpga_debugging_axi_lite_s1_s1_fixed_workload_1.s1_fixed_workload_1_bi"
+paths = [
+  "../../tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot",
+]
+expect_dir = "../../tests/fpga-debugging/axi-lite-s1/expects"
+expect_name = "s1_fixed_workload_1.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot --wave tests/fpga-debugging/axi-lite-s1/s1_fixed_workload1.vcd --instances TOP.testbench.UUT:WriteSubordinate TOP.testbench.UUT:ReadSubordinate --sample-posedge TOP.testbench.UUT.S_AXI_ACLK --show-waveform-time --time-unit ns --include-idle 2>&1"
+
+[[tests]]
+name = "bi.tests_fpga_debugging_axi_stream_s2_s2_buggy.s2_buggy_bi"
+paths = [
+  "../../tests/fpga-debugging/axi-stream-s2/s2_buggy.prot",
+]
+expect_dir = "../../tests/fpga-debugging/axi-stream-s2/expects"
+expect_name = "s2_buggy.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axi-stream-s2/s2_buggy.prot --wave tests/fpga-debugging/axi-stream-s2/s2_buggy.fst --instances TOP.testbench.UUT.axi_stream_check:AXISManager --sample-posedge TOP.testbench.UUT.axi_stream_check.i_aclk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_fpga_debugging_axi_stream_s2_s2_fixed.s2_fixed_bi"
+paths = [
+  "../../tests/fpga-debugging/axi-stream-s2/s2_fixed.prot",
+]
+expect_dir = "../../tests/fpga-debugging/axi-stream-s2/expects"
+expect_name = "s2_fixed.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axi-stream-s2/s2_fixed.prot --wave tests/fpga-debugging/axi-stream-s2/s2_fixed.fst --instances TOP.testbench.UUT.axi_stream_check:AXISManager --sample-posedge TOP.testbench.UUT.axi_stream_check.i_aclk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_fpga_debugging_axis_adapter_s3_s3_buggy.s3_buggy_bi"
+paths = [
+  "../../tests/fpga-debugging/axis-adapter-s3/s3_buggy.prot",
+]
+expect_dir = "../../tests/fpga-debugging/axis-adapter-s3/expects"
+expect_name = "s3_buggy.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axis-adapter-s3/s3_buggy.prot --wave tests/fpga-debugging/axis-adapter-s3/s3_buggy.fst --instances TOP.test_axis_adapter_64_8.UUT:AXISManager --sample-posedge TOP.test_axis_adapter_64_8.UUT.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_fpga_debugging_axis_adapter_s3_s3_fixed.s3_fixed_bi"
+paths = [
+  "../../tests/fpga-debugging/axis-adapter-s3/s3_fixed.prot",
+]
+expect_dir = "../../tests/fpga-debugging/axis-adapter-s3/expects"
+expect_name = "s3_fixed.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axis-adapter-s3/s3_fixed.prot --wave tests/fpga-debugging/axis-adapter-s3/s3_fixed.fst --instances TOP.test_axis_adapter_64_8.UUT:AXISManager --sample-posedge TOP.test_axis_adapter_64_8.UUT.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_fpga_debugging_axis_async_fifo_c4_c4_buggy.c4_buggy_bi"
+paths = [
+  "../../tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot",
+]
+expect_dir = "../../tests/fpga-debugging/axis-async-fifo-c4/expects"
+expect_name = "c4_buggy.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot --wave tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.fst --instances TOP.test_axis_async_fifo.UUT.axis_reg_inst:Sender TOP.test_axis_async_fifo.UUT.axis_reg_inst:Receiver --sample-posedge TOP.test_axis_async_fifo.UUT.axis_reg_inst.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_fpga_debugging_axis_async_fifo_c4_c4_fixed.c4_fixed_bi"
+paths = [
+  "../../tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.prot",
+]
+expect_dir = "../../tests/fpga-debugging/axis-async-fifo-c4/expects"
+expect_name = "c4_fixed.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.prot --wave tests/fpga-debugging/axis-async-fifo-c4/c4_fixed.fst --instances TOP.test_axis_async_fifo.UUT.axis_reg_inst:Sender TOP.test_axis_async_fifo.UUT.axis_reg_inst:Receiver --sample-posedge TOP.test_axis_async_fifo.UUT.axis_reg_inst.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_fpga_debugging_axis_fifo_d11_d11_buggy.d11_buggy_bi"
+paths = [
+  "../../tests/fpga-debugging/axis-fifo-d11/d11_buggy.prot",
+]
+expect_dir = "../../tests/fpga-debugging/axis-fifo-d11/expects"
+expect_name = "d11_buggy.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axis-fifo-d11/d11_buggy.prot --wave tests/fpga-debugging/axis-fifo-d11/d11_buggy.fst --instances TOP.test_axis_fifo:AxisFifo --sample-posedge TOP.test_axis_fifo.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_fpga_debugging_axis_fifo_d11_d11_fixed.d11_fixed_bi"
+paths = [
+  "../../tests/fpga-debugging/axis-fifo-d11/d11_fixed.prot",
+]
+expect_dir = "../../tests/fpga-debugging/axis-fifo-d11/expects"
+expect_name = "d11_fixed.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axis-fifo-d11/d11_fixed.prot --wave tests/fpga-debugging/axis-fifo-d11/d11_fixed.fst --instances TOP.test_axis_fifo:AxisFifo --sample-posedge TOP.test_axis_fifo.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_fpga_debugging_axis_fifo_d12_d12_buggy.d12_buggy_bi"
+paths = [
+  "../../tests/fpga-debugging/axis-fifo-d12/d12_buggy.prot",
+]
+expect_dir = "../../tests/fpga-debugging/axis-fifo-d12/expects"
+expect_name = "d12_buggy.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axis-fifo-d12/d12_buggy.prot --wave tests/fpga-debugging/axis-fifo-d12/d12_buggy.fst --instances TOP.test_axis_fifo:AxisFifo --sample-posedge TOP.test_axis_fifo.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_fpga_debugging_axis_fifo_d12_d12_fixed.d12_fixed_bi"
+paths = [
+  "../../tests/fpga-debugging/axis-fifo-d12/d12_fixed.prot",
+]
+expect_dir = "../../tests/fpga-debugging/axis-fifo-d12/expects"
+expect_name = "d12_fixed.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axis-fifo-d12/d12_fixed.prot --wave tests/fpga-debugging/axis-fifo-d12/d12_fixed.fst --instances TOP.test_axis_fifo:AxisFifo --sample-posedge TOP.test_axis_fifo.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_fpga_debugging_axis_fifo_d4_d4_buggy.d4_buggy_bi"
+paths = [
+  "../../tests/fpga-debugging/axis-fifo-d4/d4_buggy.prot",
+]
+expect_dir = "../../tests/fpga-debugging/axis-fifo-d4/expects"
+expect_name = "d4_buggy.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axis-fifo-d4/d4_buggy.prot --wave tests/fpga-debugging/axis-fifo-d4/d4_buggy.fst --instances TOP.axis_fifo_wrapper.axis_fifo_inst:AxisFifo --sample-posedge TOP.axis_fifo_wrapper.axis_fifo_inst.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_fpga_debugging_axis_fifo_d4_d4_fixed.d4_fixed_bi"
+paths = [
+  "../../tests/fpga-debugging/axis-fifo-d4/d4_fixed.prot",
+]
+expect_dir = "../../tests/fpga-debugging/axis-fifo-d4/expects"
+expect_name = "d4_fixed.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/fpga-debugging/axis-fifo-d4/d4_fixed.prot --wave tests/fpga-debugging/axis-fifo-d4/d4_fixed.fst --instances TOP.axis_fifo_wrapper.axis_fifo_inst:AxisFifo --sample-posedge TOP.axis_fifo_wrapper.axis_fifo_inst.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_identities_identity_d1.identity_d1_bi"
+paths = [
+  "../../tests/identities/identity_d1.prot",
+]
+expect_dir = "../../tests/identities/expects"
+expect_name = "identity_d1.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/identities/identity_d1.prot --wave tests/identities/identity_d1.fst --instances identity_d1:Identity 2>&1"
+
+[[tests]]
+name = "bi.tests_multi_multi0.multi0_bi"
+paths = [
+  "../../tests/multi/multi0.prot",
+]
+expect_dir = "../../tests/multi/expects"
+expect_name = "multi0.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/multi/multi0.prot --wave tests/multi/multi0.fst --instances multi0:multi0 2>&1"
+
+[[tests]]
+name = "bi.tests_multi_multi0keep.multi0keep_bi"
+paths = [
+  "../../tests/multi/multi0keep.prot",
+]
+expect_dir = "../../tests/multi/expects"
+expect_name = "multi0keep.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/multi/multi0keep.prot --wave tests/multi/multi0keep.fst --instances multi0keep:multi0keep 2>&1"
+
+[[tests]]
+name = "bi.tests_multi_multi0keep2const.multi0keep2const_bi"
+paths = [
+  "../../tests/multi/multi0keep2const.prot",
+]
+expect_dir = "../../tests/multi/expects"
+expect_name = "multi0keep2const.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/multi/multi0keep2const.prot --wave tests/multi/multi0keep2const.fst --instances multi0keep2const:multi0keep2const 2>&1"
+
+[[tests]]
+name = "bi.tests_multi_multi2const.multi2const_bi"
+paths = [
+  "../../tests/multi/multi2const.prot",
+]
+expect_dir = "../../tests/multi/expects"
+expect_name = "multi2const.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/multi/multi2const.prot --wave tests/multi/multi2const.fst --instances multi2const:multi2const 2>&1"
+
+[[tests]]
+name = "bi.tests_multi_multi2multi.multi2multi_bi"
+paths = [
+  "../../tests/multi/multi2multi.prot",
+]
+expect_dir = "../../tests/multi/expects"
+expect_name = "multi2multi.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/multi/multi2multi.prot --wave tests/multi/multi2multi.fst --instances multi2multi:multi2multi 2>&1"
+
+[[tests]]
+name = "bi.tests_multi_multi_data.multi_data_bi"
+paths = [
+  "../../tests/multi/multi_data.prot",
+]
+expect_dir = "../../tests/multi/expects"
+expect_name = "multi_data.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/multi/multi_data.prot --wave tests/multi/multi_data.fst --instances multi_data:multi_data 2>&1"
+
+[[tests]]
+name = "bi.tests_multipliers_mult_d2.mult_d2_bi"
+paths = [
+  "../../tests/multipliers/mult_d2.prot",
+]
+expect_dir = "../../tests/multipliers/expects"
+expect_name = "mult_d2.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/multipliers/mult_d2.prot --wave tests/multipliers/mult_d2.fst --instances mult_d2:Multiplier 2>&1"
+
+[[tests]]
+name = "bi.tests_picorv32_pcpi_mul_unsigned_mul.pcpi_mul_unsigned_mul_bi"
+paths = [
+  "../../tests/picorv32/pcpi_mul_unsigned_mul.prot",
+]
+expect_dir = "../../tests/picorv32/expects"
+expect_name = "pcpi_mul_unsigned_mul.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/picorv32/pcpi_mul_unsigned_mul.prot --wave tests/picorv32/unsigned_mul.fst --instances picorv32_pcpi_mul:picorv32_pcpi_mul 2>&1"
+
+[[tests]]
+name = "bi.tests_serv_serv_regfile.serv_regfile_bi"
+paths = [
+  "../../tests/serv/serv_regfile.prot",
+]
+expect_dir = "../../tests/serv/expects"
+expect_name = "serv_regfile.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/serv/serv_regfile.prot --wave tests/serv/serv_regfile.fst --instances serv_regfile:Regfile --display-hex 2>&1"
+
+[[tests]]
+name = "bi.tests_tinyaes128_aes128.aes128_bi"
+paths = [
+  "../../tests/tinyaes128/aes128.prot",
+]
+expect_dir = "../../tests/tinyaes128/expects"
+expect_name = "aes128.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/tinyaes128/aes128.prot --wave tests/tinyaes128/aes128.fst --instances aes_128:TinyAES128 --display-hex 2>&1"
+
+[[tests]]
+name = "bi.tests_wal_advanced_axis.axis_bi"
+paths = [
+  "../../tests/wal/advanced/axis.prot",
+]
+expect_dir = "../../tests/wal/advanced/expects"
+expect_name = "axis.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/wal/advanced/axis.prot --wave tests/wal/advanced/uart-axi.fst --instances uut_rx:AXIS --sample-posedge uut_rx.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_wal_advanced_axis_failing.axis_failing_bi"
+paths = [
+  "../../tests/wal/advanced/axis_failing.prot",
+]
+expect_dir = "../../tests/wal/advanced/expects"
+expect_name = "axis_failing.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/wal/advanced/axis_failing.prot --wave tests/wal/advanced/uart-axi-minimal.fst --instances uut_rx:AXIS --sample-posedge uut_rx.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_wal_advanced_axis_minimal.axis_minimal_bi"
+paths = [
+  "../../tests/wal/advanced/axis_minimal.prot",
+]
+expect_dir = "../../tests/wal/advanced/expects"
+expect_name = "axis_minimal.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/wal/advanced/axis_minimal.prot --wave tests/wal/advanced/uart-axi-minimal.fst --instances uut_rx:AXIS --sample-posedge uut_rx.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_wal_advanced_axis_truncated.axis_truncated_bi"
+paths = [
+  "../../tests/wal/advanced/axis_truncated.prot",
+]
+expect_dir = "../../tests/wal/advanced/expects"
+expect_name = "axis_truncated.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/wal/advanced/axis_truncated.prot --wave tests/wal/advanced/uart-axi-truncated.fst --instances uut_rx:AXIS --sample-posedge uut_rx.clk --show-waveform-time --time-unit ns 2>&1"
+
+[[tests]]
+name = "bi.tests_wal_advanced_axis_truncated_include_idle.axis_truncated_include_idle_bi"
+paths = [
+  "../../tests/wal/advanced/axis_truncated_include_idle.prot",
+]
+expect_dir = "../../tests/wal/advanced/expects"
+expect_name = "axis_truncated_include_idle.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/wal/advanced/axis_truncated_include_idle.prot --wave tests/wal/advanced/uart-axi-truncated.fst --instances uut_rx:AXIS --sample-posedge uut_rx.clk --show-waveform-time --time-unit ns --include-idle 2>&1"
+
+[[tests]]
+name = "bi.tests_wb_intercon_wb_arb.wb_arb_bi"
+paths = [
+  "../../tests/wb_intercon/wb_arb.prot",
+]
+expect_dir = "../../tests/wb_intercon/expects"
+expect_name = "wb_arb.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/wb_intercon/wb_arb.prot --instances wb_intercon_tb.wb_arb_tb:WBSubordinate --sample-posedge wb_intercon_tb.wb_arb_tb.wb_clk --show-waveform-time --time-unit s 2>&1"
+
+[[tests]]
+name = "bi.tests_wb_intercon_wb_cdc.wb_cdc_bi"
+paths = [
+  "../../tests/wb_intercon/wb_cdc.prot",
+]
+expect_dir = "../../tests/wb_intercon/expects"
+expect_name = "wb_cdc.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/wb_intercon/wb_cdc.prot --wave tests/wb_intercon/wb_cdc.fst --instances wb_intercon_tb.wb_cdc_tb.dut:WBSubordinate --sample-posedge wb_intercon_tb.wb_cdc_tb.dut.wbm_clk --show-waveform-time --time-unit s 2>&1"
+
+[[tests]]
+name = "bi.tests_wishbone_wishbone_monitor.wishbone_bi"
+paths = [
+  "../../tests/wishbone/wishbone.monitor.prot",
+]
+expect_dir = "../../tests/wishbone/expects"
+expect_name = "wishbone.bi.expect"
+cmd = "cd ../.. && target/debug/bi --color never --protocol tests/wishbone/wishbone.monitor.prot --wave tests/wishbone/reqwalker.vcd --instances TOP.reqwalker:WBSubordinate --sample-posedge TOP.reqwalker.i_clk 2>&1"
diff --git a/scripts/generate_runt_configs.py b/scripts/generate_runt_configs.py
index 480f9438..d7c7df91 100644
--- a/scripts/generate_runt_configs.py
+++ b/scripts/generate_runt_configs.py
@@ -91,7 +91,7 @@ def expect_name(case: dict, runner: str) -> str:
 
 def expect_dir(case: dict, runner: str) -> str:
     wave = case.get("wave")
-    base = Path(wave if runner == "monitor" and wave else case["path"]).parent
+    base = Path(wave if runner in ("monitor", "bi") and wave else case["path"]).parent
     return f"../../{base.as_posix()}/expects"
 
 
@@ -195,6 +195,23 @@ def monitor_runt_command(case: dict) -> list[tuple[str, str]]:
     return [("", repo_root_command(cmd))]
 
 
+# Same as `monitor_runt_command` above but for the BI test cases
+def bi_runt_command(case: dict) -> list[tuple[str, str]]:
+    # We pass in `--color never` to BI to suppress color in error messages
+    # (so that the .expect files only display plaintext)
+    cmd = [*binary_prefix("bi"), "--color", "never", "--protocol", case["path"]]
+    if case["wave"]:
+        cmd += ["--wave", case["wave"]]
+    if case["instances"]:
+        cmd += ["--instances", *case["instances"]]
+    cmd += case["extra_args"]
+    if case["timeout_secs"] is not None:
+        cmd = timeout_cmd(case["timeout_secs"], cmd)
+    # We redirect stderr to stdout so that the expected output files
+    # contain error messages if BI fails
+    return [("", repo_root_command(cmd, stderr="stdout"))]
+
+
 def waveform_runt_command(case: dict) -> list[tuple[str, str]]:
     ast_cmd = [
         *binary_prefix("protocols-interp"),
@@ -261,6 +278,7 @@ def fail_runt_command(case: dict) -> list[tuple[str, str]]:
     "interp": interp_runt_command,
     "graph_interp": graph_interp_runt_command,
     "monitor": monitor_runt_command,
+    "bi": bi_runt_command,
     "waveform": waveform_runt_command,
     "fail": fail_runt_command,
 }
@@ -388,6 +406,9 @@ def generate_runt_configs() -> None:
     suite_specs = {
         "interp": ("interp", tx),
         "monitor": ("monitor", mon),
+        # Note: bi uses the same cases as the monitor (i.e. MONITOR_CASES)
+        # as the monitor/bi share largely the same CLI args
+        "bi": ("bi", mon),
         "graph_interp": ("graph_interp", graph_interp_cases(tx)),
         "waveform": ("waveform", waveform_cases(tx)),
         "fail": ("fail", fail_cases(tx)),
diff --git a/tests/adders/expects/add_d1.bi.expect b/tests/adders/expects/add_d1.bi.expect
new file mode 100644
index 00000000..ff76d998
--- /dev/null
+++ b/tests/adders/expects/add_d1.bi.expect
@@ -0,0 +1,5 @@
+// trace 0
+trace {
+    add(1, 2, 3);
+    add(4, 5, 9);
+}
diff --git a/tests/adders/expects/add_d2.bi.expect b/tests/adders/expects/add_d2.bi.expect
new file mode 100644
index 00000000..ff76d998
--- /dev/null
+++ b/tests/adders/expects/add_d2.bi.expect
@@ -0,0 +1,5 @@
+// trace 0
+trace {
+    add(1, 2, 3);
+    add(4, 5, 9);
+}
diff --git a/tests/adders/expects/add_var_cyc.bi.expect b/tests/adders/expects/add_var_cyc.bi.expect
new file mode 100644
index 00000000..3d640dc7
--- /dev/null
+++ b/tests/adders/expects/add_var_cyc.bi.expect
@@ -0,0 +1,27 @@
+// trace 0
+trace {
+    loop_add(1, 2, 3, 1);
+    loop_add(1, 2, 3, 0);
+    loop_add(10, 20, 30, 0);
+}
+
+// trace 1
+trace {
+    loop_add(1, 2, 3, 2);
+    loop_add(10, 20, 30, 0);
+}
+
+// trace 2
+trace {
+    loop_add(1, 2, 3, 0);
+    loop_add(1, 2, 3, 0);
+    loop_add(1, 2, 3, 0);
+    loop_add(10, 20, 30, 0);
+}
+
+// trace 3
+trace {
+    loop_add(1, 2, 3, 0);
+    loop_add(1, 2, 3, 1);
+    loop_add(10, 20, 30, 0);
+}
diff --git a/tests/adders/expects/busy_wait.bi.expect b/tests/adders/expects/busy_wait.bi.expect
new file mode 100644
index 00000000..89398f87
--- /dev/null
+++ b/tests/adders/expects/busy_wait.bi.expect
@@ -0,0 +1,4 @@
+panicked at bi/src/bi.rs:628:21:
+[add_busy_wait@00!] Cannot fork at step zero!
+---CODE---
+101
diff --git a/tests/adders/expects/loop_with_assigns.bi.expect b/tests/adders/expects/loop_with_assigns.bi.expect
new file mode 100644
index 00000000..bb042478
--- /dev/null
+++ b/tests/adders/expects/loop_with_assigns.bi.expect
@@ -0,0 +1,4 @@
+panicked at bi/src/bi.rs:628:21:
+[loop_add@00!] Cannot fork at step zero!
+---CODE---
+101
diff --git a/tests/adders/expects/nested_busy_wait.bi.expect b/tests/adders/expects/nested_busy_wait.bi.expect
new file mode 100644
index 00000000..cd84b0ad
--- /dev/null
+++ b/tests/adders/expects/nested_busy_wait.bi.expect
@@ -0,0 +1,4 @@
+panicked at bi/src/bi.rs:628:21:
+[nested_busy_wait@00!] Cannot fork at step zero!
+---CODE---
+101
diff --git a/tests/alus/expects/alu_d1.bi.expect b/tests/alus/expects/alu_d1.bi.expect
new file mode 100644
index 00000000..16fa0842
--- /dev/null
+++ b/tests/alus/expects/alu_d1.bi.expect
@@ -0,0 +1,8 @@
+// trace 0
+trace {
+    add(1, 2, 3);
+    add(123, 245, 368);
+    sub(200, 200, 0);
+    and(100, 100, 100);
+    or(0, 230, 230);
+}
diff --git a/tests/alus/expects/alu_d2.bi.expect b/tests/alus/expects/alu_d2.bi.expect
new file mode 100644
index 00000000..16fa0842
--- /dev/null
+++ b/tests/alus/expects/alu_d2.bi.expect
@@ -0,0 +1,8 @@
+// trace 0
+trace {
+    add(1, 2, 3);
+    add(123, 245, 368);
+    sub(200, 200, 0);
+    and(100, 100, 100);
+    or(0, 230, 230);
+}
diff --git a/tests/antmicro/fifo_classic/expects/test_fifo_classic_1.bi.expect b/tests/antmicro/fifo_classic/expects/test_fifo_classic_1.bi.expect
new file mode 100644
index 00000000..ff0306dd
--- /dev/null
+++ b/tests/antmicro/fifo_classic/expects/test_fifo_classic_1.bi.expect
@@ -0,0 +1,11 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 872415232, 3511065769, 0);  // [time: 110ns -> 130ns]
+    reset();  // [time: 170.001ns -> 180.001ns]
+    reset();  // [time: 180.001ns -> 190.001ns]
+    reset();  // [time: 190.001ns -> 200.001ns]
+    write(15, 872415232, 2839611496, 0);  // [time: 240.001ns -> 260.001ns]
+}
diff --git a/tests/antmicro/fifo_classic/expects/test_fifo_classic_2.bi.expect b/tests/antmicro/fifo_classic/expects/test_fifo_classic_2.bi.expect
new file mode 100644
index 00000000..2fcf485a
--- /dev/null
+++ b/tests/antmicro/fifo_classic/expects/test_fifo_classic_2.bi.expect
@@ -0,0 +1,13 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 872415232, 3511065769, 0);  // [time: 130ns -> 150ns]
+    read(15, 872415232, 2839611496, 0);  // [time: 150ns -> 170ns]
+    reset();  // [time: 210.001ns -> 220.001ns]
+    reset();  // [time: 220.001ns -> 230.001ns]
+    reset();  // [time: 230.001ns -> 240.001ns]
+    write(15, 872415232, 4255599317, 0);  // [time: 280.001ns -> 300.001ns]
+    write(15, 872415232, 2978480611, 0);  // [time: 300.001ns -> 320.001ns]
+}
diff --git a/tests/antmicro/fifo_classic/expects/test_fifo_classic_3.bi.expect b/tests/antmicro/fifo_classic/expects/test_fifo_classic_3.bi.expect
new file mode 100644
index 00000000..f90eb06e
--- /dev/null
+++ b/tests/antmicro/fifo_classic/expects/test_fifo_classic_3.bi.expect
@@ -0,0 +1,15 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 872415232, 3511065769, 0);  // [time: 150ns -> 170ns]
+    read(15, 872415232, 2839611496, 0);  // [time: 170ns -> 190ns]
+    read(15, 872415232, 4255599317, 0);  // [time: 190ns -> 210ns]
+    reset();  // [time: 250.001ns -> 260.001ns]
+    reset();  // [time: 260.001ns -> 270.001ns]
+    reset();  // [time: 270.001ns -> 280.001ns]
+    write(15, 872415232, 2978480611, 0);  // [time: 320.001ns -> 340.001ns]
+    write(15, 872415232, 2227458782, 0);  // [time: 340.001ns -> 360.001ns]
+    write(15, 872415232, 2594436392, 0);  // [time: 360.001ns -> 380.001ns]
+}
diff --git a/tests/antmicro/fifo_classic/expects/test_fifo_classic_4.bi.expect b/tests/antmicro/fifo_classic/expects/test_fifo_classic_4.bi.expect
new file mode 100644
index 00000000..9dd58394
--- /dev/null
+++ b/tests/antmicro/fifo_classic/expects/test_fifo_classic_4.bi.expect
@@ -0,0 +1,17 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 872415232, 3511065769, 0);  // [time: 170ns -> 190ns]
+    read(15, 872415232, 2839611496, 0);  // [time: 190ns -> 210ns]
+    read(15, 872415232, 4255599317, 0);  // [time: 210ns -> 230ns]
+    read(15, 872415232, 2978480611, 0);  // [time: 230ns -> 250ns]
+    reset();  // [time: 290.001ns -> 300.001ns]
+    reset();  // [time: 300.001ns -> 310.001ns]
+    reset();  // [time: 310.001ns -> 320.001ns]
+    write(15, 872415232, 2227458782, 0);  // [time: 360.001ns -> 380.001ns]
+    write(15, 872415232, 2594436392, 0);  // [time: 380.001ns -> 400.001ns]
+    write(15, 872415232, 2879904594, 0);  // [time: 400.001ns -> 420.001ns]
+    write(15, 872415232, 2502756630, 0);  // [time: 420.001ns -> 440.001ns]
+}
diff --git a/tests/antmicro/fifo_classic/expects/test_fifo_classic_5.bi.expect b/tests/antmicro/fifo_classic/expects/test_fifo_classic_5.bi.expect
new file mode 100644
index 00000000..906c59ca
--- /dev/null
+++ b/tests/antmicro/fifo_classic/expects/test_fifo_classic_5.bi.expect
@@ -0,0 +1,19 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 872415232, 3511065769, 0);  // [time: 190ns -> 210ns]
+    read(15, 872415232, 2839611496, 0);  // [time: 210ns -> 230ns]
+    read(15, 872415232, 4255599317, 0);  // [time: 230ns -> 250ns]
+    read(15, 872415232, 2978480611, 0);  // [time: 250ns -> 270ns]
+    read(15, 872415232, 2227458782, 0);  // [time: 270ns -> 290ns]
+    reset();  // [time: 330.001ns -> 340.001ns]
+    reset();  // [time: 340.001ns -> 350.001ns]
+    reset();  // [time: 350.001ns -> 360.001ns]
+    write(15, 872415232, 2594436392, 0);  // [time: 400.001ns -> 420.001ns]
+    write(15, 872415232, 2879904594, 0);  // [time: 420.001ns -> 440.001ns]
+    write(15, 872415232, 2502756630, 0);  // [time: 440.001ns -> 460.001ns]
+    write(15, 872415232, 3888695605, 0);  // [time: 460.001ns -> 480.001ns]
+    write(15, 872415232, 4181798306, 0);  // [time: 480.001ns -> 500.001ns]
+}
diff --git a/tests/antmicro/fifo_classic/expects/test_fifo_classic_6.bi.expect b/tests/antmicro/fifo_classic/expects/test_fifo_classic_6.bi.expect
new file mode 100644
index 00000000..fd22df44
--- /dev/null
+++ b/tests/antmicro/fifo_classic/expects/test_fifo_classic_6.bi.expect
@@ -0,0 +1,21 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 872415232, 2215956531, 0);  // [time: 210ns -> 230ns]
+    read(15, 872415232, 2174594346, 0);  // [time: 230ns -> 250ns]
+    read(15, 872415232, 3706263408, 0);  // [time: 250ns -> 270ns]
+    read(15, 872415232, 3375769081, 0);  // [time: 270ns -> 290ns]
+    read(15, 872415232, 3915557832, 0);  // [time: 290ns -> 310ns]
+    read(15, 872415232, 2529678886, 0);  // [time: 310ns -> 330ns]
+    reset();  // [time: 370.001ns -> 380.001ns]
+    reset();  // [time: 380.001ns -> 390.001ns]
+    reset();  // [time: 390.001ns -> 400.001ns]
+    write(15, 872415232, 2550371957, 0);  // [time: 440.001ns -> 460.001ns]
+    write(15, 872415232, 2973140726, 0);  // [time: 460.001ns -> 480.001ns]
+    write(15, 872415232, 3658948496, 0);  // [time: 480.001ns -> 500.001ns]
+    write(15, 872415232, 4239119767, 0);  // [time: 500.001ns -> 520.001ns]
+    write(15, 872415232, 2305440508, 0);  // [time: 520.001ns -> 540.001ns]
+    write(15, 872415232, 2674771663, 0);  // [time: 540.001ns -> 560.001ns]
+}
diff --git a/tests/antmicro/fifo_classic/expects/test_fifo_classic_7.bi.expect b/tests/antmicro/fifo_classic/expects/test_fifo_classic_7.bi.expect
new file mode 100644
index 00000000..21ba8129
--- /dev/null
+++ b/tests/antmicro/fifo_classic/expects/test_fifo_classic_7.bi.expect
@@ -0,0 +1,23 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 872415232, 2215956531, 0);  // [time: 230ns -> 250ns]
+    read(15, 872415232, 2174594346, 0);  // [time: 250ns -> 270ns]
+    read(15, 872415232, 3706263408, 0);  // [time: 270ns -> 290ns]
+    read(15, 872415232, 3375769081, 0);  // [time: 290ns -> 310ns]
+    read(15, 872415232, 3915557832, 0);  // [time: 310ns -> 330ns]
+    read(15, 872415232, 2529678886, 0);  // [time: 330ns -> 350ns]
+    read(15, 872415232, 2550371957, 0);  // [time: 350ns -> 370ns]
+    reset();  // [time: 410.001ns -> 420.001ns]
+    reset();  // [time: 420.001ns -> 430.001ns]
+    reset();  // [time: 430.001ns -> 440.001ns]
+    write(15, 872415232, 2973140726, 0);  // [time: 480.001ns -> 500.001ns]
+    write(15, 872415232, 3658948496, 0);  // [time: 500.001ns -> 520.001ns]
+    write(15, 872415232, 4239119767, 0);  // [time: 520.001ns -> 540.001ns]
+    write(15, 872415232, 2305440508, 0);  // [time: 540.001ns -> 560.001ns]
+    write(15, 872415232, 2674771663, 0);  // [time: 560.001ns -> 580.001ns]
+    write(15, 872415232, 4005297405, 0);  // [time: 580.001ns -> 600.001ns]
+    write(15, 872415232, 2923162757, 0);  // [time: 600.001ns -> 620.001ns]
+}
diff --git a/tests/antmicro/fifo_classic/expects/test_fifo_classic_8.bi.expect b/tests/antmicro/fifo_classic/expects/test_fifo_classic_8.bi.expect
new file mode 100644
index 00000000..64b96213
--- /dev/null
+++ b/tests/antmicro/fifo_classic/expects/test_fifo_classic_8.bi.expect
@@ -0,0 +1,25 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 872415232, 2215956531, 0);  // [time: 250ns -> 270ns]
+    read(15, 872415232, 2174594346, 0);  // [time: 270ns -> 290ns]
+    read(15, 872415232, 3706263408, 0);  // [time: 290ns -> 310ns]
+    read(15, 872415232, 3375769081, 0);  // [time: 310ns -> 330ns]
+    read(15, 872415232, 3915557832, 0);  // [time: 330ns -> 350ns]
+    read(15, 872415232, 2529678886, 0);  // [time: 350ns -> 370ns]
+    read(15, 872415232, 2550371957, 0);  // [time: 370ns -> 390ns]
+    read(15, 872415232, 2973140726, 0);  // [time: 390ns -> 410ns]
+    reset();  // [time: 450.001ns -> 460.001ns]
+    reset();  // [time: 460.001ns -> 470.001ns]
+    reset();  // [time: 470.001ns -> 480.001ns]
+    write(15, 872415232, 3658948496, 0);  // [time: 520.001ns -> 540.001ns]
+    write(15, 872415232, 4239119767, 0);  // [time: 540.001ns -> 560.001ns]
+    write(15, 872415232, 2305440508, 0);  // [time: 560.001ns -> 580.001ns]
+    write(15, 872415232, 2674771663, 0);  // [time: 580.001ns -> 600.001ns]
+    write(15, 872415232, 4005297405, 0);  // [time: 600.001ns -> 620.001ns]
+    write(15, 872415232, 2923162757, 0);  // [time: 620.001ns -> 640.001ns]
+    write(15, 872415232, 2212602639, 0);  // [time: 640.001ns -> 660.001ns]
+    write(15, 872415232, 3940387843, 0);  // [time: 660.001ns -> 680.001ns]
+}
diff --git a/tests/antmicro/fifo_constant/expects/test_fifo_constant_1.bi.expect b/tests/antmicro/fifo_constant/expects/test_fifo_constant_1.bi.expect
new file mode 100644
index 00000000..e26f1c51
--- /dev/null
+++ b/tests/antmicro/fifo_constant/expects/test_fifo_constant_1.bi.expect
@@ -0,0 +1,16 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 872415232, 136945767, 0);  // [time: 110ns -> 130ns]
+    reset();  // [time: 170.001ns -> 180.001ns]
+    reset();  // [time: 180.001ns -> 190.001ns]
+    reset();  // [time: 190.001ns -> 200.001ns]
+    write(15, 872415232, 54221397, 0);  // [time: 240.001ns -> 260.001ns]
+    reset();  // [time: 320.002ns -> 330.002ns]
+    reset();  // [time: 330.002ns -> 340.002ns]
+    reset();  // [time: 340.002ns -> 350.002ns]
+    write(15, 872415232, 3117559521, 0);  // [time: 410.002ns -> 430.002ns]
+    read(15, 872415232, 6, 0);  // [time: 430.002ns -> 450.002ns]
+}
diff --git a/tests/antmicro/fifo_constant/expects/test_fifo_constant_2.bi.expect b/tests/antmicro/fifo_constant/expects/test_fifo_constant_2.bi.expect
new file mode 100644
index 00000000..10aa066c
--- /dev/null
+++ b/tests/antmicro/fifo_constant/expects/test_fifo_constant_2.bi.expect
@@ -0,0 +1,19 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 872415232, 136945767, 0);  // [time: 130ns -> 150ns]
+    read(15, 872415232, 54221397, 0);  // [time: 150ns -> 160ns]
+    reset();  // [time: 200.001ns -> 210.001ns]
+    reset();  // [time: 210.001ns -> 220.001ns]
+    reset();  // [time: 220.001ns -> 230.001ns]
+    write(15, 872415232, 3117559521, 0);  // [time: 270.001ns -> 290.001ns]
+    write(15, 872415232, 2456570867, 0);  // [time: 290.001ns -> 300.001ns]
+    reset();  // [time: 380.002ns -> 390.002ns]
+    reset();  // [time: 390.002ns -> 400.002ns]
+    reset();  // [time: 400.002ns -> 410.002ns]
+    write(15, 872415232, 3536148369, 0);  // [time: 470.002ns -> 490.002ns]
+    write(15, 872415232, 764390477, 0);  // [time: 490.002ns -> 500.002ns]
+    read(15, 872415232, 6, 0);  // [time: 500.002ns -> 520.002ns]
+}
diff --git a/tests/antmicro/fifo_constant/expects/test_fifo_constant_3.bi.expect b/tests/antmicro/fifo_constant/expects/test_fifo_constant_3.bi.expect
new file mode 100644
index 00000000..905246ba
--- /dev/null
+++ b/tests/antmicro/fifo_constant/expects/test_fifo_constant_3.bi.expect
@@ -0,0 +1,22 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 872415232, 136945767, 0);  // [time: 150ns -> 170ns]
+    read(15, 872415232, 54221397, 0);  // [time: 170ns -> 180ns]
+    read(15, 872415232, 3117559521, 0);  // [time: 180ns -> 190ns]
+    reset();  // [time: 230.001ns -> 240.001ns]
+    reset();  // [time: 240.001ns -> 250.001ns]
+    reset();  // [time: 250.001ns -> 260.001ns]
+    write(15, 872415232, 2456570867, 0);  // [time: 300.001ns -> 320.001ns]
+    write(15, 872415232, 3536148369, 0);  // [time: 320.001ns -> 330.001ns]
+    write(15, 872415232, 764390477, 0);  // [time: 330.001ns -> 340.001ns]
+    reset();  // [time: 440.002ns -> 450.002ns]
+    reset();  // [time: 450.002ns -> 460.002ns]
+    reset();  // [time: 460.002ns -> 470.002ns]
+    write(15, 872415232, 805776619, 0);  // [time: 530.002ns -> 550.002ns]
+    write(15, 872415232, 1651314158, 0);  // [time: 550.002ns -> 560.002ns]
+    write(15, 872415232, 3022929697, 0);  // [time: 560.002ns -> 570.002ns]
+    read(15, 872415232, 6, 0);  // [time: 570.002ns -> 590.002ns]
+}
diff --git a/tests/antmicro/fifo_constant/expects/test_fifo_constant_4.bi.expect b/tests/antmicro/fifo_constant/expects/test_fifo_constant_4.bi.expect
new file mode 100644
index 00000000..8bd13fef
--- /dev/null
+++ b/tests/antmicro/fifo_constant/expects/test_fifo_constant_4.bi.expect
@@ -0,0 +1,25 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 872415232, 136945767, 0);  // [time: 170ns -> 190ns]
+    read(15, 872415232, 54221397, 0);  // [time: 190ns -> 200ns]
+    read(15, 872415232, 3117559521, 0);  // [time: 200ns -> 210ns]
+    read(15, 872415232, 2456570867, 0);  // [time: 210ns -> 220ns]
+    reset();  // [time: 260.001ns -> 270.001ns]
+    reset();  // [time: 270.001ns -> 280.001ns]
+    reset();  // [time: 280.001ns -> 290.001ns]
+    write(15, 872415232, 3536148369, 0);  // [time: 330.001ns -> 350.001ns]
+    write(15, 872415232, 764390477, 0);  // [time: 350.001ns -> 360.001ns]
+    write(15, 872415232, 805776619, 0);  // [time: 360.001ns -> 370.001ns]
+    write(15, 872415232, 1651314158, 0);  // [time: 370.001ns -> 380.001ns]
+    reset();  // [time: 500.002ns -> 510.002ns]
+    reset();  // [time: 510.002ns -> 520.002ns]
+    reset();  // [time: 520.002ns -> 530.002ns]
+    write(15, 872415232, 3022929697, 0);  // [time: 590.002ns -> 610.002ns]
+    write(15, 872415232, 4183272239, 0);  // [time: 610.002ns -> 620.002ns]
+    write(15, 872415232, 315913722, 0);  // [time: 620.002ns -> 630.002ns]
+    write(15, 872415232, 1054576031, 0);  // [time: 630.002ns -> 640.002ns]
+    read(15, 872415232, 6, 0);  // [time: 640.002ns -> 660.002ns]
+}
diff --git a/tests/antmicro/fifo_constant/expects/test_fifo_constant_5.bi.expect b/tests/antmicro/fifo_constant/expects/test_fifo_constant_5.bi.expect
new file mode 100644
index 00000000..dcf480c0
--- /dev/null
+++ b/tests/antmicro/fifo_constant/expects/test_fifo_constant_5.bi.expect
@@ -0,0 +1,28 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 872415232, 1363247548, 0);  // [time: 190ns -> 210ns]
+    read(15, 872415232, 2498712983, 0);  // [time: 210ns -> 220ns]
+    read(15, 872415232, 2031470411, 0);  // [time: 220ns -> 230ns]
+    read(15, 872415232, 247232753, 0);  // [time: 230ns -> 240ns]
+    read(15, 872415232, 236574178, 0);  // [time: 240ns -> 250ns]
+    reset();  // [time: 290.001ns -> 300.001ns]
+    reset();  // [time: 300.001ns -> 310.001ns]
+    reset();  // [time: 310.001ns -> 320.001ns]
+    write(15, 872415232, 421022298, 0);  // [time: 360.001ns -> 380.001ns]
+    write(15, 872415232, 2203084718, 0);  // [time: 380.001ns -> 390.001ns]
+    write(15, 872415232, 2308882986, 0);  // [time: 390.001ns -> 400.001ns]
+    write(15, 872415232, 4235095479, 0);  // [time: 400.001ns -> 410.001ns]
+    write(15, 872415232, 1180440750, 0);  // [time: 410.001ns -> 420.001ns]
+    reset();  // [time: 560.002ns -> 570.002ns]
+    reset();  // [time: 570.002ns -> 580.002ns]
+    reset();  // [time: 580.002ns -> 590.002ns]
+    write(15, 872415232, 2313964829, 0);  // [time: 650.002ns -> 670.002ns]
+    write(15, 872415232, 2950684687, 0);  // [time: 670.002ns -> 680.002ns]
+    write(15, 872415232, 1632464407, 0);  // [time: 680.002ns -> 690.002ns]
+    write(15, 872415232, 531222031, 0);  // [time: 690.002ns -> 700.002ns]
+    write(15, 872415232, 2086209707, 0);  // [time: 700.002ns -> 710.002ns]
+    read(15, 872415232, 6, 0);  // [time: 710.002ns -> 730.002ns]
+}
diff --git a/tests/antmicro/fifo_constant/expects/test_fifo_constant_6.bi.expect b/tests/antmicro/fifo_constant/expects/test_fifo_constant_6.bi.expect
new file mode 100644
index 00000000..d6aea314
--- /dev/null
+++ b/tests/antmicro/fifo_constant/expects/test_fifo_constant_6.bi.expect
@@ -0,0 +1,31 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 872415232, 1363247548, 0);  // [time: 210ns -> 230ns]
+    read(15, 872415232, 2498712983, 0);  // [time: 230ns -> 240ns]
+    read(15, 872415232, 2031470411, 0);  // [time: 240ns -> 250ns]
+    read(15, 872415232, 247232753, 0);  // [time: 250ns -> 260ns]
+    read(15, 872415232, 236574178, 0);  // [time: 260ns -> 270ns]
+    read(15, 872415232, 421022298, 0);  // [time: 270ns -> 280ns]
+    reset();  // [time: 320.001ns -> 330.001ns]
+    reset();  // [time: 330.001ns -> 340.001ns]
+    reset();  // [time: 340.001ns -> 350.001ns]
+    write(15, 872415232, 2203084718, 0);  // [time: 390.001ns -> 410.001ns]
+    write(15, 872415232, 2308882986, 0);  // [time: 410.001ns -> 420.001ns]
+    write(15, 872415232, 4235095479, 0);  // [time: 420.001ns -> 430.001ns]
+    write(15, 872415232, 1180440750, 0);  // [time: 430.001ns -> 440.001ns]
+    write(15, 872415232, 2313964829, 0);  // [time: 440.001ns -> 450.001ns]
+    write(15, 872415232, 2950684687, 0);  // [time: 450.001ns -> 460.001ns]
+    reset();  // [time: 620.002ns -> 630.002ns]
+    reset();  // [time: 630.002ns -> 640.002ns]
+    reset();  // [time: 640.002ns -> 650.002ns]
+    write(15, 872415232, 1632464407, 0);  // [time: 710.002ns -> 730.002ns]
+    write(15, 872415232, 531222031, 0);  // [time: 730.002ns -> 740.002ns]
+    write(15, 872415232, 2086209707, 0);  // [time: 740.002ns -> 750.002ns]
+    write(15, 872415232, 3905452749, 0);  // [time: 750.002ns -> 760.002ns]
+    write(15, 872415232, 1047759017, 0);  // [time: 760.002ns -> 770.002ns]
+    write(15, 872415232, 1028960831, 0);  // [time: 770.002ns -> 780.002ns]
+    read(15, 872415232, 6, 0);  // [time: 780.002ns -> 800.002ns]
+}
diff --git a/tests/antmicro/fifo_constant/expects/test_fifo_constant_7.bi.expect b/tests/antmicro/fifo_constant/expects/test_fifo_constant_7.bi.expect
new file mode 100644
index 00000000..247b5a2f
--- /dev/null
+++ b/tests/antmicro/fifo_constant/expects/test_fifo_constant_7.bi.expect
@@ -0,0 +1,34 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 872415232, 1363247548, 0);  // [time: 230ns -> 250ns]
+    read(15, 872415232, 2498712983, 0);  // [time: 250ns -> 260ns]
+    read(15, 872415232, 2031470411, 0);  // [time: 260ns -> 270ns]
+    read(15, 872415232, 247232753, 0);  // [time: 270ns -> 280ns]
+    read(15, 872415232, 236574178, 0);  // [time: 280ns -> 290ns]
+    read(15, 872415232, 421022298, 0);  // [time: 290ns -> 300ns]
+    read(15, 872415232, 2203084718, 0);  // [time: 300ns -> 310ns]
+    reset();  // [time: 350.001ns -> 360.001ns]
+    reset();  // [time: 360.001ns -> 370.001ns]
+    reset();  // [time: 370.001ns -> 380.001ns]
+    write(15, 872415232, 2308882986, 0);  // [time: 420.001ns -> 440.001ns]
+    write(15, 872415232, 4235095479, 0);  // [time: 440.001ns -> 450.001ns]
+    write(15, 872415232, 1180440750, 0);  // [time: 450.001ns -> 460.001ns]
+    write(15, 872415232, 2313964829, 0);  // [time: 460.001ns -> 470.001ns]
+    write(15, 872415232, 2950684687, 0);  // [time: 470.001ns -> 480.001ns]
+    write(15, 872415232, 1632464407, 0);  // [time: 480.001ns -> 490.001ns]
+    write(15, 872415232, 531222031, 0);  // [time: 490.001ns -> 500.001ns]
+    reset();  // [time: 680.002ns -> 690.002ns]
+    reset();  // [time: 690.002ns -> 700.002ns]
+    reset();  // [time: 700.002ns -> 710.002ns]
+    write(15, 872415232, 2086209707, 0);  // [time: 770.002ns -> 790.002ns]
+    write(15, 872415232, 3905452749, 0);  // [time: 790.002ns -> 800.002ns]
+    write(15, 872415232, 1047759017, 0);  // [time: 800.002ns -> 810.002ns]
+    write(15, 872415232, 1028960831, 0);  // [time: 810.002ns -> 820.002ns]
+    write(15, 872415232, 3233599833, 0);  // [time: 820.002ns -> 830.002ns]
+    write(15, 872415232, 1516004143, 0);  // [time: 830.002ns -> 840.002ns]
+    write(15, 872415232, 619658659, 0);  // [time: 840.002ns -> 850.002ns]
+    read(15, 872415232, 6, 0);  // [time: 850.002ns -> 870.002ns]
+}
diff --git a/tests/antmicro/fifo_constant/expects/test_fifo_constant_8.bi.expect b/tests/antmicro/fifo_constant/expects/test_fifo_constant_8.bi.expect
new file mode 100644
index 00000000..951423ae
--- /dev/null
+++ b/tests/antmicro/fifo_constant/expects/test_fifo_constant_8.bi.expect
@@ -0,0 +1,37 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 872415232, 1363247548, 0);  // [time: 250ns -> 270ns]
+    read(15, 872415232, 2498712983, 0);  // [time: 270ns -> 280ns]
+    read(15, 872415232, 2031470411, 0);  // [time: 280ns -> 290ns]
+    read(15, 872415232, 247232753, 0);  // [time: 290ns -> 300ns]
+    read(15, 872415232, 236574178, 0);  // [time: 300ns -> 310ns]
+    read(15, 872415232, 421022298, 0);  // [time: 310ns -> 320ns]
+    read(15, 872415232, 2203084718, 0);  // [time: 320ns -> 330ns]
+    read(15, 872415232, 2308882986, 0);  // [time: 330ns -> 340ns]
+    reset();  // [time: 380.001ns -> 390.001ns]
+    reset();  // [time: 390.001ns -> 400.001ns]
+    reset();  // [time: 400.001ns -> 410.001ns]
+    write(15, 872415232, 4235095479, 0);  // [time: 450.001ns -> 470.001ns]
+    write(15, 872415232, 1180440750, 0);  // [time: 470.001ns -> 480.001ns]
+    write(15, 872415232, 2313964829, 0);  // [time: 480.001ns -> 490.001ns]
+    write(15, 872415232, 2950684687, 0);  // [time: 490.001ns -> 500.001ns]
+    write(15, 872415232, 1632464407, 0);  // [time: 500.001ns -> 510.001ns]
+    write(15, 872415232, 531222031, 0);  // [time: 510.001ns -> 520.001ns]
+    write(15, 872415232, 2086209707, 0);  // [time: 520.001ns -> 530.001ns]
+    write(15, 872415232, 3905452749, 0);  // [time: 530.001ns -> 540.001ns]
+    reset();  // [time: 740.002ns -> 750.002ns]
+    reset();  // [time: 750.002ns -> 760.002ns]
+    reset();  // [time: 760.002ns -> 770.002ns]
+    write(15, 872415232, 1047759017, 0);  // [time: 830.002ns -> 850.002ns]
+    write(15, 872415232, 1028960831, 0);  // [time: 850.002ns -> 860.002ns]
+    write(15, 872415232, 3233599833, 0);  // [time: 860.002ns -> 870.002ns]
+    write(15, 872415232, 1516004143, 0);  // [time: 870.002ns -> 880.002ns]
+    write(15, 872415232, 619658659, 0);  // [time: 880.002ns -> 890.002ns]
+    write(15, 872415232, 1481414104, 0);  // [time: 890.002ns -> 900.002ns]
+    write(15, 872415232, 2537393056, 0);  // [time: 900.002ns -> 910.002ns]
+    write(15, 872415232, 3649566230, 0);  // [time: 910.002ns -> 920.002ns]
+    read(15, 872415232, 6, 0);  // [time: 920.002ns -> 940.002ns]
+}
diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_16_0.bi.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_16_0.bi.expect
new file mode 100644
index 00000000..2f13eb1d
--- /dev/null
+++ b/tests/antmicro/sram_classic/expects/test_sram_classic_16_0.bi.expect
@@ -0,0 +1,41 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108864, 3946442578, 0);  // [time: 410ns -> 430ns]
+    read(15, 67108865, 2796792514, 0);  // [time: 430ns -> 450ns]
+    read(15, 67108866, 3312914512, 0);  // [time: 450ns -> 470ns]
+    read(15, 67108867, 4292142820, 0);  // [time: 470ns -> 490ns]
+    read(15, 67108868, 3525794570, 0);  // [time: 490ns -> 510ns]
+    read(15, 67108869, 2961047623, 0);  // [time: 510ns -> 530ns]
+    read(15, 67108870, 4249856274, 0);  // [time: 530ns -> 550ns]
+    read(15, 67108871, 3405678304, 0);  // [time: 550ns -> 570ns]
+    read(15, 67108872, 2415042617, 0);  // [time: 570ns -> 590ns]
+    read(15, 67108873, 3311552087, 0);  // [time: 590ns -> 610ns]
+    read(15, 67108874, 3211316809, 0);  // [time: 610ns -> 630ns]
+    read(15, 67108875, 3236997651, 0);  // [time: 630ns -> 650ns]
+    read(15, 67108876, 3369414426, 0);  // [time: 650ns -> 670ns]
+    read(15, 67108877, 3866725828, 0);  // [time: 670ns -> 690ns]
+    read(15, 67108878, 2882616058, 0);  // [time: 690ns -> 710ns]
+    read(15, 67108879, 3738458232, 0);  // [time: 710ns -> 730ns]
+    reset();  // [time: 770.001ns -> 780.001ns]
+    reset();  // [time: 780.001ns -> 790.001ns]
+    reset();  // [time: 790.001ns -> 800.001ns]
+    write(15, 67108864, 2558870979, 0);  // [time: 840.001ns -> 860.001ns]
+    write(15, 67108865, 3310254824, 0);  // [time: 860.001ns -> 880.001ns]
+    write(15, 67108866, 3635210891, 0);  // [time: 880.001ns -> 900.001ns]
+    write(15, 67108867, 2844952514, 0);  // [time: 900.001ns -> 920.001ns]
+    write(15, 67108868, 2293386100, 0);  // [time: 920.001ns -> 940.001ns]
+    write(15, 67108869, 3615462605, 0);  // [time: 940.001ns -> 960.001ns]
+    write(15, 67108870, 3569010089, 0);  // [time: 960.001ns -> 980.001ns]
+    write(15, 67108871, 3520072258, 0);  // [time: 980.001ns -> 1000.001ns]
+    write(15, 67108872, 3002516588, 0);  // [time: 1000.001ns -> 1020.001ns]
+    write(15, 67108873, 3681389096, 0);  // [time: 1020.001ns -> 1040.001ns]
+    write(15, 67108874, 2924663556, 0);  // [time: 1040.001ns -> 1060.001ns]
+    write(15, 67108875, 3055297102, 0);  // [time: 1060.001ns -> 1080.001ns]
+    write(15, 67108876, 4177639544, 0);  // [time: 1080.001ns -> 1100.001ns]
+    write(15, 67108877, 3526172361, 0);  // [time: 1100.001ns -> 1120.001ns]
+    write(15, 67108878, 2564412332, 0);  // [time: 1120.001ns -> 1140.001ns]
+    write(15, 67108879, 4210875098, 0);  // [time: 1140.001ns -> 1160.001ns]
+}
diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_16_12.bi.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_16_12.bi.expect
new file mode 100644
index 00000000..318d95b0
--- /dev/null
+++ b/tests/antmicro/sram_classic/expects/test_sram_classic_16_12.bi.expect
@@ -0,0 +1,41 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108867, 3622568730, 0);  // [time: 410ns -> 430ns]
+    read(15, 67108868, 3538707329, 0);  // [time: 430ns -> 450ns]
+    read(15, 67108869, 3440721235, 0);  // [time: 450ns -> 470ns]
+    read(15, 67108870, 3191204602, 0);  // [time: 470ns -> 490ns]
+    read(15, 67108871, 4084986393, 0);  // [time: 490ns -> 510ns]
+    read(15, 67108872, 3446247256, 0);  // [time: 510ns -> 530ns]
+    read(15, 67108873, 3908428032, 0);  // [time: 530ns -> 550ns]
+    read(15, 67108874, 2315046581, 0);  // [time: 550ns -> 570ns]
+    read(15, 67108875, 2780682871, 0);  // [time: 570ns -> 590ns]
+    read(15, 67108876, 3026674647, 0);  // [time: 590ns -> 610ns]
+    read(15, 67108877, 2376933607, 0);  // [time: 610ns -> 630ns]
+    read(15, 67108878, 2436105964, 0);  // [time: 630ns -> 650ns]
+    read(15, 67108879, 3222378968, 0);  // [time: 650ns -> 670ns]
+    read(15, 67108880, 3310323703, 0);  // [time: 670ns -> 690ns]
+    read(15, 67108881, 2550879638, 0);  // [time: 690ns -> 710ns]
+    read(15, 67108882, 3261802111, 0);  // [time: 710ns -> 730ns]
+    reset();  // [time: 770.001ns -> 780.001ns]
+    reset();  // [time: 780.001ns -> 790.001ns]
+    reset();  // [time: 790.001ns -> 800.001ns]
+    write(15, 67108867, 2711682730, 0);  // [time: 840.001ns -> 860.001ns]
+    write(15, 67108868, 4230444125, 0);  // [time: 860.001ns -> 880.001ns]
+    write(15, 67108869, 2579425060, 0);  // [time: 880.001ns -> 900.001ns]
+    write(15, 67108870, 2991027419, 0);  // [time: 900.001ns -> 920.001ns]
+    write(15, 67108871, 2417255467, 0);  // [time: 920.001ns -> 940.001ns]
+    write(15, 67108872, 4045742383, 0);  // [time: 940.001ns -> 960.001ns]
+    write(15, 67108873, 2931778361, 0);  // [time: 960.001ns -> 980.001ns]
+    write(15, 67108874, 3640821048, 0);  // [time: 980.001ns -> 1000.001ns]
+    write(15, 67108875, 3663784812, 0);  // [time: 1000.001ns -> 1020.001ns]
+    write(15, 67108876, 3627233541, 0);  // [time: 1020.001ns -> 1040.001ns]
+    write(15, 67108877, 2459429013, 0);  // [time: 1040.001ns -> 1060.001ns]
+    write(15, 67108878, 4213999775, 0);  // [time: 1060.001ns -> 1080.001ns]
+    write(15, 67108879, 2215241682, 0);  // [time: 1080.001ns -> 1100.001ns]
+    write(15, 67108880, 3801611658, 0);  // [time: 1100.001ns -> 1120.001ns]
+    write(15, 67108881, 2471241936, 0);  // [time: 1120.001ns -> 1140.001ns]
+    write(15, 67108882, 2691314341, 0);  // [time: 1140.001ns -> 1160.001ns]
+}
diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_16_4.bi.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_16_4.bi.expect
new file mode 100644
index 00000000..97bca31d
--- /dev/null
+++ b/tests/antmicro/sram_classic/expects/test_sram_classic_16_4.bi.expect
@@ -0,0 +1,41 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108865, 3946442578, 0);  // [time: 410ns -> 430ns]
+    read(15, 67108866, 2796792514, 0);  // [time: 430ns -> 450ns]
+    read(15, 67108867, 3312914512, 0);  // [time: 450ns -> 470ns]
+    read(15, 67108868, 4292142820, 0);  // [time: 470ns -> 490ns]
+    read(15, 67108869, 3525794570, 0);  // [time: 490ns -> 510ns]
+    read(15, 67108870, 2961047623, 0);  // [time: 510ns -> 530ns]
+    read(15, 67108871, 4249856274, 0);  // [time: 530ns -> 550ns]
+    read(15, 67108872, 3405678304, 0);  // [time: 550ns -> 570ns]
+    read(15, 67108873, 2415042617, 0);  // [time: 570ns -> 590ns]
+    read(15, 67108874, 3311552087, 0);  // [time: 590ns -> 610ns]
+    read(15, 67108875, 3211316809, 0);  // [time: 610ns -> 630ns]
+    read(15, 67108876, 3236997651, 0);  // [time: 630ns -> 650ns]
+    read(15, 67108877, 3369414426, 0);  // [time: 650ns -> 670ns]
+    read(15, 67108878, 3866725828, 0);  // [time: 670ns -> 690ns]
+    read(15, 67108879, 2882616058, 0);  // [time: 690ns -> 710ns]
+    read(15, 67108880, 3738458232, 0);  // [time: 710ns -> 730ns]
+    reset();  // [time: 770.001ns -> 780.001ns]
+    reset();  // [time: 780.001ns -> 790.001ns]
+    reset();  // [time: 790.001ns -> 800.001ns]
+    write(15, 67108865, 2558870979, 0);  // [time: 840.001ns -> 860.001ns]
+    write(15, 67108866, 3310254824, 0);  // [time: 860.001ns -> 880.001ns]
+    write(15, 67108867, 3635210891, 0);  // [time: 880.001ns -> 900.001ns]
+    write(15, 67108868, 2844952514, 0);  // [time: 900.001ns -> 920.001ns]
+    write(15, 67108869, 2293386100, 0);  // [time: 920.001ns -> 940.001ns]
+    write(15, 67108870, 3615462605, 0);  // [time: 940.001ns -> 960.001ns]
+    write(15, 67108871, 3569010089, 0);  // [time: 960.001ns -> 980.001ns]
+    write(15, 67108872, 3520072258, 0);  // [time: 980.001ns -> 1000.001ns]
+    write(15, 67108873, 3002516588, 0);  // [time: 1000.001ns -> 1020.001ns]
+    write(15, 67108874, 3681389096, 0);  // [time: 1020.001ns -> 1040.001ns]
+    write(15, 67108875, 2924663556, 0);  // [time: 1040.001ns -> 1060.001ns]
+    write(15, 67108876, 3055297102, 0);  // [time: 1060.001ns -> 1080.001ns]
+    write(15, 67108877, 4177639544, 0);  // [time: 1080.001ns -> 1100.001ns]
+    write(15, 67108878, 3526172361, 0);  // [time: 1100.001ns -> 1120.001ns]
+    write(15, 67108879, 2564412332, 0);  // [time: 1120.001ns -> 1140.001ns]
+    write(15, 67108880, 4210875098, 0);  // [time: 1140.001ns -> 1160.001ns]
+}
diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_16_8.bi.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_16_8.bi.expect
new file mode 100644
index 00000000..cb71ef95
--- /dev/null
+++ b/tests/antmicro/sram_classic/expects/test_sram_classic_16_8.bi.expect
@@ -0,0 +1,41 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108866, 3622568730, 0);  // [time: 410ns -> 430ns]
+    read(15, 67108867, 3538707329, 0);  // [time: 430ns -> 450ns]
+    read(15, 67108868, 3440721235, 0);  // [time: 450ns -> 470ns]
+    read(15, 67108869, 3191204602, 0);  // [time: 470ns -> 490ns]
+    read(15, 67108870, 4084986393, 0);  // [time: 490ns -> 510ns]
+    read(15, 67108871, 3446247256, 0);  // [time: 510ns -> 530ns]
+    read(15, 67108872, 3908428032, 0);  // [time: 530ns -> 550ns]
+    read(15, 67108873, 2315046581, 0);  // [time: 550ns -> 570ns]
+    read(15, 67108874, 2780682871, 0);  // [time: 570ns -> 590ns]
+    read(15, 67108875, 3026674647, 0);  // [time: 590ns -> 610ns]
+    read(15, 67108876, 2376933607, 0);  // [time: 610ns -> 630ns]
+    read(15, 67108877, 2436105964, 0);  // [time: 630ns -> 650ns]
+    read(15, 67108878, 3222378968, 0);  // [time: 650ns -> 670ns]
+    read(15, 67108879, 3310323703, 0);  // [time: 670ns -> 690ns]
+    read(15, 67108880, 2550879638, 0);  // [time: 690ns -> 710ns]
+    read(15, 67108881, 3261802111, 0);  // [time: 710ns -> 730ns]
+    reset();  // [time: 770.001ns -> 780.001ns]
+    reset();  // [time: 780.001ns -> 790.001ns]
+    reset();  // [time: 790.001ns -> 800.001ns]
+    write(15, 67108866, 2711682730, 0);  // [time: 840.001ns -> 860.001ns]
+    write(15, 67108867, 4230444125, 0);  // [time: 860.001ns -> 880.001ns]
+    write(15, 67108868, 2579425060, 0);  // [time: 880.001ns -> 900.001ns]
+    write(15, 67108869, 2991027419, 0);  // [time: 900.001ns -> 920.001ns]
+    write(15, 67108870, 2417255467, 0);  // [time: 920.001ns -> 940.001ns]
+    write(15, 67108871, 4045742383, 0);  // [time: 940.001ns -> 960.001ns]
+    write(15, 67108872, 2931778361, 0);  // [time: 960.001ns -> 980.001ns]
+    write(15, 67108873, 3640821048, 0);  // [time: 980.001ns -> 1000.001ns]
+    write(15, 67108874, 3663784812, 0);  // [time: 1000.001ns -> 1020.001ns]
+    write(15, 67108875, 3627233541, 0);  // [time: 1020.001ns -> 1040.001ns]
+    write(15, 67108876, 2459429013, 0);  // [time: 1040.001ns -> 1060.001ns]
+    write(15, 67108877, 4213999775, 0);  // [time: 1060.001ns -> 1080.001ns]
+    write(15, 67108878, 2215241682, 0);  // [time: 1080.001ns -> 1100.001ns]
+    write(15, 67108879, 3801611658, 0);  // [time: 1100.001ns -> 1120.001ns]
+    write(15, 67108880, 2471241936, 0);  // [time: 1120.001ns -> 1140.001ns]
+    write(15, 67108881, 2691314341, 0);  // [time: 1140.001ns -> 1160.001ns]
+}
diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_1_0.bi.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_1_0.bi.expect
new file mode 100644
index 00000000..5eaf9412
--- /dev/null
+++ b/tests/antmicro/sram_classic/expects/test_sram_classic_1_0.bi.expect
@@ -0,0 +1,11 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108864, 2993300090, 0);  // [time: 110ns -> 130ns]
+    reset();  // [time: 170.001ns -> 180.001ns]
+    reset();  // [time: 180.001ns -> 190.001ns]
+    reset();  // [time: 190.001ns -> 200.001ns]
+    write(15, 67108864, 3921107982, 0);  // [time: 240.001ns -> 260.001ns]
+}
diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_1_12.bi.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_1_12.bi.expect
new file mode 100644
index 00000000..d429b3d6
--- /dev/null
+++ b/tests/antmicro/sram_classic/expects/test_sram_classic_1_12.bi.expect
@@ -0,0 +1,11 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108867, 3946442578, 0);  // [time: 110ns -> 130ns]
+    reset();  // [time: 170.001ns -> 180.001ns]
+    reset();  // [time: 180.001ns -> 190.001ns]
+    reset();  // [time: 190.001ns -> 200.001ns]
+    write(15, 67108867, 2796792514, 0);  // [time: 240.001ns -> 260.001ns]
+}
diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_1_4.bi.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_1_4.bi.expect
new file mode 100644
index 00000000..a626949a
--- /dev/null
+++ b/tests/antmicro/sram_classic/expects/test_sram_classic_1_4.bi.expect
@@ -0,0 +1,11 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108865, 2993300090, 0);  // [time: 110ns -> 130ns]
+    reset();  // [time: 170.001ns -> 180.001ns]
+    reset();  // [time: 180.001ns -> 190.001ns]
+    reset();  // [time: 190.001ns -> 200.001ns]
+    write(15, 67108865, 3921107982, 0);  // [time: 240.001ns -> 260.001ns]
+}
diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_1_8.bi.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_1_8.bi.expect
new file mode 100644
index 00000000..c1285b74
--- /dev/null
+++ b/tests/antmicro/sram_classic/expects/test_sram_classic_1_8.bi.expect
@@ -0,0 +1,11 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108866, 3946442578, 0);  // [time: 110ns -> 130ns]
+    reset();  // [time: 170.001ns -> 180.001ns]
+    reset();  // [time: 180.001ns -> 190.001ns]
+    reset();  // [time: 190.001ns -> 200.001ns]
+    write(15, 67108866, 2796792514, 0);  // [time: 240.001ns -> 260.001ns]
+}
diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_2_0.bi.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_2_0.bi.expect
new file mode 100644
index 00000000..de5ee088
--- /dev/null
+++ b/tests/antmicro/sram_classic/expects/test_sram_classic_2_0.bi.expect
@@ -0,0 +1,13 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108864, 3622568730, 0);  // [time: 130ns -> 150ns]
+    read(15, 67108865, 3538707329, 0);  // [time: 150ns -> 170ns]
+    reset();  // [time: 210.001ns -> 220.001ns]
+    reset();  // [time: 220.001ns -> 230.001ns]
+    reset();  // [time: 230.001ns -> 240.001ns]
+    write(15, 67108864, 3440721235, 0);  // [time: 280.001ns -> 300.001ns]
+    write(15, 67108865, 3191204602, 0);  // [time: 300.001ns -> 320.001ns]
+}
diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_2_12.bi.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_2_12.bi.expect
new file mode 100644
index 00000000..3871f1f8
--- /dev/null
+++ b/tests/antmicro/sram_classic/expects/test_sram_classic_2_12.bi.expect
@@ -0,0 +1,13 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108867, 2993300090, 0);  // [time: 130ns -> 150ns]
+    read(15, 67108868, 3921107982, 0);  // [time: 150ns -> 170ns]
+    reset();  // [time: 210.001ns -> 220.001ns]
+    reset();  // [time: 220.001ns -> 230.001ns]
+    reset();  // [time: 230.001ns -> 240.001ns]
+    write(15, 67108867, 2480359279, 0);  // [time: 280.001ns -> 300.001ns]
+    write(15, 67108868, 3789792143, 0);  // [time: 300.001ns -> 320.001ns]
+}
diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_2_4.bi.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_2_4.bi.expect
new file mode 100644
index 00000000..1a5c670e
--- /dev/null
+++ b/tests/antmicro/sram_classic/expects/test_sram_classic_2_4.bi.expect
@@ -0,0 +1,13 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108865, 3622568730, 0);  // [time: 130ns -> 150ns]
+    read(15, 67108866, 3538707329, 0);  // [time: 150ns -> 170ns]
+    reset();  // [time: 210.001ns -> 220.001ns]
+    reset();  // [time: 220.001ns -> 230.001ns]
+    reset();  // [time: 230.001ns -> 240.001ns]
+    write(15, 67108865, 3440721235, 0);  // [time: 280.001ns -> 300.001ns]
+    write(15, 67108866, 3191204602, 0);  // [time: 300.001ns -> 320.001ns]
+}
diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_2_8.bi.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_2_8.bi.expect
new file mode 100644
index 00000000..17d7651a
--- /dev/null
+++ b/tests/antmicro/sram_classic/expects/test_sram_classic_2_8.bi.expect
@@ -0,0 +1,13 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108866, 3250481594, 0);  // [time: 130ns -> 150ns]
+    read(15, 67108867, 2390763695, 0);  // [time: 150ns -> 170ns]
+    reset();  // [time: 210.001ns -> 220.001ns]
+    reset();  // [time: 220.001ns -> 230.001ns]
+    reset();  // [time: 230.001ns -> 240.001ns]
+    write(15, 67108866, 4197550477, 0);  // [time: 280.001ns -> 300.001ns]
+    write(15, 67108867, 2445792994, 0);  // [time: 300.001ns -> 320.001ns]
+}
diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_4_0.bi.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_4_0.bi.expect
new file mode 100644
index 00000000..5ad819ac
--- /dev/null
+++ b/tests/antmicro/sram_classic/expects/test_sram_classic_4_0.bi.expect
@@ -0,0 +1,17 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108864, 2993300090, 0);  // [time: 170ns -> 190ns]
+    read(15, 67108865, 3921107982, 0);  // [time: 190ns -> 210ns]
+    read(15, 67108866, 2480359279, 0);  // [time: 210ns -> 230ns]
+    read(15, 67108867, 3789792143, 0);  // [time: 230ns -> 250ns]
+    reset();  // [time: 290.001ns -> 300.001ns]
+    reset();  // [time: 300.001ns -> 310.001ns]
+    reset();  // [time: 310.001ns -> 320.001ns]
+    write(15, 67108864, 2250616272, 0);  // [time: 360.001ns -> 380.001ns]
+    write(15, 67108865, 3654263702, 0);  // [time: 380.001ns -> 400.001ns]
+    write(15, 67108866, 2773364137, 0);  // [time: 400.001ns -> 420.001ns]
+    write(15, 67108867, 2521253772, 0);  // [time: 420.001ns -> 440.001ns]
+}
diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_4_12.bi.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_4_12.bi.expect
new file mode 100644
index 00000000..961f4bc4
--- /dev/null
+++ b/tests/antmicro/sram_classic/expects/test_sram_classic_4_12.bi.expect
@@ -0,0 +1,17 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108867, 3622568730, 0);  // [time: 170ns -> 190ns]
+    read(15, 67108868, 3538707329, 0);  // [time: 190ns -> 210ns]
+    read(15, 67108869, 3440721235, 0);  // [time: 210ns -> 230ns]
+    read(15, 67108870, 3191204602, 0);  // [time: 230ns -> 250ns]
+    reset();  // [time: 290.001ns -> 300.001ns]
+    reset();  // [time: 300.001ns -> 310.001ns]
+    reset();  // [time: 310.001ns -> 320.001ns]
+    write(15, 67108867, 4084986393, 0);  // [time: 360.001ns -> 380.001ns]
+    write(15, 67108868, 3446247256, 0);  // [time: 380.001ns -> 400.001ns]
+    write(15, 67108869, 3908428032, 0);  // [time: 400.001ns -> 420.001ns]
+    write(15, 67108870, 2315046581, 0);  // [time: 420.001ns -> 440.001ns]
+}
diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_4_4.bi.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_4_4.bi.expect
new file mode 100644
index 00000000..e1428e90
--- /dev/null
+++ b/tests/antmicro/sram_classic/expects/test_sram_classic_4_4.bi.expect
@@ -0,0 +1,17 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108865, 3946442578, 0);  // [time: 170ns -> 190ns]
+    read(15, 67108866, 2796792514, 0);  // [time: 190ns -> 210ns]
+    read(15, 67108867, 3312914512, 0);  // [time: 210ns -> 230ns]
+    read(15, 67108868, 4292142820, 0);  // [time: 230ns -> 250ns]
+    reset();  // [time: 290.001ns -> 300.001ns]
+    reset();  // [time: 300.001ns -> 310.001ns]
+    reset();  // [time: 310.001ns -> 320.001ns]
+    write(15, 67108865, 3525794570, 0);  // [time: 360.001ns -> 380.001ns]
+    write(15, 67108866, 2961047623, 0);  // [time: 380.001ns -> 400.001ns]
+    write(15, 67108867, 4249856274, 0);  // [time: 400.001ns -> 420.001ns]
+    write(15, 67108868, 3405678304, 0);  // [time: 420.001ns -> 440.001ns]
+}
diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_4_8.bi.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_4_8.bi.expect
new file mode 100644
index 00000000..01877415
--- /dev/null
+++ b/tests/antmicro/sram_classic/expects/test_sram_classic_4_8.bi.expect
@@ -0,0 +1,17 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108866, 3946442578, 0);  // [time: 170ns -> 190ns]
+    read(15, 67108867, 2796792514, 0);  // [time: 190ns -> 210ns]
+    read(15, 67108868, 3312914512, 0);  // [time: 210ns -> 230ns]
+    read(15, 67108869, 4292142820, 0);  // [time: 230ns -> 250ns]
+    reset();  // [time: 290.001ns -> 300.001ns]
+    reset();  // [time: 300.001ns -> 310.001ns]
+    reset();  // [time: 310.001ns -> 320.001ns]
+    write(15, 67108866, 3525794570, 0);  // [time: 360.001ns -> 380.001ns]
+    write(15, 67108867, 2961047623, 0);  // [time: 380.001ns -> 400.001ns]
+    write(15, 67108868, 4249856274, 0);  // [time: 400.001ns -> 420.001ns]
+    write(15, 67108869, 3405678304, 0);  // [time: 420.001ns -> 440.001ns]
+}
diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_8_0.bi.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_8_0.bi.expect
new file mode 100644
index 00000000..36649517
--- /dev/null
+++ b/tests/antmicro/sram_classic/expects/test_sram_classic_8_0.bi.expect
@@ -0,0 +1,25 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108864, 3622568730, 0);  // [time: 250ns -> 270ns]
+    read(15, 67108865, 3538707329, 0);  // [time: 270ns -> 290ns]
+    read(15, 67108866, 3440721235, 0);  // [time: 290ns -> 310ns]
+    read(15, 67108867, 3191204602, 0);  // [time: 310ns -> 330ns]
+    read(15, 67108868, 4084986393, 0);  // [time: 330ns -> 350ns]
+    read(15, 67108869, 3446247256, 0);  // [time: 350ns -> 370ns]
+    read(15, 67108870, 3908428032, 0);  // [time: 370ns -> 390ns]
+    read(15, 67108871, 2315046581, 0);  // [time: 390ns -> 410ns]
+    reset();  // [time: 450.001ns -> 460.001ns]
+    reset();  // [time: 460.001ns -> 470.001ns]
+    reset();  // [time: 470.001ns -> 480.001ns]
+    write(15, 67108864, 2780682871, 0);  // [time: 520.001ns -> 540.001ns]
+    write(15, 67108865, 3026674647, 0);  // [time: 540.001ns -> 560.001ns]
+    write(15, 67108866, 2376933607, 0);  // [time: 560.001ns -> 580.001ns]
+    write(15, 67108867, 2436105964, 0);  // [time: 580.001ns -> 600.001ns]
+    write(15, 67108868, 3222378968, 0);  // [time: 600.001ns -> 620.001ns]
+    write(15, 67108869, 3310323703, 0);  // [time: 620.001ns -> 640.001ns]
+    write(15, 67108870, 2550879638, 0);  // [time: 640.001ns -> 660.001ns]
+    write(15, 67108871, 3261802111, 0);  // [time: 660.001ns -> 680.001ns]
+}
diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_8_12.bi.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_8_12.bi.expect
new file mode 100644
index 00000000..b7f411ee
--- /dev/null
+++ b/tests/antmicro/sram_classic/expects/test_sram_classic_8_12.bi.expect
@@ -0,0 +1,25 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108867, 2993300090, 0);  // [time: 250ns -> 270ns]
+    read(15, 67108868, 3921107982, 0);  // [time: 270ns -> 290ns]
+    read(15, 67108869, 2480359279, 0);  // [time: 290ns -> 310ns]
+    read(15, 67108870, 3789792143, 0);  // [time: 310ns -> 330ns]
+    read(15, 67108871, 2250616272, 0);  // [time: 330ns -> 350ns]
+    read(15, 67108872, 3654263702, 0);  // [time: 350ns -> 370ns]
+    read(15, 67108873, 2773364137, 0);  // [time: 370ns -> 390ns]
+    read(15, 67108874, 2521253772, 0);  // [time: 390ns -> 410ns]
+    reset();  // [time: 450.001ns -> 460.001ns]
+    reset();  // [time: 460.001ns -> 470.001ns]
+    reset();  // [time: 470.001ns -> 480.001ns]
+    write(15, 67108867, 2521411224, 0);  // [time: 520.001ns -> 540.001ns]
+    write(15, 67108868, 2219799945, 0);  // [time: 540.001ns -> 560.001ns]
+    write(15, 67108869, 3487354134, 0);  // [time: 560.001ns -> 580.001ns]
+    write(15, 67108870, 2235755512, 0);  // [time: 580.001ns -> 600.001ns]
+    write(15, 67108871, 2319980602, 0);  // [time: 600.001ns -> 620.001ns]
+    write(15, 67108872, 2978178103, 0);  // [time: 620.001ns -> 640.001ns]
+    write(15, 67108873, 2464653045, 0);  // [time: 640.001ns -> 660.001ns]
+    write(15, 67108874, 2202449462, 0);  // [time: 660.001ns -> 680.001ns]
+}
diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_8_4.bi.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_8_4.bi.expect
new file mode 100644
index 00000000..9e2e1b4f
--- /dev/null
+++ b/tests/antmicro/sram_classic/expects/test_sram_classic_8_4.bi.expect
@@ -0,0 +1,25 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108865, 3250481594, 0);  // [time: 250ns -> 270ns]
+    read(15, 67108866, 2390763695, 0);  // [time: 270ns -> 290ns]
+    read(15, 67108867, 4197550477, 0);  // [time: 290ns -> 310ns]
+    read(15, 67108868, 2445792994, 0);  // [time: 310ns -> 330ns]
+    read(15, 67108869, 3897454712, 0);  // [time: 330ns -> 350ns]
+    read(15, 67108870, 3326339601, 0);  // [time: 350ns -> 370ns]
+    read(15, 67108871, 3190747046, 0);  // [time: 370ns -> 390ns]
+    read(15, 67108872, 2329522371, 0);  // [time: 390ns -> 410ns]
+    reset();  // [time: 450.001ns -> 460.001ns]
+    reset();  // [time: 460.001ns -> 470.001ns]
+    reset();  // [time: 470.001ns -> 480.001ns]
+    write(15, 67108865, 2252821017, 0);  // [time: 520.001ns -> 540.001ns]
+    write(15, 67108866, 2931126915, 0);  // [time: 540.001ns -> 560.001ns]
+    write(15, 67108867, 2608883160, 0);  // [time: 560.001ns -> 580.001ns]
+    write(15, 67108868, 4233362437, 0);  // [time: 580.001ns -> 600.001ns]
+    write(15, 67108869, 2517580333, 0);  // [time: 600.001ns -> 620.001ns]
+    write(15, 67108870, 2583768976, 0);  // [time: 620.001ns -> 640.001ns]
+    write(15, 67108871, 2451763371, 0);  // [time: 640.001ns -> 660.001ns]
+    write(15, 67108872, 2672364833, 0);  // [time: 660.001ns -> 680.001ns]
+}
diff --git a/tests/antmicro/sram_classic/expects/test_sram_classic_8_8.bi.expect b/tests/antmicro/sram_classic/expects/test_sram_classic_8_8.bi.expect
new file mode 100644
index 00000000..1347d8fd
--- /dev/null
+++ b/tests/antmicro/sram_classic/expects/test_sram_classic_8_8.bi.expect
@@ -0,0 +1,25 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108866, 2993300090, 0);  // [time: 250ns -> 270ns]
+    read(15, 67108867, 3921107982, 0);  // [time: 270ns -> 290ns]
+    read(15, 67108868, 2480359279, 0);  // [time: 290ns -> 310ns]
+    read(15, 67108869, 3789792143, 0);  // [time: 310ns -> 330ns]
+    read(15, 67108870, 2250616272, 0);  // [time: 330ns -> 350ns]
+    read(15, 67108871, 3654263702, 0);  // [time: 350ns -> 370ns]
+    read(15, 67108872, 2773364137, 0);  // [time: 370ns -> 390ns]
+    read(15, 67108873, 2521253772, 0);  // [time: 390ns -> 410ns]
+    reset();  // [time: 450.001ns -> 460.001ns]
+    reset();  // [time: 460.001ns -> 470.001ns]
+    reset();  // [time: 470.001ns -> 480.001ns]
+    write(15, 67108866, 2521411224, 0);  // [time: 520.001ns -> 540.001ns]
+    write(15, 67108867, 2219799945, 0);  // [time: 540.001ns -> 560.001ns]
+    write(15, 67108868, 3487354134, 0);  // [time: 560.001ns -> 580.001ns]
+    write(15, 67108869, 2235755512, 0);  // [time: 580.001ns -> 600.001ns]
+    write(15, 67108870, 2319980602, 0);  // [time: 600.001ns -> 620.001ns]
+    write(15, 67108871, 2978178103, 0);  // [time: 620.001ns -> 640.001ns]
+    write(15, 67108872, 2464653045, 0);  // [time: 640.001ns -> 660.001ns]
+    write(15, 67108873, 2202449462, 0);  // [time: 660.001ns -> 680.001ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_0_0.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_0_0.bi.expect
new file mode 100644
index 00000000..d079ea48
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_0_0.bi.expect
@@ -0,0 +1,61 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108864, 1016512136, 0);  // [time: 410ns -> 430ns]
+    read(15, 67108865, 226204128, 0);  // [time: 430ns -> 440ns]
+    read(15, 67108866, 2116565440, 0);  // [time: 440ns -> 450ns]
+    read(15, 67108867, 2153688786, 0);  // [time: 450ns -> 460ns]
+    read(15, 67108868, 1974223269, 0);  // [time: 460ns -> 470ns]
+    read(15, 67108869, 1053640572, 0);  // [time: 470ns -> 480ns]
+    read(15, 67108870, 2079860600, 0);  // [time: 480ns -> 490ns]
+    read(15, 67108871, 3550045624, 0);  // [time: 490ns -> 500ns]
+    read(15, 67108872, 1038322047, 0);  // [time: 500ns -> 510ns]
+    read(15, 67108873, 1502718053, 0);  // [time: 510ns -> 520ns]
+    read(15, 67108874, 1367070343, 0);  // [time: 520ns -> 530ns]
+    read(15, 67108875, 3425882885, 0);  // [time: 530ns -> 540ns]
+    read(15, 67108876, 1614916721, 0);  // [time: 540ns -> 550ns]
+    read(15, 67108877, 3041346437, 0);  // [time: 550ns -> 560ns]
+    read(15, 67108878, 3665993952, 0);  // [time: 560ns -> 570ns]
+    read(15, 67108879, 3560581876, 0);  // [time: 570ns -> 580ns]
+    reset();  // [time: 620.001ns -> 630.001ns]
+    reset();  // [time: 630.001ns -> 640.001ns]
+    reset();  // [time: 640.001ns -> 650.001ns]
+    write(15, 67108864, 3433786972, 0);  // [time: 690.001ns -> 710.001ns]
+    write(15, 67108865, 3840560806, 0);  // [time: 710.001ns -> 720.001ns]
+    write(15, 67108866, 3225552468, 0);  // [time: 720.001ns -> 730.001ns]
+    write(15, 67108867, 3717810263, 0);  // [time: 730.001ns -> 740.001ns]
+    write(15, 67108868, 3317657198, 0);  // [time: 740.001ns -> 750.001ns]
+    write(15, 67108869, 1024069544, 0);  // [time: 750.001ns -> 760.001ns]
+    write(15, 67108870, 1752245362, 0);  // [time: 760.001ns -> 770.001ns]
+    write(15, 67108871, 1579776374, 0);  // [time: 770.001ns -> 780.001ns]
+    write(15, 67108872, 904253205, 0);  // [time: 780.001ns -> 790.001ns]
+    write(15, 67108873, 1728285430, 0);  // [time: 790.001ns -> 800.001ns]
+    write(15, 67108874, 91066718, 0);  // [time: 800.001ns -> 810.001ns]
+    write(15, 67108875, 1402442819, 0);  // [time: 810.001ns -> 820.001ns]
+    write(15, 67108876, 4062122226, 0);  // [time: 820.001ns -> 830.001ns]
+    write(15, 67108877, 1191921998, 0);  // [time: 830.001ns -> 840.001ns]
+    write(15, 67108878, 1249541889, 0);  // [time: 840.001ns -> 850.001ns]
+    write(15, 67108879, 2580891116, 0);  // [time: 850.001ns -> 860.001ns]
+    reset();  // [time: 1540.002ns -> 1550.002ns]
+    reset();  // [time: 1550.002ns -> 1560.002ns]
+    reset();  // [time: 1560.002ns -> 1570.002ns]
+    write(15, 67108864, 1526706340, 0);  // [time: 1610.002ns -> 1630.002ns]
+    write(15, 67108865, 1162262173, 0);  // [time: 1630.002ns -> 1640.002ns]
+    write(15, 67108866, 3667501502, 0);  // [time: 1640.002ns -> 1650.002ns]
+    write(15, 67108867, 617255735, 0);  // [time: 1650.002ns -> 1660.002ns]
+    write(15, 67108868, 4077356414, 0);  // [time: 1660.002ns -> 1670.002ns]
+    write(15, 67108869, 1593609662, 0);  // [time: 1670.002ns -> 1680.002ns]
+    write(15, 67108870, 2148292499, 0);  // [time: 1680.002ns -> 1690.002ns]
+    write(15, 67108871, 3403556849, 0);  // [time: 1690.002ns -> 1700.002ns]
+    write(15, 67108872, 3331963440, 0);  // [time: 1700.002ns -> 1710.002ns]
+    write(15, 67108873, 1493302995, 0);  // [time: 1710.002ns -> 1720.002ns]
+    write(15, 67108874, 2710958922, 0);  // [time: 1720.002ns -> 1730.002ns]
+    write(15, 67108875, 4029972623, 0);  // [time: 1730.002ns -> 1740.002ns]
+    write(15, 67108876, 2845272388, 0);  // [time: 1740.002ns -> 1750.002ns]
+    write(15, 67108877, 70166840, 0);  // [time: 1750.002ns -> 1760.002ns]
+    write(15, 67108878, 1323291936, 0);  // [time: 1760.002ns -> 1770.002ns]
+    write(15, 67108879, 916783944, 0);  // [time: 1770.002ns -> 1780.002ns]
+    read(15, 67108864, 1526706340, 0);  // [time: 1780.002ns -> 1800.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_0_1.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_0_1.bi.expect
new file mode 100644
index 00000000..fcc2c6dc
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_0_1.bi.expect
@@ -0,0 +1,61 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108864, 518534189, 0);  // [time: 410ns -> 430ns]
+    read(15, 67108865, 844695266, 0);  // [time: 430ns -> 440ns]
+    read(15, 67108866, 3937184150, 0);  // [time: 440ns -> 450ns]
+    read(15, 67108867, 444246851, 0);  // [time: 450ns -> 460ns]
+    read(15, 67108868, 3220682802, 0);  // [time: 460ns -> 470ns]
+    read(15, 67108869, 2130811954, 0);  // [time: 470ns -> 480ns]
+    read(15, 67108870, 2002127438, 0);  // [time: 480ns -> 490ns]
+    read(15, 67108871, 493792053, 0);  // [time: 490ns -> 500ns]
+    read(15, 67108872, 63714206, 0);  // [time: 500ns -> 510ns]
+    read(15, 67108873, 2091823691, 0);  // [time: 510ns -> 520ns]
+    read(15, 67108874, 3903276977, 0);  // [time: 520ns -> 530ns]
+    read(15, 67108875, 1662756337, 0);  // [time: 530ns -> 540ns]
+    read(15, 67108876, 4101310419, 0);  // [time: 540ns -> 550ns]
+    read(15, 67108877, 903798156, 0);  // [time: 550ns -> 560ns]
+    read(15, 67108878, 3840476340, 0);  // [time: 560ns -> 570ns]
+    read(15, 67108879, 2244097975, 0);  // [time: 570ns -> 580ns]
+    reset();  // [time: 620.001ns -> 630.001ns]
+    reset();  // [time: 630.001ns -> 640.001ns]
+    reset();  // [time: 640.001ns -> 650.001ns]
+    write(15, 67108864, 3956643922, 0);  // [time: 690.001ns -> 710.001ns]
+    write(15, 67108865, 2115347845, 0);  // [time: 710.001ns -> 720.001ns]
+    write(15, 67108866, 1775201107, 0);  // [time: 720.001ns -> 730.001ns]
+    write(15, 67108867, 1046910518, 0);  // [time: 730.001ns -> 740.001ns]
+    write(15, 67108868, 345998276, 0);  // [time: 740.001ns -> 750.001ns]
+    write(15, 67108869, 2089777588, 0);  // [time: 750.001ns -> 760.001ns]
+    write(15, 67108870, 3110941387, 0);  // [time: 760.001ns -> 770.001ns]
+    write(15, 67108871, 3151493219, 0);  // [time: 770.001ns -> 780.001ns]
+    write(15, 67108872, 1789821109, 0);  // [time: 780.001ns -> 790.001ns]
+    write(15, 67108873, 976504712, 0);  // [time: 790.001ns -> 800.001ns]
+    write(15, 67108874, 3716648277, 0);  // [time: 800.001ns -> 810.001ns]
+    write(15, 67108875, 3764578858, 0);  // [time: 810.001ns -> 820.001ns]
+    write(15, 67108876, 2575976733, 0);  // [time: 820.001ns -> 830.001ns]
+    write(15, 67108877, 2758477517, 0);  // [time: 830.001ns -> 840.001ns]
+    write(15, 67108878, 801284123, 0);  // [time: 840.001ns -> 850.001ns]
+    write(15, 67108879, 1745171602, 0);  // [time: 850.001ns -> 860.001ns]
+    reset();  // [time: 1540.002ns -> 1550.002ns]
+    reset();  // [time: 1550.002ns -> 1560.002ns]
+    reset();  // [time: 1560.002ns -> 1570.002ns]
+    write(15, 67108864, 2836493204, 0);  // [time: 1610.002ns -> 1630.002ns]
+    write(15, 67108865, 3265525290, 0);  // [time: 1630.002ns -> 1640.002ns]
+    write(15, 67108866, 2395253012, 0);  // [time: 1640.002ns -> 1650.002ns]
+    write(15, 67108867, 3557189713, 0);  // [time: 1650.002ns -> 1660.002ns]
+    write(15, 67108868, 764605320, 0);  // [time: 1660.002ns -> 1670.002ns]
+    write(15, 67108869, 2679315363, 0);  // [time: 1670.002ns -> 1680.002ns]
+    write(15, 67108870, 375184876, 0);  // [time: 1680.002ns -> 1690.002ns]
+    write(15, 67108871, 4121117117, 0);  // [time: 1690.002ns -> 1700.002ns]
+    write(15, 67108872, 1446110016, 0);  // [time: 1700.002ns -> 1710.002ns]
+    write(15, 67108873, 3729875561, 0);  // [time: 1710.002ns -> 1720.002ns]
+    write(15, 67108874, 2582294219, 0);  // [time: 1720.002ns -> 1730.002ns]
+    write(15, 67108875, 409432939, 0);  // [time: 1730.002ns -> 1740.002ns]
+    write(15, 67108876, 937977575, 0);  // [time: 1740.002ns -> 1750.002ns]
+    write(15, 67108877, 1981138244, 0);  // [time: 1750.002ns -> 1760.002ns]
+    write(15, 67108878, 2912031569, 0);  // [time: 1760.002ns -> 1770.002ns]
+    write(15, 67108879, 896776296, 0);  // [time: 1770.002ns -> 1780.002ns]
+    read(15, 67108864, 2836493204, 0);  // [time: 1780.002ns -> 1800.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_0_2.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_0_2.bi.expect
new file mode 100644
index 00000000..6f08eae7
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_0_2.bi.expect
@@ -0,0 +1,61 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108864, 3495738447, 0);  // [time: 410ns -> 430ns]
+    read(15, 67108865, 1478546475, 0);  // [time: 430ns -> 440ns]
+    read(15, 67108866, 2041778918, 0);  // [time: 440ns -> 450ns]
+    read(15, 67108867, 3032895213, 0);  // [time: 450ns -> 460ns]
+    read(15, 67108868, 2020268309, 0);  // [time: 460ns -> 470ns]
+    read(15, 67108869, 3122719830, 0);  // [time: 470ns -> 480ns]
+    read(15, 67108870, 3806053567, 0);  // [time: 480ns -> 490ns]
+    read(15, 67108871, 3858565026, 0);  // [time: 490ns -> 500ns]
+    read(15, 67108872, 880624971, 0);  // [time: 500ns -> 510ns]
+    read(15, 67108873, 2554056607, 0);  // [time: 510ns -> 520ns]
+    read(15, 67108874, 1441832696, 0);  // [time: 520ns -> 530ns]
+    read(15, 67108875, 479445740, 0);  // [time: 530ns -> 540ns]
+    read(15, 67108876, 2229265910, 0);  // [time: 540ns -> 550ns]
+    read(15, 67108877, 788973880, 0);  // [time: 550ns -> 560ns]
+    read(15, 67108878, 3880977277, 0);  // [time: 560ns -> 570ns]
+    read(15, 67108879, 4096708504, 0);  // [time: 570ns -> 580ns]
+    reset();  // [time: 620.001ns -> 630.001ns]
+    reset();  // [time: 630.001ns -> 640.001ns]
+    reset();  // [time: 640.001ns -> 650.001ns]
+    write(15, 67108864, 2427636421, 0);  // [time: 690.001ns -> 710.001ns]
+    write(15, 67108865, 3595099675, 0);  // [time: 710.001ns -> 720.001ns]
+    write(15, 67108866, 2668681316, 0);  // [time: 720.001ns -> 730.001ns]
+    write(15, 67108867, 1679837987, 0);  // [time: 730.001ns -> 740.001ns]
+    write(15, 67108868, 924732013, 0);  // [time: 740.001ns -> 750.001ns]
+    write(15, 67108869, 2192079403, 0);  // [time: 750.001ns -> 760.001ns]
+    write(15, 67108870, 2042051660, 0);  // [time: 760.001ns -> 770.001ns]
+    write(15, 67108871, 989927686, 0);  // [time: 770.001ns -> 780.001ns]
+    write(15, 67108872, 3067406900, 0);  // [time: 780.001ns -> 790.001ns]
+    write(15, 67108873, 1058215073, 0);  // [time: 790.001ns -> 800.001ns]
+    write(15, 67108874, 365012335, 0);  // [time: 800.001ns -> 810.001ns]
+    write(15, 67108875, 687295108, 0);  // [time: 810.001ns -> 820.001ns]
+    write(15, 67108876, 2829218573, 0);  // [time: 820.001ns -> 830.001ns]
+    write(15, 67108877, 1448409262, 0);  // [time: 830.001ns -> 840.001ns]
+    write(15, 67108878, 400594486, 0);  // [time: 840.001ns -> 850.001ns]
+    write(15, 67108879, 4177343116, 0);  // [time: 850.001ns -> 860.001ns]
+    reset();  // [time: 1540.002ns -> 1550.002ns]
+    reset();  // [time: 1550.002ns -> 1560.002ns]
+    reset();  // [time: 1560.002ns -> 1570.002ns]
+    write(15, 67108864, 2304668716, 0);  // [time: 1610.002ns -> 1630.002ns]
+    write(15, 67108865, 2610611482, 0);  // [time: 1630.002ns -> 1640.002ns]
+    write(15, 67108866, 1468153982, 0);  // [time: 1640.002ns -> 1650.002ns]
+    write(15, 67108867, 1169841342, 0);  // [time: 1650.002ns -> 1660.002ns]
+    write(15, 67108868, 27036823, 0);  // [time: 1660.002ns -> 1670.002ns]
+    write(15, 67108869, 73783758, 0);  // [time: 1670.002ns -> 1680.002ns]
+    write(15, 67108870, 1621524717, 0);  // [time: 1680.002ns -> 1690.002ns]
+    write(15, 67108871, 3905946412, 0);  // [time: 1690.002ns -> 1700.002ns]
+    write(15, 67108872, 1563100034, 0);  // [time: 1700.002ns -> 1710.002ns]
+    write(15, 67108873, 2069336907, 0);  // [time: 1710.002ns -> 1720.002ns]
+    write(15, 67108874, 583373053, 0);  // [time: 1720.002ns -> 1730.002ns]
+    write(15, 67108875, 3629920426, 0);  // [time: 1730.002ns -> 1740.002ns]
+    write(15, 67108876, 2146122704, 0);  // [time: 1740.002ns -> 1750.002ns]
+    write(15, 67108877, 2674258699, 0);  // [time: 1750.002ns -> 1760.002ns]
+    write(15, 67108878, 1361676606, 0);  // [time: 1760.002ns -> 1770.002ns]
+    write(15, 67108879, 2435452493, 0);  // [time: 1770.002ns -> 1780.002ns]
+    read(15, 67108864, 2304668716, 0);  // [time: 1780.002ns -> 1800.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_0_3.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_0_3.bi.expect
new file mode 100644
index 00000000..d1d6d833
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_0_3.bi.expect
@@ -0,0 +1,61 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108864, 1070372987, 0);  // [time: 410ns -> 430ns]
+    read(15, 67108865, 2645947069, 0);  // [time: 430ns -> 440ns]
+    read(15, 67108866, 736643984, 0);  // [time: 440ns -> 450ns]
+    read(15, 67108867, 192007203, 0);  // [time: 450ns -> 460ns]
+    read(15, 67108868, 1925400290, 0);  // [time: 460ns -> 470ns]
+    read(15, 67108869, 1309609983, 0);  // [time: 470ns -> 480ns]
+    read(15, 67108870, 58503546, 0);  // [time: 480ns -> 490ns]
+    read(15, 67108871, 3861022989, 0);  // [time: 490ns -> 500ns]
+    read(15, 67108872, 1725708128, 0);  // [time: 500ns -> 510ns]
+    read(15, 67108873, 3760744365, 0);  // [time: 510ns -> 520ns]
+    read(15, 67108874, 3803789590, 0);  // [time: 520ns -> 530ns]
+    read(15, 67108875, 2647121574, 0);  // [time: 530ns -> 540ns]
+    read(15, 67108876, 336117328, 0);  // [time: 540ns -> 550ns]
+    read(15, 67108877, 3984726565, 0);  // [time: 550ns -> 560ns]
+    read(15, 67108878, 104808193, 0);  // [time: 560ns -> 570ns]
+    read(15, 67108879, 2315494688, 0);  // [time: 570ns -> 580ns]
+    reset();  // [time: 620.001ns -> 630.001ns]
+    reset();  // [time: 630.001ns -> 640.001ns]
+    reset();  // [time: 640.001ns -> 650.001ns]
+    write(15, 67108864, 3997204021, 0);  // [time: 690.001ns -> 710.001ns]
+    write(15, 67108865, 666660673, 0);  // [time: 710.001ns -> 720.001ns]
+    write(15, 67108866, 3910223084, 0);  // [time: 720.001ns -> 730.001ns]
+    write(15, 67108867, 1271405124, 0);  // [time: 730.001ns -> 740.001ns]
+    write(15, 67108868, 4236388983, 0);  // [time: 740.001ns -> 750.001ns]
+    write(15, 67108869, 1347016890, 0);  // [time: 750.001ns -> 760.001ns]
+    write(15, 67108870, 1337396640, 0);  // [time: 760.001ns -> 770.001ns]
+    write(15, 67108871, 3009712000, 0);  // [time: 770.001ns -> 780.001ns]
+    write(15, 67108872, 2237248361, 0);  // [time: 780.001ns -> 790.001ns]
+    write(15, 67108873, 592560133, 0);  // [time: 790.001ns -> 800.001ns]
+    write(15, 67108874, 371018497, 0);  // [time: 800.001ns -> 810.001ns]
+    write(15, 67108875, 763875626, 0);  // [time: 810.001ns -> 820.001ns]
+    write(15, 67108876, 75174504, 0);  // [time: 820.001ns -> 830.001ns]
+    write(15, 67108877, 2983449782, 0);  // [time: 830.001ns -> 840.001ns]
+    write(15, 67108878, 2295155532, 0);  // [time: 840.001ns -> 850.001ns]
+    write(15, 67108879, 1954643484, 0);  // [time: 850.001ns -> 860.001ns]
+    reset();  // [time: 1540.002ns -> 1550.002ns]
+    reset();  // [time: 1550.002ns -> 1560.002ns]
+    reset();  // [time: 1560.002ns -> 1570.002ns]
+    write(15, 67108864, 409090773, 0);  // [time: 1610.002ns -> 1630.002ns]
+    write(15, 67108865, 1348706589, 0);  // [time: 1630.002ns -> 1640.002ns]
+    write(15, 67108866, 1967918440, 0);  // [time: 1640.002ns -> 1650.002ns]
+    write(15, 67108867, 2636141882, 0);  // [time: 1650.002ns -> 1660.002ns]
+    write(15, 67108868, 533777194, 0);  // [time: 1660.002ns -> 1670.002ns]
+    write(15, 67108869, 2114809607, 0);  // [time: 1670.002ns -> 1680.002ns]
+    write(15, 67108870, 309856382, 0);  // [time: 1680.002ns -> 1690.002ns]
+    write(15, 67108871, 3466848916, 0);  // [time: 1690.002ns -> 1700.002ns]
+    write(15, 67108872, 3043756153, 0);  // [time: 1700.002ns -> 1710.002ns]
+    write(15, 67108873, 2927281001, 0);  // [time: 1710.002ns -> 1720.002ns]
+    write(15, 67108874, 1913699666, 0);  // [time: 1720.002ns -> 1730.002ns]
+    write(15, 67108875, 1847871828, 0);  // [time: 1730.002ns -> 1740.002ns]
+    write(15, 67108876, 3984372107, 0);  // [time: 1740.002ns -> 1750.002ns]
+    write(15, 67108877, 4239907193, 0);  // [time: 1750.002ns -> 1760.002ns]
+    write(15, 67108878, 1427511912, 0);  // [time: 1760.002ns -> 1770.002ns]
+    write(15, 67108879, 277973300, 0);  // [time: 1770.002ns -> 1780.002ns]
+    read(15, 67108864, 409090773, 0);  // [time: 1780.002ns -> 1800.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_12_0.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_12_0.bi.expect
new file mode 100644
index 00000000..abbf3eb6
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_12_0.bi.expect
@@ -0,0 +1,61 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108867, 1833423740, 0);  // [time: 410ns -> 430ns]
+    read(15, 67108868, 4073618608, 0);  // [time: 430ns -> 440ns]
+    read(15, 67108869, 3418745219, 0);  // [time: 440ns -> 450ns]
+    read(15, 67108870, 3757272308, 0);  // [time: 450ns -> 460ns]
+    read(15, 67108871, 1325530178, 0);  // [time: 460ns -> 470ns]
+    read(15, 67108872, 1451722922, 0);  // [time: 470ns -> 480ns]
+    read(15, 67108873, 1997677454, 0);  // [time: 480ns -> 490ns]
+    read(15, 67108874, 986005841, 0);  // [time: 490ns -> 500ns]
+    read(15, 67108875, 789975088, 0);  // [time: 500ns -> 510ns]
+    read(15, 67108876, 3746918692, 0);  // [time: 510ns -> 520ns]
+    read(15, 67108877, 410224063, 0);  // [time: 520ns -> 530ns]
+    read(15, 67108878, 864118294, 0);  // [time: 530ns -> 540ns]
+    read(15, 67108879, 908783806, 0);  // [time: 540ns -> 550ns]
+    read(15, 67108880, 2735695332, 0);  // [time: 550ns -> 560ns]
+    read(15, 67108881, 3991830963, 0);  // [time: 560ns -> 570ns]
+    read(15, 67108882, 3613974492, 0);  // [time: 570ns -> 580ns]
+    reset();  // [time: 620.001ns -> 630.001ns]
+    reset();  // [time: 630.001ns -> 640.001ns]
+    reset();  // [time: 640.001ns -> 650.001ns]
+    write(15, 67108867, 1515921225, 0);  // [time: 690.001ns -> 710.001ns]
+    write(15, 67108868, 104974629, 0);  // [time: 710.001ns -> 720.001ns]
+    write(15, 67108869, 966302149, 0);  // [time: 720.001ns -> 730.001ns]
+    write(15, 67108870, 4157870389, 0);  // [time: 730.001ns -> 740.001ns]
+    write(15, 67108871, 2924407148, 0);  // [time: 740.001ns -> 750.001ns]
+    write(15, 67108872, 1538378206, 0);  // [time: 750.001ns -> 760.001ns]
+    write(15, 67108873, 60846013, 0);  // [time: 760.001ns -> 770.001ns]
+    write(15, 67108874, 3809194079, 0);  // [time: 770.001ns -> 780.001ns]
+    write(15, 67108875, 4127502511, 0);  // [time: 780.001ns -> 790.001ns]
+    write(15, 67108876, 4180959758, 0);  // [time: 790.001ns -> 800.001ns]
+    write(15, 67108877, 700566626, 0);  // [time: 800.001ns -> 810.001ns]
+    write(15, 67108878, 2700144653, 0);  // [time: 810.001ns -> 820.001ns]
+    write(15, 67108879, 3999062826, 0);  // [time: 820.001ns -> 830.001ns]
+    write(15, 67108880, 3986108609, 0);  // [time: 830.001ns -> 840.001ns]
+    write(15, 67108881, 447162407, 0);  // [time: 840.001ns -> 850.001ns]
+    write(15, 67108882, 3816483315, 0);  // [time: 850.001ns -> 860.001ns]
+    reset();  // [time: 1540.002ns -> 1550.002ns]
+    reset();  // [time: 1550.002ns -> 1560.002ns]
+    reset();  // [time: 1560.002ns -> 1570.002ns]
+    write(15, 67108867, 1264302217, 0);  // [time: 1610.002ns -> 1630.002ns]
+    write(15, 67108868, 420700447, 0);  // [time: 1630.002ns -> 1640.002ns]
+    write(15, 67108869, 353328025, 0);  // [time: 1640.002ns -> 1650.002ns]
+    write(15, 67108870, 2517418204, 0);  // [time: 1650.002ns -> 1660.002ns]
+    write(15, 67108871, 1410989455, 0);  // [time: 1660.002ns -> 1670.002ns]
+    write(15, 67108872, 2070630692, 0);  // [time: 1670.002ns -> 1680.002ns]
+    write(15, 67108873, 1509701018, 0);  // [time: 1680.002ns -> 1690.002ns]
+    write(15, 67108874, 2805925831, 0);  // [time: 1690.002ns -> 1700.002ns]
+    write(15, 67108875, 1828261736, 0);  // [time: 1700.002ns -> 1710.002ns]
+    write(15, 67108876, 865271992, 0);  // [time: 1710.002ns -> 1720.002ns]
+    write(15, 67108877, 3589189654, 0);  // [time: 1720.002ns -> 1730.002ns]
+    write(15, 67108878, 2111939367, 0);  // [time: 1730.002ns -> 1740.002ns]
+    write(15, 67108879, 4179134294, 0);  // [time: 1740.002ns -> 1750.002ns]
+    write(15, 67108880, 1634099931, 0);  // [time: 1750.002ns -> 1760.002ns]
+    write(15, 67108881, 4072299277, 0);  // [time: 1760.002ns -> 1770.002ns]
+    write(15, 67108882, 1017567246, 0);  // [time: 1770.002ns -> 1780.002ns]
+    read(15, 67108867, 1264302217, 0);  // [time: 1780.002ns -> 1800.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_12_1.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_12_1.bi.expect
new file mode 100644
index 00000000..e1164b5a
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_12_1.bi.expect
@@ -0,0 +1,61 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108867, 3580256271, 0);  // [time: 410ns -> 430ns]
+    read(15, 67108864, 1489666683, 0);  // [time: 430ns -> 440ns]
+    read(15, 67108865, 3677074643, 0);  // [time: 440ns -> 450ns]
+    read(15, 67108866, 1878953054, 0);  // [time: 450ns -> 460ns]
+    read(15, 67108871, 2965505115, 0);  // [time: 460ns -> 470ns]
+    read(15, 67108868, 3259566096, 0);  // [time: 470ns -> 480ns]
+    read(15, 67108869, 1262153110, 0);  // [time: 480ns -> 490ns]
+    read(15, 67108870, 2451703670, 0);  // [time: 490ns -> 500ns]
+    read(15, 67108875, 3104341711, 0);  // [time: 500ns -> 510ns]
+    read(15, 67108872, 964066815, 0);  // [time: 510ns -> 520ns]
+    read(15, 67108873, 3328791441, 0);  // [time: 520ns -> 530ns]
+    read(15, 67108874, 3489570824, 0);  // [time: 530ns -> 540ns]
+    read(15, 67108879, 4241788620, 0);  // [time: 540ns -> 550ns]
+    read(15, 67108876, 3583058104, 0);  // [time: 550ns -> 560ns]
+    read(15, 67108877, 1005667378, 0);  // [time: 560ns -> 570ns]
+    read(15, 67108878, 209419171, 0);  // [time: 570ns -> 580ns]
+    reset();  // [time: 620.001ns -> 630.001ns]
+    reset();  // [time: 630.001ns -> 640.001ns]
+    reset();  // [time: 640.001ns -> 650.001ns]
+    write(15, 67108867, 1000382631, 0);  // [time: 690.001ns -> 710.001ns]
+    write(15, 67108864, 1285425234, 0);  // [time: 710.001ns -> 720.001ns]
+    write(15, 67108865, 318606993, 0);  // [time: 720.001ns -> 730.001ns]
+    write(15, 67108866, 2625467664, 0);  // [time: 730.001ns -> 740.001ns]
+    write(15, 67108871, 229964357, 0);  // [time: 740.001ns -> 750.001ns]
+    write(15, 67108868, 3036014706, 0);  // [time: 750.001ns -> 760.001ns]
+    write(15, 67108869, 1528299378, 0);  // [time: 760.001ns -> 770.001ns]
+    write(15, 67108870, 2182965409, 0);  // [time: 770.001ns -> 780.001ns]
+    write(15, 67108875, 3673940705, 0);  // [time: 780.001ns -> 790.001ns]
+    write(15, 67108872, 2347881481, 0);  // [time: 790.001ns -> 800.001ns]
+    write(15, 67108873, 2145987888, 0);  // [time: 800.001ns -> 810.001ns]
+    write(15, 67108874, 2056885632, 0);  // [time: 810.001ns -> 820.001ns]
+    write(15, 67108879, 3873405704, 0);  // [time: 820.001ns -> 830.001ns]
+    write(15, 67108876, 188298896, 0);  // [time: 830.001ns -> 840.001ns]
+    write(15, 67108877, 3827439034, 0);  // [time: 840.001ns -> 850.001ns]
+    write(15, 67108878, 2726944699, 0);  // [time: 850.001ns -> 860.001ns]
+    reset();  // [time: 1540.002ns -> 1550.002ns]
+    reset();  // [time: 1550.002ns -> 1560.002ns]
+    reset();  // [time: 1560.002ns -> 1570.002ns]
+    write(15, 67108867, 3833002895, 0);  // [time: 1610.002ns -> 1630.002ns]
+    write(15, 67108864, 1414948600, 0);  // [time: 1630.002ns -> 1640.002ns]
+    write(15, 67108865, 1931556247, 0);  // [time: 1640.002ns -> 1650.002ns]
+    write(15, 67108866, 2036215835, 0);  // [time: 1650.002ns -> 1660.002ns]
+    write(15, 67108871, 2213185472, 0);  // [time: 1660.002ns -> 1670.002ns]
+    write(15, 67108868, 2227456846, 0);  // [time: 1670.002ns -> 1680.002ns]
+    write(15, 67108869, 2213473648, 0);  // [time: 1680.002ns -> 1690.002ns]
+    write(15, 67108870, 1116257432, 0);  // [time: 1690.002ns -> 1700.002ns]
+    write(15, 67108875, 609949692, 0);  // [time: 1700.002ns -> 1710.002ns]
+    write(15, 67108872, 493401018, 0);  // [time: 1710.002ns -> 1720.002ns]
+    write(15, 67108873, 1721387478, 0);  // [time: 1720.002ns -> 1730.002ns]
+    write(15, 67108874, 1431279294, 0);  // [time: 1730.002ns -> 1740.002ns]
+    write(15, 67108879, 716225428, 0);  // [time: 1740.002ns -> 1750.002ns]
+    write(15, 67108876, 2446670843, 0);  // [time: 1750.002ns -> 1760.002ns]
+    write(15, 67108877, 1494143953, 0);  // [time: 1760.002ns -> 1770.002ns]
+    write(15, 67108878, 1325582129, 0);  // [time: 1770.002ns -> 1780.002ns]
+    read(15, 67108867, 3833002895, 0);  // [time: 1780.002ns -> 1800.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_12_2.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_12_2.bi.expect
new file mode 100644
index 00000000..7fee1f29
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_12_2.bi.expect
@@ -0,0 +1,61 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108867, 3495738447, 0);  // [time: 410ns -> 430ns]
+    read(15, 67108868, 1478546475, 0);  // [time: 430ns -> 440ns]
+    read(15, 67108869, 2041778918, 0);  // [time: 440ns -> 450ns]
+    read(15, 67108870, 3032895213, 0);  // [time: 450ns -> 460ns]
+    read(15, 67108871, 2020268309, 0);  // [time: 460ns -> 470ns]
+    read(15, 67108864, 3122719830, 0);  // [time: 470ns -> 480ns]
+    read(15, 67108865, 3806053567, 0);  // [time: 480ns -> 490ns]
+    read(15, 67108866, 3858565026, 0);  // [time: 490ns -> 500ns]
+    read(15, 67108875, 880624971, 0);  // [time: 500ns -> 510ns]
+    read(15, 67108876, 2554056607, 0);  // [time: 510ns -> 520ns]
+    read(15, 67108877, 1441832696, 0);  // [time: 520ns -> 530ns]
+    read(15, 67108878, 479445740, 0);  // [time: 530ns -> 540ns]
+    read(15, 67108879, 2229265910, 0);  // [time: 540ns -> 550ns]
+    read(15, 67108872, 788973880, 0);  // [time: 550ns -> 560ns]
+    read(15, 67108873, 3880977277, 0);  // [time: 560ns -> 570ns]
+    read(15, 67108874, 4096708504, 0);  // [time: 570ns -> 580ns]
+    reset();  // [time: 620.001ns -> 630.001ns]
+    reset();  // [time: 630.001ns -> 640.001ns]
+    reset();  // [time: 640.001ns -> 650.001ns]
+    write(15, 67108867, 2427636421, 0);  // [time: 690.001ns -> 710.001ns]
+    write(15, 67108868, 3595099675, 0);  // [time: 710.001ns -> 720.001ns]
+    write(15, 67108869, 2668681316, 0);  // [time: 720.001ns -> 730.001ns]
+    write(15, 67108870, 1679837987, 0);  // [time: 730.001ns -> 740.001ns]
+    write(15, 67108871, 924732013, 0);  // [time: 740.001ns -> 750.001ns]
+    write(15, 67108864, 2192079403, 0);  // [time: 750.001ns -> 760.001ns]
+    write(15, 67108865, 2042051660, 0);  // [time: 760.001ns -> 770.001ns]
+    write(15, 67108866, 989927686, 0);  // [time: 770.001ns -> 780.001ns]
+    write(15, 67108875, 3067406900, 0);  // [time: 780.001ns -> 790.001ns]
+    write(15, 67108876, 1058215073, 0);  // [time: 790.001ns -> 800.001ns]
+    write(15, 67108877, 365012335, 0);  // [time: 800.001ns -> 810.001ns]
+    write(15, 67108878, 687295108, 0);  // [time: 810.001ns -> 820.001ns]
+    write(15, 67108879, 2829218573, 0);  // [time: 820.001ns -> 830.001ns]
+    write(15, 67108872, 1448409262, 0);  // [time: 830.001ns -> 840.001ns]
+    write(15, 67108873, 400594486, 0);  // [time: 840.001ns -> 850.001ns]
+    write(15, 67108874, 4177343116, 0);  // [time: 850.001ns -> 860.001ns]
+    reset();  // [time: 1540.002ns -> 1550.002ns]
+    reset();  // [time: 1550.002ns -> 1560.002ns]
+    reset();  // [time: 1560.002ns -> 1570.002ns]
+    write(15, 67108867, 2304668716, 0);  // [time: 1610.002ns -> 1630.002ns]
+    write(15, 67108868, 2610611482, 0);  // [time: 1630.002ns -> 1640.002ns]
+    write(15, 67108869, 1468153982, 0);  // [time: 1640.002ns -> 1650.002ns]
+    write(15, 67108870, 1169841342, 0);  // [time: 1650.002ns -> 1660.002ns]
+    write(15, 67108871, 27036823, 0);  // [time: 1660.002ns -> 1670.002ns]
+    write(15, 67108864, 73783758, 0);  // [time: 1670.002ns -> 1680.002ns]
+    write(15, 67108865, 1621524717, 0);  // [time: 1680.002ns -> 1690.002ns]
+    write(15, 67108866, 3905946412, 0);  // [time: 1690.002ns -> 1700.002ns]
+    write(15, 67108875, 1563100034, 0);  // [time: 1700.002ns -> 1710.002ns]
+    write(15, 67108876, 2069336907, 0);  // [time: 1710.002ns -> 1720.002ns]
+    write(15, 67108877, 583373053, 0);  // [time: 1720.002ns -> 1730.002ns]
+    write(15, 67108878, 3629920426, 0);  // [time: 1730.002ns -> 1740.002ns]
+    write(15, 67108879, 2146122704, 0);  // [time: 1740.002ns -> 1750.002ns]
+    write(15, 67108872, 2674258699, 0);  // [time: 1750.002ns -> 1760.002ns]
+    write(15, 67108873, 1361676606, 0);  // [time: 1760.002ns -> 1770.002ns]
+    write(15, 67108874, 2435452493, 0);  // [time: 1770.002ns -> 1780.002ns]
+    read(15, 67108867, 2304668716, 0);  // [time: 1780.002ns -> 1800.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_12_3.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_12_3.bi.expect
new file mode 100644
index 00000000..b68e5c47
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_12_3.bi.expect
@@ -0,0 +1,61 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108867, 2727164243, 0);  // [time: 410ns -> 430ns]
+    read(15, 67108868, 1384255697, 0);  // [time: 430ns -> 440ns]
+    read(15, 67108869, 4216231340, 0);  // [time: 440ns -> 450ns]
+    read(15, 67108870, 1661993927, 0);  // [time: 450ns -> 460ns]
+    read(15, 67108871, 159950269, 0);  // [time: 460ns -> 470ns]
+    read(15, 67108872, 893905490, 0);  // [time: 470ns -> 480ns]
+    read(15, 67108873, 1464841894, 0);  // [time: 480ns -> 490ns]
+    read(15, 67108874, 710545966, 0);  // [time: 490ns -> 500ns]
+    read(15, 67108875, 3482423916, 0);  // [time: 500ns -> 510ns]
+    read(15, 67108876, 4068629318, 0);  // [time: 510ns -> 520ns]
+    read(15, 67108877, 3266524719, 0);  // [time: 520ns -> 530ns]
+    read(15, 67108878, 1808083576, 0);  // [time: 530ns -> 540ns]
+    read(15, 67108879, 3562161795, 0);  // [time: 540ns -> 550ns]
+    read(15, 67108864, 2984675510, 0);  // [time: 550ns -> 560ns]
+    read(15, 67108865, 2475539812, 0);  // [time: 560ns -> 570ns]
+    read(15, 67108866, 2138191023, 0);  // [time: 570ns -> 580ns]
+    reset();  // [time: 620.001ns -> 630.001ns]
+    reset();  // [time: 630.001ns -> 640.001ns]
+    reset();  // [time: 640.001ns -> 650.001ns]
+    write(15, 67108867, 1599974119, 0);  // [time: 690.001ns -> 710.001ns]
+    write(15, 67108868, 609858284, 0);  // [time: 710.001ns -> 720.001ns]
+    write(15, 67108869, 1648881400, 0);  // [time: 720.001ns -> 730.001ns]
+    write(15, 67108870, 572149112, 0);  // [time: 730.001ns -> 740.001ns]
+    write(15, 67108871, 602124761, 0);  // [time: 740.001ns -> 750.001ns]
+    write(15, 67108872, 3299652692, 0);  // [time: 750.001ns -> 760.001ns]
+    write(15, 67108873, 1416165996, 0);  // [time: 760.001ns -> 770.001ns]
+    write(15, 67108874, 1639735531, 0);  // [time: 770.001ns -> 780.001ns]
+    write(15, 67108875, 941900856, 0);  // [time: 780.001ns -> 790.001ns]
+    write(15, 67108876, 4103564658, 0);  // [time: 790.001ns -> 800.001ns]
+    write(15, 67108877, 788749736, 0);  // [time: 800.001ns -> 810.001ns]
+    write(15, 67108878, 1260615071, 0);  // [time: 810.001ns -> 820.001ns]
+    write(15, 67108879, 2210117974, 0);  // [time: 820.001ns -> 830.001ns]
+    write(15, 67108864, 2952803435, 0);  // [time: 830.001ns -> 840.001ns]
+    write(15, 67108865, 441673600, 0);  // [time: 840.001ns -> 850.001ns]
+    write(15, 67108866, 2137709866, 0);  // [time: 850.001ns -> 860.001ns]
+    reset();  // [time: 1540.002ns -> 1550.002ns]
+    reset();  // [time: 1550.002ns -> 1560.002ns]
+    reset();  // [time: 1560.002ns -> 1570.002ns]
+    write(15, 67108867, 2898868374, 0);  // [time: 1610.002ns -> 1630.002ns]
+    write(15, 67108868, 1922764675, 0);  // [time: 1630.002ns -> 1640.002ns]
+    write(15, 67108869, 4256406750, 0);  // [time: 1640.002ns -> 1650.002ns]
+    write(15, 67108870, 245447329, 0);  // [time: 1650.002ns -> 1660.002ns]
+    write(15, 67108871, 3225897750, 0);  // [time: 1660.002ns -> 1670.002ns]
+    write(15, 67108872, 1779082048, 0);  // [time: 1670.002ns -> 1680.002ns]
+    write(15, 67108873, 1953003128, 0);  // [time: 1680.002ns -> 1690.002ns]
+    write(15, 67108874, 4020445238, 0);  // [time: 1690.002ns -> 1700.002ns]
+    write(15, 67108875, 2174587331, 0);  // [time: 1700.002ns -> 1710.002ns]
+    write(15, 67108876, 1632125876, 0);  // [time: 1710.002ns -> 1720.002ns]
+    write(15, 67108877, 340410721, 0);  // [time: 1720.002ns -> 1730.002ns]
+    write(15, 67108878, 771941360, 0);  // [time: 1730.002ns -> 1740.002ns]
+    write(15, 67108879, 2567244845, 0);  // [time: 1740.002ns -> 1750.002ns]
+    write(15, 67108864, 899887853, 0);  // [time: 1750.002ns -> 1760.002ns]
+    write(15, 67108865, 1674678715, 0);  // [time: 1760.002ns -> 1770.002ns]
+    write(15, 67108866, 902429492, 0);  // [time: 1770.002ns -> 1780.002ns]
+    read(15, 67108867, 2898868374, 0);  // [time: 1780.002ns -> 1800.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_4_0.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_4_0.bi.expect
new file mode 100644
index 00000000..a60d8398
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_4_0.bi.expect
@@ -0,0 +1,61 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108865, 1016512136, 0);  // [time: 410ns -> 430ns]
+    read(15, 67108866, 226204128, 0);  // [time: 430ns -> 440ns]
+    read(15, 67108867, 2116565440, 0);  // [time: 440ns -> 450ns]
+    read(15, 67108868, 2153688786, 0);  // [time: 450ns -> 460ns]
+    read(15, 67108869, 1974223269, 0);  // [time: 460ns -> 470ns]
+    read(15, 67108870, 1053640572, 0);  // [time: 470ns -> 480ns]
+    read(15, 67108871, 2079860600, 0);  // [time: 480ns -> 490ns]
+    read(15, 67108872, 3550045624, 0);  // [time: 490ns -> 500ns]
+    read(15, 67108873, 1038322047, 0);  // [time: 500ns -> 510ns]
+    read(15, 67108874, 1502718053, 0);  // [time: 510ns -> 520ns]
+    read(15, 67108875, 1367070343, 0);  // [time: 520ns -> 530ns]
+    read(15, 67108876, 3425882885, 0);  // [time: 530ns -> 540ns]
+    read(15, 67108877, 1614916721, 0);  // [time: 540ns -> 550ns]
+    read(15, 67108878, 3041346437, 0);  // [time: 550ns -> 560ns]
+    read(15, 67108879, 3665993952, 0);  // [time: 560ns -> 570ns]
+    read(15, 67108880, 3560581876, 0);  // [time: 570ns -> 580ns]
+    reset();  // [time: 620.001ns -> 630.001ns]
+    reset();  // [time: 630.001ns -> 640.001ns]
+    reset();  // [time: 640.001ns -> 650.001ns]
+    write(15, 67108865, 3433786972, 0);  // [time: 690.001ns -> 710.001ns]
+    write(15, 67108866, 3840560806, 0);  // [time: 710.001ns -> 720.001ns]
+    write(15, 67108867, 3225552468, 0);  // [time: 720.001ns -> 730.001ns]
+    write(15, 67108868, 3717810263, 0);  // [time: 730.001ns -> 740.001ns]
+    write(15, 67108869, 3317657198, 0);  // [time: 740.001ns -> 750.001ns]
+    write(15, 67108870, 1024069544, 0);  // [time: 750.001ns -> 760.001ns]
+    write(15, 67108871, 1752245362, 0);  // [time: 760.001ns -> 770.001ns]
+    write(15, 67108872, 1579776374, 0);  // [time: 770.001ns -> 780.001ns]
+    write(15, 67108873, 904253205, 0);  // [time: 780.001ns -> 790.001ns]
+    write(15, 67108874, 1728285430, 0);  // [time: 790.001ns -> 800.001ns]
+    write(15, 67108875, 91066718, 0);  // [time: 800.001ns -> 810.001ns]
+    write(15, 67108876, 1402442819, 0);  // [time: 810.001ns -> 820.001ns]
+    write(15, 67108877, 4062122226, 0);  // [time: 820.001ns -> 830.001ns]
+    write(15, 67108878, 1191921998, 0);  // [time: 830.001ns -> 840.001ns]
+    write(15, 67108879, 1249541889, 0);  // [time: 840.001ns -> 850.001ns]
+    write(15, 67108880, 2580891116, 0);  // [time: 850.001ns -> 860.001ns]
+    reset();  // [time: 1540.002ns -> 1550.002ns]
+    reset();  // [time: 1550.002ns -> 1560.002ns]
+    reset();  // [time: 1560.002ns -> 1570.002ns]
+    write(15, 67108865, 1526706340, 0);  // [time: 1610.002ns -> 1630.002ns]
+    write(15, 67108866, 1162262173, 0);  // [time: 1630.002ns -> 1640.002ns]
+    write(15, 67108867, 3667501502, 0);  // [time: 1640.002ns -> 1650.002ns]
+    write(15, 67108868, 617255735, 0);  // [time: 1650.002ns -> 1660.002ns]
+    write(15, 67108869, 4077356414, 0);  // [time: 1660.002ns -> 1670.002ns]
+    write(15, 67108870, 1593609662, 0);  // [time: 1670.002ns -> 1680.002ns]
+    write(15, 67108871, 2148292499, 0);  // [time: 1680.002ns -> 1690.002ns]
+    write(15, 67108872, 3403556849, 0);  // [time: 1690.002ns -> 1700.002ns]
+    write(15, 67108873, 3331963440, 0);  // [time: 1700.002ns -> 1710.002ns]
+    write(15, 67108874, 1493302995, 0);  // [time: 1710.002ns -> 1720.002ns]
+    write(15, 67108875, 2710958922, 0);  // [time: 1720.002ns -> 1730.002ns]
+    write(15, 67108876, 4029972623, 0);  // [time: 1730.002ns -> 1740.002ns]
+    write(15, 67108877, 2845272388, 0);  // [time: 1740.002ns -> 1750.002ns]
+    write(15, 67108878, 70166840, 0);  // [time: 1750.002ns -> 1760.002ns]
+    write(15, 67108879, 1323291936, 0);  // [time: 1760.002ns -> 1770.002ns]
+    write(15, 67108880, 916783944, 0);  // [time: 1770.002ns -> 1780.002ns]
+    read(15, 67108865, 1526706340, 0);  // [time: 1780.002ns -> 1800.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_4_1.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_4_1.bi.expect
new file mode 100644
index 00000000..8662cb21
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_4_1.bi.expect
@@ -0,0 +1,61 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108865, 2821946881, 0);  // [time: 410ns -> 430ns]
+    read(15, 67108866, 4080087070, 0);  // [time: 430ns -> 440ns]
+    read(15, 67108867, 2243193877, 0);  // [time: 440ns -> 450ns]
+    read(15, 67108864, 2472849580, 0);  // [time: 450ns -> 460ns]
+    read(15, 67108869, 3565370026, 0);  // [time: 460ns -> 470ns]
+    read(15, 67108870, 890985600, 0);  // [time: 470ns -> 480ns]
+    read(15, 67108871, 4179549189, 0);  // [time: 480ns -> 490ns]
+    read(15, 67108868, 4158632492, 0);  // [time: 490ns -> 500ns]
+    read(15, 67108873, 3744957516, 0);  // [time: 500ns -> 510ns]
+    read(15, 67108874, 2300150418, 0);  // [time: 510ns -> 520ns]
+    read(15, 67108875, 2081940992, 0);  // [time: 520ns -> 530ns]
+    read(15, 67108872, 1697819148, 0);  // [time: 530ns -> 540ns]
+    read(15, 67108877, 602241333, 0);  // [time: 540ns -> 550ns]
+    read(15, 67108878, 2260552922, 0);  // [time: 550ns -> 560ns]
+    read(15, 67108879, 4251564751, 0);  // [time: 560ns -> 570ns]
+    read(15, 67108876, 3326548024, 0);  // [time: 570ns -> 580ns]
+    reset();  // [time: 620.001ns -> 630.001ns]
+    reset();  // [time: 630.001ns -> 640.001ns]
+    reset();  // [time: 640.001ns -> 650.001ns]
+    write(15, 67108865, 1044044861, 0);  // [time: 690.001ns -> 710.001ns]
+    write(15, 67108866, 4177314760, 0);  // [time: 710.001ns -> 720.001ns]
+    write(15, 67108867, 4253662683, 0);  // [time: 720.001ns -> 730.001ns]
+    write(15, 67108864, 3575602093, 0);  // [time: 730.001ns -> 740.001ns]
+    write(15, 67108869, 667576938, 0);  // [time: 740.001ns -> 750.001ns]
+    write(15, 67108870, 3110079964, 0);  // [time: 750.001ns -> 760.001ns]
+    write(15, 67108871, 3758039968, 0);  // [time: 760.001ns -> 770.001ns]
+    write(15, 67108868, 3566852678, 0);  // [time: 770.001ns -> 780.001ns]
+    write(15, 67108873, 3124984337, 0);  // [time: 780.001ns -> 790.001ns]
+    write(15, 67108874, 2124019892, 0);  // [time: 790.001ns -> 800.001ns]
+    write(15, 67108875, 4257151913, 0);  // [time: 800.001ns -> 810.001ns]
+    write(15, 67108872, 2010257240, 0);  // [time: 810.001ns -> 820.001ns]
+    write(15, 67108877, 236076834, 0);  // [time: 820.001ns -> 830.001ns]
+    write(15, 67108878, 1005361240, 0);  // [time: 830.001ns -> 840.001ns]
+    write(15, 67108879, 3482961596, 0);  // [time: 840.001ns -> 850.001ns]
+    write(15, 67108876, 416798935, 0);  // [time: 850.001ns -> 860.001ns]
+    reset();  // [time: 1540.002ns -> 1550.002ns]
+    reset();  // [time: 1550.002ns -> 1560.002ns]
+    reset();  // [time: 1560.002ns -> 1570.002ns]
+    write(15, 67108865, 5665644, 0);  // [time: 1610.002ns -> 1630.002ns]
+    write(15, 67108866, 2207028948, 0);  // [time: 1630.002ns -> 1640.002ns]
+    write(15, 67108867, 3039596975, 0);  // [time: 1640.002ns -> 1650.002ns]
+    write(15, 67108864, 2873077745, 0);  // [time: 1650.002ns -> 1660.002ns]
+    write(15, 67108869, 4156333102, 0);  // [time: 1660.002ns -> 1670.002ns]
+    write(15, 67108870, 2428683490, 0);  // [time: 1670.002ns -> 1680.002ns]
+    write(15, 67108871, 2474641325, 0);  // [time: 1680.002ns -> 1690.002ns]
+    write(15, 67108868, 2593936487, 0);  // [time: 1690.002ns -> 1700.002ns]
+    write(15, 67108873, 2521039073, 0);  // [time: 1700.002ns -> 1710.002ns]
+    write(15, 67108874, 3155595410, 0);  // [time: 1710.002ns -> 1720.002ns]
+    write(15, 67108875, 2665880696, 0);  // [time: 1720.002ns -> 1730.002ns]
+    write(15, 67108872, 1347764084, 0);  // [time: 1730.002ns -> 1740.002ns]
+    write(15, 67108877, 3198898103, 0);  // [time: 1740.002ns -> 1750.002ns]
+    write(15, 67108878, 1659773118, 0);  // [time: 1750.002ns -> 1760.002ns]
+    write(15, 67108879, 2296543553, 0);  // [time: 1760.002ns -> 1770.002ns]
+    write(15, 67108876, 1471659223, 0);  // [time: 1770.002ns -> 1780.002ns]
+    read(15, 67108865, 5665644, 0);  // [time: 1780.002ns -> 1800.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_4_2.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_4_2.bi.expect
new file mode 100644
index 00000000..c01c5814
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_4_2.bi.expect
@@ -0,0 +1,61 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108865, 3495738447, 0);  // [time: 410ns -> 430ns]
+    read(15, 67108866, 1478546475, 0);  // [time: 430ns -> 440ns]
+    read(15, 67108867, 2041778918, 0);  // [time: 440ns -> 450ns]
+    read(15, 67108868, 3032895213, 0);  // [time: 450ns -> 460ns]
+    read(15, 67108869, 2020268309, 0);  // [time: 460ns -> 470ns]
+    read(15, 67108870, 3122719830, 0);  // [time: 470ns -> 480ns]
+    read(15, 67108871, 3806053567, 0);  // [time: 480ns -> 490ns]
+    read(15, 67108864, 3858565026, 0);  // [time: 490ns -> 500ns]
+    read(15, 67108873, 880624971, 0);  // [time: 500ns -> 510ns]
+    read(15, 67108874, 2554056607, 0);  // [time: 510ns -> 520ns]
+    read(15, 67108875, 1441832696, 0);  // [time: 520ns -> 530ns]
+    read(15, 67108876, 479445740, 0);  // [time: 530ns -> 540ns]
+    read(15, 67108877, 2229265910, 0);  // [time: 540ns -> 550ns]
+    read(15, 67108878, 788973880, 0);  // [time: 550ns -> 560ns]
+    read(15, 67108879, 3880977277, 0);  // [time: 560ns -> 570ns]
+    read(15, 67108872, 4096708504, 0);  // [time: 570ns -> 580ns]
+    reset();  // [time: 620.001ns -> 630.001ns]
+    reset();  // [time: 630.001ns -> 640.001ns]
+    reset();  // [time: 640.001ns -> 650.001ns]
+    write(15, 67108865, 2427636421, 0);  // [time: 690.001ns -> 710.001ns]
+    write(15, 67108866, 3595099675, 0);  // [time: 710.001ns -> 720.001ns]
+    write(15, 67108867, 2668681316, 0);  // [time: 720.001ns -> 730.001ns]
+    write(15, 67108868, 1679837987, 0);  // [time: 730.001ns -> 740.001ns]
+    write(15, 67108869, 924732013, 0);  // [time: 740.001ns -> 750.001ns]
+    write(15, 67108870, 2192079403, 0);  // [time: 750.001ns -> 760.001ns]
+    write(15, 67108871, 2042051660, 0);  // [time: 760.001ns -> 770.001ns]
+    write(15, 67108864, 989927686, 0);  // [time: 770.001ns -> 780.001ns]
+    write(15, 67108873, 3067406900, 0);  // [time: 780.001ns -> 790.001ns]
+    write(15, 67108874, 1058215073, 0);  // [time: 790.001ns -> 800.001ns]
+    write(15, 67108875, 365012335, 0);  // [time: 800.001ns -> 810.001ns]
+    write(15, 67108876, 687295108, 0);  // [time: 810.001ns -> 820.001ns]
+    write(15, 67108877, 2829218573, 0);  // [time: 820.001ns -> 830.001ns]
+    write(15, 67108878, 1448409262, 0);  // [time: 830.001ns -> 840.001ns]
+    write(15, 67108879, 400594486, 0);  // [time: 840.001ns -> 850.001ns]
+    write(15, 67108872, 4177343116, 0);  // [time: 850.001ns -> 860.001ns]
+    reset();  // [time: 1540.002ns -> 1550.002ns]
+    reset();  // [time: 1550.002ns -> 1560.002ns]
+    reset();  // [time: 1560.002ns -> 1570.002ns]
+    write(15, 67108865, 2304668716, 0);  // [time: 1610.002ns -> 1630.002ns]
+    write(15, 67108866, 2610611482, 0);  // [time: 1630.002ns -> 1640.002ns]
+    write(15, 67108867, 1468153982, 0);  // [time: 1640.002ns -> 1650.002ns]
+    write(15, 67108868, 1169841342, 0);  // [time: 1650.002ns -> 1660.002ns]
+    write(15, 67108869, 27036823, 0);  // [time: 1660.002ns -> 1670.002ns]
+    write(15, 67108870, 73783758, 0);  // [time: 1670.002ns -> 1680.002ns]
+    write(15, 67108871, 1621524717, 0);  // [time: 1680.002ns -> 1690.002ns]
+    write(15, 67108864, 3905946412, 0);  // [time: 1690.002ns -> 1700.002ns]
+    write(15, 67108873, 1563100034, 0);  // [time: 1700.002ns -> 1710.002ns]
+    write(15, 67108874, 2069336907, 0);  // [time: 1710.002ns -> 1720.002ns]
+    write(15, 67108875, 583373053, 0);  // [time: 1720.002ns -> 1730.002ns]
+    write(15, 67108876, 3629920426, 0);  // [time: 1730.002ns -> 1740.002ns]
+    write(15, 67108877, 2146122704, 0);  // [time: 1740.002ns -> 1750.002ns]
+    write(15, 67108878, 2674258699, 0);  // [time: 1750.002ns -> 1760.002ns]
+    write(15, 67108879, 1361676606, 0);  // [time: 1760.002ns -> 1770.002ns]
+    write(15, 67108872, 2435452493, 0);  // [time: 1770.002ns -> 1780.002ns]
+    read(15, 67108865, 2304668716, 0);  // [time: 1780.002ns -> 1800.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_4_3.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_4_3.bi.expect
new file mode 100644
index 00000000..6190588c
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_4_3.bi.expect
@@ -0,0 +1,61 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108865, 1070372987, 0);  // [time: 410ns -> 430ns]
+    read(15, 67108866, 2645947069, 0);  // [time: 430ns -> 440ns]
+    read(15, 67108867, 736643984, 0);  // [time: 440ns -> 450ns]
+    read(15, 67108868, 192007203, 0);  // [time: 450ns -> 460ns]
+    read(15, 67108869, 1925400290, 0);  // [time: 460ns -> 470ns]
+    read(15, 67108870, 1309609983, 0);  // [time: 470ns -> 480ns]
+    read(15, 67108871, 58503546, 0);  // [time: 480ns -> 490ns]
+    read(15, 67108872, 3861022989, 0);  // [time: 490ns -> 500ns]
+    read(15, 67108873, 1725708128, 0);  // [time: 500ns -> 510ns]
+    read(15, 67108874, 3760744365, 0);  // [time: 510ns -> 520ns]
+    read(15, 67108875, 3803789590, 0);  // [time: 520ns -> 530ns]
+    read(15, 67108876, 2647121574, 0);  // [time: 530ns -> 540ns]
+    read(15, 67108877, 336117328, 0);  // [time: 540ns -> 550ns]
+    read(15, 67108878, 3984726565, 0);  // [time: 550ns -> 560ns]
+    read(15, 67108879, 104808193, 0);  // [time: 560ns -> 570ns]
+    read(15, 67108864, 2315494688, 0);  // [time: 570ns -> 580ns]
+    reset();  // [time: 620.001ns -> 630.001ns]
+    reset();  // [time: 630.001ns -> 640.001ns]
+    reset();  // [time: 640.001ns -> 650.001ns]
+    write(15, 67108865, 3997204021, 0);  // [time: 690.001ns -> 710.001ns]
+    write(15, 67108866, 666660673, 0);  // [time: 710.001ns -> 720.001ns]
+    write(15, 67108867, 3910223084, 0);  // [time: 720.001ns -> 730.001ns]
+    write(15, 67108868, 1271405124, 0);  // [time: 730.001ns -> 740.001ns]
+    write(15, 67108869, 4236388983, 0);  // [time: 740.001ns -> 750.001ns]
+    write(15, 67108870, 1347016890, 0);  // [time: 750.001ns -> 760.001ns]
+    write(15, 67108871, 1337396640, 0);  // [time: 760.001ns -> 770.001ns]
+    write(15, 67108872, 3009712000, 0);  // [time: 770.001ns -> 780.001ns]
+    write(15, 67108873, 2237248361, 0);  // [time: 780.001ns -> 790.001ns]
+    write(15, 67108874, 592560133, 0);  // [time: 790.001ns -> 800.001ns]
+    write(15, 67108875, 371018497, 0);  // [time: 800.001ns -> 810.001ns]
+    write(15, 67108876, 763875626, 0);  // [time: 810.001ns -> 820.001ns]
+    write(15, 67108877, 75174504, 0);  // [time: 820.001ns -> 830.001ns]
+    write(15, 67108878, 2983449782, 0);  // [time: 830.001ns -> 840.001ns]
+    write(15, 67108879, 2295155532, 0);  // [time: 840.001ns -> 850.001ns]
+    write(15, 67108864, 1954643484, 0);  // [time: 850.001ns -> 860.001ns]
+    reset();  // [time: 1540.002ns -> 1550.002ns]
+    reset();  // [time: 1550.002ns -> 1560.002ns]
+    reset();  // [time: 1560.002ns -> 1570.002ns]
+    write(15, 67108865, 409090773, 0);  // [time: 1610.002ns -> 1630.002ns]
+    write(15, 67108866, 1348706589, 0);  // [time: 1630.002ns -> 1640.002ns]
+    write(15, 67108867, 1967918440, 0);  // [time: 1640.002ns -> 1650.002ns]
+    write(15, 67108868, 2636141882, 0);  // [time: 1650.002ns -> 1660.002ns]
+    write(15, 67108869, 533777194, 0);  // [time: 1660.002ns -> 1670.002ns]
+    write(15, 67108870, 2114809607, 0);  // [time: 1670.002ns -> 1680.002ns]
+    write(15, 67108871, 309856382, 0);  // [time: 1680.002ns -> 1690.002ns]
+    write(15, 67108872, 3466848916, 0);  // [time: 1690.002ns -> 1700.002ns]
+    write(15, 67108873, 3043756153, 0);  // [time: 1700.002ns -> 1710.002ns]
+    write(15, 67108874, 2927281001, 0);  // [time: 1710.002ns -> 1720.002ns]
+    write(15, 67108875, 1913699666, 0);  // [time: 1720.002ns -> 1730.002ns]
+    write(15, 67108876, 1847871828, 0);  // [time: 1730.002ns -> 1740.002ns]
+    write(15, 67108877, 3984372107, 0);  // [time: 1740.002ns -> 1750.002ns]
+    write(15, 67108878, 4239907193, 0);  // [time: 1750.002ns -> 1760.002ns]
+    write(15, 67108879, 1427511912, 0);  // [time: 1760.002ns -> 1770.002ns]
+    write(15, 67108864, 277973300, 0);  // [time: 1770.002ns -> 1780.002ns]
+    read(15, 67108865, 409090773, 0);  // [time: 1780.002ns -> 1800.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_8_0.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_8_0.bi.expect
new file mode 100644
index 00000000..a37855f8
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_8_0.bi.expect
@@ -0,0 +1,61 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108866, 2205995893, 0);  // [time: 410ns -> 430ns]
+    read(15, 67108867, 486560095, 0);  // [time: 430ns -> 440ns]
+    read(15, 67108868, 4100133660, 0);  // [time: 440ns -> 450ns]
+    read(15, 67108869, 596618694, 0);  // [time: 450ns -> 460ns]
+    read(15, 67108870, 3499942130, 0);  // [time: 460ns -> 470ns]
+    read(15, 67108871, 2357711907, 0);  // [time: 470ns -> 480ns]
+    read(15, 67108872, 2086526797, 0);  // [time: 480ns -> 490ns]
+    read(15, 67108873, 364077448, 0);  // [time: 490ns -> 500ns]
+    read(15, 67108874, 210674739, 0);  // [time: 500ns -> 510ns]
+    read(15, 67108875, 1567286535, 0);  // [time: 510ns -> 520ns]
+    read(15, 67108876, 922799025, 0);  // [time: 520ns -> 530ns]
+    read(15, 67108877, 4171757579, 0);  // [time: 530ns -> 540ns]
+    read(15, 67108878, 740193371, 0);  // [time: 540ns -> 550ns]
+    read(15, 67108879, 872570658, 0);  // [time: 550ns -> 560ns]
+    read(15, 67108880, 608559447, 0);  // [time: 560ns -> 570ns]
+    read(15, 67108881, 1049762371, 0);  // [time: 570ns -> 580ns]
+    reset();  // [time: 620.001ns -> 630.001ns]
+    reset();  // [time: 630.001ns -> 640.001ns]
+    reset();  // [time: 640.001ns -> 650.001ns]
+    write(15, 67108866, 61321282, 0);  // [time: 690.001ns -> 710.001ns]
+    write(15, 67108867, 3113679544, 0);  // [time: 710.001ns -> 720.001ns]
+    write(15, 67108868, 2723657215, 0);  // [time: 720.001ns -> 730.001ns]
+    write(15, 67108869, 3578979173, 0);  // [time: 730.001ns -> 740.001ns]
+    write(15, 67108870, 1844094072, 0);  // [time: 740.001ns -> 750.001ns]
+    write(15, 67108871, 985922533, 0);  // [time: 750.001ns -> 760.001ns]
+    write(15, 67108872, 772047228, 0);  // [time: 760.001ns -> 770.001ns]
+    write(15, 67108873, 2786594234, 0);  // [time: 770.001ns -> 780.001ns]
+    write(15, 67108874, 3174400206, 0);  // [time: 780.001ns -> 790.001ns]
+    write(15, 67108875, 4087288639, 0);  // [time: 790.001ns -> 800.001ns]
+    write(15, 67108876, 1255295898, 0);  // [time: 800.001ns -> 810.001ns]
+    write(15, 67108877, 1278490992, 0);  // [time: 810.001ns -> 820.001ns]
+    write(15, 67108878, 3471724536, 0);  // [time: 820.001ns -> 830.001ns]
+    write(15, 67108879, 382544438, 0);  // [time: 830.001ns -> 840.001ns]
+    write(15, 67108880, 457743574, 0);  // [time: 840.001ns -> 850.001ns]
+    write(15, 67108881, 2419868428, 0);  // [time: 850.001ns -> 860.001ns]
+    reset();  // [time: 1540.002ns -> 1550.002ns]
+    reset();  // [time: 1550.002ns -> 1560.002ns]
+    reset();  // [time: 1560.002ns -> 1570.002ns]
+    write(15, 67108866, 3159959397, 0);  // [time: 1610.002ns -> 1630.002ns]
+    write(15, 67108867, 2987258927, 0);  // [time: 1630.002ns -> 1640.002ns]
+    write(15, 67108868, 3076374300, 0);  // [time: 1640.002ns -> 1650.002ns]
+    write(15, 67108869, 2145515966, 0);  // [time: 1650.002ns -> 1660.002ns]
+    write(15, 67108870, 363069260, 0);  // [time: 1660.002ns -> 1670.002ns]
+    write(15, 67108871, 1291413511, 0);  // [time: 1670.002ns -> 1680.002ns]
+    write(15, 67108872, 3582649965, 0);  // [time: 1680.002ns -> 1690.002ns]
+    write(15, 67108873, 2885357400, 0);  // [time: 1690.002ns -> 1700.002ns]
+    write(15, 67108874, 1499869988, 0);  // [time: 1700.002ns -> 1710.002ns]
+    write(15, 67108875, 2213787236, 0);  // [time: 1710.002ns -> 1720.002ns]
+    write(15, 67108876, 1663586395, 0);  // [time: 1720.002ns -> 1730.002ns]
+    write(15, 67108877, 680862039, 0);  // [time: 1730.002ns -> 1740.002ns]
+    write(15, 67108878, 4246962232, 0);  // [time: 1740.002ns -> 1750.002ns]
+    write(15, 67108879, 2414397419, 0);  // [time: 1750.002ns -> 1760.002ns]
+    write(15, 67108880, 2179858695, 0);  // [time: 1760.002ns -> 1770.002ns]
+    write(15, 67108881, 3059261273, 0);  // [time: 1770.002ns -> 1780.002ns]
+    read(15, 67108866, 3159959397, 0);  // [time: 1780.002ns -> 1800.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_8_1.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_8_1.bi.expect
new file mode 100644
index 00000000..2ae4e75f
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_8_1.bi.expect
@@ -0,0 +1,61 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108866, 2821946881, 0);  // [time: 410ns -> 430ns]
+    read(15, 67108867, 4080087070, 0);  // [time: 430ns -> 440ns]
+    read(15, 67108864, 2243193877, 0);  // [time: 440ns -> 450ns]
+    read(15, 67108865, 2472849580, 0);  // [time: 450ns -> 460ns]
+    read(15, 67108870, 3565370026, 0);  // [time: 460ns -> 470ns]
+    read(15, 67108871, 890985600, 0);  // [time: 470ns -> 480ns]
+    read(15, 67108868, 4179549189, 0);  // [time: 480ns -> 490ns]
+    read(15, 67108869, 4158632492, 0);  // [time: 490ns -> 500ns]
+    read(15, 67108874, 3744957516, 0);  // [time: 500ns -> 510ns]
+    read(15, 67108875, 2300150418, 0);  // [time: 510ns -> 520ns]
+    read(15, 67108872, 2081940992, 0);  // [time: 520ns -> 530ns]
+    read(15, 67108873, 1697819148, 0);  // [time: 530ns -> 540ns]
+    read(15, 67108878, 602241333, 0);  // [time: 540ns -> 550ns]
+    read(15, 67108879, 2260552922, 0);  // [time: 550ns -> 560ns]
+    read(15, 67108876, 4251564751, 0);  // [time: 560ns -> 570ns]
+    read(15, 67108877, 3326548024, 0);  // [time: 570ns -> 580ns]
+    reset();  // [time: 620.001ns -> 630.001ns]
+    reset();  // [time: 630.001ns -> 640.001ns]
+    reset();  // [time: 640.001ns -> 650.001ns]
+    write(15, 67108866, 1044044861, 0);  // [time: 690.001ns -> 710.001ns]
+    write(15, 67108867, 4177314760, 0);  // [time: 710.001ns -> 720.001ns]
+    write(15, 67108864, 4253662683, 0);  // [time: 720.001ns -> 730.001ns]
+    write(15, 67108865, 3575602093, 0);  // [time: 730.001ns -> 740.001ns]
+    write(15, 67108870, 667576938, 0);  // [time: 740.001ns -> 750.001ns]
+    write(15, 67108871, 3110079964, 0);  // [time: 750.001ns -> 760.001ns]
+    write(15, 67108868, 3758039968, 0);  // [time: 760.001ns -> 770.001ns]
+    write(15, 67108869, 3566852678, 0);  // [time: 770.001ns -> 780.001ns]
+    write(15, 67108874, 3124984337, 0);  // [time: 780.001ns -> 790.001ns]
+    write(15, 67108875, 2124019892, 0);  // [time: 790.001ns -> 800.001ns]
+    write(15, 67108872, 4257151913, 0);  // [time: 800.001ns -> 810.001ns]
+    write(15, 67108873, 2010257240, 0);  // [time: 810.001ns -> 820.001ns]
+    write(15, 67108878, 236076834, 0);  // [time: 820.001ns -> 830.001ns]
+    write(15, 67108879, 1005361240, 0);  // [time: 830.001ns -> 840.001ns]
+    write(15, 67108876, 3482961596, 0);  // [time: 840.001ns -> 850.001ns]
+    write(15, 67108877, 416798935, 0);  // [time: 850.001ns -> 860.001ns]
+    reset();  // [time: 1540.002ns -> 1550.002ns]
+    reset();  // [time: 1550.002ns -> 1560.002ns]
+    reset();  // [time: 1560.002ns -> 1570.002ns]
+    write(15, 67108866, 5665644, 0);  // [time: 1610.002ns -> 1630.002ns]
+    write(15, 67108867, 2207028948, 0);  // [time: 1630.002ns -> 1640.002ns]
+    write(15, 67108864, 3039596975, 0);  // [time: 1640.002ns -> 1650.002ns]
+    write(15, 67108865, 2873077745, 0);  // [time: 1650.002ns -> 1660.002ns]
+    write(15, 67108870, 4156333102, 0);  // [time: 1660.002ns -> 1670.002ns]
+    write(15, 67108871, 2428683490, 0);  // [time: 1670.002ns -> 1680.002ns]
+    write(15, 67108868, 2474641325, 0);  // [time: 1680.002ns -> 1690.002ns]
+    write(15, 67108869, 2593936487, 0);  // [time: 1690.002ns -> 1700.002ns]
+    write(15, 67108874, 2521039073, 0);  // [time: 1700.002ns -> 1710.002ns]
+    write(15, 67108875, 3155595410, 0);  // [time: 1710.002ns -> 1720.002ns]
+    write(15, 67108872, 2665880696, 0);  // [time: 1720.002ns -> 1730.002ns]
+    write(15, 67108873, 1347764084, 0);  // [time: 1730.002ns -> 1740.002ns]
+    write(15, 67108878, 3198898103, 0);  // [time: 1740.002ns -> 1750.002ns]
+    write(15, 67108879, 1659773118, 0);  // [time: 1750.002ns -> 1760.002ns]
+    write(15, 67108876, 2296543553, 0);  // [time: 1760.002ns -> 1770.002ns]
+    write(15, 67108877, 1471659223, 0);  // [time: 1770.002ns -> 1780.002ns]
+    read(15, 67108866, 5665644, 0);  // [time: 1780.002ns -> 1800.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_8_2.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_8_2.bi.expect
new file mode 100644
index 00000000..fb8baf9c
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_8_2.bi.expect
@@ -0,0 +1,61 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108866, 3495738447, 0);  // [time: 410ns -> 430ns]
+    read(15, 67108867, 1478546475, 0);  // [time: 430ns -> 440ns]
+    read(15, 67108868, 2041778918, 0);  // [time: 440ns -> 450ns]
+    read(15, 67108869, 3032895213, 0);  // [time: 450ns -> 460ns]
+    read(15, 67108870, 2020268309, 0);  // [time: 460ns -> 470ns]
+    read(15, 67108871, 3122719830, 0);  // [time: 470ns -> 480ns]
+    read(15, 67108864, 3806053567, 0);  // [time: 480ns -> 490ns]
+    read(15, 67108865, 3858565026, 0);  // [time: 490ns -> 500ns]
+    read(15, 67108874, 880624971, 0);  // [time: 500ns -> 510ns]
+    read(15, 67108875, 2554056607, 0);  // [time: 510ns -> 520ns]
+    read(15, 67108876, 1441832696, 0);  // [time: 520ns -> 530ns]
+    read(15, 67108877, 479445740, 0);  // [time: 530ns -> 540ns]
+    read(15, 67108878, 2229265910, 0);  // [time: 540ns -> 550ns]
+    read(15, 67108879, 788973880, 0);  // [time: 550ns -> 560ns]
+    read(15, 67108872, 3880977277, 0);  // [time: 560ns -> 570ns]
+    read(15, 67108873, 4096708504, 0);  // [time: 570ns -> 580ns]
+    reset();  // [time: 620.001ns -> 630.001ns]
+    reset();  // [time: 630.001ns -> 640.001ns]
+    reset();  // [time: 640.001ns -> 650.001ns]
+    write(15, 67108866, 2427636421, 0);  // [time: 690.001ns -> 710.001ns]
+    write(15, 67108867, 3595099675, 0);  // [time: 710.001ns -> 720.001ns]
+    write(15, 67108868, 2668681316, 0);  // [time: 720.001ns -> 730.001ns]
+    write(15, 67108869, 1679837987, 0);  // [time: 730.001ns -> 740.001ns]
+    write(15, 67108870, 924732013, 0);  // [time: 740.001ns -> 750.001ns]
+    write(15, 67108871, 2192079403, 0);  // [time: 750.001ns -> 760.001ns]
+    write(15, 67108864, 2042051660, 0);  // [time: 760.001ns -> 770.001ns]
+    write(15, 67108865, 989927686, 0);  // [time: 770.001ns -> 780.001ns]
+    write(15, 67108874, 3067406900, 0);  // [time: 780.001ns -> 790.001ns]
+    write(15, 67108875, 1058215073, 0);  // [time: 790.001ns -> 800.001ns]
+    write(15, 67108876, 365012335, 0);  // [time: 800.001ns -> 810.001ns]
+    write(15, 67108877, 687295108, 0);  // [time: 810.001ns -> 820.001ns]
+    write(15, 67108878, 2829218573, 0);  // [time: 820.001ns -> 830.001ns]
+    write(15, 67108879, 1448409262, 0);  // [time: 830.001ns -> 840.001ns]
+    write(15, 67108872, 400594486, 0);  // [time: 840.001ns -> 850.001ns]
+    write(15, 67108873, 4177343116, 0);  // [time: 850.001ns -> 860.001ns]
+    reset();  // [time: 1540.002ns -> 1550.002ns]
+    reset();  // [time: 1550.002ns -> 1560.002ns]
+    reset();  // [time: 1560.002ns -> 1570.002ns]
+    write(15, 67108866, 2304668716, 0);  // [time: 1610.002ns -> 1630.002ns]
+    write(15, 67108867, 2610611482, 0);  // [time: 1630.002ns -> 1640.002ns]
+    write(15, 67108868, 1468153982, 0);  // [time: 1640.002ns -> 1650.002ns]
+    write(15, 67108869, 1169841342, 0);  // [time: 1650.002ns -> 1660.002ns]
+    write(15, 67108870, 27036823, 0);  // [time: 1660.002ns -> 1670.002ns]
+    write(15, 67108871, 73783758, 0);  // [time: 1670.002ns -> 1680.002ns]
+    write(15, 67108864, 1621524717, 0);  // [time: 1680.002ns -> 1690.002ns]
+    write(15, 67108865, 3905946412, 0);  // [time: 1690.002ns -> 1700.002ns]
+    write(15, 67108874, 1563100034, 0);  // [time: 1700.002ns -> 1710.002ns]
+    write(15, 67108875, 2069336907, 0);  // [time: 1710.002ns -> 1720.002ns]
+    write(15, 67108876, 583373053, 0);  // [time: 1720.002ns -> 1730.002ns]
+    write(15, 67108877, 3629920426, 0);  // [time: 1730.002ns -> 1740.002ns]
+    write(15, 67108878, 2146122704, 0);  // [time: 1740.002ns -> 1750.002ns]
+    write(15, 67108879, 2674258699, 0);  // [time: 1750.002ns -> 1760.002ns]
+    write(15, 67108872, 1361676606, 0);  // [time: 1760.002ns -> 1770.002ns]
+    write(15, 67108873, 2435452493, 0);  // [time: 1770.002ns -> 1780.002ns]
+    read(15, 67108866, 2304668716, 0);  // [time: 1780.002ns -> 1800.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_8_3.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_8_3.bi.expect
new file mode 100644
index 00000000..6e117e35
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_16_8_3.bi.expect
@@ -0,0 +1,61 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108866, 2727164243, 0);  // [time: 410ns -> 430ns]
+    read(15, 67108867, 1384255697, 0);  // [time: 430ns -> 440ns]
+    read(15, 67108868, 4216231340, 0);  // [time: 440ns -> 450ns]
+    read(15, 67108869, 1661993927, 0);  // [time: 450ns -> 460ns]
+    read(15, 67108870, 159950269, 0);  // [time: 460ns -> 470ns]
+    read(15, 67108871, 893905490, 0);  // [time: 470ns -> 480ns]
+    read(15, 67108872, 1464841894, 0);  // [time: 480ns -> 490ns]
+    read(15, 67108873, 710545966, 0);  // [time: 490ns -> 500ns]
+    read(15, 67108874, 3482423916, 0);  // [time: 500ns -> 510ns]
+    read(15, 67108875, 4068629318, 0);  // [time: 510ns -> 520ns]
+    read(15, 67108876, 3266524719, 0);  // [time: 520ns -> 530ns]
+    read(15, 67108877, 1808083576, 0);  // [time: 530ns -> 540ns]
+    read(15, 67108878, 3562161795, 0);  // [time: 540ns -> 550ns]
+    read(15, 67108879, 2984675510, 0);  // [time: 550ns -> 560ns]
+    read(15, 67108864, 2475539812, 0);  // [time: 560ns -> 570ns]
+    read(15, 67108865, 2138191023, 0);  // [time: 570ns -> 580ns]
+    reset();  // [time: 620.001ns -> 630.001ns]
+    reset();  // [time: 630.001ns -> 640.001ns]
+    reset();  // [time: 640.001ns -> 650.001ns]
+    write(15, 67108866, 1599974119, 0);  // [time: 690.001ns -> 710.001ns]
+    write(15, 67108867, 609858284, 0);  // [time: 710.001ns -> 720.001ns]
+    write(15, 67108868, 1648881400, 0);  // [time: 720.001ns -> 730.001ns]
+    write(15, 67108869, 572149112, 0);  // [time: 730.001ns -> 740.001ns]
+    write(15, 67108870, 602124761, 0);  // [time: 740.001ns -> 750.001ns]
+    write(15, 67108871, 3299652692, 0);  // [time: 750.001ns -> 760.001ns]
+    write(15, 67108872, 1416165996, 0);  // [time: 760.001ns -> 770.001ns]
+    write(15, 67108873, 1639735531, 0);  // [time: 770.001ns -> 780.001ns]
+    write(15, 67108874, 941900856, 0);  // [time: 780.001ns -> 790.001ns]
+    write(15, 67108875, 4103564658, 0);  // [time: 790.001ns -> 800.001ns]
+    write(15, 67108876, 788749736, 0);  // [time: 800.001ns -> 810.001ns]
+    write(15, 67108877, 1260615071, 0);  // [time: 810.001ns -> 820.001ns]
+    write(15, 67108878, 2210117974, 0);  // [time: 820.001ns -> 830.001ns]
+    write(15, 67108879, 2952803435, 0);  // [time: 830.001ns -> 840.001ns]
+    write(15, 67108864, 441673600, 0);  // [time: 840.001ns -> 850.001ns]
+    write(15, 67108865, 2137709866, 0);  // [time: 850.001ns -> 860.001ns]
+    reset();  // [time: 1540.002ns -> 1550.002ns]
+    reset();  // [time: 1550.002ns -> 1560.002ns]
+    reset();  // [time: 1560.002ns -> 1570.002ns]
+    write(15, 67108866, 2898868374, 0);  // [time: 1610.002ns -> 1630.002ns]
+    write(15, 67108867, 1922764675, 0);  // [time: 1630.002ns -> 1640.002ns]
+    write(15, 67108868, 4256406750, 0);  // [time: 1640.002ns -> 1650.002ns]
+    write(15, 67108869, 245447329, 0);  // [time: 1650.002ns -> 1660.002ns]
+    write(15, 67108870, 3225897750, 0);  // [time: 1660.002ns -> 1670.002ns]
+    write(15, 67108871, 1779082048, 0);  // [time: 1670.002ns -> 1680.002ns]
+    write(15, 67108872, 1953003128, 0);  // [time: 1680.002ns -> 1690.002ns]
+    write(15, 67108873, 4020445238, 0);  // [time: 1690.002ns -> 1700.002ns]
+    write(15, 67108874, 2174587331, 0);  // [time: 1700.002ns -> 1710.002ns]
+    write(15, 67108875, 1632125876, 0);  // [time: 1710.002ns -> 1720.002ns]
+    write(15, 67108876, 340410721, 0);  // [time: 1720.002ns -> 1730.002ns]
+    write(15, 67108877, 771941360, 0);  // [time: 1730.002ns -> 1740.002ns]
+    write(15, 67108878, 2567244845, 0);  // [time: 1740.002ns -> 1750.002ns]
+    write(15, 67108879, 899887853, 0);  // [time: 1750.002ns -> 1760.002ns]
+    write(15, 67108864, 1674678715, 0);  // [time: 1760.002ns -> 1770.002ns]
+    write(15, 67108865, 902429492, 0);  // [time: 1770.002ns -> 1780.002ns]
+    read(15, 67108866, 2898868374, 0);  // [time: 1780.002ns -> 1800.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_0_0.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_0_0.bi.expect
new file mode 100644
index 00000000..c3a38561
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_0_0.bi.expect
@@ -0,0 +1,16 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108864, 2205995893, 0);  // [time: 110ns -> 130ns]
+    reset();  // [time: 170.001ns -> 180.001ns]
+    reset();  // [time: 180.001ns -> 190.001ns]
+    reset();  // [time: 190.001ns -> 200.001ns]
+    write(15, 67108864, 486560095, 0);  // [time: 240.001ns -> 260.001ns]
+    reset();  // [time: 340.002ns -> 350.002ns]
+    reset();  // [time: 350.002ns -> 360.002ns]
+    reset();  // [time: 360.002ns -> 370.002ns]
+    write(15, 67108864, 4100133660, 0);  // [time: 410.002ns -> 430.002ns]
+    read(15, 67108864, 4100133660, 0);  // [time: 430.002ns -> 450.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_0_1.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_0_1.bi.expect
new file mode 100644
index 00000000..aebae401
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_0_1.bi.expect
@@ -0,0 +1,16 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108864, 518534189, 0);  // [time: 110ns -> 130ns]
+    reset();  // [time: 170.001ns -> 180.001ns]
+    reset();  // [time: 180.001ns -> 190.001ns]
+    reset();  // [time: 190.001ns -> 200.001ns]
+    write(15, 67108864, 844695266, 0);  // [time: 240.001ns -> 260.001ns]
+    reset();  // [time: 340.002ns -> 350.002ns]
+    reset();  // [time: 350.002ns -> 360.002ns]
+    reset();  // [time: 360.002ns -> 370.002ns]
+    write(15, 67108864, 3937184150, 0);  // [time: 410.002ns -> 430.002ns]
+    read(15, 67108864, 3937184150, 0);  // [time: 430.002ns -> 450.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_0_2.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_0_2.bi.expect
new file mode 100644
index 00000000..b01c57c0
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_0_2.bi.expect
@@ -0,0 +1,16 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108864, 3580256271, 0);  // [time: 110ns -> 130ns]
+    reset();  // [time: 170.001ns -> 180.001ns]
+    reset();  // [time: 180.001ns -> 190.001ns]
+    reset();  // [time: 190.001ns -> 200.001ns]
+    write(15, 67108864, 1489666683, 0);  // [time: 240.001ns -> 260.001ns]
+    reset();  // [time: 340.002ns -> 350.002ns]
+    reset();  // [time: 350.002ns -> 360.002ns]
+    reset();  // [time: 360.002ns -> 370.002ns]
+    write(15, 67108864, 3677074643, 0);  // [time: 410.002ns -> 430.002ns]
+    read(15, 67108864, 3677074643, 0);  // [time: 430.002ns -> 450.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_0_3.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_0_3.bi.expect
new file mode 100644
index 00000000..90e7d396
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_0_3.bi.expect
@@ -0,0 +1,16 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108864, 1509562552, 0);  // [time: 110ns -> 130ns]
+    reset();  // [time: 170.001ns -> 180.001ns]
+    reset();  // [time: 180.001ns -> 190.001ns]
+    reset();  // [time: 190.001ns -> 200.001ns]
+    write(15, 67108864, 2329347035, 0);  // [time: 240.001ns -> 260.001ns]
+    reset();  // [time: 340.002ns -> 350.002ns]
+    reset();  // [time: 350.002ns -> 360.002ns]
+    reset();  // [time: 360.002ns -> 370.002ns]
+    write(15, 67108864, 3862381389, 0);  // [time: 410.002ns -> 430.002ns]
+    read(15, 67108864, 3862381389, 0);  // [time: 430.002ns -> 450.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_12_0.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_12_0.bi.expect
new file mode 100644
index 00000000..f42edacc
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_12_0.bi.expect
@@ -0,0 +1,16 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108867, 3597917862, 0);  // [time: 110ns -> 130ns]
+    reset();  // [time: 170.001ns -> 180.001ns]
+    reset();  // [time: 180.001ns -> 190.001ns]
+    reset();  // [time: 190.001ns -> 200.001ns]
+    write(15, 67108867, 1298617733, 0);  // [time: 240.001ns -> 260.001ns]
+    reset();  // [time: 340.002ns -> 350.002ns]
+    reset();  // [time: 350.002ns -> 360.002ns]
+    reset();  // [time: 360.002ns -> 370.002ns]
+    write(15, 67108867, 2330861729, 0);  // [time: 410.002ns -> 430.002ns]
+    read(15, 67108867, 2330861729, 0);  // [time: 430.002ns -> 450.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_12_1.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_12_1.bi.expect
new file mode 100644
index 00000000..896dad1e
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_12_1.bi.expect
@@ -0,0 +1,16 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108867, 2821946881, 0);  // [time: 110ns -> 130ns]
+    reset();  // [time: 170.001ns -> 180.001ns]
+    reset();  // [time: 180.001ns -> 190.001ns]
+    reset();  // [time: 190.001ns -> 200.001ns]
+    write(15, 67108867, 4080087070, 0);  // [time: 240.001ns -> 260.001ns]
+    reset();  // [time: 340.002ns -> 350.002ns]
+    reset();  // [time: 350.002ns -> 360.002ns]
+    reset();  // [time: 360.002ns -> 370.002ns]
+    write(15, 67108867, 2243193877, 0);  // [time: 410.002ns -> 430.002ns]
+    read(15, 67108867, 2243193877, 0);  // [time: 430.002ns -> 450.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_12_2.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_12_2.bi.expect
new file mode 100644
index 00000000..247aef00
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_12_2.bi.expect
@@ -0,0 +1,16 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108867, 869832817, 0);  // [time: 110ns -> 130ns]
+    reset();  // [time: 170.001ns -> 180.001ns]
+    reset();  // [time: 180.001ns -> 190.001ns]
+    reset();  // [time: 190.001ns -> 200.001ns]
+    write(15, 67108867, 2976082601, 0);  // [time: 240.001ns -> 260.001ns]
+    reset();  // [time: 340.002ns -> 350.002ns]
+    reset();  // [time: 350.002ns -> 360.002ns]
+    reset();  // [time: 360.002ns -> 370.002ns]
+    write(15, 67108867, 373695501, 0);  // [time: 410.002ns -> 430.002ns]
+    read(15, 67108867, 373695501, 0);  // [time: 430.002ns -> 450.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_12_3.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_12_3.bi.expect
new file mode 100644
index 00000000..464cc88c
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_12_3.bi.expect
@@ -0,0 +1,16 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108867, 1509562552, 0);  // [time: 110ns -> 130ns]
+    reset();  // [time: 170.001ns -> 180.001ns]
+    reset();  // [time: 180.001ns -> 190.001ns]
+    reset();  // [time: 190.001ns -> 200.001ns]
+    write(15, 67108867, 2329347035, 0);  // [time: 240.001ns -> 260.001ns]
+    reset();  // [time: 340.002ns -> 350.002ns]
+    reset();  // [time: 350.002ns -> 360.002ns]
+    reset();  // [time: 360.002ns -> 370.002ns]
+    write(15, 67108867, 3862381389, 0);  // [time: 410.002ns -> 430.002ns]
+    read(15, 67108867, 3862381389, 0);  // [time: 430.002ns -> 450.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_4_0.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_4_0.bi.expect
new file mode 100644
index 00000000..2cd9a72f
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_4_0.bi.expect
@@ -0,0 +1,16 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108865, 1691632885, 0);  // [time: 110ns -> 130ns]
+    reset();  // [time: 170.001ns -> 180.001ns]
+    reset();  // [time: 180.001ns -> 190.001ns]
+    reset();  // [time: 190.001ns -> 200.001ns]
+    write(15, 67108865, 3547248670, 0);  // [time: 240.001ns -> 260.001ns]
+    reset();  // [time: 340.002ns -> 350.002ns]
+    reset();  // [time: 350.002ns -> 360.002ns]
+    reset();  // [time: 360.002ns -> 370.002ns]
+    write(15, 67108865, 665751263, 0);  // [time: 410.002ns -> 430.002ns]
+    read(15, 67108865, 665751263, 0);  // [time: 430.002ns -> 450.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_4_1.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_4_1.bi.expect
new file mode 100644
index 00000000..80edb357
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_4_1.bi.expect
@@ -0,0 +1,16 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108865, 518534189, 0);  // [time: 110ns -> 130ns]
+    reset();  // [time: 170.001ns -> 180.001ns]
+    reset();  // [time: 180.001ns -> 190.001ns]
+    reset();  // [time: 190.001ns -> 200.001ns]
+    write(15, 67108865, 844695266, 0);  // [time: 240.001ns -> 260.001ns]
+    reset();  // [time: 340.002ns -> 350.002ns]
+    reset();  // [time: 350.002ns -> 360.002ns]
+    reset();  // [time: 360.002ns -> 370.002ns]
+    write(15, 67108865, 3937184150, 0);  // [time: 410.002ns -> 430.002ns]
+    read(15, 67108865, 3937184150, 0);  // [time: 430.002ns -> 450.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_4_2.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_4_2.bi.expect
new file mode 100644
index 00000000..7cdb5ea7
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_4_2.bi.expect
@@ -0,0 +1,16 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108865, 1016512136, 0);  // [time: 110ns -> 130ns]
+    reset();  // [time: 170.001ns -> 180.001ns]
+    reset();  // [time: 180.001ns -> 190.001ns]
+    reset();  // [time: 190.001ns -> 200.001ns]
+    write(15, 67108865, 226204128, 0);  // [time: 240.001ns -> 260.001ns]
+    reset();  // [time: 340.002ns -> 350.002ns]
+    reset();  // [time: 350.002ns -> 360.002ns]
+    reset();  // [time: 360.002ns -> 370.002ns]
+    write(15, 67108865, 2116565440, 0);  // [time: 410.002ns -> 430.002ns]
+    read(15, 67108865, 2116565440, 0);  // [time: 430.002ns -> 450.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_4_3.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_4_3.bi.expect
new file mode 100644
index 00000000..67edd59f
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_4_3.bi.expect
@@ -0,0 +1,16 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108865, 3495738447, 0);  // [time: 110ns -> 130ns]
+    reset();  // [time: 170.001ns -> 180.001ns]
+    reset();  // [time: 180.001ns -> 190.001ns]
+    reset();  // [time: 190.001ns -> 200.001ns]
+    write(15, 67108865, 1478546475, 0);  // [time: 240.001ns -> 260.001ns]
+    reset();  // [time: 340.002ns -> 350.002ns]
+    reset();  // [time: 350.002ns -> 360.002ns]
+    reset();  // [time: 360.002ns -> 370.002ns]
+    write(15, 67108865, 2041778918, 0);  // [time: 410.002ns -> 430.002ns]
+    read(15, 67108865, 2041778918, 0);  // [time: 430.002ns -> 450.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_8_0.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_8_0.bi.expect
new file mode 100644
index 00000000..07c59046
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_8_0.bi.expect
@@ -0,0 +1,16 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108866, 1691632885, 0);  // [time: 110ns -> 130ns]
+    reset();  // [time: 170.001ns -> 180.001ns]
+    reset();  // [time: 180.001ns -> 190.001ns]
+    reset();  // [time: 190.001ns -> 200.001ns]
+    write(15, 67108866, 3547248670, 0);  // [time: 240.001ns -> 260.001ns]
+    reset();  // [time: 340.002ns -> 350.002ns]
+    reset();  // [time: 350.002ns -> 360.002ns]
+    reset();  // [time: 360.002ns -> 370.002ns]
+    write(15, 67108866, 665751263, 0);  // [time: 410.002ns -> 430.002ns]
+    read(15, 67108866, 665751263, 0);  // [time: 430.002ns -> 450.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_8_1.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_8_1.bi.expect
new file mode 100644
index 00000000..7414ac38
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_8_1.bi.expect
@@ -0,0 +1,16 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108866, 2821946881, 0);  // [time: 110ns -> 130ns]
+    reset();  // [time: 170.001ns -> 180.001ns]
+    reset();  // [time: 180.001ns -> 190.001ns]
+    reset();  // [time: 190.001ns -> 200.001ns]
+    write(15, 67108866, 4080087070, 0);  // [time: 240.001ns -> 260.001ns]
+    reset();  // [time: 340.002ns -> 350.002ns]
+    reset();  // [time: 350.002ns -> 360.002ns]
+    reset();  // [time: 360.002ns -> 370.002ns]
+    write(15, 67108866, 2243193877, 0);  // [time: 410.002ns -> 430.002ns]
+    read(15, 67108866, 2243193877, 0);  // [time: 430.002ns -> 450.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_8_2.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_8_2.bi.expect
new file mode 100644
index 00000000..020b204d
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_8_2.bi.expect
@@ -0,0 +1,16 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108866, 1016512136, 0);  // [time: 110ns -> 130ns]
+    reset();  // [time: 170.001ns -> 180.001ns]
+    reset();  // [time: 180.001ns -> 190.001ns]
+    reset();  // [time: 190.001ns -> 200.001ns]
+    write(15, 67108866, 226204128, 0);  // [time: 240.001ns -> 260.001ns]
+    reset();  // [time: 340.002ns -> 350.002ns]
+    reset();  // [time: 350.002ns -> 360.002ns]
+    reset();  // [time: 360.002ns -> 370.002ns]
+    write(15, 67108866, 2116565440, 0);  // [time: 410.002ns -> 430.002ns]
+    read(15, 67108866, 2116565440, 0);  // [time: 430.002ns -> 450.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_8_3.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_8_3.bi.expect
new file mode 100644
index 00000000..288751ac
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_1_8_3.bi.expect
@@ -0,0 +1,16 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108866, 3495738447, 0);  // [time: 110ns -> 130ns]
+    reset();  // [time: 170.001ns -> 180.001ns]
+    reset();  // [time: 180.001ns -> 190.001ns]
+    reset();  // [time: 190.001ns -> 200.001ns]
+    write(15, 67108866, 1478546475, 0);  // [time: 240.001ns -> 260.001ns]
+    reset();  // [time: 340.002ns -> 350.002ns]
+    reset();  // [time: 350.002ns -> 360.002ns]
+    reset();  // [time: 360.002ns -> 370.002ns]
+    write(15, 67108866, 2041778918, 0);  // [time: 410.002ns -> 430.002ns]
+    read(15, 67108866, 2041778918, 0);  // [time: 430.002ns -> 450.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_0_0.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_0_0.bi.expect
new file mode 100644
index 00000000..883ac1d5
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_0_0.bi.expect
@@ -0,0 +1,19 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108864, 3597917862, 0);  // [time: 130ns -> 150ns]
+    read(15, 67108865, 1298617733, 0);  // [time: 150ns -> 160ns]
+    reset();  // [time: 200.001ns -> 210.001ns]
+    reset();  // [time: 210.001ns -> 220.001ns]
+    reset();  // [time: 220.001ns -> 230.001ns]
+    write(15, 67108864, 2330861729, 0);  // [time: 270.001ns -> 290.001ns]
+    write(15, 67108865, 4289318346, 0);  // [time: 290.001ns -> 300.001ns]
+    reset();  // [time: 420.002ns -> 430.002ns]
+    reset();  // [time: 430.002ns -> 440.002ns]
+    reset();  // [time: 440.002ns -> 450.002ns]
+    write(15, 67108864, 2756621846, 0);  // [time: 490.002ns -> 510.002ns]
+    write(15, 67108865, 1627127952, 0);  // [time: 510.002ns -> 520.002ns]
+    read(15, 67108864, 2756621846, 0);  // [time: 520.002ns -> 540.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_0_1.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_0_1.bi.expect
new file mode 100644
index 00000000..52f2a7ab
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_0_1.bi.expect
@@ -0,0 +1,19 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108864, 3580256271, 0);  // [time: 130ns -> 150ns]
+    read(15, 67108865, 1489666683, 0);  // [time: 150ns -> 160ns]
+    reset();  // [time: 200.001ns -> 210.001ns]
+    reset();  // [time: 210.001ns -> 220.001ns]
+    reset();  // [time: 220.001ns -> 230.001ns]
+    write(15, 67108864, 3677074643, 0);  // [time: 270.001ns -> 290.001ns]
+    write(15, 67108865, 1878953054, 0);  // [time: 290.001ns -> 300.001ns]
+    reset();  // [time: 420.002ns -> 430.002ns]
+    reset();  // [time: 430.002ns -> 440.002ns]
+    reset();  // [time: 440.002ns -> 450.002ns]
+    write(15, 67108864, 2965505115, 0);  // [time: 490.002ns -> 510.002ns]
+    write(15, 67108865, 3259566096, 0);  // [time: 510.002ns -> 520.002ns]
+    read(15, 67108864, 2965505115, 0);  // [time: 520.002ns -> 540.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_0_2.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_0_2.bi.expect
new file mode 100644
index 00000000..c67de0c0
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_0_2.bi.expect
@@ -0,0 +1,19 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108864, 869832817, 0);  // [time: 130ns -> 150ns]
+    read(15, 67108865, 2976082601, 0);  // [time: 150ns -> 160ns]
+    reset();  // [time: 200.001ns -> 210.001ns]
+    reset();  // [time: 210.001ns -> 220.001ns]
+    reset();  // [time: 220.001ns -> 230.001ns]
+    write(15, 67108864, 373695501, 0);  // [time: 270.001ns -> 290.001ns]
+    write(15, 67108865, 2110838384, 0);  // [time: 290.001ns -> 300.001ns]
+    reset();  // [time: 420.002ns -> 430.002ns]
+    reset();  // [time: 430.002ns -> 440.002ns]
+    reset();  // [time: 440.002ns -> 450.002ns]
+    write(15, 67108864, 3556455435, 0);  // [time: 490.002ns -> 510.002ns]
+    write(15, 67108865, 1804567173, 0);  // [time: 510.002ns -> 520.002ns]
+    read(15, 67108864, 3556455435, 0);  // [time: 520.002ns -> 540.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_0_3.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_0_3.bi.expect
new file mode 100644
index 00000000..9948b2bc
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_0_3.bi.expect
@@ -0,0 +1,19 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108864, 3495738447, 0);  // [time: 130ns -> 150ns]
+    read(15, 67108865, 1478546475, 0);  // [time: 150ns -> 160ns]
+    reset();  // [time: 200.001ns -> 210.001ns]
+    reset();  // [time: 210.001ns -> 220.001ns]
+    reset();  // [time: 220.001ns -> 230.001ns]
+    write(15, 67108864, 2041778918, 0);  // [time: 270.001ns -> 290.001ns]
+    write(15, 67108865, 3032895213, 0);  // [time: 290.001ns -> 300.001ns]
+    reset();  // [time: 420.002ns -> 430.002ns]
+    reset();  // [time: 430.002ns -> 440.002ns]
+    reset();  // [time: 440.002ns -> 450.002ns]
+    write(15, 67108864, 2020268309, 0);  // [time: 490.002ns -> 510.002ns]
+    write(15, 67108865, 3122719830, 0);  // [time: 510.002ns -> 520.002ns]
+    read(15, 67108864, 2020268309, 0);  // [time: 520.002ns -> 540.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_12_0.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_12_0.bi.expect
new file mode 100644
index 00000000..bbe1f1e4
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_12_0.bi.expect
@@ -0,0 +1,19 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108867, 2205995893, 0);  // [time: 130ns -> 150ns]
+    read(15, 67108868, 486560095, 0);  // [time: 150ns -> 160ns]
+    reset();  // [time: 200.001ns -> 210.001ns]
+    reset();  // [time: 210.001ns -> 220.001ns]
+    reset();  // [time: 220.001ns -> 230.001ns]
+    write(15, 67108867, 4100133660, 0);  // [time: 270.001ns -> 290.001ns]
+    write(15, 67108868, 596618694, 0);  // [time: 290.001ns -> 300.001ns]
+    reset();  // [time: 420.002ns -> 430.002ns]
+    reset();  // [time: 430.002ns -> 440.002ns]
+    reset();  // [time: 440.002ns -> 450.002ns]
+    write(15, 67108867, 3499942130, 0);  // [time: 490.002ns -> 510.002ns]
+    write(15, 67108868, 2357711907, 0);  // [time: 510.002ns -> 520.002ns]
+    read(15, 67108867, 3499942130, 0);  // [time: 520.002ns -> 540.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_12_1.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_12_1.bi.expect
new file mode 100644
index 00000000..7b49175b
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_12_1.bi.expect
@@ -0,0 +1,19 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108867, 1833423740, 0);  // [time: 130ns -> 150ns]
+    read(15, 67108864, 4073618608, 0);  // [time: 150ns -> 160ns]
+    reset();  // [time: 200.001ns -> 210.001ns]
+    reset();  // [time: 210.001ns -> 220.001ns]
+    reset();  // [time: 220.001ns -> 230.001ns]
+    write(15, 67108867, 3418745219, 0);  // [time: 270.001ns -> 290.001ns]
+    write(15, 67108864, 3757272308, 0);  // [time: 290.001ns -> 300.001ns]
+    reset();  // [time: 420.002ns -> 430.002ns]
+    reset();  // [time: 430.002ns -> 440.002ns]
+    reset();  // [time: 440.002ns -> 450.002ns]
+    write(15, 67108867, 1325530178, 0);  // [time: 490.002ns -> 510.002ns]
+    write(15, 67108864, 1451722922, 0);  // [time: 510.002ns -> 520.002ns]
+    read(15, 67108867, 1325530178, 0);  // [time: 520.002ns -> 540.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_12_2.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_12_2.bi.expect
new file mode 100644
index 00000000..9971ed4a
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_12_2.bi.expect
@@ -0,0 +1,19 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108867, 1016512136, 0);  // [time: 130ns -> 150ns]
+    read(15, 67108868, 226204128, 0);  // [time: 150ns -> 160ns]
+    reset();  // [time: 200.001ns -> 210.001ns]
+    reset();  // [time: 210.001ns -> 220.001ns]
+    reset();  // [time: 220.001ns -> 230.001ns]
+    write(15, 67108867, 2116565440, 0);  // [time: 270.001ns -> 290.001ns]
+    write(15, 67108868, 2153688786, 0);  // [time: 290.001ns -> 300.001ns]
+    reset();  // [time: 420.002ns -> 430.002ns]
+    reset();  // [time: 430.002ns -> 440.002ns]
+    reset();  // [time: 440.002ns -> 450.002ns]
+    write(15, 67108867, 1974223269, 0);  // [time: 490.002ns -> 510.002ns]
+    write(15, 67108868, 1053640572, 0);  // [time: 510.002ns -> 520.002ns]
+    read(15, 67108867, 1974223269, 0);  // [time: 520.002ns -> 540.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_12_3.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_12_3.bi.expect
new file mode 100644
index 00000000..11bf515e
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_12_3.bi.expect
@@ -0,0 +1,19 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108867, 1509562552, 0);  // [time: 130ns -> 150ns]
+    read(15, 67108868, 2329347035, 0);  // [time: 150ns -> 160ns]
+    reset();  // [time: 200.001ns -> 210.001ns]
+    reset();  // [time: 210.001ns -> 220.001ns]
+    reset();  // [time: 220.001ns -> 230.001ns]
+    write(15, 67108867, 3862381389, 0);  // [time: 270.001ns -> 290.001ns]
+    write(15, 67108868, 1142123500, 0);  // [time: 290.001ns -> 300.001ns]
+    reset();  // [time: 420.002ns -> 430.002ns]
+    reset();  // [time: 430.002ns -> 440.002ns]
+    reset();  // [time: 440.002ns -> 450.002ns]
+    write(15, 67108867, 3598508010, 0);  // [time: 490.002ns -> 510.002ns]
+    write(15, 67108868, 908644471, 0);  // [time: 510.002ns -> 520.002ns]
+    read(15, 67108867, 3598508010, 0);  // [time: 520.002ns -> 540.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_4_0.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_4_0.bi.expect
new file mode 100644
index 00000000..5c52c496
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_4_0.bi.expect
@@ -0,0 +1,19 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108865, 2950170166, 0);  // [time: 130ns -> 150ns]
+    read(15, 67108866, 2782447364, 0);  // [time: 150ns -> 160ns]
+    reset();  // [time: 200.001ns -> 210.001ns]
+    reset();  // [time: 210.001ns -> 220.001ns]
+    reset();  // [time: 220.001ns -> 230.001ns]
+    write(15, 67108865, 2586475175, 0);  // [time: 270.001ns -> 290.001ns]
+    write(15, 67108866, 2087441910, 0);  // [time: 290.001ns -> 300.001ns]
+    reset();  // [time: 420.002ns -> 430.002ns]
+    reset();  // [time: 430.002ns -> 440.002ns]
+    reset();  // [time: 440.002ns -> 450.002ns]
+    write(15, 67108865, 3875005491, 0);  // [time: 490.002ns -> 510.002ns]
+    write(15, 67108866, 2597527218, 0);  // [time: 510.002ns -> 520.002ns]
+    read(15, 67108865, 3875005491, 0);  // [time: 520.002ns -> 540.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_4_1.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_4_1.bi.expect
new file mode 100644
index 00000000..0ae4956e
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_4_1.bi.expect
@@ -0,0 +1,19 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108865, 3580256271, 0);  // [time: 130ns -> 150ns]
+    read(15, 67108866, 1489666683, 0);  // [time: 150ns -> 160ns]
+    reset();  // [time: 200.001ns -> 210.001ns]
+    reset();  // [time: 210.001ns -> 220.001ns]
+    reset();  // [time: 220.001ns -> 230.001ns]
+    write(15, 67108865, 3677074643, 0);  // [time: 270.001ns -> 290.001ns]
+    write(15, 67108866, 1878953054, 0);  // [time: 290.001ns -> 300.001ns]
+    reset();  // [time: 420.002ns -> 430.002ns]
+    reset();  // [time: 430.002ns -> 440.002ns]
+    reset();  // [time: 440.002ns -> 450.002ns]
+    write(15, 67108865, 2965505115, 0);  // [time: 490.002ns -> 510.002ns]
+    write(15, 67108866, 3259566096, 0);  // [time: 510.002ns -> 520.002ns]
+    read(15, 67108865, 2965505115, 0);  // [time: 520.002ns -> 540.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_4_2.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_4_2.bi.expect
new file mode 100644
index 00000000..0ae4956e
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_4_2.bi.expect
@@ -0,0 +1,19 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108865, 3580256271, 0);  // [time: 130ns -> 150ns]
+    read(15, 67108866, 1489666683, 0);  // [time: 150ns -> 160ns]
+    reset();  // [time: 200.001ns -> 210.001ns]
+    reset();  // [time: 210.001ns -> 220.001ns]
+    reset();  // [time: 220.001ns -> 230.001ns]
+    write(15, 67108865, 3677074643, 0);  // [time: 270.001ns -> 290.001ns]
+    write(15, 67108866, 1878953054, 0);  // [time: 290.001ns -> 300.001ns]
+    reset();  // [time: 420.002ns -> 430.002ns]
+    reset();  // [time: 430.002ns -> 440.002ns]
+    reset();  // [time: 440.002ns -> 450.002ns]
+    write(15, 67108865, 2965505115, 0);  // [time: 490.002ns -> 510.002ns]
+    write(15, 67108866, 3259566096, 0);  // [time: 510.002ns -> 520.002ns]
+    read(15, 67108865, 2965505115, 0);  // [time: 520.002ns -> 540.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_4_3.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_4_3.bi.expect
new file mode 100644
index 00000000..e2edd110
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_4_3.bi.expect
@@ -0,0 +1,19 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108865, 3495738447, 0);  // [time: 130ns -> 150ns]
+    read(15, 67108866, 1478546475, 0);  // [time: 150ns -> 160ns]
+    reset();  // [time: 200.001ns -> 210.001ns]
+    reset();  // [time: 210.001ns -> 220.001ns]
+    reset();  // [time: 220.001ns -> 230.001ns]
+    write(15, 67108865, 2041778918, 0);  // [time: 270.001ns -> 290.001ns]
+    write(15, 67108866, 3032895213, 0);  // [time: 290.001ns -> 300.001ns]
+    reset();  // [time: 420.002ns -> 430.002ns]
+    reset();  // [time: 430.002ns -> 440.002ns]
+    reset();  // [time: 440.002ns -> 450.002ns]
+    write(15, 67108865, 2020268309, 0);  // [time: 490.002ns -> 510.002ns]
+    write(15, 67108866, 3122719830, 0);  // [time: 510.002ns -> 520.002ns]
+    read(15, 67108865, 2020268309, 0);  // [time: 520.002ns -> 540.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_8_0.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_8_0.bi.expect
new file mode 100644
index 00000000..d973d119
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_8_0.bi.expect
@@ -0,0 +1,19 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108866, 2950170166, 0);  // [time: 130ns -> 150ns]
+    read(15, 67108867, 2782447364, 0);  // [time: 150ns -> 160ns]
+    reset();  // [time: 200.001ns -> 210.001ns]
+    reset();  // [time: 210.001ns -> 220.001ns]
+    reset();  // [time: 220.001ns -> 230.001ns]
+    write(15, 67108866, 2586475175, 0);  // [time: 270.001ns -> 290.001ns]
+    write(15, 67108867, 2087441910, 0);  // [time: 290.001ns -> 300.001ns]
+    reset();  // [time: 420.002ns -> 430.002ns]
+    reset();  // [time: 430.002ns -> 440.002ns]
+    reset();  // [time: 440.002ns -> 450.002ns]
+    write(15, 67108866, 3875005491, 0);  // [time: 490.002ns -> 510.002ns]
+    write(15, 67108867, 2597527218, 0);  // [time: 510.002ns -> 520.002ns]
+    read(15, 67108866, 3875005491, 0);  // [time: 520.002ns -> 540.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_8_1.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_8_1.bi.expect
new file mode 100644
index 00000000..b22b7107
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_8_1.bi.expect
@@ -0,0 +1,19 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108866, 2205995893, 0);  // [time: 130ns -> 150ns]
+    read(15, 67108867, 486560095, 0);  // [time: 150ns -> 160ns]
+    reset();  // [time: 200.001ns -> 210.001ns]
+    reset();  // [time: 210.001ns -> 220.001ns]
+    reset();  // [time: 220.001ns -> 230.001ns]
+    write(15, 67108866, 4100133660, 0);  // [time: 270.001ns -> 290.001ns]
+    write(15, 67108867, 596618694, 0);  // [time: 290.001ns -> 300.001ns]
+    reset();  // [time: 420.002ns -> 430.002ns]
+    reset();  // [time: 430.002ns -> 440.002ns]
+    reset();  // [time: 440.002ns -> 450.002ns]
+    write(15, 67108866, 3499942130, 0);  // [time: 490.002ns -> 510.002ns]
+    write(15, 67108867, 2357711907, 0);  // [time: 510.002ns -> 520.002ns]
+    read(15, 67108866, 3499942130, 0);  // [time: 520.002ns -> 540.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_8_2.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_8_2.bi.expect
new file mode 100644
index 00000000..684182f5
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_8_2.bi.expect
@@ -0,0 +1,19 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108866, 1016512136, 0);  // [time: 130ns -> 150ns]
+    read(15, 67108867, 226204128, 0);  // [time: 150ns -> 160ns]
+    reset();  // [time: 200.001ns -> 210.001ns]
+    reset();  // [time: 210.001ns -> 220.001ns]
+    reset();  // [time: 220.001ns -> 230.001ns]
+    write(15, 67108866, 2116565440, 0);  // [time: 270.001ns -> 290.001ns]
+    write(15, 67108867, 2153688786, 0);  // [time: 290.001ns -> 300.001ns]
+    reset();  // [time: 420.002ns -> 430.002ns]
+    reset();  // [time: 430.002ns -> 440.002ns]
+    reset();  // [time: 440.002ns -> 450.002ns]
+    write(15, 67108866, 1974223269, 0);  // [time: 490.002ns -> 510.002ns]
+    write(15, 67108867, 1053640572, 0);  // [time: 510.002ns -> 520.002ns]
+    read(15, 67108866, 1974223269, 0);  // [time: 520.002ns -> 540.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_8_3.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_8_3.bi.expect
new file mode 100644
index 00000000..2328e1f0
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_2_8_3.bi.expect
@@ -0,0 +1,19 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108866, 1509562552, 0);  // [time: 130ns -> 150ns]
+    read(15, 67108867, 2329347035, 0);  // [time: 150ns -> 160ns]
+    reset();  // [time: 200.001ns -> 210.001ns]
+    reset();  // [time: 210.001ns -> 220.001ns]
+    reset();  // [time: 220.001ns -> 230.001ns]
+    write(15, 67108866, 3862381389, 0);  // [time: 270.001ns -> 290.001ns]
+    write(15, 67108867, 1142123500, 0);  // [time: 290.001ns -> 300.001ns]
+    reset();  // [time: 420.002ns -> 430.002ns]
+    reset();  // [time: 430.002ns -> 440.002ns]
+    reset();  // [time: 440.002ns -> 450.002ns]
+    write(15, 67108866, 3598508010, 0);  // [time: 490.002ns -> 510.002ns]
+    write(15, 67108867, 908644471, 0);  // [time: 510.002ns -> 520.002ns]
+    read(15, 67108866, 3598508010, 0);  // [time: 520.002ns -> 540.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_0_0.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_0_0.bi.expect
new file mode 100644
index 00000000..866952c5
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_0_0.bi.expect
@@ -0,0 +1,25 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108864, 2205995893, 0);  // [time: 170ns -> 190ns]
+    read(15, 67108865, 486560095, 0);  // [time: 190ns -> 200ns]
+    read(15, 67108866, 4100133660, 0);  // [time: 200ns -> 210ns]
+    read(15, 67108867, 596618694, 0);  // [time: 210ns -> 220ns]
+    reset();  // [time: 260.001ns -> 270.001ns]
+    reset();  // [time: 270.001ns -> 280.001ns]
+    reset();  // [time: 280.001ns -> 290.001ns]
+    write(15, 67108864, 3499942130, 0);  // [time: 330.001ns -> 350.001ns]
+    write(15, 67108865, 2357711907, 0);  // [time: 350.001ns -> 360.001ns]
+    write(15, 67108866, 2086526797, 0);  // [time: 360.001ns -> 370.001ns]
+    write(15, 67108867, 364077448, 0);  // [time: 370.001ns -> 380.001ns]
+    reset();  // [time: 580.002ns -> 590.002ns]
+    reset();  // [time: 590.002ns -> 600.002ns]
+    reset();  // [time: 600.002ns -> 610.002ns]
+    write(15, 67108864, 210674739, 0);  // [time: 650.002ns -> 670.002ns]
+    write(15, 67108865, 1567286535, 0);  // [time: 670.002ns -> 680.002ns]
+    write(15, 67108866, 922799025, 0);  // [time: 680.002ns -> 690.002ns]
+    write(15, 67108867, 4171757579, 0);  // [time: 690.002ns -> 700.002ns]
+    read(15, 67108864, 210674739, 0);  // [time: 700.002ns -> 720.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_0_1.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_0_1.bi.expect
new file mode 100644
index 00000000..0c3bcb95
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_0_1.bi.expect
@@ -0,0 +1,25 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108864, 1833423740, 0);  // [time: 170ns -> 190ns]
+    read(15, 67108865, 4073618608, 0);  // [time: 190ns -> 200ns]
+    read(15, 67108866, 3418745219, 0);  // [time: 200ns -> 210ns]
+    read(15, 67108867, 3757272308, 0);  // [time: 210ns -> 220ns]
+    reset();  // [time: 260.001ns -> 270.001ns]
+    reset();  // [time: 270.001ns -> 280.001ns]
+    reset();  // [time: 280.001ns -> 290.001ns]
+    write(15, 67108864, 1325530178, 0);  // [time: 330.001ns -> 350.001ns]
+    write(15, 67108865, 1451722922, 0);  // [time: 350.001ns -> 360.001ns]
+    write(15, 67108866, 1997677454, 0);  // [time: 360.001ns -> 370.001ns]
+    write(15, 67108867, 986005841, 0);  // [time: 370.001ns -> 380.001ns]
+    reset();  // [time: 580.002ns -> 590.002ns]
+    reset();  // [time: 590.002ns -> 600.002ns]
+    reset();  // [time: 600.002ns -> 610.002ns]
+    write(15, 67108864, 789975088, 0);  // [time: 650.002ns -> 670.002ns]
+    write(15, 67108865, 3746918692, 0);  // [time: 670.002ns -> 680.002ns]
+    write(15, 67108866, 410224063, 0);  // [time: 680.002ns -> 690.002ns]
+    write(15, 67108867, 864118294, 0);  // [time: 690.002ns -> 700.002ns]
+    read(15, 67108864, 789975088, 0);  // [time: 700.002ns -> 720.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_0_2.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_0_2.bi.expect
new file mode 100644
index 00000000..17c05629
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_0_2.bi.expect
@@ -0,0 +1,25 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108864, 869832817, 0);  // [time: 170ns -> 190ns]
+    read(15, 67108865, 2976082601, 0);  // [time: 190ns -> 200ns]
+    read(15, 67108866, 373695501, 0);  // [time: 200ns -> 210ns]
+    read(15, 67108867, 2110838384, 0);  // [time: 210ns -> 220ns]
+    reset();  // [time: 260.001ns -> 270.001ns]
+    reset();  // [time: 270.001ns -> 280.001ns]
+    reset();  // [time: 280.001ns -> 290.001ns]
+    write(15, 67108864, 3556455435, 0);  // [time: 330.001ns -> 350.001ns]
+    write(15, 67108865, 1804567173, 0);  // [time: 350.001ns -> 360.001ns]
+    write(15, 67108866, 1187331577, 0);  // [time: 360.001ns -> 370.001ns]
+    write(15, 67108867, 1293993917, 0);  // [time: 370.001ns -> 380.001ns]
+    reset();  // [time: 580.002ns -> 590.002ns]
+    reset();  // [time: 590.002ns -> 600.002ns]
+    reset();  // [time: 600.002ns -> 610.002ns]
+    write(15, 67108864, 753581369, 0);  // [time: 650.002ns -> 670.002ns]
+    write(15, 67108865, 2300246917, 0);  // [time: 670.002ns -> 680.002ns]
+    write(15, 67108866, 3523846629, 0);  // [time: 680.002ns -> 690.002ns]
+    write(15, 67108867, 3751494934, 0);  // [time: 690.002ns -> 700.002ns]
+    read(15, 67108864, 753581369, 0);  // [time: 700.002ns -> 720.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_0_3.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_0_3.bi.expect
new file mode 100644
index 00000000..7251b862
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_0_3.bi.expect
@@ -0,0 +1,25 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108864, 1509562552, 0);  // [time: 170ns -> 190ns]
+    read(15, 67108865, 2329347035, 0);  // [time: 190ns -> 200ns]
+    read(15, 67108866, 3862381389, 0);  // [time: 200ns -> 210ns]
+    read(15, 67108867, 1142123500, 0);  // [time: 210ns -> 220ns]
+    reset();  // [time: 260.001ns -> 270.001ns]
+    reset();  // [time: 270.001ns -> 280.001ns]
+    reset();  // [time: 280.001ns -> 290.001ns]
+    write(15, 67108864, 3598508010, 0);  // [time: 330.001ns -> 350.001ns]
+    write(15, 67108865, 908644471, 0);  // [time: 350.001ns -> 360.001ns]
+    write(15, 67108866, 870782326, 0);  // [time: 360.001ns -> 370.001ns]
+    write(15, 67108867, 1788061457, 0);  // [time: 370.001ns -> 380.001ns]
+    reset();  // [time: 580.002ns -> 590.002ns]
+    reset();  // [time: 590.002ns -> 600.002ns]
+    reset();  // [time: 600.002ns -> 610.002ns]
+    write(15, 67108864, 1483205141, 0);  // [time: 650.002ns -> 670.002ns]
+    write(15, 67108865, 408872453, 0);  // [time: 670.002ns -> 680.002ns]
+    write(15, 67108866, 2880683308, 0);  // [time: 680.002ns -> 690.002ns]
+    write(15, 67108867, 1446265757, 0);  // [time: 690.002ns -> 700.002ns]
+    read(15, 67108864, 1483205141, 0);  // [time: 700.002ns -> 720.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_12_0.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_12_0.bi.expect
new file mode 100644
index 00000000..74443970
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_12_0.bi.expect
@@ -0,0 +1,25 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108867, 518534189, 0);  // [time: 170ns -> 190ns]
+    read(15, 67108868, 844695266, 0);  // [time: 190ns -> 200ns]
+    read(15, 67108869, 3937184150, 0);  // [time: 200ns -> 210ns]
+    read(15, 67108870, 444246851, 0);  // [time: 210ns -> 220ns]
+    reset();  // [time: 260.001ns -> 270.001ns]
+    reset();  // [time: 270.001ns -> 280.001ns]
+    reset();  // [time: 280.001ns -> 290.001ns]
+    write(15, 67108867, 3220682802, 0);  // [time: 330.001ns -> 350.001ns]
+    write(15, 67108868, 2130811954, 0);  // [time: 350.001ns -> 360.001ns]
+    write(15, 67108869, 2002127438, 0);  // [time: 360.001ns -> 370.001ns]
+    write(15, 67108870, 493792053, 0);  // [time: 370.001ns -> 380.001ns]
+    reset();  // [time: 580.002ns -> 590.002ns]
+    reset();  // [time: 590.002ns -> 600.002ns]
+    reset();  // [time: 600.002ns -> 610.002ns]
+    write(15, 67108867, 63714206, 0);  // [time: 650.002ns -> 670.002ns]
+    write(15, 67108868, 2091823691, 0);  // [time: 670.002ns -> 680.002ns]
+    write(15, 67108869, 3903276977, 0);  // [time: 680.002ns -> 690.002ns]
+    write(15, 67108870, 1662756337, 0);  // [time: 690.002ns -> 700.002ns]
+    read(15, 67108867, 63714206, 0);  // [time: 700.002ns -> 720.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_12_1.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_12_1.bi.expect
new file mode 100644
index 00000000..f3104619
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_12_1.bi.expect
@@ -0,0 +1,25 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108867, 2821946881, 0);  // [time: 170ns -> 190ns]
+    read(15, 67108864, 4080087070, 0);  // [time: 190ns -> 200ns]
+    read(15, 67108865, 2243193877, 0);  // [time: 200ns -> 210ns]
+    read(15, 67108866, 2472849580, 0);  // [time: 210ns -> 220ns]
+    reset();  // [time: 260.001ns -> 270.001ns]
+    reset();  // [time: 270.001ns -> 280.001ns]
+    reset();  // [time: 280.001ns -> 290.001ns]
+    write(15, 67108867, 3565370026, 0);  // [time: 330.001ns -> 350.001ns]
+    write(15, 67108864, 890985600, 0);  // [time: 350.001ns -> 360.001ns]
+    write(15, 67108865, 4179549189, 0);  // [time: 360.001ns -> 370.001ns]
+    write(15, 67108866, 4158632492, 0);  // [time: 370.001ns -> 380.001ns]
+    reset();  // [time: 580.002ns -> 590.002ns]
+    reset();  // [time: 590.002ns -> 600.002ns]
+    reset();  // [time: 600.002ns -> 610.002ns]
+    write(15, 67108867, 3744957516, 0);  // [time: 650.002ns -> 670.002ns]
+    write(15, 67108864, 2300150418, 0);  // [time: 670.002ns -> 680.002ns]
+    write(15, 67108865, 2081940992, 0);  // [time: 680.002ns -> 690.002ns]
+    write(15, 67108866, 1697819148, 0);  // [time: 690.002ns -> 700.002ns]
+    read(15, 67108867, 3744957516, 0);  // [time: 700.002ns -> 720.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_12_2.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_12_2.bi.expect
new file mode 100644
index 00000000..96a45f4c
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_12_2.bi.expect
@@ -0,0 +1,25 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108867, 1016512136, 0);  // [time: 170ns -> 190ns]
+    read(15, 67108868, 226204128, 0);  // [time: 190ns -> 200ns]
+    read(15, 67108869, 2116565440, 0);  // [time: 200ns -> 210ns]
+    read(15, 67108870, 2153688786, 0);  // [time: 210ns -> 220ns]
+    reset();  // [time: 260.001ns -> 270.001ns]
+    reset();  // [time: 270.001ns -> 280.001ns]
+    reset();  // [time: 280.001ns -> 290.001ns]
+    write(15, 67108867, 1974223269, 0);  // [time: 330.001ns -> 350.001ns]
+    write(15, 67108868, 1053640572, 0);  // [time: 350.001ns -> 360.001ns]
+    write(15, 67108869, 2079860600, 0);  // [time: 360.001ns -> 370.001ns]
+    write(15, 67108870, 3550045624, 0);  // [time: 370.001ns -> 380.001ns]
+    reset();  // [time: 580.002ns -> 590.002ns]
+    reset();  // [time: 590.002ns -> 600.002ns]
+    reset();  // [time: 600.002ns -> 610.002ns]
+    write(15, 67108867, 1038322047, 0);  // [time: 650.002ns -> 670.002ns]
+    write(15, 67108868, 1502718053, 0);  // [time: 670.002ns -> 680.002ns]
+    write(15, 67108869, 1367070343, 0);  // [time: 680.002ns -> 690.002ns]
+    write(15, 67108870, 3425882885, 0);  // [time: 690.002ns -> 700.002ns]
+    read(15, 67108867, 1038322047, 0);  // [time: 700.002ns -> 720.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_12_3.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_12_3.bi.expect
new file mode 100644
index 00000000..372b11fb
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_12_3.bi.expect
@@ -0,0 +1,25 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108867, 1509562552, 0);  // [time: 170ns -> 190ns]
+    read(15, 67108868, 2329347035, 0);  // [time: 190ns -> 200ns]
+    read(15, 67108869, 3862381389, 0);  // [time: 200ns -> 210ns]
+    read(15, 67108870, 1142123500, 0);  // [time: 210ns -> 220ns]
+    reset();  // [time: 260.001ns -> 270.001ns]
+    reset();  // [time: 270.001ns -> 280.001ns]
+    reset();  // [time: 280.001ns -> 290.001ns]
+    write(15, 67108867, 3598508010, 0);  // [time: 330.001ns -> 350.001ns]
+    write(15, 67108868, 908644471, 0);  // [time: 350.001ns -> 360.001ns]
+    write(15, 67108869, 870782326, 0);  // [time: 360.001ns -> 370.001ns]
+    write(15, 67108870, 1788061457, 0);  // [time: 370.001ns -> 380.001ns]
+    reset();  // [time: 580.002ns -> 590.002ns]
+    reset();  // [time: 590.002ns -> 600.002ns]
+    reset();  // [time: 600.002ns -> 610.002ns]
+    write(15, 67108867, 1483205141, 0);  // [time: 650.002ns -> 670.002ns]
+    write(15, 67108868, 408872453, 0);  // [time: 670.002ns -> 680.002ns]
+    write(15, 67108869, 2880683308, 0);  // [time: 680.002ns -> 690.002ns]
+    write(15, 67108870, 1446265757, 0);  // [time: 690.002ns -> 700.002ns]
+    read(15, 67108867, 1483205141, 0);  // [time: 700.002ns -> 720.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_4_0.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_4_0.bi.expect
new file mode 100644
index 00000000..28cf4257
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_4_0.bi.expect
@@ -0,0 +1,25 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108865, 1833423740, 0);  // [time: 170ns -> 190ns]
+    read(15, 67108866, 4073618608, 0);  // [time: 190ns -> 200ns]
+    read(15, 67108867, 3418745219, 0);  // [time: 200ns -> 210ns]
+    read(15, 67108868, 3757272308, 0);  // [time: 210ns -> 220ns]
+    reset();  // [time: 260.001ns -> 270.001ns]
+    reset();  // [time: 270.001ns -> 280.001ns]
+    reset();  // [time: 280.001ns -> 290.001ns]
+    write(15, 67108865, 1325530178, 0);  // [time: 330.001ns -> 350.001ns]
+    write(15, 67108866, 1451722922, 0);  // [time: 350.001ns -> 360.001ns]
+    write(15, 67108867, 1997677454, 0);  // [time: 360.001ns -> 370.001ns]
+    write(15, 67108868, 986005841, 0);  // [time: 370.001ns -> 380.001ns]
+    reset();  // [time: 580.002ns -> 590.002ns]
+    reset();  // [time: 590.002ns -> 600.002ns]
+    reset();  // [time: 600.002ns -> 610.002ns]
+    write(15, 67108865, 789975088, 0);  // [time: 650.002ns -> 670.002ns]
+    write(15, 67108866, 3746918692, 0);  // [time: 670.002ns -> 680.002ns]
+    write(15, 67108867, 410224063, 0);  // [time: 680.002ns -> 690.002ns]
+    write(15, 67108868, 864118294, 0);  // [time: 690.002ns -> 700.002ns]
+    read(15, 67108865, 789975088, 0);  // [time: 700.002ns -> 720.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_4_1.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_4_1.bi.expect
new file mode 100644
index 00000000..50109ac8
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_4_1.bi.expect
@@ -0,0 +1,25 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108865, 518534189, 0);  // [time: 170ns -> 190ns]
+    read(15, 67108866, 844695266, 0);  // [time: 190ns -> 200ns]
+    read(15, 67108867, 3937184150, 0);  // [time: 200ns -> 210ns]
+    read(15, 67108864, 444246851, 0);  // [time: 210ns -> 220ns]
+    reset();  // [time: 260.001ns -> 270.001ns]
+    reset();  // [time: 270.001ns -> 280.001ns]
+    reset();  // [time: 280.001ns -> 290.001ns]
+    write(15, 67108865, 3220682802, 0);  // [time: 330.001ns -> 350.001ns]
+    write(15, 67108866, 2130811954, 0);  // [time: 350.001ns -> 360.001ns]
+    write(15, 67108867, 2002127438, 0);  // [time: 360.001ns -> 370.001ns]
+    write(15, 67108864, 493792053, 0);  // [time: 370.001ns -> 380.001ns]
+    reset();  // [time: 580.002ns -> 590.002ns]
+    reset();  // [time: 590.002ns -> 600.002ns]
+    reset();  // [time: 600.002ns -> 610.002ns]
+    write(15, 67108865, 63714206, 0);  // [time: 650.002ns -> 670.002ns]
+    write(15, 67108866, 2091823691, 0);  // [time: 670.002ns -> 680.002ns]
+    write(15, 67108867, 3903276977, 0);  // [time: 680.002ns -> 690.002ns]
+    write(15, 67108864, 1662756337, 0);  // [time: 690.002ns -> 700.002ns]
+    read(15, 67108865, 63714206, 0);  // [time: 700.002ns -> 720.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_4_2.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_4_2.bi.expect
new file mode 100644
index 00000000..110541f7
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_4_2.bi.expect
@@ -0,0 +1,25 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108865, 869832817, 0);  // [time: 170ns -> 190ns]
+    read(15, 67108866, 2976082601, 0);  // [time: 190ns -> 200ns]
+    read(15, 67108867, 373695501, 0);  // [time: 200ns -> 210ns]
+    read(15, 67108868, 2110838384, 0);  // [time: 210ns -> 220ns]
+    reset();  // [time: 260.001ns -> 270.001ns]
+    reset();  // [time: 270.001ns -> 280.001ns]
+    reset();  // [time: 280.001ns -> 290.001ns]
+    write(15, 67108865, 3556455435, 0);  // [time: 330.001ns -> 350.001ns]
+    write(15, 67108866, 1804567173, 0);  // [time: 350.001ns -> 360.001ns]
+    write(15, 67108867, 1187331577, 0);  // [time: 360.001ns -> 370.001ns]
+    write(15, 67108868, 1293993917, 0);  // [time: 370.001ns -> 380.001ns]
+    reset();  // [time: 580.002ns -> 590.002ns]
+    reset();  // [time: 590.002ns -> 600.002ns]
+    reset();  // [time: 600.002ns -> 610.002ns]
+    write(15, 67108865, 753581369, 0);  // [time: 650.002ns -> 670.002ns]
+    write(15, 67108866, 2300246917, 0);  // [time: 670.002ns -> 680.002ns]
+    write(15, 67108867, 3523846629, 0);  // [time: 680.002ns -> 690.002ns]
+    write(15, 67108868, 3751494934, 0);  // [time: 690.002ns -> 700.002ns]
+    read(15, 67108865, 753581369, 0);  // [time: 700.002ns -> 720.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_4_3.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_4_3.bi.expect
new file mode 100644
index 00000000..c525398d
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_4_3.bi.expect
@@ -0,0 +1,25 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108865, 1509562552, 0);  // [time: 170ns -> 190ns]
+    read(15, 67108866, 2329347035, 0);  // [time: 190ns -> 200ns]
+    read(15, 67108867, 3862381389, 0);  // [time: 200ns -> 210ns]
+    read(15, 67108868, 1142123500, 0);  // [time: 210ns -> 220ns]
+    reset();  // [time: 260.001ns -> 270.001ns]
+    reset();  // [time: 270.001ns -> 280.001ns]
+    reset();  // [time: 280.001ns -> 290.001ns]
+    write(15, 67108865, 3598508010, 0);  // [time: 330.001ns -> 350.001ns]
+    write(15, 67108866, 908644471, 0);  // [time: 350.001ns -> 360.001ns]
+    write(15, 67108867, 870782326, 0);  // [time: 360.001ns -> 370.001ns]
+    write(15, 67108868, 1788061457, 0);  // [time: 370.001ns -> 380.001ns]
+    reset();  // [time: 580.002ns -> 590.002ns]
+    reset();  // [time: 590.002ns -> 600.002ns]
+    reset();  // [time: 600.002ns -> 610.002ns]
+    write(15, 67108865, 1483205141, 0);  // [time: 650.002ns -> 670.002ns]
+    write(15, 67108866, 408872453, 0);  // [time: 670.002ns -> 680.002ns]
+    write(15, 67108867, 2880683308, 0);  // [time: 680.002ns -> 690.002ns]
+    write(15, 67108868, 1446265757, 0);  // [time: 690.002ns -> 700.002ns]
+    read(15, 67108865, 1483205141, 0);  // [time: 700.002ns -> 720.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_8_0.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_8_0.bi.expect
new file mode 100644
index 00000000..6d06914b
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_8_0.bi.expect
@@ -0,0 +1,25 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108866, 1833423740, 0);  // [time: 170ns -> 190ns]
+    read(15, 67108867, 4073618608, 0);  // [time: 190ns -> 200ns]
+    read(15, 67108868, 3418745219, 0);  // [time: 200ns -> 210ns]
+    read(15, 67108869, 3757272308, 0);  // [time: 210ns -> 220ns]
+    reset();  // [time: 260.001ns -> 270.001ns]
+    reset();  // [time: 270.001ns -> 280.001ns]
+    reset();  // [time: 280.001ns -> 290.001ns]
+    write(15, 67108866, 1325530178, 0);  // [time: 330.001ns -> 350.001ns]
+    write(15, 67108867, 1451722922, 0);  // [time: 350.001ns -> 360.001ns]
+    write(15, 67108868, 1997677454, 0);  // [time: 360.001ns -> 370.001ns]
+    write(15, 67108869, 986005841, 0);  // [time: 370.001ns -> 380.001ns]
+    reset();  // [time: 580.002ns -> 590.002ns]
+    reset();  // [time: 590.002ns -> 600.002ns]
+    reset();  // [time: 600.002ns -> 610.002ns]
+    write(15, 67108866, 789975088, 0);  // [time: 650.002ns -> 670.002ns]
+    write(15, 67108867, 3746918692, 0);  // [time: 670.002ns -> 680.002ns]
+    write(15, 67108868, 410224063, 0);  // [time: 680.002ns -> 690.002ns]
+    write(15, 67108869, 864118294, 0);  // [time: 690.002ns -> 700.002ns]
+    read(15, 67108866, 789975088, 0);  // [time: 700.002ns -> 720.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_8_1.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_8_1.bi.expect
new file mode 100644
index 00000000..e58197ce
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_8_1.bi.expect
@@ -0,0 +1,25 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108866, 518534189, 0);  // [time: 170ns -> 190ns]
+    read(15, 67108867, 844695266, 0);  // [time: 190ns -> 200ns]
+    read(15, 67108864, 3937184150, 0);  // [time: 200ns -> 210ns]
+    read(15, 67108865, 444246851, 0);  // [time: 210ns -> 220ns]
+    reset();  // [time: 260.001ns -> 270.001ns]
+    reset();  // [time: 270.001ns -> 280.001ns]
+    reset();  // [time: 280.001ns -> 290.001ns]
+    write(15, 67108866, 3220682802, 0);  // [time: 330.001ns -> 350.001ns]
+    write(15, 67108867, 2130811954, 0);  // [time: 350.001ns -> 360.001ns]
+    write(15, 67108864, 2002127438, 0);  // [time: 360.001ns -> 370.001ns]
+    write(15, 67108865, 493792053, 0);  // [time: 370.001ns -> 380.001ns]
+    reset();  // [time: 580.002ns -> 590.002ns]
+    reset();  // [time: 590.002ns -> 600.002ns]
+    reset();  // [time: 600.002ns -> 610.002ns]
+    write(15, 67108866, 63714206, 0);  // [time: 650.002ns -> 670.002ns]
+    write(15, 67108867, 2091823691, 0);  // [time: 670.002ns -> 680.002ns]
+    write(15, 67108864, 3903276977, 0);  // [time: 680.002ns -> 690.002ns]
+    write(15, 67108865, 1662756337, 0);  // [time: 690.002ns -> 700.002ns]
+    read(15, 67108866, 63714206, 0);  // [time: 700.002ns -> 720.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_8_2.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_8_2.bi.expect
new file mode 100644
index 00000000..9c8093c8
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_8_2.bi.expect
@@ -0,0 +1,25 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108866, 1016512136, 0);  // [time: 170ns -> 190ns]
+    read(15, 67108867, 226204128, 0);  // [time: 190ns -> 200ns]
+    read(15, 67108868, 2116565440, 0);  // [time: 200ns -> 210ns]
+    read(15, 67108869, 2153688786, 0);  // [time: 210ns -> 220ns]
+    reset();  // [time: 260.001ns -> 270.001ns]
+    reset();  // [time: 270.001ns -> 280.001ns]
+    reset();  // [time: 280.001ns -> 290.001ns]
+    write(15, 67108866, 1974223269, 0);  // [time: 330.001ns -> 350.001ns]
+    write(15, 67108867, 1053640572, 0);  // [time: 350.001ns -> 360.001ns]
+    write(15, 67108868, 2079860600, 0);  // [time: 360.001ns -> 370.001ns]
+    write(15, 67108869, 3550045624, 0);  // [time: 370.001ns -> 380.001ns]
+    reset();  // [time: 580.002ns -> 590.002ns]
+    reset();  // [time: 590.002ns -> 600.002ns]
+    reset();  // [time: 600.002ns -> 610.002ns]
+    write(15, 67108866, 1038322047, 0);  // [time: 650.002ns -> 670.002ns]
+    write(15, 67108867, 1502718053, 0);  // [time: 670.002ns -> 680.002ns]
+    write(15, 67108868, 1367070343, 0);  // [time: 680.002ns -> 690.002ns]
+    write(15, 67108869, 3425882885, 0);  // [time: 690.002ns -> 700.002ns]
+    read(15, 67108866, 1038322047, 0);  // [time: 700.002ns -> 720.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_8_3.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_8_3.bi.expect
new file mode 100644
index 00000000..cc76cf64
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_4_8_3.bi.expect
@@ -0,0 +1,25 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108866, 1070372987, 0);  // [time: 170ns -> 190ns]
+    read(15, 67108867, 2645947069, 0);  // [time: 190ns -> 200ns]
+    read(15, 67108868, 736643984, 0);  // [time: 200ns -> 210ns]
+    read(15, 67108869, 192007203, 0);  // [time: 210ns -> 220ns]
+    reset();  // [time: 260.001ns -> 270.001ns]
+    reset();  // [time: 270.001ns -> 280.001ns]
+    reset();  // [time: 280.001ns -> 290.001ns]
+    write(15, 67108866, 1925400290, 0);  // [time: 330.001ns -> 350.001ns]
+    write(15, 67108867, 1309609983, 0);  // [time: 350.001ns -> 360.001ns]
+    write(15, 67108868, 58503546, 0);  // [time: 360.001ns -> 370.001ns]
+    write(15, 67108869, 3861022989, 0);  // [time: 370.001ns -> 380.001ns]
+    reset();  // [time: 580.002ns -> 590.002ns]
+    reset();  // [time: 590.002ns -> 600.002ns]
+    reset();  // [time: 600.002ns -> 610.002ns]
+    write(15, 67108866, 1725708128, 0);  // [time: 650.002ns -> 670.002ns]
+    write(15, 67108867, 3760744365, 0);  // [time: 670.002ns -> 680.002ns]
+    write(15, 67108868, 3803789590, 0);  // [time: 680.002ns -> 690.002ns]
+    write(15, 67108869, 2647121574, 0);  // [time: 690.002ns -> 700.002ns]
+    read(15, 67108866, 1725708128, 0);  // [time: 700.002ns -> 720.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_0_0.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_0_0.bi.expect
new file mode 100644
index 00000000..66d2bc8e
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_0_0.bi.expect
@@ -0,0 +1,37 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108864, 518534189, 0);  // [time: 250ns -> 270ns]
+    read(15, 67108865, 844695266, 0);  // [time: 270ns -> 280ns]
+    read(15, 67108866, 3937184150, 0);  // [time: 280ns -> 290ns]
+    read(15, 67108867, 444246851, 0);  // [time: 290ns -> 300ns]
+    read(15, 67108868, 3220682802, 0);  // [time: 300ns -> 310ns]
+    read(15, 67108869, 2130811954, 0);  // [time: 310ns -> 320ns]
+    read(15, 67108870, 2002127438, 0);  // [time: 320ns -> 330ns]
+    read(15, 67108871, 493792053, 0);  // [time: 330ns -> 340ns]
+    reset();  // [time: 380.001ns -> 390.001ns]
+    reset();  // [time: 390.001ns -> 400.001ns]
+    reset();  // [time: 400.001ns -> 410.001ns]
+    write(15, 67108864, 63714206, 0);  // [time: 450.001ns -> 470.001ns]
+    write(15, 67108865, 2091823691, 0);  // [time: 470.001ns -> 480.001ns]
+    write(15, 67108866, 3903276977, 0);  // [time: 480.001ns -> 490.001ns]
+    write(15, 67108867, 1662756337, 0);  // [time: 490.001ns -> 500.001ns]
+    write(15, 67108868, 4101310419, 0);  // [time: 500.001ns -> 510.001ns]
+    write(15, 67108869, 903798156, 0);  // [time: 510.001ns -> 520.001ns]
+    write(15, 67108870, 3840476340, 0);  // [time: 520.001ns -> 530.001ns]
+    write(15, 67108871, 2244097975, 0);  // [time: 530.001ns -> 540.001ns]
+    reset();  // [time: 900.002ns -> 910.002ns]
+    reset();  // [time: 910.002ns -> 920.002ns]
+    reset();  // [time: 920.002ns -> 930.002ns]
+    write(15, 67108864, 3956643922, 0);  // [time: 970.002ns -> 990.002ns]
+    write(15, 67108865, 2115347845, 0);  // [time: 990.002ns -> 1000.002ns]
+    write(15, 67108866, 1775201107, 0);  // [time: 1000.002ns -> 1010.002ns]
+    write(15, 67108867, 1046910518, 0);  // [time: 1010.002ns -> 1020.002ns]
+    write(15, 67108868, 345998276, 0);  // [time: 1020.002ns -> 1030.002ns]
+    write(15, 67108869, 2089777588, 0);  // [time: 1030.002ns -> 1040.002ns]
+    write(15, 67108870, 3110941387, 0);  // [time: 1040.002ns -> 1050.002ns]
+    write(15, 67108871, 3151493219, 0);  // [time: 1050.002ns -> 1060.002ns]
+    read(15, 67108864, 3956643922, 0);  // [time: 1060.002ns -> 1080.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_0_1.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_0_1.bi.expect
new file mode 100644
index 00000000..bc132178
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_0_1.bi.expect
@@ -0,0 +1,37 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108864, 2821946881, 0);  // [time: 250ns -> 270ns]
+    read(15, 67108865, 4080087070, 0);  // [time: 270ns -> 280ns]
+    read(15, 67108866, 2243193877, 0);  // [time: 280ns -> 290ns]
+    read(15, 67108867, 2472849580, 0);  // [time: 290ns -> 300ns]
+    read(15, 67108868, 3565370026, 0);  // [time: 300ns -> 310ns]
+    read(15, 67108869, 890985600, 0);  // [time: 310ns -> 320ns]
+    read(15, 67108870, 4179549189, 0);  // [time: 320ns -> 330ns]
+    read(15, 67108871, 4158632492, 0);  // [time: 330ns -> 340ns]
+    reset();  // [time: 380.001ns -> 390.001ns]
+    reset();  // [time: 390.001ns -> 400.001ns]
+    reset();  // [time: 400.001ns -> 410.001ns]
+    write(15, 67108864, 3744957516, 0);  // [time: 450.001ns -> 470.001ns]
+    write(15, 67108865, 2300150418, 0);  // [time: 470.001ns -> 480.001ns]
+    write(15, 67108866, 2081940992, 0);  // [time: 480.001ns -> 490.001ns]
+    write(15, 67108867, 1697819148, 0);  // [time: 490.001ns -> 500.001ns]
+    write(15, 67108868, 602241333, 0);  // [time: 500.001ns -> 510.001ns]
+    write(15, 67108869, 2260552922, 0);  // [time: 510.001ns -> 520.001ns]
+    write(15, 67108870, 4251564751, 0);  // [time: 520.001ns -> 530.001ns]
+    write(15, 67108871, 3326548024, 0);  // [time: 530.001ns -> 540.001ns]
+    reset();  // [time: 900.002ns -> 910.002ns]
+    reset();  // [time: 910.002ns -> 920.002ns]
+    reset();  // [time: 920.002ns -> 930.002ns]
+    write(15, 67108864, 1044044861, 0);  // [time: 970.002ns -> 990.002ns]
+    write(15, 67108865, 4177314760, 0);  // [time: 990.002ns -> 1000.002ns]
+    write(15, 67108866, 4253662683, 0);  // [time: 1000.002ns -> 1010.002ns]
+    write(15, 67108867, 3575602093, 0);  // [time: 1010.002ns -> 1020.002ns]
+    write(15, 67108868, 667576938, 0);  // [time: 1020.002ns -> 1030.002ns]
+    write(15, 67108869, 3110079964, 0);  // [time: 1030.002ns -> 1040.002ns]
+    write(15, 67108870, 3758039968, 0);  // [time: 1040.002ns -> 1050.002ns]
+    write(15, 67108871, 3566852678, 0);  // [time: 1050.002ns -> 1060.002ns]
+    read(15, 67108864, 1044044861, 0);  // [time: 1060.002ns -> 1080.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_0_2.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_0_2.bi.expect
new file mode 100644
index 00000000..37006294
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_0_2.bi.expect
@@ -0,0 +1,37 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108864, 869832817, 0);  // [time: 250ns -> 270ns]
+    read(15, 67108865, 2976082601, 0);  // [time: 270ns -> 280ns]
+    read(15, 67108866, 373695501, 0);  // [time: 280ns -> 290ns]
+    read(15, 67108867, 2110838384, 0);  // [time: 290ns -> 300ns]
+    read(15, 67108868, 3556455435, 0);  // [time: 300ns -> 310ns]
+    read(15, 67108869, 1804567173, 0);  // [time: 310ns -> 320ns]
+    read(15, 67108870, 1187331577, 0);  // [time: 320ns -> 330ns]
+    read(15, 67108871, 1293993917, 0);  // [time: 330ns -> 340ns]
+    reset();  // [time: 380.001ns -> 390.001ns]
+    reset();  // [time: 390.001ns -> 400.001ns]
+    reset();  // [time: 400.001ns -> 410.001ns]
+    write(15, 67108864, 753581369, 0);  // [time: 450.001ns -> 470.001ns]
+    write(15, 67108865, 2300246917, 0);  // [time: 470.001ns -> 480.001ns]
+    write(15, 67108866, 3523846629, 0);  // [time: 480.001ns -> 490.001ns]
+    write(15, 67108867, 3751494934, 0);  // [time: 490.001ns -> 500.001ns]
+    write(15, 67108868, 504397671, 0);  // [time: 500.001ns -> 510.001ns]
+    write(15, 67108869, 3203321461, 0);  // [time: 510.001ns -> 520.001ns]
+    write(15, 67108870, 3801714021, 0);  // [time: 520.001ns -> 530.001ns]
+    write(15, 67108871, 654543662, 0);  // [time: 530.001ns -> 540.001ns]
+    reset();  // [time: 900.002ns -> 910.002ns]
+    reset();  // [time: 910.002ns -> 920.002ns]
+    reset();  // [time: 920.002ns -> 930.002ns]
+    write(15, 67108864, 1829143953, 0);  // [time: 970.002ns -> 990.002ns]
+    write(15, 67108865, 2746894674, 0);  // [time: 990.002ns -> 1000.002ns]
+    write(15, 67108866, 3464933947, 0);  // [time: 1000.002ns -> 1010.002ns]
+    write(15, 67108867, 3350075041, 0);  // [time: 1010.002ns -> 1020.002ns]
+    write(15, 67108868, 1123364414, 0);  // [time: 1020.002ns -> 1030.002ns]
+    write(15, 67108869, 3896266205, 0);  // [time: 1030.002ns -> 1040.002ns]
+    write(15, 67108870, 3668919860, 0);  // [time: 1040.002ns -> 1050.002ns]
+    write(15, 67108871, 177490457, 0);  // [time: 1050.002ns -> 1060.002ns]
+    read(15, 67108864, 1829143953, 0);  // [time: 1060.002ns -> 1080.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_0_3.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_0_3.bi.expect
new file mode 100644
index 00000000..60d1cc31
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_0_3.bi.expect
@@ -0,0 +1,37 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108864, 1070372987, 0);  // [time: 250ns -> 270ns]
+    read(15, 67108865, 2645947069, 0);  // [time: 270ns -> 280ns]
+    read(15, 67108866, 736643984, 0);  // [time: 280ns -> 290ns]
+    read(15, 67108867, 192007203, 0);  // [time: 290ns -> 300ns]
+    read(15, 67108868, 1925400290, 0);  // [time: 300ns -> 310ns]
+    read(15, 67108869, 1309609983, 0);  // [time: 310ns -> 320ns]
+    read(15, 67108870, 58503546, 0);  // [time: 320ns -> 330ns]
+    read(15, 67108871, 3861022989, 0);  // [time: 330ns -> 340ns]
+    reset();  // [time: 380.001ns -> 390.001ns]
+    reset();  // [time: 390.001ns -> 400.001ns]
+    reset();  // [time: 400.001ns -> 410.001ns]
+    write(15, 67108864, 1725708128, 0);  // [time: 450.001ns -> 470.001ns]
+    write(15, 67108865, 3760744365, 0);  // [time: 470.001ns -> 480.001ns]
+    write(15, 67108866, 3803789590, 0);  // [time: 480.001ns -> 490.001ns]
+    write(15, 67108867, 2647121574, 0);  // [time: 490.001ns -> 500.001ns]
+    write(15, 67108868, 336117328, 0);  // [time: 500.001ns -> 510.001ns]
+    write(15, 67108869, 3984726565, 0);  // [time: 510.001ns -> 520.001ns]
+    write(15, 67108870, 104808193, 0);  // [time: 520.001ns -> 530.001ns]
+    write(15, 67108871, 2315494688, 0);  // [time: 530.001ns -> 540.001ns]
+    reset();  // [time: 900.002ns -> 910.002ns]
+    reset();  // [time: 910.002ns -> 920.002ns]
+    reset();  // [time: 920.002ns -> 930.002ns]
+    write(15, 67108864, 3997204021, 0);  // [time: 970.002ns -> 990.002ns]
+    write(15, 67108865, 666660673, 0);  // [time: 990.002ns -> 1000.002ns]
+    write(15, 67108866, 3910223084, 0);  // [time: 1000.002ns -> 1010.002ns]
+    write(15, 67108867, 1271405124, 0);  // [time: 1010.002ns -> 1020.002ns]
+    write(15, 67108868, 4236388983, 0);  // [time: 1020.002ns -> 1030.002ns]
+    write(15, 67108869, 1347016890, 0);  // [time: 1030.002ns -> 1040.002ns]
+    write(15, 67108870, 1337396640, 0);  // [time: 1040.002ns -> 1050.002ns]
+    write(15, 67108871, 3009712000, 0);  // [time: 1050.002ns -> 1060.002ns]
+    read(15, 67108864, 3997204021, 0);  // [time: 1060.002ns -> 1080.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_12_0.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_12_0.bi.expect
new file mode 100644
index 00000000..d17bbe8a
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_12_0.bi.expect
@@ -0,0 +1,37 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108867, 3580256271, 0);  // [time: 250ns -> 270ns]
+    read(15, 67108868, 1489666683, 0);  // [time: 270ns -> 280ns]
+    read(15, 67108869, 3677074643, 0);  // [time: 280ns -> 290ns]
+    read(15, 67108870, 1878953054, 0);  // [time: 290ns -> 300ns]
+    read(15, 67108871, 2965505115, 0);  // [time: 300ns -> 310ns]
+    read(15, 67108872, 3259566096, 0);  // [time: 310ns -> 320ns]
+    read(15, 67108873, 1262153110, 0);  // [time: 320ns -> 330ns]
+    read(15, 67108874, 2451703670, 0);  // [time: 330ns -> 340ns]
+    reset();  // [time: 380.001ns -> 390.001ns]
+    reset();  // [time: 390.001ns -> 400.001ns]
+    reset();  // [time: 400.001ns -> 410.001ns]
+    write(15, 67108867, 3104341711, 0);  // [time: 450.001ns -> 470.001ns]
+    write(15, 67108868, 964066815, 0);  // [time: 470.001ns -> 480.001ns]
+    write(15, 67108869, 3328791441, 0);  // [time: 480.001ns -> 490.001ns]
+    write(15, 67108870, 3489570824, 0);  // [time: 490.001ns -> 500.001ns]
+    write(15, 67108871, 4241788620, 0);  // [time: 500.001ns -> 510.001ns]
+    write(15, 67108872, 3583058104, 0);  // [time: 510.001ns -> 520.001ns]
+    write(15, 67108873, 1005667378, 0);  // [time: 520.001ns -> 530.001ns]
+    write(15, 67108874, 209419171, 0);  // [time: 530.001ns -> 540.001ns]
+    reset();  // [time: 900.002ns -> 910.002ns]
+    reset();  // [time: 910.002ns -> 920.002ns]
+    reset();  // [time: 920.002ns -> 930.002ns]
+    write(15, 67108867, 1000382631, 0);  // [time: 970.002ns -> 990.002ns]
+    write(15, 67108868, 1285425234, 0);  // [time: 990.002ns -> 1000.002ns]
+    write(15, 67108869, 318606993, 0);  // [time: 1000.002ns -> 1010.002ns]
+    write(15, 67108870, 2625467664, 0);  // [time: 1010.002ns -> 1020.002ns]
+    write(15, 67108871, 229964357, 0);  // [time: 1020.002ns -> 1030.002ns]
+    write(15, 67108872, 3036014706, 0);  // [time: 1030.002ns -> 1040.002ns]
+    write(15, 67108873, 1528299378, 0);  // [time: 1040.002ns -> 1050.002ns]
+    write(15, 67108874, 2182965409, 0);  // [time: 1050.002ns -> 1060.002ns]
+    read(15, 67108867, 1000382631, 0);  // [time: 1060.002ns -> 1080.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_12_1.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_12_1.bi.expect
new file mode 100644
index 00000000..f8f3065d
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_12_1.bi.expect
@@ -0,0 +1,37 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108867, 518534189, 0);  // [time: 250ns -> 270ns]
+    read(15, 67108864, 844695266, 0);  // [time: 270ns -> 280ns]
+    read(15, 67108865, 3937184150, 0);  // [time: 280ns -> 290ns]
+    read(15, 67108866, 444246851, 0);  // [time: 290ns -> 300ns]
+    read(15, 67108871, 3220682802, 0);  // [time: 300ns -> 310ns]
+    read(15, 67108868, 2130811954, 0);  // [time: 310ns -> 320ns]
+    read(15, 67108869, 2002127438, 0);  // [time: 320ns -> 330ns]
+    read(15, 67108870, 493792053, 0);  // [time: 330ns -> 340ns]
+    reset();  // [time: 380.001ns -> 390.001ns]
+    reset();  // [time: 390.001ns -> 400.001ns]
+    reset();  // [time: 400.001ns -> 410.001ns]
+    write(15, 67108867, 63714206, 0);  // [time: 450.001ns -> 470.001ns]
+    write(15, 67108864, 2091823691, 0);  // [time: 470.001ns -> 480.001ns]
+    write(15, 67108865, 3903276977, 0);  // [time: 480.001ns -> 490.001ns]
+    write(15, 67108866, 1662756337, 0);  // [time: 490.001ns -> 500.001ns]
+    write(15, 67108871, 4101310419, 0);  // [time: 500.001ns -> 510.001ns]
+    write(15, 67108868, 903798156, 0);  // [time: 510.001ns -> 520.001ns]
+    write(15, 67108869, 3840476340, 0);  // [time: 520.001ns -> 530.001ns]
+    write(15, 67108870, 2244097975, 0);  // [time: 530.001ns -> 540.001ns]
+    reset();  // [time: 900.002ns -> 910.002ns]
+    reset();  // [time: 910.002ns -> 920.002ns]
+    reset();  // [time: 920.002ns -> 930.002ns]
+    write(15, 67108867, 3956643922, 0);  // [time: 970.002ns -> 990.002ns]
+    write(15, 67108864, 2115347845, 0);  // [time: 990.002ns -> 1000.002ns]
+    write(15, 67108865, 1775201107, 0);  // [time: 1000.002ns -> 1010.002ns]
+    write(15, 67108866, 1046910518, 0);  // [time: 1010.002ns -> 1020.002ns]
+    write(15, 67108871, 345998276, 0);  // [time: 1020.002ns -> 1030.002ns]
+    write(15, 67108868, 2089777588, 0);  // [time: 1030.002ns -> 1040.002ns]
+    write(15, 67108869, 3110941387, 0);  // [time: 1040.002ns -> 1050.002ns]
+    write(15, 67108870, 3151493219, 0);  // [time: 1050.002ns -> 1060.002ns]
+    read(15, 67108867, 3956643922, 0);  // [time: 1060.002ns -> 1080.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_12_2.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_12_2.bi.expect
new file mode 100644
index 00000000..441adf6a
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_12_2.bi.expect
@@ -0,0 +1,37 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108867, 869832817, 0);  // [time: 250ns -> 270ns]
+    read(15, 67108868, 2976082601, 0);  // [time: 270ns -> 280ns]
+    read(15, 67108869, 373695501, 0);  // [time: 280ns -> 290ns]
+    read(15, 67108870, 2110838384, 0);  // [time: 290ns -> 300ns]
+    read(15, 67108871, 3556455435, 0);  // [time: 300ns -> 310ns]
+    read(15, 67108864, 1804567173, 0);  // [time: 310ns -> 320ns]
+    read(15, 67108865, 1187331577, 0);  // [time: 320ns -> 330ns]
+    read(15, 67108866, 1293993917, 0);  // [time: 330ns -> 340ns]
+    reset();  // [time: 380.001ns -> 390.001ns]
+    reset();  // [time: 390.001ns -> 400.001ns]
+    reset();  // [time: 400.001ns -> 410.001ns]
+    write(15, 67108867, 753581369, 0);  // [time: 450.001ns -> 470.001ns]
+    write(15, 67108868, 2300246917, 0);  // [time: 470.001ns -> 480.001ns]
+    write(15, 67108869, 3523846629, 0);  // [time: 480.001ns -> 490.001ns]
+    write(15, 67108870, 3751494934, 0);  // [time: 490.001ns -> 500.001ns]
+    write(15, 67108871, 504397671, 0);  // [time: 500.001ns -> 510.001ns]
+    write(15, 67108864, 3203321461, 0);  // [time: 510.001ns -> 520.001ns]
+    write(15, 67108865, 3801714021, 0);  // [time: 520.001ns -> 530.001ns]
+    write(15, 67108866, 654543662, 0);  // [time: 530.001ns -> 540.001ns]
+    reset();  // [time: 900.002ns -> 910.002ns]
+    reset();  // [time: 910.002ns -> 920.002ns]
+    reset();  // [time: 920.002ns -> 930.002ns]
+    write(15, 67108867, 1829143953, 0);  // [time: 970.002ns -> 990.002ns]
+    write(15, 67108868, 2746894674, 0);  // [time: 990.002ns -> 1000.002ns]
+    write(15, 67108869, 3464933947, 0);  // [time: 1000.002ns -> 1010.002ns]
+    write(15, 67108870, 3350075041, 0);  // [time: 1010.002ns -> 1020.002ns]
+    write(15, 67108871, 1123364414, 0);  // [time: 1020.002ns -> 1030.002ns]
+    write(15, 67108864, 3896266205, 0);  // [time: 1030.002ns -> 1040.002ns]
+    write(15, 67108865, 3668919860, 0);  // [time: 1040.002ns -> 1050.002ns]
+    write(15, 67108866, 177490457, 0);  // [time: 1050.002ns -> 1060.002ns]
+    read(15, 67108867, 1829143953, 0);  // [time: 1060.002ns -> 1080.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_12_3.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_12_3.bi.expect
new file mode 100644
index 00000000..1b811196
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_12_3.bi.expect
@@ -0,0 +1,37 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108867, 1070372987, 0);  // [time: 250ns -> 270ns]
+    read(15, 67108868, 2645947069, 0);  // [time: 270ns -> 280ns]
+    read(15, 67108869, 736643984, 0);  // [time: 280ns -> 290ns]
+    read(15, 67108870, 192007203, 0);  // [time: 290ns -> 300ns]
+    read(15, 67108871, 1925400290, 0);  // [time: 300ns -> 310ns]
+    read(15, 67108872, 1309609983, 0);  // [time: 310ns -> 320ns]
+    read(15, 67108873, 58503546, 0);  // [time: 320ns -> 330ns]
+    read(15, 67108874, 3861022989, 0);  // [time: 330ns -> 340ns]
+    reset();  // [time: 380.001ns -> 390.001ns]
+    reset();  // [time: 390.001ns -> 400.001ns]
+    reset();  // [time: 400.001ns -> 410.001ns]
+    write(15, 67108867, 1725708128, 0);  // [time: 450.001ns -> 470.001ns]
+    write(15, 67108868, 3760744365, 0);  // [time: 470.001ns -> 480.001ns]
+    write(15, 67108869, 3803789590, 0);  // [time: 480.001ns -> 490.001ns]
+    write(15, 67108870, 2647121574, 0);  // [time: 490.001ns -> 500.001ns]
+    write(15, 67108871, 336117328, 0);  // [time: 500.001ns -> 510.001ns]
+    write(15, 67108872, 3984726565, 0);  // [time: 510.001ns -> 520.001ns]
+    write(15, 67108873, 104808193, 0);  // [time: 520.001ns -> 530.001ns]
+    write(15, 67108874, 2315494688, 0);  // [time: 530.001ns -> 540.001ns]
+    reset();  // [time: 900.002ns -> 910.002ns]
+    reset();  // [time: 910.002ns -> 920.002ns]
+    reset();  // [time: 920.002ns -> 930.002ns]
+    write(15, 67108867, 3997204021, 0);  // [time: 970.002ns -> 990.002ns]
+    write(15, 67108868, 666660673, 0);  // [time: 990.002ns -> 1000.002ns]
+    write(15, 67108869, 3910223084, 0);  // [time: 1000.002ns -> 1010.002ns]
+    write(15, 67108870, 1271405124, 0);  // [time: 1010.002ns -> 1020.002ns]
+    write(15, 67108871, 4236388983, 0);  // [time: 1020.002ns -> 1030.002ns]
+    write(15, 67108872, 1347016890, 0);  // [time: 1030.002ns -> 1040.002ns]
+    write(15, 67108873, 1337396640, 0);  // [time: 1040.002ns -> 1050.002ns]
+    write(15, 67108874, 3009712000, 0);  // [time: 1050.002ns -> 1060.002ns]
+    read(15, 67108867, 3997204021, 0);  // [time: 1060.002ns -> 1080.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_4_0.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_4_0.bi.expect
new file mode 100644
index 00000000..c48eeb96
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_4_0.bi.expect
@@ -0,0 +1,37 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108865, 2821946881, 0);  // [time: 250ns -> 270ns]
+    read(15, 67108866, 4080087070, 0);  // [time: 270ns -> 280ns]
+    read(15, 67108867, 2243193877, 0);  // [time: 280ns -> 290ns]
+    read(15, 67108868, 2472849580, 0);  // [time: 290ns -> 300ns]
+    read(15, 67108869, 3565370026, 0);  // [time: 300ns -> 310ns]
+    read(15, 67108870, 890985600, 0);  // [time: 310ns -> 320ns]
+    read(15, 67108871, 4179549189, 0);  // [time: 320ns -> 330ns]
+    read(15, 67108872, 4158632492, 0);  // [time: 330ns -> 340ns]
+    reset();  // [time: 380.001ns -> 390.001ns]
+    reset();  // [time: 390.001ns -> 400.001ns]
+    reset();  // [time: 400.001ns -> 410.001ns]
+    write(15, 67108865, 3744957516, 0);  // [time: 450.001ns -> 470.001ns]
+    write(15, 67108866, 2300150418, 0);  // [time: 470.001ns -> 480.001ns]
+    write(15, 67108867, 2081940992, 0);  // [time: 480.001ns -> 490.001ns]
+    write(15, 67108868, 1697819148, 0);  // [time: 490.001ns -> 500.001ns]
+    write(15, 67108869, 602241333, 0);  // [time: 500.001ns -> 510.001ns]
+    write(15, 67108870, 2260552922, 0);  // [time: 510.001ns -> 520.001ns]
+    write(15, 67108871, 4251564751, 0);  // [time: 520.001ns -> 530.001ns]
+    write(15, 67108872, 3326548024, 0);  // [time: 530.001ns -> 540.001ns]
+    reset();  // [time: 900.002ns -> 910.002ns]
+    reset();  // [time: 910.002ns -> 920.002ns]
+    reset();  // [time: 920.002ns -> 930.002ns]
+    write(15, 67108865, 1044044861, 0);  // [time: 970.002ns -> 990.002ns]
+    write(15, 67108866, 4177314760, 0);  // [time: 990.002ns -> 1000.002ns]
+    write(15, 67108867, 4253662683, 0);  // [time: 1000.002ns -> 1010.002ns]
+    write(15, 67108868, 3575602093, 0);  // [time: 1010.002ns -> 1020.002ns]
+    write(15, 67108869, 667576938, 0);  // [time: 1020.002ns -> 1030.002ns]
+    write(15, 67108870, 3110079964, 0);  // [time: 1030.002ns -> 1040.002ns]
+    write(15, 67108871, 3758039968, 0);  // [time: 1040.002ns -> 1050.002ns]
+    write(15, 67108872, 3566852678, 0);  // [time: 1050.002ns -> 1060.002ns]
+    read(15, 67108865, 1044044861, 0);  // [time: 1060.002ns -> 1080.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_4_1.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_4_1.bi.expect
new file mode 100644
index 00000000..1bea919b
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_4_1.bi.expect
@@ -0,0 +1,37 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108865, 2205995893, 0);  // [time: 250ns -> 270ns]
+    read(15, 67108866, 486560095, 0);  // [time: 270ns -> 280ns]
+    read(15, 67108867, 4100133660, 0);  // [time: 280ns -> 290ns]
+    read(15, 67108864, 596618694, 0);  // [time: 290ns -> 300ns]
+    read(15, 67108869, 3499942130, 0);  // [time: 300ns -> 310ns]
+    read(15, 67108870, 2357711907, 0);  // [time: 310ns -> 320ns]
+    read(15, 67108871, 2086526797, 0);  // [time: 320ns -> 330ns]
+    read(15, 67108868, 364077448, 0);  // [time: 330ns -> 340ns]
+    reset();  // [time: 380.001ns -> 390.001ns]
+    reset();  // [time: 390.001ns -> 400.001ns]
+    reset();  // [time: 400.001ns -> 410.001ns]
+    write(15, 67108865, 210674739, 0);  // [time: 450.001ns -> 470.001ns]
+    write(15, 67108866, 1567286535, 0);  // [time: 470.001ns -> 480.001ns]
+    write(15, 67108867, 922799025, 0);  // [time: 480.001ns -> 490.001ns]
+    write(15, 67108864, 4171757579, 0);  // [time: 490.001ns -> 500.001ns]
+    write(15, 67108869, 740193371, 0);  // [time: 500.001ns -> 510.001ns]
+    write(15, 67108870, 872570658, 0);  // [time: 510.001ns -> 520.001ns]
+    write(15, 67108871, 608559447, 0);  // [time: 520.001ns -> 530.001ns]
+    write(15, 67108868, 1049762371, 0);  // [time: 530.001ns -> 540.001ns]
+    reset();  // [time: 900.002ns -> 910.002ns]
+    reset();  // [time: 910.002ns -> 920.002ns]
+    reset();  // [time: 920.002ns -> 930.002ns]
+    write(15, 67108865, 61321282, 0);  // [time: 970.002ns -> 990.002ns]
+    write(15, 67108866, 3113679544, 0);  // [time: 990.002ns -> 1000.002ns]
+    write(15, 67108867, 2723657215, 0);  // [time: 1000.002ns -> 1010.002ns]
+    write(15, 67108864, 3578979173, 0);  // [time: 1010.002ns -> 1020.002ns]
+    write(15, 67108869, 1844094072, 0);  // [time: 1020.002ns -> 1030.002ns]
+    write(15, 67108870, 985922533, 0);  // [time: 1030.002ns -> 1040.002ns]
+    write(15, 67108871, 772047228, 0);  // [time: 1040.002ns -> 1050.002ns]
+    write(15, 67108868, 2786594234, 0);  // [time: 1050.002ns -> 1060.002ns]
+    read(15, 67108865, 61321282, 0);  // [time: 1060.002ns -> 1080.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_4_2.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_4_2.bi.expect
new file mode 100644
index 00000000..efb5de91
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_4_2.bi.expect
@@ -0,0 +1,37 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108865, 869832817, 0);  // [time: 250ns -> 270ns]
+    read(15, 67108866, 2976082601, 0);  // [time: 270ns -> 280ns]
+    read(15, 67108867, 373695501, 0);  // [time: 280ns -> 290ns]
+    read(15, 67108868, 2110838384, 0);  // [time: 290ns -> 300ns]
+    read(15, 67108869, 3556455435, 0);  // [time: 300ns -> 310ns]
+    read(15, 67108870, 1804567173, 0);  // [time: 310ns -> 320ns]
+    read(15, 67108871, 1187331577, 0);  // [time: 320ns -> 330ns]
+    read(15, 67108864, 1293993917, 0);  // [time: 330ns -> 340ns]
+    reset();  // [time: 380.001ns -> 390.001ns]
+    reset();  // [time: 390.001ns -> 400.001ns]
+    reset();  // [time: 400.001ns -> 410.001ns]
+    write(15, 67108865, 753581369, 0);  // [time: 450.001ns -> 470.001ns]
+    write(15, 67108866, 2300246917, 0);  // [time: 470.001ns -> 480.001ns]
+    write(15, 67108867, 3523846629, 0);  // [time: 480.001ns -> 490.001ns]
+    write(15, 67108868, 3751494934, 0);  // [time: 490.001ns -> 500.001ns]
+    write(15, 67108869, 504397671, 0);  // [time: 500.001ns -> 510.001ns]
+    write(15, 67108870, 3203321461, 0);  // [time: 510.001ns -> 520.001ns]
+    write(15, 67108871, 3801714021, 0);  // [time: 520.001ns -> 530.001ns]
+    write(15, 67108864, 654543662, 0);  // [time: 530.001ns -> 540.001ns]
+    reset();  // [time: 900.002ns -> 910.002ns]
+    reset();  // [time: 910.002ns -> 920.002ns]
+    reset();  // [time: 920.002ns -> 930.002ns]
+    write(15, 67108865, 1829143953, 0);  // [time: 970.002ns -> 990.002ns]
+    write(15, 67108866, 2746894674, 0);  // [time: 990.002ns -> 1000.002ns]
+    write(15, 67108867, 3464933947, 0);  // [time: 1000.002ns -> 1010.002ns]
+    write(15, 67108868, 3350075041, 0);  // [time: 1010.002ns -> 1020.002ns]
+    write(15, 67108869, 1123364414, 0);  // [time: 1020.002ns -> 1030.002ns]
+    write(15, 67108870, 3896266205, 0);  // [time: 1030.002ns -> 1040.002ns]
+    write(15, 67108871, 3668919860, 0);  // [time: 1040.002ns -> 1050.002ns]
+    write(15, 67108864, 177490457, 0);  // [time: 1050.002ns -> 1060.002ns]
+    read(15, 67108865, 1829143953, 0);  // [time: 1060.002ns -> 1080.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_4_3.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_4_3.bi.expect
new file mode 100644
index 00000000..84c4435f
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_4_3.bi.expect
@@ -0,0 +1,37 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108865, 1070372987, 0);  // [time: 250ns -> 270ns]
+    read(15, 67108866, 2645947069, 0);  // [time: 270ns -> 280ns]
+    read(15, 67108867, 736643984, 0);  // [time: 280ns -> 290ns]
+    read(15, 67108868, 192007203, 0);  // [time: 290ns -> 300ns]
+    read(15, 67108869, 1925400290, 0);  // [time: 300ns -> 310ns]
+    read(15, 67108870, 1309609983, 0);  // [time: 310ns -> 320ns]
+    read(15, 67108871, 58503546, 0);  // [time: 320ns -> 330ns]
+    read(15, 67108872, 3861022989, 0);  // [time: 330ns -> 340ns]
+    reset();  // [time: 380.001ns -> 390.001ns]
+    reset();  // [time: 390.001ns -> 400.001ns]
+    reset();  // [time: 400.001ns -> 410.001ns]
+    write(15, 67108865, 1725708128, 0);  // [time: 450.001ns -> 470.001ns]
+    write(15, 67108866, 3760744365, 0);  // [time: 470.001ns -> 480.001ns]
+    write(15, 67108867, 3803789590, 0);  // [time: 480.001ns -> 490.001ns]
+    write(15, 67108868, 2647121574, 0);  // [time: 490.001ns -> 500.001ns]
+    write(15, 67108869, 336117328, 0);  // [time: 500.001ns -> 510.001ns]
+    write(15, 67108870, 3984726565, 0);  // [time: 510.001ns -> 520.001ns]
+    write(15, 67108871, 104808193, 0);  // [time: 520.001ns -> 530.001ns]
+    write(15, 67108872, 2315494688, 0);  // [time: 530.001ns -> 540.001ns]
+    reset();  // [time: 900.002ns -> 910.002ns]
+    reset();  // [time: 910.002ns -> 920.002ns]
+    reset();  // [time: 920.002ns -> 930.002ns]
+    write(15, 67108865, 3997204021, 0);  // [time: 970.002ns -> 990.002ns]
+    write(15, 67108866, 666660673, 0);  // [time: 990.002ns -> 1000.002ns]
+    write(15, 67108867, 3910223084, 0);  // [time: 1000.002ns -> 1010.002ns]
+    write(15, 67108868, 1271405124, 0);  // [time: 1010.002ns -> 1020.002ns]
+    write(15, 67108869, 4236388983, 0);  // [time: 1020.002ns -> 1030.002ns]
+    write(15, 67108870, 1347016890, 0);  // [time: 1030.002ns -> 1040.002ns]
+    write(15, 67108871, 1337396640, 0);  // [time: 1040.002ns -> 1050.002ns]
+    write(15, 67108872, 3009712000, 0);  // [time: 1050.002ns -> 1060.002ns]
+    read(15, 67108865, 3997204021, 0);  // [time: 1060.002ns -> 1080.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_8_0.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_8_0.bi.expect
new file mode 100644
index 00000000..e937ca48
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_8_0.bi.expect
@@ -0,0 +1,37 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108866, 2821946881, 0);  // [time: 250ns -> 270ns]
+    read(15, 67108867, 4080087070, 0);  // [time: 270ns -> 280ns]
+    read(15, 67108868, 2243193877, 0);  // [time: 280ns -> 290ns]
+    read(15, 67108869, 2472849580, 0);  // [time: 290ns -> 300ns]
+    read(15, 67108870, 3565370026, 0);  // [time: 300ns -> 310ns]
+    read(15, 67108871, 890985600, 0);  // [time: 310ns -> 320ns]
+    read(15, 67108872, 4179549189, 0);  // [time: 320ns -> 330ns]
+    read(15, 67108873, 4158632492, 0);  // [time: 330ns -> 340ns]
+    reset();  // [time: 380.001ns -> 390.001ns]
+    reset();  // [time: 390.001ns -> 400.001ns]
+    reset();  // [time: 400.001ns -> 410.001ns]
+    write(15, 67108866, 3744957516, 0);  // [time: 450.001ns -> 470.001ns]
+    write(15, 67108867, 2300150418, 0);  // [time: 470.001ns -> 480.001ns]
+    write(15, 67108868, 2081940992, 0);  // [time: 480.001ns -> 490.001ns]
+    write(15, 67108869, 1697819148, 0);  // [time: 490.001ns -> 500.001ns]
+    write(15, 67108870, 602241333, 0);  // [time: 500.001ns -> 510.001ns]
+    write(15, 67108871, 2260552922, 0);  // [time: 510.001ns -> 520.001ns]
+    write(15, 67108872, 4251564751, 0);  // [time: 520.001ns -> 530.001ns]
+    write(15, 67108873, 3326548024, 0);  // [time: 530.001ns -> 540.001ns]
+    reset();  // [time: 900.002ns -> 910.002ns]
+    reset();  // [time: 910.002ns -> 920.002ns]
+    reset();  // [time: 920.002ns -> 930.002ns]
+    write(15, 67108866, 1044044861, 0);  // [time: 970.002ns -> 990.002ns]
+    write(15, 67108867, 4177314760, 0);  // [time: 990.002ns -> 1000.002ns]
+    write(15, 67108868, 4253662683, 0);  // [time: 1000.002ns -> 1010.002ns]
+    write(15, 67108869, 3575602093, 0);  // [time: 1010.002ns -> 1020.002ns]
+    write(15, 67108870, 667576938, 0);  // [time: 1020.002ns -> 1030.002ns]
+    write(15, 67108871, 3110079964, 0);  // [time: 1030.002ns -> 1040.002ns]
+    write(15, 67108872, 3758039968, 0);  // [time: 1040.002ns -> 1050.002ns]
+    write(15, 67108873, 3566852678, 0);  // [time: 1050.002ns -> 1060.002ns]
+    read(15, 67108866, 1044044861, 0);  // [time: 1060.002ns -> 1080.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_8_1.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_8_1.bi.expect
new file mode 100644
index 00000000..2c1254d3
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_8_1.bi.expect
@@ -0,0 +1,37 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108866, 1833423740, 0);  // [time: 250ns -> 270ns]
+    read(15, 67108867, 4073618608, 0);  // [time: 270ns -> 280ns]
+    read(15, 67108864, 3418745219, 0);  // [time: 280ns -> 290ns]
+    read(15, 67108865, 3757272308, 0);  // [time: 290ns -> 300ns]
+    read(15, 67108870, 1325530178, 0);  // [time: 300ns -> 310ns]
+    read(15, 67108871, 1451722922, 0);  // [time: 310ns -> 320ns]
+    read(15, 67108868, 1997677454, 0);  // [time: 320ns -> 330ns]
+    read(15, 67108869, 986005841, 0);  // [time: 330ns -> 340ns]
+    reset();  // [time: 380.001ns -> 390.001ns]
+    reset();  // [time: 390.001ns -> 400.001ns]
+    reset();  // [time: 400.001ns -> 410.001ns]
+    write(15, 67108866, 789975088, 0);  // [time: 450.001ns -> 470.001ns]
+    write(15, 67108867, 3746918692, 0);  // [time: 470.001ns -> 480.001ns]
+    write(15, 67108864, 410224063, 0);  // [time: 480.001ns -> 490.001ns]
+    write(15, 67108865, 864118294, 0);  // [time: 490.001ns -> 500.001ns]
+    write(15, 67108870, 908783806, 0);  // [time: 500.001ns -> 510.001ns]
+    write(15, 67108871, 2735695332, 0);  // [time: 510.001ns -> 520.001ns]
+    write(15, 67108868, 3991830963, 0);  // [time: 520.001ns -> 530.001ns]
+    write(15, 67108869, 3613974492, 0);  // [time: 530.001ns -> 540.001ns]
+    reset();  // [time: 900.002ns -> 910.002ns]
+    reset();  // [time: 910.002ns -> 920.002ns]
+    reset();  // [time: 920.002ns -> 930.002ns]
+    write(15, 67108866, 1515921225, 0);  // [time: 970.002ns -> 990.002ns]
+    write(15, 67108867, 104974629, 0);  // [time: 990.002ns -> 1000.002ns]
+    write(15, 67108864, 966302149, 0);  // [time: 1000.002ns -> 1010.002ns]
+    write(15, 67108865, 4157870389, 0);  // [time: 1010.002ns -> 1020.002ns]
+    write(15, 67108870, 2924407148, 0);  // [time: 1020.002ns -> 1030.002ns]
+    write(15, 67108871, 1538378206, 0);  // [time: 1030.002ns -> 1040.002ns]
+    write(15, 67108868, 60846013, 0);  // [time: 1040.002ns -> 1050.002ns]
+    write(15, 67108869, 3809194079, 0);  // [time: 1050.002ns -> 1060.002ns]
+    read(15, 67108866, 1515921225, 0);  // [time: 1060.002ns -> 1080.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_8_2.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_8_2.bi.expect
new file mode 100644
index 00000000..0e6c8c94
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_8_2.bi.expect
@@ -0,0 +1,37 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108866, 869832817, 0);  // [time: 250ns -> 270ns]
+    read(15, 67108867, 2976082601, 0);  // [time: 270ns -> 280ns]
+    read(15, 67108868, 373695501, 0);  // [time: 280ns -> 290ns]
+    read(15, 67108869, 2110838384, 0);  // [time: 290ns -> 300ns]
+    read(15, 67108870, 3556455435, 0);  // [time: 300ns -> 310ns]
+    read(15, 67108871, 1804567173, 0);  // [time: 310ns -> 320ns]
+    read(15, 67108864, 1187331577, 0);  // [time: 320ns -> 330ns]
+    read(15, 67108865, 1293993917, 0);  // [time: 330ns -> 340ns]
+    reset();  // [time: 380.001ns -> 390.001ns]
+    reset();  // [time: 390.001ns -> 400.001ns]
+    reset();  // [time: 400.001ns -> 410.001ns]
+    write(15, 67108866, 753581369, 0);  // [time: 450.001ns -> 470.001ns]
+    write(15, 67108867, 2300246917, 0);  // [time: 470.001ns -> 480.001ns]
+    write(15, 67108868, 3523846629, 0);  // [time: 480.001ns -> 490.001ns]
+    write(15, 67108869, 3751494934, 0);  // [time: 490.001ns -> 500.001ns]
+    write(15, 67108870, 504397671, 0);  // [time: 500.001ns -> 510.001ns]
+    write(15, 67108871, 3203321461, 0);  // [time: 510.001ns -> 520.001ns]
+    write(15, 67108864, 3801714021, 0);  // [time: 520.001ns -> 530.001ns]
+    write(15, 67108865, 654543662, 0);  // [time: 530.001ns -> 540.001ns]
+    reset();  // [time: 900.002ns -> 910.002ns]
+    reset();  // [time: 910.002ns -> 920.002ns]
+    reset();  // [time: 920.002ns -> 930.002ns]
+    write(15, 67108866, 1829143953, 0);  // [time: 970.002ns -> 990.002ns]
+    write(15, 67108867, 2746894674, 0);  // [time: 990.002ns -> 1000.002ns]
+    write(15, 67108868, 3464933947, 0);  // [time: 1000.002ns -> 1010.002ns]
+    write(15, 67108869, 3350075041, 0);  // [time: 1010.002ns -> 1020.002ns]
+    write(15, 67108870, 1123364414, 0);  // [time: 1020.002ns -> 1030.002ns]
+    write(15, 67108871, 3896266205, 0);  // [time: 1030.002ns -> 1040.002ns]
+    write(15, 67108864, 3668919860, 0);  // [time: 1040.002ns -> 1050.002ns]
+    write(15, 67108865, 177490457, 0);  // [time: 1050.002ns -> 1060.002ns]
+    read(15, 67108866, 1829143953, 0);  // [time: 1060.002ns -> 1080.002ns]
+}
diff --git a/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_8_3.bi.expect b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_8_3.bi.expect
new file mode 100644
index 00000000..847ef6a7
--- /dev/null
+++ b/tests/antmicro/sram_incrementing/expects/test_sram_incrementing_8_8_3.bi.expect
@@ -0,0 +1,37 @@
+// trace 0
+trace {
+    reset();  // [time: 20ns -> 30ns]
+    reset();  // [time: 30ns -> 40ns]
+    reset();  // [time: 40ns -> 50ns]
+    read(15, 67108866, 1070372987, 0);  // [time: 250ns -> 270ns]
+    read(15, 67108867, 2645947069, 0);  // [time: 270ns -> 280ns]
+    read(15, 67108868, 736643984, 0);  // [time: 280ns -> 290ns]
+    read(15, 67108869, 192007203, 0);  // [time: 290ns -> 300ns]
+    read(15, 67108870, 1925400290, 0);  // [time: 300ns -> 310ns]
+    read(15, 67108871, 1309609983, 0);  // [time: 310ns -> 320ns]
+    read(15, 67108872, 58503546, 0);  // [time: 320ns -> 330ns]
+    read(15, 67108873, 3861022989, 0);  // [time: 330ns -> 340ns]
+    reset();  // [time: 380.001ns -> 390.001ns]
+    reset();  // [time: 390.001ns -> 400.001ns]
+    reset();  // [time: 400.001ns -> 410.001ns]
+    write(15, 67108866, 1725708128, 0);  // [time: 450.001ns -> 470.001ns]
+    write(15, 67108867, 3760744365, 0);  // [time: 470.001ns -> 480.001ns]
+    write(15, 67108868, 3803789590, 0);  // [time: 480.001ns -> 490.001ns]
+    write(15, 67108869, 2647121574, 0);  // [time: 490.001ns -> 500.001ns]
+    write(15, 67108870, 336117328, 0);  // [time: 500.001ns -> 510.001ns]
+    write(15, 67108871, 3984726565, 0);  // [time: 510.001ns -> 520.001ns]
+    write(15, 67108872, 104808193, 0);  // [time: 520.001ns -> 530.001ns]
+    write(15, 67108873, 2315494688, 0);  // [time: 530.001ns -> 540.001ns]
+    reset();  // [time: 900.002ns -> 910.002ns]
+    reset();  // [time: 910.002ns -> 920.002ns]
+    reset();  // [time: 920.002ns -> 930.002ns]
+    write(15, 67108866, 3997204021, 0);  // [time: 970.002ns -> 990.002ns]
+    write(15, 67108867, 666660673, 0);  // [time: 990.002ns -> 1000.002ns]
+    write(15, 67108868, 3910223084, 0);  // [time: 1000.002ns -> 1010.002ns]
+    write(15, 67108869, 1271405124, 0);  // [time: 1010.002ns -> 1020.002ns]
+    write(15, 67108870, 4236388983, 0);  // [time: 1020.002ns -> 1030.002ns]
+    write(15, 67108871, 1347016890, 0);  // [time: 1030.002ns -> 1040.002ns]
+    write(15, 67108872, 1337396640, 0);  // [time: 1040.002ns -> 1050.002ns]
+    write(15, 67108873, 3009712000, 0);  // [time: 1050.002ns -> 1060.002ns]
+    read(15, 67108866, 3997204021, 0);  // [time: 1060.002ns -> 1080.002ns]
+}
diff --git a/tests/brave_new_world_francis/expects/bit_truncation_fft.bi.expect b/tests/brave_new_world_francis/expects/bit_truncation_fft.bi.expect
new file mode 100644
index 00000000..2861938d
--- /dev/null
+++ b/tests/brave_new_world_francis/expects/bit_truncation_fft.bi.expect
@@ -0,0 +1,4 @@
+// trace 0
+trace {
+    bit_truncation_fft(8386560, 2047);
+}
diff --git a/tests/brave_new_world_francis/expects/bit_truncation_sha.bi.expect b/tests/brave_new_world_francis/expects/bit_truncation_sha.bi.expect
new file mode 100644
index 00000000..52f5d64f
--- /dev/null
+++ b/tests/brave_new_world_francis/expects/bit_truncation_sha.bi.expect
@@ -0,0 +1,4 @@
+// trace 0
+trace {
+    bit_truncation_sha(4398046511104, 68719476736);
+}
diff --git a/tests/brave_new_world_francis/expects/ftu_sha.bi.expect b/tests/brave_new_world_francis/expects/ftu_sha.bi.expect
new file mode 100644
index 00000000..bf9d06bc
--- /dev/null
+++ b/tests/brave_new_world_francis/expects/ftu_sha.bi.expect
@@ -0,0 +1,4 @@
+// trace 0
+trace {
+    failure_to_update_sha();
+}
diff --git a/tests/brave_new_world_francis/expects/signal_async.bi.expect b/tests/brave_new_world_francis/expects/signal_async.bi.expect
new file mode 100644
index 00000000..ccd9f567
--- /dev/null
+++ b/tests/brave_new_world_francis/expects/signal_async.bi.expect
@@ -0,0 +1,4 @@
+// trace 0
+trace {
+    signal_async(6, 7);
+}
diff --git a/tests/brave_new_world_francis/expects/use_without_valid.bi.expect b/tests/brave_new_world_francis/expects/use_without_valid.bi.expect
new file mode 100644
index 00000000..1b5733f2
--- /dev/null
+++ b/tests/brave_new_world_francis/expects/use_without_valid.bi.expect
@@ -0,0 +1,4 @@
+// trace 0
+trace {
+    use_without_valid(5, 5);
+}
diff --git a/tests/ethmac/expects/ethmac_wishbone_manager.bi.expect b/tests/ethmac/expects/ethmac_wishbone_manager.bi.expect
new file mode 100644
index 00000000..102c1bf9
--- /dev/null
+++ b/tests/ethmac/expects/ethmac_wishbone_manager.bi.expect
@@ -0,0 +1,8 @@
+error: the following required arguments were not provided:
+  --wave <WAVE_FILE>
+
+Usage: bi --wave <WAVE_FILE> --show-waveform-time --color <COLOR_CHOICE> --protocol <PROTOCOLS_FILE> --instances <INSTANCES>... --sample-posedge <SIGNAL_TO_SAMPLE_ON_RISING_EDGE> --time-unit <TIME_UNIT>
+
+For more information, try '--help'.
+---CODE---
+2
diff --git a/tests/ethmac/expects/ethmac_wishbone_subordinate.bi.expect b/tests/ethmac/expects/ethmac_wishbone_subordinate.bi.expect
new file mode 100644
index 00000000..102c1bf9
--- /dev/null
+++ b/tests/ethmac/expects/ethmac_wishbone_subordinate.bi.expect
@@ -0,0 +1,8 @@
+error: the following required arguments were not provided:
+  --wave <WAVE_FILE>
+
+Usage: bi --wave <WAVE_FILE> --show-waveform-time --color <COLOR_CHOICE> --protocol <PROTOCOLS_FILE> --instances <INSTANCES>... --sample-posedge <SIGNAL_TO_SAMPLE_ON_RISING_EDGE> --time-unit <TIME_UNIT>
+
+For more information, try '--help'.
+---CODE---
+2
diff --git a/tests/fifo/expects/fifo.bi.expect b/tests/fifo/expects/fifo.bi.expect
new file mode 100644
index 00000000..9ecea916
--- /dev/null
+++ b/tests/fifo/expects/fifo.bi.expect
@@ -0,0 +1,10 @@
+// trace 0
+trace {
+    reset();
+    push(3);
+    push(4);
+    idle();
+    pop(3);
+    pop(4);
+    push(1995394993);
+}
diff --git a/tests/fifo/expects/push_pop_identity.bi.expect b/tests/fifo/expects/push_pop_identity.bi.expect
new file mode 100644
index 00000000..7b7038ac
--- /dev/null
+++ b/tests/fifo/expects/push_pop_identity.bi.expect
@@ -0,0 +1,9 @@
+// trace 0
+trace {
+    reset();
+    push(2);
+    pop(2);
+    idle();
+    push(3);
+    pop(3);
+}
diff --git a/tests/fifo/expects/push_pop_loop_empty.bi.expect b/tests/fifo/expects/push_pop_loop_empty.bi.expect
new file mode 100644
index 00000000..52c71229
--- /dev/null
+++ b/tests/fifo/expects/push_pop_loop_empty.bi.expect
@@ -0,0 +1,4 @@
+panicked at bi/src/bi.rs:628:21:
+[pop_n_times@00!] Cannot fork at step zero!
+---CODE---
+101
diff --git a/tests/fifo/expects/push_pop_loop_not_empty.bi.expect b/tests/fifo/expects/push_pop_loop_not_empty.bi.expect
new file mode 100644
index 00000000..52c71229
--- /dev/null
+++ b/tests/fifo/expects/push_pop_loop_not_empty.bi.expect
@@ -0,0 +1,4 @@
+panicked at bi/src/bi.rs:628:21:
+[pop_n_times@00!] Cannot fork at step zero!
+---CODE---
+101
diff --git a/tests/fpga-debugging/axi-burst-s4/expects/s4_buggy.bi.expect b/tests/fpga-debugging/axi-burst-s4/expects/s4_buggy.bi.expect
new file mode 100644
index 00000000..b3c96b02
--- /dev/null
+++ b/tests/fpga-debugging/axi-burst-s4/expects/s4_buggy.bi.expect
@@ -0,0 +1,12 @@
+// trace 0
+trace {
+}
+error: [write_burst@95] executing step 67 of the transaction: 0 != 1
+   ┌─ tests/fpga-debugging/axi-burst-s4/s4_buggy.prot:63:5
+   │
+63 │     DUT.m_wlast := 1'b1;
+   │     ^^^^^^^^^^^^^^^^^^^^ [write_burst@95] executing step 67 of the transaction: 0 != 1
+
+Error: "Monitor failed"
+---CODE---
+1
diff --git a/tests/fpga-debugging/axi-burst-s4/expects/s4_fixed.bi.expect b/tests/fpga-debugging/axi-burst-s4/expects/s4_fixed.bi.expect
new file mode 100644
index 00000000..e92193ec
--- /dev/null
+++ b/tests/fpga-debugging/axi-burst-s4/expects/s4_fixed.bi.expect
@@ -0,0 +1,4 @@
+// trace 0
+trace {
+    write_burst(1152, 3700821297, 15);  // [time: 0.19ns -> 0.332ns]
+}
diff --git a/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy.bi.expect b/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy.bi.expect
new file mode 100644
index 00000000..523bbb01
--- /dev/null
+++ b/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy.bi.expect
@@ -0,0 +1,29 @@
+// trace 0
+trace {
+    idle();  // [time: 0ns -> 25ns]
+    write(64, 2147483648, 0, 0);  // [time: 25ns -> 100ns]
+}
+// trace 0
+trace {
+    idle();  // [time: 0ns -> 25ns]
+}
+error: [read_v2@11?1!] executing step 3 of the transaction: 1 != 0
+    ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy.prot:169:5
+    │
+169 │     assert_eq(DUT.S_AXI_ARREADY, 1'b0);
+    │     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@11?1!] executing step 3 of the transaction: 1 != 0
+
+
+// trace 1
+trace {
+    idle();  // [time: 0ns -> 25ns]
+}
+error: [read_v2@11?2?] executing step 3 of the transaction: 1 != 0
+    ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy.prot:163:9
+    │
+163 │         DUT.S_AXI_RREADY := 1'b0;
+    │         ^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@11?2?] executing step 3 of the transaction: 1 != 0
+
+Error: "Monitor failed"
+---CODE---
+1
diff --git a/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy_workload_1.bi.expect b/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy_workload_1.bi.expect
new file mode 100644
index 00000000..58ee712c
--- /dev/null
+++ b/tests/fpga-debugging/axi-lite-s1/expects/s1_buggy_workload_1.bi.expect
@@ -0,0 +1,62 @@
+// trace 0
+trace {
+    idle();  // [time: 0ns -> 25ns]
+    write_stalled(64, 2147483648, 0);  // [time: 25ns -> 75ns]
+    write_stalled(64, 2147483648, 0);  // [time: 75ns -> 100ns]
+}
+
+// trace 1
+trace {
+    write_stalled(64, 2147483648, 1);  // [time: 0ns -> 75ns]
+    write_stalled(64, 2147483648, 0);  // [time: 75ns -> 100ns]
+}
+// trace 0
+trace {
+    idle();  // [time: 0ns -> 25ns]
+    read_v1(64, 0);  // [time: 25ns -> 100ns]
+}
+error: [read_v2@4] executing step 0 of the transaction: 0 != 1
+    ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot:161:5
+    │
+161 │     DUT.S_AXI_ARVALID := 1'b1;
+    │     ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@4] executing step 0 of the transaction: 0 != 1
+
+
+// trace 1
+trace {
+    idle();  // [time: 0ns -> 25ns]
+    read_v1(64, 0);  // [time: 25ns -> 100ns]
+}
+
+// trace 2
+trace {
+    idle();  // [time: 0ns -> 25ns]
+    read_v1(64, 0);  // [time: 25ns -> 100ns]
+}
+error: [idle@4] executing step 0 of the transaction: 1 != 0
+    ┌─ tests/fpga-debugging/axi-lite-s1/s1_buggy_workload_1.prot:108:5
+    │
+108 │     DUT.S_AXI_RREADY  := 1'b0;
+    │     ^^^^^^^^^^^^^^^^^^^^^^^^^^ [idle@4] executing step 0 of the transaction: 1 != 0
+
+
+// trace 3
+trace {
+    idle();  // [time: 0ns -> 25ns]
+    read_v2(64, 0, 0);  // [time: 25ns -> 100ns]
+}
+
+// trace 4
+trace {
+    idle();  // [time: 0ns -> 25ns]
+    read_v2(64, 0, 0);  // [time: 25ns -> 100ns]
+}
+
+// trace 5
+trace {
+    idle();  // [time: 0ns -> 25ns]
+    read_v2(64, 0, 0);  // [time: 25ns -> 100ns]
+}
+Error: "Monitor failed"
+---CODE---
+1
diff --git a/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed.bi.expect b/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed.bi.expect
new file mode 100644
index 00000000..ecf4be3e
--- /dev/null
+++ b/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed.bi.expect
@@ -0,0 +1,12 @@
+// trace 0
+trace {
+    idle();  // [time: 0ns -> 25ns]
+    write(64, 2147483648, 0, 0);  // [time: 25ns -> 100ns]
+}
+// trace 0
+trace {
+    idle();  // [time: 0ns -> 25ns]
+    read_v2(68, 0, 1);  // [time: 25ns -> 125ns]
+    idle();  // [time: 125ns -> 150ns]
+    idle();  // [time: 150ns -> 150ns]
+}
diff --git a/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed_workload_1.bi.expect b/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed_workload_1.bi.expect
new file mode 100644
index 00000000..5d803553
--- /dev/null
+++ b/tests/fpga-debugging/axi-lite-s1/expects/s1_fixed_workload_1.bi.expect
@@ -0,0 +1,54 @@
+// trace 0
+trace {
+    idle();  // [time: 0ns -> 25ns]
+}
+// trace 0
+trace {
+    idle();  // [time: 0ns -> 25ns]
+    read_v1(64, 0);  // [time: 25ns -> 100ns]
+}
+error: [read_v2@4] executing step 0 of the transaction: 0 != 1
+    ┌─ tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot:161:5
+    │
+161 │     DUT.S_AXI_ARVALID := 1'b1;
+    │     ^^^^^^^^^^^^^^^^^^^^^^^^^^ [read_v2@4] executing step 0 of the transaction: 0 != 1
+
+
+// trace 1
+trace {
+    idle();  // [time: 0ns -> 25ns]
+    read_v1(64, 0);  // [time: 25ns -> 100ns]
+}
+
+// trace 2
+trace {
+    idle();  // [time: 0ns -> 25ns]
+    read_v1(64, 0);  // [time: 25ns -> 100ns]
+}
+error: [idle@4] executing step 0 of the transaction: 1 != 0
+    ┌─ tests/fpga-debugging/axi-lite-s1/s1_fixed_workload_1.prot:108:5
+    │
+108 │     DUT.S_AXI_RREADY  := 1'b0;
+    │     ^^^^^^^^^^^^^^^^^^^^^^^^^^ [idle@4] executing step 0 of the transaction: 1 != 0
+
+
+// trace 3
+trace {
+    idle();  // [time: 0ns -> 25ns]
+    read_v2(64, 0, 0);  // [time: 25ns -> 100ns]
+}
+
+// trace 4
+trace {
+    idle();  // [time: 0ns -> 25ns]
+    read_v2(64, 0, 0);  // [time: 25ns -> 100ns]
+}
+
+// trace 5
+trace {
+    idle();  // [time: 0ns -> 25ns]
+    read_v2(64, 0, 0);  // [time: 25ns -> 100ns]
+}
+Error: "Monitor failed"
+---CODE---
+1
diff --git a/tests/fpga-debugging/axi-lite-s1/s1_alt.prot b/tests/fpga-debugging/axi-lite-s1/s1_alt.prot
new file mode 100644
index 00000000..2c0b19d5
--- /dev/null
+++ b/tests/fpga-debugging/axi-lite-s1/s1_alt.prot
@@ -0,0 +1,189 @@
+
+struct Subordinate {
+    // Active-low reset
+    in  S_AXI_ARESETN: u1,
+
+    // Write address channel
+    in  S_AXI_AWVALID: u1,
+    in  S_AXI_AWADDR: u7,
+    out S_AXI_AWREADY: u1,
+
+    // Write data channel
+    in  S_AXI_WVALID: u1,
+    in  S_AXI_WDATA: u32,
+    out S_AXI_WREADY: u1,
+
+    // Write response channel
+    in  S_AXI_BREADY: u1,
+    out S_AXI_BVALID: u1,
+    out S_AXI_BRESP: u2,
+
+    // Read address channel
+    in  S_AXI_ARVALID: u1,
+    in  S_AXI_ARADDR: u7,
+    out S_AXI_ARREADY: u1,
+
+    // Read data channel
+    in  S_AXI_RREADY: u1,
+    out S_AXI_RVALID: u1,
+    out S_AXI_RDATA: u32,
+}
+
+prot reset<DUT: Subordinate>() {
+    // Reset is active-low
+    DUT.S_AXI_ARESETN := 1'b0;
+
+    // Set valid = 0 for the write data / write address / read address channels
+    DUT.S_AXI_AWVALID := 1'b0;
+    DUT.S_AXI_WVALID  := 1'b0;
+    DUT.S_AXI_ARVALID := 1'b0;
+
+    // Set ready = 0 for the write response / read data channels
+    DUT.S_AXI_BREADY  := 1'b0;
+    DUT.S_AXI_RREADY  := 1'b0;
+
+    step();
+}
+
+
+#[idle]
+prot idle<DUT: Subordinate>() {
+    // Reset is active-low, so we set reset = 1 here
+    // to indicate that the DUT is *not* reset during an `idle` transaction
+    DUT.S_AXI_ARESETN := 1'b1;
+
+    // No requests on either address channel
+    DUT.S_AXI_AWVALID := 1'b0;
+    DUT.S_AXI_AWADDR  := X;
+    DUT.S_AXI_WVALID  := 1'b0;
+    DUT.S_AXI_WDATA   := X;
+    DUT.S_AXI_ARVALID := 1'b0;
+    DUT.S_AXI_ARADDR  := X;
+
+    // No transfer on the read data channel.
+    // (Note: BREADY is deliberately left unconstrained: the workload
+    // testbenches keep BREADY high after their last write completes.)
+    DUT.S_AXI_RREADY  := 1'b0;
+
+    step();
+}
+
+// // Note: this is still WIP (this is simpler than the protocol we discussed
+// // yesterday for ease of debugging for now)
+// prot write<DUT: Subordinate>(addr: u7, data: u32, resp: u2, n: uint) {
+//     repeat n iterations {
+//         DUT.S_AXI_AWVALID := 1'b0;
+//         step();
+//     }
+//     DUT.S_AXI_AWVALID := 1'b1;
+//     DUT.S_AXI_AWADDR := addr;
+
+//     DUT.S_AXI_WVALID := 1'b1;
+//     DUT.S_AXI_WDATA := data;
+
+//     // technically this should be `while !AWREADY && !WREADY { step() }`
+//     // but our DSL doesn't have `&&`. Without loss of generality,
+//     // we wait for AWREADY to become 1
+//     while !(DUT.S_AXI_AWREADY == 1'b1) {
+//         step();   
+//     }
+//     // Assuming AWREADY & WREADY become 1 together 
+//     // (this is allowed in the AXI spec and the DUT exhibits this behavior)
+//     assert_eq(DUT.S_AXI_WREADY, 1'b1); 
+    
+//     step();
+
+//     // Remove constraints on AWVALID and WVALID
+//     DUT.S_AXI_AWVALID := X;
+//     DUT.S_AXI_WVALID := X;
+
+//     // Wait for BVALID to become 1
+//     while !(DUT.S_AXI_BVALID == 1'b1) {
+//         step();
+//     }
+//     // BVALID is now 1
+//     // Wait for some no. of cycles before BREADY becomes 1
+//     repeat n iterations {
+//         step();
+//         // BVALID must remain stable after it becomes 1
+//         assert_eq(DUT.S_AXI_BVALID, 1'b1);
+//     }
+//     DUT.S_AXI_BREADY := 1'b1;
+//     assert_eq(DUT.S_AXI_BRESP, resp);
+//     step();
+// }
+
+// RREADY is asserted before RVALID 
+// (This is allowed in section A2.3.2.2 of the AXI spec)
+prot read_v1<DUT: Subordinate>(addr: u7, data: u32) {
+    DUT.S_AXI_ARVALID := 1'b1;
+    DUT.S_AXI_ARADDR := addr;
+    
+    // Wait for ARREADY to become 1
+    while !(DUT.S_AXI_ARREADY == 1'b1) {
+        step();
+    }
+    // ARREADY is now 1
+
+    step();
+
+    assert_eq(DUT.S_AXI_ARREADY, 1'b0);
+    DUT.S_AXI_RREADY := 1'b1;
+
+    // Wait for RVALID to become 1
+    // AXI spec says that ARVALID & ARREADY must both be 1
+    // before RVALID can be asserted (A2.3.2.2)
+    while !(DUT.S_AXI_RVALID == 1'b1) {
+        step();
+        assert_eq(DUT.S_AXI_ARREADY, 1'b0);
+    }
+    assert_eq(DUT.S_AXI_RDATA, data);
+    step();
+}
+
+// RVALID is asserted before RREADY
+// (This is allowed in section A2.3.2.2 of the AXI spec)
+prot read_v2<DUT: Subordinate>(addr: u7, data: u32, n: uint) {
+    DUT.S_AXI_ARVALID := 1'b1;
+    DUT.S_AXI_ARADDR := addr;
+    
+    // Wait for ARREADY to become 1
+    while !(DUT.S_AXI_ARREADY == 1'b1) {
+        step();
+    }
+    // ARREADY is now 1
+
+    step();
+
+    fork();
+   
+    // Wait for RVALID to become 1
+    // AXI spec says that ARVALID & ARREADY must both be 1
+    // before RVALID can be asserted (A2.3.2.2)
+    while !(DUT.S_AXI_RVALID == 1'b1) {
+        step();
+    }
+    // RVALID is now 1
+
+    // While we are waiting for RREADY to become 1, 
+    // another read address request cannot arrive 
+    // (i.e. ARREADY has to remain 0). That is, we have to acknowledge
+    // the read data before another read address request can arrive.
+    assert_eq(DUT.S_AXI_ARREADY, 1'b0);
+
+    // Wait until RREADY becomes 1
+    repeat n iterations {
+        DUT.S_AXI_RREADY := 1'b0;
+        // Check that RVALID remains stable
+        assert_eq(DUT.S_AXI_RVALID, 1'b1);
+        step();
+    }
+    // Check that ARREADY remains 0 (i.e. no conflicting read address request)
+    assert_eq(DUT.S_AXI_ARREADY, 1'b0);
+
+    // Perform data transfer on the read data channel
+    DUT.S_AXI_RREADY := 1'b1;
+    assert_eq(DUT.S_AXI_RDATA, data);
+
+    step();
+}
\ No newline at end of file
diff --git a/tests/fpga-debugging/axi-stream-s2/expects/s2_buggy.bi.expect b/tests/fpga-debugging/axi-stream-s2/expects/s2_buggy.bi.expect
new file mode 100644
index 00000000..a37a8103
--- /dev/null
+++ b/tests/fpga-debugging/axi-stream-s2/expects/s2_buggy.bi.expect
@@ -0,0 +1,17 @@
+// trace 0
+trace {
+    reset();  // [time: 0ns -> 12.5ns]
+    wait_for_data();  // [time: 337.5ns -> 362.5ns]
+    wait_for_data();  // [time: 387.5ns -> 412.5ns]
+    wait_for_data();  // [time: 512.5ns -> 537.5ns]
+    wait_for_data();  // [time: 537.5ns -> 562.5ns]
+    wait_for_data();  // [time: 612.5ns -> 637.5ns]
+    wait_for_data();  // [time: 787.5ns -> 812.5ns]
+    wait_for_data();  // [time: 837.5ns -> 862.5ns]
+    recv(1);  // [time: 862.5ns -> 887.5ns]
+    recv(2);  // [time: 887.5ns -> 912.5ns]
+    recv(3);  // [time: 912.5ns -> 937.5ns]
+    recv(4);  // [time: 937.5ns -> 962.5ns]
+    recv(5);  // [time: 962.5ns -> 987.5ns]
+    recv(6);  // [time: 987.5ns -> 1012.5ns]
+}
diff --git a/tests/fpga-debugging/axi-stream-s2/expects/s2_fixed.bi.expect b/tests/fpga-debugging/axi-stream-s2/expects/s2_fixed.bi.expect
new file mode 100644
index 00000000..9e4f85a7
--- /dev/null
+++ b/tests/fpga-debugging/axi-stream-s2/expects/s2_fixed.bi.expect
@@ -0,0 +1,40 @@
+// trace 0
+trace {
+    reset();  // [time: 0ns -> 12.5ns]
+    wait_for_data();  // [time: 337.5ns -> 362.5ns]
+    wait_for_data();  // [time: 387.5ns -> 412.5ns]
+    wait_for_data();  // [time: 512.5ns -> 537.5ns]
+    wait_for_data();  // [time: 537.5ns -> 562.5ns]
+    wait_for_data();  // [time: 612.5ns -> 637.5ns]
+    wait_for_data();  // [time: 787.5ns -> 812.5ns]
+    wait_for_data();  // [time: 837.5ns -> 862.5ns]
+    recv(1);  // [time: 862.5ns -> 887.5ns]
+    recv(2);  // [time: 887.5ns -> 912.5ns]
+    recv(3);  // [time: 912.5ns -> 937.5ns]
+    recv(4);  // [time: 937.5ns -> 962.5ns]
+    recv(5);  // [time: 962.5ns -> 987.5ns]
+    recv(6);  // [time: 987.5ns -> 1012.5ns]
+    stall(7, 0);  // [time: 1012.5ns -> 1062.5ns]
+    reset();  // [time: 1062.5ns -> 1087.5ns]
+    reset();  // [time: 1087.5ns -> 1087.5ns]
+}
+
+// trace 1
+trace {
+    reset();  // [time: 0ns -> 12.5ns]
+    wait_for_data();  // [time: 337.5ns -> 362.5ns]
+    wait_for_data();  // [time: 387.5ns -> 412.5ns]
+    wait_for_data();  // [time: 512.5ns -> 537.5ns]
+    wait_for_data();  // [time: 537.5ns -> 562.5ns]
+    wait_for_data();  // [time: 612.5ns -> 637.5ns]
+    wait_for_data();  // [time: 787.5ns -> 812.5ns]
+    wait_for_data();  // [time: 837.5ns -> 862.5ns]
+    recv(1);  // [time: 862.5ns -> 887.5ns]
+    recv(2);  // [time: 887.5ns -> 912.5ns]
+    recv(3);  // [time: 912.5ns -> 937.5ns]
+    recv(4);  // [time: 937.5ns -> 962.5ns]
+    recv(5);  // [time: 962.5ns -> 987.5ns]
+    recv(6);  // [time: 987.5ns -> 1012.5ns]
+    reset();  // [time: 1062.5ns -> 1087.5ns]
+    reset();  // [time: 1087.5ns -> 1087.5ns]
+}
diff --git a/tests/fpga-debugging/axis-adapter-s3/expects/s3_buggy.bi.expect b/tests/fpga-debugging/axis-adapter-s3/expects/s3_buggy.bi.expect
new file mode 100644
index 00000000..204d6b80
--- /dev/null
+++ b/tests/fpga-debugging/axis-adapter-s3/expects/s3_buggy.bi.expect
@@ -0,0 +1,13 @@
+// trace 0
+trace {
+    reset();  // [time: 0ns -> 25ns]
+    wait_for_data();  // [time: 25ns -> 50ns]
+    wait_for_data();  // [time: 50ns -> 75ns]
+    wait_for_data();  // [time: 75ns -> 100ns]
+    recv(205);  // [time: 100ns -> 125ns]
+    recv(171);  // [time: 125ns -> 150ns]
+    recv(205);  // [time: 150ns -> 175ns]
+    recv(171);  // [time: 175ns -> 200ns]
+    recv(205);  // [time: 200ns -> 225ns]
+    recv_last(171);  // [time: 225ns -> 225ns]
+}
diff --git a/tests/fpga-debugging/axis-adapter-s3/expects/s3_fixed.bi.expect b/tests/fpga-debugging/axis-adapter-s3/expects/s3_fixed.bi.expect
new file mode 100644
index 00000000..5cbf6070
--- /dev/null
+++ b/tests/fpga-debugging/axis-adapter-s3/expects/s3_fixed.bi.expect
@@ -0,0 +1,12 @@
+// trace 0
+trace {
+    reset();  // [time: 0ns -> 25ns]
+    wait_for_data();  // [time: 25ns -> 50ns]
+    wait_for_data();  // [time: 50ns -> 75ns]
+    wait_for_data();  // [time: 75ns -> 100ns]
+    recv(205);  // [time: 100ns -> 125ns]
+    recv(171);  // [time: 125ns -> 150ns]
+    recv(205);  // [time: 150ns -> 175ns]
+    recv(171);  // [time: 175ns -> 200ns]
+    recv_last(205);  // [time: 200ns -> 200ns]
+}
diff --git a/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.bi.expect b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.bi.expect
new file mode 100644
index 00000000..3e619433
--- /dev/null
+++ b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_buggy.bi.expect
@@ -0,0 +1,47 @@
+// trace 0
+trace {
+    reset();  // [time: 0ns -> 25ns]
+    idle();  // [time: 25ns -> 50ns]
+    push(1);  // [time: 50ns -> 75ns]
+    push(2);  // [time: 75ns -> 100ns]
+    push(3);  // [time: 100ns -> 125ns]
+    push(4);  // [time: 125ns -> 150ns]
+    push(5);  // [time: 150ns -> 175ns]
+    push(6);  // [time: 175ns -> 200ns]
+    push(7);  // [time: 200ns -> 200ns]
+}
+// trace 0
+trace {
+    reset();  // [time: 0ns -> 25ns]
+}
+error: [reset@1] executing step 0 of the transaction: 0 != 1
+    ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot:115:5
+    │
+115 │     DUT.rst := 1'b1;
+    │     ^^^^^^^^^^^^^^^^ [reset@1] executing step 0 of the transaction: 0 != 1
+
+
+// trace 1
+trace {
+    reset();  // [time: 0ns -> 25ns]
+}
+error: [idle@1] executing step 0 of the transaction: 1 != 0
+   ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot:97:5
+   │
+97 │     DUT.m_axis_tready := 1'b0;
+   │     ^^^^^^^^^^^^^^^^^^^^^^^^^^ [idle@1] executing step 0 of the transaction: 1 != 0
+
+
+// trace 2
+trace {
+    reset();  // [time: 0ns -> 25ns]
+}
+error: [pop@1] executing step 0 of the transaction: 0 != 1
+   ┌─ tests/fpga-debugging/axis-async-fifo-c4/c4_buggy.prot:62:5
+   │
+62 │     assert_eq(DUT.m_axis_tvalid, 1'b1);
+   │     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ [pop@1] executing step 0 of the transaction: 0 != 1
+
+Error: "Monitor failed"
+---CODE---
+1
diff --git a/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_fixed.bi.expect b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_fixed.bi.expect
new file mode 100644
index 00000000..49910681
--- /dev/null
+++ b/tests/fpga-debugging/axis-async-fifo-c4/expects/c4_fixed.bi.expect
@@ -0,0 +1,26 @@
+// trace 0
+trace {
+    reset();  // [time: 0ns -> 25ns]
+    idle();  // [time: 25ns -> 50ns]
+    push(1);  // [time: 50ns -> 75ns]
+    push(2);  // [time: 75ns -> 100ns]
+    push(3);  // [time: 100ns -> 150ns]
+    push(4);  // [time: 150ns -> 175ns]
+    push(5);  // [time: 175ns -> 200ns]
+    push(6);  // [time: 200ns -> 225ns]
+    push(7);  // [time: 225ns -> 250ns]
+    push(8);  // [time: 250ns -> 250ns]
+}
+// trace 0
+trace {
+    reset();  // [time: 0ns -> 25ns]
+    idle();  // [time: 25ns -> 50ns]
+    idle();  // [time: 50ns -> 75ns]
+    idle();  // [time: 75ns -> 100ns]
+    pop(2);  // [time: 100ns -> 150ns]
+    pop(3);  // [time: 125ns -> 175ns]
+    pop(4);  // [time: 150ns -> 200ns]
+    pop(5);  // [time: 175ns -> 225ns]
+    pop(6);  // [time: 200ns -> 250ns]
+    pop(7);  // [time: 225ns -> 250ns]
+}
diff --git a/tests/fpga-debugging/axis-fifo-d11/expects/d11_buggy.bi.expect b/tests/fpga-debugging/axis-fifo-d11/expects/d11_buggy.bi.expect
new file mode 100644
index 00000000..c0878918
--- /dev/null
+++ b/tests/fpga-debugging/axis-fifo-d11/expects/d11_buggy.bi.expect
@@ -0,0 +1,17 @@
+// trace 0
+trace {
+    reset();  // [time: 0ns -> 25ns]
+    push(1);  // [time: 25ns -> 50ns]
+    push(1);  // [time: 50ns -> 75ns]
+    push(2);  // [time: 75ns -> 100ns]
+    push(4);  // [time: 100ns -> 125ns]
+    push(5);  // [time: 125ns -> 150ns]
+    push(6);  // [time: 150ns -> 175ns]
+    push(6);  // [time: 175ns -> 200ns]
+    push(6);  // [time: 200ns -> 225ns]
+    push(6);  // [time: 225ns -> 250ns]
+    push(6);  // [time: 250ns -> 275ns]
+    push(6);  // [time: 275ns -> 300ns]
+    reset();  // [time: 300ns -> 325ns]
+    push(6);  // [time: 325ns -> 325ns]
+}
diff --git a/tests/fpga-debugging/axis-fifo-d11/expects/d11_fixed.bi.expect b/tests/fpga-debugging/axis-fifo-d11/expects/d11_fixed.bi.expect
new file mode 100644
index 00000000..ccbf4bd8
--- /dev/null
+++ b/tests/fpga-debugging/axis-fifo-d11/expects/d11_fixed.bi.expect
@@ -0,0 +1,21 @@
+// trace 0
+trace {
+    reset();  // [time: 0ns -> 25ns]
+    push(1);  // [time: 25ns -> 50ns]
+    push(1);  // [time: 50ns -> 75ns]
+    push(2);  // [time: 75ns -> 100ns]
+    push(4);  // [time: 100ns -> 125ns]
+    push(5);  // [time: 125ns -> 150ns]
+    push(6);  // [time: 150ns -> 175ns]
+    push(6);  // [time: 175ns -> 200ns]
+    push(6);  // [time: 200ns -> 225ns]
+    push(6);  // [time: 225ns -> 250ns]
+    push(6);  // [time: 250ns -> 275ns]
+    push(6);  // [time: 275ns -> 300ns]
+    reset();  // [time: 300ns -> 325ns]
+    push(6);  // [time: 325ns -> 350ns]
+    push(6);  // [time: 350ns -> 375ns]
+    push(7);  // [time: 375ns -> 400ns]
+    push(7);  // [time: 400ns -> 425ns]
+    push(7);  // [time: 425ns -> 425ns]
+}
diff --git a/tests/fpga-debugging/axis-fifo-d12/expects/d12_buggy.bi.expect b/tests/fpga-debugging/axis-fifo-d12/expects/d12_buggy.bi.expect
new file mode 100644
index 00000000..008e0943
--- /dev/null
+++ b/tests/fpga-debugging/axis-fifo-d12/expects/d12_buggy.bi.expect
@@ -0,0 +1,16 @@
+// trace 0
+trace {
+    reset();  // [time: 0ns -> 25ns]
+    push(1);  // [time: 25ns -> 50ns]
+    push(1);  // [time: 50ns -> 75ns]
+    push(2);  // [time: 75ns -> 100ns]
+    push(3);  // [time: 100ns -> 125ns]
+    push(4);  // [time: 125ns -> 150ns]
+    push(5);  // [time: 150ns -> 175ns]
+    push(6);  // [time: 175ns -> 200ns]
+    pop(1);  // [time: 200ns -> 250ns]
+    push_and_pop(6, 2);  // [time: 225ns -> 275ns]
+    push_and_pop(6, 3);  // [time: 250ns -> 300ns]
+    push_and_pop(7, 3);  // [time: 275ns -> 325ns]
+    push_and_pop(7, 5);  // [time: 300ns -> 350ns]
+}
diff --git a/tests/fpga-debugging/axis-fifo-d12/expects/d12_fixed.bi.expect b/tests/fpga-debugging/axis-fifo-d12/expects/d12_fixed.bi.expect
new file mode 100644
index 00000000..4eeb0094
--- /dev/null
+++ b/tests/fpga-debugging/axis-fifo-d12/expects/d12_fixed.bi.expect
@@ -0,0 +1,15 @@
+// trace 0
+trace {
+    reset();  // [time: 0ns -> 25ns]
+    push(1);  // [time: 25ns -> 50ns]
+    push(1);  // [time: 50ns -> 75ns]
+    push(2);  // [time: 75ns -> 100ns]
+    push(3);  // [time: 100ns -> 125ns]
+    push(4);  // [time: 125ns -> 150ns]
+    push(5);  // [time: 150ns -> 175ns]
+    push(6);  // [time: 175ns -> 200ns]
+    pop(1);  // [time: 200ns -> 250ns]
+    push_and_pop(6, 2);  // [time: 225ns -> 275ns]
+    push_and_pop(6, 3);  // [time: 250ns -> 300ns]
+    push_and_pop(7, 3);  // [time: 275ns -> 325ns]
+}
diff --git a/tests/fpga-debugging/axis-fifo-d4/expects/d4_buggy.bi.expect b/tests/fpga-debugging/axis-fifo-d4/expects/d4_buggy.bi.expect
new file mode 100644
index 00000000..68cf837b
--- /dev/null
+++ b/tests/fpga-debugging/axis-fifo-d4/expects/d4_buggy.bi.expect
@@ -0,0 +1,47 @@
+// trace 0
+trace {
+    reset();  // [time: 0ns -> 2.5ns]
+    reset();  // [time: 2.5ns -> 5ns]
+    reset();  // [time: 5ns -> 7.5ns]
+    reset();  // [time: 7.5ns -> 10ns]
+    reset();  // [time: 10ns -> 12.5ns]
+    reset();  // [time: 12.5ns -> 15ns]
+    reset();  // [time: 15ns -> 17.5ns]
+    reset();  // [time: 17.5ns -> 20ns]
+    reset();  // [time: 20ns -> 22.5ns]
+    reset();  // [time: 22.5ns -> 25ns]
+    push(0);  // [time: 37.5ns -> 40ns]
+    push(1);  // [time: 40ns -> 42.5ns]
+    push(2);  // [time: 42.5ns -> 45ns]
+    push(3);  // [time: 45ns -> 47.5ns]
+    push(4);  // [time: 47.5ns -> 50ns]
+    push(5);  // [time: 50ns -> 52.5ns]
+    push(6);  // [time: 52.5ns -> 55ns]
+    push(7);  // [time: 55ns -> 57.5ns]
+    push(8);  // [time: 57.5ns -> 60ns]
+    push(9);  // [time: 60ns -> 62.5ns]
+    push(233);  // [time: 62.5ns -> 65ns]
+    push(0);  // [time: 77.5ns -> 80ns]
+    push(1);  // [time: 80ns -> 82.5ns]
+    push(2);  // [time: 82.5ns -> 85ns]
+    push(3);  // [time: 85ns -> 87.5ns]
+    push(4);  // [time: 87.5ns -> 90ns]
+    push(5);  // [time: 90ns -> 92.5ns]
+    push(6);  // [time: 92.5ns -> 95ns]
+    push(7);  // [time: 95ns -> 97.5ns]
+    push(8);  // [time: 97.5ns -> 100ns]
+    push(9);  // [time: 100ns -> 102.5ns]
+    push(233);  // [time: 102.5ns -> 105ns]
+    push(0);  // [time: 117.5ns -> 120ns]
+    push(1);  // [time: 120ns -> 122.5ns]
+    push(2);  // [time: 122.5ns -> 125ns]
+    push(3);  // [time: 125ns -> 127.5ns]
+    push(4);  // [time: 127.5ns -> 130ns]
+    push(5);  // [time: 130ns -> 132.5ns]
+    push(6);  // [time: 132.5ns -> 135ns]
+    push(7);  // [time: 135ns -> 137.5ns]
+    push(8);  // [time: 137.5ns -> 140ns]
+    push(9);  // [time: 140ns -> 142.5ns]
+    push(233);  // [time: 142.5ns -> 145ns]
+    push(0);  // [time: 157.5ns -> 157.5ns]
+}
diff --git a/tests/fpga-debugging/axis-fifo-d4/expects/d4_fixed.bi.expect b/tests/fpga-debugging/axis-fifo-d4/expects/d4_fixed.bi.expect
new file mode 100644
index 00000000..f831c600
--- /dev/null
+++ b/tests/fpga-debugging/axis-fifo-d4/expects/d4_fixed.bi.expect
@@ -0,0 +1,55 @@
+// trace 0
+trace {
+    reset();  // [time: 0ns -> 2.5ns]
+    reset();  // [time: 2.5ns -> 5ns]
+    reset();  // [time: 5ns -> 7.5ns]
+    reset();  // [time: 7.5ns -> 10ns]
+    reset();  // [time: 10ns -> 12.5ns]
+    reset();  // [time: 12.5ns -> 15ns]
+    reset();  // [time: 15ns -> 17.5ns]
+    reset();  // [time: 17.5ns -> 20ns]
+    reset();  // [time: 20ns -> 22.5ns]
+    reset();  // [time: 22.5ns -> 25ns]
+    push(0);  // [time: 37.5ns -> 40ns]
+    push(1);  // [time: 40ns -> 42.5ns]
+    push(2);  // [time: 42.5ns -> 45ns]
+    push(3);  // [time: 45ns -> 47.5ns]
+    push(4);  // [time: 47.5ns -> 50ns]
+    push(5);  // [time: 50ns -> 52.5ns]
+    push(6);  // [time: 52.5ns -> 55ns]
+    push(7);  // [time: 55ns -> 57.5ns]
+    push(8);  // [time: 57.5ns -> 60ns]
+    push(9);  // [time: 60ns -> 62.5ns]
+    push(233);  // [time: 62.5ns -> 65ns]
+    push(0);  // [time: 77.5ns -> 80ns]
+    push(1);  // [time: 80ns -> 82.5ns]
+    push(2);  // [time: 82.5ns -> 85ns]
+    push(3);  // [time: 85ns -> 87.5ns]
+    push(4);  // [time: 87.5ns -> 90ns]
+    push(5);  // [time: 90ns -> 92.5ns]
+    push(6);  // [time: 92.5ns -> 95ns]
+    push(7);  // [time: 95ns -> 97.5ns]
+    push(8);  // [time: 97.5ns -> 100ns]
+    push(9);  // [time: 100ns -> 102.5ns]
+    push(233);  // [time: 102.5ns -> 105ns]
+    push(0);  // [time: 117.5ns -> 120ns]
+    push(1);  // [time: 120ns -> 122.5ns]
+    push(2);  // [time: 122.5ns -> 125ns]
+    push(3);  // [time: 125ns -> 127.5ns]
+    push(4);  // [time: 127.5ns -> 130ns]
+    push(5);  // [time: 130ns -> 132.5ns]
+    push(6);  // [time: 132.5ns -> 135ns]
+    push(7);  // [time: 135ns -> 137.5ns]
+    push(8);  // [time: 137.5ns -> 140ns]
+    push(9);  // [time: 140ns -> 142.5ns]
+    push(233);  // [time: 142.5ns -> 145ns]
+}
+error: [push@63] executing step 1 of the transaction: 01 != 00
+   ┌─ tests/fpga-debugging/axis-fifo-d4/d4_fixed.prot:89:5
+   │
+89 │     DUT.s_axis_tdata := data;
+   │     ^^^^^^^^^^^^^^^^^^^^^^^^^ [push@63] executing step 1 of the transaction: 01 != 00
+
+Error: "Monitor failed"
+---CODE---
+1
diff --git a/tests/identities/expects/identity_d1.bi.expect b/tests/identities/expects/identity_d1.bi.expect
new file mode 100644
index 00000000..4b88a61a
--- /dev/null
+++ b/tests/identities/expects/identity_d1.bi.expect
@@ -0,0 +1,4 @@
+panicked at bi/src/bi.rs:739:29:
+not yet implemented: we currently expect one side of an assert_eq to be a port!
+---CODE---
+101
diff --git a/tests/multi/expects/multi0.bi.expect b/tests/multi/expects/multi0.bi.expect
new file mode 100644
index 00000000..8219b9ab
--- /dev/null
+++ b/tests/multi/expects/multi0.bi.expect
@@ -0,0 +1,4 @@
+// trace 0
+trace {
+    multi(10, 10);
+}
diff --git a/tests/multi/expects/multi0keep.bi.expect b/tests/multi/expects/multi0keep.bi.expect
new file mode 100644
index 00000000..8219b9ab
--- /dev/null
+++ b/tests/multi/expects/multi0keep.bi.expect
@@ -0,0 +1,4 @@
+// trace 0
+trace {
+    multi(10, 10);
+}
diff --git a/tests/multi/expects/multi0keep2const.bi.expect b/tests/multi/expects/multi0keep2const.bi.expect
new file mode 100644
index 00000000..8219b9ab
--- /dev/null
+++ b/tests/multi/expects/multi0keep2const.bi.expect
@@ -0,0 +1,4 @@
+// trace 0
+trace {
+    multi(10, 10);
+}
diff --git a/tests/multi/expects/multi2const.bi.expect b/tests/multi/expects/multi2const.bi.expect
new file mode 100644
index 00000000..8219b9ab
--- /dev/null
+++ b/tests/multi/expects/multi2const.bi.expect
@@ -0,0 +1,4 @@
+// trace 0
+trace {
+    multi(10, 10);
+}
diff --git a/tests/multi/expects/multi2multi.bi.expect b/tests/multi/expects/multi2multi.bi.expect
new file mode 100644
index 00000000..8219b9ab
--- /dev/null
+++ b/tests/multi/expects/multi2multi.bi.expect
@@ -0,0 +1,4 @@
+// trace 0
+trace {
+    multi(10, 10);
+}
diff --git a/tests/multi/expects/multi_data.bi.expect b/tests/multi/expects/multi_data.bi.expect
new file mode 100644
index 00000000..8219b9ab
--- /dev/null
+++ b/tests/multi/expects/multi_data.bi.expect
@@ -0,0 +1,4 @@
+// trace 0
+trace {
+    multi(10, 10);
+}
diff --git a/tests/multipliers/expects/mult_d2.bi.expect b/tests/multipliers/expects/mult_d2.bi.expect
new file mode 100644
index 00000000..e81c6c28
--- /dev/null
+++ b/tests/multipliers/expects/mult_d2.bi.expect
@@ -0,0 +1,5 @@
+// trace 0
+trace {
+    mul(1, 2, 2);
+    mul(6, 8, 48);
+}
diff --git a/tests/picorv32/expects/pcpi_mul_unsigned_mul.bi.expect b/tests/picorv32/expects/pcpi_mul_unsigned_mul.bi.expect
new file mode 100644
index 00000000..7b7bd936
--- /dev/null
+++ b/tests/picorv32/expects/pcpi_mul_unsigned_mul.bi.expect
@@ -0,0 +1,8 @@
+// trace 0
+trace {
+    pcpi_mul_reset();
+    pcpi_mul(1, 1, 1, 33554483);
+    pcpi_mul(1, 100, 100, 33554483);
+    pcpi_mul(100, 1, 100, 33554483);
+    pcpi_mul(33554483, 200, 2415929304, 33554483);
+}
diff --git a/tests/serv/expects/serv_regfile.bi.expect b/tests/serv/expects/serv_regfile.bi.expect
new file mode 100644
index 00000000..a5b7ee4e
--- /dev/null
+++ b/tests/serv/expects/serv_regfile.bi.expect
@@ -0,0 +1,6 @@
+panicked at bi/src/constraints.rs:120:9:
+assertion `left == right` failed
+  left: 32
+ right: 1
+---CODE---
+101
diff --git a/tests/tinyaes128/expects/aes128.bi.expect b/tests/tinyaes128/expects/aes128.bi.expect
new file mode 100644
index 00000000..0153c201
--- /dev/null
+++ b/tests/tinyaes128/expects/aes128.bi.expect
@@ -0,0 +1,5 @@
+// trace 0
+trace {
+    aes128(0x000102030405060708090a0b0c0d0e0f, 0x00112233445566778899aabbccddeeff, 0x69c4e0d86a7b0430d8cdb78070b4c55a);
+    aes128(0x00000000000000000000000000000000, 0x00000000000000000000000000000000, 0x66e94bd4ef8a2c3b884cfa59ca342b2e);
+}
diff --git a/tests/wal/advanced/expects/axis.bi.expect b/tests/wal/advanced/expects/axis.bi.expect
new file mode 100644
index 00000000..4a0b2a39
--- /dev/null
+++ b/tests/wal/advanced/expects/axis.bi.expect
@@ -0,0 +1,16 @@
+// trace 0
+trace {
+    send_data(0);  // [time: 804ns -> 812ns]
+    send_data(1);  // [time: 1508ns -> 1516ns]
+    send_data(2);  // [time: 2212ns -> 2220ns]
+    send_data(3);  // [time: 2916ns -> 2924ns]
+}
+error: [send_data@453] executing step 88 of the transaction: 05 != 04
+   ┌─ tests/wal/advanced/axis.prot:10:5
+   │
+10 │     D.m_axis_tdata := data;
+   │     ^^^^^^^^^^^^^^^^^^^^^^^ [send_data@453] executing step 88 of the transaction: 05 != 04
+
+Error: "Monitor failed"
+---CODE---
+1
diff --git a/tests/wal/advanced/expects/axis_failing.bi.expect b/tests/wal/advanced/expects/axis_failing.bi.expect
new file mode 100644
index 00000000..313a163a
--- /dev/null
+++ b/tests/wal/advanced/expects/axis_failing.bi.expect
@@ -0,0 +1,12 @@
+// trace 0
+trace {
+}
+error: [idle@0] executing step 0 of the transaction: 1 != 0
+   ┌─ tests/wal/advanced/axis_failing.prot:11:5
+   │
+11 │     D.m_axis_tvalid := 1'b0;
+   │     ^^^^^^^^^^^^^^^^^^^^^^^^ [idle@0] executing step 0 of the transaction: 1 != 0
+
+Error: "Monitor failed"
+---CODE---
+1
diff --git a/tests/wal/advanced/expects/axis_minimal.bi.expect b/tests/wal/advanced/expects/axis_minimal.bi.expect
new file mode 100644
index 00000000..8570d0a2
--- /dev/null
+++ b/tests/wal/advanced/expects/axis_minimal.bi.expect
@@ -0,0 +1,12 @@
+// trace 0
+trace {
+}
+error: [send_data@0] executing step 3 of the transaction: 0f != 14
+   ┌─ tests/wal/advanced/axis_minimal.prot:10:5
+   │
+10 │     D.m_axis_tdata := data;
+   │     ^^^^^^^^^^^^^^^^^^^^^^^ [send_data@0] executing step 3 of the transaction: 0f != 14
+
+Error: "Monitor failed"
+---CODE---
+1
diff --git a/tests/wal/advanced/expects/axis_truncated.bi.expect b/tests/wal/advanced/expects/axis_truncated.bi.expect
new file mode 100644
index 00000000..e11c9fe8
--- /dev/null
+++ b/tests/wal/advanced/expects/axis_truncated.bi.expect
@@ -0,0 +1,12 @@
+// trace 0
+trace {
+}
+error: [send_data@0] executing step 88 of the transaction: 0f != 0e
+   ┌─ tests/wal/advanced/axis_truncated.prot:10:5
+   │
+10 │     D.m_axis_tdata := data;
+   │     ^^^^^^^^^^^^^^^^^^^^^^^ [send_data@0] executing step 88 of the transaction: 0f != 0e
+
+Error: "Monitor failed"
+---CODE---
+1
diff --git a/tests/wal/advanced/expects/axis_truncated_include_idle.bi.expect b/tests/wal/advanced/expects/axis_truncated_include_idle.bi.expect
new file mode 100644
index 00000000..a9f16426
--- /dev/null
+++ b/tests/wal/advanced/expects/axis_truncated_include_idle.bi.expect
@@ -0,0 +1,12 @@
+// trace 0
+trace {
+}
+error: [send_data@0] executing step 88 of the transaction: 0f != 0e
+   ┌─ tests/wal/advanced/axis_truncated_include_idle.prot:11:5
+   │
+11 │     D.m_axis_tdata := data;
+   │     ^^^^^^^^^^^^^^^^^^^^^^^ [send_data@0] executing step 88 of the transaction: 0f != 0e
+
+Error: "Monitor failed"
+---CODE---
+1
diff --git a/tests/wb_intercon/expects/wb_arb.bi.expect b/tests/wb_intercon/expects/wb_arb.bi.expect
new file mode 100644
index 00000000..102c1bf9
--- /dev/null
+++ b/tests/wb_intercon/expects/wb_arb.bi.expect
@@ -0,0 +1,8 @@
+error: the following required arguments were not provided:
+  --wave <WAVE_FILE>
+
+Usage: bi --wave <WAVE_FILE> --show-waveform-time --color <COLOR_CHOICE> --protocol <PROTOCOLS_FILE> --instances <INSTANCES>... --sample-posedge <SIGNAL_TO_SAMPLE_ON_RISING_EDGE> --time-unit <TIME_UNIT>
+
+For more information, try '--help'.
+---CODE---
+2
diff --git a/tests/wb_intercon/expects/wb_cdc.bi.expect b/tests/wb_intercon/expects/wb_cdc.bi.expect
new file mode 100644
index 00000000..8e5b9c2f
--- /dev/null
+++ b/tests/wb_intercon/expects/wb_cdc.bi.expect
@@ -0,0 +1,6 @@
+panicked at bi/src/main.rs:106:9:
+assertion `left == right` failed: Only nano seconds are supported
+  left: "s"
+ right: "ns"
+---CODE---
+101
diff --git a/tests/wishbone/expects/wishbone.bi.expect b/tests/wishbone/expects/wishbone.bi.expect
new file mode 100644
index 00000000..734ce750
--- /dev/null
+++ b/tests/wishbone/expects/wishbone.bi.expect
@@ -0,0 +1,18 @@
+// trace 0
+trace {
+    read(0, 0);
+    write(0, 0);
+    read(0, 3);
+    read(0, 5);
+    read(0, 7);
+    read(0, 9);
+    read(0, 11);
+    read(0, 0);
+    write(0, 0);
+    read(0, 3);
+    read(0, 5);
+    read(0, 7);
+    read(0, 9);
+    read(0, 11);
+    read(0, 0);
+}