no SUBCKT if loading from verilog instead of GHDL

[nonchip]

I slightly modified one of the provided flows to replace the GHDL step with:

read_verilog -sv -formal ../main.sv ../vinclude/*.sv
hierarchy -check -top Mover
proc

but the generated spice will not contain any SUBCKTs, which PCBPlace dies about.
any ideas?

the code at the time of writing this issue is available in this commit, executed from the sim/pcb/ folder with this command: yosys flow_discrete_LTL.ys

[cpldcpu]

That happens also in VHDL when you flatten the design. It's quite annoying, because in that case the spice output is missing any I/O information. I am not sure how to influence this behavior in a more controlled way in Yosys.

You could removing the "top" option from the hierarchy command?

My plan was to switch to JSON as intermediate file format to address this, but I have not started working on this yet.

[nonchip]

You could removing the "top" option from the hierarchy command?

sure thing, but then:

ERROR: No top module found!

removing the flatten instead gives me a bunch of output files, but also a lot of those kinda warnings:

Warning: no (blackbox) module for cell type `$_DFFSR_PPP_' ($paramod\counter\WIDTH=16.$auto$simplemap.cc:467:simplemap_dffsr$407) found! Guessing order of ports.
Warning: no (blackbox) module for cell type `$_TBUF_' (core.$auto$simplemap.cc:293:simplemap_tribuf$260) found! Guessing order of ports.

and PCBPlace again complains, this time about:

=== Setting up array ===

Number of cells in design: 720
Area margin: 20.0%
Array Xwidth: 28
Array Ywidth: 32

=== Parsing input file & Inserting Microcells ===

Exception during parsing of input file '209_synthesized_output.sp'
Conflicting line: '.SUBCKT _paramod_counter_WIDTH_16 clk load oe in.0 in.1 in.2 in.3 in.4 in.5 in.6 in.7 in.8 in.9 in.10 in.11 in.12 in.13 in.14 in.15 out.0 out.1 out.2 out.3 out.4 out.5 out.6 out.7 out.8 out.9 out.10 out.11 out.12 out.13 out.14 out.15'
Exception message: Could not insert I/O cell in line zero! Please increase the X-width of the cell array or correct FixedIO assignment.

whatever that actually means

EDIT: ok apparently i have to define those in PCBPlace.py, choosing really high numbers to test with it works fine until:

Exception during parsing of input file '209_synthesized_output.sp'
Conflicting line: 'X0 CLK 1 ltl_NOT'
Exception message: component outside of subckt

which, yeah, that's there outside (= in the top module).
just gonna manually subckt that i guess...

aaaaand now it's thinking. btw PCBPlace.py:1020: DeprecationWarning: Sampling from a set deprecated since Python 3.9 and will be removed in a subsequent version.

EDIT 2: and then it fails because it doesn't know the cell type of the submodules i wasn't allowed to flatten.
retrying with flatten but also the manual subckt line(s):

.SUBCKT main nRST CLK nWR nRD A.0 A.1 A.2 A.3 A.4 A.5 A.6 A.7 A.8 A.9 A.10 A.11 A.12 A.13 A.14 A.15 Di.0 Di.1 Di.2 Di.3 Di.4 Di.5 Di.6 Di.7 Di.8 Di.9 Di.10 Di.11 Di.12 Di.13 Di.14 Di.15 Do.0 Do.1 Do.2 Do.3 Do.4 Do.5 Do.6 Do.7 Do.8 Do.9 Do.10 Do.11 Do.12 Do.13 Do.14 Do.15

EDIT 3: now it only dies due to:

Failed to insert footprint of cell X309, type unknown   __TBUF_
 (about 50 of those)
Failed to insert footprint of cell X375, type unknown   __DFFSR_PPP_
 (about 10)
Failed to insert footprint of cell X394, type unknown   __DLATCH_P_
 (exactly 32, which i know because that's the number of bits in my registers)

2 of which yosys already complained about (see top of this comment), but the DLATCH is new.

[cpldcpu]

Looks like you got pretty far! It seems that your design causes yosys to generate a number of cell types that are not implemented in PCBplace. The easiest way would be to change your design in a way that it does not use tristate bus and latches. Not sure about DFFSR_PPP, that should not be generated.

The harder way would be to implement them as cells in PCBPlace.py. Tristate buffers are a bit tricky though.

[cpldcpu]

PCBPlace.py:1020: DeprecationWarning: Sampling from a set deprecated since Python 3.9 and will be removed in a subsequent version.

This seems to be new - annoying.

[nonchip]

The easiest way would be to change your design in a way that it does not use tristate bus and latches.

yeah that's pretty much impossible in my design sadly. currently i'm going the manual route by just looking at a dot graph and drawing a schematic by hand. i think that's better in my case anyway since i'd like it all nicely laid out and understandable by looking at the board (kind of a "let's build this piece of logic discretely" education/art piece with lots of silkscreen explanations etc)

Tristate buffers are a bit tricky though.

i mean they should just be a single mosfet if i'm not mistaken?

[cpldcpu]

i mean they should just be a single mosfet if i'm not mistaken?

Almost all discrete MOSFETs have a body diode in parallel, so they are only high-ohmic in one direction. You could use a bipolar transistor or a CMOS pair though. Or a very simple cheat - a resistor. In any case, you would need to check functionality of the circuit in spiuce.

Btw, I don't get why you get the warning for: _DFFSR_PPP
Which libfile are you using?

[nonchip]

Almost all discrete MOSFETs have a body diode in parallel, so they are only high-ohmic in one direction.

right, didn't keep that in mind. i'll probably just use 74xxish tribufs in my case (or rather registers with OE, after all that's why i need all that storage to begin with)

Which libfile are you using?

i think that was both on LTL and RTL, should have mentioned all the modifications above, but not 110% sure.