From 22291903dc4653c4b14e5d3cd64d11a4f43f1183 Mon Sep 17 00:00:00 2001 From: KyleJeong <39640360+KyleJeong@users.noreply.github.com> Date: Wed, 13 May 2020 10:12:54 +0900 Subject: [PATCH 01/22] Create verilog_wire.py --- plugin/verilog_wire.py | 71 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 plugin/verilog_wire.py diff --git a/plugin/verilog_wire.py b/plugin/verilog_wire.py new file mode 100644 index 0000000..50db0e3 --- /dev/null +++ b/plugin/verilog_wire.py @@ -0,0 +1,71 @@ +#!/usr/bin/env python3 + +"""this script is a basic script for doing verilog editing +it parses the variables from stdin and generate a verilog name instantiation +of the variables""" + +import re +import sys + +skip_last_coma = 0 +if len(sys.argv) > 1: + skip_last_coma = int(sys.argv[1]) + +keywords = [] +keywords.extend(["input", "output", "inout", "ref", "parameter", "localparam"]) +keywords.extend(["reg", "logic", "wire", "bit", "integer", "int", "string", "type"]) +keywords.extend(["const", "unsigned"]) + +patterns = [] +patterns.append(re.compile(r'\[[^\[\]]*\]')) # port size, array size +patterns.append(re.compile(r'=.*')) # assignment +patterns.append(re.compile(r'//.*')) # // comment +patterns.append(re.compile(r'\w+\.\w+')) # interfaces with modport +for kw in keywords: # match keywords + patterns.append(re.compile("\\b%s\\b" % kw)) + +pattern_empty_line = re.compile(r'^\s*$') +pattern_open_comment = re.compile(r'/\*.*') +pattern_close_comment = re.compile(r'.*\*/') +pattern_open_to_close_comment = re.compile(r'/\*.*\*/') +pattern_punctuation = re.compile(r'[,;]') +pattern_two_words_no_coma = re.compile(r'^\s*(\w+)\s+(\w+.*)') +pattern_spaces = re.compile(r'\s+') + +ports = [] +wait_to_close_comment = 0 +indent_len = -1 + +for line in sys.stdin: + # print(line) + # get indentation length from 1st non empty line + if indent_len == -1 and not(pattern_empty_line.match(line)): + indent_len = len(re.match(r'^\s*', line).group(0)) + # handle comments + if wait_to_close_comment: + if pattern_close_comment.search(line): + line = pattern_close_comment.sub(' ', line) + wait_to_close_comment = 0 + else: + continue + if pattern_open_comment.search(line): + if pattern_close_comment.search(line): + line = pattern_open_to_close_comment.sub(' ', line) + else: + wait_to_close_comment = 1 + continue + + # delete input or output + line = line.replace("input", " ") + line = line.replace("output", "") + if "wire" not in line: + if "reg" in line: + line = line.replace("reg", "wire") + else: + line = "wire "+line + + line = line.replace(",", ";") + if line[-1] != ";": + line = line + ";" + line = line.strip() + print(line) From d777f0defc80324576cfb8d579b6f24fc1e1e815 Mon Sep 17 00:00:00 2001 From: KyleJeong <39640360+KyleJeong@users.noreply.github.com> Date: Wed, 13 May 2020 10:15:09 +0900 Subject: [PATCH 02/22] support port declaration to wire setting --- plugin/verilog_instance.vim | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/plugin/verilog_instance.vim b/plugin/verilog_instance.vim index 7cbca8b..fe931d1 100644 --- a/plugin/verilog_instance.vim +++ b/plugin/verilog_instance.vim @@ -34,3 +34,26 @@ if !hasmapto('VerilogInstance') && maparg('gb','n') ==# '' nmap gb VerilogInstance nmap gbb VerilogInstanceLine endif + +function! s:VerilogWire(type,...) abort + if a:0 + let [lnum1, lnum2] = [a:type, a:1] + else + let [lnum1, lnum2] = [line("'["), line("']")] + endif + let cmd = lnum1 . "norm! ==" + execute cmd + let cmd = lnum1 . "," . lnum2 . "!" . " " . s:plugin_dir_path . "/verilog_wire.py " . g:verilog_instance_skip_last_coma + execute cmd +endfunction + +xnoremap VerilogWire :call VerilogWire(line("'<"),line("'>")) +nnoremap VerilogWire :set opfunc=VerilogWireg@ +nnoremap VerilogWireLine :set opfunc=VerilogWireexe 'norm! 'v:count1.'g@_' +command! -range VerilogWire call s:VerilogWire(,) + +if !hasmapto('VerilogWire') && maparg('gb','n') ==# '' + xmap gw VerilogWire + nmap gw VerilogWire + nmap gww VerilogWireLine +endif From 6ce9018e7ea277275ce801ee9c78d0212c942680 Mon Sep 17 00:00:00 2001 From: KyleJeong <39640360+KyleJeong@users.noreply.github.com> Date: Wed, 13 May 2020 11:00:24 +0900 Subject: [PATCH 03/22] Update verilog_instance.vim --- plugin/verilog_instance.vim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/plugin/verilog_instance.vim b/plugin/verilog_instance.vim index fe931d1..7973585 100644 --- a/plugin/verilog_instance.vim +++ b/plugin/verilog_instance.vim @@ -52,7 +52,7 @@ nnoremap VerilogWire :set opfunc=VerilogWireg@ nnoremap VerilogWireLine :set opfunc=VerilogWireexe 'norm! 'v:count1.'g@_' command! -range VerilogWire call s:VerilogWire(,) -if !hasmapto('VerilogWire') && maparg('gb','n') ==# '' +if !hasmapto('VerilogWire') && maparg('gw','n') ==# '' xmap gw VerilogWire nmap gw VerilogWire nmap gww VerilogWireLine From 3aa366d0b5ac3ab1234116b1bdb4a45d4564d77c Mon Sep 17 00:00:00 2001 From: KyleJeong <39640360+KyleJeong@users.noreply.github.com> Date: Wed, 13 May 2020 11:05:15 +0900 Subject: [PATCH 04/22] Update verilog_wire.py --- plugin/verilog_wire.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/plugin/verilog_wire.py b/plugin/verilog_wire.py index 50db0e3..54a1ef2 100644 --- a/plugin/verilog_wire.py +++ b/plugin/verilog_wire.py @@ -65,7 +65,10 @@ line = "wire "+line line = line.replace(",", ";") + line = line.strip() + if line=="": + continue if line[-1] != ";": line = line + ";" - line = line.strip() + print(line) From 6385b2b916f2b697dffef8b8cd9b9ba5a3876fb6 Mon Sep 17 00:00:00 2001 From: KyleJeong <39640360+KyleJeong@users.noreply.github.com> Date: Wed, 13 May 2020 11:17:08 +0900 Subject: [PATCH 05/22] Update verilog_wire.py --- plugin/verilog_wire.py | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/plugin/verilog_wire.py b/plugin/verilog_wire.py index 54a1ef2..9fa94ec 100644 --- a/plugin/verilog_wire.py +++ b/plugin/verilog_wire.py @@ -55,20 +55,20 @@ wait_to_close_comment = 1 continue - # delete input or output - line = line.replace("input", " ") - line = line.replace("output", "") - if "wire" not in line: - if "reg" in line: - line = line.replace("reg", "wire") - else: - line = "wire "+line - - line = line.replace(",", ";") - line = line.strip() - if line=="": - continue - if line[-1] != ";": - line = line + ";" - - print(line) + for a_line in line.splitlines(): + if a_line.strip()=="": + continue + # delete input or output + a_line = a_line.replace("input", " ") + a_line = a_line.replace("output", "") + if "wire" not in a_line: + if "reg" in a_line: + a_line = a_line.replace("reg", "wire") + else: + a_line = "wire "+a_line + + a_line = a_line.replace(",", ";") + a_line = a_line.strip() + if a_line[-1] != ";": + a_line = a_line + ";" + print(a_line) From af359abf3021d57405513779cbaf68d1d222c268 Mon Sep 17 00:00:00 2001 From: KyleJeong <39640360+KyleJeong@users.noreply.github.com> Date: Wed, 13 May 2020 11:31:13 +0900 Subject: [PATCH 06/22] Update README.md --- README.md | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/README.md b/README.md index 4321fed..ef7b733 100644 --- a/README.md +++ b/README.md @@ -1,5 +1,10 @@ verilog-instance.vim ==================== +_KyleJeong's Modification_ + +Support 'gw' to make wire declaration from port declaration. If you found some bug, please let me know. + +_Original_ Create SystemVerilog port instantiation from port declaration. From ff9f23d89888ae0aff3b7d6c7479775306bb0154 Mon Sep 17 00:00:00 2001 From: kyle Date: Wed, 13 May 2020 22:09:41 +0900 Subject: [PATCH 07/22] Change file permissions --- plugin/verilog_wire.py | 0 1 file changed, 0 insertions(+), 0 deletions(-) mode change 100644 => 100755 plugin/verilog_wire.py diff --git a/plugin/verilog_wire.py b/plugin/verilog_wire.py old mode 100644 new mode 100755 From 862ce8e455a71d8eae2a38d9e22e114c887ba58c Mon Sep 17 00:00:00 2001 From: kyle Date: Sat, 23 May 2020 12:02:38 +0900 Subject: [PATCH 08/22] check gg --- README.md | 5 ----- plugin/verilog_instance.vim | 28 ++++++---------------------- 2 files changed, 6 insertions(+), 27 deletions(-) diff --git a/README.md b/README.md index ef7b733..4321fed 100644 --- a/README.md +++ b/README.md @@ -1,10 +1,5 @@ verilog-instance.vim ==================== -_KyleJeong's Modification_ - -Support 'gw' to make wire declaration from port declaration. If you found some bug, please let me know. - -_Original_ Create SystemVerilog port instantiation from port declaration. diff --git a/plugin/verilog_instance.vim b/plugin/verilog_instance.vim index 7973585..2154683 100644 --- a/plugin/verilog_instance.vim +++ b/plugin/verilog_instance.vim @@ -20,7 +20,6 @@ function! s:VerilogInstance(type,...) abort endif let cmd = lnum1 . "norm! ==" execute cmd - let cmd = lnum1 . "," . lnum2 . "!" . " " . s:plugin_dir_path . "/verilog_instance.py " . g:verilog_instance_skip_last_coma execute cmd endfunction @@ -30,30 +29,15 @@ nnoremap VerilogInstanceLine :set opfunc=VerilogInstanc command! -range VerilogInstance call s:VerilogInstance(,) if !hasmapto('VerilogInstance') && maparg('gb','n') ==# '' + let s:verilog_instance_wire_declaration = 0 xmap gb VerilogInstance nmap gb VerilogInstance nmap gbb VerilogInstanceLine endif -function! s:VerilogWire(type,...) abort - if a:0 - let [lnum1, lnum2] = [a:type, a:1] - else - let [lnum1, lnum2] = [line("'["), line("']")] - endif - let cmd = lnum1 . "norm! ==" - execute cmd - let cmd = lnum1 . "," . lnum2 . "!" . " " . s:plugin_dir_path . "/verilog_wire.py " . g:verilog_instance_skip_last_coma - execute cmd -endfunction - -xnoremap VerilogWire :call VerilogWire(line("'<"),line("'>")) -nnoremap VerilogWire :set opfunc=VerilogWireg@ -nnoremap VerilogWireLine :set opfunc=VerilogWireexe 'norm! 'v:count1.'g@_' -command! -range VerilogWire call s:VerilogWire(,) - -if !hasmapto('VerilogWire') && maparg('gw','n') ==# '' - xmap gw VerilogWire - nmap gw VerilogWire - nmap gww VerilogWireLine +if !hasmapto('VerilogWire') && maparg('gg','n') ==# '' + let s:verilog_instance_wire_declaration = 1 + xmap ggb VerilogInstance + nmap ggb VerilogInstance + nmap ggbb VerilogInstanceLine endif From b9fde9dae364fb9e65f5ab65ac68c5ffd8260620 Mon Sep 17 00:00:00 2001 From: kyle Date: Sat, 23 May 2020 12:02:42 +0900 Subject: [PATCH 09/22] Update verilog_instance.vim --- plugin/verilog_instance.vim | 1 + 1 file changed, 1 insertion(+) diff --git a/plugin/verilog_instance.vim b/plugin/verilog_instance.vim index 2154683..8c42694 100644 --- a/plugin/verilog_instance.vim +++ b/plugin/verilog_instance.vim @@ -20,6 +20,7 @@ function! s:VerilogInstance(type,...) abort endif let cmd = lnum1 . "norm! ==" execute cmd + let cmd = lnum1 . "," . lnum2 . "!" . " " . s:plugin_dir_path . "/verilog_instance.py " . g:verilog_instance_skip_last_coma . " " . s:verilog_instance_wire_declaration execute cmd endfunction From 8285dc7b1b8e2854a6840d294304fe6b26a856c9 Mon Sep 17 00:00:00 2001 From: KyleJeong <39640360+KyleJeong@users.noreply.github.com> Date: Sat, 23 May 2020 12:10:26 +0900 Subject: [PATCH 10/22] Delete verilog_wire.py --- plugin/verilog_wire.py | 74 ------------------------------------------ 1 file changed, 74 deletions(-) delete mode 100755 plugin/verilog_wire.py diff --git a/plugin/verilog_wire.py b/plugin/verilog_wire.py deleted file mode 100755 index 9fa94ec..0000000 --- a/plugin/verilog_wire.py +++ /dev/null @@ -1,74 +0,0 @@ -#!/usr/bin/env python3 - -"""this script is a basic script for doing verilog editing -it parses the variables from stdin and generate a verilog name instantiation -of the variables""" - -import re -import sys - -skip_last_coma = 0 -if len(sys.argv) > 1: - skip_last_coma = int(sys.argv[1]) - -keywords = [] -keywords.extend(["input", "output", "inout", "ref", "parameter", "localparam"]) -keywords.extend(["reg", "logic", "wire", "bit", "integer", "int", "string", "type"]) -keywords.extend(["const", "unsigned"]) - -patterns = [] -patterns.append(re.compile(r'\[[^\[\]]*\]')) # port size, array size -patterns.append(re.compile(r'=.*')) # assignment -patterns.append(re.compile(r'//.*')) # // comment -patterns.append(re.compile(r'\w+\.\w+')) # interfaces with modport -for kw in keywords: # match keywords - patterns.append(re.compile("\\b%s\\b" % kw)) - -pattern_empty_line = re.compile(r'^\s*$') -pattern_open_comment = re.compile(r'/\*.*') -pattern_close_comment = re.compile(r'.*\*/') -pattern_open_to_close_comment = re.compile(r'/\*.*\*/') -pattern_punctuation = re.compile(r'[,;]') -pattern_two_words_no_coma = re.compile(r'^\s*(\w+)\s+(\w+.*)') -pattern_spaces = re.compile(r'\s+') - -ports = [] -wait_to_close_comment = 0 -indent_len = -1 - -for line in sys.stdin: - # print(line) - # get indentation length from 1st non empty line - if indent_len == -1 and not(pattern_empty_line.match(line)): - indent_len = len(re.match(r'^\s*', line).group(0)) - # handle comments - if wait_to_close_comment: - if pattern_close_comment.search(line): - line = pattern_close_comment.sub(' ', line) - wait_to_close_comment = 0 - else: - continue - if pattern_open_comment.search(line): - if pattern_close_comment.search(line): - line = pattern_open_to_close_comment.sub(' ', line) - else: - wait_to_close_comment = 1 - continue - - for a_line in line.splitlines(): - if a_line.strip()=="": - continue - # delete input or output - a_line = a_line.replace("input", " ") - a_line = a_line.replace("output", "") - if "wire" not in a_line: - if "reg" in a_line: - a_line = a_line.replace("reg", "wire") - else: - a_line = "wire "+a_line - - a_line = a_line.replace(",", ";") - a_line = a_line.strip() - if a_line[-1] != ";": - a_line = a_line + ";" - print(a_line) From 88970ebe27c58a230ee5675998a495d7ae3b4098 Mon Sep 17 00:00:00 2001 From: KyleJeong <39640360+KyleJeong@users.noreply.github.com> Date: Sat, 23 May 2020 12:10:56 +0900 Subject: [PATCH 11/22] Update verilog_instance.vim --- plugin/verilog_instance.vim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/plugin/verilog_instance.vim b/plugin/verilog_instance.vim index 8c42694..2ec429f 100644 --- a/plugin/verilog_instance.vim +++ b/plugin/verilog_instance.vim @@ -36,7 +36,7 @@ if !hasmapto('VerilogInstance') && maparg('gb','n') ==# '' nmap gbb VerilogInstanceLine endif -if !hasmapto('VerilogWire') && maparg('gg','n') ==# '' +if !hasmapto('VerilogWire') && maparg('ggb','n') ==# '' let s:verilog_instance_wire_declaration = 1 xmap ggb VerilogInstance nmap ggb VerilogInstance From 633d27c7cbf2423ea1091f9bed5adf9b01568bac Mon Sep 17 00:00:00 2001 From: KyleJeong <39640360+KyleJeong@users.noreply.github.com> Date: Sat, 23 May 2020 12:12:56 +0900 Subject: [PATCH 12/22] Update verilog_instance.py --- plugin/verilog_instance.py | 70 +++++++++++++++++++++++++------------- 1 file changed, 47 insertions(+), 23 deletions(-) diff --git a/plugin/verilog_instance.py b/plugin/verilog_instance.py index e1e971a..9de6143 100755 --- a/plugin/verilog_instance.py +++ b/plugin/verilog_instance.py @@ -8,8 +8,11 @@ import sys skip_last_coma = 0 +wire_declaration = 0 if len(sys.argv) > 1: skip_last_coma = int(sys.argv[1]) + if len(sys.argv) > 2: + wire_declaration = int(sys.argv[2]) keywords = [] keywords.extend(["input", "output", "inout", "ref", "parameter", "localparam"]) @@ -31,6 +34,7 @@ pattern_punctuation = re.compile(r'[,;]') pattern_two_words_no_coma = re.compile(r'^\s*(\w+)\s+(\w+.*)') pattern_spaces = re.compile(r'\s+') +pattern_cpp_type_comment = re.compile(r'//.*') ports = [] wait_to_close_comment = 0 @@ -53,26 +57,46 @@ else: wait_to_close_comment = 1 continue - # handle all other patterns - for pattern in patterns: - line = pattern.sub(' ', line) - # handle typedef, class and interfaces - line = pattern_two_words_no_coma.sub('\\2', line) - line = pattern_punctuation.sub(' ', line) - line = pattern_spaces.sub(' ', line) - # finally, get port names - line = line.strip() - if line != "": - ports.extend(line.split(' ')) - -ports_nb = len(ports) -i = 0 -if ports_nb > 0: - max_str_len = len(max(ports, key=len)) - for port in ports: - skip_coma = skip_last_coma and i == (ports_nb - 1) - space_str = " " * (max_str_len - len(port)) - indent_str = " " * indent_len - print("%s.%s%s (%s%s)%s" % ( - indent_str, port, space_str, port, space_str, (",", "")[skip_coma])) - i = i + 1 + if wire_declaration == 0: + # handle all other patterns + for pattern in patterns: + line = pattern.sub(' ', line) + # handle typedef, class and interfaces + line = pattern_two_words_no_coma.sub('\\2', line) + line = pattern_punctuation.sub(' ', line) + line = pattern_spaces.sub(' ', line) + # finally, get port names + line = line.strip() + if line != "": + ports.extend(line.split(' ')) + else: + for a_line in line.splitlines(): + # Remove cpp style comment (//) + a_line = pattern_cpp_type_comment.sub(' ', a_line) + # Remove trailing spaces + a_line = a_line.strip() + # if line connets is empty clear it + if a_line == "": + continue + # delete input or output + a_line = a_line.replace("input", " ") + a_line = a_line.replace("output", "") + # wire keyword + if "wire" not in a_line: + if "reg" in a_line: + a_line = a_line.replace("reg", "wire") + else: + a_line = "wire " + a_line + +if wire_declaration == 0: + ports_nb = len(ports) + i = 0 + if ports_nb > 0: + max_str_len = len(max(ports, key=len)) + for port in ports: + skip_coma = skip_last_coma and i == (ports_nb - 1) + space_str = " " * (max_str_len - len(port)) + indent_str = " " * indent_len + print("%s.%s%s (%s%s)%s" % ( + indent_str, port, space_str, port, space_str, (",", "")[skip_coma])) + i = i + 1 From aac8a2a2efcbe8e5e96f961c9f29e110430a6c9f Mon Sep 17 00:00:00 2001 From: KyleJeong <39640360+KyleJeong@users.noreply.github.com> Date: Sat, 23 May 2020 12:15:31 +0900 Subject: [PATCH 13/22] Update verilog_instance.py --- plugin/verilog_instance.py | 1 + 1 file changed, 1 insertion(+) diff --git a/plugin/verilog_instance.py b/plugin/verilog_instance.py index 9de6143..d60f6f3 100755 --- a/plugin/verilog_instance.py +++ b/plugin/verilog_instance.py @@ -70,6 +70,7 @@ if line != "": ports.extend(line.split(' ')) else: + print(line) for a_line in line.splitlines(): # Remove cpp style comment (//) a_line = pattern_cpp_type_comment.sub(' ', a_line) From 7ac537f9e53e5fa82b32252b85c879c196e2a80e Mon Sep 17 00:00:00 2001 From: KyleJeong <39640360+KyleJeong@users.noreply.github.com> Date: Sat, 23 May 2020 12:20:36 +0900 Subject: [PATCH 14/22] Update verilog_instance.py --- plugin/verilog_instance.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/plugin/verilog_instance.py b/plugin/verilog_instance.py index d60f6f3..0a17a57 100755 --- a/plugin/verilog_instance.py +++ b/plugin/verilog_instance.py @@ -72,10 +72,13 @@ else: print(line) for a_line in line.splitlines(): + print(a_line) # Remove cpp style comment (//) a_line = pattern_cpp_type_comment.sub(' ', a_line) + print(a_line) # Remove trailing spaces a_line = a_line.strip() + print(a_line) # if line connets is empty clear it if a_line == "": continue From dde0659e276d886a7cb161e73962335145615e79 Mon Sep 17 00:00:00 2001 From: KyleJeong <39640360+KyleJeong@users.noreply.github.com> Date: Sat, 23 May 2020 12:22:33 +0900 Subject: [PATCH 15/22] Update verilog_instance.py --- plugin/verilog_instance.py | 1 + 1 file changed, 1 insertion(+) diff --git a/plugin/verilog_instance.py b/plugin/verilog_instance.py index 0a17a57..efa2f77 100755 --- a/plugin/verilog_instance.py +++ b/plugin/verilog_instance.py @@ -91,6 +91,7 @@ a_line = a_line.replace("reg", "wire") else: a_line = "wire " + a_line + print (a_line) if wire_declaration == 0: ports_nb = len(ports) From 1deaec312b524b968bebca77c8f0a1aca118829a Mon Sep 17 00:00:00 2001 From: KyleJeong <39640360+KyleJeong@users.noreply.github.com> Date: Sat, 23 May 2020 12:26:18 +0900 Subject: [PATCH 16/22] Update verilog_instance.py --- plugin/verilog_instance.py | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/plugin/verilog_instance.py b/plugin/verilog_instance.py index efa2f77..1f38d2c 100755 --- a/plugin/verilog_instance.py +++ b/plugin/verilog_instance.py @@ -72,13 +72,11 @@ else: print(line) for a_line in line.splitlines(): - print(a_line) # Remove cpp style comment (//) a_line = pattern_cpp_type_comment.sub(' ', a_line) - print(a_line) + # print(a_line) # Remove trailing spaces a_line = a_line.strip() - print(a_line) # if line connets is empty clear it if a_line == "": continue @@ -90,7 +88,13 @@ if "reg" in a_line: a_line = a_line.replace("reg", "wire") else: - a_line = "wire " + a_line + a_line = "wire " + a_line + + # semicolon + a_line.replace(",", ";") + if a_line[-1] != ';': + a_line = a_line + ';' + # print wire declaration print (a_line) if wire_declaration == 0: From 23a6b98a3c369c595a38ecc1ecb13db764dd8c58 Mon Sep 17 00:00:00 2001 From: KyleJeong <39640360+KyleJeong@users.noreply.github.com> Date: Sat, 23 May 2020 12:28:34 +0900 Subject: [PATCH 17/22] Update verilog_instance.py --- plugin/verilog_instance.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/plugin/verilog_instance.py b/plugin/verilog_instance.py index 1f38d2c..3e47afb 100755 --- a/plugin/verilog_instance.py +++ b/plugin/verilog_instance.py @@ -70,7 +70,7 @@ if line != "": ports.extend(line.split(' ')) else: - print(line) + # print(line) for a_line in line.splitlines(): # Remove cpp style comment (//) a_line = pattern_cpp_type_comment.sub(' ', a_line) @@ -91,7 +91,10 @@ a_line = "wire " + a_line # semicolon + print(a_line) a_line.replace(",", ";") + a_line = a_line.strip() + print(a_line) if a_line[-1] != ';': a_line = a_line + ';' # print wire declaration From 0c46d4213d708fa81b5a86aa66bef14b1f3e9bba Mon Sep 17 00:00:00 2001 From: KyleJeong <39640360+KyleJeong@users.noreply.github.com> Date: Sat, 23 May 2020 12:30:07 +0900 Subject: [PATCH 18/22] Update verilog_instance.py --- plugin/verilog_instance.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/plugin/verilog_instance.py b/plugin/verilog_instance.py index 3e47afb..d8c67af 100755 --- a/plugin/verilog_instance.py +++ b/plugin/verilog_instance.py @@ -91,10 +91,10 @@ a_line = "wire " + a_line # semicolon - print(a_line) - a_line.replace(",", ";") + # print(a_line) + a_line = a_line.replace(",", ";") a_line = a_line.strip() - print(a_line) + # print(a_line) if a_line[-1] != ';': a_line = a_line + ';' # print wire declaration From 3250d25cbd8c7f657921e56de8823b8e2e7f3cca Mon Sep 17 00:00:00 2001 From: KyleJeong <39640360+KyleJeong@users.noreply.github.com> Date: Sat, 23 May 2020 12:35:41 +0900 Subject: [PATCH 19/22] Update verilog_instance.py --- plugin/verilog_instance.py | 1 + 1 file changed, 1 insertion(+) diff --git a/plugin/verilog_instance.py b/plugin/verilog_instance.py index d8c67af..5952b1c 100755 --- a/plugin/verilog_instance.py +++ b/plugin/verilog_instance.py @@ -7,6 +7,7 @@ import re import sys +print(sys.argv[1:]) skip_last_coma = 0 wire_declaration = 0 if len(sys.argv) > 1: From 6c71d9a5d05651e1cb213f415443cfda9550674b Mon Sep 17 00:00:00 2001 From: KyleJeong <39640360+KyleJeong@users.noreply.github.com> Date: Sat, 23 May 2020 12:36:43 +0900 Subject: [PATCH 20/22] Update verilog_instance.py --- plugin/verilog_instance.py | 1 - 1 file changed, 1 deletion(-) diff --git a/plugin/verilog_instance.py b/plugin/verilog_instance.py index 5952b1c..d8c67af 100755 --- a/plugin/verilog_instance.py +++ b/plugin/verilog_instance.py @@ -7,7 +7,6 @@ import re import sys -print(sys.argv[1:]) skip_last_coma = 0 wire_declaration = 0 if len(sys.argv) > 1: From cf394a83338383e2fdfee3c66c093be070252de3 Mon Sep 17 00:00:00 2001 From: KyleJeong <39640360+KyleJeong@users.noreply.github.com> Date: Sat, 23 May 2020 12:47:47 +0900 Subject: [PATCH 21/22] Update verilog_instance.vim --- plugin/verilog_instance.vim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/plugin/verilog_instance.vim b/plugin/verilog_instance.vim index 2ec429f..e912597 100644 --- a/plugin/verilog_instance.vim +++ b/plugin/verilog_instance.vim @@ -36,7 +36,7 @@ if !hasmapto('VerilogInstance') && maparg('gb','n') ==# '' nmap gbb VerilogInstanceLine endif -if !hasmapto('VerilogWire') && maparg('ggb','n') ==# '' +if !hasmapto('VerilogInstance') && maparg('ggb','n') ==# '' let s:verilog_instance_wire_declaration = 1 xmap ggb VerilogInstance nmap ggb VerilogInstance From ead98dcefd2035203a7ac405d8ec7cadaf38a2a3 Mon Sep 17 00:00:00 2001 From: KyleJeong <39640360+KyleJeong@users.noreply.github.com> Date: Sat, 23 May 2020 12:50:01 +0900 Subject: [PATCH 22/22] Update verilog_instance.vim --- plugin/verilog_instance.vim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/plugin/verilog_instance.vim b/plugin/verilog_instance.vim index e912597..2ec429f 100644 --- a/plugin/verilog_instance.vim +++ b/plugin/verilog_instance.vim @@ -36,7 +36,7 @@ if !hasmapto('VerilogInstance') && maparg('gb','n') ==# '' nmap gbb VerilogInstanceLine endif -if !hasmapto('VerilogInstance') && maparg('ggb','n') ==# '' +if !hasmapto('VerilogWire') && maparg('ggb','n') ==# '' let s:verilog_instance_wire_declaration = 1 xmap ggb VerilogInstance nmap ggb VerilogInstance