Makefile

MAKEFILE_DIR := $(shell dirname $(realpath $(firstword $(MAKEFILE_LIST))))

RUN_TAG ?= $(shell ls librelane/runs/ | tail -n 1)

TOP = chip_top

SCL = gf180mcu_fd_sc_mcu7t5v0
SRAM = gf180mcu_fd_ip_sram
SLOT = 1x0p5

PDK_ROOT ?= $(MAKEFILE_DIR)/gf180mcu
PDK ?= gf180mcuD
PDK_COMMIT ?= 140b0494c6665b10ce9353cb1c2ef5bcc18e7d66

# Available SCL libraries:
# gf180mcu_as_sc_mcu7t3v3
# gf180mcu_fd_sc_mcu7t5v0
# gf180mcu_fd_sc_mcu9t5v0
# gf180mcu_osu_sc_gp9t3v3 (broken)
# gf180mcu_osu_sc_gp12t3v3 (broken)

ifeq ($(SCL),default)
    SCL = gf180mcu_fd_sc_mcu7t5v0
endif
SCL ?= gf180mcu_fd_sc_mcu7t5v0

# Available PAD libraries:
# gf180mcu_fd_io
# gf180mcu_ocd_io

ifeq ($(PAD),default)
    PAD = gf180mcu_fd_io
endif
PAD ?= gf180mcu_fd_io

# Available SRAM macros:
# gf180mcu_fd_ip_sram
# gf180mcu_ocd_ip_sram

ifeq ($(SRAM),default)
    SRAM = gf180mcu_fd_ip_sram
endif
SRAM ?= gf180mcu_fd_ip_sram

ifeq ($(SRAM),gf180mcu_fd_ip_sram)
    MACROS = 5v
else
    MACROS = 3v3
endif

AVAILABLE_SLOTS = 1x1 0p5x1 1x0p5 0p5x0p5
DEFAULT_SLOT = 1x1

# Slot can be any of AVAILABLE_SLOTS
SLOT ?= $(DEFAULT_SLOT)

ifeq ($(SLOT),default)
    SLOT = $(DEFAULT_SLOT)
endif

ifeq ($(filter $(SLOT),$(AVAILABLE_SLOTS)),)
    $(error $(SLOT) does not exist in AVAILABLE_SLOTS: $(AVAILABLE_SLOTS))
endif

SLOT_DEFINE = SLOT_$(shell echo $(SLOT) | tr '[:lower:]' '[:upper:]')
SRAM_DEFINE = SRAM_$(SRAM)

LIBRELANE_OPTS = --pdk ${PDK} --pdk-root ${PDK_ROOT} --manual-pdk --scl ${SCL} --pad ${PAD}
LIBRELANE_CONFIGS = librelane/slots/slot_${SLOT}.yaml librelane/macros/macros_${MACROS}.yaml librelane/config.yaml

.DEFAULT_GOAL := help

help: ## Show this help message
	@echo 'Usage: make [target]'
	@echo ''
	@echo 'Available targets:'
	@grep -E '^[a-zA-Z_-]+:.*?## .*$$' $(MAKEFILE_LIST) | awk 'BEGIN {FS = ":.*?## "}; {printf "  %-20s %s\n", $$1, $$2}'
.PHONY: help

all: caravel-librelane macros-librelane librelane copy-final ## Build the project (runs LibreLane)
.PHONY: all
.NOTPARALLEL: all

$(PDK_ROOT)/ciel/gf180mcu/versions/$(PDK_COMMIT)/$(PDK):
	ciel enable $(PDK_COMMIT) --pdk-root $(PDK_ROOT) --pdk-family $(PDK) --include-libraries all

clone-pdk: $(PDK_ROOT)/ciel/gf180mcu/versions/$(PDK_COMMIT)/$(PDK) ## Clone the gf180mcu PDK
.PHONY: clone-pdk

# Need to find a better way to
# pass the variables to LibreLane
defines:
	@echo "Writing src/generated_defines.svh"
	$(file >src/generated_defines.svh,// This file is auto-generated by the Makefile)
	$(file >>src/generated_defines.svh,`define ${SLOT_DEFINE})
	$(file >>src/generated_defines.svh,`define ${SRAM_DEFINE})
.PHONY: defines

librelane: clone-pdk defines ## Run LibreLane flow (synthesis, PnR, verification)
	SRAM_DEFINE=${SRAM_DEFINE} librelane ${LIBRELANE_CONFIGS} ${LIBRELANE_OPTS} --save-views-to $(MAKEFILE_DIR)/final
.PHONY: librelane

caravel-librelane: ## Run LibreLane flow for caravel
	#make -C caravel all
	make -C caravel librelane-nodrc
	make -C caravel copy-final
.PHONY: caravel-librelane

ztimer-librelane: ## Run LibreLane flow for macros
	make -C ztimer all
.PHONY: librelane-librelane

macros-librelane: ztimer-librelane ## Run LibreLane flow for macros
.PHONY: caravel-librelane

librelane-condensed: clone-pdk defines ## Run LibreLane flow (synthesis, PnR, verification)
	SRAM_DEFINE=${SRAM_DEFINE} librelane --condensed ${LIBRELANE_CONFIGS} ${LIBRELANE_OPTS} --save-views-to $(MAKEFILE_DIR)/final
.PHONY: librelane-condensed

librelane-nodrc: clone-pdk defines ## Run LibreLane flow without DRC checks
	SRAM_DEFINE=${SRAM_DEFINE} librelane ${LIBRELANE_CONFIGS} ${LIBRELANE_OPTS} --save-views-to $(MAKEFILE_DIR)/final --skip KLayout.Antenna --skip KLayout.Density --skip KLayout.DRC --skip Magic.DRC
.PHONY: librelane-nodrc

librelane-klayoutdrc: clone-pdk defines ## Run LibreLane flow without magic DRC checks
	SRAM_DEFINE=${SRAM_DEFINE} librelane ${LIBRELANE_CONFIGS} ${LIBRELANE_OPTS} --save-views-to $(MAKEFILE_DIR)/final --skip Magic.DRC
.PHONY: librelane-klayoutdrc

librelane-magicdrc: clone-pdk defines ## Run LibreLane flow without KLayout DRC checks
	SRAM_DEFINE=${SRAM_DEFINE} librelane ${LIBRELANE_CONFIGS} ${LIBRELANE_OPTS} --save-views-to $(MAKEFILE_DIR)/final --skip KLayout.DRC
.PHONY: librelane-magicdrc

librelane-openroad: clone-pdk defines ## Open the last run in OpenROAD
	SRAM_DEFINE=${SRAM_DEFINE} librelane ${LIBRELANE_CONFIGS} ${LIBRELANE_OPTS} --last-run --flow OpenInOpenROAD
.PHONY: librelane-openroad

librelane-klayout: clone-pdk defines ## Open the last run in KLayout
	SRAM_DEFINE=${SRAM_DEFINE} librelane ${LIBRELANE_CONFIGS} ${LIBRELANE_OPTS} --last-run --flow OpenInKLayout
.PHONY: librelane-klayout

sim: ## Run RTL simulation with cocotb
	cd cocotb; PDK_ROOT=${PDK_ROOT} PDK=${PDK} SLOT=${SLOT} PAD=${PAD} SCL=${SCL} SRAM=${SRAM}  pytest -nauto --maxschedchunk=1 --dist worksteal -v chip_top_tb.py
.PHONY: sim

sim-gl: ## Run gate-level simulation with cocotb (after copy-final)
	cd cocotb; GL=1 PDK_ROOT=${PDK_ROOT} PDK=${PDK} SLOT=${SLOT} PAD=${PAD} SCL=${SCL} SRAM=${SRAM}  pytest -nauto --maxschedchunk=1 --dist worksteal -v chip_top_tb.py
.PHONY: sim-gl

sim-view: ## View simulation waveforms in GTKWave
	gtkwave cocotb/sim_build/chip_top.fst
.PHONY: sim-view

copy-final: ## Copy final output files from the last run
	rm -rf final/
	cp -r librelane/runs/${RUN_TAG}/final/ final/
	md5sum final/gds/chip_top.gds > final/gds/chip_top.gds.md5sum
	gzip -f9 final/gds/chip_top.gds
.PHONY: copy-final