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<a class="p-name article-title" href="/2025/05/29/readtarget/">读target目录</a>
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<h2 id="target-目录内容大致解析"><a href="#target-目录内容大致解析" class="headerlink" title="target 目录内容大致解析"></a>target 目录内容大致解析</h2><h3 id="ASMparser"><a href="#ASMparser" class="headerlink" title="ASMparser"></a>ASMparser</h3><p>RISCVAsmParser.cpp - Parse RISCV assembly to MCInst instructions<br>MCInst 是machine code instruction的意思，它是在汇编和机器码之间的等级。</p>
<h3 id="问题："><a href="#问题：" class="headerlink" title="问题："></a>问题：</h3><p>为什么要有这个MCInst，为什么不直接汇编到机器码就好了？</p>
<p>A: 整个后端流水线用到了四种不同层次的指令表示：内存中的LLVM IR，SelectionDAG节点，MachineInstr，和MCInst。那么machineInstr和MCinst之间干了什么呢</p>
<h3 id="Disassembler"><a href="#Disassembler" class="headerlink" title="Disassembler"></a>Disassembler</h3><p>这就是反汇编器，好理解</p>
<h3 id="GIsel"><a href="#GIsel" class="headerlink" title="GIsel"></a>GIsel</h3><p>Global instruction select 全局指令选择，就是ISEL的一部分，但是我感觉代码不太多。是都写在其他地方了吗？</p>
<h3 id="MCTargetDesc"><a href="#MCTargetDesc" class="headerlink" title="MCTargetDesc"></a>MCTargetDesc</h3><p>MC to 机器码 关于生成elf文件。这个明天也要问一下。</p>
<h3 id="TargetInfo"><a href="#TargetInfo" class="headerlink" title="TargetInfo"></a>TargetInfo</h3><p>指定三元组信息</p>
<h3 id="RISCV-H"><a href="#RISCV-H" class="headerlink" title="RISCV.H"></a>RISCV.H</h3><p>高层次接口。<br>定义了各种pass和一些栈类型</p>
<h3 id="RISCV-td"><a href="#RISCV-td" class="headerlink" title="RISCV.td"></a>RISCV.td</h3><p>Subtarget Features && Instruction Predicates<br>某个具体的目标 CPU 子类型（subtarget）所支持的可选扩展或特性。<br>Instruction Predicates 是基于 Subtarget Features 的条件判断，用来决定：</p>
<ul>
<li><p>某条指令是否可以在当前目标上合法生成；</p>
</li>
<li><p>是否在 .td 中启用某个指令定义；</p>
</li>
<li><p>或用于指令选择（Instruction Selection）阶段条件匹配。</p>
</li>
</ul>
<h3 id="插播一条："><a href="#插播一条：" class="headerlink" title="插播一条："></a>插播一条：</h3><p>td会生成inc然后被include进cpp里面</p>
<h3 id="RISCVAsmPrinter-cpp"><a href="#RISCVAsmPrinter-cpp" class="headerlink" title="RISCVAsmPrinter.cpp"></a>RISCVAsmPrinter.cpp</h3><p>汇编转移二进制？</p>
<h3 id="RISCVInstrInfoV-td"><a href="#RISCVInstrInfoV-td" class="headerlink" title="RISCVInstrInfoV.td"></a>RISCVInstrInfoV.td</h3><p>这个要详细看一下：分部分<br>Operand and SDNode transformation definitions.</p>
<ol>
<li><p>LLVM 生成 SelectionDAG：<br>LLVM 会将 LLVM IR 转换成 SelectionDAG，里面的节点是各种 SDNode 表示的操作（如 add, load, zext 等）。</p>
</li>
<li><p>通过 Pat 匹配规则识别 SDNode 组合：</p>
<figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br></pre></td><td class="code"><pre><span class="line"> def : Pat<(add GPR:$rs1, GPR:$rs2), (ADD $rs1, $rs2)>;</span><br><span class="line">这段表示：当看到 DAG 中的 add 节点，其操作数来自寄存器时，用目标机器指令 ADD 替换。</span><br><span class="line"></span><br><span class="line">使用 Operand 规则解析寄存器、立即数、内存操作数等：</span><br><span class="line"></span><br><span class="line">tablegen</span><br></pre></td></tr></table></figure></li>
</ol>
<p>def simm5 : Operand<XLenVT>, ImmLeaf<XLenVT, [{ return isInt<5>(Imm); }]>;</p>
<figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br><span class="line">13</span><br><span class="line">14</span><br><span class="line">15</span><br><span class="line">16</span><br></pre></td><td class="code"><pre><span class="line"></span><br><span class="line">3. 它告诉编译器，某个操作数是一个 5 位有符号立即数，编码时要验证这个约束。</span><br><span class="line"></span><br><span class="line">4. 生成机器指令（MachineInstr）：</span><br><span class="line">DAG 经过 ISelDAGToDAG 的匹配和替换后，会转为 MachineInstr，并使用 Operand 信息生成二进制编码。</span><br><span class="line"></span><br><span class="line">Scheduling definitions.</span><br><span class="line">这一部分是干嘛</span><br><span class="line">Instruction class templates</span><br><span class="line">比如：</span><br><span class="line">// strided segment load vd, (rs1), rs2, vm</span><br><span class="line">成段的load，store。</span><br><span class="line">以及向量和标量的结合计算啥的</span><br><span class="line">Combination of instruction classes.</span><br><span class="line">这里是一些指令子集啥的，比如VF，F就是两个不同的子集，同时根据不同的predict实例化不同子集</span><br><span class="line">tablegen</span><br></pre></td></tr></table></figure>
<p>let Predicates = [HasVInstructions] in {<br>def VLM_V : VUnitStrideLoadMask<”vlm.v”>,<br> Sched<[WriteVLDM, ReadVLDX]>;<br>def VSM_V : VUnitStrideStoreMask<”vsm.v”>,<br> Sched<[WriteVSTM, ReadVSTM, ReadVSTX]>;<br>def : InstAlias<”vle1.v $vd, (${rs1})”,<br> (VLM_V VR:$vd, GPR:$rs1), 0>;<br>def : InstAlias<”vse1.v $vs3, (${rs1})”,<br> (VSM_V VR:$vs3, GPR:$rs1), 0>;</p>
<pre><code>RISCVInstrInfoVPseudos.td
### RISCVRegisterInfo.td
111
### VentusInstrFormatsV.td
### RISCVCallingConv.td
中断恢复
### RISCVInstrInfoVVLPatterns.td
### RISCVSchedRocket.td
### VentusInstrInfoA.td
原子化拓展(关于ventus)
下面开始关注部分文件，关注一些更有借鉴意义的。
### RISCVCodeGenPrepare.cpp
### RISCVInstrInfoXVentana.td
### RISCVSchedSiFive7.td
### VentusInstrInfoC.td
### RISCVExpandAtomicPseudoInsts.cpp
### RISCVInstrInfoZb.td
### RISCVSchedule.td
### VentusInstrInfoF.td
### RISCVExpandPseudoInsts.cpp
### RISCVInstrInfoZfh.td
### RISCVScheduleV.td
### VentusInstrInfoM.td
RISCVFrameLowering.cpp RISCVInstrInfoZicbo.td RISCVScheduleZb.td VentusInstrInfo.td
RISCVFrameLowering.h RISCVInstrInfoZk.td RISCVSearchableTables.td VentusInstrInfoVPseudos.td
RISCV.h RISCVISelDAGToDAG.cpp RISCVSExtWRemoval.cpp VentusInstrInfoVSDPatterns.td
RISCVInstrFormatsC.td RISCVISelDAGToDAG.h RISCVSubtarget.cpp VentusInstrInfoV.td
RISCVInstrFormats.td RISCVISelLowering.cpp RISCVSubtarget.h VentusInstrInfoVVLPatterns.td
RISCVInstrFormatsV.td RISCVISelLowering.h RISCVSystemOperands.td VentusLegalizeLoad.cpp
RISCVInstrInfoA.td RISCVMachineFunctionInfo.cpp RISCVTargetMachine.cpp VentusPrintfRuntimeBinding.cpp
RISCVInstrInfo.cpp RISCVMachineFunctionInfo.h RISCVTargetMachine.h VentusProgramInfo.h
RISCVInstrInfoC.td RISCVMacroFusion.cpp RISCVTargetObjectFile.cpp VentusRegextInsertion.cpp
RISCVInstrInfoD.td RISCVMacroFusion.h RISCVTargetObjectFile.h VentusRegisterInfo.td
RISCVInstrInfoF.td
</code></pre>
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<a class="p-name article-title" href="/2025/05/21/2020.5.21/">2025-5-21-为什么官方LLVM会报错的思考</a>
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<p>目前在试图看出来为什么新官方llvm编译half.ll会报错，目前认为不是指令的问题，应该是ll文件的问题。这是2025年LLVM中关于fnmadd的相关ll，它专门建立了一个文件叫做fnmadd.ll</p>
<figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br><span class="line">13</span><br><span class="line">14</span><br><span class="line">15</span><br><span class="line">16</span><br><span class="line">17</span><br><span class="line">18</span><br><span class="line">19</span><br><span class="line">20</span><br><span class="line">21</span><br><span class="line">22</span><br><span class="line">23</span><br><span class="line">24</span><br><span class="line">25</span><br><span class="line">26</span><br><span class="line">27</span><br><span class="line">28</span><br><span class="line">29</span><br><span class="line">30</span><br><span class="line">31</span><br><span class="line">32</span><br><span class="line">33</span><br><span class="line">34</span><br><span class="line">35</span><br><span class="line">36</span><br><span class="line">37</span><br><span class="line">38</span><br><span class="line">39</span><br><span class="line">40</span><br><span class="line">41</span><br><span class="line">42</span><br><span class="line">43</span><br><span class="line">44</span><br><span class="line">45</span><br><span class="line">46</span><br><span class="line">47</span><br><span class="line">48</span><br><span class="line">49</span><br><span class="line">50</span><br><span class="line">51</span><br><span class="line">52</span><br><span class="line">53</span><br><span class="line">54</span><br><span class="line">55</span><br></pre></td><td class="code"><pre><span class="line">; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py</span><br><span class="line">; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \</span><br><span class="line">; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s</span><br><span class="line">; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \</span><br><span class="line">; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s</span><br><span class="line"></span><br><span class="line">declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16(</span><br><span class="line"> <vscale x 1 x half>,</span><br><span class="line"> <vscale x 1 x half>,</span><br><span class="line"> <vscale x 1 x half>,</span><br><span class="line"> iXLen, iXLen, iXLen);</span><br><span class="line"></span><br><span class="line">define <vscale x 1 x half> @intrinsic_vfnmadd_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, iXLen %3) nounwind {</span><br><span class="line">; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv1f16_nxv1f16_nxv1f16:</span><br><span class="line">; CHECK: # %bb.0: # %entry</span><br><span class="line">; CHECK-NEXT: fsrmi a1, 0</span><br><span class="line">; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma</span><br><span class="line">; CHECK-NEXT: vfnmadd.vv v8, v9, v10</span><br><span class="line">; CHECK-NEXT: fsrm a1</span><br><span class="line">; CHECK-NEXT: ret</span><br><span class="line">entry:</span><br><span class="line"> %a = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16(</span><br><span class="line"> <vscale x 1 x half> %0,</span><br><span class="line"> <vscale x 1 x half> %1,</span><br><span class="line"> <vscale x 1 x half> %2,</span><br><span class="line"> iXLen 0, iXLen %3, iXLen 0)</span><br><span class="line"></span><br><span class="line"> ret <vscale x 1 x half> %a</span><br><span class="line">}</span><br><span class="line"></span><br><span class="line">declare <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.nxv1f16(</span><br><span class="line"> <vscale x 1 x half>,</span><br><span class="line"> <vscale x 1 x half>,</span><br><span class="line"> <vscale x 1 x half>,</span><br><span class="line"> <vscale x 1 x i1>,</span><br><span class="line"> iXLen, iXLen, iXLen);</span><br><span class="line"></span><br><span class="line">define <vscale x 1 x half> @intrinsic_vfnmadd_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {</span><br><span class="line">; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv1f16_nxv1f16_nxv1f16:</span><br><span class="line">; CHECK: # %bb.0: # %entry</span><br><span class="line">; CHECK-NEXT: fsrmi a1, 0</span><br><span class="line">; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu</span><br><span class="line">; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t</span><br><span class="line">; CHECK-NEXT: fsrm a1</span><br><span class="line">; CHECK-NEXT: ret</span><br><span class="line">entry:</span><br><span class="line"> %a = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.nxv1f16(</span><br><span class="line"> <vscale x 1 x half> %0,</span><br><span class="line"> <vscale x 1 x half> %1,</span><br><span class="line"> <vscale x 1 x half> %2,</span><br><span class="line"> <vscale x 1 x i1> %3,</span><br><span class="line"> iXLen 0, iXLen %4, iXLen 0);</span><br><span class="line"></span><br><span class="line"> ret <vscale x 1 x half> %a</span><br><span class="line">}</span><br></pre></td></tr></table></figure>
<p>但是这是老版本的half.ll</p>
<figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br><span class="line">13</span><br><span class="line">14</span><br><span class="line">15</span><br></pre></td><td class="code"><pre><span class="line">; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)</span><br><span class="line">define dso_local half @fnmadd_f(half noundef %a, half noundef %b, half noundef %c) local_unnamed_addr {</span><br><span class="line">; VENTUS-LABEL: fnmadd_f:</span><br><span class="line">; VENTUS: # %bb.0: # %entry</span><br><span class="line">; VENTUS-NEXT: lui t0, %hi(.LCPI26_0)</span><br><span class="line">; VENTUS-NEXT: lw t0, %lo(.LCPI26_0)(t0)</span><br><span class="line">; VENTUS-NEXT: vadd.vx v0, v1, zero</span><br><span class="line">; VENTUS-NEXT: vmv.v.x v1, t0</span><br><span class="line">; VENTUS-NEXT: vfmsub.vv v0, v1, v2</span><br><span class="line">; VENTUS-NEXT: ret</span><br><span class="line">entry:</span><br><span class="line"> %fneg = fmul half %b, 0xBFF3333340000000</span><br><span class="line"> %sub = fsub half %fneg, %c</span><br><span class="line"> ret half %sub</span><br><span class="line">}</span><br></pre></td></tr></table></figure>
<p>导致出错的正好是0xBFF333334000000，相关数字在新LLVM中完全消失了</p>
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<a class="p-name article-title" href="/2025/05/20/report-fix/">ventus LLVM 初步 调研 report-fix</a>
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<p>Q:第一个细节是技术上要注意一下：ventus-llvm的llc调用命令要参考ventus-llvm的readme，加上<code>-mtriple=riscv32 -mcpu=ventus-gpgpu</code>；而官方llvm的llc调用命令则是加上<code>-mtriple=riscv32 -mattr=+v,+zvfh</code>。这样应该就能解决“承影的产生代码是x86MIR而不是RISC-V MIR”以及“官方llvm跑half.ll会报错”的问题，试一试。<br>A:加上-mtriple=riscv32 -mcpu=ventus-gpgpu确实产生了riscv的MIR 但是官方执行<code>/home/wjsun/LLVM/build/bin/llc -march=riscv32 -mattr=+v,+zvfh --debug-only=isel half.ll &> out.log</code>仍然报错</p>
<figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br></pre></td><td class="code"><pre><span class="line">/home/wjsun/LLVM/build/bin/llc: error: /home/wjsun/LLVM/build/bin/llc: half.ll:369:25: error: floating point constant invalid for type</span><br><span class="line"> %fneg = fmul half %b, 0xBFF3333340000000</span><br><span class="line"> ^</span><br><span class="line"></span><br></pre></td></tr></table></figure>
<p>Q:<br>第二个细节是表达上要注意一下：要展示MIR的差异之处的话，可以直接把ventus-llvm和官方llvm在“===== Instruction selection ends:”之后的结果摆在一起，这样再得出“MIR加的指令的表示方式不同”的结论，这样会更加顺畅；而要展示发现有报错时，在贴报错信息的时候可以同步贴上执行命令，方便后续复现。<br>A：已修改()<br>Q:</p>
<ol>
<li>对于float.ll的测试，这里的差别确实是MIR加的指令的表示方式不同，不过更具体来说，是官方llvm会产生标量加指令FADD_S，而ventus-llvm却会出现向量加指令VFADD_VV。是的，同样的代码，官方会得到标量MIR，承影却会得到向量MIR，这是一个重点。<br>A:是的！完全是这样的。<br>Q:由于官方llvm对于float.ll和half.ll都只生成标量代码，如果把“-mattr=+v,+zvfh”换成“-mattr=+zfh”，可以看到最终结果跟“支持标量half”文档里官方llvm的结果应该是相似的。<br>执行/home/wjsun/LLVM/build/bin/llc -march=riscv32 -mattr=+zfh –debug-only=isel half.ll &> out.log</li>
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<p>仍然报错</p>
<figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br></pre></td><td class="code"><pre><span class="line">/home/wjsun/LLVM/build/bin/llc: error: /home/wjsun/LLVM/build/bin/llc: half.ll:369:25: error: floating point constant invalid for type</span><br><span class="line"> %fneg = fmul half %b, 0xBFF3333340000000</span><br></pre></td></tr></table></figure>
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<h1 id="Pretask-J142-PLCT-20250510"><a href="#Pretask-J142-PLCT-20250510" class="headerlink" title="Pretask-J142-PLCT-20250510"></a>Pretask-J142-PLCT-20250510</h1><h2 id="乘影-LLVM-与官方-LLVM-的-RISC-V-ZVFH-扩展支持对比及指令选择阶段分析"><a href="#乘影-LLVM-与官方-LLVM-的-RISC-V-ZVFH-扩展支持对比及指令选择阶段分析" class="headerlink" title="乘影 LLVM 与官方 LLVM 的 RISC-V ZVFH 扩展支持对比及指令选择阶段分析"></a>乘影 LLVM 与官方 LLVM 的 RISC-V ZVFH 扩展支持对比及指令选择阶段分析</h2><h3 id="概述"><a href="#概述" class="headerlink" title="概述"></a>概述</h3><p>主要对比乘影 LLVM（ventus-llvm）与官方 LLVM 在 ZVFH 扩展支持方面的实现差异，特别关注指令选择阶段。需要同时在 float 和 half 数据类型上做测试。</p>
<h3 id="前置知识"><a href="#前置知识" class="headerlink" title="前置知识"></a>前置知识</h3><p>学习前置知识了解了zvfh和zvfhmin是什么</p>
<h3 id="1-环境搭建与验证"><a href="#1-环境搭建与验证" class="headerlink" title="1. 环境搭建与验证"></a>1. 环境搭建与验证</h3><ul>
<li>克隆乘影编译器源码仓库 ventus-llvm（J142 岗位描述中提供），编译并成功构建 ventus-llvm。跑通 README 中给出的示例。<br> 成功编译产生llc，但是没有成功编译产生vecadd，原因出在gcc版本和clang的版本上。</li>
</ul>
<h3 id="2-乘影-LLVM-向量-float-测试"><a href="#2-乘影-LLVM-向量-float-测试" class="headerlink" title="2. 乘影 LLVM 向量 float 测试"></a>2. 乘影 LLVM 向量 float 测试</h3><p>这里需注意的，应该在build ventus-llvm的时候开启debug选项，不然编译出来release版本就没有办法看debug信息了！</p>
<h4 id="参考-Pretask-20250424-中“附录2：开发提示-标量-half-类型支持”的写法，使用乘影编译器的-llc-对-Pretask-20250424-的“调研提示”中提到的-float-ll-进行编译。"><a href="#参考-Pretask-20250424-中“附录2：开发提示-标量-half-类型支持”的写法，使用乘影编译器的-llc-对-Pretask-20250424-的“调研提示”中提到的-float-ll-进行编译。" class="headerlink" title="-参考 Pretask-20250424 中“附录2：开发提示 - 标量 half 类型支持”的写法，使用乘影编译器的 llc 对 Pretask-20250424 的“调研提示”中提到的 float.ll 进行编译。"></a>-参考 Pretask-20250424 中“附录2：开发提示 - 标量 half 类型支持”的写法，使用乘影编译器的 <code>llc</code> 对 Pretask-20250424 的“调研提示”中提到的 <code>float.ll</code> 进行编译。</h4><p>我使用命令<code>/home/sunwenjia/ventus/llvm-project/install/bin/llc --debug-only=isel float.ll &> ~/output2.log</code><br>观察产生MIR的代码，发现是x86MIR。</p>
<h4 id="添加编译选项-debug-only-isel，打印出指令选择阶段的-log-文件。"><a href="#添加编译选项-debug-only-isel，打印出指令选择阶段的-log-文件。" class="headerlink" title="添加编译选项 --debug-only=isel，打印出指令选择阶段的 log 文件。"></a>添加编译选项 <code>--debug-only=isel</code>，打印出指令选择阶段的 log 文件。</h4><p>生成log如下</p>
<figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br><span class="line">13</span><br><span class="line">14</span><br><span class="line">15</span><br><span class="line">16</span><br><span class="line">17</span><br><span class="line">18</span><br><span class="line">19</span><br><span class="line">20</span><br><span class="line">21</span><br><span class="line">22</span><br><span class="line">23</span><br><span class="line">24</span><br><span class="line">25</span><br><span class="line">26</span><br><span class="line">27</span><br><span class="line">28</span><br><span class="line">29</span><br><span class="line">30</span><br><span class="line">31</span><br><span class="line">32</span><br><span class="line">33</span><br><span class="line">34</span><br><span class="line">35</span><br><span class="line">36</span><br><span class="line">37</span><br><span class="line">38</span><br><span class="line">39</span><br><span class="line">40</span><br><span class="line">41</span><br><span class="line">42</span><br><span class="line">43</span><br><span class="line">44</span><br><span class="line">45</span><br><span class="line">46</span><br><span class="line">47</span><br><span class="line">48</span><br><span class="line">49</span><br><span class="line">50</span><br><span class="line">51</span><br><span class="line">52</span><br><span class="line">53</span><br><span class="line">54</span><br><span class="line">55</span><br><span class="line">56</span><br><span class="line">57</span><br><span class="line">58</span><br><span class="line">59</span><br><span class="line">60</span><br><span class="line">61</span><br><span class="line">62</span><br><span class="line">63</span><br><span class="line">64</span><br><span class="line">65</span><br><span class="line">66</span><br><span class="line">67</span><br><span class="line">68</span><br><span class="line">69</span><br><span class="line">70</span><br><span class="line">71</span><br><span class="line">72</span><br><span class="line">73</span><br><span class="line">74</span><br><span class="line">75</span><br><span class="line">76</span><br><span class="line">77</span><br><span class="line">78</span><br><span class="line">79</span><br><span class="line">80</span><br><span class="line">81</span><br><span class="line">82</span><br><span class="line">83</span><br><span class="line">84</span><br><span class="line">85</span><br><span class="line">86</span><br><span class="line">87</span><br><span class="line">88</span><br><span class="line">89</span><br><span class="line">90</span><br><span class="line">91</span><br><span class="line">92</span><br><span class="line">93</span><br><span class="line">94</span><br><span class="line">95</span><br><span class="line">96</span><br><span class="line">97</span><br><span class="line">98</span><br><span class="line">99</span><br><span class="line">100</span><br><span class="line">101</span><br><span class="line">102</span><br><span class="line">103</span><br><span class="line">104</span><br><span class="line">105</span><br><span class="line">106</span><br><span class="line">107</span><br><span class="line">108</span><br><span class="line">109</span><br><span class="line">110</span><br><span class="line">111</span><br><span class="line">112</span><br><span class="line">113</span><br><span class="line">114</span><br><span class="line">115</span><br><span class="line">116</span><br><span class="line">117</span><br></pre></td><td class="code"><pre><span class="line">=== fadd_v</span><br><span class="line">Initial selection DAG: %bb.0 'fadd_v:entry'</span><br><span class="line">SelectionDAG has 9 nodes:</span><br><span class="line"> t0: ch,glue = EntryToken</span><br><span class="line"> t2: f32,ch = CopyFromReg # D:1 t0, Register:f32 %0</span><br><span class="line"> t4: f32,ch = CopyFromReg # D:1 t0, Register:f32 %1</span><br><span class="line"> t5: f32 = fadd # D:1 t2, t4</span><br><span class="line"> t7: ch,glue = CopyToReg # D:1 t0, Register:f32 $v0, t5</span><br><span class="line"> t8: ch = RISCVISD::RET_FLAG # D:1 t7, Register:f32 $v0, t7:1</span><br><span class="line"></span><br><span class="line"></span><br><span class="line">Optimized lowered selection DAG: %bb.0 'fadd_v:entry'</span><br><span class="line">SelectionDAG has 9 nodes:</span><br><span class="line"> t0: ch,glue = EntryToken</span><br><span class="line"> t2: f32,ch = CopyFromReg # D:1 t0, Register:f32 %0</span><br><span class="line"> t4: f32,ch = CopyFromReg # D:1 t0, Register:f32 %1</span><br><span class="line"> t5: f32 = fadd # D:1 t2, t4</span><br><span class="line"> t7: ch,glue = CopyToReg # D:1 t0, Register:f32 $v0, t5</span><br><span class="line"> t8: ch = RISCVISD::RET_FLAG # D:1 t7, Register:f32 $v0, t7:1</span><br><span class="line"></span><br><span class="line"></span><br><span class="line">Type-legalized selection DAG: %bb.0 'fadd_v:entry'</span><br><span class="line">SelectionDAG has 9 nodes:</span><br><span class="line"> t0: ch,glue = EntryToken</span><br><span class="line"> t2: f32,ch = CopyFromReg # D:1 t0, Register:f32 %0</span><br><span class="line"> t4: f32,ch = CopyFromReg # D:1 t0, Register:f32 %1</span><br><span class="line"> t5: f32 = fadd # D:1 t2, t4</span><br><span class="line"> t7: ch,glue = CopyToReg # D:1 t0, Register:f32 $v0, t5</span><br><span class="line"> t8: ch = RISCVISD::RET_FLAG # D:1 t7, Register:f32 $v0, t7:1</span><br><span class="line"></span><br><span class="line"></span><br><span class="line">Legalized selection DAG: %bb.0 'fadd_v:entry'</span><br><span class="line">SelectionDAG has 9 nodes:</span><br><span class="line"> t0: ch,glue = EntryToken</span><br><span class="line"> t2: f32,ch = CopyFromReg # D:1 t0, Register:f32 %0</span><br><span class="line"> t4: f32,ch = CopyFromReg # D:1 t0, Register:f32 %1</span><br><span class="line"> t5: f32 = fadd # D:1 t2, t4</span><br><span class="line"> t7: ch,glue = CopyToReg # D:1 t0, Register:f32 $v0, t5</span><br><span class="line"> t8: ch = RISCVISD::RET_FLAG # D:1 t7, Register:f32 $v0, t7:1</span><br><span class="line"></span><br><span class="line"></span><br><span class="line">Optimized legalized selection DAG: %bb.0 'fadd_v:entry'</span><br><span class="line">SelectionDAG has 9 nodes:</span><br><span class="line"> t0: ch,glue = EntryToken</span><br><span class="line"> t2: f32,ch = CopyFromReg # D:1 t0, Register:f32 %0</span><br><span class="line"> t4: f32,ch = CopyFromReg # D:1 t0, Register:f32 %1</span><br><span class="line"> t5: f32 = fadd # D:1 t2, t4</span><br><span class="line"> t7: ch,glue = CopyToReg # D:1 t0, Register:f32 $v0, t5</span><br><span class="line"> t8: ch = RISCVISD::RET_FLAG # D:1 t7, Register:f32 $v0, t7:1</span><br><span class="line"></span><br><span class="line"></span><br><span class="line">===== Instruction selection begins: %bb.0 'entry'</span><br><span class="line"></span><br><span class="line">ISEL: Starting selection on root node: t8: ch = RISCVISD::RET_FLAG # D:1 t7, Register:f32 $v0, t7:1</span><br><span class="line">ISEL: Starting pattern match</span><br><span class="line"> Morphed node: t8: ch = PseudoRET # D:1 Register:f32 $v0, t7, t7:1</span><br><span class="line">ISEL: Match complete!</span><br><span class="line"></span><br><span class="line">ISEL: Starting selection on root node: t7: ch,glue = CopyToReg # D:1 t0, Register:f32 $v0, t5</span><br><span class="line"></span><br><span class="line">ISEL: Starting selection on root node: t5: f32 = fadd # D:1 t2, t4</span><br><span class="line">ISEL: Starting pattern match</span><br><span class="line"> Initial Opcode index to 28599</span><br><span class="line"> Match failed at index 28602</span><br><span class="line"> Continuing at 28637</span><br><span class="line"> Match failed at index 28640</span><br><span class="line"> Continuing at 28661</span><br><span class="line"> Match failed at index 28663</span><br><span class="line"> Continuing at 28685</span><br><span class="line"> Match failed at index 28691</span><br><span class="line"> Continuing at 28725</span><br><span class="line"> TypeSwitch[f32] from 28728 to 28731</span><br><span class="line"> Morphed node: t5: f32 = VFADD_VV nofpexcept # D:1 t2, t4</span><br><span class="line">ISEL: Match complete!</span><br><span class="line"></span><br><span class="line">ISEL: Starting selection on root node: t4: f32,ch = CopyFromReg # D:1 t0, Register:f32 %1</span><br><span class="line"></span><br><span class="line">ISEL: Starting selection on root node: t2: f32,ch = CopyFromReg # D:1 t0, Register:f32 %0</span><br><span class="line"></span><br><span class="line">ISEL: Starting selection on root node: t6: f32 = Register $v0</span><br><span class="line"></span><br><span class="line">ISEL: Starting selection on root node: t3: f32 = Register %1</span><br><span class="line"></span><br><span class="line">ISEL: Starting selection on root node: t1: f32 = Register %0</span><br><span class="line"></span><br><span class="line">ISEL: Starting selection on root node: t0: ch,glue = EntryToken</span><br><span class="line"></span><br><span class="line">===== Instruction selection ends:</span><br><span class="line">Selected selection DAG: %bb.0 'fadd_v:entry'</span><br><span class="line">SelectionDAG has 9 nodes:</span><br><span class="line"> t0: ch,glue = EntryToken</span><br><span class="line"> t2: f32,ch = CopyFromReg # D:1 t0, Register:f32 %0</span><br><span class="line"> t4: f32,ch = CopyFromReg # D:1 t0, Register:f32 %1</span><br><span class="line"> t5: f32 = VFADD_VV nofpexcept # D:1 t2, t4</span><br><span class="line"> t7: ch,glue = CopyToReg # D:1 t0, Register:f32 $v0, t5</span><br><span class="line"> t8: ch = PseudoRET # D:1 Register:f32 $v0, t7, t7:1</span><br><span class="line"></span><br><span class="line"></span><br><span class="line">Total amount of phi nodes to update: 0</span><br><span class="line">*** MachineFunction at end of ISel ***</span><br><span class="line"># Machine code for function fadd_v: IsSSA, TracksLiveness</span><br><span class="line">Function Live Ins: $v0 in %0, $v1 in %1</span><br><span class="line"></span><br><span class="line">bb.0.entry:</span><br><span class="line"> liveins: $v0, $v1</span><br><span class="line"> %1:vgpr = COPY $v1</span><br><span class="line"> %0:vgpr = COPY $v0</span><br><span class="line"> %2:vgpr = nofpexcept VFADD_VV %0:vgpr, %1:vgpr, implicit $frm</span><br><span class="line"> $v0 = COPY %2:vgpr</span><br><span class="line"> PseudoRET implicit $v0</span><br><span class="line"></span><br><span class="line"># End machine code for function fadd_v.</span><br><span class="line"></span><br><span class="line">.......</span><br><span class="line"></span><br><span class="line"></span><br><span class="line"></span><br></pre></td></tr></table></figure>
<p>产生了riscv代码<br>阅读并理解 log 文件中输出的内容，了解指令是如何从 SelectionDAG 节点映射到 MIR 机器指令的。相关资料博客<a target="_blank" rel="noopener" href="https://myhsu.xyz/llvm-codegen-legalization/">Legalizations in LLVM Backend</a><br>那么它总共有这几个流程</p>
<figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br></pre></td><td class="code"><pre><span class="line">Initial selection DAG: %bb.0 'fadd_v:entry'</span><br><span class="line">SelectionDAG has 9 nodes:</span><br><span class="line"> t0: ch,glue = EntryToken</span><br><span class="line"> t2: f32,ch = CopyFromReg # D:1 t0, Register:f32 %0</span><br><span class="line"> t4: f32,ch = CopyFromReg # D:1 t0, Register:f32 %1</span><br><span class="line"> t5: f32 = fadd # D:1 t2, t4</span><br><span class="line"> t7: ch,glue = CopyToReg # D:1 t0, Register:f32 $v0, t5</span><br><span class="line"> t8: ch = RISCVISD::RET_FLAG # D:1 t7, Register:f32 $v0, t7:1</span><br><span class="line"></span><br><span class="line"></span><br></pre></td></tr></table></figure>
<p>这是开始的dag</p>
<figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br></pre></td><td class="code"><pre><span class="line">Optimized lowered selection DAG: %bb.0 'fadd_v:entry'</span><br><span class="line">SelectionDAG has 9 nodes:</span><br><span class="line"> t0: ch,glue = EntryToken</span><br><span class="line"> t2: f32,ch = CopyFromReg # D:1 t0, Register:f32 %0</span><br><span class="line"> t4: f32,ch = CopyFromReg # D:1 t0, Register:f32 %1</span><br><span class="line"> t5: f32 = fadd # D:1 t2, t4</span><br><span class="line"> t7: ch,glue = CopyToReg # D:1 t0, Register:f32 $v0, t5</span><br><span class="line"> t8: ch = RISCVISD::RET_FLAG # D:1 t7, Register:f32 $v0, t7:1</span><br><span class="line"></span><br><span class="line">对这个DAG图使用pass优化,比如死代码消除等</span><br></pre></td></tr></table></figure>
<figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br></pre></td><td class="code"><pre><span class="line"></span><br><span class="line">Type-legalized selection DAG: %bb.0 'fadd_v:entry'</span><br><span class="line">SelectionDAG has 9 nodes:</span><br><span class="line"> t0: ch,glue = EntryToken</span><br><span class="line"> t2: f32,ch = CopyFromReg # D:1 t0, Register:f32 %0</span><br><span class="line"> t4: f32,ch = CopyFromReg # D:1 t0, Register:f32 %1</span><br><span class="line"> t5: f32 = fadd # D:1 t2, t4</span><br><span class="line"> t7: ch,glue = CopyToReg # D:1 t0, Register:f32 $v0, t5</span><br><span class="line"> t8: ch = RISCVISD::RET_FLAG # D:1 t7, Register:f32 $v0, t7:1</span><br><span class="line">这里是类型合法化，让当前代码映射到指定架构目标上</span><br></pre></td></tr></table></figure>
<figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br></pre></td><td class="code"><pre><span class="line">Legalized selection DAG: %bb.0 'fadd_v:entry'</span><br><span class="line">SelectionDAG has 9 nodes:</span><br><span class="line"> t0: ch,glue = EntryToken</span><br><span class="line"> t2: f32,ch = CopyFromReg # D:1 t0, Register:f32 %0</span><br><span class="line"> t4: f32,ch = CopyFromReg # D:1 t0, Register:f32 %1</span><br><span class="line"> t5: f32 = fadd # D:1 t2, t4</span><br><span class="line"> t7: ch,glue = CopyToReg # D:1 t0, Register:f32 $v0, t5</span><br><span class="line"> t8: ch = RISCVISD::RET_FLAG # D:1 t7, Register:f32 $v0, t7:1</span><br><span class="line"> 这里应该还进行了操作合法化</span><br></pre></td></tr></table></figure>
<figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br></pre></td><td class="code"><pre><span class="line">Optimized legalized selection DAG: %bb.0 'fadd_v:entry'</span><br><span class="line">SelectionDAG has 9 nodes:</span><br><span class="line"> t0: ch,glue = EntryToken</span><br><span class="line"> t2: f32,ch = CopyFromReg # D:1 t0, Register:f32 %0</span><br><span class="line"> t4: f32,ch = CopyFromReg # D:1 t0, Register:f32 %1</span><br><span class="line"> t5: f32 = fadd # D:1 t2, t4</span><br><span class="line"> t7: ch,glue = CopyToReg # D:1 t0, Register:f32 $v0, t5</span><br><span class="line"> t8: ch = RISCVISD::RET_FLAG # D:1 t7, Register:f32 $v0, t7:1</span><br><span class="line">再进行一遍优化？</span><br></pre></td></tr></table></figure>
<figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br><span class="line">13</span><br><span class="line">14</span><br><span class="line">15</span><br><span class="line">16</span><br><span class="line">17</span><br><span class="line">18</span><br><span class="line">19</span><br><span class="line">20</span><br><span class="line">21</span><br><span class="line">22</span><br><span class="line">23</span><br><span class="line">24</span><br><span class="line">25</span><br><span class="line">26</span><br><span class="line">27</span><br><span class="line">28</span><br><span class="line">29</span><br><span class="line">30</span><br><span class="line">31</span><br><span class="line">32</span><br><span class="line">33</span><br><span class="line">34</span><br><span class="line">35</span><br><span class="line">36</span><br><span class="line">37</span><br><span class="line">38</span><br><span class="line">39</span><br></pre></td><td class="code"><pre><span class="line">===== Instruction selection begins: %bb.0 'entry'</span><br><span class="line"></span><br><span class="line">ISEL: Starting selection on root node: t8: ch = RISCVISD::RET_FLAG # D:1 t7, Register:f32 $v0, t7:1</span><br><span class="line">ISEL: Starting pattern match</span><br><span class="line"> Morphed node: t8: ch = PseudoRET # D:1 Register:f32 $v0, t7, t7:1</span><br><span class="line">ISEL: Match complete!</span><br><span class="line"></span><br><span class="line">ISEL: Starting selection on root node: t7: ch,glue = CopyToReg # D:1 t0, Register:f32 $v0, t5</span><br><span class="line"></span><br><span class="line">ISEL: Starting selection on root node: t5: f32 = fadd # D:1 t2, t4</span><br><span class="line">ISEL: Starting pattern match</span><br><span class="line"> Initial Opcode index to 28599</span><br><span class="line"> Match failed at index 28602</span><br><span class="line"> Continuing at 28637</span><br><span class="line"> Match failed at index 28640</span><br><span class="line"> Continuing at 28661</span><br><span class="line"> Match failed at index 28663</span><br><span class="line"> Continuing at 28685</span><br><span class="line"> Match failed at index 28691</span><br><span class="line"> Continuing at 28725</span><br><span class="line"> TypeSwitch[f32] from 28728 to 28731</span><br><span class="line"> Morphed node: t5: f32 = VFADD_VV nofpexcept # D:1 t2, t4</span><br><span class="line">ISEL: Match complete!</span><br><span class="line"></span><br><span class="line">ISEL: Starting selection on root node: t4: f32,ch = CopyFromReg # D:1 t0, Register:f32 %1</span><br><span class="line"></span><br><span class="line">ISEL: Starting selection on root node: t2: f32,ch = CopyFromReg # D:1 t0, Register:f32 %0</span><br><span class="line"></span><br><span class="line">ISEL: Starting selection on root node: t6: f32 = Register $v0</span><br><span class="line"></span><br><span class="line">ISEL: Starting selection on root node: t3: f32 = Register %1</span><br><span class="line"></span><br><span class="line">ISEL: Starting selection on root node: t1: f32 = Register %0</span><br><span class="line"></span><br><span class="line">ISEL: Starting selection on root node: t0: ch,glue = EntryToken</span><br><span class="line"></span><br><span class="line">===== Instruction selection ends:</span><br><span class="line"></span><br><span class="line">这里是匹配MIR代码</span><br></pre></td></tr></table></figure>
<figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br></pre></td><td class="code"><pre><span class="line">===== Instruction selection ends:</span><br><span class="line">Selected selection DAG: %bb.0 'fadd_v:entry'</span><br><span class="line">SelectionDAG has 9 nodes:</span><br><span class="line"> t0: ch,glue = EntryToken</span><br><span class="line"> t2: f32,ch = CopyFromReg # D:1 t0, Register:f32 %0</span><br><span class="line"> t4: f32,ch = CopyFromReg # D:1 t0, Register:f32 %1</span><br><span class="line"> t5: f32 = VFADD_VV nofpexcept # D:1 t2, t4</span><br><span class="line"> t7: ch,glue = CopyToReg # D:1 t0, Register:f32 $v0, t5</span><br><span class="line"> t8: ch = PseudoRET # D:1 Register:f32 $v0, t7, t7:1</span><br><span class="line"></span><br><span class="line">这里可以看到add指令已经被替换成MIR风格的了</span><br></pre></td></tr></table></figure>
<figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br><span class="line">13</span><br><span class="line">14</span><br><span class="line">15</span><br></pre></td><td class="code"><pre><span class="line">Total amount of phi nodes to update: 0</span><br><span class="line">*** MachineFunction at end of ISel ***</span><br><span class="line"># Machine code for function fadd_v: IsSSA, TracksLiveness</span><br><span class="line">Function Live Ins: $v0 in %0, $v1 in %1</span><br><span class="line"></span><br><span class="line">bb.0.entry:</span><br><span class="line"> liveins: $v0, $v1</span><br><span class="line"> %1:vgpr = COPY $v1</span><br><span class="line"> %0:vgpr = COPY $v0</span><br><span class="line"> %2:vgpr = nofpexcept VFADD_VV %0:vgpr, %1:vgpr, implicit $frm</span><br><span class="line"> $v0 = COPY %2:vgpr</span><br><span class="line"> PseudoRET implicit $v0</span><br><span class="line"></span><br><span class="line"># End machine code for function fadd_v.</span><br><span class="line">MIR代码如上</span><br></pre></td></tr></table></figure>
<h3 id="3-官方-LLVM-向量-float-测试"><a href="#3-官方-LLVM-向量-float-测试" class="headerlink" title="3. 官方 LLVM 向量 float 测试"></a>3. 官方 LLVM 向量 float 测试</h3><figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br><span class="line">13</span><br><span class="line">14</span><br><span class="line">15</span><br><span class="line">16</span><br><span class="line">17</span><br><span class="line">18</span><br><span class="line">19</span><br><span class="line">20</span><br><span class="line">21</span><br><span class="line">22</span><br><span class="line">23</span><br><span class="line">24</span><br><span class="line">25</span><br><span class="line">26</span><br><span class="line">27</span><br><span class="line">28</span><br><span class="line">29</span><br><span class="line">30</span><br><span class="line">31</span><br><span class="line">32</span><br><span class="line">33</span><br><span class="line">34</span><br><span class="line">35</span><br><span class="line">36</span><br><span class="line">37</span><br><span class="line">38</span><br><span class="line">39</span><br><span class="line">40</span><br><span class="line">41</span><br><span class="line">42</span><br><span class="line">43</span><br><span class="line">44</span><br><span class="line">45</span><br><span class="line">46</span><br><span class="line">47</span><br><span class="line">48</span><br><span class="line">49</span><br><span class="line">50</span><br><span class="line">51</span><br><span class="line">52</span><br><span class="line">53</span><br><span class="line">54</span><br><span class="line">55</span><br><span class="line">56</span><br><span class="line">57</span><br><span class="line">58</span><br><span class="line">59</span><br><span class="line">60</span><br><span class="line">61</span><br><span class="line">62</span><br><span class="line">63</span><br><span class="line">64</span><br><span class="line">65</span><br><span class="line">66</span><br><span class="line">67</span><br><span class="line">68</span><br><span class="line">69</span><br><span class="line">70</span><br><span class="line">71</span><br><span class="line">72</span><br><span class="line">73</span><br><span class="line">74</span><br><span class="line">75</span><br><span class="line">76</span><br><span class="line">77</span><br><span class="line">78</span><br><span class="line">79</span><br><span class="line">80</span><br><span class="line">81</span><br><span class="line">82</span><br><span class="line">83</span><br><span class="line">84</span><br><span class="line">85</span><br><span class="line">86</span><br><span class="line">87</span><br><span class="line">88</span><br><span class="line">89</span><br><span class="line">90</span><br><span class="line">91</span><br><span class="line">92</span><br><span class="line">93</span><br><span class="line">94</span><br><span class="line">95</span><br><span class="line">96</span><br><span class="line">97</span><br><span class="line">98</span><br><span class="line">99</span><br><span class="line">100</span><br><span class="line">101</span><br><span class="line">102</span><br><span class="line">103</span><br><span class="line">104</span><br><span class="line">105</span><br><span class="line">106</span><br><span class="line">107</span><br><span class="line">108</span><br><span class="line">109</span><br><span class="line">110</span><br><span class="line">111</span><br><span class="line">112</span><br><span class="line">113</span><br><span class="line">114</span><br></pre></td><td class="code"><pre><span class="line">FastISel is disabled</span><br><span class="line"></span><br><span class="line"></span><br><span class="line"></span><br><span class="line">=== fadd_v</span><br><span class="line"></span><br><span class="line">Initial selection DAG: %bb.0 'fadd_v:entry'</span><br><span class="line">SelectionDAG has 9 nodes:</span><br><span class="line"> t0: ch,glue = EntryToken</span><br><span class="line"> t2: f32,ch = CopyFromReg t0, Register:f32 %0</span><br><span class="line"> t4: f32,ch = CopyFromReg t0, Register:f32 %1</span><br><span class="line"> t5: f32 = fadd t2, t4</span><br><span class="line"> t7: ch,glue = CopyToReg t0, Register:f32 $f10_f, t5</span><br><span class="line"> t8: ch = RISCVISD::RET_GLUE t7, Register:f32 $f10_f, t7:1</span><br><span class="line"></span><br><span class="line"></span><br><span class="line"></span><br><span class="line">Optimized lowered selection DAG: %bb.0 'fadd_v:entry'</span><br><span class="line">SelectionDAG has 9 nodes:</span><br><span class="line"> t0: ch,glue = EntryToken</span><br><span class="line"> t2: f32,ch = CopyFromReg t0, Register:f32 %0</span><br><span class="line"> t4: f32,ch = CopyFromReg t0, Register:f32 %1</span><br><span class="line"> t5: f32 = fadd t2, t4</span><br><span class="line"> t7: ch,glue = CopyToReg t0, Register:f32 $f10_f, t5</span><br><span class="line"> t8: ch = RISCVISD::RET_GLUE t7, Register:f32 $f10_f, t7:1</span><br><span class="line"></span><br><span class="line"></span><br><span class="line"></span><br><span class="line">Type-legalized selection DAG: %bb.0 'fadd_v:entry'</span><br><span class="line">SelectionDAG has 9 nodes:</span><br><span class="line"> t0: ch,glue = EntryToken</span><br><span class="line"> t2: f32,ch = CopyFromReg t0, Register:f32 %0</span><br><span class="line"> t4: f32,ch = CopyFromReg t0, Register:f32 %1</span><br><span class="line"> t5: f32 = fadd t2, t4</span><br><span class="line"> t7: ch,glue = CopyToReg t0, Register:f32 $f10_f, t5</span><br><span class="line"> t8: ch = RISCVISD::RET_GLUE t7, Register:f32 $f10_f, t7:1</span><br><span class="line"></span><br><span class="line"></span><br><span class="line"></span><br><span class="line">Legalized selection DAG: %bb.0 'fadd_v:entry'</span><br><span class="line">SelectionDAG has 9 nodes:</span><br><span class="line"> t0: ch,glue = EntryToken</span><br><span class="line"> t2: f32,ch = CopyFromReg t0, Register:f32 %0</span><br><span class="line"> t4: f32,ch = CopyFromReg t0, Register:f32 %1</span><br><span class="line"> t5: f32 = fadd t2, t4</span><br><span class="line"> t7: ch,glue = CopyToReg t0, Register:f32 $f10_f, t5</span><br><span class="line"> t8: ch = RISCVISD::RET_GLUE t7, Register:f32 $f10_f, t7:1</span><br><span class="line"></span><br><span class="line"></span><br><span class="line"></span><br><span class="line">Optimized legalized selection DAG: %bb.0 'fadd_v:entry'</span><br><span class="line">SelectionDAG has 9 nodes:</span><br><span class="line"> t0: ch,glue = EntryToken</span><br><span class="line"> t2: f32,ch = CopyFromReg t0, Register:f32 %0</span><br><span class="line"> t4: f32,ch = CopyFromReg t0, Register:f32 %1</span><br><span class="line"> t5: f32 = fadd t2, t4</span><br><span class="line"> t7: ch,glue = CopyToReg t0, Register:f32 $f10_f, t5</span><br><span class="line"> t8: ch = RISCVISD::RET_GLUE t7, Register:f32 $f10_f, t7:1</span><br><span class="line"></span><br><span class="line"></span><br><span class="line">===== Instruction selection begins: %bb.0 'entry'</span><br><span class="line"></span><br><span class="line">ISEL: Starting selection on root node: t8: ch = RISCVISD::RET_GLUE t7, Register:f32 $f10_f, t7:1</span><br><span class="line">ISEL: Starting pattern match</span><br><span class="line"> Morphed node: t8: ch = PseudoRET Register:f32 $f10_f, t7, t7:1</span><br><span class="line">ISEL: Match complete!</span><br><span class="line"></span><br><span class="line">ISEL: Starting selection on root node: t7: ch,glue = CopyToReg t0, Register:f32 $f10_f, t5</span><br><span class="line"></span><br><span class="line">ISEL: Starting selection on root node: t5: f32 = fadd t2, t4</span><br><span class="line">ISEL: Starting pattern match</span><br><span class="line"> Initial Opcode index to 1411309</span><br><span class="line"> TypeSwitch[f32] from 1411314 to 1411317</span><br><span class="line"> Morphed node: t5: f32 = FADD_S nofpexcept t2, t4, TargetConstant:i64<7></span><br><span class="line">ISEL: Match complete!</span><br><span class="line"></span><br><span class="line">ISEL: Starting selection on root node: t4: f32,ch = CopyFromReg t0, Register:f32 %1</span><br><span class="line"></span><br><span class="line">ISEL: Starting selection on root node: t2: f32,ch = CopyFromReg t0, Register:f32 %0</span><br><span class="line"></span><br><span class="line">ISEL: Starting selection on root node: t6: f32 = Register $f10_f</span><br><span class="line"></span><br><span class="line">ISEL: Starting selection on root node: t3: f32 = Register %1</span><br><span class="line"></span><br><span class="line">ISEL: Starting selection on root node: t1: f32 = Register %0</span><br><span class="line"></span><br><span class="line">ISEL: Starting selection on root node: t0: ch,glue = EntryToken</span><br><span class="line"></span><br><span class="line">===== Instruction selection ends:</span><br><span class="line"></span><br><span class="line">Selected selection DAG: %bb.0 'fadd_v:entry'</span><br><span class="line">SelectionDAG has 10 nodes:</span><br><span class="line"> t0: ch,glue = EntryToken</span><br><span class="line"> t2: f32,ch = CopyFromReg t0, Register:f32 %0</span><br><span class="line"> t4: f32,ch = CopyFromReg t0, Register:f32 %1</span><br><span class="line"> t5: f32 = FADD_S nofpexcept t2, t4, TargetConstant:i64<7></span><br><span class="line"> t7: ch,glue = CopyToReg t0, Register:f32 $f10_f, t5</span><br><span class="line"> t8: ch = PseudoRET Register:f32 $f10_f, t7, t7:1</span><br><span class="line"></span><br><span class="line"></span><br><span class="line">Total amount of phi nodes to update: 0</span><br><span class="line">*** MachineFunction at end of ISel ***</span><br><span class="line"># Machine code for function fadd_v: IsSSA, TracksLiveness</span><br><span class="line">Function Live Ins: $f10_f in %0, $f11_f in %1</span><br><span class="line"></span><br><span class="line">bb.0.entry:</span><br><span class="line"> liveins: $f10_f, $f11_f</span><br><span class="line"> %1:fpr32 = COPY $f11_f</span><br><span class="line"> %0:fpr32 = COPY $f10_f</span><br><span class="line"> %2:fpr32 = nofpexcept FADD_S %0:fpr32, %1:fpr32, 7, implicit $frm</span><br><span class="line"> $f10_f = COPY %2:fpr32</span><br><span class="line"> PseudoRET implicit $f10_f</span><br><span class="line"></span><br><span class="line"># End machine code for function fadd_v.</span><br></pre></td></tr></table></figure>
<p>发现MIR是不同的，主要的不同是寄存器符号的不同和MIR加的指令的表示方式不同</p>
<p>ventus的MIR如下</p>
<figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br></pre></td><td class="code"><pre><span class="line">bb.0.entry:</span><br><span class="line"> liveins: $v0</span><br><span class="line"> %0:vgpr = COPY $v0</span><br><span class="line"> %1:gpr = LUI target-flags(riscv-hi) @global_val</span><br><span class="line"> %2:gpr = LW killed %1:gpr, target-flags(riscv-lo) @global_val :: (dereferenceable load (s32) from @global_val)</span><br><span class="line"> %3:gprf32 = COPY %2:gpr</span><br><span class="line"> %5:vgpr = COPY %3:gprf32</span><br><span class="line"> %4:vgpr = nofpexcept VFADD_VV %0:vgpr, killed %5:vgpr, implicit $frm</span><br><span class="line"> $v0 = COPY %4:vgpr</span><br><span class="line"> PseudoRET implicit $v0</span><br></pre></td></tr></table></figure>
<p>官方LLVM是这样</p>
<figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br></pre></td><td class="code"><pre><span class="line">bb.0.entry:</span><br><span class="line"> liveins: $f10_f, $f11_f</span><br><span class="line"> %1:fpr32 = COPY $f11_f</span><br><span class="line"> %0:fpr32 = COPY $f10_f</span><br><span class="line"> %2:fpr32 = nofpexcept FADD_S %0:fpr32, %1:fpr32, 7, implicit $frm</span><br><span class="line"> $f10_f = COPY %2:fpr32</span><br><span class="line"> PseudoRET implicit $f10_f</span><br><span class="line"></span><br></pre></td></tr></table></figure>
<p>确实，经过对比发现同样的代码，官方会得到标量MIR，承影却会得到向量MIR，可以清晰的通过上面的对比发现，官方是标量加，ventus是向量加。</p>
<h3 id="4-官方-LLVM-向量-half-测试"><a href="#4-官方-LLVM-向量-half-测试" class="headerlink" title="4. 官方 LLVM 向量 half 测试"></a>4. 官方 LLVM 向量 half 测试</h3><h4 id="将-float-ll-中的所有-float-类型替换为-half，得到新的-half-ll。"><a href="#将-float-ll-中的所有-float-类型替换为-half，得到新的-half-ll。" class="headerlink" title="- 将 float.ll 中的所有 float 类型替换为 half，得到新的 half.ll。"></a>- 将 <code>float.ll</code> 中的所有 <code>float</code> 类型替换为 <code>half</code>，得到新的 <code>half.ll</code>。</h4><h4 id="同样使用官方-LLVM-运行-half-ll-得到MIR指令和-log-文件，观察它们跟运行-float-ll-的差异。"><a href="#同样使用官方-LLVM-运行-half-ll-得到MIR指令和-log-文件，观察它们跟运行-float-ll-的差异。" class="headerlink" title="- 同样使用官方 LLVM 运行 half.ll 得到MIR指令和 log 文件，观察它们跟运行 float.ll 的差异。"></a>- 同样使用官方 LLVM 运行 <code>half.ll</code> 得到MIR指令和 log 文件，观察它们跟运行 <code>float.ll</code> 的差异。</h4><h4 id="最后，尝试也用乘影-LLVM-运行-half-ll-，看是否会有报错，如有则记录报错情况并尝试猜测原因，如没有则记录MIR结果和-log-文件并评估是否符合预期。"><a href="#最后，尝试也用乘影-LLVM-运行-half-ll-，看是否会有报错，如有则记录报错情况并尝试猜测原因，如没有则记录MIR结果和-log-文件并评估是否符合预期。" class="headerlink" title="- 最后，尝试也用乘影 LLVM 运行 half.ll ，看是否会有报错，如有则记录报错情况并尝试猜测原因，如没有则记录MIR结果和 log 文件并评估是否符合预期。"></a>- 最后，尝试也用乘影 LLVM 运行 <code>half.ll</code> ，看是否会有报错，如有则记录报错情况并尝试猜测原因，如没有则记录MIR结果和 log 文件并评估是否符合预期。</h4><figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br><span class="line">13</span><br><span class="line">14</span><br><span class="line">15</span><br><span class="line">16</span><br><span class="line">17</span><br><span class="line">18</span><br><span class="line">19</span><br><span class="line">20</span><br><span class="line">21</span><br><span class="line">22</span><br><span class="line">23</span><br><span class="line">24</span><br><span class="line">25</span><br><span class="line">26</span><br><span class="line">27</span><br><span class="line">28</span><br><span class="line">29</span><br><span class="line">30</span><br><span class="line">31</span><br><span class="line">32</span><br><span class="line">33</span><br><span class="line">34</span><br><span class="line">35</span><br><span class="line">36</span><br><span class="line">37</span><br></pre></td><td class="code"><pre><span class="line"> NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py</span><br><span class="line">; RUN: llc -mtriple=riscv32 -mcpu=ventus-gpgpu -verify-machineinstrs < %s \</span><br><span class="line">; RUN: | FileCheck -check-prefix=VENTUS %s</span><br><span class="line"></span><br><span class="line">define half @fadd_v(half noundef %a, half noundef %b) {</span><br><span class="line">; VENTUS-LABEL: fadd_v:</span><br><span class="line">; VENTUS: # %bb.0: # %entry</span><br><span class="line">; VENTUS-NEXT: vfadd.vv v0, v0, v1</span><br><span class="line">; VENTUS-NEXT: ret</span><br><span class="line">entry:</span><br><span class="line"> %add = fadd half %a, %b</span><br><span class="line"> ret half %add</span><br><span class="line">}</span><br><span class="line"></span><br><span class="line">define half @fadd_f(half noundef %a) {</span><br><span class="line">; VENTUS-LABEL: fadd_f:</span><br><span class="line">; VENTUS: # %bb.0: # %entry</span><br><span class="line">; VENTUS-NEXT: lui t0, %hi(global_val)</span><br><span class="line">; VENTUS-NEXT: lw t0, %lo(global_val)(t0)</span><br><span class="line">; VENTUS-NEXT: vmv.v.x v1, t0</span><br><span class="line">; VENTUS-NEXT: vfadd.vv v0, v0, v1</span><br><span class="line">; VENTUS-NEXT: ret</span><br><span class="line">entry:</span><br><span class="line"> %val = load half, ptr @global_val, align 4</span><br><span class="line"> %add = fadd half %a, %val</span><br><span class="line"> ret half %add</span><br><span class="line">}</span><br><span class="line"></span><br><span class="line">define half @fsub_v(half noundef %a, half noundef %b) {</span><br><span class="line">; VENTUS-LABEL: fsub_v:</span><br><span class="line">; VENTUS: # %bb.0: # %entry</span><br><span class="line">; VENTUS-NEXT: vfsub.vv v0, v0, v1</span><br><span class="line">; VENTUS-NEXT: ret</span><br><span class="line">entry:</span><br><span class="line"> %add = fsub half %a, %b</span><br><span class="line"> ret half %add</span><br><span class="line">}</span><br></pre></td></tr></table></figure>
<p>先用官方llvm编译,但是修改后仍然报错<br>但是官方执行<code>/home/wjsun/LLVM/build/bin/llc -march=riscv32 -mattr=+v,+zvfh --debug-only=isel half.ll &> out.log</code>仍然报错</p>
<figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br></pre></td><td class="code"><pre><span class="line">/home/wjsun/LLVM/build/bin/llc: error: /home/wjsun/LLVM/build/bin/llc: half.ll:369:25: error: floating point constant invalid for type</span><br><span class="line"> %fneg = fmul half %b, 0xBFF3333340000000</span><br></pre></td></tr></table></figure>
<p>都是因为不符合half的存储长度造成的。那么用ventusllvm会好吗？<br>执行命令<code>/home/sunwenjia/ventus/llvm-project/install/bin/llc -mtriple=riscv32 -mcpu=ventus-gpgpu --debug-only=isel float.ll &> out3.log</code><br>也没有改变</p>
<figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br></pre></td><td class="code"><pre><span class="line">/home/sunwenjia/ventus/llvm-project/install/bin/llc: error: /home/sunwenjia/ventus/llvm-project/install/bin/llc: float.ll:207:14: error: floating point constant invalid for type</span><br><span class="line"> store half 0x3FF3333340000000, ptr addrspace(5) %b, align 4</span><br><span class="line"> ^</span><br><span class="line"></span><br><span class="line"> ^</span><br></pre></td></tr></table></figure>
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