diff --git a/boards/common/esp8266/include/periph_conf_common.h b/boards/common/esp8266/include/periph_conf_common.h index 96444e5753b4..18dd71d3cb76 100644 --- a/boards/common/esp8266/include/periph_conf_common.h +++ b/boards/common/esp8266/include/periph_conf_common.h @@ -116,8 +116,8 @@ extern "C" { #define SPI0_SCK_GPIO GPIO14 /**< HSPI / SPI_DEV(0) SCK pin */ #ifndef SPI0_CS0_GPIO -#define SPI0_CS0_GPIO GPIO15 /**< HSPI / SPI_DEV(0) CS default pin, only used when cs - parameter in spi_acquire is GPIO_UNDEF */ +#define SPI0_CS0_GPIO GPIO15 /**< HSPI / SPI_DEV(0) CS default pin, only used when cs + parameter in spi_acquire is GPIO_UNDEF */ #endif #endif /* defined(MODULE_PERIPH_SPI) || defined(DOXYGEN) */ /** @} */ diff --git a/cpu/atmega_common/include/periph_cpu_common.h b/cpu/atmega_common/include/periph_cpu_common.h index 56dc154db4b7..1190ed5e84ab 100644 --- a/cpu/atmega_common/include/periph_cpu_common.h +++ b/cpu/atmega_common/include/periph_cpu_common.h @@ -35,19 +35,19 @@ extern "C" { * @{ */ #define HAVE_GPIO_T -typedef uint8_t gpio_t; +typedef uint16_t gpio_t; /** @} */ #endif /** * @brief Definition of a fitting UNDEF value */ -#define GPIO_UNDEF (0xff) +#define GPIO_UNDEF (0xffff) /** * @brief Define a CPU specific GPIO pin generator macro */ -#define GPIO_PIN(x, y) ((x << 4) | y) +#define GPIO_PIN(x, y) ((x << 4) | y) /** * @brief Override the GPIO flanks diff --git a/cpu/atmega_common/periph/gpio.c b/cpu/atmega_common/periph/gpio.c index b5046005a2fd..347d4874af4a 100644 --- a/cpu/atmega_common/periph/gpio.c +++ b/cpu/atmega_common/periph/gpio.c @@ -218,7 +218,7 @@ static inline uint16_t _pin_addr(gpio_t pin) return (_port_addr(pin) - 0x02); } -int gpio_init(gpio_t pin, gpio_mode_t mode) +int gpio_cpu_init(gpio_t pin, gpio_mode_t mode) { uint8_t pin_mask = (1 << _pin_num(pin)); @@ -241,38 +241,38 @@ int gpio_init(gpio_t pin, gpio_mode_t mode) return 0; } -int gpio_read(gpio_t pin) +int gpio_cpu_read(gpio_t pin) { return (_SFR_MEM8(_pin_addr(pin)) & (1 << _pin_num(pin))); } -void gpio_set(gpio_t pin) +void gpio_cpu_set(gpio_t pin) { _SFR_MEM8(_port_addr(pin)) |= (1 << _pin_num(pin)); } -void gpio_clear(gpio_t pin) +void gpio_cpu_clear(gpio_t pin) { _SFR_MEM8(_port_addr(pin)) &= ~(1 << _pin_num(pin)); } -void gpio_toggle(gpio_t pin) +void gpio_cpu_toggle(gpio_t pin) { - if (gpio_read(pin)) { - gpio_clear(pin); + if (gpio_cpu_read(pin)) { + gpio_cpu_clear(pin); } else { - gpio_set(pin); + gpio_cpu_set(pin); } } -void gpio_write(gpio_t pin, int value) +void gpio_cpu_write(gpio_t pin, int value) { if (value) { - gpio_set(pin); + gpio_cpu_set(pin); } else { - gpio_clear(pin); + gpio_cpu_clear(pin); } } @@ -292,8 +292,8 @@ static inline int8_t _int_num(gpio_t pin) return -1; } -int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, - gpio_cb_t cb, void *arg) +int gpio_cpu_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, + gpio_cb_t cb, void *arg) { int8_t int_num = _int_num(pin); @@ -332,7 +332,7 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, pcint_config[offset].cb = cb; /* init gpio */ - gpio_init(pin, mode); + gpio_cpu_init(pin, mode); /* configure pcint */ cli(); switch (bank) { @@ -385,7 +385,7 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, return -1; } - gpio_init(pin, mode); + gpio_cpu_init(pin, mode); /* clear global interrupt flag */ cli(); @@ -416,13 +416,13 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, return 0; } -void gpio_irq_enable(gpio_t pin) +void gpio_cpu_irq_enable(gpio_t pin) { EIFR |= (1 << _int_num(pin)); EIMSK |= (1 << _int_num(pin)); } -void gpio_irq_disable(gpio_t pin) +void gpio_cpu_irq_disable(gpio_t pin) { EIMSK &= ~(1 << _int_num(pin)); } diff --git a/cpu/cc2538/periph/gpio.c b/cpu/cc2538/periph/gpio.c index 95cf7ae18b65..4935324423c6 100644 --- a/cpu/cc2538/periph/gpio.c +++ b/cpu/cc2538/periph/gpio.c @@ -95,7 +95,7 @@ static inline uint8_t _pp_num(gpio_t pin) return (uint8_t)((_port_num(pin) * GPIO_BITS_PER_PORT) + _pin_num(pin)); } -int gpio_init(gpio_t pin, gpio_mode_t mode) +int gpio_cpu_init(gpio_t pin, gpio_mode_t mode) { /* check if mode is valid */ if (mode == MODE_NOTSUP) { @@ -120,27 +120,27 @@ int gpio_init(gpio_t pin, gpio_mode_t mode) return 0; } -int gpio_read(gpio_t pin) +int gpio_cpu_read(gpio_t pin) { return (int)(gpio(pin)->DATA & _pin_mask(pin)); } -void gpio_set(gpio_t pin) +void gpio_cpu_set(gpio_t pin) { gpio(pin)->DATA |= _pin_mask(pin); } -void gpio_clear(gpio_t pin) +void gpio_cpu_clear(gpio_t pin) { gpio(pin)->DATA &= ~_pin_mask(pin); } -void gpio_toggle(gpio_t pin) +void gpio_cpu_toggle(gpio_t pin) { gpio(pin)->DATA ^= _pin_mask(pin); } -void gpio_write(gpio_t pin, int value) +void gpio_cpu_write(gpio_t pin, int value) { if (value) { gpio(pin)->DATA |= _pin_mask(pin); @@ -151,10 +151,10 @@ void gpio_write(gpio_t pin, int value) } #ifdef MODULE_PERIPH_GPIO_IRQ -int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, - gpio_cb_t cb, void *arg) +int gpio_cpu_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, + gpio_cb_t cb, void *arg) { - if (gpio_init(pin, mode) != 0) { + if (gpio_cpu_init(pin, mode) != 0) { return -1; } @@ -196,12 +196,12 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, return 0; } -void gpio_irq_enable(gpio_t pin) +void gpio_cpu_irq_enable(gpio_t pin) { gpio(pin)->IE |= _pin_mask(pin); } -void gpio_irq_disable(gpio_t pin) +void gpio_cpu_irq_disable(gpio_t pin) { gpio(pin)->IE &= ~_pin_mask(pin); } diff --git a/cpu/cc26x0/periph/gpio.c b/cpu/cc26x0/periph/gpio.c index 1a1c46a7c88a..f8287d0cf3da 100644 --- a/cpu/cc26x0/periph/gpio.c +++ b/cpu/cc26x0/periph/gpio.c @@ -33,7 +33,7 @@ static gpio_isr_ctx_t gpio_chan[GPIO_ISR_CHAN_NUMOF]; #endif /* MODULE_PERIPH_GPIO_IRQ */ -int gpio_init(gpio_t pin, gpio_mode_t mode) +int gpio_cpu_init(gpio_t pin, gpio_mode_t mode) { if ((unsigned int)pin > 31) return -1; @@ -53,7 +53,7 @@ int gpio_init(gpio_t pin, gpio_mode_t mode) return 0; } -int gpio_read(gpio_t pin) +int gpio_cpu_read(gpio_t pin) { if (GPIO->DOE & (1 << pin)) { return (GPIO->DOUT >> pin) & 1; @@ -63,22 +63,22 @@ int gpio_read(gpio_t pin) } } -void gpio_set(gpio_t pin) +void gpio_cpu_set(gpio_t pin) { GPIO->DOUTSET = (1 << pin); } -void gpio_clear(gpio_t pin) +void gpio_cpu_clear(gpio_t pin) { GPIO->DOUTCLR = (1 << pin); } -void gpio_toggle(gpio_t pin) +void gpio_cpu_toggle(gpio_t pin) { GPIO->DOUTTGL = (1 << pin); } -void gpio_write(gpio_t pin, int value) +void gpio_cpu_write(gpio_t pin, int value) { if (value) { GPIO->DOUTSET = (1 << pin); @@ -88,10 +88,10 @@ void gpio_write(gpio_t pin, int value) } #ifdef MODULE_PERIPH_GPIO_IRQ -int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, - gpio_cb_t cb, void *arg) +int gpio_cpu_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, + gpio_cb_t cb, void *arg) { - int init = gpio_init(pin, mode); + int init = gpio_cpu_init(pin, mode); if (init != 0) return init; @@ -105,17 +105,17 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, /* clears the interrupt flag */ GPIO->EVFLAGS |= (1 << pin); - gpio_irq_enable(pin); + gpio_cpu_irq_enable(pin); return 0; } -void gpio_irq_enable(gpio_t pin) +void gpio_cpu_irq_enable(gpio_t pin) { IOC->CFG[pin] |= IOCFG_EDGEIRQ_ENABLE; } -void gpio_irq_disable(gpio_t pin) +void gpio_cpu_irq_disable(gpio_t pin) { IOC->CFG[pin] &= ~IOCFG_EDGEIRQ_ENABLE; } @@ -124,8 +124,8 @@ void isr_edge(void) { for (unsigned pin = 0; pin < GPIO_ISR_CHAN_NUMOF; pin++) { /* doc claims EVFLAGS will only be set for pins that have edge detection enabled */ - if (GPIO->EVFLAGS & (1 << pin)) { - GPIO->EVFLAGS |= (1 << pin); + if (GPIO->EVFLAGS & (1U << pin)) { + GPIO->EVFLAGS |= (1U << pin); gpio_chan[pin].cb(gpio_chan[pin].arg); } } diff --git a/cpu/efm32/periph/gpio.c b/cpu/efm32/periph/gpio.c index 06775e078674..727bb4bbc820 100644 --- a/cpu/efm32/periph/gpio.c +++ b/cpu/efm32/periph/gpio.c @@ -49,7 +49,7 @@ static inline uint32_t _pin_num(gpio_t pin) return (pin & 0x0f); } -int gpio_init(gpio_t pin, gpio_mode_t mode) +int gpio_cpu_init(gpio_t pin, gpio_mode_t mode) { /* check for valid pin */ if (pin == GPIO_UNDEF) { @@ -69,27 +69,27 @@ int gpio_init(gpio_t pin, gpio_mode_t mode) return 0; } -int gpio_read(gpio_t pin) +int gpio_cpu_read(gpio_t pin) { return GPIO_PinInGet(_port_num(pin), _pin_num(pin)); } -void gpio_set(gpio_t pin) +void gpio_cpu_set(gpio_t pin) { GPIO_PinOutSet(_port_num(pin), _pin_num(pin)); } -void gpio_clear(gpio_t pin) +void gpio_cpu_clear(gpio_t pin) { GPIO_PinOutClear(_port_num(pin), _pin_num(pin)); } -void gpio_toggle(gpio_t pin) +void gpio_cpu_toggle(gpio_t pin) { GPIO_PinOutToggle(_port_num(pin), _pin_num(pin)); } -void gpio_write(gpio_t pin, int value) +void gpio_cpu_write(gpio_t pin, int value) { if (value) { GPIO_PinOutSet(_port_num(pin), _pin_num(pin)); @@ -105,10 +105,10 @@ static inline uint32_t _pin_mask(gpio_t pin) return (1 << _pin_num(pin)); } -int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, - gpio_cb_t cb, void *arg) +int gpio_cpu_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, + gpio_cb_t cb, void *arg) { - int result = gpio_init(pin, mode); + int result = gpio_cpu_init(pin, mode); if (result != 0) { return result; @@ -134,12 +134,12 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, return 0; } -void gpio_irq_enable(gpio_t pin) +void gpio_cpu_irq_enable(gpio_t pin) { GPIO_IntEnable(_pin_mask(pin)); } -void gpio_irq_disable(gpio_t pin) +void gpio_cpu_irq_disable(gpio_t pin) { GPIO_IntDisable(_pin_mask(pin)); } diff --git a/cpu/esp32/periph/gpio.c b/cpu/esp32/periph/gpio.c index bf1070261c63..aa9e9b7dc53f 100644 --- a/cpu/esp32/periph/gpio.c +++ b/cpu/esp32/periph/gpio.c @@ -246,7 +246,7 @@ const char* _gpio_pin_usage_str[] = #define GPIO_REG_BIT_XOR(l,h,b) if (b < 32) GPIO.l ^= BIT(b); else GPIO.h.val ^= BIT(b-32) #define REG_SET_CLR_BIT(c,r,f) if (c) REG_SET_BIT(r,f); else REG_CLR_BIT(r,f) -int gpio_init(gpio_t pin, gpio_mode_t mode) +int gpio_cpu_init(gpio_t pin, gpio_mode_t mode) { CHECK_PARAM_RET(pin < GPIO_PIN_NUMOF, -1); @@ -405,10 +405,10 @@ void IRAM gpio_int_handler (void* arg) irq_isr_exit(); } -int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, - gpio_cb_t cb, void *arg) +int gpio_cpu_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, + gpio_cb_t cb, void *arg) { - if (gpio_init(pin, mode)) { + if (gpio_cpu_init(pin, mode)) { return -1; } @@ -428,14 +428,14 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, return 0; } -void gpio_irq_enable (gpio_t pin) +void gpio_cpu_irq_enable (gpio_t pin) { CHECK_PARAM(pin < GPIO_PIN_NUMOF); gpio_int_enabled_table [pin] = true; } -void gpio_irq_disable (gpio_t pin) +void gpio_cpu_irq_disable (gpio_t pin) { CHECK_PARAM(pin < GPIO_PIN_NUMOF); @@ -444,13 +444,13 @@ void gpio_irq_disable (gpio_t pin) #endif /* MODULE_PERIPH_GPIO_IRQ */ -int gpio_read (gpio_t pin) +int gpio_cpu_read (gpio_t pin) { CHECK_PARAM_RET(pin < GPIO_PIN_NUMOF, -1); return GPIO_REG_BIT_GET(in, in1, pin) ? 1 : 0; } -void gpio_write (gpio_t pin, int value) +void gpio_cpu_write(gpio_t pin, int value) { DEBUG("%s gpio=%u val=%d\n", __func__, pin, value); CHECK_PARAM(pin < GPIO_PIN_NUMOF); @@ -462,14 +462,14 @@ void gpio_write (gpio_t pin, int value) } } -void gpio_set (gpio_t pin) +void gpio_cpu_set (gpio_t pin) { DEBUG("%s gpio=%u\n", __func__, pin); CHECK_PARAM(pin < GPIO_PIN_NUMOF); GPIO_PIN_SET(pin); } -void gpio_clear (gpio_t pin) +void gpio_cpu_clear (gpio_t pin) { DEBUG("%s gpio=%u\n", __func__, pin); CHECK_PARAM(pin < GPIO_PIN_NUMOF); @@ -477,7 +477,7 @@ void gpio_clear (gpio_t pin) } -void gpio_toggle (gpio_t pin) +void gpio_cpu_toggle (gpio_t pin) { DEBUG("%s gpio=%u\n", __func__, pin); CHECK_PARAM(pin < GPIO_PIN_NUMOF); @@ -528,5 +528,5 @@ int gpio_config_sleep_mode (gpio_t pin, bool mode, bool input) int gpio_set_direction(gpio_t pin, gpio_mode_t mode) { /* TODO implementation, for the moment we simply initialize the GPIO */ - return gpio_init(pin, mode); + return gpio_cpu_init(pin, mode); } diff --git a/cpu/esp8266/include/periph_cpu.h b/cpu/esp8266/include/periph_cpu.h index 09f0c0451c49..2d373b056c7b 100644 --- a/cpu/esp8266/include/periph_cpu.h +++ b/cpu/esp8266/include/periph_cpu.h @@ -44,16 +44,6 @@ extern "C" { #define PORT_GPIO 0 /**< port GPIO */ /** @} */ -/** - * @brief Definition of a fitting UNDEF value - */ -#define GPIO_UNDEF (GPIO_ID_NONE) - -/** - * @brief Define CPU specific GPIO pin generator macro - */ -#define GPIO_PIN(x, y) ((x << 4) | y) - /** * @brief Define CPU specific number of GPIO pins */ diff --git a/cpu/esp8266/periph/gpio.c b/cpu/esp8266/periph/gpio.c index 5608fad8840a..e35630d12691 100644 --- a/cpu/esp8266/periph/gpio.c +++ b/cpu/esp8266/periph/gpio.c @@ -75,7 +75,7 @@ _gpio_pin_usage_t _gpio_pin_usage [GPIO_PIN_NUMOF] = _GPIO /* gpio16 */ }; -int gpio_init(gpio_t pin, gpio_mode_t mode) +int gpio_cpu_init(gpio_t pin, gpio_mode_t mode) { DEBUG("%s: %d %d\n", __func__, pin, mode); @@ -189,10 +189,10 @@ void IRAM gpio_int_handler (void* arg) irq_isr_exit(); } -int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, - gpio_cb_t cb, void *arg) +int gpio_cpu_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, + gpio_cb_t cb, void *arg) { - if (gpio_init(pin, mode)) { + if (gpio_cpu_init(pin, mode)) { return -1; } @@ -214,14 +214,14 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, return 0; } -void gpio_irq_enable (gpio_t pin) +void gpio_cpu_irq_enable (gpio_t pin) { CHECK_PARAM(pin < GPIO_PIN_NUMOF); gpio_int_enabled_table [pin] = true; } -void gpio_irq_disable (gpio_t pin) +void gpio_cpu_irq_disable (gpio_t pin) { CHECK_PARAM(pin < GPIO_PIN_NUMOF); @@ -229,7 +229,7 @@ void gpio_irq_disable (gpio_t pin) } #endif /* MODULE_PERIPH_GPIO_IRQ */ -int gpio_read (gpio_t pin) +int gpio_cpu_read (gpio_t pin) { CHECK_PARAM_RET(pin < GPIO_PIN_NUMOF, -1); @@ -241,7 +241,7 @@ int gpio_read (gpio_t pin) return (GPIO.IN & BIT(pin)) ? 1 : 0; } -void gpio_write (gpio_t pin, int value) +void gpio_cpu_write(gpio_t pin, int value) { DEBUG("%s: %d %d\n", __func__, pin, value); @@ -261,17 +261,17 @@ void gpio_write (gpio_t pin, int value) } } -void gpio_set (gpio_t pin) +void gpio_cpu_set (gpio_t pin) { - gpio_write (pin, 1); + gpio_cpu_write(pin, 1); } -void gpio_clear (gpio_t pin) +void gpio_cpu_clear (gpio_t pin) { - gpio_write (pin, 0); + gpio_cpu_write(pin, 0); } -void gpio_toggle (gpio_t pin) +void gpio_cpu_toggle (gpio_t pin) { DEBUG("%s: %d\n", __func__, pin); diff --git a/cpu/ezr32wg/periph/gpio.c b/cpu/ezr32wg/periph/gpio.c index 101666c099e0..cc863027b465 100644 --- a/cpu/ezr32wg/periph/gpio.c +++ b/cpu/ezr32wg/periph/gpio.c @@ -57,7 +57,7 @@ static inline int _pin_mask(gpio_t pin) return (1 << _pin_pos(pin)); } -int gpio_init(gpio_t pin, gpio_mode_t mode) +int gpio_cpu_init(gpio_t pin, gpio_mode_t mode) { GPIO_P_TypeDef *port = _port(pin); uint32_t pin_pos = _pin_pos(pin); @@ -82,27 +82,27 @@ int gpio_init(gpio_t pin, gpio_mode_t mode) return 0; } -int gpio_read(gpio_t pin) +int gpio_cpu_read(gpio_t pin) { return _port(pin)->DIN & _pin_mask(pin); } -void gpio_set(gpio_t pin) +void gpio_cpu_set(gpio_t pin) { _port(pin)->DOUTSET = _pin_mask(pin); } -void gpio_clear(gpio_t pin) +void gpio_cpu_clear(gpio_t pin) { _port(pin)->DOUTCLR = _pin_mask(pin); } -void gpio_toggle(gpio_t pin) +void gpio_cpu_toggle(gpio_t pin) { _port(pin)->DOUTTGL = _pin_mask(pin); } -void gpio_write(gpio_t pin, int value) +void gpio_cpu_write(gpio_t pin, int value) { if (value) { _port(pin)->DOUTSET = _pin_mask(pin); @@ -113,13 +113,13 @@ void gpio_write(gpio_t pin, int value) #ifdef MODULE_PERIPH_GPIO_IRQ -int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, - gpio_cb_t cb, void *arg) +int gpio_cpu_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, + gpio_cb_t cb, void *arg) { uint32_t pin_pos = _pin_pos(pin); /* configure as input */ - gpio_init(pin, mode); + gpio_cpu_init(pin, mode); /* just in case, disable interrupt for this channel */ GPIO->IEN &= ~(1 << pin_pos); @@ -140,12 +140,12 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, return 0; } -void gpio_irq_enable(gpio_t pin) +void gpio_cpu_irq_enable(gpio_t pin) { GPIO->IEN |= _pin_mask(pin); } -void gpio_irq_disable(gpio_t pin) +void gpio_cpu_irq_disable(gpio_t pin) { GPIO->IEN &= ~(_pin_mask(pin)); } diff --git a/cpu/fe310/periph/gpio.c b/cpu/fe310/periph/gpio.c index 813d5c0fb84b..87eefce94f73 100644 --- a/cpu/fe310/periph/gpio.c +++ b/cpu/fe310/periph/gpio.c @@ -37,7 +37,7 @@ static gpio_flank_t isr_flank[GPIO_NUMOF]; static gpio_isr_ctx_t isr_ctx[GPIO_NUMOF]; #endif /* MODULE_PERIPH_GPIO_IRQ */ -int gpio_init(gpio_t pin, gpio_mode_t mode) +int gpio_cpu_init(gpio_t pin, gpio_mode_t mode) { /* Check for valid pin */ if (pin >= GPIO_NUMOF) { @@ -75,27 +75,27 @@ int gpio_init(gpio_t pin, gpio_mode_t mode) return 0; } -int gpio_read(gpio_t pin) +int gpio_cpu_read(gpio_t pin) { return (GPIO_REG(GPIO_INPUT_VAL) & (1 << pin)) ? 1 : 0; } -void gpio_set(gpio_t pin) +void gpio_cpu_set(gpio_t pin) { GPIO_REG(GPIO_OUTPUT_VAL) |= (1 << pin); } -void gpio_clear(gpio_t pin) +void gpio_cpu_clear(gpio_t pin) { GPIO_REG(GPIO_OUTPUT_VAL) &= ~(1 << pin); } -void gpio_toggle(gpio_t pin) +void gpio_cpu_toggle(gpio_t pin) { GPIO_REG(GPIO_OUTPUT_VAL) ^= (1 << pin); } -void gpio_write(gpio_t pin, int value) +void gpio_cpu_write(gpio_t pin, int value) { if (value) { GPIO_REG(GPIO_OUTPUT_VAL) |= (1 << pin); @@ -132,11 +132,11 @@ void gpio_isr(int num) } } -int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, - gpio_cb_t cb, void *arg) +int gpio_cpu_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, + gpio_cb_t cb, void *arg) { /* Configure pin */ - if (gpio_init(pin, mode) != 0) { + if (gpio_cpu_init(pin, mode) != 0) { return -1; } @@ -149,7 +149,7 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, PLIC_set_priority(INT_GPIO_BASE + pin, GPIO_INTR_PRIORITY); /* Configure the active flank(s) */ - gpio_irq_enable(pin); + gpio_cpu_irq_enable(pin); /* Save callback */ isr_ctx[pin].cb = cb; @@ -162,7 +162,7 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, return 0; } -void gpio_irq_enable(gpio_t pin) +void gpio_cpu_irq_enable(gpio_t pin) { /* Check for valid pin */ if (pin >= GPIO_NUMOF) { @@ -189,7 +189,7 @@ void gpio_irq_enable(gpio_t pin) } } -void gpio_irq_disable(gpio_t pin) +void gpio_cpu_irq_disable(gpio_t pin) { /* Check for valid pin */ if (pin >= GPIO_NUMOF) { diff --git a/cpu/kinetis/periph/gpio.c b/cpu/kinetis/periph/gpio.c index 2988efd0bcec..34606742855c 100644 --- a/cpu/kinetis/periph/gpio.c +++ b/cpu/kinetis/periph/gpio.c @@ -198,7 +198,7 @@ static inline void clk_en(gpio_t pin) } -int gpio_init(gpio_t pin, gpio_mode_t mode) +int gpio_cpu_init(gpio_t pin, gpio_mode_t mode) { #ifdef KINETIS_HAVE_PCR /* set pin to analog mode while configuring it */ @@ -247,7 +247,7 @@ void gpio_init_port(gpio_t pin, uint32_t pcr) #endif /* KINETIS_HAVE_PCR */ } -int gpio_read(gpio_t pin) +int gpio_cpu_read(gpio_t pin) { if (gpio(pin)->PDDR & (1 << pin_num(pin))) { return (gpio(pin)->PDOR & (1 << pin_num(pin))) ? 1 : 0; @@ -257,22 +257,22 @@ int gpio_read(gpio_t pin) } } -void gpio_set(gpio_t pin) +void gpio_cpu_set(gpio_t pin) { gpio(pin)->PSOR = (1 << pin_num(pin)); } -void gpio_clear(gpio_t pin) +void gpio_cpu_clear(gpio_t pin) { gpio(pin)->PCOR = (1 << pin_num(pin)); } -void gpio_toggle(gpio_t pin) +void gpio_cpu_toggle(gpio_t pin) { gpio(pin)->PTOR = (1 << pin_num(pin)); } -void gpio_write(gpio_t pin, int value) +void gpio_cpu_write(gpio_t pin, int value) { if (value) { gpio(pin)->PSOR = (1 << pin_num(pin)); @@ -283,10 +283,10 @@ void gpio_write(gpio_t pin, int value) } #ifdef MODULE_PERIPH_GPIO_IRQ -int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, - gpio_cb_t cb, void *arg) +int gpio_cpu_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, + gpio_cb_t cb, void *arg) { - if (gpio_init(pin, mode) < 0) { + if (gpio_cpu_init(pin, mode) < 0) { return -1; } @@ -313,13 +313,13 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, return 0; } -void gpio_irq_enable(gpio_t pin) +void gpio_cpu_irq_enable(gpio_t pin) { int ctx = get_ctx(port_num(pin), pin_num(pin)); port(pin)->PCR[pin_num(pin)] |= isr_ctx[ctx].state; } -void gpio_irq_disable(gpio_t pin) +void gpio_cpu_irq_disable(gpio_t pin) { int ctx = get_ctx(port_num(pin), pin_num(pin)); isr_ctx[ctx].state = port(pin)->PCR[pin_num(pin)] & PORT_PCR_IRQC_MASK; diff --git a/cpu/lm4f120/periph/gpio.c b/cpu/lm4f120/periph/gpio.c index e1b5673266bd..37b8460e674e 100644 --- a/cpu/lm4f120/periph/gpio.c +++ b/cpu/lm4f120/periph/gpio.c @@ -96,7 +96,7 @@ static gpio_state_t gpio_config[NUM_OF_PORT][NUM_OF_PINS]; #endif /* MODULE_PERIPH_GPIO_IRQ */ -int gpio_init(gpio_t pin, gpio_mode_t mode) +int gpio_cpu_init(gpio_t pin, gpio_mode_t mode) { const uint8_t port_num = _port_num(pin); const uint32_t port_addr = _port_base[port_num]; @@ -121,7 +121,7 @@ int gpio_init(gpio_t pin, gpio_mode_t mode) return 0; } -int gpio_read(gpio_t pin) +int gpio_cpu_read(gpio_t pin) { const uint8_t port_num = _port_num(pin); const uint32_t port_addr = _port_base[port_num]; @@ -130,7 +130,7 @@ int gpio_read(gpio_t pin) return HWREG(port_addr + ((1<FIOPIN & (1 << _pin(pin))) ? 1 : 0; } -void gpio_set(gpio_t pin) +void gpio_cpu_set(gpio_t pin) { LPC_GPIO_TypeDef *base = _base(pin); base->FIOSET = (1 << _pin(pin)); } -void gpio_clear(gpio_t pin) +void gpio_cpu_clear(gpio_t pin) { LPC_GPIO_TypeDef *base = _base(pin); base->FIOCLR = (1 << _pin(pin)); } -void gpio_toggle(gpio_t pin) +void gpio_cpu_toggle(gpio_t pin) { LPC_GPIO_TypeDef *base = _base(pin); base->FIOPIN ^= (1 << _pin(pin)); } -void gpio_write(gpio_t pin, int value) +void gpio_cpu_write(gpio_t pin, int value) { LPC_GPIO_TypeDef *base = _base(pin); @@ -170,8 +170,8 @@ static inline void _configure_flank(gpio_t pin, gpio_flank_t flank) } } -int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, - gpio_cb_t cb, void *arg) +int gpio_cpu_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, + gpio_cb_t cb, void *arg) { /* only certain pins can be used as interrupt pins */ if (_port(pin) != 0 && _port(pin) != 2) { @@ -179,7 +179,7 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, } /* initialize the pin */ - int result = gpio_init(pin, mode); + int result = gpio_cpu_init(pin, mode); if (result != 0) { return result; @@ -202,14 +202,14 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, return 0; } -void gpio_irq_enable(gpio_t pin) +void gpio_cpu_irq_enable(gpio_t pin) { assert(_port(pin) == 0 || _port(pin) == 2); _configure_flank(pin, isr_state[_port(pin) >> 1][_pin(pin)]); } -void gpio_irq_disable(gpio_t pin) +void gpio_cpu_irq_disable(gpio_t pin) { assert(_port(pin) == 0 || _port(pin) == 2); @@ -231,7 +231,7 @@ void isr_eint3(void) /* invoke all handlers */ for (int i = 0; i < NUMOF_IRQS; i++) { - if (status & (1 << i)) { + if (status & (1U << i)) { isr_ctx[i].cb(isr_ctx[i].arg); LPC_GPIOINT->IO0IntClr |= (1 << i); diff --git a/cpu/lpc2387/periph/gpio.c b/cpu/lpc2387/periph/gpio.c index f62c413b7e12..451a057b6fd1 100644 --- a/cpu/lpc2387/periph/gpio.c +++ b/cpu/lpc2387/periph/gpio.c @@ -67,7 +67,7 @@ void gpio_init_ports(void) { #endif /* MODULE_PERIPH_GPIO_IRQ */ } -int gpio_init(gpio_t pin, gpio_mode_t mode) +int gpio_cpu_init(gpio_t pin, gpio_mode_t mode) { unsigned _pin = pin & 31; unsigned port = pin >> 5; @@ -98,7 +98,7 @@ int gpio_init_mux(unsigned pin, unsigned mux) return 0; } -int gpio_read(gpio_t pin) +int gpio_cpu_read(gpio_t pin) { unsigned _pin = pin & 31; unsigned port = pin >> 5; @@ -106,7 +106,7 @@ int gpio_read(gpio_t pin) return (_port->PIN & (1 << _pin)) != 0; } -void gpio_set(gpio_t pin) +void gpio_cpu_set(gpio_t pin) { unsigned _pin = pin & 31; unsigned port = pin >> 5; @@ -114,7 +114,7 @@ void gpio_set(gpio_t pin) _port->SET = 1 << _pin; } -void gpio_clear(gpio_t pin) +void gpio_cpu_clear(gpio_t pin) { unsigned _pin = pin & 31; unsigned port = pin >> 5; @@ -122,23 +122,23 @@ void gpio_clear(gpio_t pin) _port->CLR = 1 << _pin; } -void gpio_toggle(gpio_t dev) +void gpio_cpu_toggle(gpio_t dev) { - if (gpio_read(dev)) { - gpio_clear(dev); + if (gpio_cpu_read(dev)) { + gpio_cpu_clear(dev); } else { - gpio_set(dev); + gpio_cpu_set(dev); } } -void gpio_write(gpio_t dev, int value) +void gpio_cpu_write(gpio_t dev, int value) { if (value) { - gpio_set(dev); + gpio_cpu_set(dev); } else { - gpio_clear(dev); + gpio_cpu_clear(dev); } } @@ -188,17 +188,17 @@ static void _gpio_configure(gpio_t pin, unsigned rising, unsigned falling) irq_restore(state); } -int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, - gpio_cb_t cb, void *arg) +int gpio_cpu_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, + gpio_cb_t cb, void *arg) { (void)mode; - DEBUG("gpio_init_int(): pin %u\n", pin); + DEBUG("gpio_cpu_init_int(): pin %u\n", pin); int isr_map_entry; /* check if interrupt is possible for this pin */ if ((isr_map_entry = _isr_map_entry(pin)) == -1) { - DEBUG("gpio_init_int(): pin %u cannot be used to generate interrupts.\n", pin); + DEBUG("gpio_cpu_init_int(): pin %u cannot be used to generate interrupts.\n", pin); return -1; } @@ -208,7 +208,7 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, if (_state_index == 0xff) { _state_index = bf_get_unset(_gpio_config_bitfield, GPIO_NUM_ISR); _gpio_isr_map[isr_map_entry] = _state_index; - DEBUG("gpio_init_int(): pin has state_index=%i isr_map_entry=%i\n", _state_index, isr_map_entry); + DEBUG("gpio_cpu_init_int(): pin has state_index=%i isr_map_entry=%i\n", _state_index, isr_map_entry); } if (_state_index == 0xff) { @@ -247,13 +247,13 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, return 0; } -void gpio_irq_enable(gpio_t pin) +void gpio_cpu_irq_enable(gpio_t pin) { int isr_map_entry =_isr_map_entry(pin); int _state_index = _gpio_isr_map[isr_map_entry]; if (_state_index == 0xff) { - DEBUG("gpio_irq_enable(): trying to enable unconfigured pin.\n"); + DEBUG("gpio_cpu_irq_enable(): trying to enable unconfigured pin.\n"); return; } @@ -262,7 +262,7 @@ void gpio_irq_enable(gpio_t pin) bf_isset(_gpio_falling, _state_index)); } -void gpio_irq_disable(gpio_t dev) +void gpio_cpu_irq_disable(gpio_t dev) { _gpio_configure(dev, 0, 0); } diff --git a/cpu/mips_pic32_common/periph/gpio.c b/cpu/mips_pic32_common/periph/gpio.c index 21d5bb226d99..06396b375423 100644 --- a/cpu/mips_pic32_common/periph/gpio.c +++ b/cpu/mips_pic32_common/periph/gpio.c @@ -120,7 +120,7 @@ static inline int check_valid_port(uint8_t port) && base_address[port].gpio != NULL; } -int gpio_init(gpio_t pin, gpio_mode_t mode) +int gpio_cpu_init(gpio_t pin, gpio_mode_t mode) { uint8_t port = GPIO_PORT(pin); uint32_t pin_no = GPIO_PIN_NO(pin); @@ -172,38 +172,38 @@ int gpio_init(gpio_t pin, gpio_mode_t mode) return 0; } -int gpio_read(gpio_t pin) +int gpio_cpu_read(gpio_t pin) { assert(check_valid_port(GPIO_PORT(pin))); return PORTx(GPIO_PORT(pin)) & GPIO_PIN_NO(pin); } -void gpio_set(gpio_t pin) +void gpio_cpu_set(gpio_t pin) { assert(check_valid_port(GPIO_PORT(pin))); LATxSET(GPIO_PORT(pin)) = GPIO_PIN_NO(pin); } -void gpio_clear(gpio_t pin) +void gpio_cpu_clear(gpio_t pin) { assert(check_valid_port(GPIO_PORT(pin))); LATxCLR(GPIO_PORT(pin)) = GPIO_PIN_NO(pin); } -void gpio_toggle(gpio_t pin) +void gpio_cpu_toggle(gpio_t pin) { assert(check_valid_port(GPIO_PORT(pin))); LATxINV(GPIO_PORT(pin)) = GPIO_PIN_NO(pin); } -void gpio_write(gpio_t pin, int value) +void gpio_cpu_write(gpio_t pin, int value) { if (value) - gpio_set(pin); + gpio_cpu_set(pin); else - gpio_clear(pin); + gpio_cpu_clear(pin); } diff --git a/cpu/msp430fxyz/periph/gpio.c b/cpu/msp430fxyz/periph/gpio.c index 2c3ce701810c..bd2aed92ec68 100644 --- a/cpu/msp430fxyz/periph/gpio.c +++ b/cpu/msp430fxyz/periph/gpio.c @@ -67,7 +67,7 @@ static inline msp_port_isr_t *_isr_port(gpio_t pin) return NULL; } -int gpio_init(gpio_t pin, gpio_mode_t mode) +int gpio_cpu_init(gpio_t pin, gpio_mode_t mode) { msp_port_t *port = _port(pin); @@ -111,7 +111,7 @@ void gpio_periph_mode(gpio_t pin, bool enable) } } -int gpio_read(gpio_t pin) +int gpio_cpu_read(gpio_t pin) { msp_port_t *port = _port(pin); if (port->DIR & _pin(pin)) { @@ -122,22 +122,22 @@ int gpio_read(gpio_t pin) } } -void gpio_set(gpio_t pin) +void gpio_cpu_set(gpio_t pin) { _port(pin)->OD |= _pin(pin); } -void gpio_clear(gpio_t pin) +void gpio_cpu_clear(gpio_t pin) { _port(pin)->OD &= ~(_pin(pin)); } -void gpio_toggle(gpio_t pin) +void gpio_cpu_toggle(gpio_t pin) { _port(pin)->OD ^= _pin(pin); } -void gpio_write(gpio_t pin, int value) +void gpio_cpu_write(gpio_t pin, int value) { if (value) { _port(pin)->OD |= _pin(pin); @@ -159,8 +159,8 @@ static int _ctx(gpio_t pin) return (_port(pin) == PORT_1) ? i : (i + 8); } -int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, - gpio_cb_t cb, void *arg) +int gpio_cpu_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, + gpio_cb_t cb, void *arg) { msp_port_isr_t *port = _isr_port(pin); @@ -172,7 +172,7 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, /* disable any activated interrupt */ port->IE &= ~(_pin(pin)); /* configure as input */ - if (gpio_init(pin, mode) < 0) { + if (gpio_cpu_init(pin, mode) < 0) { return -1; } /* save ISR context */ @@ -183,11 +183,11 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, port->IES |= (flank & _pin(pin)); /* clear pending interrupts and enable the IRQ */ port->IFG &= ~(_pin(pin)); - gpio_irq_enable(pin); + gpio_cpu_irq_enable(pin); return 0; } -void gpio_irq_enable(gpio_t pin) +void gpio_cpu_irq_enable(gpio_t pin) { msp_port_isr_t *port = _isr_port(pin); if (port) { @@ -195,7 +195,7 @@ void gpio_irq_enable(gpio_t pin) } } -void gpio_irq_disable(gpio_t pin) +void gpio_cpu_irq_disable(gpio_t pin) { msp_port_isr_t *port = _isr_port(pin); if (port) { diff --git a/cpu/native/periph/gpio.c b/cpu/native/periph/gpio.c index 39f353cbc940..7692f003e89e 100644 --- a/cpu/native/periph/gpio.c +++ b/cpu/native/periph/gpio.c @@ -19,7 +19,7 @@ #include "periph/gpio.h" -int gpio_init(gpio_t pin, gpio_mode_t mode) { +int gpio_cpu_init(gpio_t pin, gpio_mode_t mode) { (void) pin; (void) mode; @@ -29,25 +29,25 @@ int gpio_init(gpio_t pin, gpio_mode_t mode) { return -1; } -int gpio_read(gpio_t pin) { +int gpio_cpu_read(gpio_t pin) { (void) pin; return 0; } -void gpio_set(gpio_t pin) { +void gpio_cpu_set(gpio_t pin) { (void) pin; } -void gpio_clear(gpio_t pin) { +void gpio_cpu_clear(gpio_t pin) { (void) pin; } -void gpio_toggle(gpio_t pin) { +void gpio_cpu_toggle(gpio_t pin) { (void) pin; } -void gpio_write(gpio_t pin, int value) { +void gpio_cpu_write(gpio_t pin, int value) { (void) pin; (void) value; } diff --git a/cpu/nrf5x_common/periph/gpio.c b/cpu/nrf5x_common/periph/gpio.c index f53a773e5c15..8734d2e032e9 100644 --- a/cpu/nrf5x_common/periph/gpio.c +++ b/cpu/nrf5x_common/periph/gpio.c @@ -47,7 +47,7 @@ /** * @brief Index of next interrupt in GPIOTE channel list. * - * The index is incremented at the end of each call to gpio_init_int. + * The index is incremented at the end of each call to gpio_cpu_init_int. * The index cannot be greater or equal than GPIOTE_CHAN_NUMOF. */ static uint8_t _gpiote_next_index = 0; @@ -91,7 +91,7 @@ static inline int pin_num(gpio_t pin) #endif } -int gpio_init(gpio_t pin, gpio_mode_t mode) +int gpio_cpu_init(gpio_t pin, gpio_mode_t mode) { switch (mode) { case GPIO_IN: @@ -110,7 +110,7 @@ int gpio_init(gpio_t pin, gpio_mode_t mode) return 0; } -int gpio_read(gpio_t pin) +int gpio_cpu_read(gpio_t pin) { if (port(pin)->DIR & (1 << pin_num(pin))) { return (port(pin)->OUT & (1 << pin_num(pin))) ? 1 : 0; @@ -120,22 +120,22 @@ int gpio_read(gpio_t pin) } } -void gpio_set(gpio_t pin) +void gpio_cpu_set(gpio_t pin) { port(pin)->OUTSET = (1 << pin_num(pin)); } -void gpio_clear(gpio_t pin) +void gpio_cpu_clear(gpio_t pin) { port(pin)->OUTCLR = (1 << pin_num(pin)); } -void gpio_toggle(gpio_t pin) +void gpio_cpu_toggle(gpio_t pin) { port(pin)->OUT ^= (1 << pin_num(pin)); } -void gpio_write(gpio_t pin, int value) +void gpio_cpu_write(gpio_t pin, int value) { if (value) { port(pin)->OUTSET = (1 << pin_num(pin)); @@ -146,8 +146,8 @@ void gpio_write(gpio_t pin, int value) } #ifdef MODULE_PERIPH_GPIO_IRQ -int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, - gpio_cb_t cb, void *arg) +int gpio_cpu_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, + gpio_cb_t cb, void *arg) { uint8_t _pin_index = 0xff; /* Looking for already known pin in exti table */ @@ -172,7 +172,7 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, exti_chan[_pin_index].cb = cb; exti_chan[_pin_index].arg = arg; /* configure pin as input */ - gpio_init(pin, mode); + gpio_cpu_init(pin, mode); /* set interrupt priority and enable global GPIOTE interrupt */ NVIC_EnableIRQ(GPIOTE_IRQn); /* configure the GPIOTE channel: set even mode, pin and active flank */ @@ -188,7 +188,7 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, return 0; } -void gpio_irq_enable(gpio_t pin) +void gpio_cpu_irq_enable(gpio_t pin) { for (unsigned int i = 0; i < _gpiote_next_index; i++) { if (_exti_pins[i] == pin) { @@ -199,7 +199,7 @@ void gpio_irq_enable(gpio_t pin) } } -void gpio_irq_disable(gpio_t pin) +void gpio_cpu_irq_disable(gpio_t pin) { for (unsigned int i = 0; i < _gpiote_next_index; i++) { if (_exti_pins[i] == pin) { diff --git a/cpu/sam0_common/periph/gpio.c b/cpu/sam0_common/periph/gpio.c index a5f76d946bd3..2d711c45da63 100644 --- a/cpu/sam0_common/periph/gpio.c +++ b/cpu/sam0_common/periph/gpio.c @@ -84,7 +84,7 @@ void gpio_init_mux(gpio_t pin, gpio_mux_t mux) port->PMUX[pin_pos >> 1].reg |= (mux << (4 * (pin_pos & 0x1))); } -int gpio_init(gpio_t pin, gpio_mode_t mode) +int gpio_cpu_init(gpio_t pin, gpio_mode_t mode) { PortGroup* port = _port(pin); int pin_pos = _pin_pos(pin); @@ -117,7 +117,7 @@ int gpio_init(gpio_t pin, gpio_mode_t mode) return 0; } -int gpio_read(gpio_t pin) +int gpio_cpu_read(gpio_t pin) { PortGroup *port = _port(pin); int mask = _pin_mask(pin); @@ -130,22 +130,22 @@ int gpio_read(gpio_t pin) } } -void gpio_set(gpio_t pin) +void gpio_cpu_set(gpio_t pin) { _port(pin)->OUTSET.reg = _pin_mask(pin); } -void gpio_clear(gpio_t pin) +void gpio_cpu_clear(gpio_t pin) { _port(pin)->OUTCLR.reg = _pin_mask(pin); } -void gpio_toggle(gpio_t pin) +void gpio_cpu_toggle(gpio_t pin) { _port(pin)->OUTTGL.reg = _pin_mask(pin); } -void gpio_write(gpio_t pin, int value) +void gpio_cpu_write(gpio_t pin, int value) { if (value) { _port(pin)->OUTSET.reg = _pin_mask(pin); @@ -165,8 +165,8 @@ static int _exti(gpio_t pin) return exti_config[port_num][_pin_pos(pin)]; } -int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, - gpio_cb_t cb, void *arg) +int gpio_cpu_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, + gpio_cb_t cb, void *arg) { int exti = _exti(pin); @@ -179,7 +179,7 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, gpio_config[exti].cb = cb; gpio_config[exti].arg = arg; /* configure pin as input and set MUX to peripheral function A */ - gpio_init(pin, mode); + gpio_cpu_init(pin, mode); gpio_init_mux(pin, GPIO_MUX_A); #ifdef CPU_FAM_SAMD21 /* enable clocks for the EIC module */ @@ -226,7 +226,7 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, return 0; } -void gpio_irq_enable(gpio_t pin) +void gpio_cpu_irq_enable(gpio_t pin) { int exti = _exti(pin); if (exti == -1) { @@ -235,7 +235,7 @@ void gpio_irq_enable(gpio_t pin) _EIC->INTENSET.reg = (1 << exti); } -void gpio_irq_disable(gpio_t pin) +void gpio_cpu_irq_disable(gpio_t pin) { int exti = _exti(pin); if (exti == -1) { diff --git a/cpu/sam3/periph/gpio.c b/cpu/sam3/periph/gpio.c index 4eee2a15050e..daf45c637bbb 100644 --- a/cpu/sam3/periph/gpio.c +++ b/cpu/sam3/periph/gpio.c @@ -147,7 +147,7 @@ static inline int _pin_num(gpio_t pin) return (pin & 0x1f); } -int gpio_init(gpio_t pin, gpio_mode_t mode) +int gpio_cpu_init(gpio_t pin, gpio_mode_t mode) { Pio *port = _port(pin); int pin_num = _pin_num(pin); @@ -206,26 +206,26 @@ void gpio_init_mux(gpio_t pin, gpio_mux_t mux) _port(pin)->PIO_ABSR |= (mux << _pin_num(pin)); } -void gpio_set(gpio_t pin) +void gpio_cpu_set(gpio_t pin) { _port(pin)->PIO_SODR = (1 << _pin_num(pin)); } -void gpio_clear(gpio_t pin) +void gpio_cpu_clear(gpio_t pin) { _port(pin)->PIO_CODR = (1 << _pin_num(pin)); } -void gpio_toggle(gpio_t pin) +void gpio_cpu_toggle(gpio_t pin) { - if (gpio_read(pin)) { + if (gpio_cpu_read(pin)) { _port(pin)->PIO_CODR = (1 << _pin_num(pin)); } else { _port(pin)->PIO_SODR = (1 << _pin_num(pin)); } } -void gpio_write(gpio_t pin, int value) +void gpio_cpu_write(gpio_t pin, int value) { if (value) { _port(pin)->PIO_SODR = (1 << _pin_num(pin)); @@ -234,17 +234,17 @@ void gpio_write(gpio_t pin, int value) } } -void gpio_irq_enable(gpio_t pin) +void gpio_cpu_irq_enable(gpio_t pin) { NVIC_EnableIRQ((1 << (_port_num(pin) + PIOA_IRQn))); } -void gpio_irq_disable(gpio_t pin) +void gpio_cpu_irq_disable(gpio_t pin) { NVIC_DisableIRQ((1 << (_port_num(pin) + PIOA_IRQn))); } -int gpio_read(gpio_t pin) +int gpio_cpu_read(gpio_t pin) { Pio *port = _port(pin); int pin_num = _pin_num(pin); @@ -258,8 +258,8 @@ int gpio_read(gpio_t pin) } #ifdef MODULE_PERIPH_GPIO_IRQ -int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, - gpio_cb_t cb, void *arg) +int gpio_cpu_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, + gpio_cb_t cb, void *arg) { Pio *port = _port(pin); int pin_num = _pin_num(pin); @@ -271,7 +271,7 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, } /* configure pin as input */ - gpio_init(pin, mode); + gpio_cpu_init(pin, mode); /* try go grab a free spot in the context array */ int ctx_num = _get_free_ctx(); @@ -314,7 +314,7 @@ static inline void isr_handler(Pio *port, int port_num) uint32_t status = (port->PIO_ISR & port->PIO_IMR); for (int i = 0; i < 32; i++) { - if (status & (1 << i)) { + if (status & (1U << i)) { int ctx = _ctx(port_num, i); exti_ctx[ctx].cb(exti_ctx[ctx].arg); } diff --git a/cpu/stm32_common/periph/gpio.c b/cpu/stm32_common/periph/gpio.c index dd232d7482b4..cac65a6db0c0 100644 --- a/cpu/stm32_common/periph/gpio.c +++ b/cpu/stm32_common/periph/gpio.c @@ -73,7 +73,7 @@ static inline int _pin_num(gpio_t pin) return (pin & 0x0f); } -int gpio_init(gpio_t pin, gpio_mode_t mode) +int gpio_cpu_init(gpio_t pin, gpio_mode_t mode) { GPIO_TypeDef *port = _port(pin); int pin_num = _pin_num(pin); @@ -127,7 +127,7 @@ void gpio_init_af(gpio_t pin, gpio_af_t af) void gpio_init_analog(gpio_t pin) { /* enable clock, needed as this function can be used without calling - * gpio_init first */ + * gpio_cpu_init first */ #if defined(CPU_FAM_STM32F0) || defined (CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L1) periph_clk_en(AHB, (RCC_AHBENR_GPIOAEN << _port_num(pin))); #elif defined (CPU_FAM_STM32L0) @@ -141,52 +141,52 @@ void gpio_init_analog(gpio_t pin) _port(pin)->MODER |= (0x3 << (2 * _pin_num(pin))); } -void gpio_irq_enable(gpio_t pin) +void gpio_cpu_irq_enable(gpio_t pin) { EXTI->IMR |= (1 << _pin_num(pin)); } -void gpio_irq_disable(gpio_t pin) +void gpio_cpu_irq_disable(gpio_t pin) { EXTI->IMR &= ~(1 << _pin_num(pin)); } -int gpio_read(gpio_t pin) +int gpio_cpu_read(gpio_t pin) { return (_port(pin)->IDR & (1 << _pin_num(pin))); } -void gpio_set(gpio_t pin) +void gpio_cpu_set(gpio_t pin) { _port(pin)->BSRR = (1 << _pin_num(pin)); } -void gpio_clear(gpio_t pin) +void gpio_cpu_clear(gpio_t pin) { _port(pin)->BSRR = (1 << (_pin_num(pin) + 16)); } -void gpio_toggle(gpio_t pin) +void gpio_cpu_toggle(gpio_t pin) { - if (gpio_read(pin)) { - gpio_clear(pin); + if (gpio_cpu_read(pin)) { + gpio_cpu_clear(pin); } else { - gpio_set(pin); + gpio_cpu_set(pin); } } -void gpio_write(gpio_t pin, int value) +void gpio_cpu_write(gpio_t pin, int value) { if (value) { - gpio_set(pin); + gpio_cpu_set(pin); } else { - gpio_clear(pin); + gpio_cpu_clear(pin); } } #ifdef MODULE_PERIPH_GPIO_IRQ -int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, - gpio_cb_t cb, void *arg) +int gpio_cpu_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, + gpio_cb_t cb, void *arg) { int pin_num = _pin_num(pin); int port_num = _port_num(pin); @@ -199,7 +199,7 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, periph_clk_en(APB2, RCC_APB2ENR_SYSCFGEN); /* initialize pin as input */ - gpio_init(pin, mode); + gpio_cpu_init(pin, mode); /* enable global pin interrupt */ #if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32L0) diff --git a/cpu/stm32f1/periph/gpio.c b/cpu/stm32f1/periph/gpio.c index 1d0cec0a3168..cc66631a8646 100644 --- a/cpu/stm32f1/periph/gpio.c +++ b/cpu/stm32f1/periph/gpio.c @@ -75,7 +75,7 @@ static inline int _pin_num(gpio_t pin) } -int gpio_init(gpio_t pin, gpio_mode_t mode) +int gpio_cpu_init(gpio_t pin, gpio_mode_t mode) { GPIO_TypeDef *port = _port(pin); int pin_num = _pin_num(pin); @@ -133,7 +133,7 @@ void gpio_init_analog(gpio_t pin) _port(pin)->CR[pin_num >= 8] &= ~(0xfl << (4 * (pin_num - ((pin_num >= 8) * 8)))); } -int gpio_read(gpio_t pin) +int gpio_cpu_read(gpio_t pin) { GPIO_TypeDef *port = _port(pin); int pin_num = _pin_num(pin); @@ -148,27 +148,27 @@ int gpio_read(gpio_t pin) } } -void gpio_set(gpio_t pin) +void gpio_cpu_set(gpio_t pin) { _port(pin)->BSRR = (1 << _pin_num(pin)); } -void gpio_clear(gpio_t pin) +void gpio_cpu_clear(gpio_t pin) { _port(pin)->BRR = (1 << _pin_num(pin)); } -void gpio_toggle(gpio_t pin) +void gpio_cpu_toggle(gpio_t pin) { - if (gpio_read(pin)) { - gpio_clear(pin); + if (gpio_cpu_read(pin)) { + gpio_cpu_clear(pin); } else { - gpio_set(pin); + gpio_cpu_set(pin); } } -void gpio_write(gpio_t pin, int value) +void gpio_cpu_write(gpio_t pin, int value) { if (value) { _port(pin)->BSRR = (1 << _pin_num(pin)); @@ -179,15 +179,15 @@ void gpio_write(gpio_t pin, int value) } #ifdef MODULE_PERIPH_GPIO_IRQ -int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, - gpio_cb_t cb, void *arg) +int gpio_cpu_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, + gpio_cb_t cb, void *arg) { int pin_num = _pin_num(pin); /* disable interrupts on the channel we want to edit (just in case) */ EXTI->IMR &= ~(1 << pin_num); /* configure pin as input */ - gpio_init(pin, mode); + gpio_cpu_init(pin, mode); /* set callback */ exti_ctx[pin_num].cb = cb; exti_ctx[pin_num].arg = arg; @@ -218,12 +218,12 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, return 0; } -void gpio_irq_enable(gpio_t pin) +void gpio_cpu_irq_enable(gpio_t pin) { EXTI->IMR |= (1 << _pin_num(pin)); } -void gpio_irq_disable(gpio_t pin) +void gpio_cpu_irq_disable(gpio_t pin) { EXTI->IMR &= ~(1 << _pin_num(pin)); } diff --git a/drivers/Makefile.dep b/drivers/Makefile.dep index 1c7868f3f9fc..67a27e7c2b9d 100644 --- a/drivers/Makefile.dep +++ b/drivers/Makefile.dep @@ -174,6 +174,10 @@ ifneq (,$(filter ethos,$(USEMODULE))) USEMODULE += tsrb endif +ifneq (,$(filter extend_gpio,$(USEMODULE))) + USEMODULE += extend +endif + ifneq (,$(filter feetech,$(USEMODULE))) USEMODULE += uart_half_duplex endif diff --git a/drivers/Makefile.include b/drivers/Makefile.include index 7816c9ca8c89..cb1222487c81 100644 --- a/drivers/Makefile.include +++ b/drivers/Makefile.include @@ -90,6 +90,10 @@ ifneq (,$(filter encx24j600,$(USEMODULE))) USEMODULE_INCLUDES += $(RIOTBASE)/drivers/encx24j600/include endif +ifneq (,$(filter extend_%,$(USEMODULE))) + USEMODULE_INCLUDES += $(RIOTBASE)/drivers/extend/include +endif + ifneq (,$(filter feetech,$(USEMODULE))) USEMODULE_INCLUDES += $(RIOTBASE)/drivers/feetech/include endif diff --git a/drivers/extend/Makefile b/drivers/extend/Makefile new file mode 100644 index 000000000000..48422e909a47 --- /dev/null +++ b/drivers/extend/Makefile @@ -0,0 +1 @@ +include $(RIOTBASE)/Makefile.base diff --git a/drivers/extend/gpio_ext_notsup.c b/drivers/extend/gpio_ext_notsup.c new file mode 100644 index 000000000000..bf1987b3f06f --- /dev/null +++ b/drivers/extend/gpio_ext_notsup.c @@ -0,0 +1,130 @@ +/* + * Copyright (C) 2018 Acutam Automation, LLC + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup drivers_extend_gpio + * + * @{ + * + * @file + * @brief GPIO extension not-supported functions + * + * @author Matthew Blue + * + * @} + */ + +#if MODULE_EXTEND_GPIO + +#include "periph/gpio.h" +#include "extend/gpio.h" + +#define ENABLE_DEBUG (0) +#include "debug.h" + +int gpio_ext_init_notsup(void *dev, gpio_t pin, gpio_mode_t mode) +{ + (void)dev; + (void)pin; + (void)mode; + + DEBUG("[gpio_ext_init_notsup] call for dev %p\n", dev); + + return -1; +} + +int gpio_ext_init_int_notsup(void *dev, gpio_t pin, gpio_mode_t mode, + gpio_flank_t flank, gpio_cb_t cb, void *arg) +{ + (void)dev; + (void)pin; + (void)mode; + (void)flank; + (void)cb; + (void)arg; + + DEBUG("[gpio_ext_init_int_notsup] call for dev %p\n", dev); + + return -1; +} + +void gpio_ext_irq_enable_notsup(void *dev, gpio_t pin) +{ + (void)dev; + (void)pin; + + DEBUG("[gpio_ext_irq_enable_notsup] call for dev %p\n", dev); +} + +void gpio_ext_irq_disable_notsup(void *dev, gpio_t pin) +{ + (void)dev; + (void)pin; + + DEBUG("[gpio_ext_irq_disable_notsup] call for dev %p\n", dev); +} + +int gpio_ext_read_notsup(void *dev, gpio_t pin) +{ + (void)dev; + (void)pin; + + DEBUG("[gpio_ext_read_notsup] call for dev %p\n", dev); + + return 0; +} + +void gpio_ext_set_notsup(void *dev, gpio_t pin) +{ + (void)dev; + (void)pin; + + DEBUG("[gpio_ext_set_notsup] call for dev %p\n", dev); +} + +void gpio_ext_clear_notsup(void *dev, gpio_t pin) +{ + (void)dev; + (void)pin; + + DEBUG("[gpio_ext_clear_notsup] call for dev %p\n", dev); +} + +void gpio_ext_toggle_notsup(void *dev, gpio_t pin) +{ + (void)dev; + (void)pin; + + DEBUG("[gpio_toggle_notsup] call for dev %p\n", dev); +} + +void gpio_ext_write_notsup(void *dev, gpio_t pin, int value) +{ + (void)dev; + (void)pin; + (void)value; + + DEBUG("[gpio_ext_write_notsup] call for dev %p\n", dev); +} + +/* not-supported driver */ +const gpio_ext_driver_t gpio_ext_notsup_driver = { + .init = gpio_ext_init_notsup, +#ifdef MODULE_PERIPH_GPIO_IRQ + .init_int = gpio_ext_init_int_notsup, + .irq_enable = gpio_ext_irq_enable_notsup, + .irq_disable = gpio_ext_irq_disable_notsup, +#endif /* MODULE_PERIPH_GPIO_IRQ */ + .read = gpio_ext_read_notsup, + .set = gpio_ext_set_notsup, + .clear = gpio_ext_clear_notsup, + .toggle = gpio_ext_toggle_notsup, + .write = gpio_ext_write_notsup, +}; + +#endif /* MODULE_EXTEND_GPIO */ diff --git a/drivers/extend/include/gpio_ext_conf.h b/drivers/extend/include/gpio_ext_conf.h new file mode 100644 index 000000000000..9fdda4ab08a3 --- /dev/null +++ b/drivers/extend/include/gpio_ext_conf.h @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2018 Acutam Automation, LLC + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup drivers_extend_gpio + * + * @{ + * + * @file + * @brief GPIO extension device default / example list + * + * If the `extend_gpio` module is enabled, a list of GPIO extension devices + * of type @ref gpio_ext_dev_t has to be provided as a configuration. + * + * This file defines a default list containing only the device with the + * default not-supported GPIO extension functions `gpio_ext_*_notsup`. + * + * The board has to override this file with the real GPIO extension device + * list in file `boards/.../include/gpio_ext_conf.h`. + * + * @author Matthew Blue + * + * @} + */ + +#ifndef GPIO_EXT_CONF_H +#define GPIO_EXT_CONF_H + +#include + +#include "extend/gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Reference the driver struct + */ +extern const gpio_ext_driver_t gpio_ext_notsup_driver; + +/** + * @brief GPIO expansion default list if not defined + */ +static const gpio_ext_dev_t gpio_ext[] = +{ + { + .driver = &gpio_ext_notsup_driver, + .dev = NULL, + }, +}; + +#ifdef __cplusplus +} +#endif + +#endif /* GPIO_EXT_CONF_H */ +/** @} */ diff --git a/drivers/extend/include/gpio_ext_notsup.h b/drivers/extend/include/gpio_ext_notsup.h new file mode 100644 index 000000000000..b45719949f0a --- /dev/null +++ b/drivers/extend/include/gpio_ext_notsup.h @@ -0,0 +1,99 @@ +/* + * Copyright (C) 2018 Acutam Automation, LLC + * 2019 Gunar Schorcht + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup drivers_extend_gpio + * @brief GPIO extension not-supported functions + * + * The functions defined here can be used as default functions for GPIO + * extension devices that do not support all required functions of the GPIO + * extension interface. In addition, these functions can be used for testing. + * They just print a debug message, if `ENABLE_DEBUG` is set, and return with + * an error if a return value is defined. + * + * @{ + * + * @file + * @author Matthew Blue + * @author Gunar Schorcht + */ + +#ifndef GPIO_EXT_NOTSUP_H +#define GPIO_EXT_NOTSUP_H + +#include "extend/gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Not-supported function for @ref gpio_init + */ +int gpio_ext_init_notsup(void *dev, gpio_t pin, gpio_mode_t mode); + +#if MODULE_PERIPH_GPIO_IRQ || DOXYGEN + +/** + * @brief Not-supported function for @ref gpio_init_int + */ +int gpio_ext_init_int_notsup(void *dev, gpio_t pin, gpio_mode_t mode, + gpio_flank_t flank, gpio_cb_t cb, void *arg); + +/** + * @brief Not-supported function for @ref gpio_irq_enable + */ +void gpio_ext_irq_enable_notsup(void *dev, gpio_t pin); + +/** + * @brief Not-supported function for @ref gpio_irq_disable + */ +void gpio_ext_irq_disable_notsup(void *dev, gpio_t pin); + +#endif /* MODULE_PERIPH_GPIO_IRQ || DOXYGEN */ + +/** + * @brief Not-supported function for @ref gpio_read + */ +int gpio_ext_read_notsup(void *dev, gpio_t pin); + +/** + * @brief Not-supported function for @ref gpio_set + */ +void gpio_ext_set_notsup(void *dev, gpio_t pin); + +/** + * @brief Not-supported function for @ref gpio_clear + */ +void gpio_ext_clear_notsup(void *dev, gpio_t pin); + +/** + * @brief Not-supported function for @ref gpio_toggle + */ +void gpio_ext_toggle_notsup(void *dev, gpio_t pin); + +/** + * @brief Not-supported function for @ref gpio_write + */ +void gpio_ext_write_notsup(void *dev, gpio_t pin, int value); + +/** + * @brief Driver with not-supported functions + * + * Defines a driver with all not-supported GPIO extension functinos that + * can be used for testing. + */ +extern const gpio_ext_driver_t gpio_ext_notsup_driver; + +#ifdef __cplusplus +} +#endif + +#endif /* GPIO_EXT_NOTSUP_H */ +/** @} */ diff --git a/drivers/include/extend/doc.txt b/drivers/include/extend/doc.txt new file mode 100644 index 000000000000..768a51b48fb1 --- /dev/null +++ b/drivers/include/extend/doc.txt @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2018 Acutam Automation, LLC + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @defgroup drivers_extend Peripheral Driver Extension Interface + * @ingroup drivers + * @brief Peripheral extensions for intercepting API calls and redirecting + * to non-peripheral drivers + * + * The extension interface makes handling of non-CPU devices invisible to code + * using the periph APIs (periph/*.h). This is accomplished by reserving part of + * the range of values of that API's identifier. When a call to the periph API + * uses an identifier that falls within this range, it is parsed into a device + * ID that is looked up in an extension list and the call is redirected to the + * corresponding device. + * + */ diff --git a/drivers/include/extend/gpio.h b/drivers/include/extend/gpio.h new file mode 100644 index 000000000000..562986bf6625 --- /dev/null +++ b/drivers/include/extend/gpio.h @@ -0,0 +1,491 @@ +/* + * Copyright (C) 2018 Acutam Automation, LLC + * 2019 Gunar Schorcht + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @defgroup drivers_extend_gpio GPIO extension + * @ingroup drivers_extend + * @brief GPIO peripheral extension handling + * + * The GPIO extension interface makes handling of non-CPU GPIO devices invisible + * to code using the GPIO peripheral API (periph/gpio.h). This is accomplished by + * reserving part of the range of values of @ref gpio_t. When a call to the + * GPIO API uses a pin that falls within this range, it is parsed into a device + * number that is looked up in a GPIO extension device list and the call is + * redirected to the corresponding device. + * + * The GPIO extension interface uses @ref gpio_t values of following structure: + * + * ``` + * MSB LSB + * +-----+---+------------------------------------------+---------------------------+ + * | | 1 | device number | pin number | + * +-----+---+------------------------------------------+---------------------------+ + * ^ + * | |<-- (GPIO_EXT_BIT - GPIO_EXT_PIN_BITS) -->|<-- (GPIO_EXT_PIN_BITS) -->| + * | + * GPIO_EXT_BIT + * ``` + * + * The @ref GPIO_EXT_PIN is set to one to identify the @ref gpio_t value as GPIO + * extension pin. @ref GPIO_EXT_PIN_BITS defines the number of bits that are + * used to address the pin of a GPIO extension device in a @ref gpio_t value. + * It also defines the number of bits by which the GPIO extension device + * number is shifted to the left in a @ref gpio_t value. Thus, the resulting + * number of bits that can be used to address a GPIO extension device is + * `(GPIO_EXT_BIT - GPIO_EXT_PIN_BITS)`. + * + * The default value of @ref GPIO_EXT_PIN is `sizeof(gpio_t)*8 -1`. That is, + * the MSB is used. The default value of @ref GPIO_EXT_PIN_BITS is 5 to be + * able to use @ref gpio_t values with a size of 8 bit. Thus, the number of + * pins that can be addressed for one GPIO extension device is 32. If a board + * uses GPIO extension devices with more than 32 pins, its board definition has + * to override at least @ref GPIO_EXT_PIN_BITS and @ref GPIO_EXT_PIN_MASK. + * + * The following requirements have to be met in order to use the GPIO + * extension interface + * + * - The board has to provide a list of GPIO extension devices + * of type @ref gpio_ext_dev_t as a configuration in file + * `boards/.../include/gpio_ext_conf.h`. Please refer gpio_ext_conf.h + * for more information and @ref gpio_ext as an example. + * + * - GPIO extension device drivers for GPIO extender hardware modules have to + * implement a set of functions to be compatible with the GPIO extension + * interface. Please refer @ref gpio_ext_driver for more information. + * + * @{ + * + * @file + * @brief GPIO extension interface definitions + * + * @author Matthew Blue + * @author Gunar Schorcht + */ + +#ifndef EXTEND_GPIO_H +#define EXTEND_GPIO_H + +#include +#include + +#include "assert.h" +#include "periph_conf.h" +#include "periph/gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef GPIO_EXT_BIT +/** + * @brief The bit that identifies a @ref gpio_t value as GPIO extension pin + * + * @ref GPIO_EXT_BIT also defines the lowest @ref gpio_t value for GPIO + * extension pins, see @ref GPIO_EXT_BASE. + * + * By default, the MSB of @ref gpio_t used. + */ +#define GPIO_EXT_BIT ((8 * sizeof(gpio_t)) - 1) +#endif + +#ifndef GPIO_EXT_PIN_BITS +/** + * @brief Number of bits in @ref gpio_t values used to address the pin of + * a GPIO extension device + * + * Defines the number of bits that are used to address the pin of a GPIO + * extension device in @ref gpio_t values. It also defines the number of bits + * by which the GPIO extension device number is shifted to the left in + * @ref gpio_t values. Thus, the resulting number of bits that can be used + * to address a GPIO extension device is `(GPIO_EXT_BIT - GPIO_EXT_PIN_BITS)` + * + * @note @ref GPIO_EXT_PIN_BITS has to be equal to the length of the + * right-aligned 1-bit sequence in @ref GPIO_EXT_PIN_MASK. + */ +#define GPIO_EXT_PIN_BITS (5) +#endif + +#ifndef GPIO_EXT_PIN_MASK +/** + * @brief Mask for GPIO extension pin number in @ref gpio_t values + * + * @note The length of the right-aligned 1-bit sequence has to be equal + * to @ref GPIO_EXT_PIN_BITS. + */ +#define GPIO_EXT_PIN_MASK (0x1f) +#endif + +/** + * @brief Lowest @ref gpio_t value of GPIO extension pins + * + * GPIO pins greater than or equal to GPIO_EXT_BASE are GPIO extension pins. + */ +#define GPIO_EXT_BASE ((gpio_t)(1 << GPIO_EXT_BIT)) + +/** + * @brief Test whether a @ref gpio_t value refers a GPIO extension pin + * @param pin pin value of type @ref gpio_t + */ +#define GPIO_EXT_IS(pin) (pin & GPIO_EXT_BASE) + +/** + * @brief Convert the (dev, num) tuple of a GPIO extension pin to + * corresponding @ref gpio_t value + * @param dev GPIO extension device number + * @param num Pin of the GPIO extension device + */ +#define GPIO_EXT_PIN(dev, num) \ + ((gpio_t)(GPIO_EXT_BASE | \ + ((dev << GPIO_EXT_DEV_SHIFT) & GPIO_EXT_DEV_MASK) | \ + (num & GPIO_EXT_PIN_MASK))) + +/** + * @brief Shift of GPIO extension device number in @ref gpio_t values + * + * Defines the number of bits by which the GPIO extension device number + * is shifted to the left in the @ref gpio_t value. It is equal to the + * number of bits used to address a pin of a GPIO extension device, see + * @ref GPIO_EXT_PIN_BITS. + */ +#define GPIO_EXT_DEV_SHIFT (GPIO_EXT_PIN_BITS) + +/** + * @brief Mask for GPIO extension device number in @ref gpio_t values + */ +#define GPIO_EXT_DEV_MASK (~GPIO_EXT_BASE & ~GPIO_EXT_PIN_MASK) + +/** + * @brief Extract the GPIO extension device number from given @ref gpio_t value + * @param pin value of type @ref gpio_t + */ +#define GPIO_EXT_PIN_DEV(pin) ((gpio_t)((pin & GPIO_EXT_DEV_MASK) >> GPIO_EXT_DEV_SHIFT)) + +/** + * @brief Extract the GPIO extension pin number from given @ref gpio_t value + * @param pin value of type @ref gpio_t + */ +#define GPIO_EXT_PIN_NUM(pin) ((gpio_t)((pin & GPIO_EXT_PIN_MASK))) + +/** + * @brief Get GPIO extension device of type @ref gpio_ext_dev_t for given + * @ref gpio_t value + * @param pin value of type @ref gpio_t + */ +#define GPIO_EXT_DEV(pin) (gpio_ext[GPIO_EXT_PIN_DEV(pin)]) + +/** + * @brief Number of configured GPIO extension devices + */ +#define GPIO_EXT_DEV_NUMOF (ARRAY_SIZE(gpio_ext)) + +/** + * @name GPIO extension device driver functions + * + * GPIO extension device drivers have to implement the following functions + * to be compatible with the GPIO extension interface. + * + * @{ + */ + +/** + * @brief Callback typedef for @ref gpio_init + * @param dev Pointer to extension device descriptor + * @see @ref gpio_init + */ +typedef int (*gpio_ext_init_t)(void *dev, gpio_t pin, gpio_mode_t mode); + +#if MODULE_PERIPH_GPIO_IRQ || DOXYGEN + +/** + * @brief Callback typedef for @ref gpio_init_int + * @param dev Pointer to extension device descriptor + * @see @ref gpio_init_int + */ +typedef int (*gpio_ext_init_int_t)(void *dev, gpio_t pin, gpio_mode_t mode, + gpio_flank_t flank, gpio_cb_t cb, void *arg); + +/** + * @brief Callback typedef for @ref gpio_irq_enable + * @param dev Pointer to extension device descriptor + * @see @ref gpio_irq_enable + */ +typedef void (*gpio_ext_irq_enable_t)(void *dev, gpio_t pin); + +/** + * @brief Callback typedef for @ref gpio_irq_disable + * @param dev Pointer to extension device descriptor + * @see @ref gpio_irq_disable + */ +typedef void (*gpio_ext_irq_disable_t)(void *dev, gpio_t pin); + +#endif /* MODULE_PERIPH_GPIO_IRQ || DOXYGEN */ + +/** + * @brief Callback typedef for @ref gpio_read + * @param dev Pointer to extension device descriptor + * @see @ref gpio_read + */ +typedef int (*gpio_ext_read_t)(void *dev, gpio_t pin); + +/** + * @brief Callback typedef for @ref gpio_set + * @param dev Pointer to extension device descriptor + * @see @ref gpio_set + */ +typedef void (*gpio_ext_set_t)(void *dev, gpio_t pin); + +/** + * @brief Callback typedef for @ref gpio_clear + * @param dev Pointer to extension device descriptor + * @see @ref gpio_clear + */ +typedef void (*gpio_ext_clear_t)(void *dev, gpio_t pin); + +/** + * @brief Callback typedef for @ref gpio_toggle + * @param dev Pointer to extension device descriptor + * @see @ref gpio_toggle + */ +typedef void (*gpio_ext_toggle_t)(void *dev, gpio_t pin); + +/** + * @brief Callback typedef for @ref gpio_write + * @param dev Pointer to extension device descriptor + * @see @ref gpio_write + */ +typedef void (*gpio_ext_write_t)(void *dev, gpio_t pin, int value); + +/** @} */ + +/** + * @brief GPIO extension driver type + */ +typedef struct gpio_ext_driver { + gpio_ext_init_t init; /**< callback for @ref gpio_init */ +#if MODULE_PERIPH_GPIO_IRQ || DOXYGEN + gpio_ext_init_int_t init_int; /**< callback for @ref gpio_init_int */ + gpio_ext_irq_enable_t irq_enable; /**< callback for @ref gpio_irq_enable */ + gpio_ext_irq_disable_t irq_disable; /**< callback for @ref gpio_irq_disable */ +#endif /* MODULE_PERIPH_GPIO_IRQ || DOXYGEN */ + gpio_ext_read_t read; /**< callback for @ref gpio_read */ + gpio_ext_set_t set; /**< callback for @ref gpio_set */ + gpio_ext_clear_t clear; /**< callback for @ref gpio_clear */ + gpio_ext_toggle_t toggle; /**< callback for @ref gpio_toggle */ + gpio_ext_write_t write; /**< callback for @ref gpio_write */ +} gpio_ext_driver_t; + +/** + * @brief GPIO extension device type + */ +typedef struct gpio_ext_dev { + const gpio_ext_driver_t *driver; /**< pointer to extension device driver */ + void *dev; /**< pointer to extension device descriptor */ +} gpio_ext_dev_t; + +#include "gpio_ext_conf.h" + +/** + * @name GPIO API functions realized by the GPIO extension interface. + * @{ + */ + +/** + * @brief Implementation by the GPIO extension interface, see @ref gpio_init + */ +static inline int gpio_init(gpio_t pin, gpio_mode_t mode) +{ + /* + * Check that the GPIO_EXT_BIT is inside the gpio_t size. + */ + _Static_assert(GPIO_EXT_BIT < (sizeof(gpio_t) * 8), + "GPIO_EXT_BIT has to be less than sizeof(gpio_t)*8"); + /* + * Check that the gpio_t value has at least one bit left for the device + * number to address GPIO extension devices. + */ + _Static_assert(GPIO_EXT_PIN_BITS < GPIO_EXT_BIT, + "GPIO_EXT_PIN_BITS has to be less than GPIO_EXT_BIT"); + /* + * Check that the number of bits used for the device number is large enough + * to address all extension devices in the device list. + */ + _Static_assert((1 << (GPIO_EXT_BIT - GPIO_EXT_PIN_BITS)) >= GPIO_EXT_DEV_NUMOF, + "Number of bits for GPIO extension device number is too small"); + + if (GPIO_EXT_IS(pin)) { + assert(GPIO_EXT_PIN_DEV(pin) < ARRAY_SIZE(gpio_ext)); + return GPIO_EXT_DEV(pin).driver->init(GPIO_EXT_DEV(pin).dev, + GPIO_EXT_PIN_NUM(pin), mode); + } +#if MODULE_PERIPH_GPIO + return gpio_cpu_init(pin, mode); +#endif + return -1; +} + +#if MODULE_PERIPH_GPIO_IRQ || DOXYGEN + +/** + * @brief Implementation by the GPIO extension interface, see @ref gpio_init_int + */ +static inline int gpio_init_int(gpio_t pin, gpio_mode_t mode, + gpio_flank_t flank, gpio_cb_t cb, void *arg) +{ + /* + * Check that the GPIO_EXT_BIT is inside the gpio_t size. + */ + _Static_assert(GPIO_EXT_BIT < (sizeof(gpio_t) * 8), + "GPIO_EXT_BIT has to be less than sizeof(gpio_t)*8"); + /* + * Check that the gpio_t value has at least one bit left for the device + * number to address GPIO extension devices. + */ + _Static_assert(GPIO_EXT_PIN_BITS < GPIO_EXT_BIT, + "GPIO_EXT_PIN_BITS has to be less than GPIO_EXT_BIT"); + /* + * Check that the number of bits used for the device number is large enough + * to address all extension devices in the device list. + */ + _Static_assert((1 << (GPIO_EXT_BIT - GPIO_EXT_PIN_BITS)) >= GPIO_EXT_DEV_NUMOF, + "Number of bits for GPIO extension device number is too small"); + + if (GPIO_EXT_IS(pin)) { + assert(GPIO_EXT_PIN_DEV(pin) < ARRAY_SIZE(gpio_ext)); + return GPIO_EXT_DEV(pin).driver->init_int(GPIO_EXT_DEV(pin).dev, + GPIO_EXT_PIN_NUM(pin), + mode, flank, cb, arg); + } +#ifdef MODULE_PERIPH_GPIO + return gpio_cpu_init_int(pin, mode, flank, cb, arg); +#endif + return -1; +} + +/** + * @brief Implementation by the GPIO extension interface, see @ref gpio_irq_enable + */ +static inline void gpio_irq_enable(gpio_t pin) +{ + if (GPIO_EXT_IS(pin)) { + assert(GPIO_EXT_PIN_DEV(pin) < ARRAY_SIZE(gpio_ext)); + GPIO_EXT_DEV(pin).driver->irq_enable(GPIO_EXT_DEV(pin).dev, + GPIO_EXT_PIN_NUM(pin)); + return; + } +#ifdef MODULE_PERIPH_GPIO + gpio_cpu_irq_enable(pin); +#endif +} + +/** + * @brief Implementation by the GPIO extension interface, see @ref gpio_irq_disable + */ +static inline void gpio_irq_disable(gpio_t pin) +{ + if (GPIO_EXT_IS(pin)) { + assert(GPIO_EXT_PIN_DEV(pin) < ARRAY_SIZE(gpio_ext)); + GPIO_EXT_DEV(pin).driver->irq_disable(GPIO_EXT_DEV(pin).dev, + GPIO_EXT_PIN_NUM(pin)); + return; + } +#ifdef MODULE_PERIPH_GPIO + gpio_cpu_irq_disable(pin); +#endif +} + +#endif /* MODULE_PERIPH_GPIO_IRQ || DOXYGEN */ + +/** + * @brief Implementation by the GPIO extension interface, see @ref gpio_read + */ +static inline int gpio_read(gpio_t pin) +{ + if (GPIO_EXT_IS(pin)) { + assert(GPIO_EXT_PIN_DEV(pin) < ARRAY_SIZE(gpio_ext)); + return GPIO_EXT_DEV(pin).driver->read(GPIO_EXT_DEV(pin).dev, + GPIO_EXT_PIN_NUM(pin)); + } +#ifdef MODULE_PERIPH_GPIO + return gpio_cpu_read(pin); +#endif + return 0; +} + +/** + * @brief Implementation by the GPIO extension interface, see @ref gpio_set + */ +static inline void gpio_set(gpio_t pin) +{ + if (GPIO_EXT_IS(pin)) { + assert(GPIO_EXT_PIN_DEV(pin) < ARRAY_SIZE(gpio_ext)); + GPIO_EXT_DEV(pin).driver->set(GPIO_EXT_DEV(pin).dev, + GPIO_EXT_PIN_NUM(pin)); + return; + } +#ifdef MODULE_PERIPH_GPIO + gpio_cpu_set(pin); +#endif +} + +/** + * @brief Implementation by the GPIO extension interface, see @ref gpio_clear + */ +static inline void gpio_clear(gpio_t pin) +{ + if (GPIO_EXT_IS(pin)) { + assert(GPIO_EXT_PIN_DEV(pin) < ARRAY_SIZE(gpio_ext)); + GPIO_EXT_DEV(pin).driver->clear(GPIO_EXT_DEV(pin).dev, + GPIO_EXT_PIN_NUM(pin)); + return; + } +#ifdef MODULE_PERIPH_GPIO + gpio_cpu_clear(pin); +#endif +} + +/** + * @brief Implementation by the GPIO extension interface, see @ref gpio_toggle + */ +static inline void gpio_toggle(gpio_t pin) +{ + if (GPIO_EXT_IS(pin)) { + assert(GPIO_EXT_PIN_DEV(pin) < ARRAY_SIZE(gpio_ext)); + GPIO_EXT_DEV(pin).driver->toggle(GPIO_EXT_DEV(pin).dev, + GPIO_EXT_PIN_NUM(pin)); + return; + } +#ifdef MODULE_PERIPH_GPIO + gpio_cpu_toggle(pin); +#endif +} + +/** + * @brief Implementation by the GPIO extension interface, see @ref gpio_write + */ +static inline void gpio_write(gpio_t pin, int value) +{ + if (GPIO_EXT_IS(pin)) { + assert(GPIO_EXT_PIN_DEV(pin) < ARRAY_SIZE(gpio_ext)); + GPIO_EXT_DEV(pin).driver->write(GPIO_EXT_DEV(pin).dev, + GPIO_EXT_PIN_NUM(pin), value); + return; + } +#ifdef MODULE_PERIPH_GPIO + gpio_cpu_write(pin, value); +#endif +} + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* EXTEND_GPIO_H */ +/** @} */ diff --git a/drivers/include/periph/gpio.h b/drivers/include/periph/gpio.h index 03c10359fac5..d030713f249a 100644 --- a/drivers/include/periph/gpio.h +++ b/drivers/include/periph/gpio.h @@ -133,6 +133,29 @@ typedef struct { } gpio_isr_ctx_t; #endif +#ifndef DOXYGEN +/** + * @name Low-level versions of the GPIO functions + * + * These are for CPU implementation in `cpu/.../periph/gpio.c` and should not + * be called directly. + * @{ + */ +int gpio_cpu_init(gpio_t pin, gpio_mode_t mode); +int gpio_cpu_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, + gpio_cb_t cb, void *arg); +void gpio_cpu_irq_enable(gpio_t pin); +void gpio_cpu_irq_disable(gpio_t pin); +int gpio_cpu_read(gpio_t pin); +void gpio_cpu_set(gpio_t pin); +void gpio_cpu_clear(gpio_t pin); +void gpio_cpu_toggle(gpio_t pin); +void gpio_cpu_write(gpio_t pin, int value); +/** @} */ +#endif /* DOXYGEN */ + +#ifndef MODULE_EXTEND_GPIO + /** * @brief Initialize the given pin as general purpose input or output * @@ -140,13 +163,18 @@ typedef struct { * The output pin's state **should** be untouched during the initialization. * This behavior can however **not be guaranteed** by every platform. * + * The CPU has to implement the corresponding `gpio_cpu_init` function. + * * @param[in] pin pin to initialize * @param[in] mode mode of the pin, see @c gpio_mode_t * * @return 0 on success * @return -1 on error */ -int gpio_init(gpio_t pin, gpio_mode_t mode); +static inline int gpio_init(gpio_t pin, gpio_mode_t mode) +{ + return gpio_cpu_init(pin, mode); +} #if defined(MODULE_PERIPH_GPIO_IRQ) || defined(DOXYGEN) /** @@ -157,6 +185,8 @@ int gpio_init(gpio_t pin, gpio_mode_t mode); * * The interrupt is activated automatically after the initialization. * + * The CPU has to implement the corresponding `gpio_cpu_init_int` function. + * * @note You have to add the module `periph_gpio_irq` to your project to * enable this function * @@ -169,69 +199,118 @@ int gpio_init(gpio_t pin, gpio_mode_t mode); * @return 0 on success * @return -1 on error */ -int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, - gpio_cb_t cb, void *arg); +static inline int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, + gpio_cb_t cb, void *arg) +{ + return gpio_cpu_init_int(pin, mode, flank, cb, arg); +} /** * @brief Enable pin interrupt if configured as interrupt source * + * The CPU has to implement the corresponding `gpio_cpu_irq_enable` function. + * * @note You have to add the module `periph_gpio_irq` to your project to * enable this function * * @param[in] pin the pin to enable the interrupt for */ -void gpio_irq_enable(gpio_t pin); +static inline void gpio_irq_enable(gpio_t pin) +{ + gpio_cpu_irq_enable(pin); +} /** * @brief Disable the pin interrupt if configured as interrupt source * + * The CPU has to implement the corresponding `gpio_cpu_irq_disable` function. + * * @note You have to add the module `periph_gpio_irq` to your project to * enable this function * * @param[in] pin the pin to disable the interrupt for */ -void gpio_irq_disable(gpio_t pin); +static inline void gpio_irq_disable(gpio_t pin) +{ + gpio_cpu_irq_disable(pin); +} #endif /* defined(MODULE_PERIPH_GPIO_IRQ) || defined(DOXYGEN) */ /** * @brief Get the current value of the given pin * + * The CPU has to implement the corresponding `gpio_cpu_read` function. + * * @param[in] pin the pin to read * * @return 0 when pin is LOW * @return >0 for HIGH */ -int gpio_read(gpio_t pin); +static inline int gpio_read(gpio_t pin) +{ + return gpio_cpu_read(pin); +} /** * @brief Set the given pin to HIGH * + * The CPU has to implement the corresponding `gpio_cpu_set` function. + * * @param[in] pin the pin to set */ -void gpio_set(gpio_t pin); +static inline void gpio_set(gpio_t pin) +{ + gpio_cpu_set(pin); +} /** * @brief Set the given pin to LOW * + * The CPU has to implement the corresponding `gpio_cpu_clear` function. + * * @param[in] pin the pin to clear */ -void gpio_clear(gpio_t pin); +static inline void gpio_clear(gpio_t pin) +{ + gpio_cpu_clear(pin); +} /** * @brief Toggle the value of the given pin * + * The CPU has to implement the corresponding `gpio_cpu_toggle` function. + * * @param[in] pin the pin to toggle */ -void gpio_toggle(gpio_t pin); +static inline void gpio_toggle(gpio_t pin) +{ + gpio_cpu_toggle(pin); +} /** * @brief Set the given pin to the given value * + * The CPU has to implement the corresponding `gpio_cpu_write` function. + * * @param[in] pin the pin to set * @param[in] value value to set the pin to, 0 for LOW, HIGH otherwise */ -void gpio_write(gpio_t pin, int value); +static inline void gpio_write(gpio_t pin, int value) +{ + gpio_cpu_write(pin, value); +} + +#else /* !MODULE_EXTEND_GPIO */ + +/* + * If the GPIO extension API is used (module` extend_gpio` is enabled), only + * the extend/gpio.h file hase to be included here. The file has to be included + * after all the GPIO type and function prototypes definitions for the CPU. + */ +#include "extend/gpio.h" + +#endif /* !MODULE_EXTEND_GPIO */ #ifdef __cplusplus } diff --git a/makefiles/pseudomodules.inc.mk b/makefiles/pseudomodules.inc.mk index 7b72be3b7e65..db75791e3afa 100644 --- a/makefiles/pseudomodules.inc.mk +++ b/makefiles/pseudomodules.inc.mk @@ -154,6 +154,9 @@ PSEUDOMODULES += stm32_periph_% PSEUDOMODULES += periph_% NO_PSEUDOMODULES += periph_common +# periph extention interface pseudomodules +PSEUDOMODULES += extend_% + # Submodules and auto-init code provided by Skald PSEUDOMODULES += auto_init_skald PSEUDOMODULES += skald_ibeacon diff --git a/tests/extend_gpio/Makefile b/tests/extend_gpio/Makefile new file mode 100644 index 000000000000..de8e44132b1d --- /dev/null +++ b/tests/extend_gpio/Makefile @@ -0,0 +1,14 @@ +include ../Makefile.tests_common + +# The CPUs of these boards do not provide a gpio.c API. +# CPUs: cc430, mips32r2_generic, native +BOARD_BLACKLIST := chronos mips-malta native + +BOARD_INSUFFICIENT_MEMORY := arduino-duemilanove arduino-uno arduino-nano + +FEATURES_REQUIRED += periph_gpio_irq + +USEMODULE += extend_gpio + +include ./Makefile.include +include $(RIOTBASE)/Makefile.include diff --git a/tests/extend_gpio/Makefile.include b/tests/extend_gpio/Makefile.include new file mode 100644 index 000000000000..83e8b3dcf40d --- /dev/null +++ b/tests/extend_gpio/Makefile.include @@ -0,0 +1,2 @@ +# include test specific includes +export INCLUDES += -I$(CURDIR)/include diff --git a/tests/extend_gpio/include/gpio_ext_conf.h b/tests/extend_gpio/include/gpio_ext_conf.h new file mode 100644 index 000000000000..44c3ee338351 --- /dev/null +++ b/tests/extend_gpio/include/gpio_ext_conf.h @@ -0,0 +1,62 @@ +/* + * Copyright (C) 2018 Acutam Automation, LLC + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup tests + * + * @{ + * + * @file + * @brief GPIO extension test list + * + * @author Matthew Blue + * + * @} + */ + +#ifndef GPIO_EXT_CONF_H +#define GPIO_EXT_CONF_H + +#include + +#include "extend/gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Reference the driver structs + * + * @{ + */ +extern const gpio_ext_driver_t tests_extend_gpio_driver; +extern const gpio_ext_driver_t gpio_ext_notsup_driver; +/** @} */ + +/** + * @brief GPIO extension test list + */ +static const gpio_ext_dev_t gpio_ext[] = +{ + { + .driver = &tests_extend_gpio_driver, + .dev = (void *)0xbeef, + }, + { + .driver = &gpio_ext_notsup_driver, + .dev = NULL, + }, +}; + +#ifdef __cplusplus +} +#endif + +#endif /* GPIO_EXT_CONF_H */ +/** @} */ diff --git a/tests/extend_gpio/main.c b/tests/extend_gpio/main.c new file mode 100644 index 000000000000..bcddba5dd7dd --- /dev/null +++ b/tests/extend_gpio/main.c @@ -0,0 +1,189 @@ +/* + * Copyright (C) 2018 Acutam Automation, LLC + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup tests + * @{ + * + * @file + * @brief GPIO extension test routine + * + * @author Matthew Blue + * @} + */ + +#include + +#include "extend/gpio.h" +#include "periph/gpio.h" + +/* GPIO extension test functions */ +int test_gpio_init(void *dev, gpio_t pin, gpio_mode_t mode); +int test_gpio_init_int(void *dev, gpio_t pin, gpio_mode_t mode, + gpio_flank_t flank, gpio_cb_t cb, void *arg); +void test_gpio_irq_enable(void *dev, gpio_t pin); +void test_gpio_irq_disable(void *dev, gpio_t pin); +int test_gpio_read(void *dev, gpio_t pin); +void test_gpio_set(void *dev, gpio_t pin); +void test_gpio_clear(void *dev, gpio_t pin); +void test_gpio_toggle(void *dev, gpio_t pin); +void test_gpio_write(void *dev, gpio_t pin, int value); + +/* GPIO extension test driver */ +const gpio_ext_driver_t tests_extend_gpio_driver = { + .init = test_gpio_init, +#ifdef MODULE_PERIPH_GPIO_IRQ + .init_int = test_gpio_init_int, + .irq_enable = test_gpio_irq_enable, + .irq_disable = test_gpio_irq_disable, +#endif /* MODULE_PERIPH_GPIO_IRQ */ + .read = test_gpio_read, + .set = test_gpio_set, + .clear = test_gpio_clear, + .toggle = test_gpio_toggle, + .write = test_gpio_write, +}; + +int test_gpio_init(void *dev, gpio_t pin, gpio_mode_t mode) +{ + (void)mode; + + printf("init on dev %p with pin %u\n", dev, (unsigned)pin); + + return 0; +} + +#ifdef MODULE_PERIPH_GPIO_IRQ +int test_gpio_init_int(void *dev, gpio_t pin, gpio_mode_t mode, + gpio_flank_t flank, gpio_cb_t cb, void *arg) +{ + (void)mode; + (void)flank; + (void)cb; + (void)arg; + + printf("init_int on dev %p with pin %u\n", dev, (unsigned)pin); + + return 0; +} + +void test_gpio_irq_enable(void *dev, gpio_t pin) +{ + printf("irq_enable on dev %p with pin %u\n", dev, (unsigned)pin); +} + +void test_gpio_irq_disable(void *dev, gpio_t pin) +{ + printf("irq_disable on dev %p with pin %u\n", dev, (unsigned)pin); +} +#endif /* MODULE_PERIPH_GPIO_IRQ */ + +int test_gpio_read(void *dev, gpio_t pin) +{ + printf("read on dev %p with pin %u\n", dev, (unsigned)pin); + + return 0; +} + +void test_gpio_set(void *dev, gpio_t pin) +{ + printf("set on dev %p with pin %u\n", dev, (unsigned)pin); +} + +void test_gpio_clear(void *dev, gpio_t pin) +{ + printf("clear on dev %p with pin %u\n", dev, (unsigned)pin); +} + +void test_gpio_toggle(void *dev, gpio_t pin) +{ + printf("toggle on dev %p with pin %u\n", dev, (unsigned)pin); +} + +void test_gpio_write(void *dev, gpio_t pin, int value) +{ + (void)value; + + printf("write on dev %p with pin %u\n", dev, (unsigned)pin); +} + +int main(void) +{ + gpio_t num, pin; + + puts("gpio extension test routine"); + + for (num = 0; num < 4; num++) { + pin = (1 << num); + printf("Running gpio.h functions on pin %u\n", (unsigned int)pin); + + if (gpio_init(GPIO_EXT_PIN(0, pin), 0x0)) { + puts("[FAILED]"); + return 1; + } + +#ifdef MODULE_PERIPH_GPIO_IRQ + if (gpio_init_int(GPIO_EXT_PIN(0, pin), 0x0, 0x0, NULL, NULL)) { + puts("[FAILED]"); + return 1; + } + + gpio_irq_enable(GPIO_EXT_PIN(0, pin)); + gpio_irq_disable(GPIO_EXT_PIN(0, pin)); +#endif /* MODULE_PERIPH_GPIO_IRQ */ + gpio_read(GPIO_EXT_PIN(0, pin)); + gpio_set(GPIO_EXT_PIN(0, pin)); + gpio_clear(GPIO_EXT_PIN(0, pin)); + gpio_toggle(GPIO_EXT_PIN(0, pin)); + gpio_write(GPIO_EXT_PIN(0, pin), 0); + } + + puts("Running notsup functions"); + puts("(they should not print output)"); + + for (num = 0; num < 4; num++) { + pin = (1 << num); + printf("Running notsup gpio.h functions on pin %u\n", + (unsigned int)pin); + + if (!gpio_init(GPIO_EXT_PIN(1, pin), 0x0)) { + puts("[FAILED]"); + return 1; + } + +#ifdef MODULE_PERIPH_GPIO_IRQ + if (!gpio_init_int(GPIO_EXT_PIN(1, pin), 0x0, 0x0, NULL, NULL)) { + puts("[FAILED]"); + return 1; + } + + gpio_irq_enable(GPIO_EXT_PIN(1, pin)); + gpio_irq_disable(GPIO_EXT_PIN(1, pin)); +#endif /* MODULE_PERIPH_GPIO_IRQ */ + gpio_read(GPIO_EXT_PIN(1, pin)); + gpio_set(GPIO_EXT_PIN(1, pin)); + gpio_clear(GPIO_EXT_PIN(1, pin)); + gpio_toggle(GPIO_EXT_PIN(1, pin)); + gpio_write(GPIO_EXT_PIN(1, pin), 0); + } +/* + puts("Checking that all pins in range have init error using notsup"); + puts("(lack of init error implies improper redirection)"); + + for (num = 0; num <= GPIO_EXT_PIN_MASK; num++) { + if (gpio_init(GPIO_EXT_PIN(1, num), 0x0) >= 0) { + printf("init succeeded on pin %u\n", num); + puts("[FAILED]"); + return 1; + } + } +*/ + puts("[SUCCESS]"); + + return 0; +} diff --git a/tests/extend_gpio/tests/01-run.py b/tests/extend_gpio/tests/01-run.py new file mode 100755 index 000000000000..aaf6649d5e8b --- /dev/null +++ b/tests/extend_gpio/tests/01-run.py @@ -0,0 +1,38 @@ +#!/usr/bin/env python3 + +# Copyright (C) 2018 Acutam Automation, LLC +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. + +import os +import sys + + +def testfunc(child): + child.expect_exact("gpio extension test routine") + for _ in range(4): + child.expect('Running gpio.h functions on pin \d+') + child.expect('init on dev 0xbeef with pin \d+') + child.expect('init_int on dev 0xbeef with pin \d+') + child.expect('irq_enable on dev 0xbeef with pin \d+') + child.expect('irq_disable on dev 0xbeef with pin \d+') + child.expect('read on dev 0xbeef with pin \d+') + child.expect('set on dev 0xbeef with pin \d+') + child.expect('clear on dev 0xbeef with pin \d+') + child.expect('toggle on dev 0xbeef with pin \d+') + child.expect('write on dev 0xbeef with pin \d+') + child.expect_exact("Running notsup functions") + child.expect_exact("(they should not print output)") + for _ in range(4): + child.expect('Running notsup gpio.h functions on pin \d+') + child.expect_exact("Checking that all pins in range have init error using notsup") + child.expect_exact("(lack of init error implies improper redirection)") + child.expect_exact("[SUCCESS]") + + +if __name__ == "__main__": + sys.path.append(os.path.join(os.environ['RIOTBASE'], 'dist/tools/testrunner')) + from testrunner import run + sys.exit(run(testfunc)) diff --git a/tests/periph_gpio_coll/Makefile b/tests/periph_gpio_coll/Makefile new file mode 100644 index 000000000000..a56f63684008 --- /dev/null +++ b/tests/periph_gpio_coll/Makefile @@ -0,0 +1,11 @@ +include ../Makefile.tests_common + +# The CPUs of these boards do not provide a gpio.c API. +# CPUs: cc430, mips32r2_generic, native +BOARD_BLACKLIST := chronos \ + mips-malta \ + native + +USEMODULE += extend_gpio + +include $(RIOTBASE)/Makefile.include diff --git a/tests/periph_gpio_coll/main.c b/tests/periph_gpio_coll/main.c new file mode 100644 index 000000000000..a5249e2fe6af --- /dev/null +++ b/tests/periph_gpio_coll/main.c @@ -0,0 +1,367 @@ +/* + * Copyright (C) 2018 Acutam Automation, LLC + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup tests + * @{ + * + * @file + * @brief GPIO extension compile time gpio_t collision test + * + * @author Matthew Blue + * @} + */ + +#include "assert.h" +#include "periph/gpio.h" + +#if defined(CPU_ESP32) +#define COLL_PINMASK (0x3f) +#elif defined(CPU_ESP8266) +#define COLL_PINMASK (0x1f) +#elif defined(CPU_MSP430FXYZ) +#define COLL_PINMASK (0x07) +#else +#define COLL_PINMASK (0x0f) +#endif + +#define COLL_TEST(port) \ + (GPIO_PIN(port, COLL_PINMASK) >= GPIO_EXT_BASE) + +#if defined(CPU_ATMEGA1281) +#define COLL_TEST_PORTS \ + COLL_TEST(PORT_A) \ + || COLL_TEST(PORT_B) \ + || COLL_TEST(PORT_C) \ + || COLL_TEST(PORT_D) \ + || COLL_TEST(PORT_E) \ + || COLL_TEST(PORT_F) \ + || COLL_TEST(PORT_G) + +#elif defined(CPU_ATMEGA1284P) +#define COLL_TEST_PORTS \ + COLL_TEST(PORT_A) \ + || COLL_TEST(PORT_B) \ + || COLL_TEST(PORT_C) \ + || COLL_TEST(PORT_D) + +#elif defined(CPU_ATMEGA2560) +#define COLL_TEST_PORTS \ + COLL_TEST(PORT_A) \ + || COLL_TEST(PORT_B) \ + || COLL_TEST(PORT_C) \ + || COLL_TEST(PORT_D) \ + || COLL_TEST(PORT_E) \ + || COLL_TEST(PORT_F) \ + || COLL_TEST(PORT_G) \ + || COLL_TEST(PORT_H) \ + || COLL_TEST(PORT_J) \ + || COLL_TEST(PORT_K) \ + || COLL_TEST(PORT_L) + +#elif defined(CPU_ATMEGA256RFR2) +#define COLL_TEST_PORTS \ + COLL_TEST(PORT_B) \ + || COLL_TEST(PORT_D) \ + || COLL_TEST(PORT_E) \ + || COLL_TEST(PORT_F) \ + || COLL_TEST(PORT_G) + +#elif defined(CPU_ATMEGA328P) +#define COLL_TEST_PORTS \ + COLL_TEST(PORT_B) \ + || COLL_TEST(PORT_C) \ + || COLL_TEST(PORT_D) + +#elif defined(CPU_CC2538) +#define COLL_TEST_PORTS \ + COLL_TEST(PORT_A) \ + || COLL_TEST(PORT_B) \ + || COLL_TEST(PORT_C) \ + || COLL_TEST(PORT_D) + +#elif defined(CPU_CC26X0) +/* CPU does have port definitions */ +#define COLL_TEST_PORTS \ + COLL_TEST(0) + +#elif defined(CPU_EFM32) +/* PORT_A */ +#if (_GPIO_PORT_A_PIN_COUNT > 0) +#define COLL_TEST_PORTA (COLL_TEST(PA)) +#else +#define COLL_TEST_PORTA (0) +#endif +/* PORT_B */ +#if (_GPIO_PORT_B_PIN_COUNT > 0) +#define COLL_TEST_PORTB (COLL_TEST_PORTA || COLL_TEST(PB)) +#else +#define COLL_TEST_PORTB (COLL_TEST_PORTA) +#endif +/* PORT_C */ +#if (_GPIO_PORT_C_PIN_COUNT > 0) +#define COLL_TEST_PORTC (COLL_TEST_PORTB || COLL_TEST(PC)) +#else +#define COLL_TEST_PORTC (COLL_TEST_PORTB) +#endif +/* PORT_D */ +#if (_GPIO_PORT_D_PIN_COUNT > 0) +#define COLL_TEST_PORTD (COLL_TEST_PORTC || COLL_TEST(PD)) +#else +#define COLL_TEST_PORTD (COLL_TEST_PORTC) +#endif +/* PORT_E */ +#if (_GPIO_PORT_E_PIN_COUNT > 0) +#define COLL_TEST_PORTE (COLL_TEST_PORTD || COLL_TEST(PE)) +#else +#define COLL_TEST_PORTE (COLL_TEST_PORTD) +#endif +/* PORT_F */ +#if (_GPIO_PORT_F_PIN_COUNT > 0) +#define COLL_TEST_PORTF (COLL_TEST_PORTE || COLL_TEST(PF)) +#else +#define COLL_TEST_PORTF (COLL_TEST_PORTE) +#endif +/* PORT_G */ +#if (_GPIO_PORT_G_PIN_COUNT > 0) +#define COLL_TEST_PORTG (COLL_TEST_PORTF || COLL_TEST(PG)) +#else +#define COLL_TEST_PORTG (COLL_TEST_PORTF) +#endif +/* PORT_H */ +#if (_GPIO_PORT_H_PIN_COUNT > 0) +#define COLL_TEST_PORTH (COLL_TEST_PORTG || COLL_TEST(PH)) +#else +#define COLL_TEST_PORTH (COLL_TEST_PORTG) +#endif +/* PORT_I */ +#if (_GPIO_PORT_I_PIN_COUNT > 0) +#define COLL_TEST_PORTI (COLL_TEST_PORTH || COLL_TEST(PI)) +#else +#define COLL_TEST_PORTI (COLL_TEST_PORTH) +#endif +/* PORT_J */ +#if (_GPIO_PORT_J_PIN_COUNT > 0) +#define COLL_TEST_PORTJ (COLL_TEST_PORTI || COLL_TEST(PJ)) +#else +#define COLL_TEST_PORTJ (COLL_TEST_PORTI) +#endif +/* PORT_K */ +#if (_GPIO_PORT_K_PIN_COUNT > 0) +#define COLL_TEST_PORTK (COLL_TEST_PORTJ || COLL_TEST(PK)) +#else +#define COLL_TEST_PORTK (COLL_TEST_PORTJ) +#endif +/* Combination of all existent ports */ +#define COLL_TEST_PORTS (COLL_TEST_PORTK) + +#elif defined(CPU_ESP32) +/* CPU does not have port definitions */ +#define COLL_TEST_PORTS \ + COLL_TEST(0) + +#elif defined(CPU_ESP8266) +/* CPU does not have port definitions */ +#define COLL_TEST_PORTS \ + COLL_TEST(0) + +#elif defined(CPU_EZR32WG) +#define COLL_TEST_PORTS \ + COLL_TEST(PA) \ + || COLL_TEST(PB) \ + || COLL_TEST(PC) \ + || COLL_TEST(PD) \ + || COLL_TEST(PE) \ + || COLL_TEST(PF) + +#elif defined(CPU_FE310) +/* CPU does not have port definitions */ +#define COLL_TEST_PORTS \ + COLL_TEST(0) + +#elif defined(CPU_KINETIS) +#define COLL_TEST_PORTS \ + COLL_TEST(PORT_A) \ + || COLL_TEST(PORT_B) \ + || COLL_TEST(PORT_C) \ + || COLL_TEST(PORT_D) \ + || COLL_TEST(PORT_E) \ + || COLL_TEST(PORT_F) \ + || COLL_TEST(PORT_G) + +#elif defined(CPU_LM4F120) +#define COLL_TEST_PORTS \ + COLL_TEST(PORT_A) \ + || COLL_TEST(PORT_B) \ + || COLL_TEST(PORT_C) \ + || COLL_TEST(PORT_D) \ + || COLL_TEST(PORT_E) \ + || COLL_TEST(PORT_F) + +#elif defined(CPU_LPC1768) +/* CPU does not have port definitions */ +#define COLL_TEST_PORTS \ + COLL_TEST(0) + +#elif defined(CPU_LPC2387) +/* CPU does not have port definitions */ +#define COLL_TEST_PORTS \ + COLL_TEST(0) + +#elif defined(CPU_MIPS_PIC32MX) || defined(CPU_MIPS_PIC32MZ) +#define COLL_TEST_PORTS \ + COLL_TEST(PORT_A) \ + || COLL_TEST(PORT_B) \ + || COLL_TEST(PORT_C) \ + || COLL_TEST(PORT_D) \ + || COLL_TEST(PORT_E) \ + || COLL_TEST(PORT_F) \ + || COLL_TEST(PORT_G) + +#elif defined(CPU_MSP430FXYZ) +#define COLL_TEST_PORTS \ + COLL_TEST(P1) \ + || COLL_TEST(P2) \ + || COLL_TEST(P3) \ + || COLL_TEST(P4) \ + || COLL_TEST(P5) \ + || COLL_TEST(P6) + +#elif defined(CPU_NRF51) || defined(CPU_NRF52) +/* CPU does not have port definitions */ +#define COLL_TEST_PORTS \ + COLL_TEST(0) + +#elif defined(CPU_SAM3) +#define COLL_TEST_PORTS \ + COLL_TEST(PA) \ + || COLL_TEST(PB) \ + || COLL_TEST(PC) \ + || COLL_TEST(PD) + +#elif defined(CPU_SAMD21) || defined(CPU_SAML21) +#define COLL_TEST_PORTS \ + COLL_TEST(PA) \ + || COLL_TEST(PB) \ + || COLL_TEST(PC) + +#elif defined(CPU_STM32F0) +#define COLL_TEST_PORTS \ + COLL_TEST(PORT_A) \ + || COLL_TEST(PORT_B) \ + || COLL_TEST(PORT_C) \ + || COLL_TEST(PORT_D) \ + || COLL_TEST(PORT_E) \ + || COLL_TEST(PORT_F) + +#elif defined(CPU_STM32F1) +#define COLL_TEST_PORTS \ + COLL_TEST(PORT_A) \ + || COLL_TEST(PORT_B) \ + || COLL_TEST(PORT_C) \ + || COLL_TEST(PORT_D) \ + || COLL_TEST(PORT_E) \ + || COLL_TEST(PORT_F) \ + || COLL_TEST(PORT_G) + +#elif defined(CPU_STM32F2) +#define COLL_TEST_PORTS \ + COLL_TEST(PORT_A) \ + || COLL_TEST(PORT_B) \ + || COLL_TEST(PORT_C) \ + || COLL_TEST(PORT_D) \ + || COLL_TEST(PORT_E) \ + || COLL_TEST(PORT_F) \ + || COLL_TEST(PORT_G) \ + || COLL_TEST(PORT_H) \ + || COLL_TEST(PORT_I) + +#elif defined(CPU_STM32F3) +#define COLL_TEST_PORTS \ + COLL_TEST(PORT_A) \ + || COLL_TEST(PORT_B) \ + || COLL_TEST(PORT_C) \ + || COLL_TEST(PORT_D) \ + || COLL_TEST(PORT_E) \ + || COLL_TEST(PORT_F) \ + || COLL_TEST(PORT_G) \ + || COLL_TEST(PORT_H) + +#elif defined(CPU_STM32F4) +#define COLL_TEST_PORTS \ + COLL_TEST(PORT_A) \ + || COLL_TEST(PORT_B) \ + || COLL_TEST(PORT_C) \ + || COLL_TEST(PORT_D) \ + || COLL_TEST(PORT_E) \ + || COLL_TEST(PORT_F) \ + || COLL_TEST(PORT_G) \ + || COLL_TEST(PORT_H) \ + || COLL_TEST(PORT_I) + +#elif defined(CPU_STM32F7) +#define COLL_TEST_PORTS \ + COLL_TEST(PORT_A) \ + || COLL_TEST(PORT_B) \ + || COLL_TEST(PORT_C) \ + || COLL_TEST(PORT_D) \ + || COLL_TEST(PORT_E) \ + || COLL_TEST(PORT_F) \ + || COLL_TEST(PORT_G) \ + || COLL_TEST(PORT_H) \ + || COLL_TEST(PORT_I) \ + || COLL_TEST(PORT_J) \ + || COLL_TEST(PORT_K) + +#elif defined(CPU_STM32L0) +#define COLL_TEST_PORTS \ + COLL_TEST(PORT_A) \ + || COLL_TEST(PORT_B) \ + || COLL_TEST(PORT_C) \ + || COLL_TEST(PORT_D) \ + || COLL_TEST(PORT_E) \ + || COLL_TEST(PORT_H) + +#elif defined(CPU_STM32L1) +#define COLL_TEST_PORTS \ + COLL_TEST(PORT_A) \ + || COLL_TEST(PORT_B) \ + || COLL_TEST(PORT_C) \ + || COLL_TEST(PORT_D) \ + || COLL_TEST(PORT_E) \ + || COLL_TEST(PORT_F) \ + || COLL_TEST(PORT_G) \ + || COLL_TEST(PORT_H) + +#elif defined(CPU_STM32L4) +#define COLL_TEST_PORTS \ + COLL_TEST(PORT_A) \ + || COLL_TEST(PORT_B) \ + || COLL_TEST(PORT_C) \ + || COLL_TEST(PORT_D) \ + || COLL_TEST(PORT_E) \ + || COLL_TEST(PORT_F) \ + || COLL_TEST(PORT_G) \ + || COLL_TEST(PORT_H) + +#else + +/* unknown CPU (default to not testing port) */ +#define COLL_TEST_PORTS \ + COLL_TEST(0) + +#endif /* defined(CPU) */ + +#define COLL_RES (!(COLL_TEST_PORTS)) + +static_assert(COLL_RES, "[periph_gpio_coll] Collision in GPIO_EXT_PIN"); + +int main(void) +{ + return 0; +}