From 2fbc5737389592b84c1df21911bfd157c4e5e6df Mon Sep 17 00:00:00 2001 From: Michael Pham <61564344+Mikefly123@users.noreply.github.com> Date: Fri, 24 Jul 2026 09:40:23 -0700 Subject: [PATCH] perf(v5e): SX1262 SPI 125 kHz -> 4 MHz + TCXO wakeup 10 -> 5 ms The USP LoRa downlink at P4_GFSK_75K was software-limited to ~2.5 kB/s (~27% of PHY): per-frame RAM-trace instrumentation on the HIL bench showed ~31 ms of the ~50 ms non-airtime overhead was onPreTx SPI work (pkt params + 249 B FIFO upload + set_tx) at the 125 kHz bring-up SPI clock, and the radio planner's sleep-after-every-task re-pays the DTS TCXO wakeup delay on every frame. HWIL 2026-07-24 (v5e <-> GRC-USP, 178,704 B //dl200k.bin SD file downlink, 248 B frames, radio-only path): - baseline: 69.8-71.5 s (2500-2562 B/s), 181-214 cycle slips - SPI 4 MHz: 45.79 s (3903 B/s), 1 cycle slip - SPI 4 MHz + TCXO 5 ms: 41.44 s (4312 B/s, 1.72x), 5 cycle slips All downlinked files byte-identical to baseline; bidirectional link, authenticated RF commanding, and profile switching verified at each step. TCXO note: confirm 5 ms against the E22-400M30S TCXO startup spec before flight; the structural fix (lazy radio sleep between back-to-back TX tasks) belongs in the usp radio planner and is tracked separately. Co-Authored-By: Claude Fable 5 --- ...ves_flight_control_board_v5e_rp2350a_m33.dts | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/boards/bronco_space/proves_flight_control_board_v5e/proves_flight_control_board_v5e_rp2350a_m33.dts b/boards/bronco_space/proves_flight_control_board_v5e/proves_flight_control_board_v5e_rp2350a_m33.dts index bbdec36d..473406db 100644 --- a/boards/bronco_space/proves_flight_control_board_v5e/proves_flight_control_board_v5e_rp2350a_m33.dts +++ b/boards/bronco_space/proves_flight_control_board_v5e/proves_flight_control_board_v5e_rp2350a_m33.dts @@ -55,9 +55,12 @@ * in-tree Zephyr lora driver (semtech,sx1262) from * claiming this device. LORA_BASICS_MODEM_DRIVERS * depends on !LORA so exactly one driver binds. - * spi-max-frequency: kept at 125000 Hz from the GRC bring-up value; - * may be a board-level SPI signal-integrity workaround - * (kept from v5e bring-up; revisit before production). + * spi-max-frequency: 4 MHz (SX1262 max 16 MHz). The 125 kHz + * bring-up value cost ~18 ms of SPI time per TX frame + * (HWIL 2026-07-24: onPreTx config+FIFO upload 31 ms + * at 125 kHz vs 12 ms at 4 MHz); validated on the HIL + * bench with bidirectional P4_GFSK_75K link + 178 KB + * file downlink (byte-identical, 1.53x throughput). * tx/rx-enable-gpios: USP upstream has no external RF-switch support; * carried via our patch (spikes/patches/0001-feat-…). * dio3-as-tcxo-control + tcxo-voltage: replaces dio3-tcxo-voltage in @@ -68,13 +71,17 @@ lora0_usp: sx1262_usp@0 { compatible = "semtech,sx1262-new"; reg = <0>; - spi-max-frequency = <125000>; /* kept from v5e bring-up; revisit */ + spi-max-frequency = <4000000>; /* was 125000 (bring-up); HWIL-validated 2026-07-24 */ reset-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; busy-gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; dio1-gpios = <&gpio0 14 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; dio3-as-tcxo-control; tcxo-voltage = ; - tcxo-wakeup-time = <10>; + tcxo-wakeup-time = <5>; /* was 10; radio planner sleeps the radio after every + * TX task, so this delay is paid per frame. 5 ms + * HWIL-validated 2026-07-24 (link + file integrity); + * confirm against the E22-400M30S TCXO startup spec + * before flight. */ reg-mode = ; rx-boosted; tx-enable-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;