Enable `Branch` to receive voltage and send current over signals

[PhilipFackler]

Summary

We need a way to communicate voltage and current between a branch and something other than a bus.

Rationale

For co-simulation we want to communicate voltage and current between two instances of GridKit over a "network". Presently, the Branch class reads/writes these directly as owned by a BusBase, so we need to devise an alternate means of access.

Description

The "best" way to do this is somewhat open-ended. Here are my ideas (in no particular order):

• A new type (inherits from BusBase) that would substitute for one of the buses on the branch
  • implementation of Branch does not change
  • new class enables external access through signal nodes
• A new branch type (inherits from Component) that uses signals instead of buses
  • "true" bus would be connected through BusToSignalAdapter
  • duplicates Branch behavior
• Modify existing Branch type to be able to use signals
  • Add some logic to prioritize using signals if they are connected. If not, use the bus pointer as before.

In all of these cases the external communication is happening (from the system's perspective) through signal nodes. This is reflecting my expectation of the design the co-simulation will develop into...in which *.case.json files will remain useful as they are now (declaring signals that can be used externally) and adding (either in the case file or a new co-simulation configuration file) the ability to specify which signals are used for network communication.

Additional information

No response

[pelesh]

Many good ideas here. My choice would be your first option. We could create two bus-like models:

• one having signal out voltage and signal in current (replacing current BusToSignal adapter), and
• another one having signal in voltage and signal out current.

The "bus" receiving voltage would treat that voltage as constant and would collect injection currents from components connected to it.

The "bus" sending the voltage would have that voltage computed by the system it belongs based on external injection current input.

These "buses" will be boundaries of system models, connecting different (sub) systems through signal connections.

CC @alexander-novo @hambrickjc

[pelesh]

CC @abdourahmanbarry @superwhiskers

[lukelowry]

I have a draft PR #511 that is related to this. In that branch, I changed all components that interface with a bus (including Branch) to instead read VR and VI just like any other external variable. This makes formulating the models much easier and gives us more freedom to unit test components ( a lot of the unit tests right now depend a Bus). (and introduces 'external equations' concept form PowerElectronics which is a very compelling design of @alexander-novo )

It is a stepping stone toward making Bus inherit from Component which I do inlukel/unify-container-dev and it lets us collapse/simplify PhasorDynamics. I did this because it makes case partitioning much easier. If we generalize Bus as a Component then we can modify SystemModel to expose bus voltages/nodal equations via ports, and partitioning the cases becomes easier. We could remove the bus signal adapter.