Your translation from the circuit diagram to logic diagram is incorrect?

[Did-Nikole]

As far as we can workout from the circuit diagram you provided on the wiki it doesn't translate to the logic diagram, as some of the or gates for the output are interconnected in the circuit diagram between the and gating and the or gating.
After redoing the circuit into a set of formula's we came up with the following truth table.

Inputs | Outputs
6 8 | 10 14 | 15 18 | A B E F
====+=======+=======+========
0 0 | 0 0 | 0 0 | 0 0 0 0
1 0 | 0 0 | 0 0 | 0 0 0 0
0 1 | 0 0 | 0 0 | 0 0 0 0
1 1 | 0 0 | 0 0 | 0 1 1 1
0 0 | 1 0 | 0 0 | 0 0 0 0
1 0 | 1 0 | 0 0 | 0 0 0 0
0 1 | 1 0 | 0 0 | 0 0 0 0
1 1 | 1 0 | 0 0 | 0 0 1 1
0 0 | 0 1 | 0 0 | 0 0 0 0
1 0 | 0 1 | 0 0 | 0 0 0 0
0 1 | 0 1 | 0 0 | 0 0 0 0
1 1 | 0 1 | 0 0 | 0 1 0 1
0 0 | 1 1 | 0 0 | 0 0 0 0
1 0 | 1 1 | 0 0 | 0 0 0 0
0 1 | 1 1 | 0 0 | 0 0 0 0
1 1 | 1 1 | 0 0 | 0 0 0 0
0 0 | 0 0 | 1 0 | 0 0 0 0
1 0 | 0 0 | 1 0 | 0 0 0 0
0 1 | 0 0 | 1 0 | 1 1 1 1
1 1 | 0 0 | 1 0 | 1 1 1 1
0 0 | 1 0 | 1 0 | 0 0 0 0
1 0 | 1 0 | 1 0 | 0 0 0 0
0 1 | 1 0 | 1 0 | 1 1 0 0
1 1 | 1 0 | 1 0 | 1 1 1 1
0 0 | 0 1 | 1 0 | 0 0 0 0
1 0 | 0 1 | 1 0 | 0 0 0 0
0 1 | 0 1 | 1 0 | 0 0 1 1
1 1 | 0 1 | 1 0 | 0 1 1 1
0 0 | 1 1 | 1 0 | 0 0 0 0
1 0 | 1 1 | 1 0 | 0 0 0 0
0 1 | 1 1 | 1 0 | 0 0 0 0
1 1 | 1 1 | 1 0 | 0 0 0 0
0 0 | 0 0 | 0 1 | 0 0 0 0
1 0 | 0 0 | 0 1 | 1 1 1 1
0 1 | 0 0 | 0 1 | 0 0 0 0
1 1 | 0 0 | 0 1 | 1 1 1 1
0 0 | 1 0 | 0 1 | 0 0 0 0
1 0 | 1 0 | 0 1 | 1 1 1 1
0 1 | 1 0 | 0 1 | 0 0 0 0
1 1 | 1 0 | 0 1 | 1 1 1 1
0 0 | 0 1 | 0 1 | 0 0 0 0
1 0 | 0 1 | 0 1 | 0 0 1 1
0 1 | 0 1 | 0 1 | 0 0 0 0
1 1 | 0 1 | 0 1 | 0 1 1 1
0 0 | 1 1 | 0 1 | 0 0 0 0
1 0 | 1 1 | 0 1 | 0 0 1 1
0 1 | 1 1 | 0 1 | 0 0 0 0
1 1 | 1 1 | 0 1 | 0 0 1 1
0 0 | 0 0 | 1 1 | 1 0 1 0
1 0 | 0 0 | 1 1 | 1 1 1 1
0 1 | 0 0 | 1 1 | 1 1 1 1
1 1 | 0 0 | 1 1 | 1 1 1 1
0 0 | 1 0 | 1 1 | 1 0 1 0
1 0 | 1 0 | 1 1 | 1 1 1 1
0 1 | 1 0 | 1 1 | 1 1 1 0
1 1 | 1 0 | 1 1 | 1 1 1 1
0 0 | 0 1 | 1 1 | 0 0 0 0
1 0 | 0 1 | 1 1 | 0 0 1 1
0 1 | 0 1 | 1 1 | 0 0 1 1
1 1 | 0 1 | 1 1 | 0 1 1 1
0 0 | 1 1 | 1 1 | 0 0 0 0
1 0 | 1 1 | 1 1 | 0 0 1 1
0 1 | 1 1 | 1 1 | 0 0 0 0
1 1 | 1 1 | 1 1 | 0 0 1 1

LogicSim file and image attached

FullAdder.zip

[Nakazoto]

Hmm, it's not only possible, but given how I couldn't get a full match on the schematic, it is actually likely.
I'll check out the new Logisim file and truth table. Do you have a schematic or image file that shows the places where I may have something incorrect? I can then use that to retrace certain parts of the board.

[Did-Nikole]

Sorry we did most of it on pad and paper, and Gimp to view both sides of PCB at same time, will work on translation of PCB to schematic over the next few days if thats okay.