diff --git a/submission.html b/submission.html
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--- a/submission.html
+++ b/submission.html
@@ -245,9 +245,8 @@ <h3 class="mb-0" style="color: #00ADB5;"><img src="./one.gif" width="70px" heigh
             <div class="mb-5 slide-right">
               <h3 class="mb-0" style="color: #00ADB5;"><img src="./two.gif" width="70px" height="70px"> VLSI Circuit and System Design</h3>
               <ul>
-                <li><img src="./arrow-circle-right.png" width="15px" height="15px"> Low power, High-performance, and robust design of logic, memory, Analog, Mixed Signal and RF IC Design</li>
+                <li><img src="./arrow-circle-right.png" width="15px" height="15px"> Analog, Mixed Signal and RF IC Design</li>
                 <li><img src="./arrow-circle-right.png" width="15px" height="15px"> Clock-generation and distribution circuits including all digital PLLs and DLLs</li>
-                <li><img src="./arrow-circle-right.png" width="15px" height="15px"> ADC's and DAC's</li>
                 <li><img src="./arrow-circle-right.png" width="15px" height="15px"> Soft-error and fault-tolerant circuits</li> 
                 <li><img src="./arrow-circle-right.png" width="15px" height="15px"> Circuit design for reliability effects such as gate oxide integrity, electro-migration, ESD, HCI, NBTI, PBTI etc.</li>
                 <li><img src="./arrow-circle-right.png" width="15px" height="15px"> Hardware accelerators for machine learning (ML) and deep learning algorithms</li>
@@ -263,7 +262,6 @@ <h3 class="mb-0" style="color: #00ADB5;"><img src="./three.gif" width="70px" hei
               <ul>
                 <li><img src="./arrow-circle-right.png" width="15px" height="15px"> Logic and behavioral synthesis</li>
                 <li><img src="./arrow-circle-right.png" width="15px" height="15px"> Placement, Routing and Floor planning</li> 
-                <li><img src="./arrow-circle-right.png" width="15px" height="15px"> CAD tools</li>
                 <li><img src="./arrow-circle-right.png" width="15px" height="15px"> Design Automation and Methodologies</li> 
                 <li><img src="./arrow-circle-right.png" width="15px" height="15px"> Hardware attacks-detection</li> 
                 <li><img src="./arrow-circle-right.png" width="15px" height="15px"> Threat modeling & defense</li>
@@ -293,7 +291,7 @@ <h3 class="mb-0" style="color: #00ADB5;"><img src="./four.gif" width="70px" heig
             <div class="mb-5 slide-right">
               <h3 class="mb-0" style="color: #00ADB5;"><img src="./five.gif" width="70px" height="70px"> FPGA-based Design and Embedded Systems</h3>
               <ul>
-                <li><img src="./arrow-circle-right.png" width="15px" height="15px"> FPGA based designs, Hardware/Software co-design and verification</li>
+                <li><img src="./arrow-circle-right.png" width="15px" height="15px"> FPGA based designs</li>
                 <li><img src="./arrow-circle-right.png" width="15px" height="15px"> Audio, Image and video processing</li>
                 <li><img src="./arrow-circle-right.png" width="15px" height="15px"> Reconfigurable systems</li>
                 <li><img src="./arrow-circle-right.png" width="15px" height="15px"> Microcontroller, ARM, IoT and FPGA-based embedded systems design</li>
@@ -301,7 +299,7 @@ <h3 class="mb-0" style="color: #00ADB5;"><img src="./five.gif" width="70px" heig
                 <li><img src="./arrow-circle-right.png" width="15px" height="15px"> CAD for embedded systems</li> 
                 <li><img src="./arrow-circle-right.png" width="15px" height="15px"> Artificial intelligence and ML-based systems, Cyber-Physical Systems</li>
                 <li><img src="./arrow-circle-right.png" width="15px" height="15px"> RISC V based Design </li>
-                <li><img src="./arrow-circle-right.png" width="15px" height="15px"> CAD for FPGA and embedded systems</li>
+                <li><img src="./arrow-circle-right.png" width="15px" height="15px"> ARM and CAD for FPGA and embedded systems</li>
               </ul>
             </div>
           </div>