AHCI hardcodes 512-byte sectors, so a 4Kn (4096-byte native) SATA drive corrupts data. constants/ata.rs:29 SECTOR_SIZE=512, engine/build.rs:49 computes the PRDT byte count as sectors512, and the read handler copies nsectors512. IDENTIFY is issued but the logical sector size (IDENTIFY words 106 / 117-118) is never consulted, so every transfer on a 4Kn drive is 8x short and the LBAs are misinterpreted.
Widening: parse IDENTIFY word 106/117 for the logical sector size and drive all byte math from it (NVMe already does this at setup/sequence.rs:66).
Related AHCI breadth gaps (separate, lower priority): single port and single command slot only (setup/block_port.rs:28 returns the first SATA port; engine/issue.rs:37 always slot 0), no NCQ, no staggered spin-up (CAP.SSS unchecked), no port multiplier, and CAP.S64A is never checked before writing the high address dwords.
AHCI hardcodes 512-byte sectors, so a 4Kn (4096-byte native) SATA drive corrupts data. constants/ata.rs:29 SECTOR_SIZE=512, engine/build.rs:49 computes the PRDT byte count as sectors512, and the read handler copies nsectors512. IDENTIFY is issued but the logical sector size (IDENTIFY words 106 / 117-118) is never consulted, so every transfer on a 4Kn drive is 8x short and the LBAs are misinterpreted.
Widening: parse IDENTIFY word 106/117 for the logical sector size and drive all byte math from it (NVMe already does this at setup/sequence.rs:66).
Related AHCI breadth gaps (separate, lower priority): single port and single command slot only (setup/block_port.rs:28 returns the first SATA port; engine/issue.rs:37 always slot 0), no NCQ, no staggered spin-up (CAP.SSS unchecked), no port multiplier, and CAP.S64A is never checked before writing the high address dwords.