ComputerModeling2021/design.xml at main · Jihwan-Kimm/ComputerModeling2021 · GitHub

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<?xml version="1.0" encoding="UTF-8"?><hyundaiDesignTool>
    <ETHs>
        <ETH IP="192.168.0.100">
            <link rid="ECU0" type="ECU"/>
            <link rid="CAR" type="CAR"/>
        </ETH>
    </ETHs>
    <CAR IP="CAR">
        <link rid="192.168.0.100" type="ETH"/>
    </CAR>
    <SWCs>
        <SWC BCET="30" IP="LK" Virtual="1" WCET="30" consumer="" deadline="60" period="60" phase="0" readCon="0" writeCon="1">
            <impl path="/home/rubis/ComputerModeling2023/sharedObjectFiles/LK/LK.cpp" type="MANUAL"/>
            <link idxCore="0" rid="ECU0" type="ECU"/>
        </SWC>
        <SWC BCET="10" IP="CC" Virtual="1" WCET="10" consumer="" deadline="30" period="30" phase="0" readCon="0" writeCon="1">
            <impl path="/home/rubis/ComputerModeling2023/sharedObjectFiles/CC/CC.cpp" type="MANUAL"/>
            <link idxCore="0" rid="ECU0" type="ECU"/>
        </SWC>
        <SWC BCET="10" IP="SENSING" Virtual="1" WCET="10" consumer="" deadline="100" period="100" phase="0" readCon="0" writeCon="0">
            <impl path="/home/rubis/ComputerModeling2023/sharedObjectFiles/SENSING/SENSING.cpp" type="MANUAL"/>
            <link idxCore="0" rid="ECU0" type="ECU"/>
        </SWC>
    </SWCs>
    <ECUs>
        <ECU IP="ECU0" Virtual="1" numCores="1" schedPolicy="RM" sysClock="100" targetArch="SPC56EL70">
            <link idxCore="0" rid="LK" type="SWC"/>
            <link idxCore="0" rid="CC" type="SWC"/>
            <link idxCore="0" rid="SENSING" type="SWC"/>
            <link rid="192.168.0.100" type="ETH"/>
        </ECU>
    </ECUs>
</hyundaiDesignTool>