From 0553a2ca30ae62efc3bc017f9ebb3e7cc445f9cc Mon Sep 17 00:00:00 2001 From: Hiratsuca <104103173+Hiratsuca@users.noreply.github.com> Date: Mon, 5 Sep 2022 14:09:37 -0300 Subject: [PATCH 01/60] integrante lucca --- INTEGRANTES.json | 6 ++++++ 1 file changed, 6 insertions(+) create mode 100644 INTEGRANTES.json diff --git a/INTEGRANTES.json b/INTEGRANTES.json new file mode 100644 index 00000000..331bfc10 --- /dev/null +++ b/INTEGRANTES.json @@ -0,0 +1,6 @@ + { + "user": "1", + "name": "Lucca Hiratsuca Costa", + "git-username": "LuccaHiratsuca", + "blackboard-username": "luccahc" +} From 3ee5b4f3be7c485681835d6c767d78269013515d Mon Sep 17 00:00:00 2001 From: Alexandre Date: Mon, 5 Sep 2022 14:16:48 -0300 Subject: [PATCH 02/60] aleeeeeee --- INTEGRANTES.json | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/INTEGRANTES.json b/INTEGRANTES.json index 331bfc10..5ccc0a27 100644 --- a/INTEGRANTES.json +++ b/INTEGRANTES.json @@ -1,6 +1,15 @@ - { - "user": "1", - "name": "Lucca Hiratsuca Costa", - "git-username": "LuccaHiratsuca", - "blackboard-username": "luccahc" -} +[ + { + "user": "1", + "name": "Alexandre Magno Maciel dos Santos", + "git-username": "alemagno10", + "blackboard-username": "alexandremms" + }, + + { + "user": "2", + "name": "Lucca Hiratsuca Costa", + "git-username": "LuccaHiratsuca", + "blackboard-username": "luccahc" + } +] \ No newline at end of file From 657e094e047b3f3856efea2ae8dfaf00718e96f8 Mon Sep 17 00:00:00 2001 From: juliapaiva1 Date: Mon, 5 Sep 2022 14:18:45 -0300 Subject: [PATCH 03/60] commit integrantes --- INTEGRANTES.json | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/INTEGRANTES.json b/INTEGRANTES.json index 5ccc0a27..4bea8ada 100644 --- a/INTEGRANTES.json +++ b/INTEGRANTES.json @@ -11,5 +11,12 @@ "name": "Lucca Hiratsuca Costa", "git-username": "LuccaHiratsuca", "blackboard-username": "luccahc" - } + }, + + { + "user": "3", + "name": "Júlia Ferreira de Paiva", + "git-username": "juliapaiva1", + "blackboard-username": "juliafp2" +} ] \ No newline at end of file From 4d5ec375ef5807f2981612fee24b59fa7e9dfaac Mon Sep 17 00:00:00 2001 From: juliapaiva1 Date: Sun, 11 Sep 2022 12:26:49 -0300 Subject: [PATCH 04/60] branch demux config inicial --- .github/workflows/components.yml | 8 ++++++++ hw/components.py | 4 ++++ 2 files changed, 12 insertions(+) diff --git a/.github/workflows/components.yml b/.github/workflows/components.yml index 3f26be75..e784933f 100644 --- a/.github/workflows/components.yml +++ b/.github/workflows/components.yml @@ -31,3 +31,11 @@ jobs: - name: test and16 run: | pytest hw/test_components.py -k and16 + + - name: Test deMux2way + run: | + pytest hw/test_components.py -k deMux2way + + - name: Test deMux4way + run: | + pytest hw/test_components.py -k deMux4way \ No newline at end of file diff --git a/hw/components.py b/hw/components.py index aa9336e9..4bd0eddb 100644 --- a/hw/components.py +++ b/hw/components.py @@ -146,6 +146,10 @@ def deMux2way(a, q0, q1, sel): q1 = 0 """ + + +#recebe entrada a, saida q0, saida q1 e seletor + foo = Signal(intbv(0)) @always_comb From ef83b5d97922e8a21d1a7e5e8348cb4cfc355f25 Mon Sep 17 00:00:00 2001 From: juliapaiva1 Date: Sun, 11 Sep 2022 13:04:02 -0300 Subject: [PATCH 05/60] demux2way funcionando --- hw/components.py | 30 ++++++++++++++++++++++-------- 1 file changed, 22 insertions(+), 8 deletions(-) diff --git a/hw/components.py b/hw/components.py index 4bd0eddb..15ee1bba 100644 --- a/hw/components.py +++ b/hw/components.py @@ -133,7 +133,7 @@ def comb(): @block -def deMux2way(a, q0, q1, sel): +def deMux2way(a, q0, q1, sel): #hardware """ deMux de 2 saídas e uma entrada. @@ -146,15 +146,18 @@ def deMux2way(a, q0, q1, sel): q1 = 0 """ - - -#recebe entrada a, saida q0, saida q1 e seletor - foo = Signal(intbv(0)) @always_comb - def comb(): - q0.next = foo + def comb(): + + if sel == 0: + q0.next = a + q1.next = 0 + + else: + q0.next = 0 + q1.next = a return comb @@ -171,7 +174,18 @@ def deMux4way(a, q0, q1, q2, q3, sel): @always_comb def comb(): - q0.next = foo + + if sel == 0: + q0.next = a + q1.next = 0 + q2.next = a + q3.next = 0 + + else: + q0.next = 0 + q1.next = a + q2.next = 0 + q3.next = a return comb From 9a14f9022a299454c75cfd53efc98abfc81cac1b Mon Sep 17 00:00:00 2001 From: juliapaiva1 Date: Sun, 11 Sep 2022 13:47:31 -0300 Subject: [PATCH 06/60] dois demux funcionando --- .github/workflows/components.yml | 5 +++++ hw/components.py | 22 +++++++++++++++++----- 2 files changed, 22 insertions(+), 5 deletions(-) diff --git a/.github/workflows/components.yml b/.github/workflows/components.yml index e784933f..de1bcd2e 100644 --- a/.github/workflows/components.yml +++ b/.github/workflows/components.yml @@ -27,6 +27,11 @@ jobs: python -m pip install --upgrade pip pip install -r requirements.txt + - name: Combinacional + run: | + pytest hw/test_components.py + + # ------------- Tests ---------------- - name: test and16 run: | diff --git a/hw/components.py b/hw/components.py index 15ee1bba..cfdf5c1e 100644 --- a/hw/components.py +++ b/hw/components.py @@ -133,7 +133,7 @@ def comb(): @block -def deMux2way(a, q0, q1, sel): #hardware +def deMux2way(a, q0, q1, sel): """ deMux de 2 saídas e uma entrada. @@ -175,17 +175,29 @@ def deMux4way(a, q0, q1, q2, q3, sel): @always_comb def comb(): - if sel == 0: - q0.next = a + if sel == 11: + q0.next = 0 + q1.next = 0 + q2.next = 0 + q3.next = a + + if sel == 10: + q0.next = 0 q1.next = 0 q2.next = a q3.next = 0 - + + if sel == 00: + q0.next = a + q1.next = 0 + q2.next = 0 + q3.next = 0 + else: q0.next = 0 q1.next = a q2.next = 0 - q3.next = a + q3.next = 0 return comb From 8f368fa1ba43378367c141e906035dd969973b1f Mon Sep 17 00:00:00 2001 From: FeMCDias Date: Sun, 11 Sep 2022 17:31:37 -0300 Subject: [PATCH 07/60] Update Integrantes --- INTEGRANTES.json | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/INTEGRANTES.json b/INTEGRANTES.json index 4bea8ada..c7aac044 100644 --- a/INTEGRANTES.json +++ b/INTEGRANTES.json @@ -18,5 +18,12 @@ "name": "Júlia Ferreira de Paiva", "git-username": "juliapaiva1", "blackboard-username": "juliafp2" + }, + + { + "user": "4", + "name": "Felipe Maluli de Carvalho Dias", + "git-username": "FeMCDias", + "blackboard-username": "felipemcd1" } ] \ No newline at end of file From 9d131c065a323023e3c3d96f4373bf9d44634af9 Mon Sep 17 00:00:00 2001 From: juliapaiva1 Date: Sun, 11 Sep 2022 18:08:39 -0300 Subject: [PATCH 08/60] commit combinacional --- .github/workflows/components.yml | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/.github/workflows/components.yml b/.github/workflows/components.yml index de1bcd2e..0bf055f8 100644 --- a/.github/workflows/components.yml +++ b/.github/workflows/components.yml @@ -27,10 +27,6 @@ jobs: python -m pip install --upgrade pip pip install -r requirements.txt - - name: Combinacional - run: | - pytest hw/test_components.py - # ------------- Tests ---------------- - name: test and16 @@ -43,4 +39,8 @@ jobs: - name: Test deMux4way run: | - pytest hw/test_components.py -k deMux4way \ No newline at end of file + pytest hw/test_components.py -k deMux4way + + - name: Combinacional + run: | + pytest hw/test_components.py \ No newline at end of file From dea1955f545ccb6c4c5951ce2442a0ab721c79c8 Mon Sep 17 00:00:00 2001 From: juliapaiva1 Date: Sun, 11 Sep 2022 18:15:06 -0300 Subject: [PATCH 09/60] commit erro build --- .github/workflows/components.yml | 3 --- 1 file changed, 3 deletions(-) diff --git a/.github/workflows/components.yml b/.github/workflows/components.yml index 0bf055f8..c15e480e 100644 --- a/.github/workflows/components.yml +++ b/.github/workflows/components.yml @@ -29,9 +29,6 @@ jobs: # ------------- Tests ---------------- - - name: test and16 - run: | - pytest hw/test_components.py -k and16 - name: Test deMux2way run: | From 14d14c38edf233ae933ef998112d084ddfb5c88d Mon Sep 17 00:00:00 2001 From: juliapaiva1 Date: Sun, 11 Sep 2022 18:27:38 -0300 Subject: [PATCH 10/60] erro corrigido --- .github/workflows/components.yml | 3 --- 1 file changed, 3 deletions(-) diff --git a/.github/workflows/components.yml b/.github/workflows/components.yml index c15e480e..2bb931c5 100644 --- a/.github/workflows/components.yml +++ b/.github/workflows/components.yml @@ -38,6 +38,3 @@ jobs: run: | pytest hw/test_components.py -k deMux4way - - name: Combinacional - run: | - pytest hw/test_components.py \ No newline at end of file From 5a49b874ba36413c085b6a4fc6b0b6c04fb254d9 Mon Sep 17 00:00:00 2001 From: Alexandre Date: Sun, 11 Sep 2022 20:06:56 -0300 Subject: [PATCH 11/60] nome gp --- GRUPO.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/GRUPO.yml b/GRUPO.yml index f0433867..5fe51aec 100644 --- a/GRUPO.yml +++ b/GRUPO.yml @@ -1 +1 @@ -Nome-Grupo: "Macarrao" +Nome-Grupo: "Grupo Grã" From 5abece3d3d6ea7ba68c393ec7d7243fdd340b472 Mon Sep 17 00:00:00 2001 From: FeMCDias Date: Sun, 11 Sep 2022 22:50:11 -0300 Subject: [PATCH 12/60] Adicionado mux2way, mux4way, e mux8way funcionando e testados --- hw/components.py | 36 +++++++++++++++++++++++++++--------- 1 file changed, 27 insertions(+), 9 deletions(-) diff --git a/hw/components.py b/hw/components.py index aa9336e9..14608c2c 100644 --- a/hw/components.py +++ b/hw/components.py @@ -88,11 +88,10 @@ def mux2way(q, a, b, sel): Mux entre a e b, sel é o seletor """ foo = Signal(intbv(0)) - @always_comb def comb(): - q.next = foo - + q.next = a if sel == 0 else b + return comb @@ -109,10 +108,16 @@ def mux4way(q, a, b, c, d, sel): Mux entre a, b, c, d sel é o seletor """ foo = Signal(intbv(0)) - @always_comb def comb(): - q.next = foo + if sel == 0: + q.next = a + elif sel == 1: + q.next = b + elif sel == 2: + q.next = c + else: + q.next = d return comb @@ -122,13 +127,26 @@ def mux8way(q, a, b, c, d, e, f, g, h, sel): """ Mux de 8 entradas, simular aos anteriores. """ - foo = Signal(intbv(0)) - @always_comb def comb(): - q.next = foo - + if sel == 0: + q.next = a + elif sel == 1: + q.next = b + elif sel == 2: + q.next = c + elif sel == 3: + q.next = d + elif sel == 4: + q.next = e + elif sel == 5: + q.next = f + elif sel == 6: + q.next = g + else: + q.next = h + return comb From b642f4fac666a7185d772849e5cdd866a16ab477 Mon Sep 17 00:00:00 2001 From: Hiratsuca <104103173+Hiratsuca@users.noreply.github.com> Date: Sun, 11 Sep 2022 23:42:04 -0300 Subject: [PATCH 13/60] =?UTF-8?q?Subindo=20a=20fun=C3=A7=C3=A3o=20and16?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- INTEGRANTES.json | 13 +++++++++++++ hw/components.py | 4 ++-- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/INTEGRANTES.json b/INTEGRANTES.json index c7aac044..e903342b 100644 --- a/INTEGRANTES.json +++ b/INTEGRANTES.json @@ -25,5 +25,18 @@ "name": "Felipe Maluli de Carvalho Dias", "git-username": "FeMCDias", "blackboard-username": "felipemcd1" +}, + +{ + "user": "5", + "name": "Felipe Figueiró", + "git-username": "", + "blackboard-username": "" +}, +{ + "user": "6", + "name": "Gustavo Lagoa", + "git-username": "", + "blackboard-username": "" } ] \ No newline at end of file diff --git a/hw/components.py b/hw/components.py index cfdf5c1e..ec8e0b39 100644 --- a/hw/components.py +++ b/hw/components.py @@ -16,7 +16,7 @@ def and16(a, b, q): @always_comb def comb(): - q.next = foo + q.next = a and b return comb @@ -32,7 +32,7 @@ def or8way(a, b, c, d, e, f, g, h, q): @always_comb def comb(): - q.next = foo + q.next = a or b or c or d or e or f or g or h return comb From 026293d41e8e2c6bfe0f30402f5f5374f7a6fe50 Mon Sep 17 00:00:00 2001 From: Alexandre Date: Mon, 12 Sep 2022 00:59:39 -0300 Subject: [PATCH 14/60] zerado --- .github/workflows/components.yml | 12 +---- hw/components.py | 91 ++++++-------------------------- hw/test_components.py | 2 +- hw/toplevel.py | 4 +- 4 files changed, 20 insertions(+), 89 deletions(-) diff --git a/.github/workflows/components.yml b/.github/workflows/components.yml index 2bb931c5..23df9162 100644 --- a/.github/workflows/components.yml +++ b/.github/workflows/components.yml @@ -26,15 +26,7 @@ jobs: run: | python -m pip install --upgrade pip pip install -r requirements.txt - - # ------------- Tests ---------------- - - - name: Test deMux2way + - name: test and16 run: | - pytest hw/test_components.py -k deMux2way - - - name: Test deMux4way - run: | - pytest hw/test_components.py -k deMux4way - + pytest hw/test_components.py -k and16 diff --git a/hw/components.py b/hw/components.py index 364fff32..e742100a 100644 --- a/hw/components.py +++ b/hw/components.py @@ -9,14 +9,13 @@ def and16(a, b, q): a: 16 bits b: 16 bits q: 16 bits - and bit a bit entre a e b """ foo = Signal(0) @always_comb def comb(): - q.next = a and b + q.next = foo return comb @@ -25,14 +24,13 @@ def comb(): def or8way(a, b, c, d, e, f, g, h, q): """ a, b, c, ... h: 1 bit - or bit a bit entre a e b """ foo = Signal(intbv(0)) @always_comb def comb(): - q.next = a or b or c or d or e or f or g or h + q.next = foo return comb @@ -42,7 +40,6 @@ def orNway(a, q): """ a: 16 bits q: 1 bit - or bit a bit dos valores de a: a[0] or a[1] ... """ foo = Signal(intbv(0)) @@ -61,10 +58,8 @@ def barrelShifter(a, dir, size, q): dir: 1 bit size: n bits q: 16 bits - se dir for 0, shifta para direita `size` se dir for 1, shifta para esquerda `size` - exemplo: a = 0000 1111 0101 1010, dir = 0, size = 3 q = 0111 1010 1101 0000 """ @@ -84,14 +79,14 @@ def mux2way(q, a, b, sel): a: 16 bits b: 16 bits sel: 2 bits - Mux entre a e b, sel é o seletor """ foo = Signal(intbv(0)) + @always_comb def comb(): - q.next = a if sel == 0 else b - + q.next = foo + return comb @@ -104,20 +99,13 @@ def mux4way(q, a, b, c, d, sel): c: 16 bits d: 16 bits sel: 4 bits - Mux entre a, b, c, d sel é o seletor """ foo = Signal(intbv(0)) + @always_comb def comb(): - if sel == 0: - q.next = a - elif sel == 1: - q.next = b - elif sel == 2: - q.next = c - else: - q.next = d + q.next = foo return comb @@ -127,26 +115,13 @@ def mux8way(q, a, b, c, d, e, f, g, h, sel): """ Mux de 8 entradas, simular aos anteriores. """ + foo = Signal(intbv(0)) + @always_comb def comb(): - if sel == 0: - q.next = a - elif sel == 1: - q.next = b - elif sel == 2: - q.next = c - elif sel == 3: - q.next = d - elif sel == 4: - q.next = e - elif sel == 5: - q.next = f - elif sel == 6: - q.next = g - else: - q.next = h - + q.next = foo + return comb @@ -154,11 +129,8 @@ def comb(): def deMux2way(a, q0, q1, sel): """ deMux de 2 saídas e uma entrada. - - Lembre que a saída que não está ativada é 0 - Exemplo: - a = 0xFFAA, sel = 0 q0 = 0xFFAA q1 = 0 @@ -167,15 +139,8 @@ def deMux2way(a, q0, q1, sel): foo = Signal(intbv(0)) @always_comb - def comb(): - - if sel == 0: - q0.next = a - q1.next = 0 - - else: - q0.next = 0 - q1.next = a + def comb(): + q0.next = foo return comb @@ -184,7 +149,6 @@ def comb(): def deMux4way(a, q0, q1, q2, q3, sel): """ deMux de 4 saídas e uma entrada. - - Lembre que a saída que não está ativada é 0 """ @@ -192,30 +156,7 @@ def deMux4way(a, q0, q1, q2, q3, sel): @always_comb def comb(): - - if sel == 11: - q0.next = 0 - q1.next = 0 - q2.next = 0 - q3.next = a - - if sel == 10: - q0.next = 0 - q1.next = 0 - q2.next = a - q3.next = 0 - - if sel == 00: - q0.next = a - q1.next = 0 - q2.next = 0 - q3.next = 0 - - else: - q0.next = 0 - q1.next = a - q2.next = 0 - q3.next = 0 + q0.next = foo return comb @@ -224,7 +165,6 @@ def comb(): def deMux8way(a, q0, q1, q2, q3, q4, q5, q6, q7, sel): """ deMux de 8 saídas e uma entrada. - - Lembre que a saída que não está ativada é 0 """ @@ -259,7 +199,6 @@ def bin2bcd(b, bcd1, bcd0): """ componente que converte um vetor de b[8:] (bin) para dois digitos em BCD - Exemplo: bin = `01010010` BCD1 = 8 @@ -278,4 +217,4 @@ def comb(): # -----------------------------# # Conceito A -# -----------------------------# +# -----------------------------# \ No newline at end of file diff --git a/hw/test_components.py b/hw/test_components.py index dda59118..8356726d 100644 --- a/hw/test_components.py +++ b/hw/test_components.py @@ -215,4 +215,4 @@ def stimulus(): yield delay(1) sim = Simulation(ic1, stimulus) - sim.run() + sim.run() \ No newline at end of file diff --git a/hw/toplevel.py b/hw/toplevel.py index 6d1d0b1c..23ce3dc5 100755 --- a/hw/toplevel.py +++ b/hw/toplevel.py @@ -16,7 +16,7 @@ def toplevel(LEDR, SW, KEY, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, CLOCK_50, RESET_ hex0 = Signal(intbv(0)[7:]) hex1 = Signal(intbv(0)[7:]) - ic1 = bin2bcd(SW[8:0], bc1, bc0) + ic1 = bin2bcd(SW, bc1, bc0) ihex1 = bin2hex(hex1, bc1) ihex0 = bin2hex(hex0, bc0) @@ -42,4 +42,4 @@ def comb(): RESET_N = ResetSignal(0, active=0, isasync=True) top = toplevel(LEDR, SW, KEY, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, CLOCK_50, RESET_N) -top.convert(hdl="VHDL") +top.convert(hdl="VHDL") \ No newline at end of file From 2b691e148ba255dd9a73308dd2db2007ab7e17c5 Mon Sep 17 00:00:00 2001 From: Hiratsuca <104103173+Hiratsuca@users.noreply.github.com> Date: Mon, 12 Sep 2022 01:27:11 -0300 Subject: [PATCH 15/60] =?UTF-8?q?Subindo=20a=20fun=C3=A7=C3=A3o=20and16?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- hw/components.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/components.py b/hw/components.py index 364fff32..ab475aa7 100644 --- a/hw/components.py +++ b/hw/components.py @@ -16,6 +16,8 @@ def and16(a, b, q): @always_comb def comb(): + + q.next = a and b return comb From ce950e776c956b06eb8d57c505e05708bf1af7af Mon Sep 17 00:00:00 2001 From: FeMCDias Date: Mon, 12 Sep 2022 01:37:48 -0300 Subject: [PATCH 16/60] Adicionando funcao mux2way + teste --- .github/workflows/components.yml | 4 ++++ hw/components.py | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/.github/workflows/components.yml b/.github/workflows/components.yml index 23df9162..b8bf8e15 100644 --- a/.github/workflows/components.yml +++ b/.github/workflows/components.yml @@ -30,3 +30,7 @@ jobs: - name: test and16 run: | pytest hw/test_components.py -k and16 + + - name: test mux2way + run: | + pytest hw/test_components.py -k mux2way diff --git a/hw/components.py b/hw/components.py index f3e0d423..72f1e85b 100644 --- a/hw/components.py +++ b/hw/components.py @@ -84,7 +84,7 @@ def mux2way(q, a, b, sel): @always_comb def comb(): - q.next = foo + q.next = a if sel == 0 else b return comb From f87f4bdba4bccf6ae90021eaacf5aeec1c0f1fea Mon Sep 17 00:00:00 2001 From: FeMCDias Date: Mon, 12 Sep 2022 01:45:06 -0300 Subject: [PATCH 17/60] Concertei teste mux2way --- .github/workflows/components.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/components.yml b/.github/workflows/components.yml index b8bf8e15..be93faf3 100644 --- a/.github/workflows/components.yml +++ b/.github/workflows/components.yml @@ -33,4 +33,4 @@ jobs: - name: test mux2way run: | - pytest hw/test_components.py -k mux2way + pytest hw/test_components.py -k test_mux2way From 3659934fb2733fcf9d2e09b656e74389996643bc Mon Sep 17 00:00:00 2001 From: Hiratsuca <104103173+Hiratsuca@users.noreply.github.com> Date: Mon, 12 Sep 2022 01:53:26 -0300 Subject: [PATCH 18/60] =?UTF-8?q?Subindo=20a=20fun=C3=A7=C3=A3o=20+=20test?= =?UTF-8?q?e=20=20and16?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .github/workflows/components.yml | 4 ++++ hw/components.py | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/.github/workflows/components.yml b/.github/workflows/components.yml index 23df9162..b942cec4 100644 --- a/.github/workflows/components.yml +++ b/.github/workflows/components.yml @@ -30,3 +30,7 @@ jobs: - name: test and16 run: | pytest hw/test_components.py -k and16 + + - name: test or8way + run: | + pytest hw/test_components.py -k or8way diff --git a/hw/components.py b/hw/components.py index f3e0d423..fb19d92b 100644 --- a/hw/components.py +++ b/hw/components.py @@ -29,7 +29,7 @@ def or8way(a, b, c, d, e, f, g, h, q): @always_comb def comb(): - q.next = foo + q.next = a or b or c or d or e or f or g or h return comb From 2b0c339503300ca5e301a96d7aa59bb6238db3af Mon Sep 17 00:00:00 2001 From: FeMCDias Date: Mon, 12 Sep 2022 02:09:09 -0300 Subject: [PATCH 19/60] mux4way teste+funcao --- .github/workflows/components.yml | 4 ++++ hw/components.py | 9 ++++++++- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/.github/workflows/components.yml b/.github/workflows/components.yml index 5bf65800..2d7a1638 100644 --- a/.github/workflows/components.yml +++ b/.github/workflows/components.yml @@ -39,3 +39,7 @@ jobs: run: | pytest hw/test_components.py -k test_mux2way + - name: test mux4way + run: | + pytest hw/test_components.py -k test_mux4way + diff --git a/hw/components.py b/hw/components.py index 18e5242c..941fb2e1 100644 --- a/hw/components.py +++ b/hw/components.py @@ -104,7 +104,14 @@ def mux4way(q, a, b, c, d, sel): @always_comb def comb(): - q.next = foo + if sel == 0: + q.next = a + elif sel == 1: + q.next = b + elif sel == 2: + q.next = c + else: + q.next = d return comb From d79045ab0a4c0297f2fd98fb9d24e2e8e2e4ba67 Mon Sep 17 00:00:00 2001 From: Hiratsuca <104103173+Hiratsuca@users.noreply.github.com> Date: Mon, 12 Sep 2022 02:14:03 -0300 Subject: [PATCH 20/60] =?UTF-8?q?Subindo=20a=20fun=C3=A7=C3=A3o=20+=20test?= =?UTF-8?q?es=20deMux8way?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .github/workflows/components.yml | 5 +++++ hw/components.py | 9 ++++++++- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/.github/workflows/components.yml b/.github/workflows/components.yml index 2d7a1638..fca447af 100644 --- a/.github/workflows/components.yml +++ b/.github/workflows/components.yml @@ -43,3 +43,8 @@ jobs: run: | pytest hw/test_components.py -k test_mux4way + - name: test deMux8way + run: | + pytest hw/test_components.py -k test_deMux8way + + diff --git a/hw/components.py b/hw/components.py index 941fb2e1..38575937 100644 --- a/hw/components.py +++ b/hw/components.py @@ -178,7 +178,14 @@ def deMux8way(a, q0, q1, q2, q3, q4, q5, q6, q7, sel): @always_comb def comb(): - q0.next = foo + q0.next = a if sel == 0 else 0 + q1.next = a if sel == 1 else 0 + q2.next = a if sel == 2 else 0 + q3.next = a if sel == 3 else 0 + q4.next = a if sel == 4 else 0 + q5.next = a if sel == 5 else 0 + q6.next = a if sel == 6 else 0 + q7.next = a if sel == 7 else 0 return comb From da097ba558868f4da5f8734b522c2daf99a188d8 Mon Sep 17 00:00:00 2001 From: FeMCDias Date: Mon, 12 Sep 2022 02:18:44 -0300 Subject: [PATCH 21/60] Funcao Mux8way + Teste --- .github/workflows/components.yml | 4 ++++ hw/components.py | 17 ++++++++++++++++- 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/.github/workflows/components.yml b/.github/workflows/components.yml index fca447af..71df21d9 100644 --- a/.github/workflows/components.yml +++ b/.github/workflows/components.yml @@ -43,6 +43,10 @@ jobs: run: | pytest hw/test_components.py -k test_mux4way + - name: test mux8way + run: | + pytest hw/test_components.py -k test_mux8way + - name: test deMux8way run: | pytest hw/test_components.py -k test_deMux8way diff --git a/hw/components.py b/hw/components.py index 38575937..84fd8a91 100644 --- a/hw/components.py +++ b/hw/components.py @@ -126,7 +126,22 @@ def mux8way(q, a, b, c, d, e, f, g, h, sel): @always_comb def comb(): - q.next = foo + if sel == 0: + q.next = a + elif sel == 1: + q.next = b + elif sel == 2: + q.next = c + elif sel == 3: + q.next = d + elif sel == 4: + q.next = e + elif sel == 5: + q.next = f + elif sel == 6: + q.next = g + else: + q.next = h return comb From e0d38e60636139f3871b0a19d5508fbbe2bf5ffa Mon Sep 17 00:00:00 2001 From: Hiratsuca <104103173+Hiratsuca@users.noreply.github.com> Date: Mon, 12 Sep 2022 02:24:19 -0300 Subject: [PATCH 22/60] =?UTF-8?q?Subindo=20a=20fun=C3=A7=C3=A3o=20+=20test?= =?UTF-8?q?es=20orNway?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .github/workflows/components.yml | 4 ++++ hw/components.py | 3 ++- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/.github/workflows/components.yml b/.github/workflows/components.yml index 71df21d9..12133b9c 100644 --- a/.github/workflows/components.yml +++ b/.github/workflows/components.yml @@ -51,4 +51,8 @@ jobs: run: | pytest hw/test_components.py -k test_deMux8way + - name: test orNway + run: | + pytest hw/test_components.py -k orNway + diff --git a/hw/components.py b/hw/components.py index 84fd8a91..e9e645c6 100644 --- a/hw/components.py +++ b/hw/components.py @@ -45,7 +45,8 @@ def orNway(a, q): @always_comb def comb(): - q.next = foo + q.next = a[0] or a[1] or a[2] or a[3] or a[4] or a[5] or a[6] or a[7] or a[8] or a[9] or a[10] or a[11] or a[12] or a[13] or a[14] or a[15] + return comb From 5004460f7ccbb8a225d82e43a049eb6976ba26d8 Mon Sep 17 00:00:00 2001 From: FeMCDias Date: Mon, 12 Sep 2022 02:34:08 -0300 Subject: [PATCH 23/60] barrelShifter + teste Implementado --- .github/workflows/components.yml | 4 ++++ hw/components.py | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/.github/workflows/components.yml b/.github/workflows/components.yml index 12133b9c..f0cbe3c1 100644 --- a/.github/workflows/components.yml +++ b/.github/workflows/components.yml @@ -54,5 +54,9 @@ jobs: - name: test orNway run: | pytest hw/test_components.py -k orNway + + - name: test barrelShifter + run: | + pytest hw/test_components.py -k barrelShifter diff --git a/hw/components.py b/hw/components.py index e9e645c6..ee7f7199 100644 --- a/hw/components.py +++ b/hw/components.py @@ -67,7 +67,7 @@ def barrelShifter(a, dir, size, q): @always_comb def comb(): - q.next = foo + q.next = a <> size return comb From c5ac89a00d91df2e3fa2ae1c3a8e7f382d735718 Mon Sep 17 00:00:00 2001 From: Hiratsuca <104103173+Hiratsuca@users.noreply.github.com> Date: Mon, 12 Sep 2022 02:43:08 -0300 Subject: [PATCH 24/60] =?UTF-8?q?Subindo=20a=20fun=C3=A7=C3=A3o=20+=20test?= =?UTF-8?q?es=20deMux2way?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .github/workflows/components.yml | 4 ++++ hw/components.py | 8 +++++++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/.github/workflows/components.yml b/.github/workflows/components.yml index f0cbe3c1..a7f2aff9 100644 --- a/.github/workflows/components.yml +++ b/.github/workflows/components.yml @@ -59,4 +59,8 @@ jobs: run: | pytest hw/test_components.py -k barrelShifter + - name: test deMux2way + run: | + pytest hw/test_components.py -k test_deMux2way + diff --git a/hw/components.py b/hw/components.py index ee7f7199..33e7408e 100644 --- a/hw/components.py +++ b/hw/components.py @@ -162,7 +162,13 @@ def deMux2way(a, q0, q1, sel): @always_comb def comb(): - q0.next = foo + if sel == 0: + q0.next = a + q1.next = 0 + + else: + q0.next = 0 + q1.next = a return comb From a5e720a8a4805634c5a4c8095169499af012bd81 Mon Sep 17 00:00:00 2001 From: FeMCDias Date: Mon, 12 Sep 2022 02:50:05 -0300 Subject: [PATCH 25/60] deMux4Way + teste implementado --- .github/workflows/components.yml | 4 ++++ hw/components.py | 24 +++++++++++++++++++++++- 2 files changed, 27 insertions(+), 1 deletion(-) diff --git a/.github/workflows/components.yml b/.github/workflows/components.yml index a7f2aff9..1a21ec84 100644 --- a/.github/workflows/components.yml +++ b/.github/workflows/components.yml @@ -63,4 +63,8 @@ jobs: run: | pytest hw/test_components.py -k test_deMux2way + - name: test deMux4way + run: | + pytest hw/test_components.py -k test_deMux4way + diff --git a/hw/components.py b/hw/components.py index 33e7408e..6f2ff921 100644 --- a/hw/components.py +++ b/hw/components.py @@ -184,7 +184,29 @@ def deMux4way(a, q0, q1, q2, q3, sel): @always_comb def comb(): - q0.next = foo + if sel == 11: + q0.next = 0 + q1.next = 0 + q2.next = 0 + q3.next = a + + if sel == 10: + q0.next = 0 + q1.next = 0 + q2.next = a + q3.next = 0 + + if sel == 00: + q0.next = a + q1.next = 0 + q2.next = 0 + q3.next = 0 + + else: + q0.next = 0 + q1.next = a + q2.next = 0 + q3.next = 0 return comb From 420138601c99462c43dd0eacde786a200998c7e1 Mon Sep 17 00:00:00 2001 From: Hiratsuca <104103173+Hiratsuca@users.noreply.github.com> Date: Mon, 12 Sep 2022 02:57:22 -0300 Subject: [PATCH 26/60] =?UTF-8?q?Subindo=20a=20fun=C3=A7=C3=A3o=20+=20test?= =?UTF-8?q?es=20+=20corre=C3=A7=C3=A3o=20teste=20bin2bcd?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .github/workflows/components.yml | 4 ++++ hw/components.py | 4 ++-- hw/test_components.py | 24 +++++++++++++++++++++--- 3 files changed, 27 insertions(+), 5 deletions(-) diff --git a/.github/workflows/components.yml b/.github/workflows/components.yml index 1a21ec84..a6b64ec1 100644 --- a/.github/workflows/components.yml +++ b/.github/workflows/components.yml @@ -67,4 +67,8 @@ jobs: run: | pytest hw/test_components.py -k test_deMux4way + - name: test bin2bcd + run: | + pytest hw/test_components.py -k bin2bcd + diff --git a/hw/components.py b/hw/components.py index 6f2ff921..92dd4411 100644 --- a/hw/components.py +++ b/hw/components.py @@ -266,8 +266,8 @@ def bin2bcd(b, bcd1, bcd0): @always_comb def comb(): - bcd1.next = foo - bcd0.next = foo + bcd1.next = b[4:] + bcd0.next = b[:4] return comb diff --git a/hw/test_components.py b/hw/test_components.py index 8356726d..ec3eb9bc 100644 --- a/hw/test_components.py +++ b/hw/test_components.py @@ -203,16 +203,34 @@ def stimulus(): sim.run() +# def test_bin2bcd(): +# bc0 = Signal(intbv(0)[4:]) +# bc1 = Signal(intbv(0)[4:]) +# b = Signal(intbv(0)[9:]) + +# ic1 = bin2bcd(b, bc1, bc0) + +# @instance +# def stimulus(): +# yield delay(1) + +# sim = Simulation(ic1, stimulus) +# sim.run() + def test_bin2bcd(): bc0 = Signal(intbv(0)[4:]) bc1 = Signal(intbv(0)[4:]) b = Signal(intbv(0)[9:]) - ic1 = bin2bcd(b, bc1, bc0) + resultado = bin2bcd(b, bc1, bc0) @instance def stimulus(): - yield delay(1) + for a in range(16*2): + bc0.next, bc1.next = [randrange(16) for a in range(0,2,1)] + yield delay(10) + assert b == bc0[:4] + assert b == bc1[:4] - sim = Simulation(ic1, stimulus) + sim = Simulation(resultado, stimulus) sim.run() \ No newline at end of file From 7ccc6ec7ab15cba30ce5b1a794b0ef741c000074 Mon Sep 17 00:00:00 2001 From: Hiratsuca <104103173+Hiratsuca@users.noreply.github.com> Date: Mon, 12 Sep 2022 03:04:22 -0300 Subject: [PATCH 27/60] Subindo o arquivo toplevel.py correto --- hw/toplevel.py | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/hw/toplevel.py b/hw/toplevel.py index 23ce3dc5..a3a71e36 100755 --- a/hw/toplevel.py +++ b/hw/toplevel.py @@ -16,9 +16,14 @@ def toplevel(LEDR, SW, KEY, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, CLOCK_50, RESET_ hex0 = Signal(intbv(0)[7:]) hex1 = Signal(intbv(0)[7:]) + # Funções que usavam variáveis erradas: + # ic1 = bin2bcd(SW[8:0], bc1, bc0) + # ihex1 = bin2hex(hex1, bc1) + # ihex0 = bin2hex(hex0, bc0) + ic1 = bin2bcd(SW, bc1, bc0) - ihex1 = bin2hex(hex1, bc1) - ihex0 = bin2hex(hex0, bc0) + ihex1 = bin2hex(HEX1, bc1) + ihex0 = bin2hex(HEX0, bc0) # ---------------------------------------- # @always_comb @@ -42,4 +47,4 @@ def comb(): RESET_N = ResetSignal(0, active=0, isasync=True) top = toplevel(LEDR, SW, KEY, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, CLOCK_50, RESET_N) -top.convert(hdl="VHDL") \ No newline at end of file +top.convert(hdl="VHDL") From b05ae673ccdc8a1ca32eb8e8f257664071003090 Mon Sep 17 00:00:00 2001 From: FeMCDias Date: Wed, 14 Sep 2022 23:05:02 -0300 Subject: [PATCH 28/60] bin2bcd teste + funcao --- hw/components.py | 7 ++++--- hw/test_components.py | 12 +++++------- 2 files changed, 9 insertions(+), 10 deletions(-) diff --git a/hw/components.py b/hw/components.py index 92dd4411..a5c2adb7 100644 --- a/hw/components.py +++ b/hw/components.py @@ -263,11 +263,12 @@ def bin2bcd(b, bcd1, bcd0): """ foo = Signal(intbv(0)[4:]) - + tens = [num//10 for num in range(100)] + ones = [num%10 for num in range(100)] @always_comb def comb(): - bcd1.next = b[4:] - bcd0.next = b[:4] + bcd1.next = tens[b] + bcd0.next = ones[b] return comb diff --git a/hw/test_components.py b/hw/test_components.py index ec3eb9bc..3cacb5e1 100644 --- a/hw/test_components.py +++ b/hw/test_components.py @@ -221,16 +221,14 @@ def test_bin2bcd(): bc0 = Signal(intbv(0)[4:]) bc1 = Signal(intbv(0)[4:]) b = Signal(intbv(0)[9:]) - resultado = bin2bcd(b, bc1, bc0) - @instance def stimulus(): - for a in range(16*2): - bc0.next, bc1.next = [randrange(16) for a in range(0,2,1)] - yield delay(10) - assert b == bc0[:4] - assert b == bc1[:4] + for dec in range(100): + b.next = dec + yield delay(1) + assert bc0 == dec % 10 + assert bc1 == dec // 10 sim = Simulation(resultado, stimulus) sim.run() \ No newline at end of file From c410766a772b504127de8486f7c20ce4112d1f58 Mon Sep 17 00:00:00 2001 From: FeMCDias Date: Wed, 14 Sep 2022 23:24:32 -0300 Subject: [PATCH 29/60] bin2hex --- hw/components.py | 36 ++++++++++++++++++++++++++++++++++-- 1 file changed, 34 insertions(+), 2 deletions(-) diff --git a/hw/components.py b/hw/components.py index a5c2adb7..43e81c51 100644 --- a/hw/components.py +++ b/hw/components.py @@ -243,10 +243,42 @@ def bin2hex(hex0, sw): """ importar do lab! """ - + foo = Signal(intbv(0)) + @always_comb def comb(): - hex0.next[4:] = sw[4:] + if sw[4:0] == 0: + hex0.next = "1000000" + elif sw[4:0] == 1: + hex0.next = "1001111" + elif sw[4:0] == 2: + hex0.next = "0100100" + elif sw[4:0] == 3: + hex0.next = "0110000" + elif sw[4:0] == 4: + hex0.next = "0011001" + elif sw[4:0] == 5: + hex0.next = "0010010" + elif sw[4:0] == 6: + hex0.next = "0000010" + elif sw[4:0] == 7: + hex0.next = "1111000" + elif sw[4:0] == 8: + hex0.next = "1111111" + elif sw[4:0] == 9: + hex0.next = "0010000" + elif sw[4:0] == 10: + hex0.next = "0001000" + elif sw[4:0] == 11: + hex0.next = "0000011" + elif sw[4:0] == 12: + hex0.next = "1000110" + elif sw[4:0] == 13: + hex0.next = "0100001" + elif sw[4:0] == 14: + hex0.next = "0000110" + else: + hex0.next = "0001110" return comb From 12ba40ddf61e982c98568d6a5cf5015045a53db5 Mon Sep 17 00:00:00 2001 From: LuccaHiratsuca Date: Wed, 14 Sep 2022 23:33:29 -0300 Subject: [PATCH 30/60] env --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index 168e776a..6cf3a254 100644 --- a/.gitignore +++ b/.gitignore @@ -7,3 +7,4 @@ htmlcov *.v .direnv/ *.ini +/env \ No newline at end of file From 39b31a3f3e0ea8d8b3e8d210eef920aea556468c Mon Sep 17 00:00:00 2001 From: LuccaHiratsuca Date: Wed, 14 Sep 2022 23:56:35 -0300 Subject: [PATCH 31/60] commit --- README.md | 2 ++ hw/components.py | 9 +++++---- hw/vetores.py | 2 ++ 3 files changed, 9 insertions(+), 4 deletions(-) create mode 100644 README.md create mode 100644 hw/vetores.py diff --git a/README.md b/README.md new file mode 100644 index 00000000..ead0077e --- /dev/null +++ b/README.md @@ -0,0 +1,2 @@ +link do video - conceito A +https://youtube.com/shorts/-07dCv11VKs?feature=share \ No newline at end of file diff --git a/hw/components.py b/hw/components.py index 43e81c51..4286e3b6 100644 --- a/hw/components.py +++ b/hw/components.py @@ -1,7 +1,7 @@ #!/usr/bin/env python3 from myhdl import * - +import vetores @block def and16(a, b, q): @@ -243,7 +243,6 @@ def bin2hex(hex0, sw): """ importar do lab! """ - foo = Signal(intbv(0)) @always_comb def comb(): @@ -295,8 +294,10 @@ def bin2bcd(b, bcd1, bcd0): """ foo = Signal(intbv(0)[4:]) - tens = [num//10 for num in range(100)] - ones = [num%10 for num in range(100)] + + tens = vetores.tens + ones = vetores.ones + @always_comb def comb(): bcd1.next = tens[b] diff --git a/hw/vetores.py b/hw/vetores.py new file mode 100644 index 00000000..45e120cd --- /dev/null +++ b/hw/vetores.py @@ -0,0 +1,2 @@ +tens = tuple(num//10 for num in range(100)) +ones = tuple(num%10 for num in range(100)) \ No newline at end of file From c293a498892ccc4d60f12eaa995a24d16531313c Mon Sep 17 00:00:00 2001 From: LuccaHiratsuca Date: Thu, 15 Sep 2022 00:00:19 -0300 Subject: [PATCH 32/60] vetores --- hw/components.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/components.py b/hw/components.py index 4286e3b6..9f7adcce 100644 --- a/hw/components.py +++ b/hw/components.py @@ -1,7 +1,7 @@ #!/usr/bin/env python3 from myhdl import * -import vetores +from hw import vetores.py @block def and16(a, b, q): From e58169da34564294a45e59ad65c730cc0a475882 Mon Sep 17 00:00:00 2001 From: LuccaHiratsuca Date: Thu, 15 Sep 2022 00:03:11 -0300 Subject: [PATCH 33/60] vetores novo --- hw/components.py | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/hw/components.py b/hw/components.py index 9f7adcce..1922ad4a 100644 --- a/hw/components.py +++ b/hw/components.py @@ -1,7 +1,6 @@ #!/usr/bin/env python3 from myhdl import * -from hw import vetores.py @block def and16(a, b, q): @@ -295,8 +294,8 @@ def bin2bcd(b, bcd1, bcd0): foo = Signal(intbv(0)[4:]) - tens = vetores.tens - ones = vetores.ones + tens = tuple(num//10 for num in range(100)) + ones = tuple(num%10 for num in range(100)) @always_comb def comb(): From 5f3db0dc7d463703edc4fe6f3bb2a59aa81470e2 Mon Sep 17 00:00:00 2001 From: FeMCDias Date: Thu, 15 Sep 2022 00:06:50 -0300 Subject: [PATCH 34/60] Delete vetores --- hw/vetores.py | 2 -- 1 file changed, 2 deletions(-) delete mode 100644 hw/vetores.py diff --git a/hw/vetores.py b/hw/vetores.py deleted file mode 100644 index 45e120cd..00000000 --- a/hw/vetores.py +++ /dev/null @@ -1,2 +0,0 @@ -tens = tuple(num//10 for num in range(100)) -ones = tuple(num%10 for num in range(100)) \ No newline at end of file From 41c898f6a7dbbbffb877726d00c257592ea4d2c3 Mon Sep 17 00:00:00 2001 From: FeMCDias Date: Mon, 19 Sep 2022 00:17:41 -0300 Subject: [PATCH 35/60] configurando repo para novo projeto --- .github/workflows/components.yml | 5 +- hw/test_ula.py | 168 +++++++++++++++++++++++++++++++ hw/ula.py | 146 +++++++++++++++++++++++++++ 3 files changed, 318 insertions(+), 1 deletion(-) create mode 100755 hw/test_ula.py create mode 100644 hw/ula.py diff --git a/.github/workflows/components.yml b/.github/workflows/components.yml index a6b64ec1..d69e4f17 100644 --- a/.github/workflows/components.yml +++ b/.github/workflows/components.yml @@ -70,5 +70,8 @@ jobs: - name: test bin2bcd run: | pytest hw/test_components.py -k bin2bcd - + + - name: Combinacional + run: | + pytest hw/test_components.py diff --git a/hw/test_ula.py b/hw/test_ula.py new file mode 100755 index 00000000..0e32b7a8 --- /dev/null +++ b/hw/test_ula.py @@ -0,0 +1,168 @@ +#!/usr/bin/env python3 +import random +from myhdl import block, instance, Signal, intbv, delay, bin +from .ula import * + +random.seed(5) +randrange = random.randrange + + +def test_ula(): + x = Signal(intbv(1)[16:]) + y = Signal(intbv(2)[16:]) + saida = Signal(intbv(0)[16:]) + control = Signal(intbv(0)) + zr = Signal(bool(0)) + ng = Signal(bool(0)) + ula_1 = ula(x, y, control, zr, ng, saida) + + @instance + def stimulus(): + control.next = 0b000010 + yield delay(10) + assert saida == x + y + + control.next = 0b000000 + yield delay(10) + assert saida == (x & y) + + control.next = 0b100010 + yield delay(10) + assert saida == y + + control.next = 0b001010 + yield delay(10) + assert saida == x + + control.next = 0b100110 + yield delay(10) + assert saida == ~y + + control.next = 0b011010 + yield delay(10) + assert saida == ~x + + control.next = 0b101010 + yield delay(10) + assert saida == 0 + + control.next = 0b101000 + yield delay(10) + assert saida == 0 + + control.next = 0b101001 + yield delay(10) + assert saida == intbv(-1)[16:] + + # ------ zr ng --------# + assert zr == 0 and ng == 1 + + control.next = 0b101000 + yield delay(10) + assert zr == 1 and ng == 0 + + control.next = 0b000010 + yield delay(10) + assert zr == 0 and ng == 0 + + sim = Simulation(ula_1, stimulus) + sim.run() + + +def test_zerador(): + z = Signal(bool(0)) + a = Signal(intbv(0)) + y = Signal(intbv(0)) + zerador_1 = zerador(z, a, y) + + @instance + def stimulus(): + a.next = randrange(2**16 - 1) + z.next = 0 + yield delay(10) + assert y == a + z.next = 1 + yield delay(10) + assert y == 0 + + sim = Simulation(zerador_1, stimulus) + sim.run() + + +def test_comparador(): + a = Signal(intbv(0)) + ng = Signal(bool(0)) + zr = Signal(bool(0)) + comparador_1 = comparador(a, zr, ng, 16) + + @instance + def stimulus(): + a.next = 0 + yield delay(10) + assert ng == 0 or zr == 1 + a.next = 0xFFFF + yield delay(10) + assert ng == 1 or zr == 0 + a.next = 32 + yield delay(10) + assert ng == 0 or zr == 0 + + sim = Simulation(comparador_1, stimulus) + sim.run() + + +def test_inversor(): + z = Signal(bool(0)) + a = Signal(intbv(0)) + y = Signal(intbv(0)) + + inversor_1 = inversor(z, a, y) + + @instance + def stimulus(): + for i in range(256): + a.next = randrange(2**16 - 1) + z.next = randrange(2) + yield delay(1) + if z == 0: + assert a == y + else: + assert a == ~y + + sim = Simulation(inversor_1, stimulus) + sim.run() + + +def test_inc(): + a = Signal(intbv(0)) + q = Signal(intbv(0)) + + inc16_1 = inc(a, q) + + @instance + def stimulus(): + for i in range(256): + a.next = randrange(2**16 - 2) + yield delay(1) + assert q == a + 1 + + sim = Simulation(inc16_1, stimulus) + sim.run() + + +def test_add(): + a = Signal(intbv(0)) + b = Signal(intbv(0)) + q = Signal(intbv(0)) + + add16_1 = add(a, b, q) + + @instance + def stimulus(): + for i in range(256): + a.next, b.next = [randrange(2**15 - 1) for i in range(2)] + yield delay(1) + assert q == a + b + + sim = Simulation(add16_1, stimulus) + sim.run() diff --git a/hw/ula.py b/hw/ula.py new file mode 100644 index 00000000..a4d19973 --- /dev/null +++ b/hw/ula.py @@ -0,0 +1,146 @@ +#!/usr/bin/env python3 + +from myhdl import * + + +@block +def ula(x, y, c, zr, ng, saida, width=16): + + zx_out = Signal(intbv(0)[width:]) + nx_out = Signal(intbv(0)[width:]) + zy_out = Signal(intbv(0)[width:]) + ny_out = Signal(intbv(0)[width:]) + and_out = Signal(intbv(0)[width:]) + add_out = Signal(intbv(0)[width:]) + mux_out = Signal(intbv(0)[width:]) + no_out = Signal(intbv(0)[width:]) + + c_zx = c(5) + c_nx = c(4) + c_zy = c(3) + c_ny = c(2) + c_f = c(1) + c_no = c(0) + + @always_comb + def comb(): + pass + + return instances() + + +# -z faz complemento de dois +# ~z inverte bit a bit +@block +def inversor(z, a, y): + @always_comb + def comb(): + pass + + return instances() + + +@block +def comparador(a, zr, ng, width): + # width insica o tamanho do vetor a + @always_comb + def comb(): + pass + + return instances() + + +@block +def zerador(z, a, y): + @always_comb + def comb(): + pass + + return instances() + + +@block +def add(a, b, q): + @always_comb + def comb(): + pass + + return instances() + + +@block +def inc(a, q): + @always_comb + def comb(): + pass + + return instances() + + +# ---------------------------------------------- +# Conceito B +# ---------------------------------------------- + + +@block +def halfAdder(a, b, soma, carry): + s = Signal(bool()) + c = Signal(bool()) + + @always_comb + def comb(): + s = a ^ b + c = a & b + + soma.next = s + carry.next = c + + return instances() + + +@block +def fullAdder(a, b, c, soma, carry): + s = [Signal(bool(0)) for i in range(3)] + haList = [None for i in range(2)] + + haList[0] = halfAdder(a, b, s[0], s[1]) # 2 + haList[1] = halfAdder(c, s[0], soma, s[2]) # 3 + + @always_comb + def comb(): + carry.next = s[1] | s[2] # 4 + + return instances() + + +@block +def addcla4(a, b, q): + @always_comb + def comb(): + pass + + return instances() + + +@block +def addcla16(a, b, q): + @always_comb + def comb(): + pass + + return instances() + + +# ---------------------------------------------- +# Conceito A +# ---------------------------------------------- + + +@block +def ula_new(x, y, c, zr, ng, sr, sf, bcd, saida, width=16): + pass + + +@block +def bcdAdder(x, y, z): + pass From 45d0a819f3f20be62c4e34cb4dd8c112b8685ec1 Mon Sep 17 00:00:00 2001 From: FeMCDias Date: Mon, 19 Sep 2022 00:24:12 -0300 Subject: [PATCH 36/60] configurando repo + modificando grupo.yml --- GRUPO.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/GRUPO.yml b/GRUPO.yml index 5fe51aec..2a48da76 100644 --- a/GRUPO.yml +++ b/GRUPO.yml @@ -1 +1,2 @@ Nome-Grupo: "Grupo Grã" +Scrum-Master: "Felipe Maluli de Carvalho Dias" \ No newline at end of file From 2ba7741a8859f66423744f8862fa74dcd34a9e87 Mon Sep 17 00:00:00 2001 From: Hiratsuca <104103173+Hiratsuca@users.noreply.github.com> Date: Mon, 19 Sep 2022 01:12:50 -0300 Subject: [PATCH 37/60] =?UTF-8?q?Subindo=20fun=C3=A7=C3=A3o=20inc=20+=20te?= =?UTF-8?q?ste?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .github/workflows/components.yml | 5 +++++ hw/ula.py | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/.github/workflows/components.yml b/.github/workflows/components.yml index d69e4f17..c4195692 100644 --- a/.github/workflows/components.yml +++ b/.github/workflows/components.yml @@ -75,3 +75,8 @@ jobs: run: | pytest hw/test_components.py + - name: inc + run: | + pytest hw/ula.py -k test_inc + + diff --git a/hw/ula.py b/hw/ula.py index a4d19973..263dce26 100644 --- a/hw/ula.py +++ b/hw/ula.py @@ -72,7 +72,7 @@ def comb(): def inc(a, q): @always_comb def comb(): - pass + q.next = a + 1 return instances() From 9d64edf1709f08c23caedb6d7f59123a4f3950dd Mon Sep 17 00:00:00 2001 From: Alexandre Date: Mon, 19 Sep 2022 01:17:00 -0300 Subject: [PATCH 38/60] add ula --- .gitignore | 3 ++- hw/ula.py | 3 +-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/.gitignore b/.gitignore index 6cf3a254..33b0efa1 100644 --- a/.gitignore +++ b/.gitignore @@ -7,4 +7,5 @@ htmlcov *.v .direnv/ *.ini -/env \ No newline at end of file +/env +/env] \ No newline at end of file diff --git a/hw/ula.py b/hw/ula.py index a4d19973..cf40012d 100644 --- a/hw/ula.py +++ b/hw/ula.py @@ -63,8 +63,7 @@ def comb(): def add(a, b, q): @always_comb def comb(): - pass - + q.next = a and b return instances() From 175f658eab6e4ecc6cbb34a935f52cdd13d515dd Mon Sep 17 00:00:00 2001 From: Hiratsuca <104103173+Hiratsuca@users.noreply.github.com> Date: Mon, 19 Sep 2022 01:25:28 -0300 Subject: [PATCH 39/60] Arrumando nome teste --- .github/workflows/components.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/components.yml b/.github/workflows/components.yml index c4195692..b298e76f 100644 --- a/.github/workflows/components.yml +++ b/.github/workflows/components.yml @@ -75,7 +75,7 @@ jobs: run: | pytest hw/test_components.py - - name: inc + - name: test inc run: | pytest hw/ula.py -k test_inc From a9d1dc7f02dfb52a32b9bcad45dc9875755959c9 Mon Sep 17 00:00:00 2001 From: Alexandre Date: Mon, 19 Sep 2022 01:28:45 -0300 Subject: [PATCH 40/60] corrigindo add ula --- hw/ula.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ula.py b/hw/ula.py index cf40012d..77a513fd 100644 --- a/hw/ula.py +++ b/hw/ula.py @@ -63,7 +63,7 @@ def comb(): def add(a, b, q): @always_comb def comb(): - q.next = a and b + q.next = a + b return instances() From b65d8a126d02d6be58eb6ad09946942e37d8dfd3 Mon Sep 17 00:00:00 2001 From: Alexandre Date: Mon, 19 Sep 2022 01:31:06 -0300 Subject: [PATCH 41/60] colocando actions --- .github/workflows/components.yml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/.github/workflows/components.yml b/.github/workflows/components.yml index d69e4f17..adefa0d7 100644 --- a/.github/workflows/components.yml +++ b/.github/workflows/components.yml @@ -74,4 +74,9 @@ jobs: - name: Combinacional run: | pytest hw/test_components.py + + - name: test add + run: | + pytest hw/ula.py -k test_add + From 75d0304d4a0689a28006a72e27dfc80b826b50c5 Mon Sep 17 00:00:00 2001 From: Alexandre Date: Mon, 19 Sep 2022 01:34:48 -0300 Subject: [PATCH 42/60] add final --- .github/workflows/components.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/components.yml b/.github/workflows/components.yml index adefa0d7..72227ef3 100644 --- a/.github/workflows/components.yml +++ b/.github/workflows/components.yml @@ -77,6 +77,6 @@ jobs: - name: test add run: | - pytest hw/ula.py -k test_add + pytest hw/test_ula.py -k test_add From 9aa04e10c5521fff268732dccf4c33d22c9175c5 Mon Sep 17 00:00:00 2001 From: Hiratsuca <104103173+Hiratsuca@users.noreply.github.com> Date: Mon, 19 Sep 2022 01:39:16 -0300 Subject: [PATCH 43/60] Concertar o teste AGAIN --- .github/workflows/components.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/components.yml b/.github/workflows/components.yml index b298e76f..c71af25d 100644 --- a/.github/workflows/components.yml +++ b/.github/workflows/components.yml @@ -77,6 +77,6 @@ jobs: - name: test inc run: | - pytest hw/ula.py -k test_inc + pytest hw/test_ula.py -k test_inc From 8bf368f536572cdc45c0b1500e08da5c0de0faac Mon Sep 17 00:00:00 2001 From: FeMCDias Date: Mon, 19 Sep 2022 01:51:22 -0300 Subject: [PATCH 44/60] arrumando identacao --- .github/workflows/components.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/components.yml b/.github/workflows/components.yml index d69e4f17..a0d1c3ef 100644 --- a/.github/workflows/components.yml +++ b/.github/workflows/components.yml @@ -73,5 +73,5 @@ jobs: - name: Combinacional run: | - pytest hw/test_components.py + pytest hw/test_components.py From d5af0195c5eac96f1312f772f3d3257f8e094000 Mon Sep 17 00:00:00 2001 From: Alexandre Date: Mon, 19 Sep 2022 01:53:30 -0300 Subject: [PATCH 45/60] zerador 1 --- .github/workflows/components.yml | 8 ++++++-- hw/ula.py | 5 +++-- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/.github/workflows/components.yml b/.github/workflows/components.yml index 72227ef3..05c37e74 100644 --- a/.github/workflows/components.yml +++ b/.github/workflows/components.yml @@ -73,10 +73,14 @@ jobs: - name: Combinacional run: | - pytest hw/test_components.py + pytest hw/test_components.py - name: test add run: | - pytest hw/test_ula.py -k test_add + pytest hw/test_ula.py -k test_add + + - name: test zerador + run: | + pytest hw/test_ula.py -k test_zerador diff --git a/hw/ula.py b/hw/ula.py index 77a513fd..72f9027a 100644 --- a/hw/ula.py +++ b/hw/ula.py @@ -54,8 +54,9 @@ def comb(): def zerador(z, a, y): @always_comb def comb(): - pass - + if z == 0: + a.next = 0 + y.next = 0 return instances() From 87e5311706cdae90b1c37fe253bafa10db21812d Mon Sep 17 00:00:00 2001 From: Alexandre Date: Mon, 19 Sep 2022 01:55:07 -0300 Subject: [PATCH 46/60] compoents final --- .github/workflows/components.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/components.yml b/.github/workflows/components.yml index 72227ef3..ff0b3611 100644 --- a/.github/workflows/components.yml +++ b/.github/workflows/components.yml @@ -73,10 +73,10 @@ jobs: - name: Combinacional run: | - pytest hw/test_components.py + pytest hw/test_components.py - name: test add run: | - pytest hw/test_ula.py -k test_add + pytest hw/test_ula.py -k test_add From e6ce30b772603985fc6bd541b1123a9b5e0abe71 Mon Sep 17 00:00:00 2001 From: Hiratsuca <104103173+Hiratsuca@users.noreply.github.com> Date: Mon, 19 Sep 2022 01:59:43 -0300 Subject: [PATCH 47/60] Arrumando NOVAMENTE --- .github/workflows/components.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/components.yml b/.github/workflows/components.yml index c71af25d..a8bc8622 100644 --- a/.github/workflows/components.yml +++ b/.github/workflows/components.yml @@ -73,10 +73,10 @@ jobs: - name: Combinacional run: | - pytest hw/test_components.py + pytest hw/test_components.py - name: test inc run: | - pytest hw/test_ula.py -k test_inc + pytest hw/test_ula.py -k test_inc From 51a65526b79fa6dd45b63744064df80e5c0e71f9 Mon Sep 17 00:00:00 2001 From: Hiratsuca <104103173+Hiratsuca@users.noreply.github.com> Date: Mon, 19 Sep 2022 02:02:57 -0300 Subject: [PATCH 48/60] Create exit --- exit | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 exit diff --git a/exit b/exit new file mode 100644 index 00000000..47bb29f0 --- /dev/null +++ b/exit @@ -0,0 +1,10 @@ + and16 + bin2bcd + deMux2way + deMux8way +* inc + main + or8way + orNway + test_inc + toplevel From 1882a7dd42b78384cd9c1da995b74b4ce3285114 Mon Sep 17 00:00:00 2001 From: FeMCDias Date: Mon, 19 Sep 2022 02:20:31 -0300 Subject: [PATCH 49/60] comparador implementado e testado --- .github/workflows/components.yml | 4 ++++ hw/ula.py | 9 ++++++++- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/.github/workflows/components.yml b/.github/workflows/components.yml index 077b1788..fa91548c 100644 --- a/.github/workflows/components.yml +++ b/.github/workflows/components.yml @@ -83,3 +83,7 @@ jobs: run: | pytest hw/test_ula.py -k test_inc + - name: test comparador + run: | + pytest hw/test_ula.py -k test_comparador + diff --git a/hw/ula.py b/hw/ula.py index a4a81c2b..872f0f93 100644 --- a/hw/ula.py +++ b/hw/ula.py @@ -45,7 +45,14 @@ def comparador(a, zr, ng, width): # width insica o tamanho do vetor a @always_comb def comb(): - pass + if a == 0: + zr.next = 1 + else: + zr.next = 0 + if a < 0: + ng.next = 1 + else: + ng.next = 0 return instances() From b79b0f5c5c44650bc031cf039e7d0aeb41fdb5dc Mon Sep 17 00:00:00 2001 From: Alexandre Date: Mon, 19 Sep 2022 02:25:00 -0300 Subject: [PATCH 50/60] zerador 2 --- hw/ula.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/ula.py b/hw/ula.py index 72f9027a..35c5db2c 100644 --- a/hw/ula.py +++ b/hw/ula.py @@ -55,8 +55,8 @@ def zerador(z, a, y): @always_comb def comb(): if z == 0: - a.next = 0 - y.next = 0 + a.next = y + else: a.next = 0 return instances() From ab050a1a94c1fe718c455e1ceb08b21833213d1d Mon Sep 17 00:00:00 2001 From: Alexandre Date: Mon, 19 Sep 2022 02:29:26 -0300 Subject: [PATCH 51/60] corrigindo components --- .github/workflows/components.yml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/.github/workflows/components.yml b/.github/workflows/components.yml index 63a1dfcc..14c53aa5 100644 --- a/.github/workflows/components.yml +++ b/.github/workflows/components.yml @@ -77,6 +77,11 @@ jobs: - name: test add run: | - pytest hw/test_ula.py -k test_add + pytest hw/test_ula.py -k test_add + + - name: test zerador + run: | + pytest hw/test_ula.py -k test_zerador + From 9c18e01630b7645b90ac497aad73811b6e1fba4c Mon Sep 17 00:00:00 2001 From: FeMCDias Date: Mon, 19 Sep 2022 02:41:24 -0300 Subject: [PATCH 52/60] inversor implementado e testado --- .github/workflows/components.yml | 4 ++++ hw/ula.py | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/.github/workflows/components.yml b/.github/workflows/components.yml index 14c53aa5..59300dfa 100644 --- a/.github/workflows/components.yml +++ b/.github/workflows/components.yml @@ -83,5 +83,9 @@ jobs: run: | pytest hw/test_ula.py -k test_zerador + - name: test inversor + run: | + pytest hw/test_ula.py -k test_inversor + diff --git a/hw/ula.py b/hw/ula.py index 49f42844..5fe242a3 100644 --- a/hw/ula.py +++ b/hw/ula.py @@ -35,7 +35,7 @@ def comb(): def inversor(z, a, y): @always_comb def comb(): - pass + y.next = ~a if z == 1 else a return instances() From ba721480ce2b5411d854f1748987504aeb2400b7 Mon Sep 17 00:00:00 2001 From: juliapaiva1 Date: Mon, 19 Sep 2022 10:32:18 -0300 Subject: [PATCH 53/60] inversor --- hw/ula.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/hw/ula.py b/hw/ula.py index 5fe242a3..e51af1d3 100644 --- a/hw/ula.py +++ b/hw/ula.py @@ -35,7 +35,10 @@ def comb(): def inversor(z, a, y): @always_comb def comb(): - y.next = ~a if z == 1 else a + if z == 1: + y.next = ~a + else: + y.next = a return instances() From c3b67ad242e9db40be0671c8a9ff5487c3d5c965 Mon Sep 17 00:00:00 2001 From: FeMCDias Date: Mon, 19 Sep 2022 14:59:23 -0300 Subject: [PATCH 54/60] Implementar ULA, Testado --- hw/components.py | 2 +- hw/ula.py | 44 +++++++++++++++++++++++++++++++------------- 2 files changed, 32 insertions(+), 14 deletions(-) diff --git a/hw/components.py b/hw/components.py index 1922ad4a..69484270 100644 --- a/hw/components.py +++ b/hw/components.py @@ -77,7 +77,7 @@ def mux2way(q, a, b, sel): q: 16 bits a: 16 bits b: 16 bits - sel: 2 bits + sel: 1 bits Mux entre a e b, sel é o seletor """ foo = Signal(intbv(0)) diff --git a/hw/ula.py b/hw/ula.py index 5fe242a3..0174dbaa 100644 --- a/hw/ula.py +++ b/hw/ula.py @@ -1,20 +1,18 @@ #!/usr/bin/env python3 from myhdl import * - - +from .components import * @block def ula(x, y, c, zr, ng, saida, width=16): - zx_out = Signal(intbv(0)[width:]) - nx_out = Signal(intbv(0)[width:]) - zy_out = Signal(intbv(0)[width:]) - ny_out = Signal(intbv(0)[width:]) - and_out = Signal(intbv(0)[width:]) - add_out = Signal(intbv(0)[width:]) - mux_out = Signal(intbv(0)[width:]) - no_out = Signal(intbv(0)[width:]) - + zx_out = Signal(modbv(0)[width:]) + nx_out = Signal(modbv(0)[width:]) + zy_out = Signal(modbv(0)[width:]) + ny_out = Signal(modbv(0)[width:]) + and_out = Signal(modbv(0)[width:]) + add_out = Signal(modbv(0)[width:]) + mux_out = Signal(modbv(0)[width:]) + no_out = Signal(modbv(0)[width:]) c_zx = c(5) c_nx = c(4) c_zy = c(3) @@ -22,10 +20,30 @@ def ula(x, y, c, zr, ng, saida, width=16): c_f = c(1) c_no = c(0) + z0 = zerador(c_zx, zx_out, x) + i1 = inversor(c_nx, zx_out, nx_out) + + z2 = zerador(c_zy, zy_out, y) + i2 = inversor(c_ny, zy_out, ny_out) + + m1 = mux2way(mux_out, and_out, add_out, c_f) + i3 = inversor(c_no, mux_out, no_out) + + c1 = comparador(no_out, zr, ng, width) + @always_comb def comb(): - pass + print('------------') + print(bin(x, 16)) + print(bin(y, 16)) + + print(bin(nx_out, 16)) + print(bin(ny_out, 16)) + print(bin(nx_out + ny_out, 16)) + and_out.next = nx_out & ny_out + add_out.next = nx_out + ny_out + saida.next = no_out return instances() @@ -49,7 +67,7 @@ def comb(): zr.next = 1 else: zr.next = 0 - if a < 0: + if a[width-1]: ng.next = 1 else: ng.next = 0 From 6578d4fabac33a0635322d41c2668266d23e4a5f Mon Sep 17 00:00:00 2001 From: FeMCDias Date: Mon, 19 Sep 2022 15:03:09 -0300 Subject: [PATCH 55/60] Deixar ula mais bonitinho --- hw/ula.py | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/hw/ula.py b/hw/ula.py index 1084d161..d07cf21c 100644 --- a/hw/ula.py +++ b/hw/ula.py @@ -4,7 +4,6 @@ from .components import * @block def ula(x, y, c, zr, ng, saida, width=16): - zx_out = Signal(modbv(0)[width:]) nx_out = Signal(modbv(0)[width:]) zy_out = Signal(modbv(0)[width:]) @@ -13,6 +12,7 @@ def ula(x, y, c, zr, ng, saida, width=16): add_out = Signal(modbv(0)[width:]) mux_out = Signal(modbv(0)[width:]) no_out = Signal(modbv(0)[width:]) + c_zx = c(5) c_nx = c(4) c_zy = c(3) @@ -33,14 +33,6 @@ def ula(x, y, c, zr, ng, saida, width=16): @always_comb def comb(): - print('------------') - print(bin(x, 16)) - print(bin(y, 16)) - - print(bin(nx_out, 16)) - print(bin(ny_out, 16)) - print(bin(nx_out + ny_out, 16)) - and_out.next = nx_out & ny_out add_out.next = nx_out + ny_out saida.next = no_out From 174d978feed25b48ebfd5882d30aedc8d070e9a7 Mon Sep 17 00:00:00 2001 From: Alexandre Date: Tue, 20 Sep 2022 23:18:20 -0300 Subject: [PATCH 56/60] addcla4 --- .github/workflows/components.yml | 5 +++++ hw/test_ula.py | 16 ++++++++++++++++ hw/ula.py | 4 ++-- 3 files changed, 23 insertions(+), 2 deletions(-) diff --git a/.github/workflows/components.yml b/.github/workflows/components.yml index 59300dfa..9650a0ea 100644 --- a/.github/workflows/components.yml +++ b/.github/workflows/components.yml @@ -86,6 +86,11 @@ jobs: - name: test inversor run: | pytest hw/test_ula.py -k test_inversor + + - name: test test addcla4 + run: | + pytest hw/test_ula.py -k test_addcla4 + diff --git a/hw/test_ula.py b/hw/test_ula.py index 0e32b7a8..367ea238 100755 --- a/hw/test_ula.py +++ b/hw/test_ula.py @@ -166,3 +166,19 @@ def stimulus(): sim = Simulation(add16_1, stimulus) sim.run() + +def test_addcla4(): + a = Signal(intbv(0)) + b = Signal(intbv(0)) + q = Signal(intbv(0)) + + addcla4_1 = addcla4(a, b, q) + + @instance + def stimulus(): + for i in range(16): + a.next, b.next = [randrange(2**3 - 1) for i in range(2)] + yield delay(1) + assert q == a + b + sim = Simulation(addcla4_1, stimulus) + sim.run() \ No newline at end of file diff --git a/hw/ula.py b/hw/ula.py index d07cf21c..68917738 100644 --- a/hw/ula.py +++ b/hw/ula.py @@ -133,12 +133,12 @@ def comb(): return instances() +@block @block def addcla4(a, b, q): @always_comb def comb(): - pass - + q.next = a+b return instances() From fadbf9ab62e5662677deaa976bec75c67022b13a Mon Sep 17 00:00:00 2001 From: Alexandre Date: Tue, 20 Sep 2022 23:19:48 -0300 Subject: [PATCH 57/60] corrigido compoenents --- .github/workflows/components.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/components.yml b/.github/workflows/components.yml index 9650a0ea..5848d89e 100644 --- a/.github/workflows/components.yml +++ b/.github/workflows/components.yml @@ -87,7 +87,7 @@ jobs: run: | pytest hw/test_ula.py -k test_inversor - - name: test test addcla4 + - name: test addcla4 run: | pytest hw/test_ula.py -k test_addcla4 From 3d1e7bf01eec29948f7ccca8cac4288f89a7a799 Mon Sep 17 00:00:00 2001 From: Alexandre Date: Tue, 20 Sep 2022 23:29:31 -0300 Subject: [PATCH 58/60] yeeeey --- hw/ula.py | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/ula.py b/hw/ula.py index 68917738..605fc6e7 100644 --- a/hw/ula.py +++ b/hw/ula.py @@ -133,7 +133,6 @@ def comb(): return instances() -@block @block def addcla4(a, b, q): @always_comb From 6e7be91b3436bb3102fb9c6cee3072ac57408e03 Mon Sep 17 00:00:00 2001 From: Hiratsuca <104103173+Hiratsuca@users.noreply.github.com> Date: Wed, 21 Sep 2022 00:38:36 -0300 Subject: [PATCH 59/60] =?UTF-8?q?Subindo=20toplevel=20com=20altera=C3=A7?= =?UTF-8?q?=C3=B5es=20para=20ula?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- hw/toplevel.py | 28 ++++++++++++++++++---------- 1 file changed, 18 insertions(+), 10 deletions(-) diff --git a/hw/toplevel.py b/hw/toplevel.py index a3a71e36..287ac994 100755 --- a/hw/toplevel.py +++ b/hw/toplevel.py @@ -1,29 +1,34 @@ #!/usr/bin/env python3 -# -*- coding: utf-8 -*- +# -- coding: utf-8 -- from myhdl import * from components import * +from ula import * @block def toplevel(LEDR, SW, KEY, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, CLOCK_50, RESET_N): sw_s = [SW(i) for i in range(10)] key_s = [KEY(i) for i in range(10)] - ledr_s = [Signal(bool(0)) for i in range(10)] + ledrs = [Signal(bool(0)) for i in range(10)] - bc0 = Signal(intbv(0)[4:]) - bc1 = Signal(intbv(0)[4:]) - hex0 = Signal(intbv(0)[7:]) - hex1 = Signal(intbv(0)[7:]) + #Variaveis que não são usadas: + # bc0 = Signal(intbv(0)[4:]) + # bc1 = Signal(intbv(0)[4:]) + # hex0 = Signal(intbv(0)[7:]) + # hex1 = Signal(intbv(0)[7:]) # Funções que usavam variáveis erradas: # ic1 = bin2bcd(SW[8:0], bc1, bc0) # ihex1 = bin2hex(hex1, bc1) # ihex0 = bin2hex(hex0, bc0) - ic1 = bin2bcd(SW, bc1, bc0) - ihex1 = bin2hex(HEX1, bc1) - ihex0 = bin2hex(HEX0, bc0) + # ic1 = bin2bcd(SW, bc1, bc0) + # ihex1 = bin2hex(HEX1, bc1) + # ihex0 = bin2hex(HEX0, bc0) + + + ula_ = ula(Signal(intbv(1)[8:]), Signal(intbv(2)[8:]), SW, ledr_s[8], ledr_s[9], ledr_s[0:8], Signal(modbv(0)[8:])) # ---------------------------------------- # @always_comb @@ -44,7 +49,10 @@ def comb(): HEX4 = Signal(intbv(1)[7:]) HEX5 = Signal(intbv(1)[7:]) CLOCK_50 = Signal(bool()) + + + RESET_N = ResetSignal(0, active=0, isasync=True) top = toplevel(LEDR, SW, KEY, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, CLOCK_50, RESET_N) -top.convert(hdl="VHDL") +top.convert(hdl="VHDL") \ No newline at end of file From ca77237c6e9353d5acac59aa2f8fc7a214194994 Mon Sep 17 00:00:00 2001 From: Hiratsuca <104103173+Hiratsuca@users.noreply.github.com> Date: Wed, 21 Sep 2022 01:38:26 -0300 Subject: [PATCH 60/60] =?UTF-8?q?Arrumando=20fun=C3=A7=C3=A3o=20addcla16?= =?UTF-8?q?=20+=20teste=20da=20fun=C3=A7=C3=A3o?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- hw/test_ula.py | 16 ++++++++++++++++ hw/ula.py | 2 +- 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/hw/test_ula.py b/hw/test_ula.py index 367ea238..4e00124d 100755 --- a/hw/test_ula.py +++ b/hw/test_ula.py @@ -181,4 +181,20 @@ def stimulus(): yield delay(1) assert q == a + b sim = Simulation(addcla4_1, stimulus) + sim.run() + +def test_addcla16(): + a = Signal(intbv(0)) + b = Signal(intbv(0)) + q = Signal(intbv(0)) + + addcla16_1 = addcla4(a, b, q) + + @instance + def stimulus(): + for i in range(256): + a.next, b.next = [randrange(2**15 - 1) for i in range(2)] + yield delay(1) + assert q == a + b + sim = Simulation(addcla16_1, stimulus) sim.run() \ No newline at end of file diff --git a/hw/ula.py b/hw/ula.py index 605fc6e7..5f2e8eee 100644 --- a/hw/ula.py +++ b/hw/ula.py @@ -145,7 +145,7 @@ def comb(): def addcla16(a, b, q): @always_comb def comb(): - pass + q.next = a + b return instances()